Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 39
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 11:02:04.233415 lava-dispatcher, installed at version: 2024.05
2 11:02:04.233614 start: 0 validate
3 11:02:04.233723 Start time: 2024-07-10 11:02:04.233718+00:00 (UTC)
4 11:02:04.233853 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:02:04.233996 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 11:02:04.501013 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:02:04.501170 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:02:04.767932 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:02:04.768732 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:02:33.623685 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:02:33.624318 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:02:34.152919 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:02:34.153557 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 11:02:34.429693 validate duration: 30.20
16 11:02:34.430910 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:02:34.431432 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:02:34.431872 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:02:34.432565 Not decompressing ramdisk as can be used compressed.
20 11:02:34.433027 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 11:02:34.433371 saving as /var/lib/lava/dispatcher/tmp/14786822/tftp-deploy-6460t7t3/ramdisk/initrd.cpio.gz
22 11:02:34.433689 total size: 5628169 (5 MB)
23 11:02:37.616238 progress 0 % (0 MB)
24 11:02:37.625891 progress 5 % (0 MB)
25 11:02:37.633580 progress 10 % (0 MB)
26 11:02:37.634991 progress 15 % (0 MB)
27 11:02:37.636478 progress 20 % (1 MB)
28 11:02:37.637795 progress 25 % (1 MB)
29 11:02:37.639281 progress 30 % (1 MB)
30 11:02:37.640764 progress 35 % (1 MB)
31 11:02:37.642098 progress 40 % (2 MB)
32 11:02:37.643582 progress 45 % (2 MB)
33 11:02:37.644961 progress 50 % (2 MB)
34 11:02:37.646451 progress 55 % (2 MB)
35 11:02:37.647886 progress 60 % (3 MB)
36 11:02:37.649170 progress 65 % (3 MB)
37 11:02:37.650670 progress 70 % (3 MB)
38 11:02:37.652025 progress 75 % (4 MB)
39 11:02:37.653466 progress 80 % (4 MB)
40 11:02:37.654799 progress 85 % (4 MB)
41 11:02:37.656253 progress 90 % (4 MB)
42 11:02:37.657686 progress 95 % (5 MB)
43 11:02:37.659024 progress 100 % (5 MB)
44 11:02:37.659225 5 MB downloaded in 3.23 s (1.66 MB/s)
45 11:02:37.659365 end: 1.1.1 http-download (duration 00:00:03) [common]
47 11:02:37.659581 end: 1.1 download-retry (duration 00:00:03) [common]
48 11:02:37.659658 start: 1.2 download-retry (timeout 00:09:57) [common]
49 11:02:37.659731 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 11:02:37.659864 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 11:02:37.659923 saving as /var/lib/lava/dispatcher/tmp/14786822/tftp-deploy-6460t7t3/kernel/Image
52 11:02:37.659974 total size: 54813184 (52 MB)
53 11:02:37.660026 No compression specified
54 11:02:37.661052 progress 0 % (0 MB)
55 11:02:37.674317 progress 5 % (2 MB)
56 11:02:37.687388 progress 10 % (5 MB)
57 11:02:37.700569 progress 15 % (7 MB)
58 11:02:37.713876 progress 20 % (10 MB)
59 11:02:37.727013 progress 25 % (13 MB)
60 11:02:37.740109 progress 30 % (15 MB)
61 11:02:37.753433 progress 35 % (18 MB)
62 11:02:37.767480 progress 40 % (20 MB)
63 11:02:37.780683 progress 45 % (23 MB)
64 11:02:37.794607 progress 50 % (26 MB)
65 11:02:37.807774 progress 55 % (28 MB)
66 11:02:37.820808 progress 60 % (31 MB)
67 11:02:37.834199 progress 65 % (34 MB)
68 11:02:37.847196 progress 70 % (36 MB)
69 11:02:37.860395 progress 75 % (39 MB)
70 11:02:37.873711 progress 80 % (41 MB)
71 11:02:37.886972 progress 85 % (44 MB)
72 11:02:37.900418 progress 90 % (47 MB)
73 11:02:37.913936 progress 95 % (49 MB)
74 11:02:37.926890 progress 100 % (52 MB)
75 11:02:37.927118 52 MB downloaded in 0.27 s (195.68 MB/s)
76 11:02:37.927267 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:02:37.927474 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:02:37.927552 start: 1.3 download-retry (timeout 00:09:57) [common]
80 11:02:37.927625 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 11:02:37.927754 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:02:37.927813 saving as /var/lib/lava/dispatcher/tmp/14786822/tftp-deploy-6460t7t3/dtb/mt8192-asurada-spherion-r0.dtb
83 11:02:37.927865 total size: 47258 (0 MB)
84 11:02:37.927917 No compression specified
85 11:02:37.929008 progress 69 % (0 MB)
86 11:02:37.929258 progress 100 % (0 MB)
87 11:02:37.929435 0 MB downloaded in 0.00 s (28.74 MB/s)
88 11:02:37.929546 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:02:37.929743 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:02:37.929816 start: 1.4 download-retry (timeout 00:09:57) [common]
92 11:02:37.929889 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 11:02:37.929994 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 11:02:37.930097 saving as /var/lib/lava/dispatcher/tmp/14786822/tftp-deploy-6460t7t3/nfsrootfs/full.rootfs.tar
95 11:02:37.930149 total size: 120894716 (115 MB)
96 11:02:37.930202 Using unxz to decompress xz
97 11:02:37.931435 progress 0 % (0 MB)
98 11:02:38.285873 progress 5 % (5 MB)
99 11:02:38.628489 progress 10 % (11 MB)
100 11:02:38.980611 progress 15 % (17 MB)
101 11:02:39.313928 progress 20 % (23 MB)
102 11:02:39.618168 progress 25 % (28 MB)
103 11:02:39.959002 progress 30 % (34 MB)
104 11:02:40.283542 progress 35 % (40 MB)
105 11:02:40.462284 progress 40 % (46 MB)
106 11:02:40.646721 progress 45 % (51 MB)
107 11:02:40.949210 progress 50 % (57 MB)
108 11:02:41.309028 progress 55 % (63 MB)
109 11:02:41.659631 progress 60 % (69 MB)
110 11:02:42.007015 progress 65 % (74 MB)
111 11:02:42.348867 progress 70 % (80 MB)
112 11:02:42.695515 progress 75 % (86 MB)
113 11:02:43.022836 progress 80 % (92 MB)
114 11:02:43.360634 progress 85 % (98 MB)
115 11:02:43.694800 progress 90 % (103 MB)
116 11:02:44.026591 progress 95 % (109 MB)
117 11:02:44.376855 progress 100 % (115 MB)
118 11:02:44.382350 115 MB downloaded in 6.45 s (17.87 MB/s)
119 11:02:44.382571 end: 1.4.1 http-download (duration 00:00:06) [common]
121 11:02:44.382901 end: 1.4 download-retry (duration 00:00:06) [common]
122 11:02:44.383016 start: 1.5 download-retry (timeout 00:09:50) [common]
123 11:02:44.383130 start: 1.5.1 http-download (timeout 00:09:50) [common]
124 11:02:44.383309 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 11:02:44.383404 saving as /var/lib/lava/dispatcher/tmp/14786822/tftp-deploy-6460t7t3/modules/modules.tar
126 11:02:44.383489 total size: 8607984 (8 MB)
127 11:02:44.383572 Using unxz to decompress xz
128 11:02:44.385144 progress 0 % (0 MB)
129 11:02:44.406811 progress 5 % (0 MB)
130 11:02:44.431577 progress 10 % (0 MB)
131 11:02:44.455492 progress 15 % (1 MB)
132 11:02:44.483890 progress 20 % (1 MB)
133 11:02:44.508352 progress 25 % (2 MB)
134 11:02:44.531971 progress 30 % (2 MB)
135 11:02:44.554570 progress 35 % (2 MB)
136 11:02:44.580665 progress 40 % (3 MB)
137 11:02:44.605440 progress 45 % (3 MB)
138 11:02:44.629606 progress 50 % (4 MB)
139 11:02:44.654653 progress 55 % (4 MB)
140 11:02:44.678451 progress 60 % (4 MB)
141 11:02:44.701640 progress 65 % (5 MB)
142 11:02:44.727391 progress 70 % (5 MB)
143 11:02:44.755703 progress 75 % (6 MB)
144 11:02:44.785064 progress 80 % (6 MB)
145 11:02:44.809419 progress 85 % (7 MB)
146 11:02:44.833122 progress 90 % (7 MB)
147 11:02:44.856783 progress 95 % (7 MB)
148 11:02:44.879886 progress 100 % (8 MB)
149 11:02:44.885406 8 MB downloaded in 0.50 s (16.36 MB/s)
150 11:02:44.885578 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:02:44.885790 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:02:44.885869 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 11:02:44.885944 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 11:02:48.472183 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14786822/extract-nfsrootfs-hzf441ob
156 11:02:48.472359 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 11:02:48.472445 start: 1.6.2 lava-overlay (timeout 00:09:46) [common]
158 11:02:48.472595 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2
159 11:02:48.472712 makedir: /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin
160 11:02:48.472805 makedir: /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/tests
161 11:02:48.472892 makedir: /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/results
162 11:02:48.472972 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-add-keys
163 11:02:48.473095 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-add-sources
164 11:02:48.473211 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-background-process-start
165 11:02:48.473326 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-background-process-stop
166 11:02:48.473447 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-common-functions
167 11:02:48.473579 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-echo-ipv4
168 11:02:48.473782 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-install-packages
169 11:02:48.473939 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-installed-packages
170 11:02:48.474121 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-os-build
171 11:02:48.474235 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-probe-channel
172 11:02:48.474350 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-probe-ip
173 11:02:48.474462 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-target-ip
174 11:02:48.474572 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-target-mac
175 11:02:48.474684 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-target-storage
176 11:02:48.474798 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-test-case
177 11:02:48.474910 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-test-event
178 11:02:48.475019 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-test-feedback
179 11:02:48.475129 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-test-raise
180 11:02:48.475240 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-test-reference
181 11:02:48.475352 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-test-runner
182 11:02:48.475462 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-test-set
183 11:02:48.475571 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-test-shell
184 11:02:48.475690 Updating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-add-keys (debian)
185 11:02:48.480356 Updating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-add-sources (debian)
186 11:02:48.481417 Updating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-install-packages (debian)
187 11:02:48.482467 Updating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-installed-packages (debian)
188 11:02:48.482798 Updating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/bin/lava-os-build (debian)
189 11:02:48.483048 Creating /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/environment
190 11:02:48.483196 LAVA metadata
191 11:02:48.483269 - LAVA_JOB_ID=14786822
192 11:02:48.483327 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:02:48.483434 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:46) [common]
194 11:02:48.483491 skipped lava-vland-overlay
195 11:02:48.483561 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:02:48.483633 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:46) [common]
197 11:02:48.483689 skipped lava-multinode-overlay
198 11:02:48.483752 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:02:48.483820 start: 1.6.2.3 test-definition (timeout 00:09:46) [common]
200 11:02:48.483886 Loading test definitions
201 11:02:48.483961 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:46) [common]
202 11:02:48.484019 Using /lava-14786822 at stage 0
203 11:02:48.484304 uuid=14786822_1.6.2.3.1 testdef=None
204 11:02:48.484383 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:02:48.484456 start: 1.6.2.3.2 test-overlay (timeout 00:09:46) [common]
206 11:02:48.485052 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:02:48.485264 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:46) [common]
209 11:02:48.485770 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:02:48.485974 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:46) [common]
212 11:02:48.486542 runner path: /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/0/tests/0_timesync-off test_uuid 14786822_1.6.2.3.1
213 11:02:48.486682 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:02:48.486880 start: 1.6.2.3.5 git-repo-action (timeout 00:09:46) [common]
216 11:02:48.486944 Using /lava-14786822 at stage 0
217 11:02:48.487031 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:02:48.487105 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/0/tests/1_kselftest-rtc'
219 11:02:52.192393 Running '/usr/bin/git checkout kernelci.org
220 11:02:52.326785 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 11:02:52.327370 uuid=14786822_1.6.2.3.5 testdef=None
222 11:02:52.327549 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 11:02:52.327858 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 11:02:52.328956 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:02:52.329286 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 11:02:52.330876 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:02:52.331234 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 11:02:52.332724 runner path: /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/0/tests/1_kselftest-rtc test_uuid 14786822_1.6.2.3.5
232 11:02:52.332833 BOARD='mt8192-asurada-spherion-r0'
233 11:02:52.332920 BRANCH='cip'
234 11:02:52.333001 SKIPFILE='/dev/null'
235 11:02:52.333082 SKIP_INSTALL='True'
236 11:02:52.333161 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz'
237 11:02:52.333241 TST_CASENAME=''
238 11:02:52.333321 TST_CMDFILES='rtc'
239 11:02:52.333524 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:02:52.333837 Creating lava-test-runner.conf files
242 11:02:52.333922 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14786822/lava-overlay-sqpxgsx2/lava-14786822/0 for stage 0
243 11:02:52.334073 - 0_timesync-off
244 11:02:52.334162 - 1_kselftest-rtc
245 11:02:52.334283 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 11:02:52.334386 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 11:02:59.586980 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 11:02:59.587114 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 11:02:59.587197 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:02:59.587276 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 11:02:59.587352 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 11:02:59.733657 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:02:59.733797 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 11:02:59.733873 extracting modules file /var/lib/lava/dispatcher/tmp/14786822/tftp-deploy-6460t7t3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786822/extract-nfsrootfs-hzf441ob
255 11:02:59.959348 extracting modules file /var/lib/lava/dispatcher/tmp/14786822/tftp-deploy-6460t7t3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786822/extract-overlay-ramdisk-z5smapdn/ramdisk
256 11:03:00.222135 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:03:00.222285 start: 1.6.5 apply-overlay-tftp (timeout 00:09:34) [common]
258 11:03:00.222362 [common] Applying overlay to NFS
259 11:03:00.222422 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786822/compress-overlay-nscqnr32/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14786822/extract-nfsrootfs-hzf441ob
260 11:03:01.055053 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:03:01.055193 start: 1.6.6 configure-preseed-file (timeout 00:09:33) [common]
262 11:03:01.055278 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:03:01.055355 start: 1.6.7 compress-ramdisk (timeout 00:09:33) [common]
264 11:03:01.055423 Building ramdisk /var/lib/lava/dispatcher/tmp/14786822/extract-overlay-ramdisk-z5smapdn/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14786822/extract-overlay-ramdisk-z5smapdn/ramdisk
265 11:03:01.351038 >> 129845 blocks
266 11:03:03.442250 rename /var/lib/lava/dispatcher/tmp/14786822/extract-overlay-ramdisk-z5smapdn/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14786822/tftp-deploy-6460t7t3/ramdisk/ramdisk.cpio.gz
267 11:03:03.442441 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:03:03.442564 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 11:03:03.442677 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 11:03:03.442796 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14786822/tftp-deploy-6460t7t3/kernel/Image']
271 11:03:18.048171 Returned 0 in 14 seconds
272 11:03:18.048337 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14786822/tftp-deploy-6460t7t3/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14786822/tftp-deploy-6460t7t3/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14786822/tftp-deploy-6460t7t3/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14786822/tftp-deploy-6460t7t3/kernel/image.itb
273 11:03:18.398652 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:03:18.398777 output: Created: Wed Jul 10 12:03:18 2024
275 11:03:18.398836 output: Image 0 (kernel-1)
276 11:03:18.398890 output: Description:
277 11:03:18.398942 output: Created: Wed Jul 10 12:03:18 2024
278 11:03:18.398992 output: Type: Kernel Image
279 11:03:18.399041 output: Compression: lzma compressed
280 11:03:18.399093 output: Data Size: 13116259 Bytes = 12808.85 KiB = 12.51 MiB
281 11:03:18.399142 output: Architecture: AArch64
282 11:03:18.399189 output: OS: Linux
283 11:03:18.399236 output: Load Address: 0x00000000
284 11:03:18.399284 output: Entry Point: 0x00000000
285 11:03:18.399331 output: Hash algo: crc32
286 11:03:18.399380 output: Hash value: 9bb85fb9
287 11:03:18.399427 output: Image 1 (fdt-1)
288 11:03:18.399474 output: Description: mt8192-asurada-spherion-r0
289 11:03:18.399521 output: Created: Wed Jul 10 12:03:18 2024
290 11:03:18.399567 output: Type: Flat Device Tree
291 11:03:18.399614 output: Compression: uncompressed
292 11:03:18.399662 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 11:03:18.399709 output: Architecture: AArch64
294 11:03:18.399756 output: Hash algo: crc32
295 11:03:18.399802 output: Hash value: 0f8e4d2e
296 11:03:18.399849 output: Image 2 (ramdisk-1)
297 11:03:18.399895 output: Description: unavailable
298 11:03:18.399943 output: Created: Wed Jul 10 12:03:18 2024
299 11:03:18.399990 output: Type: RAMDisk Image
300 11:03:18.400037 output: Compression: uncompressed
301 11:03:18.400084 output: Data Size: 18707877 Bytes = 18269.41 KiB = 17.84 MiB
302 11:03:18.400131 output: Architecture: AArch64
303 11:03:18.400177 output: OS: Linux
304 11:03:18.400247 output: Load Address: unavailable
305 11:03:18.400325 output: Entry Point: unavailable
306 11:03:18.400387 output: Hash algo: crc32
307 11:03:18.400434 output: Hash value: e5c6c733
308 11:03:18.400485 output: Default Configuration: 'conf-1'
309 11:03:18.400534 output: Configuration 0 (conf-1)
310 11:03:18.400580 output: Description: mt8192-asurada-spherion-r0
311 11:03:18.400627 output: Kernel: kernel-1
312 11:03:18.400674 output: Init Ramdisk: ramdisk-1
313 11:03:18.400721 output: FDT: fdt-1
314 11:03:18.400768 output: Loadables: kernel-1
315 11:03:18.400814 output:
316 11:03:18.400911 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 11:03:18.400985 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 11:03:18.401058 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 11:03:18.401131 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 11:03:18.401192 No LXC device requested
321 11:03:18.401262 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:03:18.401331 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 11:03:18.401397 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:03:18.401451 Checking files for TFTP limit of 4294967296 bytes.
325 11:03:18.401814 end: 1 tftp-deploy (duration 00:00:44) [common]
326 11:03:18.401901 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:03:18.401977 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:03:18.402113 substitutions:
329 11:03:18.402171 - {DTB}: 14786822/tftp-deploy-6460t7t3/dtb/mt8192-asurada-spherion-r0.dtb
330 11:03:18.402226 - {INITRD}: 14786822/tftp-deploy-6460t7t3/ramdisk/ramdisk.cpio.gz
331 11:03:18.402278 - {KERNEL}: 14786822/tftp-deploy-6460t7t3/kernel/Image
332 11:03:18.402329 - {LAVA_MAC}: None
333 11:03:18.402380 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14786822/extract-nfsrootfs-hzf441ob
334 11:03:18.402430 - {NFS_SERVER_IP}: 192.168.201.1
335 11:03:18.402479 - {PRESEED_CONFIG}: None
336 11:03:18.402535 - {PRESEED_LOCAL}: None
337 11:03:18.402585 - {RAMDISK}: 14786822/tftp-deploy-6460t7t3/ramdisk/ramdisk.cpio.gz
338 11:03:18.402633 - {ROOT_PART}: None
339 11:03:18.402681 - {ROOT}: None
340 11:03:18.402729 - {SERVER_IP}: 192.168.201.1
341 11:03:18.402776 - {TEE}: None
342 11:03:18.402824 Parsed boot commands:
343 11:03:18.402872 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:03:18.403003 Parsed boot commands: tftpboot 192.168.201.1 14786822/tftp-deploy-6460t7t3/kernel/image.itb 14786822/tftp-deploy-6460t7t3/kernel/cmdline
345 11:03:18.403081 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:03:18.403153 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:03:18.403225 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:03:18.403293 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:03:18.403347 Not connected, no need to disconnect.
350 11:03:18.403412 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:03:18.403480 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:03:18.403533 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 11:03:18.406729 Setting prompt string to ['lava-test: # ']
354 11:03:18.407055 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:03:18.407171 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:03:18.407261 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:03:18.407360 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:03:18.407533 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
359 11:03:27.566957 >> Command sent successfully.
360 11:03:27.570429 Returned 0 in 9 seconds
361 11:03:27.570598 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 11:03:27.570899 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 11:03:27.571016 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 11:03:27.571117 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:03:27.571201 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:03:27.571292 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:03:27.571783 [Enter `^Ec?' for help]
369 11:03:29.096260
370 11:03:29.096377
371 11:03:29.096441 F0: 102B 0000
372 11:03:29.096506
373 11:03:29.096558 F3: 1001 0000 [0200]
374 11:03:29.096614
375 11:03:29.100041 F3: 1001 0000
376 11:03:29.100118
377 11:03:29.100195 F7: 102D 0000
378 11:03:29.100302
379 11:03:29.100386 F1: 0000 0000
380 11:03:29.100468
381 11:03:29.103140 V0: 0000 0000 [0001]
382 11:03:29.103218
383 11:03:29.103278 00: 0007 8000
384 11:03:29.103333
385 11:03:29.106970 01: 0000 0000
386 11:03:29.107047
387 11:03:29.107104 BP: 0C00 0209 [0000]
388 11:03:29.107157
389 11:03:29.110922 G0: 1182 0000
390 11:03:29.110996
391 11:03:29.111053 EC: 0000 0021 [4000]
392 11:03:29.111106
393 11:03:29.114187 S7: 0000 0000 [0000]
394 11:03:29.114261
395 11:03:29.114318 CC: 0000 0000 [0001]
396 11:03:29.114371
397 11:03:29.118238 T0: 0000 0040 [010F]
398 11:03:29.118312
399 11:03:29.118369 Jump to BL
400 11:03:29.118422
401 11:03:29.142633
402 11:03:29.142715
403 11:03:29.150425 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 11:03:29.153830 ARM64: Exception handlers installed.
405 11:03:29.157376 ARM64: Testing exception
406 11:03:29.160923 ARM64: Done test exception
407 11:03:29.168388 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 11:03:29.175981 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 11:03:29.183016 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 11:03:29.193398 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 11:03:29.200317 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 11:03:29.210512 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 11:03:29.220713 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 11:03:29.227114 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 11:03:29.245746 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 11:03:29.248992 WDT: Last reset was cold boot
417 11:03:29.252164 SPI1(PAD0) initialized at 2873684 Hz
418 11:03:29.255988 SPI5(PAD0) initialized at 992727 Hz
419 11:03:29.258925 VBOOT: Loading verstage.
420 11:03:29.266143 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 11:03:29.269080 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 11:03:29.272356 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 11:03:29.275909 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 11:03:29.283525 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 11:03:29.289578 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 11:03:29.300775 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
427 11:03:29.300878
428 11:03:29.300966
429 11:03:29.310344 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 11:03:29.313978 ARM64: Exception handlers installed.
431 11:03:29.317403 ARM64: Testing exception
432 11:03:29.317476 ARM64: Done test exception
433 11:03:29.323956 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 11:03:29.327354 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 11:03:29.341804 Probing TPM: . done!
436 11:03:29.341904 TPM ready after 0 ms
437 11:03:29.348450 Connected to device vid:did:rid of 1ae0:0028:00
438 11:03:29.355062 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 11:03:29.394597 Initialized TPM device CR50 revision 0
440 11:03:29.406660 tlcl_send_startup: Startup return code is 0
441 11:03:29.406821 TPM: setup succeeded
442 11:03:29.418375 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 11:03:29.427130 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 11:03:29.437289 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 11:03:29.446497 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 11:03:29.449377 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 11:03:29.453142 in-header: 03 07 00 00 08 00 00 00
448 11:03:29.456885 in-data: aa e4 47 04 13 02 00 00
449 11:03:29.460217 Chrome EC: UHEPI supported
450 11:03:29.466349 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 11:03:29.470399 in-header: 03 a9 00 00 08 00 00 00
452 11:03:29.473226 in-data: 84 60 60 08 00 00 00 00
453 11:03:29.473302 Phase 1
454 11:03:29.476819 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 11:03:29.483176 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 11:03:29.490201 VB2:vb2_check_recovery() Recovery was requested manually
457 11:03:29.496982 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
458 11:03:29.497066 Recovery requested (1009000e)
459 11:03:29.505086 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:03:29.510494 tlcl_extend: response is 0
461 11:03:29.521256 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:03:29.524727 tlcl_extend: response is 0
463 11:03:29.531235 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:03:29.551237 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 11:03:29.558402 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:03:29.558480
467 11:03:29.558540
468 11:03:29.567970 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:03:29.571618 ARM64: Exception handlers installed.
470 11:03:29.574841 ARM64: Testing exception
471 11:03:29.574939 ARM64: Done test exception
472 11:03:29.596945 pmic_efuse_setting: Set efuses in 11 msecs
473 11:03:29.600490 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:03:29.606839 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:03:29.610419 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:03:29.617132 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:03:29.620694 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:03:29.627085 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:03:29.631038 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:03:29.634829 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:03:29.642030 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:03:29.645843 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:03:29.649340 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:03:29.652327 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:03:29.659561 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:03:29.663662 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:03:29.669998 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:03:29.676646 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:03:29.679611 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:03:29.686722 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:03:29.693424 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:03:29.696435 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:03:29.703378 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:03:29.709983 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:03:29.713597 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:03:29.720311 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:03:29.726864 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:03:29.730141 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:03:29.736864 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:03:29.740184 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:03:29.746875 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:03:29.750388 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:03:29.756893 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:03:29.760118 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:03:29.766614 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:03:29.770371 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:03:29.776843 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:03:29.780147 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:03:29.787284 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:03:29.790215 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:03:29.797889 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:03:29.800752 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:03:29.804829 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:03:29.807865 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:03:29.814410 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:03:29.817989 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:03:29.820873 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:03:29.827950 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:03:29.831364 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:03:29.834600 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:03:29.841345 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:03:29.844506 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:03:29.848263 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:03:29.851566 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:03:29.861342 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
526 11:03:29.868013 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:03:29.871421 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:03:29.881219 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:03:29.887943 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:03:29.894798 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:03:29.898962 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:03:29.901756 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:03:29.909948 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x2a
534 11:03:29.916819 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:03:29.919748 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 11:03:29.923473 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:03:29.934209 [RTC]rtc_get_frequency_meter,154: input=15, output=759
538 11:03:29.944090 [RTC]rtc_get_frequency_meter,154: input=23, output=942
539 11:03:29.953607 [RTC]rtc_get_frequency_meter,154: input=19, output=851
540 11:03:29.963229 [RTC]rtc_get_frequency_meter,154: input=17, output=806
541 11:03:29.972541 [RTC]rtc_get_frequency_meter,154: input=16, output=782
542 11:03:29.982134 [RTC]rtc_get_frequency_meter,154: input=16, output=782
543 11:03:29.991462 [RTC]rtc_get_frequency_meter,154: input=17, output=804
544 11:03:29.995434 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 11:03:30.001925 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 11:03:30.005695 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 11:03:30.008428 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 11:03:30.015243 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 11:03:30.018876 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 11:03:30.022140 ADC[4]: Raw value=905465 ID=7
551 11:03:30.022215 ADC[3]: Raw value=213441 ID=1
552 11:03:30.025200 RAM Code: 0x71
553 11:03:30.028416 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 11:03:30.035355 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 11:03:30.042477 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 11:03:30.048974 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 11:03:30.052434 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 11:03:30.055515 in-header: 03 07 00 00 08 00 00 00
559 11:03:30.058807 in-data: aa e4 47 04 13 02 00 00
560 11:03:30.061885 Chrome EC: UHEPI supported
561 11:03:30.068623 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 11:03:30.072155 in-header: 03 a9 00 00 08 00 00 00
563 11:03:30.075349 in-data: 84 60 60 08 00 00 00 00
564 11:03:30.078673 MRC: failed to locate region type 0.
565 11:03:30.085469 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 11:03:30.088578 DRAM-K: Running full calibration
567 11:03:30.095425 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 11:03:30.095514 header.status = 0x0
569 11:03:30.099301 header.version = 0x6 (expected: 0x6)
570 11:03:30.102342 header.size = 0xd00 (expected: 0xd00)
571 11:03:30.105669 header.flags = 0x0
572 11:03:30.111910 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 11:03:30.128044 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 11:03:30.135105 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 11:03:30.137999 dram_init: ddr_geometry: 2
576 11:03:30.138123 [EMI] MDL number = 2
577 11:03:30.141733 [EMI] Get MDL freq = 0
578 11:03:30.145059 dram_init: ddr_type: 0
579 11:03:30.145168 is_discrete_lpddr4: 1
580 11:03:30.148183 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 11:03:30.148259
582 11:03:30.148317
583 11:03:30.151848 [Bian_co] ETT version 0.0.0.1
584 11:03:30.158751 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 11:03:30.158868
586 11:03:30.161972 dramc_set_vcore_voltage set vcore to 650000
587 11:03:30.162090 Read voltage for 800, 4
588 11:03:30.165110 Vio18 = 0
589 11:03:30.165184 Vcore = 650000
590 11:03:30.165239 Vdram = 0
591 11:03:30.168960 Vddq = 0
592 11:03:30.169026 Vmddr = 0
593 11:03:30.171768 dram_init: config_dvfs: 1
594 11:03:30.175182 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 11:03:30.181565 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 11:03:30.185232 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 11:03:30.188491 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 11:03:30.191729 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 11:03:30.195465 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 11:03:30.198428 MEM_TYPE=3, freq_sel=18
601 11:03:30.201832 sv_algorithm_assistance_LP4_1600
602 11:03:30.205716 ============ PULL DRAM RESETB DOWN ============
603 11:03:30.208743 ========== PULL DRAM RESETB DOWN end =========
604 11:03:30.215174 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 11:03:30.218442 ===================================
606 11:03:30.218564 LPDDR4 DRAM CONFIGURATION
607 11:03:30.221750 ===================================
608 11:03:30.225335 EX_ROW_EN[0] = 0x0
609 11:03:30.228898 EX_ROW_EN[1] = 0x0
610 11:03:30.228973 LP4Y_EN = 0x0
611 11:03:30.231866 WORK_FSP = 0x0
612 11:03:30.231965 WL = 0x2
613 11:03:30.235594 RL = 0x2
614 11:03:30.235669 BL = 0x2
615 11:03:30.238498 RPST = 0x0
616 11:03:30.238573 RD_PRE = 0x0
617 11:03:30.242133 WR_PRE = 0x1
618 11:03:30.242208 WR_PST = 0x0
619 11:03:30.245438 DBI_WR = 0x0
620 11:03:30.245513 DBI_RD = 0x0
621 11:03:30.248775 OTF = 0x1
622 11:03:30.252295 ===================================
623 11:03:30.255359 ===================================
624 11:03:30.255434 ANA top config
625 11:03:30.258707 ===================================
626 11:03:30.262518 DLL_ASYNC_EN = 0
627 11:03:30.265637 ALL_SLAVE_EN = 1
628 11:03:30.265712 NEW_RANK_MODE = 1
629 11:03:30.268720 DLL_IDLE_MODE = 1
630 11:03:30.272151 LP45_APHY_COMB_EN = 1
631 11:03:30.275483 TX_ODT_DIS = 1
632 11:03:30.275557 NEW_8X_MODE = 1
633 11:03:30.279100 ===================================
634 11:03:30.282811 ===================================
635 11:03:30.285476 data_rate = 1600
636 11:03:30.288698 CKR = 1
637 11:03:30.293134 DQ_P2S_RATIO = 8
638 11:03:30.295942 ===================================
639 11:03:30.298980 CA_P2S_RATIO = 8
640 11:03:30.303015 DQ_CA_OPEN = 0
641 11:03:30.303091 DQ_SEMI_OPEN = 0
642 11:03:30.306759 CA_SEMI_OPEN = 0
643 11:03:30.310284 CA_FULL_RATE = 0
644 11:03:30.314204 DQ_CKDIV4_EN = 1
645 11:03:30.314282 CA_CKDIV4_EN = 1
646 11:03:30.317770 CA_PREDIV_EN = 0
647 11:03:30.321579 PH8_DLY = 0
648 11:03:30.324823 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 11:03:30.324898 DQ_AAMCK_DIV = 4
650 11:03:30.329143 CA_AAMCK_DIV = 4
651 11:03:30.332431 CA_ADMCK_DIV = 4
652 11:03:30.332534 DQ_TRACK_CA_EN = 0
653 11:03:30.336052 CA_PICK = 800
654 11:03:30.339505 CA_MCKIO = 800
655 11:03:30.342699 MCKIO_SEMI = 0
656 11:03:30.345860 PLL_FREQ = 3068
657 11:03:30.349637 DQ_UI_PI_RATIO = 32
658 11:03:30.353208 CA_UI_PI_RATIO = 0
659 11:03:30.356397 ===================================
660 11:03:30.359677 ===================================
661 11:03:30.359755 memory_type:LPDDR4
662 11:03:30.362631 GP_NUM : 10
663 11:03:30.365759 SRAM_EN : 1
664 11:03:30.365840 MD32_EN : 0
665 11:03:30.369355 ===================================
666 11:03:30.372681 [ANA_INIT] >>>>>>>>>>>>>>
667 11:03:30.376649 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 11:03:30.379719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 11:03:30.383045 ===================================
670 11:03:30.386035 data_rate = 1600,PCW = 0X7600
671 11:03:30.386179 ===================================
672 11:03:30.389972 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 11:03:30.396363 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:03:30.403090 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 11:03:30.406487 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 11:03:30.409932 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:03:30.413512 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 11:03:30.416170 [ANA_INIT] flow start
679 11:03:30.416276 [ANA_INIT] PLL >>>>>>>>
680 11:03:30.419933 [ANA_INIT] PLL <<<<<<<<
681 11:03:30.423066 [ANA_INIT] MIDPI >>>>>>>>
682 11:03:30.426219 [ANA_INIT] MIDPI <<<<<<<<
683 11:03:30.426309 [ANA_INIT] DLL >>>>>>>>
684 11:03:30.430187 [ANA_INIT] flow end
685 11:03:30.433031 ============ LP4 DIFF to SE enter ============
686 11:03:30.436441 ============ LP4 DIFF to SE exit ============
687 11:03:30.439663 [ANA_INIT] <<<<<<<<<<<<<
688 11:03:30.443376 [Flow] Enable top DCM control >>>>>
689 11:03:30.446864 [Flow] Enable top DCM control <<<<<
690 11:03:30.449777 Enable DLL master slave shuffle
691 11:03:30.456859 ==============================================================
692 11:03:30.456978 Gating Mode config
693 11:03:30.463235 ==============================================================
694 11:03:30.463395 Config description:
695 11:03:30.473062 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 11:03:30.479874 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 11:03:30.486991 SELPH_MODE 0: By rank 1: By Phase
698 11:03:30.490255 ==============================================================
699 11:03:30.493492 GAT_TRACK_EN = 1
700 11:03:30.496657 RX_GATING_MODE = 2
701 11:03:30.499958 RX_GATING_TRACK_MODE = 2
702 11:03:30.503338 SELPH_MODE = 1
703 11:03:30.507105 PICG_EARLY_EN = 1
704 11:03:30.510264 VALID_LAT_VALUE = 1
705 11:03:30.513488 ==============================================================
706 11:03:30.517012 Enter into Gating configuration >>>>
707 11:03:30.519780 Exit from Gating configuration <<<<
708 11:03:30.523272 Enter into DVFS_PRE_config >>>>>
709 11:03:30.537327 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 11:03:30.537410 Exit from DVFS_PRE_config <<<<<
711 11:03:30.539984 Enter into PICG configuration >>>>
712 11:03:30.543462 Exit from PICG configuration <<<<
713 11:03:30.547111 [RX_INPUT] configuration >>>>>
714 11:03:30.550087 [RX_INPUT] configuration <<<<<
715 11:03:30.557247 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 11:03:30.560092 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 11:03:30.566822 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 11:03:30.573799 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 11:03:30.580176 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 11:03:30.587563 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 11:03:30.590492 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 11:03:30.593857 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 11:03:30.597458 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 11:03:30.600391 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 11:03:30.607082 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 11:03:30.610384 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 11:03:30.613758 ===================================
728 11:03:30.617707 LPDDR4 DRAM CONFIGURATION
729 11:03:30.620813 ===================================
730 11:03:30.620889 EX_ROW_EN[0] = 0x0
731 11:03:30.624101 EX_ROW_EN[1] = 0x0
732 11:03:30.624177 LP4Y_EN = 0x0
733 11:03:30.627173 WORK_FSP = 0x0
734 11:03:30.627247 WL = 0x2
735 11:03:30.630944 RL = 0x2
736 11:03:30.631018 BL = 0x2
737 11:03:30.634046 RPST = 0x0
738 11:03:30.634134 RD_PRE = 0x0
739 11:03:30.637225 WR_PRE = 0x1
740 11:03:30.637299 WR_PST = 0x0
741 11:03:30.640757 DBI_WR = 0x0
742 11:03:30.640831 DBI_RD = 0x0
743 11:03:30.644482 OTF = 0x1
744 11:03:30.647817 ===================================
745 11:03:30.650952 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 11:03:30.654190 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 11:03:30.660486 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 11:03:30.664149 ===================================
749 11:03:30.664223 LPDDR4 DRAM CONFIGURATION
750 11:03:30.667149 ===================================
751 11:03:30.670664 EX_ROW_EN[0] = 0x10
752 11:03:30.674076 EX_ROW_EN[1] = 0x0
753 11:03:30.674151 LP4Y_EN = 0x0
754 11:03:30.677723 WORK_FSP = 0x0
755 11:03:30.677797 WL = 0x2
756 11:03:30.680634 RL = 0x2
757 11:03:30.680741 BL = 0x2
758 11:03:30.684142 RPST = 0x0
759 11:03:30.684216 RD_PRE = 0x0
760 11:03:30.687696 WR_PRE = 0x1
761 11:03:30.687770 WR_PST = 0x0
762 11:03:30.690949 DBI_WR = 0x0
763 11:03:30.691023 DBI_RD = 0x0
764 11:03:30.694092 OTF = 0x1
765 11:03:30.697532 ===================================
766 11:03:30.703896 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 11:03:30.707282 nWR fixed to 40
768 11:03:30.707357 [ModeRegInit_LP4] CH0 RK0
769 11:03:30.710781 [ModeRegInit_LP4] CH0 RK1
770 11:03:30.714041 [ModeRegInit_LP4] CH1 RK0
771 11:03:30.714129 [ModeRegInit_LP4] CH1 RK1
772 11:03:30.717661 match AC timing 13
773 11:03:30.721312 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 11:03:30.724415 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 11:03:30.731003 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 11:03:30.734254 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 11:03:30.740826 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 11:03:30.740902 [EMI DOE] emi_dcm 0
779 11:03:30.747800 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 11:03:30.747876 ==
781 11:03:30.750987 Dram Type= 6, Freq= 0, CH_0, rank 0
782 11:03:30.753996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 11:03:30.754082 ==
784 11:03:30.760981 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 11:03:30.763974 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 11:03:30.774236 [CA 0] Center 36 (6~67) winsize 62
787 11:03:30.777613 [CA 1] Center 36 (6~67) winsize 62
788 11:03:30.780573 [CA 2] Center 34 (4~65) winsize 62
789 11:03:30.783904 [CA 3] Center 33 (3~64) winsize 62
790 11:03:30.787206 [CA 4] Center 33 (3~63) winsize 61
791 11:03:30.791032 [CA 5] Center 32 (2~62) winsize 61
792 11:03:30.791106
793 11:03:30.794782 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 11:03:30.794875
795 11:03:30.797760 [CATrainingPosCal] consider 1 rank data
796 11:03:30.802135 u2DelayCellTimex100 = 270/100 ps
797 11:03:30.804585 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 11:03:30.808282 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 11:03:30.811520 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 11:03:30.814696 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
801 11:03:30.821476 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
802 11:03:30.825426 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
803 11:03:30.825501
804 11:03:30.828138 CA PerBit enable=1, Macro0, CA PI delay=32
805 11:03:30.828213
806 11:03:30.831399 [CBTSetCACLKResult] CA Dly = 32
807 11:03:30.831474 CS Dly: 4 (0~35)
808 11:03:30.831531 ==
809 11:03:30.835249 Dram Type= 6, Freq= 0, CH_0, rank 1
810 11:03:30.838133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:03:30.841768 ==
812 11:03:30.845115 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 11:03:30.851394 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 11:03:30.860077 [CA 0] Center 37 (7~67) winsize 61
815 11:03:30.863778 [CA 1] Center 36 (6~67) winsize 62
816 11:03:30.866740 [CA 2] Center 34 (4~64) winsize 61
817 11:03:30.870647 [CA 3] Center 33 (3~64) winsize 62
818 11:03:30.873638 [CA 4] Center 32 (2~63) winsize 62
819 11:03:30.877557 [CA 5] Center 32 (2~63) winsize 62
820 11:03:30.877669
821 11:03:30.880720 [CmdBusTrainingLP45] Vref(ca) range 1: 30
822 11:03:30.880795
823 11:03:30.884068 [CATrainingPosCal] consider 2 rank data
824 11:03:30.887198 u2DelayCellTimex100 = 270/100 ps
825 11:03:30.890576 CA0 delay=37 (7~67),Diff = 5 PI (36 cell)
826 11:03:30.893800 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 11:03:30.897714 CA2 delay=34 (4~64),Diff = 2 PI (14 cell)
828 11:03:30.903881 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
829 11:03:30.907386 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
830 11:03:30.910481 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
831 11:03:30.910558
832 11:03:30.914480 CA PerBit enable=1, Macro0, CA PI delay=32
833 11:03:30.914555
834 11:03:30.917170 [CBTSetCACLKResult] CA Dly = 32
835 11:03:30.917246 CS Dly: 4 (0~36)
836 11:03:30.917302
837 11:03:30.920475 ----->DramcWriteLeveling(PI) begin...
838 11:03:30.920550 ==
839 11:03:30.924216 Dram Type= 6, Freq= 0, CH_0, rank 0
840 11:03:30.930811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 11:03:30.930893 ==
842 11:03:30.934360 Write leveling (Byte 0): 33 => 33
843 11:03:30.937238 Write leveling (Byte 1): 29 => 29
844 11:03:30.937317 DramcWriteLeveling(PI) end<-----
845 11:03:30.937375
846 11:03:30.941100 ==
847 11:03:30.944284 Dram Type= 6, Freq= 0, CH_0, rank 0
848 11:03:30.947372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 11:03:30.947452 ==
850 11:03:30.950836 [Gating] SW mode calibration
851 11:03:30.957701 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 11:03:30.960784 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 11:03:30.967472 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 11:03:30.970832 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 11:03:30.974306 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 11:03:30.981207 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:03:30.984713 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:03:30.987847 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:03:30.990720 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:03:30.998058 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:03:31.001092 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:03:31.004957 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:03:31.011334 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:03:31.015229 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:03:31.018306 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:03:31.024538 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:03:31.027734 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:03:31.031320 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:03:31.034778 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:03:31.041767 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
871 11:03:31.044966 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
872 11:03:31.047908 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
873 11:03:31.054961 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:03:31.057980 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:03:31.061819 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:03:31.068036 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:03:31.071902 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:03:31.074993 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 11:03:31.081657 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
880 11:03:31.085267 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 11:03:31.088444 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:03:31.095148 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:03:31.098200 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 11:03:31.101589 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 11:03:31.108275 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 11:03:31.111619 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
887 11:03:31.115009 0 10 8 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
888 11:03:31.118480 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
889 11:03:31.125290 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:03:31.128819 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:03:31.131946 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 11:03:31.138884 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 11:03:31.141929 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 11:03:31.145140 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
895 11:03:31.152099 0 11 8 | B1->B0 | 2929 4141 | 1 0 | (0 0) (0 0)
896 11:03:31.154881 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
897 11:03:31.158638 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:03:31.165720 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:03:31.168726 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 11:03:31.171816 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 11:03:31.178933 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 11:03:31.181648 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 11:03:31.185549 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
904 11:03:31.188575 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:03:31.195052 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:03:31.198761 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:03:31.202370 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:03:31.208910 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:03:31.212452 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:03:31.215520 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:03:31.222383 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:03:31.225896 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:03:31.229243 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:03:31.235552 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:03:31.239682 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 11:03:31.242345 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 11:03:31.246098 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 11:03:31.252529 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 11:03:31.255749 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
920 11:03:31.259542 Total UI for P1: 0, mck2ui 16
921 11:03:31.262324 best dqsien dly found for B0: ( 0, 14, 6)
922 11:03:31.265715 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
923 11:03:31.272336 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 11:03:31.272414 Total UI for P1: 0, mck2ui 16
925 11:03:31.279352 best dqsien dly found for B1: ( 0, 14, 12)
926 11:03:31.282535 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
927 11:03:31.285719 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
928 11:03:31.285794
929 11:03:31.288969 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
930 11:03:31.292723 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
931 11:03:31.295875 [Gating] SW calibration Done
932 11:03:31.295950 ==
933 11:03:31.299193 Dram Type= 6, Freq= 0, CH_0, rank 0
934 11:03:31.302312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 11:03:31.302388 ==
936 11:03:31.305624 RX Vref Scan: 0
937 11:03:31.305698
938 11:03:31.305755 RX Vref 0 -> 0, step: 1
939 11:03:31.305809
940 11:03:31.309073 RX Delay -130 -> 252, step: 16
941 11:03:31.312663 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
942 11:03:31.319203 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
943 11:03:31.322751 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
944 11:03:31.326242 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
945 11:03:31.329568 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
946 11:03:31.332600 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
947 11:03:31.339603 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
948 11:03:31.342881 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
949 11:03:31.346075 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
950 11:03:31.349071 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
951 11:03:31.352555 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
952 11:03:31.359766 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
953 11:03:31.362884 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
954 11:03:31.365745 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
955 11:03:31.369437 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
956 11:03:31.372701 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
957 11:03:31.372793 ==
958 11:03:31.376667 Dram Type= 6, Freq= 0, CH_0, rank 0
959 11:03:31.382914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 11:03:31.382990 ==
961 11:03:31.383066 DQS Delay:
962 11:03:31.386170 DQS0 = 0, DQS1 = 0
963 11:03:31.386259 DQM Delay:
964 11:03:31.386348 DQM0 = 89, DQM1 = 79
965 11:03:31.389183 DQ Delay:
966 11:03:31.392697 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
967 11:03:31.395820 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
968 11:03:31.399361 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
969 11:03:31.402816 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
970 11:03:31.402886
971 11:03:31.402942
972 11:03:31.402994 ==
973 11:03:31.406425 Dram Type= 6, Freq= 0, CH_0, rank 0
974 11:03:31.409790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 11:03:31.409866 ==
976 11:03:31.409925
977 11:03:31.409977
978 11:03:31.412796 TX Vref Scan disable
979 11:03:31.416265 == TX Byte 0 ==
980 11:03:31.419804 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
981 11:03:31.422653 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
982 11:03:31.426611 == TX Byte 1 ==
983 11:03:31.429607 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
984 11:03:31.433141 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
985 11:03:31.433216 ==
986 11:03:31.436125 Dram Type= 6, Freq= 0, CH_0, rank 0
987 11:03:31.439460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 11:03:31.439560 ==
989 11:03:31.454569 TX Vref=22, minBit 8, minWin=27, winSum=447
990 11:03:31.457799 TX Vref=24, minBit 8, minWin=27, winSum=451
991 11:03:31.461051 TX Vref=26, minBit 10, minWin=27, winSum=454
992 11:03:31.464307 TX Vref=28, minBit 10, minWin=27, winSum=455
993 11:03:31.467354 TX Vref=30, minBit 4, minWin=28, winSum=456
994 11:03:31.473974 TX Vref=32, minBit 2, minWin=28, winSum=455
995 11:03:31.477689 [TxChooseVref] Worse bit 4, Min win 28, Win sum 456, Final Vref 30
996 11:03:31.477803
997 11:03:31.480997 Final TX Range 1 Vref 30
998 11:03:31.481098
999 11:03:31.481166 ==
1000 11:03:31.483849 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 11:03:31.487289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 11:03:31.487393 ==
1003 11:03:31.487486
1004 11:03:31.490974
1005 11:03:31.491113 TX Vref Scan disable
1006 11:03:31.494113 == TX Byte 0 ==
1007 11:03:31.497480 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1008 11:03:31.501204 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1009 11:03:31.504036 == TX Byte 1 ==
1010 11:03:31.507566 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1011 11:03:31.510986 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1012 11:03:31.511075
1013 11:03:31.514166 [DATLAT]
1014 11:03:31.514241 Freq=800, CH0 RK0
1015 11:03:31.514299
1016 11:03:31.517802 DATLAT Default: 0xa
1017 11:03:31.517878 0, 0xFFFF, sum = 0
1018 11:03:31.521224 1, 0xFFFF, sum = 0
1019 11:03:31.521299 2, 0xFFFF, sum = 0
1020 11:03:31.524150 3, 0xFFFF, sum = 0
1021 11:03:31.524226 4, 0xFFFF, sum = 0
1022 11:03:31.527764 5, 0xFFFF, sum = 0
1023 11:03:31.527842 6, 0xFFFF, sum = 0
1024 11:03:31.531377 7, 0xFFFF, sum = 0
1025 11:03:31.534758 8, 0xFFFF, sum = 0
1026 11:03:31.534837 9, 0x0, sum = 1
1027 11:03:31.534898 10, 0x0, sum = 2
1028 11:03:31.538144 11, 0x0, sum = 3
1029 11:03:31.538222 12, 0x0, sum = 4
1030 11:03:31.541356 best_step = 10
1031 11:03:31.541433
1032 11:03:31.541492 ==
1033 11:03:31.544296 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 11:03:31.547977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 11:03:31.548055 ==
1036 11:03:31.551379 RX Vref Scan: 1
1037 11:03:31.551456
1038 11:03:31.551515 Set Vref Range= 32 -> 127
1039 11:03:31.551569
1040 11:03:31.554671 RX Vref 32 -> 127, step: 1
1041 11:03:31.554748
1042 11:03:31.557797 RX Delay -95 -> 252, step: 8
1043 11:03:31.557873
1044 11:03:31.561215 Set Vref, RX VrefLevel [Byte0]: 32
1045 11:03:31.564310 [Byte1]: 32
1046 11:03:31.564387
1047 11:03:31.567668 Set Vref, RX VrefLevel [Byte0]: 33
1048 11:03:31.571470 [Byte1]: 33
1049 11:03:31.574777
1050 11:03:31.574852 Set Vref, RX VrefLevel [Byte0]: 34
1051 11:03:31.577632 [Byte1]: 34
1052 11:03:31.582627
1053 11:03:31.582720 Set Vref, RX VrefLevel [Byte0]: 35
1054 11:03:31.585668 [Byte1]: 35
1055 11:03:31.590103
1056 11:03:31.590179 Set Vref, RX VrefLevel [Byte0]: 36
1057 11:03:31.592984 [Byte1]: 36
1058 11:03:31.597689
1059 11:03:31.597765 Set Vref, RX VrefLevel [Byte0]: 37
1060 11:03:31.600860 [Byte1]: 37
1061 11:03:31.604925
1062 11:03:31.608087 Set Vref, RX VrefLevel [Byte0]: 38
1063 11:03:31.608164 [Byte1]: 38
1064 11:03:31.612468
1065 11:03:31.612544 Set Vref, RX VrefLevel [Byte0]: 39
1066 11:03:31.616114 [Byte1]: 39
1067 11:03:31.619913
1068 11:03:31.619988 Set Vref, RX VrefLevel [Byte0]: 40
1069 11:03:31.623704 [Byte1]: 40
1070 11:03:31.627898
1071 11:03:31.627973 Set Vref, RX VrefLevel [Byte0]: 41
1072 11:03:31.631237 [Byte1]: 41
1073 11:03:31.635080
1074 11:03:31.635195 Set Vref, RX VrefLevel [Byte0]: 42
1075 11:03:31.638723 [Byte1]: 42
1076 11:03:31.642886
1077 11:03:31.642960 Set Vref, RX VrefLevel [Byte0]: 43
1078 11:03:31.646266 [Byte1]: 43
1079 11:03:31.650490
1080 11:03:31.650565 Set Vref, RX VrefLevel [Byte0]: 44
1081 11:03:31.653693 [Byte1]: 44
1082 11:03:31.657899
1083 11:03:31.657973 Set Vref, RX VrefLevel [Byte0]: 45
1084 11:03:31.661482 [Byte1]: 45
1085 11:03:31.665916
1086 11:03:31.665991 Set Vref, RX VrefLevel [Byte0]: 46
1087 11:03:31.669052 [Byte1]: 46
1088 11:03:31.673179
1089 11:03:31.673253 Set Vref, RX VrefLevel [Byte0]: 47
1090 11:03:31.676925 [Byte1]: 47
1091 11:03:31.680888
1092 11:03:31.680962 Set Vref, RX VrefLevel [Byte0]: 48
1093 11:03:31.684164 [Byte1]: 48
1094 11:03:31.688327
1095 11:03:31.688401 Set Vref, RX VrefLevel [Byte0]: 49
1096 11:03:31.691942 [Byte1]: 49
1097 11:03:31.696412
1098 11:03:31.696486 Set Vref, RX VrefLevel [Byte0]: 50
1099 11:03:31.699532 [Byte1]: 50
1100 11:03:31.703954
1101 11:03:31.704058 Set Vref, RX VrefLevel [Byte0]: 51
1102 11:03:31.706887 [Byte1]: 51
1103 11:03:31.711430
1104 11:03:31.711504 Set Vref, RX VrefLevel [Byte0]: 52
1105 11:03:31.714986 [Byte1]: 52
1106 11:03:31.718937
1107 11:03:31.719032 Set Vref, RX VrefLevel [Byte0]: 53
1108 11:03:31.722698 [Byte1]: 53
1109 11:03:31.726407
1110 11:03:31.726473 Set Vref, RX VrefLevel [Byte0]: 54
1111 11:03:31.730240 [Byte1]: 54
1112 11:03:31.734366
1113 11:03:31.734438 Set Vref, RX VrefLevel [Byte0]: 55
1114 11:03:31.740392 [Byte1]: 55
1115 11:03:31.740482
1116 11:03:31.744149 Set Vref, RX VrefLevel [Byte0]: 56
1117 11:03:31.747601 [Byte1]: 56
1118 11:03:31.747668
1119 11:03:31.750803 Set Vref, RX VrefLevel [Byte0]: 57
1120 11:03:31.753997 [Byte1]: 57
1121 11:03:31.754113
1122 11:03:31.757005 Set Vref, RX VrefLevel [Byte0]: 58
1123 11:03:31.760425 [Byte1]: 58
1124 11:03:31.764776
1125 11:03:31.764869 Set Vref, RX VrefLevel [Byte0]: 59
1126 11:03:31.767721 [Byte1]: 59
1127 11:03:31.771961
1128 11:03:31.772057 Set Vref, RX VrefLevel [Byte0]: 60
1129 11:03:31.775403 [Byte1]: 60
1130 11:03:31.780113
1131 11:03:31.780203 Set Vref, RX VrefLevel [Byte0]: 61
1132 11:03:31.783055 [Byte1]: 61
1133 11:03:31.787273
1134 11:03:31.787371 Set Vref, RX VrefLevel [Byte0]: 62
1135 11:03:31.790415 [Byte1]: 62
1136 11:03:31.795387
1137 11:03:31.795453 Set Vref, RX VrefLevel [Byte0]: 63
1138 11:03:31.797989 [Byte1]: 63
1139 11:03:31.802553
1140 11:03:31.802624 Set Vref, RX VrefLevel [Byte0]: 64
1141 11:03:31.805550 [Byte1]: 64
1142 11:03:31.810123
1143 11:03:31.810190 Set Vref, RX VrefLevel [Byte0]: 65
1144 11:03:31.813693 [Byte1]: 65
1145 11:03:31.818045
1146 11:03:31.818128 Set Vref, RX VrefLevel [Byte0]: 66
1147 11:03:31.821297 [Byte1]: 66
1148 11:03:31.825724
1149 11:03:31.825819 Set Vref, RX VrefLevel [Byte0]: 67
1150 11:03:31.828753 [Byte1]: 67
1151 11:03:31.832598
1152 11:03:31.832684 Set Vref, RX VrefLevel [Byte0]: 68
1153 11:03:31.836195 [Byte1]: 68
1154 11:03:31.840800
1155 11:03:31.840886 Set Vref, RX VrefLevel [Byte0]: 69
1156 11:03:31.843915 [Byte1]: 69
1157 11:03:31.848446
1158 11:03:31.848514 Set Vref, RX VrefLevel [Byte0]: 70
1159 11:03:31.851717 [Byte1]: 70
1160 11:03:31.855702
1161 11:03:31.855767 Set Vref, RX VrefLevel [Byte0]: 71
1162 11:03:31.858908 [Byte1]: 71
1163 11:03:31.863080
1164 11:03:31.863154 Set Vref, RX VrefLevel [Byte0]: 72
1165 11:03:31.866234 [Byte1]: 72
1166 11:03:31.870649
1167 11:03:31.870723 Set Vref, RX VrefLevel [Byte0]: 73
1168 11:03:31.874039 [Byte1]: 73
1169 11:03:31.878540
1170 11:03:31.878614 Set Vref, RX VrefLevel [Byte0]: 74
1171 11:03:31.881468 [Byte1]: 74
1172 11:03:31.886246
1173 11:03:31.886364 Set Vref, RX VrefLevel [Byte0]: 75
1174 11:03:31.889171 [Byte1]: 75
1175 11:03:31.893341
1176 11:03:31.893415 Set Vref, RX VrefLevel [Byte0]: 76
1177 11:03:31.896894 [Byte1]: 76
1178 11:03:31.901419
1179 11:03:31.901493 Set Vref, RX VrefLevel [Byte0]: 77
1180 11:03:31.904604 [Byte1]: 77
1181 11:03:31.908946
1182 11:03:31.909020 Final RX Vref Byte 0 = 62 to rank0
1183 11:03:31.912129 Final RX Vref Byte 1 = 54 to rank0
1184 11:03:31.915933 Final RX Vref Byte 0 = 62 to rank1
1185 11:03:31.919163 Final RX Vref Byte 1 = 54 to rank1==
1186 11:03:31.922134 Dram Type= 6, Freq= 0, CH_0, rank 0
1187 11:03:31.925608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1188 11:03:31.928964 ==
1189 11:03:31.929054 DQS Delay:
1190 11:03:31.929135 DQS0 = 0, DQS1 = 0
1191 11:03:31.932594 DQM Delay:
1192 11:03:31.932672 DQM0 = 92, DQM1 = 84
1193 11:03:31.935572 DQ Delay:
1194 11:03:31.935678 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1195 11:03:31.938748 DQ4 =96, DQ5 =80, DQ6 =96, DQ7 =100
1196 11:03:31.942328 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1197 11:03:31.945601 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =92
1198 11:03:31.948922
1199 11:03:31.948996
1200 11:03:31.955710 [DQSOSCAuto] RK0, (LSB)MR18= 0x544a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
1201 11:03:31.959088 CH0 RK0: MR19=606, MR18=544A
1202 11:03:31.965845 CH0_RK0: MR19=0x606, MR18=0x544A, DQSOSC=388, MR23=63, INC=98, DEC=65
1203 11:03:31.965961
1204 11:03:31.969050 ----->DramcWriteLeveling(PI) begin...
1205 11:03:31.969126 ==
1206 11:03:31.972417 Dram Type= 6, Freq= 0, CH_0, rank 1
1207 11:03:31.976176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1208 11:03:31.976252 ==
1209 11:03:31.979275 Write leveling (Byte 0): 33 => 33
1210 11:03:31.982646 Write leveling (Byte 1): 30 => 30
1211 11:03:31.985720 DramcWriteLeveling(PI) end<-----
1212 11:03:31.985811
1213 11:03:31.985870 ==
1214 11:03:31.989570 Dram Type= 6, Freq= 0, CH_0, rank 1
1215 11:03:31.993067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1216 11:03:31.993142 ==
1217 11:03:31.996327 [Gating] SW mode calibration
1218 11:03:32.002352 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1219 11:03:32.009289 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1220 11:03:32.053413 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1221 11:03:32.053741 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1222 11:03:32.053821 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1223 11:03:32.053879 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:03:32.053944 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:03:32.054537 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:03:32.054829 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:03:32.054934 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:03:32.054987 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:03:32.055048 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:03:32.097215 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:03:32.097564 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:03:32.097646 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:03:32.097712 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:03:32.098402 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:03:32.098659 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:03:32.098735 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:03:32.098793 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1238 11:03:32.099468 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1239 11:03:32.099767 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:03:32.113552 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:03:32.113867 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 11:03:32.113935 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:03:32.117229 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:03:32.119993 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 11:03:32.123523 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 11:03:32.126570 0 9 8 | B1->B0 | 3030 2929 | 0 0 | (0 0) (0 0)
1247 11:03:32.129813 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 11:03:32.137090 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 11:03:32.140009 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 11:03:32.143463 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 11:03:32.146581 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 11:03:32.153317 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 11:03:32.157120 0 10 4 | B1->B0 | 3232 3333 | 1 1 | (1 1) (1 1)
1254 11:03:32.160488 0 10 8 | B1->B0 | 2828 2626 | 0 0 | (1 0) (1 0)
1255 11:03:32.166814 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 11:03:32.170701 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 11:03:32.173383 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 11:03:32.180051 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 11:03:32.183865 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 11:03:32.187307 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 11:03:32.193775 0 11 4 | B1->B0 | 2a29 2525 | 1 0 | (0 0) (0 0)
1262 11:03:32.196784 0 11 8 | B1->B0 | 3b3b 3a3a | 0 0 | (0 0) (0 0)
1263 11:03:32.199945 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 11:03:32.207195 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 11:03:32.210470 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 11:03:32.213786 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 11:03:32.220334 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 11:03:32.223688 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 11:03:32.226704 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 11:03:32.233648 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1271 11:03:32.237252 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:03:32.240243 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:03:32.243460 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:03:32.250360 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:03:32.253844 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:03:32.256812 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:03:32.263494 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:03:32.267351 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 11:03:32.270549 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 11:03:32.277459 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 11:03:32.280256 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 11:03:32.283759 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 11:03:32.290511 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 11:03:32.294307 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 11:03:32.297051 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 11:03:32.303831 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1287 11:03:32.307067 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1288 11:03:32.310471 Total UI for P1: 0, mck2ui 16
1289 11:03:32.314288 best dqsien dly found for B0: ( 0, 14, 8)
1290 11:03:32.317121 Total UI for P1: 0, mck2ui 16
1291 11:03:32.320244 best dqsien dly found for B1: ( 0, 14, 8)
1292 11:03:32.323657 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1293 11:03:32.327560 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1294 11:03:32.327654
1295 11:03:32.330985 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1296 11:03:32.333624 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1297 11:03:32.337116 [Gating] SW calibration Done
1298 11:03:32.337196 ==
1299 11:03:32.340770 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 11:03:32.344182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 11:03:32.344260 ==
1302 11:03:32.347485 RX Vref Scan: 0
1303 11:03:32.347588
1304 11:03:32.347674 RX Vref 0 -> 0, step: 1
1305 11:03:32.347753
1306 11:03:32.350566 RX Delay -130 -> 252, step: 16
1307 11:03:32.354254 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1308 11:03:32.360502 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1309 11:03:32.364000 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1310 11:03:32.367387 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1311 11:03:32.370977 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1312 11:03:32.374323 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1313 11:03:32.380874 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1314 11:03:32.384110 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1315 11:03:32.387976 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1316 11:03:32.391162 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1317 11:03:32.393967 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1318 11:03:32.400950 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1319 11:03:32.404160 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
1320 11:03:32.407325 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1321 11:03:32.410922 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1322 11:03:32.414032 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1323 11:03:32.418057 ==
1324 11:03:32.418134 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 11:03:32.424174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 11:03:32.424252 ==
1327 11:03:32.424312 DQS Delay:
1328 11:03:32.427347 DQS0 = 0, DQS1 = 0
1329 11:03:32.427438 DQM Delay:
1330 11:03:32.431086 DQM0 = 93, DQM1 = 85
1331 11:03:32.431205 DQ Delay:
1332 11:03:32.434405 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1333 11:03:32.437898 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1334 11:03:32.441105 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1335 11:03:32.444190 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =93
1336 11:03:32.444265
1337 11:03:32.444322
1338 11:03:32.444375 ==
1339 11:03:32.447993 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 11:03:32.450986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 11:03:32.451062 ==
1342 11:03:32.451120
1343 11:03:32.451172
1344 11:03:32.454218 TX Vref Scan disable
1345 11:03:32.457466 == TX Byte 0 ==
1346 11:03:32.461018 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1347 11:03:32.464366 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1348 11:03:32.467892 == TX Byte 1 ==
1349 11:03:32.470954 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1350 11:03:32.474365 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1351 11:03:32.474440 ==
1352 11:03:32.477790 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 11:03:32.481045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 11:03:32.481120 ==
1355 11:03:32.495696 TX Vref=22, minBit 8, minWin=27, winSum=446
1356 11:03:32.498731 TX Vref=24, minBit 10, minWin=27, winSum=453
1357 11:03:32.502229 TX Vref=26, minBit 10, minWin=27, winSum=453
1358 11:03:32.505575 TX Vref=28, minBit 7, minWin=28, winSum=458
1359 11:03:32.509264 TX Vref=30, minBit 3, minWin=28, winSum=457
1360 11:03:32.515678 TX Vref=32, minBit 10, minWin=27, winSum=453
1361 11:03:32.519184 [TxChooseVref] Worse bit 7, Min win 28, Win sum 458, Final Vref 28
1362 11:03:32.519325
1363 11:03:32.522347 Final TX Range 1 Vref 28
1364 11:03:32.522423
1365 11:03:32.522479 ==
1366 11:03:32.525779 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 11:03:32.528896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 11:03:32.528995 ==
1369 11:03:32.532891
1370 11:03:32.532988
1371 11:03:32.533070 TX Vref Scan disable
1372 11:03:32.535987 == TX Byte 0 ==
1373 11:03:32.539007 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1374 11:03:32.543039 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1375 11:03:32.545844 == TX Byte 1 ==
1376 11:03:32.548981 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1377 11:03:32.552740 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1378 11:03:32.555713
1379 11:03:32.555810 [DATLAT]
1380 11:03:32.555894 Freq=800, CH0 RK1
1381 11:03:32.555973
1382 11:03:32.559670 DATLAT Default: 0xa
1383 11:03:32.559745 0, 0xFFFF, sum = 0
1384 11:03:32.562256 1, 0xFFFF, sum = 0
1385 11:03:32.562331 2, 0xFFFF, sum = 0
1386 11:03:32.565971 3, 0xFFFF, sum = 0
1387 11:03:32.566097 4, 0xFFFF, sum = 0
1388 11:03:32.569139 5, 0xFFFF, sum = 0
1389 11:03:32.572455 6, 0xFFFF, sum = 0
1390 11:03:32.572532 7, 0xFFFF, sum = 0
1391 11:03:32.575985 8, 0xFFFF, sum = 0
1392 11:03:32.576061 9, 0x0, sum = 1
1393 11:03:32.576120 10, 0x0, sum = 2
1394 11:03:32.579065 11, 0x0, sum = 3
1395 11:03:32.579156 12, 0x0, sum = 4
1396 11:03:32.582635 best_step = 10
1397 11:03:32.582709
1398 11:03:32.582766 ==
1399 11:03:32.585882 Dram Type= 6, Freq= 0, CH_0, rank 1
1400 11:03:32.589310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1401 11:03:32.589385 ==
1402 11:03:32.592564 RX Vref Scan: 0
1403 11:03:32.592638
1404 11:03:32.592694 RX Vref 0 -> 0, step: 1
1405 11:03:32.592747
1406 11:03:32.596391 RX Delay -79 -> 252, step: 8
1407 11:03:32.602876 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1408 11:03:32.606305 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1409 11:03:32.609308 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1410 11:03:32.612830 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1411 11:03:32.616093 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1412 11:03:32.622930 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1413 11:03:32.625895 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1414 11:03:32.629550 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1415 11:03:32.632866 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1416 11:03:32.636144 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1417 11:03:32.639503 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1418 11:03:32.646404 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1419 11:03:32.649324 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1420 11:03:32.652912 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1421 11:03:32.656277 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1422 11:03:32.663156 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1423 11:03:32.663231 ==
1424 11:03:32.666132 Dram Type= 6, Freq= 0, CH_0, rank 1
1425 11:03:32.669949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1426 11:03:32.670047 ==
1427 11:03:32.670106 DQS Delay:
1428 11:03:32.673422 DQS0 = 0, DQS1 = 0
1429 11:03:32.673496 DQM Delay:
1430 11:03:32.676147 DQM0 = 93, DQM1 = 83
1431 11:03:32.676221 DQ Delay:
1432 11:03:32.680056 DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =88
1433 11:03:32.683164 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1434 11:03:32.686314 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1435 11:03:32.689630 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1436 11:03:32.689704
1437 11:03:32.689761
1438 11:03:32.696222 [DQSOSCAuto] RK1, (LSB)MR18= 0x4717, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1439 11:03:32.700176 CH0 RK1: MR19=606, MR18=4717
1440 11:03:32.706268 CH0_RK1: MR19=0x606, MR18=0x4717, DQSOSC=392, MR23=63, INC=96, DEC=64
1441 11:03:32.709844 [RxdqsGatingPostProcess] freq 800
1442 11:03:32.712919 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1443 11:03:32.716325 Pre-setting of DQS Precalculation
1444 11:03:32.723276 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1445 11:03:32.723351 ==
1446 11:03:32.726303 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 11:03:32.729645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 11:03:32.729722 ==
1449 11:03:32.736488 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1450 11:03:32.743195 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1451 11:03:32.750612 [CA 0] Center 36 (6~67) winsize 62
1452 11:03:32.754501 [CA 1] Center 36 (6~67) winsize 62
1453 11:03:32.757591 [CA 2] Center 35 (5~66) winsize 62
1454 11:03:32.760937 [CA 3] Center 34 (4~65) winsize 62
1455 11:03:32.764734 [CA 4] Center 34 (4~65) winsize 62
1456 11:03:32.767731 [CA 5] Center 34 (4~65) winsize 62
1457 11:03:32.767806
1458 11:03:32.770841 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1459 11:03:32.770915
1460 11:03:32.774617 [CATrainingPosCal] consider 1 rank data
1461 11:03:32.777836 u2DelayCellTimex100 = 270/100 ps
1462 11:03:32.780945 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1463 11:03:32.783909 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1464 11:03:32.791208 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1465 11:03:32.794342 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1466 11:03:32.797933 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1467 11:03:32.800529 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1468 11:03:32.800618
1469 11:03:32.804350 CA PerBit enable=1, Macro0, CA PI delay=34
1470 11:03:32.804424
1471 11:03:32.807431 [CBTSetCACLKResult] CA Dly = 34
1472 11:03:32.807505 CS Dly: 6 (0~37)
1473 11:03:32.807563 ==
1474 11:03:32.810876 Dram Type= 6, Freq= 0, CH_1, rank 1
1475 11:03:32.817396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1476 11:03:32.817471 ==
1477 11:03:32.821376 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1478 11:03:32.827621 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1479 11:03:32.837095 [CA 0] Center 36 (6~67) winsize 62
1480 11:03:32.841635 [CA 1] Center 37 (6~68) winsize 63
1481 11:03:32.844173 [CA 2] Center 35 (4~66) winsize 63
1482 11:03:32.847016 [CA 3] Center 34 (4~65) winsize 62
1483 11:03:32.850175 [CA 4] Center 35 (5~66) winsize 62
1484 11:03:32.854144 [CA 5] Center 34 (4~65) winsize 62
1485 11:03:32.854219
1486 11:03:32.857296 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1487 11:03:32.857373
1488 11:03:32.860602 [CATrainingPosCal] consider 2 rank data
1489 11:03:32.863990 u2DelayCellTimex100 = 270/100 ps
1490 11:03:32.867103 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1491 11:03:32.870323 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1492 11:03:32.877370 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1493 11:03:32.880593 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1494 11:03:32.883792 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1495 11:03:32.886955 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1496 11:03:32.887045
1497 11:03:32.890372 CA PerBit enable=1, Macro0, CA PI delay=34
1498 11:03:32.890443
1499 11:03:32.893947 [CBTSetCACLKResult] CA Dly = 34
1500 11:03:32.894073 CS Dly: 6 (0~38)
1501 11:03:32.894158
1502 11:03:32.897238 ----->DramcWriteLeveling(PI) begin...
1503 11:03:32.897327 ==
1504 11:03:32.900407 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 11:03:32.907345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1506 11:03:32.907443 ==
1507 11:03:32.910360 Write leveling (Byte 0): 26 => 26
1508 11:03:32.914095 Write leveling (Byte 1): 26 => 26
1509 11:03:32.914171 DramcWriteLeveling(PI) end<-----
1510 11:03:32.917062
1511 11:03:32.917136 ==
1512 11:03:32.921002 Dram Type= 6, Freq= 0, CH_1, rank 0
1513 11:03:32.923897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1514 11:03:32.923973 ==
1515 11:03:32.927351 [Gating] SW mode calibration
1516 11:03:32.933724 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1517 11:03:32.937397 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1518 11:03:32.943863 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1519 11:03:32.947948 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1520 11:03:32.950872 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:03:32.957486 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:03:32.961154 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:03:32.964324 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:03:32.970785 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:03:32.973988 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:03:32.977763 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:03:32.980972 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:03:32.987817 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:03:32.991037 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:03:32.994250 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:03:33.000886 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:03:33.004254 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:03:33.007519 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:03:33.014384 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1535 11:03:33.017548 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1536 11:03:33.020743 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:03:33.027588 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:03:33.030839 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:03:33.034126 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:03:33.041073 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:03:33.044158 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 11:03:33.047479 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 11:03:33.054661 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1544 11:03:33.057490 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 11:03:33.060775 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 11:03:33.064478 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 11:03:33.070890 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 11:03:33.074449 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 11:03:33.077422 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 11:03:33.084163 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1551 11:03:33.087368 0 10 4 | B1->B0 | 3232 2c2c | 0 0 | (0 1) (0 0)
1552 11:03:33.090983 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
1553 11:03:33.097860 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 11:03:33.101033 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 11:03:33.104431 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 11:03:33.111009 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 11:03:33.114389 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 11:03:33.117729 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 11:03:33.124219 0 11 4 | B1->B0 | 2e2e 3a3a | 0 0 | (0 0) (0 0)
1560 11:03:33.127469 0 11 8 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
1561 11:03:33.131391 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 11:03:33.137635 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 11:03:33.140911 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 11:03:33.144553 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 11:03:33.147989 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 11:03:33.154517 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 11:03:33.157687 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1568 11:03:33.161449 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:03:33.167723 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:03:33.171156 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:03:33.174526 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:03:33.181550 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:03:33.184321 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:03:33.187889 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:03:33.194756 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:03:33.198143 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 11:03:33.201128 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 11:03:33.208234 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 11:03:33.211286 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 11:03:33.214760 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 11:03:33.221316 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 11:03:33.225331 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 11:03:33.228122 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1584 11:03:33.231407 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1585 11:03:33.235000 Total UI for P1: 0, mck2ui 16
1586 11:03:33.238337 best dqsien dly found for B0: ( 0, 14, 4)
1587 11:03:33.241270 Total UI for P1: 0, mck2ui 16
1588 11:03:33.244790 best dqsien dly found for B1: ( 0, 14, 4)
1589 11:03:33.248067 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1590 11:03:33.251351 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1591 11:03:33.251427
1592 11:03:33.258208 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1593 11:03:33.261484 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1594 11:03:33.261559 [Gating] SW calibration Done
1595 11:03:33.264880 ==
1596 11:03:33.267958 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 11:03:33.271184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 11:03:33.271260 ==
1599 11:03:33.271318 RX Vref Scan: 0
1600 11:03:33.271372
1601 11:03:33.275003 RX Vref 0 -> 0, step: 1
1602 11:03:33.275078
1603 11:03:33.278001 RX Delay -130 -> 252, step: 16
1604 11:03:33.281310 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1605 11:03:33.284940 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1606 11:03:33.288172 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1607 11:03:33.294776 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1608 11:03:33.298050 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1609 11:03:33.301319 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1610 11:03:33.304914 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1611 11:03:33.308183 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1612 11:03:33.314661 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1613 11:03:33.318689 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1614 11:03:33.321923 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1615 11:03:33.324865 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1616 11:03:33.328153 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1617 11:03:33.334880 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1618 11:03:33.338530 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1619 11:03:33.341434 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1620 11:03:33.341509 ==
1621 11:03:33.345663 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 11:03:33.348342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 11:03:33.348419 ==
1624 11:03:33.351807 DQS Delay:
1625 11:03:33.351882 DQS0 = 0, DQS1 = 0
1626 11:03:33.354955 DQM Delay:
1627 11:03:33.355030 DQM0 = 92, DQM1 = 86
1628 11:03:33.355089 DQ Delay:
1629 11:03:33.358821 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1630 11:03:33.361946 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1631 11:03:33.364987 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1632 11:03:33.368243 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1633 11:03:33.368318
1634 11:03:33.368376
1635 11:03:33.368429 ==
1636 11:03:33.371949 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 11:03:33.378704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 11:03:33.378780 ==
1639 11:03:33.378839
1640 11:03:33.378892
1641 11:03:33.378943 TX Vref Scan disable
1642 11:03:33.382346 == TX Byte 0 ==
1643 11:03:33.385578 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1644 11:03:33.391973 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1645 11:03:33.392049 == TX Byte 1 ==
1646 11:03:33.395327 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1647 11:03:33.402370 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1648 11:03:33.402446 ==
1649 11:03:33.405594 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 11:03:33.408884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 11:03:33.408960 ==
1652 11:03:33.421386 TX Vref=22, minBit 1, minWin=26, winSum=433
1653 11:03:33.424711 TX Vref=24, minBit 1, minWin=26, winSum=439
1654 11:03:33.427751 TX Vref=26, minBit 0, minWin=27, winSum=447
1655 11:03:33.431332 TX Vref=28, minBit 1, minWin=27, winSum=449
1656 11:03:33.434565 TX Vref=30, minBit 1, minWin=27, winSum=451
1657 11:03:33.437815 TX Vref=32, minBit 1, minWin=27, winSum=447
1658 11:03:33.444868 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 30
1659 11:03:33.444949
1660 11:03:33.447901 Final TX Range 1 Vref 30
1661 11:03:33.447977
1662 11:03:33.448035 ==
1663 11:03:33.451692 Dram Type= 6, Freq= 0, CH_1, rank 0
1664 11:03:33.454955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1665 11:03:33.455060 ==
1666 11:03:33.455118
1667 11:03:33.455204
1668 11:03:33.458178 TX Vref Scan disable
1669 11:03:33.461755 == TX Byte 0 ==
1670 11:03:33.464779 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1671 11:03:33.468377 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1672 11:03:33.471846 == TX Byte 1 ==
1673 11:03:33.474884 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1674 11:03:33.478234 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1675 11:03:33.478303
1676 11:03:33.481787 [DATLAT]
1677 11:03:33.481849 Freq=800, CH1 RK0
1678 11:03:33.481903
1679 11:03:33.485021 DATLAT Default: 0xa
1680 11:03:33.485095 0, 0xFFFF, sum = 0
1681 11:03:33.488171 1, 0xFFFF, sum = 0
1682 11:03:33.488248 2, 0xFFFF, sum = 0
1683 11:03:33.491665 3, 0xFFFF, sum = 0
1684 11:03:33.491741 4, 0xFFFF, sum = 0
1685 11:03:33.494721 5, 0xFFFF, sum = 0
1686 11:03:33.494797 6, 0xFFFF, sum = 0
1687 11:03:33.498333 7, 0xFFFF, sum = 0
1688 11:03:33.498421 8, 0xFFFF, sum = 0
1689 11:03:33.501375 9, 0x0, sum = 1
1690 11:03:33.501451 10, 0x0, sum = 2
1691 11:03:33.504801 11, 0x0, sum = 3
1692 11:03:33.504877 12, 0x0, sum = 4
1693 11:03:33.509025 best_step = 10
1694 11:03:33.509100
1695 11:03:33.509157 ==
1696 11:03:33.511426 Dram Type= 6, Freq= 0, CH_1, rank 0
1697 11:03:33.515157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1698 11:03:33.515286 ==
1699 11:03:33.518296 RX Vref Scan: 1
1700 11:03:33.518370
1701 11:03:33.518428 Set Vref Range= 32 -> 127
1702 11:03:33.518482
1703 11:03:33.522032 RX Vref 32 -> 127, step: 1
1704 11:03:33.522143
1705 11:03:33.524720 RX Delay -79 -> 252, step: 8
1706 11:03:33.524783
1707 11:03:33.528396 Set Vref, RX VrefLevel [Byte0]: 32
1708 11:03:33.531505 [Byte1]: 32
1709 11:03:33.531580
1710 11:03:33.535326 Set Vref, RX VrefLevel [Byte0]: 33
1711 11:03:33.538207 [Byte1]: 33
1712 11:03:33.538282
1713 11:03:33.541714 Set Vref, RX VrefLevel [Byte0]: 34
1714 11:03:33.544959 [Byte1]: 34
1715 11:03:33.548902
1716 11:03:33.549017 Set Vref, RX VrefLevel [Byte0]: 35
1717 11:03:33.552174 [Byte1]: 35
1718 11:03:33.556561
1719 11:03:33.556636 Set Vref, RX VrefLevel [Byte0]: 36
1720 11:03:33.559604 [Byte1]: 36
1721 11:03:33.563773
1722 11:03:33.563848 Set Vref, RX VrefLevel [Byte0]: 37
1723 11:03:33.567209 [Byte1]: 37
1724 11:03:33.571679
1725 11:03:33.571755 Set Vref, RX VrefLevel [Byte0]: 38
1726 11:03:33.574499 [Byte1]: 38
1727 11:03:33.579191
1728 11:03:33.579266 Set Vref, RX VrefLevel [Byte0]: 39
1729 11:03:33.582470 [Byte1]: 39
1730 11:03:33.586658
1731 11:03:33.586733 Set Vref, RX VrefLevel [Byte0]: 40
1732 11:03:33.591057 [Byte1]: 40
1733 11:03:33.594166
1734 11:03:33.594242 Set Vref, RX VrefLevel [Byte0]: 41
1735 11:03:33.597534 [Byte1]: 41
1736 11:03:33.601599
1737 11:03:33.601700 Set Vref, RX VrefLevel [Byte0]: 42
1738 11:03:33.604889 [Byte1]: 42
1739 11:03:33.609747
1740 11:03:33.609842 Set Vref, RX VrefLevel [Byte0]: 43
1741 11:03:33.612568 [Byte1]: 43
1742 11:03:33.616546
1743 11:03:33.616654 Set Vref, RX VrefLevel [Byte0]: 44
1744 11:03:33.619864 [Byte1]: 44
1745 11:03:33.624634
1746 11:03:33.624726 Set Vref, RX VrefLevel [Byte0]: 45
1747 11:03:33.627566 [Byte1]: 45
1748 11:03:33.631738
1749 11:03:33.631816 Set Vref, RX VrefLevel [Byte0]: 46
1750 11:03:33.634888 [Byte1]: 46
1751 11:03:33.639483
1752 11:03:33.639560 Set Vref, RX VrefLevel [Byte0]: 47
1753 11:03:33.642976 [Byte1]: 47
1754 11:03:33.647007
1755 11:03:33.647108 Set Vref, RX VrefLevel [Byte0]: 48
1756 11:03:33.650193 [Byte1]: 48
1757 11:03:33.654240
1758 11:03:33.654345 Set Vref, RX VrefLevel [Byte0]: 49
1759 11:03:33.657805 [Byte1]: 49
1760 11:03:33.662407
1761 11:03:33.662507 Set Vref, RX VrefLevel [Byte0]: 50
1762 11:03:33.665539 [Byte1]: 50
1763 11:03:33.669929
1764 11:03:33.670034 Set Vref, RX VrefLevel [Byte0]: 51
1765 11:03:33.673133 [Byte1]: 51
1766 11:03:33.676855
1767 11:03:33.676932 Set Vref, RX VrefLevel [Byte0]: 52
1768 11:03:33.680358 [Byte1]: 52
1769 11:03:33.684536
1770 11:03:33.684636 Set Vref, RX VrefLevel [Byte0]: 53
1771 11:03:33.687797 [Byte1]: 53
1772 11:03:33.692400
1773 11:03:33.692477 Set Vref, RX VrefLevel [Byte0]: 54
1774 11:03:33.695352 [Byte1]: 54
1775 11:03:33.699833
1776 11:03:33.699910 Set Vref, RX VrefLevel [Byte0]: 55
1777 11:03:33.703446 [Byte1]: 55
1778 11:03:33.707072
1779 11:03:33.707148 Set Vref, RX VrefLevel [Byte0]: 56
1780 11:03:33.710495 [Byte1]: 56
1781 11:03:33.714820
1782 11:03:33.714922 Set Vref, RX VrefLevel [Byte0]: 57
1783 11:03:33.718110 [Byte1]: 57
1784 11:03:33.722605
1785 11:03:33.722685 Set Vref, RX VrefLevel [Byte0]: 58
1786 11:03:33.725746 [Byte1]: 58
1787 11:03:33.729855
1788 11:03:33.733473 Set Vref, RX VrefLevel [Byte0]: 59
1789 11:03:33.733548 [Byte1]: 59
1790 11:03:33.737758
1791 11:03:33.737833 Set Vref, RX VrefLevel [Byte0]: 60
1792 11:03:33.740941 [Byte1]: 60
1793 11:03:33.745327
1794 11:03:33.745403 Set Vref, RX VrefLevel [Byte0]: 61
1795 11:03:33.748139 [Byte1]: 61
1796 11:03:33.752800
1797 11:03:33.752901 Set Vref, RX VrefLevel [Byte0]: 62
1798 11:03:33.757170 [Byte1]: 62
1799 11:03:33.760274
1800 11:03:33.760345 Set Vref, RX VrefLevel [Byte0]: 63
1801 11:03:33.763251 [Byte1]: 63
1802 11:03:33.767825
1803 11:03:33.767901 Set Vref, RX VrefLevel [Byte0]: 64
1804 11:03:33.771005 [Byte1]: 64
1805 11:03:33.775011
1806 11:03:33.775101 Set Vref, RX VrefLevel [Byte0]: 65
1807 11:03:33.779168 [Byte1]: 65
1808 11:03:33.782637
1809 11:03:33.782736 Set Vref, RX VrefLevel [Byte0]: 66
1810 11:03:33.786512 [Byte1]: 66
1811 11:03:33.790747
1812 11:03:33.790827 Set Vref, RX VrefLevel [Byte0]: 67
1813 11:03:33.793513 [Byte1]: 67
1814 11:03:33.797826
1815 11:03:33.797900 Set Vref, RX VrefLevel [Byte0]: 68
1816 11:03:33.801102 [Byte1]: 68
1817 11:03:33.805366
1818 11:03:33.805448 Set Vref, RX VrefLevel [Byte0]: 69
1819 11:03:33.808989 [Byte1]: 69
1820 11:03:33.812742
1821 11:03:33.812818 Final RX Vref Byte 0 = 59 to rank0
1822 11:03:33.816336 Final RX Vref Byte 1 = 56 to rank0
1823 11:03:33.819993 Final RX Vref Byte 0 = 59 to rank1
1824 11:03:33.823430 Final RX Vref Byte 1 = 56 to rank1==
1825 11:03:33.826399 Dram Type= 6, Freq= 0, CH_1, rank 0
1826 11:03:33.829633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1827 11:03:33.833553 ==
1828 11:03:33.833630 DQS Delay:
1829 11:03:33.833688 DQS0 = 0, DQS1 = 0
1830 11:03:33.836419 DQM Delay:
1831 11:03:33.836511 DQM0 = 94, DQM1 = 89
1832 11:03:33.839500 DQ Delay:
1833 11:03:33.843381 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1834 11:03:33.846493 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =92
1835 11:03:33.846589 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1836 11:03:33.852996 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1837 11:03:33.853096
1838 11:03:33.853179
1839 11:03:33.859612 [DQSOSCAuto] RK0, (LSB)MR18= 0x324d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1840 11:03:33.862848 CH1 RK0: MR19=606, MR18=324D
1841 11:03:33.869709 CH1_RK0: MR19=0x606, MR18=0x324D, DQSOSC=390, MR23=63, INC=97, DEC=64
1842 11:03:33.869808
1843 11:03:33.873340 ----->DramcWriteLeveling(PI) begin...
1844 11:03:33.873419 ==
1845 11:03:33.876312 Dram Type= 6, Freq= 0, CH_1, rank 1
1846 11:03:33.879608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1847 11:03:33.879716 ==
1848 11:03:33.883145 Write leveling (Byte 0): 27 => 27
1849 11:03:33.886959 Write leveling (Byte 1): 28 => 28
1850 11:03:33.889922 DramcWriteLeveling(PI) end<-----
1851 11:03:33.890036
1852 11:03:33.890136 ==
1853 11:03:33.892947 Dram Type= 6, Freq= 0, CH_1, rank 1
1854 11:03:33.896350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1855 11:03:33.896442 ==
1856 11:03:33.899522 [Gating] SW mode calibration
1857 11:03:33.906617 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1858 11:03:33.913207 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1859 11:03:33.916443 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1860 11:03:33.919612 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1861 11:03:33.926385 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 11:03:33.929621 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 11:03:33.933394 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 11:03:33.939647 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 11:03:33.942945 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 11:03:33.946554 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 11:03:33.952984 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 11:03:33.956643 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 11:03:33.959849 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 11:03:33.966687 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 11:03:33.969449 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 11:03:33.973455 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 11:03:33.976220 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 11:03:33.983176 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 11:03:33.986615 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 11:03:33.989682 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1877 11:03:33.996729 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 11:03:33.999681 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 11:03:34.003612 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 11:03:34.010134 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 11:03:34.013491 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:03:34.016720 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 11:03:34.023276 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 11:03:34.026341 0 9 4 | B1->B0 | 2929 2424 | 0 1 | (0 0) (1 1)
1885 11:03:34.029741 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1886 11:03:34.036724 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1887 11:03:34.039615 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 11:03:34.043458 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 11:03:34.049721 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 11:03:34.052940 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 11:03:34.056290 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
1892 11:03:34.060187 0 10 4 | B1->B0 | 2525 2c2c | 0 1 | (1 0) (1 0)
1893 11:03:34.066665 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1894 11:03:34.069817 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:03:34.073758 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:03:34.079920 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 11:03:34.083620 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 11:03:34.086706 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 11:03:34.093478 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
1900 11:03:34.096417 0 11 4 | B1->B0 | 3c3c 2c2c | 0 0 | (1 1) (1 1)
1901 11:03:34.099824 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 11:03:34.106906 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 11:03:34.110348 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 11:03:34.113458 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 11:03:34.119831 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 11:03:34.123794 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 11:03:34.126696 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 11:03:34.133344 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1909 11:03:34.136476 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 11:03:34.140185 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 11:03:34.143653 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 11:03:34.149993 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 11:03:34.153738 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 11:03:34.156956 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 11:03:34.163636 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 11:03:34.166958 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 11:03:34.169983 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 11:03:34.177083 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 11:03:34.180363 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 11:03:34.184088 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 11:03:34.190170 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 11:03:34.193577 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 11:03:34.197033 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 11:03:34.203742 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1925 11:03:34.207110 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 11:03:34.210308 Total UI for P1: 0, mck2ui 16
1927 11:03:34.213698 best dqsien dly found for B0: ( 0, 14, 4)
1928 11:03:34.216890 Total UI for P1: 0, mck2ui 16
1929 11:03:34.220807 best dqsien dly found for B1: ( 0, 14, 4)
1930 11:03:34.224121 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1931 11:03:34.227405 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1932 11:03:34.227515
1933 11:03:34.230553 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1934 11:03:34.233647 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1935 11:03:34.237303 [Gating] SW calibration Done
1936 11:03:34.237405 ==
1937 11:03:34.240741 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 11:03:34.243904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 11:03:34.244007 ==
1940 11:03:34.246931 RX Vref Scan: 0
1941 11:03:34.247026
1942 11:03:34.247110 RX Vref 0 -> 0, step: 1
1943 11:03:34.247192
1944 11:03:34.250704 RX Delay -130 -> 252, step: 16
1945 11:03:34.253735 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1946 11:03:34.260707 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1947 11:03:34.263938 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1948 11:03:34.267433 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1949 11:03:34.270689 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1950 11:03:34.273978 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1951 11:03:34.281358 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1952 11:03:34.284284 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1953 11:03:34.287331 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1954 11:03:34.290565 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1955 11:03:34.294214 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1956 11:03:34.300551 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1957 11:03:34.304145 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1958 11:03:34.307417 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1959 11:03:34.311426 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1960 11:03:34.314253 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1961 11:03:34.317260 ==
1962 11:03:34.317387 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 11:03:34.324444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 11:03:34.324560 ==
1965 11:03:34.324649 DQS Delay:
1966 11:03:34.327748 DQS0 = 0, DQS1 = 0
1967 11:03:34.327842 DQM Delay:
1968 11:03:34.327925 DQM0 = 92, DQM1 = 88
1969 11:03:34.330971 DQ Delay:
1970 11:03:34.334695 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1971 11:03:34.337898 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1972 11:03:34.341465 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1973 11:03:34.344841 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1974 11:03:34.344945
1975 11:03:34.345065
1976 11:03:34.345148 ==
1977 11:03:34.347964 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 11:03:34.351058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 11:03:34.351173 ==
1980 11:03:34.351232
1981 11:03:34.351285
1982 11:03:34.354213 TX Vref Scan disable
1983 11:03:34.358152 == TX Byte 0 ==
1984 11:03:34.361104 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1985 11:03:34.364463 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1986 11:03:34.367516 == TX Byte 1 ==
1987 11:03:34.371100 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1988 11:03:34.374322 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1989 11:03:34.374404 ==
1990 11:03:34.377753 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 11:03:34.381517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 11:03:34.381624 ==
1993 11:03:34.395478 TX Vref=22, minBit 2, minWin=26, winSum=443
1994 11:03:34.398672 TX Vref=24, minBit 0, minWin=27, winSum=446
1995 11:03:34.401945 TX Vref=26, minBit 0, minWin=27, winSum=448
1996 11:03:34.405751 TX Vref=28, minBit 2, minWin=27, winSum=449
1997 11:03:34.408756 TX Vref=30, minBit 2, minWin=27, winSum=452
1998 11:03:34.412235 TX Vref=32, minBit 2, minWin=27, winSum=450
1999 11:03:34.418951 [TxChooseVref] Worse bit 2, Min win 27, Win sum 452, Final Vref 30
2000 11:03:34.419047
2001 11:03:34.422554 Final TX Range 1 Vref 30
2002 11:03:34.422632
2003 11:03:34.422691 ==
2004 11:03:34.425614 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 11:03:34.428781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 11:03:34.428862 ==
2007 11:03:34.428921
2008 11:03:34.428974
2009 11:03:34.432057 TX Vref Scan disable
2010 11:03:34.435244 == TX Byte 0 ==
2011 11:03:34.439141 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2012 11:03:34.441856 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2013 11:03:34.445462 == TX Byte 1 ==
2014 11:03:34.449086 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2015 11:03:34.452158 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2016 11:03:34.452245
2017 11:03:34.455248 [DATLAT]
2018 11:03:34.455325 Freq=800, CH1 RK1
2019 11:03:34.455384
2020 11:03:34.458918 DATLAT Default: 0xa
2021 11:03:34.458996 0, 0xFFFF, sum = 0
2022 11:03:34.462240 1, 0xFFFF, sum = 0
2023 11:03:34.462320 2, 0xFFFF, sum = 0
2024 11:03:34.465415 3, 0xFFFF, sum = 0
2025 11:03:34.465519 4, 0xFFFF, sum = 0
2026 11:03:34.468511 5, 0xFFFF, sum = 0
2027 11:03:34.468591 6, 0xFFFF, sum = 0
2028 11:03:34.472216 7, 0xFFFF, sum = 0
2029 11:03:34.472295 8, 0xFFFF, sum = 0
2030 11:03:34.475375 9, 0x0, sum = 1
2031 11:03:34.475455 10, 0x0, sum = 2
2032 11:03:34.478416 11, 0x0, sum = 3
2033 11:03:34.478495 12, 0x0, sum = 4
2034 11:03:34.482274 best_step = 10
2035 11:03:34.482360
2036 11:03:34.482418 ==
2037 11:03:34.485333 Dram Type= 6, Freq= 0, CH_1, rank 1
2038 11:03:34.488393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2039 11:03:34.488473 ==
2040 11:03:34.492311 RX Vref Scan: 0
2041 11:03:34.492389
2042 11:03:34.492497 RX Vref 0 -> 0, step: 1
2043 11:03:34.492566
2044 11:03:34.495467 RX Delay -79 -> 252, step: 8
2045 11:03:34.502168 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2046 11:03:34.505620 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2047 11:03:34.508754 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2048 11:03:34.511916 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2049 11:03:34.515781 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2050 11:03:34.518728 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2051 11:03:34.525952 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2052 11:03:34.528555 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2053 11:03:34.532800 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2054 11:03:34.535397 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2055 11:03:34.538848 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2056 11:03:34.545131 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2057 11:03:34.548750 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2058 11:03:34.551782 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2059 11:03:34.555629 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2060 11:03:34.558745 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2061 11:03:34.558830 ==
2062 11:03:34.561923 Dram Type= 6, Freq= 0, CH_1, rank 1
2063 11:03:34.568685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2064 11:03:34.568778 ==
2065 11:03:34.568839 DQS Delay:
2066 11:03:34.572289 DQS0 = 0, DQS1 = 0
2067 11:03:34.572374 DQM Delay:
2068 11:03:34.572433 DQM0 = 96, DQM1 = 90
2069 11:03:34.575453 DQ Delay:
2070 11:03:34.578990 DQ0 =96, DQ1 =92, DQ2 =84, DQ3 =92
2071 11:03:34.581885 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2072 11:03:34.585607 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2073 11:03:34.588698 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2074 11:03:34.588778
2075 11:03:34.588838
2076 11:03:34.595802 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
2077 11:03:34.599054 CH1 RK1: MR19=606, MR18=4B14
2078 11:03:34.605307 CH1_RK1: MR19=0x606, MR18=0x4B14, DQSOSC=391, MR23=63, INC=96, DEC=64
2079 11:03:34.609007 [RxdqsGatingPostProcess] freq 800
2080 11:03:34.612395 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2081 11:03:34.615362 Pre-setting of DQS Precalculation
2082 11:03:34.622409 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2083 11:03:34.629107 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2084 11:03:34.635552 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2085 11:03:34.635656
2086 11:03:34.635749
2087 11:03:34.638882 [Calibration Summary] 1600 Mbps
2088 11:03:34.638961 CH 0, Rank 0
2089 11:03:34.642369 SW Impedance : PASS
2090 11:03:34.645368 DUTY Scan : NO K
2091 11:03:34.645452 ZQ Calibration : PASS
2092 11:03:34.648714 Jitter Meter : NO K
2093 11:03:34.652117 CBT Training : PASS
2094 11:03:34.652233 Write leveling : PASS
2095 11:03:34.655578 RX DQS gating : PASS
2096 11:03:34.659200 RX DQ/DQS(RDDQC) : PASS
2097 11:03:34.659309 TX DQ/DQS : PASS
2098 11:03:34.662530 RX DATLAT : PASS
2099 11:03:34.662604 RX DQ/DQS(Engine): PASS
2100 11:03:34.666792 TX OE : NO K
2101 11:03:34.666871 All Pass.
2102 11:03:34.666929
2103 11:03:34.669475 CH 0, Rank 1
2104 11:03:34.669545 SW Impedance : PASS
2105 11:03:34.672786 DUTY Scan : NO K
2106 11:03:34.675946 ZQ Calibration : PASS
2107 11:03:34.676024 Jitter Meter : NO K
2108 11:03:34.679461 CBT Training : PASS
2109 11:03:34.682798 Write leveling : PASS
2110 11:03:34.682882 RX DQS gating : PASS
2111 11:03:34.686337 RX DQ/DQS(RDDQC) : PASS
2112 11:03:34.686408 TX DQ/DQS : PASS
2113 11:03:34.689341 RX DATLAT : PASS
2114 11:03:34.692989 RX DQ/DQS(Engine): PASS
2115 11:03:34.693064 TX OE : NO K
2116 11:03:34.696086 All Pass.
2117 11:03:34.696156
2118 11:03:34.696231 CH 1, Rank 0
2119 11:03:34.699618 SW Impedance : PASS
2120 11:03:34.699686 DUTY Scan : NO K
2121 11:03:34.703012 ZQ Calibration : PASS
2122 11:03:34.706433 Jitter Meter : NO K
2123 11:03:34.706518 CBT Training : PASS
2124 11:03:34.709526 Write leveling : PASS
2125 11:03:34.712783 RX DQS gating : PASS
2126 11:03:34.712866 RX DQ/DQS(RDDQC) : PASS
2127 11:03:34.716058 TX DQ/DQS : PASS
2128 11:03:34.719974 RX DATLAT : PASS
2129 11:03:34.720051 RX DQ/DQS(Engine): PASS
2130 11:03:34.722984 TX OE : NO K
2131 11:03:34.723056 All Pass.
2132 11:03:34.723135
2133 11:03:34.723206 CH 1, Rank 1
2134 11:03:34.726476 SW Impedance : PASS
2135 11:03:34.729491 DUTY Scan : NO K
2136 11:03:34.729564 ZQ Calibration : PASS
2137 11:03:34.733500 Jitter Meter : NO K
2138 11:03:34.736604 CBT Training : PASS
2139 11:03:34.736678 Write leveling : PASS
2140 11:03:34.739917 RX DQS gating : PASS
2141 11:03:34.742970 RX DQ/DQS(RDDQC) : PASS
2142 11:03:34.743041 TX DQ/DQS : PASS
2143 11:03:34.746235 RX DATLAT : PASS
2144 11:03:34.749626 RX DQ/DQS(Engine): PASS
2145 11:03:34.749701 TX OE : NO K
2146 11:03:34.753455 All Pass.
2147 11:03:34.753536
2148 11:03:34.753622 DramC Write-DBI off
2149 11:03:34.756463 PER_BANK_REFRESH: Hybrid Mode
2150 11:03:34.756541 TX_TRACKING: ON
2151 11:03:34.760167 [GetDramInforAfterCalByMRR] Vendor 6.
2152 11:03:34.766206 [GetDramInforAfterCalByMRR] Revision 606.
2153 11:03:34.769677 [GetDramInforAfterCalByMRR] Revision 2 0.
2154 11:03:34.769757 MR0 0x3b3b
2155 11:03:34.769844 MR8 0x5151
2156 11:03:34.773664 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2157 11:03:34.773739
2158 11:03:34.776316 MR0 0x3b3b
2159 11:03:34.776393 MR8 0x5151
2160 11:03:34.779663 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2161 11:03:34.779736
2162 11:03:34.789721 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2163 11:03:34.793391 [FAST_K] Save calibration result to emmc
2164 11:03:34.796354 [FAST_K] Save calibration result to emmc
2165 11:03:34.800236 dram_init: config_dvfs: 1
2166 11:03:34.802883 dramc_set_vcore_voltage set vcore to 662500
2167 11:03:34.806949 Read voltage for 1200, 2
2168 11:03:34.807028 Vio18 = 0
2169 11:03:34.807091 Vcore = 662500
2170 11:03:34.807146 Vdram = 0
2171 11:03:34.809802 Vddq = 0
2172 11:03:34.809872 Vmddr = 0
2173 11:03:34.816455 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2174 11:03:34.819782 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2175 11:03:34.823512 MEM_TYPE=3, freq_sel=15
2176 11:03:34.826690 sv_algorithm_assistance_LP4_1600
2177 11:03:34.829859 ============ PULL DRAM RESETB DOWN ============
2178 11:03:34.833476 ========== PULL DRAM RESETB DOWN end =========
2179 11:03:34.839846 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2180 11:03:34.843113 ===================================
2181 11:03:34.843224 LPDDR4 DRAM CONFIGURATION
2182 11:03:34.846455 ===================================
2183 11:03:34.849704 EX_ROW_EN[0] = 0x0
2184 11:03:34.849803 EX_ROW_EN[1] = 0x0
2185 11:03:34.853460 LP4Y_EN = 0x0
2186 11:03:34.853564 WORK_FSP = 0x0
2187 11:03:34.856557 WL = 0x4
2188 11:03:34.860374 RL = 0x4
2189 11:03:34.860474 BL = 0x2
2190 11:03:34.863190 RPST = 0x0
2191 11:03:34.863285 RD_PRE = 0x0
2192 11:03:34.866901 WR_PRE = 0x1
2193 11:03:34.867029 WR_PST = 0x0
2194 11:03:34.870179 DBI_WR = 0x0
2195 11:03:34.870277 DBI_RD = 0x0
2196 11:03:34.873166 OTF = 0x1
2197 11:03:34.877111 ===================================
2198 11:03:34.880130 ===================================
2199 11:03:34.880229 ANA top config
2200 11:03:34.883882 ===================================
2201 11:03:34.886664 DLL_ASYNC_EN = 0
2202 11:03:34.889993 ALL_SLAVE_EN = 0
2203 11:03:34.890141 NEW_RANK_MODE = 1
2204 11:03:34.893874 DLL_IDLE_MODE = 1
2205 11:03:34.897144 LP45_APHY_COMB_EN = 1
2206 11:03:34.900218 TX_ODT_DIS = 1
2207 11:03:34.900326 NEW_8X_MODE = 1
2208 11:03:34.903144 ===================================
2209 11:03:34.907064 ===================================
2210 11:03:34.909939 data_rate = 2400
2211 11:03:34.913382 CKR = 1
2212 11:03:34.916700 DQ_P2S_RATIO = 8
2213 11:03:34.920349 ===================================
2214 11:03:34.923339 CA_P2S_RATIO = 8
2215 11:03:34.923419 DQ_CA_OPEN = 0
2216 11:03:34.927074 DQ_SEMI_OPEN = 0
2217 11:03:34.930709 CA_SEMI_OPEN = 0
2218 11:03:34.933471 CA_FULL_RATE = 0
2219 11:03:34.937573 DQ_CKDIV4_EN = 0
2220 11:03:34.940191 CA_CKDIV4_EN = 0
2221 11:03:34.940278 CA_PREDIV_EN = 0
2222 11:03:34.944077 PH8_DLY = 17
2223 11:03:34.947155 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2224 11:03:34.950219 DQ_AAMCK_DIV = 4
2225 11:03:34.953877 CA_AAMCK_DIV = 4
2226 11:03:34.956833 CA_ADMCK_DIV = 4
2227 11:03:34.956915 DQ_TRACK_CA_EN = 0
2228 11:03:34.960051 CA_PICK = 1200
2229 11:03:34.963802 CA_MCKIO = 1200
2230 11:03:34.966937 MCKIO_SEMI = 0
2231 11:03:34.970036 PLL_FREQ = 2366
2232 11:03:34.973930 DQ_UI_PI_RATIO = 32
2233 11:03:34.977399 CA_UI_PI_RATIO = 0
2234 11:03:34.980409 ===================================
2235 11:03:34.983617 ===================================
2236 11:03:34.983697 memory_type:LPDDR4
2237 11:03:34.986869 GP_NUM : 10
2238 11:03:34.990740 SRAM_EN : 1
2239 11:03:34.990821 MD32_EN : 0
2240 11:03:34.993931 ===================================
2241 11:03:34.997014 [ANA_INIT] >>>>>>>>>>>>>>
2242 11:03:35.000415 <<<<<< [CONFIGURE PHASE]: ANA_TX
2243 11:03:35.003672 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2244 11:03:35.007114 ===================================
2245 11:03:35.007198 data_rate = 2400,PCW = 0X5b00
2246 11:03:35.010727 ===================================
2247 11:03:35.018252 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2248 11:03:35.020790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2249 11:03:35.027026 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2250 11:03:35.030848 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2251 11:03:35.033808 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2252 11:03:35.036969 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2253 11:03:35.040699 [ANA_INIT] flow start
2254 11:03:35.043977 [ANA_INIT] PLL >>>>>>>>
2255 11:03:35.044079 [ANA_INIT] PLL <<<<<<<<
2256 11:03:35.047771 [ANA_INIT] MIDPI >>>>>>>>
2257 11:03:35.050545 [ANA_INIT] MIDPI <<<<<<<<
2258 11:03:35.050628 [ANA_INIT] DLL >>>>>>>>
2259 11:03:35.053919 [ANA_INIT] DLL <<<<<<<<
2260 11:03:35.056943 [ANA_INIT] flow end
2261 11:03:35.060284 ============ LP4 DIFF to SE enter ============
2262 11:03:35.063638 ============ LP4 DIFF to SE exit ============
2263 11:03:35.067179 [ANA_INIT] <<<<<<<<<<<<<
2264 11:03:35.070314 [Flow] Enable top DCM control >>>>>
2265 11:03:35.073986 [Flow] Enable top DCM control <<<<<
2266 11:03:35.077042 Enable DLL master slave shuffle
2267 11:03:35.080420 ==============================================================
2268 11:03:35.084117 Gating Mode config
2269 11:03:35.087749 ==============================================================
2270 11:03:35.090505 Config description:
2271 11:03:35.100704 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2272 11:03:35.107186 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2273 11:03:35.111042 SELPH_MODE 0: By rank 1: By Phase
2274 11:03:35.117501 ==============================================================
2275 11:03:35.120728 GAT_TRACK_EN = 1
2276 11:03:35.124700 RX_GATING_MODE = 2
2277 11:03:35.127871 RX_GATING_TRACK_MODE = 2
2278 11:03:35.130817 SELPH_MODE = 1
2279 11:03:35.130893 PICG_EARLY_EN = 1
2280 11:03:35.134579 VALID_LAT_VALUE = 1
2281 11:03:35.140677 ==============================================================
2282 11:03:35.144214 Enter into Gating configuration >>>>
2283 11:03:35.147380 Exit from Gating configuration <<<<
2284 11:03:35.151004 Enter into DVFS_PRE_config >>>>>
2285 11:03:35.160819 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2286 11:03:35.164019 Exit from DVFS_PRE_config <<<<<
2287 11:03:35.167431 Enter into PICG configuration >>>>
2288 11:03:35.171197 Exit from PICG configuration <<<<
2289 11:03:35.173962 [RX_INPUT] configuration >>>>>
2290 11:03:35.177679 [RX_INPUT] configuration <<<<<
2291 11:03:35.180866 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2292 11:03:35.187303 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2293 11:03:35.194101 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2294 11:03:35.200657 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2295 11:03:35.207301 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2296 11:03:35.210418 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2297 11:03:35.217032 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2298 11:03:35.220646 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2299 11:03:35.223829 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2300 11:03:35.227074 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2301 11:03:35.234002 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2302 11:03:35.237481 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2303 11:03:35.240624 ===================================
2304 11:03:35.244128 LPDDR4 DRAM CONFIGURATION
2305 11:03:35.247101 ===================================
2306 11:03:35.247195 EX_ROW_EN[0] = 0x0
2307 11:03:35.250574 EX_ROW_EN[1] = 0x0
2308 11:03:35.250736 LP4Y_EN = 0x0
2309 11:03:35.254041 WORK_FSP = 0x0
2310 11:03:35.254161 WL = 0x4
2311 11:03:35.257476 RL = 0x4
2312 11:03:35.257557 BL = 0x2
2313 11:03:35.260593 RPST = 0x0
2314 11:03:35.260705 RD_PRE = 0x0
2315 11:03:35.264230 WR_PRE = 0x1
2316 11:03:35.264310 WR_PST = 0x0
2317 11:03:35.267346 DBI_WR = 0x0
2318 11:03:35.267426 DBI_RD = 0x0
2319 11:03:35.270725 OTF = 0x1
2320 11:03:35.274247 ===================================
2321 11:03:35.277670 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2322 11:03:35.281486 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2323 11:03:35.287904 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2324 11:03:35.290864 ===================================
2325 11:03:35.290949 LPDDR4 DRAM CONFIGURATION
2326 11:03:35.294325 ===================================
2327 11:03:35.297116 EX_ROW_EN[0] = 0x10
2328 11:03:35.300900 EX_ROW_EN[1] = 0x0
2329 11:03:35.300980 LP4Y_EN = 0x0
2330 11:03:35.304253 WORK_FSP = 0x0
2331 11:03:35.304332 WL = 0x4
2332 11:03:35.307490 RL = 0x4
2333 11:03:35.307593 BL = 0x2
2334 11:03:35.310495 RPST = 0x0
2335 11:03:35.310571 RD_PRE = 0x0
2336 11:03:35.313915 WR_PRE = 0x1
2337 11:03:35.313995 WR_PST = 0x0
2338 11:03:35.317584 DBI_WR = 0x0
2339 11:03:35.317663 DBI_RD = 0x0
2340 11:03:35.320826 OTF = 0x1
2341 11:03:35.324056 ===================================
2342 11:03:35.331046 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2343 11:03:35.331139 ==
2344 11:03:35.334417 Dram Type= 6, Freq= 0, CH_0, rank 0
2345 11:03:35.337359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2346 11:03:35.337444 ==
2347 11:03:35.340481 [Duty_Offset_Calibration]
2348 11:03:35.340563 B0:2 B1:1 CA:1
2349 11:03:35.340639
2350 11:03:35.344072 [DutyScan_Calibration_Flow] k_type=0
2351 11:03:35.353944
2352 11:03:35.354101 ==CLK 0==
2353 11:03:35.357799 Final CLK duty delay cell = 0
2354 11:03:35.360918 [0] MAX Duty = 5218%(X100), DQS PI = 24
2355 11:03:35.364119 [0] MIN Duty = 4875%(X100), DQS PI = 0
2356 11:03:35.364202 [0] AVG Duty = 5046%(X100)
2357 11:03:35.364262
2358 11:03:35.367240 CH0 CLK Duty spec in!! Max-Min= 343%
2359 11:03:35.373672 [DutyScan_Calibration_Flow] ====Done====
2360 11:03:35.373777
2361 11:03:35.377247 [DutyScan_Calibration_Flow] k_type=1
2362 11:03:35.392733
2363 11:03:35.392908 ==DQS 0 ==
2364 11:03:35.395928 Final DQS duty delay cell = -4
2365 11:03:35.399086 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2366 11:03:35.402770 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2367 11:03:35.406157 [-4] AVG Duty = 4937%(X100)
2368 11:03:35.406262
2369 11:03:35.406381 ==DQS 1 ==
2370 11:03:35.409094 Final DQS duty delay cell = 0
2371 11:03:35.412708 [0] MAX Duty = 5156%(X100), DQS PI = 62
2372 11:03:35.415831 [0] MIN Duty = 5000%(X100), DQS PI = 32
2373 11:03:35.419001 [0] AVG Duty = 5078%(X100)
2374 11:03:35.419084
2375 11:03:35.422671 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2376 11:03:35.422751
2377 11:03:35.426029 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2378 11:03:35.428987 [DutyScan_Calibration_Flow] ====Done====
2379 11:03:35.429065
2380 11:03:35.432352 [DutyScan_Calibration_Flow] k_type=3
2381 11:03:35.449098
2382 11:03:35.449226 ==DQM 0 ==
2383 11:03:35.452501 Final DQM duty delay cell = 0
2384 11:03:35.455762 [0] MAX Duty = 5156%(X100), DQS PI = 30
2385 11:03:35.459696 [0] MIN Duty = 4875%(X100), DQS PI = 58
2386 11:03:35.459784 [0] AVG Duty = 5015%(X100)
2387 11:03:35.462793
2388 11:03:35.462872 ==DQM 1 ==
2389 11:03:35.466118 Final DQM duty delay cell = 0
2390 11:03:35.469150 [0] MAX Duty = 5093%(X100), DQS PI = 0
2391 11:03:35.472578 [0] MIN Duty = 5031%(X100), DQS PI = 2
2392 11:03:35.472657 [0] AVG Duty = 5062%(X100)
2393 11:03:35.475945
2394 11:03:35.479575 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2395 11:03:35.479667
2396 11:03:35.482859 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2397 11:03:35.486207 [DutyScan_Calibration_Flow] ====Done====
2398 11:03:35.486285
2399 11:03:35.489364 [DutyScan_Calibration_Flow] k_type=2
2400 11:03:35.505953
2401 11:03:35.506107 ==DQ 0 ==
2402 11:03:35.508971 Final DQ duty delay cell = 0
2403 11:03:35.512342 [0] MAX Duty = 5062%(X100), DQS PI = 32
2404 11:03:35.515665 [0] MIN Duty = 4844%(X100), DQS PI = 62
2405 11:03:35.515748 [0] AVG Duty = 4953%(X100)
2406 11:03:35.515805
2407 11:03:35.519409 ==DQ 1 ==
2408 11:03:35.522661 Final DQ duty delay cell = 0
2409 11:03:35.525654 [0] MAX Duty = 5093%(X100), DQS PI = 24
2410 11:03:35.528932 [0] MIN Duty = 4907%(X100), DQS PI = 36
2411 11:03:35.529010 [0] AVG Duty = 5000%(X100)
2412 11:03:35.529069
2413 11:03:35.532330 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2414 11:03:35.532408
2415 11:03:35.535908 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2416 11:03:35.542321 [DutyScan_Calibration_Flow] ====Done====
2417 11:03:35.542434 ==
2418 11:03:35.546116 Dram Type= 6, Freq= 0, CH_1, rank 0
2419 11:03:35.548995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2420 11:03:35.549076 ==
2421 11:03:35.552585 [Duty_Offset_Calibration]
2422 11:03:35.552665 B0:1 B1:0 CA:1
2423 11:03:35.552738
2424 11:03:35.555789 [DutyScan_Calibration_Flow] k_type=0
2425 11:03:35.565162
2426 11:03:35.565260 ==CLK 0==
2427 11:03:35.568171 Final CLK duty delay cell = -4
2428 11:03:35.571742 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2429 11:03:35.575141 [-4] MIN Duty = 4876%(X100), DQS PI = 50
2430 11:03:35.578224 [-4] AVG Duty = 4938%(X100)
2431 11:03:35.578327
2432 11:03:35.581424 CH1 CLK Duty spec in!! Max-Min= 124%
2433 11:03:35.584638 [DutyScan_Calibration_Flow] ====Done====
2434 11:03:35.584735
2435 11:03:35.588271 [DutyScan_Calibration_Flow] k_type=1
2436 11:03:35.604830
2437 11:03:35.604944 ==DQS 0 ==
2438 11:03:35.607955 Final DQS duty delay cell = 0
2439 11:03:35.611076 [0] MAX Duty = 5094%(X100), DQS PI = 26
2440 11:03:35.614465 [0] MIN Duty = 4875%(X100), DQS PI = 0
2441 11:03:35.614558 [0] AVG Duty = 4984%(X100)
2442 11:03:35.617697
2443 11:03:35.617776 ==DQS 1 ==
2444 11:03:35.621460 Final DQS duty delay cell = 0
2445 11:03:35.625025 [0] MAX Duty = 5187%(X100), DQS PI = 18
2446 11:03:35.627918 [0] MIN Duty = 4969%(X100), DQS PI = 10
2447 11:03:35.627999 [0] AVG Duty = 5078%(X100)
2448 11:03:35.631286
2449 11:03:35.634521 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2450 11:03:35.634600
2451 11:03:35.638315 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2452 11:03:35.641366 [DutyScan_Calibration_Flow] ====Done====
2453 11:03:35.641446
2454 11:03:35.644489 [DutyScan_Calibration_Flow] k_type=3
2455 11:03:35.661666
2456 11:03:35.661836 ==DQM 0 ==
2457 11:03:35.664492 Final DQM duty delay cell = 0
2458 11:03:35.668132 [0] MAX Duty = 5156%(X100), DQS PI = 8
2459 11:03:35.671455 [0] MIN Duty = 5031%(X100), DQS PI = 0
2460 11:03:35.671565 [0] AVG Duty = 5093%(X100)
2461 11:03:35.674861
2462 11:03:35.674967 ==DQM 1 ==
2463 11:03:35.677820 Final DQM duty delay cell = 0
2464 11:03:35.681436 [0] MAX Duty = 5031%(X100), DQS PI = 26
2465 11:03:35.684735 [0] MIN Duty = 4875%(X100), DQS PI = 36
2466 11:03:35.684815 [0] AVG Duty = 4953%(X100)
2467 11:03:35.684903
2468 11:03:35.691220 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2469 11:03:35.691331
2470 11:03:35.694685 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2471 11:03:35.698205 [DutyScan_Calibration_Flow] ====Done====
2472 11:03:35.698324
2473 11:03:35.701439 [DutyScan_Calibration_Flow] k_type=2
2474 11:03:35.717268
2475 11:03:35.717378 ==DQ 0 ==
2476 11:03:35.720694 Final DQ duty delay cell = -4
2477 11:03:35.723684 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2478 11:03:35.726917 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2479 11:03:35.730331 [-4] AVG Duty = 4984%(X100)
2480 11:03:35.730418
2481 11:03:35.730481 ==DQ 1 ==
2482 11:03:35.733915 Final DQ duty delay cell = 0
2483 11:03:35.737126 [0] MAX Duty = 5125%(X100), DQS PI = 20
2484 11:03:35.740740 [0] MIN Duty = 4938%(X100), DQS PI = 34
2485 11:03:35.740824 [0] AVG Duty = 5031%(X100)
2486 11:03:35.740883
2487 11:03:35.743952 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2488 11:03:35.744023
2489 11:03:35.747629 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2490 11:03:35.753931 [DutyScan_Calibration_Flow] ====Done====
2491 11:03:35.757528 nWR fixed to 30
2492 11:03:35.757619 [ModeRegInit_LP4] CH0 RK0
2493 11:03:35.760723 [ModeRegInit_LP4] CH0 RK1
2494 11:03:35.763701 [ModeRegInit_LP4] CH1 RK0
2495 11:03:35.763777 [ModeRegInit_LP4] CH1 RK1
2496 11:03:35.767363 match AC timing 7
2497 11:03:35.770771 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2498 11:03:35.774140 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2499 11:03:35.780355 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2500 11:03:35.784147 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2501 11:03:35.790489 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2502 11:03:35.790587 ==
2503 11:03:35.794054 Dram Type= 6, Freq= 0, CH_0, rank 0
2504 11:03:35.797391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2505 11:03:35.797470 ==
2506 11:03:35.804368 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2507 11:03:35.807247 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2508 11:03:35.817570 [CA 0] Center 38 (8~69) winsize 62
2509 11:03:35.821352 [CA 1] Center 39 (8~70) winsize 63
2510 11:03:35.823786 [CA 2] Center 35 (4~66) winsize 63
2511 11:03:35.827122 [CA 3] Center 34 (4~65) winsize 62
2512 11:03:35.831092 [CA 4] Center 33 (3~64) winsize 62
2513 11:03:35.833965 [CA 5] Center 32 (3~62) winsize 60
2514 11:03:35.834045
2515 11:03:35.837374 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2516 11:03:35.837447
2517 11:03:35.841372 [CATrainingPosCal] consider 1 rank data
2518 11:03:35.844312 u2DelayCellTimex100 = 270/100 ps
2519 11:03:35.847433 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2520 11:03:35.850626 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2521 11:03:35.854198 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2522 11:03:35.861087 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2523 11:03:35.864087 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2524 11:03:35.867885 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2525 11:03:35.867968
2526 11:03:35.871207 CA PerBit enable=1, Macro0, CA PI delay=32
2527 11:03:35.871278
2528 11:03:35.874335 [CBTSetCACLKResult] CA Dly = 32
2529 11:03:35.874412 CS Dly: 6 (0~37)
2530 11:03:35.874469 ==
2531 11:03:35.877415 Dram Type= 6, Freq= 0, CH_0, rank 1
2532 11:03:35.884688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 11:03:35.884783 ==
2534 11:03:35.887632 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2535 11:03:35.894420 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2536 11:03:35.903222 [CA 0] Center 38 (8~69) winsize 62
2537 11:03:35.906032 [CA 1] Center 38 (8~69) winsize 62
2538 11:03:35.909606 [CA 2] Center 35 (4~66) winsize 63
2539 11:03:35.913130 [CA 3] Center 34 (4~65) winsize 62
2540 11:03:35.916173 [CA 4] Center 33 (3~64) winsize 62
2541 11:03:35.919612 [CA 5] Center 32 (3~62) winsize 60
2542 11:03:35.919691
2543 11:03:35.923278 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2544 11:03:35.923361
2545 11:03:35.926270 [CATrainingPosCal] consider 2 rank data
2546 11:03:35.930252 u2DelayCellTimex100 = 270/100 ps
2547 11:03:35.932984 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2548 11:03:35.936392 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2549 11:03:35.943292 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2550 11:03:35.946209 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2551 11:03:35.949493 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2552 11:03:35.953105 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2553 11:03:35.953190
2554 11:03:35.956573 CA PerBit enable=1, Macro0, CA PI delay=32
2555 11:03:35.956651
2556 11:03:35.960098 [CBTSetCACLKResult] CA Dly = 32
2557 11:03:35.960174 CS Dly: 6 (0~38)
2558 11:03:35.960249
2559 11:03:35.963109 ----->DramcWriteLeveling(PI) begin...
2560 11:03:35.966321 ==
2561 11:03:35.966407 Dram Type= 6, Freq= 0, CH_0, rank 0
2562 11:03:35.973449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2563 11:03:35.973541 ==
2564 11:03:35.976466 Write leveling (Byte 0): 35 => 35
2565 11:03:35.979936 Write leveling (Byte 1): 31 => 31
2566 11:03:35.980025 DramcWriteLeveling(PI) end<-----
2567 11:03:35.983227
2568 11:03:35.983299 ==
2569 11:03:35.986560 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 11:03:35.990213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 11:03:35.990288 ==
2572 11:03:35.993710 [Gating] SW mode calibration
2573 11:03:35.999761 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2574 11:03:36.003310 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2575 11:03:36.010445 0 15 0 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
2576 11:03:36.013717 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2577 11:03:36.017015 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2578 11:03:36.023635 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2579 11:03:36.026841 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 11:03:36.030276 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 11:03:36.036794 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
2582 11:03:36.040224 0 15 28 | B1->B0 | 3333 2323 | 1 0 | (1 0) (1 0)
2583 11:03:36.043661 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
2584 11:03:36.046792 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 11:03:36.053604 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2586 11:03:36.056818 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 11:03:36.059979 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 11:03:36.066603 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 11:03:36.069947 1 0 24 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
2590 11:03:36.073621 1 0 28 | B1->B0 | 2929 4646 | 1 0 | (0 0) (0 0)
2591 11:03:36.080384 1 1 0 | B1->B0 | 3737 4545 | 1 0 | (0 0) (0 0)
2592 11:03:36.083187 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 11:03:36.086885 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 11:03:36.093580 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 11:03:36.096559 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 11:03:36.100125 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 11:03:36.106847 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 11:03:36.110558 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2599 11:03:36.113808 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2600 11:03:36.120077 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2601 11:03:36.123993 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 11:03:36.126780 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 11:03:36.130455 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 11:03:36.136917 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 11:03:36.140781 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 11:03:36.143821 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 11:03:36.150764 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 11:03:36.153852 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 11:03:36.157417 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 11:03:36.163943 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 11:03:36.167135 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 11:03:36.170639 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 11:03:36.177362 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 11:03:36.181019 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2615 11:03:36.184475 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2616 11:03:36.187537 Total UI for P1: 0, mck2ui 16
2617 11:03:36.190790 best dqsien dly found for B0: ( 1, 3, 28)
2618 11:03:36.194386 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 11:03:36.197377 Total UI for P1: 0, mck2ui 16
2620 11:03:36.200410 best dqsien dly found for B1: ( 1, 4, 0)
2621 11:03:36.204544 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2622 11:03:36.207333 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2623 11:03:36.210708
2624 11:03:36.214344 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2625 11:03:36.217458 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2626 11:03:36.220568 [Gating] SW calibration Done
2627 11:03:36.220674 ==
2628 11:03:36.223842 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 11:03:36.227884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 11:03:36.227983 ==
2631 11:03:36.228077 RX Vref Scan: 0
2632 11:03:36.228158
2633 11:03:36.230821 RX Vref 0 -> 0, step: 1
2634 11:03:36.230906
2635 11:03:36.234392 RX Delay -40 -> 252, step: 8
2636 11:03:36.237628 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
2637 11:03:36.240948 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2638 11:03:36.247542 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2639 11:03:36.250819 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2640 11:03:36.254476 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2641 11:03:36.257376 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2642 11:03:36.260724 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2643 11:03:36.263882 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2644 11:03:36.271103 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2645 11:03:36.274407 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2646 11:03:36.277682 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2647 11:03:36.281369 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2648 11:03:36.284289 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2649 11:03:36.290880 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2650 11:03:36.294844 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2651 11:03:36.297271 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2652 11:03:36.297354 ==
2653 11:03:36.300623 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 11:03:36.304494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 11:03:36.304576 ==
2656 11:03:36.307351 DQS Delay:
2657 11:03:36.307420 DQS0 = 0, DQS1 = 0
2658 11:03:36.310925 DQM Delay:
2659 11:03:36.310999 DQM0 = 121, DQM1 = 113
2660 11:03:36.314408 DQ Delay:
2661 11:03:36.317379 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2662 11:03:36.320601 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2663 11:03:36.324145 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2664 11:03:36.327751 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2665 11:03:36.327835
2666 11:03:36.327893
2667 11:03:36.327946 ==
2668 11:03:36.330966 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 11:03:36.334378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 11:03:36.334449 ==
2671 11:03:36.334505
2672 11:03:36.334562
2673 11:03:36.337453 TX Vref Scan disable
2674 11:03:36.340528 == TX Byte 0 ==
2675 11:03:36.344504 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2676 11:03:36.347540 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2677 11:03:36.350771 == TX Byte 1 ==
2678 11:03:36.353971 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2679 11:03:36.357831 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2680 11:03:36.357910 ==
2681 11:03:36.360944 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 11:03:36.364476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 11:03:36.367480 ==
2684 11:03:36.378015 TX Vref=22, minBit 3, minWin=24, winSum=403
2685 11:03:36.381165 TX Vref=24, minBit 0, minWin=25, winSum=409
2686 11:03:36.384719 TX Vref=26, minBit 2, minWin=25, winSum=411
2687 11:03:36.387960 TX Vref=28, minBit 10, minWin=25, winSum=415
2688 11:03:36.390865 TX Vref=30, minBit 0, minWin=26, winSum=421
2689 11:03:36.394325 TX Vref=32, minBit 4, minWin=25, winSum=418
2690 11:03:36.401267 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 30
2691 11:03:36.401369
2692 11:03:36.404831 Final TX Range 1 Vref 30
2693 11:03:36.404903
2694 11:03:36.404958 ==
2695 11:03:36.408053 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 11:03:36.411279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 11:03:36.411372 ==
2698 11:03:36.411445
2699 11:03:36.414381
2700 11:03:36.414464 TX Vref Scan disable
2701 11:03:36.417916 == TX Byte 0 ==
2702 11:03:36.421297 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2703 11:03:36.424871 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2704 11:03:36.428504 == TX Byte 1 ==
2705 11:03:36.431966 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2706 11:03:36.435970 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2707 11:03:36.436052
2708 11:03:36.438122 [DATLAT]
2709 11:03:36.438198 Freq=1200, CH0 RK0
2710 11:03:36.438256
2711 11:03:36.441784 DATLAT Default: 0xd
2712 11:03:36.441905 0, 0xFFFF, sum = 0
2713 11:03:36.445011 1, 0xFFFF, sum = 0
2714 11:03:36.445090 2, 0xFFFF, sum = 0
2715 11:03:36.449047 3, 0xFFFF, sum = 0
2716 11:03:36.449129 4, 0xFFFF, sum = 0
2717 11:03:36.451375 5, 0xFFFF, sum = 0
2718 11:03:36.451469 6, 0xFFFF, sum = 0
2719 11:03:36.454800 7, 0xFFFF, sum = 0
2720 11:03:36.454897 8, 0xFFFF, sum = 0
2721 11:03:36.457988 9, 0xFFFF, sum = 0
2722 11:03:36.458129 10, 0xFFFF, sum = 0
2723 11:03:36.461173 11, 0xFFFF, sum = 0
2724 11:03:36.464486 12, 0x0, sum = 1
2725 11:03:36.464566 13, 0x0, sum = 2
2726 11:03:36.464625 14, 0x0, sum = 3
2727 11:03:36.468223 15, 0x0, sum = 4
2728 11:03:36.468300 best_step = 13
2729 11:03:36.468358
2730 11:03:36.468411 ==
2731 11:03:36.471474 Dram Type= 6, Freq= 0, CH_0, rank 0
2732 11:03:36.478296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2733 11:03:36.478381 ==
2734 11:03:36.478440 RX Vref Scan: 1
2735 11:03:36.478499
2736 11:03:36.481414 Set Vref Range= 32 -> 127
2737 11:03:36.481490
2738 11:03:36.485406 RX Vref 32 -> 127, step: 1
2739 11:03:36.485483
2740 11:03:36.488483 RX Delay -13 -> 252, step: 4
2741 11:03:36.488560
2742 11:03:36.491326 Set Vref, RX VrefLevel [Byte0]: 32
2743 11:03:36.491403 [Byte1]: 32
2744 11:03:36.496422
2745 11:03:36.496506 Set Vref, RX VrefLevel [Byte0]: 33
2746 11:03:36.499352 [Byte1]: 33
2747 11:03:36.504276
2748 11:03:36.504357 Set Vref, RX VrefLevel [Byte0]: 34
2749 11:03:36.507632 [Byte1]: 34
2750 11:03:36.512099
2751 11:03:36.512187 Set Vref, RX VrefLevel [Byte0]: 35
2752 11:03:36.515366 [Byte1]: 35
2753 11:03:36.520045
2754 11:03:36.520126 Set Vref, RX VrefLevel [Byte0]: 36
2755 11:03:36.523417 [Byte1]: 36
2756 11:03:36.527737
2757 11:03:36.527843 Set Vref, RX VrefLevel [Byte0]: 37
2758 11:03:36.531523 [Byte1]: 37
2759 11:03:36.535577
2760 11:03:36.535657 Set Vref, RX VrefLevel [Byte0]: 38
2761 11:03:36.538897 [Byte1]: 38
2762 11:03:36.543906
2763 11:03:36.543990 Set Vref, RX VrefLevel [Byte0]: 39
2764 11:03:36.547266 [Byte1]: 39
2765 11:03:36.551269
2766 11:03:36.551351 Set Vref, RX VrefLevel [Byte0]: 40
2767 11:03:36.554871 [Byte1]: 40
2768 11:03:36.559222
2769 11:03:36.559309 Set Vref, RX VrefLevel [Byte0]: 41
2770 11:03:36.562726 [Byte1]: 41
2771 11:03:36.566973
2772 11:03:36.567056 Set Vref, RX VrefLevel [Byte0]: 42
2773 11:03:36.570737 [Byte1]: 42
2774 11:03:36.575329
2775 11:03:36.575412 Set Vref, RX VrefLevel [Byte0]: 43
2776 11:03:36.578069 [Byte1]: 43
2777 11:03:36.583234
2778 11:03:36.583321 Set Vref, RX VrefLevel [Byte0]: 44
2779 11:03:36.586517 [Byte1]: 44
2780 11:03:36.590968
2781 11:03:36.591047 Set Vref, RX VrefLevel [Byte0]: 45
2782 11:03:36.594196 [Byte1]: 45
2783 11:03:36.598396
2784 11:03:36.602362 Set Vref, RX VrefLevel [Byte0]: 46
2785 11:03:36.602461 [Byte1]: 46
2786 11:03:36.606426
2787 11:03:36.606528 Set Vref, RX VrefLevel [Byte0]: 47
2788 11:03:36.609988 [Byte1]: 47
2789 11:03:36.614412
2790 11:03:36.614485 Set Vref, RX VrefLevel [Byte0]: 48
2791 11:03:36.617596 [Byte1]: 48
2792 11:03:36.622728
2793 11:03:36.622817 Set Vref, RX VrefLevel [Byte0]: 49
2794 11:03:36.625548 [Byte1]: 49
2795 11:03:36.630329
2796 11:03:36.630415 Set Vref, RX VrefLevel [Byte0]: 50
2797 11:03:36.633761 [Byte1]: 50
2798 11:03:36.637970
2799 11:03:36.638081 Set Vref, RX VrefLevel [Byte0]: 51
2800 11:03:36.641271 [Byte1]: 51
2801 11:03:36.646134
2802 11:03:36.646249 Set Vref, RX VrefLevel [Byte0]: 52
2803 11:03:36.649225 [Byte1]: 52
2804 11:03:36.653734
2805 11:03:36.653816 Set Vref, RX VrefLevel [Byte0]: 53
2806 11:03:36.657477 [Byte1]: 53
2807 11:03:36.661847
2808 11:03:36.661934 Set Vref, RX VrefLevel [Byte0]: 54
2809 11:03:36.668069 [Byte1]: 54
2810 11:03:36.668154
2811 11:03:36.671871 Set Vref, RX VrefLevel [Byte0]: 55
2812 11:03:36.675151 [Byte1]: 55
2813 11:03:36.675233
2814 11:03:36.678272 Set Vref, RX VrefLevel [Byte0]: 56
2815 11:03:36.681431 [Byte1]: 56
2816 11:03:36.685163
2817 11:03:36.685241 Set Vref, RX VrefLevel [Byte0]: 57
2818 11:03:36.688702 [Byte1]: 57
2819 11:03:36.693673
2820 11:03:36.693788 Set Vref, RX VrefLevel [Byte0]: 58
2821 11:03:36.697089 [Byte1]: 58
2822 11:03:36.701400
2823 11:03:36.701482 Set Vref, RX VrefLevel [Byte0]: 59
2824 11:03:36.704777 [Byte1]: 59
2825 11:03:36.709262
2826 11:03:36.709347 Set Vref, RX VrefLevel [Byte0]: 60
2827 11:03:36.712142 [Byte1]: 60
2828 11:03:36.717053
2829 11:03:36.717138 Set Vref, RX VrefLevel [Byte0]: 61
2830 11:03:36.720645 [Byte1]: 61
2831 11:03:36.724961
2832 11:03:36.725071 Set Vref, RX VrefLevel [Byte0]: 62
2833 11:03:36.728073 [Byte1]: 62
2834 11:03:36.732820
2835 11:03:36.732996 Set Vref, RX VrefLevel [Byte0]: 63
2836 11:03:36.736514 [Byte1]: 63
2837 11:03:36.740523
2838 11:03:36.740605 Set Vref, RX VrefLevel [Byte0]: 64
2839 11:03:36.744298 [Byte1]: 64
2840 11:03:36.748243
2841 11:03:36.748345 Set Vref, RX VrefLevel [Byte0]: 65
2842 11:03:36.751587 [Byte1]: 65
2843 11:03:36.756409
2844 11:03:36.756503 Set Vref, RX VrefLevel [Byte0]: 66
2845 11:03:36.759520 [Byte1]: 66
2846 11:03:36.764468
2847 11:03:36.764566 Set Vref, RX VrefLevel [Byte0]: 67
2848 11:03:36.767689 [Byte1]: 67
2849 11:03:36.772191
2850 11:03:36.772320 Set Vref, RX VrefLevel [Byte0]: 68
2851 11:03:36.775605 [Byte1]: 68
2852 11:03:36.779907
2853 11:03:36.780000 Set Vref, RX VrefLevel [Byte0]: 69
2854 11:03:36.783801 [Byte1]: 69
2855 11:03:36.788232
2856 11:03:36.788319 Final RX Vref Byte 0 = 53 to rank0
2857 11:03:36.791344 Final RX Vref Byte 1 = 49 to rank0
2858 11:03:36.795177 Final RX Vref Byte 0 = 53 to rank1
2859 11:03:36.797765 Final RX Vref Byte 1 = 49 to rank1==
2860 11:03:36.801308 Dram Type= 6, Freq= 0, CH_0, rank 0
2861 11:03:36.808375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2862 11:03:36.808475 ==
2863 11:03:36.808584 DQS Delay:
2864 11:03:36.808727 DQS0 = 0, DQS1 = 0
2865 11:03:36.811239 DQM Delay:
2866 11:03:36.811305 DQM0 = 120, DQM1 = 112
2867 11:03:36.814777 DQ Delay:
2868 11:03:36.818143 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2869 11:03:36.821627 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2870 11:03:36.824678 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2871 11:03:36.827761 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =122
2872 11:03:36.827837
2873 11:03:36.827894
2874 11:03:36.834830 [DQSOSCAuto] RK0, (LSB)MR18= 0x1812, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 400 ps
2875 11:03:36.837807 CH0 RK0: MR19=404, MR18=1812
2876 11:03:36.844442 CH0_RK0: MR19=0x404, MR18=0x1812, DQSOSC=400, MR23=63, INC=40, DEC=27
2877 11:03:36.844538
2878 11:03:36.847942 ----->DramcWriteLeveling(PI) begin...
2879 11:03:36.848019 ==
2880 11:03:36.851186 Dram Type= 6, Freq= 0, CH_0, rank 1
2881 11:03:36.854496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 11:03:36.858345 ==
2883 11:03:36.858429 Write leveling (Byte 0): 34 => 34
2884 11:03:36.861262 Write leveling (Byte 1): 28 => 28
2885 11:03:36.865007 DramcWriteLeveling(PI) end<-----
2886 11:03:36.865082
2887 11:03:36.865139 ==
2888 11:03:36.867979 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 11:03:36.874937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 11:03:36.875023 ==
2891 11:03:36.875083 [Gating] SW mode calibration
2892 11:03:36.884641 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2893 11:03:36.887797 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2894 11:03:36.891581 0 15 0 | B1->B0 | 3434 3333 | 0 0 | (0 0) (1 1)
2895 11:03:36.898029 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 11:03:36.901571 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 11:03:36.904698 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 11:03:36.911953 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 11:03:36.914603 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 11:03:36.918237 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 11:03:36.925048 0 15 28 | B1->B0 | 2d2d 2c2c | 1 0 | (1 0) (0 0)
2902 11:03:36.928057 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2903 11:03:36.931439 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 11:03:36.938510 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 11:03:36.941521 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 11:03:36.945370 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 11:03:36.951974 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 11:03:36.955411 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 11:03:36.958485 1 0 28 | B1->B0 | 4444 4242 | 0 0 | (0 0) (0 0)
2910 11:03:36.961836 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 11:03:36.968555 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 11:03:36.971581 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 11:03:36.974951 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 11:03:36.981833 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 11:03:36.984909 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 11:03:36.988713 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 11:03:36.995221 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2918 11:03:36.998489 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2919 11:03:37.002091 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 11:03:37.008608 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 11:03:37.012337 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 11:03:37.014981 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 11:03:37.022075 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 11:03:37.025025 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 11:03:37.028663 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 11:03:37.035232 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 11:03:37.038757 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 11:03:37.041789 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 11:03:37.045101 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 11:03:37.051976 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 11:03:37.055155 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 11:03:37.058546 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 11:03:37.065647 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2934 11:03:37.068567 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 11:03:37.071990 Total UI for P1: 0, mck2ui 16
2936 11:03:37.075187 best dqsien dly found for B0: ( 1, 3, 28)
2937 11:03:37.078453 Total UI for P1: 0, mck2ui 16
2938 11:03:37.081940 best dqsien dly found for B1: ( 1, 3, 28)
2939 11:03:37.085453 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2940 11:03:37.088757 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2941 11:03:37.088839
2942 11:03:37.091817 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2943 11:03:37.095603 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2944 11:03:37.098903 [Gating] SW calibration Done
2945 11:03:37.098983 ==
2946 11:03:37.102158 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 11:03:37.105242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 11:03:37.108689 ==
2949 11:03:37.108764 RX Vref Scan: 0
2950 11:03:37.108821
2951 11:03:37.111896 RX Vref 0 -> 0, step: 1
2952 11:03:37.111967
2953 11:03:37.112025 RX Delay -40 -> 252, step: 8
2954 11:03:37.118530 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2955 11:03:37.122078 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2956 11:03:37.125223 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2957 11:03:37.128962 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2958 11:03:37.132231 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2959 11:03:37.139030 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2960 11:03:37.142386 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2961 11:03:37.145614 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2962 11:03:37.148812 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2963 11:03:37.152703 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2964 11:03:37.155663 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2965 11:03:37.162386 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2966 11:03:37.166129 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2967 11:03:37.169069 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2968 11:03:37.172440 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2969 11:03:37.179351 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2970 11:03:37.179443 ==
2971 11:03:37.182529 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 11:03:37.186055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 11:03:37.186138 ==
2974 11:03:37.186196 DQS Delay:
2975 11:03:37.189299 DQS0 = 0, DQS1 = 0
2976 11:03:37.189374 DQM Delay:
2977 11:03:37.192392 DQM0 = 122, DQM1 = 111
2978 11:03:37.192469 DQ Delay:
2979 11:03:37.196686 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2980 11:03:37.199280 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2981 11:03:37.202855 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =103
2982 11:03:37.205860 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2983 11:03:37.205956
2984 11:03:37.206028
2985 11:03:37.206121 ==
2986 11:03:37.209229 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 11:03:37.215995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 11:03:37.216086 ==
2989 11:03:37.216144
2990 11:03:37.216196
2991 11:03:37.216246 TX Vref Scan disable
2992 11:03:37.219662 == TX Byte 0 ==
2993 11:03:37.223017 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2994 11:03:37.226226 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2995 11:03:37.229524 == TX Byte 1 ==
2996 11:03:37.232936 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2997 11:03:37.236369 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2998 11:03:37.239311 ==
2999 11:03:37.242722 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 11:03:37.246031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 11:03:37.246126 ==
3002 11:03:37.258036 TX Vref=22, minBit 1, minWin=25, winSum=408
3003 11:03:37.261506 TX Vref=24, minBit 1, minWin=25, winSum=415
3004 11:03:37.264535 TX Vref=26, minBit 3, minWin=25, winSum=418
3005 11:03:37.267832 TX Vref=28, minBit 3, minWin=25, winSum=422
3006 11:03:37.271743 TX Vref=30, minBit 0, minWin=26, winSum=425
3007 11:03:37.274875 TX Vref=32, minBit 5, minWin=25, winSum=421
3008 11:03:37.281020 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 30
3009 11:03:37.281118
3010 11:03:37.284675 Final TX Range 1 Vref 30
3011 11:03:37.284756
3012 11:03:37.284816 ==
3013 11:03:37.287887 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 11:03:37.291401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 11:03:37.291489 ==
3016 11:03:37.294445
3017 11:03:37.294543
3018 11:03:37.294627 TX Vref Scan disable
3019 11:03:37.298137 == TX Byte 0 ==
3020 11:03:37.301242 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3021 11:03:37.304507 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3022 11:03:37.307750 == TX Byte 1 ==
3023 11:03:37.310947 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3024 11:03:37.317484 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3025 11:03:37.317609
3026 11:03:37.317695 [DATLAT]
3027 11:03:37.317775 Freq=1200, CH0 RK1
3028 11:03:37.317864
3029 11:03:37.321108 DATLAT Default: 0xd
3030 11:03:37.321208 0, 0xFFFF, sum = 0
3031 11:03:37.324076 1, 0xFFFF, sum = 0
3032 11:03:37.327553 2, 0xFFFF, sum = 0
3033 11:03:37.327662 3, 0xFFFF, sum = 0
3034 11:03:37.330631 4, 0xFFFF, sum = 0
3035 11:03:37.330709 5, 0xFFFF, sum = 0
3036 11:03:37.334107 6, 0xFFFF, sum = 0
3037 11:03:37.334178 7, 0xFFFF, sum = 0
3038 11:03:37.337891 8, 0xFFFF, sum = 0
3039 11:03:37.337997 9, 0xFFFF, sum = 0
3040 11:03:37.340378 10, 0xFFFF, sum = 0
3041 11:03:37.340479 11, 0xFFFF, sum = 0
3042 11:03:37.343967 12, 0x0, sum = 1
3043 11:03:37.344037 13, 0x0, sum = 2
3044 11:03:37.347522 14, 0x0, sum = 3
3045 11:03:37.347600 15, 0x0, sum = 4
3046 11:03:37.350785 best_step = 13
3047 11:03:37.350876
3048 11:03:37.350959 ==
3049 11:03:37.354112 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 11:03:37.357216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 11:03:37.357296 ==
3052 11:03:37.357357 RX Vref Scan: 0
3053 11:03:37.360835
3054 11:03:37.360904 RX Vref 0 -> 0, step: 1
3055 11:03:37.360976
3056 11:03:37.364373 RX Delay -13 -> 252, step: 4
3057 11:03:37.370773 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3058 11:03:37.373828 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3059 11:03:37.377728 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3060 11:03:37.380844 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3061 11:03:37.383996 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3062 11:03:37.387072 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3063 11:03:37.393737 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3064 11:03:37.396821 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3065 11:03:37.400766 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3066 11:03:37.403836 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3067 11:03:37.407051 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3068 11:03:37.413766 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3069 11:03:37.416910 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3070 11:03:37.420201 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3071 11:03:37.423742 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3072 11:03:37.430461 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3073 11:03:37.430554 ==
3074 11:03:37.433678 Dram Type= 6, Freq= 0, CH_0, rank 1
3075 11:03:37.437323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 11:03:37.437427 ==
3077 11:03:37.437515 DQS Delay:
3078 11:03:37.440590 DQS0 = 0, DQS1 = 0
3079 11:03:37.440669 DQM Delay:
3080 11:03:37.443410 DQM0 = 121, DQM1 = 110
3081 11:03:37.443493 DQ Delay:
3082 11:03:37.446791 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118
3083 11:03:37.450280 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3084 11:03:37.453349 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3085 11:03:37.456782 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3086 11:03:37.456881
3087 11:03:37.456973
3088 11:03:37.466606 [DQSOSCAuto] RK1, (LSB)MR18= 0x15f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 401 ps
3089 11:03:37.470311 CH0 RK1: MR19=403, MR18=15F6
3090 11:03:37.473703 CH0_RK1: MR19=0x403, MR18=0x15F6, DQSOSC=401, MR23=63, INC=40, DEC=27
3091 11:03:37.476544 [RxdqsGatingPostProcess] freq 1200
3092 11:03:37.483603 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3093 11:03:37.487124 best DQS0 dly(2T, 0.5T) = (0, 11)
3094 11:03:37.489963 best DQS1 dly(2T, 0.5T) = (0, 12)
3095 11:03:37.493811 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3096 11:03:37.496724 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3097 11:03:37.500016 best DQS0 dly(2T, 0.5T) = (0, 11)
3098 11:03:37.503877 best DQS1 dly(2T, 0.5T) = (0, 11)
3099 11:03:37.506485 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3100 11:03:37.509704 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3101 11:03:37.513498 Pre-setting of DQS Precalculation
3102 11:03:37.516723 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3103 11:03:37.516811 ==
3104 11:03:37.520009 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 11:03:37.523106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 11:03:37.523180 ==
3107 11:03:37.529586 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3108 11:03:37.536659 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3109 11:03:37.544763 [CA 0] Center 37 (7~67) winsize 61
3110 11:03:37.547891 [CA 1] Center 37 (7~68) winsize 62
3111 11:03:37.551138 [CA 2] Center 35 (5~65) winsize 61
3112 11:03:37.554193 [CA 3] Center 34 (4~64) winsize 61
3113 11:03:37.557369 [CA 4] Center 34 (4~64) winsize 61
3114 11:03:37.561040 [CA 5] Center 33 (3~63) winsize 61
3115 11:03:37.561119
3116 11:03:37.564343 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3117 11:03:37.564440
3118 11:03:37.567724 [CATrainingPosCal] consider 1 rank data
3119 11:03:37.570800 u2DelayCellTimex100 = 270/100 ps
3120 11:03:37.574244 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3121 11:03:37.577816 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3122 11:03:37.584239 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3123 11:03:37.587968 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3124 11:03:37.590881 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3125 11:03:37.594700 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3126 11:03:37.594779
3127 11:03:37.597907 CA PerBit enable=1, Macro0, CA PI delay=33
3128 11:03:37.598001
3129 11:03:37.601127 [CBTSetCACLKResult] CA Dly = 33
3130 11:03:37.601194 CS Dly: 7 (0~38)
3131 11:03:37.601248 ==
3132 11:03:37.604295 Dram Type= 6, Freq= 0, CH_1, rank 1
3133 11:03:37.610753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 11:03:37.610841 ==
3135 11:03:37.614801 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3136 11:03:37.620886 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3137 11:03:37.630180 [CA 0] Center 37 (7~68) winsize 62
3138 11:03:37.633323 [CA 1] Center 38 (8~68) winsize 61
3139 11:03:37.636450 [CA 2] Center 35 (5~65) winsize 61
3140 11:03:37.639599 [CA 3] Center 34 (4~65) winsize 62
3141 11:03:37.643419 [CA 4] Center 34 (4~65) winsize 62
3142 11:03:37.646826 [CA 5] Center 34 (4~64) winsize 61
3143 11:03:37.646898
3144 11:03:37.649927 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3145 11:03:37.650031
3146 11:03:37.653118 [CATrainingPosCal] consider 2 rank data
3147 11:03:37.656280 u2DelayCellTimex100 = 270/100 ps
3148 11:03:37.659895 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3149 11:03:37.663691 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3150 11:03:37.669551 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3151 11:03:37.672960 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3152 11:03:37.676459 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3153 11:03:37.680071 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3154 11:03:37.680148
3155 11:03:37.683190 CA PerBit enable=1, Macro0, CA PI delay=33
3156 11:03:37.683284
3157 11:03:37.686436 [CBTSetCACLKResult] CA Dly = 33
3158 11:03:37.686522 CS Dly: 9 (0~42)
3159 11:03:37.686597
3160 11:03:37.689732 ----->DramcWriteLeveling(PI) begin...
3161 11:03:37.693374 ==
3162 11:03:37.693443 Dram Type= 6, Freq= 0, CH_1, rank 0
3163 11:03:37.699707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 11:03:37.699806 ==
3165 11:03:37.703047 Write leveling (Byte 0): 25 => 25
3166 11:03:37.706773 Write leveling (Byte 1): 28 => 28
3167 11:03:37.709730 DramcWriteLeveling(PI) end<-----
3168 11:03:37.709804
3169 11:03:37.709864 ==
3170 11:03:37.713077 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 11:03:37.716498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 11:03:37.716590 ==
3173 11:03:37.719648 [Gating] SW mode calibration
3174 11:03:37.726269 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3175 11:03:37.732986 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3176 11:03:37.736888 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 11:03:37.739843 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 11:03:37.742780 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 11:03:37.749351 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 11:03:37.752745 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 11:03:37.756316 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3182 11:03:37.762876 0 15 24 | B1->B0 | 3232 2929 | 0 0 | (0 1) (0 1)
3183 11:03:37.766317 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3184 11:03:37.769535 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 11:03:37.776599 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 11:03:37.779314 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 11:03:37.782677 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 11:03:37.789348 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 11:03:37.792442 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 11:03:37.796048 1 0 24 | B1->B0 | 3434 3f3f | 0 1 | (0 0) (0 0)
3191 11:03:37.803170 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 11:03:37.806495 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 11:03:37.809679 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 11:03:37.816320 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 11:03:37.819242 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 11:03:37.822601 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 11:03:37.828990 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 11:03:37.832565 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3199 11:03:37.835804 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3200 11:03:37.842546 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 11:03:37.845774 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 11:03:37.849635 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 11:03:37.856504 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 11:03:37.859032 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 11:03:37.862628 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 11:03:37.865946 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 11:03:37.872575 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 11:03:37.876403 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 11:03:37.879608 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 11:03:37.886247 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 11:03:37.889092 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 11:03:37.892701 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 11:03:37.899290 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 11:03:37.902488 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3215 11:03:37.905986 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3216 11:03:37.912392 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 11:03:37.915717 Total UI for P1: 0, mck2ui 16
3218 11:03:37.919253 best dqsien dly found for B0: ( 1, 3, 26)
3219 11:03:37.919355 Total UI for P1: 0, mck2ui 16
3220 11:03:37.925942 best dqsien dly found for B1: ( 1, 3, 26)
3221 11:03:37.929065 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3222 11:03:37.932479 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3223 11:03:37.932560
3224 11:03:37.935665 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3225 11:03:37.938986 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3226 11:03:37.942089 [Gating] SW calibration Done
3227 11:03:37.942167 ==
3228 11:03:37.945682 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 11:03:37.948842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 11:03:37.948944 ==
3231 11:03:37.952097 RX Vref Scan: 0
3232 11:03:37.952174
3233 11:03:37.952270 RX Vref 0 -> 0, step: 1
3234 11:03:37.952348
3235 11:03:37.956027 RX Delay -40 -> 252, step: 8
3236 11:03:37.962409 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3237 11:03:37.965399 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3238 11:03:37.968993 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3239 11:03:37.972040 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3240 11:03:37.975801 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3241 11:03:37.979262 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3242 11:03:37.985470 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3243 11:03:37.988970 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3244 11:03:37.992690 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3245 11:03:37.995502 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3246 11:03:37.999537 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3247 11:03:38.005948 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3248 11:03:38.009389 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3249 11:03:38.012018 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3250 11:03:38.015274 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3251 11:03:38.022569 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3252 11:03:38.022688 ==
3253 11:03:38.025701 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 11:03:38.028799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 11:03:38.028906 ==
3256 11:03:38.028991 DQS Delay:
3257 11:03:38.032315 DQS0 = 0, DQS1 = 0
3258 11:03:38.032384 DQM Delay:
3259 11:03:38.035575 DQM0 = 120, DQM1 = 116
3260 11:03:38.035648 DQ Delay:
3261 11:03:38.038640 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3262 11:03:38.041841 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3263 11:03:38.045182 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3264 11:03:38.048590 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3265 11:03:38.048696
3266 11:03:38.048791
3267 11:03:38.052562 ==
3268 11:03:38.052670 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 11:03:38.058722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 11:03:38.058832 ==
3271 11:03:38.058918
3272 11:03:38.059000
3273 11:03:38.062126 TX Vref Scan disable
3274 11:03:38.062218 == TX Byte 0 ==
3275 11:03:38.065114 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3276 11:03:38.072298 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3277 11:03:38.072407 == TX Byte 1 ==
3278 11:03:38.075263 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3279 11:03:38.082174 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3280 11:03:38.082287 ==
3281 11:03:38.085181 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 11:03:38.088532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 11:03:38.088631 ==
3284 11:03:38.100458 TX Vref=22, minBit 11, minWin=24, winSum=411
3285 11:03:38.103353 TX Vref=24, minBit 9, minWin=25, winSum=420
3286 11:03:38.107061 TX Vref=26, minBit 10, minWin=25, winSum=423
3287 11:03:38.110226 TX Vref=28, minBit 3, minWin=26, winSum=430
3288 11:03:38.113569 TX Vref=30, minBit 2, minWin=26, winSum=429
3289 11:03:38.120360 TX Vref=32, minBit 11, minWin=25, winSum=426
3290 11:03:38.123564 [TxChooseVref] Worse bit 3, Min win 26, Win sum 430, Final Vref 28
3291 11:03:38.123679
3292 11:03:38.126700 Final TX Range 1 Vref 28
3293 11:03:38.126794
3294 11:03:38.126869 ==
3295 11:03:38.130370 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 11:03:38.133708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 11:03:38.137916 ==
3298 11:03:38.138026
3299 11:03:38.138103
3300 11:03:38.138156 TX Vref Scan disable
3301 11:03:38.140525 == TX Byte 0 ==
3302 11:03:38.143864 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3303 11:03:38.146790 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3304 11:03:38.150317 == TX Byte 1 ==
3305 11:03:38.153833 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3306 11:03:38.156772 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3307 11:03:38.160433
3308 11:03:38.160517 [DATLAT]
3309 11:03:38.160577 Freq=1200, CH1 RK0
3310 11:03:38.160630
3311 11:03:38.163787 DATLAT Default: 0xd
3312 11:03:38.163866 0, 0xFFFF, sum = 0
3313 11:03:38.167178 1, 0xFFFF, sum = 0
3314 11:03:38.167257 2, 0xFFFF, sum = 0
3315 11:03:38.170406 3, 0xFFFF, sum = 0
3316 11:03:38.170501 4, 0xFFFF, sum = 0
3317 11:03:38.173657 5, 0xFFFF, sum = 0
3318 11:03:38.173750 6, 0xFFFF, sum = 0
3319 11:03:38.177250 7, 0xFFFF, sum = 0
3320 11:03:38.180319 8, 0xFFFF, sum = 0
3321 11:03:38.180409 9, 0xFFFF, sum = 0
3322 11:03:38.183374 10, 0xFFFF, sum = 0
3323 11:03:38.183468 11, 0xFFFF, sum = 0
3324 11:03:38.186673 12, 0x0, sum = 1
3325 11:03:38.186766 13, 0x0, sum = 2
3326 11:03:38.190576 14, 0x0, sum = 3
3327 11:03:38.190674 15, 0x0, sum = 4
3328 11:03:38.190749 best_step = 13
3329 11:03:38.190832
3330 11:03:38.193753 ==
3331 11:03:38.196964 Dram Type= 6, Freq= 0, CH_1, rank 0
3332 11:03:38.200140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3333 11:03:38.200221 ==
3334 11:03:38.200280 RX Vref Scan: 1
3335 11:03:38.200333
3336 11:03:38.203671 Set Vref Range= 32 -> 127
3337 11:03:38.203764
3338 11:03:38.206691 RX Vref 32 -> 127, step: 1
3339 11:03:38.206783
3340 11:03:38.210672 RX Delay -5 -> 252, step: 4
3341 11:03:38.210767
3342 11:03:38.213215 Set Vref, RX VrefLevel [Byte0]: 32
3343 11:03:38.217021 [Byte1]: 32
3344 11:03:38.217115
3345 11:03:38.220507 Set Vref, RX VrefLevel [Byte0]: 33
3346 11:03:38.223333 [Byte1]: 33
3347 11:03:38.223409
3348 11:03:38.226698 Set Vref, RX VrefLevel [Byte0]: 34
3349 11:03:38.229726 [Byte1]: 34
3350 11:03:38.234049
3351 11:03:38.234132 Set Vref, RX VrefLevel [Byte0]: 35
3352 11:03:38.237801 [Byte1]: 35
3353 11:03:38.242170
3354 11:03:38.242257 Set Vref, RX VrefLevel [Byte0]: 36
3355 11:03:38.245461 [Byte1]: 36
3356 11:03:38.249730
3357 11:03:38.249816 Set Vref, RX VrefLevel [Byte0]: 37
3358 11:03:38.253477 [Byte1]: 37
3359 11:03:38.258237
3360 11:03:38.258325 Set Vref, RX VrefLevel [Byte0]: 38
3361 11:03:38.261240 [Byte1]: 38
3362 11:03:38.265679
3363 11:03:38.265764 Set Vref, RX VrefLevel [Byte0]: 39
3364 11:03:38.269238 [Byte1]: 39
3365 11:03:38.273597
3366 11:03:38.273683 Set Vref, RX VrefLevel [Byte0]: 40
3367 11:03:38.276980 [Byte1]: 40
3368 11:03:38.281353
3369 11:03:38.281441 Set Vref, RX VrefLevel [Byte0]: 41
3370 11:03:38.284830 [Byte1]: 41
3371 11:03:38.289409
3372 11:03:38.289499 Set Vref, RX VrefLevel [Byte0]: 42
3373 11:03:38.292419 [Byte1]: 42
3374 11:03:38.297247
3375 11:03:38.297332 Set Vref, RX VrefLevel [Byte0]: 43
3376 11:03:38.300499 [Byte1]: 43
3377 11:03:38.305000
3378 11:03:38.305090 Set Vref, RX VrefLevel [Byte0]: 44
3379 11:03:38.308422 [Byte1]: 44
3380 11:03:38.312694
3381 11:03:38.312782 Set Vref, RX VrefLevel [Byte0]: 45
3382 11:03:38.315993 [Byte1]: 45
3383 11:03:38.320893
3384 11:03:38.320980 Set Vref, RX VrefLevel [Byte0]: 46
3385 11:03:38.323903 [Byte1]: 46
3386 11:03:38.328247
3387 11:03:38.328327 Set Vref, RX VrefLevel [Byte0]: 47
3388 11:03:38.331480 [Byte1]: 47
3389 11:03:38.336293
3390 11:03:38.336374 Set Vref, RX VrefLevel [Byte0]: 48
3391 11:03:38.339696 [Byte1]: 48
3392 11:03:38.344470
3393 11:03:38.344557 Set Vref, RX VrefLevel [Byte0]: 49
3394 11:03:38.347370 [Byte1]: 49
3395 11:03:38.351934
3396 11:03:38.352015 Set Vref, RX VrefLevel [Byte0]: 50
3397 11:03:38.355121 [Byte1]: 50
3398 11:03:38.360530
3399 11:03:38.360621 Set Vref, RX VrefLevel [Byte0]: 51
3400 11:03:38.362918 [Byte1]: 51
3401 11:03:38.367628
3402 11:03:38.367707 Set Vref, RX VrefLevel [Byte0]: 52
3403 11:03:38.371409 [Byte1]: 52
3404 11:03:38.375448
3405 11:03:38.375528 Set Vref, RX VrefLevel [Byte0]: 53
3406 11:03:38.379350 [Byte1]: 53
3407 11:03:38.383354
3408 11:03:38.383443 Set Vref, RX VrefLevel [Byte0]: 54
3409 11:03:38.386837 [Byte1]: 54
3410 11:03:38.391539
3411 11:03:38.391620 Set Vref, RX VrefLevel [Byte0]: 55
3412 11:03:38.394787 [Byte1]: 55
3413 11:03:38.399031
3414 11:03:38.399111 Set Vref, RX VrefLevel [Byte0]: 56
3415 11:03:38.402241 [Byte1]: 56
3416 11:03:38.407387
3417 11:03:38.407468 Set Vref, RX VrefLevel [Byte0]: 57
3418 11:03:38.410276 [Byte1]: 57
3419 11:03:38.414765
3420 11:03:38.414844 Set Vref, RX VrefLevel [Byte0]: 58
3421 11:03:38.418284 [Byte1]: 58
3422 11:03:38.422549
3423 11:03:38.422627 Set Vref, RX VrefLevel [Byte0]: 59
3424 11:03:38.426127 [Byte1]: 59
3425 11:03:38.430944
3426 11:03:38.431027 Set Vref, RX VrefLevel [Byte0]: 60
3427 11:03:38.433766 [Byte1]: 60
3428 11:03:38.438467
3429 11:03:38.438549 Set Vref, RX VrefLevel [Byte0]: 61
3430 11:03:38.441933 [Byte1]: 61
3431 11:03:38.446185
3432 11:03:38.446264 Set Vref, RX VrefLevel [Byte0]: 62
3433 11:03:38.450171 [Byte1]: 62
3434 11:03:38.453833
3435 11:03:38.453939 Set Vref, RX VrefLevel [Byte0]: 63
3436 11:03:38.457338 [Byte1]: 63
3437 11:03:38.461970
3438 11:03:38.462105 Set Vref, RX VrefLevel [Byte0]: 64
3439 11:03:38.465314 [Byte1]: 64
3440 11:03:38.469645
3441 11:03:38.469752 Set Vref, RX VrefLevel [Byte0]: 65
3442 11:03:38.473498 [Byte1]: 65
3443 11:03:38.478193
3444 11:03:38.478275 Set Vref, RX VrefLevel [Byte0]: 66
3445 11:03:38.481088 [Byte1]: 66
3446 11:03:38.485813
3447 11:03:38.485915 Set Vref, RX VrefLevel [Byte0]: 67
3448 11:03:38.488899 [Byte1]: 67
3449 11:03:38.493506
3450 11:03:38.493633 Final RX Vref Byte 0 = 53 to rank0
3451 11:03:38.496709 Final RX Vref Byte 1 = 52 to rank0
3452 11:03:38.499841 Final RX Vref Byte 0 = 53 to rank1
3453 11:03:38.503895 Final RX Vref Byte 1 = 52 to rank1==
3454 11:03:38.506635 Dram Type= 6, Freq= 0, CH_1, rank 0
3455 11:03:38.513003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3456 11:03:38.513094 ==
3457 11:03:38.513152 DQS Delay:
3458 11:03:38.513205 DQS0 = 0, DQS1 = 0
3459 11:03:38.516866 DQM Delay:
3460 11:03:38.516943 DQM0 = 119, DQM1 = 117
3461 11:03:38.519975 DQ Delay:
3462 11:03:38.523067 DQ0 =122, DQ1 =114, DQ2 =110, DQ3 =116
3463 11:03:38.526895 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3464 11:03:38.530140 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3465 11:03:38.532974 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3466 11:03:38.533053
3467 11:03:38.533111
3468 11:03:38.539708 [DQSOSCAuto] RK0, (LSB)MR18= 0x518, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 408 ps
3469 11:03:38.543732 CH1 RK0: MR19=404, MR18=518
3470 11:03:38.550159 CH1_RK0: MR19=0x404, MR18=0x518, DQSOSC=400, MR23=63, INC=40, DEC=27
3471 11:03:38.550254
3472 11:03:38.553220 ----->DramcWriteLeveling(PI) begin...
3473 11:03:38.553298 ==
3474 11:03:38.556217 Dram Type= 6, Freq= 0, CH_1, rank 1
3475 11:03:38.559560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3476 11:03:38.563277 ==
3477 11:03:38.563381 Write leveling (Byte 0): 26 => 26
3478 11:03:38.566397 Write leveling (Byte 1): 29 => 29
3479 11:03:38.570333 DramcWriteLeveling(PI) end<-----
3480 11:03:38.570429
3481 11:03:38.570502 ==
3482 11:03:38.573457 Dram Type= 6, Freq= 0, CH_1, rank 1
3483 11:03:38.580115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3484 11:03:38.580220 ==
3485 11:03:38.580281 [Gating] SW mode calibration
3486 11:03:38.589569 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3487 11:03:38.592925 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3488 11:03:38.599763 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 11:03:38.603298 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3490 11:03:38.606604 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3491 11:03:38.609863 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 11:03:38.617004 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 11:03:38.619944 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3494 11:03:38.623134 0 15 24 | B1->B0 | 2727 3333 | 0 1 | (1 0) (1 0)
3495 11:03:38.629713 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 1)
3496 11:03:38.633473 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 11:03:38.636498 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 11:03:38.643054 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3499 11:03:38.646580 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 11:03:38.649739 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 11:03:38.656139 1 0 20 | B1->B0 | 2a2a 2323 | 1 0 | (0 0) (0 0)
3502 11:03:38.659472 1 0 24 | B1->B0 | 4545 2727 | 0 0 | (0 0) (0 0)
3503 11:03:38.662992 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3504 11:03:38.670139 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 11:03:38.672985 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 11:03:38.676157 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 11:03:38.682896 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 11:03:38.686510 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 11:03:38.689575 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3510 11:03:38.696314 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3511 11:03:38.699501 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3512 11:03:38.702779 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 11:03:38.709501 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 11:03:38.712916 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 11:03:38.717144 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 11:03:38.719587 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 11:03:38.726139 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 11:03:38.729377 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 11:03:38.732953 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 11:03:38.739113 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 11:03:38.743075 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 11:03:38.745946 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 11:03:38.752627 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 11:03:38.755777 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 11:03:38.759398 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3526 11:03:38.766323 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3527 11:03:38.768998 Total UI for P1: 0, mck2ui 16
3528 11:03:38.772224 best dqsien dly found for B1: ( 1, 3, 20)
3529 11:03:38.775742 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3530 11:03:38.779024 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 11:03:38.782384 Total UI for P1: 0, mck2ui 16
3532 11:03:38.785572 best dqsien dly found for B0: ( 1, 3, 26)
3533 11:03:38.788824 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3534 11:03:38.792395 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3535 11:03:38.795603
3536 11:03:38.798580 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3537 11:03:38.802048 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3538 11:03:38.805728 [Gating] SW calibration Done
3539 11:03:38.805811 ==
3540 11:03:38.809011 Dram Type= 6, Freq= 0, CH_1, rank 1
3541 11:03:38.812463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3542 11:03:38.812545 ==
3543 11:03:38.812604 RX Vref Scan: 0
3544 11:03:38.812657
3545 11:03:38.815664 RX Vref 0 -> 0, step: 1
3546 11:03:38.815740
3547 11:03:38.819036 RX Delay -40 -> 252, step: 8
3548 11:03:38.822302 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3549 11:03:38.825361 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3550 11:03:38.831929 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3551 11:03:38.835444 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3552 11:03:38.838790 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3553 11:03:38.842527 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3554 11:03:38.845602 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3555 11:03:38.852310 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3556 11:03:38.855412 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3557 11:03:38.858908 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3558 11:03:38.862722 iDelay=200, Bit 10, Center 119 (48 ~ 191) 144
3559 11:03:38.865641 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3560 11:03:38.872136 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3561 11:03:38.875332 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3562 11:03:38.879072 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3563 11:03:38.882302 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3564 11:03:38.882384 ==
3565 11:03:38.885353 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 11:03:38.889294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 11:03:38.892029 ==
3568 11:03:38.892105 DQS Delay:
3569 11:03:38.892162 DQS0 = 0, DQS1 = 0
3570 11:03:38.895403 DQM Delay:
3571 11:03:38.895476 DQM0 = 119, DQM1 = 118
3572 11:03:38.898808 DQ Delay:
3573 11:03:38.902331 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3574 11:03:38.905485 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3575 11:03:38.908560 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3576 11:03:38.912201 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3577 11:03:38.912290
3578 11:03:38.912365
3579 11:03:38.912435 ==
3580 11:03:38.915206 Dram Type= 6, Freq= 0, CH_1, rank 1
3581 11:03:38.919153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3582 11:03:38.919242 ==
3583 11:03:38.922216
3584 11:03:38.922308
3585 11:03:38.922380 TX Vref Scan disable
3586 11:03:38.925347 == TX Byte 0 ==
3587 11:03:38.928588 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3588 11:03:38.932450 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3589 11:03:38.935872 == TX Byte 1 ==
3590 11:03:38.938781 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3591 11:03:38.942063 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3592 11:03:38.942169 ==
3593 11:03:38.945249 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 11:03:38.951834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 11:03:38.951926 ==
3596 11:03:38.962344 TX Vref=22, minBit 9, minWin=25, winSum=421
3597 11:03:38.966027 TX Vref=24, minBit 9, minWin=25, winSum=423
3598 11:03:38.969052 TX Vref=26, minBit 1, minWin=26, winSum=431
3599 11:03:38.972626 TX Vref=28, minBit 9, minWin=26, winSum=432
3600 11:03:38.975668 TX Vref=30, minBit 8, minWin=26, winSum=431
3601 11:03:38.979124 TX Vref=32, minBit 9, minWin=26, winSum=434
3602 11:03:38.985825 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 32
3603 11:03:38.985937
3604 11:03:38.989268 Final TX Range 1 Vref 32
3605 11:03:38.989343
3606 11:03:38.989399 ==
3607 11:03:38.992666 Dram Type= 6, Freq= 0, CH_1, rank 1
3608 11:03:38.996021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3609 11:03:38.996097 ==
3610 11:03:38.996160
3611 11:03:38.996214
3612 11:03:38.999119 TX Vref Scan disable
3613 11:03:39.002528 == TX Byte 0 ==
3614 11:03:39.006081 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3615 11:03:39.009376 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3616 11:03:39.012716 == TX Byte 1 ==
3617 11:03:39.015871 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3618 11:03:39.019008 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3619 11:03:39.019126
3620 11:03:39.022802 [DATLAT]
3621 11:03:39.022904 Freq=1200, CH1 RK1
3622 11:03:39.022965
3623 11:03:39.026065 DATLAT Default: 0xd
3624 11:03:39.026162 0, 0xFFFF, sum = 0
3625 11:03:39.029357 1, 0xFFFF, sum = 0
3626 11:03:39.029504 2, 0xFFFF, sum = 0
3627 11:03:39.032465 3, 0xFFFF, sum = 0
3628 11:03:39.032589 4, 0xFFFF, sum = 0
3629 11:03:39.036355 5, 0xFFFF, sum = 0
3630 11:03:39.036459 6, 0xFFFF, sum = 0
3631 11:03:39.039488 7, 0xFFFF, sum = 0
3632 11:03:39.039605 8, 0xFFFF, sum = 0
3633 11:03:39.042792 9, 0xFFFF, sum = 0
3634 11:03:39.045739 10, 0xFFFF, sum = 0
3635 11:03:39.045824 11, 0xFFFF, sum = 0
3636 11:03:39.048961 12, 0x0, sum = 1
3637 11:03:39.049035 13, 0x0, sum = 2
3638 11:03:39.052283 14, 0x0, sum = 3
3639 11:03:39.052354 15, 0x0, sum = 4
3640 11:03:39.052418 best_step = 13
3641 11:03:39.052470
3642 11:03:39.055510 ==
3643 11:03:39.059164 Dram Type= 6, Freq= 0, CH_1, rank 1
3644 11:03:39.062847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3645 11:03:39.062931 ==
3646 11:03:39.062987 RX Vref Scan: 0
3647 11:03:39.063039
3648 11:03:39.065834 RX Vref 0 -> 0, step: 1
3649 11:03:39.065928
3650 11:03:39.068895 RX Delay -5 -> 252, step: 4
3651 11:03:39.072674 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3652 11:03:39.075978 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3653 11:03:39.082250 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3654 11:03:39.085374 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3655 11:03:39.089135 iDelay=195, Bit 4, Center 118 (59 ~ 178) 120
3656 11:03:39.092463 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3657 11:03:39.095616 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3658 11:03:39.102510 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3659 11:03:39.105493 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3660 11:03:39.108688 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3661 11:03:39.112398 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3662 11:03:39.115686 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3663 11:03:39.122252 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3664 11:03:39.125571 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3665 11:03:39.128753 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3666 11:03:39.132382 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3667 11:03:39.132457 ==
3668 11:03:39.135584 Dram Type= 6, Freq= 0, CH_1, rank 1
3669 11:03:39.142201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3670 11:03:39.142324 ==
3671 11:03:39.142433 DQS Delay:
3672 11:03:39.145249 DQS0 = 0, DQS1 = 0
3673 11:03:39.145321 DQM Delay:
3674 11:03:39.145383 DQM0 = 120, DQM1 = 118
3675 11:03:39.148856 DQ Delay:
3676 11:03:39.152447 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3677 11:03:39.155674 DQ4 =118, DQ5 =132, DQ6 =130, DQ7 =120
3678 11:03:39.158766 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3679 11:03:39.162082 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3680 11:03:39.162166
3681 11:03:39.162223
3682 11:03:39.172391 [DQSOSCAuto] RK1, (LSB)MR18= 0x13ef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 402 ps
3683 11:03:39.172496 CH1 RK1: MR19=403, MR18=13EF
3684 11:03:39.178611 CH1_RK1: MR19=0x403, MR18=0x13EF, DQSOSC=402, MR23=63, INC=40, DEC=27
3685 11:03:39.182500 [RxdqsGatingPostProcess] freq 1200
3686 11:03:39.188806 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3687 11:03:39.192691 best DQS0 dly(2T, 0.5T) = (0, 11)
3688 11:03:39.195675 best DQS1 dly(2T, 0.5T) = (0, 11)
3689 11:03:39.198800 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3690 11:03:39.201972 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3691 11:03:39.205624 best DQS0 dly(2T, 0.5T) = (0, 11)
3692 11:03:39.205705 best DQS1 dly(2T, 0.5T) = (0, 11)
3693 11:03:39.208714 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3694 11:03:39.211945 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3695 11:03:39.215526 Pre-setting of DQS Precalculation
3696 11:03:39.221846 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3697 11:03:39.228487 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3698 11:03:39.235457 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3699 11:03:39.235551
3700 11:03:39.235610
3701 11:03:39.238663 [Calibration Summary] 2400 Mbps
3702 11:03:39.238731 CH 0, Rank 0
3703 11:03:39.242248 SW Impedance : PASS
3704 11:03:39.245543 DUTY Scan : NO K
3705 11:03:39.245614 ZQ Calibration : PASS
3706 11:03:39.248905 Jitter Meter : NO K
3707 11:03:39.252194 CBT Training : PASS
3708 11:03:39.252294 Write leveling : PASS
3709 11:03:39.255710 RX DQS gating : PASS
3710 11:03:39.258902 RX DQ/DQS(RDDQC) : PASS
3711 11:03:39.259004 TX DQ/DQS : PASS
3712 11:03:39.261869 RX DATLAT : PASS
3713 11:03:39.265504 RX DQ/DQS(Engine): PASS
3714 11:03:39.265584 TX OE : NO K
3715 11:03:39.268529 All Pass.
3716 11:03:39.268616
3717 11:03:39.268673 CH 0, Rank 1
3718 11:03:39.271977 SW Impedance : PASS
3719 11:03:39.272086 DUTY Scan : NO K
3720 11:03:39.275247 ZQ Calibration : PASS
3721 11:03:39.278710 Jitter Meter : NO K
3722 11:03:39.278817 CBT Training : PASS
3723 11:03:39.281916 Write leveling : PASS
3724 11:03:39.282036 RX DQS gating : PASS
3725 11:03:39.285835 RX DQ/DQS(RDDQC) : PASS
3726 11:03:39.288525 TX DQ/DQS : PASS
3727 11:03:39.288620 RX DATLAT : PASS
3728 11:03:39.292048 RX DQ/DQS(Engine): PASS
3729 11:03:39.295458 TX OE : NO K
3730 11:03:39.295589 All Pass.
3731 11:03:39.295692
3732 11:03:39.295748 CH 1, Rank 0
3733 11:03:39.298400 SW Impedance : PASS
3734 11:03:39.301702 DUTY Scan : NO K
3735 11:03:39.301794 ZQ Calibration : PASS
3736 11:03:39.305376 Jitter Meter : NO K
3737 11:03:39.308641 CBT Training : PASS
3738 11:03:39.308719 Write leveling : PASS
3739 11:03:39.312149 RX DQS gating : PASS
3740 11:03:39.314971 RX DQ/DQS(RDDQC) : PASS
3741 11:03:39.315065 TX DQ/DQS : PASS
3742 11:03:39.318710 RX DATLAT : PASS
3743 11:03:39.321972 RX DQ/DQS(Engine): PASS
3744 11:03:39.322115 TX OE : NO K
3745 11:03:39.322190 All Pass.
3746 11:03:39.325200
3747 11:03:39.325277 CH 1, Rank 1
3748 11:03:39.328273 SW Impedance : PASS
3749 11:03:39.328351 DUTY Scan : NO K
3750 11:03:39.331469 ZQ Calibration : PASS
3751 11:03:39.335243 Jitter Meter : NO K
3752 11:03:39.335336 CBT Training : PASS
3753 11:03:39.338736 Write leveling : PASS
3754 11:03:39.338827 RX DQS gating : PASS
3755 11:03:39.341654 RX DQ/DQS(RDDQC) : PASS
3756 11:03:39.344817 TX DQ/DQS : PASS
3757 11:03:39.344909 RX DATLAT : PASS
3758 11:03:39.348587 RX DQ/DQS(Engine): PASS
3759 11:03:39.351776 TX OE : NO K
3760 11:03:39.351857 All Pass.
3761 11:03:39.351944
3762 11:03:39.354763 DramC Write-DBI off
3763 11:03:39.354854 PER_BANK_REFRESH: Hybrid Mode
3764 11:03:39.357978 TX_TRACKING: ON
3765 11:03:39.368236 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3766 11:03:39.371672 [FAST_K] Save calibration result to emmc
3767 11:03:39.374698 dramc_set_vcore_voltage set vcore to 650000
3768 11:03:39.374778 Read voltage for 600, 5
3769 11:03:39.378495 Vio18 = 0
3770 11:03:39.378571 Vcore = 650000
3771 11:03:39.378634 Vdram = 0
3772 11:03:39.381355 Vddq = 0
3773 11:03:39.381431 Vmddr = 0
3774 11:03:39.385318 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3775 11:03:39.391555 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3776 11:03:39.394624 MEM_TYPE=3, freq_sel=19
3777 11:03:39.397951 sv_algorithm_assistance_LP4_1600
3778 11:03:39.401775 ============ PULL DRAM RESETB DOWN ============
3779 11:03:39.404882 ========== PULL DRAM RESETB DOWN end =========
3780 11:03:39.411304 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3781 11:03:39.414482 ===================================
3782 11:03:39.414562 LPDDR4 DRAM CONFIGURATION
3783 11:03:39.417960 ===================================
3784 11:03:39.421830 EX_ROW_EN[0] = 0x0
3785 11:03:39.421940 EX_ROW_EN[1] = 0x0
3786 11:03:39.424881 LP4Y_EN = 0x0
3787 11:03:39.424967 WORK_FSP = 0x0
3788 11:03:39.427935 WL = 0x2
3789 11:03:39.428007 RL = 0x2
3790 11:03:39.431177 BL = 0x2
3791 11:03:39.434625 RPST = 0x0
3792 11:03:39.434698 RD_PRE = 0x0
3793 11:03:39.438423 WR_PRE = 0x1
3794 11:03:39.438491 WR_PST = 0x0
3795 11:03:39.441423 DBI_WR = 0x0
3796 11:03:39.441491 DBI_RD = 0x0
3797 11:03:39.444629 OTF = 0x1
3798 11:03:39.447699 ===================================
3799 11:03:39.451730 ===================================
3800 11:03:39.451803 ANA top config
3801 11:03:39.454934 ===================================
3802 11:03:39.458020 DLL_ASYNC_EN = 0
3803 11:03:39.461287 ALL_SLAVE_EN = 1
3804 11:03:39.461361 NEW_RANK_MODE = 1
3805 11:03:39.464508 DLL_IDLE_MODE = 1
3806 11:03:39.467496 LP45_APHY_COMB_EN = 1
3807 11:03:39.471638 TX_ODT_DIS = 1
3808 11:03:39.471725 NEW_8X_MODE = 1
3809 11:03:39.474460 ===================================
3810 11:03:39.477562 ===================================
3811 11:03:39.480839 data_rate = 1200
3812 11:03:39.484518 CKR = 1
3813 11:03:39.487804 DQ_P2S_RATIO = 8
3814 11:03:39.491339 ===================================
3815 11:03:39.494475 CA_P2S_RATIO = 8
3816 11:03:39.497660 DQ_CA_OPEN = 0
3817 11:03:39.500936 DQ_SEMI_OPEN = 0
3818 11:03:39.501019 CA_SEMI_OPEN = 0
3819 11:03:39.504094 CA_FULL_RATE = 0
3820 11:03:39.507735 DQ_CKDIV4_EN = 1
3821 11:03:39.510735 CA_CKDIV4_EN = 1
3822 11:03:39.514179 CA_PREDIV_EN = 0
3823 11:03:39.517251 PH8_DLY = 0
3824 11:03:39.517323 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3825 11:03:39.521130 DQ_AAMCK_DIV = 4
3826 11:03:39.523990 CA_AAMCK_DIV = 4
3827 11:03:39.527158 CA_ADMCK_DIV = 4
3828 11:03:39.531003 DQ_TRACK_CA_EN = 0
3829 11:03:39.534280 CA_PICK = 600
3830 11:03:39.537178 CA_MCKIO = 600
3831 11:03:39.537250 MCKIO_SEMI = 0
3832 11:03:39.541745 PLL_FREQ = 2288
3833 11:03:39.543828 DQ_UI_PI_RATIO = 32
3834 11:03:39.547125 CA_UI_PI_RATIO = 0
3835 11:03:39.550380 ===================================
3836 11:03:39.553733 ===================================
3837 11:03:39.557252 memory_type:LPDDR4
3838 11:03:39.557364 GP_NUM : 10
3839 11:03:39.560688 SRAM_EN : 1
3840 11:03:39.560853 MD32_EN : 0
3841 11:03:39.563784 ===================================
3842 11:03:39.567083 [ANA_INIT] >>>>>>>>>>>>>>
3843 11:03:39.570497 <<<<<< [CONFIGURE PHASE]: ANA_TX
3844 11:03:39.573858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3845 11:03:39.576994 ===================================
3846 11:03:39.580665 data_rate = 1200,PCW = 0X5800
3847 11:03:39.583887 ===================================
3848 11:03:39.587520 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3849 11:03:39.593785 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3850 11:03:39.597440 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3851 11:03:39.604318 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3852 11:03:39.607385 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3853 11:03:39.610629 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3854 11:03:39.610703 [ANA_INIT] flow start
3855 11:03:39.614120 [ANA_INIT] PLL >>>>>>>>
3856 11:03:39.616901 [ANA_INIT] PLL <<<<<<<<
3857 11:03:39.617002 [ANA_INIT] MIDPI >>>>>>>>
3858 11:03:39.620164 [ANA_INIT] MIDPI <<<<<<<<
3859 11:03:39.623579 [ANA_INIT] DLL >>>>>>>>
3860 11:03:39.623656 [ANA_INIT] flow end
3861 11:03:39.630356 ============ LP4 DIFF to SE enter ============
3862 11:03:39.634182 ============ LP4 DIFF to SE exit ============
3863 11:03:39.634260 [ANA_INIT] <<<<<<<<<<<<<
3864 11:03:39.637137 [Flow] Enable top DCM control >>>>>
3865 11:03:39.640558 [Flow] Enable top DCM control <<<<<
3866 11:03:39.643865 Enable DLL master slave shuffle
3867 11:03:39.650732 ==============================================================
3868 11:03:39.653865 Gating Mode config
3869 11:03:39.657429 ==============================================================
3870 11:03:39.660413 Config description:
3871 11:03:39.670342 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3872 11:03:39.677557 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3873 11:03:39.680592 SELPH_MODE 0: By rank 1: By Phase
3874 11:03:39.687524 ==============================================================
3875 11:03:39.690842 GAT_TRACK_EN = 1
3876 11:03:39.690922 RX_GATING_MODE = 2
3877 11:03:39.693869 RX_GATING_TRACK_MODE = 2
3878 11:03:39.697407 SELPH_MODE = 1
3879 11:03:39.700591 PICG_EARLY_EN = 1
3880 11:03:39.703807 VALID_LAT_VALUE = 1
3881 11:03:39.710161 ==============================================================
3882 11:03:39.713983 Enter into Gating configuration >>>>
3883 11:03:39.716876 Exit from Gating configuration <<<<
3884 11:03:39.720835 Enter into DVFS_PRE_config >>>>>
3885 11:03:39.730319 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3886 11:03:39.734138 Exit from DVFS_PRE_config <<<<<
3887 11:03:39.737382 Enter into PICG configuration >>>>
3888 11:03:39.740155 Exit from PICG configuration <<<<
3889 11:03:39.744000 [RX_INPUT] configuration >>>>>
3890 11:03:39.747233 [RX_INPUT] configuration <<<<<
3891 11:03:39.750106 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3892 11:03:39.756720 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3893 11:03:39.763723 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3894 11:03:39.769924 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3895 11:03:39.773880 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3896 11:03:39.780398 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3897 11:03:39.783541 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3898 11:03:39.790505 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3899 11:03:39.793780 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3900 11:03:39.797034 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3901 11:03:39.800379 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3902 11:03:39.806786 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3903 11:03:39.810645 ===================================
3904 11:03:39.810778 LPDDR4 DRAM CONFIGURATION
3905 11:03:39.813231 ===================================
3906 11:03:39.816521 EX_ROW_EN[0] = 0x0
3907 11:03:39.820318 EX_ROW_EN[1] = 0x0
3908 11:03:39.820451 LP4Y_EN = 0x0
3909 11:03:39.823089 WORK_FSP = 0x0
3910 11:03:39.823193 WL = 0x2
3911 11:03:39.827016 RL = 0x2
3912 11:03:39.827124 BL = 0x2
3913 11:03:39.830291 RPST = 0x0
3914 11:03:39.830404 RD_PRE = 0x0
3915 11:03:39.833559 WR_PRE = 0x1
3916 11:03:39.833666 WR_PST = 0x0
3917 11:03:39.837148 DBI_WR = 0x0
3918 11:03:39.837277 DBI_RD = 0x0
3919 11:03:39.840043 OTF = 0x1
3920 11:03:39.843761 ===================================
3921 11:03:39.846996 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3922 11:03:39.850257 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3923 11:03:39.856564 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3924 11:03:39.860314 ===================================
3925 11:03:39.860436 LPDDR4 DRAM CONFIGURATION
3926 11:03:39.863525 ===================================
3927 11:03:39.866582 EX_ROW_EN[0] = 0x10
3928 11:03:39.869543 EX_ROW_EN[1] = 0x0
3929 11:03:39.869622 LP4Y_EN = 0x0
3930 11:03:39.873406 WORK_FSP = 0x0
3931 11:03:39.873481 WL = 0x2
3932 11:03:39.876642 RL = 0x2
3933 11:03:39.876746 BL = 0x2
3934 11:03:39.879620 RPST = 0x0
3935 11:03:39.879733 RD_PRE = 0x0
3936 11:03:39.883014 WR_PRE = 0x1
3937 11:03:39.883121 WR_PST = 0x0
3938 11:03:39.886718 DBI_WR = 0x0
3939 11:03:39.886820 DBI_RD = 0x0
3940 11:03:39.889762 OTF = 0x1
3941 11:03:39.893040 ===================================
3942 11:03:39.899812 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3943 11:03:39.902987 nWR fixed to 30
3944 11:03:39.903110 [ModeRegInit_LP4] CH0 RK0
3945 11:03:39.906174 [ModeRegInit_LP4] CH0 RK1
3946 11:03:39.909963 [ModeRegInit_LP4] CH1 RK0
3947 11:03:39.910085 [ModeRegInit_LP4] CH1 RK1
3948 11:03:39.912979 match AC timing 17
3949 11:03:39.916331 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3950 11:03:39.919770 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3951 11:03:39.926249 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3952 11:03:39.929479 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3953 11:03:39.936527 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3954 11:03:39.936645 ==
3955 11:03:39.939324 Dram Type= 6, Freq= 0, CH_0, rank 0
3956 11:03:39.942862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3957 11:03:39.942942 ==
3958 11:03:39.949307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3959 11:03:39.956060 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3960 11:03:39.959600 [CA 0] Center 35 (5~66) winsize 62
3961 11:03:39.962473 [CA 1] Center 35 (5~66) winsize 62
3962 11:03:39.965645 [CA 2] Center 33 (3~64) winsize 62
3963 11:03:39.969175 [CA 3] Center 33 (2~64) winsize 63
3964 11:03:39.972269 [CA 4] Center 33 (2~64) winsize 63
3965 11:03:39.976281 [CA 5] Center 32 (2~63) winsize 62
3966 11:03:39.976385
3967 11:03:39.978930 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3968 11:03:39.978999
3969 11:03:39.982811 [CATrainingPosCal] consider 1 rank data
3970 11:03:39.985962 u2DelayCellTimex100 = 270/100 ps
3971 11:03:39.988946 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3972 11:03:39.992536 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3973 11:03:39.995518 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3974 11:03:39.999520 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3975 11:03:40.002605 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3976 11:03:40.005741 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3977 11:03:40.005836
3978 11:03:40.012478 CA PerBit enable=1, Macro0, CA PI delay=32
3979 11:03:40.012560
3980 11:03:40.012626 [CBTSetCACLKResult] CA Dly = 32
3981 11:03:40.015480 CS Dly: 4 (0~35)
3982 11:03:40.015551 ==
3983 11:03:40.018768 Dram Type= 6, Freq= 0, CH_0, rank 1
3984 11:03:40.022562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3985 11:03:40.022642 ==
3986 11:03:40.029011 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3987 11:03:40.035694 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3988 11:03:40.039137 [CA 0] Center 35 (5~66) winsize 62
3989 11:03:40.042176 [CA 1] Center 35 (5~66) winsize 62
3990 11:03:40.045559 [CA 2] Center 33 (3~64) winsize 62
3991 11:03:40.048619 [CA 3] Center 33 (3~64) winsize 62
3992 11:03:40.052449 [CA 4] Center 32 (2~63) winsize 62
3993 11:03:40.055958 [CA 5] Center 32 (2~63) winsize 62
3994 11:03:40.056036
3995 11:03:40.058848 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3996 11:03:40.058919
3997 11:03:40.062238 [CATrainingPosCal] consider 2 rank data
3998 11:03:40.065296 u2DelayCellTimex100 = 270/100 ps
3999 11:03:40.069082 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4000 11:03:40.071878 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4001 11:03:40.075523 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4002 11:03:40.078891 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4003 11:03:40.082116 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4004 11:03:40.085479 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4005 11:03:40.089080
4006 11:03:40.092450 CA PerBit enable=1, Macro0, CA PI delay=32
4007 11:03:40.092536
4008 11:03:40.095477 [CBTSetCACLKResult] CA Dly = 32
4009 11:03:40.095554 CS Dly: 4 (0~36)
4010 11:03:40.095612
4011 11:03:40.098416 ----->DramcWriteLeveling(PI) begin...
4012 11:03:40.098494 ==
4013 11:03:40.101704 Dram Type= 6, Freq= 0, CH_0, rank 0
4014 11:03:40.105669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4015 11:03:40.105792 ==
4016 11:03:40.108797 Write leveling (Byte 0): 35 => 35
4017 11:03:40.112204 Write leveling (Byte 1): 32 => 32
4018 11:03:40.115513 DramcWriteLeveling(PI) end<-----
4019 11:03:40.115609
4020 11:03:40.115667 ==
4021 11:03:40.118294 Dram Type= 6, Freq= 0, CH_0, rank 0
4022 11:03:40.125272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4023 11:03:40.125379 ==
4024 11:03:40.125438 [Gating] SW mode calibration
4025 11:03:40.135333 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4026 11:03:40.138322 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4027 11:03:40.141944 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4028 11:03:40.148533 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4029 11:03:40.151831 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4030 11:03:40.155407 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
4031 11:03:40.161917 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4032 11:03:40.165027 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 11:03:40.168789 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 11:03:40.175324 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 11:03:40.178995 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 11:03:40.181919 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 11:03:40.188265 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 11:03:40.192123 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
4039 11:03:40.195457 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4040 11:03:40.201878 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 11:03:40.205099 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 11:03:40.208567 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 11:03:40.215082 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 11:03:40.218029 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 11:03:40.222069 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4046 11:03:40.228052 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 11:03:40.231355 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4048 11:03:40.234555 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 11:03:40.241350 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 11:03:40.245067 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 11:03:40.248131 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 11:03:40.251767 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 11:03:40.257971 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 11:03:40.261672 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 11:03:40.264883 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 11:03:40.271348 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 11:03:40.275072 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 11:03:40.278356 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 11:03:40.284627 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 11:03:40.288213 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 11:03:40.291357 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 11:03:40.297866 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4063 11:03:40.301853 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 11:03:40.305043 Total UI for P1: 0, mck2ui 16
4065 11:03:40.307811 best dqsien dly found for B0: ( 0, 13, 12)
4066 11:03:40.311710 Total UI for P1: 0, mck2ui 16
4067 11:03:40.314948 best dqsien dly found for B1: ( 0, 13, 14)
4068 11:03:40.318321 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4069 11:03:40.321554 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4070 11:03:40.321639
4071 11:03:40.324506 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4072 11:03:40.328529 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4073 11:03:40.331018 [Gating] SW calibration Done
4074 11:03:40.331100 ==
4075 11:03:40.334454 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 11:03:40.337848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 11:03:40.341085 ==
4078 11:03:40.341165 RX Vref Scan: 0
4079 11:03:40.341226
4080 11:03:40.344416 RX Vref 0 -> 0, step: 1
4081 11:03:40.344495
4082 11:03:40.347985 RX Delay -230 -> 252, step: 16
4083 11:03:40.351137 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4084 11:03:40.354718 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4085 11:03:40.357774 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4086 11:03:40.364558 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4087 11:03:40.367992 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4088 11:03:40.371267 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4089 11:03:40.374303 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4090 11:03:40.378453 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4091 11:03:40.384714 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4092 11:03:40.388014 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4093 11:03:40.390830 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4094 11:03:40.394879 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4095 11:03:40.400973 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4096 11:03:40.404304 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4097 11:03:40.408013 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4098 11:03:40.411119 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4099 11:03:40.411203 ==
4100 11:03:40.414272 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 11:03:40.420974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 11:03:40.421066 ==
4103 11:03:40.421129 DQS Delay:
4104 11:03:40.424615 DQS0 = 0, DQS1 = 0
4105 11:03:40.424697 DQM Delay:
4106 11:03:40.424757 DQM0 = 51, DQM1 = 45
4107 11:03:40.427678 DQ Delay:
4108 11:03:40.431031 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4109 11:03:40.434833 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4110 11:03:40.437812 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4111 11:03:40.440852 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4112 11:03:40.440934
4113 11:03:40.440995
4114 11:03:40.441049 ==
4115 11:03:40.444231 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 11:03:40.447610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 11:03:40.447694 ==
4118 11:03:40.447756
4119 11:03:40.447811
4120 11:03:40.451114 TX Vref Scan disable
4121 11:03:40.451199 == TX Byte 0 ==
4122 11:03:40.457586 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4123 11:03:40.460808 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4124 11:03:40.460896 == TX Byte 1 ==
4125 11:03:40.467481 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4126 11:03:40.471120 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4127 11:03:40.471236 ==
4128 11:03:40.474499 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 11:03:40.477559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 11:03:40.477671 ==
4131 11:03:40.477766
4132 11:03:40.481038
4133 11:03:40.481132 TX Vref Scan disable
4134 11:03:40.484597 == TX Byte 0 ==
4135 11:03:40.487751 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4136 11:03:40.494373 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4137 11:03:40.494471 == TX Byte 1 ==
4138 11:03:40.498027 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4139 11:03:40.504416 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4140 11:03:40.504530
4141 11:03:40.504620 [DATLAT]
4142 11:03:40.504704 Freq=600, CH0 RK0
4143 11:03:40.504787
4144 11:03:40.507750 DATLAT Default: 0x9
4145 11:03:40.507841 0, 0xFFFF, sum = 0
4146 11:03:40.511299 1, 0xFFFF, sum = 0
4147 11:03:40.511396 2, 0xFFFF, sum = 0
4148 11:03:40.514168 3, 0xFFFF, sum = 0
4149 11:03:40.517294 4, 0xFFFF, sum = 0
4150 11:03:40.517369 5, 0xFFFF, sum = 0
4151 11:03:40.521100 6, 0xFFFF, sum = 0
4152 11:03:40.521172 7, 0xFFFF, sum = 0
4153 11:03:40.524093 8, 0x0, sum = 1
4154 11:03:40.524162 9, 0x0, sum = 2
4155 11:03:40.524222 10, 0x0, sum = 3
4156 11:03:40.527307 11, 0x0, sum = 4
4157 11:03:40.527373 best_step = 9
4158 11:03:40.527429
4159 11:03:40.527482 ==
4160 11:03:40.530711 Dram Type= 6, Freq= 0, CH_0, rank 0
4161 11:03:40.537758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 11:03:40.537871 ==
4163 11:03:40.537960 RX Vref Scan: 1
4164 11:03:40.538052
4165 11:03:40.540776 RX Vref 0 -> 0, step: 1
4166 11:03:40.540867
4167 11:03:40.544465 RX Delay -163 -> 252, step: 8
4168 11:03:40.544560
4169 11:03:40.547775 Set Vref, RX VrefLevel [Byte0]: 53
4170 11:03:40.550901 [Byte1]: 49
4171 11:03:40.551002
4172 11:03:40.554084 Final RX Vref Byte 0 = 53 to rank0
4173 11:03:40.557384 Final RX Vref Byte 1 = 49 to rank0
4174 11:03:40.560521 Final RX Vref Byte 0 = 53 to rank1
4175 11:03:40.564159 Final RX Vref Byte 1 = 49 to rank1==
4176 11:03:40.567621 Dram Type= 6, Freq= 0, CH_0, rank 0
4177 11:03:40.570576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 11:03:40.570687 ==
4179 11:03:40.573817 DQS Delay:
4180 11:03:40.573913 DQS0 = 0, DQS1 = 0
4181 11:03:40.574000 DQM Delay:
4182 11:03:40.577111 DQM0 = 52, DQM1 = 45
4183 11:03:40.577196 DQ Delay:
4184 11:03:40.580603 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4185 11:03:40.584453 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =56
4186 11:03:40.587223 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =36
4187 11:03:40.590890 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4188 11:03:40.590991
4189 11:03:40.591087
4190 11:03:40.600813 [DQSOSCAuto] RK0, (LSB)MR18= 0x776a, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 387 ps
4191 11:03:40.603928 CH0 RK0: MR19=808, MR18=776A
4192 11:03:40.607158 CH0_RK0: MR19=0x808, MR18=0x776A, DQSOSC=387, MR23=63, INC=175, DEC=116
4193 11:03:40.607236
4194 11:03:40.610938 ----->DramcWriteLeveling(PI) begin...
4195 11:03:40.613795 ==
4196 11:03:40.617326 Dram Type= 6, Freq= 0, CH_0, rank 1
4197 11:03:40.620494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 11:03:40.620602 ==
4199 11:03:40.624163 Write leveling (Byte 0): 35 => 35
4200 11:03:40.627132 Write leveling (Byte 1): 31 => 31
4201 11:03:40.630798 DramcWriteLeveling(PI) end<-----
4202 11:03:40.630878
4203 11:03:40.630952 ==
4204 11:03:40.634431 Dram Type= 6, Freq= 0, CH_0, rank 1
4205 11:03:40.637297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4206 11:03:40.637402 ==
4207 11:03:40.640535 [Gating] SW mode calibration
4208 11:03:40.647048 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4209 11:03:40.653653 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4210 11:03:40.656989 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4211 11:03:40.660321 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4212 11:03:40.664018 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4213 11:03:40.670860 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4214 11:03:40.674021 0 9 16 | B1->B0 | 2b2b 2727 | 1 0 | (1 1) (0 0)
4215 11:03:40.676967 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 11:03:40.683981 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 11:03:40.687249 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 11:03:40.690617 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 11:03:40.697368 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 11:03:40.700503 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 11:03:40.704245 0 10 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4222 11:03:40.710272 0 10 16 | B1->B0 | 3d3d 4343 | 1 0 | (0 0) (0 0)
4223 11:03:40.713568 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 11:03:40.717199 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 11:03:40.724005 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 11:03:40.727169 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 11:03:40.730250 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 11:03:40.737133 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4229 11:03:40.740155 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4230 11:03:40.743344 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4231 11:03:40.750431 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 11:03:40.753299 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 11:03:40.757574 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 11:03:40.763379 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 11:03:40.767002 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 11:03:40.770315 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 11:03:40.776954 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 11:03:40.780186 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 11:03:40.783240 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 11:03:40.789665 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 11:03:40.792967 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 11:03:40.796280 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 11:03:40.802766 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 11:03:40.806575 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 11:03:40.809608 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4246 11:03:40.816512 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 11:03:40.816628 Total UI for P1: 0, mck2ui 16
4248 11:03:40.823138 best dqsien dly found for B0: ( 0, 13, 12)
4249 11:03:40.823245 Total UI for P1: 0, mck2ui 16
4250 11:03:40.826272 best dqsien dly found for B1: ( 0, 13, 14)
4251 11:03:40.832678 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4252 11:03:40.836586 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4253 11:03:40.836673
4254 11:03:40.839654 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4255 11:03:40.843167 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4256 11:03:40.846031 [Gating] SW calibration Done
4257 11:03:40.846119 ==
4258 11:03:40.849675 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 11:03:40.852664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 11:03:40.852798 ==
4261 11:03:40.855982 RX Vref Scan: 0
4262 11:03:40.856063
4263 11:03:40.856124 RX Vref 0 -> 0, step: 1
4264 11:03:40.856178
4265 11:03:40.859413 RX Delay -230 -> 252, step: 16
4266 11:03:40.863068 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4267 11:03:40.869752 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4268 11:03:40.872979 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4269 11:03:40.876267 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4270 11:03:40.879446 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4271 11:03:40.886597 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4272 11:03:40.889057 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4273 11:03:40.892510 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4274 11:03:40.896463 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4275 11:03:40.899432 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4276 11:03:40.906017 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4277 11:03:40.909771 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4278 11:03:40.912694 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4279 11:03:40.915831 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4280 11:03:40.922533 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4281 11:03:40.926264 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4282 11:03:40.926417 ==
4283 11:03:40.929294 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 11:03:40.932438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 11:03:40.932524 ==
4286 11:03:40.936422 DQS Delay:
4287 11:03:40.936557 DQS0 = 0, DQS1 = 0
4288 11:03:40.936625 DQM Delay:
4289 11:03:40.939634 DQM0 = 52, DQM1 = 42
4290 11:03:40.939709 DQ Delay:
4291 11:03:40.942689 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4292 11:03:40.945917 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4293 11:03:40.949435 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =33
4294 11:03:40.952515 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4295 11:03:40.952654
4296 11:03:40.952743
4297 11:03:40.952831 ==
4298 11:03:40.955684 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 11:03:40.962270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 11:03:40.962379 ==
4301 11:03:40.962466
4302 11:03:40.962537
4303 11:03:40.962591 TX Vref Scan disable
4304 11:03:40.966303 == TX Byte 0 ==
4305 11:03:40.969401 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4306 11:03:40.972530 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4307 11:03:40.976366 == TX Byte 1 ==
4308 11:03:40.979687 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4309 11:03:40.982774 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4310 11:03:40.986717 ==
4311 11:03:40.989777 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 11:03:40.992975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 11:03:40.993050 ==
4314 11:03:40.993108
4315 11:03:40.993161
4316 11:03:40.996068 TX Vref Scan disable
4317 11:03:40.996159 == TX Byte 0 ==
4318 11:03:41.002468 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4319 11:03:41.005949 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4320 11:03:41.009642 == TX Byte 1 ==
4321 11:03:41.012669 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4322 11:03:41.015864 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4323 11:03:41.015940
4324 11:03:41.015997 [DATLAT]
4325 11:03:41.019595 Freq=600, CH0 RK1
4326 11:03:41.019670
4327 11:03:41.019728 DATLAT Default: 0x9
4328 11:03:41.022561 0, 0xFFFF, sum = 0
4329 11:03:41.022656 1, 0xFFFF, sum = 0
4330 11:03:41.026314 2, 0xFFFF, sum = 0
4331 11:03:41.029555 3, 0xFFFF, sum = 0
4332 11:03:41.029633 4, 0xFFFF, sum = 0
4333 11:03:41.032444 5, 0xFFFF, sum = 0
4334 11:03:41.032523 6, 0xFFFF, sum = 0
4335 11:03:41.035949 7, 0xFFFF, sum = 0
4336 11:03:41.036027 8, 0x0, sum = 1
4337 11:03:41.036087 9, 0x0, sum = 2
4338 11:03:41.039376 10, 0x0, sum = 3
4339 11:03:41.039457 11, 0x0, sum = 4
4340 11:03:41.042337 best_step = 9
4341 11:03:41.042412
4342 11:03:41.042471 ==
4343 11:03:41.045778 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 11:03:41.049526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 11:03:41.049604 ==
4346 11:03:41.052608 RX Vref Scan: 0
4347 11:03:41.052678
4348 11:03:41.052748 RX Vref 0 -> 0, step: 1
4349 11:03:41.052806
4350 11:03:41.055982 RX Delay -179 -> 252, step: 8
4351 11:03:41.063514 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4352 11:03:41.066565 iDelay=197, Bit 1, Center 52 (-91 ~ 196) 288
4353 11:03:41.069979 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4354 11:03:41.073024 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4355 11:03:41.076677 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4356 11:03:41.083250 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4357 11:03:41.086399 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4358 11:03:41.090345 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4359 11:03:41.092816 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4360 11:03:41.096598 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4361 11:03:41.102980 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4362 11:03:41.106167 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4363 11:03:41.109840 iDelay=197, Bit 12, Center 48 (-91 ~ 188) 280
4364 11:03:41.112883 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4365 11:03:41.119511 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4366 11:03:41.123353 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4367 11:03:41.123429 ==
4368 11:03:41.126320 Dram Type= 6, Freq= 0, CH_0, rank 1
4369 11:03:41.129442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 11:03:41.129519 ==
4371 11:03:41.132822 DQS Delay:
4372 11:03:41.132898 DQS0 = 0, DQS1 = 0
4373 11:03:41.132960 DQM Delay:
4374 11:03:41.135942 DQM0 = 52, DQM1 = 46
4375 11:03:41.136018 DQ Delay:
4376 11:03:41.139366 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4377 11:03:41.142630 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =56
4378 11:03:41.145976 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4379 11:03:41.149317 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4380 11:03:41.149393
4381 11:03:41.149484
4382 11:03:41.159363 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b2b, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 389 ps
4383 11:03:41.159450 CH0 RK1: MR19=808, MR18=6B2B
4384 11:03:41.166245 CH0_RK1: MR19=0x808, MR18=0x6B2B, DQSOSC=389, MR23=63, INC=173, DEC=115
4385 11:03:41.169445 [RxdqsGatingPostProcess] freq 600
4386 11:03:41.176480 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4387 11:03:41.179596 Pre-setting of DQS Precalculation
4388 11:03:41.183138 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4389 11:03:41.183218 ==
4390 11:03:41.186445 Dram Type= 6, Freq= 0, CH_1, rank 0
4391 11:03:41.189627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 11:03:41.192827 ==
4393 11:03:41.196626 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4394 11:03:41.203141 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4395 11:03:41.206354 [CA 0] Center 36 (5~67) winsize 63
4396 11:03:41.209706 [CA 1] Center 36 (5~67) winsize 63
4397 11:03:41.213347 [CA 2] Center 34 (4~65) winsize 62
4398 11:03:41.216192 [CA 3] Center 34 (4~65) winsize 62
4399 11:03:41.219376 [CA 4] Center 34 (4~65) winsize 62
4400 11:03:41.223276 [CA 5] Center 33 (3~64) winsize 62
4401 11:03:41.223352
4402 11:03:41.226631 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4403 11:03:41.226764
4404 11:03:41.229756 [CATrainingPosCal] consider 1 rank data
4405 11:03:41.232694 u2DelayCellTimex100 = 270/100 ps
4406 11:03:41.236525 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4407 11:03:41.239279 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4408 11:03:41.242596 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4409 11:03:41.246218 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4410 11:03:41.252530 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4411 11:03:41.255867 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4412 11:03:41.255964
4413 11:03:41.259409 CA PerBit enable=1, Macro0, CA PI delay=33
4414 11:03:41.259508
4415 11:03:41.262608 [CBTSetCACLKResult] CA Dly = 33
4416 11:03:41.262705 CS Dly: 5 (0~36)
4417 11:03:41.262788 ==
4418 11:03:41.266254 Dram Type= 6, Freq= 0, CH_1, rank 1
4419 11:03:41.269324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 11:03:41.272744 ==
4421 11:03:41.276098 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4422 11:03:41.282496 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4423 11:03:41.286229 [CA 0] Center 36 (6~67) winsize 62
4424 11:03:41.289733 [CA 1] Center 36 (6~67) winsize 62
4425 11:03:41.292459 [CA 2] Center 35 (4~66) winsize 63
4426 11:03:41.296251 [CA 3] Center 35 (4~66) winsize 63
4427 11:03:41.299709 [CA 4] Center 35 (4~66) winsize 63
4428 11:03:41.302784 [CA 5] Center 34 (4~65) winsize 62
4429 11:03:41.302882
4430 11:03:41.305969 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4431 11:03:41.306100
4432 11:03:41.309345 [CATrainingPosCal] consider 2 rank data
4433 11:03:41.312426 u2DelayCellTimex100 = 270/100 ps
4434 11:03:41.316331 CA0 delay=36 (6~67),Diff = 2 PI (19 cell)
4435 11:03:41.319344 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4436 11:03:41.322981 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4437 11:03:41.325923 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4438 11:03:41.332836 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4439 11:03:41.335892 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4440 11:03:41.335989
4441 11:03:41.339092 CA PerBit enable=1, Macro0, CA PI delay=34
4442 11:03:41.339188
4443 11:03:41.342789 [CBTSetCACLKResult] CA Dly = 34
4444 11:03:41.342885 CS Dly: 6 (0~38)
4445 11:03:41.342968
4446 11:03:41.346072 ----->DramcWriteLeveling(PI) begin...
4447 11:03:41.346171 ==
4448 11:03:41.349120 Dram Type= 6, Freq= 0, CH_1, rank 0
4449 11:03:41.356000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4450 11:03:41.356128 ==
4451 11:03:41.359585 Write leveling (Byte 0): 31 => 31
4452 11:03:41.362747 Write leveling (Byte 1): 32 => 32
4453 11:03:41.362844 DramcWriteLeveling(PI) end<-----
4454 11:03:41.362929
4455 11:03:41.366201 ==
4456 11:03:41.369755 Dram Type= 6, Freq= 0, CH_1, rank 0
4457 11:03:41.372589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 11:03:41.372689 ==
4459 11:03:41.375980 [Gating] SW mode calibration
4460 11:03:41.383195 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4461 11:03:41.386125 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4462 11:03:41.392620 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4463 11:03:41.396008 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4464 11:03:41.399692 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4465 11:03:41.406096 0 9 12 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (0 0)
4466 11:03:41.408950 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 11:03:41.412696 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 11:03:41.419573 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 11:03:41.422921 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 11:03:41.425831 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 11:03:41.432677 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 11:03:41.435703 0 10 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
4473 11:03:41.438865 0 10 12 | B1->B0 | 3333 3b3b | 0 0 | (0 0) (0 0)
4474 11:03:41.442516 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 11:03:41.449561 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 11:03:41.452868 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 11:03:41.455584 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 11:03:41.462948 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 11:03:41.465977 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 11:03:41.469113 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 11:03:41.475576 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4482 11:03:41.479101 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 11:03:41.482485 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 11:03:41.488821 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 11:03:41.492530 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 11:03:41.495847 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 11:03:41.502269 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 11:03:41.505333 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 11:03:41.509085 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 11:03:41.516094 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 11:03:41.518601 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 11:03:41.522133 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 11:03:41.528560 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 11:03:41.532007 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 11:03:41.535449 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 11:03:41.541882 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4497 11:03:41.545716 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4498 11:03:41.548910 Total UI for P1: 0, mck2ui 16
4499 11:03:41.551847 best dqsien dly found for B0: ( 0, 13, 10)
4500 11:03:41.555555 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 11:03:41.558673 Total UI for P1: 0, mck2ui 16
4502 11:03:41.562546 best dqsien dly found for B1: ( 0, 13, 10)
4503 11:03:41.565662 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4504 11:03:41.568587 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4505 11:03:41.568687
4506 11:03:41.575625 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4507 11:03:41.578854 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4508 11:03:41.578957 [Gating] SW calibration Done
4509 11:03:41.579046 ==
4510 11:03:41.582131 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 11:03:41.588648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 11:03:41.588743 ==
4513 11:03:41.588822 RX Vref Scan: 0
4514 11:03:41.588899
4515 11:03:41.592296 RX Vref 0 -> 0, step: 1
4516 11:03:41.592390
4517 11:03:41.595477 RX Delay -230 -> 252, step: 16
4518 11:03:41.598468 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4519 11:03:41.601911 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4520 11:03:41.608452 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4521 11:03:41.612180 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4522 11:03:41.615325 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4523 11:03:41.618245 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4524 11:03:41.621775 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4525 11:03:41.628754 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4526 11:03:41.631776 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4527 11:03:41.634908 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4528 11:03:41.638254 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4529 11:03:41.645326 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4530 11:03:41.648266 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4531 11:03:41.651825 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4532 11:03:41.655267 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4533 11:03:41.661658 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4534 11:03:41.661769 ==
4535 11:03:41.665304 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 11:03:41.669004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 11:03:41.669110 ==
4538 11:03:41.669199 DQS Delay:
4539 11:03:41.671741 DQS0 = 0, DQS1 = 0
4540 11:03:41.671841 DQM Delay:
4541 11:03:41.674823 DQM0 = 52, DQM1 = 47
4542 11:03:41.674924 DQ Delay:
4543 11:03:41.678442 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4544 11:03:41.681547 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4545 11:03:41.685182 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =49
4546 11:03:41.688196 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4547 11:03:41.688299
4548 11:03:41.688394
4549 11:03:41.688471 ==
4550 11:03:41.692036 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 11:03:41.694918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 11:03:41.695019 ==
4553 11:03:41.695112
4554 11:03:41.695204
4555 11:03:41.698055 TX Vref Scan disable
4556 11:03:41.701576 == TX Byte 0 ==
4557 11:03:41.704985 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4558 11:03:41.708094 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4559 11:03:41.711405 == TX Byte 1 ==
4560 11:03:41.714697 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4561 11:03:41.717979 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4562 11:03:41.718068 ==
4563 11:03:41.721526 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 11:03:41.728709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 11:03:41.728791 ==
4566 11:03:41.728865
4567 11:03:41.728931
4568 11:03:41.728981 TX Vref Scan disable
4569 11:03:41.732297 == TX Byte 0 ==
4570 11:03:41.735965 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4571 11:03:41.742175 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4572 11:03:41.742278 == TX Byte 1 ==
4573 11:03:41.745972 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4574 11:03:41.749584 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4575 11:03:41.752986
4576 11:03:41.753064 [DATLAT]
4577 11:03:41.753123 Freq=600, CH1 RK0
4578 11:03:41.753176
4579 11:03:41.755538 DATLAT Default: 0x9
4580 11:03:41.755636 0, 0xFFFF, sum = 0
4581 11:03:41.759080 1, 0xFFFF, sum = 0
4582 11:03:41.759196 2, 0xFFFF, sum = 0
4583 11:03:41.762536 3, 0xFFFF, sum = 0
4584 11:03:41.762628 4, 0xFFFF, sum = 0
4585 11:03:41.765888 5, 0xFFFF, sum = 0
4586 11:03:41.769399 6, 0xFFFF, sum = 0
4587 11:03:41.769479 7, 0xFFFF, sum = 0
4588 11:03:41.769556 8, 0x0, sum = 1
4589 11:03:41.772451 9, 0x0, sum = 2
4590 11:03:41.772532 10, 0x0, sum = 3
4591 11:03:41.775798 11, 0x0, sum = 4
4592 11:03:41.775877 best_step = 9
4593 11:03:41.775953
4594 11:03:41.776023 ==
4595 11:03:41.779311 Dram Type= 6, Freq= 0, CH_1, rank 0
4596 11:03:41.785594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 11:03:41.785678 ==
4598 11:03:41.785755 RX Vref Scan: 1
4599 11:03:41.785827
4600 11:03:41.788838 RX Vref 0 -> 0, step: 1
4601 11:03:41.788917
4602 11:03:41.792241 RX Delay -163 -> 252, step: 8
4603 11:03:41.792320
4604 11:03:41.795477 Set Vref, RX VrefLevel [Byte0]: 53
4605 11:03:41.798722 [Byte1]: 52
4606 11:03:41.798801
4607 11:03:41.802256 Final RX Vref Byte 0 = 53 to rank0
4608 11:03:41.805361 Final RX Vref Byte 1 = 52 to rank0
4609 11:03:41.809059 Final RX Vref Byte 0 = 53 to rank1
4610 11:03:41.812524 Final RX Vref Byte 1 = 52 to rank1==
4611 11:03:41.815616 Dram Type= 6, Freq= 0, CH_1, rank 0
4612 11:03:41.818633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 11:03:41.818716 ==
4614 11:03:41.822204 DQS Delay:
4615 11:03:41.822284 DQS0 = 0, DQS1 = 0
4616 11:03:41.825238 DQM Delay:
4617 11:03:41.825316 DQM0 = 48, DQM1 = 45
4618 11:03:41.825393 DQ Delay:
4619 11:03:41.828488 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4620 11:03:41.832506 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4621 11:03:41.835492 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4622 11:03:41.839011 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4623 11:03:41.839085
4624 11:03:41.839150
4625 11:03:41.848658 [DQSOSCAuto] RK0, (LSB)MR18= 0x5479, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
4626 11:03:41.851971 CH1 RK0: MR19=808, MR18=5479
4627 11:03:41.855578 CH1_RK0: MR19=0x808, MR18=0x5479, DQSOSC=387, MR23=63, INC=175, DEC=116
4628 11:03:41.855673
4629 11:03:41.861918 ----->DramcWriteLeveling(PI) begin...
4630 11:03:41.862047 ==
4631 11:03:41.865084 Dram Type= 6, Freq= 0, CH_1, rank 1
4632 11:03:41.868426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4633 11:03:41.868519 ==
4634 11:03:41.872144 Write leveling (Byte 0): 30 => 30
4635 11:03:41.874980 Write leveling (Byte 1): 30 => 30
4636 11:03:41.878856 DramcWriteLeveling(PI) end<-----
4637 11:03:41.878949
4638 11:03:41.879055 ==
4639 11:03:41.881889 Dram Type= 6, Freq= 0, CH_1, rank 1
4640 11:03:41.885144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 11:03:41.885245 ==
4642 11:03:41.888542 [Gating] SW mode calibration
4643 11:03:41.894953 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4644 11:03:41.902289 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4645 11:03:41.905570 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4646 11:03:41.908286 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4647 11:03:41.912226 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
4648 11:03:41.918743 0 9 12 | B1->B0 | 2d2d 2f2f | 1 1 | (0 0) (1 1)
4649 11:03:41.922003 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4650 11:03:41.925121 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 11:03:41.931546 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 11:03:41.935349 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 11:03:41.938446 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 11:03:41.945205 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 11:03:41.948297 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4656 11:03:41.951791 0 10 12 | B1->B0 | 3939 3535 | 1 0 | (0 0) (0 0)
4657 11:03:41.958440 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 11:03:41.961722 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 11:03:41.965363 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 11:03:41.971408 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 11:03:41.974620 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 11:03:41.978133 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 11:03:41.985185 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 11:03:41.988156 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4665 11:03:41.991852 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 11:03:41.998154 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 11:03:42.001376 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 11:03:42.004546 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 11:03:42.011847 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 11:03:42.015056 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 11:03:42.018174 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 11:03:42.024888 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 11:03:42.027946 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 11:03:42.031554 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 11:03:42.038116 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 11:03:42.041315 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 11:03:42.044866 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 11:03:42.048017 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 11:03:42.054464 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 11:03:42.058358 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 11:03:42.061400 Total UI for P1: 0, mck2ui 16
4682 11:03:42.064740 best dqsien dly found for B0: ( 0, 13, 10)
4683 11:03:42.068182 Total UI for P1: 0, mck2ui 16
4684 11:03:42.071829 best dqsien dly found for B1: ( 0, 13, 10)
4685 11:03:42.075064 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4686 11:03:42.078154 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4687 11:03:42.078223
4688 11:03:42.081020 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4689 11:03:42.088506 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4690 11:03:42.088587 [Gating] SW calibration Done
4691 11:03:42.088646 ==
4692 11:03:42.091798 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 11:03:42.098120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 11:03:42.098210 ==
4695 11:03:42.098271 RX Vref Scan: 0
4696 11:03:42.098330
4697 11:03:42.101799 RX Vref 0 -> 0, step: 1
4698 11:03:42.101876
4699 11:03:42.104622 RX Delay -230 -> 252, step: 16
4700 11:03:42.108091 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4701 11:03:42.111303 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4702 11:03:42.114475 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4703 11:03:42.121208 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4704 11:03:42.124998 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4705 11:03:42.128094 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4706 11:03:42.131430 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4707 11:03:42.134560 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4708 11:03:42.141116 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4709 11:03:42.144898 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4710 11:03:42.147831 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4711 11:03:42.151210 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4712 11:03:42.157710 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4713 11:03:42.161118 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4714 11:03:42.164791 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4715 11:03:42.167832 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4716 11:03:42.167904 ==
4717 11:03:42.171056 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 11:03:42.177894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 11:03:42.177994 ==
4720 11:03:42.178125 DQS Delay:
4721 11:03:42.181236 DQS0 = 0, DQS1 = 0
4722 11:03:42.181323 DQM Delay:
4723 11:03:42.181403 DQM0 = 51, DQM1 = 49
4724 11:03:42.184861 DQ Delay:
4725 11:03:42.187826 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4726 11:03:42.191311 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4727 11:03:42.194935 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =49
4728 11:03:42.198315 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4729 11:03:42.198415
4730 11:03:42.198506
4731 11:03:42.198587 ==
4732 11:03:42.201697 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 11:03:42.204656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 11:03:42.204765 ==
4735 11:03:42.204850
4736 11:03:42.204933
4737 11:03:42.208035 TX Vref Scan disable
4738 11:03:42.208132 == TX Byte 0 ==
4739 11:03:42.214613 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4740 11:03:42.217755 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4741 11:03:42.217852 == TX Byte 1 ==
4742 11:03:42.224325 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4743 11:03:42.227963 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4744 11:03:42.228063 ==
4745 11:03:42.231259 Dram Type= 6, Freq= 0, CH_1, rank 1
4746 11:03:42.234358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4747 11:03:42.234463 ==
4748 11:03:42.234548
4749 11:03:42.237712
4750 11:03:42.237808 TX Vref Scan disable
4751 11:03:42.241157 == TX Byte 0 ==
4752 11:03:42.244543 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4753 11:03:42.247829 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4754 11:03:42.251054 == TX Byte 1 ==
4755 11:03:42.254692 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4756 11:03:42.261008 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4757 11:03:42.261106
4758 11:03:42.261184 [DATLAT]
4759 11:03:42.261267 Freq=600, CH1 RK1
4760 11:03:42.261346
4761 11:03:42.264472 DATLAT Default: 0x9
4762 11:03:42.264572 0, 0xFFFF, sum = 0
4763 11:03:42.267767 1, 0xFFFF, sum = 0
4764 11:03:42.271119 2, 0xFFFF, sum = 0
4765 11:03:42.271226 3, 0xFFFF, sum = 0
4766 11:03:42.274241 4, 0xFFFF, sum = 0
4767 11:03:42.274354 5, 0xFFFF, sum = 0
4768 11:03:42.277677 6, 0xFFFF, sum = 0
4769 11:03:42.277758 7, 0xFFFF, sum = 0
4770 11:03:42.280953 8, 0x0, sum = 1
4771 11:03:42.281024 9, 0x0, sum = 2
4772 11:03:42.281082 10, 0x0, sum = 3
4773 11:03:42.284425 11, 0x0, sum = 4
4774 11:03:42.284491 best_step = 9
4775 11:03:42.284545
4776 11:03:42.284595 ==
4777 11:03:42.287656 Dram Type= 6, Freq= 0, CH_1, rank 1
4778 11:03:42.294404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4779 11:03:42.294486 ==
4780 11:03:42.294545 RX Vref Scan: 0
4781 11:03:42.294598
4782 11:03:42.297567 RX Vref 0 -> 0, step: 1
4783 11:03:42.297641
4784 11:03:42.301021 RX Delay -163 -> 252, step: 8
4785 11:03:42.304321 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4786 11:03:42.310695 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4787 11:03:42.314161 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4788 11:03:42.317519 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4789 11:03:42.320971 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4790 11:03:42.324170 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4791 11:03:42.330931 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4792 11:03:42.333812 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4793 11:03:42.337114 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4794 11:03:42.340562 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4795 11:03:42.344367 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4796 11:03:42.350395 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4797 11:03:42.353790 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4798 11:03:42.357056 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4799 11:03:42.360297 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4800 11:03:42.367423 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4801 11:03:42.367544 ==
4802 11:03:42.370529 Dram Type= 6, Freq= 0, CH_1, rank 1
4803 11:03:42.373641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4804 11:03:42.373739 ==
4805 11:03:42.373814 DQS Delay:
4806 11:03:42.377043 DQS0 = 0, DQS1 = 0
4807 11:03:42.377112 DQM Delay:
4808 11:03:42.380687 DQM0 = 49, DQM1 = 45
4809 11:03:42.380776 DQ Delay:
4810 11:03:42.384121 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4811 11:03:42.387357 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4812 11:03:42.390796 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4813 11:03:42.393814 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4814 11:03:42.393889
4815 11:03:42.393947
4816 11:03:42.400387 [DQSOSCAuto] RK1, (LSB)MR18= 0x7328, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 388 ps
4817 11:03:42.403677 CH1 RK1: MR19=808, MR18=7328
4818 11:03:42.410714 CH1_RK1: MR19=0x808, MR18=0x7328, DQSOSC=388, MR23=63, INC=174, DEC=116
4819 11:03:42.413799 [RxdqsGatingPostProcess] freq 600
4820 11:03:42.420761 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4821 11:03:42.424006 Pre-setting of DQS Precalculation
4822 11:03:42.427225 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4823 11:03:42.433622 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4824 11:03:42.440270 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4825 11:03:42.440354
4826 11:03:42.440413
4827 11:03:42.443776 [Calibration Summary] 1200 Mbps
4828 11:03:42.446849 CH 0, Rank 0
4829 11:03:42.446925 SW Impedance : PASS
4830 11:03:42.450392 DUTY Scan : NO K
4831 11:03:42.453817 ZQ Calibration : PASS
4832 11:03:42.453893 Jitter Meter : NO K
4833 11:03:42.456842 CBT Training : PASS
4834 11:03:42.460666 Write leveling : PASS
4835 11:03:42.460742 RX DQS gating : PASS
4836 11:03:42.463888 RX DQ/DQS(RDDQC) : PASS
4837 11:03:42.463977 TX DQ/DQS : PASS
4838 11:03:42.467287 RX DATLAT : PASS
4839 11:03:42.470325 RX DQ/DQS(Engine): PASS
4840 11:03:42.470400 TX OE : NO K
4841 11:03:42.473665 All Pass.
4842 11:03:42.473739
4843 11:03:42.473796 CH 0, Rank 1
4844 11:03:42.476731 SW Impedance : PASS
4845 11:03:42.476806 DUTY Scan : NO K
4846 11:03:42.480502 ZQ Calibration : PASS
4847 11:03:42.483877 Jitter Meter : NO K
4848 11:03:42.483952 CBT Training : PASS
4849 11:03:42.486829 Write leveling : PASS
4850 11:03:42.490297 RX DQS gating : PASS
4851 11:03:42.490376 RX DQ/DQS(RDDQC) : PASS
4852 11:03:42.493463 TX DQ/DQS : PASS
4853 11:03:42.496848 RX DATLAT : PASS
4854 11:03:42.496946 RX DQ/DQS(Engine): PASS
4855 11:03:42.500633 TX OE : NO K
4856 11:03:42.500711 All Pass.
4857 11:03:42.500769
4858 11:03:42.503709 CH 1, Rank 0
4859 11:03:42.503785 SW Impedance : PASS
4860 11:03:42.507225 DUTY Scan : NO K
4861 11:03:42.510438 ZQ Calibration : PASS
4862 11:03:42.510515 Jitter Meter : NO K
4863 11:03:42.513627 CBT Training : PASS
4864 11:03:42.513705 Write leveling : PASS
4865 11:03:42.516701 RX DQS gating : PASS
4866 11:03:42.520236 RX DQ/DQS(RDDQC) : PASS
4867 11:03:42.520314 TX DQ/DQS : PASS
4868 11:03:42.523396 RX DATLAT : PASS
4869 11:03:42.526768 RX DQ/DQS(Engine): PASS
4870 11:03:42.526874 TX OE : NO K
4871 11:03:42.530476 All Pass.
4872 11:03:42.530553
4873 11:03:42.530628 CH 1, Rank 1
4874 11:03:42.533267 SW Impedance : PASS
4875 11:03:42.533358 DUTY Scan : NO K
4876 11:03:42.536797 ZQ Calibration : PASS
4877 11:03:42.540493 Jitter Meter : NO K
4878 11:03:42.540569 CBT Training : PASS
4879 11:03:42.543258 Write leveling : PASS
4880 11:03:42.546929 RX DQS gating : PASS
4881 11:03:42.547006 RX DQ/DQS(RDDQC) : PASS
4882 11:03:42.550312 TX DQ/DQS : PASS
4883 11:03:42.553342 RX DATLAT : PASS
4884 11:03:42.553418 RX DQ/DQS(Engine): PASS
4885 11:03:42.557178 TX OE : NO K
4886 11:03:42.557262 All Pass.
4887 11:03:42.557345
4888 11:03:42.559948 DramC Write-DBI off
4889 11:03:42.563212 PER_BANK_REFRESH: Hybrid Mode
4890 11:03:42.563303 TX_TRACKING: ON
4891 11:03:42.573684 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4892 11:03:42.576751 [FAST_K] Save calibration result to emmc
4893 11:03:42.579902 dramc_set_vcore_voltage set vcore to 662500
4894 11:03:42.583110 Read voltage for 933, 3
4895 11:03:42.583186 Vio18 = 0
4896 11:03:42.583245 Vcore = 662500
4897 11:03:42.583298 Vdram = 0
4898 11:03:42.586694 Vddq = 0
4899 11:03:42.586771 Vmddr = 0
4900 11:03:42.593389 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4901 11:03:42.596393 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4902 11:03:42.599725 MEM_TYPE=3, freq_sel=17
4903 11:03:42.603384 sv_algorithm_assistance_LP4_1600
4904 11:03:42.606279 ============ PULL DRAM RESETB DOWN ============
4905 11:03:42.610028 ========== PULL DRAM RESETB DOWN end =========
4906 11:03:42.616372 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4907 11:03:42.619991 ===================================
4908 11:03:42.620084 LPDDR4 DRAM CONFIGURATION
4909 11:03:42.622975 ===================================
4910 11:03:42.626653 EX_ROW_EN[0] = 0x0
4911 11:03:42.630123 EX_ROW_EN[1] = 0x0
4912 11:03:42.630202 LP4Y_EN = 0x0
4913 11:03:42.632952 WORK_FSP = 0x0
4914 11:03:42.633029 WL = 0x3
4915 11:03:42.636321 RL = 0x3
4916 11:03:42.636414 BL = 0x2
4917 11:03:42.639394 RPST = 0x0
4918 11:03:42.639495 RD_PRE = 0x0
4919 11:03:42.643170 WR_PRE = 0x1
4920 11:03:42.643280 WR_PST = 0x0
4921 11:03:42.646290 DBI_WR = 0x0
4922 11:03:42.646395 DBI_RD = 0x0
4923 11:03:42.649956 OTF = 0x1
4924 11:03:42.652795 ===================================
4925 11:03:42.656132 ===================================
4926 11:03:42.656234 ANA top config
4927 11:03:42.659789 ===================================
4928 11:03:42.662827 DLL_ASYNC_EN = 0
4929 11:03:42.666199 ALL_SLAVE_EN = 1
4930 11:03:42.666280 NEW_RANK_MODE = 1
4931 11:03:42.669451 DLL_IDLE_MODE = 1
4932 11:03:42.673162 LP45_APHY_COMB_EN = 1
4933 11:03:42.676120 TX_ODT_DIS = 1
4934 11:03:42.679792 NEW_8X_MODE = 1
4935 11:03:42.682979 ===================================
4936 11:03:42.686278 ===================================
4937 11:03:42.686382 data_rate = 1866
4938 11:03:42.689505 CKR = 1
4939 11:03:42.692588 DQ_P2S_RATIO = 8
4940 11:03:42.696416 ===================================
4941 11:03:42.699437 CA_P2S_RATIO = 8
4942 11:03:42.702778 DQ_CA_OPEN = 0
4943 11:03:42.705792 DQ_SEMI_OPEN = 0
4944 11:03:42.705887 CA_SEMI_OPEN = 0
4945 11:03:42.709223 CA_FULL_RATE = 0
4946 11:03:42.712528 DQ_CKDIV4_EN = 1
4947 11:03:42.716029 CA_CKDIV4_EN = 1
4948 11:03:42.719568 CA_PREDIV_EN = 0
4949 11:03:42.722779 PH8_DLY = 0
4950 11:03:42.722875 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4951 11:03:42.726021 DQ_AAMCK_DIV = 4
4952 11:03:42.729562 CA_AAMCK_DIV = 4
4953 11:03:42.732537 CA_ADMCK_DIV = 4
4954 11:03:42.735831 DQ_TRACK_CA_EN = 0
4955 11:03:42.739651 CA_PICK = 933
4956 11:03:42.739757 CA_MCKIO = 933
4957 11:03:42.742978 MCKIO_SEMI = 0
4958 11:03:42.746235 PLL_FREQ = 3732
4959 11:03:42.749313 DQ_UI_PI_RATIO = 32
4960 11:03:42.752763 CA_UI_PI_RATIO = 0
4961 11:03:42.756437 ===================================
4962 11:03:42.759731 ===================================
4963 11:03:42.762710 memory_type:LPDDR4
4964 11:03:42.762796 GP_NUM : 10
4965 11:03:42.765853 SRAM_EN : 1
4966 11:03:42.765960 MD32_EN : 0
4967 11:03:42.769454 ===================================
4968 11:03:42.772624 [ANA_INIT] >>>>>>>>>>>>>>
4969 11:03:42.776034 <<<<<< [CONFIGURE PHASE]: ANA_TX
4970 11:03:42.779191 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4971 11:03:42.782626 ===================================
4972 11:03:42.786096 data_rate = 1866,PCW = 0X8f00
4973 11:03:42.789664 ===================================
4974 11:03:42.792653 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4975 11:03:42.799532 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4976 11:03:42.802560 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4977 11:03:42.809116 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4978 11:03:42.812305 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4979 11:03:42.816094 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4980 11:03:42.816178 [ANA_INIT] flow start
4981 11:03:42.818916 [ANA_INIT] PLL >>>>>>>>
4982 11:03:42.822423 [ANA_INIT] PLL <<<<<<<<
4983 11:03:42.822505 [ANA_INIT] MIDPI >>>>>>>>
4984 11:03:42.825633 [ANA_INIT] MIDPI <<<<<<<<
4985 11:03:42.829338 [ANA_INIT] DLL >>>>>>>>
4986 11:03:42.829421 [ANA_INIT] flow end
4987 11:03:42.835405 ============ LP4 DIFF to SE enter ============
4988 11:03:42.838843 ============ LP4 DIFF to SE exit ============
4989 11:03:42.842171 [ANA_INIT] <<<<<<<<<<<<<
4990 11:03:42.842253 [Flow] Enable top DCM control >>>>>
4991 11:03:42.846084 [Flow] Enable top DCM control <<<<<
4992 11:03:42.849437 Enable DLL master slave shuffle
4993 11:03:42.855984 ==============================================================
4994 11:03:42.859053 Gating Mode config
4995 11:03:42.862332 ==============================================================
4996 11:03:42.865392 Config description:
4997 11:03:42.875360 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4998 11:03:42.882194 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4999 11:03:42.886206 SELPH_MODE 0: By rank 1: By Phase
5000 11:03:42.892666 ==============================================================
5001 11:03:42.895751 GAT_TRACK_EN = 1
5002 11:03:42.899125 RX_GATING_MODE = 2
5003 11:03:42.899216 RX_GATING_TRACK_MODE = 2
5004 11:03:42.902074 SELPH_MODE = 1
5005 11:03:42.905773 PICG_EARLY_EN = 1
5006 11:03:42.909133 VALID_LAT_VALUE = 1
5007 11:03:42.915442 ==============================================================
5008 11:03:42.918981 Enter into Gating configuration >>>>
5009 11:03:42.922288 Exit from Gating configuration <<<<
5010 11:03:42.925441 Enter into DVFS_PRE_config >>>>>
5011 11:03:42.935270 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5012 11:03:42.939006 Exit from DVFS_PRE_config <<<<<
5013 11:03:42.942295 Enter into PICG configuration >>>>
5014 11:03:42.945313 Exit from PICG configuration <<<<
5015 11:03:42.948808 [RX_INPUT] configuration >>>>>
5016 11:03:42.951794 [RX_INPUT] configuration <<<<<
5017 11:03:42.955500 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5018 11:03:42.962328 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5019 11:03:42.968858 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5020 11:03:42.975264 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5021 11:03:42.978854 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5022 11:03:42.985924 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5023 11:03:42.989030 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5024 11:03:42.995877 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5025 11:03:42.998875 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5026 11:03:43.002392 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5027 11:03:43.005786 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5028 11:03:43.011771 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5029 11:03:43.015144 ===================================
5030 11:03:43.015246 LPDDR4 DRAM CONFIGURATION
5031 11:03:43.018375 ===================================
5032 11:03:43.021844 EX_ROW_EN[0] = 0x0
5033 11:03:43.025035 EX_ROW_EN[1] = 0x0
5034 11:03:43.025198 LP4Y_EN = 0x0
5035 11:03:43.028372 WORK_FSP = 0x0
5036 11:03:43.028505 WL = 0x3
5037 11:03:43.031378 RL = 0x3
5038 11:03:43.031477 BL = 0x2
5039 11:03:43.035087 RPST = 0x0
5040 11:03:43.035241 RD_PRE = 0x0
5041 11:03:43.038319 WR_PRE = 0x1
5042 11:03:43.038434 WR_PST = 0x0
5043 11:03:43.041801 DBI_WR = 0x0
5044 11:03:43.041903 DBI_RD = 0x0
5045 11:03:43.045240 OTF = 0x1
5046 11:03:43.048242 ===================================
5047 11:03:43.051340 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5048 11:03:43.054853 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5049 11:03:43.061532 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5050 11:03:43.064664 ===================================
5051 11:03:43.064767 LPDDR4 DRAM CONFIGURATION
5052 11:03:43.068366 ===================================
5053 11:03:43.071527 EX_ROW_EN[0] = 0x10
5054 11:03:43.074714 EX_ROW_EN[1] = 0x0
5055 11:03:43.074790 LP4Y_EN = 0x0
5056 11:03:43.078183 WORK_FSP = 0x0
5057 11:03:43.078283 WL = 0x3
5058 11:03:43.081261 RL = 0x3
5059 11:03:43.081331 BL = 0x2
5060 11:03:43.084492 RPST = 0x0
5061 11:03:43.084607 RD_PRE = 0x0
5062 11:03:43.088033 WR_PRE = 0x1
5063 11:03:43.088112 WR_PST = 0x0
5064 11:03:43.091152 DBI_WR = 0x0
5065 11:03:43.091254 DBI_RD = 0x0
5066 11:03:43.094656 OTF = 0x1
5067 11:03:43.098224 ===================================
5068 11:03:43.104782 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5069 11:03:43.108188 nWR fixed to 30
5070 11:03:43.111557 [ModeRegInit_LP4] CH0 RK0
5071 11:03:43.111732 [ModeRegInit_LP4] CH0 RK1
5072 11:03:43.114783 [ModeRegInit_LP4] CH1 RK0
5073 11:03:43.117745 [ModeRegInit_LP4] CH1 RK1
5074 11:03:43.117849 match AC timing 9
5075 11:03:43.124259 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5076 11:03:43.127485 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5077 11:03:43.130891 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5078 11:03:43.140312 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5079 11:03:43.140795 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5080 11:03:43.140889 ==
5081 11:03:43.144105 Dram Type= 6, Freq= 0, CH_0, rank 0
5082 11:03:43.147848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5083 11:03:43.147933 ==
5084 11:03:43.154212 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5085 11:03:43.160713 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5086 11:03:43.164712 [CA 0] Center 37 (6~68) winsize 63
5087 11:03:43.167334 [CA 1] Center 37 (6~68) winsize 63
5088 11:03:43.170861 [CA 2] Center 34 (4~65) winsize 62
5089 11:03:43.174221 [CA 3] Center 34 (3~65) winsize 63
5090 11:03:43.177889 [CA 4] Center 32 (2~63) winsize 62
5091 11:03:43.181083 [CA 5] Center 32 (2~62) winsize 61
5092 11:03:43.181183
5093 11:03:43.184077 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5094 11:03:43.184171
5095 11:03:43.187742 [CATrainingPosCal] consider 1 rank data
5096 11:03:43.191065 u2DelayCellTimex100 = 270/100 ps
5097 11:03:43.194227 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5098 11:03:43.197433 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5099 11:03:43.201204 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5100 11:03:43.204623 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5101 11:03:43.207795 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5102 11:03:43.210765 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5103 11:03:43.210850
5104 11:03:43.217565 CA PerBit enable=1, Macro0, CA PI delay=32
5105 11:03:43.217641
5106 11:03:43.217700 [CBTSetCACLKResult] CA Dly = 32
5107 11:03:43.220851 CS Dly: 5 (0~36)
5108 11:03:43.220919 ==
5109 11:03:43.224656 Dram Type= 6, Freq= 0, CH_0, rank 1
5110 11:03:43.227869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5111 11:03:43.227946 ==
5112 11:03:43.234482 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5113 11:03:43.240887 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5114 11:03:43.244016 [CA 0] Center 37 (6~68) winsize 63
5115 11:03:43.247940 [CA 1] Center 37 (7~68) winsize 62
5116 11:03:43.250928 [CA 2] Center 34 (4~65) winsize 62
5117 11:03:43.254270 [CA 3] Center 34 (4~65) winsize 62
5118 11:03:43.257464 [CA 4] Center 32 (2~63) winsize 62
5119 11:03:43.261214 [CA 5] Center 32 (2~62) winsize 61
5120 11:03:43.261293
5121 11:03:43.264141 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5122 11:03:43.264218
5123 11:03:43.267638 [CATrainingPosCal] consider 2 rank data
5124 11:03:43.270939 u2DelayCellTimex100 = 270/100 ps
5125 11:03:43.273935 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5126 11:03:43.277127 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5127 11:03:43.280692 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5128 11:03:43.283789 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5129 11:03:43.287123 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5130 11:03:43.290747 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5131 11:03:43.293853
5132 11:03:43.297124 CA PerBit enable=1, Macro0, CA PI delay=32
5133 11:03:43.297201
5134 11:03:43.300347 [CBTSetCACLKResult] CA Dly = 32
5135 11:03:43.300424 CS Dly: 5 (0~37)
5136 11:03:43.300483
5137 11:03:43.304110 ----->DramcWriteLeveling(PI) begin...
5138 11:03:43.304188 ==
5139 11:03:43.307328 Dram Type= 6, Freq= 0, CH_0, rank 0
5140 11:03:43.310559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5141 11:03:43.313632 ==
5142 11:03:43.313708 Write leveling (Byte 0): 33 => 33
5143 11:03:43.317287 Write leveling (Byte 1): 28 => 28
5144 11:03:43.320549 DramcWriteLeveling(PI) end<-----
5145 11:03:43.320628
5146 11:03:43.320687 ==
5147 11:03:43.323701 Dram Type= 6, Freq= 0, CH_0, rank 0
5148 11:03:43.330589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5149 11:03:43.330668 ==
5150 11:03:43.330726 [Gating] SW mode calibration
5151 11:03:43.340880 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5152 11:03:43.343841 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5153 11:03:43.347371 0 14 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
5154 11:03:43.354144 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 11:03:43.357128 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 11:03:43.360816 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 11:03:43.366958 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 11:03:43.370393 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 11:03:43.373711 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5160 11:03:43.380595 0 14 28 | B1->B0 | 3232 2525 | 1 1 | (1 1) (1 0)
5161 11:03:43.384089 0 15 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5162 11:03:43.387415 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 11:03:43.394350 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 11:03:43.397430 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 11:03:43.400769 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 11:03:43.407661 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 11:03:43.411030 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5168 11:03:43.414370 0 15 28 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
5169 11:03:43.420824 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5170 11:03:43.424026 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 11:03:43.427732 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 11:03:43.433718 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 11:03:43.436839 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 11:03:43.440175 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 11:03:43.447394 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 11:03:43.450350 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5177 11:03:43.453704 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 11:03:43.460644 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 11:03:43.463713 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 11:03:43.467084 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 11:03:43.470333 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 11:03:43.476858 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 11:03:43.480403 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 11:03:43.483926 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 11:03:43.490157 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 11:03:43.493480 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 11:03:43.497208 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 11:03:43.504066 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 11:03:43.506974 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 11:03:43.509997 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 11:03:43.516906 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 11:03:43.519933 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5193 11:03:43.523395 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 11:03:43.527372 Total UI for P1: 0, mck2ui 16
5195 11:03:43.530305 best dqsien dly found for B0: ( 1, 2, 28)
5196 11:03:43.533378 Total UI for P1: 0, mck2ui 16
5197 11:03:43.537052 best dqsien dly found for B1: ( 1, 2, 30)
5198 11:03:43.540266 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5199 11:03:43.543420 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5200 11:03:43.543497
5201 11:03:43.550021 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5202 11:03:43.553867 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5203 11:03:43.553976 [Gating] SW calibration Done
5204 11:03:43.556905 ==
5205 11:03:43.556985 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 11:03:43.563505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 11:03:43.563631 ==
5208 11:03:43.563724 RX Vref Scan: 0
5209 11:03:43.563808
5210 11:03:43.567072 RX Vref 0 -> 0, step: 1
5211 11:03:43.567157
5212 11:03:43.570003 RX Delay -80 -> 252, step: 8
5213 11:03:43.573837 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5214 11:03:43.576734 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5215 11:03:43.579738 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5216 11:03:43.586701 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5217 11:03:43.590084 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5218 11:03:43.593217 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5219 11:03:43.596301 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5220 11:03:43.599760 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5221 11:03:43.603133 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5222 11:03:43.609829 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5223 11:03:43.613592 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5224 11:03:43.616642 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5225 11:03:43.620051 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5226 11:03:43.623026 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5227 11:03:43.629407 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5228 11:03:43.632845 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5229 11:03:43.632924 ==
5230 11:03:43.636806 Dram Type= 6, Freq= 0, CH_0, rank 0
5231 11:03:43.639670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5232 11:03:43.639743 ==
5233 11:03:43.639818 DQS Delay:
5234 11:03:43.643181 DQS0 = 0, DQS1 = 0
5235 11:03:43.643249 DQM Delay:
5236 11:03:43.646252 DQM0 = 104, DQM1 = 94
5237 11:03:43.646337 DQ Delay:
5238 11:03:43.649659 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5239 11:03:43.653048 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5240 11:03:43.656036 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =91
5241 11:03:43.659895 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5242 11:03:43.659992
5243 11:03:43.660086
5244 11:03:43.660174 ==
5245 11:03:43.662685 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 11:03:43.669480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 11:03:43.669584 ==
5248 11:03:43.669671
5249 11:03:43.669751
5250 11:03:43.669846 TX Vref Scan disable
5251 11:03:43.673363 == TX Byte 0 ==
5252 11:03:43.676619 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5253 11:03:43.683614 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5254 11:03:43.683695 == TX Byte 1 ==
5255 11:03:43.686595 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5256 11:03:43.690184 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5257 11:03:43.693116 ==
5258 11:03:43.696509 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 11:03:43.700479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 11:03:43.700557 ==
5261 11:03:43.700655
5262 11:03:43.700708
5263 11:03:43.703061 TX Vref Scan disable
5264 11:03:43.703136 == TX Byte 0 ==
5265 11:03:43.709663 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5266 11:03:43.713217 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5267 11:03:43.713302 == TX Byte 1 ==
5268 11:03:43.719743 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5269 11:03:43.723111 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5270 11:03:43.723188
5271 11:03:43.723245 [DATLAT]
5272 11:03:43.726449 Freq=933, CH0 RK0
5273 11:03:43.726516
5274 11:03:43.726577 DATLAT Default: 0xd
5275 11:03:43.730224 0, 0xFFFF, sum = 0
5276 11:03:43.730299 1, 0xFFFF, sum = 0
5277 11:03:43.733039 2, 0xFFFF, sum = 0
5278 11:03:43.733102 3, 0xFFFF, sum = 0
5279 11:03:43.736427 4, 0xFFFF, sum = 0
5280 11:03:43.739758 5, 0xFFFF, sum = 0
5281 11:03:43.739859 6, 0xFFFF, sum = 0
5282 11:03:43.743125 7, 0xFFFF, sum = 0
5283 11:03:43.743218 8, 0xFFFF, sum = 0
5284 11:03:43.746555 9, 0xFFFF, sum = 0
5285 11:03:43.746663 10, 0x0, sum = 1
5286 11:03:43.749799 11, 0x0, sum = 2
5287 11:03:43.749866 12, 0x0, sum = 3
5288 11:03:43.749919 13, 0x0, sum = 4
5289 11:03:43.753093 best_step = 11
5290 11:03:43.753156
5291 11:03:43.753207 ==
5292 11:03:43.756227 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 11:03:43.759672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 11:03:43.759768 ==
5295 11:03:43.762872 RX Vref Scan: 1
5296 11:03:43.762936
5297 11:03:43.762990 RX Vref 0 -> 0, step: 1
5298 11:03:43.766562
5299 11:03:43.766642 RX Delay -53 -> 252, step: 4
5300 11:03:43.766696
5301 11:03:43.769829 Set Vref, RX VrefLevel [Byte0]: 53
5302 11:03:43.772930 [Byte1]: 49
5303 11:03:43.777585
5304 11:03:43.777679 Final RX Vref Byte 0 = 53 to rank0
5305 11:03:43.780447 Final RX Vref Byte 1 = 49 to rank0
5306 11:03:43.784478 Final RX Vref Byte 0 = 53 to rank1
5307 11:03:43.787083 Final RX Vref Byte 1 = 49 to rank1==
5308 11:03:43.790226 Dram Type= 6, Freq= 0, CH_0, rank 0
5309 11:03:43.797461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 11:03:43.797565 ==
5311 11:03:43.797649 DQS Delay:
5312 11:03:43.800240 DQS0 = 0, DQS1 = 0
5313 11:03:43.800370 DQM Delay:
5314 11:03:43.800454 DQM0 = 104, DQM1 = 95
5315 11:03:43.803782 DQ Delay:
5316 11:03:43.807123 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5317 11:03:43.810661 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =112
5318 11:03:43.813900 DQ8 =84, DQ9 =84, DQ10 =98, DQ11 =92
5319 11:03:43.817266 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5320 11:03:43.817376
5321 11:03:43.817455
5322 11:03:43.823708 [DQSOSCAuto] RK0, (LSB)MR18= 0x3930, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
5323 11:03:43.827368 CH0 RK0: MR19=505, MR18=3930
5324 11:03:43.833784 CH0_RK0: MR19=0x505, MR18=0x3930, DQSOSC=404, MR23=63, INC=66, DEC=44
5325 11:03:43.833874
5326 11:03:43.836939 ----->DramcWriteLeveling(PI) begin...
5327 11:03:43.837035 ==
5328 11:03:43.840602 Dram Type= 6, Freq= 0, CH_0, rank 1
5329 11:03:43.843577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 11:03:43.843688 ==
5331 11:03:43.847008 Write leveling (Byte 0): 32 => 32
5332 11:03:43.850233 Write leveling (Byte 1): 28 => 28
5333 11:03:43.853363 DramcWriteLeveling(PI) end<-----
5334 11:03:43.853461
5335 11:03:43.853544 ==
5336 11:03:43.857244 Dram Type= 6, Freq= 0, CH_0, rank 1
5337 11:03:43.863558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 11:03:43.863665 ==
5339 11:03:43.863751 [Gating] SW mode calibration
5340 11:03:43.873726 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5341 11:03:43.876815 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5342 11:03:43.880561 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5343 11:03:43.886940 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 11:03:43.889932 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 11:03:43.893205 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 11:03:43.900231 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 11:03:43.903274 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 11:03:43.907338 0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5349 11:03:43.913709 0 14 28 | B1->B0 | 2828 2c2c | 0 0 | (0 0) (1 0)
5350 11:03:43.916929 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5351 11:03:43.919952 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 11:03:43.926614 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 11:03:43.929851 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 11:03:43.933103 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 11:03:43.939691 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 11:03:43.943352 0 15 24 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
5357 11:03:43.946913 0 15 28 | B1->B0 | 3c3c 3838 | 1 1 | (0 0) (0 0)
5358 11:03:43.953085 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 11:03:43.957081 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 11:03:43.959677 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 11:03:43.966568 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 11:03:43.969607 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 11:03:43.973706 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 11:03:43.980058 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5365 11:03:43.983510 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5366 11:03:43.986471 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5367 11:03:43.993726 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 11:03:43.996560 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 11:03:43.999930 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 11:03:44.003361 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 11:03:44.009559 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 11:03:44.013026 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 11:03:44.016374 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 11:03:44.022643 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 11:03:44.026206 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 11:03:44.029855 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 11:03:44.036071 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 11:03:44.039904 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 11:03:44.042928 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 11:03:44.049721 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5381 11:03:44.053056 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5382 11:03:44.056162 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 11:03:44.059917 Total UI for P1: 0, mck2ui 16
5384 11:03:44.063344 best dqsien dly found for B0: ( 1, 2, 28)
5385 11:03:44.066195 Total UI for P1: 0, mck2ui 16
5386 11:03:44.069643 best dqsien dly found for B1: ( 1, 2, 26)
5387 11:03:44.072823 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5388 11:03:44.076586 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5389 11:03:44.076674
5390 11:03:44.082905 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5391 11:03:44.086118 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5392 11:03:44.086209 [Gating] SW calibration Done
5393 11:03:44.089977 ==
5394 11:03:44.093068 Dram Type= 6, Freq= 0, CH_0, rank 1
5395 11:03:44.096234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5396 11:03:44.096312 ==
5397 11:03:44.096370 RX Vref Scan: 0
5398 11:03:44.096424
5399 11:03:44.099533 RX Vref 0 -> 0, step: 1
5400 11:03:44.099609
5401 11:03:44.102776 RX Delay -80 -> 252, step: 8
5402 11:03:44.106248 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5403 11:03:44.109436 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5404 11:03:44.112958 iDelay=208, Bit 2, Center 107 (16 ~ 199) 184
5405 11:03:44.119574 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5406 11:03:44.122438 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5407 11:03:44.125756 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5408 11:03:44.129502 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5409 11:03:44.132561 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5410 11:03:44.139283 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5411 11:03:44.142501 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5412 11:03:44.146076 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5413 11:03:44.149231 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5414 11:03:44.152297 iDelay=208, Bit 12, Center 99 (16 ~ 183) 168
5415 11:03:44.155831 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5416 11:03:44.162024 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5417 11:03:44.165739 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5418 11:03:44.165837 ==
5419 11:03:44.169004 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 11:03:44.171990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 11:03:44.172061 ==
5422 11:03:44.175393 DQS Delay:
5423 11:03:44.175457 DQS0 = 0, DQS1 = 0
5424 11:03:44.178980 DQM Delay:
5425 11:03:44.179049 DQM0 = 105, DQM1 = 95
5426 11:03:44.179104 DQ Delay:
5427 11:03:44.182289 DQ0 =107, DQ1 =107, DQ2 =107, DQ3 =103
5428 11:03:44.185527 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5429 11:03:44.188701 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5430 11:03:44.195870 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =103
5431 11:03:44.195952
5432 11:03:44.196013
5433 11:03:44.196067 ==
5434 11:03:44.198807 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 11:03:44.202168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 11:03:44.202239 ==
5437 11:03:44.202296
5438 11:03:44.202348
5439 11:03:44.205933 TX Vref Scan disable
5440 11:03:44.205997 == TX Byte 0 ==
5441 11:03:44.212338 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5442 11:03:44.215564 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5443 11:03:44.215632 == TX Byte 1 ==
5444 11:03:44.222492 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5445 11:03:44.225373 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5446 11:03:44.225473 ==
5447 11:03:44.229115 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 11:03:44.232214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 11:03:44.232289 ==
5450 11:03:44.232349
5451 11:03:44.232402
5452 11:03:44.235312 TX Vref Scan disable
5453 11:03:44.239064 == TX Byte 0 ==
5454 11:03:44.242338 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5455 11:03:44.245292 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5456 11:03:44.248782 == TX Byte 1 ==
5457 11:03:44.252104 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5458 11:03:44.255732 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5459 11:03:44.255815
5460 11:03:44.258855 [DATLAT]
5461 11:03:44.258965 Freq=933, CH0 RK1
5462 11:03:44.259040
5463 11:03:44.262245 DATLAT Default: 0xb
5464 11:03:44.262351 0, 0xFFFF, sum = 0
5465 11:03:44.265527 1, 0xFFFF, sum = 0
5466 11:03:44.265608 2, 0xFFFF, sum = 0
5467 11:03:44.268892 3, 0xFFFF, sum = 0
5468 11:03:44.268972 4, 0xFFFF, sum = 0
5469 11:03:44.272294 5, 0xFFFF, sum = 0
5470 11:03:44.272375 6, 0xFFFF, sum = 0
5471 11:03:44.275939 7, 0xFFFF, sum = 0
5472 11:03:44.276018 8, 0xFFFF, sum = 0
5473 11:03:44.279091 9, 0xFFFF, sum = 0
5474 11:03:44.279194 10, 0x0, sum = 1
5475 11:03:44.282697 11, 0x0, sum = 2
5476 11:03:44.282781 12, 0x0, sum = 3
5477 11:03:44.285879 13, 0x0, sum = 4
5478 11:03:44.285984 best_step = 11
5479 11:03:44.286074
5480 11:03:44.286148 ==
5481 11:03:44.288690 Dram Type= 6, Freq= 0, CH_0, rank 1
5482 11:03:44.295997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5483 11:03:44.296081 ==
5484 11:03:44.296158 RX Vref Scan: 0
5485 11:03:44.296233
5486 11:03:44.298597 RX Vref 0 -> 0, step: 1
5487 11:03:44.298666
5488 11:03:44.302313 RX Delay -45 -> 252, step: 4
5489 11:03:44.305521 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5490 11:03:44.308809 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5491 11:03:44.315323 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5492 11:03:44.319013 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5493 11:03:44.322318 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5494 11:03:44.325553 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5495 11:03:44.328582 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5496 11:03:44.335595 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5497 11:03:44.338623 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5498 11:03:44.341845 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5499 11:03:44.345137 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5500 11:03:44.348156 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5501 11:03:44.351685 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5502 11:03:44.358636 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5503 11:03:44.361787 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5504 11:03:44.364873 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5505 11:03:44.364963 ==
5506 11:03:44.368585 Dram Type= 6, Freq= 0, CH_0, rank 1
5507 11:03:44.371504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5508 11:03:44.374788 ==
5509 11:03:44.374864 DQS Delay:
5510 11:03:44.374942 DQS0 = 0, DQS1 = 0
5511 11:03:44.378518 DQM Delay:
5512 11:03:44.378589 DQM0 = 104, DQM1 = 94
5513 11:03:44.381527 DQ Delay:
5514 11:03:44.384983 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5515 11:03:44.388379 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5516 11:03:44.391595 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =88
5517 11:03:44.394812 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =102
5518 11:03:44.394885
5519 11:03:44.394960
5520 11:03:44.401746 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5521 11:03:44.405354 CH0 RK1: MR19=505, MR18=2C05
5522 11:03:44.412601 CH0_RK1: MR19=0x505, MR18=0x2C05, DQSOSC=408, MR23=63, INC=65, DEC=43
5523 11:03:44.415329 [RxdqsGatingPostProcess] freq 933
5524 11:03:44.418367 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5525 11:03:44.421713 best DQS0 dly(2T, 0.5T) = (0, 10)
5526 11:03:44.424809 best DQS1 dly(2T, 0.5T) = (0, 10)
5527 11:03:44.428016 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5528 11:03:44.431789 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5529 11:03:44.434935 best DQS0 dly(2T, 0.5T) = (0, 10)
5530 11:03:44.438741 best DQS1 dly(2T, 0.5T) = (0, 10)
5531 11:03:44.441821 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5532 11:03:44.445265 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5533 11:03:44.448259 Pre-setting of DQS Precalculation
5534 11:03:44.451660 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5535 11:03:44.451761 ==
5536 11:03:44.454939 Dram Type= 6, Freq= 0, CH_1, rank 0
5537 11:03:44.462152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5538 11:03:44.462246 ==
5539 11:03:44.465310 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5540 11:03:44.471895 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5541 11:03:44.475060 [CA 0] Center 36 (6~67) winsize 62
5542 11:03:44.478208 [CA 1] Center 37 (6~68) winsize 63
5543 11:03:44.481461 [CA 2] Center 35 (5~65) winsize 61
5544 11:03:44.485552 [CA 3] Center 34 (4~65) winsize 62
5545 11:03:44.488641 [CA 4] Center 34 (4~64) winsize 61
5546 11:03:44.491441 [CA 5] Center 33 (3~64) winsize 62
5547 11:03:44.491514
5548 11:03:44.494940 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5549 11:03:44.495028
5550 11:03:44.498293 [CATrainingPosCal] consider 1 rank data
5551 11:03:44.501658 u2DelayCellTimex100 = 270/100 ps
5552 11:03:44.504858 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5553 11:03:44.508480 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5554 11:03:44.511435 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5555 11:03:44.518569 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5556 11:03:44.521617 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5557 11:03:44.525057 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5558 11:03:44.525128
5559 11:03:44.528515 CA PerBit enable=1, Macro0, CA PI delay=33
5560 11:03:44.528585
5561 11:03:44.531858 [CBTSetCACLKResult] CA Dly = 33
5562 11:03:44.531931 CS Dly: 6 (0~37)
5563 11:03:44.532004 ==
5564 11:03:44.535299 Dram Type= 6, Freq= 0, CH_1, rank 1
5565 11:03:44.541526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5566 11:03:44.541635 ==
5567 11:03:44.544808 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5568 11:03:44.551592 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5569 11:03:44.555024 [CA 0] Center 36 (6~67) winsize 62
5570 11:03:44.558223 [CA 1] Center 37 (7~68) winsize 62
5571 11:03:44.561964 [CA 2] Center 35 (4~66) winsize 63
5572 11:03:44.564657 [CA 3] Center 34 (4~65) winsize 62
5573 11:03:44.568465 [CA 4] Center 34 (4~65) winsize 62
5574 11:03:44.571585 [CA 5] Center 34 (4~64) winsize 61
5575 11:03:44.571686
5576 11:03:44.574806 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5577 11:03:44.574889
5578 11:03:44.578220 [CATrainingPosCal] consider 2 rank data
5579 11:03:44.581517 u2DelayCellTimex100 = 270/100 ps
5580 11:03:44.584667 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5581 11:03:44.588138 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5582 11:03:44.595012 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5583 11:03:44.598173 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5584 11:03:44.601436 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5585 11:03:44.604806 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5586 11:03:44.604901
5587 11:03:44.608170 CA PerBit enable=1, Macro0, CA PI delay=34
5588 11:03:44.608254
5589 11:03:44.611583 [CBTSetCACLKResult] CA Dly = 34
5590 11:03:44.611686 CS Dly: 7 (0~39)
5591 11:03:44.611770
5592 11:03:44.615073 ----->DramcWriteLeveling(PI) begin...
5593 11:03:44.617820 ==
5594 11:03:44.621548 Dram Type= 6, Freq= 0, CH_1, rank 0
5595 11:03:44.624651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5596 11:03:44.624744 ==
5597 11:03:44.627895 Write leveling (Byte 0): 25 => 25
5598 11:03:44.631586 Write leveling (Byte 1): 30 => 30
5599 11:03:44.634893 DramcWriteLeveling(PI) end<-----
5600 11:03:44.634966
5601 11:03:44.635039 ==
5602 11:03:44.637908 Dram Type= 6, Freq= 0, CH_1, rank 0
5603 11:03:44.641143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5604 11:03:44.641236 ==
5605 11:03:44.644626 [Gating] SW mode calibration
5606 11:03:44.651334 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5607 11:03:44.657762 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5608 11:03:44.661336 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 11:03:44.664570 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 11:03:44.671178 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 11:03:44.674509 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 11:03:44.677780 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 11:03:44.680931 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5614 11:03:44.687465 0 14 24 | B1->B0 | 3333 2d2d | 0 0 | (0 1) (0 0)
5615 11:03:44.690876 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5616 11:03:44.694129 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 11:03:44.701130 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 11:03:44.704599 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 11:03:44.707444 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 11:03:44.714420 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 11:03:44.717740 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 11:03:44.721094 0 15 24 | B1->B0 | 2828 3838 | 1 1 | (0 0) (0 0)
5623 11:03:44.727449 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5624 11:03:44.731071 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 11:03:44.734000 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 11:03:44.740883 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 11:03:44.744471 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 11:03:44.747570 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 11:03:44.754477 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 11:03:44.757867 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5631 11:03:44.760990 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5632 11:03:44.767656 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 11:03:44.770752 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 11:03:44.774218 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 11:03:44.780869 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 11:03:44.784397 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 11:03:44.787361 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 11:03:44.793898 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 11:03:44.797915 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 11:03:44.800544 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 11:03:44.804366 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 11:03:44.810461 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 11:03:44.814338 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 11:03:44.817494 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 11:03:44.824029 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 11:03:44.827514 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 11:03:44.830410 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 11:03:44.834313 Total UI for P1: 0, mck2ui 16
5649 11:03:44.837097 best dqsien dly found for B0: ( 1, 2, 26)
5650 11:03:44.841040 Total UI for P1: 0, mck2ui 16
5651 11:03:44.843949 best dqsien dly found for B1: ( 1, 2, 26)
5652 11:03:44.847163 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5653 11:03:44.851008 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5654 11:03:44.851106
5655 11:03:44.857449 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5656 11:03:44.860534 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5657 11:03:44.863917 [Gating] SW calibration Done
5658 11:03:44.863992 ==
5659 11:03:44.867032 Dram Type= 6, Freq= 0, CH_1, rank 0
5660 11:03:44.870812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5661 11:03:44.870911 ==
5662 11:03:44.870996 RX Vref Scan: 0
5663 11:03:44.871084
5664 11:03:44.873938 RX Vref 0 -> 0, step: 1
5665 11:03:44.874094
5666 11:03:44.876967 RX Delay -80 -> 252, step: 8
5667 11:03:44.880908 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5668 11:03:44.883914 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5669 11:03:44.887586 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5670 11:03:44.894146 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5671 11:03:44.897235 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5672 11:03:44.900699 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5673 11:03:44.903638 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5674 11:03:44.906961 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5675 11:03:44.910567 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5676 11:03:44.917092 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5677 11:03:44.920674 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5678 11:03:44.923806 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5679 11:03:44.926882 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5680 11:03:44.930753 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5681 11:03:44.936966 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5682 11:03:44.940805 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5683 11:03:44.940881 ==
5684 11:03:44.943638 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 11:03:44.947127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 11:03:44.947222 ==
5687 11:03:44.947306 DQS Delay:
5688 11:03:44.950575 DQS0 = 0, DQS1 = 0
5689 11:03:44.950668 DQM Delay:
5690 11:03:44.953910 DQM0 = 103, DQM1 = 98
5691 11:03:44.953987 DQ Delay:
5692 11:03:44.957304 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5693 11:03:44.960260 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5694 11:03:44.963911 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5695 11:03:44.967054 DQ12 =107, DQ13 =103, DQ14 =107, DQ15 =107
5696 11:03:44.967128
5697 11:03:44.967211
5698 11:03:44.967278 ==
5699 11:03:44.970240 Dram Type= 6, Freq= 0, CH_1, rank 0
5700 11:03:44.977323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5701 11:03:44.977418 ==
5702 11:03:44.977500
5703 11:03:44.977579
5704 11:03:44.977659 TX Vref Scan disable
5705 11:03:44.981153 == TX Byte 0 ==
5706 11:03:44.984146 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5707 11:03:44.991001 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5708 11:03:44.991071 == TX Byte 1 ==
5709 11:03:44.994081 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5710 11:03:45.001329 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5711 11:03:45.001438 ==
5712 11:03:45.003969 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 11:03:45.007438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 11:03:45.007527 ==
5715 11:03:45.007608
5716 11:03:45.007709
5717 11:03:45.010494 TX Vref Scan disable
5718 11:03:45.010557 == TX Byte 0 ==
5719 11:03:45.017244 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5720 11:03:45.020553 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5721 11:03:45.020623 == TX Byte 1 ==
5722 11:03:45.027547 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5723 11:03:45.030726 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5724 11:03:45.030824
5725 11:03:45.030921 [DATLAT]
5726 11:03:45.033994 Freq=933, CH1 RK0
5727 11:03:45.034082
5728 11:03:45.034142 DATLAT Default: 0xd
5729 11:03:45.037176 0, 0xFFFF, sum = 0
5730 11:03:45.037252 1, 0xFFFF, sum = 0
5731 11:03:45.041209 2, 0xFFFF, sum = 0
5732 11:03:45.041308 3, 0xFFFF, sum = 0
5733 11:03:45.044375 4, 0xFFFF, sum = 0
5734 11:03:45.044451 5, 0xFFFF, sum = 0
5735 11:03:45.047355 6, 0xFFFF, sum = 0
5736 11:03:45.050872 7, 0xFFFF, sum = 0
5737 11:03:45.050975 8, 0xFFFF, sum = 0
5738 11:03:45.053991 9, 0xFFFF, sum = 0
5739 11:03:45.054101 10, 0x0, sum = 1
5740 11:03:45.054190 11, 0x0, sum = 2
5741 11:03:45.057425 12, 0x0, sum = 3
5742 11:03:45.057523 13, 0x0, sum = 4
5743 11:03:45.060558 best_step = 11
5744 11:03:45.060658
5745 11:03:45.060747 ==
5746 11:03:45.064104 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 11:03:45.067343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 11:03:45.067421 ==
5749 11:03:45.070620 RX Vref Scan: 1
5750 11:03:45.070696
5751 11:03:45.070755 RX Vref 0 -> 0, step: 1
5752 11:03:45.074019
5753 11:03:45.074118 RX Delay -45 -> 252, step: 4
5754 11:03:45.074203
5755 11:03:45.077255 Set Vref, RX VrefLevel [Byte0]: 53
5756 11:03:45.080571 [Byte1]: 52
5757 11:03:45.085119
5758 11:03:45.085197 Final RX Vref Byte 0 = 53 to rank0
5759 11:03:45.088121 Final RX Vref Byte 1 = 52 to rank0
5760 11:03:45.091355 Final RX Vref Byte 0 = 53 to rank1
5761 11:03:45.094735 Final RX Vref Byte 1 = 52 to rank1==
5762 11:03:45.098429 Dram Type= 6, Freq= 0, CH_1, rank 0
5763 11:03:45.104606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 11:03:45.104684 ==
5765 11:03:45.104743 DQS Delay:
5766 11:03:45.104798 DQS0 = 0, DQS1 = 0
5767 11:03:45.108651 DQM Delay:
5768 11:03:45.108727 DQM0 = 102, DQM1 = 98
5769 11:03:45.111524 DQ Delay:
5770 11:03:45.114975 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5771 11:03:45.118033 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =102
5772 11:03:45.121461 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92
5773 11:03:45.124677 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106
5774 11:03:45.124754
5775 11:03:45.124813
5776 11:03:45.131498 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e35, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5777 11:03:45.134338 CH1 RK0: MR19=505, MR18=1E35
5778 11:03:45.141063 CH1_RK0: MR19=0x505, MR18=0x1E35, DQSOSC=405, MR23=63, INC=66, DEC=44
5779 11:03:45.141144
5780 11:03:45.144442 ----->DramcWriteLeveling(PI) begin...
5781 11:03:45.144518 ==
5782 11:03:45.147475 Dram Type= 6, Freq= 0, CH_1, rank 1
5783 11:03:45.150903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5784 11:03:45.150981 ==
5785 11:03:45.154707 Write leveling (Byte 0): 27 => 27
5786 11:03:45.157558 Write leveling (Byte 1): 29 => 29
5787 11:03:45.160767 DramcWriteLeveling(PI) end<-----
5788 11:03:45.160877
5789 11:03:45.160969 ==
5790 11:03:45.164243 Dram Type= 6, Freq= 0, CH_1, rank 1
5791 11:03:45.167930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 11:03:45.170822 ==
5793 11:03:45.170926 [Gating] SW mode calibration
5794 11:03:45.181545 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5795 11:03:45.184424 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5796 11:03:45.187855 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 11:03:45.194560 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 11:03:45.197802 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 11:03:45.201304 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 11:03:45.207790 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 11:03:45.210952 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5802 11:03:45.215009 0 14 24 | B1->B0 | 2f2f 3030 | 0 0 | (0 1) (0 0)
5803 11:03:45.221190 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 11:03:45.224589 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 11:03:45.227566 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 11:03:45.234543 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 11:03:45.237909 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 11:03:45.240966 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 11:03:45.248350 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 11:03:45.250695 0 15 24 | B1->B0 | 3939 2929 | 0 0 | (0 0) (0 0)
5811 11:03:45.254510 0 15 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5812 11:03:45.261378 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 11:03:45.264177 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 11:03:45.267572 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 11:03:45.274036 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 11:03:45.277636 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 11:03:45.280968 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 11:03:45.284129 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5819 11:03:45.290959 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5820 11:03:45.293908 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 11:03:45.297267 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 11:03:45.303855 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 11:03:45.307811 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 11:03:45.310591 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 11:03:45.317281 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 11:03:45.320866 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 11:03:45.324077 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 11:03:45.330609 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 11:03:45.333696 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 11:03:45.337459 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 11:03:45.343905 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 11:03:45.347215 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 11:03:45.350268 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 11:03:45.357392 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5835 11:03:45.360528 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5836 11:03:45.363748 Total UI for P1: 0, mck2ui 16
5837 11:03:45.367389 best dqsien dly found for B0: ( 1, 2, 24)
5838 11:03:45.370331 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 11:03:45.374173 Total UI for P1: 0, mck2ui 16
5840 11:03:45.377060 best dqsien dly found for B1: ( 1, 2, 26)
5841 11:03:45.380336 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5842 11:03:45.383769 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5843 11:03:45.383845
5844 11:03:45.390469 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5845 11:03:45.393549 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5846 11:03:45.393624 [Gating] SW calibration Done
5847 11:03:45.396918 ==
5848 11:03:45.400218 Dram Type= 6, Freq= 0, CH_1, rank 1
5849 11:03:45.403486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5850 11:03:45.403579 ==
5851 11:03:45.403670 RX Vref Scan: 0
5852 11:03:45.403739
5853 11:03:45.406906 RX Vref 0 -> 0, step: 1
5854 11:03:45.406981
5855 11:03:45.410069 RX Delay -80 -> 252, step: 8
5856 11:03:45.413657 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5857 11:03:45.416653 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5858 11:03:45.420212 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5859 11:03:45.426958 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5860 11:03:45.429777 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5861 11:03:45.433200 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5862 11:03:45.436946 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5863 11:03:45.439652 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5864 11:03:45.443322 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5865 11:03:45.449802 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5866 11:03:45.453526 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5867 11:03:45.456619 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5868 11:03:45.459865 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5869 11:03:45.463088 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5870 11:03:45.470408 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5871 11:03:45.473382 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5872 11:03:45.473458 ==
5873 11:03:45.476655 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 11:03:45.480033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 11:03:45.480103 ==
5876 11:03:45.480161 DQS Delay:
5877 11:03:45.483166 DQS0 = 0, DQS1 = 0
5878 11:03:45.483241 DQM Delay:
5879 11:03:45.486217 DQM0 = 102, DQM1 = 98
5880 11:03:45.486321 DQ Delay:
5881 11:03:45.490115 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5882 11:03:45.493296 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5883 11:03:45.496703 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5884 11:03:45.499832 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5885 11:03:45.499907
5886 11:03:45.499964
5887 11:03:45.500018 ==
5888 11:03:45.503371 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 11:03:45.509800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 11:03:45.509898 ==
5891 11:03:45.509982
5892 11:03:45.510086
5893 11:03:45.510138 TX Vref Scan disable
5894 11:03:45.513573 == TX Byte 0 ==
5895 11:03:45.516779 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5896 11:03:45.523454 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5897 11:03:45.523530 == TX Byte 1 ==
5898 11:03:45.526552 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5899 11:03:45.533381 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5900 11:03:45.533461 ==
5901 11:03:45.536682 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 11:03:45.540157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 11:03:45.540236 ==
5904 11:03:45.540343
5905 11:03:45.540424
5906 11:03:45.543553 TX Vref Scan disable
5907 11:03:45.543629 == TX Byte 0 ==
5908 11:03:45.550209 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5909 11:03:45.553285 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5910 11:03:45.553361 == TX Byte 1 ==
5911 11:03:45.560141 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5912 11:03:45.563262 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5913 11:03:45.563337
5914 11:03:45.563394 [DATLAT]
5915 11:03:45.566311 Freq=933, CH1 RK1
5916 11:03:45.566386
5917 11:03:45.566443 DATLAT Default: 0xb
5918 11:03:45.569598 0, 0xFFFF, sum = 0
5919 11:03:45.569674 1, 0xFFFF, sum = 0
5920 11:03:45.573156 2, 0xFFFF, sum = 0
5921 11:03:45.573231 3, 0xFFFF, sum = 0
5922 11:03:45.576581 4, 0xFFFF, sum = 0
5923 11:03:45.579653 5, 0xFFFF, sum = 0
5924 11:03:45.579730 6, 0xFFFF, sum = 0
5925 11:03:45.583261 7, 0xFFFF, sum = 0
5926 11:03:45.583338 8, 0xFFFF, sum = 0
5927 11:03:45.586276 9, 0xFFFF, sum = 0
5928 11:03:45.586374 10, 0x0, sum = 1
5929 11:03:45.589859 11, 0x0, sum = 2
5930 11:03:45.589935 12, 0x0, sum = 3
5931 11:03:45.589994 13, 0x0, sum = 4
5932 11:03:45.592937 best_step = 11
5933 11:03:45.593011
5934 11:03:45.593068 ==
5935 11:03:45.596362 Dram Type= 6, Freq= 0, CH_1, rank 1
5936 11:03:45.599555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5937 11:03:45.599631 ==
5938 11:03:45.602840 RX Vref Scan: 0
5939 11:03:45.602931
5940 11:03:45.603021 RX Vref 0 -> 0, step: 1
5941 11:03:45.606142
5942 11:03:45.606251 RX Delay -45 -> 252, step: 4
5943 11:03:45.613772 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5944 11:03:45.617017 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5945 11:03:45.620348 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5946 11:03:45.624131 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5947 11:03:45.627307 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5948 11:03:45.633570 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5949 11:03:45.637241 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5950 11:03:45.640331 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5951 11:03:45.643544 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5952 11:03:45.646705 iDelay=203, Bit 9, Center 88 (-1 ~ 178) 180
5953 11:03:45.653830 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5954 11:03:45.657039 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5955 11:03:45.660415 iDelay=203, Bit 12, Center 106 (19 ~ 194) 176
5956 11:03:45.664004 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5957 11:03:45.666916 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5958 11:03:45.674084 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5959 11:03:45.674165 ==
5960 11:03:45.677091 Dram Type= 6, Freq= 0, CH_1, rank 1
5961 11:03:45.680448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5962 11:03:45.680552 ==
5963 11:03:45.680639 DQS Delay:
5964 11:03:45.683442 DQS0 = 0, DQS1 = 0
5965 11:03:45.683541 DQM Delay:
5966 11:03:45.687027 DQM0 = 104, DQM1 = 98
5967 11:03:45.687122 DQ Delay:
5968 11:03:45.690512 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =98
5969 11:03:45.693470 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5970 11:03:45.697046 DQ8 =88, DQ9 =88, DQ10 =100, DQ11 =92
5971 11:03:45.699895 DQ12 =106, DQ13 =104, DQ14 =102, DQ15 =106
5972 11:03:45.699973
5973 11:03:45.700031
5974 11:03:45.710188 [DQSOSCAuto] RK1, (LSB)MR18= 0x3002, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
5975 11:03:45.710271 CH1 RK1: MR19=505, MR18=3002
5976 11:03:45.716743 CH1_RK1: MR19=0x505, MR18=0x3002, DQSOSC=406, MR23=63, INC=65, DEC=43
5977 11:03:45.720225 [RxdqsGatingPostProcess] freq 933
5978 11:03:45.726661 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5979 11:03:45.729690 best DQS0 dly(2T, 0.5T) = (0, 10)
5980 11:03:45.733263 best DQS1 dly(2T, 0.5T) = (0, 10)
5981 11:03:45.736444 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5982 11:03:45.740326 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5983 11:03:45.743442 best DQS0 dly(2T, 0.5T) = (0, 10)
5984 11:03:45.747161 best DQS1 dly(2T, 0.5T) = (0, 10)
5985 11:03:45.749888 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5986 11:03:45.749963 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5987 11:03:45.753380 Pre-setting of DQS Precalculation
5988 11:03:45.760118 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5989 11:03:45.766640 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5990 11:03:45.773233 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5991 11:03:45.773334
5992 11:03:45.773428
5993 11:03:45.776644 [Calibration Summary] 1866 Mbps
5994 11:03:45.780223 CH 0, Rank 0
5995 11:03:45.780298 SW Impedance : PASS
5996 11:03:45.783592 DUTY Scan : NO K
5997 11:03:45.783668 ZQ Calibration : PASS
5998 11:03:45.787440 Jitter Meter : NO K
5999 11:03:45.789663 CBT Training : PASS
6000 11:03:45.789738 Write leveling : PASS
6001 11:03:45.792984 RX DQS gating : PASS
6002 11:03:45.796652 RX DQ/DQS(RDDQC) : PASS
6003 11:03:45.796728 TX DQ/DQS : PASS
6004 11:03:45.799993 RX DATLAT : PASS
6005 11:03:45.803498 RX DQ/DQS(Engine): PASS
6006 11:03:45.803573 TX OE : NO K
6007 11:03:45.806258 All Pass.
6008 11:03:45.806333
6009 11:03:45.806415 CH 0, Rank 1
6010 11:03:45.809865 SW Impedance : PASS
6011 11:03:45.809953 DUTY Scan : NO K
6012 11:03:45.812946 ZQ Calibration : PASS
6013 11:03:45.816202 Jitter Meter : NO K
6014 11:03:45.816325 CBT Training : PASS
6015 11:03:45.819529 Write leveling : PASS
6016 11:03:45.823352 RX DQS gating : PASS
6017 11:03:45.823488 RX DQ/DQS(RDDQC) : PASS
6018 11:03:45.826500 TX DQ/DQS : PASS
6019 11:03:45.829780 RX DATLAT : PASS
6020 11:03:45.829854 RX DQ/DQS(Engine): PASS
6021 11:03:45.832904 TX OE : NO K
6022 11:03:45.832978 All Pass.
6023 11:03:45.833035
6024 11:03:45.836652 CH 1, Rank 0
6025 11:03:45.836726 SW Impedance : PASS
6026 11:03:45.839615 DUTY Scan : NO K
6027 11:03:45.839730 ZQ Calibration : PASS
6028 11:03:45.842956 Jitter Meter : NO K
6029 11:03:45.846753 CBT Training : PASS
6030 11:03:45.846829 Write leveling : PASS
6031 11:03:45.849962 RX DQS gating : PASS
6032 11:03:45.853142 RX DQ/DQS(RDDQC) : PASS
6033 11:03:45.853217 TX DQ/DQS : PASS
6034 11:03:45.856355 RX DATLAT : PASS
6035 11:03:45.859655 RX DQ/DQS(Engine): PASS
6036 11:03:45.859745 TX OE : NO K
6037 11:03:45.863200 All Pass.
6038 11:03:45.863278
6039 11:03:45.863337 CH 1, Rank 1
6040 11:03:45.866348 SW Impedance : PASS
6041 11:03:45.866439 DUTY Scan : NO K
6042 11:03:45.869784 ZQ Calibration : PASS
6043 11:03:45.872697 Jitter Meter : NO K
6044 11:03:45.872812 CBT Training : PASS
6045 11:03:45.876271 Write leveling : PASS
6046 11:03:45.879479 RX DQS gating : PASS
6047 11:03:45.879554 RX DQ/DQS(RDDQC) : PASS
6048 11:03:45.883115 TX DQ/DQS : PASS
6049 11:03:45.883224 RX DATLAT : PASS
6050 11:03:45.886049 RX DQ/DQS(Engine): PASS
6051 11:03:45.889339 TX OE : NO K
6052 11:03:45.889435 All Pass.
6053 11:03:45.889515
6054 11:03:45.893249 DramC Write-DBI off
6055 11:03:45.893313 PER_BANK_REFRESH: Hybrid Mode
6056 11:03:45.895985 TX_TRACKING: ON
6057 11:03:45.905964 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6058 11:03:45.909565 [FAST_K] Save calibration result to emmc
6059 11:03:45.912602 dramc_set_vcore_voltage set vcore to 650000
6060 11:03:45.912707 Read voltage for 400, 6
6061 11:03:45.915951 Vio18 = 0
6062 11:03:45.916039 Vcore = 650000
6063 11:03:45.916119 Vdram = 0
6064 11:03:45.919750 Vddq = 0
6065 11:03:45.919817 Vmddr = 0
6066 11:03:45.926159 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6067 11:03:45.929230 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6068 11:03:45.932577 MEM_TYPE=3, freq_sel=20
6069 11:03:45.936190 sv_algorithm_assistance_LP4_800
6070 11:03:45.939318 ============ PULL DRAM RESETB DOWN ============
6071 11:03:45.942727 ========== PULL DRAM RESETB DOWN end =========
6072 11:03:45.949689 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6073 11:03:45.952913 ===================================
6074 11:03:45.953010 LPDDR4 DRAM CONFIGURATION
6075 11:03:45.955975 ===================================
6076 11:03:45.959239 EX_ROW_EN[0] = 0x0
6077 11:03:45.959306 EX_ROW_EN[1] = 0x0
6078 11:03:45.963014 LP4Y_EN = 0x0
6079 11:03:45.963087 WORK_FSP = 0x0
6080 11:03:45.966153 WL = 0x2
6081 11:03:45.966251 RL = 0x2
6082 11:03:45.969633 BL = 0x2
6083 11:03:45.972453 RPST = 0x0
6084 11:03:45.972548 RD_PRE = 0x0
6085 11:03:45.975999 WR_PRE = 0x1
6086 11:03:45.976111 WR_PST = 0x0
6087 11:03:45.979176 DBI_WR = 0x0
6088 11:03:45.979272 DBI_RD = 0x0
6089 11:03:45.983010 OTF = 0x1
6090 11:03:45.986258 ===================================
6091 11:03:45.989397 ===================================
6092 11:03:45.989488 ANA top config
6093 11:03:45.992833 ===================================
6094 11:03:45.995852 DLL_ASYNC_EN = 0
6095 11:03:45.999751 ALL_SLAVE_EN = 1
6096 11:03:45.999828 NEW_RANK_MODE = 1
6097 11:03:46.002845 DLL_IDLE_MODE = 1
6098 11:03:46.006124 LP45_APHY_COMB_EN = 1
6099 11:03:46.009262 TX_ODT_DIS = 1
6100 11:03:46.009337 NEW_8X_MODE = 1
6101 11:03:46.012644 ===================================
6102 11:03:46.016453 ===================================
6103 11:03:46.019600 data_rate = 800
6104 11:03:46.022467 CKR = 1
6105 11:03:46.026241 DQ_P2S_RATIO = 4
6106 11:03:46.029295 ===================================
6107 11:03:46.032383 CA_P2S_RATIO = 4
6108 11:03:46.036154 DQ_CA_OPEN = 0
6109 11:03:46.036247 DQ_SEMI_OPEN = 1
6110 11:03:46.039121 CA_SEMI_OPEN = 1
6111 11:03:46.043035 CA_FULL_RATE = 0
6112 11:03:46.046156 DQ_CKDIV4_EN = 0
6113 11:03:46.049515 CA_CKDIV4_EN = 1
6114 11:03:46.052613 CA_PREDIV_EN = 0
6115 11:03:46.052687 PH8_DLY = 0
6116 11:03:46.055690 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6117 11:03:46.059360 DQ_AAMCK_DIV = 0
6118 11:03:46.062548 CA_AAMCK_DIV = 0
6119 11:03:46.065729 CA_ADMCK_DIV = 4
6120 11:03:46.068885 DQ_TRACK_CA_EN = 0
6121 11:03:46.068975 CA_PICK = 800
6122 11:03:46.072734 CA_MCKIO = 400
6123 11:03:46.075999 MCKIO_SEMI = 400
6124 11:03:46.079520 PLL_FREQ = 3016
6125 11:03:46.082334 DQ_UI_PI_RATIO = 32
6126 11:03:46.086164 CA_UI_PI_RATIO = 32
6127 11:03:46.088893 ===================================
6128 11:03:46.092678 ===================================
6129 11:03:46.095872 memory_type:LPDDR4
6130 11:03:46.095951 GP_NUM : 10
6131 11:03:46.098964 SRAM_EN : 1
6132 11:03:46.099030 MD32_EN : 0
6133 11:03:46.102074 ===================================
6134 11:03:46.105458 [ANA_INIT] >>>>>>>>>>>>>>
6135 11:03:46.109016 <<<<<< [CONFIGURE PHASE]: ANA_TX
6136 11:03:46.112227 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6137 11:03:46.115631 ===================================
6138 11:03:46.119169 data_rate = 800,PCW = 0X7400
6139 11:03:46.122432 ===================================
6140 11:03:46.125173 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6141 11:03:46.129031 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6142 11:03:46.142487 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6143 11:03:46.145624 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6144 11:03:46.149043 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6145 11:03:46.152430 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6146 11:03:46.155390 [ANA_INIT] flow start
6147 11:03:46.158768 [ANA_INIT] PLL >>>>>>>>
6148 11:03:46.158846 [ANA_INIT] PLL <<<<<<<<
6149 11:03:46.161833 [ANA_INIT] MIDPI >>>>>>>>
6150 11:03:46.165438 [ANA_INIT] MIDPI <<<<<<<<
6151 11:03:46.165518 [ANA_INIT] DLL >>>>>>>>
6152 11:03:46.168595 [ANA_INIT] flow end
6153 11:03:46.171995 ============ LP4 DIFF to SE enter ============
6154 11:03:46.175623 ============ LP4 DIFF to SE exit ============
6155 11:03:46.178559 [ANA_INIT] <<<<<<<<<<<<<
6156 11:03:46.182395 [Flow] Enable top DCM control >>>>>
6157 11:03:46.185430 [Flow] Enable top DCM control <<<<<
6158 11:03:46.188629 Enable DLL master slave shuffle
6159 11:03:46.195702 ==============================================================
6160 11:03:46.195803 Gating Mode config
6161 11:03:46.202283 ==============================================================
6162 11:03:46.202373 Config description:
6163 11:03:46.211877 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6164 11:03:46.219160 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6165 11:03:46.225950 SELPH_MODE 0: By rank 1: By Phase
6166 11:03:46.228665 ==============================================================
6167 11:03:46.232476 GAT_TRACK_EN = 0
6168 11:03:46.235375 RX_GATING_MODE = 2
6169 11:03:46.239231 RX_GATING_TRACK_MODE = 2
6170 11:03:46.242404 SELPH_MODE = 1
6171 11:03:46.245457 PICG_EARLY_EN = 1
6172 11:03:46.248894 VALID_LAT_VALUE = 1
6173 11:03:46.255285 ==============================================================
6174 11:03:46.258729 Enter into Gating configuration >>>>
6175 11:03:46.262513 Exit from Gating configuration <<<<
6176 11:03:46.262592 Enter into DVFS_PRE_config >>>>>
6177 11:03:46.275676 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6178 11:03:46.278986 Exit from DVFS_PRE_config <<<<<
6179 11:03:46.282492 Enter into PICG configuration >>>>
6180 11:03:46.285683 Exit from PICG configuration <<<<
6181 11:03:46.285785 [RX_INPUT] configuration >>>>>
6182 11:03:46.288771 [RX_INPUT] configuration <<<<<
6183 11:03:46.295315 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6184 11:03:46.298974 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6185 11:03:46.305545 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6186 11:03:46.311823 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6187 11:03:46.318808 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6188 11:03:46.325687 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6189 11:03:46.329052 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6190 11:03:46.331836 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6191 11:03:46.339139 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6192 11:03:46.342313 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6193 11:03:46.345265 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6194 11:03:46.348768 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6195 11:03:46.352239 ===================================
6196 11:03:46.355264 LPDDR4 DRAM CONFIGURATION
6197 11:03:46.358690 ===================================
6198 11:03:46.361912 EX_ROW_EN[0] = 0x0
6199 11:03:46.362017 EX_ROW_EN[1] = 0x0
6200 11:03:46.365169 LP4Y_EN = 0x0
6201 11:03:46.365250 WORK_FSP = 0x0
6202 11:03:46.368435 WL = 0x2
6203 11:03:46.368516 RL = 0x2
6204 11:03:46.372130 BL = 0x2
6205 11:03:46.372202 RPST = 0x0
6206 11:03:46.375538 RD_PRE = 0x0
6207 11:03:46.375612 WR_PRE = 0x1
6208 11:03:46.378635 WR_PST = 0x0
6209 11:03:46.378736 DBI_WR = 0x0
6210 11:03:46.381715 DBI_RD = 0x0
6211 11:03:46.381815 OTF = 0x1
6212 11:03:46.384993 ===================================
6213 11:03:46.392060 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6214 11:03:46.395185 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6215 11:03:46.399079 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6216 11:03:46.401728 ===================================
6217 11:03:46.405008 LPDDR4 DRAM CONFIGURATION
6218 11:03:46.408859 ===================================
6219 11:03:46.411735 EX_ROW_EN[0] = 0x10
6220 11:03:46.411810 EX_ROW_EN[1] = 0x0
6221 11:03:46.415230 LP4Y_EN = 0x0
6222 11:03:46.415313 WORK_FSP = 0x0
6223 11:03:46.418455 WL = 0x2
6224 11:03:46.418522 RL = 0x2
6225 11:03:46.421686 BL = 0x2
6226 11:03:46.421789 RPST = 0x0
6227 11:03:46.424694 RD_PRE = 0x0
6228 11:03:46.424786 WR_PRE = 0x1
6229 11:03:46.428562 WR_PST = 0x0
6230 11:03:46.428657 DBI_WR = 0x0
6231 11:03:46.431997 DBI_RD = 0x0
6232 11:03:46.432065 OTF = 0x1
6233 11:03:46.435028 ===================================
6234 11:03:46.441624 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6235 11:03:46.446173 nWR fixed to 30
6236 11:03:46.449676 [ModeRegInit_LP4] CH0 RK0
6237 11:03:46.449770 [ModeRegInit_LP4] CH0 RK1
6238 11:03:46.452876 [ModeRegInit_LP4] CH1 RK0
6239 11:03:46.456238 [ModeRegInit_LP4] CH1 RK1
6240 11:03:46.456331 match AC timing 19
6241 11:03:46.462904 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6242 11:03:46.466203 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6243 11:03:46.469486 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6244 11:03:46.476588 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6245 11:03:46.479919 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6246 11:03:46.480017 ==
6247 11:03:46.482927 Dram Type= 6, Freq= 0, CH_0, rank 0
6248 11:03:46.486290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6249 11:03:46.486383 ==
6250 11:03:46.492537 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6251 11:03:46.499537 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6252 11:03:46.502694 [CA 0] Center 36 (8~64) winsize 57
6253 11:03:46.506345 [CA 1] Center 36 (8~64) winsize 57
6254 11:03:46.509652 [CA 2] Center 36 (8~64) winsize 57
6255 11:03:46.509738 [CA 3] Center 36 (8~64) winsize 57
6256 11:03:46.512810 [CA 4] Center 36 (8~64) winsize 57
6257 11:03:46.516670 [CA 5] Center 36 (8~64) winsize 57
6258 11:03:46.516745
6259 11:03:46.522917 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6260 11:03:46.523000
6261 11:03:46.525980 [CATrainingPosCal] consider 1 rank data
6262 11:03:46.529165 u2DelayCellTimex100 = 270/100 ps
6263 11:03:46.532274 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 11:03:46.536090 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 11:03:46.539832 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 11:03:46.542424 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 11:03:46.545555 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 11:03:46.549421 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 11:03:46.549490
6270 11:03:46.552522 CA PerBit enable=1, Macro0, CA PI delay=36
6271 11:03:46.552589
6272 11:03:46.555620 [CBTSetCACLKResult] CA Dly = 36
6273 11:03:46.559000 CS Dly: 1 (0~32)
6274 11:03:46.559091 ==
6275 11:03:46.562635 Dram Type= 6, Freq= 0, CH_0, rank 1
6276 11:03:46.566103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6277 11:03:46.566174 ==
6278 11:03:46.573030 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6279 11:03:46.575675 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6280 11:03:46.579057 [CA 0] Center 36 (8~64) winsize 57
6281 11:03:46.582225 [CA 1] Center 36 (8~64) winsize 57
6282 11:03:46.585862 [CA 2] Center 36 (8~64) winsize 57
6283 11:03:46.589079 [CA 3] Center 36 (8~64) winsize 57
6284 11:03:46.592193 [CA 4] Center 36 (8~64) winsize 57
6285 11:03:46.595792 [CA 5] Center 36 (8~64) winsize 57
6286 11:03:46.595871
6287 11:03:46.599283 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6288 11:03:46.599363
6289 11:03:46.602143 [CATrainingPosCal] consider 2 rank data
6290 11:03:46.605959 u2DelayCellTimex100 = 270/100 ps
6291 11:03:46.608950 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 11:03:46.612612 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 11:03:46.615751 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 11:03:46.622057 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 11:03:46.625851 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 11:03:46.629034 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 11:03:46.629115
6298 11:03:46.632281 CA PerBit enable=1, Macro0, CA PI delay=36
6299 11:03:46.632360
6300 11:03:46.635574 [CBTSetCACLKResult] CA Dly = 36
6301 11:03:46.635653 CS Dly: 1 (0~32)
6302 11:03:46.635747
6303 11:03:46.639326 ----->DramcWriteLeveling(PI) begin...
6304 11:03:46.639411 ==
6305 11:03:46.642256 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 11:03:46.649278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 11:03:46.649358 ==
6308 11:03:46.652102 Write leveling (Byte 0): 40 => 8
6309 11:03:46.655883 Write leveling (Byte 1): 40 => 8
6310 11:03:46.655967 DramcWriteLeveling(PI) end<-----
6311 11:03:46.656043
6312 11:03:46.658886 ==
6313 11:03:46.662212 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 11:03:46.665410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 11:03:46.665491 ==
6316 11:03:46.669360 [Gating] SW mode calibration
6317 11:03:46.675358 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6318 11:03:46.678610 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6319 11:03:46.685343 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6320 11:03:46.689127 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6321 11:03:46.692031 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6322 11:03:46.699001 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6323 11:03:46.701879 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6324 11:03:46.705767 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6325 11:03:46.711963 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 11:03:46.715031 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6327 11:03:46.718581 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6328 11:03:46.721893 Total UI for P1: 0, mck2ui 16
6329 11:03:46.725028 best dqsien dly found for B0: ( 0, 14, 24)
6330 11:03:46.728719 Total UI for P1: 0, mck2ui 16
6331 11:03:46.731628 best dqsien dly found for B1: ( 0, 14, 24)
6332 11:03:46.735244 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6333 11:03:46.738654 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6334 11:03:46.738736
6335 11:03:46.745716 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6336 11:03:46.748784 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6337 11:03:46.748867 [Gating] SW calibration Done
6338 11:03:46.752073 ==
6339 11:03:46.755126 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 11:03:46.758800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 11:03:46.758881 ==
6342 11:03:46.758959 RX Vref Scan: 0
6343 11:03:46.759032
6344 11:03:46.761711 RX Vref 0 -> 0, step: 1
6345 11:03:46.761816
6346 11:03:46.765279 RX Delay -410 -> 252, step: 16
6347 11:03:46.768283 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6348 11:03:46.771831 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6349 11:03:46.778207 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6350 11:03:46.781944 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6351 11:03:46.785222 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6352 11:03:46.788210 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6353 11:03:46.795458 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6354 11:03:46.798580 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6355 11:03:46.801878 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6356 11:03:46.804976 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6357 11:03:46.812071 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6358 11:03:46.815223 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6359 11:03:46.818956 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6360 11:03:46.821471 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6361 11:03:46.828182 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6362 11:03:46.831625 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6363 11:03:46.831730 ==
6364 11:03:46.835218 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 11:03:46.838479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 11:03:46.838556 ==
6367 11:03:46.842023 DQS Delay:
6368 11:03:46.842091 DQS0 = 27, DQS1 = 35
6369 11:03:46.845676 DQM Delay:
6370 11:03:46.845746 DQM0 = 9, DQM1 = 11
6371 11:03:46.845803 DQ Delay:
6372 11:03:46.848528 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6373 11:03:46.851650 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6374 11:03:46.854938 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6375 11:03:46.858034 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6376 11:03:46.858106
6377 11:03:46.858167
6378 11:03:46.858220 ==
6379 11:03:46.861571 Dram Type= 6, Freq= 0, CH_0, rank 0
6380 11:03:46.868100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6381 11:03:46.868203 ==
6382 11:03:46.868292
6383 11:03:46.868373
6384 11:03:46.868452 TX Vref Scan disable
6385 11:03:46.871654 == TX Byte 0 ==
6386 11:03:46.874552 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6387 11:03:46.878096 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6388 11:03:46.881815 == TX Byte 1 ==
6389 11:03:46.884611 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6390 11:03:46.888252 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6391 11:03:46.888322 ==
6392 11:03:46.891355 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 11:03:46.898387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 11:03:46.898459 ==
6395 11:03:46.898524
6396 11:03:46.898579
6397 11:03:46.898630 TX Vref Scan disable
6398 11:03:46.901460 == TX Byte 0 ==
6399 11:03:46.904973 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6400 11:03:46.908252 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6401 11:03:46.911280 == TX Byte 1 ==
6402 11:03:46.914540 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6403 11:03:46.917829 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6404 11:03:46.917895
6405 11:03:46.921497 [DATLAT]
6406 11:03:46.921586 Freq=400, CH0 RK0
6407 11:03:46.921667
6408 11:03:46.924651 DATLAT Default: 0xf
6409 11:03:46.924745 0, 0xFFFF, sum = 0
6410 11:03:46.927934 1, 0xFFFF, sum = 0
6411 11:03:46.928002 2, 0xFFFF, sum = 0
6412 11:03:46.931363 3, 0xFFFF, sum = 0
6413 11:03:46.931453 4, 0xFFFF, sum = 0
6414 11:03:46.934655 5, 0xFFFF, sum = 0
6415 11:03:46.934723 6, 0xFFFF, sum = 0
6416 11:03:46.937822 7, 0xFFFF, sum = 0
6417 11:03:46.937887 8, 0xFFFF, sum = 0
6418 11:03:46.941597 9, 0xFFFF, sum = 0
6419 11:03:46.941700 10, 0xFFFF, sum = 0
6420 11:03:46.944727 11, 0xFFFF, sum = 0
6421 11:03:46.947672 12, 0xFFFF, sum = 0
6422 11:03:46.947781 13, 0x0, sum = 1
6423 11:03:46.950804 14, 0x0, sum = 2
6424 11:03:46.950871 15, 0x0, sum = 3
6425 11:03:46.954449 16, 0x0, sum = 4
6426 11:03:46.954547 best_step = 14
6427 11:03:46.954629
6428 11:03:46.954710 ==
6429 11:03:46.957459 Dram Type= 6, Freq= 0, CH_0, rank 0
6430 11:03:46.961162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 11:03:46.961234 ==
6432 11:03:46.963970 RX Vref Scan: 1
6433 11:03:46.964041
6434 11:03:46.968044 RX Vref 0 -> 0, step: 1
6435 11:03:46.968113
6436 11:03:46.968190 RX Delay -311 -> 252, step: 8
6437 11:03:46.968291
6438 11:03:46.970776 Set Vref, RX VrefLevel [Byte0]: 53
6439 11:03:46.973942 [Byte1]: 49
6440 11:03:46.979309
6441 11:03:46.979382 Final RX Vref Byte 0 = 53 to rank0
6442 11:03:46.982776 Final RX Vref Byte 1 = 49 to rank0
6443 11:03:46.986154 Final RX Vref Byte 0 = 53 to rank1
6444 11:03:46.989638 Final RX Vref Byte 1 = 49 to rank1==
6445 11:03:46.992746 Dram Type= 6, Freq= 0, CH_0, rank 0
6446 11:03:46.999225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 11:03:46.999328 ==
6448 11:03:46.999413 DQS Delay:
6449 11:03:46.999494 DQS0 = 28, DQS1 = 36
6450 11:03:47.002938 DQM Delay:
6451 11:03:47.003033 DQM0 = 11, DQM1 = 12
6452 11:03:47.006279 DQ Delay:
6453 11:03:47.009550 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6454 11:03:47.009644 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6455 11:03:47.012579 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6456 11:03:47.015883 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6457 11:03:47.015978
6458 11:03:47.016061
6459 11:03:47.026386 [DQSOSCAuto] RK0, (LSB)MR18= 0xd6c3, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 383 ps
6460 11:03:47.029312 CH0 RK0: MR19=C0C, MR18=D6C3
6461 11:03:47.035824 CH0_RK0: MR19=0xC0C, MR18=0xD6C3, DQSOSC=383, MR23=63, INC=402, DEC=268
6462 11:03:47.035927 ==
6463 11:03:47.039654 Dram Type= 6, Freq= 0, CH_0, rank 1
6464 11:03:47.042653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 11:03:47.042752 ==
6466 11:03:47.045792 [Gating] SW mode calibration
6467 11:03:47.052586 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6468 11:03:47.055908 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6469 11:03:47.063302 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6470 11:03:47.066292 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6471 11:03:47.069680 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6472 11:03:47.076141 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6473 11:03:47.079624 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6474 11:03:47.082551 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 11:03:47.089719 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 11:03:47.092736 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 11:03:47.096157 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6478 11:03:47.099160 Total UI for P1: 0, mck2ui 16
6479 11:03:47.102573 best dqsien dly found for B0: ( 0, 14, 24)
6480 11:03:47.106046 Total UI for P1: 0, mck2ui 16
6481 11:03:47.108897 best dqsien dly found for B1: ( 0, 14, 24)
6482 11:03:47.112420 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6483 11:03:47.118736 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6484 11:03:47.118821
6485 11:03:47.121987 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6486 11:03:47.125376 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6487 11:03:47.128976 [Gating] SW calibration Done
6488 11:03:47.129074 ==
6489 11:03:47.132184 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 11:03:47.135287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 11:03:47.135384 ==
6492 11:03:47.138542 RX Vref Scan: 0
6493 11:03:47.138637
6494 11:03:47.138720 RX Vref 0 -> 0, step: 1
6495 11:03:47.138799
6496 11:03:47.142550 RX Delay -410 -> 252, step: 16
6497 11:03:47.145673 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6498 11:03:47.152542 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6499 11:03:47.155538 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6500 11:03:47.158694 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6501 11:03:47.161733 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6502 11:03:47.168991 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6503 11:03:47.172108 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6504 11:03:47.175353 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6505 11:03:47.178578 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6506 11:03:47.184931 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6507 11:03:47.188210 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6508 11:03:47.191767 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6509 11:03:47.195034 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6510 11:03:47.201827 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6511 11:03:47.204817 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6512 11:03:47.208400 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6513 11:03:47.208513 ==
6514 11:03:47.211350 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 11:03:47.218492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 11:03:47.218598 ==
6517 11:03:47.218684 DQS Delay:
6518 11:03:47.221990 DQS0 = 19, DQS1 = 35
6519 11:03:47.222108 DQM Delay:
6520 11:03:47.222192 DQM0 = 5, DQM1 = 12
6521 11:03:47.225041 DQ Delay:
6522 11:03:47.225136 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6523 11:03:47.228306 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6524 11:03:47.231909 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6525 11:03:47.235290 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6526 11:03:47.235419
6527 11:03:47.235526
6528 11:03:47.238175 ==
6529 11:03:47.241788 Dram Type= 6, Freq= 0, CH_0, rank 1
6530 11:03:47.244894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6531 11:03:47.244998 ==
6532 11:03:47.245083
6533 11:03:47.245163
6534 11:03:47.248424 TX Vref Scan disable
6535 11:03:47.248521 == TX Byte 0 ==
6536 11:03:47.251558 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6537 11:03:47.255291 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6538 11:03:47.258457 == TX Byte 1 ==
6539 11:03:47.261558 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6540 11:03:47.265248 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6541 11:03:47.268350 ==
6542 11:03:47.271432 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 11:03:47.275252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 11:03:47.275355 ==
6545 11:03:47.275439
6546 11:03:47.275518
6547 11:03:47.278245 TX Vref Scan disable
6548 11:03:47.278342 == TX Byte 0 ==
6549 11:03:47.281625 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6550 11:03:47.288305 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6551 11:03:47.288403 == TX Byte 1 ==
6552 11:03:47.291494 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6553 11:03:47.295469 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6554 11:03:47.295565
6555 11:03:47.298322 [DATLAT]
6556 11:03:47.298416 Freq=400, CH0 RK1
6557 11:03:47.298499
6558 11:03:47.301487 DATLAT Default: 0xe
6559 11:03:47.301580 0, 0xFFFF, sum = 0
6560 11:03:47.304751 1, 0xFFFF, sum = 0
6561 11:03:47.304850 2, 0xFFFF, sum = 0
6562 11:03:47.308530 3, 0xFFFF, sum = 0
6563 11:03:47.308653 4, 0xFFFF, sum = 0
6564 11:03:47.311726 5, 0xFFFF, sum = 0
6565 11:03:47.311822 6, 0xFFFF, sum = 0
6566 11:03:47.314666 7, 0xFFFF, sum = 0
6567 11:03:47.318407 8, 0xFFFF, sum = 0
6568 11:03:47.318503 9, 0xFFFF, sum = 0
6569 11:03:47.321602 10, 0xFFFF, sum = 0
6570 11:03:47.321696 11, 0xFFFF, sum = 0
6571 11:03:47.325183 12, 0xFFFF, sum = 0
6572 11:03:47.325277 13, 0x0, sum = 1
6573 11:03:47.327925 14, 0x0, sum = 2
6574 11:03:47.328025 15, 0x0, sum = 3
6575 11:03:47.332019 16, 0x0, sum = 4
6576 11:03:47.332118 best_step = 14
6577 11:03:47.332204
6578 11:03:47.332285 ==
6579 11:03:47.334766 Dram Type= 6, Freq= 0, CH_0, rank 1
6580 11:03:47.338020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6581 11:03:47.338119 ==
6582 11:03:47.341523 RX Vref Scan: 0
6583 11:03:47.341620
6584 11:03:47.345092 RX Vref 0 -> 0, step: 1
6585 11:03:47.345189
6586 11:03:47.345275 RX Delay -311 -> 252, step: 8
6587 11:03:47.353371 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6588 11:03:47.356620 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6589 11:03:47.360085 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6590 11:03:47.363601 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6591 11:03:47.370315 iDelay=217, Bit 4, Center -12 (-239 ~ 216) 456
6592 11:03:47.373221 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6593 11:03:47.376797 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6594 11:03:47.379930 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6595 11:03:47.386706 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6596 11:03:47.389904 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6597 11:03:47.393156 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6598 11:03:47.396944 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6599 11:03:47.403846 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6600 11:03:47.406374 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6601 11:03:47.409737 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6602 11:03:47.416404 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6603 11:03:47.416507 ==
6604 11:03:47.419602 Dram Type= 6, Freq= 0, CH_0, rank 1
6605 11:03:47.423532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 11:03:47.423632 ==
6607 11:03:47.423717 DQS Delay:
6608 11:03:47.426463 DQS0 = 24, DQS1 = 32
6609 11:03:47.426561 DQM Delay:
6610 11:03:47.429649 DQM0 = 9, DQM1 = 9
6611 11:03:47.429745 DQ Delay:
6612 11:03:47.433407 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6613 11:03:47.436258 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6614 11:03:47.439465 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =0
6615 11:03:47.442661 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6616 11:03:47.442760
6617 11:03:47.442845
6618 11:03:47.449400 [DQSOSCAuto] RK1, (LSB)MR18= 0xc867, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 385 ps
6619 11:03:47.452988 CH0 RK1: MR19=C0C, MR18=C867
6620 11:03:47.459505 CH0_RK1: MR19=0xC0C, MR18=0xC867, DQSOSC=385, MR23=63, INC=398, DEC=265
6621 11:03:47.462667 [RxdqsGatingPostProcess] freq 400
6622 11:03:47.465800 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6623 11:03:47.469675 best DQS0 dly(2T, 0.5T) = (0, 10)
6624 11:03:47.472479 best DQS1 dly(2T, 0.5T) = (0, 10)
6625 11:03:47.475898 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6626 11:03:47.479310 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6627 11:03:47.483068 best DQS0 dly(2T, 0.5T) = (0, 10)
6628 11:03:47.486221 best DQS1 dly(2T, 0.5T) = (0, 10)
6629 11:03:47.489667 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6630 11:03:47.492851 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6631 11:03:47.495800 Pre-setting of DQS Precalculation
6632 11:03:47.499021 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6633 11:03:47.503118 ==
6634 11:03:47.506425 Dram Type= 6, Freq= 0, CH_1, rank 0
6635 11:03:47.509537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6636 11:03:47.509637 ==
6637 11:03:47.513149 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6638 11:03:47.519043 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6639 11:03:47.522493 [CA 0] Center 36 (8~64) winsize 57
6640 11:03:47.526222 [CA 1] Center 36 (8~64) winsize 57
6641 11:03:47.529435 [CA 2] Center 36 (8~64) winsize 57
6642 11:03:47.532778 [CA 3] Center 36 (8~64) winsize 57
6643 11:03:47.535945 [CA 4] Center 36 (8~64) winsize 57
6644 11:03:47.539074 [CA 5] Center 36 (8~64) winsize 57
6645 11:03:47.539172
6646 11:03:47.542840 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6647 11:03:47.542939
6648 11:03:47.545843 [CATrainingPosCal] consider 1 rank data
6649 11:03:47.549213 u2DelayCellTimex100 = 270/100 ps
6650 11:03:47.552776 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 11:03:47.555620 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 11:03:47.559015 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 11:03:47.562184 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 11:03:47.566089 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 11:03:47.572345 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 11:03:47.572444
6657 11:03:47.575876 CA PerBit enable=1, Macro0, CA PI delay=36
6658 11:03:47.575974
6659 11:03:47.579212 [CBTSetCACLKResult] CA Dly = 36
6660 11:03:47.579309 CS Dly: 1 (0~32)
6661 11:03:47.579392 ==
6662 11:03:47.582783 Dram Type= 6, Freq= 0, CH_1, rank 1
6663 11:03:47.585583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6664 11:03:47.589108 ==
6665 11:03:47.592103 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6666 11:03:47.598774 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6667 11:03:47.602166 [CA 0] Center 36 (8~64) winsize 57
6668 11:03:47.605828 [CA 1] Center 36 (8~64) winsize 57
6669 11:03:47.608739 [CA 2] Center 36 (8~64) winsize 57
6670 11:03:47.612324 [CA 3] Center 36 (8~64) winsize 57
6671 11:03:47.615588 [CA 4] Center 36 (8~64) winsize 57
6672 11:03:47.618813 [CA 5] Center 36 (8~64) winsize 57
6673 11:03:47.618911
6674 11:03:47.622088 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6675 11:03:47.622185
6676 11:03:47.625250 [CATrainingPosCal] consider 2 rank data
6677 11:03:47.628765 u2DelayCellTimex100 = 270/100 ps
6678 11:03:47.632165 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 11:03:47.635917 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 11:03:47.639032 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 11:03:47.642336 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 11:03:47.645399 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 11:03:47.648780 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 11:03:47.648878
6685 11:03:47.651962 CA PerBit enable=1, Macro0, CA PI delay=36
6686 11:03:47.655263
6687 11:03:47.655359 [CBTSetCACLKResult] CA Dly = 36
6688 11:03:47.659051 CS Dly: 1 (0~32)
6689 11:03:47.659147
6690 11:03:47.662257 ----->DramcWriteLeveling(PI) begin...
6691 11:03:47.662354 ==
6692 11:03:47.665632 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 11:03:47.668986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 11:03:47.669085 ==
6695 11:03:47.672444 Write leveling (Byte 0): 40 => 8
6696 11:03:47.675295 Write leveling (Byte 1): 40 => 8
6697 11:03:47.679157 DramcWriteLeveling(PI) end<-----
6698 11:03:47.679257
6699 11:03:47.679342 ==
6700 11:03:47.682464 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 11:03:47.685656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 11:03:47.685756 ==
6703 11:03:47.688671 [Gating] SW mode calibration
6704 11:03:47.695926 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6705 11:03:47.702244 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6706 11:03:47.705361 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6707 11:03:47.709135 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6708 11:03:47.715600 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6709 11:03:47.719022 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6710 11:03:47.722256 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6711 11:03:47.728823 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6712 11:03:47.732458 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 11:03:47.735597 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6714 11:03:47.741809 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6715 11:03:47.745517 Total UI for P1: 0, mck2ui 16
6716 11:03:47.748580 best dqsien dly found for B0: ( 0, 14, 24)
6717 11:03:47.751792 Total UI for P1: 0, mck2ui 16
6718 11:03:47.755435 best dqsien dly found for B1: ( 0, 14, 24)
6719 11:03:47.758291 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6720 11:03:47.761995 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6721 11:03:47.762100
6722 11:03:47.765202 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6723 11:03:47.768838 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6724 11:03:47.771560 [Gating] SW calibration Done
6725 11:03:47.771661 ==
6726 11:03:47.775536 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 11:03:47.778049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 11:03:47.778129 ==
6729 11:03:47.782014 RX Vref Scan: 0
6730 11:03:47.782083
6731 11:03:47.784600 RX Vref 0 -> 0, step: 1
6732 11:03:47.784669
6733 11:03:47.784741 RX Delay -410 -> 252, step: 16
6734 11:03:47.791927 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6735 11:03:47.794902 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6736 11:03:47.798832 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6737 11:03:47.801964 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6738 11:03:47.808143 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6739 11:03:47.811817 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6740 11:03:47.815198 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6741 11:03:47.818448 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6742 11:03:47.824941 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6743 11:03:47.828117 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6744 11:03:47.831772 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6745 11:03:47.834756 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6746 11:03:47.841337 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6747 11:03:47.844819 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6748 11:03:47.848216 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6749 11:03:47.854415 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6750 11:03:47.854495 ==
6751 11:03:47.857813 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 11:03:47.861745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 11:03:47.861837 ==
6754 11:03:47.861918 DQS Delay:
6755 11:03:47.864430 DQS0 = 35, DQS1 = 35
6756 11:03:47.864500 DQM Delay:
6757 11:03:47.868032 DQM0 = 16, DQM1 = 13
6758 11:03:47.868123 DQ Delay:
6759 11:03:47.871391 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6760 11:03:47.874613 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6761 11:03:47.877842 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6762 11:03:47.880929 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6763 11:03:47.880997
6764 11:03:47.881084
6765 11:03:47.881170 ==
6766 11:03:47.884324 Dram Type= 6, Freq= 0, CH_1, rank 0
6767 11:03:47.888212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6768 11:03:47.888283 ==
6769 11:03:47.888354
6770 11:03:47.888420
6771 11:03:47.891094 TX Vref Scan disable
6772 11:03:47.894551 == TX Byte 0 ==
6773 11:03:47.898342 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6774 11:03:47.900984 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6775 11:03:47.901058 == TX Byte 1 ==
6776 11:03:47.907872 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6777 11:03:47.911254 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6778 11:03:47.911330 ==
6779 11:03:47.914501 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 11:03:47.918227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 11:03:47.918320 ==
6782 11:03:47.918391
6783 11:03:47.918443
6784 11:03:47.921346 TX Vref Scan disable
6785 11:03:47.925048 == TX Byte 0 ==
6786 11:03:47.927931 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6787 11:03:47.931568 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6788 11:03:47.931644 == TX Byte 1 ==
6789 11:03:47.938236 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6790 11:03:47.941103 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6791 11:03:47.941192
6792 11:03:47.941249 [DATLAT]
6793 11:03:47.944512 Freq=400, CH1 RK0
6794 11:03:47.944586
6795 11:03:47.944644 DATLAT Default: 0xf
6796 11:03:47.947878 0, 0xFFFF, sum = 0
6797 11:03:47.947955 1, 0xFFFF, sum = 0
6798 11:03:47.951857 2, 0xFFFF, sum = 0
6799 11:03:47.951963 3, 0xFFFF, sum = 0
6800 11:03:47.954978 4, 0xFFFF, sum = 0
6801 11:03:47.955054 5, 0xFFFF, sum = 0
6802 11:03:47.958255 6, 0xFFFF, sum = 0
6803 11:03:47.961141 7, 0xFFFF, sum = 0
6804 11:03:47.961233 8, 0xFFFF, sum = 0
6805 11:03:47.964802 9, 0xFFFF, sum = 0
6806 11:03:47.964896 10, 0xFFFF, sum = 0
6807 11:03:47.968161 11, 0xFFFF, sum = 0
6808 11:03:47.968243 12, 0xFFFF, sum = 0
6809 11:03:47.971286 13, 0x0, sum = 1
6810 11:03:47.971365 14, 0x0, sum = 2
6811 11:03:47.974455 15, 0x0, sum = 3
6812 11:03:47.974555 16, 0x0, sum = 4
6813 11:03:47.974639 best_step = 14
6814 11:03:47.977817
6815 11:03:47.977918 ==
6816 11:03:47.981640 Dram Type= 6, Freq= 0, CH_1, rank 0
6817 11:03:47.984732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 11:03:47.984870 ==
6819 11:03:47.984929 RX Vref Scan: 1
6820 11:03:47.984983
6821 11:03:47.987760 RX Vref 0 -> 0, step: 1
6822 11:03:47.987834
6823 11:03:47.990809 RX Delay -311 -> 252, step: 8
6824 11:03:47.990884
6825 11:03:47.994568 Set Vref, RX VrefLevel [Byte0]: 53
6826 11:03:47.997853 [Byte1]: 52
6827 11:03:48.001567
6828 11:03:48.001669 Final RX Vref Byte 0 = 53 to rank0
6829 11:03:48.005010 Final RX Vref Byte 1 = 52 to rank0
6830 11:03:48.008469 Final RX Vref Byte 0 = 53 to rank1
6831 11:03:48.011882 Final RX Vref Byte 1 = 52 to rank1==
6832 11:03:48.014931 Dram Type= 6, Freq= 0, CH_1, rank 0
6833 11:03:48.021712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 11:03:48.021809 ==
6835 11:03:48.021880 DQS Delay:
6836 11:03:48.021934 DQS0 = 32, DQS1 = 32
6837 11:03:48.024795 DQM Delay:
6838 11:03:48.024869 DQM0 = 13, DQM1 = 11
6839 11:03:48.028490 DQ Delay:
6840 11:03:48.031612 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6841 11:03:48.031687 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6842 11:03:48.034597 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6843 11:03:48.037943 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6844 11:03:48.038040
6845 11:03:48.038110
6846 11:03:48.048107 [DQSOSCAuto] RK0, (LSB)MR18= 0x99d0, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 390 ps
6847 11:03:48.051250 CH1 RK0: MR19=C0C, MR18=99D0
6848 11:03:48.058450 CH1_RK0: MR19=0xC0C, MR18=0x99D0, DQSOSC=384, MR23=63, INC=400, DEC=267
6849 11:03:48.058535 ==
6850 11:03:48.061638 Dram Type= 6, Freq= 0, CH_1, rank 1
6851 11:03:48.064678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 11:03:48.064829 ==
6853 11:03:48.068019 [Gating] SW mode calibration
6854 11:03:48.074758 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6855 11:03:48.077872 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6856 11:03:48.084844 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6857 11:03:48.088068 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6858 11:03:48.091707 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6859 11:03:48.098332 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6860 11:03:48.101546 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6861 11:03:48.104660 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6862 11:03:48.111403 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 11:03:48.114639 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6864 11:03:48.117960 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6865 11:03:48.121805 Total UI for P1: 0, mck2ui 16
6866 11:03:48.124896 best dqsien dly found for B0: ( 0, 14, 24)
6867 11:03:48.127931 Total UI for P1: 0, mck2ui 16
6868 11:03:48.131335 best dqsien dly found for B1: ( 0, 14, 24)
6869 11:03:48.134518 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6870 11:03:48.137825 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6871 11:03:48.137955
6872 11:03:48.144374 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6873 11:03:48.147902 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6874 11:03:48.151158 [Gating] SW calibration Done
6875 11:03:48.151242 ==
6876 11:03:48.154747 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 11:03:48.157968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 11:03:48.158092 ==
6879 11:03:48.158179 RX Vref Scan: 0
6880 11:03:48.158259
6881 11:03:48.160922 RX Vref 0 -> 0, step: 1
6882 11:03:48.160999
6883 11:03:48.164790 RX Delay -410 -> 252, step: 16
6884 11:03:48.168194 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6885 11:03:48.174063 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6886 11:03:48.177638 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6887 11:03:48.180806 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6888 11:03:48.184274 iDelay=230, Bit 4, Center -11 (-234 ~ 213) 448
6889 11:03:48.188361 iDelay=230, Bit 5, Center 5 (-218 ~ 229) 448
6890 11:03:48.194777 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6891 11:03:48.197951 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6892 11:03:48.201065 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6893 11:03:48.204385 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6894 11:03:48.210986 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6895 11:03:48.214725 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6896 11:03:48.217553 iDelay=230, Bit 12, Center -3 (-234 ~ 229) 464
6897 11:03:48.221021 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6898 11:03:48.228126 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6899 11:03:48.231305 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6900 11:03:48.231438 ==
6901 11:03:48.234513 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 11:03:48.237780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 11:03:48.237884 ==
6904 11:03:48.241064 DQS Delay:
6905 11:03:48.241163 DQS0 = 35, DQS1 = 35
6906 11:03:48.244605 DQM Delay:
6907 11:03:48.244687 DQM0 = 21, DQM1 = 18
6908 11:03:48.244745 DQ Delay:
6909 11:03:48.247989 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6910 11:03:48.251035 DQ4 =24, DQ5 =40, DQ6 =32, DQ7 =16
6911 11:03:48.254731 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6912 11:03:48.257874 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6913 11:03:48.257965
6914 11:03:48.258049
6915 11:03:48.258104 ==
6916 11:03:48.261185 Dram Type= 6, Freq= 0, CH_1, rank 1
6917 11:03:48.267722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6918 11:03:48.267818 ==
6919 11:03:48.267877
6920 11:03:48.267929
6921 11:03:48.267980 TX Vref Scan disable
6922 11:03:48.270764 == TX Byte 0 ==
6923 11:03:48.274666 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6924 11:03:48.277969 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6925 11:03:48.281200 == TX Byte 1 ==
6926 11:03:48.284386 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6927 11:03:48.287310 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6928 11:03:48.287421 ==
6929 11:03:48.290787 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 11:03:48.297443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 11:03:48.297543 ==
6932 11:03:48.297617
6933 11:03:48.297684
6934 11:03:48.297734 TX Vref Scan disable
6935 11:03:48.300597 == TX Byte 0 ==
6936 11:03:48.304170 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6937 11:03:48.307616 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6938 11:03:48.310876 == TX Byte 1 ==
6939 11:03:48.314099 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6940 11:03:48.317272 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6941 11:03:48.317409
6942 11:03:48.320707 [DATLAT]
6943 11:03:48.320784 Freq=400, CH1 RK1
6944 11:03:48.320844
6945 11:03:48.324459 DATLAT Default: 0xe
6946 11:03:48.324572 0, 0xFFFF, sum = 0
6947 11:03:48.327142 1, 0xFFFF, sum = 0
6948 11:03:48.327239 2, 0xFFFF, sum = 0
6949 11:03:48.330616 3, 0xFFFF, sum = 0
6950 11:03:48.330695 4, 0xFFFF, sum = 0
6951 11:03:48.334135 5, 0xFFFF, sum = 0
6952 11:03:48.334213 6, 0xFFFF, sum = 0
6953 11:03:48.337547 7, 0xFFFF, sum = 0
6954 11:03:48.337652 8, 0xFFFF, sum = 0
6955 11:03:48.340629 9, 0xFFFF, sum = 0
6956 11:03:48.344026 10, 0xFFFF, sum = 0
6957 11:03:48.344104 11, 0xFFFF, sum = 0
6958 11:03:48.347384 12, 0xFFFF, sum = 0
6959 11:03:48.347462 13, 0x0, sum = 1
6960 11:03:48.350600 14, 0x0, sum = 2
6961 11:03:48.350678 15, 0x0, sum = 3
6962 11:03:48.350738 16, 0x0, sum = 4
6963 11:03:48.353837 best_step = 14
6964 11:03:48.353913
6965 11:03:48.353972 ==
6966 11:03:48.357008 Dram Type= 6, Freq= 0, CH_1, rank 1
6967 11:03:48.361009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6968 11:03:48.361090 ==
6969 11:03:48.363781 RX Vref Scan: 0
6970 11:03:48.363857
6971 11:03:48.363916 RX Vref 0 -> 0, step: 1
6972 11:03:48.367302
6973 11:03:48.367379 RX Delay -311 -> 252, step: 8
6974 11:03:48.375459 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6975 11:03:48.378775 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6976 11:03:48.382110 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6977 11:03:48.385374 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6978 11:03:48.392271 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6979 11:03:48.395219 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6980 11:03:48.399101 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6981 11:03:48.402268 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6982 11:03:48.408655 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6983 11:03:48.411838 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6984 11:03:48.415316 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6985 11:03:48.418806 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6986 11:03:48.425640 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6987 11:03:48.428777 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6988 11:03:48.432019 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6989 11:03:48.436059 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6990 11:03:48.439282 ==
6991 11:03:48.439394 Dram Type= 6, Freq= 0, CH_1, rank 1
6992 11:03:48.445732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6993 11:03:48.445844 ==
6994 11:03:48.445906 DQS Delay:
6995 11:03:48.449093 DQS0 = 28, DQS1 = 36
6996 11:03:48.449191 DQM Delay:
6997 11:03:48.452748 DQM0 = 11, DQM1 = 15
6998 11:03:48.452847 DQ Delay:
6999 11:03:48.455770 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7000 11:03:48.458697 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =12
7001 11:03:48.461964 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
7002 11:03:48.465968 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7003 11:03:48.466065
7004 11:03:48.466151
7005 11:03:48.472350 [DQSOSCAuto] RK1, (LSB)MR18= 0xce5e, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 384 ps
7006 11:03:48.475625 CH1 RK1: MR19=C0C, MR18=CE5E
7007 11:03:48.481894 CH1_RK1: MR19=0xC0C, MR18=0xCE5E, DQSOSC=384, MR23=63, INC=400, DEC=267
7008 11:03:48.485599 [RxdqsGatingPostProcess] freq 400
7009 11:03:48.489013 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7010 11:03:48.492478 best DQS0 dly(2T, 0.5T) = (0, 10)
7011 11:03:48.495485 best DQS1 dly(2T, 0.5T) = (0, 10)
7012 11:03:48.499165 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7013 11:03:48.501870 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7014 11:03:48.505455 best DQS0 dly(2T, 0.5T) = (0, 10)
7015 11:03:48.508912 best DQS1 dly(2T, 0.5T) = (0, 10)
7016 11:03:48.512183 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7017 11:03:48.515567 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7018 11:03:48.518618 Pre-setting of DQS Precalculation
7019 11:03:48.521711 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7020 11:03:48.532005 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7021 11:03:48.538655 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7022 11:03:48.538730
7023 11:03:48.538788
7024 11:03:48.541941 [Calibration Summary] 800 Mbps
7025 11:03:48.542023 CH 0, Rank 0
7026 11:03:48.545742 SW Impedance : PASS
7027 11:03:48.545865 DUTY Scan : NO K
7028 11:03:48.548710 ZQ Calibration : PASS
7029 11:03:48.552088 Jitter Meter : NO K
7030 11:03:48.552162 CBT Training : PASS
7031 11:03:48.555520 Write leveling : PASS
7032 11:03:48.558574 RX DQS gating : PASS
7033 11:03:48.558671 RX DQ/DQS(RDDQC) : PASS
7034 11:03:48.562204 TX DQ/DQS : PASS
7035 11:03:48.565498 RX DATLAT : PASS
7036 11:03:48.565572 RX DQ/DQS(Engine): PASS
7037 11:03:48.568690 TX OE : NO K
7038 11:03:48.568754 All Pass.
7039 11:03:48.568808
7040 11:03:48.572015 CH 0, Rank 1
7041 11:03:48.572088 SW Impedance : PASS
7042 11:03:48.575039 DUTY Scan : NO K
7043 11:03:48.575138 ZQ Calibration : PASS
7044 11:03:48.578307 Jitter Meter : NO K
7045 11:03:48.581839 CBT Training : PASS
7046 11:03:48.581913 Write leveling : NO K
7047 11:03:48.585012 RX DQS gating : PASS
7048 11:03:48.588279 RX DQ/DQS(RDDQC) : PASS
7049 11:03:48.588373 TX DQ/DQS : PASS
7050 11:03:48.592008 RX DATLAT : PASS
7051 11:03:48.595172 RX DQ/DQS(Engine): PASS
7052 11:03:48.595288 TX OE : NO K
7053 11:03:48.598384 All Pass.
7054 11:03:48.598483
7055 11:03:48.598567 CH 1, Rank 0
7056 11:03:48.601640 SW Impedance : PASS
7057 11:03:48.601735 DUTY Scan : NO K
7058 11:03:48.605394 ZQ Calibration : PASS
7059 11:03:48.608654 Jitter Meter : NO K
7060 11:03:48.608752 CBT Training : PASS
7061 11:03:48.611830 Write leveling : PASS
7062 11:03:48.615136 RX DQS gating : PASS
7063 11:03:48.615233 RX DQ/DQS(RDDQC) : PASS
7064 11:03:48.618394 TX DQ/DQS : PASS
7065 11:03:48.618492 RX DATLAT : PASS
7066 11:03:48.621539 RX DQ/DQS(Engine): PASS
7067 11:03:48.625081 TX OE : NO K
7068 11:03:48.625148 All Pass.
7069 11:03:48.625206
7070 11:03:48.625269 CH 1, Rank 1
7071 11:03:48.628424 SW Impedance : PASS
7072 11:03:48.631991 DUTY Scan : NO K
7073 11:03:48.632083 ZQ Calibration : PASS
7074 11:03:48.635194 Jitter Meter : NO K
7075 11:03:48.638698 CBT Training : PASS
7076 11:03:48.638776 Write leveling : NO K
7077 11:03:48.641514 RX DQS gating : PASS
7078 11:03:48.645284 RX DQ/DQS(RDDQC) : PASS
7079 11:03:48.645373 TX DQ/DQS : PASS
7080 11:03:48.648249 RX DATLAT : PASS
7081 11:03:48.651795 RX DQ/DQS(Engine): PASS
7082 11:03:48.651908 TX OE : NO K
7083 11:03:48.655331 All Pass.
7084 11:03:48.655418
7085 11:03:48.655508 DramC Write-DBI off
7086 11:03:48.658246 PER_BANK_REFRESH: Hybrid Mode
7087 11:03:48.658310 TX_TRACKING: ON
7088 11:03:48.668354 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7089 11:03:48.671670 [FAST_K] Save calibration result to emmc
7090 11:03:48.674941 dramc_set_vcore_voltage set vcore to 725000
7091 11:03:48.678192 Read voltage for 1600, 0
7092 11:03:48.678290 Vio18 = 0
7093 11:03:48.681772 Vcore = 725000
7094 11:03:48.681843 Vdram = 0
7095 11:03:48.681900 Vddq = 0
7096 11:03:48.681956 Vmddr = 0
7097 11:03:48.688593 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7098 11:03:48.695540 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7099 11:03:48.695613 MEM_TYPE=3, freq_sel=13
7100 11:03:48.698232 sv_algorithm_assistance_LP4_3733
7101 11:03:48.701386 ============ PULL DRAM RESETB DOWN ============
7102 11:03:48.707975 ========== PULL DRAM RESETB DOWN end =========
7103 11:03:48.711746 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7104 11:03:48.714916 ===================================
7105 11:03:48.718089 LPDDR4 DRAM CONFIGURATION
7106 11:03:48.721317 ===================================
7107 11:03:48.721402 EX_ROW_EN[0] = 0x0
7108 11:03:48.725120 EX_ROW_EN[1] = 0x0
7109 11:03:48.725205 LP4Y_EN = 0x0
7110 11:03:48.728351 WORK_FSP = 0x1
7111 11:03:48.728438 WL = 0x5
7112 11:03:48.731576 RL = 0x5
7113 11:03:48.735018 BL = 0x2
7114 11:03:48.735101 RPST = 0x0
7115 11:03:48.738170 RD_PRE = 0x0
7116 11:03:48.738240 WR_PRE = 0x1
7117 11:03:48.741515 WR_PST = 0x1
7118 11:03:48.741597 DBI_WR = 0x0
7119 11:03:48.744795 DBI_RD = 0x0
7120 11:03:48.744882 OTF = 0x1
7121 11:03:48.748311 ===================================
7122 11:03:48.751840 ===================================
7123 11:03:48.754505 ANA top config
7124 11:03:48.758267 ===================================
7125 11:03:48.758337 DLL_ASYNC_EN = 0
7126 11:03:48.761322 ALL_SLAVE_EN = 0
7127 11:03:48.764764 NEW_RANK_MODE = 1
7128 11:03:48.767956 DLL_IDLE_MODE = 1
7129 11:03:48.768032 LP45_APHY_COMB_EN = 1
7130 11:03:48.771391 TX_ODT_DIS = 0
7131 11:03:48.774813 NEW_8X_MODE = 1
7132 11:03:48.777931 ===================================
7133 11:03:48.781070 ===================================
7134 11:03:48.784599 data_rate = 3200
7135 11:03:48.788210 CKR = 1
7136 11:03:48.791430 DQ_P2S_RATIO = 8
7137 11:03:48.791504 ===================================
7138 11:03:48.794656 CA_P2S_RATIO = 8
7139 11:03:48.798153 DQ_CA_OPEN = 0
7140 11:03:48.801647 DQ_SEMI_OPEN = 0
7141 11:03:48.804882 CA_SEMI_OPEN = 0
7142 11:03:48.807986 CA_FULL_RATE = 0
7143 11:03:48.808060 DQ_CKDIV4_EN = 0
7144 11:03:48.811304 CA_CKDIV4_EN = 0
7145 11:03:48.814240 CA_PREDIV_EN = 0
7146 11:03:48.818230 PH8_DLY = 12
7147 11:03:48.820965 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7148 11:03:48.824625 DQ_AAMCK_DIV = 4
7149 11:03:48.824699 CA_AAMCK_DIV = 4
7150 11:03:48.827885 CA_ADMCK_DIV = 4
7151 11:03:48.831060 DQ_TRACK_CA_EN = 0
7152 11:03:48.834500 CA_PICK = 1600
7153 11:03:48.837587 CA_MCKIO = 1600
7154 11:03:48.840929 MCKIO_SEMI = 0
7155 11:03:48.844554 PLL_FREQ = 3068
7156 11:03:48.847708 DQ_UI_PI_RATIO = 32
7157 11:03:48.847778 CA_UI_PI_RATIO = 0
7158 11:03:48.851407 ===================================
7159 11:03:48.854773 ===================================
7160 11:03:48.857937 memory_type:LPDDR4
7161 11:03:48.861235 GP_NUM : 10
7162 11:03:48.861296 SRAM_EN : 1
7163 11:03:48.864627 MD32_EN : 0
7164 11:03:48.867564 ===================================
7165 11:03:48.871165 [ANA_INIT] >>>>>>>>>>>>>>
7166 11:03:48.871231 <<<<<< [CONFIGURE PHASE]: ANA_TX
7167 11:03:48.877880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7168 11:03:48.877977 ===================================
7169 11:03:48.881078 data_rate = 3200,PCW = 0X7600
7170 11:03:48.884608 ===================================
7171 11:03:48.887719 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7172 11:03:48.894790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7173 11:03:48.901275 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7174 11:03:48.904342 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7175 11:03:48.908106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7176 11:03:48.911210 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7177 11:03:48.914392 [ANA_INIT] flow start
7178 11:03:48.914466 [ANA_INIT] PLL >>>>>>>>
7179 11:03:48.917715 [ANA_INIT] PLL <<<<<<<<
7180 11:03:48.921126 [ANA_INIT] MIDPI >>>>>>>>
7181 11:03:48.924375 [ANA_INIT] MIDPI <<<<<<<<
7182 11:03:48.924449 [ANA_INIT] DLL >>>>>>>>
7183 11:03:48.927838 [ANA_INIT] DLL <<<<<<<<
7184 11:03:48.927912 [ANA_INIT] flow end
7185 11:03:48.934041 ============ LP4 DIFF to SE enter ============
7186 11:03:48.937422 ============ LP4 DIFF to SE exit ============
7187 11:03:48.941266 [ANA_INIT] <<<<<<<<<<<<<
7188 11:03:48.944631 [Flow] Enable top DCM control >>>>>
7189 11:03:48.947269 [Flow] Enable top DCM control <<<<<
7190 11:03:48.947342 Enable DLL master slave shuffle
7191 11:03:48.954515 ==============================================================
7192 11:03:48.957800 Gating Mode config
7193 11:03:48.960634 ==============================================================
7194 11:03:48.964470 Config description:
7195 11:03:48.973925 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7196 11:03:48.980640 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7197 11:03:48.984421 SELPH_MODE 0: By rank 1: By Phase
7198 11:03:48.990554 ==============================================================
7199 11:03:48.993906 GAT_TRACK_EN = 1
7200 11:03:48.997052 RX_GATING_MODE = 2
7201 11:03:49.000751 RX_GATING_TRACK_MODE = 2
7202 11:03:49.003901 SELPH_MODE = 1
7203 11:03:49.003975 PICG_EARLY_EN = 1
7204 11:03:49.007104 VALID_LAT_VALUE = 1
7205 11:03:49.014166 ==============================================================
7206 11:03:49.017119 Enter into Gating configuration >>>>
7207 11:03:49.020851 Exit from Gating configuration <<<<
7208 11:03:49.023770 Enter into DVFS_PRE_config >>>>>
7209 11:03:49.033659 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7210 11:03:49.037520 Exit from DVFS_PRE_config <<<<<
7211 11:03:49.040222 Enter into PICG configuration >>>>
7212 11:03:49.044090 Exit from PICG configuration <<<<
7213 11:03:49.047350 [RX_INPUT] configuration >>>>>
7214 11:03:49.050536 [RX_INPUT] configuration <<<<<
7215 11:03:49.053908 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7216 11:03:49.060401 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7217 11:03:49.067403 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7218 11:03:49.074062 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7219 11:03:49.080651 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7220 11:03:49.083965 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7221 11:03:49.090558 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7222 11:03:49.094339 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7223 11:03:49.097624 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7224 11:03:49.101046 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7225 11:03:49.103946 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7226 11:03:49.110684 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7227 11:03:49.113782 ===================================
7228 11:03:49.117183 LPDDR4 DRAM CONFIGURATION
7229 11:03:49.117258 ===================================
7230 11:03:49.120531 EX_ROW_EN[0] = 0x0
7231 11:03:49.123826 EX_ROW_EN[1] = 0x0
7232 11:03:49.123900 LP4Y_EN = 0x0
7233 11:03:49.127405 WORK_FSP = 0x1
7234 11:03:49.127480 WL = 0x5
7235 11:03:49.130752 RL = 0x5
7236 11:03:49.130826 BL = 0x2
7237 11:03:49.133870 RPST = 0x0
7238 11:03:49.133966 RD_PRE = 0x0
7239 11:03:49.137897 WR_PRE = 0x1
7240 11:03:49.137994 WR_PST = 0x1
7241 11:03:49.141025 DBI_WR = 0x0
7242 11:03:49.141099 DBI_RD = 0x0
7243 11:03:49.144291 OTF = 0x1
7244 11:03:49.147534 ===================================
7245 11:03:49.150898 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7246 11:03:49.154323 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7247 11:03:49.160712 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7248 11:03:49.164193 ===================================
7249 11:03:49.164267 LPDDR4 DRAM CONFIGURATION
7250 11:03:49.167472 ===================================
7251 11:03:49.170888 EX_ROW_EN[0] = 0x10
7252 11:03:49.170962 EX_ROW_EN[1] = 0x0
7253 11:03:49.174618 LP4Y_EN = 0x0
7254 11:03:49.177725 WORK_FSP = 0x1
7255 11:03:49.177799 WL = 0x5
7256 11:03:49.181379 RL = 0x5
7257 11:03:49.181452 BL = 0x2
7258 11:03:49.184483 RPST = 0x0
7259 11:03:49.184565 RD_PRE = 0x0
7260 11:03:49.187881 WR_PRE = 0x1
7261 11:03:49.187954 WR_PST = 0x1
7262 11:03:49.190986 DBI_WR = 0x0
7263 11:03:49.191060 DBI_RD = 0x0
7264 11:03:49.194062 OTF = 0x1
7265 11:03:49.197689 ===================================
7266 11:03:49.204132 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7267 11:03:49.204207 ==
7268 11:03:49.207850 Dram Type= 6, Freq= 0, CH_0, rank 0
7269 11:03:49.210673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7270 11:03:49.210747 ==
7271 11:03:49.214208 [Duty_Offset_Calibration]
7272 11:03:49.214282 B0:2 B1:1 CA:1
7273 11:03:49.214338
7274 11:03:49.217217 [DutyScan_Calibration_Flow] k_type=0
7275 11:03:49.227814
7276 11:03:49.227893 ==CLK 0==
7277 11:03:49.230977 Final CLK duty delay cell = 0
7278 11:03:49.234360 [0] MAX Duty = 5187%(X100), DQS PI = 22
7279 11:03:49.237966 [0] MIN Duty = 4876%(X100), DQS PI = 48
7280 11:03:49.238096 [0] AVG Duty = 5031%(X100)
7281 11:03:49.240805
7282 11:03:49.244294 CH0 CLK Duty spec in!! Max-Min= 311%
7283 11:03:49.247659 [DutyScan_Calibration_Flow] ====Done====
7284 11:03:49.247725
7285 11:03:49.251214 [DutyScan_Calibration_Flow] k_type=1
7286 11:03:49.266557
7287 11:03:49.266673 ==DQS 0 ==
7288 11:03:49.270103 Final DQS duty delay cell = -4
7289 11:03:49.273196 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7290 11:03:49.276457 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7291 11:03:49.280305 [-4] AVG Duty = 4891%(X100)
7292 11:03:49.280379
7293 11:03:49.280436 ==DQS 1 ==
7294 11:03:49.283540 Final DQS duty delay cell = 0
7295 11:03:49.286923 [0] MAX Duty = 5218%(X100), DQS PI = 22
7296 11:03:49.290286 [0] MIN Duty = 5031%(X100), DQS PI = 52
7297 11:03:49.293184 [0] AVG Duty = 5124%(X100)
7298 11:03:49.293260
7299 11:03:49.296382 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7300 11:03:49.296456
7301 11:03:49.300023 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7302 11:03:49.302973 [DutyScan_Calibration_Flow] ====Done====
7303 11:03:49.303048
7304 11:03:49.306216 [DutyScan_Calibration_Flow] k_type=3
7305 11:03:49.324449
7306 11:03:49.324525 ==DQM 0 ==
7307 11:03:49.327532 Final DQM duty delay cell = 0
7308 11:03:49.330920 [0] MAX Duty = 5187%(X100), DQS PI = 32
7309 11:03:49.334082 [0] MIN Duty = 4875%(X100), DQS PI = 58
7310 11:03:49.337326 [0] AVG Duty = 5031%(X100)
7311 11:03:49.337417
7312 11:03:49.337475 ==DQM 1 ==
7313 11:03:49.340963 Final DQM duty delay cell = 0
7314 11:03:49.344291 [0] MAX Duty = 5187%(X100), DQS PI = 6
7315 11:03:49.347336 [0] MIN Duty = 5031%(X100), DQS PI = 48
7316 11:03:49.351396 [0] AVG Duty = 5109%(X100)
7317 11:03:49.351472
7318 11:03:49.353867 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7319 11:03:49.353938
7320 11:03:49.357350 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7321 11:03:49.361017 [DutyScan_Calibration_Flow] ====Done====
7322 11:03:49.361092
7323 11:03:49.364020 [DutyScan_Calibration_Flow] k_type=2
7324 11:03:49.381278
7325 11:03:49.381395 ==DQ 0 ==
7326 11:03:49.384626 Final DQ duty delay cell = 0
7327 11:03:49.387999 [0] MAX Duty = 5062%(X100), DQS PI = 26
7328 11:03:49.391289 [0] MIN Duty = 4907%(X100), DQS PI = 0
7329 11:03:49.391365 [0] AVG Duty = 4984%(X100)
7330 11:03:49.391423
7331 11:03:49.394529 ==DQ 1 ==
7332 11:03:49.398546 Final DQ duty delay cell = 0
7333 11:03:49.401049 [0] MAX Duty = 5093%(X100), DQS PI = 6
7334 11:03:49.404964 [0] MIN Duty = 4907%(X100), DQS PI = 34
7335 11:03:49.405042 [0] AVG Duty = 5000%(X100)
7336 11:03:49.405115
7337 11:03:49.408403 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7338 11:03:49.408510
7339 11:03:49.411183 CH0 DQ 1 Duty spec in!! Max-Min= 186%
7340 11:03:49.418027 [DutyScan_Calibration_Flow] ====Done====
7341 11:03:49.418118 ==
7342 11:03:49.421187 Dram Type= 6, Freq= 0, CH_1, rank 0
7343 11:03:49.424705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7344 11:03:49.424781 ==
7345 11:03:49.427795 [Duty_Offset_Calibration]
7346 11:03:49.427871 B0:1 B1:0 CA:0
7347 11:03:49.427929
7348 11:03:49.431061 [DutyScan_Calibration_Flow] k_type=0
7349 11:03:49.440606
7350 11:03:49.440682 ==CLK 0==
7351 11:03:49.444231 Final CLK duty delay cell = -4
7352 11:03:49.447532 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7353 11:03:49.450723 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7354 11:03:49.454023 [-4] AVG Duty = 4906%(X100)
7355 11:03:49.454100
7356 11:03:49.457429 CH1 CLK Duty spec in!! Max-Min= 125%
7357 11:03:49.460871 [DutyScan_Calibration_Flow] ====Done====
7358 11:03:49.460962
7359 11:03:49.463577 [DutyScan_Calibration_Flow] k_type=1
7360 11:03:49.481182
7361 11:03:49.481260 ==DQS 0 ==
7362 11:03:49.484074 Final DQS duty delay cell = 0
7363 11:03:49.487703 [0] MAX Duty = 5094%(X100), DQS PI = 32
7364 11:03:49.490829 [0] MIN Duty = 4844%(X100), DQS PI = 46
7365 11:03:49.493951 [0] AVG Duty = 4969%(X100)
7366 11:03:49.494033
7367 11:03:49.494093 ==DQS 1 ==
7368 11:03:49.497280 Final DQS duty delay cell = 0
7369 11:03:49.501243 [0] MAX Duty = 5249%(X100), DQS PI = 16
7370 11:03:49.504372 [0] MIN Duty = 4938%(X100), DQS PI = 8
7371 11:03:49.504449 [0] AVG Duty = 5093%(X100)
7372 11:03:49.507543
7373 11:03:49.510842 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7374 11:03:49.510918
7375 11:03:49.513970 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7376 11:03:49.517090 [DutyScan_Calibration_Flow] ====Done====
7377 11:03:49.517166
7378 11:03:49.520917 [DutyScan_Calibration_Flow] k_type=3
7379 11:03:49.537598
7380 11:03:49.537672 ==DQM 0 ==
7381 11:03:49.541023 Final DQM duty delay cell = 0
7382 11:03:49.544229 [0] MAX Duty = 5187%(X100), DQS PI = 8
7383 11:03:49.547447 [0] MIN Duty = 4969%(X100), DQS PI = 48
7384 11:03:49.547525 [0] AVG Duty = 5078%(X100)
7385 11:03:49.550893
7386 11:03:49.550983 ==DQM 1 ==
7387 11:03:49.553950 Final DQM duty delay cell = 0
7388 11:03:49.557516 [0] MAX Duty = 5093%(X100), DQS PI = 16
7389 11:03:49.561109 [0] MIN Duty = 4907%(X100), DQS PI = 32
7390 11:03:49.561209 [0] AVG Duty = 5000%(X100)
7391 11:03:49.564178
7392 11:03:49.567775 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7393 11:03:49.567849
7394 11:03:49.570904 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7395 11:03:49.574221 [DutyScan_Calibration_Flow] ====Done====
7396 11:03:49.574295
7397 11:03:49.577102 [DutyScan_Calibration_Flow] k_type=2
7398 11:03:49.593604
7399 11:03:49.593679 ==DQ 0 ==
7400 11:03:49.597014 Final DQ duty delay cell = -4
7401 11:03:49.600410 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7402 11:03:49.603378 [-4] MIN Duty = 4875%(X100), DQS PI = 44
7403 11:03:49.606870 [-4] AVG Duty = 4953%(X100)
7404 11:03:49.606944
7405 11:03:49.607001 ==DQ 1 ==
7406 11:03:49.610525 Final DQ duty delay cell = 0
7407 11:03:49.613652 [0] MAX Duty = 5093%(X100), DQS PI = 16
7408 11:03:49.616710 [0] MIN Duty = 4938%(X100), DQS PI = 8
7409 11:03:49.616800 [0] AVG Duty = 5015%(X100)
7410 11:03:49.620592
7411 11:03:49.620666 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7412 11:03:49.623731
7413 11:03:49.626865 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7414 11:03:49.630637 [DutyScan_Calibration_Flow] ====Done====
7415 11:03:49.634219 nWR fixed to 30
7416 11:03:49.634295 [ModeRegInit_LP4] CH0 RK0
7417 11:03:49.637072 [ModeRegInit_LP4] CH0 RK1
7418 11:03:49.640253 [ModeRegInit_LP4] CH1 RK0
7419 11:03:49.643864 [ModeRegInit_LP4] CH1 RK1
7420 11:03:49.643938 match AC timing 5
7421 11:03:49.646929 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7422 11:03:49.653584 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7423 11:03:49.656710 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7424 11:03:49.663684 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7425 11:03:49.666941 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7426 11:03:49.667039 [MiockJmeterHQA]
7427 11:03:49.667123
7428 11:03:49.669945 [DramcMiockJmeter] u1RxGatingPI = 0
7429 11:03:49.673222 0 : 4258, 4029
7430 11:03:49.673300 4 : 4363, 4138
7431 11:03:49.676652 8 : 4252, 4027
7432 11:03:49.676726 12 : 4363, 4137
7433 11:03:49.676785 16 : 4253, 4027
7434 11:03:49.679800 20 : 4253, 4026
7435 11:03:49.679875 24 : 4363, 4138
7436 11:03:49.683120 28 : 4252, 4027
7437 11:03:49.683233 32 : 4363, 4138
7438 11:03:49.686522 36 : 4250, 4027
7439 11:03:49.686597 40 : 4253, 4026
7440 11:03:49.689982 44 : 4250, 4027
7441 11:03:49.690100 48 : 4253, 4026
7442 11:03:49.690159 52 : 4360, 4138
7443 11:03:49.692834 56 : 4250, 4027
7444 11:03:49.692911 60 : 4361, 4137
7445 11:03:49.696402 64 : 4360, 4138
7446 11:03:49.696480 68 : 4250, 4027
7447 11:03:49.699588 72 : 4253, 4029
7448 11:03:49.699663 76 : 4360, 4138
7449 11:03:49.702965 80 : 4363, 4140
7450 11:03:49.703041 84 : 4363, 4140
7451 11:03:49.703100 88 : 4250, 226
7452 11:03:49.706725 92 : 4253, 0
7453 11:03:49.706801 96 : 4252, 0
7454 11:03:49.709497 100 : 4252, 0
7455 11:03:49.709573 104 : 4361, 0
7456 11:03:49.709632 108 : 4360, 0
7457 11:03:49.713381 112 : 4363, 0
7458 11:03:49.713457 116 : 4252, 0
7459 11:03:49.713516 120 : 4360, 0
7460 11:03:49.716335 124 : 4361, 0
7461 11:03:49.716412 128 : 4250, 0
7462 11:03:49.719961 132 : 4250, 0
7463 11:03:49.720036 136 : 4250, 0
7464 11:03:49.720094 140 : 4250, 0
7465 11:03:49.723211 144 : 4250, 0
7466 11:03:49.723287 148 : 4250, 0
7467 11:03:49.726253 152 : 4250, 0
7468 11:03:49.726329 156 : 4361, 0
7469 11:03:49.726388 160 : 4250, 0
7470 11:03:49.729360 164 : 4360, 0
7471 11:03:49.729454 168 : 4250, 0
7472 11:03:49.732794 172 : 4363, 0
7473 11:03:49.732909 176 : 4250, 0
7474 11:03:49.732996 180 : 4250, 0
7475 11:03:49.736163 184 : 4250, 0
7476 11:03:49.736246 188 : 4250, 0
7477 11:03:49.736307 192 : 4250, 0
7478 11:03:49.739464 196 : 4250, 0
7479 11:03:49.739540 200 : 4250, 0
7480 11:03:49.742866 204 : 4250, 919
7481 11:03:49.742942 208 : 4360, 4103
7482 11:03:49.746539 212 : 4252, 4029
7483 11:03:49.746616 216 : 4249, 4027
7484 11:03:49.749606 220 : 4361, 4137
7485 11:03:49.749707 224 : 4253, 4029
7486 11:03:49.752532 228 : 4250, 4027
7487 11:03:49.752615 232 : 4250, 4027
7488 11:03:49.752704 236 : 4250, 4026
7489 11:03:49.756186 240 : 4253, 4029
7490 11:03:49.756262 244 : 4363, 4139
7491 11:03:49.759677 248 : 4250, 4027
7492 11:03:49.759753 252 : 4250, 4026
7493 11:03:49.762924 256 : 4250, 4027
7494 11:03:49.763000 260 : 4360, 4137
7495 11:03:49.766369 264 : 4360, 4138
7496 11:03:49.766469 268 : 4250, 4027
7497 11:03:49.769336 272 : 4361, 4137
7498 11:03:49.769411 276 : 4253, 4029
7499 11:03:49.772469 280 : 4250, 4027
7500 11:03:49.772545 284 : 4250, 4027
7501 11:03:49.776242 288 : 4250, 4027
7502 11:03:49.776318 292 : 4253, 4029
7503 11:03:49.776384 296 : 4363, 4140
7504 11:03:49.779618 300 : 4249, 4027
7505 11:03:49.779695 304 : 4250, 4026
7506 11:03:49.782187 308 : 4250, 4005
7507 11:03:49.782266 312 : 4363, 2205
7508 11:03:49.785466 316 : 4360, 7
7509 11:03:49.785542
7510 11:03:49.785600 MIOCK jitter meter ch=0
7511 11:03:49.789476
7512 11:03:49.789550 1T = (316-88) = 228 dly cells
7513 11:03:49.796041 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7514 11:03:49.796120 ==
7515 11:03:49.799048 Dram Type= 6, Freq= 0, CH_0, rank 0
7516 11:03:49.802056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7517 11:03:49.802146 ==
7518 11:03:49.809287 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7519 11:03:49.812087 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7520 11:03:49.818717 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7521 11:03:49.822664 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7522 11:03:49.832329 [CA 0] Center 42 (12~73) winsize 62
7523 11:03:49.835409 [CA 1] Center 42 (12~73) winsize 62
7524 11:03:49.839224 [CA 2] Center 37 (7~67) winsize 61
7525 11:03:49.842720 [CA 3] Center 37 (7~67) winsize 61
7526 11:03:49.845584 [CA 4] Center 36 (6~66) winsize 61
7527 11:03:49.849598 [CA 5] Center 35 (6~64) winsize 59
7528 11:03:49.849673
7529 11:03:49.852313 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7530 11:03:49.852388
7531 11:03:49.856362 [CATrainingPosCal] consider 1 rank data
7532 11:03:49.858813 u2DelayCellTimex100 = 285/100 ps
7533 11:03:49.862316 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7534 11:03:49.868925 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7535 11:03:49.872394 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7536 11:03:49.875431 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7537 11:03:49.879043 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7538 11:03:49.881932 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7539 11:03:49.882059
7540 11:03:49.885567 CA PerBit enable=1, Macro0, CA PI delay=35
7541 11:03:49.885659
7542 11:03:49.889086 [CBTSetCACLKResult] CA Dly = 35
7543 11:03:49.892257 CS Dly: 9 (0~40)
7544 11:03:49.895576 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7545 11:03:49.898937 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7546 11:03:49.899012 ==
7547 11:03:49.902722 Dram Type= 6, Freq= 0, CH_0, rank 1
7548 11:03:49.905934 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7549 11:03:49.906023 ==
7550 11:03:49.912493 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7551 11:03:49.915938 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7552 11:03:49.922307 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7553 11:03:49.925891 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7554 11:03:49.935477 [CA 0] Center 43 (13~73) winsize 61
7555 11:03:49.938811 [CA 1] Center 42 (12~73) winsize 62
7556 11:03:49.942148 [CA 2] Center 37 (8~67) winsize 60
7557 11:03:49.945509 [CA 3] Center 37 (8~67) winsize 60
7558 11:03:49.948817 [CA 4] Center 36 (6~66) winsize 61
7559 11:03:49.952008 [CA 5] Center 35 (5~65) winsize 61
7560 11:03:49.952100
7561 11:03:49.955617 [CmdBusTrainingLP45] Vref(ca) range 0: 28
7562 11:03:49.955692
7563 11:03:49.958867 [CATrainingPosCal] consider 2 rank data
7564 11:03:49.961967 u2DelayCellTimex100 = 285/100 ps
7565 11:03:49.968967 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7566 11:03:49.971856 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7567 11:03:49.975548 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7568 11:03:49.978763 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7569 11:03:49.981877 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7570 11:03:49.985312 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7571 11:03:49.985387
7572 11:03:49.988371 CA PerBit enable=1, Macro0, CA PI delay=35
7573 11:03:49.988446
7574 11:03:49.992236 [CBTSetCACLKResult] CA Dly = 35
7575 11:03:49.995081 CS Dly: 9 (0~41)
7576 11:03:49.998765 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7577 11:03:50.002171 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7578 11:03:50.002246
7579 11:03:50.005395 ----->DramcWriteLeveling(PI) begin...
7580 11:03:50.005471 ==
7581 11:03:50.008549 Dram Type= 6, Freq= 0, CH_0, rank 0
7582 11:03:50.012219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7583 11:03:50.015400 ==
7584 11:03:50.015474 Write leveling (Byte 0): 35 => 35
7585 11:03:50.018531 Write leveling (Byte 1): 26 => 26
7586 11:03:50.021907 DramcWriteLeveling(PI) end<-----
7587 11:03:50.021982
7588 11:03:50.022083 ==
7589 11:03:50.025650 Dram Type= 6, Freq= 0, CH_0, rank 0
7590 11:03:50.031769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7591 11:03:50.031845 ==
7592 11:03:50.031903 [Gating] SW mode calibration
7593 11:03:50.041869 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7594 11:03:50.045090 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7595 11:03:50.048465 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 11:03:50.055081 1 4 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7597 11:03:50.058466 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7598 11:03:50.067765 1 4 12 | B1->B0 | 2323 3b3a | 0 1 | (0 0) (1 1)
7599 11:03:50.068477 1 4 16 | B1->B0 | 2323 3636 | 0 1 | (0 0) (1 1)
7600 11:03:50.071748 1 4 20 | B1->B0 | 3433 3736 | 1 1 | (0 0) (1 1)
7601 11:03:50.075507 1 4 24 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
7602 11:03:50.081917 1 4 28 | B1->B0 | 3434 3939 | 1 1 | (1 1) (0 0)
7603 11:03:50.085181 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7604 11:03:50.088743 1 5 4 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7605 11:03:50.095573 1 5 8 | B1->B0 | 3434 3332 | 1 1 | (1 1) (0 1)
7606 11:03:50.098683 1 5 12 | B1->B0 | 3434 2d2c | 1 1 | (1 1) (0 0)
7607 11:03:50.101933 1 5 16 | B1->B0 | 3333 2c2b | 1 1 | (1 0) (0 1)
7608 11:03:50.108470 1 5 20 | B1->B0 | 2525 2727 | 0 1 | (1 0) (0 0)
7609 11:03:50.111999 1 5 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
7610 11:03:50.115555 1 5 28 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7611 11:03:50.121771 1 6 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
7612 11:03:50.125238 1 6 4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7613 11:03:50.128783 1 6 8 | B1->B0 | 2323 302f | 0 1 | (0 0) (1 1)
7614 11:03:50.135131 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7615 11:03:50.138697 1 6 16 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7616 11:03:50.141643 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7617 11:03:50.145280 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7618 11:03:50.152026 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7619 11:03:50.155235 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 11:03:50.162161 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 11:03:50.165453 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7622 11:03:50.168743 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7623 11:03:50.171892 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7624 11:03:50.178426 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7625 11:03:50.181707 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 11:03:50.185191 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 11:03:50.191945 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 11:03:50.195182 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 11:03:50.198602 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 11:03:50.205454 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 11:03:50.208541 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 11:03:50.212119 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 11:03:50.218502 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 11:03:50.221722 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 11:03:50.224888 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 11:03:50.232155 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 11:03:50.235363 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 11:03:50.238427 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7639 11:03:50.244872 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7640 11:03:50.244941 Total UI for P1: 0, mck2ui 16
7641 11:03:50.251285 best dqsien dly found for B0: ( 1, 9, 12)
7642 11:03:50.255151 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7643 11:03:50.258079 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 11:03:50.261611 Total UI for P1: 0, mck2ui 16
7645 11:03:50.265234 best dqsien dly found for B1: ( 1, 9, 18)
7646 11:03:50.268235 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7647 11:03:50.271476 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7648 11:03:50.271541
7649 11:03:50.274809 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7650 11:03:50.281441 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7651 11:03:50.281510 [Gating] SW calibration Done
7652 11:03:50.281566 ==
7653 11:03:50.285069 Dram Type= 6, Freq= 0, CH_0, rank 0
7654 11:03:50.292047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7655 11:03:50.292142 ==
7656 11:03:50.292232 RX Vref Scan: 0
7657 11:03:50.292312
7658 11:03:50.294828 RX Vref 0 -> 0, step: 1
7659 11:03:50.294890
7660 11:03:50.297974 RX Delay 0 -> 252, step: 8
7661 11:03:50.301514 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7662 11:03:50.304995 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7663 11:03:50.308161 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7664 11:03:50.315053 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7665 11:03:50.318356 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7666 11:03:50.321594 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7667 11:03:50.324890 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7668 11:03:50.328472 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7669 11:03:50.331571 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7670 11:03:50.338181 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7671 11:03:50.341238 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7672 11:03:50.345034 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7673 11:03:50.348384 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7674 11:03:50.354906 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7675 11:03:50.358201 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7676 11:03:50.361428 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7677 11:03:50.361502 ==
7678 11:03:50.364743 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 11:03:50.367898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7680 11:03:50.367993 ==
7681 11:03:50.371236 DQS Delay:
7682 11:03:50.371324 DQS0 = 0, DQS1 = 0
7683 11:03:50.374849 DQM Delay:
7684 11:03:50.374918 DQM0 = 137, DQM1 = 130
7685 11:03:50.374973 DQ Delay:
7686 11:03:50.378011 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7687 11:03:50.381684 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7688 11:03:50.387823 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7689 11:03:50.391010 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7690 11:03:50.391098
7691 11:03:50.391157
7692 11:03:50.391209 ==
7693 11:03:50.394849 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 11:03:50.398014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 11:03:50.398137 ==
7696 11:03:50.398255
7697 11:03:50.398350
7698 11:03:50.401436 TX Vref Scan disable
7699 11:03:50.404411 == TX Byte 0 ==
7700 11:03:50.407953 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7701 11:03:50.411084 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7702 11:03:50.414753 == TX Byte 1 ==
7703 11:03:50.417854 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7704 11:03:50.421432 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7705 11:03:50.421528 ==
7706 11:03:50.424401 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 11:03:50.427641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 11:03:50.431099 ==
7709 11:03:50.443096
7710 11:03:50.446195 TX Vref early break, caculate TX vref
7711 11:03:50.449354 TX Vref=16, minBit 0, minWin=23, winSum=381
7712 11:03:50.453202 TX Vref=18, minBit 0, minWin=23, winSum=391
7713 11:03:50.456412 TX Vref=20, minBit 0, minWin=24, winSum=402
7714 11:03:50.459707 TX Vref=22, minBit 0, minWin=25, winSum=411
7715 11:03:50.462838 TX Vref=24, minBit 0, minWin=26, winSum=420
7716 11:03:50.469122 TX Vref=26, minBit 6, minWin=25, winSum=426
7717 11:03:50.472414 TX Vref=28, minBit 6, minWin=24, winSum=425
7718 11:03:50.475778 TX Vref=30, minBit 6, minWin=23, winSum=406
7719 11:03:50.479343 TX Vref=32, minBit 1, minWin=24, winSum=404
7720 11:03:50.482373 TX Vref=34, minBit 6, minWin=23, winSum=394
7721 11:03:50.489952 [TxChooseVref] Worse bit 0, Min win 26, Win sum 420, Final Vref 24
7722 11:03:50.490086
7723 11:03:50.492748 Final TX Range 0 Vref 24
7724 11:03:50.492844
7725 11:03:50.492903 ==
7726 11:03:50.496220 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 11:03:50.499549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7728 11:03:50.499624 ==
7729 11:03:50.499681
7730 11:03:50.499734
7731 11:03:50.502795 TX Vref Scan disable
7732 11:03:50.509509 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7733 11:03:50.509584 == TX Byte 0 ==
7734 11:03:50.512681 u2DelayCellOfst[0]=13 cells (4 PI)
7735 11:03:50.516063 u2DelayCellOfst[1]=17 cells (5 PI)
7736 11:03:50.519537 u2DelayCellOfst[2]=10 cells (3 PI)
7737 11:03:50.522936 u2DelayCellOfst[3]=10 cells (3 PI)
7738 11:03:50.526220 u2DelayCellOfst[4]=10 cells (3 PI)
7739 11:03:50.529632 u2DelayCellOfst[5]=0 cells (0 PI)
7740 11:03:50.532699 u2DelayCellOfst[6]=17 cells (5 PI)
7741 11:03:50.535648 u2DelayCellOfst[7]=17 cells (5 PI)
7742 11:03:50.539154 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7743 11:03:50.542479 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7744 11:03:50.545886 == TX Byte 1 ==
7745 11:03:50.545960 u2DelayCellOfst[8]=0 cells (0 PI)
7746 11:03:50.550123 u2DelayCellOfst[9]=0 cells (0 PI)
7747 11:03:50.552305 u2DelayCellOfst[10]=6 cells (2 PI)
7748 11:03:50.556025 u2DelayCellOfst[11]=3 cells (1 PI)
7749 11:03:50.559722 u2DelayCellOfst[12]=10 cells (3 PI)
7750 11:03:50.562903 u2DelayCellOfst[13]=10 cells (3 PI)
7751 11:03:50.565698 u2DelayCellOfst[14]=13 cells (4 PI)
7752 11:03:50.569677 u2DelayCellOfst[15]=10 cells (3 PI)
7753 11:03:50.572456 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7754 11:03:50.579014 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7755 11:03:50.579087 DramC Write-DBI on
7756 11:03:50.579160 ==
7757 11:03:50.582715 Dram Type= 6, Freq= 0, CH_0, rank 0
7758 11:03:50.586239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7759 11:03:50.589337 ==
7760 11:03:50.589405
7761 11:03:50.589476
7762 11:03:50.589545 TX Vref Scan disable
7763 11:03:50.592994 == TX Byte 0 ==
7764 11:03:50.595909 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7765 11:03:50.599077 == TX Byte 1 ==
7766 11:03:50.602433 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7767 11:03:50.602527 DramC Write-DBI off
7768 11:03:50.606370
7769 11:03:50.606437 [DATLAT]
7770 11:03:50.606507 Freq=1600, CH0 RK0
7771 11:03:50.606576
7772 11:03:50.609254 DATLAT Default: 0xf
7773 11:03:50.609360 0, 0xFFFF, sum = 0
7774 11:03:50.613187 1, 0xFFFF, sum = 0
7775 11:03:50.613280 2, 0xFFFF, sum = 0
7776 11:03:50.616067 3, 0xFFFF, sum = 0
7777 11:03:50.616134 4, 0xFFFF, sum = 0
7778 11:03:50.619458 5, 0xFFFF, sum = 0
7779 11:03:50.619523 6, 0xFFFF, sum = 0
7780 11:03:50.622575 7, 0xFFFF, sum = 0
7781 11:03:50.626315 8, 0xFFFF, sum = 0
7782 11:03:50.626415 9, 0xFFFF, sum = 0
7783 11:03:50.629565 10, 0xFFFF, sum = 0
7784 11:03:50.629666 11, 0xFFFF, sum = 0
7785 11:03:50.632733 12, 0xFFFF, sum = 0
7786 11:03:50.632833 13, 0xFFFF, sum = 0
7787 11:03:50.636144 14, 0x0, sum = 1
7788 11:03:50.636236 15, 0x0, sum = 2
7789 11:03:50.639156 16, 0x0, sum = 3
7790 11:03:50.639248 17, 0x0, sum = 4
7791 11:03:50.642640 best_step = 15
7792 11:03:50.642706
7793 11:03:50.642777 ==
7794 11:03:50.645959 Dram Type= 6, Freq= 0, CH_0, rank 0
7795 11:03:50.649257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7796 11:03:50.649339 ==
7797 11:03:50.649410 RX Vref Scan: 1
7798 11:03:50.652794
7799 11:03:50.652870 Set Vref Range= 24 -> 127
7800 11:03:50.652946
7801 11:03:50.655719 RX Vref 24 -> 127, step: 1
7802 11:03:50.655795
7803 11:03:50.658791 RX Delay 27 -> 252, step: 4
7804 11:03:50.658867
7805 11:03:50.662528 Set Vref, RX VrefLevel [Byte0]: 24
7806 11:03:50.665400 [Byte1]: 24
7807 11:03:50.665477
7808 11:03:50.668841 Set Vref, RX VrefLevel [Byte0]: 25
7809 11:03:50.672343 [Byte1]: 25
7810 11:03:50.672456
7811 11:03:50.675261 Set Vref, RX VrefLevel [Byte0]: 26
7812 11:03:50.678590 [Byte1]: 26
7813 11:03:50.682623
7814 11:03:50.682716 Set Vref, RX VrefLevel [Byte0]: 27
7815 11:03:50.685762 [Byte1]: 27
7816 11:03:50.690305
7817 11:03:50.690379 Set Vref, RX VrefLevel [Byte0]: 28
7818 11:03:50.693422 [Byte1]: 28
7819 11:03:50.698185
7820 11:03:50.698277 Set Vref, RX VrefLevel [Byte0]: 29
7821 11:03:50.701010 [Byte1]: 29
7822 11:03:50.705788
7823 11:03:50.705876 Set Vref, RX VrefLevel [Byte0]: 30
7824 11:03:50.708782 [Byte1]: 30
7825 11:03:50.712643
7826 11:03:50.712752 Set Vref, RX VrefLevel [Byte0]: 31
7827 11:03:50.716136 [Byte1]: 31
7828 11:03:50.720559
7829 11:03:50.720633 Set Vref, RX VrefLevel [Byte0]: 32
7830 11:03:50.723752 [Byte1]: 32
7831 11:03:50.727605
7832 11:03:50.727724 Set Vref, RX VrefLevel [Byte0]: 33
7833 11:03:50.731435 [Byte1]: 33
7834 11:03:50.735166
7835 11:03:50.735242 Set Vref, RX VrefLevel [Byte0]: 34
7836 11:03:50.738546 [Byte1]: 34
7837 11:03:50.743104
7838 11:03:50.743181 Set Vref, RX VrefLevel [Byte0]: 35
7839 11:03:50.746584 [Byte1]: 35
7840 11:03:50.750377
7841 11:03:50.750453 Set Vref, RX VrefLevel [Byte0]: 36
7842 11:03:50.753599 [Byte1]: 36
7843 11:03:50.758131
7844 11:03:50.758208 Set Vref, RX VrefLevel [Byte0]: 37
7845 11:03:50.761550 [Byte1]: 37
7846 11:03:50.765862
7847 11:03:50.765967 Set Vref, RX VrefLevel [Byte0]: 38
7848 11:03:50.769137 [Byte1]: 38
7849 11:03:50.773250
7850 11:03:50.773326 Set Vref, RX VrefLevel [Byte0]: 39
7851 11:03:50.776546 [Byte1]: 39
7852 11:03:50.780360
7853 11:03:50.780436 Set Vref, RX VrefLevel [Byte0]: 40
7854 11:03:50.784102 [Byte1]: 40
7855 11:03:50.788241
7856 11:03:50.788318 Set Vref, RX VrefLevel [Byte0]: 41
7857 11:03:50.791555 [Byte1]: 41
7858 11:03:50.795420
7859 11:03:50.795520 Set Vref, RX VrefLevel [Byte0]: 42
7860 11:03:50.799021 [Byte1]: 42
7861 11:03:50.803139
7862 11:03:50.803215 Set Vref, RX VrefLevel [Byte0]: 43
7863 11:03:50.806815 [Byte1]: 43
7864 11:03:50.810425
7865 11:03:50.810493 Set Vref, RX VrefLevel [Byte0]: 44
7866 11:03:50.814146 [Byte1]: 44
7867 11:03:50.818162
7868 11:03:50.818287 Set Vref, RX VrefLevel [Byte0]: 45
7869 11:03:50.821444 [Byte1]: 45
7870 11:03:50.826164
7871 11:03:50.826237 Set Vref, RX VrefLevel [Byte0]: 46
7872 11:03:50.829602 [Byte1]: 46
7873 11:03:50.833295
7874 11:03:50.833369 Set Vref, RX VrefLevel [Byte0]: 47
7875 11:03:50.836560 [Byte1]: 47
7876 11:03:50.840761
7877 11:03:50.844174 Set Vref, RX VrefLevel [Byte0]: 48
7878 11:03:50.847450 [Byte1]: 48
7879 11:03:50.847526
7880 11:03:50.850767 Set Vref, RX VrefLevel [Byte0]: 49
7881 11:03:50.854069 [Byte1]: 49
7882 11:03:50.854158
7883 11:03:50.857362 Set Vref, RX VrefLevel [Byte0]: 50
7884 11:03:50.860803 [Byte1]: 50
7885 11:03:50.860877
7886 11:03:50.863985 Set Vref, RX VrefLevel [Byte0]: 51
7887 11:03:50.867087 [Byte1]: 51
7888 11:03:50.870874
7889 11:03:50.870964 Set Vref, RX VrefLevel [Byte0]: 52
7890 11:03:50.874218 [Byte1]: 52
7891 11:03:50.878274
7892 11:03:50.878345 Set Vref, RX VrefLevel [Byte0]: 53
7893 11:03:50.882311 [Byte1]: 53
7894 11:03:50.886150
7895 11:03:50.886244 Set Vref, RX VrefLevel [Byte0]: 54
7896 11:03:50.889436 [Byte1]: 54
7897 11:03:50.893488
7898 11:03:50.893578 Set Vref, RX VrefLevel [Byte0]: 55
7899 11:03:50.897354 [Byte1]: 55
7900 11:03:50.901236
7901 11:03:50.901305 Set Vref, RX VrefLevel [Byte0]: 56
7902 11:03:50.904383 [Byte1]: 56
7903 11:03:50.908596
7904 11:03:50.908688 Set Vref, RX VrefLevel [Byte0]: 57
7905 11:03:50.911717 [Byte1]: 57
7906 11:03:50.916150
7907 11:03:50.916241 Set Vref, RX VrefLevel [Byte0]: 58
7908 11:03:50.919625 [Byte1]: 58
7909 11:03:50.923931
7910 11:03:50.924021 Set Vref, RX VrefLevel [Byte0]: 59
7911 11:03:50.927033 [Byte1]: 59
7912 11:03:50.931234
7913 11:03:50.931327 Set Vref, RX VrefLevel [Byte0]: 60
7914 11:03:50.934190 [Byte1]: 60
7915 11:03:50.938660
7916 11:03:50.938757 Set Vref, RX VrefLevel [Byte0]: 61
7917 11:03:50.941845 [Byte1]: 61
7918 11:03:50.946521
7919 11:03:50.946591 Set Vref, RX VrefLevel [Byte0]: 62
7920 11:03:50.949965 [Byte1]: 62
7921 11:03:50.953740
7922 11:03:50.953809 Set Vref, RX VrefLevel [Byte0]: 63
7923 11:03:50.957164 [Byte1]: 63
7924 11:03:50.961198
7925 11:03:50.961290 Set Vref, RX VrefLevel [Byte0]: 64
7926 11:03:50.965057 [Byte1]: 64
7927 11:03:50.968995
7928 11:03:50.969089 Set Vref, RX VrefLevel [Byte0]: 65
7929 11:03:50.972364 [Byte1]: 65
7930 11:03:50.976321
7931 11:03:50.976412 Set Vref, RX VrefLevel [Byte0]: 66
7932 11:03:50.979710 [Byte1]: 66
7933 11:03:50.983902
7934 11:03:50.983995 Set Vref, RX VrefLevel [Byte0]: 67
7935 11:03:50.987023 [Byte1]: 67
7936 11:03:50.991503
7937 11:03:50.991570 Set Vref, RX VrefLevel [Byte0]: 68
7938 11:03:50.994952 [Byte1]: 68
7939 11:03:50.998981
7940 11:03:50.999046 Set Vref, RX VrefLevel [Byte0]: 69
7941 11:03:51.002632 [Byte1]: 69
7942 11:03:51.006861
7943 11:03:51.006935 Set Vref, RX VrefLevel [Byte0]: 70
7944 11:03:51.010201 [Byte1]: 70
7945 11:03:51.014218
7946 11:03:51.014280 Set Vref, RX VrefLevel [Byte0]: 71
7947 11:03:51.017376 [Byte1]: 71
7948 11:03:51.021933
7949 11:03:51.022027 Set Vref, RX VrefLevel [Byte0]: 72
7950 11:03:51.024892 [Byte1]: 72
7951 11:03:51.029387
7952 11:03:51.029486 Set Vref, RX VrefLevel [Byte0]: 73
7953 11:03:51.032357 [Byte1]: 73
7954 11:03:51.036822
7955 11:03:51.036897 Final RX Vref Byte 0 = 54 to rank0
7956 11:03:51.040256 Final RX Vref Byte 1 = 61 to rank0
7957 11:03:51.043266 Final RX Vref Byte 0 = 54 to rank1
7958 11:03:51.047110 Final RX Vref Byte 1 = 61 to rank1==
7959 11:03:51.049943 Dram Type= 6, Freq= 0, CH_0, rank 0
7960 11:03:51.056369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7961 11:03:51.056444 ==
7962 11:03:51.056501 DQS Delay:
7963 11:03:51.056585 DQS0 = 0, DQS1 = 0
7964 11:03:51.059948 DQM Delay:
7965 11:03:51.060022 DQM0 = 133, DQM1 = 128
7966 11:03:51.063259 DQ Delay:
7967 11:03:51.066620 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =130
7968 11:03:51.070138 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =138
7969 11:03:51.073376 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7970 11:03:51.076991 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =136
7971 11:03:51.077084
7972 11:03:51.077177
7973 11:03:51.077260
7974 11:03:51.080006 [DramC_TX_OE_Calibration] TA2
7975 11:03:51.083381 Original DQ_B0 (3 6) =30, OEN = 27
7976 11:03:51.086818 Original DQ_B1 (3 6) =30, OEN = 27
7977 11:03:51.089723 24, 0x0, End_B0=24 End_B1=24
7978 11:03:51.089794 25, 0x0, End_B0=25 End_B1=25
7979 11:03:51.092960 26, 0x0, End_B0=26 End_B1=26
7980 11:03:51.096374 27, 0x0, End_B0=27 End_B1=27
7981 11:03:51.099851 28, 0x0, End_B0=28 End_B1=28
7982 11:03:51.103099 29, 0x0, End_B0=29 End_B1=29
7983 11:03:51.103165 30, 0x0, End_B0=30 End_B1=30
7984 11:03:51.106310 31, 0x4141, End_B0=30 End_B1=30
7985 11:03:51.110125 Byte0 end_step=30 best_step=27
7986 11:03:51.112921 Byte1 end_step=30 best_step=27
7987 11:03:51.116166 Byte0 TX OE(2T, 0.5T) = (3, 3)
7988 11:03:51.116255 Byte1 TX OE(2T, 0.5T) = (3, 3)
7989 11:03:51.119961
7990 11:03:51.120026
7991 11:03:51.126512 [DQSOSCAuto] RK0, (LSB)MR18= 0x2823, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
7992 11:03:51.129606 CH0 RK0: MR19=303, MR18=2823
7993 11:03:51.136385 CH0_RK0: MR19=0x303, MR18=0x2823, DQSOSC=389, MR23=63, INC=24, DEC=16
7994 11:03:51.136477
7995 11:03:51.139493 ----->DramcWriteLeveling(PI) begin...
7996 11:03:51.139579 ==
7997 11:03:51.142699 Dram Type= 6, Freq= 0, CH_0, rank 1
7998 11:03:51.146614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7999 11:03:51.146678 ==
8000 11:03:51.149916 Write leveling (Byte 0): 37 => 37
8001 11:03:51.153076 Write leveling (Byte 1): 27 => 27
8002 11:03:51.156568 DramcWriteLeveling(PI) end<-----
8003 11:03:51.156654
8004 11:03:51.156733 ==
8005 11:03:51.159252 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 11:03:51.163338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 11:03:51.163402 ==
8008 11:03:51.165922 [Gating] SW mode calibration
8009 11:03:51.172956 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8010 11:03:51.179250 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8011 11:03:51.183181 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 11:03:51.186136 1 4 4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8013 11:03:51.192743 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8014 11:03:51.195910 1 4 12 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
8015 11:03:51.199485 1 4 16 | B1->B0 | 3131 3838 | 1 1 | (1 1) (1 1)
8016 11:03:51.205933 1 4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8017 11:03:51.209137 1 4 24 | B1->B0 | 3434 3938 | 1 1 | (1 1) (0 0)
8018 11:03:51.212631 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
8019 11:03:51.219147 1 5 0 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
8020 11:03:51.222701 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 11:03:51.225967 1 5 8 | B1->B0 | 3434 3837 | 1 1 | (1 1) (0 0)
8022 11:03:51.232819 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
8023 11:03:51.236091 1 5 16 | B1->B0 | 3030 2525 | 0 0 | (0 1) (1 0)
8024 11:03:51.239126 1 5 20 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
8025 11:03:51.245888 1 5 24 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
8026 11:03:51.249161 1 5 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8027 11:03:51.252477 1 6 0 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
8028 11:03:51.259073 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8029 11:03:51.262890 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8030 11:03:51.265626 1 6 12 | B1->B0 | 2424 3535 | 0 1 | (0 0) (1 1)
8031 11:03:51.272797 1 6 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
8032 11:03:51.275935 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 11:03:51.279409 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 11:03:51.286383 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 11:03:51.288812 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 11:03:51.292487 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 11:03:51.295956 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 11:03:51.302876 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8039 11:03:51.305663 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8040 11:03:51.308900 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 11:03:51.316059 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 11:03:51.319506 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 11:03:51.322485 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 11:03:51.329064 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 11:03:51.332203 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 11:03:51.335598 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 11:03:51.342431 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 11:03:51.345531 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 11:03:51.349109 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 11:03:51.355644 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 11:03:51.359571 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 11:03:51.362148 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 11:03:51.369259 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 11:03:51.372496 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8055 11:03:51.375725 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8056 11:03:51.382407 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 11:03:51.382499 Total UI for P1: 0, mck2ui 16
8058 11:03:51.389072 best dqsien dly found for B0: ( 1, 9, 14)
8059 11:03:51.389165 Total UI for P1: 0, mck2ui 16
8060 11:03:51.392374 best dqsien dly found for B1: ( 1, 9, 14)
8061 11:03:51.398793 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8062 11:03:51.402416 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8063 11:03:51.402501
8064 11:03:51.405910 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8065 11:03:51.409308 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8066 11:03:51.412530 [Gating] SW calibration Done
8067 11:03:51.412605 ==
8068 11:03:51.415554 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 11:03:51.418608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 11:03:51.418683 ==
8071 11:03:51.422111 RX Vref Scan: 0
8072 11:03:51.422186
8073 11:03:51.422275 RX Vref 0 -> 0, step: 1
8074 11:03:51.422329
8075 11:03:51.425736 RX Delay 0 -> 252, step: 8
8076 11:03:51.428702 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8077 11:03:51.432309 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8078 11:03:51.439209 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8079 11:03:51.442312 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8080 11:03:51.445430 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8081 11:03:51.448723 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8082 11:03:51.451964 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8083 11:03:51.458510 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
8084 11:03:51.462453 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8085 11:03:51.465453 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8086 11:03:51.468853 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8087 11:03:51.475328 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8088 11:03:51.478672 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8089 11:03:51.481848 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8090 11:03:51.485232 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8091 11:03:51.488430 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8092 11:03:51.492259 ==
8093 11:03:51.492328 Dram Type= 6, Freq= 0, CH_0, rank 1
8094 11:03:51.498841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8095 11:03:51.498904 ==
8096 11:03:51.498958 DQS Delay:
8097 11:03:51.501444 DQS0 = 0, DQS1 = 0
8098 11:03:51.501502 DQM Delay:
8099 11:03:51.505314 DQM0 = 137, DQM1 = 128
8100 11:03:51.505371 DQ Delay:
8101 11:03:51.508775 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8102 11:03:51.511829 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =147
8103 11:03:51.514845 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8104 11:03:51.518481 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8105 11:03:51.518542
8106 11:03:51.518593
8107 11:03:51.518643 ==
8108 11:03:51.522043 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 11:03:51.528250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 11:03:51.528324 ==
8111 11:03:51.528379
8112 11:03:51.528431
8113 11:03:51.528480 TX Vref Scan disable
8114 11:03:51.531900 == TX Byte 0 ==
8115 11:03:51.534952 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8116 11:03:51.538552 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8117 11:03:51.541558 == TX Byte 1 ==
8118 11:03:51.545191 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8119 11:03:51.551486 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8120 11:03:51.551554 ==
8121 11:03:51.555288 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 11:03:51.558072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 11:03:51.558158 ==
8124 11:03:51.571988
8125 11:03:51.575219 TX Vref early break, caculate TX vref
8126 11:03:51.578417 TX Vref=16, minBit 1, minWin=23, winSum=389
8127 11:03:51.582383 TX Vref=18, minBit 3, minWin=23, winSum=397
8128 11:03:51.585639 TX Vref=20, minBit 1, minWin=24, winSum=404
8129 11:03:51.588320 TX Vref=22, minBit 3, minWin=24, winSum=414
8130 11:03:51.591629 TX Vref=24, minBit 1, minWin=25, winSum=421
8131 11:03:51.598958 TX Vref=26, minBit 4, minWin=25, winSum=424
8132 11:03:51.602224 TX Vref=28, minBit 0, minWin=26, winSum=425
8133 11:03:51.605750 TX Vref=30, minBit 0, minWin=25, winSum=416
8134 11:03:51.608673 TX Vref=32, minBit 0, minWin=24, winSum=409
8135 11:03:51.612192 TX Vref=34, minBit 1, minWin=24, winSum=401
8136 11:03:51.618779 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
8137 11:03:51.618847
8138 11:03:51.622114 Final TX Range 0 Vref 28
8139 11:03:51.622187
8140 11:03:51.622243 ==
8141 11:03:51.625529 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 11:03:51.628745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 11:03:51.628808 ==
8144 11:03:51.628861
8145 11:03:51.628921
8146 11:03:51.631898 TX Vref Scan disable
8147 11:03:51.638772 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8148 11:03:51.638838 == TX Byte 0 ==
8149 11:03:51.641958 u2DelayCellOfst[0]=17 cells (5 PI)
8150 11:03:51.645286 u2DelayCellOfst[1]=17 cells (5 PI)
8151 11:03:51.648951 u2DelayCellOfst[2]=13 cells (4 PI)
8152 11:03:51.652410 u2DelayCellOfst[3]=10 cells (3 PI)
8153 11:03:51.655137 u2DelayCellOfst[4]=10 cells (3 PI)
8154 11:03:51.658750 u2DelayCellOfst[5]=0 cells (0 PI)
8155 11:03:51.658811 u2DelayCellOfst[6]=17 cells (5 PI)
8156 11:03:51.661803 u2DelayCellOfst[7]=17 cells (5 PI)
8157 11:03:51.668674 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8158 11:03:51.671884 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8159 11:03:51.671977 == TX Byte 1 ==
8160 11:03:51.675105 u2DelayCellOfst[8]=0 cells (0 PI)
8161 11:03:51.678331 u2DelayCellOfst[9]=0 cells (0 PI)
8162 11:03:51.682233 u2DelayCellOfst[10]=6 cells (2 PI)
8163 11:03:51.685230 u2DelayCellOfst[11]=3 cells (1 PI)
8164 11:03:51.688619 u2DelayCellOfst[12]=10 cells (3 PI)
8165 11:03:51.691924 u2DelayCellOfst[13]=10 cells (3 PI)
8166 11:03:51.694994 u2DelayCellOfst[14]=13 cells (4 PI)
8167 11:03:51.698850 u2DelayCellOfst[15]=10 cells (3 PI)
8168 11:03:51.701709 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8169 11:03:51.705060 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8170 11:03:51.708543 DramC Write-DBI on
8171 11:03:51.708627 ==
8172 11:03:51.711671 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 11:03:51.715106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 11:03:51.715171 ==
8175 11:03:51.715223
8176 11:03:51.718805
8177 11:03:51.718862 TX Vref Scan disable
8178 11:03:51.721552 == TX Byte 0 ==
8179 11:03:51.725073 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8180 11:03:51.728807 == TX Byte 1 ==
8181 11:03:51.731977 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8182 11:03:51.732044 DramC Write-DBI off
8183 11:03:51.732096
8184 11:03:51.735433 [DATLAT]
8185 11:03:51.735491 Freq=1600, CH0 RK1
8186 11:03:51.735542
8187 11:03:51.738529 DATLAT Default: 0xf
8188 11:03:51.738611 0, 0xFFFF, sum = 0
8189 11:03:51.741895 1, 0xFFFF, sum = 0
8190 11:03:51.741980 2, 0xFFFF, sum = 0
8191 11:03:51.745346 3, 0xFFFF, sum = 0
8192 11:03:51.745411 4, 0xFFFF, sum = 0
8193 11:03:51.748525 5, 0xFFFF, sum = 0
8194 11:03:51.748613 6, 0xFFFF, sum = 0
8195 11:03:51.751573 7, 0xFFFF, sum = 0
8196 11:03:51.754826 8, 0xFFFF, sum = 0
8197 11:03:51.754887 9, 0xFFFF, sum = 0
8198 11:03:51.758264 10, 0xFFFF, sum = 0
8199 11:03:51.758349 11, 0xFFFF, sum = 0
8200 11:03:51.761849 12, 0xFFFF, sum = 0
8201 11:03:51.761915 13, 0xFFFF, sum = 0
8202 11:03:51.764943 14, 0x0, sum = 1
8203 11:03:51.765004 15, 0x0, sum = 2
8204 11:03:51.768594 16, 0x0, sum = 3
8205 11:03:51.768682 17, 0x0, sum = 4
8206 11:03:51.771540 best_step = 15
8207 11:03:51.771605
8208 11:03:51.771661 ==
8209 11:03:51.774992 Dram Type= 6, Freq= 0, CH_0, rank 1
8210 11:03:51.778222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8211 11:03:51.778284 ==
8212 11:03:51.778336 RX Vref Scan: 0
8213 11:03:51.778386
8214 11:03:51.781383 RX Vref 0 -> 0, step: 1
8215 11:03:51.781481
8216 11:03:51.784542 RX Delay 19 -> 252, step: 4
8217 11:03:51.788556 iDelay=191, Bit 0, Center 132 (79 ~ 186) 108
8218 11:03:51.794646 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8219 11:03:51.798077 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8220 11:03:51.801684 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8221 11:03:51.805579 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8222 11:03:51.807857 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8223 11:03:51.811677 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8224 11:03:51.818035 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8225 11:03:51.821913 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8226 11:03:51.825127 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8227 11:03:51.828449 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8228 11:03:51.831701 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8229 11:03:51.838065 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8230 11:03:51.841532 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8231 11:03:51.844847 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8232 11:03:51.848017 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8233 11:03:51.848104 ==
8234 11:03:51.851204 Dram Type= 6, Freq= 0, CH_0, rank 1
8235 11:03:51.857868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8236 11:03:51.857960 ==
8237 11:03:51.858073 DQS Delay:
8238 11:03:51.861151 DQS0 = 0, DQS1 = 0
8239 11:03:51.861234 DQM Delay:
8240 11:03:51.861313 DQM0 = 134, DQM1 = 127
8241 11:03:51.865079 DQ Delay:
8242 11:03:51.867777 DQ0 =132, DQ1 =138, DQ2 =130, DQ3 =132
8243 11:03:51.871349 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =142
8244 11:03:51.875071 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8245 11:03:51.877760 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8246 11:03:51.877846
8247 11:03:51.877925
8248 11:03:51.878002
8249 11:03:51.881622 [DramC_TX_OE_Calibration] TA2
8250 11:03:51.884737 Original DQ_B0 (3 6) =30, OEN = 27
8251 11:03:51.888038 Original DQ_B1 (3 6) =30, OEN = 27
8252 11:03:51.891280 24, 0x0, End_B0=24 End_B1=24
8253 11:03:51.891347 25, 0x0, End_B0=25 End_B1=25
8254 11:03:51.894699 26, 0x0, End_B0=26 End_B1=26
8255 11:03:51.897832 27, 0x0, End_B0=27 End_B1=27
8256 11:03:51.901729 28, 0x0, End_B0=28 End_B1=28
8257 11:03:51.904737 29, 0x0, End_B0=29 End_B1=29
8258 11:03:51.904808 30, 0x0, End_B0=30 End_B1=30
8259 11:03:51.907936 31, 0x4141, End_B0=30 End_B1=30
8260 11:03:51.911200 Byte0 end_step=30 best_step=27
8261 11:03:51.914811 Byte1 end_step=30 best_step=27
8262 11:03:51.917797 Byte0 TX OE(2T, 0.5T) = (3, 3)
8263 11:03:51.921697 Byte1 TX OE(2T, 0.5T) = (3, 3)
8264 11:03:51.921765
8265 11:03:51.921820
8266 11:03:51.928313 [DQSOSCAuto] RK1, (LSB)MR18= 0x230b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8267 11:03:51.931473 CH0 RK1: MR19=303, MR18=230B
8268 11:03:51.938152 CH0_RK1: MR19=0x303, MR18=0x230B, DQSOSC=392, MR23=63, INC=24, DEC=16
8269 11:03:51.941295 [RxdqsGatingPostProcess] freq 1600
8270 11:03:51.944712 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8271 11:03:51.947737 best DQS0 dly(2T, 0.5T) = (1, 1)
8272 11:03:51.951449 best DQS1 dly(2T, 0.5T) = (1, 1)
8273 11:03:51.954687 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8274 11:03:51.957980 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8275 11:03:51.961166 best DQS0 dly(2T, 0.5T) = (1, 1)
8276 11:03:51.964444 best DQS1 dly(2T, 0.5T) = (1, 1)
8277 11:03:51.967939 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8278 11:03:51.971306 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8279 11:03:51.974387 Pre-setting of DQS Precalculation
8280 11:03:51.977860 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8281 11:03:51.977926 ==
8282 11:03:51.981033 Dram Type= 6, Freq= 0, CH_1, rank 0
8283 11:03:51.984364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8284 11:03:51.987595 ==
8285 11:03:51.990900 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8286 11:03:51.994188 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8287 11:03:52.001246 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8288 11:03:52.004210 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8289 11:03:52.014615 [CA 0] Center 42 (12~72) winsize 61
8290 11:03:52.017858 [CA 1] Center 42 (12~72) winsize 61
8291 11:03:52.021170 [CA 2] Center 39 (10~68) winsize 59
8292 11:03:52.024382 [CA 3] Center 38 (9~67) winsize 59
8293 11:03:52.027761 [CA 4] Center 38 (9~68) winsize 60
8294 11:03:52.031037 [CA 5] Center 37 (8~67) winsize 60
8295 11:03:52.031107
8296 11:03:52.034158 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8297 11:03:52.034229
8298 11:03:52.037650 [CATrainingPosCal] consider 1 rank data
8299 11:03:52.040906 u2DelayCellTimex100 = 285/100 ps
8300 11:03:52.044590 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8301 11:03:52.051338 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8302 11:03:52.054459 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8303 11:03:52.057744 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8304 11:03:52.061040 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8305 11:03:52.064415 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8306 11:03:52.064515
8307 11:03:52.067570 CA PerBit enable=1, Macro0, CA PI delay=37
8308 11:03:52.067656
8309 11:03:52.071504 [CBTSetCACLKResult] CA Dly = 37
8310 11:03:52.074331 CS Dly: 10 (0~41)
8311 11:03:52.078135 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8312 11:03:52.081278 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8313 11:03:52.081365 ==
8314 11:03:52.084518 Dram Type= 6, Freq= 0, CH_1, rank 1
8315 11:03:52.087364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 11:03:52.090738 ==
8317 11:03:52.094153 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8318 11:03:52.097416 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8319 11:03:52.104480 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8320 11:03:52.107705 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8321 11:03:52.117980 [CA 0] Center 42 (12~72) winsize 61
8322 11:03:52.121307 [CA 1] Center 41 (12~71) winsize 60
8323 11:03:52.124443 [CA 2] Center 38 (9~68) winsize 60
8324 11:03:52.127833 [CA 3] Center 37 (8~67) winsize 60
8325 11:03:52.131345 [CA 4] Center 38 (8~68) winsize 61
8326 11:03:52.134673 [CA 5] Center 37 (8~67) winsize 60
8327 11:03:52.134737
8328 11:03:52.137900 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8329 11:03:52.137984
8330 11:03:52.141087 [CATrainingPosCal] consider 2 rank data
8331 11:03:52.144774 u2DelayCellTimex100 = 285/100 ps
8332 11:03:52.148030 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8333 11:03:52.154621 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8334 11:03:52.157898 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8335 11:03:52.161501 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8336 11:03:52.164659 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8337 11:03:52.168083 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8338 11:03:52.168174
8339 11:03:52.171318 CA PerBit enable=1, Macro0, CA PI delay=37
8340 11:03:52.171387
8341 11:03:52.174540 [CBTSetCACLKResult] CA Dly = 37
8342 11:03:52.178173 CS Dly: 11 (0~44)
8343 11:03:52.181470 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8344 11:03:52.184560 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8345 11:03:52.184651
8346 11:03:52.188311 ----->DramcWriteLeveling(PI) begin...
8347 11:03:52.188402 ==
8348 11:03:52.191338 Dram Type= 6, Freq= 0, CH_1, rank 0
8349 11:03:52.194543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8350 11:03:52.197822 ==
8351 11:03:52.197910 Write leveling (Byte 0): 25 => 25
8352 11:03:52.201040 Write leveling (Byte 1): 28 => 28
8353 11:03:52.204371 DramcWriteLeveling(PI) end<-----
8354 11:03:52.204455
8355 11:03:52.204532 ==
8356 11:03:52.207452 Dram Type= 6, Freq= 0, CH_1, rank 0
8357 11:03:52.214094 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8358 11:03:52.214169 ==
8359 11:03:52.217511 [Gating] SW mode calibration
8360 11:03:52.224578 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8361 11:03:52.227852 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8362 11:03:52.234342 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 11:03:52.237568 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 11:03:52.241147 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8365 11:03:52.247637 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8366 11:03:52.250822 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 11:03:52.254607 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 11:03:52.257541 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 11:03:52.263897 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 11:03:52.267603 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 11:03:52.271245 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 11:03:52.277087 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
8373 11:03:52.280732 1 5 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (1 0)
8374 11:03:52.283732 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 11:03:52.290711 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 11:03:52.293926 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 11:03:52.296967 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 11:03:52.304461 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 11:03:52.307237 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 11:03:52.310883 1 6 8 | B1->B0 | 2525 4242 | 0 1 | (0 0) (0 0)
8381 11:03:52.317352 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 11:03:52.320439 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 11:03:52.323801 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 11:03:52.330340 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 11:03:52.333711 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 11:03:52.337534 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 11:03:52.344385 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 11:03:52.347589 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8389 11:03:52.351225 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8390 11:03:52.357507 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 11:03:52.360455 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 11:03:52.363582 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 11:03:52.370484 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 11:03:52.373900 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 11:03:52.377101 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 11:03:52.383763 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 11:03:52.387238 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 11:03:52.390415 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 11:03:52.396712 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 11:03:52.400644 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 11:03:52.403825 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 11:03:52.407094 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 11:03:52.413730 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 11:03:52.416820 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8405 11:03:52.420424 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8406 11:03:52.427492 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 11:03:52.430536 Total UI for P1: 0, mck2ui 16
8408 11:03:52.433559 best dqsien dly found for B0: ( 1, 9, 10)
8409 11:03:52.433654 Total UI for P1: 0, mck2ui 16
8410 11:03:52.440084 best dqsien dly found for B1: ( 1, 9, 10)
8411 11:03:52.443321 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8412 11:03:52.446829 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8413 11:03:52.446918
8414 11:03:52.450246 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8415 11:03:52.453424 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8416 11:03:52.456611 [Gating] SW calibration Done
8417 11:03:52.456706 ==
8418 11:03:52.460536 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 11:03:52.464188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 11:03:52.464285 ==
8421 11:03:52.467079 RX Vref Scan: 0
8422 11:03:52.467172
8423 11:03:52.467256 RX Vref 0 -> 0, step: 1
8424 11:03:52.467336
8425 11:03:52.470585 RX Delay 0 -> 252, step: 8
8426 11:03:52.473550 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8427 11:03:52.480343 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8428 11:03:52.483815 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8429 11:03:52.487127 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8430 11:03:52.490309 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8431 11:03:52.493782 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8432 11:03:52.500415 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8433 11:03:52.503756 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8434 11:03:52.507270 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8435 11:03:52.510516 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8436 11:03:52.513827 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8437 11:03:52.520601 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8438 11:03:52.523237 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8439 11:03:52.526895 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8440 11:03:52.529919 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8441 11:03:52.533420 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8442 11:03:52.536583 ==
8443 11:03:52.536658 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 11:03:52.543223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 11:03:52.543301 ==
8446 11:03:52.543361 DQS Delay:
8447 11:03:52.546529 DQS0 = 0, DQS1 = 0
8448 11:03:52.546604 DQM Delay:
8449 11:03:52.549600 DQM0 = 136, DQM1 = 132
8450 11:03:52.549676 DQ Delay:
8451 11:03:52.553196 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8452 11:03:52.556633 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8453 11:03:52.559861 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8454 11:03:52.563010 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8455 11:03:52.563086
8456 11:03:52.563145
8457 11:03:52.563202 ==
8458 11:03:52.566846 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 11:03:52.573419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 11:03:52.573529 ==
8461 11:03:52.573615
8462 11:03:52.573707
8463 11:03:52.573787 TX Vref Scan disable
8464 11:03:52.576708 == TX Byte 0 ==
8465 11:03:52.579921 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8466 11:03:52.586608 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8467 11:03:52.586679 == TX Byte 1 ==
8468 11:03:52.590156 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8469 11:03:52.596663 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8470 11:03:52.596736 ==
8471 11:03:52.599614 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 11:03:52.603282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 11:03:52.603352 ==
8474 11:03:52.615366
8475 11:03:52.618842 TX Vref early break, caculate TX vref
8476 11:03:52.621922 TX Vref=16, minBit 0, minWin=22, winSum=377
8477 11:03:52.625346 TX Vref=18, minBit 5, minWin=23, winSum=389
8478 11:03:52.628657 TX Vref=20, minBit 0, minWin=24, winSum=398
8479 11:03:52.631944 TX Vref=22, minBit 1, minWin=24, winSum=409
8480 11:03:52.635155 TX Vref=24, minBit 9, minWin=24, winSum=415
8481 11:03:52.642393 TX Vref=26, minBit 0, minWin=26, winSum=427
8482 11:03:52.645579 TX Vref=28, minBit 0, minWin=26, winSum=427
8483 11:03:52.648816 TX Vref=30, minBit 0, minWin=25, winSum=418
8484 11:03:52.652097 TX Vref=32, minBit 0, minWin=24, winSum=414
8485 11:03:52.655397 TX Vref=34, minBit 2, minWin=24, winSum=401
8486 11:03:52.662233 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 26
8487 11:03:52.662306
8488 11:03:52.665200 Final TX Range 0 Vref 26
8489 11:03:52.665289
8490 11:03:52.665372 ==
8491 11:03:52.668352 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 11:03:52.672076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 11:03:52.672154 ==
8494 11:03:52.672211
8495 11:03:52.672271
8496 11:03:52.675444 TX Vref Scan disable
8497 11:03:52.681868 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8498 11:03:52.681962 == TX Byte 0 ==
8499 11:03:52.685136 u2DelayCellOfst[0]=13 cells (4 PI)
8500 11:03:52.688483 u2DelayCellOfst[1]=10 cells (3 PI)
8501 11:03:52.692078 u2DelayCellOfst[2]=0 cells (0 PI)
8502 11:03:52.695292 u2DelayCellOfst[3]=3 cells (1 PI)
8503 11:03:52.698396 u2DelayCellOfst[4]=6 cells (2 PI)
8504 11:03:52.701996 u2DelayCellOfst[5]=17 cells (5 PI)
8505 11:03:52.704934 u2DelayCellOfst[6]=17 cells (5 PI)
8506 11:03:52.704998 u2DelayCellOfst[7]=6 cells (2 PI)
8507 11:03:52.711948 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8508 11:03:52.715119 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8509 11:03:52.715186 == TX Byte 1 ==
8510 11:03:52.718867 u2DelayCellOfst[8]=0 cells (0 PI)
8511 11:03:52.721785 u2DelayCellOfst[9]=0 cells (0 PI)
8512 11:03:52.724914 u2DelayCellOfst[10]=13 cells (4 PI)
8513 11:03:52.728472 u2DelayCellOfst[11]=3 cells (1 PI)
8514 11:03:52.731725 u2DelayCellOfst[12]=17 cells (5 PI)
8515 11:03:52.735023 u2DelayCellOfst[13]=13 cells (4 PI)
8516 11:03:52.738231 u2DelayCellOfst[14]=17 cells (5 PI)
8517 11:03:52.741445 u2DelayCellOfst[15]=17 cells (5 PI)
8518 11:03:52.744919 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8519 11:03:52.751477 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8520 11:03:52.751546 DramC Write-DBI on
8521 11:03:52.751602 ==
8522 11:03:52.754661 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 11:03:52.757946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 11:03:52.758063 ==
8525 11:03:52.761410
8526 11:03:52.761474
8527 11:03:52.761535 TX Vref Scan disable
8528 11:03:52.764958 == TX Byte 0 ==
8529 11:03:52.768271 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8530 11:03:52.771948 == TX Byte 1 ==
8531 11:03:52.774818 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8532 11:03:52.774889 DramC Write-DBI off
8533 11:03:52.778223
8534 11:03:52.778291 [DATLAT]
8535 11:03:52.778344 Freq=1600, CH1 RK0
8536 11:03:52.778396
8537 11:03:52.781601 DATLAT Default: 0xf
8538 11:03:52.781686 0, 0xFFFF, sum = 0
8539 11:03:52.784594 1, 0xFFFF, sum = 0
8540 11:03:52.784680 2, 0xFFFF, sum = 0
8541 11:03:52.788148 3, 0xFFFF, sum = 0
8542 11:03:52.788260 4, 0xFFFF, sum = 0
8543 11:03:52.791383 5, 0xFFFF, sum = 0
8544 11:03:52.791449 6, 0xFFFF, sum = 0
8545 11:03:52.794790 7, 0xFFFF, sum = 0
8546 11:03:52.798450 8, 0xFFFF, sum = 0
8547 11:03:52.798525 9, 0xFFFF, sum = 0
8548 11:03:52.801480 10, 0xFFFF, sum = 0
8549 11:03:52.801568 11, 0xFFFF, sum = 0
8550 11:03:52.805034 12, 0xFFFF, sum = 0
8551 11:03:52.805121 13, 0xFFFF, sum = 0
8552 11:03:52.807804 14, 0x0, sum = 1
8553 11:03:52.807867 15, 0x0, sum = 2
8554 11:03:52.811218 16, 0x0, sum = 3
8555 11:03:52.811288 17, 0x0, sum = 4
8556 11:03:52.814387 best_step = 15
8557 11:03:52.814451
8558 11:03:52.814508 ==
8559 11:03:52.818284 Dram Type= 6, Freq= 0, CH_1, rank 0
8560 11:03:52.820929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8561 11:03:52.821022 ==
8562 11:03:52.821106 RX Vref Scan: 1
8563 11:03:52.824579
8564 11:03:52.824666 Set Vref Range= 24 -> 127
8565 11:03:52.824749
8566 11:03:52.828003 RX Vref 24 -> 127, step: 1
8567 11:03:52.828068
8568 11:03:52.831329 RX Delay 27 -> 252, step: 4
8569 11:03:52.831394
8570 11:03:52.835069 Set Vref, RX VrefLevel [Byte0]: 24
8571 11:03:52.837833 [Byte1]: 24
8572 11:03:52.837921
8573 11:03:52.841067 Set Vref, RX VrefLevel [Byte0]: 25
8574 11:03:52.844762 [Byte1]: 25
8575 11:03:52.844856
8576 11:03:52.847949 Set Vref, RX VrefLevel [Byte0]: 26
8577 11:03:52.851186 [Byte1]: 26
8578 11:03:52.854951
8579 11:03:52.855021 Set Vref, RX VrefLevel [Byte0]: 27
8580 11:03:52.858088 [Byte1]: 27
8581 11:03:52.862381
8582 11:03:52.862447 Set Vref, RX VrefLevel [Byte0]: 28
8583 11:03:52.865587 [Byte1]: 28
8584 11:03:52.870172
8585 11:03:52.870265 Set Vref, RX VrefLevel [Byte0]: 29
8586 11:03:52.873518 [Byte1]: 29
8587 11:03:52.877489
8588 11:03:52.877595 Set Vref, RX VrefLevel [Byte0]: 30
8589 11:03:52.880789 [Byte1]: 30
8590 11:03:52.884853
8591 11:03:52.884945 Set Vref, RX VrefLevel [Byte0]: 31
8592 11:03:52.888137 [Byte1]: 31
8593 11:03:52.892748
8594 11:03:52.892850 Set Vref, RX VrefLevel [Byte0]: 32
8595 11:03:52.896217 [Byte1]: 32
8596 11:03:52.900178
8597 11:03:52.900268 Set Vref, RX VrefLevel [Byte0]: 33
8598 11:03:52.903300 [Byte1]: 33
8599 11:03:52.907246
8600 11:03:52.907334 Set Vref, RX VrefLevel [Byte0]: 34
8601 11:03:52.910723 [Byte1]: 34
8602 11:03:52.914806
8603 11:03:52.914898 Set Vref, RX VrefLevel [Byte0]: 35
8604 11:03:52.918203 [Byte1]: 35
8605 11:03:52.922716
8606 11:03:52.922824 Set Vref, RX VrefLevel [Byte0]: 36
8607 11:03:52.925841 [Byte1]: 36
8608 11:03:52.929918
8609 11:03:52.930014 Set Vref, RX VrefLevel [Byte0]: 37
8610 11:03:52.934208 [Byte1]: 37
8611 11:03:52.937883
8612 11:03:52.937976 Set Vref, RX VrefLevel [Byte0]: 38
8613 11:03:52.941133 [Byte1]: 38
8614 11:03:52.945118
8615 11:03:52.945211 Set Vref, RX VrefLevel [Byte0]: 39
8616 11:03:52.948213 [Byte1]: 39
8617 11:03:52.952861
8618 11:03:52.952954 Set Vref, RX VrefLevel [Byte0]: 40
8619 11:03:52.956190 [Byte1]: 40
8620 11:03:52.960349
8621 11:03:52.960443 Set Vref, RX VrefLevel [Byte0]: 41
8622 11:03:52.963504 [Byte1]: 41
8623 11:03:52.968102
8624 11:03:52.968192 Set Vref, RX VrefLevel [Byte0]: 42
8625 11:03:52.970978 [Byte1]: 42
8626 11:03:52.975373
8627 11:03:52.975467 Set Vref, RX VrefLevel [Byte0]: 43
8628 11:03:52.978758 [Byte1]: 43
8629 11:03:52.982924
8630 11:03:52.983019 Set Vref, RX VrefLevel [Byte0]: 44
8631 11:03:52.986189 [Byte1]: 44
8632 11:03:52.990806
8633 11:03:52.990877 Set Vref, RX VrefLevel [Byte0]: 45
8634 11:03:52.994022 [Byte1]: 45
8635 11:03:52.998482
8636 11:03:52.998577 Set Vref, RX VrefLevel [Byte0]: 46
8637 11:03:53.000980 [Byte1]: 46
8638 11:03:53.005778
8639 11:03:53.005873 Set Vref, RX VrefLevel [Byte0]: 47
8640 11:03:53.008825 [Byte1]: 47
8641 11:03:53.012994
8642 11:03:53.013093 Set Vref, RX VrefLevel [Byte0]: 48
8643 11:03:53.016005 [Byte1]: 48
8644 11:03:53.020592
8645 11:03:53.020683 Set Vref, RX VrefLevel [Byte0]: 49
8646 11:03:53.023921 [Byte1]: 49
8647 11:03:53.028292
8648 11:03:53.028383 Set Vref, RX VrefLevel [Byte0]: 50
8649 11:03:53.031161 [Byte1]: 50
8650 11:03:53.035693
8651 11:03:53.035787 Set Vref, RX VrefLevel [Byte0]: 51
8652 11:03:53.038717 [Byte1]: 51
8653 11:03:53.043239
8654 11:03:53.043330 Set Vref, RX VrefLevel [Byte0]: 52
8655 11:03:53.046323 [Byte1]: 52
8656 11:03:53.050780
8657 11:03:53.050850 Set Vref, RX VrefLevel [Byte0]: 53
8658 11:03:53.053852 [Byte1]: 53
8659 11:03:53.057977
8660 11:03:53.058062 Set Vref, RX VrefLevel [Byte0]: 54
8661 11:03:53.061571 [Byte1]: 54
8662 11:03:53.065862
8663 11:03:53.065956 Set Vref, RX VrefLevel [Byte0]: 55
8664 11:03:53.069222 [Byte1]: 55
8665 11:03:53.073192
8666 11:03:53.073261 Set Vref, RX VrefLevel [Byte0]: 56
8667 11:03:53.076745 [Byte1]: 56
8668 11:03:53.080676
8669 11:03:53.080769 Set Vref, RX VrefLevel [Byte0]: 57
8670 11:03:53.083912 [Byte1]: 57
8671 11:03:53.088346
8672 11:03:53.088414 Set Vref, RX VrefLevel [Byte0]: 58
8673 11:03:53.091604 [Byte1]: 58
8674 11:03:53.095641
8675 11:03:53.095737 Set Vref, RX VrefLevel [Byte0]: 59
8676 11:03:53.099361 [Byte1]: 59
8677 11:03:53.103253
8678 11:03:53.103342 Set Vref, RX VrefLevel [Byte0]: 60
8679 11:03:53.106688 [Byte1]: 60
8680 11:03:53.111076
8681 11:03:53.111167 Set Vref, RX VrefLevel [Byte0]: 61
8682 11:03:53.114559 [Byte1]: 61
8683 11:03:53.118462
8684 11:03:53.118531 Set Vref, RX VrefLevel [Byte0]: 62
8685 11:03:53.121836 [Byte1]: 62
8686 11:03:53.125802
8687 11:03:53.125892 Set Vref, RX VrefLevel [Byte0]: 63
8688 11:03:53.129019 [Byte1]: 63
8689 11:03:53.133417
8690 11:03:53.133507 Set Vref, RX VrefLevel [Byte0]: 64
8691 11:03:53.136538 [Byte1]: 64
8692 11:03:53.140900
8693 11:03:53.140989 Set Vref, RX VrefLevel [Byte0]: 65
8694 11:03:53.144187 [Byte1]: 65
8695 11:03:53.148803
8696 11:03:53.148897 Set Vref, RX VrefLevel [Byte0]: 66
8697 11:03:53.151652 [Byte1]: 66
8698 11:03:53.155760
8699 11:03:53.155850 Set Vref, RX VrefLevel [Byte0]: 67
8700 11:03:53.159184 [Byte1]: 67
8701 11:03:53.163552
8702 11:03:53.163624 Set Vref, RX VrefLevel [Byte0]: 68
8703 11:03:53.167113 [Byte1]: 68
8704 11:03:53.170914
8705 11:03:53.171009 Set Vref, RX VrefLevel [Byte0]: 69
8706 11:03:53.174960 [Byte1]: 69
8707 11:03:53.178473
8708 11:03:53.178560 Set Vref, RX VrefLevel [Byte0]: 70
8709 11:03:53.181740 [Byte1]: 70
8710 11:03:53.186449
8711 11:03:53.186544 Set Vref, RX VrefLevel [Byte0]: 71
8712 11:03:53.189591 [Byte1]: 71
8713 11:03:53.194078
8714 11:03:53.194169 Set Vref, RX VrefLevel [Byte0]: 72
8715 11:03:53.196880 [Byte1]: 72
8716 11:03:53.201003
8717 11:03:53.201094 Set Vref, RX VrefLevel [Byte0]: 73
8718 11:03:53.204354 [Byte1]: 73
8719 11:03:53.208547
8720 11:03:53.208639 Set Vref, RX VrefLevel [Byte0]: 74
8721 11:03:53.211998 [Byte1]: 74
8722 11:03:53.216453
8723 11:03:53.216547 Set Vref, RX VrefLevel [Byte0]: 75
8724 11:03:53.219471 [Byte1]: 75
8725 11:03:53.224232
8726 11:03:53.224321 Final RX Vref Byte 0 = 58 to rank0
8727 11:03:53.226884 Final RX Vref Byte 1 = 60 to rank0
8728 11:03:53.230637 Final RX Vref Byte 0 = 58 to rank1
8729 11:03:53.233941 Final RX Vref Byte 1 = 60 to rank1==
8730 11:03:53.237148 Dram Type= 6, Freq= 0, CH_1, rank 0
8731 11:03:53.243600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8732 11:03:53.243694 ==
8733 11:03:53.243781 DQS Delay:
8734 11:03:53.247478 DQS0 = 0, DQS1 = 0
8735 11:03:53.247567 DQM Delay:
8736 11:03:53.247645 DQM0 = 134, DQM1 = 130
8737 11:03:53.250159 DQ Delay:
8738 11:03:53.254029 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8739 11:03:53.257281 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132
8740 11:03:53.260299 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =122
8741 11:03:53.264058 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
8742 11:03:53.264143
8743 11:03:53.264224
8744 11:03:53.264300
8745 11:03:53.267178 [DramC_TX_OE_Calibration] TA2
8746 11:03:53.270546 Original DQ_B0 (3 6) =30, OEN = 27
8747 11:03:53.273545 Original DQ_B1 (3 6) =30, OEN = 27
8748 11:03:53.277276 24, 0x0, End_B0=24 End_B1=24
8749 11:03:53.277371 25, 0x0, End_B0=25 End_B1=25
8750 11:03:53.280533 26, 0x0, End_B0=26 End_B1=26
8751 11:03:53.283503 27, 0x0, End_B0=27 End_B1=27
8752 11:03:53.287011 28, 0x0, End_B0=28 End_B1=28
8753 11:03:53.287102 29, 0x0, End_B0=29 End_B1=29
8754 11:03:53.290380 30, 0x0, End_B0=30 End_B1=30
8755 11:03:53.293547 31, 0x4141, End_B0=30 End_B1=30
8756 11:03:53.296868 Byte0 end_step=30 best_step=27
8757 11:03:53.301049 Byte1 end_step=30 best_step=27
8758 11:03:53.303545 Byte0 TX OE(2T, 0.5T) = (3, 3)
8759 11:03:53.306936 Byte1 TX OE(2T, 0.5T) = (3, 3)
8760 11:03:53.306998
8761 11:03:53.307051
8762 11:03:53.313426 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a28, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8763 11:03:53.316994 CH1 RK0: MR19=303, MR18=1A28
8764 11:03:53.323328 CH1_RK0: MR19=0x303, MR18=0x1A28, DQSOSC=389, MR23=63, INC=24, DEC=16
8765 11:03:53.323424
8766 11:03:53.327013 ----->DramcWriteLeveling(PI) begin...
8767 11:03:53.327114 ==
8768 11:03:53.330387 Dram Type= 6, Freq= 0, CH_1, rank 1
8769 11:03:53.333405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8770 11:03:53.333496 ==
8771 11:03:53.336544 Write leveling (Byte 0): 26 => 26
8772 11:03:53.339812 Write leveling (Byte 1): 28 => 28
8773 11:03:53.343231 DramcWriteLeveling(PI) end<-----
8774 11:03:53.343321
8775 11:03:53.343403 ==
8776 11:03:53.346482 Dram Type= 6, Freq= 0, CH_1, rank 1
8777 11:03:53.350219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8778 11:03:53.350332 ==
8779 11:03:53.353455 [Gating] SW mode calibration
8780 11:03:53.359866 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8781 11:03:53.366698 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8782 11:03:53.369822 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 11:03:53.373143 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 11:03:53.380010 1 4 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8785 11:03:53.383207 1 4 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
8786 11:03:53.386771 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 11:03:53.393370 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 11:03:53.396337 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 11:03:53.399853 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 11:03:53.406640 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 11:03:53.409866 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8792 11:03:53.413316 1 5 8 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 1)
8793 11:03:53.419713 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 11:03:53.423129 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8795 11:03:53.426729 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 11:03:53.433673 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 11:03:53.436867 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 11:03:53.439831 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 11:03:53.446430 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 11:03:53.449570 1 6 8 | B1->B0 | 403f 2424 | 1 0 | (0 0) (0 0)
8801 11:03:53.453268 1 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8802 11:03:53.459544 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 11:03:53.463545 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 11:03:53.466630 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 11:03:53.469809 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 11:03:53.476179 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 11:03:53.479830 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 11:03:53.482908 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8809 11:03:53.489490 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8810 11:03:53.493314 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 11:03:53.496423 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 11:03:53.503313 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 11:03:53.506356 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 11:03:53.509550 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 11:03:53.516328 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 11:03:53.520017 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 11:03:53.522938 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 11:03:53.529428 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 11:03:53.533332 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 11:03:53.536269 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 11:03:53.543291 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 11:03:53.546285 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 11:03:53.549280 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8824 11:03:53.555929 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8825 11:03:53.559430 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8826 11:03:53.562716 Total UI for P1: 0, mck2ui 16
8827 11:03:53.566362 best dqsien dly found for B1: ( 1, 9, 6)
8828 11:03:53.569463 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8829 11:03:53.576576 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 11:03:53.576652 Total UI for P1: 0, mck2ui 16
8831 11:03:53.579615 best dqsien dly found for B0: ( 1, 9, 12)
8832 11:03:53.582941 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8833 11:03:53.589520 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8834 11:03:53.589596
8835 11:03:53.593092 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8836 11:03:53.596000 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8837 11:03:53.599792 [Gating] SW calibration Done
8838 11:03:53.599866 ==
8839 11:03:53.602734 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 11:03:53.605977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 11:03:53.606078 ==
8842 11:03:53.609920 RX Vref Scan: 0
8843 11:03:53.610022
8844 11:03:53.610087 RX Vref 0 -> 0, step: 1
8845 11:03:53.610147
8846 11:03:53.612779 RX Delay 0 -> 252, step: 8
8847 11:03:53.616473 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8848 11:03:53.619181 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8849 11:03:53.626527 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8850 11:03:53.629300 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8851 11:03:53.632972 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8852 11:03:53.636568 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8853 11:03:53.639678 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8854 11:03:53.646437 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8855 11:03:53.649723 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8856 11:03:53.652908 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8857 11:03:53.656273 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8858 11:03:53.659603 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8859 11:03:53.666224 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8860 11:03:53.669897 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8861 11:03:53.672640 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8862 11:03:53.676061 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8863 11:03:53.676167 ==
8864 11:03:53.679422 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 11:03:53.686315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 11:03:53.686444 ==
8867 11:03:53.686558 DQS Delay:
8868 11:03:53.686668 DQS0 = 0, DQS1 = 0
8869 11:03:53.689920 DQM Delay:
8870 11:03:53.690051 DQM0 = 136, DQM1 = 133
8871 11:03:53.692924 DQ Delay:
8872 11:03:53.696068 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8873 11:03:53.699698 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8874 11:03:53.702732 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8875 11:03:53.706711 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8876 11:03:53.706833
8877 11:03:53.706947
8878 11:03:53.707056 ==
8879 11:03:53.709143 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 11:03:53.712556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 11:03:53.712658 ==
8882 11:03:53.716183
8883 11:03:53.716286
8884 11:03:53.716382 TX Vref Scan disable
8885 11:03:53.719261 == TX Byte 0 ==
8886 11:03:53.722976 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8887 11:03:53.726327 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8888 11:03:53.729273 == TX Byte 1 ==
8889 11:03:53.732509 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8890 11:03:53.735848 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8891 11:03:53.735946 ==
8892 11:03:53.739428 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 11:03:53.745879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 11:03:53.745963 ==
8895 11:03:53.757474
8896 11:03:53.760719 TX Vref early break, caculate TX vref
8897 11:03:53.764148 TX Vref=16, minBit 0, minWin=23, winSum=380
8898 11:03:53.767306 TX Vref=18, minBit 0, minWin=23, winSum=391
8899 11:03:53.770692 TX Vref=20, minBit 0, minWin=24, winSum=407
8900 11:03:53.774202 TX Vref=22, minBit 0, minWin=24, winSum=408
8901 11:03:53.777437 TX Vref=24, minBit 0, minWin=24, winSum=414
8902 11:03:53.784454 TX Vref=26, minBit 6, minWin=25, winSum=425
8903 11:03:53.787494 TX Vref=28, minBit 0, minWin=25, winSum=429
8904 11:03:53.790596 TX Vref=30, minBit 0, minWin=25, winSum=423
8905 11:03:53.794038 TX Vref=32, minBit 6, minWin=24, winSum=409
8906 11:03:53.797184 TX Vref=34, minBit 0, minWin=24, winSum=403
8907 11:03:53.803756 [TxChooseVref] Worse bit 0, Min win 25, Win sum 429, Final Vref 28
8908 11:03:53.803850
8909 11:03:53.807015 Final TX Range 0 Vref 28
8910 11:03:53.807123
8911 11:03:53.807184 ==
8912 11:03:53.810682 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 11:03:53.814196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 11:03:53.814318 ==
8915 11:03:53.814429
8916 11:03:53.814536
8917 11:03:53.817713 TX Vref Scan disable
8918 11:03:53.824140 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8919 11:03:53.824265 == TX Byte 0 ==
8920 11:03:53.827186 u2DelayCellOfst[0]=17 cells (5 PI)
8921 11:03:53.830616 u2DelayCellOfst[1]=10 cells (3 PI)
8922 11:03:53.833664 u2DelayCellOfst[2]=0 cells (0 PI)
8923 11:03:53.837317 u2DelayCellOfst[3]=6 cells (2 PI)
8924 11:03:53.840514 u2DelayCellOfst[4]=6 cells (2 PI)
8925 11:03:53.843919 u2DelayCellOfst[5]=17 cells (5 PI)
8926 11:03:53.846976 u2DelayCellOfst[6]=17 cells (5 PI)
8927 11:03:53.847112 u2DelayCellOfst[7]=6 cells (2 PI)
8928 11:03:53.853620 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8929 11:03:53.856986 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8930 11:03:53.857117 == TX Byte 1 ==
8931 11:03:53.860406 u2DelayCellOfst[8]=0 cells (0 PI)
8932 11:03:53.863603 u2DelayCellOfst[9]=3 cells (1 PI)
8933 11:03:53.866794 u2DelayCellOfst[10]=10 cells (3 PI)
8934 11:03:53.870416 u2DelayCellOfst[11]=3 cells (1 PI)
8935 11:03:53.873282 u2DelayCellOfst[12]=13 cells (4 PI)
8936 11:03:53.876669 u2DelayCellOfst[13]=13 cells (4 PI)
8937 11:03:53.879862 u2DelayCellOfst[14]=17 cells (5 PI)
8938 11:03:53.883791 u2DelayCellOfst[15]=17 cells (5 PI)
8939 11:03:53.887083 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8940 11:03:53.893505 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8941 11:03:53.893633 DramC Write-DBI on
8942 11:03:53.893749 ==
8943 11:03:53.896871 Dram Type= 6, Freq= 0, CH_1, rank 1
8944 11:03:53.900312 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8945 11:03:53.903527 ==
8946 11:03:53.903663
8947 11:03:53.903781
8948 11:03:53.903897 TX Vref Scan disable
8949 11:03:53.906656 == TX Byte 0 ==
8950 11:03:53.909776 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8951 11:03:53.913474 == TX Byte 1 ==
8952 11:03:53.916533 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8953 11:03:53.919982 DramC Write-DBI off
8954 11:03:53.920114
8955 11:03:53.920229 [DATLAT]
8956 11:03:53.920342 Freq=1600, CH1 RK1
8957 11:03:53.920455
8958 11:03:53.923300 DATLAT Default: 0xf
8959 11:03:53.923395 0, 0xFFFF, sum = 0
8960 11:03:53.926526 1, 0xFFFF, sum = 0
8961 11:03:53.930027 2, 0xFFFF, sum = 0
8962 11:03:53.930130 3, 0xFFFF, sum = 0
8963 11:03:53.933221 4, 0xFFFF, sum = 0
8964 11:03:53.933317 5, 0xFFFF, sum = 0
8965 11:03:53.936704 6, 0xFFFF, sum = 0
8966 11:03:53.936804 7, 0xFFFF, sum = 0
8967 11:03:53.939963 8, 0xFFFF, sum = 0
8968 11:03:53.940062 9, 0xFFFF, sum = 0
8969 11:03:53.943123 10, 0xFFFF, sum = 0
8970 11:03:53.943229 11, 0xFFFF, sum = 0
8971 11:03:53.946373 12, 0xFFFF, sum = 0
8972 11:03:53.946482 13, 0xFFFF, sum = 0
8973 11:03:53.950454 14, 0x0, sum = 1
8974 11:03:53.950559 15, 0x0, sum = 2
8975 11:03:53.953259 16, 0x0, sum = 3
8976 11:03:53.953365 17, 0x0, sum = 4
8977 11:03:53.956343 best_step = 15
8978 11:03:53.956447
8979 11:03:53.956542 ==
8980 11:03:53.960014 Dram Type= 6, Freq= 0, CH_1, rank 1
8981 11:03:53.963292 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8982 11:03:53.963409 ==
8983 11:03:53.966637 RX Vref Scan: 0
8984 11:03:53.966748
8985 11:03:53.966860 RX Vref 0 -> 0, step: 1
8986 11:03:53.966954
8987 11:03:53.969764 RX Delay 19 -> 252, step: 4
8988 11:03:53.973045 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8989 11:03:53.979773 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8990 11:03:53.982949 iDelay=195, Bit 2, Center 124 (75 ~ 174) 100
8991 11:03:53.986249 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8992 11:03:53.989602 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8993 11:03:53.993564 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8994 11:03:53.999812 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8995 11:03:54.003199 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8996 11:03:54.006127 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8997 11:03:54.009486 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8998 11:03:54.013196 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8999 11:03:54.019840 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9000 11:03:54.023073 iDelay=195, Bit 12, Center 142 (91 ~ 194) 104
9001 11:03:54.026404 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9002 11:03:54.029678 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9003 11:03:54.032807 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9004 11:03:54.035900 ==
9005 11:03:54.035980 Dram Type= 6, Freq= 0, CH_1, rank 1
9006 11:03:54.042877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9007 11:03:54.042991 ==
9008 11:03:54.043082 DQS Delay:
9009 11:03:54.046248 DQS0 = 0, DQS1 = 0
9010 11:03:54.046354 DQM Delay:
9011 11:03:54.049320 DQM0 = 134, DQM1 = 131
9012 11:03:54.049421 DQ Delay:
9013 11:03:54.052920 DQ0 =138, DQ1 =132, DQ2 =124, DQ3 =130
9014 11:03:54.056361 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9015 11:03:54.059546 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
9016 11:03:54.062751 DQ12 =142, DQ13 =138, DQ14 =136, DQ15 =140
9017 11:03:54.062855
9018 11:03:54.062948
9019 11:03:54.063037
9020 11:03:54.066448 [DramC_TX_OE_Calibration] TA2
9021 11:03:54.069529 Original DQ_B0 (3 6) =30, OEN = 27
9022 11:03:54.072911 Original DQ_B1 (3 6) =30, OEN = 27
9023 11:03:54.075924 24, 0x0, End_B0=24 End_B1=24
9024 11:03:54.079101 25, 0x0, End_B0=25 End_B1=25
9025 11:03:54.079213 26, 0x0, End_B0=26 End_B1=26
9026 11:03:54.082740 27, 0x0, End_B0=27 End_B1=27
9027 11:03:54.086096 28, 0x0, End_B0=28 End_B1=28
9028 11:03:54.089231 29, 0x0, End_B0=29 End_B1=29
9029 11:03:54.089323 30, 0x0, End_B0=30 End_B1=30
9030 11:03:54.092580 31, 0x4545, End_B0=30 End_B1=30
9031 11:03:54.095922 Byte0 end_step=30 best_step=27
9032 11:03:54.099086 Byte1 end_step=30 best_step=27
9033 11:03:54.102924 Byte0 TX OE(2T, 0.5T) = (3, 3)
9034 11:03:54.106137 Byte1 TX OE(2T, 0.5T) = (3, 3)
9035 11:03:54.106255
9036 11:03:54.106358
9037 11:03:54.112481 [DQSOSCAuto] RK1, (LSB)MR18= 0x250a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
9038 11:03:54.115718 CH1 RK1: MR19=303, MR18=250A
9039 11:03:54.122531 CH1_RK1: MR19=0x303, MR18=0x250A, DQSOSC=391, MR23=63, INC=24, DEC=16
9040 11:03:54.125705 [RxdqsGatingPostProcess] freq 1600
9041 11:03:54.128994 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9042 11:03:54.132300 best DQS0 dly(2T, 0.5T) = (1, 1)
9043 11:03:54.136318 best DQS1 dly(2T, 0.5T) = (1, 1)
9044 11:03:54.139260 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9045 11:03:54.142517 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9046 11:03:54.145644 best DQS0 dly(2T, 0.5T) = (1, 1)
9047 11:03:54.149117 best DQS1 dly(2T, 0.5T) = (1, 1)
9048 11:03:54.152259 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9049 11:03:54.155842 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9050 11:03:54.158791 Pre-setting of DQS Precalculation
9051 11:03:54.162185 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9052 11:03:54.168724 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9053 11:03:54.178786 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9054 11:03:54.178903
9055 11:03:54.179004
9056 11:03:54.182616 [Calibration Summary] 3200 Mbps
9057 11:03:54.182724 CH 0, Rank 0
9058 11:03:54.186104 SW Impedance : PASS
9059 11:03:54.186194 DUTY Scan : NO K
9060 11:03:54.189366 ZQ Calibration : PASS
9061 11:03:54.189453 Jitter Meter : NO K
9062 11:03:54.192451 CBT Training : PASS
9063 11:03:54.195738 Write leveling : PASS
9064 11:03:54.195805 RX DQS gating : PASS
9065 11:03:54.199415 RX DQ/DQS(RDDQC) : PASS
9066 11:03:54.202230 TX DQ/DQS : PASS
9067 11:03:54.202322 RX DATLAT : PASS
9068 11:03:54.205922 RX DQ/DQS(Engine): PASS
9069 11:03:54.209168 TX OE : PASS
9070 11:03:54.209256 All Pass.
9071 11:03:54.209335
9072 11:03:54.209412 CH 0, Rank 1
9073 11:03:54.212683 SW Impedance : PASS
9074 11:03:54.215650 DUTY Scan : NO K
9075 11:03:54.215728 ZQ Calibration : PASS
9076 11:03:54.218817 Jitter Meter : NO K
9077 11:03:54.222413 CBT Training : PASS
9078 11:03:54.222481 Write leveling : PASS
9079 11:03:54.225523 RX DQS gating : PASS
9080 11:03:54.229398 RX DQ/DQS(RDDQC) : PASS
9081 11:03:54.229494 TX DQ/DQS : PASS
9082 11:03:54.232123 RX DATLAT : PASS
9083 11:03:54.232189 RX DQ/DQS(Engine): PASS
9084 11:03:54.235545 TX OE : PASS
9085 11:03:54.235617 All Pass.
9086 11:03:54.235677
9087 11:03:54.238553 CH 1, Rank 0
9088 11:03:54.242584 SW Impedance : PASS
9089 11:03:54.242654 DUTY Scan : NO K
9090 11:03:54.245502 ZQ Calibration : PASS
9091 11:03:54.245592 Jitter Meter : NO K
9092 11:03:54.248640 CBT Training : PASS
9093 11:03:54.252190 Write leveling : PASS
9094 11:03:54.252283 RX DQS gating : PASS
9095 11:03:54.255683 RX DQ/DQS(RDDQC) : PASS
9096 11:03:54.258443 TX DQ/DQS : PASS
9097 11:03:54.258528 RX DATLAT : PASS
9098 11:03:54.262315 RX DQ/DQS(Engine): PASS
9099 11:03:54.265212 TX OE : PASS
9100 11:03:54.265281 All Pass.
9101 11:03:54.265336
9102 11:03:54.265387 CH 1, Rank 1
9103 11:03:54.268189 SW Impedance : PASS
9104 11:03:54.271639 DUTY Scan : NO K
9105 11:03:54.271732 ZQ Calibration : PASS
9106 11:03:54.274893 Jitter Meter : NO K
9107 11:03:54.278360 CBT Training : PASS
9108 11:03:54.278442 Write leveling : PASS
9109 11:03:54.281588 RX DQS gating : PASS
9110 11:03:54.284789 RX DQ/DQS(RDDQC) : PASS
9111 11:03:54.284878 TX DQ/DQS : PASS
9112 11:03:54.288023 RX DATLAT : PASS
9113 11:03:54.292160 RX DQ/DQS(Engine): PASS
9114 11:03:54.292249 TX OE : PASS
9115 11:03:54.292332 All Pass.
9116 11:03:54.295177
9117 11:03:54.295244 DramC Write-DBI on
9118 11:03:54.298552 PER_BANK_REFRESH: Hybrid Mode
9119 11:03:54.298621 TX_TRACKING: ON
9120 11:03:54.308392 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9121 11:03:54.315016 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9122 11:03:54.324853 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9123 11:03:54.328017 [FAST_K] Save calibration result to emmc
9124 11:03:54.332061 sync common calibartion params.
9125 11:03:54.332152 sync cbt_mode0:1, 1:1
9126 11:03:54.334527 dram_init: ddr_geometry: 2
9127 11:03:54.338449 dram_init: ddr_geometry: 2
9128 11:03:54.338523 dram_init: ddr_geometry: 2
9129 11:03:54.341728 0:dram_rank_size:100000000
9130 11:03:54.344995 1:dram_rank_size:100000000
9131 11:03:54.351218 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9132 11:03:54.351310 DFS_SHUFFLE_HW_MODE: ON
9133 11:03:54.354533 dramc_set_vcore_voltage set vcore to 725000
9134 11:03:54.357804 Read voltage for 1600, 0
9135 11:03:54.357898 Vio18 = 0
9136 11:03:54.360991 Vcore = 725000
9137 11:03:54.361078 Vdram = 0
9138 11:03:54.361161 Vddq = 0
9139 11:03:54.364266 Vmddr = 0
9140 11:03:54.364353 switch to 3200 Mbps bootup
9141 11:03:54.368023 [DramcRunTimeConfig]
9142 11:03:54.368110 PHYPLL
9143 11:03:54.371206 DPM_CONTROL_AFTERK: ON
9144 11:03:54.371296 PER_BANK_REFRESH: ON
9145 11:03:54.374499 REFRESH_OVERHEAD_REDUCTION: ON
9146 11:03:54.377561 CMD_PICG_NEW_MODE: OFF
9147 11:03:54.377649 XRTWTW_NEW_MODE: ON
9148 11:03:54.380727 XRTRTR_NEW_MODE: ON
9149 11:03:54.380794 TX_TRACKING: ON
9150 11:03:54.384286 RDSEL_TRACKING: OFF
9151 11:03:54.387608 DQS Precalculation for DVFS: ON
9152 11:03:54.387674 RX_TRACKING: OFF
9153 11:03:54.391348 HW_GATING DBG: ON
9154 11:03:54.391441 ZQCS_ENABLE_LP4: ON
9155 11:03:54.394230 RX_PICG_NEW_MODE: ON
9156 11:03:54.394298 TX_PICG_NEW_MODE: ON
9157 11:03:54.397626 ENABLE_RX_DCM_DPHY: ON
9158 11:03:54.401376 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9159 11:03:54.404585 DUMMY_READ_FOR_TRACKING: OFF
9160 11:03:54.404674 !!! SPM_CONTROL_AFTERK: OFF
9161 11:03:54.407650 !!! SPM could not control APHY
9162 11:03:54.411043 IMPEDANCE_TRACKING: ON
9163 11:03:54.411110 TEMP_SENSOR: ON
9164 11:03:54.413920 HW_SAVE_FOR_SR: OFF
9165 11:03:54.417155 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9166 11:03:54.420939 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9167 11:03:54.421005 Read ODT Tracking: ON
9168 11:03:54.424266 Refresh Rate DeBounce: ON
9169 11:03:54.427307 DFS_NO_QUEUE_FLUSH: ON
9170 11:03:54.431169 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9171 11:03:54.431263 ENABLE_DFS_RUNTIME_MRW: OFF
9172 11:03:54.433874 DDR_RESERVE_NEW_MODE: ON
9173 11:03:54.437762 MR_CBT_SWITCH_FREQ: ON
9174 11:03:54.437851 =========================
9175 11:03:54.458298 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9176 11:03:54.461233 dram_init: ddr_geometry: 2
9177 11:03:54.479219 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9178 11:03:54.482593 dram_init: dram init end (result: 0)
9179 11:03:54.489835 DRAM-K: Full calibration passed in 24389 msecs
9180 11:03:54.492402 MRC: failed to locate region type 0.
9181 11:03:54.492495 DRAM rank0 size:0x100000000,
9182 11:03:54.495925 DRAM rank1 size=0x100000000
9183 11:03:54.505945 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9184 11:03:54.512932 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9185 11:03:54.518849 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9186 11:03:54.526092 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9187 11:03:54.529111 DRAM rank0 size:0x100000000,
9188 11:03:54.532134 DRAM rank1 size=0x100000000
9189 11:03:54.532225 CBMEM:
9190 11:03:54.535534 IMD: root @ 0xfffff000 254 entries.
9191 11:03:54.538699 IMD: root @ 0xffffec00 62 entries.
9192 11:03:54.541961 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9193 11:03:54.549181 WARNING: RO_VPD is uninitialized or empty.
9194 11:03:54.552375 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9195 11:03:54.559959 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9196 11:03:54.572542 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9197 11:03:54.583690 BS: romstage times (exec / console): total (unknown) / 23930 ms
9198 11:03:54.583791
9199 11:03:54.583878
9200 11:03:54.593643 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9201 11:03:54.597601 ARM64: Exception handlers installed.
9202 11:03:54.600284 ARM64: Testing exception
9203 11:03:54.604177 ARM64: Done test exception
9204 11:03:54.604267 Enumerating buses...
9205 11:03:54.607436 Show all devs... Before device enumeration.
9206 11:03:54.610511 Root Device: enabled 1
9207 11:03:54.614223 CPU_CLUSTER: 0: enabled 1
9208 11:03:54.614298 CPU: 00: enabled 1
9209 11:03:54.617185 Compare with tree...
9210 11:03:54.617308 Root Device: enabled 1
9211 11:03:54.620607 CPU_CLUSTER: 0: enabled 1
9212 11:03:54.623763 CPU: 00: enabled 1
9213 11:03:54.623853 Root Device scanning...
9214 11:03:54.627563 scan_static_bus for Root Device
9215 11:03:54.630629 CPU_CLUSTER: 0 enabled
9216 11:03:54.634071 scan_static_bus for Root Device done
9217 11:03:54.637058 scan_bus: bus Root Device finished in 8 msecs
9218 11:03:54.637135 done
9219 11:03:54.643836 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9220 11:03:54.647256 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9221 11:03:54.653485 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9222 11:03:54.657399 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9223 11:03:54.660216 Allocating resources...
9224 11:03:54.660292 Reading resources...
9225 11:03:54.664126 Root Device read_resources bus 0 link: 0
9226 11:03:54.667480 DRAM rank0 size:0x100000000,
9227 11:03:54.670672 DRAM rank1 size=0x100000000
9228 11:03:54.673941 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9229 11:03:54.677277 CPU: 00 missing read_resources
9230 11:03:54.680507 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9231 11:03:54.686910 Root Device read_resources bus 0 link: 0 done
9232 11:03:54.686987 Done reading resources.
9233 11:03:54.694182 Show resources in subtree (Root Device)...After reading.
9234 11:03:54.697268 Root Device child on link 0 CPU_CLUSTER: 0
9235 11:03:54.700402 CPU_CLUSTER: 0 child on link 0 CPU: 00
9236 11:03:54.710386 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9237 11:03:54.710466 CPU: 00
9238 11:03:54.713947 Root Device assign_resources, bus 0 link: 0
9239 11:03:54.717391 CPU_CLUSTER: 0 missing set_resources
9240 11:03:54.720268 Root Device assign_resources, bus 0 link: 0 done
9241 11:03:54.724039 Done setting resources.
9242 11:03:54.729911 Show resources in subtree (Root Device)...After assigning values.
9243 11:03:54.733906 Root Device child on link 0 CPU_CLUSTER: 0
9244 11:03:54.737249 CPU_CLUSTER: 0 child on link 0 CPU: 00
9245 11:03:54.746727 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9246 11:03:54.746838 CPU: 00
9247 11:03:54.750308 Done allocating resources.
9248 11:03:54.753836 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9249 11:03:54.757041 Enabling resources...
9250 11:03:54.757137 done.
9251 11:03:54.760608 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9252 11:03:54.763371 Initializing devices...
9253 11:03:54.766385 Root Device init
9254 11:03:54.766481 init hardware done!
9255 11:03:54.769992 0x00000018: ctrlr->caps
9256 11:03:54.773163 52.000 MHz: ctrlr->f_max
9257 11:03:54.773257 0.400 MHz: ctrlr->f_min
9258 11:03:54.776573 0x40ff8080: ctrlr->voltages
9259 11:03:54.776668 sclk: 390625
9260 11:03:54.779728 Bus Width = 1
9261 11:03:54.779821 sclk: 390625
9262 11:03:54.779913 Bus Width = 1
9263 11:03:54.783199 Early init status = 3
9264 11:03:54.789706 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9265 11:03:54.793034 in-header: 03 fc 00 00 01 00 00 00
9266 11:03:54.793148 in-data: 00
9267 11:03:54.799875 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9268 11:03:54.803323 in-header: 03 fd 00 00 00 00 00 00
9269 11:03:54.806386 in-data:
9270 11:03:54.809489 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9271 11:03:54.814261 in-header: 03 fc 00 00 01 00 00 00
9272 11:03:54.817580 in-data: 00
9273 11:03:54.820937 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9274 11:03:54.826840 in-header: 03 fd 00 00 00 00 00 00
9275 11:03:54.829822 in-data:
9276 11:03:54.833226 [SSUSB] Setting up USB HOST controller...
9277 11:03:54.836537 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9278 11:03:54.839645 [SSUSB] phy power-on done.
9279 11:03:54.842933 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9280 11:03:54.849574 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9281 11:03:54.852884 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9282 11:03:54.859681 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9283 11:03:54.866647 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9284 11:03:54.872741 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9285 11:03:54.879811 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9286 11:03:54.886162 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9287 11:03:54.886260 SPM: binary array size = 0x9dc
9288 11:03:54.892906 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9289 11:03:54.900189 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9290 11:03:54.906397 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9291 11:03:54.909448 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9292 11:03:54.912697 configure_display: Starting display init
9293 11:03:54.949400 anx7625_power_on_init: Init interface.
9294 11:03:54.952933 anx7625_disable_pd_protocol: Disabled PD feature.
9295 11:03:54.956203 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9296 11:03:54.984225 anx7625_start_dp_work: Secure OCM version=00
9297 11:03:54.987509 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9298 11:03:55.002167 sp_tx_get_edid_block: EDID Block = 1
9299 11:03:55.104823 Extracted contents:
9300 11:03:55.107859 header: 00 ff ff ff ff ff ff 00
9301 11:03:55.111128 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9302 11:03:55.114882 version: 01 04
9303 11:03:55.117826 basic params: 95 1f 11 78 0a
9304 11:03:55.121169 chroma info: 76 90 94 55 54 90 27 21 50 54
9305 11:03:55.125094 established: 00 00 00
9306 11:03:55.131066 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9307 11:03:55.134834 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9308 11:03:55.141420 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9309 11:03:55.148023 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9310 11:03:55.154547 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9311 11:03:55.157769 extensions: 00
9312 11:03:55.157879 checksum: fb
9313 11:03:55.157943
9314 11:03:55.161508 Manufacturer: IVO Model 57d Serial Number 0
9315 11:03:55.164764 Made week 0 of 2020
9316 11:03:55.164887 EDID version: 1.4
9317 11:03:55.167865 Digital display
9318 11:03:55.171092 6 bits per primary color channel
9319 11:03:55.171196 DisplayPort interface
9320 11:03:55.174870 Maximum image size: 31 cm x 17 cm
9321 11:03:55.174938 Gamma: 220%
9322 11:03:55.178190 Check DPMS levels
9323 11:03:55.181369 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9324 11:03:55.184503 First detailed timing is preferred timing
9325 11:03:55.187762 Established timings supported:
9326 11:03:55.191413 Standard timings supported:
9327 11:03:55.191482 Detailed timings
9328 11:03:55.197561 Hex of detail: 383680a07038204018303c0035ae10000019
9329 11:03:55.201113 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9330 11:03:55.204576 0780 0798 07c8 0820 hborder 0
9331 11:03:55.211276 0438 043b 0447 0458 vborder 0
9332 11:03:55.211380 -hsync -vsync
9333 11:03:55.214765 Did detailed timing
9334 11:03:55.217905 Hex of detail: 000000000000000000000000000000000000
9335 11:03:55.221244 Manufacturer-specified data, tag 0
9336 11:03:55.227783 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9337 11:03:55.227873 ASCII string: InfoVision
9338 11:03:55.234168 Hex of detail: 000000fe00523134304e574635205248200a
9339 11:03:55.237868 ASCII string: R140NWF5 RH
9340 11:03:55.237972 Checksum
9341 11:03:55.238082 Checksum: 0xfb (valid)
9342 11:03:55.244099 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9343 11:03:55.247653 DSI data_rate: 832800000 bps
9344 11:03:55.251210 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9345 11:03:55.254137 anx7625_parse_edid: pixelclock(138800).
9346 11:03:55.260883 hactive(1920), hsync(48), hfp(24), hbp(88)
9347 11:03:55.264193 vactive(1080), vsync(12), vfp(3), vbp(17)
9348 11:03:55.267330 anx7625_dsi_config: config dsi.
9349 11:03:55.273906 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9350 11:03:55.286542 anx7625_dsi_config: success to config DSI
9351 11:03:55.290591 anx7625_dp_start: MIPI phy setup OK.
9352 11:03:55.293897 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9353 11:03:55.297020 mtk_ddp_mode_set invalid vrefresh 60
9354 11:03:55.299968 main_disp_path_setup
9355 11:03:55.300037 ovl_layer_smi_id_en
9356 11:03:55.303341 ovl_layer_smi_id_en
9357 11:03:55.303420 ccorr_config
9358 11:03:55.303481 aal_config
9359 11:03:55.307124 gamma_config
9360 11:03:55.307221 postmask_config
9361 11:03:55.307291 dither_config
9362 11:03:55.313907 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9363 11:03:55.319988 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9364 11:03:55.323670 Root Device init finished in 554 msecs
9365 11:03:55.323760 CPU_CLUSTER: 0 init
9366 11:03:55.333215 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9367 11:03:55.336499 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9368 11:03:55.340329 APU_MBOX 0x190000b0 = 0x10001
9369 11:03:55.343523 APU_MBOX 0x190001b0 = 0x10001
9370 11:03:55.346376 APU_MBOX 0x190005b0 = 0x10001
9371 11:03:55.350163 APU_MBOX 0x190006b0 = 0x10001
9372 11:03:55.353327 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9373 11:03:55.365513 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9374 11:03:55.378598 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9375 11:03:55.384836 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9376 11:03:55.396305 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9377 11:03:55.405239 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9378 11:03:55.408892 CPU_CLUSTER: 0 init finished in 81 msecs
9379 11:03:55.412232 Devices initialized
9380 11:03:55.415653 Show all devs... After init.
9381 11:03:55.415724 Root Device: enabled 1
9382 11:03:55.418623 CPU_CLUSTER: 0: enabled 1
9383 11:03:55.422335 CPU: 00: enabled 1
9384 11:03:55.425758 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9385 11:03:55.428943 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9386 11:03:55.432511 ELOG: NV offset 0x57f000 size 0x1000
9387 11:03:55.438560 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9388 11:03:55.445601 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9389 11:03:55.448588 ELOG: Event(17) added with size 13 at 2024-07-10 11:03:41 UTC
9390 11:03:55.451909 out: cmd=0x121: 03 db 21 01 00 00 00 00
9391 11:03:55.455678 in-header: 03 14 00 00 2c 00 00 00
9392 11:03:55.469316 in-data: 29 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9393 11:03:55.476361 ELOG: Event(A1) added with size 10 at 2024-07-10 11:03:41 UTC
9394 11:03:55.482260 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9395 11:03:55.489405 ELOG: Event(A0) added with size 9 at 2024-07-10 11:03:41 UTC
9396 11:03:55.492845 elog_add_boot_reason: Logged dev mode boot
9397 11:03:55.495927 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9398 11:03:55.499030 Finalize devices...
9399 11:03:55.499127 Devices finalized
9400 11:03:55.505821 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9401 11:03:55.509027 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9402 11:03:55.512228 in-header: 03 07 00 00 08 00 00 00
9403 11:03:55.515368 in-data: aa e4 47 04 13 02 00 00
9404 11:03:55.519442 Chrome EC: UHEPI supported
9405 11:03:55.525328 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9406 11:03:55.528742 in-header: 03 a9 00 00 08 00 00 00
9407 11:03:55.531877 in-data: 84 60 60 08 00 00 00 00
9408 11:03:55.535223 ELOG: Event(91) added with size 10 at 2024-07-10 11:03:41 UTC
9409 11:03:55.542370 Chrome EC: clear events_b mask to 0x0000000020004000
9410 11:03:55.549164 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9411 11:03:55.553003 in-header: 03 fd 00 00 00 00 00 00
9412 11:03:55.553102 in-data:
9413 11:03:55.559522 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9414 11:03:55.562620 Writing coreboot table at 0xffe64000
9415 11:03:55.566487 0. 000000000010a000-0000000000113fff: RAMSTAGE
9416 11:03:55.569651 1. 0000000040000000-00000000400fffff: RAM
9417 11:03:55.572397 2. 0000000040100000-000000004032afff: RAMSTAGE
9418 11:03:55.579531 3. 000000004032b000-00000000545fffff: RAM
9419 11:03:55.582823 4. 0000000054600000-000000005465ffff: BL31
9420 11:03:55.585886 5. 0000000054660000-00000000ffe63fff: RAM
9421 11:03:55.592880 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9422 11:03:55.595796 7. 0000000100000000-000000023fffffff: RAM
9423 11:03:55.595913 Passing 5 GPIOs to payload:
9424 11:03:55.602480 NAME | PORT | POLARITY | VALUE
9425 11:03:55.606342 EC in RW | 0x000000aa | low | undefined
9426 11:03:55.612480 EC interrupt | 0x00000005 | low | undefined
9427 11:03:55.615952 TPM interrupt | 0x000000ab | high | undefined
9428 11:03:55.619055 SD card detect | 0x00000011 | high | undefined
9429 11:03:55.626200 speaker enable | 0x00000093 | high | undefined
9430 11:03:55.629372 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9431 11:03:55.632860 in-header: 03 f9 00 00 02 00 00 00
9432 11:03:55.632937 in-data: 02 00
9433 11:03:55.636074 ADC[4]: Raw value=903618 ID=7
9434 11:03:55.639319 ADC[3]: Raw value=213441 ID=1
9435 11:03:55.639396 RAM Code: 0x71
9436 11:03:55.642514 ADC[6]: Raw value=75701 ID=0
9437 11:03:55.645786 ADC[5]: Raw value=212703 ID=1
9438 11:03:55.645863 SKU Code: 0x1
9439 11:03:55.652442 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d8d2
9440 11:03:55.655758 coreboot table: 964 bytes.
9441 11:03:55.659573 IMD ROOT 0. 0xfffff000 0x00001000
9442 11:03:55.662755 IMD SMALL 1. 0xffffe000 0x00001000
9443 11:03:55.666015 RO MCACHE 2. 0xffffc000 0x00001104
9444 11:03:55.669854 CONSOLE 3. 0xfff7c000 0x00080000
9445 11:03:55.672721 FMAP 4. 0xfff7b000 0x00000452
9446 11:03:55.676133 TIME STAMP 5. 0xfff7a000 0x00000910
9447 11:03:55.679406 VBOOT WORK 6. 0xfff66000 0x00014000
9448 11:03:55.682571 RAMOOPS 7. 0xffe66000 0x00100000
9449 11:03:55.686364 COREBOOT 8. 0xffe64000 0x00002000
9450 11:03:55.686441 IMD small region:
9451 11:03:55.689505 IMD ROOT 0. 0xffffec00 0x00000400
9452 11:03:55.693027 VPD 1. 0xffffeb80 0x0000006c
9453 11:03:55.696100 MMC STATUS 2. 0xffffeb60 0x00000004
9454 11:03:55.702638 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9455 11:03:55.709580 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9456 11:03:55.748721 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9457 11:03:55.752059 Checking segment from ROM address 0x40100000
9458 11:03:55.755150 Checking segment from ROM address 0x4010001c
9459 11:03:55.761761 Loading segment from ROM address 0x40100000
9460 11:03:55.761871 code (compression=0)
9461 11:03:55.768926 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9462 11:03:55.778269 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9463 11:03:55.778347 it's not compressed!
9464 11:03:55.785686 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9465 11:03:55.789088 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9466 11:03:55.809289 Loading segment from ROM address 0x4010001c
9467 11:03:55.809368 Entry Point 0x80000000
9468 11:03:55.812101 Loaded segments
9469 11:03:55.815743 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9470 11:03:55.822419 Jumping to boot code at 0x80000000(0xffe64000)
9471 11:03:55.828783 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9472 11:03:55.835379 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9473 11:03:55.843303 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9474 11:03:55.846732 Checking segment from ROM address 0x40100000
9475 11:03:55.849932 Checking segment from ROM address 0x4010001c
9476 11:03:55.856519 Loading segment from ROM address 0x40100000
9477 11:03:55.856613 code (compression=1)
9478 11:03:55.863068 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9479 11:03:55.872839 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9480 11:03:55.872917 using LZMA
9481 11:03:55.881760 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9482 11:03:55.888121 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9483 11:03:55.891444 Loading segment from ROM address 0x4010001c
9484 11:03:55.891527 Entry Point 0x54601000
9485 11:03:55.894928 Loaded segments
9486 11:03:55.898517 NOTICE: MT8192 bl31_setup
9487 11:03:55.905341 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9488 11:03:55.908675 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9489 11:03:55.911954 WARNING: region 0:
9490 11:03:55.915092 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 11:03:55.915160 WARNING: region 1:
9492 11:03:55.921569 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9493 11:03:55.924972 WARNING: region 2:
9494 11:03:55.928462 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9495 11:03:55.931682 WARNING: region 3:
9496 11:03:55.934918 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9497 11:03:55.938543 WARNING: region 4:
9498 11:03:55.944947 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9499 11:03:55.945074 WARNING: region 5:
9500 11:03:55.948114 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9501 11:03:55.951552 WARNING: region 6:
9502 11:03:55.954706 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9503 11:03:55.958683 WARNING: region 7:
9504 11:03:55.961687 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9505 11:03:55.968348 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9506 11:03:55.971397 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9507 11:03:55.975215 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9508 11:03:55.981620 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9509 11:03:55.984802 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9510 11:03:55.988349 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9511 11:03:55.995125 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9512 11:03:55.998505 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9513 11:03:56.004803 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9514 11:03:56.008231 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9515 11:03:56.011651 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9516 11:03:56.018212 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9517 11:03:56.021563 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9518 11:03:56.024774 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9519 11:03:56.031420 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9520 11:03:56.035246 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9521 11:03:56.041787 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9522 11:03:56.045297 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9523 11:03:56.048256 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9524 11:03:56.054894 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9525 11:03:56.059020 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9526 11:03:56.061529 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9527 11:03:56.068141 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9528 11:03:56.071392 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9529 11:03:56.078198 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9530 11:03:56.081558 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9531 11:03:56.084804 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9532 11:03:56.091536 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9533 11:03:56.094870 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9534 11:03:56.101456 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9535 11:03:56.104799 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9536 11:03:56.108579 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9537 11:03:56.115012 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9538 11:03:56.118458 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9539 11:03:56.121441 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9540 11:03:56.124956 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9541 11:03:56.131465 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9542 11:03:56.135173 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9543 11:03:56.138516 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9544 11:03:56.141721 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9545 11:03:56.148370 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9546 11:03:56.151466 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9547 11:03:56.154502 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9548 11:03:56.158373 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9549 11:03:56.164886 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9550 11:03:56.168322 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9551 11:03:56.171520 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9552 11:03:56.174898 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9553 11:03:56.181602 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9554 11:03:56.184762 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9555 11:03:56.191216 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9556 11:03:56.194432 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9557 11:03:56.201011 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9558 11:03:56.204387 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9559 11:03:56.207848 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9560 11:03:56.214470 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9561 11:03:56.218019 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9562 11:03:56.224560 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9563 11:03:56.228126 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9564 11:03:56.234039 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9565 11:03:56.237603 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9566 11:03:56.244127 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9567 11:03:56.247545 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9568 11:03:56.250846 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9569 11:03:56.257513 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9570 11:03:56.261471 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9571 11:03:56.267511 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9572 11:03:56.271021 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9573 11:03:56.277829 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9574 11:03:56.280940 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9575 11:03:56.284388 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9576 11:03:56.290954 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9577 11:03:56.294195 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9578 11:03:56.300955 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9579 11:03:56.304089 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9580 11:03:56.310671 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9581 11:03:56.313864 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9582 11:03:56.320825 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9583 11:03:56.324020 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9584 11:03:56.327650 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9585 11:03:56.334584 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9586 11:03:56.337413 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9587 11:03:56.344510 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9588 11:03:56.347572 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9589 11:03:56.353748 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9590 11:03:56.357315 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9591 11:03:56.360645 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9592 11:03:56.367229 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9593 11:03:56.370650 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9594 11:03:56.377096 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9595 11:03:56.380779 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9596 11:03:56.386896 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9597 11:03:56.390830 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9598 11:03:56.397169 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9599 11:03:56.400510 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9600 11:03:56.404389 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9601 11:03:56.410787 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9602 11:03:56.413857 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9603 11:03:56.417157 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9604 11:03:56.420441 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9605 11:03:56.427081 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9606 11:03:56.430348 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9607 11:03:56.433868 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9608 11:03:56.440334 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9609 11:03:56.443594 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9610 11:03:56.451013 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9611 11:03:56.453598 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9612 11:03:56.457551 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9613 11:03:56.463889 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9614 11:03:56.467283 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9615 11:03:56.473916 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9616 11:03:56.476937 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9617 11:03:56.483681 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9618 11:03:56.486980 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9619 11:03:56.490247 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9620 11:03:56.497060 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9621 11:03:56.500395 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9622 11:03:56.503951 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9623 11:03:56.510533 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9624 11:03:56.513911 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9625 11:03:56.517313 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9626 11:03:56.520760 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9627 11:03:56.523669 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9628 11:03:56.530725 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9629 11:03:56.533649 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9630 11:03:56.540427 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9631 11:03:56.543823 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9632 11:03:56.547218 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9633 11:03:56.553597 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9634 11:03:56.556676 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9635 11:03:56.560103 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9636 11:03:56.566614 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9637 11:03:56.570379 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9638 11:03:56.577189 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9639 11:03:56.580086 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9640 11:03:56.583868 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9641 11:03:56.590345 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9642 11:03:56.593424 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9643 11:03:56.600212 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9644 11:03:56.603796 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9645 11:03:56.607026 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9646 11:03:56.613866 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9647 11:03:56.616620 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9648 11:03:56.623219 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9649 11:03:56.627082 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9650 11:03:56.630520 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9651 11:03:56.636998 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9652 11:03:56.640112 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9653 11:03:56.646743 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9654 11:03:56.650037 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9655 11:03:56.652987 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9656 11:03:56.659965 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9657 11:03:56.663154 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9658 11:03:56.666827 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9659 11:03:56.673625 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9660 11:03:56.676839 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9661 11:03:56.682976 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9662 11:03:56.686478 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9663 11:03:56.690212 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9664 11:03:56.696925 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9665 11:03:56.700296 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9666 11:03:56.707194 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9667 11:03:56.709785 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9668 11:03:56.713238 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9669 11:03:56.720057 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9670 11:03:56.723490 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9671 11:03:56.726726 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9672 11:03:56.733421 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9673 11:03:56.736878 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9674 11:03:56.743484 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9675 11:03:56.746710 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9676 11:03:56.749925 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9677 11:03:56.756822 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9678 11:03:56.760417 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9679 11:03:56.763267 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9680 11:03:56.769803 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9681 11:03:56.773489 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9682 11:03:56.779747 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9683 11:03:56.783140 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9684 11:03:56.786629 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9685 11:03:56.793062 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9686 11:03:56.796418 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9687 11:03:56.803051 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9688 11:03:56.806380 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9689 11:03:56.809595 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9690 11:03:56.816369 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9691 11:03:56.819567 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9692 11:03:56.826933 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9693 11:03:56.829765 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9694 11:03:56.833504 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9695 11:03:56.839616 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9696 11:03:56.843111 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9697 11:03:56.850049 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9698 11:03:56.853675 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9699 11:03:56.856876 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9700 11:03:56.863311 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9701 11:03:56.867068 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9702 11:03:56.873454 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9703 11:03:56.876494 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9704 11:03:56.879923 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9705 11:03:56.887139 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9706 11:03:56.889776 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9707 11:03:56.896492 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9708 11:03:56.900203 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9709 11:03:56.906265 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9710 11:03:56.909669 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9711 11:03:56.913453 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9712 11:03:56.920102 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9713 11:03:56.923419 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9714 11:03:56.929912 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9715 11:03:56.933693 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9716 11:03:56.936755 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9717 11:03:56.943559 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9718 11:03:56.947016 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9719 11:03:56.953097 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9720 11:03:56.956485 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9721 11:03:56.959975 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9722 11:03:56.966530 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9723 11:03:56.970189 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9724 11:03:56.976498 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9725 11:03:56.979951 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9726 11:03:56.983751 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9727 11:03:56.990119 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9728 11:03:56.993277 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9729 11:03:56.999682 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9730 11:03:57.003224 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9731 11:03:57.009861 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9732 11:03:57.013248 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9733 11:03:57.016735 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9734 11:03:57.023416 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9735 11:03:57.026464 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9736 11:03:57.029645 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9737 11:03:57.032937 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9738 11:03:57.036261 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9739 11:03:57.042875 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9740 11:03:57.046463 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9741 11:03:57.053081 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9742 11:03:57.056144 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9743 11:03:57.059379 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9744 11:03:57.066412 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9745 11:03:57.069299 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9746 11:03:57.075954 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9747 11:03:57.079425 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9748 11:03:57.082899 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9749 11:03:57.089878 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9750 11:03:57.092673 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9751 11:03:57.096219 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9752 11:03:57.103225 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9753 11:03:57.106584 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9754 11:03:57.109702 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9755 11:03:57.116239 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9756 11:03:57.119860 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9757 11:03:57.123092 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9758 11:03:57.129562 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9759 11:03:57.133394 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9760 11:03:57.136331 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9761 11:03:57.142992 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9762 11:03:57.146131 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9763 11:03:57.150173 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9764 11:03:57.156332 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9765 11:03:57.159845 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9766 11:03:57.166205 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9767 11:03:57.169823 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9768 11:03:57.172847 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9769 11:03:57.179475 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9770 11:03:57.182842 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9771 11:03:57.186082 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9772 11:03:57.192972 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9773 11:03:57.196526 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9774 11:03:57.199420 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9775 11:03:57.206286 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9776 11:03:57.209580 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9777 11:03:57.213068 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9778 11:03:57.215993 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9779 11:03:57.219506 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9780 11:03:57.226252 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9781 11:03:57.229280 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9782 11:03:57.232944 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9783 11:03:57.235961 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9784 11:03:57.242717 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9785 11:03:57.245893 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9786 11:03:57.249677 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9787 11:03:57.256498 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9788 11:03:57.259690 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9789 11:03:57.266356 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9790 11:03:57.269279 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9791 11:03:57.273072 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9792 11:03:57.279743 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9793 11:03:57.282737 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9794 11:03:57.286208 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9795 11:03:57.292696 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9796 11:03:57.296053 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9797 11:03:57.303035 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9798 11:03:57.306057 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9799 11:03:57.312903 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9800 11:03:57.315974 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9801 11:03:57.319718 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9802 11:03:57.326422 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9803 11:03:57.329912 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9804 11:03:57.335989 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9805 11:03:57.339513 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9806 11:03:57.342948 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9807 11:03:57.349287 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9808 11:03:57.352754 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9809 11:03:57.359800 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9810 11:03:57.362942 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9811 11:03:57.366284 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9812 11:03:57.372799 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9813 11:03:57.376328 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9814 11:03:57.382502 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9815 11:03:57.386203 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9816 11:03:57.392823 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9817 11:03:57.395660 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9818 11:03:57.399543 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9819 11:03:57.406075 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9820 11:03:57.409526 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9821 11:03:57.415453 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9822 11:03:57.419657 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9823 11:03:57.422686 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9824 11:03:57.428697 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9825 11:03:57.432028 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9826 11:03:57.439302 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9827 11:03:57.442407 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9828 11:03:57.445671 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9829 11:03:57.452281 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9830 11:03:57.455345 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9831 11:03:57.461757 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9832 11:03:57.465311 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9833 11:03:57.472375 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9834 11:03:57.475488 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9835 11:03:57.478598 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9836 11:03:57.485587 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9837 11:03:57.488411 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9838 11:03:57.495541 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9839 11:03:57.498784 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9840 11:03:57.502224 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9841 11:03:57.508816 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9842 11:03:57.511894 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9843 11:03:57.515303 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9844 11:03:57.522165 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9845 11:03:57.525839 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9846 11:03:57.531838 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9847 11:03:57.535735 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9848 11:03:57.541898 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9849 11:03:57.545502 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9850 11:03:57.549010 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9851 11:03:57.555466 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9852 11:03:57.558407 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9853 11:03:57.565444 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9854 11:03:57.568663 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9855 11:03:57.571935 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9856 11:03:57.578961 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9857 11:03:57.582641 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9858 11:03:57.585078 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9859 11:03:57.592158 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9860 11:03:57.595376 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9861 11:03:57.601956 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9862 11:03:57.605585 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9863 11:03:57.611987 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9864 11:03:57.615394 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9865 11:03:57.621769 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9866 11:03:57.625062 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9867 11:03:57.628298 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9868 11:03:57.635651 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9869 11:03:57.638518 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9870 11:03:57.645371 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9871 11:03:57.648552 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9872 11:03:57.655853 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9873 11:03:57.658607 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9874 11:03:57.662359 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9875 11:03:57.668445 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9876 11:03:57.672147 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9877 11:03:57.678465 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9878 11:03:57.682339 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9879 11:03:57.688677 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9880 11:03:57.692282 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9881 11:03:57.698650 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9882 11:03:57.701885 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9883 11:03:57.705373 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9884 11:03:57.711996 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9885 11:03:57.715299 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9886 11:03:57.721773 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9887 11:03:57.725322 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9888 11:03:57.728553 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9889 11:03:57.735373 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9890 11:03:57.738427 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9891 11:03:57.745651 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9892 11:03:57.748647 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9893 11:03:57.755826 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9894 11:03:57.758832 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9895 11:03:57.762176 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9896 11:03:57.768528 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9897 11:03:57.771999 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9898 11:03:57.778912 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9899 11:03:57.781799 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9900 11:03:57.788484 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9901 11:03:57.791795 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9902 11:03:57.795112 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9903 11:03:57.802274 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9904 11:03:57.805674 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9905 11:03:57.812243 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9906 11:03:57.815178 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9907 11:03:57.818577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9908 11:03:57.825182 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9909 11:03:57.828416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9910 11:03:57.834953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9911 11:03:57.838868 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9912 11:03:57.845023 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9913 11:03:57.848352 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9914 11:03:57.855694 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9915 11:03:57.858762 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9916 11:03:57.865071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9917 11:03:57.868622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9918 11:03:57.874936 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9919 11:03:57.878434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9920 11:03:57.885018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9921 11:03:57.888532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9922 11:03:57.891759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9923 11:03:57.898524 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9924 11:03:57.901818 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9925 11:03:57.908700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9926 11:03:57.912103 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9927 11:03:57.918478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9928 11:03:57.921909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9929 11:03:57.928600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9930 11:03:57.931435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9931 11:03:57.938072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9932 11:03:57.941641 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9933 11:03:57.948451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9934 11:03:57.951598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9935 11:03:57.958397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9936 11:03:57.961979 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9937 11:03:57.968378 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9938 11:03:57.971466 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9939 11:03:57.978129 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9940 11:03:57.978232 INFO: [APUAPC] vio 0
9941 11:03:57.985303 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9942 11:03:57.988581 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9943 11:03:57.992294 INFO: [APUAPC] D0_APC_0: 0x400510
9944 11:03:57.995119 INFO: [APUAPC] D0_APC_1: 0x0
9945 11:03:57.998315 INFO: [APUAPC] D0_APC_2: 0x1540
9946 11:03:58.001687 INFO: [APUAPC] D0_APC_3: 0x0
9947 11:03:58.005076 INFO: [APUAPC] D1_APC_0: 0xffffffff
9948 11:03:58.008299 INFO: [APUAPC] D1_APC_1: 0xffffffff
9949 11:03:58.012010 INFO: [APUAPC] D1_APC_2: 0x3fffff
9950 11:03:58.015278 INFO: [APUAPC] D1_APC_3: 0x0
9951 11:03:58.018529 INFO: [APUAPC] D2_APC_0: 0xffffffff
9952 11:03:58.021659 INFO: [APUAPC] D2_APC_1: 0xffffffff
9953 11:03:58.025339 INFO: [APUAPC] D2_APC_2: 0x3fffff
9954 11:03:58.028549 INFO: [APUAPC] D2_APC_3: 0x0
9955 11:03:58.032042 INFO: [APUAPC] D3_APC_0: 0xffffffff
9956 11:03:58.034906 INFO: [APUAPC] D3_APC_1: 0xffffffff
9957 11:03:58.038318 INFO: [APUAPC] D3_APC_2: 0x3fffff
9958 11:03:58.038393 INFO: [APUAPC] D3_APC_3: 0x0
9959 11:03:58.045282 INFO: [APUAPC] D4_APC_0: 0xffffffff
9960 11:03:58.048376 INFO: [APUAPC] D4_APC_1: 0xffffffff
9961 11:03:58.051836 INFO: [APUAPC] D4_APC_2: 0x3fffff
9962 11:03:58.051926 INFO: [APUAPC] D4_APC_3: 0x0
9963 11:03:58.054831 INFO: [APUAPC] D5_APC_0: 0xffffffff
9964 11:03:58.058472 INFO: [APUAPC] D5_APC_1: 0xffffffff
9965 11:03:58.061633 INFO: [APUAPC] D5_APC_2: 0x3fffff
9966 11:03:58.065276 INFO: [APUAPC] D5_APC_3: 0x0
9967 11:03:58.068484 INFO: [APUAPC] D6_APC_0: 0xffffffff
9968 11:03:58.071516 INFO: [APUAPC] D6_APC_1: 0xffffffff
9969 11:03:58.074650 INFO: [APUAPC] D6_APC_2: 0x3fffff
9970 11:03:58.078470 INFO: [APUAPC] D6_APC_3: 0x0
9971 11:03:58.081910 INFO: [APUAPC] D7_APC_0: 0xffffffff
9972 11:03:58.085389 INFO: [APUAPC] D7_APC_1: 0xffffffff
9973 11:03:58.088308 INFO: [APUAPC] D7_APC_2: 0x3fffff
9974 11:03:58.091692 INFO: [APUAPC] D7_APC_3: 0x0
9975 11:03:58.095103 INFO: [APUAPC] D8_APC_0: 0xffffffff
9976 11:03:58.098311 INFO: [APUAPC] D8_APC_1: 0xffffffff
9977 11:03:58.101578 INFO: [APUAPC] D8_APC_2: 0x3fffff
9978 11:03:58.104699 INFO: [APUAPC] D8_APC_3: 0x0
9979 11:03:58.108326 INFO: [APUAPC] D9_APC_0: 0xffffffff
9980 11:03:58.111726 INFO: [APUAPC] D9_APC_1: 0xffffffff
9981 11:03:58.115100 INFO: [APUAPC] D9_APC_2: 0x3fffff
9982 11:03:58.118381 INFO: [APUAPC] D9_APC_3: 0x0
9983 11:03:58.121339 INFO: [APUAPC] D10_APC_0: 0xffffffff
9984 11:03:58.124956 INFO: [APUAPC] D10_APC_1: 0xffffffff
9985 11:03:58.127944 INFO: [APUAPC] D10_APC_2: 0x3fffff
9986 11:03:58.131650 INFO: [APUAPC] D10_APC_3: 0x0
9987 11:03:58.134701 INFO: [APUAPC] D11_APC_0: 0xffffffff
9988 11:03:58.138121 INFO: [APUAPC] D11_APC_1: 0xffffffff
9989 11:03:58.141684 INFO: [APUAPC] D11_APC_2: 0x3fffff
9990 11:03:58.144482 INFO: [APUAPC] D11_APC_3: 0x0
9991 11:03:58.148010 INFO: [APUAPC] D12_APC_0: 0xffffffff
9992 11:03:58.151624 INFO: [APUAPC] D12_APC_1: 0xffffffff
9993 11:03:58.155081 INFO: [APUAPC] D12_APC_2: 0x3fffff
9994 11:03:58.157961 INFO: [APUAPC] D12_APC_3: 0x0
9995 11:03:58.161803 INFO: [APUAPC] D13_APC_0: 0xffffffff
9996 11:03:58.164904 INFO: [APUAPC] D13_APC_1: 0xffffffff
9997 11:03:58.167819 INFO: [APUAPC] D13_APC_2: 0x3fffff
9998 11:03:58.171150 INFO: [APUAPC] D13_APC_3: 0x0
9999 11:03:58.174686 INFO: [APUAPC] D14_APC_0: 0xffffffff
10000 11:03:58.178191 INFO: [APUAPC] D14_APC_1: 0xffffffff
10001 11:03:58.181605 INFO: [APUAPC] D14_APC_2: 0x3fffff
10002 11:03:58.184616 INFO: [APUAPC] D14_APC_3: 0x0
10003 11:03:58.187907 INFO: [APUAPC] D15_APC_0: 0xffffffff
10004 11:03:58.191335 INFO: [APUAPC] D15_APC_1: 0xffffffff
10005 11:03:58.195330 INFO: [APUAPC] D15_APC_2: 0x3fffff
10006 11:03:58.198543 INFO: [APUAPC] D15_APC_3: 0x0
10007 11:03:58.201543 INFO: [APUAPC] APC_CON: 0x4
10008 11:03:58.204853 INFO: [NOCDAPC] D0_APC_0: 0x0
10009 11:03:58.208303 INFO: [NOCDAPC] D0_APC_1: 0x0
10010 11:03:58.208369 INFO: [NOCDAPC] D1_APC_0: 0x0
10011 11:03:58.211452 INFO: [NOCDAPC] D1_APC_1: 0xfff
10012 11:03:58.214956 INFO: [NOCDAPC] D2_APC_0: 0x0
10013 11:03:58.218309 INFO: [NOCDAPC] D2_APC_1: 0xfff
10014 11:03:58.221845 INFO: [NOCDAPC] D3_APC_0: 0x0
10015 11:03:58.224544 INFO: [NOCDAPC] D3_APC_1: 0xfff
10016 11:03:58.227836 INFO: [NOCDAPC] D4_APC_0: 0x0
10017 11:03:58.231218 INFO: [NOCDAPC] D4_APC_1: 0xfff
10018 11:03:58.234982 INFO: [NOCDAPC] D5_APC_0: 0x0
10019 11:03:58.238323 INFO: [NOCDAPC] D5_APC_1: 0xfff
10020 11:03:58.241386 INFO: [NOCDAPC] D6_APC_0: 0x0
10021 11:03:58.244772 INFO: [NOCDAPC] D6_APC_1: 0xfff
10022 11:03:58.244864 INFO: [NOCDAPC] D7_APC_0: 0x0
10023 11:03:58.247883 INFO: [NOCDAPC] D7_APC_1: 0xfff
10024 11:03:58.251420 INFO: [NOCDAPC] D8_APC_0: 0x0
10025 11:03:58.254329 INFO: [NOCDAPC] D8_APC_1: 0xfff
10026 11:03:58.257947 INFO: [NOCDAPC] D9_APC_0: 0x0
10027 11:03:58.261637 INFO: [NOCDAPC] D9_APC_1: 0xfff
10028 11:03:58.264756 INFO: [NOCDAPC] D10_APC_0: 0x0
10029 11:03:58.267950 INFO: [NOCDAPC] D10_APC_1: 0xfff
10030 11:03:58.271281 INFO: [NOCDAPC] D11_APC_0: 0x0
10031 11:03:58.274703 INFO: [NOCDAPC] D11_APC_1: 0xfff
10032 11:03:58.277583 INFO: [NOCDAPC] D12_APC_0: 0x0
10033 11:03:58.280901 INFO: [NOCDAPC] D12_APC_1: 0xfff
10034 11:03:58.284577 INFO: [NOCDAPC] D13_APC_0: 0x0
10035 11:03:58.284670 INFO: [NOCDAPC] D13_APC_1: 0xfff
10036 11:03:58.287534 INFO: [NOCDAPC] D14_APC_0: 0x0
10037 11:03:58.291011 INFO: [NOCDAPC] D14_APC_1: 0xfff
10038 11:03:58.294157 INFO: [NOCDAPC] D15_APC_0: 0x0
10039 11:03:58.298145 INFO: [NOCDAPC] D15_APC_1: 0xfff
10040 11:03:58.300737 INFO: [NOCDAPC] APC_CON: 0x4
10041 11:03:58.304731 INFO: [APUAPC] set_apusys_apc done
10042 11:03:58.307732 INFO: [DEVAPC] devapc_init done
10043 11:03:58.311050 INFO: GICv3 without legacy support detected.
10044 11:03:58.314260 INFO: ARM GICv3 driver initialized in EL3
10045 11:03:58.321184 INFO: Maximum SPI INTID supported: 639
10046 11:03:58.324431 INFO: BL31: Initializing runtime services
10047 11:03:58.330910 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10048 11:03:58.330986 INFO: SPM: enable CPC mode
10049 11:03:58.337454 INFO: mcdi ready for mcusys-off-idle and system suspend
10050 11:03:58.340810 INFO: BL31: Preparing for EL3 exit to normal world
10051 11:03:58.344067 INFO: Entry point address = 0x80000000
10052 11:03:58.347385 INFO: SPSR = 0x8
10053 11:03:58.353156
10054 11:03:58.353225
10055 11:03:58.353282
10056 11:03:58.356277 Starting depthcharge on Spherion...
10057 11:03:58.356343
10058 11:03:58.356400 Wipe memory regions:
10059 11:03:58.356454
10060 11:03:58.357059 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10061 11:03:58.357170 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10062 11:03:58.357247 Setting prompt string to ['asurada:']
10063 11:03:58.357312 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10064 11:03:58.359692 [0x00000040000000, 0x00000054600000)
10065 11:03:58.482240
10066 11:03:58.482353 [0x00000054660000, 0x00000080000000)
10067 11:03:58.742808
10068 11:03:58.742956 [0x000000821a7280, 0x000000ffe64000)
10069 11:03:59.487229
10070 11:03:59.487350 [0x00000100000000, 0x00000240000000)
10071 11:04:01.377095
10072 11:04:01.380369 Initializing XHCI USB controller at 0x11200000.
10073 11:04:02.418616
10074 11:04:02.421493 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10075 11:04:02.421706
10076 11:04:02.421824
10077 11:04:02.422112 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10078 11:04:02.422200 Sending line: 'tftpboot 192.168.201.1 14786822/tftp-deploy-6460t7t3/kernel/image.itb 14786822/tftp-deploy-6460t7t3/kernel/cmdline '
10080 11:04:02.522717 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10081 11:04:02.522828 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10082 11:04:02.526890 asurada: tftpboot 192.168.201.1 14786822/tftp-deploy-6460t7t3/kernel/image.itp-deploy-6460t7t3/kernel/cmdline
10083 11:04:02.526966
10084 11:04:02.527025 Waiting for link
10085 11:04:02.684610
10086 11:04:02.684713 R8152: Initializing
10087 11:04:02.684774
10088 11:04:02.688309 Version 9 (ocp_data = 6010)
10089 11:04:02.688385
10090 11:04:02.691311 R8152: Done initializing
10091 11:04:02.691387
10092 11:04:02.691445 Adding net device
10093 11:04:04.566570
10094 11:04:04.566687 done.
10095 11:04:04.566747
10096 11:04:04.566803 MAC: 00:e0:4c:78:7a:aa
10097 11:04:04.566857
10098 11:04:04.569844 Sending DHCP discover... done.
10099 11:04:04.569920
10100 11:04:04.573352 Waiting for reply... done.
10101 11:04:04.573451
10102 11:04:04.576725 Sending DHCP request... done.
10103 11:04:04.576814
10104 11:04:04.600109 Waiting for reply... done.
10105 11:04:04.600205
10106 11:04:04.600268 My ip is 192.168.201.12
10107 11:04:04.600323
10108 11:04:04.603070 The DHCP server ip is 192.168.201.1
10109 11:04:04.603151
10110 11:04:04.610417 TFTP server IP predefined by user: 192.168.201.1
10111 11:04:04.610496
10112 11:04:04.616914 Bootfile predefined by user: 14786822/tftp-deploy-6460t7t3/kernel/image.itb
10113 11:04:04.617008
10114 11:04:04.617091 Sending tftp read request... done.
10115 11:04:04.619758
10116 11:04:04.623520 Waiting for the transfer...
10117 11:04:04.623596
10118 11:04:04.885982 00000000 ################################################################
10119 11:04:04.886130
10120 11:04:05.147386 00080000 ################################################################
10121 11:04:05.147536
10122 11:04:05.411327 00100000 ################################################################
10123 11:04:05.411443
10124 11:04:05.670489 00180000 ################################################################
10125 11:04:05.670627
10126 11:04:05.924003 00200000 ################################################################
10127 11:04:05.924145
10128 11:04:06.178738 00280000 ################################################################
10129 11:04:06.178851
10130 11:04:06.432265 00300000 ################################################################
10131 11:04:06.432384
10132 11:04:06.681889 00380000 ################################################################
10133 11:04:06.682002
10134 11:04:06.932994 00400000 ################################################################
10135 11:04:06.933153
10136 11:04:07.184599 00480000 ################################################################
10137 11:04:07.184723
10138 11:04:07.435562 00500000 ################################################################
10139 11:04:07.435679
10140 11:04:07.692537 00580000 ################################################################
10141 11:04:07.692652
10142 11:04:07.951531 00600000 ################################################################
10143 11:04:07.951651
10144 11:04:08.212163 00680000 ################################################################
10145 11:04:08.212283
10146 11:04:08.469804 00700000 ################################################################
10147 11:04:08.469918
10148 11:04:08.739868 00780000 ################################################################
10149 11:04:08.739986
10150 11:04:09.010523 00800000 ################################################################
10151 11:04:09.010647
10152 11:04:09.291838 00880000 ################################################################
10153 11:04:09.291961
10154 11:04:09.586121 00900000 ################################################################
10155 11:04:09.586248
10156 11:04:09.864040 00980000 ################################################################
10157 11:04:09.864161
10158 11:04:10.150812 00a00000 ################################################################
10159 11:04:10.150936
10160 11:04:10.441345 00a80000 ################################################################
10161 11:04:10.441457
10162 11:04:10.710796 00b00000 ################################################################
10163 11:04:10.710907
10164 11:04:11.003591 00b80000 ################################################################
10165 11:04:11.003704
10166 11:04:11.283715 00c00000 ################################################################
10167 11:04:11.283830
10168 11:04:11.572953 00c80000 ################################################################
10169 11:04:11.573067
10170 11:04:11.832608 00d00000 ################################################################
10171 11:04:11.832720
10172 11:04:12.106486 00d80000 ################################################################
10173 11:04:12.106604
10174 11:04:12.376259 00e00000 ################################################################
10175 11:04:12.376372
10176 11:04:12.670912 00e80000 ################################################################
10177 11:04:12.671042
10178 11:04:12.946070 00f00000 ################################################################
10179 11:04:12.946182
10180 11:04:13.228621 00f80000 ################################################################
10181 11:04:13.228733
10182 11:04:13.507912 01000000 ################################################################
10183 11:04:13.508030
10184 11:04:13.776209 01080000 ################################################################
10185 11:04:13.776315
10186 11:04:14.061543 01100000 ################################################################
10187 11:04:14.061666
10188 11:04:14.354273 01180000 ################################################################
10189 11:04:14.354404
10190 11:04:14.625765 01200000 ################################################################
10191 11:04:14.625874
10192 11:04:14.895294 01280000 ################################################################
10193 11:04:14.895407
10194 11:04:15.179484 01300000 ################################################################
10195 11:04:15.179609
10196 11:04:15.456787 01380000 ################################################################
10197 11:04:15.456991
10198 11:04:15.756624 01400000 ################################################################
10199 11:04:15.756749
10200 11:04:16.051411 01480000 ################################################################
10201 11:04:16.051533
10202 11:04:16.339761 01500000 ################################################################
10203 11:04:16.339887
10204 11:04:16.628101 01580000 ################################################################
10205 11:04:16.628213
10206 11:04:16.893739 01600000 ################################################################
10207 11:04:16.893867
10208 11:04:17.164252 01680000 ################################################################
10209 11:04:17.164369
10210 11:04:17.420007 01700000 ################################################################
10211 11:04:17.420119
10212 11:04:17.679970 01780000 ################################################################
10213 11:04:17.680085
10214 11:04:17.944521 01800000 ################################################################
10215 11:04:17.944645
10216 11:04:18.199516 01880000 ################################################################
10217 11:04:18.199639
10218 11:04:18.449726 01900000 ################################################################
10219 11:04:18.449843
10220 11:04:18.700384 01980000 ################################################################
10221 11:04:18.700524
10222 11:04:18.951718 01a00000 ################################################################
10223 11:04:18.951831
10224 11:04:19.209324 01a80000 ################################################################
10225 11:04:19.209436
10226 11:04:19.469381 01b00000 ################################################################
10227 11:04:19.469488
10228 11:04:19.736505 01b80000 ################################################################
10229 11:04:19.736640
10230 11:04:20.008034 01c00000 ################################################################
10231 11:04:20.008146
10232 11:04:20.276682 01c80000 ################################################################
10233 11:04:20.276832
10234 11:04:20.555591 01d00000 ################################################################
10235 11:04:20.555701
10236 11:04:20.826480 01d80000 ################################################################
10237 11:04:20.826596
10238 11:04:21.041761 01e00000 ################################################### done.
10239 11:04:21.041879
10240 11:04:21.044784 The bootfile was 31873422 bytes long.
10241 11:04:21.044869
10242 11:04:21.048349 Sending tftp read request... done.
10243 11:04:21.048440
10244 11:04:21.048500 Waiting for the transfer...
10245 11:04:21.048555
10246 11:04:21.051846 00000000 # done.
10247 11:04:21.051926
10248 11:04:21.058532 Command line loaded dynamically from TFTP file: 14786822/tftp-deploy-6460t7t3/kernel/cmdline
10249 11:04:21.058612
10250 11:04:21.081674 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14786822/extract-nfsrootfs-hzf441ob,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10251 11:04:21.081767
10252 11:04:21.081827 Loading FIT.
10253 11:04:21.081883
10254 11:04:21.085008 Image ramdisk-1 has 18707877 bytes.
10255 11:04:21.085085
10256 11:04:21.088457 Image fdt-1 has 47258 bytes.
10257 11:04:21.088533
10258 11:04:21.091326 Image kernel-1 has 13116259 bytes.
10259 11:04:21.091404
10260 11:04:21.101636 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10261 11:04:21.101715
10262 11:04:21.118310 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10263 11:04:21.118391
10264 11:04:21.125048 Choosing best match conf-1 for compat google,spherion-rev2.
10265 11:04:21.125129
10266 11:04:21.128548 Connected to device vid:did:rid of 1ae0:0028:00
10267 11:04:21.140257
10268 11:04:21.143611 tpm_get_response: command 0x17b, return code 0x0
10269 11:04:21.143703
10270 11:04:21.146895 ec_init: CrosEC protocol v3 supported (256, 248)
10271 11:04:21.150856
10272 11:04:21.150931 tpm_cleanup: add release locality here.
10273 11:04:21.154305
10274 11:04:21.154379 Shutting down all USB controllers.
10275 11:04:21.154438
10276 11:04:21.157454 Removing current net device
10277 11:04:21.157528
10278 11:04:21.164717 Exiting depthcharge with code 4 at timestamp: 52017629
10279 11:04:21.164792
10280 11:04:21.168007 LZMA decompressing kernel-1 to 0x821a6718
10281 11:04:21.168083
10282 11:04:21.171522 LZMA decompressing kernel-1 to 0x40000000
10283 11:04:22.786245
10284 11:04:22.786361 jumping to kernel
10285 11:04:22.786820 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10286 11:04:22.786912 start: 2.2.5 auto-login-action (timeout 00:03:56) [common]
10287 11:04:22.786983 Setting prompt string to ['Linux version [0-9]']
10288 11:04:22.787046 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10289 11:04:22.787113 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10290 11:04:22.867498
10291 11:04:22.870504 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10292 11:04:22.874155 start: 2.2.5.1 login-action (timeout 00:03:56) [common]
10293 11:04:22.874267 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10294 11:04:22.874335 Setting prompt string to []
10295 11:04:22.874409 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10296 11:04:22.874488 Using line separator: #'\n'#
10297 11:04:22.874541 No login prompt set.
10298 11:04:22.874594 Parsing kernel messages
10299 11:04:22.874644 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10300 11:04:22.874741 [login-action] Waiting for messages, (timeout 00:03:56)
10301 11:04:22.874800 Waiting using forced prompt support (timeout 00:01:58)
10302 11:04:22.893572 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j261272-arm64-gcc-12-defconfig-arm64-chromebook-bgdbp) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024
10303 11:04:22.896681 [ 0.000000] random: crng init done
10304 11:04:22.900410 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10305 11:04:22.903815 [ 0.000000] efi: UEFI not found.
10306 11:04:22.913256 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10307 11:04:22.920848 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10308 11:04:22.930484 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10309 11:04:22.940253 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10310 11:04:22.946719 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10311 11:04:22.950228 [ 0.000000] printk: bootconsole [mtk8250] enabled
10312 11:04:22.958085 [ 0.000000] NUMA: No NUMA configuration found
10313 11:04:22.964733 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10314 11:04:22.971533 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10315 11:04:22.971604 [ 0.000000] Zone ranges:
10316 11:04:22.977695 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10317 11:04:22.981323 [ 0.000000] DMA32 empty
10318 11:04:22.987769 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10319 11:04:22.991079 [ 0.000000] Movable zone start for each node
10320 11:04:22.994441 [ 0.000000] Early memory node ranges
10321 11:04:23.001155 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10322 11:04:23.007645 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10323 11:04:23.015069 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10324 11:04:23.021253 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10325 11:04:23.027639 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10326 11:04:23.034045 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10327 11:04:23.091642 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10328 11:04:23.098276 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10329 11:04:23.104414 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10330 11:04:23.108349 [ 0.000000] psci: probing for conduit method from DT.
10331 11:04:23.114690 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10332 11:04:23.117537 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10333 11:04:23.124961 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10334 11:04:23.128068 [ 0.000000] psci: SMC Calling Convention v1.2
10335 11:04:23.134291 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10336 11:04:23.137976 [ 0.000000] Detected VIPT I-cache on CPU0
10337 11:04:23.144494 [ 0.000000] CPU features: detected: GIC system register CPU interface
10338 11:04:23.150908 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10339 11:04:23.157721 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10340 11:04:23.164482 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10341 11:04:23.171073 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10342 11:04:23.178057 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10343 11:04:23.184610 [ 0.000000] alternatives: applying boot alternatives
10344 11:04:23.187866 [ 0.000000] Fallback order for Node 0: 0
10345 11:04:23.194181 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10346 11:04:23.197898 [ 0.000000] Policy zone: Normal
10347 11:04:23.224285 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14786822/extract-nfsrootfs-hzf441ob,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10348 11:04:23.234123 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10349 11:04:23.244175 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10350 11:04:23.254298 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10351 11:04:23.261249 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10352 11:04:23.264032 <6>[ 0.000000] software IO TLB: area num 8.
10353 11:04:23.322386 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10354 11:04:23.471278 <6>[ 0.000000] Memory: 7945788K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 406980K reserved, 32768K cma-reserved)
10355 11:04:23.477892 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10356 11:04:23.484688 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10357 11:04:23.487915 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10358 11:04:23.494822 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10359 11:04:23.501401 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10360 11:04:23.504847 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10361 11:04:23.514822 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10362 11:04:23.521069 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10363 11:04:23.524900 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10364 11:04:23.532757 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10365 11:04:23.535803 <6>[ 0.000000] GICv3: 608 SPIs implemented
10366 11:04:23.542230 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10367 11:04:23.546155 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10368 11:04:23.549299 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10369 11:04:23.558742 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10370 11:04:23.568794 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10371 11:04:23.582110 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10372 11:04:23.588726 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10373 11:04:23.597825 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10374 11:04:23.611316 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10375 11:04:23.618024 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10376 11:04:23.624568 <6>[ 0.009182] Console: colour dummy device 80x25
10377 11:04:23.634822 <6>[ 0.013914] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10378 11:04:23.638314 <6>[ 0.024355] pid_max: default: 32768 minimum: 301
10379 11:04:23.644251 <6>[ 0.029229] LSM: Security Framework initializing
10380 11:04:23.650946 <6>[ 0.034198] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10381 11:04:23.661185 <6>[ 0.042010] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10382 11:04:23.667555 <6>[ 0.051436] cblist_init_generic: Setting adjustable number of callback queues.
10383 11:04:23.674022 <6>[ 0.058879] cblist_init_generic: Setting shift to 3 and lim to 1.
10384 11:04:23.684331 <6>[ 0.065218] cblist_init_generic: Setting adjustable number of callback queues.
10385 11:04:23.687553 <6>[ 0.072691] cblist_init_generic: Setting shift to 3 and lim to 1.
10386 11:04:23.693950 <6>[ 0.079091] rcu: Hierarchical SRCU implementation.
10387 11:04:23.701135 <6>[ 0.084106] rcu: Max phase no-delay instances is 1000.
10388 11:04:23.707651 <6>[ 0.091135] EFI services will not be available.
10389 11:04:23.710491 <6>[ 0.096093] smp: Bringing up secondary CPUs ...
10390 11:04:23.718646 <6>[ 0.101145] Detected VIPT I-cache on CPU1
10391 11:04:23.725613 <6>[ 0.101217] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10392 11:04:23.731784 <6>[ 0.101247] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10393 11:04:23.735205 <6>[ 0.101592] Detected VIPT I-cache on CPU2
10394 11:04:23.741975 <6>[ 0.101645] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10395 11:04:23.748566 <6>[ 0.101664] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10396 11:04:23.755242 <6>[ 0.101929] Detected VIPT I-cache on CPU3
10397 11:04:23.761838 <6>[ 0.101977] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10398 11:04:23.768582 <6>[ 0.101991] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10399 11:04:23.771664 <6>[ 0.102302] CPU features: detected: Spectre-v4
10400 11:04:23.778526 <6>[ 0.102308] CPU features: detected: Spectre-BHB
10401 11:04:23.782038 <6>[ 0.102313] Detected PIPT I-cache on CPU4
10402 11:04:23.788805 <6>[ 0.102373] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10403 11:04:23.795488 <6>[ 0.102390] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10404 11:04:23.801973 <6>[ 0.102684] Detected PIPT I-cache on CPU5
10405 11:04:23.808571 <6>[ 0.102751] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10406 11:04:23.815179 <6>[ 0.102766] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10407 11:04:23.818449 <6>[ 0.103050] Detected PIPT I-cache on CPU6
10408 11:04:23.825125 <6>[ 0.103116] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10409 11:04:23.831475 <6>[ 0.103132] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10410 11:04:23.838646 <6>[ 0.103436] Detected PIPT I-cache on CPU7
10411 11:04:23.844726 <6>[ 0.103502] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10412 11:04:23.851520 <6>[ 0.103517] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10413 11:04:23.854862 <6>[ 0.103566] smp: Brought up 1 node, 8 CPUs
10414 11:04:23.861353 <6>[ 0.244977] SMP: Total of 8 processors activated.
10415 11:04:23.864700 <6>[ 0.249898] CPU features: detected: 32-bit EL0 Support
10416 11:04:23.874672 <6>[ 0.255261] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10417 11:04:23.881351 <6>[ 0.264061] CPU features: detected: Common not Private translations
10418 11:04:23.884527 <6>[ 0.270538] CPU features: detected: CRC32 instructions
10419 11:04:23.891107 <6>[ 0.275889] CPU features: detected: RCpc load-acquire (LDAPR)
10420 11:04:23.898352 <6>[ 0.281849] CPU features: detected: LSE atomic instructions
10421 11:04:23.904980 <6>[ 0.287630] CPU features: detected: Privileged Access Never
10422 11:04:23.908063 <6>[ 0.293410] CPU features: detected: RAS Extension Support
10423 11:04:23.917739 <6>[ 0.299053] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10424 11:04:23.921106 <6>[ 0.306274] CPU: All CPU(s) started at EL2
10425 11:04:23.927783 <6>[ 0.310618] alternatives: applying system-wide alternatives
10426 11:04:23.936719 <6>[ 0.321478] devtmpfs: initialized
10427 11:04:23.948849 <6>[ 0.330349] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10428 11:04:23.958798 <6>[ 0.340312] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10429 11:04:23.965574 <6>[ 0.348559] pinctrl core: initialized pinctrl subsystem
10430 11:04:23.968444 <6>[ 0.355247] DMI not present or invalid.
10431 11:04:23.975680 <6>[ 0.359667] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10432 11:04:23.985293 <6>[ 0.366576] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10433 11:04:23.991653 <6>[ 0.374161] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10434 11:04:24.001690 <6>[ 0.382391] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10435 11:04:24.005000 <6>[ 0.390637] audit: initializing netlink subsys (disabled)
10436 11:04:24.014845 <5>[ 0.396337] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10437 11:04:24.021611 <6>[ 0.397068] thermal_sys: Registered thermal governor 'step_wise'
10438 11:04:24.028352 <6>[ 0.404305] thermal_sys: Registered thermal governor 'power_allocator'
10439 11:04:24.031837 <6>[ 0.410563] cpuidle: using governor menu
10440 11:04:24.038418 <6>[ 0.421527] NET: Registered PF_QIPCRTR protocol family
10441 11:04:24.045570 <6>[ 0.427066] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10442 11:04:24.048427 <6>[ 0.434167] ASID allocator initialised with 32768 entries
10443 11:04:24.055798 <6>[ 0.440764] Serial: AMBA PL011 UART driver
10444 11:04:24.065147 <4>[ 0.450225] Trying to register duplicate clock ID: 134
10445 11:04:24.125186 <6>[ 0.513294] KASLR enabled
10446 11:04:24.139111 <6>[ 0.520950] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10447 11:04:24.146234 <6>[ 0.527965] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10448 11:04:24.152866 <6>[ 0.534453] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10449 11:04:24.159427 <6>[ 0.541458] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10450 11:04:24.165938 <6>[ 0.547945] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10451 11:04:24.172323 <6>[ 0.554949] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10452 11:04:24.178957 <6>[ 0.561435] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10453 11:04:24.185477 <6>[ 0.568438] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10454 11:04:24.188652 <6>[ 0.575922] ACPI: Interpreter disabled.
10455 11:04:24.197907 <6>[ 0.582385] iommu: Default domain type: Translated
10456 11:04:24.204580 <6>[ 0.587531] iommu: DMA domain TLB invalidation policy: strict mode
10457 11:04:24.207365 <5>[ 0.594192] SCSI subsystem initialized
10458 11:04:24.213951 <6>[ 0.598448] usbcore: registered new interface driver usbfs
10459 11:04:24.220774 <6>[ 0.604181] usbcore: registered new interface driver hub
10460 11:04:24.223702 <6>[ 0.609731] usbcore: registered new device driver usb
10461 11:04:24.230977 <6>[ 0.615872] pps_core: LinuxPPS API ver. 1 registered
10462 11:04:24.240789 <6>[ 0.621068] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10463 11:04:24.244271 <6>[ 0.630410] PTP clock support registered
10464 11:04:24.247890 <6>[ 0.634652] EDAC MC: Ver: 3.0.0
10465 11:04:24.255362 <6>[ 0.639848] FPGA manager framework
10466 11:04:24.261382 <6>[ 0.643526] Advanced Linux Sound Architecture Driver Initialized.
10467 11:04:24.264697 <6>[ 0.650329] vgaarb: loaded
10468 11:04:24.271916 <6>[ 0.653501] clocksource: Switched to clocksource arch_sys_counter
10469 11:04:24.274977 <5>[ 0.659949] VFS: Disk quotas dquot_6.6.0
10470 11:04:24.281901 <6>[ 0.664138] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10471 11:04:24.284653 <6>[ 0.671330] pnp: PnP ACPI: disabled
10472 11:04:24.293189 <6>[ 0.678031] NET: Registered PF_INET protocol family
10473 11:04:24.302956 <6>[ 0.683624] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10474 11:04:24.314607 <6>[ 0.695949] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10475 11:04:24.324399 <6>[ 0.704762] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10476 11:04:24.330619 <6>[ 0.712731] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10477 11:04:24.337414 <6>[ 0.721431] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10478 11:04:24.349370 <6>[ 0.731177] TCP: Hash tables configured (established 65536 bind 65536)
10479 11:04:24.356457 <6>[ 0.738052] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10480 11:04:24.362868 <6>[ 0.745248] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10481 11:04:24.369093 <6>[ 0.752954] NET: Registered PF_UNIX/PF_LOCAL protocol family
10482 11:04:24.376071 <6>[ 0.759109] RPC: Registered named UNIX socket transport module.
10483 11:04:24.379438 <6>[ 0.765263] RPC: Registered udp transport module.
10484 11:04:24.385841 <6>[ 0.770196] RPC: Registered tcp transport module.
10485 11:04:24.392862 <6>[ 0.775130] RPC: Registered tcp NFSv4.1 backchannel transport module.
10486 11:04:24.395553 <6>[ 0.781797] PCI: CLS 0 bytes, default 64
10487 11:04:24.399055 <6>[ 0.786170] Unpacking initramfs...
10488 11:04:24.408934 <6>[ 0.789886] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10489 11:04:24.415565 <6>[ 0.798516] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10490 11:04:24.422420 <6>[ 0.807323] kvm [1]: IPA Size Limit: 40 bits
10491 11:04:24.425699 <6>[ 0.811853] kvm [1]: GICv3: no GICV resource entry
10492 11:04:24.432328 <6>[ 0.816875] kvm [1]: disabling GICv2 emulation
10493 11:04:24.438833 <6>[ 0.821556] kvm [1]: GIC system register CPU interface enabled
10494 11:04:24.442406 <6>[ 0.827716] kvm [1]: vgic interrupt IRQ18
10495 11:04:24.448594 <6>[ 0.833553] kvm [1]: VHE mode initialized successfully
10496 11:04:24.455313 <5>[ 0.839946] Initialise system trusted keyrings
10497 11:04:24.461802 <6>[ 0.844718] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10498 11:04:24.469503 <6>[ 0.854723] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10499 11:04:24.476184 <5>[ 0.861107] NFS: Registering the id_resolver key type
10500 11:04:24.479797 <5>[ 0.866405] Key type id_resolver registered
10501 11:04:24.486484 <5>[ 0.870821] Key type id_legacy registered
10502 11:04:24.492844 <6>[ 0.875106] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10503 11:04:24.499691 <6>[ 0.882027] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10504 11:04:24.506254 <6>[ 0.889732] 9p: Installing v9fs 9p2000 file system support
10505 11:04:24.541933 <5>[ 0.926906] Key type asymmetric registered
10506 11:04:24.545728 <5>[ 0.931236] Asymmetric key parser 'x509' registered
10507 11:04:24.555508 <6>[ 0.936375] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10508 11:04:24.558738 <6>[ 0.943991] io scheduler mq-deadline registered
10509 11:04:24.562204 <6>[ 0.948750] io scheduler kyber registered
10510 11:04:24.580470 <6>[ 0.965845] EINJ: ACPI disabled.
10511 11:04:24.614329 <4>[ 0.992331] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10512 11:04:24.623784 <4>[ 1.002980] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10513 11:04:24.638873 <6>[ 1.024051] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10514 11:04:24.647283 <6>[ 1.032183] printk: console [ttyS0] disabled
10515 11:04:24.675521 <6>[ 1.056817] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10516 11:04:24.681914 <6>[ 1.066301] printk: console [ttyS0] enabled
10517 11:04:24.684989 <6>[ 1.066301] printk: console [ttyS0] enabled
10518 11:04:24.691692 <6>[ 1.075196] printk: bootconsole [mtk8250] disabled
10519 11:04:24.694933 <6>[ 1.075196] printk: bootconsole [mtk8250] disabled
10520 11:04:24.701561 <6>[ 1.086268] SuperH (H)SCI(F) driver initialized
10521 11:04:24.705341 <6>[ 1.091534] msm_serial: driver initialized
10522 11:04:24.718992 <6>[ 1.100457] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10523 11:04:24.728667 <6>[ 1.109005] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10524 11:04:24.735478 <6>[ 1.117547] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10525 11:04:24.745360 <6>[ 1.126174] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10526 11:04:24.751890 <6>[ 1.134881] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10527 11:04:24.762524 <6>[ 1.143601] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10528 11:04:24.771810 <6>[ 1.152142] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10529 11:04:24.778582 <6>[ 1.160936] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10530 11:04:24.788526 <6>[ 1.169478] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10531 11:04:24.799820 <6>[ 1.184970] loop: module loaded
10532 11:04:24.806849 <6>[ 1.191002] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10533 11:04:24.828758 <4>[ 1.213786] mtk-pmic-keys: Failed to locate of_node [id: -1]
10534 11:04:24.835464 <6>[ 1.220616] megasas: 07.719.03.00-rc1
10535 11:04:24.845098 <6>[ 1.230289] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10536 11:04:24.856086 <6>[ 1.240874] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10537 11:04:24.871691 <6>[ 1.256703] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10538 11:04:24.925494 <6>[ 1.304056] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10539 11:04:25.194403 <6>[ 1.579193] Freeing initrd memory: 18268K
10540 11:04:25.205753 <6>[ 1.590709] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10541 11:04:25.216486 <6>[ 1.601593] tun: Universal TUN/TAP device driver, 1.6
10542 11:04:25.219862 <6>[ 1.607651] thunder_xcv, ver 1.0
10543 11:04:25.223661 <6>[ 1.611158] thunder_bgx, ver 1.0
10544 11:04:25.227121 <6>[ 1.614656] nicpf, ver 1.0
10545 11:04:25.236954 <6>[ 1.618670] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10546 11:04:25.240076 <6>[ 1.626145] hns3: Copyright (c) 2017 Huawei Corporation.
10547 11:04:25.243923 <6>[ 1.631734] hclge is initializing
10548 11:04:25.250331 <6>[ 1.635313] e1000: Intel(R) PRO/1000 Network Driver
10549 11:04:25.257019 <6>[ 1.640443] e1000: Copyright (c) 1999-2006 Intel Corporation.
10550 11:04:25.260105 <6>[ 1.646456] e1000e: Intel(R) PRO/1000 Network Driver
10551 11:04:25.266956 <6>[ 1.651672] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10552 11:04:25.273678 <6>[ 1.657857] igb: Intel(R) Gigabit Ethernet Network Driver
10553 11:04:25.280182 <6>[ 1.663506] igb: Copyright (c) 2007-2014 Intel Corporation.
10554 11:04:25.286704 <6>[ 1.669341] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10555 11:04:25.293733 <6>[ 1.675859] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10556 11:04:25.296904 <6>[ 1.682322] sky2: driver version 1.30
10557 11:04:25.303528 <6>[ 1.687253] usbcore: registered new device driver r8152-cfgselector
10558 11:04:25.310048 <6>[ 1.693790] usbcore: registered new interface driver r8152
10559 11:04:25.313309 <6>[ 1.699601] VFIO - User Level meta-driver version: 0.3
10560 11:04:25.322588 <6>[ 1.707858] usbcore: registered new interface driver usb-storage
10561 11:04:25.329864 <6>[ 1.714306] usbcore: registered new device driver onboard-usb-hub
10562 11:04:25.338513 <6>[ 1.723446] mt6397-rtc mt6359-rtc: registered as rtc0
10563 11:04:25.348730 <6>[ 1.728913] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-10T11:04:10 UTC (1720609450)
10564 11:04:25.351990 <6>[ 1.738481] i2c_dev: i2c /dev entries driver
10565 11:04:25.365228 <4>[ 1.750541] cpu cpu0: supply cpu not found, using dummy regulator
10566 11:04:25.372031 <4>[ 1.757003] cpu cpu1: supply cpu not found, using dummy regulator
10567 11:04:25.378645 <4>[ 1.763408] cpu cpu2: supply cpu not found, using dummy regulator
10568 11:04:25.385916 <4>[ 1.769810] cpu cpu3: supply cpu not found, using dummy regulator
10569 11:04:25.392404 <4>[ 1.776207] cpu cpu4: supply cpu not found, using dummy regulator
10570 11:04:25.398900 <4>[ 1.782604] cpu cpu5: supply cpu not found, using dummy regulator
10571 11:04:25.405534 <4>[ 1.789005] cpu cpu6: supply cpu not found, using dummy regulator
10572 11:04:25.412037 <4>[ 1.795423] cpu cpu7: supply cpu not found, using dummy regulator
10573 11:04:25.430958 <6>[ 1.816062] cpu cpu0: EM: created perf domain
10574 11:04:25.434395 <6>[ 1.820981] cpu cpu4: EM: created perf domain
10575 11:04:25.441358 <6>[ 1.826546] sdhci: Secure Digital Host Controller Interface driver
10576 11:04:25.448129 <6>[ 1.832980] sdhci: Copyright(c) Pierre Ossman
10577 11:04:25.455152 <6>[ 1.837937] Synopsys Designware Multimedia Card Interface Driver
10578 11:04:25.461721 <6>[ 1.844573] sdhci-pltfm: SDHCI platform and OF driver helper
10579 11:04:25.465134 <6>[ 1.844615] mmc0: CQHCI version 5.10
10580 11:04:25.471978 <6>[ 1.854838] ledtrig-cpu: registered to indicate activity on CPUs
10581 11:04:25.478233 <6>[ 1.861917] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10582 11:04:25.485282 <6>[ 1.868968] usbcore: registered new interface driver usbhid
10583 11:04:25.488549 <6>[ 1.874789] usbhid: USB HID core driver
10584 11:04:25.495234 <6>[ 1.878987] spi_master spi0: will run message pump with realtime priority
10585 11:04:25.540662 <6>[ 1.918821] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10586 11:04:25.559104 <6>[ 1.934196] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10587 11:04:25.562603 <6>[ 1.944080] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15c14
10588 11:04:25.569711 <6>[ 1.954714] cros-ec-spi spi0.0: Chrome EC device registered
10589 11:04:25.576299 <6>[ 1.960746] mmc0: Command Queue Engine enabled
10590 11:04:25.583538 <6>[ 1.965552] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10591 11:04:25.586242 <6>[ 1.973283] mmcblk0: mmc0:0001 DA4128 116 GiB
10592 11:04:25.597162 <6>[ 1.982316] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10593 11:04:25.604519 <6>[ 1.989821] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10594 11:04:25.611131 <6>[ 1.996022] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10595 11:04:25.621541 <6>[ 2.001841] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10596 11:04:25.628513 <6>[ 2.001983] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10597 11:04:25.631366 <6>[ 2.012436] NET: Registered PF_PACKET protocol family
10598 11:04:25.638172 <6>[ 2.023077] 9pnet: Installing 9P2000 support
10599 11:04:25.641586 <5>[ 2.027649] Key type dns_resolver registered
10600 11:04:25.648173 <6>[ 2.032669] registered taskstats version 1
10601 11:04:25.651308 <5>[ 2.037053] Loading compiled-in X.509 certificates
10602 11:04:25.682482 <4>[ 2.060864] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10603 11:04:25.692687 <4>[ 2.071822] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10604 11:04:25.707466 <6>[ 2.092505] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10605 11:04:25.714504 <6>[ 2.099574] xhci-mtk 11200000.usb: xHCI Host Controller
10606 11:04:25.721111 <6>[ 2.105076] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10607 11:04:25.731447 <6>[ 2.112919] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10608 11:04:25.738197 <6>[ 2.122345] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10609 11:04:25.744988 <6>[ 2.128435] xhci-mtk 11200000.usb: xHCI Host Controller
10610 11:04:25.751772 <6>[ 2.133914] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10611 11:04:25.758317 <6>[ 2.141566] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10612 11:04:25.764853 <6>[ 2.149193] hub 1-0:1.0: USB hub found
10613 11:04:25.768136 <6>[ 2.153214] hub 1-0:1.0: 1 port detected
10614 11:04:25.774627 <6>[ 2.157501] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10615 11:04:25.781197 <6>[ 2.166037] hub 2-0:1.0: USB hub found
10616 11:04:25.784404 <6>[ 2.170047] hub 2-0:1.0: 1 port detected
10617 11:04:25.792286 <6>[ 2.177357] mtk-msdc 11f70000.mmc: Got CD GPIO
10618 11:04:25.810285 <6>[ 2.191542] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10619 11:04:25.816716 <6>[ 2.200011] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10620 11:04:25.826812 <6>[ 2.208355] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10621 11:04:25.833315 <6>[ 2.216719] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10622 11:04:25.843905 <6>[ 2.225059] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10623 11:04:25.850276 <6>[ 2.233414] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10624 11:04:25.859738 <6>[ 2.241754] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10625 11:04:25.866567 <6>[ 2.250106] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10626 11:04:25.876525 <6>[ 2.258445] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10627 11:04:25.883647 <6>[ 2.266795] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10628 11:04:25.893414 <6>[ 2.275135] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10629 11:04:25.903222 <6>[ 2.283492] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10630 11:04:25.910580 <6>[ 2.291832] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10631 11:04:25.920029 <6>[ 2.300182] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10632 11:04:25.926629 <6>[ 2.308524] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10633 11:04:25.933157 <6>[ 2.317234] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10634 11:04:25.939986 <6>[ 2.324419] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10635 11:04:25.946127 <6>[ 2.331206] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10636 11:04:25.952858 <6>[ 2.337980] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10637 11:04:25.962809 <6>[ 2.344908] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10638 11:04:25.969539 <6>[ 2.351760] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10639 11:04:25.979616 <6>[ 2.360894] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10640 11:04:25.989465 <6>[ 2.370014] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10641 11:04:25.999725 <6>[ 2.379309] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10642 11:04:26.009800 <6>[ 2.388777] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10643 11:04:26.016490 <6>[ 2.398245] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10644 11:04:26.025767 <6>[ 2.407365] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10645 11:04:26.036193 <6>[ 2.416832] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10646 11:04:26.045737 <6>[ 2.425951] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10647 11:04:26.055653 <6>[ 2.435246] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10648 11:04:26.065619 <6>[ 2.445437] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10649 11:04:26.075981 <6>[ 2.456866] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10650 11:04:26.082632 <6>[ 2.467867] Trying to probe devices needed for running init ...
10651 11:04:26.093097 <3>[ 2.475091] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10652 11:04:26.200148 <6>[ 2.581789] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10653 11:04:26.354691 <6>[ 2.739790] hub 1-1:1.0: USB hub found
10654 11:04:26.357682 <6>[ 2.744189] hub 1-1:1.0: 4 ports detected
10655 11:04:26.370011 <6>[ 2.754870] hub 1-1:1.0: USB hub found
10656 11:04:26.373095 <6>[ 2.759279] hub 1-1:1.0: 4 ports detected
10657 11:04:26.480481 <6>[ 2.862137] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10658 11:04:26.506304 <6>[ 2.891658] hub 2-1:1.0: USB hub found
10659 11:04:26.510233 <6>[ 2.896160] hub 2-1:1.0: 3 ports detected
10660 11:04:26.521014 <6>[ 2.906200] hub 2-1:1.0: USB hub found
10661 11:04:26.524560 <6>[ 2.910565] hub 2-1:1.0: 3 ports detected
10662 11:04:26.691884 <6>[ 3.073794] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10663 11:04:26.824699 <6>[ 3.209639] hub 1-1.4:1.0: USB hub found
10664 11:04:26.828115 <6>[ 3.214302] hub 1-1.4:1.0: 2 ports detected
10665 11:04:26.840507 <6>[ 3.225700] hub 1-1.4:1.0: USB hub found
10666 11:04:26.843914 <6>[ 3.230285] hub 1-1.4:1.0: 2 ports detected
10667 11:04:26.903961 <6>[ 3.286030] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10668 11:04:27.012273 <6>[ 3.394460] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10669 11:04:27.048536 <4>[ 3.430253] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10670 11:04:27.058174 <4>[ 3.439346] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10671 11:04:27.097826 <6>[ 3.483347] r8152 2-1.3:1.0 eth0: v1.12.13
10672 11:04:27.139564 <6>[ 3.521626] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10673 11:04:27.335928 <6>[ 3.717730] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10674 11:04:28.680695 <6>[ 5.066188] r8152 2-1.3:1.0 eth0: carrier on
10675 11:04:31.076334 <5>[ 5.085588] Sending DHCP requests .., OK
10676 11:04:31.082847 <6>[ 7.465883] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10677 11:04:31.085959 <6>[ 7.474178] IP-Config: Complete:
10678 11:04:31.099287 <6>[ 7.477673] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10679 11:04:31.105690 <6>[ 7.488381] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10680 11:04:31.112412 <6>[ 7.496995] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10681 11:04:31.118932 <6>[ 7.497004] nameserver0=192.168.201.1
10682 11:04:31.122536 <6>[ 7.509130] clk: Disabling unused clocks
10683 11:04:31.125483 <6>[ 7.514655] ALSA device list:
10684 11:04:31.132181 <6>[ 7.517935] No soundcards found.
10685 11:04:31.140366 <6>[ 7.525731] Freeing unused kernel memory: 8512K
10686 11:04:31.143855 <6>[ 7.530612] Run /init as init process
10687 11:04:31.152557 Loading, please wait...
10688 11:04:31.186393 Starting systemd-udevd version 252.22-1~deb12u1
10689 11:04:31.427336 <6>[ 7.809610] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10690 11:04:31.433695 <6>[ 7.811298] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10691 11:04:31.440308 <6>[ 7.826214] remoteproc remoteproc0: scp is available
10692 11:04:31.450244 <6>[ 7.831508] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10693 11:04:31.457329 <6>[ 7.831532] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10694 11:04:31.467395 <4>[ 7.831733] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10695 11:04:31.473795 <6>[ 7.832291] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10696 11:04:31.480535 <6>[ 7.834182] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10697 11:04:31.490351 <6>[ 7.834281] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10698 11:04:31.500443 <6>[ 7.834299] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10699 11:04:31.503469 <6>[ 7.844898] remoteproc remoteproc0: powering up scp
10700 11:04:31.513459 <6>[ 7.849705] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10701 11:04:31.520039 <6>[ 7.857322] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10702 11:04:31.530330 <6>[ 7.867482] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10703 11:04:31.533446 <6>[ 7.872660] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10704 11:04:31.543400 <3>[ 7.893557] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 11:04:31.549935 <6>[ 7.895209] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10706 11:04:31.556430 <4>[ 7.898492] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10707 11:04:31.566822 <4>[ 7.898659] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10708 11:04:31.573249 <3>[ 7.903139] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 11:04:31.580049 <6>[ 7.911526] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10710 11:04:31.589937 <6>[ 7.911534] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10711 11:04:31.593401 <6>[ 7.926242] mc: Linux media interface: v0.10
10712 11:04:31.602961 <3>[ 7.933569] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10713 11:04:31.609464 <6>[ 7.935757] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10714 11:04:31.616424 <6>[ 7.998796] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10715 11:04:31.626620 <6>[ 7.998823] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10716 11:04:31.632715 <6>[ 7.998831] remoteproc remoteproc0: remote processor scp is now up
10717 11:04:31.639304 <3>[ 8.001230] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 11:04:31.649535 <6>[ 8.012155] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10719 11:04:31.656176 <6>[ 8.014427] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10720 11:04:31.662448 <6>[ 8.014435] pci_bus 0000:00: root bus resource [bus 00-ff]
10721 11:04:31.669300 <6>[ 8.014442] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10722 11:04:31.679412 <6>[ 8.014447] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10723 11:04:31.686125 <6>[ 8.014483] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10724 11:04:31.693152 <6>[ 8.014508] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10725 11:04:31.696841 <6>[ 8.014602] pci 0000:00:00.0: supports D1 D2
10726 11:04:31.706534 <6>[ 8.014606] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10727 11:04:31.713222 <6>[ 8.016314] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10728 11:04:31.719875 <6>[ 8.016429] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10729 11:04:31.726313 <6>[ 8.016460] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10730 11:04:31.733691 <6>[ 8.016483] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10731 11:04:31.743078 <6>[ 8.016502] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10732 11:04:31.746506 <6>[ 8.016643] pci 0000:01:00.0: supports D1 D2
10733 11:04:31.753310 <6>[ 8.016649] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10734 11:04:31.760103 <3>[ 8.016704] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10735 11:04:31.769644 <6>[ 8.024598] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10736 11:04:31.779660 <6>[ 8.026269] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10737 11:04:31.790259 <6>[ 8.026562] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10738 11:04:31.796412 <4>[ 8.028037] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10739 11:04:31.803211 <4>[ 8.028037] Fallback method does not support PEC.
10740 11:04:31.810229 <3>[ 8.031333] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 11:04:31.817298 <6>[ 8.033746] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10742 11:04:31.823736 <6>[ 8.033783] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10743 11:04:31.833876 <6>[ 8.033790] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10744 11:04:31.840026 <6>[ 8.033809] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10745 11:04:31.849983 <6>[ 8.033825] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10746 11:04:31.856644 <6>[ 8.033841] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10747 11:04:31.863161 <6>[ 8.033858] pci 0000:00:00.0: PCI bridge to [bus 01]
10748 11:04:31.870172 <6>[ 8.033866] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10749 11:04:31.876745 <6>[ 8.034011] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10750 11:04:31.883021 <6>[ 8.034927] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10751 11:04:31.889760 <6>[ 8.035211] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10752 11:04:31.893410 <6>[ 8.041284] videodev: Linux video capture interface: v2.00
10753 11:04:31.903049 <6>[ 8.042663] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10754 11:04:31.910350 <3>[ 8.047810] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10755 11:04:31.912837 <6>[ 8.077533] Bluetooth: Core ver 2.22
10756 11:04:31.923124 <5>[ 8.078459] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10757 11:04:31.929971 <3>[ 8.084091] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10758 11:04:31.936261 <6>[ 8.088722] NET: Registered PF_BLUETOOTH protocol family
10759 11:04:31.943272 <5>[ 8.091910] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10760 11:04:31.952788 <5>[ 8.092143] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10761 11:04:31.959264 <4>[ 8.092199] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10762 11:04:31.965874 <6>[ 8.092204] cfg80211: failed to load regulatory.db
10763 11:04:31.972945 <3>[ 8.095583] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10764 11:04:31.979736 <6>[ 8.103750] Bluetooth: HCI device and connection manager initialized
10765 11:04:31.989315 <3>[ 8.110072] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10766 11:04:31.992456 <6>[ 8.117509] Bluetooth: HCI socket layer initialized
10767 11:04:32.002769 <3>[ 8.117511] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10768 11:04:32.009054 <6>[ 8.119511] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10769 11:04:32.023338 <6>[ 8.120644] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10770 11:04:32.025708 <6>[ 8.120800] usbcore: registered new interface driver uvcvideo
10771 11:04:32.035712 <3>[ 8.124955] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10772 11:04:32.038885 <6>[ 8.132425] Bluetooth: L2CAP socket layer initialized
10773 11:04:32.049050 <3>[ 8.136942] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 11:04:32.052129 <6>[ 8.143834] Bluetooth: SCO socket layer initialized
10775 11:04:32.062307 <3>[ 8.151962] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 11:04:32.068875 <6>[ 8.171491] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10777 11:04:32.075549 <6>[ 8.179139] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10778 11:04:32.082391 <6>[ 8.179230] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10779 11:04:32.088560 <3>[ 8.179293] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 11:04:32.095771 <6>[ 8.197665] mt7921e 0000:01:00.0: ASIC revision: 79610010
10781 11:04:32.105254 <3>[ 8.201010] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10782 11:04:32.111849 <3>[ 8.201678] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10783 11:04:32.118365 <6>[ 8.232371] usbcore: registered new interface driver btusb
10784 11:04:32.128315 <4>[ 8.233002] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10785 11:04:32.134704 <3>[ 8.233014] Bluetooth: hci0: Failed to load firmware file (-2)
10786 11:04:32.141585 <3>[ 8.233019] Bluetooth: hci0: Failed to set up firmware (-2)
10787 11:04:32.151471 <4>[ 8.233024] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10788 11:04:32.157920 <3>[ 8.239920] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10789 11:04:32.168378 <3>[ 8.239923] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10790 11:04:32.174283 <6>[ 8.300394] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10791 11:04:32.178259 <6>[ 8.300394]
10792 11:04:32.184499 <3>[ 8.301523] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10793 11:04:32.194644 <6>[ 8.564683] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10794 11:04:32.197509 Begin: Loading essential drivers ... done.
10795 11:04:32.200845 Begin: Running /scripts/init-premount ... done.
10796 11:04:32.207600 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10797 11:04:32.217334 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10798 11:04:32.220556 Device /sys/class/net/eth0 found
10799 11:04:32.220635 done.
10800 11:04:32.259626 Begin: Waiting up to 180 secs for any network device to become available ... done.
10801 11:04:32.311731 IP-Config: eth0 hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10802 11:04:32.318653 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10803 11:04:32.325389 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10804 11:04:32.332036 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10805 11:04:32.338519 host : mt8192-asurada-spherion-r0-cbg-0
10806 11:04:32.345348 domain : lava-rack
10807 11:04:32.348535 rootserver: 192.168.201.1 rootpath:
10808 11:04:32.348612 filename :
10809 11:04:32.357062 done.
10810 11:04:32.364327 Begin: Running /scripts/nfs-bottom ... done.
10811 11:04:32.378685 Begin: Running /scripts/init-bottom ... done.
10812 11:04:33.699228 <6>[ 10.085072] NET: Registered PF_INET6 protocol family
10813 11:04:33.706506 <6>[ 10.092420] Segment Routing with IPv6
10814 11:04:33.709589 <6>[ 10.096415] In-situ OAM (IOAM) with IPv6
10815 11:04:33.876705 <30>[ 10.235867] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10816 11:04:33.883045 <30>[ 10.268979] systemd[1]: Detected architecture arm64.
10817 11:04:33.890820
10818 11:04:33.894194 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10819 11:04:33.894272
10820 11:04:33.920484 <30>[ 10.306702] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10821 11:04:34.981896 <30>[ 11.364544] systemd[1]: Queued start job for default target graphical.target.
10822 11:04:35.015705 <30>[ 11.398744] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10823 11:04:35.022826 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10824 11:04:35.044901 <30>[ 11.427595] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10825 11:04:35.054666 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10826 11:04:35.072514 <30>[ 11.455474] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10827 11:04:35.082772 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10828 11:04:35.101305 <30>[ 11.484013] systemd[1]: Created slice user.slice - User and Session Slice.
10829 11:04:35.107940 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10830 11:04:35.131338 <30>[ 11.510676] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10831 11:04:35.140799 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10832 11:04:35.159001 <30>[ 11.538053] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10833 11:04:35.165101 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10834 11:04:35.193273 <30>[ 11.566474] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10835 11:04:35.203312 <30>[ 11.586374] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10836 11:04:35.210141 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10837 11:04:35.227860 <30>[ 11.610193] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10838 11:04:35.237073 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10839 11:04:35.255371 <30>[ 11.638316] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10840 11:04:35.265556 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10841 11:04:35.280505 <30>[ 11.666314] systemd[1]: Reached target paths.target - Path Units.
10842 11:04:35.290270 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10843 11:04:35.307429 <30>[ 11.690178] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10844 11:04:35.314225 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10845 11:04:35.327952 <30>[ 11.713786] systemd[1]: Reached target slices.target - Slice Units.
10846 11:04:35.337981 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10847 11:04:35.351856 <30>[ 11.738292] systemd[1]: Reached target swap.target - Swaps.
10848 11:04:35.358836 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10849 11:04:35.379523 <30>[ 11.762310] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10850 11:04:35.389397 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10851 11:04:35.408168 <30>[ 11.790768] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10852 11:04:35.417810 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10853 11:04:35.437605 <30>[ 11.820568] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10854 11:04:35.447847 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10855 11:04:35.464786 <30>[ 11.847365] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10856 11:04:35.474756 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10857 11:04:35.491901 <30>[ 11.874437] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10858 11:04:35.498397 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10859 11:04:35.516350 <30>[ 11.899286] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10860 11:04:35.526238 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10861 11:04:35.546161 <30>[ 11.929056] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10862 11:04:35.556078 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10863 11:04:35.571315 <30>[ 11.954287] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10864 11:04:35.580952 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10865 11:04:35.635329 <30>[ 12.018054] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10866 11:04:35.642052 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10867 11:04:35.663413 <30>[ 12.046427] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10868 11:04:35.670131 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10869 11:04:35.739077 <30>[ 12.122204] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10870 11:04:35.745716 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10871 11:04:35.774346 <30>[ 12.150092] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10872 11:04:35.788599 <30>[ 12.171396] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10873 11:04:35.798891 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10874 11:04:35.820827 <30>[ 12.203252] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10875 11:04:35.826744 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10876 11:04:35.852800 <30>[ 12.235494] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10877 11:04:35.859458 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10878 11:04:35.884464 <30>[ 12.267152] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10879 11:04:35.894649 Startin<6>[ 12.276457] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10880 11:04:35.900900 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10881 11:04:35.923848 <30>[ 12.306961] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10882 11:04:35.930891 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10883 11:04:35.995594 <30>[ 12.378382] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10884 11:04:36.002417 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10885 11:04:36.028526 <30>[ 12.411456] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10886 11:04:36.038771 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop..<6>[ 12.426419] fuse: init (API version 7.37)
10887 11:04:36.038856 .
10888 11:04:36.083464 <30>[ 12.466535] systemd[1]: Starting systemd-journald.service - Journal Service...
10889 11:04:36.090569 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10890 11:04:36.122709 <30>[ 12.505727] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10891 11:04:36.129256 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10892 11:04:36.155210 <30>[ 12.535059] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10893 11:04:36.162312 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10894 11:04:36.183657 <30>[ 12.566787] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10895 11:04:36.193750 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10896 11:04:36.217455 <30>[ 12.599772] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10897 11:04:36.223709 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10898 11:04:36.252561 <3>[ 12.635317] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 11:04:36.259652 <30>[ 12.636285] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10900 11:04:36.269360 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10901 11:04:36.287587 <30>[ 12.670168] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10902 11:04:36.297341 <3>[ 12.670886] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 11:04:36.303834 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10904 11:04:36.327430 <30>[ 12.710021] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10905 11:04:36.333820 <3>[ 12.712463] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 11:04:36.344128 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10907 11:04:36.364198 <3>[ 12.747218] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 11:04:36.374573 <30>[ 12.757725] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10909 11:04:36.385026 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10910 11:04:36.403125 <3>[ 12.786149] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 11:04:36.409935 <30>[ 12.786688] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10912 11:04:36.420348 <30>[ 12.803002] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10913 11:04:36.430283 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10914 11:04:36.444956 <30>[ 12.830777] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10915 11:04:36.454962 <3>[ 12.833008] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 11:04:36.465023 <30>[ 12.838906] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10917 11:04:36.471528 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10918 11:04:36.485391 <3>[ 12.867936] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 11:04:36.495942 <30>[ 12.879188] systemd[1]: modprobe@drm.service: Deactivated successfully.
10920 11:04:36.503660 <30>[ 12.886724] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10921 11:04:36.517289 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 12.898118] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 11:04:36.520674 rm.service[0m - Load Kernel Module drm.
10923 11:04:36.540483 <30>[ 12.923233] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10924 11:04:36.551003 <30>[ 12.931517] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10925 11:04:36.557453 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10926 11:04:36.576053 <30>[ 12.958254] systemd[1]: Started systemd-journald.service - Journal Service.
10927 11:04:36.582125 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10928 11:04:36.600777 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10929 11:04:36.624185 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10930 11:04:36.650235 <4>[ 13.026466] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10931 11:04:36.660202 <3>[ 13.042153] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10932 11:04:36.666834 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10933 11:04:36.686663 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10934 11:04:36.704270 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10935 11:04:36.724335 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10936 11:04:36.745929 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10937 11:04:36.787628 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10938 11:04:36.812490 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10939 11:04:36.836514 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10940 11:04:36.861511 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10941 11:04:36.887898 Startin<46>[ 13.271418] systemd-journald[312]: Received client request to flush runtime journal.
10942 11:04:36.894501 g [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10943 11:04:36.923712 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10944 11:04:37.216228 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10945 11:04:37.235789 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10946 11:04:37.256002 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10947 11:04:37.391757 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10948 11:04:38.025374 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10949 11:04:38.068129 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10950 11:04:38.324330 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10951 11:04:38.390377 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10952 11:04:38.408049 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10953 11:04:38.427431 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10954 11:04:38.476719 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10955 11:04:38.505263 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10956 11:04:38.714331 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10957 11:04:38.771412 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10958 11:04:38.886658 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10959 11:04:38.998333 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10960 11:04:39.097988 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10961 11:04:39.126539 Starting [0;1;39msystemd-update-ut…rd System Boot/Sh<6>[ 15.511607] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10962 11:04:39.126634 utdown in UTMP...
10963 11:04:39.238461 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10964 11:04:39.249541 <4>[ 15.636050] power_supply_show_property: 4 callbacks suppressed
10965 11:04:39.259804 <3>[ 15.636082] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 11:04:39.296771 <3>[ 15.679807] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 11:04:39.306564 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10968 11:04:39.328941 <3>[ 15.712335] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 11:04:39.339613 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10970 11:04:39.361473 <3>[ 15.744970] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 11:04:39.390889 <3>[ 15.774388] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 11:04:39.397874 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10973 11:04:39.421852 <3>[ 15.804922] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 11:04:39.433830 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10975 11:04:39.459335 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Sync<3>[ 15.840306] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 11:04:39.459423 hronization.
10977 11:04:39.487375 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kb<3>[ 15.870290] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 11:04:39.487459 d_backlight.
10979 11:04:39.515835 <3>[ 15.899045] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 11:04:39.527403 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10981 11:04:39.544937 <3>[ 15.928452] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10982 11:04:39.555401 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10983 11:04:39.571083 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10984 11:04:39.587498 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10985 11:04:39.617822 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10986 11:04:39.637549 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10987 11:04:39.655271 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10988 11:04:39.673933 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10989 11:04:39.694830 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10990 11:04:39.711237 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10991 11:04:39.729367 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10992 11:04:39.747292 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10993 11:04:39.763175 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10994 11:04:39.779547 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10995 11:04:39.832242 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10996 11:04:39.884052 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10997 11:04:40.029475 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10998 11:04:40.054602 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10999 11:04:40.123983 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11000 11:04:40.144480 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11001 11:04:40.168590 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11002 11:04:40.235674 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11003 11:04:40.258884 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11004 11:04:40.276395 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11005 11:04:40.308816 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11006 11:04:40.330171 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11007 11:04:40.380648 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11008 11:04:40.401973 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11009 11:04:40.424747 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11010 11:04:40.468981 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11011 11:04:40.520503 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11012 11:04:40.616236
11013 11:04:40.619628 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11014 11:04:40.619703
11015 11:04:40.622975 debian-bookworm-arm64 login: root (automatic login)
11016 11:04:40.623054
11017 11:04:40.910319 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024 aarch64
11018 11:04:40.910756
11019 11:04:40.917095 The programs included with the Debian GNU/Linux system are free software;
11020 11:04:40.923800 the exact distribution terms for each program are described in the
11021 11:04:40.927142 individual files in /usr/share/doc/*/copyright.
11022 11:04:40.927528
11023 11:04:40.934078 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11024 11:04:40.937168 permitted by applicable law.
11025 11:04:42.003950 Matched prompt #10: / #
11027 11:04:42.004982 Setting prompt string to ['/ #']
11028 11:04:42.005402 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11030 11:04:42.006774 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11031 11:04:42.007248 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
11032 11:04:42.007574 Setting prompt string to ['/ #']
11033 11:04:42.007859 Forcing a shell prompt, looking for ['/ #']
11034 11:04:42.008139 Sending line: ''
11036 11:04:42.059237 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11037 11:04:42.059617 Waiting using forced prompt support (timeout 00:02:30)
11038 11:04:42.065261 / #
11039 11:04:42.066240 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11040 11:04:42.066718 start: 2.2.7 export-device-env (timeout 00:03:36) [common]
11041 11:04:42.067126 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14786822/extract-nfsrootfs-hzf441ob'"
11043 11:04:42.174671 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14786822/extract-nfsrootfs-hzf441ob'
11044 11:04:42.175543 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
11046 11:04:42.282950 / # export NFS_SERVER_IP='192.168.201.1'
11047 11:04:42.283813 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11048 11:04:42.284317 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
11049 11:04:42.284795 end: 2 depthcharge-action (duration 00:01:24) [common]
11050 11:04:42.285275 start: 3 lava-test-retry (timeout 00:07:52) [common]
11051 11:04:42.285723 start: 3.1 lava-test-shell (timeout 00:07:52) [common]
11052 11:04:42.286154 Using namespace: common
11053 11:04:42.286531 Sending line: '#'
11055 11:04:42.387897 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11056 11:04:42.393329 / # #
11057 11:04:42.394121 Using /lava-14786822
11058 11:04:42.394660 Sending line: 'export SHELL=/bin/bash'
11060 11:04:42.502201 / # export SHELL=/bin/bash
11061 11:04:42.502837 Sending line: '. /lava-14786822/environment'
11063 11:04:42.610493 / # . /lava-14786822/environment
11064 11:04:42.615164 Sending line: '/lava-14786822/bin/lava-test-runner /lava-14786822/0'
11066 11:04:42.716471 Test shell timeout: 10s (minimum of the action and connection timeout)
11067 11:04:42.721889 / # /lava-14786822/bin/lava-test-runner /lava-14786822/0
11068 11:04:42.976901 + export TESTRUN_ID=0_timesync-off
11069 11:04:42.980933 + TESTRUN_ID=0_timesync-off
11070 11:04:42.983550 + cd /lava-14786822/0/tests/0_timesync-off
11071 11:04:42.986960 ++ cat uuid
11072 11:04:42.994137 + UUID=14786822_1.6.2.3.1
11073 11:04:42.994530 + set +x
11074 11:04:43.000714 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14786822_1.6.2.3.1>
11075 11:04:43.001358 Received signal: <STARTRUN> 0_timesync-off 14786822_1.6.2.3.1
11076 11:04:43.001691 Starting test lava.0_timesync-off (14786822_1.6.2.3.1)
11077 11:04:43.002102 Skipping test definition patterns.
11078 11:04:43.004215 + systemctl stop systemd-timesyncd
11079 11:04:43.085603 + set +x
11080 11:04:43.088315 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14786822_1.6.2.3.1>
11081 11:04:43.088948 Received signal: <ENDRUN> 0_timesync-off 14786822_1.6.2.3.1
11082 11:04:43.089313 Ending use of test pattern.
11083 11:04:43.089598 Ending test lava.0_timesync-off (14786822_1.6.2.3.1), duration 0.09
11085 11:04:43.158430 + export TESTRUN_ID=1_kselftest-rtc
11086 11:04:43.161814 + TESTRUN_ID=1_kselftest-rtc
11087 11:04:43.164968 + cd /lava-14786822/0/tests/1_kselftest-rtc
11088 11:04:43.168164 ++ cat uuid
11089 11:04:43.171832 + UUID=14786822_1.6.2.3.5
11090 11:04:43.172221 + set +x
11091 11:04:43.178307 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 14786822_1.6.2.3.5>
11092 11:04:43.178968 Received signal: <STARTRUN> 1_kselftest-rtc 14786822_1.6.2.3.5
11093 11:04:43.179303 Starting test lava.1_kselftest-rtc (14786822_1.6.2.3.5)
11094 11:04:43.179644 Skipping test definition patterns.
11095 11:04:43.181843 + cd ./automated/linux/kselftest/
11096 11:04:43.207804 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
11097 11:04:43.245481 INFO: install_deps skipped
11098 11:04:43.737388 --2024-07-10 11:04:29-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz
11099 11:04:43.775392 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11100 11:04:43.908057 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11101 11:04:44.040780 HTTP request sent, awaiting response... 200 OK
11102 11:04:44.044050 Length: 1919896 (1.8M) [application/octet-stream]
11103 11:04:44.047354 Saving to: 'kselftest_armhf.tar.gz'
11104 11:04:44.047735
11105 11:04:44.048028
11106 11:04:44.305516 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11107 11:04:44.572261 kselftest_armhf.tar 2%[ ] 47.81K 181KB/s
11108 11:04:44.885489 kselftest_armhf.tar 11%[=> ] 217.50K 409KB/s
11109 11:04:45.023418 kselftest_armhf.tar 43%[=======> ] 822.71K 974KB/s
11110 11:04:45.029539 kselftest_armhf.tar 100%[===================>] 1.83M 1.86MB/s in 1.0s
11111 11:04:45.030128
11112 11:04:45.196570 2024-07-10 11:04:30 (1.86 MB/s) - 'kselftest_armhf.tar.gz' saved [1919896/1919896]
11113 11:04:45.196685
11114 11:04:51.290392 skiplist:
11115 11:04:51.293861 ========================================
11116 11:04:51.297097 ========================================
11117 11:04:51.332815 rtc:rtctest
11118 11:04:51.350499 ============== Tests to run ===============
11119 11:04:51.350613 rtc:rtctest
11120 11:04:51.353923 ===========End Tests to run ===============
11121 11:04:51.357069 shardfile-rtc pass
11122 11:04:51.444898 <12>[ 27.832888] kselftest: Running tests in rtc
11123 11:04:51.453235 TAP version 13
11124 11:04:51.465908 1..1
11125 11:04:51.493500 # selftests: rtc: rtctest
11126 11:04:51.931126 # TAP version 13
11127 11:04:51.931273 # 1..8
11128 11:04:51.934613 # # Starting 8 tests from 2 test cases.
11129 11:04:51.937383 # # RUN rtc.date_read ...
11130 11:04:51.944025 # # rtctest.c:49:date_read:Current RTC date/time is 10/07/2024 11:04:37.
11131 11:04:51.947790 # # OK rtc.date_read
11132 11:04:51.950653 # ok 1 rtc.date_read
11133 11:04:51.954434 # # RUN rtc.date_read_loop ...
11134 11:04:51.964297 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11135 11:05:01.573805 <6>[ 37.966115] vpu: disabling
11136 11:05:01.577259 <6>[ 37.969188] vproc2: disabling
11137 11:05:01.580571 <6>[ 37.972483] vproc1: disabling
11138 11:05:01.583744 <6>[ 37.976232] vaud18: disabling
11139 11:05:01.591741 <6>[ 37.980541] vsram_others: disabling
11140 11:05:01.594751 <6>[ 37.984690] va09: disabling
11141 11:05:01.598306 <6>[ 37.988039] vsram_md: disabling
11142 11:05:01.601258 <6>[ 37.991788] Vgpu: disabling
11143 11:05:22.280551 # # rtctest.c:115:date_read_loop:Performed 2657 RTC time reads.
11144 11:05:22.283973 # # OK rtc.date_read_loop
11145 11:05:22.287354 # ok 2 rtc.date_read_loop
11146 11:05:22.290452 # # RUN rtc.uie_read ...
11147 11:05:25.262000 # # OK rtc.uie_read
11148 11:05:25.265219 # ok 3 rtc.uie_read
11149 11:05:25.268100 # # RUN rtc.uie_select ...
11150 11:05:28.261497 # # OK rtc.uie_select
11151 11:05:28.264412 # ok 4 rtc.uie_select
11152 11:05:28.268008 # # RUN rtc.alarm_alm_set ...
11153 11:05:28.274802 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 11:05:17.
11154 11:05:28.278162 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11155 11:05:28.284959 # # alarm_alm_set: Test terminated by assertion
11156 11:05:28.287462 # # FAIL rtc.alarm_alm_set
11157 11:05:28.287537 # not ok 5 rtc.alarm_alm_set
11158 11:05:28.294183 # # RUN rtc.alarm_wkalm_set ...
11159 11:05:28.300763 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 10/07/2024 11:05:17.
11160 11:05:31.264212 # # OK rtc.alarm_wkalm_set
11161 11:05:31.264342 # ok 6 rtc.alarm_wkalm_set
11162 11:05:31.270525 # # RUN rtc.alarm_alm_set_minute ...
11163 11:05:31.274023 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 11:06:00.
11164 11:05:31.280779 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11165 11:05:31.287176 # # alarm_alm_set_minute: Test terminated by assertion
11166 11:05:31.290677 # # FAIL rtc.alarm_alm_set_minute
11167 11:05:31.293998 # not ok 7 rtc.alarm_alm_set_minute
11168 11:05:31.297017 # # RUN rtc.alarm_wkalm_set_minute ...
11169 11:05:31.304182 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 10/07/2024 11:06:00.
11170 11:06:14.259731 # # OK rtc.alarm_wkalm_set_minute
11171 11:06:14.263052 # ok 8 rtc.alarm_wkalm_set_minute
11172 11:06:14.266476 # # FAILED: 6 / 8 tests passed.
11173 11:06:14.269905 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11174 11:06:14.273087 not ok 1 selftests: rtc: rtctest # exit=1
11175 11:06:15.769595 rtc_rtctest_rtc_date_read pass
11176 11:06:15.772922 rtc_rtctest_rtc_date_read_loop pass
11177 11:06:15.776136 rtc_rtctest_rtc_uie_read pass
11178 11:06:15.779639 rtc_rtctest_rtc_uie_select pass
11179 11:06:15.782899 rtc_rtctest_rtc_alarm_alm_set fail
11180 11:06:15.786132 rtc_rtctest_rtc_alarm_wkalm_set pass
11181 11:06:15.790395 rtc_rtctest_rtc_alarm_alm_set_minute fail
11182 11:06:15.792876 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11183 11:06:15.796585 rtc_rtctest fail
11184 11:06:15.847035 + ../../utils/send-to-lava.sh ./output/result.txt
11185 11:06:15.925482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11186 11:06:15.925770 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11188 11:06:15.978162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11189 11:06:15.978437 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11191 11:06:16.034645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11192 11:06:16.034913 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11194 11:06:16.084568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11195 11:06:16.084834 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11197 11:06:16.134207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11198 11:06:16.134476 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11200 11:06:16.180969 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11202 11:06:16.183841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11203 11:06:16.227825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11204 11:06:16.228096 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11206 11:06:16.264010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11207 11:06:16.264311 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11209 11:06:16.316855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11210 11:06:16.317502 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11212 11:06:16.372808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11213 11:06:16.373233 + set +x
11214 11:06:16.373812 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11216 11:06:16.379498 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 14786822_1.6.2.3.5>
11217 11:06:16.379888 <LAVA_TEST_RUNNER EXIT>
11218 11:06:16.380419 Received signal: <ENDRUN> 1_kselftest-rtc 14786822_1.6.2.3.5
11219 11:06:16.380739 Ending use of test pattern.
11220 11:06:16.381011 Ending test lava.1_kselftest-rtc (14786822_1.6.2.3.5), duration 93.20
11222 11:06:16.381968 ok: lava_test_shell seems to have completed
11223 11:06:16.382652 shardfile-rtc: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest: fail
11224 11:06:16.383124 end: 3.1 lava-test-shell (duration 00:01:34) [common]
11225 11:06:16.383505 end: 3 lava-test-retry (duration 00:01:34) [common]
11226 11:06:16.383901 start: 4 finalize (timeout 00:06:18) [common]
11227 11:06:16.384289 start: 4.1 power-off (timeout 00:00:30) [common]
11228 11:06:16.384875 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
11229 11:06:18.500849 >> Command sent successfully.
11230 11:06:18.504244 Returned 0 in 2 seconds
11231 11:06:18.504390 end: 4.1 power-off (duration 00:00:02) [common]
11233 11:06:18.504591 start: 4.2 read-feedback (timeout 00:06:16) [common]
11234 11:06:18.504739 Listened to connection for namespace 'common' for up to 1s
11235 11:06:18.505003 Listened to connection for namespace 'common' for up to 1s
11236 11:06:19.505752 Finalising connection for namespace 'common'
11237 11:06:19.505898 Disconnecting from shell: Finalise
11238 11:06:19.505975 / #
11239 11:06:19.606262 end: 4.2 read-feedback (duration 00:00:01) [common]
11240 11:06:19.606411 end: 4 finalize (duration 00:00:03) [common]
11241 11:06:19.606520 Cleaning after the job
11242 11:06:19.606619 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786822/tftp-deploy-6460t7t3/ramdisk
11243 11:06:19.608895 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786822/tftp-deploy-6460t7t3/kernel
11244 11:06:19.620146 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786822/tftp-deploy-6460t7t3/dtb
11245 11:06:19.620317 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786822/tftp-deploy-6460t7t3/nfsrootfs
11246 11:06:19.688381 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786822/tftp-deploy-6460t7t3/modules
11247 11:06:19.695208 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14786822
11248 11:06:20.323409 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14786822
11249 11:06:20.323587 Job finished correctly