Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 1
- Kernel Errors: 40
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 85
1 11:09:30.701805 lava-dispatcher, installed at version: 2024.05
2 11:09:30.702020 start: 0 validate
3 11:09:30.702145 Start time: 2024-07-10 11:09:30.702139+00:00 (UTC)
4 11:09:30.702281 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:09:30.702435 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 11:09:30.972220 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:09:30.972979 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:09:36.663512 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:09:36.663707 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 11:09:36.929240 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:09:36.929391 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
12 11:09:36.931729 validate duration: 6.23
14 11:09:36.931979 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:09:36.932096 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:09:36.932217 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:09:36.932417 Not decompressing ramdisk as can be used compressed.
18 11:09:36.932529 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 11:09:36.932612 saving as /var/lib/lava/dispatcher/tmp/14786846/tftp-deploy-qqigt0vp/ramdisk/rootfs.cpio.gz
20 11:09:36.932686 total size: 28105535 (26 MB)
21 11:09:36.933864 progress 0 % (0 MB)
22 11:09:36.942202 progress 5 % (1 MB)
23 11:09:36.950469 progress 10 % (2 MB)
24 11:09:36.958453 progress 15 % (4 MB)
25 11:09:36.966053 progress 20 % (5 MB)
26 11:09:36.973641 progress 25 % (6 MB)
27 11:09:36.981315 progress 30 % (8 MB)
28 11:09:36.988912 progress 35 % (9 MB)
29 11:09:36.996511 progress 40 % (10 MB)
30 11:09:37.003940 progress 45 % (12 MB)
31 11:09:37.011534 progress 50 % (13 MB)
32 11:09:37.019112 progress 55 % (14 MB)
33 11:09:37.026768 progress 60 % (16 MB)
34 11:09:37.034311 progress 65 % (17 MB)
35 11:09:37.041905 progress 70 % (18 MB)
36 11:09:37.049500 progress 75 % (20 MB)
37 11:09:37.057078 progress 80 % (21 MB)
38 11:09:37.064580 progress 85 % (22 MB)
39 11:09:37.071971 progress 90 % (24 MB)
40 11:09:37.079423 progress 95 % (25 MB)
41 11:09:37.086844 progress 100 % (26 MB)
42 11:09:37.087067 26 MB downloaded in 0.15 s (173.63 MB/s)
43 11:09:37.087231 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:09:37.087476 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:09:37.087562 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:09:37.087645 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:09:37.087792 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
49 11:09:37.087859 saving as /var/lib/lava/dispatcher/tmp/14786846/tftp-deploy-qqigt0vp/kernel/Image
50 11:09:37.087917 total size: 54813184 (52 MB)
51 11:09:37.087975 No compression specified
52 11:09:37.089175 progress 0 % (0 MB)
53 11:09:37.103763 progress 5 % (2 MB)
54 11:09:37.118588 progress 10 % (5 MB)
55 11:09:37.133227 progress 15 % (7 MB)
56 11:09:37.147922 progress 20 % (10 MB)
57 11:09:37.162712 progress 25 % (13 MB)
58 11:09:37.177177 progress 30 % (15 MB)
59 11:09:37.191876 progress 35 % (18 MB)
60 11:09:37.206571 progress 40 % (20 MB)
61 11:09:37.221279 progress 45 % (23 MB)
62 11:09:37.236061 progress 50 % (26 MB)
63 11:09:37.251019 progress 55 % (28 MB)
64 11:09:37.265529 progress 60 % (31 MB)
65 11:09:37.280196 progress 65 % (34 MB)
66 11:09:37.294792 progress 70 % (36 MB)
67 11:09:37.309475 progress 75 % (39 MB)
68 11:09:37.324300 progress 80 % (41 MB)
69 11:09:37.339028 progress 85 % (44 MB)
70 11:09:37.353916 progress 90 % (47 MB)
71 11:09:37.368727 progress 95 % (49 MB)
72 11:09:37.383188 progress 100 % (52 MB)
73 11:09:37.383443 52 MB downloaded in 0.30 s (176.89 MB/s)
74 11:09:37.383605 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:09:37.383835 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:09:37.383923 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:09:37.384006 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:09:37.384146 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
80 11:09:37.384213 saving as /var/lib/lava/dispatcher/tmp/14786846/tftp-deploy-qqigt0vp/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
81 11:09:37.384270 total size: 57695 (0 MB)
82 11:09:37.384327 No compression specified
83 11:09:37.385376 progress 56 % (0 MB)
84 11:09:37.385655 progress 100 % (0 MB)
85 11:09:37.385862 0 MB downloaded in 0.00 s (34.62 MB/s)
86 11:09:37.385984 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:09:37.386204 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:09:37.386286 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:09:37.386368 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:09:37.386482 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
92 11:09:37.386548 saving as /var/lib/lava/dispatcher/tmp/14786846/tftp-deploy-qqigt0vp/modules/modules.tar
93 11:09:37.386605 total size: 8607984 (8 MB)
94 11:09:37.386663 Using unxz to decompress xz
95 11:09:37.388146 progress 0 % (0 MB)
96 11:09:37.410593 progress 5 % (0 MB)
97 11:09:37.437783 progress 10 % (0 MB)
98 11:09:37.464388 progress 15 % (1 MB)
99 11:09:37.491005 progress 20 % (1 MB)
100 11:09:37.517289 progress 25 % (2 MB)
101 11:09:37.543348 progress 30 % (2 MB)
102 11:09:37.568522 progress 35 % (2 MB)
103 11:09:37.598600 progress 40 % (3 MB)
104 11:09:37.626105 progress 45 % (3 MB)
105 11:09:37.653312 progress 50 % (4 MB)
106 11:09:37.680824 progress 55 % (4 MB)
107 11:09:37.707939 progress 60 % (4 MB)
108 11:09:37.734080 progress 65 % (5 MB)
109 11:09:37.762187 progress 70 % (5 MB)
110 11:09:37.792143 progress 75 % (6 MB)
111 11:09:37.822379 progress 80 % (6 MB)
112 11:09:37.848341 progress 85 % (7 MB)
113 11:09:37.873973 progress 90 % (7 MB)
114 11:09:37.899875 progress 95 % (7 MB)
115 11:09:37.924560 progress 100 % (8 MB)
116 11:09:37.930685 8 MB downloaded in 0.54 s (15.09 MB/s)
117 11:09:37.930864 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:09:37.931113 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:09:37.931201 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:09:37.931285 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:09:37.931361 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:09:37.931438 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:09:37.931614 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4
125 11:09:37.931743 makedir: /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin
126 11:09:37.931843 makedir: /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/tests
127 11:09:37.931939 makedir: /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/results
128 11:09:37.932030 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-add-keys
129 11:09:37.932168 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-add-sources
130 11:09:37.932299 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-background-process-start
131 11:09:37.932425 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-background-process-stop
132 11:09:37.932596 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-common-functions
133 11:09:37.932754 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-echo-ipv4
134 11:09:37.932915 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-install-packages
135 11:09:37.933040 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-installed-packages
136 11:09:37.933162 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-os-build
137 11:09:37.933290 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-probe-channel
138 11:09:37.933412 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-probe-ip
139 11:09:37.933535 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-target-ip
140 11:09:37.933656 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-target-mac
141 11:09:37.933776 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-target-storage
142 11:09:37.933906 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-test-case
143 11:09:37.934028 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-test-event
144 11:09:37.934149 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-test-feedback
145 11:09:37.934271 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-test-raise
146 11:09:37.934399 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-test-reference
147 11:09:37.934518 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-test-runner
148 11:09:37.934640 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-test-set
149 11:09:37.934760 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-test-shell
150 11:09:37.934882 Updating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-install-packages (oe)
151 11:09:37.935033 Updating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/bin/lava-installed-packages (oe)
152 11:09:37.935152 Creating /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/environment
153 11:09:37.935250 LAVA metadata
154 11:09:37.935319 - LAVA_JOB_ID=14786846
155 11:09:37.935380 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:09:37.935476 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:09:37.935536 skipped lava-vland-overlay
158 11:09:37.935607 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:09:37.935683 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:09:37.935742 skipped lava-multinode-overlay
161 11:09:37.935811 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:09:37.935894 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:09:37.935962 Loading test definitions
164 11:09:37.936045 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:09:37.936112 Using /lava-14786846 at stage 0
166 11:09:37.936428 uuid=14786846_1.5.2.3.1 testdef=None
167 11:09:37.936520 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:09:37.936604 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:09:37.937063 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:09:37.937276 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:09:37.937880 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:09:37.938105 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:09:37.938695 runner path: /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/0/tests/0_v4l2-compliance-uvc test_uuid 14786846_1.5.2.3.1
176 11:09:37.938851 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:09:37.939056 Creating lava-test-runner.conf files
179 11:09:37.939115 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14786846/lava-overlay-flpn51s4/lava-14786846/0 for stage 0
180 11:09:37.939200 - 0_v4l2-compliance-uvc
181 11:09:37.939296 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:09:37.939377 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:09:37.946020 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:09:37.946123 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:09:37.946208 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:09:37.946290 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:09:37.946372 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:09:38.818465 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:09:38.818624 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:09:38.818707 extracting modules file /var/lib/lava/dispatcher/tmp/14786846/tftp-deploy-qqigt0vp/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786846/extract-overlay-ramdisk-hmn_qrpi/ramdisk
191 11:09:39.072831 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:09:39.072982 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 11:09:39.073074 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786846/compress-overlay-6r34lx6h/overlay-1.5.2.4.tar.gz to ramdisk
194 11:09:39.073141 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786846/compress-overlay-6r34lx6h/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14786846/extract-overlay-ramdisk-hmn_qrpi/ramdisk
195 11:09:39.080100 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:09:39.080204 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 11:09:39.080293 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:09:39.080382 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 11:09:39.080495 Building ramdisk /var/lib/lava/dispatcher/tmp/14786846/extract-overlay-ramdisk-hmn_qrpi/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14786846/extract-overlay-ramdisk-hmn_qrpi/ramdisk
200 11:09:39.729777 >> 275391 blocks
201 11:09:44.396968 rename /var/lib/lava/dispatcher/tmp/14786846/extract-overlay-ramdisk-hmn_qrpi/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14786846/tftp-deploy-qqigt0vp/ramdisk/ramdisk.cpio.gz
202 11:09:44.397149 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 11:09:44.397245 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 11:09:44.397330 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 11:09:44.397413 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14786846/tftp-deploy-qqigt0vp/kernel/Image']
206 11:09:59.542922 Returned 0 in 15 seconds
207 11:09:59.543116 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14786846/tftp-deploy-qqigt0vp/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14786846/tftp-deploy-qqigt0vp/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14786846/tftp-deploy-qqigt0vp/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14786846/tftp-deploy-qqigt0vp/kernel/image.itb
208 11:10:00.193573 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:10:00.193715 output: Created: Wed Jul 10 12:10:00 2024
210 11:10:00.193809 output: Image 0 (kernel-1)
211 11:10:00.193891 output: Description:
212 11:10:00.193970 output: Created: Wed Jul 10 12:10:00 2024
213 11:10:00.194048 output: Type: Kernel Image
214 11:10:00.194125 output: Compression: lzma compressed
215 11:10:00.194222 output: Data Size: 13116259 Bytes = 12808.85 KiB = 12.51 MiB
216 11:10:00.194319 output: Architecture: AArch64
217 11:10:00.194414 output: OS: Linux
218 11:10:00.194508 output: Load Address: 0x00000000
219 11:10:00.194602 output: Entry Point: 0x00000000
220 11:10:00.194696 output: Hash algo: crc32
221 11:10:00.194789 output: Hash value: 9bb85fb9
222 11:10:00.194883 output: Image 1 (fdt-1)
223 11:10:00.194976 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
224 11:10:00.195070 output: Created: Wed Jul 10 12:10:00 2024
225 11:10:00.195164 output: Type: Flat Device Tree
226 11:10:00.195257 output: Compression: uncompressed
227 11:10:00.195351 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
228 11:10:00.195444 output: Architecture: AArch64
229 11:10:00.195538 output: Hash algo: crc32
230 11:10:00.195631 output: Hash value: a9713552
231 11:10:00.195724 output: Image 2 (ramdisk-1)
232 11:10:00.195816 output: Description: unavailable
233 11:10:00.195908 output: Created: Wed Jul 10 12:10:00 2024
234 11:10:00.196001 output: Type: RAMDisk Image
235 11:10:00.196094 output: Compression: uncompressed
236 11:10:00.196186 output: Data Size: 41182229 Bytes = 40217.02 KiB = 39.27 MiB
237 11:10:00.196279 output: Architecture: AArch64
238 11:10:00.196372 output: OS: Linux
239 11:10:00.196475 output: Load Address: unavailable
240 11:10:00.196569 output: Entry Point: unavailable
241 11:10:00.196662 output: Hash algo: crc32
242 11:10:00.196755 output: Hash value: 113b4d4e
243 11:10:00.196847 output: Default Configuration: 'conf-1'
244 11:10:00.196940 output: Configuration 0 (conf-1)
245 11:10:00.197033 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
246 11:10:00.197126 output: Kernel: kernel-1
247 11:10:00.197218 output: Init Ramdisk: ramdisk-1
248 11:10:00.197312 output: FDT: fdt-1
249 11:10:00.197405 output: Loadables: kernel-1
250 11:10:00.197497 output:
251 11:10:00.197657 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 11:10:00.197779 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 11:10:00.197904 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 11:10:00.198027 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 11:10:00.198126 No LXC device requested
256 11:10:00.198249 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:10:00.198370 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 11:10:00.198487 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:10:00.198583 Checking files for TFTP limit of 4294967296 bytes.
260 11:10:00.199147 end: 1 tftp-deploy (duration 00:00:23) [common]
261 11:10:00.199280 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:10:00.199408 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:10:00.199558 substitutions:
264 11:10:00.199658 - {DTB}: 14786846/tftp-deploy-qqigt0vp/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
265 11:10:00.199760 - {INITRD}: 14786846/tftp-deploy-qqigt0vp/ramdisk/ramdisk.cpio.gz
266 11:10:00.199867 - {KERNEL}: 14786846/tftp-deploy-qqigt0vp/kernel/Image
267 11:10:00.199947 - {LAVA_MAC}: None
268 11:10:00.200025 - {PRESEED_CONFIG}: None
269 11:10:00.200101 - {PRESEED_LOCAL}: None
270 11:10:00.200196 - {RAMDISK}: 14786846/tftp-deploy-qqigt0vp/ramdisk/ramdisk.cpio.gz
271 11:10:00.200305 - {ROOT_PART}: None
272 11:10:00.200403 - {ROOT}: None
273 11:10:00.200509 - {SERVER_IP}: 192.168.201.1
274 11:10:00.200604 - {TEE}: None
275 11:10:00.200699 Parsed boot commands:
276 11:10:00.200792 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:10:00.201016 Parsed boot commands: tftpboot 192.168.201.1 14786846/tftp-deploy-qqigt0vp/kernel/image.itb 14786846/tftp-deploy-qqigt0vp/kernel/cmdline
278 11:10:00.201143 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:10:00.201268 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:10:00.201390 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:10:00.201509 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:10:00.201605 Not connected, no need to disconnect.
283 11:10:00.201723 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:10:00.201842 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:10:00.201938 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-0'
286 11:10:00.205093 Setting prompt string to ['lava-test: # ']
287 11:10:00.205474 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:10:00.205619 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:10:00.205729 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:10:00.205833 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:10:00.206049 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-0', '--port=1', '--command=reboot']
292 11:10:09.341724 >> Command sent successfully.
293 11:10:09.345068 Returned 0 in 9 seconds
294 11:10:09.345227 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 11:10:09.345448 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 11:10:09.345540 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 11:10:09.345614 Setting prompt string to 'Starting depthcharge on Juniper...'
299 11:10:09.345675 Changing prompt to 'Starting depthcharge on Juniper...'
300 11:10:09.345742 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
301 11:10:09.346108 [Enter `^Ec?' for help]
302 11:10:15.955833 [DL] 00000000 00000000 010701
303 11:10:15.960709
304 11:10:15.961153
305 11:10:15.961437 F0: 102B 0000
306 11:10:15.961715
307 11:10:15.961994 F3: 1006 0033 [0200]
308 11:10:15.964314
309 11:10:15.964741 F3: 4001 00E0 [0200]
310 11:10:15.965042
311 11:10:15.965320 F3: 0000 0000
312 11:10:15.967245
313 11:10:15.967621 V0: 0000 0000 [0001]
314 11:10:15.967917
315 11:10:15.968186 00: 1027 0002
316 11:10:15.968490
317 11:10:15.970704 01: 0000 0000
318 11:10:15.971089
319 11:10:15.971449 BP: 0C00 0251 [0000]
320 11:10:15.971730
321 11:10:15.974212 G0: 1182 0000
322 11:10:15.974590
323 11:10:15.974885 EC: 0004 0000 [0001]
324 11:10:15.975160
325 11:10:15.977699 S7: 0000 0000 [0000]
326 11:10:15.978115
327 11:10:15.978562 CC: 0000 0000 [0001]
328 11:10:15.980753
329 11:10:15.981151 T0: 0000 00DB [000F]
330 11:10:15.981550
331 11:10:15.981921 Jump to BL
332 11:10:15.982286
333 11:10:16.016704
334 11:10:16.017099
335 11:10:16.023309 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
336 11:10:16.026603 ARM64: Exception handlers installed.
337 11:10:16.030136 ARM64: Testing exception
338 11:10:16.033331 ARM64: Done test exception
339 11:10:16.037898 WDT: Last reset was cold boot
340 11:10:16.038385 SPI0(PAD0) initialized at 992727 Hz
341 11:10:16.044525 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
342 11:10:16.044942 Manufacturer: ef
343 11:10:16.051047 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
344 11:10:16.063731 Probing TPM: . done!
345 11:10:16.064119 TPM ready after 0 ms
346 11:10:16.070061 Connected to device vid:did:rid of 1ae0:0028:00
347 11:10:16.077090 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
348 11:10:16.111961 Initialized TPM device CR50 revision 0
349 11:10:16.124584 tlcl_send_startup: Startup return code is 0
350 11:10:16.124998 TPM: setup succeeded
351 11:10:16.133405 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
352 11:10:16.136419 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
353 11:10:16.139790 in-header: 03 19 00 00 08 00 00 00
354 11:10:16.143237 in-data: a2 e0 47 00 13 00 00 00
355 11:10:16.146441 Chrome EC: UHEPI supported
356 11:10:16.153596 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
357 11:10:16.156410 in-header: 03 a1 00 00 08 00 00 00
358 11:10:16.160351 in-data: 84 60 60 10 00 00 00 00
359 11:10:16.160474 Phase 1
360 11:10:16.163793 FMAP: area GBB found @ 3f5000 (12032 bytes)
361 11:10:16.170267 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
362 11:10:16.176979 VB2:vb2_check_recovery() Recovery was requested manually
363 11:10:16.179961 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
364 11:10:16.185906 Recovery requested (1009000e)
365 11:10:16.191778 tlcl_extend: response is 0
366 11:10:16.200156 tlcl_extend: response is 0
367 11:10:16.225196
368 11:10:16.225312
369 11:10:16.231993 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
370 11:10:16.235799 ARM64: Exception handlers installed.
371 11:10:16.238776 ARM64: Testing exception
372 11:10:16.241852 ARM64: Done test exception
373 11:10:16.257101 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0xc268, sec=0x2017
374 11:10:16.263885 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
375 11:10:16.267171 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
376 11:10:16.275431 [RTC]rtc_get_frequency_meter,134: input=0xf, output=915
377 11:10:16.282731 [RTC]rtc_get_frequency_meter,134: input=0x7, output=780
378 11:10:16.289768 [RTC]rtc_get_frequency_meter,134: input=0xb, output=845
379 11:10:16.296604 [RTC]rtc_get_frequency_meter,134: input=0x9, output=816
380 11:10:16.303118 [RTC]rtc_get_frequency_meter,134: input=0x8, output=797
381 11:10:16.310434 [RTC]rtc_get_frequency_meter,134: input=0x7, output=779
382 11:10:16.316862 [RTC]rtc_get_frequency_meter,134: input=0x8, output=797
383 11:10:16.320474 [RTC]rtc_osc_init,208: EOSC32 cali val = 0xc268
384 11:10:16.327386 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
385 11:10:16.330675 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
386 11:10:16.333952 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
387 11:10:16.337180 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
388 11:10:16.340400 in-header: 03 19 00 00 08 00 00 00
389 11:10:16.343896 in-data: a2 e0 47 00 13 00 00 00
390 11:10:16.347097 Chrome EC: UHEPI supported
391 11:10:16.354023 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
392 11:10:16.357393 in-header: 03 a1 00 00 08 00 00 00
393 11:10:16.360500 in-data: 84 60 60 10 00 00 00 00
394 11:10:16.363917 Skip loading cached calibration data
395 11:10:16.370456 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
396 11:10:16.373966 in-header: 03 a1 00 00 08 00 00 00
397 11:10:16.377256 in-data: 84 60 60 10 00 00 00 00
398 11:10:16.383841 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
399 11:10:16.387132 in-header: 03 a1 00 00 08 00 00 00
400 11:10:16.390594 in-data: 84 60 60 10 00 00 00 00
401 11:10:16.394134 ADC[3]: Raw value=216571 ID=1
402 11:10:16.394212 Manufacturer: ef
403 11:10:16.400820 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
404 11:10:16.404228 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
405 11:10:16.407583 CBFS @ 21000 size 3d4000
406 11:10:16.411169 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
407 11:10:16.417309 CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB'
408 11:10:16.420599 CBFS: Found @ offset 3c700 size 44
409 11:10:16.420733 DRAM-K: Full Calibration
410 11:10:16.427572 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 11:10:16.427772 CBFS @ 21000 size 3d4000
412 11:10:16.434447 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
413 11:10:16.438015 CBFS: Locating 'fallback/dram'
414 11:10:16.440894 CBFS: Found @ offset 24b00 size 12268
415 11:10:16.468612 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps
416 11:10:16.472321 ddr_geometry: 1, config: 0x0
417 11:10:16.475221 header.status = 0x0
418 11:10:16.478588 header.magic = 0x44524d4b (expected: 0x44524d4b)
419 11:10:16.481714 header.version = 0x5 (expected: 0x5)
420 11:10:16.485324 header.size = 0x8f0 (expected: 0x8f0)
421 11:10:16.485729 header.config = 0x0
422 11:10:16.488669 header.flags = 0x0
423 11:10:16.489183 header.checksum = 0x0
424 11:10:16.495380 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
425 11:10:16.502000 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
426 11:10:16.505793 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
427 11:10:16.508812 ddr_geometry:1
428 11:10:16.509236 [EMI] new MDL number = 1
429 11:10:16.511868 dram_cbt_mode_extern: 0
430 11:10:16.515858 dram_cbt_mode [RK0]: 0, [RK1]: 0
431 11:10:16.522381 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
432 11:10:16.522900
433 11:10:16.523299
434 11:10:16.525818 [Bianco] ETT version 0.0.0.1
435 11:10:16.529037 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
436 11:10:16.529439
437 11:10:16.532401 vSetVcoreByFreq with vcore:762500, freq=1600
438 11:10:16.532972
439 11:10:16.535239 [DramcInit]
440 11:10:16.535761 AutoRefreshCKEOff AutoREF OFF
441 11:10:16.538928 DDRPhyPLLSetting-CKEOFF
442 11:10:16.541898 DDRPhyPLLSetting-CKEON
443 11:10:16.542294
444 11:10:16.542591 Enable WDQS
445 11:10:16.545834 [ModeRegInit_LP4] CH0 RK0
446 11:10:16.549581 Write Rank0 MR13 =0x18
447 11:10:16.549966 Write Rank0 MR12 =0x5d
448 11:10:16.552878 Write Rank0 MR1 =0x56
449 11:10:16.556188 Write Rank0 MR2 =0x1a
450 11:10:16.556608 Write Rank0 MR11 =0x0
451 11:10:16.559575 Write Rank0 MR22 =0x38
452 11:10:16.559962 Write Rank0 MR14 =0x5d
453 11:10:16.562802 Write Rank0 MR3 =0x30
454 11:10:16.566175 Write Rank0 MR13 =0x58
455 11:10:16.566557 Write Rank0 MR12 =0x5d
456 11:10:16.569398 Write Rank0 MR1 =0x56
457 11:10:16.569784 Write Rank0 MR2 =0x2d
458 11:10:16.572894 Write Rank0 MR11 =0x23
459 11:10:16.576211 Write Rank0 MR22 =0x34
460 11:10:16.576637 Write Rank0 MR14 =0x10
461 11:10:16.579572 Write Rank0 MR3 =0x30
462 11:10:16.579958 Write Rank0 MR13 =0xd8
463 11:10:16.582973 [ModeRegInit_LP4] CH0 RK1
464 11:10:16.585974 Write Rank1 MR13 =0x18
465 11:10:16.586362 Write Rank1 MR12 =0x5d
466 11:10:16.589618 Write Rank1 MR1 =0x56
467 11:10:16.593087 Write Rank1 MR2 =0x1a
468 11:10:16.593468 Write Rank1 MR11 =0x0
469 11:10:16.596078 Write Rank1 MR22 =0x38
470 11:10:16.596493 Write Rank1 MR14 =0x5d
471 11:10:16.599591 Write Rank1 MR3 =0x30
472 11:10:16.602705 Write Rank1 MR13 =0x58
473 11:10:16.603112 Write Rank1 MR12 =0x5d
474 11:10:16.606169 Write Rank1 MR1 =0x56
475 11:10:16.606555 Write Rank1 MR2 =0x2d
476 11:10:16.609594 Write Rank1 MR11 =0x23
477 11:10:16.613137 Write Rank1 MR22 =0x34
478 11:10:16.613650 Write Rank1 MR14 =0x10
479 11:10:16.616274 Write Rank1 MR3 =0x30
480 11:10:16.619481 Write Rank1 MR13 =0xd8
481 11:10:16.619862 [ModeRegInit_LP4] CH1 RK0
482 11:10:16.622719 Write Rank0 MR13 =0x18
483 11:10:16.623133 Write Rank0 MR12 =0x5d
484 11:10:16.626591 Write Rank0 MR1 =0x56
485 11:10:16.629832 Write Rank0 MR2 =0x1a
486 11:10:16.630217 Write Rank0 MR11 =0x0
487 11:10:16.632988 Write Rank0 MR22 =0x38
488 11:10:16.633433 Write Rank0 MR14 =0x5d
489 11:10:16.636529 Write Rank0 MR3 =0x30
490 11:10:16.639857 Write Rank0 MR13 =0x58
491 11:10:16.640239 Write Rank0 MR12 =0x5d
492 11:10:16.643166 Write Rank0 MR1 =0x56
493 11:10:16.643547 Write Rank0 MR2 =0x2d
494 11:10:16.646139 Write Rank0 MR11 =0x23
495 11:10:16.649620 Write Rank0 MR22 =0x34
496 11:10:16.650006 Write Rank0 MR14 =0x10
497 11:10:16.653179 Write Rank0 MR3 =0x30
498 11:10:16.656269 Write Rank0 MR13 =0xd8
499 11:10:16.656684 [ModeRegInit_LP4] CH1 RK1
500 11:10:16.659714 Write Rank1 MR13 =0x18
501 11:10:16.660097 Write Rank1 MR12 =0x5d
502 11:10:16.663081 Write Rank1 MR1 =0x56
503 11:10:16.666309 Write Rank1 MR2 =0x1a
504 11:10:16.666690 Write Rank1 MR11 =0x0
505 11:10:16.669733 Write Rank1 MR22 =0x38
506 11:10:16.670118 Write Rank1 MR14 =0x5d
507 11:10:16.673023 Write Rank1 MR3 =0x30
508 11:10:16.676312 Write Rank1 MR13 =0x58
509 11:10:16.676756 Write Rank1 MR12 =0x5d
510 11:10:16.679680 Write Rank1 MR1 =0x56
511 11:10:16.683335 Write Rank1 MR2 =0x2d
512 11:10:16.683737 Write Rank1 MR11 =0x23
513 11:10:16.686685 Write Rank1 MR22 =0x34
514 11:10:16.687201 Write Rank1 MR14 =0x10
515 11:10:16.689781 Write Rank1 MR3 =0x30
516 11:10:16.692953 Write Rank1 MR13 =0xd8
517 11:10:16.693335 match AC timing 3
518 11:10:16.703047 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
519 11:10:16.703441 [MiockJmeterHQA]
520 11:10:16.709830 vSetVcoreByFreq with vcore:762500, freq=1600
521 11:10:16.813794
522 11:10:16.814194 MIOCK jitter meter ch=0
523 11:10:16.814492
524 11:10:16.817069 1T = (102-17) = 85 dly cells
525 11:10:16.823721 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 735/100 ps
526 11:10:16.827357 vSetVcoreByFreq with vcore:725000, freq=1200
527 11:10:16.926468
528 11:10:16.926895 MIOCK jitter meter ch=0
529 11:10:16.927195
530 11:10:16.929871 1T = (96-16) = 80 dly cells
531 11:10:16.937324 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
532 11:10:16.940725 vSetVcoreByFreq with vcore:725000, freq=800
533 11:10:17.038629
534 11:10:17.039027 MIOCK jitter meter ch=0
535 11:10:17.039322
536 11:10:17.042210 1T = (96-16) = 80 dly cells
537 11:10:17.048953 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
538 11:10:17.051947 vSetVcoreByFreq with vcore:762500, freq=1600
539 11:10:17.055876 vSetVcoreByFreq with vcore:762500, freq=1600
540 11:10:17.056259
541 11:10:17.056610 K DRVP
542 11:10:17.058894 1. OCD DRVP=0 CALOUT=0
543 11:10:17.062196 1. OCD DRVP=1 CALOUT=0
544 11:10:17.062587 1. OCD DRVP=2 CALOUT=0
545 11:10:17.065365 1. OCD DRVP=3 CALOUT=0
546 11:10:17.065752 1. OCD DRVP=4 CALOUT=0
547 11:10:17.068759 1. OCD DRVP=5 CALOUT=0
548 11:10:17.072334 1. OCD DRVP=6 CALOUT=0
549 11:10:17.072756 1. OCD DRVP=7 CALOUT=0
550 11:10:17.075740 1. OCD DRVP=8 CALOUT=0
551 11:10:17.079125 1. OCD DRVP=9 CALOUT=1
552 11:10:17.079512
553 11:10:17.081818 1. OCD DRVP calibration OK! DRVP=9
554 11:10:17.082205
555 11:10:17.082497
556 11:10:17.082858
557 11:10:17.083137 K ODTN
558 11:10:17.085403 3. OCD ODTN=0 ,CALOUT=1
559 11:10:17.085809 3. OCD ODTN=1 ,CALOUT=1
560 11:10:17.088807 3. OCD ODTN=2 ,CALOUT=1
561 11:10:17.091964 3. OCD ODTN=3 ,CALOUT=1
562 11:10:17.092351 3. OCD ODTN=4 ,CALOUT=1
563 11:10:17.095409 3. OCD ODTN=5 ,CALOUT=1
564 11:10:17.095806 3. OCD ODTN=6 ,CALOUT=1
565 11:10:17.098936 3. OCD ODTN=7 ,CALOUT=0
566 11:10:17.099320
567 11:10:17.102262 3. OCD ODTN calibration OK! ODTN=7
568 11:10:17.102649
569 11:10:17.105563 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=7
570 11:10:17.109170 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15
571 11:10:17.115323 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15 (After Adjust)
572 11:10:17.115703
573 11:10:17.115995 K DRVP
574 11:10:17.118724 1. OCD DRVP=0 CALOUT=0
575 11:10:17.119170 1. OCD DRVP=1 CALOUT=0
576 11:10:17.122164 1. OCD DRVP=2 CALOUT=0
577 11:10:17.125576 1. OCD DRVP=3 CALOUT=0
578 11:10:17.125962 1. OCD DRVP=4 CALOUT=0
579 11:10:17.128793 1. OCD DRVP=5 CALOUT=0
580 11:10:17.132286 1. OCD DRVP=6 CALOUT=0
581 11:10:17.132726 1. OCD DRVP=7 CALOUT=0
582 11:10:17.135456 1. OCD DRVP=8 CALOUT=0
583 11:10:17.135843 1. OCD DRVP=9 CALOUT=0
584 11:10:17.138765 1. OCD DRVP=10 CALOUT=0
585 11:10:17.142298 1. OCD DRVP=11 CALOUT=1
586 11:10:17.142687
587 11:10:17.145272 1. OCD DRVP calibration OK! DRVP=11
588 11:10:17.145661
589 11:10:17.145955
590 11:10:17.146225
591 11:10:17.146484 K ODTN
592 11:10:17.148848 3. OCD ODTN=0 ,CALOUT=1
593 11:10:17.149236 3. OCD ODTN=1 ,CALOUT=1
594 11:10:17.152157 3. OCD ODTN=2 ,CALOUT=1
595 11:10:17.155561 3. OCD ODTN=3 ,CALOUT=1
596 11:10:17.155950 3. OCD ODTN=4 ,CALOUT=1
597 11:10:17.159139 3. OCD ODTN=5 ,CALOUT=1
598 11:10:17.162471 3. OCD ODTN=6 ,CALOUT=1
599 11:10:17.162859 3. OCD ODTN=7 ,CALOUT=1
600 11:10:17.165682 3. OCD ODTN=8 ,CALOUT=1
601 11:10:17.166071 3. OCD ODTN=9 ,CALOUT=1
602 11:10:17.169089 3. OCD ODTN=10 ,CALOUT=1
603 11:10:17.172274 3. OCD ODTN=11 ,CALOUT=1
604 11:10:17.172716 3. OCD ODTN=12 ,CALOUT=1
605 11:10:17.175452 3. OCD ODTN=13 ,CALOUT=1
606 11:10:17.178760 3. OCD ODTN=14 ,CALOUT=1
607 11:10:17.179148 3. OCD ODTN=15 ,CALOUT=0
608 11:10:17.182279
609 11:10:17.182658 3. OCD ODTN calibration OK! ODTN=15
610 11:10:17.185923
611 11:10:17.189415 [SwImpedanceCal] DRVP=11, DRVN=9, ODTN=15
612 11:10:17.192552 term_option=1, Reg: DRVP=11, DRVN=9, ODTN=15
613 11:10:17.195553 term_option=1, Reg: DRVP=11, DRVN=9, ODTN=15 (After Adjust)
614 11:10:17.195937
615 11:10:17.199591 [DramcInit]
616 11:10:17.202590 AutoRefreshCKEOff AutoREF OFF
617 11:10:17.202971 DDRPhyPLLSetting-CKEOFF
618 11:10:17.205932 DDRPhyPLLSetting-CKEON
619 11:10:17.206311
620 11:10:17.206609 Enable WDQS
621 11:10:17.206882 ==
622 11:10:17.212982 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
623 11:10:17.216178 fsp= 1, odt_onoff= 1, Byte mode= 0
624 11:10:17.216589 ==
625 11:10:17.219496 [Duty_Offset_Calibration]
626 11:10:17.219875
627 11:10:17.220168 ===========================
628 11:10:17.222864 B0:1 B1:1 CA:1
629 11:10:17.241740 ==
630 11:10:17.244978 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
631 11:10:17.247979 fsp= 1, odt_onoff= 1, Byte mode= 0
632 11:10:17.248360 ==
633 11:10:17.251514 [Duty_Offset_Calibration]
634 11:10:17.251895
635 11:10:17.254783 ===========================
636 11:10:17.255167 B0:1 B1:0 CA:2
637 11:10:17.288183 [ModeRegInit_LP4] CH0 RK0
638 11:10:17.291314 Write Rank0 MR13 =0x18
639 11:10:17.291696 Write Rank0 MR12 =0x5d
640 11:10:17.294617 Write Rank0 MR1 =0x56
641 11:10:17.297876 Write Rank0 MR2 =0x1a
642 11:10:17.298257 Write Rank0 MR11 =0x0
643 11:10:17.301267 Write Rank0 MR22 =0x38
644 11:10:17.301647 Write Rank0 MR14 =0x5d
645 11:10:17.304614 Write Rank0 MR3 =0x30
646 11:10:17.307910 Write Rank0 MR13 =0x58
647 11:10:17.308290 Write Rank0 MR12 =0x5d
648 11:10:17.311156 Write Rank0 MR1 =0x56
649 11:10:17.311536 Write Rank0 MR2 =0x2d
650 11:10:17.314864 Write Rank0 MR11 =0x23
651 11:10:17.318139 Write Rank0 MR22 =0x34
652 11:10:17.318520 Write Rank0 MR14 =0x10
653 11:10:17.321540 Write Rank0 MR3 =0x30
654 11:10:17.324802 Write Rank0 MR13 =0xd8
655 11:10:17.325182 [ModeRegInit_LP4] CH0 RK1
656 11:10:17.328059 Write Rank1 MR13 =0x18
657 11:10:17.328438 Write Rank1 MR12 =0x5d
658 11:10:17.331270 Write Rank1 MR1 =0x56
659 11:10:17.334814 Write Rank1 MR2 =0x1a
660 11:10:17.335198 Write Rank1 MR11 =0x0
661 11:10:17.337648 Write Rank1 MR22 =0x38
662 11:10:17.340859 Write Rank1 MR14 =0x5d
663 11:10:17.340961 Write Rank1 MR3 =0x30
664 11:10:17.344233 Write Rank1 MR13 =0x58
665 11:10:17.344323 Write Rank1 MR12 =0x5d
666 11:10:17.348175 Write Rank1 MR1 =0x56
667 11:10:17.348276 Write Rank1 MR2 =0x2d
668 11:10:17.351365 Write Rank1 MR11 =0x23
669 11:10:17.354610 Write Rank1 MR22 =0x34
670 11:10:17.354716 Write Rank1 MR14 =0x10
671 11:10:17.357541 Write Rank1 MR3 =0x30
672 11:10:17.361062 Write Rank1 MR13 =0xd8
673 11:10:17.361196 [ModeRegInit_LP4] CH1 RK0
674 11:10:17.364430 Write Rank0 MR13 =0x18
675 11:10:17.368064 Write Rank0 MR12 =0x5d
676 11:10:17.368213 Write Rank0 MR1 =0x56
677 11:10:17.371532 Write Rank0 MR2 =0x1a
678 11:10:17.371705 Write Rank0 MR11 =0x0
679 11:10:17.374646 Write Rank0 MR22 =0x38
680 11:10:17.377832 Write Rank0 MR14 =0x5d
681 11:10:17.378038 Write Rank0 MR3 =0x30
682 11:10:17.381162 Write Rank0 MR13 =0x58
683 11:10:17.381506 Write Rank0 MR12 =0x5d
684 11:10:17.384378 Write Rank0 MR1 =0x56
685 11:10:17.388039 Write Rank0 MR2 =0x2d
686 11:10:17.388362 Write Rank0 MR11 =0x23
687 11:10:17.391342 Write Rank0 MR22 =0x34
688 11:10:17.391740 Write Rank0 MR14 =0x10
689 11:10:17.394890 Write Rank0 MR3 =0x30
690 11:10:17.398370 Write Rank0 MR13 =0xd8
691 11:10:17.398752 [ModeRegInit_LP4] CH1 RK1
692 11:10:17.401896 Write Rank1 MR13 =0x18
693 11:10:17.404993 Write Rank1 MR12 =0x5d
694 11:10:17.405376 Write Rank1 MR1 =0x56
695 11:10:17.408497 Write Rank1 MR2 =0x1a
696 11:10:17.409096 Write Rank1 MR11 =0x0
697 11:10:17.411982 Write Rank1 MR22 =0x38
698 11:10:17.414949 Write Rank1 MR14 =0x5d
699 11:10:17.415396 Write Rank1 MR3 =0x30
700 11:10:17.418496 Write Rank1 MR13 =0x58
701 11:10:17.418905 Write Rank1 MR12 =0x5d
702 11:10:17.421675 Write Rank1 MR1 =0x56
703 11:10:17.425357 Write Rank1 MR2 =0x2d
704 11:10:17.425753 Write Rank1 MR11 =0x23
705 11:10:17.428877 Write Rank1 MR22 =0x34
706 11:10:17.429274 Write Rank1 MR14 =0x10
707 11:10:17.431592 Write Rank1 MR3 =0x30
708 11:10:17.435265 Write Rank1 MR13 =0xd8
709 11:10:17.435663 match AC timing 3
710 11:10:17.445218 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
711 11:10:17.448369 DramC Write-DBI off
712 11:10:17.448812 DramC Read-DBI off
713 11:10:17.451888 Write Rank0 MR13 =0x59
714 11:10:17.452283 ==
715 11:10:17.454881 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
716 11:10:17.458260 fsp= 1, odt_onoff= 1, Byte mode= 0
717 11:10:17.458659 ==
718 11:10:17.462131 === u2Vref_new: 0x56 --> 0x2d
719 11:10:17.465169 === u2Vref_new: 0x58 --> 0x38
720 11:10:17.468348 === u2Vref_new: 0x5a --> 0x39
721 11:10:17.471551 === u2Vref_new: 0x5c --> 0x3c
722 11:10:17.475094 === u2Vref_new: 0x5e --> 0x3d
723 11:10:17.478263 === u2Vref_new: 0x60 --> 0xa0
724 11:10:17.481360 [CA 0] Center 35 (7~63) winsize 57
725 11:10:17.484819 [CA 1] Center 36 (9~63) winsize 55
726 11:10:17.488396 [CA 2] Center 29 (0~58) winsize 59
727 11:10:17.491640 [CA 3] Center 24 (-3~52) winsize 56
728 11:10:17.491832 [CA 4] Center 25 (-3~53) winsize 57
729 11:10:17.495034 [CA 5] Center 30 (0~60) winsize 61
730 11:10:17.495213
731 11:10:17.498355 [CATrainingPosCal] consider 1 rank data
732 11:10:17.501809 u2DelayCellTimex100 = 735/100 ps
733 11:10:17.507993 CA0 delay=35 (7~63),Diff = 11 PI (14 cell)
734 11:10:17.511619 CA1 delay=36 (9~63),Diff = 12 PI (15 cell)
735 11:10:17.514844 CA2 delay=29 (0~58),Diff = 5 PI (6 cell)
736 11:10:17.518378 CA3 delay=24 (-3~52),Diff = 0 PI (0 cell)
737 11:10:17.521660 CA4 delay=25 (-3~53),Diff = 1 PI (1 cell)
738 11:10:17.524985 CA5 delay=30 (0~60),Diff = 6 PI (7 cell)
739 11:10:17.525070
740 11:10:17.528230 CA PerBit enable=1, Macro0, CA PI delay=24
741 11:10:17.531570 === u2Vref_new: 0x5e --> 0x3d
742 11:10:17.531654
743 11:10:17.534851 Vref(ca) range 1: 30
744 11:10:17.534935
745 11:10:17.535000 CS Dly= 9 (40-0-32)
746 11:10:17.538481 Write Rank0 MR13 =0xd8
747 11:10:17.538566 Write Rank0 MR13 =0xd8
748 11:10:17.541726 Write Rank0 MR12 =0x5e
749 11:10:17.545229 Write Rank1 MR13 =0x59
750 11:10:17.545312 ==
751 11:10:17.548325 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
752 11:10:17.551540 fsp= 1, odt_onoff= 1, Byte mode= 0
753 11:10:17.551627 ==
754 11:10:17.554908 === u2Vref_new: 0x56 --> 0x2d
755 11:10:17.558792 === u2Vref_new: 0x58 --> 0x38
756 11:10:17.561742 === u2Vref_new: 0x5a --> 0x39
757 11:10:17.564973 === u2Vref_new: 0x5c --> 0x3c
758 11:10:17.568333 === u2Vref_new: 0x5e --> 0x3d
759 11:10:17.572032 === u2Vref_new: 0x60 --> 0xa0
760 11:10:17.575361 [CA 0] Center 35 (8~63) winsize 56
761 11:10:17.578743 [CA 1] Center 36 (9~63) winsize 55
762 11:10:17.581854 [CA 2] Center 31 (3~60) winsize 58
763 11:10:17.585087 [CA 3] Center 26 (-2~54) winsize 57
764 11:10:17.588590 [CA 4] Center 26 (-2~55) winsize 58
765 11:10:17.588703 [CA 5] Center 31 (2~61) winsize 60
766 11:10:17.591983
767 11:10:17.595466 [CATrainingPosCal] consider 2 rank data
768 11:10:17.595574 u2DelayCellTimex100 = 735/100 ps
769 11:10:17.602148 CA0 delay=35 (8~63),Diff = 10 PI (13 cell)
770 11:10:17.605417 CA1 delay=36 (9~63),Diff = 11 PI (14 cell)
771 11:10:17.608745 CA2 delay=30 (3~58),Diff = 5 PI (6 cell)
772 11:10:17.612231 CA3 delay=25 (-2~52),Diff = 0 PI (0 cell)
773 11:10:17.615370 CA4 delay=25 (-2~53),Diff = 0 PI (0 cell)
774 11:10:17.618648 CA5 delay=31 (2~60),Diff = 6 PI (7 cell)
775 11:10:17.618753
776 11:10:17.621958 CA PerBit enable=1, Macro0, CA PI delay=25
777 11:10:17.625871 === u2Vref_new: 0x60 --> 0xa0
778 11:10:17.625977
779 11:10:17.629014 Vref(ca) range 1: 32
780 11:10:17.629119
781 11:10:17.629213 CS Dly= 8 (39-0-32)
782 11:10:17.632325 Write Rank1 MR13 =0xd8
783 11:10:17.632425 Write Rank1 MR13 =0xd8
784 11:10:17.635487 Write Rank1 MR12 =0x60
785 11:10:17.639082 [RankSwap] Rank num 2, (Multi 1), Rank 0
786 11:10:17.642163 Write Rank0 MR2 =0xad
787 11:10:17.642247 [Write Leveling]
788 11:10:17.645479 delay byte0 byte1 byte2 byte3
789 11:10:17.645564
790 11:10:17.648863 10 0 0
791 11:10:17.648949 11 0 0
792 11:10:17.649016 12 0 0
793 11:10:17.652197 13 0 0
794 11:10:17.652293 14 0 0
795 11:10:17.655720 15 0 0
796 11:10:17.655813 16 0 0
797 11:10:17.655884 17 0 0
798 11:10:17.659128 18 0 0
799 11:10:17.659221 19 0 0
800 11:10:17.662734 20 0 0
801 11:10:17.662826 21 0 0
802 11:10:17.665715 22 0 0
803 11:10:17.665807 23 0 0
804 11:10:17.665894 24 0 ff
805 11:10:17.668994 25 0 ff
806 11:10:17.669094 26 0 ff
807 11:10:17.672274 27 0 ff
808 11:10:17.672407 28 0 ff
809 11:10:17.675524 29 0 ff
810 11:10:17.675636 30 0 ff
811 11:10:17.675749 31 0 ff
812 11:10:17.678961 32 ff ff
813 11:10:17.679086 33 ff ff
814 11:10:17.682375 34 ff ff
815 11:10:17.682516 35 ff ff
816 11:10:17.686098 36 ff ff
817 11:10:17.686289 37 ff ff
818 11:10:17.689274 38 ff ff
819 11:10:17.692353 pass bytecount = 0xff (0xff: all bytes pass)
820 11:10:17.692500
821 11:10:17.692613 DQS0 dly: 32
822 11:10:17.695790 DQS1 dly: 24
823 11:10:17.695923 Write Rank0 MR2 =0x2d
824 11:10:17.699332 [RankSwap] Rank num 2, (Multi 1), Rank 0
825 11:10:17.702475 Write Rank0 MR1 =0xd6
826 11:10:17.702607 [Gating]
827 11:10:17.702710 ==
828 11:10:17.709028 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
829 11:10:17.712429 fsp= 1, odt_onoff= 1, Byte mode= 0
830 11:10:17.712582 ==
831 11:10:17.715953 3 1 0 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
832 11:10:17.719088 3 1 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
833 11:10:17.725989 3 1 8 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
834 11:10:17.729348 3 1 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
835 11:10:17.732800 3 1 16 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
836 11:10:17.739859 3 1 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
837 11:10:17.742810 3 1 24 |2c2c 3534 |(11 0)(11 11) |(0 0)(0 1)| 0
838 11:10:17.746491 3 1 28 |303 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
839 11:10:17.749814 3 2 0 |3534 807 |(11 11)(11 11) |(0 0)(1 1)| 0
840 11:10:17.756251 3 2 4 |3534 e0e |(11 11)(11 11) |(0 0)(1 1)| 0
841 11:10:17.760026 3 2 8 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
842 11:10:17.762660 3 2 12 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
843 11:10:17.769527 3 2 16 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
844 11:10:17.772866 3 2 20 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
845 11:10:17.776314 3 2 24 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
846 11:10:17.782868 3 2 28 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
847 11:10:17.786435 3 3 0 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
848 11:10:17.789738 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
849 11:10:17.793257 3 3 8 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
850 11:10:17.800003 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
851 11:10:17.803237 [Byte 1] Lead/lag falling Transition (3, 3, 12)
852 11:10:17.806697 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
853 11:10:17.813326 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
854 11:10:17.816652 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
855 11:10:17.819776 3 3 28 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
856 11:10:17.823041 3 4 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
857 11:10:17.830235 3 4 4 |3d3d 100f |(11 11)(11 11) |(1 1)(1 1)| 0
858 11:10:17.833294 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
859 11:10:17.836748 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
860 11:10:17.843427 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
861 11:10:17.846751 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
862 11:10:17.850085 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
863 11:10:17.856581 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
864 11:10:17.859941 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
865 11:10:17.863138 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
866 11:10:17.866819 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
867 11:10:17.873355 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
868 11:10:17.876587 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
869 11:10:17.879975 [Byte 0] Lead/lag falling Transition (3, 5, 16)
870 11:10:17.886472 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
871 11:10:17.890032 [Byte 0] Lead/lag Transition tap number (2)
872 11:10:17.893407 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
873 11:10:17.896834 [Byte 1] Lead/lag falling Transition (3, 5, 24)
874 11:10:17.903526 3 5 28 |3c3c 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
875 11:10:17.907065 3 6 0 |4646 1e1e |(0 0)(11 11) |(0 0)(1 0)| 0
876 11:10:17.910178 [Byte 0]First pass (3, 6, 0)
877 11:10:17.913722 [Byte 1] Lead/lag Transition tap number (3)
878 11:10:17.916655 3 6 4 |4646 c0c |(0 0)(11 11) |(0 0)(0 0)| 0
879 11:10:17.919988 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
880 11:10:17.923408 [Byte 1]First pass (3, 6, 8)
881 11:10:17.926890 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
882 11:10:17.933711 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
883 11:10:17.936788 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
884 11:10:17.940075 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
885 11:10:17.943829 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
886 11:10:17.946813 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
887 11:10:17.953696 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
888 11:10:17.957212 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
889 11:10:17.960158 All bytes gating window > 1UI, Early break!
890 11:10:17.960753
891 11:10:17.963943 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 20)
892 11:10:17.964399
893 11:10:17.967045 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 30)
894 11:10:17.967593
895 11:10:17.967956
896 11:10:17.968430
897 11:10:17.970313 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 20)
898 11:10:17.970813
899 11:10:17.977405 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 30)
900 11:10:17.977954
901 11:10:17.978416
902 11:10:17.978872 Write Rank0 MR1 =0x56
903 11:10:17.979298
904 11:10:17.980528 best RODT dly(2T, 0.5T) = (2, 2)
905 11:10:17.980966
906 11:10:17.983949 best RODT dly(2T, 0.5T) = (2, 2)
907 11:10:17.984326 ==
908 11:10:17.990347 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
909 11:10:17.994354 fsp= 1, odt_onoff= 1, Byte mode= 0
910 11:10:17.994833 ==
911 11:10:17.997642 Start DQ dly to find pass range UseTestEngine =0
912 11:10:18.000761 x-axis: bit #, y-axis: DQ dly (-127~63)
913 11:10:18.004032 RX Vref Scan = 0
914 11:10:18.004429 -26, [0] xxxxxxxx xxxxxxxx [MSB]
915 11:10:18.007347 -25, [0] xxxxxxxx xxxxxxxx [MSB]
916 11:10:18.010564 -24, [0] xxxxxxxx xxxxxxxx [MSB]
917 11:10:18.013873 -23, [0] xxxxxxxx xxxxxxxx [MSB]
918 11:10:18.017336 -22, [0] xxxxxxxx xxxxxxxx [MSB]
919 11:10:18.020794 -21, [0] xxxxxxxx xxxxxxxx [MSB]
920 11:10:18.024072 -20, [0] xxxxxxxx xxxxxxxx [MSB]
921 11:10:18.027481 -19, [0] xxxxxxxx xxxxxxxx [MSB]
922 11:10:18.027889 -18, [0] xxxxxxxx xxxxxxxx [MSB]
923 11:10:18.030772 -17, [0] xxxxxxxx xxxxxxxx [MSB]
924 11:10:18.034154 -16, [0] xxxxxxxx xxxxxxxx [MSB]
925 11:10:18.037319 -15, [0] xxxxxxxx xxxxxxxx [MSB]
926 11:10:18.040936 -14, [0] xxxxxxxx xxxxxxxx [MSB]
927 11:10:18.044024 -13, [0] xxxxxxxx xxxxxxxx [MSB]
928 11:10:18.047519 -12, [0] xxxxxxxx xxxxxxxx [MSB]
929 11:10:18.050880 -11, [0] xxxxxxxx xxxxxxxx [MSB]
930 11:10:18.051301 -10, [0] xxxxxxxx xxxxxxxx [MSB]
931 11:10:18.054535 -9, [0] xxxxxxxx xxxxxxxx [MSB]
932 11:10:18.057661 -8, [0] xxxxxxxx xxxxxxxx [MSB]
933 11:10:18.060916 -7, [0] xxxxxxxx xxxxxxxx [MSB]
934 11:10:18.064411 -6, [0] xxxxxxxx xxxxxxxx [MSB]
935 11:10:18.067836 -5, [0] xxxxxxxx xxxxxxxx [MSB]
936 11:10:18.071033 -4, [0] xxxxxxxx xxxxxxxx [MSB]
937 11:10:18.071441 -3, [0] xxxxxxxx xxxxxxxx [MSB]
938 11:10:18.074178 -2, [0] xxxoxxxx oxxxxxxx [MSB]
939 11:10:18.077572 -1, [0] xxxoxxxx ooxoxxxx [MSB]
940 11:10:18.080933 0, [0] xxxoxoxx ooxoxxxx [MSB]
941 11:10:18.084600 1, [0] xxxoxoox ooxoooxx [MSB]
942 11:10:18.087949 2, [0] xxxoxoox ooxoooxx [MSB]
943 11:10:18.088337 3, [0] xxxoxoox ooxoooox [MSB]
944 11:10:18.091193 4, [0] xxxoxooo ooxooooo [MSB]
945 11:10:18.094441 5, [0] xooooooo ooxooooo [MSB]
946 11:10:18.097916 6, [0] oooooooo ooxooooo [MSB]
947 11:10:18.101103 7, [0] oooooooo ooxooooo [MSB]
948 11:10:18.104444 32, [0] oooxoooo oooooooo [MSB]
949 11:10:18.104876 33, [0] oooxoooo xooooooo [MSB]
950 11:10:18.107549 34, [0] oooxoooo xooooooo [MSB]
951 11:10:18.111048 35, [0] oooxoooo xooooooo [MSB]
952 11:10:18.114560 36, [0] oooxoxoo xooxoooo [MSB]
953 11:10:18.117867 37, [0] oooxoxxx xxoxoooo [MSB]
954 11:10:18.121126 38, [0] oooxoxxx xxoxxoxo [MSB]
955 11:10:18.124335 39, [0] oooxxxxx xxoxxxxo [MSB]
956 11:10:18.124777 40, [0] oooxxxxx xxoxxxxo [MSB]
957 11:10:18.127629 41, [0] xxoxxxxx xxoxxxxo [MSB]
958 11:10:18.131038 42, [0] xxxxxxxx xxoxxxxx [MSB]
959 11:10:18.134348 43, [0] xxxxxxxx xxoxxxxx [MSB]
960 11:10:18.137770 44, [0] xxxxxxxx xxxxxxxx [MSB]
961 11:10:18.141040 iDelay=44, Bit 0, Center 23 (6 ~ 40) 35
962 11:10:18.144290 iDelay=44, Bit 1, Center 22 (5 ~ 40) 36
963 11:10:18.147554 iDelay=44, Bit 2, Center 23 (5 ~ 41) 37
964 11:10:18.150835 iDelay=44, Bit 3, Center 14 (-2 ~ 31) 34
965 11:10:18.154468 iDelay=44, Bit 4, Center 21 (5 ~ 38) 34
966 11:10:18.157858 iDelay=44, Bit 5, Center 17 (0 ~ 35) 36
967 11:10:18.160938 iDelay=44, Bit 6, Center 18 (1 ~ 36) 36
968 11:10:18.164511 iDelay=44, Bit 7, Center 20 (4 ~ 36) 33
969 11:10:18.167754 iDelay=44, Bit 8, Center 15 (-2 ~ 32) 35
970 11:10:18.174585 iDelay=44, Bit 9, Center 17 (-1 ~ 36) 38
971 11:10:18.177546 iDelay=44, Bit 10, Center 25 (8 ~ 43) 36
972 11:10:18.180952 iDelay=44, Bit 11, Center 17 (-1 ~ 35) 37
973 11:10:18.184669 iDelay=44, Bit 12, Center 19 (1 ~ 37) 37
974 11:10:18.188301 iDelay=44, Bit 13, Center 19 (1 ~ 38) 38
975 11:10:18.191487 iDelay=44, Bit 14, Center 20 (3 ~ 37) 35
976 11:10:18.194839 iDelay=44, Bit 15, Center 22 (4 ~ 41) 38
977 11:10:18.195411 ==
978 11:10:18.201472 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
979 11:10:18.204699 fsp= 1, odt_onoff= 1, Byte mode= 0
980 11:10:18.205204 ==
981 11:10:18.205677 DQS Delay:
982 11:10:18.206128 DQS0 = 0, DQS1 = 0
983 11:10:18.208039 DQM Delay:
984 11:10:18.208425 DQM0 = 19, DQM1 = 19
985 11:10:18.211525 DQ Delay:
986 11:10:18.214508 DQ0 =23, DQ1 =22, DQ2 =23, DQ3 =14
987 11:10:18.215079 DQ4 =21, DQ5 =17, DQ6 =18, DQ7 =20
988 11:10:18.217959 DQ8 =15, DQ9 =17, DQ10 =25, DQ11 =17
989 11:10:18.221749 DQ12 =19, DQ13 =19, DQ14 =20, DQ15 =22
990 11:10:18.225066
991 11:10:18.225446
992 11:10:18.225742 DramC Write-DBI off
993 11:10:18.226020 ==
994 11:10:18.231601 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
995 11:10:18.234648 fsp= 1, odt_onoff= 1, Byte mode= 0
996 11:10:18.235036 ==
997 11:10:18.237947 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
998 11:10:18.238334
999 11:10:18.241725 Begin, DQ Scan Range 920~1176
1000 11:10:18.242130
1001 11:10:18.242425
1002 11:10:18.244513 TX Vref Scan disable
1003 11:10:18.248357 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1004 11:10:18.251646 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1005 11:10:18.254859 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1006 11:10:18.258248 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1007 11:10:18.261391 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1008 11:10:18.264662 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1009 11:10:18.268280 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1010 11:10:18.271788 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1011 11:10:18.274688 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1012 11:10:18.278426 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1013 11:10:18.281451 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1014 11:10:18.284724 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1015 11:10:18.287960 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1016 11:10:18.291345 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1017 11:10:18.294676 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1018 11:10:18.298294 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1019 11:10:18.301614 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1020 11:10:18.308427 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1021 11:10:18.311847 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1022 11:10:18.314955 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1023 11:10:18.318455 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1024 11:10:18.321644 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1025 11:10:18.324952 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1026 11:10:18.328920 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1027 11:10:18.331713 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1028 11:10:18.335009 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1029 11:10:18.338829 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1030 11:10:18.341781 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1031 11:10:18.345519 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1032 11:10:18.348874 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1033 11:10:18.352129 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1034 11:10:18.355428 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1035 11:10:18.358945 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1036 11:10:18.362039 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1037 11:10:18.365278 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1038 11:10:18.368507 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1039 11:10:18.375469 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1040 11:10:18.378579 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1041 11:10:18.381859 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1042 11:10:18.385554 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1043 11:10:18.388572 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1044 11:10:18.392005 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1045 11:10:18.395652 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1046 11:10:18.398913 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1047 11:10:18.401996 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1048 11:10:18.405609 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1049 11:10:18.408993 966 |3 6 6|[0] xxxxxxxx oxxoxxxx [MSB]
1050 11:10:18.412328 967 |3 6 7|[0] xxxxxxxx ooxoxxxx [MSB]
1051 11:10:18.415578 968 |3 6 8|[0] xxxxxxxx ooxoooox [MSB]
1052 11:10:18.419254 969 |3 6 9|[0] xxxxxxxx ooxoooox [MSB]
1053 11:10:18.422390 970 |3 6 10|[0] xxxxxxxx ooxoooox [MSB]
1054 11:10:18.425719 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
1055 11:10:18.428861 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
1056 11:10:18.432629 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
1057 11:10:18.435412 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
1058 11:10:18.439332 975 |3 6 15|[0] xxxoxoox oooooooo [MSB]
1059 11:10:18.442044 976 |3 6 16|[0] xoxooooo oooooooo [MSB]
1060 11:10:18.449761 985 |3 6 25|[0] oooooooo xooooooo [MSB]
1061 11:10:18.453574 986 |3 6 26|[0] oooooooo xooooooo [MSB]
1062 11:10:18.456856 987 |3 6 27|[0] oooooooo xxxxxxxx [MSB]
1063 11:10:18.460127 988 |3 6 28|[0] oooooooo xxxxxxxx [MSB]
1064 11:10:18.463388 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1065 11:10:18.466905 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1066 11:10:18.469997 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1067 11:10:18.473222 992 |3 6 32|[0] oooxoooo xxxxxxxx [MSB]
1068 11:10:18.476746 993 |3 6 33|[0] oooxoooo xxxxxxxx [MSB]
1069 11:10:18.479971 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
1070 11:10:18.483735 995 |3 6 35|[0] oooxoxxo xxxxxxxx [MSB]
1071 11:10:18.486989 996 |3 6 36|[0] oooxxxxx xxxxxxxx [MSB]
1072 11:10:18.490255 997 |3 6 37|[0] xxxxxxxx xxxxxxxx [MSB]
1073 11:10:18.493574 Byte0, DQ PI dly=984, DQM PI dly= 984
1074 11:10:18.500487 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
1075 11:10:18.500880
1076 11:10:18.503164 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
1077 11:10:18.503549
1078 11:10:18.506958 Byte1, DQ PI dly=976, DQM PI dly= 976
1079 11:10:18.510316 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 16)
1080 11:10:18.510700
1081 11:10:18.516672 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 16)
1082 11:10:18.517060
1083 11:10:18.517382 ==
1084 11:10:18.520208 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1085 11:10:18.523384 fsp= 1, odt_onoff= 1, Byte mode= 0
1086 11:10:18.523769 ==
1087 11:10:18.526815 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1088 11:10:18.530316
1089 11:10:18.530698 Begin, DQ Scan Range 952~1016
1090 11:10:18.533656 Write Rank0 MR14 =0x0
1091 11:10:18.541638
1092 11:10:18.542108 CH=0, VrefRange= 0, VrefLevel = 0
1093 11:10:18.548210 TX Bit0 (978~993) 16 985, Bit8 (967~977) 11 972,
1094 11:10:18.551693 TX Bit1 (977~992) 16 984, Bit9 (969~983) 15 976,
1095 11:10:18.558033 TX Bit2 (978~993) 16 985, Bit10 (975~987) 13 981,
1096 11:10:18.561491 TX Bit3 (974~985) 12 979, Bit11 (968~981) 14 974,
1097 11:10:18.564906 TX Bit4 (978~991) 14 984, Bit12 (970~983) 14 976,
1098 11:10:18.571531 TX Bit5 (976~990) 15 983, Bit13 (970~983) 14 976,
1099 11:10:18.574775 TX Bit6 (977~989) 13 983, Bit14 (969~984) 16 976,
1100 11:10:18.578282 TX Bit7 (978~991) 14 984, Bit15 (975~985) 11 980,
1101 11:10:18.578669
1102 11:10:18.584659 wait MRW command Rank0 MR14 =0x2 fired (1)
1103 11:10:18.585044 Write Rank0 MR14 =0x2
1104 11:10:18.593510
1105 11:10:18.593888 CH=0, VrefRange= 0, VrefLevel = 2
1106 11:10:18.600134 TX Bit0 (978~993) 16 985, Bit8 (967~979) 13 973,
1107 11:10:18.603695 TX Bit1 (977~992) 16 984, Bit9 (969~984) 16 976,
1108 11:10:18.610413 TX Bit2 (978~993) 16 985, Bit10 (975~988) 14 981,
1109 11:10:18.613622 TX Bit3 (974~986) 13 980, Bit11 (968~982) 15 975,
1110 11:10:18.617010 TX Bit4 (977~991) 15 984, Bit12 (970~984) 15 977,
1111 11:10:18.623867 TX Bit5 (976~991) 16 983, Bit13 (969~984) 16 976,
1112 11:10:18.627068 TX Bit6 (977~990) 14 983, Bit14 (969~985) 17 977,
1113 11:10:18.630225 TX Bit7 (977~992) 16 984, Bit15 (974~986) 13 980,
1114 11:10:18.630612
1115 11:10:18.633572 Write Rank0 MR14 =0x4
1116 11:10:18.642140
1117 11:10:18.642525 CH=0, VrefRange= 0, VrefLevel = 4
1118 11:10:18.649011 TX Bit0 (978~994) 17 986, Bit8 (967~981) 15 974,
1119 11:10:18.652327 TX Bit1 (977~993) 17 985, Bit9 (969~984) 16 976,
1120 11:10:18.659261 TX Bit2 (977~994) 18 985, Bit10 (975~989) 15 982,
1121 11:10:18.662189 TX Bit3 (974~987) 14 980, Bit11 (968~983) 16 975,
1122 11:10:18.665729 TX Bit4 (977~992) 16 984, Bit12 (970~984) 15 977,
1123 11:10:18.672451 TX Bit5 (975~991) 17 983, Bit13 (969~984) 16 976,
1124 11:10:18.675594 TX Bit6 (976~991) 16 983, Bit14 (969~985) 17 977,
1125 11:10:18.679161 TX Bit7 (977~992) 16 984, Bit15 (974~987) 14 980,
1126 11:10:18.679662
1127 11:10:18.682473 Write Rank0 MR14 =0x6
1128 11:10:18.690502
1129 11:10:18.691030 CH=0, VrefRange= 0, VrefLevel = 6
1130 11:10:18.697370 TX Bit0 (977~994) 18 985, Bit8 (967~982) 16 974,
1131 11:10:18.700548 TX Bit1 (977~993) 17 985, Bit9 (969~985) 17 977,
1132 11:10:18.707394 TX Bit2 (978~994) 17 986, Bit10 (974~990) 17 982,
1133 11:10:18.710619 TX Bit3 (973~987) 15 980, Bit11 (968~983) 16 975,
1134 11:10:18.713875 TX Bit4 (977~992) 16 984, Bit12 (969~984) 16 976,
1135 11:10:18.720614 TX Bit5 (975~992) 18 983, Bit13 (969~985) 17 977,
1136 11:10:18.724077 TX Bit6 (976~992) 17 984, Bit14 (969~986) 18 977,
1137 11:10:18.727418 TX Bit7 (977~992) 16 984, Bit15 (974~989) 16 981,
1138 11:10:18.727803
1139 11:10:18.730907 Write Rank0 MR14 =0x8
1140 11:10:18.780186
1141 11:10:18.780718 CH=0, VrefRange= 0, VrefLevel = 8
1142 11:10:18.781376 TX Bit0 (977~995) 19 986, Bit8 (966~982) 17 974,
1143 11:10:18.781812 TX Bit1 (976~994) 19 985, Bit9 (968~985) 18 976,
1144 11:10:18.782238 TX Bit2 (977~994) 18 985, Bit10 (974~990) 17 982,
1145 11:10:18.782682 TX Bit3 (972~989) 18 980, Bit11 (968~984) 17 976,
1146 11:10:18.783034 TX Bit4 (977~993) 17 985, Bit12 (969~985) 17 977,
1147 11:10:18.783314 TX Bit5 (974~992) 19 983, Bit13 (969~985) 17 977,
1148 11:10:18.783572 TX Bit6 (976~992) 17 984, Bit14 (968~986) 19 977,
1149 11:10:18.783919 TX Bit7 (977~993) 17 985, Bit15 (973~990) 18 981,
1150 11:10:18.784183
1151 11:10:18.784436 wait MRW command Rank0 MR14 =0xa fired (1)
1152 11:10:18.815959 Write Rank0 MR14 =0xa
1153 11:10:18.816343
1154 11:10:18.816721 CH=0, VrefRange= 0, VrefLevel = 10
1155 11:10:18.817009 TX Bit0 (977~995) 19 986, Bit8 (966~982) 17 974,
1156 11:10:18.817593 TX Bit1 (976~994) 19 985, Bit9 (968~985) 18 976,
1157 11:10:18.817886 TX Bit2 (977~995) 19 986, Bit10 (973~990) 18 981,
1158 11:10:18.818151 TX Bit3 (972~990) 19 981, Bit11 (967~984) 18 975,
1159 11:10:18.818408 TX Bit4 (976~993) 18 984, Bit12 (969~986) 18 977,
1160 11:10:18.819851 TX Bit5 (974~992) 19 983, Bit13 (969~986) 18 977,
1161 11:10:18.826590 TX Bit6 (975~992) 18 983, Bit14 (968~987) 20 977,
1162 11:10:18.829961 TX Bit7 (977~993) 17 985, Bit15 (972~990) 19 981,
1163 11:10:18.830360
1164 11:10:18.833097 Write Rank0 MR14 =0xc
1165 11:10:18.841424
1166 11:10:18.844531 CH=0, VrefRange= 0, VrefLevel = 12
1167 11:10:18.847738 TX Bit0 (977~997) 21 987, Bit8 (966~983) 18 974,
1168 11:10:18.851248 TX Bit1 (976~994) 19 985, Bit9 (968~986) 19 977,
1169 11:10:18.857789 TX Bit2 (977~997) 21 987, Bit10 (972~990) 19 981,
1170 11:10:18.861218 TX Bit3 (972~990) 19 981, Bit11 (967~984) 18 975,
1171 11:10:18.864328 TX Bit4 (976~994) 19 985, Bit12 (969~986) 18 977,
1172 11:10:18.871427 TX Bit5 (974~993) 20 983, Bit13 (968~986) 19 977,
1173 11:10:18.874460 TX Bit6 (975~993) 19 984, Bit14 (968~988) 21 978,
1174 11:10:18.877689 TX Bit7 (977~994) 18 985, Bit15 (972~990) 19 981,
1175 11:10:18.878074
1176 11:10:18.880826 Write Rank0 MR14 =0xe
1177 11:10:18.890247
1178 11:10:18.890627 CH=0, VrefRange= 0, VrefLevel = 14
1179 11:10:18.896711 TX Bit0 (977~997) 21 987, Bit8 (966~984) 19 975,
1180 11:10:18.899854 TX Bit1 (976~996) 21 986, Bit9 (968~987) 20 977,
1181 11:10:18.906823 TX Bit2 (976~997) 22 986, Bit10 (972~991) 20 981,
1182 11:10:18.910160 TX Bit3 (972~991) 20 981, Bit11 (967~985) 19 976,
1183 11:10:18.913359 TX Bit4 (976~994) 19 985, Bit12 (968~987) 20 977,
1184 11:10:18.919910 TX Bit5 (973~993) 21 983, Bit13 (968~987) 20 977,
1185 11:10:18.923151 TX Bit6 (975~993) 19 984, Bit14 (968~988) 21 978,
1186 11:10:18.926808 TX Bit7 (977~994) 18 985, Bit15 (971~990) 20 980,
1187 11:10:18.926914
1188 11:10:18.930114 Write Rank0 MR14 =0x10
1189 11:10:18.939446
1190 11:10:18.942324 CH=0, VrefRange= 0, VrefLevel = 16
1191 11:10:18.945848 TX Bit0 (976~998) 23 987, Bit8 (965~984) 20 974,
1192 11:10:18.949286 TX Bit1 (976~996) 21 986, Bit9 (968~988) 21 978,
1193 11:10:18.955965 TX Bit2 (976~998) 23 987, Bit10 (971~991) 21 981,
1194 11:10:18.958974 TX Bit3 (971~991) 21 981, Bit11 (967~985) 19 976,
1195 11:10:18.962815 TX Bit4 (976~995) 20 985, Bit12 (968~988) 21 978,
1196 11:10:18.969438 TX Bit5 (973~994) 22 983, Bit13 (968~988) 21 978,
1197 11:10:18.972777 TX Bit6 (975~994) 20 984, Bit14 (968~989) 22 978,
1198 11:10:18.975849 TX Bit7 (976~995) 20 985, Bit15 (971~991) 21 981,
1199 11:10:18.975937
1200 11:10:18.978942 Write Rank0 MR14 =0x12
1201 11:10:18.988225
1202 11:10:18.991880 CH=0, VrefRange= 0, VrefLevel = 18
1203 11:10:18.994907 TX Bit0 (976~998) 23 987, Bit8 (965~984) 20 974,
1204 11:10:18.998511 TX Bit1 (976~996) 21 986, Bit9 (967~988) 22 977,
1205 11:10:19.004994 TX Bit2 (977~998) 22 987, Bit10 (971~992) 22 981,
1206 11:10:19.008563 TX Bit3 (970~991) 22 980, Bit11 (966~986) 21 976,
1207 11:10:19.012002 TX Bit4 (975~995) 21 985, Bit12 (968~989) 22 978,
1208 11:10:19.018513 TX Bit5 (972~994) 23 983, Bit13 (968~989) 22 978,
1209 11:10:19.021959 TX Bit6 (975~994) 20 984, Bit14 (967~990) 24 978,
1210 11:10:19.025663 TX Bit7 (976~995) 20 985, Bit15 (971~991) 21 981,
1211 11:10:19.025747
1212 11:10:19.028447 Write Rank0 MR14 =0x14
1213 11:10:19.037778
1214 11:10:19.037890 CH=0, VrefRange= 0, VrefLevel = 20
1215 11:10:19.044513 TX Bit0 (976~998) 23 987, Bit8 (965~985) 21 975,
1216 11:10:19.048119 TX Bit1 (975~997) 23 986, Bit9 (967~989) 23 978,
1217 11:10:19.054626 TX Bit2 (976~998) 23 987, Bit10 (971~992) 22 981,
1218 11:10:19.057764 TX Bit3 (971~992) 22 981, Bit11 (966~986) 21 976,
1219 11:10:19.061048 TX Bit4 (975~997) 23 986, Bit12 (968~989) 22 978,
1220 11:10:19.067777 TX Bit5 (972~994) 23 983, Bit13 (968~989) 22 978,
1221 11:10:19.071029 TX Bit6 (974~995) 22 984, Bit14 (967~990) 24 978,
1222 11:10:19.074272 TX Bit7 (976~996) 21 986, Bit15 (970~992) 23 981,
1223 11:10:19.074356
1224 11:10:19.078038 Write Rank0 MR14 =0x16
1225 11:10:19.087484
1226 11:10:19.087569 CH=0, VrefRange= 0, VrefLevel = 22
1227 11:10:19.094284 TX Bit0 (976~999) 24 987, Bit8 (964~985) 22 974,
1228 11:10:19.097436 TX Bit1 (975~998) 24 986, Bit9 (967~989) 23 978,
1229 11:10:19.104032 TX Bit2 (976~999) 24 987, Bit10 (970~993) 24 981,
1230 11:10:19.107285 TX Bit3 (970~992) 23 981, Bit11 (966~987) 22 976,
1231 11:10:19.110916 TX Bit4 (975~997) 23 986, Bit12 (968~990) 23 979,
1232 11:10:19.117412 TX Bit5 (972~995) 24 983, Bit13 (967~990) 24 978,
1233 11:10:19.120875 TX Bit6 (974~995) 22 984, Bit14 (967~990) 24 978,
1234 11:10:19.124318 TX Bit7 (976~996) 21 986, Bit15 (970~992) 23 981,
1235 11:10:19.124431
1236 11:10:19.127325 Write Rank0 MR14 =0x18
1237 11:10:19.136683
1238 11:10:19.140307 CH=0, VrefRange= 0, VrefLevel = 24
1239 11:10:19.143361 TX Bit0 (976~999) 24 987, Bit8 (964~986) 23 975,
1240 11:10:19.146663 TX Bit1 (975~998) 24 986, Bit9 (967~990) 24 978,
1241 11:10:19.153542 TX Bit2 (976~999) 24 987, Bit10 (970~993) 24 981,
1242 11:10:19.156999 TX Bit3 (969~993) 25 981, Bit11 (965~988) 24 976,
1243 11:10:19.160246 TX Bit4 (975~998) 24 986, Bit12 (968~990) 23 979,
1244 11:10:19.166800 TX Bit5 (971~995) 25 983, Bit13 (967~990) 24 978,
1245 11:10:19.170459 TX Bit6 (974~996) 23 985, Bit14 (967~991) 25 979,
1246 11:10:19.173458 TX Bit7 (975~998) 24 986, Bit15 (970~992) 23 981,
1247 11:10:19.173571
1248 11:10:19.176779 Write Rank0 MR14 =0x1a
1249 11:10:19.186308
1250 11:10:19.189594 CH=0, VrefRange= 0, VrefLevel = 26
1251 11:10:19.192896 TX Bit0 (976~999) 24 987, Bit8 (963~987) 25 975,
1252 11:10:19.196210 TX Bit1 (975~999) 25 987, Bit9 (967~990) 24 978,
1253 11:10:19.202969 TX Bit2 (976~999) 24 987, Bit10 (970~993) 24 981,
1254 11:10:19.206331 TX Bit3 (969~993) 25 981, Bit11 (965~987) 23 976,
1255 11:10:19.209607 TX Bit4 (974~998) 25 986, Bit12 (968~990) 23 979,
1256 11:10:19.216041 TX Bit5 (971~996) 26 983, Bit13 (967~990) 24 978,
1257 11:10:19.219667 TX Bit6 (974~996) 23 985, Bit14 (967~991) 25 979,
1258 11:10:19.223085 TX Bit7 (975~998) 24 986, Bit15 (970~993) 24 981,
1259 11:10:19.223172
1260 11:10:19.226012 Write Rank0 MR14 =0x1c
1261 11:10:19.235933
1262 11:10:19.236025 CH=0, VrefRange= 0, VrefLevel = 28
1263 11:10:19.242368 TX Bit0 (976~1000) 25 988, Bit8 (964~987) 24 975,
1264 11:10:19.246132 TX Bit1 (975~999) 25 987, Bit9 (967~990) 24 978,
1265 11:10:19.252445 TX Bit2 (976~999) 24 987, Bit10 (969~993) 25 981,
1266 11:10:19.256099 TX Bit3 (969~993) 25 981, Bit11 (965~989) 25 977,
1267 11:10:19.259426 TX Bit4 (975~999) 25 987, Bit12 (967~990) 24 978,
1268 11:10:19.266224 TX Bit5 (970~996) 27 983, Bit13 (967~990) 24 978,
1269 11:10:19.269446 TX Bit6 (973~997) 25 985, Bit14 (967~991) 25 979,
1270 11:10:19.272442 TX Bit7 (975~999) 25 987, Bit15 (969~993) 25 981,
1271 11:10:19.272539
1272 11:10:19.275789 Write Rank0 MR14 =0x1e
1273 11:10:19.285759
1274 11:10:19.285846 CH=0, VrefRange= 0, VrefLevel = 30
1275 11:10:19.292831 TX Bit0 (976~1000) 25 988, Bit8 (964~987) 24 975,
1276 11:10:19.295997 TX Bit1 (975~999) 25 987, Bit9 (967~990) 24 978,
1277 11:10:19.302800 TX Bit2 (976~999) 24 987, Bit10 (969~993) 25 981,
1278 11:10:19.305905 TX Bit3 (969~993) 25 981, Bit11 (965~989) 25 977,
1279 11:10:19.309141 TX Bit4 (975~999) 25 987, Bit12 (967~990) 24 978,
1280 11:10:19.315890 TX Bit5 (970~996) 27 983, Bit13 (967~990) 24 978,
1281 11:10:19.319144 TX Bit6 (973~997) 25 985, Bit14 (967~991) 25 979,
1282 11:10:19.322194 TX Bit7 (975~999) 25 987, Bit15 (969~993) 25 981,
1283 11:10:19.325402
1284 11:10:19.325513 Write Rank0 MR14 =0x20
1285 11:10:19.335658
1286 11:10:19.335770 CH=0, VrefRange= 0, VrefLevel = 32
1287 11:10:19.341964 TX Bit0 (976~1000) 25 988, Bit8 (964~987) 24 975,
1288 11:10:19.345532 TX Bit1 (975~999) 25 987, Bit9 (967~990) 24 978,
1289 11:10:19.352027 TX Bit2 (976~999) 24 987, Bit10 (969~993) 25 981,
1290 11:10:19.355643 TX Bit3 (969~993) 25 981, Bit11 (965~989) 25 977,
1291 11:10:19.358977 TX Bit4 (975~999) 25 987, Bit12 (967~990) 24 978,
1292 11:10:19.365741 TX Bit5 (970~996) 27 983, Bit13 (967~990) 24 978,
1293 11:10:19.368775 TX Bit6 (973~997) 25 985, Bit14 (967~991) 25 979,
1294 11:10:19.372031 TX Bit7 (975~999) 25 987, Bit15 (969~993) 25 981,
1295 11:10:19.372138
1296 11:10:19.375516 Write Rank0 MR14 =0x22
1297 11:10:19.385173
1298 11:10:19.388369 CH=0, VrefRange= 0, VrefLevel = 34
1299 11:10:19.391946 TX Bit0 (976~1000) 25 988, Bit8 (964~987) 24 975,
1300 11:10:19.395292 TX Bit1 (975~999) 25 987, Bit9 (967~990) 24 978,
1301 11:10:19.401620 TX Bit2 (976~999) 24 987, Bit10 (969~993) 25 981,
1302 11:10:19.405173 TX Bit3 (969~993) 25 981, Bit11 (965~989) 25 977,
1303 11:10:19.408391 TX Bit4 (975~999) 25 987, Bit12 (967~990) 24 978,
1304 11:10:19.415122 TX Bit5 (970~996) 27 983, Bit13 (967~990) 24 978,
1305 11:10:19.418463 TX Bit6 (973~997) 25 985, Bit14 (967~991) 25 979,
1306 11:10:19.421913 TX Bit7 (975~999) 25 987, Bit15 (969~993) 25 981,
1307 11:10:19.421996
1308 11:10:19.425032 Write Rank0 MR14 =0x24
1309 11:10:19.434890
1310 11:10:19.438170 CH=0, VrefRange= 0, VrefLevel = 36
1311 11:10:19.441239 TX Bit0 (976~1000) 25 988, Bit8 (964~987) 24 975,
1312 11:10:19.444507 TX Bit1 (975~999) 25 987, Bit9 (967~990) 24 978,
1313 11:10:19.451202 TX Bit2 (976~999) 24 987, Bit10 (969~993) 25 981,
1314 11:10:19.454598 TX Bit3 (969~993) 25 981, Bit11 (965~989) 25 977,
1315 11:10:19.458038 TX Bit4 (975~999) 25 987, Bit12 (967~990) 24 978,
1316 11:10:19.464831 TX Bit5 (970~996) 27 983, Bit13 (967~990) 24 978,
1317 11:10:19.468195 TX Bit6 (973~997) 25 985, Bit14 (967~991) 25 979,
1318 11:10:19.471413 TX Bit7 (975~999) 25 987, Bit15 (969~993) 25 981,
1319 11:10:19.471496
1320 11:10:19.474546
1321 11:10:19.478099 TX Vref found, early break! 372< 377
1322 11:10:19.481274 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
1323 11:10:19.484630 u1DelayCellOfst[0]=9 cells (7 PI)
1324 11:10:19.487998 u1DelayCellOfst[1]=7 cells (6 PI)
1325 11:10:19.491128 u1DelayCellOfst[2]=7 cells (6 PI)
1326 11:10:19.494485 u1DelayCellOfst[3]=0 cells (0 PI)
1327 11:10:19.494568 u1DelayCellOfst[4]=7 cells (6 PI)
1328 11:10:19.498357 u1DelayCellOfst[5]=2 cells (2 PI)
1329 11:10:19.501564 u1DelayCellOfst[6]=5 cells (4 PI)
1330 11:10:19.504734 u1DelayCellOfst[7]=7 cells (6 PI)
1331 11:10:19.508023 Byte0, DQ PI dly=981, DQM PI dly= 984
1332 11:10:19.514860 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
1333 11:10:19.514943
1334 11:10:19.518205 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
1335 11:10:19.518287
1336 11:10:19.521621 u1DelayCellOfst[8]=0 cells (0 PI)
1337 11:10:19.524936 u1DelayCellOfst[9]=3 cells (3 PI)
1338 11:10:19.528291 u1DelayCellOfst[10]=7 cells (6 PI)
1339 11:10:19.531443 u1DelayCellOfst[11]=2 cells (2 PI)
1340 11:10:19.531525 u1DelayCellOfst[12]=3 cells (3 PI)
1341 11:10:19.534746 u1DelayCellOfst[13]=3 cells (3 PI)
1342 11:10:19.538143 u1DelayCellOfst[14]=5 cells (4 PI)
1343 11:10:19.541346 u1DelayCellOfst[15]=7 cells (6 PI)
1344 11:10:19.545039 Byte1, DQ PI dly=975, DQM PI dly= 978
1345 11:10:19.551794 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 15)
1346 11:10:19.551877
1347 11:10:19.554957 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 15)
1348 11:10:19.555040
1349 11:10:19.558147 Write Rank0 MR14 =0x1c
1350 11:10:19.558229
1351 11:10:19.558293 Final TX Range 0 Vref 28
1352 11:10:19.558353
1353 11:10:19.565147 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1354 11:10:19.565230
1355 11:10:19.571587 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1356 11:10:19.578786 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1357 11:10:19.585314 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1358 11:10:19.588201 Write Rank0 MR3 =0xb0
1359 11:10:19.591918 DramC Write-DBI on
1360 11:10:19.592023 ==
1361 11:10:19.595243 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1362 11:10:19.598539 fsp= 1, odt_onoff= 1, Byte mode= 0
1363 11:10:19.598640 ==
1364 11:10:19.601449 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1365 11:10:19.601533
1366 11:10:19.605390 Begin, DQ Scan Range 698~762
1367 11:10:19.605474
1368 11:10:19.605538
1369 11:10:19.608611 TX Vref Scan disable
1370 11:10:19.611750 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1371 11:10:19.615032 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1372 11:10:19.618237 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1373 11:10:19.622191 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1374 11:10:19.625072 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1375 11:10:19.628243 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1376 11:10:19.631587 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1377 11:10:19.635517 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1378 11:10:19.638307 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1379 11:10:19.641597 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1380 11:10:19.645026 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1381 11:10:19.651787 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
1382 11:10:19.655171 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
1383 11:10:19.658196 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
1384 11:10:19.661634 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1385 11:10:19.665160 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1386 11:10:19.668672 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1387 11:10:19.671853 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1388 11:10:19.675049 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1389 11:10:19.678196 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
1390 11:10:19.681777 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
1391 11:10:19.688835 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
1392 11:10:19.692071 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
1393 11:10:19.695619 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1394 11:10:19.699097 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1395 11:10:19.702025 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1396 11:10:19.705464 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1397 11:10:19.708785 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1398 11:10:19.712129 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1399 11:10:19.715923 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
1400 11:10:19.718785 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
1401 11:10:19.722079 745 |2 6 41|[0] xxxxxxxx xxxxxxxx [MSB]
1402 11:10:19.725936 Byte0, DQ PI dly=731, DQM PI dly= 731
1403 11:10:19.728968 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 27)
1404 11:10:19.732223
1405 11:10:19.735646 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 27)
1406 11:10:19.735747
1407 11:10:19.738858 Byte1, DQ PI dly=721, DQM PI dly= 721
1408 11:10:19.742312 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 17)
1409 11:10:19.742417
1410 11:10:19.745459 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 17)
1411 11:10:19.749166
1412 11:10:19.752781 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1413 11:10:19.762303 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1414 11:10:19.769039 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1415 11:10:19.769149 Write Rank0 MR3 =0x30
1416 11:10:19.772328 DramC Write-DBI off
1417 11:10:19.772433
1418 11:10:19.772538 [DATLAT]
1419 11:10:19.775427 Freq=1600, CH0 RK0, use_rxtx_scan=0
1420 11:10:19.775531
1421 11:10:19.778862 DATLAT Default: 0xf
1422 11:10:19.778967 7, 0xFFFF, sum=0
1423 11:10:19.782351 8, 0xFFFF, sum=0
1424 11:10:19.782457 9, 0xFFFF, sum=0
1425 11:10:19.785950 10, 0xFFFF, sum=0
1426 11:10:19.786062 11, 0xFFFF, sum=0
1427 11:10:19.788900 12, 0xFFFF, sum=0
1428 11:10:19.788985 13, 0xFFFF, sum=0
1429 11:10:19.789053 14, 0x0, sum=1
1430 11:10:19.792266 15, 0x0, sum=2
1431 11:10:19.792350 16, 0x0, sum=3
1432 11:10:19.795817 17, 0x0, sum=4
1433 11:10:19.798851 pattern=2 first_step=14 total pass=5 best_step=16
1434 11:10:19.798936 ==
1435 11:10:19.805497 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1436 11:10:19.805581 fsp= 1, odt_onoff= 1, Byte mode= 0
1437 11:10:19.809351 ==
1438 11:10:19.812998 Start DQ dly to find pass range UseTestEngine =1
1439 11:10:19.815579 x-axis: bit #, y-axis: DQ dly (-127~63)
1440 11:10:19.815662 RX Vref Scan = 1
1441 11:10:19.931815
1442 11:10:19.931927 RX Vref found, early break!
1443 11:10:19.931993
1444 11:10:19.938771 Final RX Vref 12, apply to both rank0 and 1
1445 11:10:19.938856 ==
1446 11:10:19.942082 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1447 11:10:19.945537 fsp= 1, odt_onoff= 1, Byte mode= 0
1448 11:10:19.945620 ==
1449 11:10:19.945685 DQS Delay:
1450 11:10:19.948426 DQS0 = 0, DQS1 = 0
1451 11:10:19.948549 DQM Delay:
1452 11:10:19.952366 DQM0 = 19, DQM1 = 19
1453 11:10:19.952489 DQ Delay:
1454 11:10:19.955456 DQ0 =22, DQ1 =20, DQ2 =21, DQ3 =15
1455 11:10:19.958801 DQ4 =21, DQ5 =17, DQ6 =19, DQ7 =20
1456 11:10:19.961778 DQ8 =14, DQ9 =17, DQ10 =25, DQ11 =16
1457 11:10:19.965167 DQ12 =19, DQ13 =18, DQ14 =20, DQ15 =23
1458 11:10:19.965250
1459 11:10:19.965313
1460 11:10:19.965372
1461 11:10:19.969049 [DramC_TX_OE_Calibration] TA2
1462 11:10:19.972062 Original DQ_B0 (3 6) =30, OEN = 27
1463 11:10:19.975173 Original DQ_B1 (3 6) =30, OEN = 27
1464 11:10:19.978786 23, 0x0, End_B0=23 End_B1=23
1465 11:10:19.978871 24, 0x0, End_B0=24 End_B1=24
1466 11:10:19.982161 25, 0x0, End_B0=25 End_B1=25
1467 11:10:19.985329 26, 0x0, End_B0=26 End_B1=26
1468 11:10:19.988684 27, 0x0, End_B0=27 End_B1=27
1469 11:10:19.988775 28, 0x0, End_B0=28 End_B1=28
1470 11:10:19.991945 29, 0x0, End_B0=29 End_B1=29
1471 11:10:19.995406 30, 0x0, End_B0=30 End_B1=30
1472 11:10:19.998694 31, 0xFFFF, End_B0=30 End_B1=30
1473 11:10:20.002018 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1474 11:10:20.008946 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1475 11:10:20.009078
1476 11:10:20.009179
1477 11:10:20.012026 Write Rank0 MR23 =0x3f
1478 11:10:20.012174 [DQSOSC]
1479 11:10:20.022234 [DQSOSCAuto] RK0, (LSB)MR18= 0x1111, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1480 11:10:20.025725 CH0_RK0: MR19=0x303, MR18=0x1111, DQSOSC=401, MR23=63, INC=15, DEC=22
1481 11:10:20.028800 Write Rank0 MR23 =0x3f
1482 11:10:20.029048 [DQSOSC]
1483 11:10:20.039369 [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1484 11:10:20.039754 CH0 RK0: MR19=303, MR18=1313
1485 11:10:20.045891 [RankSwap] Rank num 2, (Multi 1), Rank 1
1486 11:10:20.046272 Write Rank0 MR2 =0xad
1487 11:10:20.048835 [Write Leveling]
1488 11:10:20.049324 delay byte0 byte1 byte2 byte3
1489 11:10:20.052360
1490 11:10:20.052924 10 0 0
1491 11:10:20.053420 11 0 0
1492 11:10:20.056002 12 0 0
1493 11:10:20.056689 13 0 0
1494 11:10:20.058828 14 0 0
1495 11:10:20.059420 15 0 0
1496 11:10:20.059919 16 0 0
1497 11:10:20.062637 17 0 0
1498 11:10:20.062996 18 0 0
1499 11:10:20.065891 19 0 0
1500 11:10:20.066375 20 0 0
1501 11:10:20.069237 21 0 0
1502 11:10:20.069744 22 0 0
1503 11:10:20.070090 23 0 0
1504 11:10:20.072737 24 0 ff
1505 11:10:20.073208 25 0 ff
1506 11:10:20.075617 26 ff ff
1507 11:10:20.076174 27 ff ff
1508 11:10:20.079229 28 ff ff
1509 11:10:20.079615 29 ff ff
1510 11:10:20.082757 30 ff ff
1511 11:10:20.083143 31 ff ff
1512 11:10:20.083510 32 ff ff
1513 11:10:20.089413 pass bytecount = 0xff (0xff: all bytes pass)
1514 11:10:20.089813
1515 11:10:20.090157 DQS0 dly: 26
1516 11:10:20.090440 DQS1 dly: 24
1517 11:10:20.092873 Write Rank0 MR2 =0x2d
1518 11:10:20.095932 [RankSwap] Rank num 2, (Multi 1), Rank 0
1519 11:10:20.099186 Write Rank1 MR1 =0xd6
1520 11:10:20.099582 [Gating]
1521 11:10:20.100078 ==
1522 11:10:20.105931 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1523 11:10:20.106326 fsp= 1, odt_onoff= 1, Byte mode= 0
1524 11:10:20.109084 ==
1525 11:10:20.112506 3 1 0 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1526 11:10:20.115599 3 1 4 |2c2b 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1527 11:10:20.119546 3 1 8 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1528 11:10:20.125787 3 1 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1529 11:10:20.129369 3 1 16 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1530 11:10:20.132634 3 1 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1531 11:10:20.138946 3 1 24 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1532 11:10:20.142275 3 1 28 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1533 11:10:20.145990 3 2 0 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1534 11:10:20.152232 3 2 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1535 11:10:20.155825 3 2 8 |1211 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1536 11:10:20.158908 3 2 12 |3534 1716 |(11 11)(11 11) |(0 0)(1 1)| 0
1537 11:10:20.166061 3 2 16 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1538 11:10:20.169415 3 2 20 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1539 11:10:20.172811 3 2 24 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1540 11:10:20.179261 3 2 28 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1541 11:10:20.182489 3 3 0 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1542 11:10:20.185964 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1543 11:10:20.189398 3 3 8 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1544 11:10:20.195763 3 3 12 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1545 11:10:20.199110 3 3 16 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1546 11:10:20.202530 3 3 20 |3534 c0b |(11 11)(11 11) |(0 0)(1 1)| 0
1547 11:10:20.209630 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1548 11:10:20.212752 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1549 11:10:20.216046 [Byte 1] Lead/lag falling Transition (3, 3, 28)
1550 11:10:20.219191 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1551 11:10:20.226429 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1552 11:10:20.229336 3 4 8 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1553 11:10:20.232560 3 4 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1554 11:10:20.239240 3 4 16 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
1555 11:10:20.242710 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1556 11:10:20.246046 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1557 11:10:20.252760 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1558 11:10:20.256099 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1559 11:10:20.259825 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1560 11:10:20.262581 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1561 11:10:20.269522 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1562 11:10:20.272624 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1563 11:10:20.275986 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1564 11:10:20.282657 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1565 11:10:20.286052 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1566 11:10:20.289231 [Byte 0] Lead/lag falling Transition (3, 5, 28)
1567 11:10:20.295879 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1568 11:10:20.299448 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1569 11:10:20.302677 [Byte 0] Lead/lag Transition tap number (3)
1570 11:10:20.305924 [Byte 1] Lead/lag falling Transition (3, 6, 4)
1571 11:10:20.312580 3 6 8 |404 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
1572 11:10:20.316358 [Byte 1] Lead/lag Transition tap number (2)
1573 11:10:20.319501 3 6 12 |4646 3e3d |(0 0)(11 11) |(0 0)(0 0)| 0
1574 11:10:20.322890 [Byte 0]First pass (3, 6, 12)
1575 11:10:20.326019 3 6 16 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
1576 11:10:20.329739 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1577 11:10:20.332877 [Byte 1]First pass (3, 6, 20)
1578 11:10:20.336160 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1579 11:10:20.339524 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1580 11:10:20.346260 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1581 11:10:20.349481 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1582 11:10:20.353278 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1583 11:10:20.356451 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1584 11:10:20.359485 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1585 11:10:20.366094 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1586 11:10:20.369761 All bytes gating window > 1UI, Early break!
1587 11:10:20.370146
1588 11:10:20.372833 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 2)
1589 11:10:20.373312
1590 11:10:20.376085 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 8)
1591 11:10:20.376616
1592 11:10:20.376930
1593 11:10:20.377206
1594 11:10:20.379387 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 2)
1595 11:10:20.379773
1596 11:10:20.386428 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
1597 11:10:20.386998
1598 11:10:20.387364
1599 11:10:20.387512 Write Rank1 MR1 =0x56
1600 11:10:20.387630
1601 11:10:20.389317 best RODT dly(2T, 0.5T) = (2, 3)
1602 11:10:20.389541
1603 11:10:20.392613 best RODT dly(2T, 0.5T) = (2, 3)
1604 11:10:20.392782 ==
1605 11:10:20.399726 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1606 11:10:20.402725 fsp= 1, odt_onoff= 1, Byte mode= 0
1607 11:10:20.402943 ==
1608 11:10:20.406230 Start DQ dly to find pass range UseTestEngine =0
1609 11:10:20.409695 x-axis: bit #, y-axis: DQ dly (-127~63)
1610 11:10:20.409843 RX Vref Scan = 0
1611 11:10:20.412845 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1612 11:10:20.416162 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1613 11:10:20.419294 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1614 11:10:20.423121 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1615 11:10:20.426515 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1616 11:10:20.429661 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1617 11:10:20.432949 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1618 11:10:20.433064 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1619 11:10:20.436009 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1620 11:10:20.439737 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1621 11:10:20.443164 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1622 11:10:20.446400 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1623 11:10:20.449740 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1624 11:10:20.453040 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1625 11:10:20.456214 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1626 11:10:20.459420 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1627 11:10:20.459613 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1628 11:10:20.462707 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1629 11:10:20.465999 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1630 11:10:20.469101 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1631 11:10:20.473051 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1632 11:10:20.476151 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1633 11:10:20.479569 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1634 11:10:20.479697 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1635 11:10:20.482531 -2, [0] xxxxxxxx oxxoxxxx [MSB]
1636 11:10:20.486203 -1, [0] xxxoxxxx oxxoxxxx [MSB]
1637 11:10:20.489544 0, [0] xxxoxxxx oxxoxxxx [MSB]
1638 11:10:20.492610 1, [0] xxxoxoxx ooxoooxx [MSB]
1639 11:10:20.496141 2, [0] xxxoxooo ooxoooxx [MSB]
1640 11:10:20.496268 3, [0] xxxooooo ooxoooox [MSB]
1641 11:10:20.499507 4, [0] xooooooo ooxoooox [MSB]
1642 11:10:20.502461 5, [0] oooooooo ooxooooo [MSB]
1643 11:10:20.505843 6, [0] oooooooo ooxooooo [MSB]
1644 11:10:20.509181 33, [0] oooooooo xooooooo [MSB]
1645 11:10:20.512820 34, [0] oooxoooo xooooooo [MSB]
1646 11:10:20.512968 35, [0] oooxoooo xooooooo [MSB]
1647 11:10:20.515926 36, [0] oooxoooo xooxoooo [MSB]
1648 11:10:20.519666 37, [0] oooxoxoo xxoxoxoo [MSB]
1649 11:10:20.523137 38, [0] oooxoxoo xxoxoxxo [MSB]
1650 11:10:20.526343 39, [0] oooxoxxx xxoxxxxo [MSB]
1651 11:10:20.529483 40, [0] oooxoxxx xxoxxxxo [MSB]
1652 11:10:20.532975 41, [0] oxxxxxxx xxoxxxxx [MSB]
1653 11:10:20.533101 42, [0] oxxxxxxx xxoxxxxx [MSB]
1654 11:10:20.536545 43, [0] xxxxxxxx xxoxxxxx [MSB]
1655 11:10:20.539694 44, [0] xxxxxxxx xxoxxxxx [MSB]
1656 11:10:20.542766 45, [0] xxxxxxxx xxxxxxxx [MSB]
1657 11:10:20.546739 iDelay=45, Bit 0, Center 23 (5 ~ 42) 38
1658 11:10:20.549430 iDelay=45, Bit 1, Center 22 (4 ~ 40) 37
1659 11:10:20.553438 iDelay=45, Bit 2, Center 22 (4 ~ 40) 37
1660 11:10:20.556256 iDelay=45, Bit 3, Center 16 (-1 ~ 33) 35
1661 11:10:20.559957 iDelay=45, Bit 4, Center 21 (3 ~ 40) 38
1662 11:10:20.563112 iDelay=45, Bit 5, Center 18 (1 ~ 36) 36
1663 11:10:20.566450 iDelay=45, Bit 6, Center 20 (2 ~ 38) 37
1664 11:10:20.570032 iDelay=45, Bit 7, Center 20 (2 ~ 38) 37
1665 11:10:20.573119 iDelay=45, Bit 8, Center 15 (-2 ~ 32) 35
1666 11:10:20.576614 iDelay=45, Bit 9, Center 18 (1 ~ 36) 36
1667 11:10:20.583684 iDelay=45, Bit 10, Center 25 (7 ~ 44) 38
1668 11:10:20.586997 iDelay=45, Bit 11, Center 16 (-2 ~ 35) 38
1669 11:10:20.590157 iDelay=45, Bit 12, Center 19 (1 ~ 38) 38
1670 11:10:20.593607 iDelay=45, Bit 13, Center 18 (1 ~ 36) 36
1671 11:10:20.596722 iDelay=45, Bit 14, Center 20 (3 ~ 37) 35
1672 11:10:20.600028 iDelay=45, Bit 15, Center 22 (5 ~ 40) 36
1673 11:10:20.600112 ==
1674 11:10:20.606479 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1675 11:10:20.606567 fsp= 1, odt_onoff= 1, Byte mode= 0
1676 11:10:20.609971 ==
1677 11:10:20.610055 DQS Delay:
1678 11:10:20.610120 DQS0 = 0, DQS1 = 0
1679 11:10:20.613702 DQM Delay:
1680 11:10:20.613786 DQM0 = 20, DQM1 = 19
1681 11:10:20.616465 DQ Delay:
1682 11:10:20.619875 DQ0 =23, DQ1 =22, DQ2 =22, DQ3 =16
1683 11:10:20.619961 DQ4 =21, DQ5 =18, DQ6 =20, DQ7 =20
1684 11:10:20.623469 DQ8 =15, DQ9 =18, DQ10 =25, DQ11 =16
1685 11:10:20.626735 DQ12 =19, DQ13 =18, DQ14 =20, DQ15 =22
1686 11:10:20.626820
1687 11:10:20.630196
1688 11:10:20.630288 DramC Write-DBI off
1689 11:10:20.630366 ==
1690 11:10:20.636594 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1691 11:10:20.640110 fsp= 1, odt_onoff= 1, Byte mode= 0
1692 11:10:20.640195 ==
1693 11:10:20.643703 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1694 11:10:20.643788
1695 11:10:20.646934 Begin, DQ Scan Range 920~1176
1696 11:10:20.647018
1697 11:10:20.647083
1698 11:10:20.650136 TX Vref Scan disable
1699 11:10:20.653340 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1700 11:10:20.656849 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1701 11:10:20.660115 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1702 11:10:20.663326 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1703 11:10:20.667114 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1704 11:10:20.670290 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1705 11:10:20.673443 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1706 11:10:20.677130 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1707 11:10:20.680420 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1708 11:10:20.683839 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1709 11:10:20.687087 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1710 11:10:20.690433 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1711 11:10:20.693566 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1712 11:10:20.696689 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1713 11:10:20.700173 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1714 11:10:20.703406 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1715 11:10:20.710192 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1716 11:10:20.713673 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1717 11:10:20.716640 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1718 11:10:20.720565 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1719 11:10:20.723552 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1720 11:10:20.726974 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1721 11:10:20.730120 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1722 11:10:20.733158 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1723 11:10:20.736746 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1724 11:10:20.740209 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1725 11:10:20.743487 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1726 11:10:20.747093 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1727 11:10:20.749965 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1728 11:10:20.753408 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1729 11:10:20.756467 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1730 11:10:20.759909 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1731 11:10:20.766923 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1732 11:10:20.770049 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1733 11:10:20.773363 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1734 11:10:20.776602 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1735 11:10:20.780279 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1736 11:10:20.783419 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1737 11:10:20.786690 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1738 11:10:20.790167 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1739 11:10:20.793416 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1740 11:10:20.797260 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1741 11:10:20.799987 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1742 11:10:20.803530 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1743 11:10:20.806676 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1744 11:10:20.809921 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1745 11:10:20.813633 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1746 11:10:20.816933 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1747 11:10:20.820433 968 |3 6 8|[0] xxxxxxxx oxxoxxxx [MSB]
1748 11:10:20.823964 969 |3 6 9|[0] xxxxxxxx ooxooxxx [MSB]
1749 11:10:20.827235 970 |3 6 10|[0] xxxxxxxx ooxooxox [MSB]
1750 11:10:20.830450 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1751 11:10:20.833528 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1752 11:10:20.837239 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1753 11:10:20.843716 974 |3 6 14|[0] xoxooooo ooxooooo [MSB]
1754 11:10:20.847566 975 |3 6 15|[0] xoxooooo oooooooo [MSB]
1755 11:10:20.850584 987 |3 6 27|[0] oooooooo xooooooo [MSB]
1756 11:10:20.853696 988 |3 6 28|[0] oooooooo xxxxxxxx [MSB]
1757 11:10:20.857386 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1758 11:10:20.860382 990 |3 6 30|[0] oooxoooo xxxxxxxx [MSB]
1759 11:10:20.863862 991 |3 6 31|[0] oooxoooo xxxxxxxx [MSB]
1760 11:10:20.867260 992 |3 6 32|[0] xxxxxxxx xxxxxxxx [MSB]
1761 11:10:20.870437 Byte0, DQ PI dly=982, DQM PI dly= 982
1762 11:10:20.877430 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
1763 11:10:20.877819
1764 11:10:20.880553 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
1765 11:10:20.880944
1766 11:10:20.883763 Byte1, DQ PI dly=979, DQM PI dly= 979
1767 11:10:20.887385 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1768 11:10:20.890450
1769 11:10:20.894264 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1770 11:10:20.894654
1771 11:10:20.894952 ==
1772 11:10:20.897531 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1773 11:10:20.900832 fsp= 1, odt_onoff= 1, Byte mode= 0
1774 11:10:20.901312 ==
1775 11:10:20.907503 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1776 11:10:20.908027
1777 11:10:20.910450 Begin, DQ Scan Range 955~1019
1778 11:10:20.913613 wait MRW command Rank1 MR14 =0x0 fired (1)
1779 11:10:20.914121 Write Rank1 MR14 =0x0
1780 11:10:20.922287
1781 11:10:20.922760 CH=0, VrefRange= 0, VrefLevel = 0
1782 11:10:20.929009 TX Bit0 (977~991) 15 984, Bit8 (969~982) 14 975,
1783 11:10:20.932181 TX Bit1 (976~987) 12 981, Bit9 (970~985) 16 977,
1784 11:10:20.939276 TX Bit2 (977~990) 14 983, Bit10 (977~986) 10 981,
1785 11:10:20.942608 TX Bit3 (970~983) 14 976, Bit11 (970~983) 14 976,
1786 11:10:20.945668 TX Bit4 (976~989) 14 982, Bit12 (974~985) 12 979,
1787 11:10:20.952507 TX Bit5 (973~986) 14 979, Bit13 (974~982) 9 978,
1788 11:10:20.956095 TX Bit6 (975~988) 14 981, Bit14 (974~984) 11 979,
1789 11:10:20.959179 TX Bit7 (976~990) 15 983, Bit15 (976~986) 11 981,
1790 11:10:20.959571
1791 11:10:20.962296 Write Rank1 MR14 =0x2
1792 11:10:20.970271
1793 11:10:20.970705 CH=0, VrefRange= 0, VrefLevel = 2
1794 11:10:20.976865 TX Bit0 (977~991) 15 984, Bit8 (969~982) 14 975,
1795 11:10:20.979888 TX Bit1 (976~988) 13 982, Bit9 (970~985) 16 977,
1796 11:10:20.987088 TX Bit2 (977~990) 14 983, Bit10 (976~990) 15 983,
1797 11:10:20.990387 TX Bit3 (970~983) 14 976, Bit11 (970~983) 14 976,
1798 11:10:20.993510 TX Bit4 (976~990) 15 983, Bit12 (972~985) 14 978,
1799 11:10:21.000189 TX Bit5 (973~986) 14 979, Bit13 (974~983) 10 978,
1800 11:10:21.003418 TX Bit6 (975~989) 15 982, Bit14 (973~985) 13 979,
1801 11:10:21.007161 TX Bit7 (975~990) 16 982, Bit15 (976~990) 15 983,
1802 11:10:21.007547
1803 11:10:21.010432 Write Rank1 MR14 =0x4
1804 11:10:21.017977
1805 11:10:21.018359 CH=0, VrefRange= 0, VrefLevel = 4
1806 11:10:21.024674 TX Bit0 (977~992) 16 984, Bit8 (969~983) 15 976,
1807 11:10:21.028026 TX Bit1 (976~989) 14 982, Bit9 (970~985) 16 977,
1808 11:10:21.034545 TX Bit2 (977~991) 15 984, Bit10 (976~990) 15 983,
1809 11:10:21.037872 TX Bit3 (970~984) 15 977, Bit11 (970~983) 14 976,
1810 11:10:21.041197 TX Bit4 (975~990) 16 982, Bit12 (971~986) 16 978,
1811 11:10:21.047754 TX Bit5 (972~988) 17 980, Bit13 (973~984) 12 978,
1812 11:10:21.051424 TX Bit6 (974~990) 17 982, Bit14 (973~986) 14 979,
1813 11:10:21.054483 TX Bit7 (975~991) 17 983, Bit15 (975~990) 16 982,
1814 11:10:21.054955
1815 11:10:21.057637 Write Rank1 MR14 =0x6
1816 11:10:21.065657
1817 11:10:21.066034 CH=0, VrefRange= 0, VrefLevel = 6
1818 11:10:21.072256 TX Bit0 (976~992) 17 984, Bit8 (968~984) 17 976,
1819 11:10:21.075870 TX Bit1 (976~990) 15 983, Bit9 (970~986) 17 978,
1820 11:10:21.079200 TX Bit2 (977~991) 15 984, Bit10 (976~991) 16 983,
1821 11:10:21.085718 TX Bit3 (969~985) 17 977, Bit11 (969~984) 16 976,
1822 11:10:21.089513 TX Bit4 (975~991) 17 983, Bit12 (971~987) 17 979,
1823 11:10:21.095847 TX Bit5 (971~988) 18 979, Bit13 (973~984) 12 978,
1824 11:10:21.099191 TX Bit6 (973~990) 18 981, Bit14 (973~987) 15 980,
1825 11:10:21.102604 TX Bit7 (975~991) 17 983, Bit15 (975~991) 17 983,
1826 11:10:21.103095
1827 11:10:21.105967 Write Rank1 MR14 =0x8
1828 11:10:21.113489
1829 11:10:21.113870 CH=0, VrefRange= 0, VrefLevel = 8
1830 11:10:21.120870 TX Bit0 (976~993) 18 984, Bit8 (969~984) 16 976,
1831 11:10:21.123468 TX Bit1 (976~991) 16 983, Bit9 (970~987) 18 978,
1832 11:10:21.130478 TX Bit2 (976~991) 16 983, Bit10 (976~991) 16 983,
1833 11:10:21.133979 TX Bit3 (970~986) 17 978, Bit11 (969~984) 16 976,
1834 11:10:21.137195 TX Bit4 (975~991) 17 983, Bit12 (970~987) 18 978,
1835 11:10:21.143869 TX Bit5 (971~989) 19 980, Bit13 (973~985) 13 979,
1836 11:10:21.147022 TX Bit6 (973~990) 18 981, Bit14 (971~988) 18 979,
1837 11:10:21.150646 TX Bit7 (974~991) 18 982, Bit15 (975~991) 17 983,
1838 11:10:21.151032
1839 11:10:21.153929 Write Rank1 MR14 =0xa
1840 11:10:21.161588
1841 11:10:21.164908 CH=0, VrefRange= 0, VrefLevel = 10
1842 11:10:21.168587 TX Bit0 (976~993) 18 984, Bit8 (968~985) 18 976,
1843 11:10:21.171613 TX Bit1 (975~991) 17 983, Bit9 (969~988) 20 978,
1844 11:10:21.178173 TX Bit2 (976~992) 17 984, Bit10 (976~992) 17 984,
1845 11:10:21.181931 TX Bit3 (969~987) 19 978, Bit11 (968~985) 18 976,
1846 11:10:21.185102 TX Bit4 (974~992) 19 983, Bit12 (970~989) 20 979,
1847 11:10:21.191654 TX Bit5 (971~990) 20 980, Bit13 (971~985) 15 978,
1848 11:10:21.195005 TX Bit6 (972~991) 20 981, Bit14 (971~989) 19 980,
1849 11:10:21.198492 TX Bit7 (974~992) 19 983, Bit15 (975~991) 17 983,
1850 11:10:21.199008
1851 11:10:21.201721 Write Rank1 MR14 =0xc
1852 11:10:21.209602
1853 11:10:21.213346 CH=0, VrefRange= 0, VrefLevel = 12
1854 11:10:21.216425 TX Bit0 (976~993) 18 984, Bit8 (968~985) 18 976,
1855 11:10:21.219789 TX Bit1 (975~992) 18 983, Bit9 (969~988) 20 978,
1856 11:10:21.226329 TX Bit2 (976~992) 17 984, Bit10 (975~992) 18 983,
1857 11:10:21.230007 TX Bit3 (969~987) 19 978, Bit11 (969~986) 18 977,
1858 11:10:21.233457 TX Bit4 (974~992) 19 983, Bit12 (970~989) 20 979,
1859 11:10:21.240090 TX Bit5 (970~990) 21 980, Bit13 (971~986) 16 978,
1860 11:10:21.243500 TX Bit6 (972~991) 20 981, Bit14 (971~989) 19 980,
1861 11:10:21.246525 TX Bit7 (973~992) 20 982, Bit15 (975~992) 18 983,
1862 11:10:21.246917
1863 11:10:21.250032 Write Rank1 MR14 =0xe
1864 11:10:21.257945
1865 11:10:21.261536 CH=0, VrefRange= 0, VrefLevel = 14
1866 11:10:21.264568 TX Bit0 (975~994) 20 984, Bit8 (968~985) 18 976,
1867 11:10:21.267865 TX Bit1 (975~992) 18 983, Bit9 (969~989) 21 979,
1868 11:10:21.274862 TX Bit2 (976~993) 18 984, Bit10 (975~992) 18 983,
1869 11:10:21.278027 TX Bit3 (969~988) 20 978, Bit11 (968~986) 19 977,
1870 11:10:21.281287 TX Bit4 (973~992) 20 982, Bit12 (970~989) 20 979,
1871 11:10:21.287974 TX Bit5 (970~990) 21 980, Bit13 (971~987) 17 979,
1872 11:10:21.291756 TX Bit6 (971~991) 21 981, Bit14 (970~990) 21 980,
1873 11:10:21.295086 TX Bit7 (973~992) 20 982, Bit15 (974~992) 19 983,
1874 11:10:21.295658
1875 11:10:21.298158 Write Rank1 MR14 =0x10
1876 11:10:21.306339
1877 11:10:21.306972 CH=0, VrefRange= 0, VrefLevel = 16
1878 11:10:21.313552 TX Bit0 (975~995) 21 985, Bit8 (967~986) 20 976,
1879 11:10:21.316563 TX Bit1 (974~992) 19 983, Bit9 (969~990) 22 979,
1880 11:10:21.323458 TX Bit2 (976~993) 18 984, Bit10 (975~993) 19 984,
1881 11:10:21.326800 TX Bit3 (969~989) 21 979, Bit11 (968~986) 19 977,
1882 11:10:21.330103 TX Bit4 (973~993) 21 983, Bit12 (970~990) 21 980,
1883 11:10:21.336574 TX Bit5 (970~991) 22 980, Bit13 (970~988) 19 979,
1884 11:10:21.340023 TX Bit6 (971~992) 22 981, Bit14 (970~990) 21 980,
1885 11:10:21.343580 TX Bit7 (972~993) 22 982, Bit15 (974~993) 20 983,
1886 11:10:21.343970
1887 11:10:21.346599 Write Rank1 MR14 =0x12
1888 11:10:21.354844
1889 11:10:21.358124 CH=0, VrefRange= 0, VrefLevel = 18
1890 11:10:21.361816 TX Bit0 (975~995) 21 985, Bit8 (967~987) 21 977,
1891 11:10:21.365290 TX Bit1 (974~993) 20 983, Bit9 (969~990) 22 979,
1892 11:10:21.371634 TX Bit2 (976~994) 19 985, Bit10 (974~993) 20 983,
1893 11:10:21.375109 TX Bit3 (968~990) 23 979, Bit11 (968~987) 20 977,
1894 11:10:21.378087 TX Bit4 (972~993) 22 982, Bit12 (969~990) 22 979,
1895 11:10:21.384949 TX Bit5 (970~991) 22 980, Bit13 (970~989) 20 979,
1896 11:10:21.388284 TX Bit6 (971~992) 22 981, Bit14 (969~991) 23 980,
1897 11:10:21.391427 TX Bit7 (972~993) 22 982, Bit15 (973~993) 21 983,
1898 11:10:21.391960
1899 11:10:21.395408 Write Rank1 MR14 =0x14
1900 11:10:21.403756
1901 11:10:21.407156 CH=0, VrefRange= 0, VrefLevel = 20
1902 11:10:21.410413 TX Bit0 (975~996) 22 985, Bit8 (967~988) 22 977,
1903 11:10:21.413591 TX Bit1 (974~994) 21 984, Bit9 (968~990) 23 979,
1904 11:10:21.420411 TX Bit2 (975~994) 20 984, Bit10 (974~994) 21 984,
1905 11:10:21.423227 TX Bit3 (968~990) 23 979, Bit11 (968~989) 22 978,
1906 11:10:21.426957 TX Bit4 (972~994) 23 983, Bit12 (969~991) 23 980,
1907 11:10:21.433403 TX Bit5 (970~991) 22 980, Bit13 (970~989) 20 979,
1908 11:10:21.436580 TX Bit6 (970~992) 23 981, Bit14 (969~991) 23 980,
1909 11:10:21.440442 TX Bit7 (971~994) 24 982, Bit15 (973~994) 22 983,
1910 11:10:21.440852
1911 11:10:21.443252 Write Rank1 MR14 =0x16
1912 11:10:21.452439
1913 11:10:21.455723 CH=0, VrefRange= 0, VrefLevel = 22
1914 11:10:21.458966 TX Bit0 (975~997) 23 986, Bit8 (967~989) 23 978,
1915 11:10:21.462185 TX Bit1 (973~994) 22 983, Bit9 (968~991) 24 979,
1916 11:10:21.468803 TX Bit2 (975~995) 21 985, Bit10 (974~995) 22 984,
1917 11:10:21.472067 TX Bit3 (968~990) 23 979, Bit11 (967~989) 23 978,
1918 11:10:21.475518 TX Bit4 (972~994) 23 983, Bit12 (969~991) 23 980,
1919 11:10:21.482238 TX Bit5 (969~992) 24 980, Bit13 (969~990) 22 979,
1920 11:10:21.485544 TX Bit6 (970~993) 24 981, Bit14 (969~991) 23 980,
1921 11:10:21.489120 TX Bit7 (971~994) 24 982, Bit15 (973~994) 22 983,
1922 11:10:21.489662
1923 11:10:21.492230 Write Rank1 MR14 =0x18
1924 11:10:21.501362
1925 11:10:21.501845 CH=0, VrefRange= 0, VrefLevel = 24
1926 11:10:21.507987 TX Bit0 (975~997) 23 986, Bit8 (967~989) 23 978,
1927 11:10:21.510918 TX Bit1 (973~995) 23 984, Bit9 (968~991) 24 979,
1928 11:10:21.517926 TX Bit2 (975~996) 22 985, Bit10 (974~995) 22 984,
1929 11:10:21.521085 TX Bit3 (968~991) 24 979, Bit11 (967~990) 24 978,
1930 11:10:21.524389 TX Bit4 (971~994) 24 982, Bit12 (968~991) 24 979,
1931 11:10:21.531287 TX Bit5 (969~992) 24 980, Bit13 (969~990) 22 979,
1932 11:10:21.535298 TX Bit6 (970~993) 24 981, Bit14 (969~991) 23 980,
1933 11:10:21.537910 TX Bit7 (971~995) 25 983, Bit15 (973~995) 23 984,
1934 11:10:21.538294
1935 11:10:21.541204 Write Rank1 MR14 =0x1a
1936 11:10:21.550019
1937 11:10:21.553701 CH=0, VrefRange= 0, VrefLevel = 26
1938 11:10:21.556757 TX Bit0 (974~998) 25 986, Bit8 (966~990) 25 978,
1939 11:10:21.560158 TX Bit1 (973~995) 23 984, Bit9 (968~991) 24 979,
1940 11:10:21.567055 TX Bit2 (974~996) 23 985, Bit10 (973~996) 24 984,
1941 11:10:21.570162 TX Bit3 (967~991) 25 979, Bit11 (967~990) 24 978,
1942 11:10:21.573549 TX Bit4 (971~995) 25 983, Bit12 (969~992) 24 980,
1943 11:10:21.580323 TX Bit5 (969~992) 24 980, Bit13 (969~990) 22 979,
1944 11:10:21.583588 TX Bit6 (970~994) 25 982, Bit14 (969~992) 24 980,
1945 11:10:21.586827 TX Bit7 (971~995) 25 983, Bit15 (971~995) 25 983,
1946 11:10:21.587217
1947 11:10:21.593679 wait MRW command Rank1 MR14 =0x1c fired (1)
1948 11:10:21.594195 Write Rank1 MR14 =0x1c
1949 11:10:21.602724
1950 11:10:21.605985 CH=0, VrefRange= 0, VrefLevel = 28
1951 11:10:21.609864 TX Bit0 (974~998) 25 986, Bit8 (966~990) 25 978,
1952 11:10:21.612994 TX Bit1 (972~995) 24 983, Bit9 (968~991) 24 979,
1953 11:10:21.619426 TX Bit2 (975~997) 23 986, Bit10 (972~997) 26 984,
1954 11:10:21.622958 TX Bit3 (967~991) 25 979, Bit11 (967~990) 24 978,
1955 11:10:21.626193 TX Bit4 (971~996) 26 983, Bit12 (968~992) 25 980,
1956 11:10:21.632973 TX Bit5 (969~992) 24 980, Bit13 (969~991) 23 980,
1957 11:10:21.636697 TX Bit6 (970~994) 25 982, Bit14 (968~992) 25 980,
1958 11:10:21.639617 TX Bit7 (970~996) 27 983, Bit15 (971~995) 25 983,
1959 11:10:21.640129
1960 11:10:21.642980 Write Rank1 MR14 =0x1e
1961 11:10:21.652070
1962 11:10:21.655564 CH=0, VrefRange= 0, VrefLevel = 30
1963 11:10:21.658711 TX Bit0 (973~998) 26 985, Bit8 (966~990) 25 978,
1964 11:10:21.661930 TX Bit1 (972~996) 25 984, Bit9 (968~991) 24 979,
1965 11:10:21.668942 TX Bit2 (974~997) 24 985, Bit10 (972~997) 26 984,
1966 11:10:21.671554 TX Bit3 (967~991) 25 979, Bit11 (967~991) 25 979,
1967 11:10:21.675390 TX Bit4 (970~996) 27 983, Bit12 (968~992) 25 980,
1968 11:10:21.681998 TX Bit5 (969~993) 25 981, Bit13 (969~991) 23 980,
1969 11:10:21.685356 TX Bit6 (969~995) 27 982, Bit14 (968~992) 25 980,
1970 11:10:21.688755 TX Bit7 (971~996) 26 983, Bit15 (972~996) 25 984,
1971 11:10:21.689315
1972 11:10:21.695238 wait MRW command Rank1 MR14 =0x20 fired (1)
1973 11:10:21.695769 Write Rank1 MR14 =0x20
1974 11:10:21.704284
1975 11:10:21.707737 CH=0, VrefRange= 0, VrefLevel = 32
1976 11:10:21.711111 TX Bit0 (974~998) 25 986, Bit8 (967~990) 24 978,
1977 11:10:21.714444 TX Bit1 (972~996) 25 984, Bit9 (968~990) 23 979,
1978 11:10:21.721316 TX Bit2 (974~998) 25 986, Bit10 (972~997) 26 984,
1979 11:10:21.724684 TX Bit3 (968~991) 24 979, Bit11 (966~990) 25 978,
1980 11:10:21.727842 TX Bit4 (970~997) 28 983, Bit12 (968~992) 25 980,
1981 11:10:21.734566 TX Bit5 (968~993) 26 980, Bit13 (968~991) 24 979,
1982 11:10:21.737856 TX Bit6 (969~995) 27 982, Bit14 (968~992) 25 980,
1983 11:10:21.741153 TX Bit7 (971~997) 27 984, Bit15 (971~995) 25 983,
1984 11:10:21.741582
1985 11:10:21.744718 Write Rank1 MR14 =0x22
1986 11:10:21.753726
1987 11:10:21.754256 CH=0, VrefRange= 0, VrefLevel = 34
1988 11:10:21.760038 TX Bit0 (974~998) 25 986, Bit8 (967~990) 24 978,
1989 11:10:21.763659 TX Bit1 (972~996) 25 984, Bit9 (968~990) 23 979,
1990 11:10:21.770295 TX Bit2 (974~998) 25 986, Bit10 (972~997) 26 984,
1991 11:10:21.773502 TX Bit3 (968~991) 24 979, Bit11 (966~990) 25 978,
1992 11:10:21.777064 TX Bit4 (970~997) 28 983, Bit12 (968~992) 25 980,
1993 11:10:21.783650 TX Bit5 (968~993) 26 980, Bit13 (968~991) 24 979,
1994 11:10:21.787057 TX Bit6 (969~995) 27 982, Bit14 (968~992) 25 980,
1995 11:10:21.790415 TX Bit7 (971~997) 27 984, Bit15 (971~995) 25 983,
1996 11:10:21.790930
1997 11:10:21.793804 Write Rank1 MR14 =0x24
1998 11:10:21.802423
1999 11:10:21.802947 CH=0, VrefRange= 0, VrefLevel = 36
2000 11:10:21.809252 TX Bit0 (974~998) 25 986, Bit8 (967~990) 24 978,
2001 11:10:21.812546 TX Bit1 (972~996) 25 984, Bit9 (968~990) 23 979,
2002 11:10:21.818979 TX Bit2 (974~998) 25 986, Bit10 (972~997) 26 984,
2003 11:10:21.822773 TX Bit3 (968~991) 24 979, Bit11 (966~990) 25 978,
2004 11:10:21.825611 TX Bit4 (970~997) 28 983, Bit12 (968~992) 25 980,
2005 11:10:21.832264 TX Bit5 (968~993) 26 980, Bit13 (968~991) 24 979,
2006 11:10:21.835510 TX Bit6 (969~995) 27 982, Bit14 (968~992) 25 980,
2007 11:10:21.839021 TX Bit7 (971~997) 27 984, Bit15 (971~995) 25 983,
2008 11:10:21.839529
2009 11:10:21.842245 Write Rank1 MR14 =0x26
2010 11:10:21.851176
2011 11:10:21.854320 CH=0, VrefRange= 0, VrefLevel = 38
2012 11:10:21.857998 TX Bit0 (974~998) 25 986, Bit8 (967~990) 24 978,
2013 11:10:21.861254 TX Bit1 (972~996) 25 984, Bit9 (968~990) 23 979,
2014 11:10:21.867783 TX Bit2 (974~998) 25 986, Bit10 (972~997) 26 984,
2015 11:10:21.871131 TX Bit3 (968~991) 24 979, Bit11 (966~990) 25 978,
2016 11:10:21.874260 TX Bit4 (970~997) 28 983, Bit12 (968~992) 25 980,
2017 11:10:21.881355 TX Bit5 (968~993) 26 980, Bit13 (968~991) 24 979,
2018 11:10:21.884435 TX Bit6 (969~995) 27 982, Bit14 (968~992) 25 980,
2019 11:10:21.887946 TX Bit7 (971~997) 27 984, Bit15 (971~995) 25 983,
2020 11:10:21.888331
2021 11:10:21.888745
2022 11:10:21.891388 TX Vref found, early break! 377< 383
2023 11:10:21.898334 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
2024 11:10:21.901185 u1DelayCellOfst[0]=9 cells (7 PI)
2025 11:10:21.905002 u1DelayCellOfst[1]=6 cells (5 PI)
2026 11:10:21.908171 u1DelayCellOfst[2]=9 cells (7 PI)
2027 11:10:21.908609 u1DelayCellOfst[3]=0 cells (0 PI)
2028 11:10:21.911534 u1DelayCellOfst[4]=5 cells (4 PI)
2029 11:10:21.914698 u1DelayCellOfst[5]=1 cells (1 PI)
2030 11:10:21.918102 u1DelayCellOfst[6]=3 cells (3 PI)
2031 11:10:21.921447 u1DelayCellOfst[7]=6 cells (5 PI)
2032 11:10:21.924682 Byte0, DQ PI dly=979, DQM PI dly= 982
2033 11:10:21.927926 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
2034 11:10:21.928516
2035 11:10:21.935066 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
2036 11:10:21.935452
2037 11:10:21.937925 u1DelayCellOfst[8]=0 cells (0 PI)
2038 11:10:21.941685 u1DelayCellOfst[9]=1 cells (1 PI)
2039 11:10:21.945167 u1DelayCellOfst[10]=7 cells (6 PI)
2040 11:10:21.945549 u1DelayCellOfst[11]=0 cells (0 PI)
2041 11:10:21.948502 u1DelayCellOfst[12]=2 cells (2 PI)
2042 11:10:21.951313 u1DelayCellOfst[13]=1 cells (1 PI)
2043 11:10:21.955025 u1DelayCellOfst[14]=2 cells (2 PI)
2044 11:10:21.958293 u1DelayCellOfst[15]=6 cells (5 PI)
2045 11:10:21.961572 Byte1, DQ PI dly=978, DQM PI dly= 981
2046 11:10:21.965275 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
2047 11:10:21.965716
2048 11:10:21.972039 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
2049 11:10:21.972746
2050 11:10:21.973102 Write Rank1 MR14 =0x20
2051 11:10:21.973420
2052 11:10:21.975316 Final TX Range 0 Vref 32
2053 11:10:21.975810
2054 11:10:21.981983 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2055 11:10:21.982876
2056 11:10:21.988284 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2057 11:10:21.994716 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2058 11:10:22.001968 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2059 11:10:22.004937 Write Rank1 MR3 =0xb0
2060 11:10:22.005091 DramC Write-DBI on
2061 11:10:22.008404 ==
2062 11:10:22.012017 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2063 11:10:22.015019 fsp= 1, odt_onoff= 1, Byte mode= 0
2064 11:10:22.015158 ==
2065 11:10:22.018426 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2066 11:10:22.018564
2067 11:10:22.021765 Begin, DQ Scan Range 701~765
2068 11:10:22.021851
2069 11:10:22.021933
2070 11:10:22.025200 TX Vref Scan disable
2071 11:10:22.028342 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2072 11:10:22.031649 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2073 11:10:22.035229 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2074 11:10:22.038550 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2075 11:10:22.041689 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2076 11:10:22.045189 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2077 11:10:22.048084 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2078 11:10:22.051577 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2079 11:10:22.054817 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2080 11:10:22.058226 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2081 11:10:22.061667 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
2082 11:10:22.065230 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2083 11:10:22.068820 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2084 11:10:22.071840 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2085 11:10:22.081071 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2086 11:10:22.084243 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2087 11:10:22.088113 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2088 11:10:22.091181 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2089 11:10:22.094540 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2090 11:10:22.097819 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2091 11:10:22.101534 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2092 11:10:22.104822 743 |2 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
2093 11:10:22.108233 Byte0, DQ PI dly=728, DQM PI dly= 728
2094 11:10:22.111531 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 24)
2095 11:10:22.111610
2096 11:10:22.117804 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 24)
2097 11:10:22.117892
2098 11:10:22.121425 Byte1, DQ PI dly=723, DQM PI dly= 723
2099 11:10:22.124917 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
2100 11:10:22.124995
2101 11:10:22.128145 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
2102 11:10:22.128254
2103 11:10:22.134907 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2104 11:10:22.141659 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2105 11:10:22.148113 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2106 11:10:22.151312 Write Rank1 MR3 =0x30
2107 11:10:22.154541 DramC Write-DBI off
2108 11:10:22.154617
2109 11:10:22.154679 [DATLAT]
2110 11:10:22.158219 Freq=1600, CH0 RK1, use_rxtx_scan=0
2111 11:10:22.158379
2112 11:10:22.158488 DATLAT Default: 0x10
2113 11:10:22.161274 7, 0xFFFF, sum=0
2114 11:10:22.161372 8, 0xFFFF, sum=0
2115 11:10:22.164422 9, 0xFFFF, sum=0
2116 11:10:22.164524 10, 0xFFFF, sum=0
2117 11:10:22.167822 11, 0xFFFF, sum=0
2118 11:10:22.167906 12, 0xFFFF, sum=0
2119 11:10:22.171611 13, 0xFFFF, sum=0
2120 11:10:22.171718 14, 0x0, sum=1
2121 11:10:22.174985 15, 0x0, sum=2
2122 11:10:22.175094 16, 0x0, sum=3
2123 11:10:22.175207 17, 0x0, sum=4
2124 11:10:22.181284 pattern=2 first_step=14 total pass=5 best_step=16
2125 11:10:22.181366 ==
2126 11:10:22.184528 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2127 11:10:22.188396 fsp= 1, odt_onoff= 1, Byte mode= 0
2128 11:10:22.188506 ==
2129 11:10:22.194945 Start DQ dly to find pass range UseTestEngine =1
2130 11:10:22.198072 x-axis: bit #, y-axis: DQ dly (-127~63)
2131 11:10:22.198165 RX Vref Scan = 0
2132 11:10:22.201490 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2133 11:10:22.205044 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2134 11:10:22.208202 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2135 11:10:22.211579 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2136 11:10:22.214908 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2137 11:10:22.214994 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2138 11:10:22.217941 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2139 11:10:22.221699 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2140 11:10:22.224991 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2141 11:10:22.228280 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2142 11:10:22.231517 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2143 11:10:22.235039 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2144 11:10:22.238245 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2145 11:10:22.238331 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2146 11:10:22.241794 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2147 11:10:22.244806 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2148 11:10:22.248249 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2149 11:10:22.251953 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2150 11:10:22.255024 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2151 11:10:22.258801 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2152 11:10:22.258887 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2153 11:10:22.262218 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2154 11:10:22.265402 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2155 11:10:22.268570 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2156 11:10:22.271964 -2, [0] xxxoxxxx oxxoxxxx [MSB]
2157 11:10:22.274965 -1, [0] xxxoxxxx oxxoxxxx [MSB]
2158 11:10:22.278869 0, [0] xxxoxxxx oxxoxxxx [MSB]
2159 11:10:22.278955 1, [0] xxxoxoxx ooxoooxx [MSB]
2160 11:10:22.281935 2, [0] xxxoxoxx ooxoooxx [MSB]
2161 11:10:22.285354 3, [0] xxxoxooo ooxoooox [MSB]
2162 11:10:22.288337 4, [0] xxxoxooo ooxoooox [MSB]
2163 11:10:22.291986 5, [0] ooxooooo ooxoooox [MSB]
2164 11:10:22.295592 6, [0] oooooooo ooxooooo [MSB]
2165 11:10:22.298331 33, [0] oooooooo xooooooo [MSB]
2166 11:10:22.302008 34, [0] oooxoooo xooooooo [MSB]
2167 11:10:22.304919 35, [0] oooxoxoo xooxoooo [MSB]
2168 11:10:22.308624 36, [0] oooxoxoo xooxoxoo [MSB]
2169 11:10:22.308710 37, [0] oooxoxoo xxoxoxoo [MSB]
2170 11:10:22.312028 38, [0] oooxoxxo xxoxxxxo [MSB]
2171 11:10:22.315229 39, [0] oxxxoxxx xxoxxxxo [MSB]
2172 11:10:22.318507 40, [0] oxxxxxxx xxoxxxxx [MSB]
2173 11:10:22.322026 41, [0] xxxxxxxx xxoxxxxx [MSB]
2174 11:10:22.325504 42, [0] xxxxxxxx xxoxxxxx [MSB]
2175 11:10:22.328781 43, [0] xxxxxxxx xxoxxxxx [MSB]
2176 11:10:22.328866 44, [0] xxxxxxxx xxxxxxxx [MSB]
2177 11:10:22.332157 iDelay=44, Bit 0, Center 22 (5 ~ 40) 36
2178 11:10:22.335307 iDelay=44, Bit 1, Center 21 (5 ~ 38) 34
2179 11:10:22.342372 iDelay=44, Bit 2, Center 22 (6 ~ 38) 33
2180 11:10:22.345545 iDelay=44, Bit 3, Center 15 (-2 ~ 33) 36
2181 11:10:22.348292 iDelay=44, Bit 4, Center 22 (5 ~ 39) 35
2182 11:10:22.352023 iDelay=44, Bit 5, Center 17 (1 ~ 34) 34
2183 11:10:22.355392 iDelay=44, Bit 6, Center 20 (3 ~ 37) 35
2184 11:10:22.358580 iDelay=44, Bit 7, Center 20 (3 ~ 38) 36
2185 11:10:22.362117 iDelay=44, Bit 8, Center 15 (-2 ~ 32) 35
2186 11:10:22.365166 iDelay=44, Bit 9, Center 18 (1 ~ 36) 36
2187 11:10:22.368343 iDelay=44, Bit 10, Center 25 (7 ~ 43) 37
2188 11:10:22.372286 iDelay=44, Bit 11, Center 16 (-2 ~ 34) 37
2189 11:10:22.375587 iDelay=44, Bit 12, Center 19 (1 ~ 37) 37
2190 11:10:22.378575 iDelay=44, Bit 13, Center 18 (1 ~ 35) 35
2191 11:10:22.382041 iDelay=44, Bit 14, Center 20 (3 ~ 37) 35
2192 11:10:22.388923 iDelay=44, Bit 15, Center 22 (6 ~ 39) 34
2193 11:10:22.389007 ==
2194 11:10:22.391870 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2195 11:10:22.395386 fsp= 1, odt_onoff= 1, Byte mode= 0
2196 11:10:22.395470 ==
2197 11:10:22.395535 DQS Delay:
2198 11:10:22.399026 DQS0 = 0, DQS1 = 0
2199 11:10:22.399109 DQM Delay:
2200 11:10:22.402274 DQM0 = 19, DQM1 = 19
2201 11:10:22.402363 DQ Delay:
2202 11:10:22.405711 DQ0 =22, DQ1 =21, DQ2 =22, DQ3 =15
2203 11:10:22.409020 DQ4 =22, DQ5 =17, DQ6 =20, DQ7 =20
2204 11:10:22.412298 DQ8 =15, DQ9 =18, DQ10 =25, DQ11 =16
2205 11:10:22.415784 DQ12 =19, DQ13 =18, DQ14 =20, DQ15 =22
2206 11:10:22.415909
2207 11:10:22.416001
2208 11:10:22.416086
2209 11:10:22.418995 [DramC_TX_OE_Calibration] TA2
2210 11:10:22.422758 Original DQ_B0 (3 6) =30, OEN = 27
2211 11:10:22.425475 Original DQ_B1 (3 6) =30, OEN = 27
2212 11:10:22.429049 23, 0x0, End_B0=23 End_B1=23
2213 11:10:22.429202 24, 0x0, End_B0=24 End_B1=24
2214 11:10:22.432440 25, 0x0, End_B0=25 End_B1=25
2215 11:10:22.435681 26, 0x0, End_B0=26 End_B1=26
2216 11:10:22.438901 27, 0x0, End_B0=27 End_B1=27
2217 11:10:22.439110 28, 0x0, End_B0=28 End_B1=28
2218 11:10:22.442472 29, 0x0, End_B0=29 End_B1=29
2219 11:10:22.446022 30, 0x0, End_B0=30 End_B1=30
2220 11:10:22.448603 31, 0xFFFF, End_B0=30 End_B1=30
2221 11:10:22.452413 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2222 11:10:22.459264 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2223 11:10:22.459363
2224 11:10:22.459439
2225 11:10:22.462018 Write Rank1 MR23 =0x3f
2226 11:10:22.462125 [DQSOSC]
2227 11:10:22.472428 [DQSOSCAuto] RK1, (LSB)MR18= 0xd9d9, (MSB)MR19= 0x202, tDQSOscB0 = 432 ps tDQSOscB1 = 432 ps
2228 11:10:22.475875 CH0_RK1: MR19=0x202, MR18=0xD9D9, DQSOSC=432, MR23=63, INC=13, DEC=19
2229 11:10:22.479048 Write Rank1 MR23 =0x3f
2230 11:10:22.479198 [DQSOSC]
2231 11:10:22.489398 [DQSOSCAuto] RK1, (LSB)MR18= 0xdbdb, (MSB)MR19= 0x202, tDQSOscB0 = 430 ps tDQSOscB1 = 430 ps
2232 11:10:22.489608 CH0 RK1: MR19=202, MR18=DBDB
2233 11:10:22.492751 [RxdqsGatingPostProcess] freq 1600
2234 11:10:22.499563 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2235 11:10:22.499935 Rank: 0
2236 11:10:22.502491 best DQS0 dly(2T, 0.5T) = (2, 5)
2237 11:10:22.506074 best DQS1 dly(2T, 0.5T) = (2, 5)
2238 11:10:22.509437 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
2239 11:10:22.512642 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
2240 11:10:22.513040 Rank: 1
2241 11:10:22.515973 best DQS0 dly(2T, 0.5T) = (2, 6)
2242 11:10:22.519220 best DQS1 dly(2T, 0.5T) = (2, 6)
2243 11:10:22.522976 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2244 11:10:22.525844 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2245 11:10:22.529630 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2246 11:10:22.532674 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2247 11:10:22.539620 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2248 11:10:22.540007 Write Rank0 MR13 =0x59
2249 11:10:22.540305 ==
2250 11:10:22.546586 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2251 11:10:22.549710 fsp= 1, odt_onoff= 1, Byte mode= 0
2252 11:10:22.550095 ==
2253 11:10:22.553004 === u2Vref_new: 0x56 --> 0x3a
2254 11:10:22.556396 === u2Vref_new: 0x58 --> 0x58
2255 11:10:22.559526 === u2Vref_new: 0x5a --> 0x5a
2256 11:10:22.562528 === u2Vref_new: 0x5c --> 0x78
2257 11:10:22.562947 === u2Vref_new: 0x5e --> 0x7a
2258 11:10:22.566348 === u2Vref_new: 0x60 --> 0x90
2259 11:10:22.569729 [CA 0] Center 38 (13~63) winsize 51
2260 11:10:22.572976 [CA 1] Center 37 (12~63) winsize 52
2261 11:10:22.576654 [CA 2] Center 34 (6~63) winsize 58
2262 11:10:22.580165 [CA 3] Center 34 (6~63) winsize 58
2263 11:10:22.583376 [CA 4] Center 34 (6~63) winsize 58
2264 11:10:22.586439 [CA 5] Center 28 (-2~58) winsize 61
2265 11:10:22.586821
2266 11:10:22.589628 [CATrainingPosCal] consider 1 rank data
2267 11:10:22.592974 u2DelayCellTimex100 = 735/100 ps
2268 11:10:22.596344 CA0 delay=38 (13~63),Diff = 10 PI (13 cell)
2269 11:10:22.599833 CA1 delay=37 (12~63),Diff = 9 PI (11 cell)
2270 11:10:22.603012 CA2 delay=34 (6~63),Diff = 6 PI (7 cell)
2271 11:10:22.609630 CA3 delay=34 (6~63),Diff = 6 PI (7 cell)
2272 11:10:22.612981 CA4 delay=34 (6~63),Diff = 6 PI (7 cell)
2273 11:10:22.616993 CA5 delay=28 (-2~58),Diff = 0 PI (0 cell)
2274 11:10:22.617385
2275 11:10:22.619648 CA PerBit enable=1, Macro0, CA PI delay=28
2276 11:10:22.623000 === u2Vref_new: 0x5e --> 0x7a
2277 11:10:22.623395
2278 11:10:22.623786 Vref(ca) range 1: 30
2279 11:10:22.624165
2280 11:10:22.626310 CS Dly= 11 (42-0-32)
2281 11:10:22.629610 Write Rank0 MR13 =0xd8
2282 11:10:22.630001 Write Rank0 MR13 =0xd8
2283 11:10:22.633139 Write Rank0 MR12 =0x5e
2284 11:10:22.633529 Write Rank1 MR13 =0x59
2285 11:10:22.636532 ==
2286 11:10:22.639665 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2287 11:10:22.643100 fsp= 1, odt_onoff= 1, Byte mode= 0
2288 11:10:22.643572 ==
2289 11:10:22.646334 === u2Vref_new: 0x56 --> 0x3a
2290 11:10:22.649578 === u2Vref_new: 0x58 --> 0x58
2291 11:10:22.652863 === u2Vref_new: 0x5a --> 0x5a
2292 11:10:22.656311 === u2Vref_new: 0x5c --> 0x78
2293 11:10:22.659530 === u2Vref_new: 0x5e --> 0x7a
2294 11:10:22.662907 === u2Vref_new: 0x60 --> 0x90
2295 11:10:22.666194 [CA 0] Center 38 (13~63) winsize 51
2296 11:10:22.669505 [CA 1] Center 38 (13~63) winsize 51
2297 11:10:22.672290 [CA 2] Center 35 (7~63) winsize 57
2298 11:10:22.672513 [CA 3] Center 34 (6~63) winsize 58
2299 11:10:22.676243 [CA 4] Center 35 (7~63) winsize 57
2300 11:10:22.679257 [CA 5] Center 27 (-2~57) winsize 60
2301 11:10:22.679485
2302 11:10:22.682599 [CATrainingPosCal] consider 2 rank data
2303 11:10:22.686527 u2DelayCellTimex100 = 735/100 ps
2304 11:10:22.689594 CA0 delay=38 (13~63),Diff = 11 PI (14 cell)
2305 11:10:22.696565 CA1 delay=38 (13~63),Diff = 11 PI (14 cell)
2306 11:10:22.699589 CA2 delay=35 (7~63),Diff = 8 PI (10 cell)
2307 11:10:22.702673 CA3 delay=34 (6~63),Diff = 7 PI (9 cell)
2308 11:10:22.706109 CA4 delay=35 (7~63),Diff = 8 PI (10 cell)
2309 11:10:22.709712 CA5 delay=27 (-2~57),Diff = 0 PI (0 cell)
2310 11:10:22.709939
2311 11:10:22.713058 CA PerBit enable=1, Macro0, CA PI delay=27
2312 11:10:22.716567 === u2Vref_new: 0x5e --> 0x7a
2313 11:10:22.716801
2314 11:10:22.719624 Vref(ca) range 1: 30
2315 11:10:22.719924
2316 11:10:22.720111 CS Dly= 11 (42-0-32)
2317 11:10:22.722744 Write Rank1 MR13 =0xd8
2318 11:10:22.726041 Write Rank1 MR13 =0xd8
2319 11:10:22.726420 Write Rank1 MR12 =0x5e
2320 11:10:22.729730 [RankSwap] Rank num 2, (Multi 1), Rank 0
2321 11:10:22.733010 Write Rank0 MR2 =0xad
2322 11:10:22.733435 [Write Leveling]
2323 11:10:22.737024 delay byte0 byte1 byte2 byte3
2324 11:10:22.737477
2325 11:10:22.739501 10 0 0
2326 11:10:22.739961 11 0 0
2327 11:10:22.743053 12 0 0
2328 11:10:22.743439 13 0 0
2329 11:10:22.743776 14 0 0
2330 11:10:22.746844 15 0 0
2331 11:10:22.747304 16 0 0
2332 11:10:22.750075 17 0 0
2333 11:10:22.750469 18 0 0
2334 11:10:22.750773 19 0 0
2335 11:10:22.753212 20 0 0
2336 11:10:22.753691 21 0 0
2337 11:10:22.756373 22 0 0
2338 11:10:22.756797 23 0 0
2339 11:10:22.757098 24 0 ff
2340 11:10:22.759764 25 0 ff
2341 11:10:22.760164 26 0 ff
2342 11:10:22.763241 27 0 ff
2343 11:10:22.763699 28 0 ff
2344 11:10:22.766509 29 0 ff
2345 11:10:22.766970 30 0 ff
2346 11:10:22.770046 31 0 ff
2347 11:10:22.770515 32 0 ff
2348 11:10:22.770898 33 ff ff
2349 11:10:22.773670 34 ff ff
2350 11:10:22.774129 35 ff ff
2351 11:10:22.777030 36 ff ff
2352 11:10:22.777489 37 ff ff
2353 11:10:22.779958 38 ff ff
2354 11:10:22.780417 39 ff ff
2355 11:10:22.783645 pass bytecount = 0xff (0xff: all bytes pass)
2356 11:10:22.784099
2357 11:10:22.786438 DQS0 dly: 33
2358 11:10:22.786816 DQS1 dly: 24
2359 11:10:22.789890 Write Rank0 MR2 =0x2d
2360 11:10:22.793238 [RankSwap] Rank num 2, (Multi 1), Rank 0
2361 11:10:22.793701 Write Rank0 MR1 =0xd6
2362 11:10:22.796667 [Gating]
2363 11:10:22.797116 ==
2364 11:10:22.799695 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2365 11:10:22.803035 fsp= 1, odt_onoff= 1, Byte mode= 0
2366 11:10:22.803417 ==
2367 11:10:22.809818 3 1 0 |3636 2c2b |(0 0)(11 11) |(0 0)(1 1)| 0
2368 11:10:22.813602 3 1 4 |3535 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
2369 11:10:22.816626 3 1 8 |2020 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
2370 11:10:22.820240 3 1 12 |3636 2c2b |(0 0)(11 11) |(1 1)(1 1)| 0
2371 11:10:22.826525 3 1 16 |807 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
2372 11:10:22.830342 [Byte 1] Lead/lag falling Transition (3, 1, 16)
2373 11:10:22.833454 3 1 20 |3535 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2374 11:10:22.839842 3 1 24 |2e2e 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2375 11:10:22.843234 3 1 28 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2376 11:10:22.846429 3 2 0 |3434 2c2b |(0 0)(11 11) |(0 1)(1 0)| 0
2377 11:10:22.850211 3 2 4 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2378 11:10:22.856856 3 2 8 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2379 11:10:22.860002 3 2 12 |3333 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2380 11:10:22.863836 3 2 16 |1f1e 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2381 11:10:22.869974 3 2 20 |2726 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2382 11:10:22.873687 [Byte 1] Lead/lag Transition tap number (10)
2383 11:10:22.876780 3 2 24 |3d3d 404 |(11 11)(11 11) |(1 1)(0 0)| 0
2384 11:10:22.880573 3 2 28 |202 2424 |(11 11)(11 11) |(1 1)(0 0)| 0
2385 11:10:22.886668 3 3 0 |3d3c 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2386 11:10:22.890405 3 3 4 |1716 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2387 11:10:22.893555 3 3 8 |3c3c 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2388 11:10:22.900316 3 3 12 |3d3c 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2389 11:10:22.903329 3 3 16 |2322 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2390 11:10:22.906968 3 3 20 |1d1c 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2391 11:10:22.913939 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2392 11:10:22.916954 [Byte 0] Lead/lag falling Transition (3, 3, 24)
2393 11:10:22.920332 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2394 11:10:22.923605 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2395 11:10:22.930467 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2396 11:10:22.933706 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2397 11:10:22.936825 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2398 11:10:22.943380 3 4 16 |2928 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2399 11:10:22.946650 3 4 20 |1918 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2400 11:10:22.949581 3 4 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2401 11:10:22.956915 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2402 11:10:22.960132 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2403 11:10:22.963513 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2404 11:10:22.970473 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2405 11:10:22.973139 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2406 11:10:22.976530 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2407 11:10:22.983463 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2408 11:10:22.986538 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2409 11:10:22.989863 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2410 11:10:22.993102 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2411 11:10:22.999867 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2412 11:10:23.003154 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2413 11:10:23.006950 [Byte 0] Lead/lag falling Transition (3, 6, 8)
2414 11:10:23.013451 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2415 11:10:23.016546 [Byte 0] Lead/lag Transition tap number (2)
2416 11:10:23.020243 3 6 16 |403 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2417 11:10:23.023106 [Byte 1] Lead/lag falling Transition (3, 6, 16)
2418 11:10:23.029890 3 6 20 |2020 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2419 11:10:23.033258 [Byte 1] Lead/lag Transition tap number (2)
2420 11:10:23.036540 3 6 24 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
2421 11:10:23.039939 [Byte 0]First pass (3, 6, 24)
2422 11:10:23.043055 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2423 11:10:23.046891 [Byte 1]First pass (3, 6, 28)
2424 11:10:23.049371 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2425 11:10:23.052994 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2426 11:10:23.056253 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2427 11:10:23.063079 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2428 11:10:23.066459 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2429 11:10:23.069301 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2430 11:10:23.072697 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2431 11:10:23.079409 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2432 11:10:23.082543 All bytes gating window > 1UI, Early break!
2433 11:10:23.082932
2434 11:10:23.086397 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 12)
2435 11:10:23.086825
2436 11:10:23.089339 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 20)
2437 11:10:23.089726
2438 11:10:23.090023
2439 11:10:23.090335
2440 11:10:23.092708 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
2441 11:10:23.093138
2442 11:10:23.099291 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 20)
2443 11:10:23.099675
2444 11:10:23.100069
2445 11:10:23.100358 Write Rank0 MR1 =0x56
2446 11:10:23.100698
2447 11:10:23.102779 best RODT dly(2T, 0.5T) = (2, 3)
2448 11:10:23.103161
2449 11:10:23.106003 best RODT dly(2T, 0.5T) = (2, 3)
2450 11:10:23.106390 ==
2451 11:10:23.112512 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2452 11:10:23.115991 fsp= 1, odt_onoff= 1, Byte mode= 0
2453 11:10:23.116372 ==
2454 11:10:23.119325 Start DQ dly to find pass range UseTestEngine =0
2455 11:10:23.122674 x-axis: bit #, y-axis: DQ dly (-127~63)
2456 11:10:23.126126 RX Vref Scan = 0
2457 11:10:23.129204 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2458 11:10:23.129608 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2459 11:10:23.132589 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2460 11:10:23.135847 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2461 11:10:23.139310 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2462 11:10:23.142217 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2463 11:10:23.145726 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2464 11:10:23.149003 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2465 11:10:23.152314 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2466 11:10:23.152750 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2467 11:10:23.155788 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2468 11:10:23.159342 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2469 11:10:23.162536 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2470 11:10:23.165638 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2471 11:10:23.169004 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2472 11:10:23.172481 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2473 11:10:23.175628 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2474 11:10:23.176020 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2475 11:10:23.179389 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2476 11:10:23.182524 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2477 11:10:23.185859 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2478 11:10:23.189051 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2479 11:10:23.192733 -4, [0] xxxxxxxx xxxxxxxo [MSB]
2480 11:10:23.195877 -3, [0] xxxxxxxx xxxxxxxo [MSB]
2481 11:10:23.196264 -2, [0] xxxxxxxx xxxxxxxo [MSB]
2482 11:10:23.199018 -1, [0] xxxxxxxx xoxxxxxo [MSB]
2483 11:10:23.202681 0, [0] xxxoxxxx ooxxxxxo [MSB]
2484 11:10:23.205803 1, [0] xxooxxxx ooxxxxxo [MSB]
2485 11:10:23.209363 2, [0] xxooxxxx ooxxxxxo [MSB]
2486 11:10:23.212221 3, [0] oxooxxxo oooxxxxo [MSB]
2487 11:10:23.212662 4, [0] oxoooxxo oooxooxo [MSB]
2488 11:10:23.215838 5, [0] oooooxoo ooooooxo [MSB]
2489 11:10:23.218911 31, [0] oooooooo ooooooox [MSB]
2490 11:10:23.222637 32, [0] oooooooo ooooooox [MSB]
2491 11:10:23.225567 33, [0] oooooooo ooooooox [MSB]
2492 11:10:23.229327 34, [0] oooooooo ooooooox [MSB]
2493 11:10:23.232782 35, [0] oooxoooo ooooooox [MSB]
2494 11:10:23.233206 36, [0] oooxoooo xxooooox [MSB]
2495 11:10:23.235965 37, [0] ooxxoooo xxooooox [MSB]
2496 11:10:23.239153 38, [0] ooxxoooo xxooooox [MSB]
2497 11:10:23.242348 39, [0] ooxxooox xxooooox [MSB]
2498 11:10:23.245872 40, [0] oxxxooox xxxoooox [MSB]
2499 11:10:23.249283 41, [0] oxxxxoox xxxxxxox [MSB]
2500 11:10:23.252451 42, [0] xxxxxoox xxxxxxxx [MSB]
2501 11:10:23.253011 43, [0] xxxxxxxx xxxxxxxx [MSB]
2502 11:10:23.255619 iDelay=43, Bit 0, Center 22 (3 ~ 41) 39
2503 11:10:23.262180 iDelay=43, Bit 1, Center 22 (5 ~ 39) 35
2504 11:10:23.265633 iDelay=43, Bit 2, Center 18 (1 ~ 36) 36
2505 11:10:23.268760 iDelay=43, Bit 3, Center 17 (0 ~ 34) 35
2506 11:10:23.272150 iDelay=43, Bit 4, Center 22 (4 ~ 40) 37
2507 11:10:23.275752 iDelay=43, Bit 5, Center 24 (6 ~ 42) 37
2508 11:10:23.278731 iDelay=43, Bit 6, Center 23 (5 ~ 42) 38
2509 11:10:23.282335 iDelay=43, Bit 7, Center 20 (3 ~ 38) 36
2510 11:10:23.285540 iDelay=43, Bit 8, Center 17 (0 ~ 35) 36
2511 11:10:23.289041 iDelay=43, Bit 9, Center 17 (-1 ~ 35) 37
2512 11:10:23.291883 iDelay=43, Bit 10, Center 21 (3 ~ 39) 37
2513 11:10:23.295186 iDelay=43, Bit 11, Center 22 (5 ~ 40) 36
2514 11:10:23.298678 iDelay=43, Bit 12, Center 22 (4 ~ 40) 37
2515 11:10:23.304996 iDelay=43, Bit 13, Center 22 (4 ~ 40) 37
2516 11:10:23.308651 iDelay=43, Bit 14, Center 23 (6 ~ 41) 36
2517 11:10:23.311970 iDelay=43, Bit 15, Center 13 (-4 ~ 30) 35
2518 11:10:23.312352 ==
2519 11:10:23.315285 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2520 11:10:23.318492 fsp= 1, odt_onoff= 1, Byte mode= 0
2521 11:10:23.318878 ==
2522 11:10:23.321708 DQS Delay:
2523 11:10:23.322090 DQS0 = 0, DQS1 = 0
2524 11:10:23.322391 DQM Delay:
2525 11:10:23.324982 DQM0 = 21, DQM1 = 19
2526 11:10:23.325367 DQ Delay:
2527 11:10:23.328517 DQ0 =22, DQ1 =22, DQ2 =18, DQ3 =17
2528 11:10:23.331845 DQ4 =22, DQ5 =24, DQ6 =23, DQ7 =20
2529 11:10:23.335346 DQ8 =17, DQ9 =17, DQ10 =21, DQ11 =22
2530 11:10:23.338791 DQ12 =22, DQ13 =22, DQ14 =23, DQ15 =13
2531 11:10:23.339249
2532 11:10:23.339547
2533 11:10:23.342165 DramC Write-DBI off
2534 11:10:23.342624 ==
2535 11:10:23.345146 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2536 11:10:23.348574 fsp= 1, odt_onoff= 1, Byte mode= 0
2537 11:10:23.349050 ==
2538 11:10:23.355681 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2539 11:10:23.356146
2540 11:10:23.358935 Begin, DQ Scan Range 920~1176
2541 11:10:23.359391
2542 11:10:23.359691
2543 11:10:23.359967 TX Vref Scan disable
2544 11:10:23.362295 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
2545 11:10:23.365474 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
2546 11:10:23.368941 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
2547 11:10:23.375367 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
2548 11:10:23.378638 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
2549 11:10:23.381843 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
2550 11:10:23.385370 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
2551 11:10:23.388730 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
2552 11:10:23.391790 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
2553 11:10:23.395436 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2554 11:10:23.398569 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2555 11:10:23.401954 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2556 11:10:23.405378 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2557 11:10:23.408665 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2558 11:10:23.411905 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2559 11:10:23.415299 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2560 11:10:23.418352 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2561 11:10:23.421869 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2562 11:10:23.428165 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2563 11:10:23.431632 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2564 11:10:23.435392 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2565 11:10:23.438218 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2566 11:10:23.442022 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2567 11:10:23.445182 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2568 11:10:23.448311 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2569 11:10:23.451728 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2570 11:10:23.455176 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2571 11:10:23.458548 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2572 11:10:23.461734 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2573 11:10:23.465183 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2574 11:10:23.467678 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2575 11:10:23.471267 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2576 11:10:23.474764 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2577 11:10:23.481122 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2578 11:10:23.484706 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2579 11:10:23.487810 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2580 11:10:23.491453 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2581 11:10:23.494367 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2582 11:10:23.498299 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2583 11:10:23.501243 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2584 11:10:23.504939 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2585 11:10:23.508548 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2586 11:10:23.511690 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2587 11:10:23.514708 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2588 11:10:23.517820 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2589 11:10:23.521491 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2590 11:10:23.524837 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2591 11:10:23.528117 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2592 11:10:23.531172 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2593 11:10:23.535085 969 |3 6 9|[0] xxxxxxxx xxxxxxxo [MSB]
2594 11:10:23.537722 970 |3 6 10|[0] xxxxxxxx ooxxxxxo [MSB]
2595 11:10:23.541340 971 |3 6 11|[0] xxxxxxxx ooxxxxxo [MSB]
2596 11:10:23.544890 972 |3 6 12|[0] xxxxxxxx oooxxxoo [MSB]
2597 11:10:23.547961 973 |3 6 13|[0] xxxxxxxx oooxoxoo [MSB]
2598 11:10:23.554663 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
2599 11:10:23.558011 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
2600 11:10:23.561401 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
2601 11:10:23.564490 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
2602 11:10:23.568129 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
2603 11:10:23.571356 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
2604 11:10:23.574804 980 |3 6 20|[0] xxxxxxxx oooooooo [MSB]
2605 11:10:23.578232 981 |3 6 21|[0] xooooxoo oooooooo [MSB]
2606 11:10:23.581309 982 |3 6 22|[0] oooooxoo oooooooo [MSB]
2607 11:10:23.584811 986 |3 6 26|[0] oooooooo ooooooox [MSB]
2608 11:10:23.588088 987 |3 6 27|[0] oooooooo ooooooox [MSB]
2609 11:10:23.591318 988 |3 6 28|[0] oooooooo oxooooox [MSB]
2610 11:10:23.594475 989 |3 6 29|[0] oooooooo xxooooox [MSB]
2611 11:10:23.598059 990 |3 6 30|[0] oooooooo xxooooox [MSB]
2612 11:10:23.604434 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
2613 11:10:23.607899 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
2614 11:10:23.611794 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
2615 11:10:23.614524 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
2616 11:10:23.617401 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
2617 11:10:23.621587 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
2618 11:10:23.625048 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
2619 11:10:23.627959 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
2620 11:10:23.631255 999 |3 6 39|[0] oooxoooo xxxxxxxx [MSB]
2621 11:10:23.634519 1000 |3 6 40|[0] oooxoooo xxxxxxxx [MSB]
2622 11:10:23.637870 1001 |3 6 41|[0] ooxxooox xxxxxxxx [MSB]
2623 11:10:23.641233 1002 |3 6 42|[0] xxxxxxxx xxxxxxxx [MSB]
2624 11:10:23.644492 Byte0, DQ PI dly=990, DQM PI dly= 990
2625 11:10:23.651412 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 30)
2626 11:10:23.651912
2627 11:10:23.654622 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 30)
2628 11:10:23.655135
2629 11:10:23.657928 Byte1, DQ PI dly=979, DQM PI dly= 979
2630 11:10:23.661248 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
2631 11:10:23.661744
2632 11:10:23.668156 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
2633 11:10:23.668718
2634 11:10:23.669053 ==
2635 11:10:23.671010 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2636 11:10:23.674696 fsp= 1, odt_onoff= 1, Byte mode= 0
2637 11:10:23.675215 ==
2638 11:10:23.680730 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2639 11:10:23.681151
2640 11:10:23.681476 Begin, DQ Scan Range 955~1019
2641 11:10:23.684364 Write Rank0 MR14 =0x0
2642 11:10:23.692962
2643 11:10:23.693459 CH=1, VrefRange= 0, VrefLevel = 0
2644 11:10:23.699996 TX Bit0 (984~999) 16 991, Bit8 (973~984) 12 978,
2645 11:10:23.703094 TX Bit1 (983~995) 13 989, Bit9 (973~983) 11 978,
2646 11:10:23.709895 TX Bit2 (981~995) 15 988, Bit10 (976~986) 11 981,
2647 11:10:23.713419 TX Bit3 (980~992) 13 986, Bit11 (976~987) 12 981,
2648 11:10:23.716336 TX Bit4 (983~997) 15 990, Bit12 (976~986) 11 981,
2649 11:10:23.723324 TX Bit5 (985~998) 14 991, Bit13 (977~987) 11 982,
2650 11:10:23.726736 TX Bit6 (984~997) 14 990, Bit14 (975~986) 12 980,
2651 11:10:23.730091 TX Bit7 (983~995) 13 989, Bit15 (969~979) 11 974,
2652 11:10:23.730550
2653 11:10:23.733298 Write Rank0 MR14 =0x2
2654 11:10:23.742493
2655 11:10:23.742991 CH=1, VrefRange= 0, VrefLevel = 2
2656 11:10:23.748997 TX Bit0 (984~1000) 17 992, Bit8 (972~984) 13 978,
2657 11:10:23.751966 TX Bit1 (983~996) 14 989, Bit9 (973~983) 11 978,
2658 11:10:23.759506 TX Bit2 (981~996) 16 988, Bit10 (975~986) 12 980,
2659 11:10:23.761855 TX Bit3 (979~993) 15 986, Bit11 (975~988) 14 981,
2660 11:10:23.765754 TX Bit4 (982~998) 17 990, Bit12 (975~988) 14 981,
2661 11:10:23.772320 TX Bit5 (984~999) 16 991, Bit13 (976~988) 13 982,
2662 11:10:23.775478 TX Bit6 (983~998) 16 990, Bit14 (975~987) 13 981,
2663 11:10:23.779031 TX Bit7 (983~997) 15 990, Bit15 (969~980) 12 974,
2664 11:10:23.782086
2665 11:10:23.782541 Write Rank0 MR14 =0x4
2666 11:10:23.791239
2667 11:10:23.791619 CH=1, VrefRange= 0, VrefLevel = 4
2668 11:10:23.797879 TX Bit0 (983~1000) 18 991, Bit8 (972~985) 14 978,
2669 11:10:23.801178 TX Bit1 (982~998) 17 990, Bit9 (972~984) 13 978,
2670 11:10:23.807701 TX Bit2 (981~996) 16 988, Bit10 (975~987) 13 981,
2671 11:10:23.811558 TX Bit3 (978~993) 16 985, Bit11 (975~988) 14 981,
2672 11:10:23.814696 TX Bit4 (982~999) 18 990, Bit12 (975~989) 15 982,
2673 11:10:23.821480 TX Bit5 (984~999) 16 991, Bit13 (976~989) 14 982,
2674 11:10:23.824085 TX Bit6 (983~999) 17 991, Bit14 (974~988) 15 981,
2675 11:10:23.827683 TX Bit7 (983~997) 15 990, Bit15 (969~982) 14 975,
2676 11:10:23.830904
2677 11:10:23.831450 Write Rank0 MR14 =0x6
2678 11:10:23.840291
2679 11:10:23.840728 CH=1, VrefRange= 0, VrefLevel = 6
2680 11:10:23.847131 TX Bit0 (983~1001) 19 992, Bit8 (972~985) 14 978,
2681 11:10:23.850366 TX Bit1 (982~998) 17 990, Bit9 (972~984) 13 978,
2682 11:10:23.857030 TX Bit2 (979~998) 20 988, Bit10 (974~988) 15 981,
2683 11:10:23.860505 TX Bit3 (978~994) 17 986, Bit11 (975~990) 16 982,
2684 11:10:23.863606 TX Bit4 (982~999) 18 990, Bit12 (975~990) 16 982,
2685 11:10:23.870978 TX Bit5 (984~999) 16 991, Bit13 (976~990) 15 983,
2686 11:10:23.874597 TX Bit6 (983~999) 17 991, Bit14 (974~988) 15 981,
2687 11:10:23.877116 TX Bit7 (983~998) 16 990, Bit15 (969~983) 15 976,
2688 11:10:23.877598
2689 11:10:23.880234 Write Rank0 MR14 =0x8
2690 11:10:23.890346
2691 11:10:23.892977 CH=1, VrefRange= 0, VrefLevel = 8
2692 11:10:23.896203 TX Bit0 (983~1001) 19 992, Bit8 (971~986) 16 978,
2693 11:10:23.899868 TX Bit1 (982~999) 18 990, Bit9 (971~985) 15 978,
2694 11:10:23.906729 TX Bit2 (979~998) 20 988, Bit10 (974~989) 16 981,
2695 11:10:23.909452 TX Bit3 (978~995) 18 986, Bit11 (975~990) 16 982,
2696 11:10:23.912989 TX Bit4 (982~1000) 19 991, Bit12 (974~991) 18 982,
2697 11:10:23.919694 TX Bit5 (984~1000) 17 992, Bit13 (976~991) 16 983,
2698 11:10:23.922911 TX Bit6 (982~999) 18 990, Bit14 (974~989) 16 981,
2699 11:10:23.929471 TX Bit7 (982~999) 18 990, Bit15 (968~983) 16 975,
2700 11:10:23.929871
2701 11:10:23.930265 Write Rank0 MR14 =0xa
2702 11:10:23.939762
2703 11:10:23.942789 CH=1, VrefRange= 0, VrefLevel = 10
2704 11:10:23.946060 TX Bit0 (983~1001) 19 992, Bit8 (970~986) 17 978,
2705 11:10:23.949127 TX Bit1 (982~999) 18 990, Bit9 (970~985) 16 977,
2706 11:10:23.956144 TX Bit2 (979~999) 21 989, Bit10 (974~990) 17 982,
2707 11:10:23.959440 TX Bit3 (978~996) 19 987, Bit11 (974~991) 18 982,
2708 11:10:23.962509 TX Bit4 (981~1000) 20 990, Bit12 (974~991) 18 982,
2709 11:10:23.968963 TX Bit5 (983~1000) 18 991, Bit13 (975~991) 17 983,
2710 11:10:23.972170 TX Bit6 (982~1000) 19 991, Bit14 (973~990) 18 981,
2711 11:10:23.978801 TX Bit7 (982~999) 18 990, Bit15 (968~984) 17 976,
2712 11:10:23.979182
2713 11:10:23.979474 Write Rank0 MR14 =0xc
2714 11:10:23.989328
2715 11:10:23.989809 CH=1, VrefRange= 0, VrefLevel = 12
2716 11:10:23.996165 TX Bit0 (982~1002) 21 992, Bit8 (970~987) 18 978,
2717 11:10:23.998998 TX Bit1 (981~1000) 20 990, Bit9 (970~985) 16 977,
2718 11:10:24.005763 TX Bit2 (978~999) 22 988, Bit10 (973~990) 18 981,
2719 11:10:24.009245 TX Bit3 (978~996) 19 987, Bit11 (975~991) 17 983,
2720 11:10:24.012350 TX Bit4 (981~1001) 21 991, Bit12 (974~992) 19 983,
2721 11:10:24.018940 TX Bit5 (983~1000) 18 991, Bit13 (975~991) 17 983,
2722 11:10:24.022708 TX Bit6 (982~1000) 19 991, Bit14 (972~991) 20 981,
2723 11:10:24.029169 TX Bit7 (981~1000) 20 990, Bit15 (968~984) 17 976,
2724 11:10:24.029552
2725 11:10:24.029848 Write Rank0 MR14 =0xe
2726 11:10:24.039428
2727 11:10:24.042423 CH=1, VrefRange= 0, VrefLevel = 14
2728 11:10:24.045681 TX Bit0 (982~1002) 21 992, Bit8 (970~987) 18 978,
2729 11:10:24.048942 TX Bit1 (979~1000) 22 989, Bit9 (970~986) 17 978,
2730 11:10:24.055753 TX Bit2 (978~1000) 23 989, Bit10 (973~991) 19 982,
2731 11:10:24.058790 TX Bit3 (977~997) 21 987, Bit11 (974~991) 18 982,
2732 11:10:24.062382 TX Bit4 (980~1001) 22 990, Bit12 (973~992) 20 982,
2733 11:10:24.069007 TX Bit5 (983~1001) 19 992, Bit13 (975~992) 18 983,
2734 11:10:24.072318 TX Bit6 (981~1000) 20 990, Bit14 (972~991) 20 981,
2735 11:10:24.079180 TX Bit7 (981~1000) 20 990, Bit15 (967~985) 19 976,
2736 11:10:24.079637
2737 11:10:24.079933 Write Rank0 MR14 =0x10
2738 11:10:24.089329
2739 11:10:24.092613 CH=1, VrefRange= 0, VrefLevel = 16
2740 11:10:24.095773 TX Bit0 (982~1002) 21 992, Bit8 (970~989) 20 979,
2741 11:10:24.099190 TX Bit1 (979~1001) 23 990, Bit9 (970~986) 17 978,
2742 11:10:24.105547 TX Bit2 (978~1000) 23 989, Bit10 (972~992) 21 982,
2743 11:10:24.108741 TX Bit3 (977~998) 22 987, Bit11 (973~992) 20 982,
2744 11:10:24.112543 TX Bit4 (980~1001) 22 990, Bit12 (973~992) 20 982,
2745 11:10:24.119615 TX Bit5 (982~1001) 20 991, Bit13 (975~992) 18 983,
2746 11:10:24.122970 TX Bit6 (981~1001) 21 991, Bit14 (972~992) 21 982,
2747 11:10:24.129188 TX Bit7 (981~1000) 20 990, Bit15 (967~985) 19 976,
2748 11:10:24.129655
2749 11:10:24.129950 Write Rank0 MR14 =0x12
2750 11:10:24.139586
2751 11:10:24.142729 CH=1, VrefRange= 0, VrefLevel = 18
2752 11:10:24.145901 TX Bit0 (982~1002) 21 992, Bit8 (970~989) 20 979,
2753 11:10:24.149540 TX Bit1 (980~1001) 22 990, Bit9 (970~987) 18 978,
2754 11:10:24.155611 TX Bit2 (978~1000) 23 989, Bit10 (972~992) 21 982,
2755 11:10:24.159236 TX Bit3 (977~998) 22 987, Bit11 (973~992) 20 982,
2756 11:10:24.162575 TX Bit4 (979~1002) 24 990, Bit12 (972~993) 22 982,
2757 11:10:24.169185 TX Bit5 (982~1002) 21 992, Bit13 (975~992) 18 983,
2758 11:10:24.172239 TX Bit6 (980~1001) 22 990, Bit14 (971~992) 22 981,
2759 11:10:24.179125 TX Bit7 (979~1001) 23 990, Bit15 (967~985) 19 976,
2760 11:10:24.179601
2761 11:10:24.182745 wait MRW command Rank0 MR14 =0x14 fired (1)
2762 11:10:24.185581 Write Rank0 MR14 =0x14
2763 11:10:24.193727
2764 11:10:24.196994 CH=1, VrefRange= 0, VrefLevel = 20
2765 11:10:24.200352 TX Bit0 (981~1004) 24 992, Bit8 (970~990) 21 980,
2766 11:10:24.203883 TX Bit1 (979~1002) 24 990, Bit9 (970~988) 19 979,
2767 11:10:24.210776 TX Bit2 (978~1001) 24 989, Bit10 (971~992) 22 981,
2768 11:10:24.213663 TX Bit3 (977~999) 23 988, Bit11 (972~992) 21 982,
2769 11:10:24.217056 TX Bit4 (979~1002) 24 990, Bit12 (971~993) 23 982,
2770 11:10:24.223769 TX Bit5 (982~1003) 22 992, Bit13 (974~992) 19 983,
2771 11:10:24.226576 TX Bit6 (979~1002) 24 990, Bit14 (971~992) 22 981,
2772 11:10:24.233667 TX Bit7 (980~1001) 22 990, Bit15 (967~986) 20 976,
2773 11:10:24.234206
2774 11:10:24.234647 Write Rank0 MR14 =0x16
2775 11:10:24.244187
2776 11:10:24.247844 CH=1, VrefRange= 0, VrefLevel = 22
2777 11:10:24.250924 TX Bit0 (980~1004) 25 992, Bit8 (969~991) 23 980,
2778 11:10:24.254174 TX Bit1 (978~1002) 25 990, Bit9 (969~989) 21 979,
2779 11:10:24.260528 TX Bit2 (977~1001) 25 989, Bit10 (971~992) 22 981,
2780 11:10:24.263816 TX Bit3 (977~999) 23 988, Bit11 (972~992) 21 982,
2781 11:10:24.267373 TX Bit4 (979~1002) 24 990, Bit12 (971~993) 23 982,
2782 11:10:24.273905 TX Bit5 (982~1003) 22 992, Bit13 (974~993) 20 983,
2783 11:10:24.277363 TX Bit6 (980~1002) 23 991, Bit14 (971~993) 23 982,
2784 11:10:24.283895 TX Bit7 (979~1001) 23 990, Bit15 (967~986) 20 976,
2785 11:10:24.284290
2786 11:10:24.284721 Write Rank0 MR14 =0x18
2787 11:10:24.294548
2788 11:10:24.297531 CH=1, VrefRange= 0, VrefLevel = 24
2789 11:10:24.301295 TX Bit0 (980~1004) 25 992, Bit8 (969~991) 23 980,
2790 11:10:24.304658 TX Bit1 (978~1002) 25 990, Bit9 (969~989) 21 979,
2791 11:10:24.311150 TX Bit2 (977~1001) 25 989, Bit10 (971~992) 22 981,
2792 11:10:24.314514 TX Bit3 (976~999) 24 987, Bit11 (971~993) 23 982,
2793 11:10:24.317746 TX Bit4 (978~1003) 26 990, Bit12 (971~994) 24 982,
2794 11:10:24.324588 TX Bit5 (981~1004) 24 992, Bit13 (974~993) 20 983,
2795 11:10:24.327501 TX Bit6 (979~1002) 24 990, Bit14 (971~993) 23 982,
2796 11:10:24.334120 TX Bit7 (979~1002) 24 990, Bit15 (967~987) 21 977,
2797 11:10:24.334609
2798 11:10:24.334928 Write Rank0 MR14 =0x1a
2799 11:10:24.345147
2800 11:10:24.348505 CH=1, VrefRange= 0, VrefLevel = 26
2801 11:10:24.351877 TX Bit0 (980~1006) 27 993, Bit8 (969~991) 23 980,
2802 11:10:24.354986 TX Bit1 (978~1002) 25 990, Bit9 (969~990) 22 979,
2803 11:10:24.361645 TX Bit2 (977~1001) 25 989, Bit10 (970~993) 24 981,
2804 11:10:24.365190 TX Bit3 (976~1000) 25 988, Bit11 (971~993) 23 982,
2805 11:10:24.371969 TX Bit4 (978~1003) 26 990, Bit12 (971~994) 24 982,
2806 11:10:24.375063 TX Bit5 (981~1004) 24 992, Bit13 (973~993) 21 983,
2807 11:10:24.378846 TX Bit6 (979~1003) 25 991, Bit14 (970~993) 24 981,
2808 11:10:24.385443 TX Bit7 (979~1002) 24 990, Bit15 (966~987) 22 976,
2809 11:10:24.385907
2810 11:10:24.386201 Write Rank0 MR14 =0x1c
2811 11:10:24.396191
2812 11:10:24.399656 CH=1, VrefRange= 0, VrefLevel = 28
2813 11:10:24.402935 TX Bit0 (979~1006) 28 992, Bit8 (968~991) 24 979,
2814 11:10:24.405918 TX Bit1 (978~1003) 26 990, Bit9 (969~991) 23 980,
2815 11:10:24.412578 TX Bit2 (977~1002) 26 989, Bit10 (970~993) 24 981,
2816 11:10:24.415943 TX Bit3 (976~1000) 25 988, Bit11 (970~994) 25 982,
2817 11:10:24.419058 TX Bit4 (978~1004) 27 991, Bit12 (970~994) 25 982,
2818 11:10:24.426178 TX Bit5 (980~1005) 26 992, Bit13 (972~994) 23 983,
2819 11:10:24.429409 TX Bit6 (978~1003) 26 990, Bit14 (970~993) 24 981,
2820 11:10:24.435859 TX Bit7 (978~1003) 26 990, Bit15 (966~988) 23 977,
2821 11:10:24.436240
2822 11:10:24.436565 Write Rank0 MR14 =0x1e
2823 11:10:24.447440
2824 11:10:24.450683 CH=1, VrefRange= 0, VrefLevel = 30
2825 11:10:24.454026 TX Bit0 (979~1006) 28 992, Bit8 (968~991) 24 979,
2826 11:10:24.456674 TX Bit1 (978~1003) 26 990, Bit9 (969~991) 23 980,
2827 11:10:24.463584 TX Bit2 (977~1002) 26 989, Bit10 (970~993) 24 981,
2828 11:10:24.467089 TX Bit3 (976~1000) 25 988, Bit11 (970~994) 25 982,
2829 11:10:24.470396 TX Bit4 (978~1004) 27 991, Bit12 (970~994) 25 982,
2830 11:10:24.477382 TX Bit5 (980~1005) 26 992, Bit13 (972~994) 23 983,
2831 11:10:24.480114 TX Bit6 (978~1003) 26 990, Bit14 (970~993) 24 981,
2832 11:10:24.486787 TX Bit7 (978~1003) 26 990, Bit15 (966~988) 23 977,
2833 11:10:24.487296
2834 11:10:24.487624 Write Rank0 MR14 =0x20
2835 11:10:24.497882
2836 11:10:24.501095 CH=1, VrefRange= 0, VrefLevel = 32
2837 11:10:24.504584 TX Bit0 (979~1006) 28 992, Bit8 (968~991) 24 979,
2838 11:10:24.508052 TX Bit1 (978~1003) 26 990, Bit9 (969~991) 23 980,
2839 11:10:24.514245 TX Bit2 (977~1002) 26 989, Bit10 (970~993) 24 981,
2840 11:10:24.517861 TX Bit3 (976~1000) 25 988, Bit11 (970~994) 25 982,
2841 11:10:24.521358 TX Bit4 (978~1004) 27 991, Bit12 (970~994) 25 982,
2842 11:10:24.527345 TX Bit5 (980~1005) 26 992, Bit13 (972~994) 23 983,
2843 11:10:24.530921 TX Bit6 (978~1003) 26 990, Bit14 (970~993) 24 981,
2844 11:10:24.537798 TX Bit7 (978~1003) 26 990, Bit15 (966~988) 23 977,
2845 11:10:24.538350
2846 11:10:24.538682 Write Rank0 MR14 =0x22
2847 11:10:24.548550
2848 11:10:24.552340 CH=1, VrefRange= 0, VrefLevel = 34
2849 11:10:24.555808 TX Bit0 (979~1006) 28 992, Bit8 (968~991) 24 979,
2850 11:10:24.558735 TX Bit1 (978~1003) 26 990, Bit9 (969~991) 23 980,
2851 11:10:24.565565 TX Bit2 (977~1002) 26 989, Bit10 (970~993) 24 981,
2852 11:10:24.569074 TX Bit3 (976~1000) 25 988, Bit11 (970~994) 25 982,
2853 11:10:24.572682 TX Bit4 (978~1004) 27 991, Bit12 (970~994) 25 982,
2854 11:10:24.578863 TX Bit5 (980~1005) 26 992, Bit13 (972~994) 23 983,
2855 11:10:24.582538 TX Bit6 (978~1003) 26 990, Bit14 (970~993) 24 981,
2856 11:10:24.588750 TX Bit7 (978~1003) 26 990, Bit15 (966~988) 23 977,
2857 11:10:24.589144
2858 11:10:24.589443 Write Rank0 MR14 =0x24
2859 11:10:24.599511
2860 11:10:24.602636 CH=1, VrefRange= 0, VrefLevel = 36
2861 11:10:24.605765 TX Bit0 (979~1006) 28 992, Bit8 (968~991) 24 979,
2862 11:10:24.609360 TX Bit1 (978~1003) 26 990, Bit9 (969~991) 23 980,
2863 11:10:24.616447 TX Bit2 (977~1002) 26 989, Bit10 (970~993) 24 981,
2864 11:10:24.619548 TX Bit3 (976~1000) 25 988, Bit11 (970~994) 25 982,
2865 11:10:24.622662 TX Bit4 (978~1004) 27 991, Bit12 (970~994) 25 982,
2866 11:10:24.628993 TX Bit5 (980~1005) 26 992, Bit13 (972~994) 23 983,
2867 11:10:24.632781 TX Bit6 (978~1003) 26 990, Bit14 (970~993) 24 981,
2868 11:10:24.639421 TX Bit7 (978~1003) 26 990, Bit15 (966~988) 23 977,
2869 11:10:24.639880
2870 11:10:24.640183 Write Rank0 MR14 =0x26
2871 11:10:24.650467
2872 11:10:24.653175 CH=1, VrefRange= 0, VrefLevel = 38
2873 11:10:24.657159 TX Bit0 (979~1006) 28 992, Bit8 (968~991) 24 979,
2874 11:10:24.660084 TX Bit1 (978~1003) 26 990, Bit9 (969~991) 23 980,
2875 11:10:24.666856 TX Bit2 (977~1002) 26 989, Bit10 (970~993) 24 981,
2876 11:10:24.670477 TX Bit3 (976~1000) 25 988, Bit11 (970~994) 25 982,
2877 11:10:24.673352 TX Bit4 (978~1004) 27 991, Bit12 (970~994) 25 982,
2878 11:10:24.680364 TX Bit5 (980~1005) 26 992, Bit13 (972~994) 23 983,
2879 11:10:24.683262 TX Bit6 (978~1003) 26 990, Bit14 (970~993) 24 981,
2880 11:10:24.690011 TX Bit7 (978~1003) 26 990, Bit15 (966~988) 23 977,
2881 11:10:24.690583
2882 11:10:24.691018
2883 11:10:24.693433 TX Vref found, early break! 373< 380
2884 11:10:24.696552 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
2885 11:10:24.700044 u1DelayCellOfst[0]=5 cells (4 PI)
2886 11:10:24.703487 u1DelayCellOfst[1]=2 cells (2 PI)
2887 11:10:24.706575 u1DelayCellOfst[2]=1 cells (1 PI)
2888 11:10:24.709993 u1DelayCellOfst[3]=0 cells (0 PI)
2889 11:10:24.713092 u1DelayCellOfst[4]=3 cells (3 PI)
2890 11:10:24.716340 u1DelayCellOfst[5]=5 cells (4 PI)
2891 11:10:24.719853 u1DelayCellOfst[6]=2 cells (2 PI)
2892 11:10:24.720256 u1DelayCellOfst[7]=2 cells (2 PI)
2893 11:10:24.723031 Byte0, DQ PI dly=988, DQM PI dly= 990
2894 11:10:24.729815 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
2895 11:10:24.730208
2896 11:10:24.733745 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
2897 11:10:24.734136
2898 11:10:24.736787 u1DelayCellOfst[8]=2 cells (2 PI)
2899 11:10:24.740197 u1DelayCellOfst[9]=3 cells (3 PI)
2900 11:10:24.743393 u1DelayCellOfst[10]=5 cells (4 PI)
2901 11:10:24.746529 u1DelayCellOfst[11]=6 cells (5 PI)
2902 11:10:24.749813 u1DelayCellOfst[12]=6 cells (5 PI)
2903 11:10:24.753423 u1DelayCellOfst[13]=7 cells (6 PI)
2904 11:10:24.756567 u1DelayCellOfst[14]=5 cells (4 PI)
2905 11:10:24.756955 u1DelayCellOfst[15]=0 cells (0 PI)
2906 11:10:24.759945 Byte1, DQ PI dly=977, DQM PI dly= 980
2907 11:10:24.766826 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
2908 11:10:24.767217
2909 11:10:24.769909 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
2910 11:10:24.770339
2911 11:10:24.773191 Write Rank0 MR14 =0x1c
2912 11:10:24.773759
2913 11:10:24.774070 Final TX Range 0 Vref 28
2914 11:10:24.776971
2915 11:10:24.779862 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2916 11:10:24.783474
2917 11:10:24.786345 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2918 11:10:24.796589 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2919 11:10:24.802856 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2920 11:10:24.803376 Write Rank0 MR3 =0xb0
2921 11:10:24.806658 DramC Write-DBI on
2922 11:10:24.807159 ==
2923 11:10:24.810339 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2924 11:10:24.813148 fsp= 1, odt_onoff= 1, Byte mode= 0
2925 11:10:24.813538 ==
2926 11:10:24.819657 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2927 11:10:24.820104
2928 11:10:24.822967 Begin, DQ Scan Range 700~764
2929 11:10:24.823411
2930 11:10:24.823707
2931 11:10:24.823981 TX Vref Scan disable
2932 11:10:24.826463 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2933 11:10:24.829908 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2934 11:10:24.833047 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2935 11:10:24.839798 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2936 11:10:24.843041 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2937 11:10:24.846381 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2938 11:10:24.850215 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2939 11:10:24.852913 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2940 11:10:24.856578 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2941 11:10:24.860213 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2942 11:10:24.863270 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2943 11:10:24.866744 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2944 11:10:24.869614 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2945 11:10:24.872991 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2946 11:10:24.876024 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2947 11:10:24.879776 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2948 11:10:24.883165 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2949 11:10:24.886520 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2950 11:10:24.890188 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2951 11:10:24.893389 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
2952 11:10:24.896425 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
2953 11:10:24.899598 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
2954 11:10:24.902940 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
2955 11:10:24.911454 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2956 11:10:24.915228 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2957 11:10:24.918110 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2958 11:10:24.921649 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2959 11:10:24.924959 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2960 11:10:24.928364 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2961 11:10:24.931603 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2962 11:10:24.935284 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2963 11:10:24.938023 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
2964 11:10:24.941696 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
2965 11:10:24.944938 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
2966 11:10:24.948401 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
2967 11:10:24.951742 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
2968 11:10:24.955303 750 |2 6 46|[0] xxxxxxxx xxxxxxxx [MSB]
2969 11:10:24.958683 Byte0, DQ PI dly=736, DQM PI dly= 736
2970 11:10:24.965139 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 32)
2971 11:10:24.965598
2972 11:10:24.969051 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 32)
2973 11:10:24.969512
2974 11:10:24.971844 Byte1, DQ PI dly=724, DQM PI dly= 724
2975 11:10:24.974726 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 20)
2976 11:10:24.975119
2977 11:10:24.981793 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 20)
2978 11:10:24.982318
2979 11:10:24.988238 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2980 11:10:24.994979 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2981 11:10:25.001654 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2982 11:10:25.004820 Write Rank0 MR3 =0x30
2983 11:10:25.005205 DramC Write-DBI off
2984 11:10:25.005521
2985 11:10:25.005798 [DATLAT]
2986 11:10:25.007940 Freq=1600, CH1 RK0, use_rxtx_scan=0
2987 11:10:25.008324
2988 11:10:25.011576 DATLAT Default: 0xf
2989 11:10:25.012086 7, 0xFFFF, sum=0
2990 11:10:25.015131 8, 0xFFFF, sum=0
2991 11:10:25.015605 9, 0xFFFF, sum=0
2992 11:10:25.017836 10, 0xFFFF, sum=0
2993 11:10:25.018229 11, 0xFFFF, sum=0
2994 11:10:25.021331 12, 0xFFFF, sum=0
2995 11:10:25.021723 13, 0xFFFF, sum=0
2996 11:10:25.024963 14, 0x0, sum=1
2997 11:10:25.025429 15, 0x0, sum=2
2998 11:10:25.028028 16, 0x0, sum=3
2999 11:10:25.028422 17, 0x0, sum=4
3000 11:10:25.031135 pattern=2 first_step=14 total pass=5 best_step=16
3001 11:10:25.031518 ==
3002 11:10:25.038322 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3003 11:10:25.041398 fsp= 1, odt_onoff= 1, Byte mode= 0
3004 11:10:25.041789 ==
3005 11:10:25.045325 Start DQ dly to find pass range UseTestEngine =1
3006 11:10:25.048258 x-axis: bit #, y-axis: DQ dly (-127~63)
3007 11:10:25.051753 RX Vref Scan = 1
3008 11:10:25.157639
3009 11:10:25.158236 RX Vref found, early break!
3010 11:10:25.158576
3011 11:10:25.164871 Final RX Vref 11, apply to both rank0 and 1
3012 11:10:25.165376 ==
3013 11:10:25.167922 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3014 11:10:25.171219 fsp= 1, odt_onoff= 1, Byte mode= 0
3015 11:10:25.171644 ==
3016 11:10:25.171977 DQS Delay:
3017 11:10:25.174922 DQS0 = 0, DQS1 = 0
3018 11:10:25.175419 DQM Delay:
3019 11:10:25.178211 DQM0 = 20, DQM1 = 19
3020 11:10:25.178706 DQ Delay:
3021 11:10:25.181257 DQ0 =22, DQ1 =22, DQ2 =18, DQ3 =16
3022 11:10:25.184257 DQ4 =22, DQ5 =23, DQ6 =23, DQ7 =21
3023 11:10:25.187719 DQ8 =17, DQ9 =16, DQ10 =20, DQ11 =22
3024 11:10:25.190871 DQ12 =22, DQ13 =21, DQ14 =23, DQ15 =13
3025 11:10:25.191258
3026 11:10:25.191554
3027 11:10:25.191827
3028 11:10:25.193970 [DramC_TX_OE_Calibration] TA2
3029 11:10:25.197754 Original DQ_B0 (3 6) =30, OEN = 27
3030 11:10:25.200805 Original DQ_B1 (3 6) =30, OEN = 27
3031 11:10:25.204410 23, 0x0, End_B0=23 End_B1=23
3032 11:10:25.204944 24, 0x0, End_B0=24 End_B1=24
3033 11:10:25.207880 25, 0x0, End_B0=25 End_B1=25
3034 11:10:25.211313 26, 0x0, End_B0=26 End_B1=26
3035 11:10:25.214201 27, 0x0, End_B0=27 End_B1=27
3036 11:10:25.214593 28, 0x0, End_B0=28 End_B1=28
3037 11:10:25.217773 29, 0x0, End_B0=29 End_B1=29
3038 11:10:25.221088 30, 0x0, End_B0=30 End_B1=30
3039 11:10:25.224502 31, 0xFFFF, End_B0=30 End_B1=30
3040 11:10:25.230967 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3041 11:10:25.234611 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3042 11:10:25.235074
3043 11:10:25.235374
3044 11:10:25.238540 Write Rank0 MR23 =0x3f
3045 11:10:25.239000 [DQSOSC]
3046 11:10:25.248132 [DQSOSCAuto] RK0, (LSB)MR18= 0xc0c0, (MSB)MR19= 0x202, tDQSOscB0 = 447 ps tDQSOscB1 = 447 ps
3047 11:10:25.251139 CH1_RK0: MR19=0x202, MR18=0xC0C0, DQSOSC=447, MR23=63, INC=12, DEC=18
3048 11:10:25.255010 Write Rank0 MR23 =0x3f
3049 11:10:25.255472 [DQSOSC]
3050 11:10:25.264884 [DQSOSCAuto] RK0, (LSB)MR18= 0xbfbf, (MSB)MR19= 0x202, tDQSOscB0 = 448 ps tDQSOscB1 = 448 ps
3051 11:10:25.265349 CH1 RK0: MR19=202, MR18=BFBF
3052 11:10:25.271068 [RankSwap] Rank num 2, (Multi 1), Rank 1
3053 11:10:25.271519 Write Rank0 MR2 =0xad
3054 11:10:25.274575 [Write Leveling]
3055 11:10:25.277878 delay byte0 byte1 byte2 byte3
3056 11:10:25.278337
3057 11:10:25.278644 10 0 0
3058 11:10:25.278933 11 0 0
3059 11:10:25.280993 12 0 0
3060 11:10:25.281384 13 0 0
3061 11:10:25.284446 14 0 0
3062 11:10:25.284980 15 0 0
3063 11:10:25.285290 16 0 0
3064 11:10:25.287793 17 0 0
3065 11:10:25.288382 18 0 0
3066 11:10:25.291008 19 0 0
3067 11:10:25.291400 20 0 0
3068 11:10:25.294371 21 0 0
3069 11:10:25.294763 22 0 0
3070 11:10:25.295070 23 0 0
3071 11:10:25.297552 24 0 0
3072 11:10:25.297949 25 0 ff
3073 11:10:25.300964 26 0 ff
3074 11:10:25.301358 27 0 ff
3075 11:10:25.304779 28 0 ff
3076 11:10:25.305250 29 0 ff
3077 11:10:25.305559 30 0 ff
3078 11:10:25.307708 31 0 ff
3079 11:10:25.308101 32 0 ff
3080 11:10:25.311279 33 0 ff
3081 11:10:25.311747 34 ff ff
3082 11:10:25.314227 35 ff ff
3083 11:10:25.314622 36 ff ff
3084 11:10:25.317871 37 ff ff
3085 11:10:25.318264 38 ff ff
3086 11:10:25.321267 39 ff ff
3087 11:10:25.321658 40 ff ff
3088 11:10:25.324830 pass bytecount = 0xff (0xff: all bytes pass)
3089 11:10:25.325297
3090 11:10:25.327745 DQS0 dly: 34
3091 11:10:25.328152 DQS1 dly: 25
3092 11:10:25.331178 Write Rank0 MR2 =0x2d
3093 11:10:25.334143 [RankSwap] Rank num 2, (Multi 1), Rank 0
3094 11:10:25.334531 Write Rank1 MR1 =0xd6
3095 11:10:25.337725 [Gating]
3096 11:10:25.338182 ==
3097 11:10:25.341197 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3098 11:10:25.344522 fsp= 1, odt_onoff= 1, Byte mode= 0
3099 11:10:25.344985 ==
3100 11:10:25.350682 3 1 0 |3636 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
3101 11:10:25.354091 3 1 4 |2828 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
3102 11:10:25.357538 3 1 8 |3434 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
3103 11:10:25.360773 3 1 12 |3434 2c2b |(0 0)(11 11) |(0 1)(1 0)| 0
3104 11:10:25.367393 3 1 16 |3433 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3105 11:10:25.371139 3 1 20 |3433 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3106 11:10:25.374000 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3107 11:10:25.381107 3 1 28 |b0b 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3108 11:10:25.384072 3 2 0 |a0a 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3109 11:10:25.387342 3 2 4 |2b2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3110 11:10:25.390659 3 2 8 |202 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3111 11:10:25.397452 3 2 12 |403 201 |(11 11)(11 11) |(1 1)(0 0)| 0
3112 11:10:25.400549 3 2 16 |403 c0c |(11 11)(11 11) |(1 1)(0 0)| 0
3113 11:10:25.403707 [Byte 0] Lead/lag Transition tap number (1)
3114 11:10:25.407228 3 2 20 |3c3b 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
3115 11:10:25.413604 3 2 24 |3a3a 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3116 11:10:25.417488 3 2 28 |3332 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
3117 11:10:25.420440 3 3 0 |706 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3118 11:10:25.427068 3 3 4 |3838 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3119 11:10:25.430417 3 3 8 |807 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3120 11:10:25.434053 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3121 11:10:25.440549 [Byte 0] Lead/lag falling Transition (3, 3, 12)
3122 11:10:25.444144 3 3 16 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
3123 11:10:25.447132 [Byte 1] Lead/lag Transition tap number (1)
3124 11:10:25.450601 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3125 11:10:25.457811 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3126 11:10:25.460355 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3127 11:10:25.463903 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3128 11:10:25.470541 3 4 4 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3129 11:10:25.473737 3 4 8 |e0e 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3130 11:10:25.476954 3 4 12 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
3131 11:10:25.480514 3 4 16 |3d3d 1c1b |(11 11)(11 11) |(1 1)(1 1)| 0
3132 11:10:25.486775 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3133 11:10:25.490101 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3134 11:10:25.493442 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3135 11:10:25.500690 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3136 11:10:25.503275 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3137 11:10:25.506724 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3138 11:10:25.513702 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3139 11:10:25.517012 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3140 11:10:25.520093 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3141 11:10:25.526957 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3142 11:10:25.530083 [Byte 0] Lead/lag falling Transition (3, 5, 24)
3143 11:10:25.533790 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3144 11:10:25.536786 [Byte 0] Lead/lag Transition tap number (2)
3145 11:10:25.543290 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3146 11:10:25.547126 3 6 4 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3147 11:10:25.550153 [Byte 1] Lead/lag falling Transition (3, 6, 4)
3148 11:10:25.556723 3 6 8 |a0a 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3149 11:10:25.559878 [Byte 1] Lead/lag Transition tap number (2)
3150 11:10:25.563636 3 6 12 |4646 2c2c |(0 0)(11 11) |(0 0)(0 0)| 0
3151 11:10:25.567167 [Byte 0]First pass (3, 6, 12)
3152 11:10:25.570386 3 6 16 |4646 a0a |(0 0)(11 11) |(0 0)(0 0)| 0
3153 11:10:25.573384 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3154 11:10:25.576765 [Byte 1]First pass (3, 6, 20)
3155 11:10:25.579974 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3156 11:10:25.583386 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3157 11:10:25.590007 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3158 11:10:25.593279 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3159 11:10:25.596541 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3160 11:10:25.599841 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3161 11:10:25.606532 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3162 11:10:25.609789 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3163 11:10:25.613075 All bytes gating window > 1UI, Early break!
3164 11:10:25.613457
3165 11:10:25.616405 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 28)
3166 11:10:25.616823
3167 11:10:25.619550 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 8)
3168 11:10:25.619932
3169 11:10:25.620226
3170 11:10:25.620533
3171 11:10:25.622971 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 28)
3172 11:10:25.626269
3173 11:10:25.629547 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
3174 11:10:25.629932
3175 11:10:25.630227
3176 11:10:25.630499 Write Rank1 MR1 =0x56
3177 11:10:25.630764
3178 11:10:25.633383 best RODT dly(2T, 0.5T) = (2, 2)
3179 11:10:25.633767
3180 11:10:25.636548 best RODT dly(2T, 0.5T) = (2, 3)
3181 11:10:25.636938 ==
3182 11:10:25.643289 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3183 11:10:25.646743 fsp= 1, odt_onoff= 1, Byte mode= 0
3184 11:10:25.647203 ==
3185 11:10:25.649973 Start DQ dly to find pass range UseTestEngine =0
3186 11:10:25.653459 x-axis: bit #, y-axis: DQ dly (-127~63)
3187 11:10:25.656217 RX Vref Scan = 0
3188 11:10:25.659943 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3189 11:10:25.660423 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3190 11:10:25.663167 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3191 11:10:25.666225 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3192 11:10:25.669607 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3193 11:10:25.673122 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3194 11:10:25.676393 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3195 11:10:25.679524 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3196 11:10:25.682575 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3197 11:10:25.685934 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3198 11:10:25.686444 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3199 11:10:25.689381 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3200 11:10:25.693212 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3201 11:10:25.696149 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3202 11:10:25.699690 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3203 11:10:25.703004 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3204 11:10:25.706298 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3205 11:10:25.709755 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3206 11:10:25.710216 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3207 11:10:25.712896 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3208 11:10:25.716161 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3209 11:10:25.719243 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3210 11:10:25.722849 -4, [0] xxxxxxxx xxxxxxxo [MSB]
3211 11:10:25.726034 -3, [0] xxxoxxxx xxxxxxxo [MSB]
3212 11:10:25.729330 -2, [0] xxxoxxxx xoxxxxxo [MSB]
3213 11:10:25.729718 -1, [0] xxxoxxxx xoxxxxxo [MSB]
3214 11:10:25.732532 0, [0] xxooxxxx ooxxxxxo [MSB]
3215 11:10:25.736405 1, [0] xxooxxxx ooxxxxxo [MSB]
3216 11:10:25.739383 2, [0] xxooxxxo ooxxxxxo [MSB]
3217 11:10:25.742344 3, [0] xxoooxxo oooxxxxo [MSB]
3218 11:10:25.745699 4, [0] oooooxoo ooooooxo [MSB]
3219 11:10:25.749131 5, [0] oooooooo ooooooxo [MSB]
3220 11:10:25.749600 32, [0] oooooooo ooooooox [MSB]
3221 11:10:25.752087 33, [0] oooooooo ooooooox [MSB]
3222 11:10:25.755714 34, [0] oooooooo ooooooox [MSB]
3223 11:10:25.758727 35, [0] oooxoooo xxooooox [MSB]
3224 11:10:25.762286 36, [0] oooxoooo xxooooox [MSB]
3225 11:10:25.765461 37, [0] ooxxoooo xxooooox [MSB]
3226 11:10:25.768649 38, [0] ooxxoooo xxooooox [MSB]
3227 11:10:25.769037 39, [0] oxxxxoox xxooooox [MSB]
3228 11:10:25.771964 40, [0] oxxxxoox xxxoooox [MSB]
3229 11:10:25.775590 41, [0] oxxxxoox xxxxxxox [MSB]
3230 11:10:25.778822 42, [0] xxxxxxxx xxxxxxxx [MSB]
3231 11:10:25.782314 iDelay=42, Bit 0, Center 22 (4 ~ 41) 38
3232 11:10:25.785784 iDelay=42, Bit 1, Center 21 (4 ~ 38) 35
3233 11:10:25.789171 iDelay=42, Bit 2, Center 18 (0 ~ 36) 37
3234 11:10:25.791965 iDelay=42, Bit 3, Center 15 (-3 ~ 34) 38
3235 11:10:25.795716 iDelay=42, Bit 4, Center 20 (3 ~ 38) 36
3236 11:10:25.798864 iDelay=42, Bit 5, Center 23 (5 ~ 41) 37
3237 11:10:25.802223 iDelay=42, Bit 6, Center 22 (4 ~ 41) 38
3238 11:10:25.808528 iDelay=42, Bit 7, Center 20 (2 ~ 38) 37
3239 11:10:25.811791 iDelay=42, Bit 8, Center 17 (0 ~ 34) 35
3240 11:10:25.815148 iDelay=42, Bit 9, Center 16 (-2 ~ 34) 37
3241 11:10:25.818524 iDelay=42, Bit 10, Center 21 (3 ~ 39) 37
3242 11:10:25.821949 iDelay=42, Bit 11, Center 22 (4 ~ 40) 37
3243 11:10:25.825154 iDelay=42, Bit 12, Center 22 (4 ~ 40) 37
3244 11:10:25.828523 iDelay=42, Bit 13, Center 22 (4 ~ 40) 37
3245 11:10:25.831916 iDelay=42, Bit 14, Center 23 (6 ~ 41) 36
3246 11:10:25.835010 iDelay=42, Bit 15, Center 13 (-4 ~ 31) 36
3247 11:10:25.835395 ==
3248 11:10:25.841628 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3249 11:10:25.844779 fsp= 1, odt_onoff= 1, Byte mode= 0
3250 11:10:25.845165 ==
3251 11:10:25.845492 DQS Delay:
3252 11:10:25.848072 DQS0 = 0, DQS1 = 0
3253 11:10:25.848501 DQM Delay:
3254 11:10:25.851465 DQM0 = 20, DQM1 = 19
3255 11:10:25.851844 DQ Delay:
3256 11:10:25.855187 DQ0 =22, DQ1 =21, DQ2 =18, DQ3 =15
3257 11:10:25.858464 DQ4 =20, DQ5 =23, DQ6 =22, DQ7 =20
3258 11:10:25.861564 DQ8 =17, DQ9 =16, DQ10 =21, DQ11 =22
3259 11:10:25.865174 DQ12 =22, DQ13 =22, DQ14 =23, DQ15 =13
3260 11:10:25.865556
3261 11:10:25.865849
3262 11:10:25.866122 DramC Write-DBI off
3263 11:10:25.868615 ==
3264 11:10:25.871802 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3265 11:10:25.875168 fsp= 1, odt_onoff= 1, Byte mode= 0
3266 11:10:25.875635 ==
3267 11:10:25.878337 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3268 11:10:25.878735
3269 11:10:25.881801 Begin, DQ Scan Range 921~1177
3270 11:10:25.882259
3271 11:10:25.882559
3272 11:10:25.884918 TX Vref Scan disable
3273 11:10:25.888236 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
3274 11:10:25.891816 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
3275 11:10:25.894537 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
3276 11:10:25.897812 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
3277 11:10:25.901635 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
3278 11:10:25.904741 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
3279 11:10:25.907837 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
3280 11:10:25.911519 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3281 11:10:25.918150 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3282 11:10:25.921313 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3283 11:10:25.924726 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3284 11:10:25.927841 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3285 11:10:25.931135 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3286 11:10:25.934677 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3287 11:10:25.938677 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3288 11:10:25.941303 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3289 11:10:25.944623 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3290 11:10:25.947590 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3291 11:10:25.951040 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3292 11:10:25.954717 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3293 11:10:25.957631 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3294 11:10:25.961049 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3295 11:10:25.964085 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3296 11:10:25.967358 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3297 11:10:25.974371 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3298 11:10:25.977808 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3299 11:10:25.981205 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3300 11:10:25.984818 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3301 11:10:25.987757 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3302 11:10:25.991452 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3303 11:10:25.994411 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3304 11:10:25.997505 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3305 11:10:26.001338 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3306 11:10:26.004235 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3307 11:10:26.007258 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3308 11:10:26.010981 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3309 11:10:26.014374 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3310 11:10:26.017798 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3311 11:10:26.021162 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3312 11:10:26.024113 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3313 11:10:26.030610 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3314 11:10:26.034314 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3315 11:10:26.037231 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3316 11:10:26.040974 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3317 11:10:26.043999 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3318 11:10:26.047113 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3319 11:10:26.050623 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3320 11:10:26.054350 968 |3 6 8|[0] xxxxxxxx xxxxxxxo [MSB]
3321 11:10:26.057407 969 |3 6 9|[0] xxxxxxxx xxxxxxxo [MSB]
3322 11:10:26.060946 970 |3 6 10|[0] xxxxxxxx ooxxxxxo [MSB]
3323 11:10:26.063810 971 |3 6 11|[0] xxxxxxxx ooxxxxxo [MSB]
3324 11:10:26.067146 972 |3 6 12|[0] xxxxxxxx oooxxxxo [MSB]
3325 11:10:26.070568 973 |3 6 13|[0] xxxxxxxx ooooxooo [MSB]
3326 11:10:26.074007 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
3327 11:10:26.077743 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
3328 11:10:26.080683 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
3329 11:10:26.084320 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
3330 11:10:26.087174 978 |3 6 18|[0] xooooxxx oooooooo [MSB]
3331 11:10:26.091132 979 |3 6 19|[0] ooooooox oooooooo [MSB]
3332 11:10:26.098317 986 |3 6 26|[0] oooooooo ooooooox [MSB]
3333 11:10:26.101305 987 |3 6 27|[0] oooooooo ooooooox [MSB]
3334 11:10:26.104872 988 |3 6 28|[0] oooooooo ooooooox [MSB]
3335 11:10:26.108611 989 |3 6 29|[0] oooooooo ooooooox [MSB]
3336 11:10:26.111593 990 |3 6 30|[0] oooooooo xxooooox [MSB]
3337 11:10:26.115021 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
3338 11:10:26.118481 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
3339 11:10:26.121702 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
3340 11:10:26.125266 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
3341 11:10:26.128401 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
3342 11:10:26.131561 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
3343 11:10:26.135191 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
3344 11:10:26.138394 998 |3 6 38|[0] oooxoooo xxxxxxxx [MSB]
3345 11:10:26.141671 999 |3 6 39|[0] oooxoooo xxxxxxxx [MSB]
3346 11:10:26.144997 1000 |3 6 40|[0] ooxxooox xxxxxxxx [MSB]
3347 11:10:26.151662 1001 |3 6 41|[0] oxxxxoxx xxxxxxxx [MSB]
3348 11:10:26.154547 1002 |3 6 42|[0] xxxxxxxx xxxxxxxx [MSB]
3349 11:10:26.158042 Byte0, DQ PI dly=988, DQM PI dly= 988
3350 11:10:26.161684 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
3351 11:10:26.162171
3352 11:10:26.164814 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
3353 11:10:26.165200
3354 11:10:26.168309 Byte1, DQ PI dly=979, DQM PI dly= 979
3355 11:10:26.175047 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
3356 11:10:26.175511
3357 11:10:26.178242 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
3358 11:10:26.178709
3359 11:10:26.179006 ==
3360 11:10:26.184831 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3361 11:10:26.188036 fsp= 1, odt_onoff= 1, Byte mode= 0
3362 11:10:26.188536 ==
3363 11:10:26.191714 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3364 11:10:26.192182
3365 11:10:26.194714 Begin, DQ Scan Range 955~1019
3366 11:10:26.195177 Write Rank1 MR14 =0x0
3367 11:10:26.204357
3368 11:10:26.204908 CH=1, VrefRange= 0, VrefLevel = 0
3369 11:10:26.211212 TX Bit0 (983~998) 16 990, Bit8 (971~985) 15 978,
3370 11:10:26.214725 TX Bit1 (981~996) 16 988, Bit9 (972~985) 14 978,
3371 11:10:26.221213 TX Bit2 (979~993) 15 986, Bit10 (976~986) 11 981,
3372 11:10:26.224743 TX Bit3 (978~990) 13 984, Bit11 (976~988) 13 982,
3373 11:10:26.227508 TX Bit4 (981~996) 16 988, Bit12 (977~986) 10 981,
3374 11:10:26.234770 TX Bit5 (982~998) 17 990, Bit13 (976~989) 14 982,
3375 11:10:26.237989 TX Bit6 (982~997) 16 989, Bit14 (976~986) 11 981,
3376 11:10:26.241208 TX Bit7 (983~994) 12 988, Bit15 (969~979) 11 974,
3377 11:10:26.241709
3378 11:10:26.244425 Write Rank1 MR14 =0x2
3379 11:10:26.253368
3380 11:10:26.253891 CH=1, VrefRange= 0, VrefLevel = 2
3381 11:10:26.260195 TX Bit0 (982~998) 17 990, Bit8 (971~985) 15 978,
3382 11:10:26.263266 TX Bit1 (980~997) 18 988, Bit9 (971~985) 15 978,
3383 11:10:26.270268 TX Bit2 (978~994) 17 986, Bit10 (975~987) 13 981,
3384 11:10:26.273262 TX Bit3 (978~991) 14 984, Bit11 (976~989) 14 982,
3385 11:10:26.276582 TX Bit4 (980~996) 17 988, Bit12 (976~987) 12 981,
3386 11:10:26.283385 TX Bit5 (982~998) 17 990, Bit13 (976~990) 15 983,
3387 11:10:26.286150 TX Bit6 (981~998) 18 989, Bit14 (976~987) 12 981,
3388 11:10:26.290086 TX Bit7 (983~995) 13 989, Bit15 (969~981) 13 975,
3389 11:10:26.293362
3390 11:10:26.296634 wait MRW command Rank1 MR14 =0x4 fired (1)
3391 11:10:26.297168 Write Rank1 MR14 =0x4
3392 11:10:26.306309
3393 11:10:26.306806 CH=1, VrefRange= 0, VrefLevel = 4
3394 11:10:26.312909 TX Bit0 (982~999) 18 990, Bit8 (970~986) 17 978,
3395 11:10:26.315997 TX Bit1 (981~998) 18 989, Bit9 (971~985) 15 978,
3396 11:10:26.322738 TX Bit2 (979~995) 17 987, Bit10 (975~987) 13 981,
3397 11:10:26.325900 TX Bit3 (978~991) 14 984, Bit11 (976~989) 14 982,
3398 11:10:26.329541 TX Bit4 (980~997) 18 988, Bit12 (975~988) 14 981,
3399 11:10:26.336257 TX Bit5 (982~999) 18 990, Bit13 (975~990) 16 982,
3400 11:10:26.339748 TX Bit6 (981~998) 18 989, Bit14 (976~987) 12 981,
3401 11:10:26.342728 TX Bit7 (983~996) 14 989, Bit15 (969~983) 15 976,
3402 11:10:26.343193
3403 11:10:26.346334 Write Rank1 MR14 =0x6
3404 11:10:26.355397
3405 11:10:26.355916 CH=1, VrefRange= 0, VrefLevel = 6
3406 11:10:26.361630 TX Bit0 (981~999) 19 990, Bit8 (970~986) 17 978,
3407 11:10:26.365067 TX Bit1 (980~998) 19 989, Bit9 (971~986) 16 978,
3408 11:10:26.368773 TX Bit2 (978~996) 19 987, Bit10 (974~988) 15 981,
3409 11:10:26.375290 TX Bit3 (977~992) 16 984, Bit11 (975~990) 16 982,
3410 11:10:26.378383 TX Bit4 (979~998) 20 988, Bit12 (976~989) 14 982,
3411 11:10:26.384948 TX Bit5 (981~999) 19 990, Bit13 (975~991) 17 983,
3412 11:10:26.388575 TX Bit6 (980~999) 20 989, Bit14 (975~988) 14 981,
3413 11:10:26.391989 TX Bit7 (982~997) 16 989, Bit15 (969~982) 14 975,
3414 11:10:26.392544
3415 11:10:26.395195 Write Rank1 MR14 =0x8
3416 11:10:26.403816
3417 11:10:26.404278 CH=1, VrefRange= 0, VrefLevel = 8
3418 11:10:26.410493 TX Bit0 (981~1000) 20 990, Bit8 (970~986) 17 978,
3419 11:10:26.414166 TX Bit1 (979~998) 20 988, Bit9 (971~986) 16 978,
3420 11:10:26.420600 TX Bit2 (978~997) 20 987, Bit10 (974~990) 17 982,
3421 11:10:26.423736 TX Bit3 (977~993) 17 985, Bit11 (975~991) 17 983,
3422 11:10:26.427210 TX Bit4 (979~998) 20 988, Bit12 (975~990) 16 982,
3423 11:10:26.433597 TX Bit5 (981~999) 19 990, Bit13 (975~991) 17 983,
3424 11:10:26.437529 TX Bit6 (980~999) 20 989, Bit14 (974~989) 16 981,
3425 11:10:26.440705 TX Bit7 (981~997) 17 989, Bit15 (969~983) 15 976,
3426 11:10:26.441268
3427 11:10:26.443497 Write Rank1 MR14 =0xa
3428 11:10:26.453221
3429 11:10:26.453613 CH=1, VrefRange= 0, VrefLevel = 10
3430 11:10:26.459430 TX Bit0 (980~1000) 21 990, Bit8 (970~987) 18 978,
3431 11:10:26.463300 TX Bit1 (979~999) 21 989, Bit9 (971~987) 17 979,
3432 11:10:26.469631 TX Bit2 (978~997) 20 987, Bit10 (973~990) 18 981,
3433 11:10:26.472961 TX Bit3 (977~994) 18 985, Bit11 (975~991) 17 983,
3434 11:10:26.476180 TX Bit4 (979~999) 21 989, Bit12 (975~991) 17 983,
3435 11:10:26.483263 TX Bit5 (981~1000) 20 990, Bit13 (975~992) 18 983,
3436 11:10:26.486729 TX Bit6 (979~999) 21 989, Bit14 (974~990) 17 982,
3437 11:10:26.493187 TX Bit7 (981~998) 18 989, Bit15 (968~984) 17 976,
3438 11:10:26.493571
3439 11:10:26.493869 Write Rank1 MR14 =0xc
3440 11:10:26.502703
3441 11:10:26.505735 CH=1, VrefRange= 0, VrefLevel = 12
3442 11:10:26.509193 TX Bit0 (981~1000) 20 990, Bit8 (970~987) 18 978,
3443 11:10:26.512398 TX Bit1 (979~999) 21 989, Bit9 (970~987) 18 978,
3444 11:10:26.518933 TX Bit2 (978~998) 21 988, Bit10 (973~991) 19 982,
3445 11:10:26.521999 TX Bit3 (977~994) 18 985, Bit11 (974~991) 18 982,
3446 11:10:26.525724 TX Bit4 (978~999) 22 988, Bit12 (975~991) 17 983,
3447 11:10:26.532286 TX Bit5 (980~1000) 21 990, Bit13 (974~992) 19 983,
3448 11:10:26.535562 TX Bit6 (979~999) 21 989, Bit14 (973~991) 19 982,
3449 11:10:26.542168 TX Bit7 (980~999) 20 989, Bit15 (968~984) 17 976,
3450 11:10:26.542628
3451 11:10:26.543009 Write Rank1 MR14 =0xe
3452 11:10:26.552073
3453 11:10:26.555341 CH=1, VrefRange= 0, VrefLevel = 14
3454 11:10:26.558771 TX Bit0 (980~1001) 22 990, Bit8 (970~988) 19 979,
3455 11:10:26.561945 TX Bit1 (978~999) 22 988, Bit9 (970~988) 19 979,
3456 11:10:26.568434 TX Bit2 (978~998) 21 988, Bit10 (972~991) 20 981,
3457 11:10:26.571935 TX Bit3 (976~996) 21 986, Bit11 (974~992) 19 983,
3458 11:10:26.575236 TX Bit4 (978~999) 22 988, Bit12 (974~991) 18 982,
3459 11:10:26.581750 TX Bit5 (979~1001) 23 990, Bit13 (974~992) 19 983,
3460 11:10:26.585579 TX Bit6 (979~1000) 22 989, Bit14 (974~991) 18 982,
3461 11:10:26.591960 TX Bit7 (980~999) 20 989, Bit15 (968~985) 18 976,
3462 11:10:26.592348
3463 11:10:26.592686 Write Rank1 MR14 =0x10
3464 11:10:26.601695
3465 11:10:26.605220 CH=1, VrefRange= 0, VrefLevel = 16
3466 11:10:26.608832 TX Bit0 (980~1002) 23 991, Bit8 (970~990) 21 980,
3467 11:10:26.612257 TX Bit1 (979~1000) 22 989, Bit9 (970~988) 19 979,
3468 11:10:26.619321 TX Bit2 (977~998) 22 987, Bit10 (972~991) 20 981,
3469 11:10:26.621823 TX Bit3 (976~996) 21 986, Bit11 (973~992) 20 982,
3470 11:10:26.625192 TX Bit4 (978~1000) 23 989, Bit12 (973~992) 20 982,
3471 11:10:26.631628 TX Bit5 (979~1001) 23 990, Bit13 (973~992) 20 982,
3472 11:10:26.634911 TX Bit6 (979~1000) 22 989, Bit14 (972~991) 20 981,
3473 11:10:26.641647 TX Bit7 (979~999) 21 989, Bit15 (968~985) 18 976,
3474 11:10:26.642036
3475 11:10:26.642333 Write Rank1 MR14 =0x12
3476 11:10:26.651715
3477 11:10:26.655573 CH=1, VrefRange= 0, VrefLevel = 18
3478 11:10:26.658945 TX Bit0 (979~1002) 24 990, Bit8 (969~990) 22 979,
3479 11:10:26.662221 TX Bit1 (978~1000) 23 989, Bit9 (970~990) 21 980,
3480 11:10:26.668594 TX Bit2 (977~999) 23 988, Bit10 (971~992) 22 981,
3481 11:10:26.672068 TX Bit3 (977~996) 20 986, Bit11 (973~992) 20 982,
3482 11:10:26.675210 TX Bit4 (978~1000) 23 989, Bit12 (972~992) 21 982,
3483 11:10:26.682044 TX Bit5 (979~1002) 24 990, Bit13 (973~993) 21 983,
3484 11:10:26.685272 TX Bit6 (978~1000) 23 989, Bit14 (972~992) 21 982,
3485 11:10:26.691941 TX Bit7 (980~1000) 21 990, Bit15 (967~986) 20 976,
3486 11:10:26.692389
3487 11:10:26.692749 Write Rank1 MR14 =0x14
3488 11:10:26.702095
3489 11:10:26.702587 CH=1, VrefRange= 0, VrefLevel = 20
3490 11:10:26.708529 TX Bit0 (979~1003) 25 991, Bit8 (969~991) 23 980,
3491 11:10:26.712188 TX Bit1 (978~1001) 24 989, Bit9 (970~990) 21 980,
3492 11:10:26.719112 TX Bit2 (977~999) 23 988, Bit10 (971~992) 22 981,
3493 11:10:26.722250 TX Bit3 (976~998) 23 987, Bit11 (972~993) 22 982,
3494 11:10:26.725832 TX Bit4 (978~1000) 23 989, Bit12 (972~992) 21 982,
3495 11:10:26.732227 TX Bit5 (979~1002) 24 990, Bit13 (972~993) 22 982,
3496 11:10:26.735574 TX Bit6 (978~1001) 24 989, Bit14 (972~992) 21 982,
3497 11:10:26.742093 TX Bit7 (979~1000) 22 989, Bit15 (967~986) 20 976,
3498 11:10:26.742593
3499 11:10:26.742921 Write Rank1 MR14 =0x16
3500 11:10:26.752631
3501 11:10:26.755884 CH=1, VrefRange= 0, VrefLevel = 22
3502 11:10:26.759459 TX Bit0 (978~1003) 26 990, Bit8 (969~991) 23 980,
3503 11:10:26.762435 TX Bit1 (978~1001) 24 989, Bit9 (970~991) 22 980,
3504 11:10:26.769268 TX Bit2 (977~1000) 24 988, Bit10 (971~992) 22 981,
3505 11:10:26.772248 TX Bit3 (976~998) 23 987, Bit11 (972~993) 22 982,
3506 11:10:26.775865 TX Bit4 (978~1001) 24 989, Bit12 (972~993) 22 982,
3507 11:10:26.782726 TX Bit5 (978~1003) 26 990, Bit13 (972~993) 22 982,
3508 11:10:26.785698 TX Bit6 (978~1001) 24 989, Bit14 (971~992) 22 981,
3509 11:10:26.792548 TX Bit7 (979~1000) 22 989, Bit15 (967~987) 21 977,
3510 11:10:26.792936
3511 11:10:26.793279 Write Rank1 MR14 =0x18
3512 11:10:26.803039
3513 11:10:26.806042 CH=1, VrefRange= 0, VrefLevel = 24
3514 11:10:26.809339 TX Bit0 (978~1003) 26 990, Bit8 (969~991) 23 980,
3515 11:10:26.812737 TX Bit1 (978~1002) 25 990, Bit9 (968~991) 24 979,
3516 11:10:26.819635 TX Bit2 (977~1000) 24 988, Bit10 (971~993) 23 982,
3517 11:10:26.822411 TX Bit3 (975~998) 24 986, Bit11 (971~994) 24 982,
3518 11:10:26.826362 TX Bit4 (978~1001) 24 989, Bit12 (972~993) 22 982,
3519 11:10:26.832730 TX Bit5 (978~1003) 26 990, Bit13 (972~994) 23 983,
3520 11:10:26.836449 TX Bit6 (978~1002) 25 990, Bit14 (970~992) 23 981,
3521 11:10:26.842556 TX Bit7 (979~1001) 23 990, Bit15 (967~987) 21 977,
3522 11:10:26.842857
3523 11:10:26.842922 Write Rank1 MR14 =0x1a
3524 11:10:26.852950
3525 11:10:26.856291 CH=1, VrefRange= 0, VrefLevel = 26
3526 11:10:26.859897 TX Bit0 (978~1004) 27 991, Bit8 (969~992) 24 980,
3527 11:10:26.863096 TX Bit1 (978~1002) 25 990, Bit9 (969~991) 23 980,
3528 11:10:26.869540 TX Bit2 (977~1000) 24 988, Bit10 (970~993) 24 981,
3529 11:10:26.872781 TX Bit3 (975~998) 24 986, Bit11 (971~994) 24 982,
3530 11:10:26.876535 TX Bit4 (978~1002) 25 990, Bit12 (971~993) 23 982,
3531 11:10:26.882867 TX Bit5 (978~1004) 27 991, Bit13 (971~994) 24 982,
3532 11:10:26.886491 TX Bit6 (978~1002) 25 990, Bit14 (971~993) 23 982,
3533 11:10:26.892972 TX Bit7 (979~1001) 23 990, Bit15 (966~988) 23 977,
3534 11:10:26.893247
3535 11:10:26.893416 Write Rank1 MR14 =0x1c
3536 11:10:26.903429
3537 11:10:26.906710 CH=1, VrefRange= 0, VrefLevel = 28
3538 11:10:26.910339 TX Bit0 (978~1005) 28 991, Bit8 (968~992) 25 980,
3539 11:10:26.913871 TX Bit1 (978~1003) 26 990, Bit9 (969~992) 24 980,
3540 11:10:26.920446 TX Bit2 (977~1001) 25 989, Bit10 (970~993) 24 981,
3541 11:10:26.923569 TX Bit3 (975~999) 25 987, Bit11 (971~994) 24 982,
3542 11:10:26.926902 TX Bit4 (978~1002) 25 990, Bit12 (971~993) 23 982,
3543 11:10:26.933763 TX Bit5 (979~1004) 26 991, Bit13 (971~995) 25 983,
3544 11:10:26.936907 TX Bit6 (977~1003) 27 990, Bit14 (970~993) 24 981,
3545 11:10:26.943415 TX Bit7 (978~1002) 25 990, Bit15 (966~989) 24 977,
3546 11:10:26.943734
3547 11:10:26.943912 Write Rank1 MR14 =0x1e
3548 11:10:26.954703
3549 11:10:26.958139 CH=1, VrefRange= 0, VrefLevel = 30
3550 11:10:26.961440 TX Bit0 (978~1005) 28 991, Bit8 (968~992) 25 980,
3551 11:10:26.964910 TX Bit1 (978~1003) 26 990, Bit9 (969~991) 23 980,
3552 11:10:26.970968 TX Bit2 (976~1001) 26 988, Bit10 (970~994) 25 982,
3553 11:10:26.974170 TX Bit3 (975~999) 25 987, Bit11 (970~994) 25 982,
3554 11:10:26.977677 TX Bit4 (977~1003) 27 990, Bit12 (971~994) 24 982,
3555 11:10:26.983946 TX Bit5 (978~1004) 27 991, Bit13 (971~995) 25 983,
3556 11:10:26.987237 TX Bit6 (977~1003) 27 990, Bit14 (970~994) 25 982,
3557 11:10:26.993895 TX Bit7 (978~1002) 25 990, Bit15 (966~990) 25 978,
3558 11:10:26.993976
3559 11:10:26.994047 Write Rank1 MR14 =0x20
3560 11:10:27.004895
3561 11:10:27.007851 CH=1, VrefRange= 0, VrefLevel = 32
3562 11:10:27.011298 TX Bit0 (978~1005) 28 991, Bit8 (968~992) 25 980,
3563 11:10:27.014620 TX Bit1 (978~1003) 26 990, Bit9 (969~991) 23 980,
3564 11:10:27.021992 TX Bit2 (976~1001) 26 988, Bit10 (970~994) 25 982,
3565 11:10:27.025026 TX Bit3 (975~999) 25 987, Bit11 (970~994) 25 982,
3566 11:10:27.028143 TX Bit4 (977~1003) 27 990, Bit12 (971~994) 24 982,
3567 11:10:27.034652 TX Bit5 (978~1004) 27 991, Bit13 (971~995) 25 983,
3568 11:10:27.038491 TX Bit6 (977~1003) 27 990, Bit14 (970~994) 25 982,
3569 11:10:27.044557 TX Bit7 (978~1002) 25 990, Bit15 (966~990) 25 978,
3570 11:10:27.044732
3571 11:10:27.044847 Write Rank1 MR14 =0x22
3572 11:10:27.055722
3573 11:10:27.055856 CH=1, VrefRange= 0, VrefLevel = 34
3574 11:10:27.062548 TX Bit0 (978~1005) 28 991, Bit8 (968~992) 25 980,
3575 11:10:27.066014 TX Bit1 (978~1003) 26 990, Bit9 (969~991) 23 980,
3576 11:10:27.072884 TX Bit2 (976~1001) 26 988, Bit10 (970~994) 25 982,
3577 11:10:27.075985 TX Bit3 (975~999) 25 987, Bit11 (970~994) 25 982,
3578 11:10:27.079093 TX Bit4 (977~1003) 27 990, Bit12 (971~994) 24 982,
3579 11:10:27.085696 TX Bit5 (978~1004) 27 991, Bit13 (971~995) 25 983,
3580 11:10:27.088986 TX Bit6 (977~1003) 27 990, Bit14 (970~994) 25 982,
3581 11:10:27.095886 TX Bit7 (978~1002) 25 990, Bit15 (966~990) 25 978,
3582 11:10:27.096404
3583 11:10:27.096804 Write Rank1 MR14 =0x24
3584 11:10:27.106661
3585 11:10:27.107145 CH=1, VrefRange= 0, VrefLevel = 36
3586 11:10:27.113022 TX Bit0 (978~1005) 28 991, Bit8 (968~992) 25 980,
3587 11:10:27.116284 TX Bit1 (978~1003) 26 990, Bit9 (969~991) 23 980,
3588 11:10:27.122808 TX Bit2 (976~1001) 26 988, Bit10 (970~994) 25 982,
3589 11:10:27.126829 TX Bit3 (975~999) 25 987, Bit11 (970~994) 25 982,
3590 11:10:27.129313 TX Bit4 (977~1003) 27 990, Bit12 (971~994) 24 982,
3591 11:10:27.136385 TX Bit5 (978~1004) 27 991, Bit13 (971~995) 25 983,
3592 11:10:27.139418 TX Bit6 (977~1003) 27 990, Bit14 (970~994) 25 982,
3593 11:10:27.146013 TX Bit7 (978~1002) 25 990, Bit15 (966~990) 25 978,
3594 11:10:27.146462
3595 11:10:27.146759
3596 11:10:27.149643 TX Vref found, early break! 385< 387
3597 11:10:27.152696 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
3598 11:10:27.156250 u1DelayCellOfst[0]=5 cells (4 PI)
3599 11:10:27.159516 u1DelayCellOfst[1]=3 cells (3 PI)
3600 11:10:27.163218 u1DelayCellOfst[2]=1 cells (1 PI)
3601 11:10:27.165924 u1DelayCellOfst[3]=0 cells (0 PI)
3602 11:10:27.169604 u1DelayCellOfst[4]=3 cells (3 PI)
3603 11:10:27.172743 u1DelayCellOfst[5]=5 cells (4 PI)
3604 11:10:27.176068 u1DelayCellOfst[6]=3 cells (3 PI)
3605 11:10:27.176448 u1DelayCellOfst[7]=3 cells (3 PI)
3606 11:10:27.179648 Byte0, DQ PI dly=987, DQM PI dly= 989
3607 11:10:27.186340 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
3608 11:10:27.186800
3609 11:10:27.189498 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
3610 11:10:27.189958
3611 11:10:27.192905 u1DelayCellOfst[8]=2 cells (2 PI)
3612 11:10:27.196153 u1DelayCellOfst[9]=2 cells (2 PI)
3613 11:10:27.199432 u1DelayCellOfst[10]=5 cells (4 PI)
3614 11:10:27.202614 u1DelayCellOfst[11]=5 cells (4 PI)
3615 11:10:27.206110 u1DelayCellOfst[12]=5 cells (4 PI)
3616 11:10:27.209515 u1DelayCellOfst[13]=6 cells (5 PI)
3617 11:10:27.212745 u1DelayCellOfst[14]=5 cells (4 PI)
3618 11:10:27.215751 u1DelayCellOfst[15]=0 cells (0 PI)
3619 11:10:27.219267 Byte1, DQ PI dly=978, DQM PI dly= 980
3620 11:10:27.222180 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
3621 11:10:27.222656
3622 11:10:27.225689 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
3623 11:10:27.226191
3624 11:10:27.229232 Write Rank1 MR14 =0x1e
3625 11:10:27.229616
3626 11:10:27.232256 Final TX Range 0 Vref 30
3627 11:10:27.232735
3628 11:10:27.238829 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3629 11:10:27.238912
3630 11:10:27.245401 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3631 11:10:27.251955 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3632 11:10:27.258465 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3633 11:10:27.258547 Write Rank1 MR3 =0xb0
3634 11:10:27.261894 DramC Write-DBI on
3635 11:10:27.261978 ==
3636 11:10:27.268725 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3637 11:10:27.268809 fsp= 1, odt_onoff= 1, Byte mode= 0
3638 11:10:27.271871 ==
3639 11:10:27.275255 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3640 11:10:27.275354
3641 11:10:27.278268 Begin, DQ Scan Range 700~764
3642 11:10:27.278352
3643 11:10:27.278417
3644 11:10:27.278478 TX Vref Scan disable
3645 11:10:27.281782 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3646 11:10:27.288713 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3647 11:10:27.291927 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3648 11:10:27.295328 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3649 11:10:27.298576 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3650 11:10:27.301796 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3651 11:10:27.305331 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3652 11:10:27.308431 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3653 11:10:27.311942 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3654 11:10:27.315013 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3655 11:10:27.318281 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3656 11:10:27.321656 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3657 11:10:27.325086 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
3658 11:10:27.328687 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
3659 11:10:27.332062 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
3660 11:10:27.335196 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3661 11:10:27.338512 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3662 11:10:27.341714 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3663 11:10:27.345072 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3664 11:10:27.348342 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3665 11:10:27.351889 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3666 11:10:27.355063 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3667 11:10:27.364265 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
3668 11:10:27.367422 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
3669 11:10:27.370770 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
3670 11:10:27.374183 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
3671 11:10:27.377356 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
3672 11:10:27.381029 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3673 11:10:27.384410 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3674 11:10:27.387742 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3675 11:10:27.391286 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3676 11:10:27.394394 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3677 11:10:27.397660 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3678 11:10:27.401065 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3679 11:10:27.404009 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3680 11:10:27.407315 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3681 11:10:27.410472 751 |2 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
3682 11:10:27.414003 Byte0, DQ PI dly=736, DQM PI dly= 736
3683 11:10:27.420650 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 32)
3684 11:10:27.420917
3685 11:10:27.424064 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 32)
3686 11:10:27.424391
3687 11:10:27.427605 Byte1, DQ PI dly=724, DQM PI dly= 724
3688 11:10:27.430747 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 20)
3689 11:10:27.434568
3690 11:10:27.437582 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 20)
3691 11:10:27.437969
3692 11:10:27.444537 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3693 11:10:27.451064 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3694 11:10:27.457534 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3695 11:10:27.460931 Write Rank1 MR3 =0x30
3696 11:10:27.461377 DramC Write-DBI off
3697 11:10:27.461679
3698 11:10:27.461955 [DATLAT]
3699 11:10:27.464430 Freq=1600, CH1 RK1, use_rxtx_scan=0
3700 11:10:27.464922
3701 11:10:27.467720 DATLAT Default: 0x10
3702 11:10:27.471218 7, 0xFFFF, sum=0
3703 11:10:27.471619 8, 0xFFFF, sum=0
3704 11:10:27.471925 9, 0xFFFF, sum=0
3705 11:10:27.474516 10, 0xFFFF, sum=0
3706 11:10:27.474959 11, 0xFFFF, sum=0
3707 11:10:27.477380 12, 0xFFFF, sum=0
3708 11:10:27.477806 13, 0xFFFF, sum=0
3709 11:10:27.480818 14, 0x0, sum=1
3710 11:10:27.481206 15, 0x0, sum=2
3711 11:10:27.484142 16, 0x0, sum=3
3712 11:10:27.484583 17, 0x0, sum=4
3713 11:10:27.487885 pattern=2 first_step=14 total pass=5 best_step=16
3714 11:10:27.490487 ==
3715 11:10:27.493905 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3716 11:10:27.497796 fsp= 1, odt_onoff= 1, Byte mode= 0
3717 11:10:27.498309 ==
3718 11:10:27.500959 Start DQ dly to find pass range UseTestEngine =1
3719 11:10:27.504274 x-axis: bit #, y-axis: DQ dly (-127~63)
3720 11:10:27.507740 RX Vref Scan = 0
3721 11:10:27.510896 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3722 11:10:27.514191 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3723 11:10:27.514778 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3724 11:10:27.517460 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3725 11:10:27.520727 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3726 11:10:27.524053 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3727 11:10:27.526990 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3728 11:10:27.530466 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3729 11:10:27.533910 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3730 11:10:27.537229 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3731 11:10:27.540259 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3732 11:10:27.540749 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3733 11:10:27.543956 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3734 11:10:27.547248 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3735 11:10:27.550610 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3736 11:10:27.554117 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3737 11:10:27.557230 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3738 11:10:27.560654 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3739 11:10:27.563908 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3740 11:10:27.564520 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3741 11:10:27.567103 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3742 11:10:27.570500 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3743 11:10:27.573538 -4, [0] xxxxxxxx xxxxxxxo [MSB]
3744 11:10:27.576982 -3, [0] xxxxxxxx xxxxxxxo [MSB]
3745 11:10:27.580428 -2, [0] xxxoxxxx xxxxxxxo [MSB]
3746 11:10:27.583802 -1, [0] xxxoxxxx xoxxxxxo [MSB]
3747 11:10:27.584237 0, [0] xxooxxxx ooxxxxxo [MSB]
3748 11:10:27.587205 1, [0] xxooxxxx ooxxxxxo [MSB]
3749 11:10:27.590475 2, [0] xxooxxxx ooxxxxxo [MSB]
3750 11:10:27.594027 3, [0] oxooxxxo ooxxxxxo [MSB]
3751 11:10:27.597129 4, [0] oooooxxo ooooooxo [MSB]
3752 11:10:27.600524 32, [0] oooooooo ooooooox [MSB]
3753 11:10:27.604133 33, [0] oooooooo ooooooox [MSB]
3754 11:10:27.607234 34, [0] oooooooo ooooooox [MSB]
3755 11:10:27.610254 35, [0] oooxoooo oxooooox [MSB]
3756 11:10:27.613753 36, [0] oooxoooo xxooooox [MSB]
3757 11:10:27.614159 37, [0] ooxxoooo xxooooox [MSB]
3758 11:10:27.616993 38, [0] ooxxoooo xxooooox [MSB]
3759 11:10:27.620196 39, [0] ooxxooox xxxoooox [MSB]
3760 11:10:27.623939 40, [0] oxxxxoox xxxoooox [MSB]
3761 11:10:27.627241 41, [0] xxxxxxox xxxxxxxx [MSB]
3762 11:10:27.630558 42, [0] xxxxxxxx xxxxxxxx [MSB]
3763 11:10:27.633744 iDelay=42, Bit 0, Center 21 (3 ~ 40) 38
3764 11:10:27.636972 iDelay=42, Bit 1, Center 21 (4 ~ 39) 36
3765 11:10:27.640262 iDelay=42, Bit 2, Center 18 (0 ~ 36) 37
3766 11:10:27.643414 iDelay=42, Bit 3, Center 16 (-2 ~ 34) 37
3767 11:10:27.646810 iDelay=42, Bit 4, Center 21 (4 ~ 39) 36
3768 11:10:27.650461 iDelay=42, Bit 5, Center 22 (5 ~ 40) 36
3769 11:10:27.653539 iDelay=42, Bit 6, Center 23 (5 ~ 41) 37
3770 11:10:27.657487 iDelay=42, Bit 7, Center 20 (3 ~ 38) 36
3771 11:10:27.660208 iDelay=42, Bit 8, Center 17 (0 ~ 35) 36
3772 11:10:27.664073 iDelay=42, Bit 9, Center 16 (-1 ~ 34) 36
3773 11:10:27.667445 iDelay=42, Bit 10, Center 21 (4 ~ 38) 35
3774 11:10:27.674276 iDelay=42, Bit 11, Center 22 (4 ~ 40) 37
3775 11:10:27.676907 iDelay=42, Bit 12, Center 22 (4 ~ 40) 37
3776 11:10:27.680588 iDelay=42, Bit 13, Center 22 (4 ~ 40) 37
3777 11:10:27.683425 iDelay=42, Bit 14, Center 22 (5 ~ 40) 36
3778 11:10:27.687262 iDelay=42, Bit 15, Center 13 (-4 ~ 31) 36
3779 11:10:27.687725 ==
3780 11:10:27.693615 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3781 11:10:27.694074 fsp= 1, odt_onoff= 1, Byte mode= 0
3782 11:10:27.696805 ==
3783 11:10:27.697193 DQS Delay:
3784 11:10:27.697497 DQS0 = 0, DQS1 = 0
3785 11:10:27.699997 DQM Delay:
3786 11:10:27.700383 DQM0 = 20, DQM1 = 19
3787 11:10:27.703575 DQ Delay:
3788 11:10:27.706795 DQ0 =21, DQ1 =21, DQ2 =18, DQ3 =16
3789 11:10:27.707186 DQ4 =21, DQ5 =22, DQ6 =23, DQ7 =20
3790 11:10:27.710148 DQ8 =17, DQ9 =16, DQ10 =21, DQ11 =22
3791 11:10:27.716620 DQ12 =22, DQ13 =22, DQ14 =22, DQ15 =13
3792 11:10:27.717129
3793 11:10:27.717438
3794 11:10:27.717709
3795 11:10:27.719993 [DramC_TX_OE_Calibration] TA2
3796 11:10:27.720377 Original DQ_B0 (3 6) =30, OEN = 27
3797 11:10:27.723196 Original DQ_B1 (3 6) =30, OEN = 27
3798 11:10:27.726874 23, 0x0, End_B0=23 End_B1=23
3799 11:10:27.729869 24, 0x0, End_B0=24 End_B1=24
3800 11:10:27.733134 25, 0x0, End_B0=25 End_B1=25
3801 11:10:27.733574 26, 0x0, End_B0=26 End_B1=26
3802 11:10:27.736856 27, 0x0, End_B0=27 End_B1=27
3803 11:10:27.740258 28, 0x0, End_B0=28 End_B1=28
3804 11:10:27.743689 29, 0x0, End_B0=29 End_B1=29
3805 11:10:27.746940 30, 0x0, End_B0=30 End_B1=30
3806 11:10:27.747405 31, 0xFFFF, End_B0=30 End_B1=30
3807 11:10:27.753310 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3808 11:10:27.760235 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3809 11:10:27.760767
3810 11:10:27.761067
3811 11:10:27.761337 Write Rank1 MR23 =0x3f
3812 11:10:27.763590 [DQSOSC]
3813 11:10:27.770281 [DQSOSCAuto] RK1, (LSB)MR18= 0xcece, (MSB)MR19= 0x202, tDQSOscB0 = 438 ps tDQSOscB1 = 438 ps
3814 11:10:27.776841 CH1_RK1: MR19=0x202, MR18=0xCECE, DQSOSC=438, MR23=63, INC=12, DEC=19
3815 11:10:27.780440 Write Rank1 MR23 =0x3f
3816 11:10:27.780961 [DQSOSC]
3817 11:10:27.786964 [DQSOSCAuto] RK1, (LSB)MR18= 0xcdcd, (MSB)MR19= 0x202, tDQSOscB0 = 439 ps tDQSOscB1 = 439 ps
3818 11:10:27.790532 CH1 RK1: MR19=202, MR18=CDCD
3819 11:10:27.793539 [RxdqsGatingPostProcess] freq 1600
3820 11:10:27.800154 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3821 11:10:27.800665 Rank: 0
3822 11:10:27.802901 best DQS0 dly(2T, 0.5T) = (2, 6)
3823 11:10:27.806400 best DQS1 dly(2T, 0.5T) = (2, 6)
3824 11:10:27.809816 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3825 11:10:27.813081 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3826 11:10:27.813473 Rank: 1
3827 11:10:27.816254 best DQS0 dly(2T, 0.5T) = (2, 5)
3828 11:10:27.819742 best DQS1 dly(2T, 0.5T) = (2, 6)
3829 11:10:27.822729 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3830 11:10:27.826471 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3831 11:10:27.830131 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3832 11:10:27.833110 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3833 11:10:27.836079 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3834 11:10:27.839728
3835 11:10:27.840188
3836 11:10:27.843056 [Calibration Summary] Freqency 1600
3837 11:10:27.843512 CH 0, Rank 0
3838 11:10:27.843810 All Pass.
3839 11:10:27.844084
3840 11:10:27.846082 CH 0, Rank 1
3841 11:10:27.846462 All Pass.
3842 11:10:27.846756
3843 11:10:27.847026 CH 1, Rank 0
3844 11:10:27.849376 All Pass.
3845 11:10:27.849756
3846 11:10:27.850049 CH 1, Rank 1
3847 11:10:27.850321 All Pass.
3848 11:10:27.850580
3849 11:10:27.856184 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3850 11:10:27.863265 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3851 11:10:27.869516 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3852 11:10:27.873168 Write Rank0 MR3 =0xb0
3853 11:10:27.879982 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3854 11:10:27.886362 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3855 11:10:27.893156 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3856 11:10:27.896434 Write Rank1 MR3 =0xb0
3857 11:10:27.902956 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3858 11:10:27.909731 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3859 11:10:27.916134 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3860 11:10:27.919648 Write Rank0 MR3 =0xb0
3861 11:10:27.926240 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3862 11:10:27.932418 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3863 11:10:27.939704 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3864 11:10:27.940178 Write Rank1 MR3 =0xb0
3865 11:10:27.943167 DramC Write-DBI on
3866 11:10:27.945827 [GetDramInforAfterCalByMRR] Vendor 6.
3867 11:10:27.949129 [GetDramInforAfterCalByMRR] Revision 505.
3868 11:10:27.949592 MR8 1111
3869 11:10:27.956259 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3870 11:10:27.956776 MR8 1111
3871 11:10:27.959623 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3872 11:10:27.962720 MR8 1111
3873 11:10:27.965979 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3874 11:10:27.966361 MR8 1111
3875 11:10:27.972853 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3876 11:10:27.982716 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3877 11:10:27.983252 Write Rank0 MR13 =0xd0
3878 11:10:27.985355 Write Rank1 MR13 =0xd0
3879 11:10:27.989415 Write Rank0 MR13 =0xd0
3880 11:10:27.989876 Write Rank1 MR13 =0xd0
3881 11:10:27.992228 Save calibration result to emmc
3882 11:10:27.992816
3883 11:10:27.993122
3884 11:10:27.996012 [DramcModeReg_Check] Freq_1600, FSP_1
3885 11:10:27.998959 FSP_1, CH_0, RK0
3886 11:10:27.999485 Write Rank0 MR13 =0xd8
3887 11:10:28.002165 MR12 = 0x5e (global = 0x5e) match
3888 11:10:28.005482 MR14 = 0x1c (global = 0x1c) match
3889 11:10:28.009309 FSP_1, CH_0, RK1
3890 11:10:28.009769 Write Rank1 MR13 =0xd8
3891 11:10:28.012758 MR12 = 0x60 (global = 0x60) match
3892 11:10:28.016121 MR14 = 0x20 (global = 0x20) match
3893 11:10:28.019050 FSP_1, CH_1, RK0
3894 11:10:28.019434 Write Rank0 MR13 =0xd8
3895 11:10:28.022372 MR12 = 0x5e (global = 0x5e) match
3896 11:10:28.025719 MR14 = 0x1c (global = 0x1c) match
3897 11:10:28.029444 FSP_1, CH_1, RK1
3898 11:10:28.029960 Write Rank1 MR13 =0xd8
3899 11:10:28.032204 MR12 = 0x5e (global = 0x5e) match
3900 11:10:28.035422 MR14 = 0x1e (global = 0x1e) match
3901 11:10:28.035802
3902 11:10:28.038669 [MEM_TEST] 02: After DFS, before run time config
3903 11:10:28.051095 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3904 11:10:28.051481
3905 11:10:28.051780 [TA2_TEST]
3906 11:10:28.052059 === TA2 HW
3907 11:10:28.054906 TA2 PAT: XTALK
3908 11:10:28.057696 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3909 11:10:28.064388 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3910 11:10:28.067742 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3911 11:10:28.074630 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3912 11:10:28.075088
3913 11:10:28.075383
3914 11:10:28.075650 Settings after calibration
3915 11:10:28.075913
3916 11:10:28.077909 [DramcRunTimeConfig]
3917 11:10:28.081247 TransferPLLToSPMControl - MODE SW PHYPLL
3918 11:10:28.081713 TX_TRACKING: ON
3919 11:10:28.084609 RX_TRACKING: ON
3920 11:10:28.085067 HW_GATING: ON
3921 11:10:28.088124 HW_GATING DBG: OFF
3922 11:10:28.088636 ddr_geometry:1
3923 11:10:28.090881 ddr_geometry:1
3924 11:10:28.091331 ddr_geometry:1
3925 11:10:28.094665 ddr_geometry:1
3926 11:10:28.095131 ddr_geometry:1
3927 11:10:28.095431 ddr_geometry:1
3928 11:10:28.097602 ddr_geometry:1
3929 11:10:28.098010 ddr_geometry:1
3930 11:10:28.100833 High Freq DUMMY_READ_FOR_TRACKING: ON
3931 11:10:28.104273 ZQCS_ENABLE_LP4: OFF
3932 11:10:28.107773 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
3933 11:10:28.110734 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
3934 11:10:28.111118 SPM_CONTROL_AFTERK: ON
3935 11:10:28.114045 IMPEDANCE_TRACKING: ON
3936 11:10:28.114422 TEMP_SENSOR: ON
3937 11:10:28.117693 PER_BANK_REFRESH: ON
3938 11:10:28.118086 HW_SAVE_FOR_SR: ON
3939 11:10:28.121202 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3940 11:10:28.124241 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
3941 11:10:28.127859 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
3942 11:10:28.130879 Read ODT Tracking: ON
3943 11:10:28.134194 =========================
3944 11:10:28.134823
3945 11:10:28.135155 [TA2_TEST]
3946 11:10:28.135614 === TA2 HW
3947 11:10:28.141286 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
3948 11:10:28.144430 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
3949 11:10:28.150747 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
3950 11:10:28.154750 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
3951 11:10:28.155213
3952 11:10:28.157188 [MEM_TEST] 03: After run time config
3953 11:10:28.168853 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3954 11:10:28.172164 [complex_mem_test] start addr:0x40024000, len:131072
3955 11:10:28.376370 1st complex R/W mem test pass
3956 11:10:28.382996 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
3957 11:10:28.386546 sync preloader write leveling
3958 11:10:28.389875 sync preloader cbt_mr12
3959 11:10:28.393099 sync preloader cbt_clk_dly
3960 11:10:28.393294 sync preloader cbt_cmd_dly
3961 11:10:28.396281 sync preloader cbt_cs
3962 11:10:28.399523 sync preloader cbt_ca_perbit_delay
3963 11:10:28.399757 sync preloader clk_delay
3964 11:10:28.402919 sync preloader dqs_delay
3965 11:10:28.406610 sync preloader u1Gating2T_Save
3966 11:10:28.409519 sync preloader u1Gating05T_Save
3967 11:10:28.412779 sync preloader u1Gatingfine_tune_Save
3968 11:10:28.416389 sync preloader u1Gatingucpass_count_Save
3969 11:10:28.419422 sync preloader u1TxWindowPerbitVref_Save
3970 11:10:28.423245 sync preloader u1TxCenter_min_Save
3971 11:10:28.426342 sync preloader u1TxCenter_max_Save
3972 11:10:28.429761 sync preloader u1Txwin_center_Save
3973 11:10:28.433009 sync preloader u1Txfirst_pass_Save
3974 11:10:28.436205 sync preloader u1Txlast_pass_Save
3975 11:10:28.440025 sync preloader u1RxDatlat_Save
3976 11:10:28.443092 sync preloader u1RxWinPerbitVref_Save
3977 11:10:28.446127 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3978 11:10:28.449653 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3979 11:10:28.453065 sync preloader delay_cell_unit
3980 11:10:28.459910 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
3981 11:10:28.462894 sync preloader write leveling
3982 11:10:28.463357 sync preloader cbt_mr12
3983 11:10:28.466729 sync preloader cbt_clk_dly
3984 11:10:28.469962 sync preloader cbt_cmd_dly
3985 11:10:28.470423 sync preloader cbt_cs
3986 11:10:28.472812 sync preloader cbt_ca_perbit_delay
3987 11:10:28.476751 sync preloader clk_delay
3988 11:10:28.480020 sync preloader dqs_delay
3989 11:10:28.480512 sync preloader u1Gating2T_Save
3990 11:10:28.483368 sync preloader u1Gating05T_Save
3991 11:10:28.486651 sync preloader u1Gatingfine_tune_Save
3992 11:10:28.490058 sync preloader u1Gatingucpass_count_Save
3993 11:10:28.496614 sync preloader u1TxWindowPerbitVref_Save
3994 11:10:28.497118 sync preloader u1TxCenter_min_Save
3995 11:10:28.499951 sync preloader u1TxCenter_max_Save
3996 11:10:28.502972 sync preloader u1Txwin_center_Save
3997 11:10:28.506200 sync preloader u1Txfirst_pass_Save
3998 11:10:28.509814 sync preloader u1Txlast_pass_Save
3999 11:10:28.512874 sync preloader u1RxDatlat_Save
4000 11:10:28.516434 sync preloader u1RxWinPerbitVref_Save
4001 11:10:28.519606 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4002 11:10:28.523069 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4003 11:10:28.526267 sync preloader delay_cell_unit
4004 11:10:28.532828 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
4005 11:10:28.535951 sync preloader write leveling
4006 11:10:28.539537 sync preloader cbt_mr12
4007 11:10:28.540024 sync preloader cbt_clk_dly
4008 11:10:28.542974 sync preloader cbt_cmd_dly
4009 11:10:28.546285 sync preloader cbt_cs
4010 11:10:28.549496 sync preloader cbt_ca_perbit_delay
4011 11:10:28.549882 sync preloader clk_delay
4012 11:10:28.552782 sync preloader dqs_delay
4013 11:10:28.555992 sync preloader u1Gating2T_Save
4014 11:10:28.559509 sync preloader u1Gating05T_Save
4015 11:10:28.562857 sync preloader u1Gatingfine_tune_Save
4016 11:10:28.566316 sync preloader u1Gatingucpass_count_Save
4017 11:10:28.569561 sync preloader u1TxWindowPerbitVref_Save
4018 11:10:28.572654 sync preloader u1TxCenter_min_Save
4019 11:10:28.576195 sync preloader u1TxCenter_max_Save
4020 11:10:28.579421 sync preloader u1Txwin_center_Save
4021 11:10:28.582854 sync preloader u1Txfirst_pass_Save
4022 11:10:28.586084 sync preloader u1Txlast_pass_Save
4023 11:10:28.586711 sync preloader u1RxDatlat_Save
4024 11:10:28.589495 sync preloader u1RxWinPerbitVref_Save
4025 11:10:28.596116 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4026 11:10:28.599287 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4027 11:10:28.602852 sync preloader delay_cell_unit
4028 11:10:28.606156 just_for_test_dump_coreboot_params dump all params
4029 11:10:28.609357 dump source = 0x0
4030 11:10:28.609832 dump params frequency:1600
4031 11:10:28.612842 dump params rank number:2
4032 11:10:28.613221
4033 11:10:28.616047 dump params write leveling
4034 11:10:28.619735 write leveling[0][0][0] = 0x20
4035 11:10:28.620197 write leveling[0][0][1] = 0x18
4036 11:10:28.622978 write leveling[0][1][0] = 0x1a
4037 11:10:28.626004 write leveling[0][1][1] = 0x18
4038 11:10:28.629386 write leveling[1][0][0] = 0x21
4039 11:10:28.632629 write leveling[1][0][1] = 0x18
4040 11:10:28.635690 write leveling[1][1][0] = 0x22
4041 11:10:28.636078 write leveling[1][1][1] = 0x19
4042 11:10:28.639155 dump params cbt_cs
4043 11:10:28.642526 cbt_cs[0][0] = 0x8
4044 11:10:28.642985 cbt_cs[0][1] = 0x8
4045 11:10:28.645569 cbt_cs[1][0] = 0xb
4046 11:10:28.645957 cbt_cs[1][1] = 0xb
4047 11:10:28.649160 dump params cbt_mr12
4048 11:10:28.649543 cbt_mr12[0][0] = 0x1e
4049 11:10:28.652213 cbt_mr12[0][1] = 0x20
4050 11:10:28.652621 cbt_mr12[1][0] = 0x1e
4051 11:10:28.655522 cbt_mr12[1][1] = 0x1e
4052 11:10:28.658873 dump params tx window
4053 11:10:28.659255 tx_center_min[0][0][0] = 981
4054 11:10:28.662768 tx_center_max[0][0][0] = 988
4055 11:10:28.666167 tx_center_min[0][0][1] = 975
4056 11:10:28.669353 tx_center_max[0][0][1] = 981
4057 11:10:28.672242 tx_center_min[0][1][0] = 979
4058 11:10:28.672667 tx_center_max[0][1][0] = 986
4059 11:10:28.676067 tx_center_min[0][1][1] = 978
4060 11:10:28.679260 tx_center_max[0][1][1] = 984
4061 11:10:28.682751 tx_center_min[1][0][0] = 988
4062 11:10:28.683212 tx_center_max[1][0][0] = 992
4063 11:10:28.685894 tx_center_min[1][0][1] = 977
4064 11:10:28.688872 tx_center_max[1][0][1] = 983
4065 11:10:28.692126 tx_center_min[1][1][0] = 987
4066 11:10:28.695866 tx_center_max[1][1][0] = 991
4067 11:10:28.696256 tx_center_min[1][1][1] = 978
4068 11:10:28.699275 tx_center_max[1][1][1] = 983
4069 11:10:28.702964 dump params tx window
4070 11:10:28.705939 tx_win_center[0][0][0] = 988
4071 11:10:28.706338 tx_first_pass[0][0][0] = 976
4072 11:10:28.709402 tx_last_pass[0][0][0] = 1000
4073 11:10:28.712626 tx_win_center[0][0][1] = 987
4074 11:10:28.715940 tx_first_pass[0][0][1] = 975
4075 11:10:28.716323 tx_last_pass[0][0][1] = 999
4076 11:10:28.719232 tx_win_center[0][0][2] = 987
4077 11:10:28.722591 tx_first_pass[0][0][2] = 976
4078 11:10:28.725972 tx_last_pass[0][0][2] = 999
4079 11:10:28.729372 tx_win_center[0][0][3] = 981
4080 11:10:28.729754 tx_first_pass[0][0][3] = 969
4081 11:10:28.732886 tx_last_pass[0][0][3] = 993
4082 11:10:28.736029 tx_win_center[0][0][4] = 987
4083 11:10:28.739678 tx_first_pass[0][0][4] = 975
4084 11:10:28.740141 tx_last_pass[0][0][4] = 999
4085 11:10:28.742643 tx_win_center[0][0][5] = 983
4086 11:10:28.745913 tx_first_pass[0][0][5] = 970
4087 11:10:28.748857 tx_last_pass[0][0][5] = 996
4088 11:10:28.752727 tx_win_center[0][0][6] = 985
4089 11:10:28.753107 tx_first_pass[0][0][6] = 973
4090 11:10:28.755574 tx_last_pass[0][0][6] = 997
4091 11:10:28.758974 tx_win_center[0][0][7] = 987
4092 11:10:28.762353 tx_first_pass[0][0][7] = 975
4093 11:10:28.765754 tx_last_pass[0][0][7] = 999
4094 11:10:28.766208 tx_win_center[0][0][8] = 975
4095 11:10:28.768756 tx_first_pass[0][0][8] = 964
4096 11:10:28.772090 tx_last_pass[0][0][8] = 987
4097 11:10:28.775892 tx_win_center[0][0][9] = 978
4098 11:10:28.776363 tx_first_pass[0][0][9] = 967
4099 11:10:28.779061 tx_last_pass[0][0][9] = 990
4100 11:10:28.782492 tx_win_center[0][0][10] = 981
4101 11:10:28.786032 tx_first_pass[0][0][10] = 969
4102 11:10:28.788776 tx_last_pass[0][0][10] = 993
4103 11:10:28.789156 tx_win_center[0][0][11] = 977
4104 11:10:28.792343 tx_first_pass[0][0][11] = 965
4105 11:10:28.795298 tx_last_pass[0][0][11] = 989
4106 11:10:28.798726 tx_win_center[0][0][12] = 978
4107 11:10:28.802528 tx_first_pass[0][0][12] = 967
4108 11:10:28.802987 tx_last_pass[0][0][12] = 990
4109 11:10:28.805454 tx_win_center[0][0][13] = 978
4110 11:10:28.808894 tx_first_pass[0][0][13] = 967
4111 11:10:28.812536 tx_last_pass[0][0][13] = 990
4112 11:10:28.815714 tx_win_center[0][0][14] = 979
4113 11:10:28.816125 tx_first_pass[0][0][14] = 967
4114 11:10:28.819374 tx_last_pass[0][0][14] = 991
4115 11:10:28.822182 tx_win_center[0][0][15] = 981
4116 11:10:28.825940 tx_first_pass[0][0][15] = 969
4117 11:10:28.829022 tx_last_pass[0][0][15] = 993
4118 11:10:28.829405 tx_win_center[0][1][0] = 986
4119 11:10:28.832592 tx_first_pass[0][1][0] = 974
4120 11:10:28.835927 tx_last_pass[0][1][0] = 998
4121 11:10:28.838896 tx_win_center[0][1][1] = 984
4122 11:10:28.839283 tx_first_pass[0][1][1] = 972
4123 11:10:28.842756 tx_last_pass[0][1][1] = 996
4124 11:10:28.845930 tx_win_center[0][1][2] = 986
4125 11:10:28.849013 tx_first_pass[0][1][2] = 974
4126 11:10:28.852438 tx_last_pass[0][1][2] = 998
4127 11:10:28.852846 tx_win_center[0][1][3] = 979
4128 11:10:28.856098 tx_first_pass[0][1][3] = 968
4129 11:10:28.859133 tx_last_pass[0][1][3] = 991
4130 11:10:28.862703 tx_win_center[0][1][4] = 983
4131 11:10:28.863172 tx_first_pass[0][1][4] = 970
4132 11:10:28.865838 tx_last_pass[0][1][4] = 997
4133 11:10:28.869419 tx_win_center[0][1][5] = 980
4134 11:10:28.872346 tx_first_pass[0][1][5] = 968
4135 11:10:28.875685 tx_last_pass[0][1][5] = 993
4136 11:10:28.876068 tx_win_center[0][1][6] = 982
4137 11:10:28.878837 tx_first_pass[0][1][6] = 969
4138 11:10:28.882101 tx_last_pass[0][1][6] = 995
4139 11:10:28.885244 tx_win_center[0][1][7] = 984
4140 11:10:28.885626 tx_first_pass[0][1][7] = 971
4141 11:10:28.888951 tx_last_pass[0][1][7] = 997
4142 11:10:28.892529 tx_win_center[0][1][8] = 978
4143 11:10:28.895403 tx_first_pass[0][1][8] = 967
4144 11:10:28.898698 tx_last_pass[0][1][8] = 990
4145 11:10:28.899081 tx_win_center[0][1][9] = 979
4146 11:10:28.901942 tx_first_pass[0][1][9] = 968
4147 11:10:28.905844 tx_last_pass[0][1][9] = 990
4148 11:10:28.909405 tx_win_center[0][1][10] = 984
4149 11:10:28.909901 tx_first_pass[0][1][10] = 972
4150 11:10:28.912270 tx_last_pass[0][1][10] = 997
4151 11:10:28.915317 tx_win_center[0][1][11] = 978
4152 11:10:28.918782 tx_first_pass[0][1][11] = 966
4153 11:10:28.922417 tx_last_pass[0][1][11] = 990
4154 11:10:28.922818 tx_win_center[0][1][12] = 980
4155 11:10:28.925364 tx_first_pass[0][1][12] = 968
4156 11:10:28.928565 tx_last_pass[0][1][12] = 992
4157 11:10:28.932122 tx_win_center[0][1][13] = 979
4158 11:10:28.935553 tx_first_pass[0][1][13] = 968
4159 11:10:28.938697 tx_last_pass[0][1][13] = 991
4160 11:10:28.939205 tx_win_center[0][1][14] = 980
4161 11:10:28.942130 tx_first_pass[0][1][14] = 968
4162 11:10:28.945918 tx_last_pass[0][1][14] = 992
4163 11:10:28.948954 tx_win_center[0][1][15] = 983
4164 11:10:28.952396 tx_first_pass[0][1][15] = 971
4165 11:10:28.952906 tx_last_pass[0][1][15] = 995
4166 11:10:28.955846 tx_win_center[1][0][0] = 992
4167 11:10:28.958717 tx_first_pass[1][0][0] = 979
4168 11:10:28.962249 tx_last_pass[1][0][0] = 1006
4169 11:10:28.962724 tx_win_center[1][0][1] = 990
4170 11:10:28.965472 tx_first_pass[1][0][1] = 978
4171 11:10:28.968618 tx_last_pass[1][0][1] = 1003
4172 11:10:28.971987 tx_win_center[1][0][2] = 989
4173 11:10:28.975347 tx_first_pass[1][0][2] = 977
4174 11:10:28.975733 tx_last_pass[1][0][2] = 1002
4175 11:10:28.979209 tx_win_center[1][0][3] = 988
4176 11:10:28.982563 tx_first_pass[1][0][3] = 976
4177 11:10:28.985842 tx_last_pass[1][0][3] = 1000
4178 11:10:28.986313 tx_win_center[1][0][4] = 991
4179 11:10:28.988851 tx_first_pass[1][0][4] = 978
4180 11:10:28.992656 tx_last_pass[1][0][4] = 1004
4181 11:10:28.995818 tx_win_center[1][0][5] = 992
4182 11:10:28.999001 tx_first_pass[1][0][5] = 980
4183 11:10:28.999477 tx_last_pass[1][0][5] = 1005
4184 11:10:29.002137 tx_win_center[1][0][6] = 990
4185 11:10:29.005205 tx_first_pass[1][0][6] = 978
4186 11:10:29.008957 tx_last_pass[1][0][6] = 1003
4187 11:10:29.011902 tx_win_center[1][0][7] = 990
4188 11:10:29.012282 tx_first_pass[1][0][7] = 978
4189 11:10:29.015174 tx_last_pass[1][0][7] = 1003
4190 11:10:29.018582 tx_win_center[1][0][8] = 979
4191 11:10:29.022253 tx_first_pass[1][0][8] = 968
4192 11:10:29.025469 tx_last_pass[1][0][8] = 991
4193 11:10:29.025879 tx_win_center[1][0][9] = 980
4194 11:10:29.028627 tx_first_pass[1][0][9] = 969
4195 11:10:29.032031 tx_last_pass[1][0][9] = 991
4196 11:10:29.035154 tx_win_center[1][0][10] = 981
4197 11:10:29.038592 tx_first_pass[1][0][10] = 970
4198 11:10:29.038986 tx_last_pass[1][0][10] = 993
4199 11:10:29.041581 tx_win_center[1][0][11] = 982
4200 11:10:29.044933 tx_first_pass[1][0][11] = 970
4201 11:10:29.048526 tx_last_pass[1][0][11] = 994
4202 11:10:29.051446 tx_win_center[1][0][12] = 982
4203 11:10:29.051965 tx_first_pass[1][0][12] = 970
4204 11:10:29.054837 tx_last_pass[1][0][12] = 994
4205 11:10:29.058256 tx_win_center[1][0][13] = 983
4206 11:10:29.061561 tx_first_pass[1][0][13] = 972
4207 11:10:29.065035 tx_last_pass[1][0][13] = 994
4208 11:10:29.065416 tx_win_center[1][0][14] = 981
4209 11:10:29.067932 tx_first_pass[1][0][14] = 970
4210 11:10:29.071584 tx_last_pass[1][0][14] = 993
4211 11:10:29.074886 tx_win_center[1][0][15] = 977
4212 11:10:29.078281 tx_first_pass[1][0][15] = 966
4213 11:10:29.078668 tx_last_pass[1][0][15] = 988
4214 11:10:29.081336 tx_win_center[1][1][0] = 991
4215 11:10:29.084721 tx_first_pass[1][1][0] = 978
4216 11:10:29.088052 tx_last_pass[1][1][0] = 1005
4217 11:10:29.091238 tx_win_center[1][1][1] = 990
4218 11:10:29.091802 tx_first_pass[1][1][1] = 978
4219 11:10:29.094474 tx_last_pass[1][1][1] = 1003
4220 11:10:29.098011 tx_win_center[1][1][2] = 988
4221 11:10:29.101469 tx_first_pass[1][1][2] = 976
4222 11:10:29.104625 tx_last_pass[1][1][2] = 1001
4223 11:10:29.105015 tx_win_center[1][1][3] = 987
4224 11:10:29.107939 tx_first_pass[1][1][3] = 975
4225 11:10:29.111337 tx_last_pass[1][1][3] = 999
4226 11:10:29.114273 tx_win_center[1][1][4] = 990
4227 11:10:29.114657 tx_first_pass[1][1][4] = 977
4228 11:10:29.118183 tx_last_pass[1][1][4] = 1003
4229 11:10:29.121195 tx_win_center[1][1][5] = 991
4230 11:10:29.124572 tx_first_pass[1][1][5] = 978
4231 11:10:29.127573 tx_last_pass[1][1][5] = 1004
4232 11:10:29.128060 tx_win_center[1][1][6] = 990
4233 11:10:29.131167 tx_first_pass[1][1][6] = 977
4234 11:10:29.134116 tx_last_pass[1][1][6] = 1003
4235 11:10:29.137648 tx_win_center[1][1][7] = 990
4236 11:10:29.141054 tx_first_pass[1][1][7] = 978
4237 11:10:29.141445 tx_last_pass[1][1][7] = 1002
4238 11:10:29.144199 tx_win_center[1][1][8] = 980
4239 11:10:29.147897 tx_first_pass[1][1][8] = 968
4240 11:10:29.151311 tx_last_pass[1][1][8] = 992
4241 11:10:29.151697 tx_win_center[1][1][9] = 980
4242 11:10:29.154732 tx_first_pass[1][1][9] = 969
4243 11:10:29.157497 tx_last_pass[1][1][9] = 991
4244 11:10:29.161187 tx_win_center[1][1][10] = 982
4245 11:10:29.164486 tx_first_pass[1][1][10] = 970
4246 11:10:29.164881 tx_last_pass[1][1][10] = 994
4247 11:10:29.167837 tx_win_center[1][1][11] = 982
4248 11:10:29.170885 tx_first_pass[1][1][11] = 970
4249 11:10:29.174262 tx_last_pass[1][1][11] = 994
4250 11:10:29.178148 tx_win_center[1][1][12] = 982
4251 11:10:29.178676 tx_first_pass[1][1][12] = 971
4252 11:10:29.181086 tx_last_pass[1][1][12] = 994
4253 11:10:29.184482 tx_win_center[1][1][13] = 983
4254 11:10:29.187403 tx_first_pass[1][1][13] = 971
4255 11:10:29.190631 tx_last_pass[1][1][13] = 995
4256 11:10:29.191022 tx_win_center[1][1][14] = 982
4257 11:10:29.194838 tx_first_pass[1][1][14] = 970
4258 11:10:29.197343 tx_last_pass[1][1][14] = 994
4259 11:10:29.201092 tx_win_center[1][1][15] = 978
4260 11:10:29.204056 tx_first_pass[1][1][15] = 966
4261 11:10:29.204495 tx_last_pass[1][1][15] = 990
4262 11:10:29.207466 dump params rx window
4263 11:10:29.211043 rx_firspass[0][0][0] = 5
4264 11:10:29.211508 rx_lastpass[0][0][0] = 38
4265 11:10:29.214134 rx_firspass[0][0][1] = 5
4266 11:10:29.217619 rx_lastpass[0][0][1] = 36
4267 11:10:29.220867 rx_firspass[0][0][2] = 6
4268 11:10:29.221334 rx_lastpass[0][0][2] = 36
4269 11:10:29.224255 rx_firspass[0][0][3] = -2
4270 11:10:29.228135 rx_lastpass[0][0][3] = 31
4271 11:10:29.228652 rx_firspass[0][0][4] = 5
4272 11:10:29.230546 rx_lastpass[0][0][4] = 37
4273 11:10:29.233940 rx_firspass[0][0][5] = 1
4274 11:10:29.237282 rx_lastpass[0][0][5] = 31
4275 11:10:29.237667 rx_firspass[0][0][6] = 3
4276 11:10:29.240721 rx_lastpass[0][0][6] = 34
4277 11:10:29.243761 rx_firspass[0][0][7] = 5
4278 11:10:29.244205 rx_lastpass[0][0][7] = 36
4279 11:10:29.247328 rx_firspass[0][0][8] = -2
4280 11:10:29.250680 rx_lastpass[0][0][8] = 32
4281 11:10:29.251066 rx_firspass[0][0][9] = 1
4282 11:10:29.254190 rx_lastpass[0][0][9] = 32
4283 11:10:29.257484 rx_firspass[0][0][10] = 8
4284 11:10:29.260566 rx_lastpass[0][0][10] = 41
4285 11:10:29.260971 rx_firspass[0][0][11] = 1
4286 11:10:29.263940 rx_lastpass[0][0][11] = 32
4287 11:10:29.267353 rx_firspass[0][0][12] = 2
4288 11:10:29.267855 rx_lastpass[0][0][12] = 36
4289 11:10:29.270453 rx_firspass[0][0][13] = 3
4290 11:10:29.274131 rx_lastpass[0][0][13] = 33
4291 11:10:29.277085 rx_firspass[0][0][14] = 2
4292 11:10:29.277467 rx_lastpass[0][0][14] = 37
4293 11:10:29.280282 rx_firspass[0][0][15] = 7
4294 11:10:29.283888 rx_lastpass[0][0][15] = 37
4295 11:10:29.284516 rx_firspass[0][1][0] = 5
4296 11:10:29.287267 rx_lastpass[0][1][0] = 40
4297 11:10:29.290515 rx_firspass[0][1][1] = 5
4298 11:10:29.293707 rx_lastpass[0][1][1] = 38
4299 11:10:29.294175 rx_firspass[0][1][2] = 6
4300 11:10:29.297315 rx_lastpass[0][1][2] = 38
4301 11:10:29.300073 rx_firspass[0][1][3] = -2
4302 11:10:29.300338 rx_lastpass[0][1][3] = 33
4303 11:10:29.303438 rx_firspass[0][1][4] = 5
4304 11:10:29.307191 rx_lastpass[0][1][4] = 39
4305 11:10:29.307421 rx_firspass[0][1][5] = 1
4306 11:10:29.310393 rx_lastpass[0][1][5] = 34
4307 11:10:29.313630 rx_firspass[0][1][6] = 3
4308 11:10:29.316868 rx_lastpass[0][1][6] = 37
4309 11:10:29.316998 rx_firspass[0][1][7] = 3
4310 11:10:29.320325 rx_lastpass[0][1][7] = 38
4311 11:10:29.323585 rx_firspass[0][1][8] = -2
4312 11:10:29.323702 rx_lastpass[0][1][8] = 32
4313 11:10:29.326738 rx_firspass[0][1][9] = 1
4314 11:10:29.330748 rx_lastpass[0][1][9] = 36
4315 11:10:29.333604 rx_firspass[0][1][10] = 7
4316 11:10:29.333723 rx_lastpass[0][1][10] = 43
4317 11:10:29.337226 rx_firspass[0][1][11] = -2
4318 11:10:29.340118 rx_lastpass[0][1][11] = 34
4319 11:10:29.340227 rx_firspass[0][1][12] = 1
4320 11:10:29.343680 rx_lastpass[0][1][12] = 37
4321 11:10:29.346829 rx_firspass[0][1][13] = 1
4322 11:10:29.350256 rx_lastpass[0][1][13] = 35
4323 11:10:29.350375 rx_firspass[0][1][14] = 3
4324 11:10:29.353576 rx_lastpass[0][1][14] = 37
4325 11:10:29.356983 rx_firspass[0][1][15] = 6
4326 11:10:29.357062 rx_lastpass[0][1][15] = 39
4327 11:10:29.360384 rx_firspass[1][0][0] = 5
4328 11:10:29.363934 rx_lastpass[1][0][0] = 39
4329 11:10:29.367201 rx_firspass[1][0][1] = 4
4330 11:10:29.367271 rx_lastpass[1][0][1] = 38
4331 11:10:29.370401 rx_firspass[1][0][2] = 2
4332 11:10:29.373868 rx_lastpass[1][0][2] = 35
4333 11:10:29.373993 rx_firspass[1][0][3] = -1
4334 11:10:29.377076 rx_lastpass[1][0][3] = 33
4335 11:10:29.380324 rx_firspass[1][0][4] = 5
4336 11:10:29.380422 rx_lastpass[1][0][4] = 38
4337 11:10:29.383785 rx_firspass[1][0][5] = 7
4338 11:10:29.387119 rx_lastpass[1][0][5] = 39
4339 11:10:29.390992 rx_firspass[1][0][6] = 7
4340 11:10:29.391076 rx_lastpass[1][0][6] = 40
4341 11:10:29.393593 rx_firspass[1][0][7] = 5
4342 11:10:29.396966 rx_lastpass[1][0][7] = 38
4343 11:10:29.397050 rx_firspass[1][0][8] = 1
4344 11:10:29.400339 rx_lastpass[1][0][8] = 33
4345 11:10:29.403641 rx_firspass[1][0][9] = 0
4346 11:10:29.403725 rx_lastpass[1][0][9] = 32
4347 11:10:29.406983 rx_firspass[1][0][10] = 5
4348 11:10:29.410187 rx_lastpass[1][0][10] = 35
4349 11:10:29.413504 rx_firspass[1][0][11] = 5
4350 11:10:29.413587 rx_lastpass[1][0][11] = 38
4351 11:10:29.416651 rx_firspass[1][0][12] = 6
4352 11:10:29.420155 rx_lastpass[1][0][12] = 38
4353 11:10:29.423776 rx_firspass[1][0][13] = 5
4354 11:10:29.423859 rx_lastpass[1][0][13] = 37
4355 11:10:29.426984 rx_firspass[1][0][14] = 7
4356 11:10:29.430262 rx_lastpass[1][0][14] = 38
4357 11:10:29.430345 rx_firspass[1][0][15] = -3
4358 11:10:29.433553 rx_lastpass[1][0][15] = 30
4359 11:10:29.437145 rx_firspass[1][1][0] = 3
4360 11:10:29.440534 rx_lastpass[1][1][0] = 40
4361 11:10:29.440643 rx_firspass[1][1][1] = 4
4362 11:10:29.443233 rx_lastpass[1][1][1] = 39
4363 11:10:29.446796 rx_firspass[1][1][2] = 0
4364 11:10:29.446880 rx_lastpass[1][1][2] = 36
4365 11:10:29.450053 rx_firspass[1][1][3] = -2
4366 11:10:29.453434 rx_lastpass[1][1][3] = 34
4367 11:10:29.456712 rx_firspass[1][1][4] = 4
4368 11:10:29.456824 rx_lastpass[1][1][4] = 39
4369 11:10:29.460221 rx_firspass[1][1][5] = 5
4370 11:10:29.463648 rx_lastpass[1][1][5] = 40
4371 11:10:29.463737 rx_firspass[1][1][6] = 5
4372 11:10:29.466891 rx_lastpass[1][1][6] = 41
4373 11:10:29.470078 rx_firspass[1][1][7] = 3
4374 11:10:29.470163 rx_lastpass[1][1][7] = 38
4375 11:10:29.473352 rx_firspass[1][1][8] = 0
4376 11:10:29.476926 rx_lastpass[1][1][8] = 35
4377 11:10:29.480109 rx_firspass[1][1][9] = -1
4378 11:10:29.480219 rx_lastpass[1][1][9] = 34
4379 11:10:29.483468 rx_firspass[1][1][10] = 4
4380 11:10:29.487160 rx_lastpass[1][1][10] = 38
4381 11:10:29.487243 rx_firspass[1][1][11] = 4
4382 11:10:29.490265 rx_lastpass[1][1][11] = 40
4383 11:10:29.493166 rx_firspass[1][1][12] = 4
4384 11:10:29.496846 rx_lastpass[1][1][12] = 40
4385 11:10:29.496959 rx_firspass[1][1][13] = 4
4386 11:10:29.500046 rx_lastpass[1][1][13] = 40
4387 11:10:29.503359 rx_firspass[1][1][14] = 5
4388 11:10:29.503461 rx_lastpass[1][1][14] = 40
4389 11:10:29.506809 rx_firspass[1][1][15] = -4
4390 11:10:29.509888 rx_lastpass[1][1][15] = 31
4391 11:10:29.513125 dump params clk_delay
4392 11:10:29.513230 clk_delay[0] = 1
4393 11:10:29.516590 clk_delay[1] = 0
4394 11:10:29.516664 dump params dqs_delay
4395 11:10:29.520020 dqs_delay[0][0] = -2
4396 11:10:29.520093 dqs_delay[0][1] = 0
4397 11:10:29.523236 dqs_delay[1][0] = 0
4398 11:10:29.523342 dqs_delay[1][1] = 0
4399 11:10:29.526456 dump params delay_cell_unit = 735
4400 11:10:29.529873 dump source = 0x0
4401 11:10:29.529956 dump params frequency:1200
4402 11:10:29.533068 dump params rank number:2
4403 11:10:29.533138
4404 11:10:29.536376 dump params write leveling
4405 11:10:29.540000 write leveling[0][0][0] = 0x0
4406 11:10:29.543226 write leveling[0][0][1] = 0x0
4407 11:10:29.543329 write leveling[0][1][0] = 0x0
4408 11:10:29.546434 write leveling[0][1][1] = 0x0
4409 11:10:29.550380 write leveling[1][0][0] = 0x0
4410 11:10:29.553372 write leveling[1][0][1] = 0x0
4411 11:10:29.556934 write leveling[1][1][0] = 0x0
4412 11:10:29.557011 write leveling[1][1][1] = 0x0
4413 11:10:29.560114 dump params cbt_cs
4414 11:10:29.560224 cbt_cs[0][0] = 0x0
4415 11:10:29.563589 cbt_cs[0][1] = 0x0
4416 11:10:29.563687 cbt_cs[1][0] = 0x0
4417 11:10:29.566656 cbt_cs[1][1] = 0x0
4418 11:10:29.566736 dump params cbt_mr12
4419 11:10:29.570118 cbt_mr12[0][0] = 0x0
4420 11:10:29.573753 cbt_mr12[0][1] = 0x0
4421 11:10:29.573836 cbt_mr12[1][0] = 0x0
4422 11:10:29.576863 cbt_mr12[1][1] = 0x0
4423 11:10:29.576947 dump params tx window
4424 11:10:29.580227 tx_center_min[0][0][0] = 0
4425 11:10:29.583690 tx_center_max[0][0][0] = 0
4426 11:10:29.583801 tx_center_min[0][0][1] = 0
4427 11:10:29.586870 tx_center_max[0][0][1] = 0
4428 11:10:29.590083 tx_center_min[0][1][0] = 0
4429 11:10:29.593387 tx_center_max[0][1][0] = 0
4430 11:10:29.593472 tx_center_min[0][1][1] = 0
4431 11:10:29.596632 tx_center_max[0][1][1] = 0
4432 11:10:29.600296 tx_center_min[1][0][0] = 0
4433 11:10:29.603633 tx_center_max[1][0][0] = 0
4434 11:10:29.603717 tx_center_min[1][0][1] = 0
4435 11:10:29.606862 tx_center_max[1][0][1] = 0
4436 11:10:29.610166 tx_center_min[1][1][0] = 0
4437 11:10:29.613630 tx_center_max[1][1][0] = 0
4438 11:10:29.613716 tx_center_min[1][1][1] = 0
4439 11:10:29.616847 tx_center_max[1][1][1] = 0
4440 11:10:29.619941 dump params tx window
4441 11:10:29.620073 tx_win_center[0][0][0] = 0
4442 11:10:29.623410 tx_first_pass[0][0][0] = 0
4443 11:10:29.626827 tx_last_pass[0][0][0] = 0
4444 11:10:29.629916 tx_win_center[0][0][1] = 0
4445 11:10:29.629993 tx_first_pass[0][0][1] = 0
4446 11:10:29.633826 tx_last_pass[0][0][1] = 0
4447 11:10:29.637108 tx_win_center[0][0][2] = 0
4448 11:10:29.637186 tx_first_pass[0][0][2] = 0
4449 11:10:29.640310 tx_last_pass[0][0][2] = 0
4450 11:10:29.643520 tx_win_center[0][0][3] = 0
4451 11:10:29.646888 tx_first_pass[0][0][3] = 0
4452 11:10:29.647057 tx_last_pass[0][0][3] = 0
4453 11:10:29.650108 tx_win_center[0][0][4] = 0
4454 11:10:29.653364 tx_first_pass[0][0][4] = 0
4455 11:10:29.656806 tx_last_pass[0][0][4] = 0
4456 11:10:29.656982 tx_win_center[0][0][5] = 0
4457 11:10:29.659918 tx_first_pass[0][0][5] = 0
4458 11:10:29.663376 tx_last_pass[0][0][5] = 0
4459 11:10:29.663494 tx_win_center[0][0][6] = 0
4460 11:10:29.667419 tx_first_pass[0][0][6] = 0
4461 11:10:29.670260 tx_last_pass[0][0][6] = 0
4462 11:10:29.673769 tx_win_center[0][0][7] = 0
4463 11:10:29.673878 tx_first_pass[0][0][7] = 0
4464 11:10:29.676956 tx_last_pass[0][0][7] = 0
4465 11:10:29.680429 tx_win_center[0][0][8] = 0
4466 11:10:29.680568 tx_first_pass[0][0][8] = 0
4467 11:10:29.683788 tx_last_pass[0][0][8] = 0
4468 11:10:29.686848 tx_win_center[0][0][9] = 0
4469 11:10:29.690160 tx_first_pass[0][0][9] = 0
4470 11:10:29.690263 tx_last_pass[0][0][9] = 0
4471 11:10:29.694017 tx_win_center[0][0][10] = 0
4472 11:10:29.697169 tx_first_pass[0][0][10] = 0
4473 11:10:29.700092 tx_last_pass[0][0][10] = 0
4474 11:10:29.700202 tx_win_center[0][0][11] = 0
4475 11:10:29.703469 tx_first_pass[0][0][11] = 0
4476 11:10:29.707262 tx_last_pass[0][0][11] = 0
4477 11:10:29.710613 tx_win_center[0][0][12] = 0
4478 11:10:29.710695 tx_first_pass[0][0][12] = 0
4479 11:10:29.713567 tx_last_pass[0][0][12] = 0
4480 11:10:29.717459 tx_win_center[0][0][13] = 0
4481 11:10:29.720068 tx_first_pass[0][0][13] = 0
4482 11:10:29.720168 tx_last_pass[0][0][13] = 0
4483 11:10:29.723583 tx_win_center[0][0][14] = 0
4484 11:10:29.726690 tx_first_pass[0][0][14] = 0
4485 11:10:29.730141 tx_last_pass[0][0][14] = 0
4486 11:10:29.730222 tx_win_center[0][0][15] = 0
4487 11:10:29.733331 tx_first_pass[0][0][15] = 0
4488 11:10:29.736992 tx_last_pass[0][0][15] = 0
4489 11:10:29.740216 tx_win_center[0][1][0] = 0
4490 11:10:29.740296 tx_first_pass[0][1][0] = 0
4491 11:10:29.743838 tx_last_pass[0][1][0] = 0
4492 11:10:29.746951 tx_win_center[0][1][1] = 0
4493 11:10:29.750049 tx_first_pass[0][1][1] = 0
4494 11:10:29.750133 tx_last_pass[0][1][1] = 0
4495 11:10:29.753422 tx_win_center[0][1][2] = 0
4496 11:10:29.756877 tx_first_pass[0][1][2] = 0
4497 11:10:29.756962 tx_last_pass[0][1][2] = 0
4498 11:10:29.760067 tx_win_center[0][1][3] = 0
4499 11:10:29.763464 tx_first_pass[0][1][3] = 0
4500 11:10:29.766577 tx_last_pass[0][1][3] = 0
4501 11:10:29.766662 tx_win_center[0][1][4] = 0
4502 11:10:29.770182 tx_first_pass[0][1][4] = 0
4503 11:10:29.773241 tx_last_pass[0][1][4] = 0
4504 11:10:29.777199 tx_win_center[0][1][5] = 0
4505 11:10:29.777284 tx_first_pass[0][1][5] = 0
4506 11:10:29.780119 tx_last_pass[0][1][5] = 0
4507 11:10:29.783495 tx_win_center[0][1][6] = 0
4508 11:10:29.783579 tx_first_pass[0][1][6] = 0
4509 11:10:29.786946 tx_last_pass[0][1][6] = 0
4510 11:10:29.790161 tx_win_center[0][1][7] = 0
4511 11:10:29.793446 tx_first_pass[0][1][7] = 0
4512 11:10:29.793530 tx_last_pass[0][1][7] = 0
4513 11:10:29.796974 tx_win_center[0][1][8] = 0
4514 11:10:29.800209 tx_first_pass[0][1][8] = 0
4515 11:10:29.800320 tx_last_pass[0][1][8] = 0
4516 11:10:29.803619 tx_win_center[0][1][9] = 0
4517 11:10:29.806631 tx_first_pass[0][1][9] = 0
4518 11:10:29.809952 tx_last_pass[0][1][9] = 0
4519 11:10:29.810036 tx_win_center[0][1][10] = 0
4520 11:10:29.813254 tx_first_pass[0][1][10] = 0
4521 11:10:29.816733 tx_last_pass[0][1][10] = 0
4522 11:10:29.819817 tx_win_center[0][1][11] = 0
4523 11:10:29.819931 tx_first_pass[0][1][11] = 0
4524 11:10:29.823502 tx_last_pass[0][1][11] = 0
4525 11:10:29.826568 tx_win_center[0][1][12] = 0
4526 11:10:29.830175 tx_first_pass[0][1][12] = 0
4527 11:10:29.830285 tx_last_pass[0][1][12] = 0
4528 11:10:29.833398 tx_win_center[0][1][13] = 0
4529 11:10:29.836723 tx_first_pass[0][1][13] = 0
4530 11:10:29.840057 tx_last_pass[0][1][13] = 0
4531 11:10:29.840142 tx_win_center[0][1][14] = 0
4532 11:10:29.843319 tx_first_pass[0][1][14] = 0
4533 11:10:29.846764 tx_last_pass[0][1][14] = 0
4534 11:10:29.849691 tx_win_center[0][1][15] = 0
4535 11:10:29.849795 tx_first_pass[0][1][15] = 0
4536 11:10:29.853392 tx_last_pass[0][1][15] = 0
4537 11:10:29.856587 tx_win_center[1][0][0] = 0
4538 11:10:29.859874 tx_first_pass[1][0][0] = 0
4539 11:10:29.859958 tx_last_pass[1][0][0] = 0
4540 11:10:29.863284 tx_win_center[1][0][1] = 0
4541 11:10:29.866556 tx_first_pass[1][0][1] = 0
4542 11:10:29.870044 tx_last_pass[1][0][1] = 0
4543 11:10:29.870128 tx_win_center[1][0][2] = 0
4544 11:10:29.873503 tx_first_pass[1][0][2] = 0
4545 11:10:29.876588 tx_last_pass[1][0][2] = 0
4546 11:10:29.876673 tx_win_center[1][0][3] = 0
4547 11:10:29.879923 tx_first_pass[1][0][3] = 0
4548 11:10:29.883342 tx_last_pass[1][0][3] = 0
4549 11:10:29.886527 tx_win_center[1][0][4] = 0
4550 11:10:29.886611 tx_first_pass[1][0][4] = 0
4551 11:10:29.889963 tx_last_pass[1][0][4] = 0
4552 11:10:29.893417 tx_win_center[1][0][5] = 0
4553 11:10:29.897008 tx_first_pass[1][0][5] = 0
4554 11:10:29.897092 tx_last_pass[1][0][5] = 0
4555 11:10:29.899719 tx_win_center[1][0][6] = 0
4556 11:10:29.903128 tx_first_pass[1][0][6] = 0
4557 11:10:29.903216 tx_last_pass[1][0][6] = 0
4558 11:10:29.906414 tx_win_center[1][0][7] = 0
4559 11:10:29.909870 tx_first_pass[1][0][7] = 0
4560 11:10:29.913175 tx_last_pass[1][0][7] = 0
4561 11:10:29.913261 tx_win_center[1][0][8] = 0
4562 11:10:29.916433 tx_first_pass[1][0][8] = 0
4563 11:10:29.919704 tx_last_pass[1][0][8] = 0
4564 11:10:29.919788 tx_win_center[1][0][9] = 0
4565 11:10:29.923139 tx_first_pass[1][0][9] = 0
4566 11:10:29.926418 tx_last_pass[1][0][9] = 0
4567 11:10:29.929519 tx_win_center[1][0][10] = 0
4568 11:10:29.929604 tx_first_pass[1][0][10] = 0
4569 11:10:29.933195 tx_last_pass[1][0][10] = 0
4570 11:10:29.936269 tx_win_center[1][0][11] = 0
4571 11:10:29.939577 tx_first_pass[1][0][11] = 0
4572 11:10:29.939683 tx_last_pass[1][0][11] = 0
4573 11:10:29.942830 tx_win_center[1][0][12] = 0
4574 11:10:29.946339 tx_first_pass[1][0][12] = 0
4575 11:10:29.949960 tx_last_pass[1][0][12] = 0
4576 11:10:29.950036 tx_win_center[1][0][13] = 0
4577 11:10:29.952944 tx_first_pass[1][0][13] = 0
4578 11:10:29.956032 tx_last_pass[1][0][13] = 0
4579 11:10:29.959297 tx_win_center[1][0][14] = 0
4580 11:10:29.962895 tx_first_pass[1][0][14] = 0
4581 11:10:29.962984 tx_last_pass[1][0][14] = 0
4582 11:10:29.966405 tx_win_center[1][0][15] = 0
4583 11:10:29.970053 tx_first_pass[1][0][15] = 0
4584 11:10:29.972623 tx_last_pass[1][0][15] = 0
4585 11:10:29.972694 tx_win_center[1][1][0] = 0
4586 11:10:29.976260 tx_first_pass[1][1][0] = 0
4587 11:10:29.979464 tx_last_pass[1][1][0] = 0
4588 11:10:29.979540 tx_win_center[1][1][1] = 0
4589 11:10:29.982735 tx_first_pass[1][1][1] = 0
4590 11:10:29.985967 tx_last_pass[1][1][1] = 0
4591 11:10:29.989303 tx_win_center[1][1][2] = 0
4592 11:10:29.989390 tx_first_pass[1][1][2] = 0
4593 11:10:29.992704 tx_last_pass[1][1][2] = 0
4594 11:10:29.996277 tx_win_center[1][1][3] = 0
4595 11:10:29.999223 tx_first_pass[1][1][3] = 0
4596 11:10:29.999300 tx_last_pass[1][1][3] = 0
4597 11:10:30.002828 tx_win_center[1][1][4] = 0
4598 11:10:30.005686 tx_first_pass[1][1][4] = 0
4599 11:10:30.005772 tx_last_pass[1][1][4] = 0
4600 11:10:30.009257 tx_win_center[1][1][5] = 0
4601 11:10:30.012349 tx_first_pass[1][1][5] = 0
4602 11:10:30.015880 tx_last_pass[1][1][5] = 0
4603 11:10:30.015963 tx_win_center[1][1][6] = 0
4604 11:10:30.019724 tx_first_pass[1][1][6] = 0
4605 11:10:30.022523 tx_last_pass[1][1][6] = 0
4606 11:10:30.022628 tx_win_center[1][1][7] = 0
4607 11:10:30.026142 tx_first_pass[1][1][7] = 0
4608 11:10:30.029422 tx_last_pass[1][1][7] = 0
4609 11:10:30.032722 tx_win_center[1][1][8] = 0
4610 11:10:30.032832 tx_first_pass[1][1][8] = 0
4611 11:10:30.035929 tx_last_pass[1][1][8] = 0
4612 11:10:30.039340 tx_win_center[1][1][9] = 0
4613 11:10:30.042886 tx_first_pass[1][1][9] = 0
4614 11:10:30.042964 tx_last_pass[1][1][9] = 0
4615 11:10:30.046140 tx_win_center[1][1][10] = 0
4616 11:10:30.049550 tx_first_pass[1][1][10] = 0
4617 11:10:30.049658 tx_last_pass[1][1][10] = 0
4618 11:10:30.052891 tx_win_center[1][1][11] = 0
4619 11:10:30.056298 tx_first_pass[1][1][11] = 0
4620 11:10:30.059676 tx_last_pass[1][1][11] = 0
4621 11:10:30.059754 tx_win_center[1][1][12] = 0
4622 11:10:30.063002 tx_first_pass[1][1][12] = 0
4623 11:10:30.065982 tx_last_pass[1][1][12] = 0
4624 11:10:30.069557 tx_win_center[1][1][13] = 0
4625 11:10:30.069640 tx_first_pass[1][1][13] = 0
4626 11:10:30.072862 tx_last_pass[1][1][13] = 0
4627 11:10:30.075927 tx_win_center[1][1][14] = 0
4628 11:10:30.079282 tx_first_pass[1][1][14] = 0
4629 11:10:30.079384 tx_last_pass[1][1][14] = 0
4630 11:10:30.083021 tx_win_center[1][1][15] = 0
4631 11:10:30.086217 tx_first_pass[1][1][15] = 0
4632 11:10:30.089406 tx_last_pass[1][1][15] = 0
4633 11:10:30.089515 dump params rx window
4634 11:10:30.093200 rx_firspass[0][0][0] = 0
4635 11:10:30.096319 rx_lastpass[0][0][0] = 0
4636 11:10:30.096424 rx_firspass[0][0][1] = 0
4637 11:10:30.099478 rx_lastpass[0][0][1] = 0
4638 11:10:30.103099 rx_firspass[0][0][2] = 0
4639 11:10:30.103213 rx_lastpass[0][0][2] = 0
4640 11:10:30.106144 rx_firspass[0][0][3] = 0
4641 11:10:30.109410 rx_lastpass[0][0][3] = 0
4642 11:10:30.109517 rx_firspass[0][0][4] = 0
4643 11:10:30.112634 rx_lastpass[0][0][4] = 0
4644 11:10:30.115923 rx_firspass[0][0][5] = 0
4645 11:10:30.116032 rx_lastpass[0][0][5] = 0
4646 11:10:30.119273 rx_firspass[0][0][6] = 0
4647 11:10:30.122654 rx_lastpass[0][0][6] = 0
4648 11:10:30.126659 rx_firspass[0][0][7] = 0
4649 11:10:30.126733 rx_lastpass[0][0][7] = 0
4650 11:10:30.129890 rx_firspass[0][0][8] = 0
4651 11:10:30.132737 rx_lastpass[0][0][8] = 0
4652 11:10:30.132808 rx_firspass[0][0][9] = 0
4653 11:10:30.136091 rx_lastpass[0][0][9] = 0
4654 11:10:30.139292 rx_firspass[0][0][10] = 0
4655 11:10:30.139401 rx_lastpass[0][0][10] = 0
4656 11:10:30.142619 rx_firspass[0][0][11] = 0
4657 11:10:30.145929 rx_lastpass[0][0][11] = 0
4658 11:10:30.149762 rx_firspass[0][0][12] = 0
4659 11:10:30.149864 rx_lastpass[0][0][12] = 0
4660 11:10:30.152839 rx_firspass[0][0][13] = 0
4661 11:10:30.156364 rx_lastpass[0][0][13] = 0
4662 11:10:30.156482 rx_firspass[0][0][14] = 0
4663 11:10:30.159638 rx_lastpass[0][0][14] = 0
4664 11:10:30.163042 rx_firspass[0][0][15] = 0
4665 11:10:30.166060 rx_lastpass[0][0][15] = 0
4666 11:10:30.166138 rx_firspass[0][1][0] = 0
4667 11:10:30.169390 rx_lastpass[0][1][0] = 0
4668 11:10:30.172507 rx_firspass[0][1][1] = 0
4669 11:10:30.172591 rx_lastpass[0][1][1] = 0
4670 11:10:30.176288 rx_firspass[0][1][2] = 0
4671 11:10:30.179585 rx_lastpass[0][1][2] = 0
4672 11:10:30.179662 rx_firspass[0][1][3] = 0
4673 11:10:30.183211 rx_lastpass[0][1][3] = 0
4674 11:10:30.185852 rx_firspass[0][1][4] = 0
4675 11:10:30.185922 rx_lastpass[0][1][4] = 0
4676 11:10:30.189192 rx_firspass[0][1][5] = 0
4677 11:10:30.192576 rx_lastpass[0][1][5] = 0
4678 11:10:30.192651 rx_firspass[0][1][6] = 0
4679 11:10:30.195872 rx_lastpass[0][1][6] = 0
4680 11:10:30.199425 rx_firspass[0][1][7] = 0
4681 11:10:30.199533 rx_lastpass[0][1][7] = 0
4682 11:10:30.202490 rx_firspass[0][1][8] = 0
4683 11:10:30.206067 rx_lastpass[0][1][8] = 0
4684 11:10:30.209238 rx_firspass[0][1][9] = 0
4685 11:10:30.209318 rx_lastpass[0][1][9] = 0
4686 11:10:30.213205 rx_firspass[0][1][10] = 0
4687 11:10:30.216194 rx_lastpass[0][1][10] = 0
4688 11:10:30.216308 rx_firspass[0][1][11] = 0
4689 11:10:30.219434 rx_lastpass[0][1][11] = 0
4690 11:10:30.222836 rx_firspass[0][1][12] = 0
4691 11:10:30.226134 rx_lastpass[0][1][12] = 0
4692 11:10:30.226216 rx_firspass[0][1][13] = 0
4693 11:10:30.229406 rx_lastpass[0][1][13] = 0
4694 11:10:30.233050 rx_firspass[0][1][14] = 0
4695 11:10:30.233122 rx_lastpass[0][1][14] = 0
4696 11:10:30.235800 rx_firspass[0][1][15] = 0
4697 11:10:30.239248 rx_lastpass[0][1][15] = 0
4698 11:10:30.242357 rx_firspass[1][0][0] = 0
4699 11:10:30.242473 rx_lastpass[1][0][0] = 0
4700 11:10:30.245834 rx_firspass[1][0][1] = 0
4701 11:10:30.249212 rx_lastpass[1][0][1] = 0
4702 11:10:30.249316 rx_firspass[1][0][2] = 0
4703 11:10:30.252292 rx_lastpass[1][0][2] = 0
4704 11:10:30.255991 rx_firspass[1][0][3] = 0
4705 11:10:30.256092 rx_lastpass[1][0][3] = 0
4706 11:10:30.259220 rx_firspass[1][0][4] = 0
4707 11:10:30.262450 rx_lastpass[1][0][4] = 0
4708 11:10:30.262528 rx_firspass[1][0][5] = 0
4709 11:10:30.265907 rx_lastpass[1][0][5] = 0
4710 11:10:30.269318 rx_firspass[1][0][6] = 0
4711 11:10:30.269428 rx_lastpass[1][0][6] = 0
4712 11:10:30.272679 rx_firspass[1][0][7] = 0
4713 11:10:30.276358 rx_lastpass[1][0][7] = 0
4714 11:10:30.276481 rx_firspass[1][0][8] = 0
4715 11:10:30.279140 rx_lastpass[1][0][8] = 0
4716 11:10:30.282619 rx_firspass[1][0][9] = 0
4717 11:10:30.285947 rx_lastpass[1][0][9] = 0
4718 11:10:30.286052 rx_firspass[1][0][10] = 0
4719 11:10:30.289445 rx_lastpass[1][0][10] = 0
4720 11:10:30.292697 rx_firspass[1][0][11] = 0
4721 11:10:30.292794 rx_lastpass[1][0][11] = 0
4722 11:10:30.295570 rx_firspass[1][0][12] = 0
4723 11:10:30.298969 rx_lastpass[1][0][12] = 0
4724 11:10:30.302380 rx_firspass[1][0][13] = 0
4725 11:10:30.302454 rx_lastpass[1][0][13] = 0
4726 11:10:30.305609 rx_firspass[1][0][14] = 0
4727 11:10:30.308682 rx_lastpass[1][0][14] = 0
4728 11:10:30.308785 rx_firspass[1][0][15] = 0
4729 11:10:30.312292 rx_lastpass[1][0][15] = 0
4730 11:10:30.315874 rx_firspass[1][1][0] = 0
4731 11:10:30.315976 rx_lastpass[1][1][0] = 0
4732 11:10:30.318832 rx_firspass[1][1][1] = 0
4733 11:10:30.322558 rx_lastpass[1][1][1] = 0
4734 11:10:30.325834 rx_firspass[1][1][2] = 0
4735 11:10:30.325934 rx_lastpass[1][1][2] = 0
4736 11:10:30.328943 rx_firspass[1][1][3] = 0
4737 11:10:30.332041 rx_lastpass[1][1][3] = 0
4738 11:10:30.332123 rx_firspass[1][1][4] = 0
4739 11:10:30.335444 rx_lastpass[1][1][4] = 0
4740 11:10:30.338837 rx_firspass[1][1][5] = 0
4741 11:10:30.338921 rx_lastpass[1][1][5] = 0
4742 11:10:30.342140 rx_firspass[1][1][6] = 0
4743 11:10:30.345726 rx_lastpass[1][1][6] = 0
4744 11:10:30.345809 rx_firspass[1][1][7] = 0
4745 11:10:30.349001 rx_lastpass[1][1][7] = 0
4746 11:10:30.352275 rx_firspass[1][1][8] = 0
4747 11:10:30.352358 rx_lastpass[1][1][8] = 0
4748 11:10:30.355541 rx_firspass[1][1][9] = 0
4749 11:10:30.358766 rx_lastpass[1][1][9] = 0
4750 11:10:30.362106 rx_firspass[1][1][10] = 0
4751 11:10:30.362189 rx_lastpass[1][1][10] = 0
4752 11:10:30.365961 rx_firspass[1][1][11] = 0
4753 11:10:30.369241 rx_lastpass[1][1][11] = 0
4754 11:10:30.369324 rx_firspass[1][1][12] = 0
4755 11:10:30.372380 rx_lastpass[1][1][12] = 0
4756 11:10:30.375563 rx_firspass[1][1][13] = 0
4757 11:10:30.378646 rx_lastpass[1][1][13] = 0
4758 11:10:30.378729 rx_firspass[1][1][14] = 0
4759 11:10:30.382380 rx_lastpass[1][1][14] = 0
4760 11:10:30.386277 rx_firspass[1][1][15] = 0
4761 11:10:30.386360 rx_lastpass[1][1][15] = 0
4762 11:10:30.389044 dump params clk_delay
4763 11:10:30.389127 clk_delay[0] = 0
4764 11:10:30.392315 clk_delay[1] = 0
4765 11:10:30.395675 dump params dqs_delay
4766 11:10:30.395775 dqs_delay[0][0] = 0
4767 11:10:30.398929 dqs_delay[0][1] = 0
4768 11:10:30.399025 dqs_delay[1][0] = 0
4769 11:10:30.402200 dqs_delay[1][1] = 0
4770 11:10:30.405582 dump params delay_cell_unit = 735
4771 11:10:30.405665 dump source = 0x0
4772 11:10:30.408846 dump params frequency:800
4773 11:10:30.411980 dump params rank number:2
4774 11:10:30.412062
4775 11:10:30.412127 dump params write leveling
4776 11:10:30.415772 write leveling[0][0][0] = 0x0
4777 11:10:30.418405 write leveling[0][0][1] = 0x0
4778 11:10:30.421814 write leveling[0][1][0] = 0x0
4779 11:10:30.425339 write leveling[0][1][1] = 0x0
4780 11:10:30.425422 write leveling[1][0][0] = 0x0
4781 11:10:30.428382 write leveling[1][0][1] = 0x0
4782 11:10:30.432009 write leveling[1][1][0] = 0x0
4783 11:10:30.435441 write leveling[1][1][1] = 0x0
4784 11:10:30.435536 dump params cbt_cs
4785 11:10:30.438476 cbt_cs[0][0] = 0x0
4786 11:10:30.438586 cbt_cs[0][1] = 0x0
4787 11:10:30.441691 cbt_cs[1][0] = 0x0
4788 11:10:30.441789 cbt_cs[1][1] = 0x0
4789 11:10:30.445175 dump params cbt_mr12
4790 11:10:30.448317 cbt_mr12[0][0] = 0x0
4791 11:10:30.448420 cbt_mr12[0][1] = 0x0
4792 11:10:30.451939 cbt_mr12[1][0] = 0x0
4793 11:10:30.452047 cbt_mr12[1][1] = 0x0
4794 11:10:30.455299 dump params tx window
4795 11:10:30.458548 tx_center_min[0][0][0] = 0
4796 11:10:30.458652 tx_center_max[0][0][0] = 0
4797 11:10:30.461646 tx_center_min[0][0][1] = 0
4798 11:10:30.464871 tx_center_max[0][0][1] = 0
4799 11:10:30.468277 tx_center_min[0][1][0] = 0
4800 11:10:30.468390 tx_center_max[0][1][0] = 0
4801 11:10:30.471939 tx_center_min[0][1][1] = 0
4802 11:10:30.475141 tx_center_max[0][1][1] = 0
4803 11:10:30.475241 tx_center_min[1][0][0] = 0
4804 11:10:30.478652 tx_center_max[1][0][0] = 0
4805 11:10:30.481759 tx_center_min[1][0][1] = 0
4806 11:10:30.484924 tx_center_max[1][0][1] = 0
4807 11:10:30.485000 tx_center_min[1][1][0] = 0
4808 11:10:30.488274 tx_center_max[1][1][0] = 0
4809 11:10:30.491699 tx_center_min[1][1][1] = 0
4810 11:10:30.494966 tx_center_max[1][1][1] = 0
4811 11:10:30.495043 dump params tx window
4812 11:10:30.498214 tx_win_center[0][0][0] = 0
4813 11:10:30.501529 tx_first_pass[0][0][0] = 0
4814 11:10:30.501636 tx_last_pass[0][0][0] = 0
4815 11:10:30.505022 tx_win_center[0][0][1] = 0
4816 11:10:30.508142 tx_first_pass[0][0][1] = 0
4817 11:10:30.511374 tx_last_pass[0][0][1] = 0
4818 11:10:30.511480 tx_win_center[0][0][2] = 0
4819 11:10:30.514652 tx_first_pass[0][0][2] = 0
4820 11:10:30.518120 tx_last_pass[0][0][2] = 0
4821 11:10:30.521478 tx_win_center[0][0][3] = 0
4822 11:10:30.521584 tx_first_pass[0][0][3] = 0
4823 11:10:30.524655 tx_last_pass[0][0][3] = 0
4824 11:10:30.528018 tx_win_center[0][0][4] = 0
4825 11:10:30.531430 tx_first_pass[0][0][4] = 0
4826 11:10:30.531518 tx_last_pass[0][0][4] = 0
4827 11:10:30.534586 tx_win_center[0][0][5] = 0
4828 11:10:30.537662 tx_first_pass[0][0][5] = 0
4829 11:10:30.537746 tx_last_pass[0][0][5] = 0
4830 11:10:30.541181 tx_win_center[0][0][6] = 0
4831 11:10:30.544378 tx_first_pass[0][0][6] = 0
4832 11:10:30.548186 tx_last_pass[0][0][6] = 0
4833 11:10:30.548271 tx_win_center[0][0][7] = 0
4834 11:10:30.551551 tx_first_pass[0][0][7] = 0
4835 11:10:30.554968 tx_last_pass[0][0][7] = 0
4836 11:10:30.555051 tx_win_center[0][0][8] = 0
4837 11:10:30.557760 tx_first_pass[0][0][8] = 0
4838 11:10:30.561158 tx_last_pass[0][0][8] = 0
4839 11:10:30.565027 tx_win_center[0][0][9] = 0
4840 11:10:30.565111 tx_first_pass[0][0][9] = 0
4841 11:10:30.568050 tx_last_pass[0][0][9] = 0
4842 11:10:30.571080 tx_win_center[0][0][10] = 0
4843 11:10:30.574399 tx_first_pass[0][0][10] = 0
4844 11:10:30.574486 tx_last_pass[0][0][10] = 0
4845 11:10:30.577804 tx_win_center[0][0][11] = 0
4846 11:10:30.581299 tx_first_pass[0][0][11] = 0
4847 11:10:30.584479 tx_last_pass[0][0][11] = 0
4848 11:10:30.584564 tx_win_center[0][0][12] = 0
4849 11:10:30.587962 tx_first_pass[0][0][12] = 0
4850 11:10:30.591126 tx_last_pass[0][0][12] = 0
4851 11:10:30.594287 tx_win_center[0][0][13] = 0
4852 11:10:30.594371 tx_first_pass[0][0][13] = 0
4853 11:10:30.597960 tx_last_pass[0][0][13] = 0
4854 11:10:30.601280 tx_win_center[0][0][14] = 0
4855 11:10:30.604380 tx_first_pass[0][0][14] = 0
4856 11:10:30.604471 tx_last_pass[0][0][14] = 0
4857 11:10:30.607664 tx_win_center[0][0][15] = 0
4858 11:10:30.611110 tx_first_pass[0][0][15] = 0
4859 11:10:30.614346 tx_last_pass[0][0][15] = 0
4860 11:10:30.614430 tx_win_center[0][1][0] = 0
4861 11:10:30.617599 tx_first_pass[0][1][0] = 0
4862 11:10:30.620889 tx_last_pass[0][1][0] = 0
4863 11:10:30.624307 tx_win_center[0][1][1] = 0
4864 11:10:30.624385 tx_first_pass[0][1][1] = 0
4865 11:10:30.627305 tx_last_pass[0][1][1] = 0
4866 11:10:30.630859 tx_win_center[0][1][2] = 0
4867 11:10:30.634640 tx_first_pass[0][1][2] = 0
4868 11:10:30.634742 tx_last_pass[0][1][2] = 0
4869 11:10:30.637403 tx_win_center[0][1][3] = 0
4870 11:10:30.640735 tx_first_pass[0][1][3] = 0
4871 11:10:30.640851 tx_last_pass[0][1][3] = 0
4872 11:10:30.644039 tx_win_center[0][1][4] = 0
4873 11:10:30.647992 tx_first_pass[0][1][4] = 0
4874 11:10:30.651013 tx_last_pass[0][1][4] = 0
4875 11:10:30.651097 tx_win_center[0][1][5] = 0
4876 11:10:30.654203 tx_first_pass[0][1][5] = 0
4877 11:10:30.657573 tx_last_pass[0][1][5] = 0
4878 11:10:30.657678 tx_win_center[0][1][6] = 0
4879 11:10:30.660652 tx_first_pass[0][1][6] = 0
4880 11:10:30.664169 tx_last_pass[0][1][6] = 0
4881 11:10:30.667410 tx_win_center[0][1][7] = 0
4882 11:10:30.667486 tx_first_pass[0][1][7] = 0
4883 11:10:30.670978 tx_last_pass[0][1][7] = 0
4884 11:10:30.674250 tx_win_center[0][1][8] = 0
4885 11:10:30.677372 tx_first_pass[0][1][8] = 0
4886 11:10:30.677483 tx_last_pass[0][1][8] = 0
4887 11:10:30.681032 tx_win_center[0][1][9] = 0
4888 11:10:30.684278 tx_first_pass[0][1][9] = 0
4889 11:10:30.684394 tx_last_pass[0][1][9] = 0
4890 11:10:30.687886 tx_win_center[0][1][10] = 0
4891 11:10:30.690987 tx_first_pass[0][1][10] = 0
4892 11:10:30.694109 tx_last_pass[0][1][10] = 0
4893 11:10:30.694225 tx_win_center[0][1][11] = 0
4894 11:10:30.697547 tx_first_pass[0][1][11] = 0
4895 11:10:30.701010 tx_last_pass[0][1][11] = 0
4896 11:10:30.704078 tx_win_center[0][1][12] = 0
4897 11:10:30.704190 tx_first_pass[0][1][12] = 0
4898 11:10:30.707649 tx_last_pass[0][1][12] = 0
4899 11:10:30.710945 tx_win_center[0][1][13] = 0
4900 11:10:30.714434 tx_first_pass[0][1][13] = 0
4901 11:10:30.714545 tx_last_pass[0][1][13] = 0
4902 11:10:30.717314 tx_win_center[0][1][14] = 0
4903 11:10:30.721244 tx_first_pass[0][1][14] = 0
4904 11:10:30.724163 tx_last_pass[0][1][14] = 0
4905 11:10:30.724271 tx_win_center[0][1][15] = 0
4906 11:10:30.727555 tx_first_pass[0][1][15] = 0
4907 11:10:30.730894 tx_last_pass[0][1][15] = 0
4908 11:10:30.734460 tx_win_center[1][0][0] = 0
4909 11:10:30.734571 tx_first_pass[1][0][0] = 0
4910 11:10:30.737151 tx_last_pass[1][0][0] = 0
4911 11:10:30.740655 tx_win_center[1][0][1] = 0
4912 11:10:30.744096 tx_first_pass[1][0][1] = 0
4913 11:10:30.744204 tx_last_pass[1][0][1] = 0
4914 11:10:30.747192 tx_win_center[1][0][2] = 0
4915 11:10:30.750322 tx_first_pass[1][0][2] = 0
4916 11:10:30.750406 tx_last_pass[1][0][2] = 0
4917 11:10:30.754222 tx_win_center[1][0][3] = 0
4918 11:10:30.757461 tx_first_pass[1][0][3] = 0
4919 11:10:30.760408 tx_last_pass[1][0][3] = 0
4920 11:10:30.760504 tx_win_center[1][0][4] = 0
4921 11:10:30.763828 tx_first_pass[1][0][4] = 0
4922 11:10:30.767230 tx_last_pass[1][0][4] = 0
4923 11:10:30.770452 tx_win_center[1][0][5] = 0
4924 11:10:30.770536 tx_first_pass[1][0][5] = 0
4925 11:10:30.773937 tx_last_pass[1][0][5] = 0
4926 11:10:30.777239 tx_win_center[1][0][6] = 0
4927 11:10:30.777322 tx_first_pass[1][0][6] = 0
4928 11:10:30.780931 tx_last_pass[1][0][6] = 0
4929 11:10:30.783996 tx_win_center[1][0][7] = 0
4930 11:10:30.787615 tx_first_pass[1][0][7] = 0
4931 11:10:30.787696 tx_last_pass[1][0][7] = 0
4932 11:10:30.790350 tx_win_center[1][0][8] = 0
4933 11:10:30.793901 tx_first_pass[1][0][8] = 0
4934 11:10:30.797035 tx_last_pass[1][0][8] = 0
4935 11:10:30.797150 tx_win_center[1][0][9] = 0
4936 11:10:30.800635 tx_first_pass[1][0][9] = 0
4937 11:10:30.803717 tx_last_pass[1][0][9] = 0
4938 11:10:30.803821 tx_win_center[1][0][10] = 0
4939 11:10:30.807048 tx_first_pass[1][0][10] = 0
4940 11:10:30.810567 tx_last_pass[1][0][10] = 0
4941 11:10:30.813815 tx_win_center[1][0][11] = 0
4942 11:10:30.813899 tx_first_pass[1][0][11] = 0
4943 11:10:30.816891 tx_last_pass[1][0][11] = 0
4944 11:10:30.820872 tx_win_center[1][0][12] = 0
4945 11:10:30.823600 tx_first_pass[1][0][12] = 0
4946 11:10:30.823710 tx_last_pass[1][0][12] = 0
4947 11:10:30.827225 tx_win_center[1][0][13] = 0
4948 11:10:30.830522 tx_first_pass[1][0][13] = 0
4949 11:10:30.833850 tx_last_pass[1][0][13] = 0
4950 11:10:30.833933 tx_win_center[1][0][14] = 0
4951 11:10:30.837257 tx_first_pass[1][0][14] = 0
4952 11:10:30.840514 tx_last_pass[1][0][14] = 0
4953 11:10:30.843807 tx_win_center[1][0][15] = 0
4954 11:10:30.847087 tx_first_pass[1][0][15] = 0
4955 11:10:30.847170 tx_last_pass[1][0][15] = 0
4956 11:10:30.850913 tx_win_center[1][1][0] = 0
4957 11:10:30.854100 tx_first_pass[1][1][0] = 0
4958 11:10:30.854189 tx_last_pass[1][1][0] = 0
4959 11:10:30.857245 tx_win_center[1][1][1] = 0
4960 11:10:30.860227 tx_first_pass[1][1][1] = 0
4961 11:10:30.864330 tx_last_pass[1][1][1] = 0
4962 11:10:30.864435 tx_win_center[1][1][2] = 0
4963 11:10:30.866944 tx_first_pass[1][1][2] = 0
4964 11:10:30.870524 tx_last_pass[1][1][2] = 0
4965 11:10:30.870612 tx_win_center[1][1][3] = 0
4966 11:10:30.873610 tx_first_pass[1][1][3] = 0
4967 11:10:30.877021 tx_last_pass[1][1][3] = 0
4968 11:10:30.881091 tx_win_center[1][1][4] = 0
4969 11:10:30.881207 tx_first_pass[1][1][4] = 0
4970 11:10:30.884102 tx_last_pass[1][1][4] = 0
4971 11:10:30.887349 tx_win_center[1][1][5] = 0
4972 11:10:30.890579 tx_first_pass[1][1][5] = 0
4973 11:10:30.890661 tx_last_pass[1][1][5] = 0
4974 11:10:30.893878 tx_win_center[1][1][6] = 0
4975 11:10:30.897165 tx_first_pass[1][1][6] = 0
4976 11:10:30.897249 tx_last_pass[1][1][6] = 0
4977 11:10:30.900690 tx_win_center[1][1][7] = 0
4978 11:10:30.903947 tx_first_pass[1][1][7] = 0
4979 11:10:30.907104 tx_last_pass[1][1][7] = 0
4980 11:10:30.907214 tx_win_center[1][1][8] = 0
4981 11:10:30.910413 tx_first_pass[1][1][8] = 0
4982 11:10:30.913664 tx_last_pass[1][1][8] = 0
4983 11:10:30.916922 tx_win_center[1][1][9] = 0
4984 11:10:30.917005 tx_first_pass[1][1][9] = 0
4985 11:10:30.920140 tx_last_pass[1][1][9] = 0
4986 11:10:30.923620 tx_win_center[1][1][10] = 0
4987 11:10:30.923725 tx_first_pass[1][1][10] = 0
4988 11:10:30.926889 tx_last_pass[1][1][10] = 0
4989 11:10:30.930506 tx_win_center[1][1][11] = 0
4990 11:10:30.933720 tx_first_pass[1][1][11] = 0
4991 11:10:30.933822 tx_last_pass[1][1][11] = 0
4992 11:10:30.936878 tx_win_center[1][1][12] = 0
4993 11:10:30.940348 tx_first_pass[1][1][12] = 0
4994 11:10:30.943958 tx_last_pass[1][1][12] = 0
4995 11:10:30.944042 tx_win_center[1][1][13] = 0
4996 11:10:30.947022 tx_first_pass[1][1][13] = 0
4997 11:10:30.950220 tx_last_pass[1][1][13] = 0
4998 11:10:30.953341 tx_win_center[1][1][14] = 0
4999 11:10:30.956942 tx_first_pass[1][1][14] = 0
5000 11:10:30.957043 tx_last_pass[1][1][14] = 0
5001 11:10:30.960059 tx_win_center[1][1][15] = 0
5002 11:10:30.963425 tx_first_pass[1][1][15] = 0
5003 11:10:30.966925 tx_last_pass[1][1][15] = 0
5004 11:10:30.967009 dump params rx window
5005 11:10:30.970064 rx_firspass[0][0][0] = 0
5006 11:10:30.970148 rx_lastpass[0][0][0] = 0
5007 11:10:30.973418 rx_firspass[0][0][1] = 0
5008 11:10:30.976594 rx_lastpass[0][0][1] = 0
5009 11:10:30.979913 rx_firspass[0][0][2] = 0
5010 11:10:30.979996 rx_lastpass[0][0][2] = 0
5011 11:10:30.983246 rx_firspass[0][0][3] = 0
5012 11:10:30.986567 rx_lastpass[0][0][3] = 0
5013 11:10:30.986651 rx_firspass[0][0][4] = 0
5014 11:10:30.989764 rx_lastpass[0][0][4] = 0
5015 11:10:30.993590 rx_firspass[0][0][5] = 0
5016 11:10:30.993674 rx_lastpass[0][0][5] = 0
5017 11:10:30.996883 rx_firspass[0][0][6] = 0
5018 11:10:31.000204 rx_lastpass[0][0][6] = 0
5019 11:10:31.000287 rx_firspass[0][0][7] = 0
5020 11:10:31.003121 rx_lastpass[0][0][7] = 0
5021 11:10:31.006648 rx_firspass[0][0][8] = 0
5022 11:10:31.009905 rx_lastpass[0][0][8] = 0
5023 11:10:31.009990 rx_firspass[0][0][9] = 0
5024 11:10:31.013035 rx_lastpass[0][0][9] = 0
5025 11:10:31.016282 rx_firspass[0][0][10] = 0
5026 11:10:31.016366 rx_lastpass[0][0][10] = 0
5027 11:10:31.020247 rx_firspass[0][0][11] = 0
5028 11:10:31.023027 rx_lastpass[0][0][11] = 0
5029 11:10:31.023110 rx_firspass[0][0][12] = 0
5030 11:10:31.026486 rx_lastpass[0][0][12] = 0
5031 11:10:31.029591 rx_firspass[0][0][13] = 0
5032 11:10:31.033010 rx_lastpass[0][0][13] = 0
5033 11:10:31.033097 rx_firspass[0][0][14] = 0
5034 11:10:31.036658 rx_lastpass[0][0][14] = 0
5035 11:10:31.039807 rx_firspass[0][0][15] = 0
5036 11:10:31.039890 rx_lastpass[0][0][15] = 0
5037 11:10:31.043223 rx_firspass[0][1][0] = 0
5038 11:10:31.046263 rx_lastpass[0][1][0] = 0
5039 11:10:31.046376 rx_firspass[0][1][1] = 0
5040 11:10:31.049995 rx_lastpass[0][1][1] = 0
5041 11:10:31.053178 rx_firspass[0][1][2] = 0
5042 11:10:31.056234 rx_lastpass[0][1][2] = 0
5043 11:10:31.056345 rx_firspass[0][1][3] = 0
5044 11:10:31.059610 rx_lastpass[0][1][3] = 0
5045 11:10:31.062881 rx_firspass[0][1][4] = 0
5046 11:10:31.062965 rx_lastpass[0][1][4] = 0
5047 11:10:31.066289 rx_firspass[0][1][5] = 0
5048 11:10:31.069974 rx_lastpass[0][1][5] = 0
5049 11:10:31.070084 rx_firspass[0][1][6] = 0
5050 11:10:31.073032 rx_lastpass[0][1][6] = 0
5051 11:10:31.076216 rx_firspass[0][1][7] = 0
5052 11:10:31.076326 rx_lastpass[0][1][7] = 0
5053 11:10:31.079407 rx_firspass[0][1][8] = 0
5054 11:10:31.083192 rx_lastpass[0][1][8] = 0
5055 11:10:31.083276 rx_firspass[0][1][9] = 0
5056 11:10:31.086567 rx_lastpass[0][1][9] = 0
5057 11:10:31.089858 rx_firspass[0][1][10] = 0
5058 11:10:31.092952 rx_lastpass[0][1][10] = 0
5059 11:10:31.093036 rx_firspass[0][1][11] = 0
5060 11:10:31.096489 rx_lastpass[0][1][11] = 0
5061 11:10:31.099505 rx_firspass[0][1][12] = 0
5062 11:10:31.099589 rx_lastpass[0][1][12] = 0
5063 11:10:31.102911 rx_firspass[0][1][13] = 0
5064 11:10:31.106197 rx_lastpass[0][1][13] = 0
5065 11:10:31.109605 rx_firspass[0][1][14] = 0
5066 11:10:31.109689 rx_lastpass[0][1][14] = 0
5067 11:10:31.112924 rx_firspass[0][1][15] = 0
5068 11:10:31.116143 rx_lastpass[0][1][15] = 0
5069 11:10:31.116260 rx_firspass[1][0][0] = 0
5070 11:10:31.119441 rx_lastpass[1][0][0] = 0
5071 11:10:31.122854 rx_firspass[1][0][1] = 0
5072 11:10:31.126331 rx_lastpass[1][0][1] = 0
5073 11:10:31.126414 rx_firspass[1][0][2] = 0
5074 11:10:31.129676 rx_lastpass[1][0][2] = 0
5075 11:10:31.132903 rx_firspass[1][0][3] = 0
5076 11:10:31.132987 rx_lastpass[1][0][3] = 0
5077 11:10:31.136200 rx_firspass[1][0][4] = 0
5078 11:10:31.139427 rx_lastpass[1][0][4] = 0
5079 11:10:31.139511 rx_firspass[1][0][5] = 0
5080 11:10:31.142599 rx_lastpass[1][0][5] = 0
5081 11:10:31.145951 rx_firspass[1][0][6] = 0
5082 11:10:31.146037 rx_lastpass[1][0][6] = 0
5083 11:10:31.149349 rx_firspass[1][0][7] = 0
5084 11:10:31.152625 rx_lastpass[1][0][7] = 0
5085 11:10:31.152709 rx_firspass[1][0][8] = 0
5086 11:10:31.155884 rx_lastpass[1][0][8] = 0
5087 11:10:31.159232 rx_firspass[1][0][9] = 0
5088 11:10:31.162827 rx_lastpass[1][0][9] = 0
5089 11:10:31.162911 rx_firspass[1][0][10] = 0
5090 11:10:31.166102 rx_lastpass[1][0][10] = 0
5091 11:10:31.169297 rx_firspass[1][0][11] = 0
5092 11:10:31.169380 rx_lastpass[1][0][11] = 0
5093 11:10:31.172569 rx_firspass[1][0][12] = 0
5094 11:10:31.175996 rx_lastpass[1][0][12] = 0
5095 11:10:31.179080 rx_firspass[1][0][13] = 0
5096 11:10:31.179164 rx_lastpass[1][0][13] = 0
5097 11:10:31.182518 rx_firspass[1][0][14] = 0
5098 11:10:31.185677 rx_lastpass[1][0][14] = 0
5099 11:10:31.185761 rx_firspass[1][0][15] = 0
5100 11:10:31.189044 rx_lastpass[1][0][15] = 0
5101 11:10:31.192490 rx_firspass[1][1][0] = 0
5102 11:10:31.192589 rx_lastpass[1][1][0] = 0
5103 11:10:31.195660 rx_firspass[1][1][1] = 0
5104 11:10:31.198847 rx_lastpass[1][1][1] = 0
5105 11:10:31.202562 rx_firspass[1][1][2] = 0
5106 11:10:31.202666 rx_lastpass[1][1][2] = 0
5107 11:10:31.205550 rx_firspass[1][1][3] = 0
5108 11:10:31.208885 rx_lastpass[1][1][3] = 0
5109 11:10:31.208968 rx_firspass[1][1][4] = 0
5110 11:10:31.212290 rx_lastpass[1][1][4] = 0
5111 11:10:31.216002 rx_firspass[1][1][5] = 0
5112 11:10:31.216085 rx_lastpass[1][1][5] = 0
5113 11:10:31.219160 rx_firspass[1][1][6] = 0
5114 11:10:31.222568 rx_lastpass[1][1][6] = 0
5115 11:10:31.222651 rx_firspass[1][1][7] = 0
5116 11:10:31.225887 rx_lastpass[1][1][7] = 0
5117 11:10:31.229347 rx_firspass[1][1][8] = 0
5118 11:10:31.229430 rx_lastpass[1][1][8] = 0
5119 11:10:31.232571 rx_firspass[1][1][9] = 0
5120 11:10:31.235766 rx_lastpass[1][1][9] = 0
5121 11:10:31.239020 rx_firspass[1][1][10] = 0
5122 11:10:31.239104 rx_lastpass[1][1][10] = 0
5123 11:10:31.242237 rx_firspass[1][1][11] = 0
5124 11:10:31.245726 rx_lastpass[1][1][11] = 0
5125 11:10:31.245811 rx_firspass[1][1][12] = 0
5126 11:10:31.248727 rx_lastpass[1][1][12] = 0
5127 11:10:31.252029 rx_firspass[1][1][13] = 0
5128 11:10:31.255524 rx_lastpass[1][1][13] = 0
5129 11:10:31.255608 rx_firspass[1][1][14] = 0
5130 11:10:31.258747 rx_lastpass[1][1][14] = 0
5131 11:10:31.262196 rx_firspass[1][1][15] = 0
5132 11:10:31.262279 rx_lastpass[1][1][15] = 0
5133 11:10:31.265397 dump params clk_delay
5134 11:10:31.268674 clk_delay[0] = 0
5135 11:10:31.268758 clk_delay[1] = 0
5136 11:10:31.272195 dump params dqs_delay
5137 11:10:31.272279 dqs_delay[0][0] = 0
5138 11:10:31.275318 dqs_delay[0][1] = 0
5139 11:10:31.275402 dqs_delay[1][0] = 0
5140 11:10:31.278571 dqs_delay[1][1] = 0
5141 11:10:31.282061 dump params delay_cell_unit = 735
5142 11:10:31.282145 mt_set_emi_preloader end
5143 11:10:31.288532 [mt_mem_init] dram size: 0x100000000, rank number: 2
5144 11:10:31.291891 [complex_mem_test] start addr:0x40000000, len:20480
5145 11:10:31.328898 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5146 11:10:31.335836 [complex_mem_test] start addr:0x80000000, len:20480
5147 11:10:31.371493 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5148 11:10:31.377766 [complex_mem_test] start addr:0xc0000000, len:20480
5149 11:10:31.413965 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5150 11:10:31.420613 [complex_mem_test] start addr:0x56000000, len:8192
5151 11:10:31.437141 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5152 11:10:31.437226 ddr_geometry:1
5153 11:10:31.443683 [complex_mem_test] start addr:0x80000000, len:8192
5154 11:10:31.460892 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5155 11:10:31.463975 dram_init: dram init end (result: 0)
5156 11:10:31.470762 Successfully loaded DRAM blobs and ran DRAM calibration
5157 11:10:31.480840 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5158 11:10:31.480925 CBMEM:
5159 11:10:31.484102 IMD: root @ 00000000fffff000 254 entries.
5160 11:10:31.487154 IMD: root @ 00000000ffffec00 62 entries.
5161 11:10:31.493816 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5162 11:10:31.500451 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5163 11:10:31.503819 in-header: 03 a1 00 00 08 00 00 00
5164 11:10:31.507045 in-data: 84 60 60 10 00 00 00 00
5165 11:10:31.510718 Chrome EC: clear events_b mask to 0x0000000020004000
5166 11:10:31.517808 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5167 11:10:31.521198 in-header: 03 fd 00 00 00 00 00 00
5168 11:10:31.521301 in-data:
5169 11:10:31.527776 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5170 11:10:31.527858 CBFS @ 21000 size 3d4000
5171 11:10:31.534514 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5172 11:10:31.537704 CBFS: Locating 'fallback/ramstage'
5173 11:10:31.540881 CBFS: Found @ offset 10d40 size d563
5174 11:10:31.562680 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5175 11:10:31.574607 Accumulated console time in romstage 13586 ms
5176 11:10:31.574729
5177 11:10:31.574799
5178 11:10:31.584584 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5179 11:10:31.587779 ARM64: Exception handlers installed.
5180 11:10:31.587862 ARM64: Testing exception
5181 11:10:31.591732 ARM64: Done test exception
5182 11:10:31.594489 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5183 11:10:31.597837 Manufacturer: ef
5184 11:10:31.601069 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5185 11:10:31.608050 WARNING: RO_VPD is uninitialized or empty.
5186 11:10:31.611158 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5187 11:10:31.614425 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5188 11:10:31.624575 read SPI 0x550600 0x3a00: 4533 us, 3275 KB/s, 26.200 Mbps
5189 11:10:31.627869 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5190 11:10:31.634518 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5191 11:10:31.634602 Enumerating buses...
5192 11:10:31.640969 Show all devs... Before device enumeration.
5193 11:10:31.641054 Root Device: enabled 1
5194 11:10:31.644267 CPU_CLUSTER: 0: enabled 1
5195 11:10:31.644351 CPU: 00: enabled 1
5196 11:10:31.648001 Compare with tree...
5197 11:10:31.651427 Root Device: enabled 1
5198 11:10:31.651510 CPU_CLUSTER: 0: enabled 1
5199 11:10:31.654406 CPU: 00: enabled 1
5200 11:10:31.657730 Root Device scanning...
5201 11:10:31.657813 root_dev_scan_bus for Root Device
5202 11:10:31.661323 CPU_CLUSTER: 0 enabled
5203 11:10:31.664405 root_dev_scan_bus for Root Device done
5204 11:10:31.670832 scan_bus: scanning of bus Root Device took 10689 usecs
5205 11:10:31.670916 done
5206 11:10:31.674166 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5207 11:10:31.677893 Allocating resources...
5208 11:10:31.677976 Reading resources...
5209 11:10:31.680968 Root Device read_resources bus 0 link: 0
5210 11:10:31.687628 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5211 11:10:31.687713 CPU: 00 missing read_resources
5212 11:10:31.694430 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5213 11:10:31.697627 Root Device read_resources bus 0 link: 0 done
5214 11:10:31.700864 Done reading resources.
5215 11:10:31.704031 Show resources in subtree (Root Device)...After reading.
5216 11:10:31.707628 Root Device child on link 0 CPU_CLUSTER: 0
5217 11:10:31.711037 CPU_CLUSTER: 0 child on link 0 CPU: 00
5218 11:10:31.720923 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5219 11:10:31.721037 CPU: 00
5220 11:10:31.724427 Setting resources...
5221 11:10:31.727482 Root Device assign_resources, bus 0 link: 0
5222 11:10:31.730773 CPU_CLUSTER: 0 missing set_resources
5223 11:10:31.734558 Root Device assign_resources, bus 0 link: 0
5224 11:10:31.737440 Done setting resources.
5225 11:10:31.744047 Show resources in subtree (Root Device)...After assigning values.
5226 11:10:31.747421 Root Device child on link 0 CPU_CLUSTER: 0
5227 11:10:31.751284 CPU_CLUSTER: 0 child on link 0 CPU: 00
5228 11:10:31.761235 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5229 11:10:31.761652 CPU: 00
5230 11:10:31.764680 Done allocating resources.
5231 11:10:31.767922 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5232 11:10:31.771216 Enabling resources...
5233 11:10:31.771721 done.
5234 11:10:31.774471 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5235 11:10:31.777968 Initializing devices...
5236 11:10:31.778356 Root Device init ...
5237 11:10:31.781069 mainboard_init: Starting display init.
5238 11:10:31.784397 ADC[4]: Raw value=76102 ID=0
5239 11:10:31.807203 anx7625_power_on_init: Init interface.
5240 11:10:31.810895 anx7625_disable_pd_protocol: Disabled PD feature.
5241 11:10:31.817322 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5242 11:10:31.864427 anx7625_start_dp_work: Secure OCM version=00
5243 11:10:31.867441 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5244 11:10:31.884643 sp_tx_get_edid_block: EDID Block = 1
5245 11:10:32.001739 Extracted contents:
5246 11:10:32.005029 header: 00 ff ff ff ff ff ff 00
5247 11:10:32.008258 serial number: 06 af 5c 14 00 00 00 00 00 1a
5248 11:10:32.011464 version: 01 04
5249 11:10:32.014982 basic params: 95 1a 0e 78 02
5250 11:10:32.018414 chroma info: 99 85 95 55 56 92 28 22 50 54
5251 11:10:32.021928 established: 00 00 00
5252 11:10:32.028761 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5253 11:10:32.031656 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5254 11:10:32.038214 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5255 11:10:32.045086 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5256 11:10:32.051555 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5257 11:10:32.054786 extensions: 00
5258 11:10:32.055168 checksum: ae
5259 11:10:32.055469
5260 11:10:32.058000 Manufacturer: AUO Model 145c Serial Number 0
5261 11:10:32.061874 Made week 0 of 2016
5262 11:10:32.062258 EDID version: 1.4
5263 11:10:32.065007 Digital display
5264 11:10:32.068317 6 bits per primary color channel
5265 11:10:32.068783 DisplayPort interface
5266 11:10:32.071728 Maximum image size: 26 cm x 14 cm
5267 11:10:32.075120 Gamma: 220%
5268 11:10:32.075505 Check DPMS levels
5269 11:10:32.078302 Supported color formats: RGB 4:4:4
5270 11:10:32.081682 First detailed timing is preferred timing
5271 11:10:32.084842 Established timings supported:
5272 11:10:32.088340 Standard timings supported:
5273 11:10:32.088788 Detailed timings
5274 11:10:32.094824 Hex of detail: ce1d56ea50001a3030204600009010000018
5275 11:10:32.098234 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5276 11:10:32.101775 0556 0586 05a6 0640 hborder 0
5277 11:10:32.104615 0300 0304 030a 031a vborder 0
5278 11:10:32.108219 -hsync -vsync
5279 11:10:32.111263 Did detailed timing
5280 11:10:32.114853 Hex of detail: 0000000f0000000000000000000000000020
5281 11:10:32.118380 Manufacturer-specified data, tag 15
5282 11:10:32.124769 Hex of detail: 000000fe0041554f0a202020202020202020
5283 11:10:32.125158 ASCII string: AUO
5284 11:10:32.127827 Hex of detail: 000000fe004231313658414230312e34200a
5285 11:10:32.131223 ASCII string: B116XAB01.4
5286 11:10:32.131609 Checksum
5287 11:10:32.134625 Checksum: 0xae (valid)
5288 11:10:32.141135 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5289 11:10:32.141523 DSI data_rate: 457800000 bps
5290 11:10:32.148651 anx7625_parse_edid: set default k value to 0x3d for panel
5291 11:10:32.152215 anx7625_parse_edid: pixelclock(76300).
5292 11:10:32.155426 hactive(1366), hsync(32), hfp(48), hbp(154)
5293 11:10:32.159264 vactive(768), vsync(6), vfp(4), vbp(16)
5294 11:10:32.162019 anx7625_dsi_config: config dsi.
5295 11:10:32.170368 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5296 11:10:32.191306 anx7625_dsi_config: success to config DSI
5297 11:10:32.194536 anx7625_dp_start: MIPI phy setup OK.
5298 11:10:32.197357 [SSUSB] Setting up USB HOST controller...
5299 11:10:32.201195 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5300 11:10:32.204484 [SSUSB] phy power-on done.
5301 11:10:32.208226 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5302 11:10:32.211524 in-header: 03 fc 01 00 00 00 00 00
5303 11:10:32.212027 in-data:
5304 11:10:32.218210 handle_proto3_response: EC response with error code: 1
5305 11:10:32.218674 SPM: pcm index = 1
5306 11:10:32.221405 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5307 11:10:32.224684 CBFS @ 21000 size 3d4000
5308 11:10:32.231478 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5309 11:10:32.234686 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5310 11:10:32.238051 CBFS: Found @ offset 1e7c0 size 1026
5311 11:10:32.244571 read SPI 0x3f808 0x1026: 1271 us, 3252 KB/s, 26.016 Mbps
5312 11:10:32.247873 SPM: binary array size = 2988
5313 11:10:32.251265 SPM: version = pcm_allinone_v1.17.2_20180829
5314 11:10:32.254333 SPM binary loaded in 32 msecs
5315 11:10:32.262382 spm_kick_im_to_fetch: ptr = 000000004021eec2
5316 11:10:32.265348 spm_kick_im_to_fetch: len = 2988
5317 11:10:32.265726 SPM: spm_kick_pcm_to_run
5318 11:10:32.268835 SPM: spm_kick_pcm_to_run done
5319 11:10:32.271909 SPM: spm_init done in 52 msecs
5320 11:10:32.275487 Root Device init finished in 494962 usecs
5321 11:10:32.278630 CPU_CLUSTER: 0 init ...
5322 11:10:32.288798 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5323 11:10:32.291733 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5324 11:10:32.294935 CBFS @ 21000 size 3d4000
5325 11:10:32.298286 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5326 11:10:32.301747 CBFS: Locating 'sspm.bin'
5327 11:10:32.304961 CBFS: Found @ offset 208c0 size 41cb
5328 11:10:32.315479 read SPI 0x418f8 0x41cb: 5142 us, 3275 KB/s, 26.200 Mbps
5329 11:10:32.323353 CPU_CLUSTER: 0 init finished in 42800 usecs
5330 11:10:32.323744 Devices initialized
5331 11:10:32.326544 Show all devs... After init.
5332 11:10:32.329992 Root Device: enabled 1
5333 11:10:32.330379 CPU_CLUSTER: 0: enabled 1
5334 11:10:32.333267 CPU: 00: enabled 1
5335 11:10:32.336569 BS: BS_DEV_INIT times (ms): entry 0 run 224 exit 0
5336 11:10:32.339909 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5337 11:10:32.343111 ELOG: NV offset 0x558000 size 0x1000
5338 11:10:32.350640 read SPI 0x558000 0x1000: 1258 us, 3255 KB/s, 26.040 Mbps
5339 11:10:32.357835 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5340 11:10:32.360991 ELOG: Event(17) added with size 13 at 2024-07-10 11:10:26 UTC
5341 11:10:32.364424 out: cmd=0x121: 03 db 21 01 00 00 00 00
5342 11:10:32.367556 in-header: 03 eb 00 00 2c 00 00 00
5343 11:10:32.381177 in-data: 40 4b 00 00 00 00 00 00 02 10 00 00 06 80 00 00 7d cb 00 00 06 80 00 00 77 fe 01 00 06 80 00 00 00 0e 01 00 06 80 00 00 60 02 02 00
5344 11:10:32.384297 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5345 11:10:32.387687 in-header: 03 19 00 00 08 00 00 00
5346 11:10:32.390992 in-data: a2 e0 47 00 13 00 00 00
5347 11:10:32.394116 Chrome EC: UHEPI supported
5348 11:10:32.400722 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5349 11:10:32.403889 in-header: 03 e1 00 00 08 00 00 00
5350 11:10:32.407233 in-data: 84 20 60 10 00 00 00 00
5351 11:10:32.410788 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5352 11:10:32.417429 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5353 11:10:32.420559 in-header: 03 e1 00 00 08 00 00 00
5354 11:10:32.423915 in-data: 84 20 60 10 00 00 00 00
5355 11:10:32.430738 ELOG: Event(A1) added with size 10 at 2024-07-10 11:10:26 UTC
5356 11:10:32.437368 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5357 11:10:32.440645 ELOG: Event(A0) added with size 9 at 2024-07-10 11:10:26 UTC
5358 11:10:32.447084 elog_add_boot_reason: Logged dev mode boot
5359 11:10:32.447473 Finalize devices...
5360 11:10:32.450382 Devices finalized
5361 11:10:32.454046 BS: BS_POST_DEVICE times (ms): entry 3 run 0 exit 0
5362 11:10:32.460254 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5363 11:10:32.463673 ELOG: Event(91) added with size 10 at 2024-07-10 11:10:26 UTC
5364 11:10:32.467317 Writing coreboot table at 0xffeda000
5365 11:10:32.473394 0. 0000000000114000-000000000011efff: RAMSTAGE
5366 11:10:32.477162 1. 0000000040000000-000000004023cfff: RAMSTAGE
5367 11:10:32.480280 2. 000000004023d000-00000000545fffff: RAM
5368 11:10:32.483630 3. 0000000054600000-000000005465ffff: BL31
5369 11:10:32.486826 4. 0000000054660000-00000000ffed9fff: RAM
5370 11:10:32.493852 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5371 11:10:32.497016 6. 0000000100000000-000000013fffffff: RAM
5372 11:10:32.499863 Passing 5 GPIOs to payload:
5373 11:10:32.503618 NAME | PORT | POLARITY | VALUE
5374 11:10:32.509990 write protect | 0x00000096 | low | high
5375 11:10:32.513507 EC in RW | 0x000000b1 | high | undefined
5376 11:10:32.516712 EC interrupt | 0x00000097 | low | undefined
5377 11:10:32.523880 TPM interrupt | 0x00000099 | high | undefined
5378 11:10:32.526980 speaker enable | 0x000000af | high | undefined
5379 11:10:32.530072 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5380 11:10:32.533244 in-header: 03 f7 00 00 02 00 00 00
5381 11:10:32.536768 in-data: 04 00
5382 11:10:32.537295 Board ID: 4
5383 11:10:32.539696 ADC[3]: Raw value=215504 ID=1
5384 11:10:32.540118 RAM code: 1
5385 11:10:32.540423 SKU ID: 16
5386 11:10:32.546486 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5387 11:10:32.546888 CBFS @ 21000 size 3d4000
5388 11:10:32.553558 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5389 11:10:32.559989 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum c00c
5390 11:10:32.563104 coreboot table: 940 bytes.
5391 11:10:32.566378 IMD ROOT 0. 00000000fffff000 00001000
5392 11:10:32.570170 IMD SMALL 1. 00000000ffffe000 00001000
5393 11:10:32.573467 CONSOLE 2. 00000000fffde000 00020000
5394 11:10:32.576592 FMAP 3. 00000000fffdd000 0000047c
5395 11:10:32.579599 TIME STAMP 4. 00000000fffdc000 00000910
5396 11:10:32.583341 RAMOOPS 5. 00000000ffedc000 00100000
5397 11:10:32.586650 COREBOOT 6. 00000000ffeda000 00002000
5398 11:10:32.589940 IMD small region:
5399 11:10:32.593110 IMD ROOT 0. 00000000ffffec00 00000400
5400 11:10:32.596601 VBOOT WORK 1. 00000000ffffeb00 00000100
5401 11:10:32.599784 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5402 11:10:32.602919 VPD 3. 00000000ffffea60 0000006c
5403 11:10:32.609947 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5404 11:10:32.616576 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5405 11:10:32.619710 in-header: 03 e1 00 00 08 00 00 00
5406 11:10:32.622962 in-data: 84 20 60 10 00 00 00 00
5407 11:10:32.626312 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5408 11:10:32.629588 CBFS @ 21000 size 3d4000
5409 11:10:32.633264 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5410 11:10:32.636376 CBFS: Locating 'fallback/payload'
5411 11:10:32.645089 CBFS: Found @ offset dc040 size 439a0
5412 11:10:32.732604 read SPI 0xfd078 0x439a0: 84379 us, 3281 KB/s, 26.248 Mbps
5413 11:10:32.735882 Checking segment from ROM address 0x0000000040003a00
5414 11:10:32.742351 Checking segment from ROM address 0x0000000040003a1c
5415 11:10:32.746050 Loading segment from ROM address 0x0000000040003a00
5416 11:10:32.749094 code (compression=0)
5417 11:10:32.759888 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5418 11:10:32.766272 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5419 11:10:32.769680 it's not compressed!
5420 11:10:32.772395 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5421 11:10:32.779248 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5422 11:10:32.786648 Loading segment from ROM address 0x0000000040003a1c
5423 11:10:32.790428 Entry Point 0x0000000080000000
5424 11:10:32.790538 Loaded segments
5425 11:10:32.796864 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5426 11:10:32.799991 Jumping to boot code at 0000000080000000(00000000ffeda000)
5427 11:10:32.810222 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5428 11:10:32.813521 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5429 11:10:32.816407 CBFS @ 21000 size 3d4000
5430 11:10:32.823206 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5431 11:10:32.826861 CBFS: Locating 'fallback/bl31'
5432 11:10:32.830398 CBFS: Found @ offset 36dc0 size 5820
5433 11:10:32.840666 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5434 11:10:32.844412 Checking segment from ROM address 0x0000000040003a00
5435 11:10:32.851079 Checking segment from ROM address 0x0000000040003a1c
5436 11:10:32.854074 Loading segment from ROM address 0x0000000040003a00
5437 11:10:32.857320 code (compression=1)
5438 11:10:32.864238 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5439 11:10:32.874244 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5440 11:10:32.874329 using LZMA
5441 11:10:32.882855 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5442 11:10:32.889253 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5443 11:10:32.892750 Loading segment from ROM address 0x0000000040003a1c
5444 11:10:32.896174 Entry Point 0x0000000054601000
5445 11:10:32.896258 Loaded segments
5446 11:10:32.899522 NOTICE: MT8183 bl31_setup
5447 11:10:32.906861 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5448 11:10:32.909865 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5449 11:10:32.913209 INFO: [DEVAPC] dump DEVAPC registers:
5450 11:10:32.922989 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5451 11:10:32.929892 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5452 11:10:32.939605 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5453 11:10:32.946132 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5454 11:10:32.956422 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5455 11:10:32.963006 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5456 11:10:32.973029 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5457 11:10:32.979660 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5458 11:10:32.986259 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5459 11:10:32.996319 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5460 11:10:33.002922 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5461 11:10:33.013325 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5462 11:10:33.019596 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5463 11:10:33.026298 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5464 11:10:33.035891 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5465 11:10:33.042669 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5466 11:10:33.049616 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5467 11:10:33.056240 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5468 11:10:33.066281 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5469 11:10:33.072577 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5470 11:10:33.079156 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5471 11:10:33.085878 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5472 11:10:33.089291 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5473 11:10:33.092640 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5474 11:10:33.095846 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5475 11:10:33.099210 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5476 11:10:33.102655 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5477 11:10:33.109145 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5478 11:10:33.115585 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5479 11:10:33.115665 WARNING: region 0:
5480 11:10:33.119142 WARNING: apc:0x168, sa:0x0, ea:0xfff
5481 11:10:33.122398 WARNING: region 1:
5482 11:10:33.125893 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5483 11:10:33.125970 WARNING: region 2:
5484 11:10:33.128841 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5485 11:10:33.132129 WARNING: region 3:
5486 11:10:33.135544 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5487 11:10:33.135638 WARNING: region 4:
5488 11:10:33.142397 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5489 11:10:33.142492 WARNING: region 5:
5490 11:10:33.145568 WARNING: apc:0x0, sa:0x0, ea:0x0
5491 11:10:33.148968 WARNING: region 6:
5492 11:10:33.149082 WARNING: apc:0x0, sa:0x0, ea:0x0
5493 11:10:33.152568 WARNING: region 7:
5494 11:10:33.155985 WARNING: apc:0x0, sa:0x0, ea:0x0
5495 11:10:33.162216 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5496 11:10:33.165740 INFO: SPM: enable SPMC mode
5497 11:10:33.169060 NOTICE: spm_boot_init() start
5498 11:10:33.172766 NOTICE: spm_boot_init() end
5499 11:10:33.175711 INFO: BL31: Initializing runtime services
5500 11:10:33.179052 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5501 11:10:33.186032 INFO: BL31: Preparing for EL3 exit to normal world
5502 11:10:33.189266 INFO: Entry point address = 0x80000000
5503 11:10:33.192333 INFO: SPSR = 0x8
5504 11:10:33.213473
5505 11:10:33.213848
5506 11:10:33.214142
5507 11:10:33.215681 end: 2.2.3 depthcharge-start (duration 00:00:24) [common]
5508 11:10:33.216133 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
5509 11:10:33.216593 Setting prompt string to ['jacuzzi:']
5510 11:10:33.216930 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:27)
5511 11:10:33.217524 Starting depthcharge on Juniper...
5512 11:10:33.217881
5513 11:10:33.219775 vboot_handoff: creating legacy vboot_handoff structure
5514 11:10:33.220154
5515 11:10:33.223355 ec_init(0): CrosEC protocol v3 supported (544, 544)
5516 11:10:33.223741
5517 11:10:33.226685 Wipe memory regions:
5518 11:10:33.227220
5519 11:10:33.229979 [0x00000040000000, 0x00000054600000)
5520 11:10:33.273013
5521 11:10:33.273545 [0x00000054660000, 0x00000080000000)
5522 11:10:33.364490
5523 11:10:33.365011 [0x000000811994a0, 0x000000ffeda000)
5524 11:10:33.623845
5525 11:10:33.624075 [0x00000100000000, 0x00000140000000)
5526 11:10:33.756613
5527 11:10:33.759880 Initializing XHCI USB controller at 0x11200000.
5528 11:10:33.783122
5529 11:10:33.786327 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5530 11:10:33.786838
5531 11:10:33.787275
5532 11:10:33.788058 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5533 11:10:33.788505 Sending line: 'tftpboot 192.168.201.1 14786846/tftp-deploy-qqigt0vp/kernel/image.itb 14786846/tftp-deploy-qqigt0vp/kernel/cmdline '
5535 11:10:33.889990 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5536 11:10:33.890364 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:26)
5537 11:10:33.894859 jacuzzi: tftpboot 192.168.201.1 14786846/tftp-deploy-qqigt0vp/kernel/image.itp-deploy-qqigt0vp/kernel/cmdline
5538 11:10:33.895251
5539 11:10:33.895547 Waiting for link
5540 11:10:34.296664
5541 11:10:34.297163 R8152: Initializing
5542 11:10:34.297500
5543 11:10:34.300325 Version 9 (ocp_data = 6010)
5544 11:10:34.300843
5545 11:10:34.303474 R8152: Done initializing
5546 11:10:34.303904
5547 11:10:34.304327 Adding net device
5548 11:10:34.688667
5549 11:10:34.689127 done.
5550 11:10:34.689522
5551 11:10:34.689880 MAC: 00:e0:4c:68:0b:b9
5552 11:10:34.690238
5553 11:10:34.691953 Sending DHCP discover... done.
5554 11:10:34.692286
5555 11:10:34.694934 Waiting for reply... done.
5556 11:10:34.695167
5557 11:10:34.698274 Sending DHCP request... done.
5558 11:10:34.698435
5559 11:10:34.698550 Waiting for reply... done.
5560 11:10:34.698653
5561 11:10:34.701499 My ip is 192.168.201.13
5562 11:10:34.701671
5563 11:10:34.704993 The DHCP server ip is 192.168.201.1
5564 11:10:34.705181
5565 11:10:34.708361 TFTP server IP predefined by user: 192.168.201.1
5566 11:10:34.708598
5567 11:10:34.715045 Bootfile predefined by user: 14786846/tftp-deploy-qqigt0vp/kernel/image.itb
5568 11:10:34.715269
5569 11:10:34.718456 Sending tftp read request... done.
5570 11:10:34.718706
5571 11:10:34.725378 Waiting for the transfer...
5572 11:10:34.725608
5573 11:10:35.088142 00000000 ################################################################
5574 11:10:35.088276
5575 11:10:35.368601 00080000 ################################################################
5576 11:10:35.368726
5577 11:10:35.655435 00100000 ################################################################
5578 11:10:35.655576
5579 11:10:35.935751 00180000 ################################################################
5580 11:10:35.935890
5581 11:10:36.195692 00200000 ################################################################
5582 11:10:36.195829
5583 11:10:36.454569 00280000 ################################################################
5584 11:10:36.454712
5585 11:10:36.715540 00300000 ################################################################
5586 11:10:36.715673
5587 11:10:36.984617 00380000 ################################################################
5588 11:10:36.984747
5589 11:10:37.279521 00400000 ################################################################
5590 11:10:37.279652
5591 11:10:37.577656 00480000 ################################################################
5592 11:10:37.577786
5593 11:10:37.860318 00500000 ################################################################
5594 11:10:37.860476
5595 11:10:38.135311 00580000 ################################################################
5596 11:10:38.135444
5597 11:10:38.409019 00600000 ################################################################
5598 11:10:38.409146
5599 11:10:38.698521 00680000 ################################################################
5600 11:10:38.698653
5601 11:10:38.982874 00700000 ################################################################
5602 11:10:38.982998
5603 11:10:39.274047 00780000 ################################################################
5604 11:10:39.274180
5605 11:10:39.562469 00800000 ################################################################
5606 11:10:39.562598
5607 11:10:39.858934 00880000 ################################################################
5608 11:10:39.859069
5609 11:10:40.155219 00900000 ################################################################
5610 11:10:40.155345
5611 11:10:40.442118 00980000 ################################################################
5612 11:10:40.442251
5613 11:10:40.741444 00a00000 ################################################################
5614 11:10:40.741575
5615 11:10:41.038954 00a80000 ################################################################
5616 11:10:41.039086
5617 11:10:41.326099 00b00000 ################################################################
5618 11:10:41.326271
5619 11:10:41.580222 00b80000 ################################################################
5620 11:10:41.580346
5621 11:10:41.833401 00c00000 ################################################################
5622 11:10:41.833532
5623 11:10:42.126685 00c80000 ################################################################
5624 11:10:42.126814
5625 11:10:42.383562 00d00000 ################################################################
5626 11:10:42.383688
5627 11:10:42.645620 00d80000 ################################################################
5628 11:10:42.645742
5629 11:10:42.916923 00e00000 ################################################################
5630 11:10:42.917043
5631 11:10:43.225501 00e80000 ################################################################
5632 11:10:43.225994
5633 11:10:43.546903 00f00000 ################################################################
5634 11:10:43.547058
5635 11:10:43.840514 00f80000 ################################################################
5636 11:10:43.841026
5637 11:10:44.175456 01000000 ################################################################
5638 11:10:44.176046
5639 11:10:44.511379 01080000 ################################################################
5640 11:10:44.511829
5641 11:10:44.859045 01100000 ################################################################
5642 11:10:44.859503
5643 11:10:45.202540 01180000 ################################################################
5644 11:10:45.203205
5645 11:10:45.541504 01200000 ################################################################
5646 11:10:45.541835
5647 11:10:45.854617 01280000 ################################################################
5648 11:10:45.855103
5649 11:10:46.184234 01300000 ################################################################
5650 11:10:46.184369
5651 11:10:46.455495 01380000 ################################################################
5652 11:10:46.455618
5653 11:10:46.715937 01400000 ################################################################
5654 11:10:46.716067
5655 11:10:46.975587 01480000 ################################################################
5656 11:10:46.975712
5657 11:10:47.247479 01500000 ################################################################
5658 11:10:47.247616
5659 11:10:47.541687 01580000 ################################################################
5660 11:10:47.541821
5661 11:10:47.823181 01600000 ################################################################
5662 11:10:47.823344
5663 11:10:48.112731 01680000 ################################################################
5664 11:10:48.112867
5665 11:10:48.387534 01700000 ################################################################
5666 11:10:48.387696
5667 11:10:48.674080 01780000 ################################################################
5668 11:10:48.674219
5669 11:10:48.973168 01800000 ################################################################
5670 11:10:48.973315
5671 11:10:49.271429 01880000 ################################################################
5672 11:10:49.271568
5673 11:10:49.555830 01900000 ################################################################
5674 11:10:49.555956
5675 11:10:49.839011 01980000 ################################################################
5676 11:10:49.839164
5677 11:10:50.114212 01a00000 ################################################################
5678 11:10:50.114341
5679 11:10:50.385909 01a80000 ################################################################
5680 11:10:50.386069
5681 11:10:50.681754 01b00000 ################################################################
5682 11:10:50.681903
5683 11:10:50.960322 01b80000 ################################################################
5684 11:10:50.960479
5685 11:10:51.239415 01c00000 ################################################################
5686 11:10:51.239565
5687 11:10:51.529283 01c80000 ################################################################
5688 11:10:51.529739
5689 11:10:51.863443 01d00000 ################################################################
5690 11:10:51.863896
5691 11:10:52.203439 01d80000 ################################################################
5692 11:10:52.203889
5693 11:10:52.529436 01e00000 ################################################################
5694 11:10:52.529567
5695 11:10:52.786234 01e80000 ################################################################
5696 11:10:52.786396
5697 11:10:53.063787 01f00000 ################################################################
5698 11:10:53.063965
5699 11:10:53.356576 01f80000 ################################################################
5700 11:10:53.356710
5701 11:10:53.647580 02000000 ################################################################
5702 11:10:53.647756
5703 11:10:53.930735 02080000 ################################################################
5704 11:10:53.930870
5705 11:10:54.216645 02100000 ################################################################
5706 11:10:54.216775
5707 11:10:54.481071 02180000 ################################################################
5708 11:10:54.481197
5709 11:10:54.767608 02200000 ################################################################
5710 11:10:54.767741
5711 11:10:55.047788 02280000 ################################################################
5712 11:10:55.047919
5713 11:10:55.331038 02300000 ################################################################
5714 11:10:55.331172
5715 11:10:55.606554 02380000 ################################################################
5716 11:10:55.606688
5717 11:10:55.902493 02400000 ################################################################
5718 11:10:55.902635
5719 11:10:56.206889 02480000 ################################################################
5720 11:10:56.207027
5721 11:10:56.499313 02500000 ################################################################
5722 11:10:56.499447
5723 11:10:56.790772 02580000 ################################################################
5724 11:10:56.790924
5725 11:10:57.078058 02600000 ################################################################
5726 11:10:57.078195
5727 11:10:57.352628 02680000 ################################################################
5728 11:10:57.352765
5729 11:10:57.639829 02700000 ################################################################
5730 11:10:57.639951
5731 11:10:57.929163 02780000 ################################################################
5732 11:10:57.929288
5733 11:10:58.222436 02800000 ################################################################
5734 11:10:58.222583
5735 11:10:58.499455 02880000 ################################################################
5736 11:10:58.499581
5737 11:10:58.779026 02900000 ################################################################
5738 11:10:58.779154
5739 11:10:59.088817 02980000 ################################################################
5740 11:10:59.088955
5741 11:10:59.373195 02a00000 ################################################################
5742 11:10:59.373334
5743 11:10:59.671914 02a80000 ################################################################
5744 11:10:59.672046
5745 11:10:59.967409 02b00000 ################################################################
5746 11:10:59.967546
5747 11:11:00.261286 02b80000 ################################################################
5748 11:11:00.261419
5749 11:11:00.560386 02c00000 ################################################################
5750 11:11:00.560532
5751 11:11:00.858081 02c80000 ################################################################
5752 11:11:00.858218
5753 11:11:01.158485 02d00000 ################################################################
5754 11:11:01.158615
5755 11:11:01.443744 02d80000 ################################################################
5756 11:11:01.443867
5757 11:11:01.706993 02e00000 ################################################################
5758 11:11:01.707146
5759 11:11:01.971997 02e80000 ################################################################
5760 11:11:01.972117
5761 11:11:02.236987 02f00000 ################################################################
5762 11:11:02.237110
5763 11:11:02.496420 02f80000 ################################################################
5764 11:11:02.496553
5765 11:11:02.766901 03000000 ################################################################
5766 11:11:02.767028
5767 11:11:03.037692 03080000 ################################################################
5768 11:11:03.037813
5769 11:11:03.326770 03100000 ################################################################
5770 11:11:03.326892
5771 11:11:03.616849 03180000 ################################################################
5772 11:11:03.616975
5773 11:11:03.902321 03200000 ################################################################
5774 11:11:03.902445
5775 11:11:04.166279 03280000 ################################################################
5776 11:11:04.166427
5777 11:11:04.418658 03300000 ################################################################
5778 11:11:04.418805
5779 11:11:04.608908 03380000 ############################################ done.
5780 11:11:04.609027
5781 11:11:04.612451 The bootfile was 54358226 bytes long.
5782 11:11:04.612568
5783 11:11:04.615835 Sending tftp read request... done.
5784 11:11:04.615919
5785 11:11:04.619414 Waiting for the transfer...
5786 11:11:04.619532
5787 11:11:04.622732 00000000 # done.
5788 11:11:04.622833
5789 11:11:04.628872 Command line loaded dynamically from TFTP file: 14786846/tftp-deploy-qqigt0vp/kernel/cmdline
5790 11:11:04.628989
5791 11:11:04.645911 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
5792 11:11:04.646365
5793 11:11:04.646692 Loading FIT.
5794 11:11:04.647114
5795 11:11:04.649160 Image ramdisk-1 has 41182229 bytes.
5796 11:11:04.649624
5797 11:11:04.652691 Image fdt-1 has 57695 bytes.
5798 11:11:04.653195
5799 11:11:04.655839 Image kernel-1 has 13116259 bytes.
5800 11:11:04.656307
5801 11:11:04.665991 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5802 11:11:04.666504
5803 11:11:04.675969 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5804 11:11:04.676378
5805 11:11:04.682483 Choosing best match conf-1 for compat google,juniper-sku16.
5806 11:11:04.686140
5807 11:11:04.690958 Connected to device vid:did:rid of 1ae0:0028:00
5808 11:11:04.699208
5809 11:11:04.702624 tpm_get_response: command 0x17b, return code 0x0
5810 11:11:04.702709
5811 11:11:04.705929 tpm_cleanup: add release locality here.
5812 11:11:04.706014
5813 11:11:04.709305 Shutting down all USB controllers.
5814 11:11:04.709389
5815 11:11:04.712508 Removing current net device
5816 11:11:04.712593
5817 11:11:04.716048 Exiting depthcharge with code 4 at timestamp: 48721776
5818 11:11:04.716132
5819 11:11:04.719598 LZMA decompressing kernel-1 to 0x80193568
5820 11:11:04.719683
5821 11:11:04.725417 LZMA decompressing kernel-1 to 0x40000000
5822 11:11:06.589028
5823 11:11:06.589487 jumping to kernel
5824 11:11:06.591432 end: 2.2.4 bootloader-commands (duration 00:00:33) [common]
5825 11:11:06.591888 start: 2.2.5 auto-login-action (timeout 00:03:54) [common]
5826 11:11:06.592228 Setting prompt string to ['Linux version [0-9]']
5827 11:11:06.592583 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5828 11:11:06.592939 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5829 11:11:06.664215
5830 11:11:06.667136 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5831 11:11:06.671185 start: 2.2.5.1 login-action (timeout 00:03:54) [common]
5832 11:11:06.671806 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5833 11:11:06.672329 Setting prompt string to []
5834 11:11:06.672849 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5835 11:11:06.673238 Using line separator: #'\n'#
5836 11:11:06.673552 No login prompt set.
5837 11:11:06.673866 Parsing kernel messages
5838 11:11:06.674151 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5839 11:11:06.674685 [login-action] Waiting for messages, (timeout 00:03:54)
5840 11:11:06.674979 Waiting using forced prompt support (timeout 00:01:57)
5841 11:11:06.690049 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j261272-arm64-gcc-12-defconfig-arm64-chromebook-bgdbp) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024
5842 11:11:06.694082 [ 0.000000] random: crng init done
5843 11:11:06.696995 [ 0.000000] Machine model: Google juniper sku16 board
5844 11:11:06.700584 [ 0.000000] efi: UEFI not found.
5845 11:11:06.710091 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5846 11:11:06.716769 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5847 11:11:06.723715 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5848 11:11:06.730373 [ 0.000000] printk: bootconsole [mtk8250] enabled
5849 11:11:06.738292 [ 0.000000] NUMA: No NUMA configuration found
5850 11:11:06.745124 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5851 11:11:06.751150 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5852 11:11:06.751768 [ 0.000000] Zone ranges:
5853 11:11:06.757530 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5854 11:11:06.760877 [ 0.000000] DMA32 empty
5855 11:11:06.767935 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5856 11:11:06.770820 [ 0.000000] Movable zone start for each node
5857 11:11:06.774265 [ 0.000000] Early memory node ranges
5858 11:11:06.781308 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5859 11:11:06.788021 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5860 11:11:06.794391 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5861 11:11:06.800783 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5862 11:11:06.808019 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5863 11:11:06.814360 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5864 11:11:06.834412 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5865 11:11:06.840887 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5866 11:11:06.847683 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5867 11:11:06.851071 [ 0.000000] psci: probing for conduit method from DT.
5868 11:11:06.857686 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5869 11:11:06.860923 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5870 11:11:06.867355 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5871 11:11:06.870636 [ 0.000000] psci: SMC Calling Convention v1.1
5872 11:11:06.877574 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5873 11:11:06.880944 [ 0.000000] Detected VIPT I-cache on CPU0
5874 11:11:06.887627 [ 0.000000] CPU features: detected: GIC system register CPU interface
5875 11:11:06.893828 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5876 11:11:06.900636 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5877 11:11:06.907590 [ 0.000000] CPU features: detected: ARM erratum 845719
5878 11:11:06.910698 [ 0.000000] alternatives: applying boot alternatives
5879 11:11:06.914336 [ 0.000000] Fallback order for Node 0: 0
5880 11:11:06.920517 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5881 11:11:06.924029 [ 0.000000] Policy zone: Normal
5882 11:11:06.943981 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
5883 11:11:06.956957 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5884 11:11:06.963738 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5885 11:11:06.973863 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5886 11:11:06.980333 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
5887 11:11:06.983500 <6>[ 0.000000] software IO TLB: area num 8.
5888 11:11:07.009580 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5889 11:11:07.067457 <6>[ 0.000000] Memory: 3874860K/4191232K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 283604K reserved, 32768K cma-reserved)
5890 11:11:07.074586 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5891 11:11:07.081082 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5892 11:11:07.084230 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5893 11:11:07.091285 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5894 11:11:07.097391 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5895 11:11:07.101140 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5896 11:11:07.110978 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5897 11:11:07.117946 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5898 11:11:07.120801 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5899 11:11:07.133235 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5900 11:11:07.139695 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5901 11:11:07.143283 <6>[ 0.000000] GICv3: 640 SPIs implemented
5902 11:11:07.146706 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5903 11:11:07.152694 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5904 11:11:07.155896 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5905 11:11:07.162428 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5906 11:11:07.176026 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5907 11:11:07.185505 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5908 11:11:07.192259 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5909 11:11:07.204520 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5910 11:11:07.218342 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5911 11:11:07.224486 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5912 11:11:07.231314 <6>[ 0.009479] Console: colour dummy device 80x25
5913 11:11:07.234432 <6>[ 0.014514] printk: console [tty1] enabled
5914 11:11:07.248056 <6>[ 0.018905] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5915 11:11:07.251772 <6>[ 0.029369] pid_max: default: 32768 minimum: 301
5916 11:11:07.254450 <6>[ 0.034249] LSM: Security Framework initializing
5917 11:11:07.264420 <6>[ 0.039165] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5918 11:11:07.271363 <6>[ 0.046789] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5919 11:11:07.277216 <4>[ 0.055665] cacheinfo: Unable to detect cache hierarchy for CPU 0
5920 11:11:07.287635 <6>[ 0.062294] cblist_init_generic: Setting adjustable number of callback queues.
5921 11:11:07.293807 <6>[ 0.069739] cblist_init_generic: Setting shift to 3 and lim to 1.
5922 11:11:07.300629 <6>[ 0.076092] cblist_init_generic: Setting adjustable number of callback queues.
5923 11:11:07.307412 <6>[ 0.083537] cblist_init_generic: Setting shift to 3 and lim to 1.
5924 11:11:07.310914 <6>[ 0.089935] rcu: Hierarchical SRCU implementation.
5925 11:11:07.317122 <6>[ 0.094961] rcu: Max phase no-delay instances is 1000.
5926 11:11:07.324546 <6>[ 0.102875] EFI services will not be available.
5927 11:11:07.328111 <6>[ 0.107829] smp: Bringing up secondary CPUs ...
5928 11:11:07.338525 <6>[ 0.113092] Detected VIPT I-cache on CPU1
5929 11:11:07.345110 <4>[ 0.113139] cacheinfo: Unable to detect cache hierarchy for CPU 1
5930 11:11:07.351693 <6>[ 0.113147] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5931 11:11:07.358030 <6>[ 0.113180] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5932 11:11:07.361685 <6>[ 0.113661] Detected VIPT I-cache on CPU2
5933 11:11:07.368417 <4>[ 0.113694] cacheinfo: Unable to detect cache hierarchy for CPU 2
5934 11:11:07.375034 <6>[ 0.113699] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5935 11:11:07.381661 <6>[ 0.113710] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5936 11:11:07.384969 <6>[ 0.114156] Detected VIPT I-cache on CPU3
5937 11:11:07.391576 <4>[ 0.114187] cacheinfo: Unable to detect cache hierarchy for CPU 3
5938 11:11:07.398133 <6>[ 0.114191] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5939 11:11:07.404708 <6>[ 0.114203] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5940 11:11:07.411506 <6>[ 0.114778] CPU features: detected: Spectre-v2
5941 11:11:07.415068 <6>[ 0.114789] CPU features: detected: Spectre-BHB
5942 11:11:07.421318 <6>[ 0.114792] CPU features: detected: ARM erratum 858921
5943 11:11:07.424935 <6>[ 0.114798] Detected VIPT I-cache on CPU4
5944 11:11:07.431417 <4>[ 0.114846] cacheinfo: Unable to detect cache hierarchy for CPU 4
5945 11:11:07.438306 <6>[ 0.114853] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5946 11:11:07.445007 <6>[ 0.114861] arch_timer: Enabling local workaround for ARM erratum 858921
5947 11:11:07.452420 <6>[ 0.114872] arch_timer: CPU4: Trapping CNTVCT access
5948 11:11:07.458186 <6>[ 0.114880] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5949 11:11:07.461837 <6>[ 0.115365] Detected VIPT I-cache on CPU5
5950 11:11:07.467789 <4>[ 0.115405] cacheinfo: Unable to detect cache hierarchy for CPU 5
5951 11:11:07.475303 <6>[ 0.115410] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5952 11:11:07.482007 <6>[ 0.115417] arch_timer: Enabling local workaround for ARM erratum 858921
5953 11:11:07.488190 <6>[ 0.115423] arch_timer: CPU5: Trapping CNTVCT access
5954 11:11:07.494858 <6>[ 0.115428] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5955 11:11:07.498162 <6>[ 0.115865] Detected VIPT I-cache on CPU6
5956 11:11:07.504926 <4>[ 0.115911] cacheinfo: Unable to detect cache hierarchy for CPU 6
5957 11:11:07.511442 <6>[ 0.115917] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5958 11:11:07.517880 <6>[ 0.115924] arch_timer: Enabling local workaround for ARM erratum 858921
5959 11:11:07.524384 <6>[ 0.115930] arch_timer: CPU6: Trapping CNTVCT access
5960 11:11:07.531403 <6>[ 0.115935] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5961 11:11:07.534606 <6>[ 0.116465] Detected VIPT I-cache on CPU7
5962 11:11:07.541064 <4>[ 0.116508] cacheinfo: Unable to detect cache hierarchy for CPU 7
5963 11:11:07.547799 <6>[ 0.116514] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5964 11:11:07.557594 <6>[ 0.116521] arch_timer: Enabling local workaround for ARM erratum 858921
5965 11:11:07.560790 <6>[ 0.116528] arch_timer: CPU7: Trapping CNTVCT access
5966 11:11:07.567143 <6>[ 0.116533] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5967 11:11:07.570883 <6>[ 0.116581] smp: Brought up 1 node, 8 CPUs
5968 11:11:07.577327 <6>[ 0.355500] SMP: Total of 8 processors activated.
5969 11:11:07.583604 <6>[ 0.360436] CPU features: detected: 32-bit EL0 Support
5970 11:11:07.587197 <6>[ 0.365814] CPU features: detected: 32-bit EL1 Support
5971 11:11:07.593784 <6>[ 0.371182] CPU features: detected: CRC32 instructions
5972 11:11:07.597437 <6>[ 0.376607] CPU: All CPU(s) started at EL2
5973 11:11:07.603560 <6>[ 0.380945] alternatives: applying system-wide alternatives
5974 11:11:07.610784 <6>[ 0.389007] devtmpfs: initialized
5975 11:11:07.622881 <6>[ 0.397926] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5976 11:11:07.633238 <6>[ 0.407876] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5977 11:11:07.636592 <6>[ 0.415598] pinctrl core: initialized pinctrl subsystem
5978 11:11:07.644922 <6>[ 0.422712] DMI not present or invalid.
5979 11:11:07.651666 <6>[ 0.427083] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5980 11:11:07.658471 <6>[ 0.433981] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5981 11:11:07.667903 <6>[ 0.441508] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5982 11:11:07.674496 <6>[ 0.449761] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5983 11:11:07.681391 <6>[ 0.457936] audit: initializing netlink subsys (disabled)
5984 11:11:07.688218 <5>[ 0.463640] audit: type=2000 audit(0.332:1): state=initialized audit_enabled=0 res=1
5985 11:11:07.694195 <6>[ 0.464623] thermal_sys: Registered thermal governor 'step_wise'
5986 11:11:07.700769 <6>[ 0.471606] thermal_sys: Registered thermal governor 'power_allocator'
5987 11:11:07.704380 <6>[ 0.477907] cpuidle: using governor menu
5988 11:11:07.711186 <6>[ 0.488873] NET: Registered PF_QIPCRTR protocol family
5989 11:11:07.717811 <6>[ 0.494359] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5990 11:11:07.724188 <6>[ 0.501457] ASID allocator initialised with 32768 entries
5991 11:11:07.730758 <6>[ 0.508232] Serial: AMBA PL011 UART driver
5992 11:11:07.741205 <4>[ 0.519577] Trying to register duplicate clock ID: 113
5993 11:11:07.801783 <6>[ 0.576283] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5994 11:11:07.815928 <6>[ 0.590686] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5995 11:11:07.819199 <6>[ 0.600457] KASLR enabled
5996 11:11:07.833521 <6>[ 0.608419] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5997 11:11:07.840305 <6>[ 0.615424] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5998 11:11:07.847287 <6>[ 0.621901] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5999 11:11:07.853611 <6>[ 0.628892] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
6000 11:11:07.860334 <6>[ 0.635365] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
6001 11:11:07.867014 <6>[ 0.642355] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
6002 11:11:07.873476 <6>[ 0.648830] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
6003 11:11:07.880001 <6>[ 0.655819] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
6004 11:11:07.883608 <6>[ 0.663385] ACPI: Interpreter disabled.
6005 11:11:07.893584 <6>[ 0.671366] iommu: Default domain type: Translated
6006 11:11:07.899435 <6>[ 0.676475] iommu: DMA domain TLB invalidation policy: strict mode
6007 11:11:07.902950 <5>[ 0.683107] SCSI subsystem initialized
6008 11:11:07.909535 <6>[ 0.687517] usbcore: registered new interface driver usbfs
6009 11:11:07.916649 <6>[ 0.693244] usbcore: registered new interface driver hub
6010 11:11:07.919329 <6>[ 0.698784] usbcore: registered new device driver usb
6011 11:11:07.926714 <6>[ 0.705092] pps_core: LinuxPPS API ver. 1 registered
6012 11:11:07.937321 <6>[ 0.710277] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
6013 11:11:07.940298 <6>[ 0.719602] PTP clock support registered
6014 11:11:07.943609 <6>[ 0.723854] EDAC MC: Ver: 3.0.0
6015 11:11:07.951743 <6>[ 0.729493] FPGA manager framework
6016 11:11:07.958081 <6>[ 0.733177] Advanced Linux Sound Architecture Driver Initialized.
6017 11:11:07.960990 <6>[ 0.739938] vgaarb: loaded
6018 11:11:07.967773 <6>[ 0.743058] clocksource: Switched to clocksource arch_sys_counter
6019 11:11:07.971466 <5>[ 0.749489] VFS: Disk quotas dquot_6.6.0
6020 11:11:07.977807 <6>[ 0.753664] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
6021 11:11:07.981033 <6>[ 0.760837] pnp: PnP ACPI: disabled
6022 11:11:07.989416 <6>[ 0.767706] NET: Registered PF_INET protocol family
6023 11:11:07.996366 <6>[ 0.772930] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
6024 11:11:08.008690 <6>[ 0.782836] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
6025 11:11:08.015146 <6>[ 0.791589] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
6026 11:11:08.024940 <6>[ 0.799541] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
6027 11:11:08.031505 <6>[ 0.807776] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
6028 11:11:08.038298 <6>[ 0.815869] TCP: Hash tables configured (established 32768 bind 32768)
6029 11:11:08.047746 <6>[ 0.822696] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
6030 11:11:08.055259 <6>[ 0.829670] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
6031 11:11:08.061137 <6>[ 0.837149] NET: Registered PF_UNIX/PF_LOCAL protocol family
6032 11:11:08.068081 <6>[ 0.843283] RPC: Registered named UNIX socket transport module.
6033 11:11:08.071461 <6>[ 0.849428] RPC: Registered udp transport module.
6034 11:11:08.077941 <6>[ 0.854354] RPC: Registered tcp transport module.
6035 11:11:08.084917 <6>[ 0.859277] RPC: Registered tcp NFSv4.1 backchannel transport module.
6036 11:11:08.088057 <6>[ 0.865930] PCI: CLS 0 bytes, default 64
6037 11:11:08.091105 <6>[ 0.870217] Unpacking initramfs...
6038 11:11:08.100947 <6>[ 0.873988] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
6039 11:11:08.107507 <6>[ 0.882617] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
6040 11:11:08.114001 <6>[ 0.891475] kvm [1]: IPA Size Limit: 40 bits
6041 11:11:08.117360 <6>[ 0.897793] kvm [1]: vgic-v2@c420000
6042 11:11:08.124355 <6>[ 0.901610] kvm [1]: GIC system register CPU interface enabled
6043 11:11:08.127347 <6>[ 0.907784] kvm [1]: vgic interrupt IRQ18
6044 11:11:08.133936 <6>[ 0.912148] kvm [1]: Hyp mode initialized successfully
6045 11:11:08.141074 <5>[ 0.918405] Initialise system trusted keyrings
6046 11:11:08.147539 <6>[ 0.923235] workingset: timestamp_bits=42 max_order=20 bucket_order=0
6047 11:11:08.155022 <6>[ 0.933172] squashfs: version 4.0 (2009/01/31) Phillip Lougher
6048 11:11:08.161457 <5>[ 0.939696] NFS: Registering the id_resolver key type
6049 11:11:08.165372 <5>[ 0.945015] Key type id_resolver registered
6050 11:11:08.171422 <5>[ 0.949430] Key type id_legacy registered
6051 11:11:08.178286 <6>[ 0.953738] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
6052 11:11:08.185161 <6>[ 0.960664] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
6053 11:11:08.191740 <6>[ 0.968441] 9p: Installing v9fs 9p2000 file system support
6054 11:11:08.219575 <5>[ 0.997397] Key type asymmetric registered
6055 11:11:08.222591 <5>[ 1.001741] Asymmetric key parser 'x509' registered
6056 11:11:08.232302 <6>[ 1.006895] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
6057 11:11:08.235557 <6>[ 1.014512] io scheduler mq-deadline registered
6058 11:11:08.239483 <6>[ 1.019268] io scheduler kyber registered
6059 11:11:08.261970 <6>[ 1.040108] EINJ: ACPI disabled.
6060 11:11:08.268665 <4>[ 1.043898] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
6061 11:11:08.306924 <6>[ 1.084888] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
6062 11:11:08.315508 <6>[ 1.093429] printk: console [ttyS0] disabled
6063 11:11:08.343706 <6>[ 1.118083] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
6064 11:11:08.350327 <6>[ 1.127571] printk: console [ttyS0] enabled
6065 11:11:08.353633 <6>[ 1.127571] printk: console [ttyS0] enabled
6066 11:11:08.359886 <6>[ 1.136488] printk: bootconsole [mtk8250] disabled
6067 11:11:08.363699 <6>[ 1.136488] printk: bootconsole [mtk8250] disabled
6068 11:11:08.373379 <3>[ 1.147018] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
6069 11:11:08.379619 <3>[ 1.155401] mt6577-uart 11003000.serial: Error applying setting, reverse things back
6070 11:11:08.409337 <6>[ 1.183811] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
6071 11:11:08.416078 <6>[ 1.193466] serial serial0: tty port ttyS1 registered
6072 11:11:08.422820 <6>[ 1.200062] SuperH (H)SCI(F) driver initialized
6073 11:11:08.425881 <6>[ 1.205548] msm_serial: driver initialized
6074 11:11:08.441228 <6>[ 1.215905] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
6075 11:11:08.451122 <6>[ 1.224504] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
6076 11:11:08.458105 <6>[ 1.233079] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
6077 11:11:08.467655 <6>[ 1.241647] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
6078 11:11:08.474318 <6>[ 1.250299] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
6079 11:11:08.484448 <6>[ 1.258960] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
6080 11:11:08.494145 <6>[ 1.267701] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
6081 11:11:08.501335 <6>[ 1.276441] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
6082 11:11:08.511382 <6>[ 1.285008] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
6083 11:11:08.521056 <6>[ 1.293809] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
6084 11:11:08.528338 <4>[ 1.306263] cacheinfo: Unable to detect cache hierarchy for CPU 0
6085 11:11:08.537409 <6>[ 1.315597] loop: module loaded
6086 11:11:08.549669 <6>[ 1.327543] vsim1: Bringing 1800000uV into 2700000-2700000uV
6087 11:11:08.567356 <6>[ 1.345493] megasas: 07.719.03.00-rc1
6088 11:11:08.576037 <6>[ 1.354301] spi-nor spi1.0: w25q64dw (8192 Kbytes)
6089 11:11:08.588309 <6>[ 1.366437] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
6090 11:11:08.605756 <6>[ 1.383330] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
6091 11:11:08.662372 <6>[ 1.433878] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1d
6092 11:11:09.417963 <6>[ 2.196012] Freeing initrd memory: 40212K
6093 11:11:09.433396 <4>[ 2.207896] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
6094 11:11:09.440015 <4>[ 2.217146] CPU: 5 PID: 1 Comm: swapper/0 Not tainted 6.1.96-cip24 #1
6095 11:11:09.446847 <4>[ 2.223845] Hardware name: Google juniper sku16 board (DT)
6096 11:11:09.450048 <4>[ 2.229584] Call trace:
6097 11:11:09.453382 <4>[ 2.232284] dump_backtrace.part.0+0xe0/0xf0
6098 11:11:09.456379 <4>[ 2.236821] show_stack+0x18/0x30
6099 11:11:09.459916 <4>[ 2.240395] dump_stack_lvl+0x64/0x80
6100 11:11:09.463624 <4>[ 2.244315] dump_stack+0x18/0x34
6101 11:11:09.469638 <4>[ 2.247883] sysfs_warn_dup+0x64/0x80
6102 11:11:09.472988 <4>[ 2.251805] sysfs_do_create_link_sd+0xf0/0x100
6103 11:11:09.476550 <4>[ 2.256592] sysfs_create_link+0x20/0x40
6104 11:11:09.483159 <4>[ 2.260771] bus_add_device+0x64/0x120
6105 11:11:09.486977 <4>[ 2.264777] device_add+0x354/0x7ec
6106 11:11:09.489954 <4>[ 2.268522] of_device_add+0x44/0x60
6107 11:11:09.496658 <4>[ 2.272356] of_platform_device_create_pdata+0x90/0x124
6108 11:11:09.499661 <4>[ 2.277838] of_platform_bus_create+0x154/0x380
6109 11:11:09.502889 <4>[ 2.282624] of_platform_populate+0x50/0xfc
6110 11:11:09.509461 <4>[ 2.287063] parse_mtd_partitions+0x1d8/0x4e0
6111 11:11:09.513195 <4>[ 2.291679] mtd_device_parse_register+0xec/0x2e0
6112 11:11:09.516504 <4>[ 2.296640] spi_nor_probe+0x280/0x2f4
6113 11:11:09.522993 <4>[ 2.300646] spi_mem_probe+0x6c/0xc0
6114 11:11:09.525802 <4>[ 2.304477] spi_probe+0x84/0xe4
6115 11:11:09.529641 <4>[ 2.307962] really_probe+0xbc/0x2dc
6116 11:11:09.532733 <4>[ 2.311792] __driver_probe_device+0x78/0x114
6117 11:11:09.539320 <4>[ 2.316403] driver_probe_device+0xd8/0x15c
6118 11:11:09.542705 <4>[ 2.320840] __device_attach_driver+0xb8/0x134
6119 11:11:09.545927 <4>[ 2.325538] bus_for_each_drv+0x7c/0xd4
6120 11:11:09.548888 <4>[ 2.329631] __device_attach+0x9c/0x1a0
6121 11:11:09.555456 <4>[ 2.333721] device_initial_probe+0x14/0x20
6122 11:11:09.558999 <4>[ 2.338158] bus_probe_device+0x98/0xa0
6123 11:11:09.562247 <4>[ 2.342249] device_add+0x3c0/0x7ec
6124 11:11:09.565457 <4>[ 2.345994] __spi_add_device+0x78/0x120
6125 11:11:09.568895 <4>[ 2.350171] spi_add_device+0x44/0x80
6126 11:11:09.576021 <4>[ 2.354087] spi_register_controller+0x704/0xb20
6127 11:11:09.578977 <4>[ 2.358960] devm_spi_register_controller+0x4c/0xac
6128 11:11:09.585830 <4>[ 2.364094] mtk_spi_probe+0x4f4/0x684
6129 11:11:09.588992 <4>[ 2.368097] platform_probe+0x68/0xc0
6130 11:11:09.592322 <4>[ 2.372015] really_probe+0xbc/0x2dc
6131 11:11:09.595899 <4>[ 2.375844] __driver_probe_device+0x78/0x114
6132 11:11:09.602834 <4>[ 2.380455] driver_probe_device+0xd8/0x15c
6133 11:11:09.606141 <4>[ 2.384892] __driver_attach+0x94/0x19c
6134 11:11:09.609107 <4>[ 2.388982] bus_for_each_dev+0x74/0xd0
6135 11:11:09.612393 <4>[ 2.393074] driver_attach+0x24/0x30
6136 11:11:09.615953 <4>[ 2.396903] bus_add_driver+0x154/0x20c
6137 11:11:09.622858 <4>[ 2.400993] driver_register+0x78/0x130
6138 11:11:09.626109 <4>[ 2.405083] __platform_driver_register+0x28/0x34
6139 11:11:09.629458 <4>[ 2.410042] mtk_spi_driver_init+0x1c/0x28
6140 11:11:09.635765 <4>[ 2.414398] do_one_initcall+0x64/0x1dc
6141 11:11:09.639213 <4>[ 2.418488] kernel_init_freeable+0x218/0x284
6142 11:11:09.642307 <4>[ 2.423103] kernel_init+0x24/0x12c
6143 11:11:09.645495 <4>[ 2.426848] ret_from_fork+0x10/0x20
6144 11:11:09.657229 <6>[ 2.435770] tun: Universal TUN/TAP device driver, 1.6
6145 11:11:09.660444 <6>[ 2.442071] thunder_xcv, ver 1.0
6146 11:11:09.663885 <6>[ 2.445587] thunder_bgx, ver 1.0
6147 11:11:09.667313 <6>[ 2.449089] nicpf, ver 1.0
6148 11:11:09.678304 <6>[ 2.453459] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
6149 11:11:09.681514 <6>[ 2.460943] hns3: Copyright (c) 2017 Huawei Corporation.
6150 11:11:09.685056 <6>[ 2.466540] hclge is initializing
6151 11:11:09.691623 <6>[ 2.470131] e1000: Intel(R) PRO/1000 Network Driver
6152 11:11:09.698128 <6>[ 2.475267] e1000: Copyright (c) 1999-2006 Intel Corporation.
6153 11:11:09.701583 <6>[ 2.481290] e1000e: Intel(R) PRO/1000 Network Driver
6154 11:11:09.708141 <6>[ 2.486510] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
6155 11:11:09.715003 <6>[ 2.492703] igb: Intel(R) Gigabit Ethernet Network Driver
6156 11:11:09.722127 <6>[ 2.498359] igb: Copyright (c) 2007-2014 Intel Corporation.
6157 11:11:09.728658 <6>[ 2.504203] igbvf: Intel(R) Gigabit Virtual Function Network Driver
6158 11:11:09.735445 <6>[ 2.510725] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
6159 11:11:09.738767 <6>[ 2.517285] sky2: driver version 1.30
6160 11:11:09.745336 <6>[ 2.522543] usbcore: registered new device driver r8152-cfgselector
6161 11:11:09.751696 <6>[ 2.529086] usbcore: registered new interface driver r8152
6162 11:11:09.758354 <6>[ 2.534919] VFIO - User Level meta-driver version: 0.3
6163 11:11:09.765559 <6>[ 2.542710] mtu3 11201000.usb: uwk - reg:0x420, version:101
6164 11:11:09.772174 <4>[ 2.548583] mtu3 11201000.usb: supply vbus not found, using dummy regulator
6165 11:11:09.778149 <6>[ 2.555864] mtu3 11201000.usb: dr_mode: 1, drd: auto
6166 11:11:09.785467 <6>[ 2.561090] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
6167 11:11:09.788879 <6>[ 2.567272] mtu3 11201000.usb: usb3-drd: 0
6168 11:11:09.795084 <6>[ 2.572818] mtu3 11201000.usb: xHCI platform device register success...
6169 11:11:09.806650 <4>[ 2.581500] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
6170 11:11:09.813382 <6>[ 2.589444] xhci-mtk 11200000.usb: xHCI Host Controller
6171 11:11:09.820287 <6>[ 2.594972] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
6172 11:11:09.826614 <6>[ 2.602693] xhci-mtk 11200000.usb: USB3 root hub has no ports
6173 11:11:09.836641 <6>[ 2.608704] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
6174 11:11:09.840008 <6>[ 2.618127] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
6175 11:11:09.846751 <6>[ 2.624203] xhci-mtk 11200000.usb: xHCI Host Controller
6176 11:11:09.852893 <6>[ 2.629691] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
6177 11:11:09.859668 <6>[ 2.637349] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6178 11:11:09.866265 <6>[ 2.644163] hub 1-0:1.0: USB hub found
6179 11:11:09.869530 <6>[ 2.648194] hub 1-0:1.0: 1 port detected
6180 11:11:09.879641 <6>[ 2.653524] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6181 11:11:09.883089 <6>[ 2.662138] hub 2-0:1.0: USB hub found
6182 11:11:09.889432 <3>[ 2.666166] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6183 11:11:09.896485 <6>[ 2.674044] usbcore: registered new interface driver usb-storage
6184 11:11:09.902752 <6>[ 2.680651] usbcore: registered new device driver onboard-usb-hub
6185 11:11:09.920686 <4>[ 2.695167] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6186 11:11:09.929729 <6>[ 2.707490] mt6397-rtc mt6358-rtc: registered as rtc0
6187 11:11:09.939341 <6>[ 2.712977] mt6397-rtc mt6358-rtc: setting system clock to 2024-07-10T11:11:04 UTC (1720609864)
6188 11:11:09.942555 <6>[ 2.722868] i2c_dev: i2c /dev entries driver
6189 11:11:09.954610 <6>[ 2.729295] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6190 11:11:09.964530 <6>[ 2.737617] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6191 11:11:09.967827 <6>[ 2.746520] i2c 4-0058: Fixed dependency cycle(s) with /panel
6192 11:11:09.977605 <6>[ 2.752553] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6193 11:11:09.993974 <6>[ 2.772008] cpu cpu0: EM: created perf domain
6194 11:11:10.007145 <6>[ 2.777532] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6195 11:11:10.010025 <6>[ 2.788814] cpu cpu4: EM: created perf domain
6196 11:11:10.017882 <6>[ 2.795542] sdhci: Secure Digital Host Controller Interface driver
6197 11:11:10.024600 <6>[ 2.801997] sdhci: Copyright(c) Pierre Ossman
6198 11:11:10.031056 <6>[ 2.807380] Synopsys Designware Multimedia Card Interface Driver
6199 11:11:10.037545 <6>[ 2.807882] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6200 11:11:10.040414 <6>[ 2.814475] sdhci-pltfm: SDHCI platform and OF driver helper
6201 11:11:10.049177 <6>[ 2.827124] ledtrig-cpu: registered to indicate activity on CPUs
6202 11:11:10.056774 <6>[ 2.834850] usbcore: registered new interface driver usbhid
6203 11:11:10.060143 <6>[ 2.840693] usbhid: USB HID core driver
6204 11:11:10.070625 <6>[ 2.844975] spi_master spi2: will run message pump with realtime priority
6205 11:11:10.077678 <4>[ 2.845001] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6206 11:11:10.084451 <4>[ 2.859269] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6207 11:11:10.097814 <6>[ 2.864571] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6208 11:11:10.114616 <6>[ 2.882615] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6209 11:11:10.121134 <4>[ 2.891312] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6210 11:11:10.127931 <6>[ 2.903897] cros-ec-spi spi2.0: Chrome EC device registered
6211 11:11:10.134918 <4>[ 2.910558] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6212 11:11:10.147773 <4>[ 2.922296] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6213 11:11:10.154080 <4>[ 2.931119] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6214 11:11:10.166592 <6>[ 2.941211] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6215 11:11:10.182542 <6>[ 2.960591] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x13014
6216 11:11:10.190012 <6>[ 2.968294] mmc0: new HS400 MMC card at address 0001
6217 11:11:10.197204 <6>[ 2.974859] mmcblk0: mmc0:0001 DA4032 29.1 GiB
6218 11:11:10.209471 <6>[ 2.987552] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6219 11:11:10.220791 <6>[ 2.998317] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB
6220 11:11:10.227593 <6>[ 3.005325] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB
6221 11:11:10.237183 <6>[ 3.007471] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6222 11:11:10.247685 <6>[ 3.011518] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6223 11:11:10.257146 <6>[ 3.031685] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6224 11:11:10.263991 <6>[ 3.031751] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0)
6225 11:11:10.276986 <6>[ 3.035272] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6226 11:11:10.280354 <6>[ 3.037157] NET: Registered PF_PACKET protocol family
6227 11:11:10.287424 <6>[ 3.037300] 9pnet: Installing 9P2000 support
6228 11:11:10.290274 <5>[ 3.037359] Key type dns_resolver registered
6229 11:11:10.293828 <6>[ 3.041795] registered taskstats version 1
6230 11:11:10.300364 <5>[ 3.077848] Loading compiled-in X.509 certificates
6231 11:11:10.307041 <6>[ 3.079277] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6232 11:11:10.360845 <3>[ 3.135471] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6233 11:11:10.390490 <6>[ 3.161797] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6234 11:11:10.401217 <6>[ 3.175477] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6235 11:11:10.411436 <6>[ 3.184046] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6236 11:11:10.417918 <6>[ 3.192573] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6237 11:11:10.427515 <6>[ 3.201095] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6238 11:11:10.434116 <6>[ 3.209618] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6239 11:11:10.443941 <6>[ 3.218139] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6240 11:11:10.450617 <6>[ 3.226657] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6241 11:11:10.458130 <6>[ 3.235856] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6242 11:11:10.465155 <6>[ 3.243245] hub 1-1:1.0: USB hub found
6243 11:11:10.471971 <6>[ 3.243407] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6244 11:11:10.475387 <6>[ 3.247868] hub 1-1:1.0: 3 ports detected
6245 11:11:10.481761 <6>[ 3.254591] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6246 11:11:10.488801 <6>[ 3.265403] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6247 11:11:10.498462 <6>[ 3.272934] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6248 11:11:10.505166 <6>[ 3.281363] panfrost 13040000.gpu: clock rate = 511999970
6249 11:11:10.514389 <6>[ 3.287066] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6250 11:11:10.521533 <6>[ 3.297085] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6251 11:11:10.531087 <6>[ 3.305092] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6252 11:11:10.541105 <6>[ 3.313525] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6253 11:11:10.548050 <6>[ 3.325602] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6254 11:11:10.562347 <6>[ 3.336529] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6255 11:11:10.571697 <6>[ 3.345444] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6256 11:11:10.581908 <6>[ 3.354594] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6257 11:11:10.588674 <6>[ 3.363724] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6258 11:11:10.598559 <6>[ 3.372852] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6259 11:11:10.608751 <6>[ 3.382155] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6260 11:11:10.618518 <6>[ 3.391455] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6261 11:11:10.628822 <6>[ 3.400931] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6262 11:11:10.635159 <6>[ 3.410410] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6263 11:11:10.644673 <6>[ 3.419537] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6264 11:11:10.717580 <6>[ 3.492336] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6265 11:11:10.727252 <6>[ 3.501203] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6266 11:11:10.738430 <6>[ 3.513364] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6267 11:11:10.772345 <6>[ 3.547079] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6268 11:11:11.446851 <6>[ 3.739743] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6269 11:11:11.456943 <4>[ 3.856356] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6270 11:11:11.463759 <4>[ 3.856373] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6271 11:11:11.470784 <6>[ 3.909299] r8152 1-1.2:1.0 eth0: v1.12.13
6272 11:11:11.477161 <6>[ 3.987111] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6273 11:11:11.483701 <6>[ 4.205327] Console: switching to colour frame buffer device 170x48
6274 11:11:11.489985 <6>[ 4.265841] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6275 11:11:11.511167 <6>[ 4.282052] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6276 11:11:11.527857 <6>[ 4.299020] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6277 11:11:11.534647 <6>[ 4.311432] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6278 11:11:11.545464 <6>[ 4.319873] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6279 11:11:11.555270 <6>[ 4.326850] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6280 11:11:11.574692 <6>[ 4.346202] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6281 11:11:12.735601 <6>[ 5.513217] r8152 1-1.2:1.0 eth0: carrier on
6282 11:11:15.745461 <5>[ 5.539073] Sending DHCP requests .., OK
6283 11:11:15.751920 <6>[ 8.527555] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.13
6284 11:11:15.754946 <6>[ 8.535993] IP-Config: Complete:
6285 11:11:15.768416 <6>[ 8.539559] device=eth0, hwaddr=00:e0:4c:68:0b:b9, ipaddr=192.168.201.13, mask=255.255.255.0, gw=192.168.201.1
6286 11:11:15.778394 <6>[ 8.550456] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-0, domain=lava-rack, nis-domain=(none)
6287 11:11:15.789777 <6>[ 8.564827] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6288 11:11:15.798775 <6>[ 8.564837] nameserver0=192.168.201.1
6289 11:11:15.807144 <6>[ 8.584721] clk: Disabling unused clocks
6290 11:11:15.811709 <6>[ 8.592745] ALSA device list:
6291 11:11:15.820963 <6>[ 8.598656] No soundcards found.
6292 11:11:15.829640 <6>[ 8.607661] Freeing unused kernel memory: 8512K
6293 11:11:15.836984 <6>[ 8.614828] Run /init as init process
6294 11:11:15.866143 <6>[ 8.644224] NET: Registered PF_INET6 protocol family
6295 11:11:15.873160 <6>[ 8.651281] Segment Routing with IPv6
6296 11:11:15.876567 <6>[ 8.655909] In-situ OAM (IOAM) with IPv6
6297 11:11:15.923302 <30>[ 8.674772] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6298 11:11:15.932165 <30>[ 8.710006] systemd[1]: Detected architecture arm64.
6299 11:11:15.932798
6300 11:11:15.938498 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6301 11:11:15.938995
6302 11:11:15.957737 <30>[ 8.735505] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6303 11:11:16.105353 <30>[ 8.879881] systemd[1]: Queued start job for default target graphical.target.
6304 11:11:16.130147 <30>[ 8.904797] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6305 11:11:16.139976 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6306 11:11:16.157350 <30>[ 8.932060] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6307 11:11:16.167615 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6308 11:11:16.190105 <30>[ 8.964582] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6309 11:11:16.201177 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6310 11:11:16.221604 <30>[ 8.995910] systemd[1]: Created slice user.slice - User and Session Slice.
6311 11:11:16.230882 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6312 11:11:16.252390 <30>[ 9.023609] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6313 11:11:16.263859 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6314 11:11:16.284280 <30>[ 9.055490] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6315 11:11:16.295752 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6316 11:11:16.322588 <30>[ 9.087384] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6317 11:11:16.340411 <30>[ 9.114758] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6318 11:11:16.347444 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6319 11:11:16.364557 <30>[ 9.139272] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6320 11:11:16.377384 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6321 11:11:16.393089 <30>[ 9.167300] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6322 11:11:16.407244 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6323 11:11:16.421374 <30>[ 9.199340] systemd[1]: Reached target paths.target - Path Units.
6324 11:11:16.436090 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6325 11:11:16.452398 <30>[ 9.227279] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6326 11:11:16.465115 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6327 11:11:16.477386 <30>[ 9.255225] systemd[1]: Reached target slices.target - Slice Units.
6328 11:11:16.491877 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6329 11:11:16.505397 <30>[ 9.283287] systemd[1]: Reached target swap.target - Swaps.
6330 11:11:16.515802 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6331 11:11:16.537108 <30>[ 9.311315] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6332 11:11:16.550611 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6333 11:11:16.569008 <30>[ 9.343669] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6334 11:11:16.582843 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6335 11:11:16.602206 <30>[ 9.376988] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6336 11:11:16.615611 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6337 11:11:16.632872 <30>[ 9.408019] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6338 11:11:16.647100 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6339 11:11:16.665021 <30>[ 9.439910] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6340 11:11:16.677397 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6341 11:11:16.697097 <30>[ 9.472072] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6342 11:11:16.710342 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6343 11:11:16.728961 <30>[ 9.503965] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6344 11:11:16.742164 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6345 11:11:16.760449 <30>[ 9.535730] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6346 11:11:16.773604 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6347 11:11:16.816502 <30>[ 9.591517] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6348 11:11:16.829532 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6349 11:11:16.853720 <30>[ 9.628631] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6350 11:11:16.864735 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6351 11:11:16.889885 <30>[ 9.664833] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6352 11:11:16.900942 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6353 11:11:16.927672 <30>[ 9.695987] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6354 11:11:16.964600 <30>[ 9.739750] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6355 11:11:16.977595 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6356 11:11:17.002114 <30>[ 9.777161] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6357 11:11:17.013626 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6358 11:11:17.056906 <30>[ 9.831849] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6359 11:11:17.072180 Starting [0;1;39mmodprobe@dm_mod.s…[<6>[ 9.846708] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6360 11:11:17.075365 0m - Load Kernel Module dm_mod...
6361 11:11:17.102269 <30>[ 9.877503] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6362 11:11:17.113642 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
6363 11:11:17.138576 <30>[ 9.913375] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6364 11:11:17.150480 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6365 11:11:17.200921 <30>[ 9.975714] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6366 11:11:17.212872 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6367 11:11:17.239125 <30>[ 10.013688] systemd[1]: Starting systemd-journald.service - Journal Service...
6368 11:11:17.249287 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6369 11:11:17.267792 <30>[ 10.043025] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6370 11:11:17.277538 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6371 11:11:17.304121 <30>[ 10.075615] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6372 11:11:17.314775 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6373 11:11:17.337453 <30>[ 10.111672] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6374 11:11:17.349639 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6375 11:11:17.388950 <30>[ 10.163883] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6376 11:11:17.400328 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6377 11:11:17.420653 <30>[ 10.195374] systemd[1]: Started systemd-journald.service - Journal Service.
6378 11:11:17.431031 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6379 11:11:17.450288 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
6380 11:11:17.469403 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
6381 11:11:17.489491 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
6382 11:11:17.506163 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6383 11:11:17.525990 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6384 11:11:17.550124 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6385 11:11:17.573478 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6386 11:11:17.597700 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6387 11:11:17.619994 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6388 11:11:17.637441 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6389 11:11:17.657896 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6390 11:11:17.681635 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6391 11:11:17.741777 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6392 11:11:17.772124 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
6393 11:11:17.795157 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
6394 11:11:17.810805 See 'systemctl status systemd-remount-fs.service' for details.
6395 11:11:17.835432 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6396 11:11:17.854965 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6397 11:11:17.874282 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6398 11:11:17.915191 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6399 11:11:17.937123 <46>[ 10.711048] systemd-journald[197]: Received client request to flush runtime journal.
6400 11:11:17.950720 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6401 11:11:17.975297 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6402 11:11:18.001514 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6403 11:11:18.023505 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6404 11:11:18.043296 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6405 11:11:18.086426 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6406 11:11:18.116157 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6407 11:11:18.137887 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6408 11:11:18.156653 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6409 11:11:18.197257 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6410 11:11:18.220611 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6411 11:11:18.241791 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6412 11:11:18.305215 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6413 11:11:18.327681 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6414 11:11:18.345398 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6415 11:11:18.383958 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6416 11:11:18.406186 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6417 11:11:18.421290 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6418 11:11:18.524126 <3>[ 11.302272] mtk-scp 10500000.scp: invalid resource
6419 11:11:18.533986 <6>[ 11.308182] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6420 11:11:18.537394 <3>[ 11.316102] thermal_sys: Failed to find 'trips' node
6421 11:11:18.543947 <6>[ 11.317985] remoteproc remoteproc0: scp is available
6422 11:11:18.554407 <3>[ 11.318132] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6423 11:11:18.560854 <3>[ 11.318140] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6424 11:11:18.574048 <3>[ 11.318145] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6425 11:11:18.580791 <3>[ 11.318150] elan_i2c 2-0015: Error applying setting, reverse things back
6426 11:11:18.587477 <3>[ 11.328866] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6427 11:11:18.594230 <4>[ 11.338028] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6428 11:11:18.604138 <6>[ 11.338757] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6429 11:11:18.610818 <3>[ 11.344639] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6430 11:11:18.617672 <6>[ 11.355595] remoteproc remoteproc0: powering up scp
6431 11:11:18.624204 <4>[ 11.362540] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6432 11:11:18.634120 <4>[ 11.369866] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6433 11:11:18.640589 <6>[ 11.379276] mc: Linux media interface: v0.10
6434 11:11:18.643888 <3>[ 11.379636] thermal_sys: Failed to find 'trips' node
6435 11:11:18.651235 <3>[ 11.379640] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6436 11:11:18.660558 <3>[ 11.379648] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6437 11:11:18.667459 <4>[ 11.379650] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6438 11:11:18.673757 <4>[ 11.380981] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6439 11:11:18.683481 <4>[ 11.381123] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6440 11:11:18.693873 <4>[ 11.381989] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6441 11:11:18.703686 <6>[ 11.383382] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6442 11:11:18.710030 <3>[ 11.386366] remoteproc remoteproc0: request_firmware failed: -2
6443 11:11:18.720035 <6>[ 11.386601] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6444 11:11:18.729567 <6>[ 11.386709] cs_system_cfg: CoreSight Configuration manager initialised
6445 11:11:18.743078 <3>[ 11.387190] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6446 11:11:18.749867 <6>[ 11.390779] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6447 11:11:18.757210 <5>[ 11.396139] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6448 11:11:18.767324 <6>[ 11.400334] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6449 11:11:18.773519 <5>[ 11.419423] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6450 11:11:18.780459 <6>[ 11.423360] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6451 11:11:18.790342 <3>[ 11.424811] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6452 11:11:18.800034 <3>[ 11.424840] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6453 11:11:18.806750 <3>[ 11.424848] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6454 11:11:18.816673 <3>[ 11.424970] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6455 11:11:18.823011 <3>[ 11.424979] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6456 11:11:18.833072 <3>[ 11.424987] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6457 11:11:18.843013 <3>[ 11.424996] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6458 11:11:18.849898 <3>[ 11.425004] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6459 11:11:18.860167 <3>[ 11.425051] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6460 11:11:18.867086 <5>[ 11.428295] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6461 11:11:18.873784 <6>[ 11.435434] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6462 11:11:18.884084 <4>[ 11.443572] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6463 11:11:18.894155 <6>[ 11.451219] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6464 11:11:18.900757 <6>[ 11.458406] cfg80211: failed to load regulatory.db
6465 11:11:18.907265 <6>[ 11.465904] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6466 11:11:18.917188 <6>[ 11.519893] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6467 11:11:18.927018 <6>[ 11.525118] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6468 11:11:18.933426 <6>[ 11.541889] videodev: Linux video capture interface: v2.00
6469 11:11:18.940164 <6>[ 11.549899] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6470 11:11:18.953720 <3>[ 11.556279] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6471 11:11:18.957130 <6>[ 11.557614] Bluetooth: Core ver 2.22
6472 11:11:18.964534 <6>[ 11.557670] NET: Registered PF_BLUETOOTH protocol family
6473 11:11:18.970941 <6>[ 11.557674] Bluetooth: HCI device and connection manager initialized
6474 11:11:18.977761 <6>[ 11.557690] Bluetooth: HCI socket layer initialized
6475 11:11:18.985621 <6>[ 11.557696] Bluetooth: L2CAP socket layer initialized
6476 11:11:18.988610 <6>[ 11.557713] Bluetooth: SCO socket layer initialized
6477 11:11:18.995486 <6>[ 11.572477] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6478 11:11:19.002800 <3>[ 11.574524] debugfs: File 'Playback' in directory 'dapm' already present!
6479 11:11:19.009650 <6>[ 11.591900] Bluetooth: HCI UART driver ver 2.3
6480 11:11:19.016249 <6>[ 11.591980] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6481 11:11:19.022354 <3>[ 11.599595] debugfs: File 'Capture' in directory 'dapm' already present!
6482 11:11:19.034554 <6>[ 11.600420] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6483 11:11:19.049306 <6>[ 11.600856] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6
6484 11:11:19.057731 <6>[ 11.608303] Bluetooth: HCI UART protocol H4 registered
6485 11:11:19.066090 <6>[ 11.616784] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6486 11:11:19.078379 <6>[ 11.618014] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video0
6487 11:11:19.091801 <6>[ 11.625106] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6488 11:11:19.098753 <6>[ 11.625227] Bluetooth: HCI UART protocol LL registered
6489 11:11:19.106047 <6>[ 11.625233] usbcore: registered new interface driver uvcvideo
6490 11:11:19.117452 <6>[ 11.634122] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video3 (81,3)
6491 11:11:19.127921 <6>[ 11.640793] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6492 11:11:19.139900 <6>[ 11.640803] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6493 11:11:19.153355 <6>[ 11.641121] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6494 11:11:19.160309 <6>[ 11.642275] Bluetooth: HCI UART protocol Three-wire (H5) registered
6495 11:11:19.172282 <4>[ 11.757476] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6496 11:11:19.178797 <4>[ 11.757476] Fallback method does not support PEC.
6497 11:11:19.185121 <6>[ 11.761626] Bluetooth: HCI UART protocol Broadcom registered
6498 11:11:19.194772 <3>[ 11.769181] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6499 11:11:19.201384 <6>[ 11.771807] Bluetooth: HCI UART protocol QCA registered
6500 11:11:19.208634 <6>[ 11.773001] Bluetooth: hci0: setting up ROME/QCA6390
6501 11:11:19.219042 <3>[ 11.786207] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6502 11:11:19.228016 <6>[ 11.786812] Bluetooth: HCI UART protocol Marvell registered
6503 11:11:19.241343 <6>[ 11.791556] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6504 11:11:19.250264 <3>[ 11.992511] Bluetooth: hci0: Frame reassembly failed (-84)
6505 11:11:19.348032 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/system<3>[ 12.121273] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6506 11:11:19.348153 d-backlight.
6507 11:11:19.355094 <3>[ 12.121765] power_supply sbs-12-000b: driver failed to report `capacity_level' property: -6
6508 11:11:19.365092 <3>[ 12.134879] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6509 11:11:19.391843 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m <3>[ 12.167980] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6510 11:11:19.395057 - System Time Set.
6511 11:11:19.410018 <3>[ 12.184905] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6512 11:11:19.427059 <3>[ 12.201582] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6513 11:11:19.446530 <3>[ 12.220960] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6514 11:11:19.462283 Starting [0;1;39msystemd-backlight…ess of backlight:<3>[ 12.237732] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6515 11:11:19.465516 backlight_lcd0...
6516 11:11:19.486040 <6>[ 12.263674] Bluetooth: hci0: QCA Product ID :0x00000008
6517 11:11:19.493158 <6>[ 12.271143] Bluetooth: hci0: QCA SOC Version :0x00000044
6518 11:11:19.501144 <6>[ 12.278705] Bluetooth: hci0: QCA ROM Version :0x00000302
6519 11:11:19.511146 Starting [0;1;39msyste<6>[ 12.286498] Bluetooth: hci0: QCA Patch Version:0x00000111
6520 11:11:19.517804 md-networkd.…ice[0m - Network<6>[ 12.295443] Bluetooth: hci0: QCA controller version 0x00440302
6521 11:11:19.521269 Configuration...
6522 11:11:19.527507 <6>[ 12.304466] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6523 11:11:19.538146 <4>[ 12.313342] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6524 11:11:19.549638 <3>[ 12.324664] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6525 11:11:19.556134 <3>[ 12.334699] Bluetooth: hci0: QCA Failed to download patch (-2)
6526 11:11:19.567265 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6527 11:11:19.610229 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6528 11:11:19.644350 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6529 11:11:19.655689 <6>[ 12.430459] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6530 11:11:19.666762 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6531 11:11:19.685443 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6532 11:11:19.701641 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6533 11:11:19.718636 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6534 11:11:19.740353 [[0;32m OK [0m] Started [0;1;39msystemd-tmp<4>[ 12.516450] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6535 11:11:19.743749 files-c… Cleanup of Temporary Directories.
6536 11:11:19.750444 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6537 11:11:19.761243 <4>[ 12.536345] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6538 11:11:19.777986 [[0;32m OK [0m] Listening on [0;1;39mdbus.s<4>[ 12.553198] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6539 11:11:19.781386 ocket[…- D-Bus System Message Bus Socket.
6540 11:11:19.791547 [[0;32m OK [<4>[ 12.566869] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6541 11:11:19.794889 0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6542 11:11:19.815260 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6543 11:11:19.835459 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6544 11:11:19.873582 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6545 11:11:19.911484 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6546 11:11:19.938802 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6547 11:11:19.959994 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6548 11:11:19.990210 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6549 11:11:20.048627 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6550 11:11:20.071395 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6551 11:11:20.091824 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6552 11:11:20.132215 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6553 11:11:20.152169 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6554 11:11:20.172349 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6555 11:11:20.193838 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6556 11:11:20.212326 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6557 11:11:20.263351 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6558 11:11:20.302413 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6559 11:11:20.334422
6560 11:11:20.337780 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6561 11:11:20.338539
6562 11:11:20.341091 debian-bookworm-arm64 login: root (automatic login)
6563 11:11:20.342029
6564 11:11:20.358953 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024 aarch64
6565 11:11:20.359674
6566 11:11:20.365444 The programs included with the Debian GNU/Linux system are free software;
6567 11:11:20.372447 the exact distribution terms for each program are described in the
6568 11:11:20.375708 individual files in /usr/share/doc/*/copyright.
6569 11:11:20.376145
6570 11:11:20.382610 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6571 11:11:20.385543 permitted by applicable law.
6572 11:11:20.387149 Matched prompt #10: / #
6574 11:11:20.388161 Setting prompt string to ['/ #']
6575 11:11:20.388710 end: 2.2.5.1 login-action (duration 00:00:14) [common]
6577 11:11:20.389757 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
6578 11:11:20.390216 start: 2.2.6 expect-shell-connection (timeout 00:03:40) [common]
6579 11:11:20.390589 Setting prompt string to ['/ #']
6580 11:11:20.390924 Forcing a shell prompt, looking for ['/ #']
6581 11:11:20.391232 Sending line: ''
6583 11:11:20.442235 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6584 11:11:20.442646 Waiting using forced prompt support (timeout 00:02:30)
6585 11:11:20.447612 / #
6586 11:11:20.448326 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6587 11:11:20.448819 start: 2.2.7 export-device-env (timeout 00:03:40) [common]
6588 11:11:20.449320 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6589 11:11:20.449772 end: 2.2 depthcharge-retry (duration 00:01:20) [common]
6590 11:11:20.450192 end: 2 depthcharge-action (duration 00:01:20) [common]
6591 11:11:20.450654 start: 3 lava-test-retry (timeout 00:08:16) [common]
6592 11:11:20.451115 start: 3.1 lava-test-shell (timeout 00:08:16) [common]
6593 11:11:20.451512 Using namespace: common
6594 11:11:20.451859 Sending line: '#'
6596 11:11:20.553118 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6597 11:11:20.558415 / # #
6598 11:11:20.559111 Using /lava-14786846
6599 11:11:20.559447 Sending line: 'export SHELL=/bin/sh'
6601 11:11:20.666460 / # export SHELL=/bin/sh
6602 11:11:20.667132 Sending line: '. /lava-14786846/environment'
6604 11:11:20.773232 / # . /lava-14786846/environment
6605 11:11:20.774032 Sending line: '/lava-14786846/bin/lava-test-runner /lava-14786846/0'
6607 11:11:20.874834 Test shell timeout: 10s (minimum of the action and connection timeout)
6608 11:11:20.879642 / # /lava-14786846/bin/lava-test-runner /lava-14786846/0
6609 11:11:20.905925 + export TESTRUN_ID=0_v4l2-compliance-uvc
6610 11:11:20.909068 + cd /lava-14786846/0/tests/0_v4l2-compliance-uvc
6611 11:11:20.909172 + cat uuid
6612 11:11:20.912236 + UUID=14786846_1.5.2.3.1
6613 11:11:20.912345 + set +x
6614 11:11:20.918902 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 14786846_1.5.2.3.1>
6615 11:11:20.919160 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 14786846_1.5.2.3.1
6616 11:11:20.919232 Starting test lava.0_v4l2-compliance-uvc (14786846_1.5.2.3.1)
6617 11:11:20.919311 Skipping test definition patterns.
6618 11:11:20.922101 + /usr/bin/v4l2-parser.sh -d uvcvideo
6619 11:11:20.928934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
6620 11:11:20.929041 device: /dev/video1
6621 11:11:20.929313 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
6623 11:11:22.271521 <3>[ 15.049047] uvcvideo 1-1.3:1.1: Failed to resubmit video URB (-1).
6624 11:11:27.814662 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
6625 11:11:27.828574 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
6626 11:11:27.840565
6627 11:11:27.858311 Compliance test for uvcvideo device /dev/video1:
6628 11:11:27.870260
6629 11:11:27.884071 Driver Info:
6630 11:11:27.900207 Driver name : uvcvideo
6631 11:11:27.918514 Card type : HD WebCam: HD WebCam
6632 11:11:27.932606 Bus info : usb-11200000.usb-1.3
6633 11:11:27.944192 Driver version : 6.1.96
6634 11:11:27.958047 Capabilities : 0x84a00001
6635 11:11:27.978079 Metadata Capture
6636 11:11:27.992548 Streaming
6637 11:11:28.005087 Extended Pix Format
6638 11:11:28.021410 Device Capabilities
6639 11:11:28.036193 Device Caps : 0x04200001
6640 11:11:28.056291 Streaming
6641 11:11:28.071844 Extended Pix Format
6642 11:11:28.085342 Media Driver Info:
6643 11:11:28.097711 Driver name : uvcvideo
6644 11:11:28.116490 Model : HD WebCam: HD WebCam
6645 11:11:28.128404 Serial :
6646 11:11:28.147713 Bus info : usb-11200000.usb-1.3
6647 11:11:28.156339 Media version : 6.1.96
6648 11:11:28.173562 Hardware revision: 0x00003269 (12905)
6649 11:11:28.185885 Driver version : 6.1.96
6650 11:11:28.201494 Interface Info:
6651 11:11:28.220076 <LAVA_SIGNAL_TESTSET START Interface-Info>
6652 11:11:28.220761 Received signal: <TESTSET> START Interface-Info
6653 11:11:28.221102 Starting test_set Interface-Info
6654 11:11:28.223437 ID : 0x03000002
6655 11:11:28.235509 Type : V4L Video
6656 11:11:28.249349 Entity Info:
6657 11:11:28.260222 <LAVA_SIGNAL_TESTSET STOP>
6658 11:11:28.260875 Received signal: <TESTSET> STOP
6659 11:11:28.261197 Closing test_set Interface-Info
6660 11:11:28.271873 <LAVA_SIGNAL_TESTSET START Entity-Info>
6661 11:11:28.272524 Received signal: <TESTSET> START Entity-Info
6662 11:11:28.272847 Starting test_set Entity-Info
6663 11:11:28.274832 ID : 0x00000001 (1)
6664 11:11:28.287926 Name : HD WebCam: HD WebCam
6665 11:11:28.297575 Function : V4L2 I/O
6666 11:11:28.310653 Flags : default
6667 11:11:28.324603 Pad 0x01000007 : 0: Sink
6668 11:11:28.349785 Link 0x02000013: from remote pad 0x100000a of entity 'Extension 4' (Video Pixel Formatter): Data, Enabled, Immutable
6669 11:11:28.353405
6670 11:11:28.367918 Required ioctls:
6671 11:11:28.376908 <LAVA_SIGNAL_TESTSET STOP>
6672 11:11:28.377530 Received signal: <TESTSET> STOP
6673 11:11:28.377842 Closing test_set Entity-Info
6674 11:11:28.387571 <LAVA_SIGNAL_TESTSET START Required-ioctls>
6675 11:11:28.388190 Received signal: <TESTSET> START Required-ioctls
6676 11:11:28.388546 Starting test_set Required-ioctls
6677 11:11:28.391021 test MC information (see 'Media Driver Info' above): OK
6678 11:11:28.420404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
6679 11:11:28.421077 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
6681 11:11:28.423686 test VIDIOC_QUERYCAP: OK
6682 11:11:28.447845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
6683 11:11:28.448493 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
6685 11:11:28.451264 test invalid ioctls: OK
6686 11:11:28.476339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
6687 11:11:28.476450
6688 11:11:28.476693 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
6690 11:11:28.490257 Allow for multiple opens:
6691 11:11:28.498770 <LAVA_SIGNAL_TESTSET STOP>
6692 11:11:28.499022 Received signal: <TESTSET> STOP
6693 11:11:28.499091 Closing test_set Required-ioctls
6694 11:11:28.510208 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
6695 11:11:28.510458 Received signal: <TESTSET> START Allow-for-multiple-opens
6696 11:11:28.510527 Starting test_set Allow-for-multiple-opens
6697 11:11:28.513337 test second /dev/video1 open: OK
6698 11:11:28.542000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video1-open RESULT=pass>
6699 11:11:28.542254 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video1-open RESULT=pass
6701 11:11:28.545421 test VIDIOC_QUERYCAP: OK
6702 11:11:28.571460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
6703 11:11:28.571711 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
6705 11:11:28.574793 test VIDIOC_G/S_PRIORITY: OK
6706 11:11:28.602639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
6707 11:11:28.602893 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
6709 11:11:28.605631 test for unlimited opens: OK
6710 11:11:28.630162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
6711 11:11:28.630248
6712 11:11:28.630477 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
6714 11:11:28.644591 Debug ioctls:
6715 11:11:28.653224 <LAVA_SIGNAL_TESTSET STOP>
6716 11:11:28.653473 Received signal: <TESTSET> STOP
6717 11:11:28.653543 Closing test_set Allow-for-multiple-opens
6718 11:11:28.663044 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
6719 11:11:28.663292 Received signal: <TESTSET> START Debug-ioctls
6720 11:11:28.663360 Starting test_set Debug-ioctls
6721 11:11:28.666551 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
6722 11:11:28.692025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
6723 11:11:28.692279 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
6725 11:11:28.698416 test VIDIOC_LOG_STATUS: OK (Not Supported)
6726 11:11:28.721688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
6727 11:11:28.721789
6728 11:11:28.722046 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
6730 11:11:28.736130 Input ioctls:
6731 11:11:28.747291 <LAVA_SIGNAL_TESTSET STOP>
6732 11:11:28.747548 Received signal: <TESTSET> STOP
6733 11:11:28.747632 Closing test_set Debug-ioctls
6734 11:11:28.758254 <LAVA_SIGNAL_TESTSET START Input-ioctls>
6735 11:11:28.758511 Received signal: <TESTSET> START Input-ioctls
6736 11:11:28.758583 Starting test_set Input-ioctls
6737 11:11:28.761788 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
6738 11:11:28.793058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
6739 11:11:28.793400 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
6741 11:11:28.796299 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
6742 11:11:28.821086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
6743 11:11:28.821382 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
6745 11:11:28.827963 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
6746 11:11:28.855129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
6747 11:11:28.855447 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
6749 11:11:28.861325 test VIDIOC_ENUMAUDIO: OK (Not Supported)
6750 11:11:28.886574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
6751 11:11:28.886829 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
6753 11:11:28.889980 test VIDIOC_G/S/ENUMINPUT: OK
6754 11:11:28.918689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
6755 11:11:28.918947 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
6757 11:11:28.925442 test VIDIOC_G/S_AUDIO: OK (Not Supported)
6758 11:11:28.948291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
6759 11:11:28.948544 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
6761 11:11:28.951495 Inputs: 1 Audio Inputs: 0 Tuners: 0
6762 11:11:28.963184
6763 11:11:28.985438 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
6764 11:11:29.013346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
6765 11:11:29.013599 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
6767 11:11:29.019569 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
6768 11:11:29.042718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
6769 11:11:29.042968 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
6771 11:11:29.049392 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
6772 11:11:29.072120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
6773 11:11:29.072372 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
6775 11:11:29.078153 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
6776 11:11:29.102790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
6777 11:11:29.103041 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
6779 11:11:29.109365 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
6780 11:11:29.137643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
6781 11:11:29.137738
6782 11:11:29.137971 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
6784 11:11:29.161299 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
6785 11:11:29.187903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
6786 11:11:29.188347 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
6788 11:11:29.194430 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
6789 11:11:29.222366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
6790 11:11:29.223047 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
6792 11:11:29.226133 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
6793 11:11:29.251814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
6794 11:11:29.252427 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
6796 11:11:29.255557 test VIDIOC_G/S_EDID: OK (Not Supported)
6797 11:11:29.282482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
6798 11:11:29.282877
6799 11:11:29.283402 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
6801 11:11:29.299610 Control ioctls (Input 0):
6802 11:11:29.310333 <LAVA_SIGNAL_TESTSET STOP>
6803 11:11:29.310948 Received signal: <TESTSET> STOP
6804 11:11:29.311264 Closing test_set Input-ioctls
6805 11:11:29.321223 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
6806 11:11:29.321835 Received signal: <TESTSET> START Control-ioctls-Input-0
6807 11:11:29.322149 Starting test_set Control-ioctls-Input-0
6808 11:11:29.323961 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
6809 11:11:29.352715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
6810 11:11:29.353102 test VIDIOC_QUERYCTRL: OK
6811 11:11:29.353629 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
6813 11:11:29.378657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
6814 11:11:29.379275 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
6816 11:11:29.381942 test VIDIOC_G/S_CTRL: OK
6817 11:11:29.406531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
6818 11:11:29.407151 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
6820 11:11:29.409922 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
6821 11:11:29.435076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
6822 11:11:29.435691 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
6824 11:11:29.441639 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
6825 11:11:29.470481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
6826 11:11:29.471147 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
6828 11:11:29.473377 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
6829 11:11:29.498150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
6830 11:11:29.498766 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
6832 11:11:29.501285 Standard Controls: 15 Private Controls: 0
6833 11:11:29.512268
6834 11:11:29.527562 Format ioctls (Input 0):
6835 11:11:29.537735 <LAVA_SIGNAL_TESTSET STOP>
6836 11:11:29.538344 Received signal: <TESTSET> STOP
6837 11:11:29.538648 Closing test_set Control-ioctls-Input-0
6838 11:11:29.547708 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
6839 11:11:29.548399 Received signal: <TESTSET> START Format-ioctls-Input-0
6840 11:11:29.548743 Starting test_set Format-ioctls-Input-0
6841 11:11:29.551140 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
6842 11:11:29.583236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
6843 11:11:29.583527 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
6845 11:11:29.586455 test VIDIOC_G/S_PARM: OK
6846 11:11:29.609442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
6847 11:11:29.609694 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
6849 11:11:29.612738 test VIDIOC_G_FBUF: OK (Not Supported)
6850 11:11:29.639725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
6851 11:11:29.640344 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
6853 11:11:29.642958 test VIDIOC_G_FMT: OK
6854 11:11:29.672941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
6855 11:11:29.673550 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
6857 11:11:29.676076 test VIDIOC_TRY_FMT: OK
6858 11:11:29.703132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
6859 11:11:29.703860 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
6861 11:11:29.709849 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
6862 11:11:29.716186 test VIDIOC_S_FMT: OK
6863 11:11:29.748256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
6864 11:11:29.749032 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
6866 11:11:29.751374 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
6867 11:11:29.788185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
6868 11:11:29.789098 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
6870 11:11:29.791459 test Cropping: OK (Not Supported)
6871 11:11:29.821252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
6872 11:11:29.821930 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
6874 11:11:29.823794 test Composing: OK (Not Supported)
6875 11:11:29.848283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
6876 11:11:29.849041 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
6878 11:11:29.851783 test Scaling: OK (Not Supported)
6879 11:11:29.878910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
6880 11:11:29.879410
6881 11:11:29.880152 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
6883 11:11:29.894747 Codec ioctls (Input 0):
6884 11:11:29.904101 <LAVA_SIGNAL_TESTSET STOP>
6885 11:11:29.904760 Received signal: <TESTSET> STOP
6886 11:11:29.905085 Closing test_set Format-ioctls-Input-0
6887 11:11:29.915814 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
6888 11:11:29.916572 Received signal: <TESTSET> START Codec-ioctls-Input-0
6889 11:11:29.916941 Starting test_set Codec-ioctls-Input-0
6890 11:11:29.919106 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
6891 11:11:29.946269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
6892 11:11:29.946884 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
6894 11:11:29.953165 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
6895 11:11:29.975810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
6896 11:11:29.976421 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
6898 11:11:29.982528 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
6899 11:11:30.006212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
6900 11:11:30.006600
6901 11:11:30.007131 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
6903 11:11:30.020385 Buffer ioctls (Input 0):
6904 11:11:30.028853 <LAVA_SIGNAL_TESTSET STOP>
6905 11:11:30.029467 Received signal: <TESTSET> STOP
6906 11:11:30.029775 Closing test_set Codec-ioctls-Input-0
6907 11:11:30.040035 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
6908 11:11:30.040646 Received signal: <TESTSET> START Buffer-ioctls-Input-0
6909 11:11:30.040965 Starting test_set Buffer-ioctls-Input-0
6910 11:11:30.043170 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
6911 11:11:30.071951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
6912 11:11:30.072204 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
6914 11:11:30.075245 test CREATE_BUFS maximum buffers: OK
6915 11:11:30.102964 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
6917 11:11:30.105444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
6918 11:11:30.105529 test VIDIOC_EXPBUF: OK
6919 11:11:30.132253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
6920 11:11:30.132475 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
6922 11:11:30.135286 test Requests: OK (Not Supported)
6923 11:11:30.160956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
6924 11:11:30.161046
6925 11:11:30.161283 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
6927 11:11:30.176326 Test input 0:
6928 11:11:30.188601
6929 11:11:30.203094 Streaming ioctls:
6930 11:11:30.212396 <LAVA_SIGNAL_TESTSET STOP>
6931 11:11:30.212675 Received signal: <TESTSET> STOP
6932 11:11:30.212744 Closing test_set Buffer-ioctls-Input-0
6933 11:11:30.223019 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
6934 11:11:30.223274 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
6935 11:11:30.223345 Starting test_set Streaming-ioctls_Test-input-0
6936 11:11:30.226432 test read/write: OK (Not Supported)
6937 11:11:30.253919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
6938 11:11:30.254173 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
6940 11:11:30.257210 test blocking wait: OK
6941 11:11:30.283065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
6942 11:11:30.283317 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
6944 11:11:30.289721 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
6945 11:11:30.296319 test MMAP (no poll): FAIL
6946 11:11:30.328423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
6947 11:11:30.328689 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
6949 11:11:30.334411 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
6950 11:11:30.342872 test MMAP (select): FAIL
6951 11:11:30.371981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
6952 11:11:30.372233 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
6954 11:11:30.378448 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
6955 11:11:30.387697 test MMAP (epoll): FAIL
6956 11:11:30.417377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
6957 11:11:30.417463
6958 11:11:30.417695 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
6960 11:11:30.656927
6961 11:11:30.667608 test USERPTR (no poll): OK
6962 11:11:30.696922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
6963 11:11:30.697311
6964 11:11:30.697838 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
6966 11:11:30.933777
6967 11:11:30.945319 test USERPTR (select): OK
6968 11:11:30.975916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
6969 11:11:30.976584 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
6971 11:11:30.979892 test DMABUF: Cannot test, specify --expbuf-device
6972 11:11:30.990333
6973 11:11:31.011859 Total for uvcvideo device /dev/video1: 54, Succeeded: 51, Failed: 3, Warnings: 1
6974 11:11:31.018178 <LAVA_TEST_RUNNER EXIT>
6975 11:11:31.018767 ok: lava_test_shell seems to have completed
6976 11:11:31.019033 Marking unfinished test run as failed
6978 11:11:31.022138 device-presence: pass
MC-information-see-Media-Driver-Info-above:
set: Required-ioctls
result: pass
VIDIOC_QUERYCAP:
set: Allow-for-multiple-opens
result: pass
invalid-ioctls:
set: Required-ioctls
result: pass
second-/dev/video1-open:
set: Allow-for-multiple-opens
result: pass
VIDIOC_G/S_PRIORITY:
set: Allow-for-multiple-opens
result: pass
for-unlimited-opens:
set: Allow-for-multiple-opens
result: pass
VIDIOC_DBG_G/S_REGISTER:
set: Debug-ioctls
result: pass
VIDIOC_LOG_STATUS:
set: Debug-ioctls
result: pass
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
set: Input-ioctls
result: pass
VIDIOC_G/S_FREQUENCY:
set: Input-ioctls
result: pass
VIDIOC_S_HW_FREQ_SEEK:
set: Input-ioctls
result: pass
VIDIOC_ENUMAUDIO:
set: Input-ioctls
result: pass
VIDIOC_G/S/ENUMINPUT:
set: Input-ioctls
result: pass
VIDIOC_G/S_AUDIO:
set: Input-ioctls
result: pass
VIDIOC_G/S_MODULATOR:
set: Input-ioctls
result: pass
VIDIOC_ENUMAUDOUT:
set: Input-ioctls
result: pass
VIDIOC_G/S/ENUMOUTPUT:
set: Input-ioctls
result: pass
VIDIOC_G/S_AUDOUT:
set: Input-ioctls
result: pass
VIDIOC_ENUM/G/S/QUERY_STD:
set: Input-ioctls
result: pass
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
set: Input-ioctls
result: pass
VIDIOC_DV_TIMINGS_CAP:
set: Input-ioctls
result: pass
VIDIOC_G/S_EDID:
set: Input-ioctls
result: pass
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
set: Control-ioctls-Input-0
result: pass
VIDIOC_QUERYCTRL:
set: Control-ioctls-Input-0
result: pass
VIDIOC_G/S_CTRL:
set: Control-ioctls-Input-0
result: pass
VIDIOC_G/S/TRY_EXT_CTRLS:
set: Control-ioctls-Input-0
result: pass
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
set: Control-ioctls-Input-0
result: pass
VIDIOC_G/S_JPEGCOMP:
set: Control-ioctls-Input-0
result: pass
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
set: Format-ioctls-Input-0
result: pass
VIDIOC_G/S_PARM:
set: Format-ioctls-Input-0
result: pass
VIDIOC_G_FBUF:
set: Format-ioctls-Input-0
result: pass
VIDIOC_G_FMT:
set: Format-ioctls-Input-0
result: pass
VIDIOC_TRY_FMT:
set: Format-ioctls-Input-0
result: pass
VIDIOC_S_FMT:
set: Format-ioctls-Input-0
result: pass
VIDIOC_G_SLICED_VBI_CAP:
set: Format-ioctls-Input-0
result: pass
Cropping:
set: Format-ioctls-Input-0
result: pass
Composing:
set: Format-ioctls-Input-0
result: pass
Scaling:
set: Format-ioctls-Input-0
result: pass
VIDIOC_TRY_ENCODER_CMD:
set: Codec-ioctls-Input-0
result: pass
VIDIOC_G_ENC_INDEX:
set: Codec-ioctls-Input-0
result: pass
VIDIOC_TRY_DECODER_CMD:
set: Codec-ioctls-Input-0
result: pass
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
set: Buffer-ioctls-Input-0
result: pass
CREATE_BUFS-maximum-buffers:
set: Buffer-ioctls-Input-0
result: pass
VIDIOC_EXPBUF:
set: Buffer-ioctls-Input-0
result: pass
Requests:
set: Buffer-ioctls-Input-0
result: pass
read/write:
set: Streaming-ioctls_Test-input-0
result: pass
blocking-wait:
set: Streaming-ioctls_Test-input-0
result: pass
MMAP-no-poll:
set: Streaming-ioctls_Test-input-0
result: fail
MMAP-select:
set: Streaming-ioctls_Test-input-0
result: fail
MMAP-epoll:
set: Streaming-ioctls_Test-input-0
result: fail
USERPTR-no-poll:
set: Streaming-ioctls_Test-input-0
result: pass
USERPTR-select:
set: Streaming-ioctls_Test-input-0
result: pass
6979 11:11:31.022606 end: 3.1 lava-test-shell (duration 00:00:11) [common]
6980 11:11:31.022917 end: 3 lava-test-retry (duration 00:00:11) [common]
6981 11:11:31.023229 start: 4 finalize (timeout 00:08:06) [common]
6982 11:11:31.023551 start: 4.1 power-off (timeout 00:00:30) [common]
6983 11:11:31.024094 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-0', '--port=1', '--command=off']
6984 11:11:33.123053 >> Command sent successfully.
6985 11:11:33.138233 Returned 0 in 2 seconds
6986 11:11:33.138823 end: 4.1 power-off (duration 00:00:02) [common]
6988 11:11:33.139920 start: 4.2 read-feedback (timeout 00:08:04) [common]
6989 11:11:33.140618 Listened to connection for namespace 'common' for up to 1s
6990 11:11:34.140720 Finalising connection for namespace 'common'
6991 11:11:34.141301 Disconnecting from shell: Finalise
6992 11:11:34.141655 / #
6993 11:11:34.242522 end: 4.2 read-feedback (duration 00:00:01) [common]
6994 11:11:34.243053 end: 4 finalize (duration 00:00:03) [common]
6995 11:11:34.243527 Cleaning after the job
6996 11:11:34.243960 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786846/tftp-deploy-qqigt0vp/ramdisk
6997 11:11:34.263590 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786846/tftp-deploy-qqigt0vp/kernel
6998 11:11:34.291335 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786846/tftp-deploy-qqigt0vp/dtb
6999 11:11:34.291540 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786846/tftp-deploy-qqigt0vp/modules
7000 11:11:34.297726 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14786846
7001 11:11:34.367191 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14786846
7002 11:11:34.367364 Job finished correctly