Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 28
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 11:02:00.125439 lava-dispatcher, installed at version: 2024.05
2 11:02:00.125635 start: 0 validate
3 11:02:00.125747 Start time: 2024-07-10 11:02:00.125742+00:00 (UTC)
4 11:02:00.125876 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:02:00.126015 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 11:02:00.412359 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:02:00.413113 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:03:18.985632 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:03:18.986353 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:03:19.255650 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:03:19.255831 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
12 11:03:19.791181 validate duration: 79.67
14 11:03:19.792292 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:03:19.792761 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:03:19.793245 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:03:19.793900 Not decompressing ramdisk as can be used compressed.
18 11:03:19.794297 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 11:03:19.794611 saving as /var/lib/lava/dispatcher/tmp/14786807/tftp-deploy-8zc7obp1/ramdisk/rootfs.cpio.gz
20 11:03:19.794910 total size: 28105535 (26 MB)
21 11:03:20.065307 progress 0 % (0 MB)
22 11:03:20.072291 progress 5 % (1 MB)
23 11:03:20.079108 progress 10 % (2 MB)
24 11:03:20.085917 progress 15 % (4 MB)
25 11:03:20.092760 progress 20 % (5 MB)
26 11:03:20.099602 progress 25 % (6 MB)
27 11:03:20.106675 progress 30 % (8 MB)
28 11:03:20.113676 progress 35 % (9 MB)
29 11:03:20.120457 progress 40 % (10 MB)
30 11:03:20.127148 progress 45 % (12 MB)
31 11:03:20.133955 progress 50 % (13 MB)
32 11:03:20.140748 progress 55 % (14 MB)
33 11:03:20.147761 progress 60 % (16 MB)
34 11:03:20.154631 progress 65 % (17 MB)
35 11:03:20.161478 progress 70 % (18 MB)
36 11:03:20.168259 progress 75 % (20 MB)
37 11:03:20.175097 progress 80 % (21 MB)
38 11:03:20.181945 progress 85 % (22 MB)
39 11:03:20.188819 progress 90 % (24 MB)
40 11:03:20.195553 progress 95 % (25 MB)
41 11:03:20.202273 progress 100 % (26 MB)
42 11:03:20.202479 26 MB downloaded in 0.41 s (65.76 MB/s)
43 11:03:20.202631 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:03:20.202848 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:03:20.202926 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:03:20.203000 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:03:20.203129 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
49 11:03:20.203189 saving as /var/lib/lava/dispatcher/tmp/14786807/tftp-deploy-8zc7obp1/kernel/Image
50 11:03:20.203242 total size: 54813184 (52 MB)
51 11:03:20.203296 No compression specified
52 11:03:20.204279 progress 0 % (0 MB)
53 11:03:20.217738 progress 5 % (2 MB)
54 11:03:20.231270 progress 10 % (5 MB)
55 11:03:20.244419 progress 15 % (7 MB)
56 11:03:20.257817 progress 20 % (10 MB)
57 11:03:20.271240 progress 25 % (13 MB)
58 11:03:20.284374 progress 30 % (15 MB)
59 11:03:20.297658 progress 35 % (18 MB)
60 11:03:20.311016 progress 40 % (20 MB)
61 11:03:20.324287 progress 45 % (23 MB)
62 11:03:20.337789 progress 50 % (26 MB)
63 11:03:20.351441 progress 55 % (28 MB)
64 11:03:20.364806 progress 60 % (31 MB)
65 11:03:20.378291 progress 65 % (34 MB)
66 11:03:20.391536 progress 70 % (36 MB)
67 11:03:20.404771 progress 75 % (39 MB)
68 11:03:20.418154 progress 80 % (41 MB)
69 11:03:20.431453 progress 85 % (44 MB)
70 11:03:20.445151 progress 90 % (47 MB)
71 11:03:20.458571 progress 95 % (49 MB)
72 11:03:20.472000 progress 100 % (52 MB)
73 11:03:20.472240 52 MB downloaded in 0.27 s (194.33 MB/s)
74 11:03:20.472392 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:03:20.472628 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:03:20.472721 start: 1.3 download-retry (timeout 00:09:59) [common]
78 11:03:20.472797 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 11:03:20.472923 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:03:20.472984 saving as /var/lib/lava/dispatcher/tmp/14786807/tftp-deploy-8zc7obp1/dtb/mt8192-asurada-spherion-r0.dtb
81 11:03:20.473037 total size: 47258 (0 MB)
82 11:03:20.473090 No compression specified
83 11:03:20.474142 progress 69 % (0 MB)
84 11:03:20.474392 progress 100 % (0 MB)
85 11:03:20.474535 0 MB downloaded in 0.00 s (30.13 MB/s)
86 11:03:20.474662 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:03:20.474942 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:03:20.475029 start: 1.4 download-retry (timeout 00:09:59) [common]
90 11:03:20.475109 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 11:03:20.475219 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
92 11:03:20.475280 saving as /var/lib/lava/dispatcher/tmp/14786807/tftp-deploy-8zc7obp1/modules/modules.tar
93 11:03:20.475333 total size: 8607984 (8 MB)
94 11:03:20.475387 Using unxz to decompress xz
95 11:03:20.476787 progress 0 % (0 MB)
96 11:03:20.497049 progress 5 % (0 MB)
97 11:03:20.521454 progress 10 % (0 MB)
98 11:03:20.545892 progress 15 % (1 MB)
99 11:03:20.569936 progress 20 % (1 MB)
100 11:03:20.593222 progress 25 % (2 MB)
101 11:03:20.616927 progress 30 % (2 MB)
102 11:03:20.639385 progress 35 % (2 MB)
103 11:03:20.665843 progress 40 % (3 MB)
104 11:03:20.690079 progress 45 % (3 MB)
105 11:03:20.714928 progress 50 % (4 MB)
106 11:03:20.741430 progress 55 % (4 MB)
107 11:03:20.767883 progress 60 % (4 MB)
108 11:03:20.792046 progress 65 % (5 MB)
109 11:03:20.818374 progress 70 % (5 MB)
110 11:03:20.845424 progress 75 % (6 MB)
111 11:03:20.873142 progress 80 % (6 MB)
112 11:03:20.896498 progress 85 % (7 MB)
113 11:03:20.919549 progress 90 % (7 MB)
114 11:03:20.942674 progress 95 % (7 MB)
115 11:03:20.965351 progress 100 % (8 MB)
116 11:03:20.970685 8 MB downloaded in 0.50 s (16.57 MB/s)
117 11:03:20.970885 end: 1.4.1 http-download (duration 00:00:00) [common]
119 11:03:20.971239 end: 1.4 download-retry (duration 00:00:00) [common]
120 11:03:20.971352 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:03:20.971460 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:03:20.971563 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:03:20.971645 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:03:20.971811 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5
125 11:03:20.971931 makedir: /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin
126 11:03:20.972025 makedir: /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/tests
127 11:03:20.972122 makedir: /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/results
128 11:03:20.972236 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-add-keys
129 11:03:20.972399 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-add-sources
130 11:03:20.972551 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-background-process-start
131 11:03:20.972698 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-background-process-stop
132 11:03:20.972847 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-common-functions
133 11:03:20.972965 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-echo-ipv4
134 11:03:20.973080 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-install-packages
135 11:03:20.973241 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-installed-packages
136 11:03:20.973398 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-os-build
137 11:03:20.973515 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-probe-channel
138 11:03:20.973635 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-probe-ip
139 11:03:20.973751 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-target-ip
140 11:03:20.973866 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-target-mac
141 11:03:20.973984 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-target-storage
142 11:03:20.974103 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-test-case
143 11:03:20.974218 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-test-event
144 11:03:20.974329 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-test-feedback
145 11:03:20.974443 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-test-raise
146 11:03:20.974569 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-test-reference
147 11:03:20.974683 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-test-runner
148 11:03:20.974798 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-test-set
149 11:03:20.974914 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-test-shell
150 11:03:20.975073 Updating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-install-packages (oe)
151 11:03:20.975238 Updating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/bin/lava-installed-packages (oe)
152 11:03:20.975356 Creating /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/environment
153 11:03:20.975451 LAVA metadata
154 11:03:20.975521 - LAVA_JOB_ID=14786807
155 11:03:20.975584 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:03:20.975679 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:03:20.975736 skipped lava-vland-overlay
158 11:03:20.975810 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:03:20.975882 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:03:20.975938 skipped lava-multinode-overlay
161 11:03:20.976003 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:03:20.976078 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:03:20.976142 Loading test definitions
164 11:03:20.976223 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:03:20.976284 Using /lava-14786807 at stage 0
166 11:03:20.976583 uuid=14786807_1.5.2.3.1 testdef=None
167 11:03:20.976672 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:03:20.976784 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:03:20.977280 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:03:20.977479 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:03:20.978097 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:03:20.978308 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:03:20.978851 runner path: /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/0/tests/0_v4l2-compliance-uvc test_uuid 14786807_1.5.2.3.1
176 11:03:20.978994 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:03:20.979188 Creating lava-test-runner.conf files
179 11:03:20.979245 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14786807/lava-overlay-2dpozic5/lava-14786807/0 for stage 0
180 11:03:20.979327 - 0_v4l2-compliance-uvc
181 11:03:20.979417 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:03:20.979493 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:03:20.985610 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:03:20.985707 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:03:20.985787 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:03:20.985875 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:03:20.985971 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:03:21.772626 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:03:21.772815 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:03:21.772908 extracting modules file /var/lib/lava/dispatcher/tmp/14786807/tftp-deploy-8zc7obp1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14786807/extract-overlay-ramdisk-6c_juycx/ramdisk
191 11:03:22.030190 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:03:22.030332 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 11:03:22.030409 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786807/compress-overlay-tdwlr3y9/overlay-1.5.2.4.tar.gz to ramdisk
194 11:03:22.030471 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14786807/compress-overlay-tdwlr3y9/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14786807/extract-overlay-ramdisk-6c_juycx/ramdisk
195 11:03:22.037038 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:03:22.037149 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 11:03:22.037235 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:03:22.037314 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 11:03:22.037380 Building ramdisk /var/lib/lava/dispatcher/tmp/14786807/extract-overlay-ramdisk-6c_juycx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14786807/extract-overlay-ramdisk-6c_juycx/ramdisk
200 11:03:22.622495 >> 275391 blocks
201 11:03:26.893809 rename /var/lib/lava/dispatcher/tmp/14786807/extract-overlay-ramdisk-6c_juycx/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14786807/tftp-deploy-8zc7obp1/ramdisk/ramdisk.cpio.gz
202 11:03:26.893971 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 11:03:26.894061 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 11:03:26.894175 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 11:03:26.894288 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14786807/tftp-deploy-8zc7obp1/kernel/Image']
206 11:03:40.657617 Returned 0 in 13 seconds
207 11:03:40.657814 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14786807/tftp-deploy-8zc7obp1/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14786807/tftp-deploy-8zc7obp1/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14786807/tftp-deploy-8zc7obp1/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14786807/tftp-deploy-8zc7obp1/kernel/image.itb
208 11:03:41.240386 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:03:41.240519 output: Created: Wed Jul 10 12:03:41 2024
210 11:03:41.240602 output: Image 0 (kernel-1)
211 11:03:41.240676 output: Description:
212 11:03:41.240748 output: Created: Wed Jul 10 12:03:41 2024
213 11:03:41.240818 output: Type: Kernel Image
214 11:03:41.240887 output: Compression: lzma compressed
215 11:03:41.240975 output: Data Size: 13116259 Bytes = 12808.85 KiB = 12.51 MiB
216 11:03:41.241062 output: Architecture: AArch64
217 11:03:41.241192 output: OS: Linux
218 11:03:41.241278 output: Load Address: 0x00000000
219 11:03:41.241363 output: Entry Point: 0x00000000
220 11:03:41.241446 output: Hash algo: crc32
221 11:03:41.241531 output: Hash value: 9bb85fb9
222 11:03:41.241614 output: Image 1 (fdt-1)
223 11:03:41.241698 output: Description: mt8192-asurada-spherion-r0
224 11:03:41.241782 output: Created: Wed Jul 10 12:03:41 2024
225 11:03:41.241866 output: Type: Flat Device Tree
226 11:03:41.241950 output: Compression: uncompressed
227 11:03:41.242034 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 11:03:41.242118 output: Architecture: AArch64
229 11:03:41.242201 output: Hash algo: crc32
230 11:03:41.242284 output: Hash value: 0f8e4d2e
231 11:03:41.242367 output: Image 2 (ramdisk-1)
232 11:03:41.242450 output: Description: unavailable
233 11:03:41.242533 output: Created: Wed Jul 10 12:03:41 2024
234 11:03:41.242617 output: Type: RAMDisk Image
235 11:03:41.242700 output: Compression: uncompressed
236 11:03:41.242783 output: Data Size: 41185889 Bytes = 40220.59 KiB = 39.28 MiB
237 11:03:41.242867 output: Architecture: AArch64
238 11:03:41.242951 output: OS: Linux
239 11:03:41.243034 output: Load Address: unavailable
240 11:03:41.243116 output: Entry Point: unavailable
241 11:03:41.243199 output: Hash algo: crc32
242 11:03:41.243282 output: Hash value: 80093361
243 11:03:41.243365 output: Default Configuration: 'conf-1'
244 11:03:41.243448 output: Configuration 0 (conf-1)
245 11:03:41.243530 output: Description: mt8192-asurada-spherion-r0
246 11:03:41.243613 output: Kernel: kernel-1
247 11:03:41.243696 output: Init Ramdisk: ramdisk-1
248 11:03:41.243780 output: FDT: fdt-1
249 11:03:41.243863 output: Loadables: kernel-1
250 11:03:41.243945 output:
251 11:03:41.244090 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 11:03:41.244199 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 11:03:41.244311 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 11:03:41.244423 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 11:03:41.244513 No LXC device requested
256 11:03:41.244622 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:03:41.244731 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 11:03:41.244836 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:03:41.244922 Checking files for TFTP limit of 4294967296 bytes.
260 11:03:41.245477 end: 1 tftp-deploy (duration 00:00:21) [common]
261 11:03:41.245598 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:03:41.245745 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:03:41.245890 substitutions:
264 11:03:41.245980 - {DTB}: 14786807/tftp-deploy-8zc7obp1/dtb/mt8192-asurada-spherion-r0.dtb
265 11:03:41.246064 - {INITRD}: 14786807/tftp-deploy-8zc7obp1/ramdisk/ramdisk.cpio.gz
266 11:03:41.246144 - {KERNEL}: 14786807/tftp-deploy-8zc7obp1/kernel/Image
267 11:03:41.246223 - {LAVA_MAC}: None
268 11:03:41.246300 - {PRESEED_CONFIG}: None
269 11:03:41.246378 - {PRESEED_LOCAL}: None
270 11:03:41.246455 - {RAMDISK}: 14786807/tftp-deploy-8zc7obp1/ramdisk/ramdisk.cpio.gz
271 11:03:41.246537 - {ROOT_PART}: None
272 11:03:41.246614 - {ROOT}: None
273 11:03:41.246690 - {SERVER_IP}: 192.168.201.1
274 11:03:41.246766 - {TEE}: None
275 11:03:41.246834 Parsed boot commands:
276 11:03:41.246884 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:03:41.247021 Parsed boot commands: tftpboot 192.168.201.1 14786807/tftp-deploy-8zc7obp1/kernel/image.itb 14786807/tftp-deploy-8zc7obp1/kernel/cmdline
278 11:03:41.247100 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:03:41.247205 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:03:41.247304 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:03:41.247401 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:03:41.247487 Not connected, no need to disconnect.
283 11:03:41.247591 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:03:41.247701 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:03:41.247777 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 11:03:41.250775 Setting prompt string to ['lava-test: # ']
287 11:03:41.251079 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:03:41.251176 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:03:41.251313 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:03:41.251424 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:03:41.251604 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
292 11:03:50.374539 >> Command sent successfully.
293 11:03:50.377762 Returned 0 in 9 seconds
294 11:03:50.377926 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 11:03:50.378240 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 11:03:50.378332 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 11:03:50.378401 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:03:50.378456 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:03:50.378513 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:03:50.378852 [Enter `^Ec?' for help]
302 11:03:51.956513
303 11:03:51.956647
304 11:03:51.956709 F0: 102B 0000
305 11:03:51.956769
306 11:03:51.956825 F3: 1001 0000 [0200]
307 11:03:51.959832
308 11:03:51.959910 F3: 1001 0000
309 11:03:51.959972
310 11:03:51.960026 F7: 102D 0000
311 11:03:51.960078
312 11:03:51.960128 F1: 0000 0000
313 11:03:51.963514
314 11:03:51.963587 V0: 0000 0000 [0001]
315 11:03:51.963645
316 11:03:51.963699 00: 0007 8000
317 11:03:51.963752
318 11:03:51.967462 01: 0000 0000
319 11:03:51.967540
320 11:03:51.967598 BP: 0C00 0209 [0000]
321 11:03:51.967651
322 11:03:51.971131 G0: 1182 0000
323 11:03:51.971205
324 11:03:51.971263 EC: 0000 0021 [4000]
325 11:03:51.971316
326 11:03:51.974976 S7: 0000 0000 [0000]
327 11:03:51.975051
328 11:03:51.975109 CC: 0000 0000 [0001]
329 11:03:51.975163
330 11:03:51.978363 T0: 0000 0040 [010F]
331 11:03:51.978438
332 11:03:51.978496 Jump to BL
333 11:03:51.978550
334 11:03:52.003407
335 11:03:52.003485
336 11:03:52.009700 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 11:03:52.013362 ARM64: Exception handlers installed.
338 11:03:52.016706 ARM64: Testing exception
339 11:03:52.020443 ARM64: Done test exception
340 11:03:52.027012 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 11:03:52.037333 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 11:03:52.043488 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 11:03:52.054188 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 11:03:52.060949 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 11:03:52.070855 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 11:03:52.080923 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 11:03:52.087712 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 11:03:52.106550 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 11:03:52.109299 WDT: Last reset was cold boot
350 11:03:52.113105 SPI1(PAD0) initialized at 2873684 Hz
351 11:03:52.116641 SPI5(PAD0) initialized at 992727 Hz
352 11:03:52.120000 VBOOT: Loading verstage.
353 11:03:52.125942 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 11:03:52.129595 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 11:03:52.132850 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 11:03:52.136190 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 11:03:52.143438 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 11:03:52.150628 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 11:03:52.161436 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
360 11:03:52.161551
361 11:03:52.161646
362 11:03:52.171150 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 11:03:52.174567 ARM64: Exception handlers installed.
364 11:03:52.178381 ARM64: Testing exception
365 11:03:52.178459 ARM64: Done test exception
366 11:03:52.184478 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 11:03:52.188236 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 11:03:52.201802 Probing TPM: . done!
369 11:03:52.201916 TPM ready after 0 ms
370 11:03:52.208806 Connected to device vid:did:rid of 1ae0:0028:00
371 11:03:52.215452 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 11:03:52.219493 Initialized TPM device CR50 revision 0
373 11:03:52.267346 tlcl_send_startup: Startup return code is 0
374 11:03:52.267472 TPM: setup succeeded
375 11:03:52.279080 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 11:03:52.287755 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 11:03:52.298546 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 11:03:52.307001 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 11:03:52.310462 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 11:03:52.313737 in-header: 03 07 00 00 08 00 00 00
381 11:03:52.317227 in-data: aa e4 47 04 13 02 00 00
382 11:03:52.320305 Chrome EC: UHEPI supported
383 11:03:52.327105 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 11:03:52.331876 in-header: 03 a9 00 00 08 00 00 00
385 11:03:52.333796 in-data: 84 60 60 08 00 00 00 00
386 11:03:52.333895 Phase 1
387 11:03:52.337209 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 11:03:52.343814 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 11:03:52.350968 VB2:vb2_check_recovery() Recovery was requested manually
390 11:03:52.355267 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 11:03:52.357088 Recovery requested (1009000e)
392 11:03:52.360815 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:03:52.370439 tlcl_extend: response is 0
394 11:03:52.381332 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:03:52.384383 tlcl_extend: response is 0
396 11:03:52.390917 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:03:52.411544 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 11:03:52.418206 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:03:52.418309
400 11:03:52.418368
401 11:03:52.428498 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:03:52.431475 ARM64: Exception handlers installed.
403 11:03:52.434933 ARM64: Testing exception
404 11:03:52.435016 ARM64: Done test exception
405 11:03:52.456866 pmic_efuse_setting: Set efuses in 11 msecs
406 11:03:52.460563 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:03:52.467668 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:03:52.471986 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:03:52.475004 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:03:52.481255 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:03:52.484581 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:03:52.491499 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:03:52.494732 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:03:52.501310 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:03:52.504962 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:03:52.508087 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:03:52.515111 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:03:52.517988 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:03:52.521066 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:03:52.528262 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:03:52.535503 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:03:52.541933 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:03:52.545745 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:03:52.552123 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:03:52.558425 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:03:52.561933 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:03:52.568463 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:03:52.575526 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:03:52.578620 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:03:52.585469 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:03:52.588842 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:03:52.596238 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:03:52.602336 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:03:52.605838 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:03:52.612297 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:03:52.616324 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:03:52.620023 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:03:52.625938 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:03:52.629324 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:03:52.635877 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:03:52.639025 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:03:52.645951 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:03:52.649086 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:03:52.656082 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:03:52.660044 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:03:52.663612 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:03:52.669994 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:03:52.673539 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:03:52.677319 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:03:52.683629 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:03:52.687180 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:03:52.690179 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:03:52.693774 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:03:52.700480 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:03:52.703504 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:03:52.707012 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:03:52.710819 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:03:52.720012 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 11:03:52.727009 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:03:52.733702 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:03:52.740512 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:03:52.750535 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:03:52.753937 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:03:52.757246 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:03:52.763998 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:03:52.771126 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x37
467 11:03:52.773707 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:03:52.781448 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 11:03:52.784665 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:03:52.794140 [RTC]rtc_get_frequency_meter,154: input=15, output=792
471 11:03:52.797566 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 11:03:52.804566 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 11:03:52.807335 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
474 11:03:52.810871 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 11:03:52.814085 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
476 11:03:52.817593 ADC[4]: Raw value=901328 ID=7
477 11:03:52.820940 ADC[3]: Raw value=212967 ID=1
478 11:03:52.821046 RAM Code: 0x71
479 11:03:52.827577 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 11:03:52.830907 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 11:03:52.841080 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 11:03:52.847777 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 11:03:52.851191 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 11:03:52.854641 in-header: 03 07 00 00 08 00 00 00
485 11:03:52.857947 in-data: aa e4 47 04 13 02 00 00
486 11:03:52.858032 Chrome EC: UHEPI supported
487 11:03:52.864621 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 11:03:52.869017 in-header: 03 a9 00 00 08 00 00 00
489 11:03:52.872312 in-data: 84 60 60 08 00 00 00 00
490 11:03:52.875544 MRC: failed to locate region type 0.
491 11:03:52.882376 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 11:03:52.886395 DRAM-K: Running full calibration
493 11:03:52.892392 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 11:03:52.895980 header.status = 0x0
495 11:03:52.899554 header.version = 0x6 (expected: 0x6)
496 11:03:52.903182 header.size = 0xd00 (expected: 0xd00)
497 11:03:52.903268 header.flags = 0x0
498 11:03:52.909002 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 11:03:52.926518 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
500 11:03:52.933473 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 11:03:52.936686 dram_init: ddr_geometry: 2
502 11:03:52.936771 [EMI] MDL number = 2
503 11:03:52.940107 [EMI] Get MDL freq = 0
504 11:03:52.943712 dram_init: ddr_type: 0
505 11:03:52.943795 is_discrete_lpddr4: 1
506 11:03:52.947211 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 11:03:52.947298
508 11:03:52.947357
509 11:03:52.950286 [Bian_co] ETT version 0.0.0.1
510 11:03:52.957034 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 11:03:52.957186
512 11:03:52.960317 dramc_set_vcore_voltage set vcore to 650000
513 11:03:52.960397 Read voltage for 800, 4
514 11:03:52.963752 Vio18 = 0
515 11:03:52.963833 Vcore = 650000
516 11:03:52.963892 Vdram = 0
517 11:03:52.967553 Vddq = 0
518 11:03:52.967636 Vmddr = 0
519 11:03:52.970510 dram_init: config_dvfs: 1
520 11:03:52.973837 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 11:03:52.980524 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 11:03:52.983959 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
523 11:03:52.987460 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
524 11:03:52.990702 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
525 11:03:52.993929 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
526 11:03:52.997362 MEM_TYPE=3, freq_sel=18
527 11:03:53.000554 sv_algorithm_assistance_LP4_1600
528 11:03:53.004265 ============ PULL DRAM RESETB DOWN ============
529 11:03:53.007640 ========== PULL DRAM RESETB DOWN end =========
530 11:03:53.014012 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 11:03:53.018580 ===================================
532 11:03:53.018673 LPDDR4 DRAM CONFIGURATION
533 11:03:53.021327 ===================================
534 11:03:53.024305 EX_ROW_EN[0] = 0x0
535 11:03:53.024385 EX_ROW_EN[1] = 0x0
536 11:03:53.027504 LP4Y_EN = 0x0
537 11:03:53.027581 WORK_FSP = 0x0
538 11:03:53.031730 WL = 0x2
539 11:03:53.031811 RL = 0x2
540 11:03:53.034679 BL = 0x2
541 11:03:53.037543 RPST = 0x0
542 11:03:53.037620 RD_PRE = 0x0
543 11:03:53.041182 WR_PRE = 0x1
544 11:03:53.041261 WR_PST = 0x0
545 11:03:53.044570 DBI_WR = 0x0
546 11:03:53.044648 DBI_RD = 0x0
547 11:03:53.047843 OTF = 0x1
548 11:03:53.051075 ===================================
549 11:03:53.055015 ===================================
550 11:03:53.055100 ANA top config
551 11:03:53.059102 ===================================
552 11:03:53.061369 DLL_ASYNC_EN = 0
553 11:03:53.061452 ALL_SLAVE_EN = 1
554 11:03:53.064541 NEW_RANK_MODE = 1
555 11:03:53.068035 DLL_IDLE_MODE = 1
556 11:03:53.071248 LP45_APHY_COMB_EN = 1
557 11:03:53.075296 TX_ODT_DIS = 1
558 11:03:53.075386 NEW_8X_MODE = 1
559 11:03:53.077971 ===================================
560 11:03:53.081580 ===================================
561 11:03:53.085026 data_rate = 1600
562 11:03:53.088452 CKR = 1
563 11:03:53.091557 DQ_P2S_RATIO = 8
564 11:03:53.094994 ===================================
565 11:03:53.098459 CA_P2S_RATIO = 8
566 11:03:53.098541 DQ_CA_OPEN = 0
567 11:03:53.102679 DQ_SEMI_OPEN = 0
568 11:03:53.105743 CA_SEMI_OPEN = 0
569 11:03:53.108936 CA_FULL_RATE = 0
570 11:03:53.109019 DQ_CKDIV4_EN = 1
571 11:03:53.112510 CA_CKDIV4_EN = 1
572 11:03:53.116188 CA_PREDIV_EN = 0
573 11:03:53.120615 PH8_DLY = 0
574 11:03:53.120706 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 11:03:53.124862 DQ_AAMCK_DIV = 4
576 11:03:53.128064 CA_AAMCK_DIV = 4
577 11:03:53.131945 CA_ADMCK_DIV = 4
578 11:03:53.132035 DQ_TRACK_CA_EN = 0
579 11:03:53.135794 CA_PICK = 800
580 11:03:53.139285 CA_MCKIO = 800
581 11:03:53.142705 MCKIO_SEMI = 0
582 11:03:53.146150 PLL_FREQ = 3068
583 11:03:53.146243 DQ_UI_PI_RATIO = 32
584 11:03:53.149835 CA_UI_PI_RATIO = 0
585 11:03:53.153038 ===================================
586 11:03:53.156538 ===================================
587 11:03:53.159105 memory_type:LPDDR4
588 11:03:53.162816 GP_NUM : 10
589 11:03:53.162901 SRAM_EN : 1
590 11:03:53.165990 MD32_EN : 0
591 11:03:53.169696 ===================================
592 11:03:53.169782 [ANA_INIT] >>>>>>>>>>>>>>
593 11:03:53.172766 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 11:03:53.176087 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 11:03:53.180070 ===================================
596 11:03:53.183479 data_rate = 1600,PCW = 0X7600
597 11:03:53.186126 ===================================
598 11:03:53.189626 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 11:03:53.196717 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 11:03:53.200183 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 11:03:53.206400 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 11:03:53.209919 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 11:03:53.213155 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 11:03:53.213259 [ANA_INIT] flow start
605 11:03:53.216679 [ANA_INIT] PLL >>>>>>>>
606 11:03:53.220057 [ANA_INIT] PLL <<<<<<<<
607 11:03:53.220140 [ANA_INIT] MIDPI >>>>>>>>
608 11:03:53.223191 [ANA_INIT] MIDPI <<<<<<<<
609 11:03:53.226856 [ANA_INIT] DLL >>>>>>>>
610 11:03:53.226940 [ANA_INIT] flow end
611 11:03:53.233345 ============ LP4 DIFF to SE enter ============
612 11:03:53.237075 ============ LP4 DIFF to SE exit ============
613 11:03:53.237187 [ANA_INIT] <<<<<<<<<<<<<
614 11:03:53.240082 [Flow] Enable top DCM control >>>>>
615 11:03:53.244095 [Flow] Enable top DCM control <<<<<
616 11:03:53.246825 Enable DLL master slave shuffle
617 11:03:53.253307 ==============================================================
618 11:03:53.253407 Gating Mode config
619 11:03:53.261555 ==============================================================
620 11:03:53.264160 Config description:
621 11:03:53.273836 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 11:03:53.281032 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 11:03:53.283772 SELPH_MODE 0: By rank 1: By Phase
624 11:03:53.291012 ==============================================================
625 11:03:53.291115 GAT_TRACK_EN = 1
626 11:03:53.294021 RX_GATING_MODE = 2
627 11:03:53.298018 RX_GATING_TRACK_MODE = 2
628 11:03:53.301136 SELPH_MODE = 1
629 11:03:53.303957 PICG_EARLY_EN = 1
630 11:03:53.307250 VALID_LAT_VALUE = 1
631 11:03:53.314485 ==============================================================
632 11:03:53.317456 Enter into Gating configuration >>>>
633 11:03:53.320550 Exit from Gating configuration <<<<
634 11:03:53.323942 Enter into DVFS_PRE_config >>>>>
635 11:03:53.334212 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 11:03:53.337449 Exit from DVFS_PRE_config <<<<<
637 11:03:53.341252 Enter into PICG configuration >>>>
638 11:03:53.344694 Exit from PICG configuration <<<<
639 11:03:53.344778 [RX_INPUT] configuration >>>>>
640 11:03:53.348119 [RX_INPUT] configuration <<<<<
641 11:03:53.354041 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 11:03:53.357580 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 11:03:53.364480 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 11:03:53.371199 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 11:03:53.378065 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 11:03:53.384982 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 11:03:53.387610 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 11:03:53.391322 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 11:03:53.394718 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 11:03:53.401511 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 11:03:53.404563 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 11:03:53.408141 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 11:03:53.412279 ===================================
654 11:03:53.414655 LPDDR4 DRAM CONFIGURATION
655 11:03:53.418379 ===================================
656 11:03:53.418474 EX_ROW_EN[0] = 0x0
657 11:03:53.421507 EX_ROW_EN[1] = 0x0
658 11:03:53.424726 LP4Y_EN = 0x0
659 11:03:53.424810 WORK_FSP = 0x0
660 11:03:53.428460 WL = 0x2
661 11:03:53.428539 RL = 0x2
662 11:03:53.431836 BL = 0x2
663 11:03:53.431913 RPST = 0x0
664 11:03:53.435258 RD_PRE = 0x0
665 11:03:53.435335 WR_PRE = 0x1
666 11:03:53.438471 WR_PST = 0x0
667 11:03:53.438587 DBI_WR = 0x0
668 11:03:53.441464 DBI_RD = 0x0
669 11:03:53.441541 OTF = 0x1
670 11:03:53.445022 ===================================
671 11:03:53.449083 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 11:03:53.455168 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 11:03:53.458753 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 11:03:53.462088 ===================================
675 11:03:53.465090 LPDDR4 DRAM CONFIGURATION
676 11:03:53.468613 ===================================
677 11:03:53.468717 EX_ROW_EN[0] = 0x10
678 11:03:53.472030 EX_ROW_EN[1] = 0x0
679 11:03:53.472110 LP4Y_EN = 0x0
680 11:03:53.475762 WORK_FSP = 0x0
681 11:03:53.475845 WL = 0x2
682 11:03:53.478370 RL = 0x2
683 11:03:53.478447 BL = 0x2
684 11:03:53.481936 RPST = 0x0
685 11:03:53.482015 RD_PRE = 0x0
686 11:03:53.486763 WR_PRE = 0x1
687 11:03:53.486842 WR_PST = 0x0
688 11:03:53.488674 DBI_WR = 0x0
689 11:03:53.488750 DBI_RD = 0x0
690 11:03:53.492491 OTF = 0x1
691 11:03:53.495213 ===================================
692 11:03:53.502226 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 11:03:53.505687 nWR fixed to 40
694 11:03:53.509248 [ModeRegInit_LP4] CH0 RK0
695 11:03:53.509332 [ModeRegInit_LP4] CH0 RK1
696 11:03:53.511941 [ModeRegInit_LP4] CH1 RK0
697 11:03:53.515933 [ModeRegInit_LP4] CH1 RK1
698 11:03:53.516017 match AC timing 13
699 11:03:53.522408 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 11:03:53.525818 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 11:03:53.529250 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 11:03:53.532380 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 11:03:53.539271 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 11:03:53.539367 [EMI DOE] emi_dcm 0
705 11:03:53.546016 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 11:03:53.546107 ==
707 11:03:53.549235 Dram Type= 6, Freq= 0, CH_0, rank 0
708 11:03:53.552871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 11:03:53.552953 ==
710 11:03:53.556076 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 11:03:53.562485 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 11:03:53.572530 [CA 0] Center 37 (7~68) winsize 62
713 11:03:53.575892 [CA 1] Center 37 (6~68) winsize 63
714 11:03:53.579659 [CA 2] Center 35 (5~66) winsize 62
715 11:03:53.582744 [CA 3] Center 34 (4~65) winsize 62
716 11:03:53.586432 [CA 4] Center 34 (3~65) winsize 63
717 11:03:53.590374 [CA 5] Center 33 (3~64) winsize 62
718 11:03:53.590461
719 11:03:53.592793 [CmdBusTrainingLP45] Vref(ca) range 1: 32
720 11:03:53.592873
721 11:03:53.597460 [CATrainingPosCal] consider 1 rank data
722 11:03:53.599581 u2DelayCellTimex100 = 270/100 ps
723 11:03:53.602913 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
724 11:03:53.606084 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
725 11:03:53.609548 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
726 11:03:53.616537 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
727 11:03:53.620063 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
728 11:03:53.622910 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
729 11:03:53.622993
730 11:03:53.626800 CA PerBit enable=1, Macro0, CA PI delay=33
731 11:03:53.626882
732 11:03:53.630100 [CBTSetCACLKResult] CA Dly = 33
733 11:03:53.630178 CS Dly: 5 (0~36)
734 11:03:53.630238 ==
735 11:03:53.633167 Dram Type= 6, Freq= 0, CH_0, rank 1
736 11:03:53.636556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 11:03:53.639845 ==
738 11:03:53.644129 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 11:03:53.649827 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 11:03:53.659230 [CA 0] Center 37 (6~68) winsize 63
741 11:03:53.662177 [CA 1] Center 37 (6~68) winsize 63
742 11:03:53.666358 [CA 2] Center 35 (4~66) winsize 63
743 11:03:53.669454 [CA 3] Center 35 (4~66) winsize 63
744 11:03:53.672819 [CA 4] Center 34 (4~65) winsize 62
745 11:03:53.676477 [CA 5] Center 33 (3~64) winsize 62
746 11:03:53.676593
747 11:03:53.679718 [CmdBusTrainingLP45] Vref(ca) range 1: 34
748 11:03:53.679815
749 11:03:53.682877 [CATrainingPosCal] consider 2 rank data
750 11:03:53.687834 u2DelayCellTimex100 = 270/100 ps
751 11:03:53.690112 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
752 11:03:53.694129 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
753 11:03:53.696983 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
754 11:03:53.700413 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
755 11:03:53.703579 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
756 11:03:53.707281 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
757 11:03:53.707365
758 11:03:53.713791 CA PerBit enable=1, Macro0, CA PI delay=33
759 11:03:53.713926
760 11:03:53.713988 [CBTSetCACLKResult] CA Dly = 33
761 11:03:53.717452 CS Dly: 6 (0~38)
762 11:03:53.717536
763 11:03:53.720905 ----->DramcWriteLeveling(PI) begin...
764 11:03:53.720994 ==
765 11:03:53.724352 Dram Type= 6, Freq= 0, CH_0, rank 0
766 11:03:53.727086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 11:03:53.727168 ==
768 11:03:53.730224 Write leveling (Byte 0): 32 => 32
769 11:03:53.733948 Write leveling (Byte 1): 27 => 27
770 11:03:53.737033 DramcWriteLeveling(PI) end<-----
771 11:03:53.737112
772 11:03:53.737214 ==
773 11:03:53.740299 Dram Type= 6, Freq= 0, CH_0, rank 0
774 11:03:53.743934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 11:03:53.747467 ==
776 11:03:53.747550 [Gating] SW mode calibration
777 11:03:53.753716 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 11:03:53.760558 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 11:03:53.764126 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 11:03:53.770555 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 11:03:53.774071 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
782 11:03:53.778225 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
783 11:03:53.780979 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 11:03:53.788424 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 11:03:53.790967 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 11:03:53.794398 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 11:03:53.801072 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 11:03:53.804244 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 11:03:53.807739 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:03:53.814670 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:03:53.817450 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:03:53.821112 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:03:53.827914 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:03:53.830875 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:03:53.834669 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:03:53.838313 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:03:53.844469 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
798 11:03:53.848009 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
799 11:03:53.851414 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:03:53.857808 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:03:53.861456 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:03:53.865405 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:03:53.871450 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 11:03:53.874645 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 11:03:53.878691 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
806 11:03:53.885158 0 9 12 | B1->B0 | 2a2a 3232 | 0 0 | (0 0) (0 0)
807 11:03:53.888043 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 11:03:53.891503 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 11:03:53.895060 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 11:03:53.901798 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 11:03:53.904793 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 11:03:53.908281 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 11:03:53.915075 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
814 11:03:53.919261 0 10 12 | B1->B0 | 2e2e 2424 | 0 0 | (1 1) (0 0)
815 11:03:53.921620 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 11:03:53.928294 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 11:03:53.932599 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 11:03:53.935169 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 11:03:53.941846 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 11:03:53.945022 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 11:03:53.948939 0 11 8 | B1->B0 | 2626 2e2e | 0 0 | (0 0) (0 0)
822 11:03:53.955130 0 11 12 | B1->B0 | 3d3d 4343 | 0 0 | (0 0) (0 0)
823 11:03:53.958468 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 11:03:53.962273 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 11:03:53.965785 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 11:03:53.972020 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 11:03:53.975894 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 11:03:53.978830 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 11:03:53.985354 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
830 11:03:53.988719 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 11:03:53.992484 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 11:03:53.999134 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 11:03:54.002407 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 11:03:54.006128 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 11:03:54.012440 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 11:03:54.016165 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 11:03:54.019906 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 11:03:54.022434 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:03:54.028984 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:03:54.032296 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:03:54.035617 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:03:54.042388 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:03:54.046616 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:03:54.048917 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:03:54.055807 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
846 11:03:54.059253 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 11:03:54.062612 Total UI for P1: 0, mck2ui 16
848 11:03:54.065802 best dqsien dly found for B0: ( 0, 14, 8)
849 11:03:54.069365 Total UI for P1: 0, mck2ui 16
850 11:03:54.073599 best dqsien dly found for B1: ( 0, 14, 8)
851 11:03:54.076287 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
852 11:03:54.079585 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
853 11:03:54.079677
854 11:03:54.082672 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
855 11:03:54.086459 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
856 11:03:54.089518 [Gating] SW calibration Done
857 11:03:54.089599 ==
858 11:03:54.092827 Dram Type= 6, Freq= 0, CH_0, rank 0
859 11:03:54.096056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
860 11:03:54.096138 ==
861 11:03:54.100147 RX Vref Scan: 0
862 11:03:54.100228
863 11:03:54.100289 RX Vref 0 -> 0, step: 1
864 11:03:54.100344
865 11:03:54.102996 RX Delay -130 -> 252, step: 16
866 11:03:54.109672 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
867 11:03:54.112925 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
868 11:03:54.116810 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
869 11:03:54.120247 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
870 11:03:54.123199 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
871 11:03:54.126725 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
872 11:03:54.133880 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
873 11:03:54.137777 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
874 11:03:54.139868 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
875 11:03:54.143314 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
876 11:03:54.146807 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
877 11:03:54.153316 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
878 11:03:54.157050 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
879 11:03:54.160804 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
880 11:03:54.163877 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
881 11:03:54.166921 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
882 11:03:54.167005 ==
883 11:03:54.170215 Dram Type= 6, Freq= 0, CH_0, rank 0
884 11:03:54.176905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
885 11:03:54.177005 ==
886 11:03:54.177066 DQS Delay:
887 11:03:54.180295 DQS0 = 0, DQS1 = 0
888 11:03:54.180376 DQM Delay:
889 11:03:54.180435 DQM0 = 85, DQM1 = 78
890 11:03:54.184264 DQ Delay:
891 11:03:54.187185 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
892 11:03:54.190052 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =85
893 11:03:54.194018 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =77
894 11:03:54.196984 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
895 11:03:54.197065
896 11:03:54.197148
897 11:03:54.197217 ==
898 11:03:54.200251 Dram Type= 6, Freq= 0, CH_0, rank 0
899 11:03:54.204024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 11:03:54.204111 ==
901 11:03:54.204169
902 11:03:54.204223
903 11:03:54.207351 TX Vref Scan disable
904 11:03:54.207428 == TX Byte 0 ==
905 11:03:54.213647 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
906 11:03:54.217648 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
907 11:03:54.217746 == TX Byte 1 ==
908 11:03:54.223672 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
909 11:03:54.227388 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
910 11:03:54.227504 ==
911 11:03:54.231019 Dram Type= 6, Freq= 0, CH_0, rank 0
912 11:03:54.234423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 11:03:54.234507 ==
914 11:03:54.248392 TX Vref=22, minBit 12, minWin=26, winSum=441
915 11:03:54.251767 TX Vref=24, minBit 7, minWin=27, winSum=445
916 11:03:54.255613 TX Vref=26, minBit 10, minWin=27, winSum=452
917 11:03:54.258514 TX Vref=28, minBit 8, minWin=27, winSum=453
918 11:03:54.262093 TX Vref=30, minBit 12, minWin=27, winSum=455
919 11:03:54.268515 TX Vref=32, minBit 12, minWin=27, winSum=454
920 11:03:54.272174 [TxChooseVref] Worse bit 12, Min win 27, Win sum 455, Final Vref 30
921 11:03:54.272266
922 11:03:54.275525 Final TX Range 1 Vref 30
923 11:03:54.275602
924 11:03:54.275660 ==
925 11:03:54.278324 Dram Type= 6, Freq= 0, CH_0, rank 0
926 11:03:54.281833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 11:03:54.281917 ==
928 11:03:54.285330
929 11:03:54.285409
930 11:03:54.285468 TX Vref Scan disable
931 11:03:54.288975 == TX Byte 0 ==
932 11:03:54.292178 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
933 11:03:54.295513 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
934 11:03:54.298844 == TX Byte 1 ==
935 11:03:54.302405 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
936 11:03:54.305375 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
937 11:03:54.308893
938 11:03:54.308975 [DATLAT]
939 11:03:54.309051 Freq=800, CH0 RK0
940 11:03:54.309109
941 11:03:54.312824 DATLAT Default: 0xa
942 11:03:54.312924 0, 0xFFFF, sum = 0
943 11:03:54.316193 1, 0xFFFF, sum = 0
944 11:03:54.316274 2, 0xFFFF, sum = 0
945 11:03:54.318774 3, 0xFFFF, sum = 0
946 11:03:54.318854 4, 0xFFFF, sum = 0
947 11:03:54.322359 5, 0xFFFF, sum = 0
948 11:03:54.322440 6, 0xFFFF, sum = 0
949 11:03:54.325676 7, 0xFFFF, sum = 0
950 11:03:54.325763 8, 0xFFFF, sum = 0
951 11:03:54.328935 9, 0x0, sum = 1
952 11:03:54.329016 10, 0x0, sum = 2
953 11:03:54.333120 11, 0x0, sum = 3
954 11:03:54.333209 12, 0x0, sum = 4
955 11:03:54.335891 best_step = 10
956 11:03:54.335998
957 11:03:54.336060 ==
958 11:03:54.339444 Dram Type= 6, Freq= 0, CH_0, rank 0
959 11:03:54.342442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 11:03:54.342521 ==
961 11:03:54.345861 RX Vref Scan: 1
962 11:03:54.345939
963 11:03:54.345998 Set Vref Range= 32 -> 127
964 11:03:54.346053
965 11:03:54.349164 RX Vref 32 -> 127, step: 1
966 11:03:54.349244
967 11:03:54.353040 RX Delay -95 -> 252, step: 8
968 11:03:54.353143
969 11:03:54.356317 Set Vref, RX VrefLevel [Byte0]: 32
970 11:03:54.359340 [Byte1]: 32
971 11:03:54.359419
972 11:03:54.362619 Set Vref, RX VrefLevel [Byte0]: 33
973 11:03:54.366012 [Byte1]: 33
974 11:03:54.366093
975 11:03:54.369246 Set Vref, RX VrefLevel [Byte0]: 34
976 11:03:54.373057 [Byte1]: 34
977 11:03:54.376590
978 11:03:54.376677 Set Vref, RX VrefLevel [Byte0]: 35
979 11:03:54.379805 [Byte1]: 35
980 11:03:54.384417
981 11:03:54.384505 Set Vref, RX VrefLevel [Byte0]: 36
982 11:03:54.387489 [Byte1]: 36
983 11:03:54.392058
984 11:03:54.392143 Set Vref, RX VrefLevel [Byte0]: 37
985 11:03:54.395789 [Byte1]: 37
986 11:03:54.399852
987 11:03:54.399955 Set Vref, RX VrefLevel [Byte0]: 38
988 11:03:54.402924 [Byte1]: 38
989 11:03:54.406956
990 11:03:54.407040 Set Vref, RX VrefLevel [Byte0]: 39
991 11:03:54.410661 [Byte1]: 39
992 11:03:54.414654
993 11:03:54.414755 Set Vref, RX VrefLevel [Byte0]: 40
994 11:03:54.417755 [Byte1]: 40
995 11:03:54.422671
996 11:03:54.422758 Set Vref, RX VrefLevel [Byte0]: 41
997 11:03:54.425448 [Byte1]: 41
998 11:03:54.430435
999 11:03:54.430532 Set Vref, RX VrefLevel [Byte0]: 42
1000 11:03:54.433395 [Byte1]: 42
1001 11:03:54.437337
1002 11:03:54.437422 Set Vref, RX VrefLevel [Byte0]: 43
1003 11:03:54.440854 [Byte1]: 43
1004 11:03:54.444769
1005 11:03:54.444854 Set Vref, RX VrefLevel [Byte0]: 44
1006 11:03:54.448688 [Byte1]: 44
1007 11:03:54.453413
1008 11:03:54.453500 Set Vref, RX VrefLevel [Byte0]: 45
1009 11:03:54.455920 [Byte1]: 45
1010 11:03:54.460189
1011 11:03:54.460271 Set Vref, RX VrefLevel [Byte0]: 46
1012 11:03:54.463611 [Byte1]: 46
1013 11:03:54.468398
1014 11:03:54.468480 Set Vref, RX VrefLevel [Byte0]: 47
1015 11:03:54.471312 [Byte1]: 47
1016 11:03:54.475331
1017 11:03:54.475416 Set Vref, RX VrefLevel [Byte0]: 48
1018 11:03:54.478733 [Byte1]: 48
1019 11:03:54.482855
1020 11:03:54.482935 Set Vref, RX VrefLevel [Byte0]: 49
1021 11:03:54.486626 [Byte1]: 49
1022 11:03:54.490536
1023 11:03:54.490613 Set Vref, RX VrefLevel [Byte0]: 50
1024 11:03:54.493878 [Byte1]: 50
1025 11:03:54.498279
1026 11:03:54.498356 Set Vref, RX VrefLevel [Byte0]: 51
1027 11:03:54.502303 [Byte1]: 51
1028 11:03:54.505644
1029 11:03:54.505725 Set Vref, RX VrefLevel [Byte0]: 52
1030 11:03:54.509420 [Byte1]: 52
1031 11:03:54.513423
1032 11:03:54.513505 Set Vref, RX VrefLevel [Byte0]: 53
1033 11:03:54.516818 [Byte1]: 53
1034 11:03:54.520967
1035 11:03:54.521050 Set Vref, RX VrefLevel [Byte0]: 54
1036 11:03:54.524300 [Byte1]: 54
1037 11:03:54.529134
1038 11:03:54.529231 Set Vref, RX VrefLevel [Byte0]: 55
1039 11:03:54.531916 [Byte1]: 55
1040 11:03:54.536124
1041 11:03:54.536219 Set Vref, RX VrefLevel [Byte0]: 56
1042 11:03:54.539398 [Byte1]: 56
1043 11:03:54.543956
1044 11:03:54.544037 Set Vref, RX VrefLevel [Byte0]: 57
1045 11:03:54.546907 [Byte1]: 57
1046 11:03:54.551697
1047 11:03:54.551783 Set Vref, RX VrefLevel [Byte0]: 58
1048 11:03:54.555192 [Byte1]: 58
1049 11:03:54.558733
1050 11:03:54.558814 Set Vref, RX VrefLevel [Byte0]: 59
1051 11:03:54.561954 [Byte1]: 59
1052 11:03:54.567039
1053 11:03:54.567122 Set Vref, RX VrefLevel [Byte0]: 60
1054 11:03:54.570182 [Byte1]: 60
1055 11:03:54.574109
1056 11:03:54.574217 Set Vref, RX VrefLevel [Byte0]: 61
1057 11:03:54.577990 [Byte1]: 61
1058 11:03:54.582277
1059 11:03:54.582364 Set Vref, RX VrefLevel [Byte0]: 62
1060 11:03:54.585079 [Byte1]: 62
1061 11:03:54.589991
1062 11:03:54.590078 Set Vref, RX VrefLevel [Byte0]: 63
1063 11:03:54.592753 [Byte1]: 63
1064 11:03:54.596858
1065 11:03:54.596942 Set Vref, RX VrefLevel [Byte0]: 64
1066 11:03:54.600246 [Byte1]: 64
1067 11:03:54.604433
1068 11:03:54.604518 Set Vref, RX VrefLevel [Byte0]: 65
1069 11:03:54.607702 [Byte1]: 65
1070 11:03:54.612222
1071 11:03:54.612304 Set Vref, RX VrefLevel [Byte0]: 66
1072 11:03:54.615509 [Byte1]: 66
1073 11:03:54.619476
1074 11:03:54.619562 Set Vref, RX VrefLevel [Byte0]: 67
1075 11:03:54.623248 [Byte1]: 67
1076 11:03:54.627494
1077 11:03:54.627578 Set Vref, RX VrefLevel [Byte0]: 68
1078 11:03:54.630366 [Byte1]: 68
1079 11:03:54.634935
1080 11:03:54.635020 Set Vref, RX VrefLevel [Byte0]: 69
1081 11:03:54.638522 [Byte1]: 69
1082 11:03:54.642438
1083 11:03:54.642524 Set Vref, RX VrefLevel [Byte0]: 70
1084 11:03:54.646121 [Byte1]: 70
1085 11:03:54.649977
1086 11:03:54.650063 Set Vref, RX VrefLevel [Byte0]: 71
1087 11:03:54.653461 [Byte1]: 71
1088 11:03:54.657584
1089 11:03:54.657667 Set Vref, RX VrefLevel [Byte0]: 72
1090 11:03:54.660822 [Byte1]: 72
1091 11:03:54.665321
1092 11:03:54.665406 Set Vref, RX VrefLevel [Byte0]: 73
1093 11:03:54.669030 [Byte1]: 73
1094 11:03:54.673642
1095 11:03:54.673730 Set Vref, RX VrefLevel [Byte0]: 74
1096 11:03:54.676056 [Byte1]: 74
1097 11:03:54.680632
1098 11:03:54.680719 Set Vref, RX VrefLevel [Byte0]: 75
1099 11:03:54.683945 [Byte1]: 75
1100 11:03:54.688330
1101 11:03:54.688414 Set Vref, RX VrefLevel [Byte0]: 76
1102 11:03:54.691366 [Byte1]: 76
1103 11:03:54.696022
1104 11:03:54.696107 Final RX Vref Byte 0 = 61 to rank0
1105 11:03:54.699424 Final RX Vref Byte 1 = 58 to rank0
1106 11:03:54.702645 Final RX Vref Byte 0 = 61 to rank1
1107 11:03:54.705817 Final RX Vref Byte 1 = 58 to rank1==
1108 11:03:54.709407 Dram Type= 6, Freq= 0, CH_0, rank 0
1109 11:03:54.712763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1110 11:03:54.715955 ==
1111 11:03:54.716040 DQS Delay:
1112 11:03:54.716100 DQS0 = 0, DQS1 = 0
1113 11:03:54.719414 DQM Delay:
1114 11:03:54.719493 DQM0 = 88, DQM1 = 79
1115 11:03:54.722644 DQ Delay:
1116 11:03:54.722757 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =80
1117 11:03:54.726146 DQ4 =92, DQ5 =76, DQ6 =96, DQ7 =96
1118 11:03:54.729463 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1119 11:03:54.733468 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1120 11:03:54.733569
1121 11:03:54.733630
1122 11:03:54.742811 [DQSOSCAuto] RK0, (LSB)MR18= 0x3119, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1123 11:03:54.746444 CH0 RK0: MR19=606, MR18=3119
1124 11:03:54.749351 CH0_RK0: MR19=0x606, MR18=0x3119, DQSOSC=397, MR23=63, INC=93, DEC=62
1125 11:03:54.753550
1126 11:03:54.756130 ----->DramcWriteLeveling(PI) begin...
1127 11:03:54.756213 ==
1128 11:03:54.759613 Dram Type= 6, Freq= 0, CH_0, rank 1
1129 11:03:54.763982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1130 11:03:54.764068 ==
1131 11:03:54.766449 Write leveling (Byte 0): 29 => 29
1132 11:03:54.769986 Write leveling (Byte 1): 28 => 28
1133 11:03:54.772889 DramcWriteLeveling(PI) end<-----
1134 11:03:54.772997
1135 11:03:54.773098 ==
1136 11:03:54.776283 Dram Type= 6, Freq= 0, CH_0, rank 1
1137 11:03:54.779489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1138 11:03:54.779624 ==
1139 11:03:54.783143 [Gating] SW mode calibration
1140 11:03:54.789518 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1141 11:03:54.793725 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1142 11:03:54.799720 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1143 11:03:54.802969 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1144 11:03:54.806809 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1145 11:03:54.814363 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 11:03:54.816949 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 11:03:54.820199 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 11:03:54.826831 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 11:03:54.830351 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 11:03:54.833590 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 11:03:54.836910 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 11:03:54.843848 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 11:03:54.847203 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 11:03:54.850309 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 11:03:54.857751 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 11:03:54.860753 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 11:03:54.863823 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 11:03:54.870637 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 11:03:54.873900 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1160 11:03:54.877442 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1161 11:03:54.883658 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:03:54.887243 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:03:54.929158 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:03:54.929581 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:03:54.930050 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:03:54.930146 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:03:54.930424 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:03:54.931117 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
1169 11:03:54.931400 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (1 1) (1 1)
1170 11:03:54.931748 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 11:03:54.931842 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 11:03:54.934633 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 11:03:54.937896 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 11:03:54.941113 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 11:03:54.944614 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
1176 11:03:54.948035 0 10 8 | B1->B0 | 3333 2929 | 1 0 | (1 0) (0 0)
1177 11:03:54.951658 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:03:54.957782 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:03:54.961573 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 11:03:54.964943 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 11:03:54.972263 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 11:03:54.974795 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 11:03:54.978192 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1184 11:03:54.984729 0 11 8 | B1->B0 | 3030 4343 | 0 0 | (1 1) (0 0)
1185 11:03:54.988097 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1186 11:03:54.991495 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 11:03:54.995542 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 11:03:55.002321 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 11:03:55.005998 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 11:03:55.009316 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 11:03:55.015673 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1192 11:03:55.018935 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1193 11:03:55.022659 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1194 11:03:55.028874 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 11:03:55.032602 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 11:03:55.035356 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 11:03:55.042136 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 11:03:55.045818 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 11:03:55.049108 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 11:03:55.052609 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 11:03:55.058937 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 11:03:55.062777 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 11:03:55.065738 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 11:03:55.072694 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 11:03:55.075893 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 11:03:55.079512 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:03:55.086319 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1208 11:03:55.089074 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1209 11:03:55.092847 Total UI for P1: 0, mck2ui 16
1210 11:03:55.096216 best dqsien dly found for B0: ( 0, 14, 4)
1211 11:03:55.099733 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 11:03:55.103055 Total UI for P1: 0, mck2ui 16
1213 11:03:55.106572 best dqsien dly found for B1: ( 0, 14, 10)
1214 11:03:55.109449 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1215 11:03:55.113345 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1216 11:03:55.113452
1217 11:03:55.116094 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1218 11:03:55.121006 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1219 11:03:55.122913 [Gating] SW calibration Done
1220 11:03:55.123012 ==
1221 11:03:55.126330 Dram Type= 6, Freq= 0, CH_0, rank 1
1222 11:03:55.132987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1223 11:03:55.133110 ==
1224 11:03:55.133207 RX Vref Scan: 0
1225 11:03:55.133288
1226 11:03:55.137109 RX Vref 0 -> 0, step: 1
1227 11:03:55.137219
1228 11:03:55.139806 RX Delay -130 -> 252, step: 16
1229 11:03:55.143190 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1230 11:03:55.146322 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1231 11:03:55.150082 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1232 11:03:55.153064 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1233 11:03:55.159775 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1234 11:03:55.163687 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1235 11:03:55.166563 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1236 11:03:55.169894 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1237 11:03:55.173667 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1238 11:03:55.176973 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1239 11:03:55.183351 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1240 11:03:55.187011 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1241 11:03:55.190230 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1242 11:03:55.193389 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1243 11:03:55.196838 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1244 11:03:55.203966 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1245 11:03:55.204092 ==
1246 11:03:55.206919 Dram Type= 6, Freq= 0, CH_0, rank 1
1247 11:03:55.210610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1248 11:03:55.210712 ==
1249 11:03:55.210795 DQS Delay:
1250 11:03:55.213579 DQS0 = 0, DQS1 = 0
1251 11:03:55.213680 DQM Delay:
1252 11:03:55.217023 DQM0 = 85, DQM1 = 74
1253 11:03:55.217130 DQ Delay:
1254 11:03:55.220523 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1255 11:03:55.223748 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1256 11:03:55.227250 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1257 11:03:55.230834 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =85
1258 11:03:55.230937
1259 11:03:55.231021
1260 11:03:55.231102 ==
1261 11:03:55.233951 Dram Type= 6, Freq= 0, CH_0, rank 1
1262 11:03:55.237379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1263 11:03:55.237480 ==
1264 11:03:55.237564
1265 11:03:55.237644
1266 11:03:55.240794 TX Vref Scan disable
1267 11:03:55.244530 == TX Byte 0 ==
1268 11:03:55.247183 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1269 11:03:55.250672 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1270 11:03:55.254121 == TX Byte 1 ==
1271 11:03:55.257521 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1272 11:03:55.260649 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1273 11:03:55.260754 ==
1274 11:03:55.264907 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 11:03:55.267628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 11:03:55.271006 ==
1277 11:03:55.282113 TX Vref=22, minBit 2, minWin=27, winSum=442
1278 11:03:55.285902 TX Vref=24, minBit 2, minWin=27, winSum=445
1279 11:03:55.289085 TX Vref=26, minBit 6, minWin=27, winSum=450
1280 11:03:55.292280 TX Vref=28, minBit 12, minWin=27, winSum=454
1281 11:03:55.296075 TX Vref=30, minBit 0, minWin=28, winSum=453
1282 11:03:55.299363 TX Vref=32, minBit 0, minWin=28, winSum=455
1283 11:03:55.305932 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 32
1284 11:03:55.306055
1285 11:03:55.309354 Final TX Range 1 Vref 32
1286 11:03:55.309456
1287 11:03:55.309541 ==
1288 11:03:55.312490 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 11:03:55.316035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 11:03:55.316140 ==
1291 11:03:55.316226
1292 11:03:55.316306
1293 11:03:55.319299 TX Vref Scan disable
1294 11:03:55.323455 == TX Byte 0 ==
1295 11:03:55.326006 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1296 11:03:55.329453 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1297 11:03:55.332683 == TX Byte 1 ==
1298 11:03:55.336508 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1299 11:03:55.339191 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1300 11:03:55.339294
1301 11:03:55.343232 [DATLAT]
1302 11:03:55.343336 Freq=800, CH0 RK1
1303 11:03:55.343422
1304 11:03:55.346304 DATLAT Default: 0xa
1305 11:03:55.346405 0, 0xFFFF, sum = 0
1306 11:03:55.349453 1, 0xFFFF, sum = 0
1307 11:03:55.349563 2, 0xFFFF, sum = 0
1308 11:03:55.352915 3, 0xFFFF, sum = 0
1309 11:03:55.353017 4, 0xFFFF, sum = 0
1310 11:03:55.356020 5, 0xFFFF, sum = 0
1311 11:03:55.356122 6, 0xFFFF, sum = 0
1312 11:03:55.359299 7, 0xFFFF, sum = 0
1313 11:03:55.359400 8, 0xFFFF, sum = 0
1314 11:03:55.362720 9, 0x0, sum = 1
1315 11:03:55.362818 10, 0x0, sum = 2
1316 11:03:55.366955 11, 0x0, sum = 3
1317 11:03:55.367059 12, 0x0, sum = 4
1318 11:03:55.369562 best_step = 10
1319 11:03:55.369658
1320 11:03:55.369741 ==
1321 11:03:55.373322 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 11:03:55.376614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 11:03:55.376719 ==
1324 11:03:55.376802 RX Vref Scan: 0
1325 11:03:55.376882
1326 11:03:55.379709 RX Vref 0 -> 0, step: 1
1327 11:03:55.379804
1328 11:03:55.382834 RX Delay -95 -> 252, step: 8
1329 11:03:55.386833 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1330 11:03:55.393269 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1331 11:03:55.396473 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1332 11:03:55.400364 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1333 11:03:55.403254 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1334 11:03:55.406437 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1335 11:03:55.410082 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1336 11:03:55.416992 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1337 11:03:55.420395 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1338 11:03:55.423182 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1339 11:03:55.426675 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1340 11:03:55.430311 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1341 11:03:55.436706 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1342 11:03:55.440134 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1343 11:03:55.443612 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1344 11:03:55.447191 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1345 11:03:55.447301 ==
1346 11:03:55.451241 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 11:03:55.457509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 11:03:55.457630 ==
1349 11:03:55.457715 DQS Delay:
1350 11:03:55.457795 DQS0 = 0, DQS1 = 0
1351 11:03:55.460737 DQM Delay:
1352 11:03:55.460834 DQM0 = 87, DQM1 = 77
1353 11:03:55.463809 DQ Delay:
1354 11:03:55.466950 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1355 11:03:55.467050 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1356 11:03:55.471229 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1357 11:03:55.473590 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1358 11:03:55.477547
1359 11:03:55.477653
1360 11:03:55.484222 [DQSOSCAuto] RK1, (LSB)MR18= 0x3620, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1361 11:03:55.486975 CH0 RK1: MR19=606, MR18=3620
1362 11:03:55.494508 CH0_RK1: MR19=0x606, MR18=0x3620, DQSOSC=396, MR23=63, INC=94, DEC=62
1363 11:03:55.494639 [RxdqsGatingPostProcess] freq 800
1364 11:03:55.500866 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1365 11:03:55.504630 Pre-setting of DQS Precalculation
1366 11:03:55.507495 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1367 11:03:55.511209 ==
1368 11:03:55.511318 Dram Type= 6, Freq= 0, CH_1, rank 0
1369 11:03:55.517876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 11:03:55.517997 ==
1371 11:03:55.521526 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1372 11:03:55.527936 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1373 11:03:55.537028 [CA 0] Center 36 (6~66) winsize 61
1374 11:03:55.540491 [CA 1] Center 36 (6~67) winsize 62
1375 11:03:55.543851 [CA 2] Center 34 (4~65) winsize 62
1376 11:03:55.547001 [CA 3] Center 33 (3~64) winsize 62
1377 11:03:55.551145 [CA 4] Center 34 (3~65) winsize 63
1378 11:03:55.553963 [CA 5] Center 33 (3~64) winsize 62
1379 11:03:55.554065
1380 11:03:55.557551 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1381 11:03:55.557651
1382 11:03:55.560952 [CATrainingPosCal] consider 1 rank data
1383 11:03:55.564007 u2DelayCellTimex100 = 270/100 ps
1384 11:03:55.567395 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1385 11:03:55.570640 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1386 11:03:55.574076 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1387 11:03:55.581433 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1388 11:03:55.584156 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1389 11:03:55.587879 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1390 11:03:55.587991
1391 11:03:55.590953 CA PerBit enable=1, Macro0, CA PI delay=33
1392 11:03:55.591050
1393 11:03:55.594480 [CBTSetCACLKResult] CA Dly = 33
1394 11:03:55.594578 CS Dly: 5 (0~36)
1395 11:03:55.594662 ==
1396 11:03:55.597897 Dram Type= 6, Freq= 0, CH_1, rank 1
1397 11:03:55.604061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1398 11:03:55.604178 ==
1399 11:03:55.607680 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1400 11:03:55.614159 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1401 11:03:55.622984 [CA 0] Center 36 (6~66) winsize 61
1402 11:03:55.626746 [CA 1] Center 36 (6~67) winsize 62
1403 11:03:55.630480 [CA 2] Center 34 (4~64) winsize 61
1404 11:03:55.633144 [CA 3] Center 33 (3~64) winsize 62
1405 11:03:55.636578 [CA 4] Center 34 (4~65) winsize 62
1406 11:03:55.640009 [CA 5] Center 33 (3~64) winsize 62
1407 11:03:55.640117
1408 11:03:55.643338 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1409 11:03:55.643438
1410 11:03:55.646852 [CATrainingPosCal] consider 2 rank data
1411 11:03:55.650269 u2DelayCellTimex100 = 270/100 ps
1412 11:03:55.654581 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1413 11:03:55.656576 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1414 11:03:55.660473 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1415 11:03:55.666817 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1416 11:03:55.670352 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1417 11:03:55.673515 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1418 11:03:55.673619
1419 11:03:55.677226 CA PerBit enable=1, Macro0, CA PI delay=33
1420 11:03:55.677331
1421 11:03:55.680633 [CBTSetCACLKResult] CA Dly = 33
1422 11:03:55.680734 CS Dly: 5 (0~37)
1423 11:03:55.680818
1424 11:03:55.683917 ----->DramcWriteLeveling(PI) begin...
1425 11:03:55.684018 ==
1426 11:03:55.687915 Dram Type= 6, Freq= 0, CH_1, rank 0
1427 11:03:55.694215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1428 11:03:55.694333 ==
1429 11:03:55.697071 Write leveling (Byte 0): 27 => 27
1430 11:03:55.700305 Write leveling (Byte 1): 28 => 28
1431 11:03:55.700404 DramcWriteLeveling(PI) end<-----
1432 11:03:55.700489
1433 11:03:55.703965 ==
1434 11:03:55.704067 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 11:03:55.710684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 11:03:55.710809 ==
1437 11:03:55.713571 [Gating] SW mode calibration
1438 11:03:55.720388 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1439 11:03:55.724454 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1440 11:03:55.730029 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1441 11:03:55.734212 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1442 11:03:55.736989 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1443 11:03:55.744275 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 11:03:55.747931 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 11:03:55.750365 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 11:03:55.754399 0 6 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1447 11:03:55.760413 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 11:03:55.764426 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 11:03:55.767626 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 11:03:55.774032 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 11:03:55.777902 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 11:03:55.780681 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 11:03:55.787913 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:03:55.791545 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1455 11:03:55.793826 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1456 11:03:55.800692 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1457 11:03:55.804059 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1458 11:03:55.807884 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:03:55.811032 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:03:55.817859 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:03:55.821275 0 8 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1462 11:03:55.824633 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:03:55.831152 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:03:55.834382 0 9 0 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
1465 11:03:55.837898 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:03:55.844739 0 9 8 | B1->B0 | 2a2a 2d2d | 1 1 | (1 1) (0 0)
1467 11:03:55.848052 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 11:03:55.851047 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 11:03:55.858134 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 11:03:55.861253 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 11:03:55.864823 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 11:03:55.867789 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 11:03:55.874439 0 10 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1474 11:03:55.878472 0 10 8 | B1->B0 | 2f2f 3030 | 0 0 | (0 1) (0 1)
1475 11:03:55.881548 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:03:55.888488 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:03:55.892135 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 11:03:55.894884 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 11:03:55.901711 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 11:03:55.904848 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1481 11:03:55.908272 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1482 11:03:55.912009 0 11 8 | B1->B0 | 3737 3434 | 0 1 | (0 0) (0 0)
1483 11:03:55.918734 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 11:03:55.921623 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 11:03:55.925486 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 11:03:55.931693 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 11:03:55.935498 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 11:03:55.939035 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 11:03:55.945888 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 11:03:55.948667 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1491 11:03:55.952116 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 11:03:55.958980 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 11:03:55.962715 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 11:03:55.965580 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 11:03:55.972132 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 11:03:55.975777 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 11:03:55.979335 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 11:03:55.982224 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 11:03:55.988927 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 11:03:55.992344 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 11:03:55.995592 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 11:03:56.002914 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 11:03:56.006031 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 11:03:56.009050 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 11:03:56.016073 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 11:03:56.019227 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1507 11:03:56.022503 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 11:03:56.026233 Total UI for P1: 0, mck2ui 16
1509 11:03:56.029542 best dqsien dly found for B0: ( 0, 14, 8)
1510 11:03:56.032690 Total UI for P1: 0, mck2ui 16
1511 11:03:56.036179 best dqsien dly found for B1: ( 0, 14, 8)
1512 11:03:56.039321 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1513 11:03:56.042745 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1514 11:03:56.042853
1515 11:03:56.046495 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1516 11:03:56.049624 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1517 11:03:56.053029 [Gating] SW calibration Done
1518 11:03:56.053147 ==
1519 11:03:56.056131 Dram Type= 6, Freq= 0, CH_1, rank 0
1520 11:03:56.059915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1521 11:03:56.063074 ==
1522 11:03:56.063180 RX Vref Scan: 0
1523 11:03:56.063264
1524 11:03:56.066107 RX Vref 0 -> 0, step: 1
1525 11:03:56.066209
1526 11:03:56.069493 RX Delay -130 -> 252, step: 16
1527 11:03:56.074220 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1528 11:03:56.075977 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1529 11:03:56.079746 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1530 11:03:56.082858 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1531 11:03:56.090057 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1532 11:03:56.093033 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1533 11:03:56.096272 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1534 11:03:56.099835 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1535 11:03:56.103124 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1536 11:03:56.106219 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1537 11:03:56.113313 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1538 11:03:56.116276 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1539 11:03:56.120040 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1540 11:03:56.123190 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1541 11:03:56.126497 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1542 11:03:56.133471 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1543 11:03:56.133600 ==
1544 11:03:56.137317 Dram Type= 6, Freq= 0, CH_1, rank 0
1545 11:03:56.140008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1546 11:03:56.140112 ==
1547 11:03:56.140196 DQS Delay:
1548 11:03:56.143661 DQS0 = 0, DQS1 = 0
1549 11:03:56.143765 DQM Delay:
1550 11:03:56.146849 DQM0 = 82, DQM1 = 74
1551 11:03:56.146947 DQ Delay:
1552 11:03:56.150184 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1553 11:03:56.154583 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =69
1554 11:03:56.156685 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1555 11:03:56.160435 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1556 11:03:56.160548
1557 11:03:56.160658
1558 11:03:56.160812 ==
1559 11:03:56.163382 Dram Type= 6, Freq= 0, CH_1, rank 0
1560 11:03:56.166963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1561 11:03:56.167068 ==
1562 11:03:56.167154
1563 11:03:56.167235
1564 11:03:56.170345 TX Vref Scan disable
1565 11:03:56.173739 == TX Byte 0 ==
1566 11:03:56.177271 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1567 11:03:56.180329 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1568 11:03:56.183547 == TX Byte 1 ==
1569 11:03:56.187373 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1570 11:03:56.190209 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1571 11:03:56.190316 ==
1572 11:03:56.193665 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 11:03:56.197196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 11:03:56.200237 ==
1575 11:03:56.213281 TX Vref=22, minBit 10, minWin=26, winSum=435
1576 11:03:56.214768 TX Vref=24, minBit 0, minWin=27, winSum=441
1577 11:03:56.218509 TX Vref=26, minBit 0, minWin=27, winSum=444
1578 11:03:56.221682 TX Vref=28, minBit 0, minWin=28, winSum=449
1579 11:03:56.225034 TX Vref=30, minBit 11, minWin=27, winSum=452
1580 11:03:56.228402 TX Vref=32, minBit 0, minWin=28, winSum=451
1581 11:03:56.235218 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 32
1582 11:03:56.235341
1583 11:03:56.238603 Final TX Range 1 Vref 32
1584 11:03:56.238705
1585 11:03:56.238789 ==
1586 11:03:56.241947 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 11:03:56.245192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 11:03:56.245294 ==
1589 11:03:56.245378
1590 11:03:56.245458
1591 11:03:56.248538 TX Vref Scan disable
1592 11:03:56.252181 == TX Byte 0 ==
1593 11:03:56.255664 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1594 11:03:56.259023 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1595 11:03:56.262257 == TX Byte 1 ==
1596 11:03:56.265776 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1597 11:03:56.268679 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1598 11:03:56.268780
1599 11:03:56.272145 [DATLAT]
1600 11:03:56.272247 Freq=800, CH1 RK0
1601 11:03:56.272334
1602 11:03:56.275212 DATLAT Default: 0xa
1603 11:03:56.275310 0, 0xFFFF, sum = 0
1604 11:03:56.279268 1, 0xFFFF, sum = 0
1605 11:03:56.279372 2, 0xFFFF, sum = 0
1606 11:03:56.281956 3, 0xFFFF, sum = 0
1607 11:03:56.282056 4, 0xFFFF, sum = 0
1608 11:03:56.286196 5, 0xFFFF, sum = 0
1609 11:03:56.286294 6, 0xFFFF, sum = 0
1610 11:03:56.289087 7, 0xFFFF, sum = 0
1611 11:03:56.289227 8, 0xFFFF, sum = 0
1612 11:03:56.292834 9, 0x0, sum = 1
1613 11:03:56.292934 10, 0x0, sum = 2
1614 11:03:56.296031 11, 0x0, sum = 3
1615 11:03:56.296130 12, 0x0, sum = 4
1616 11:03:56.299445 best_step = 10
1617 11:03:56.299547
1618 11:03:56.299632 ==
1619 11:03:56.302341 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 11:03:56.305840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 11:03:56.305943 ==
1622 11:03:56.306027 RX Vref Scan: 1
1623 11:03:56.309432
1624 11:03:56.309530 Set Vref Range= 32 -> 127
1625 11:03:56.309614
1626 11:03:56.312934 RX Vref 32 -> 127, step: 1
1627 11:03:56.313032
1628 11:03:56.315888 RX Delay -111 -> 252, step: 8
1629 11:03:56.315967
1630 11:03:56.319164 Set Vref, RX VrefLevel [Byte0]: 32
1631 11:03:56.322680 [Byte1]: 32
1632 11:03:56.322778
1633 11:03:56.325790 Set Vref, RX VrefLevel [Byte0]: 33
1634 11:03:56.329712 [Byte1]: 33
1635 11:03:56.332177
1636 11:03:56.332254 Set Vref, RX VrefLevel [Byte0]: 34
1637 11:03:56.335735 [Byte1]: 34
1638 11:03:56.340482
1639 11:03:56.340567 Set Vref, RX VrefLevel [Byte0]: 35
1640 11:03:56.343134 [Byte1]: 35
1641 11:03:56.347647
1642 11:03:56.347732 Set Vref, RX VrefLevel [Byte0]: 36
1643 11:03:56.351176 [Byte1]: 36
1644 11:03:56.355372
1645 11:03:56.355461 Set Vref, RX VrefLevel [Byte0]: 37
1646 11:03:56.358548 [Byte1]: 37
1647 11:03:56.363112
1648 11:03:56.363200 Set Vref, RX VrefLevel [Byte0]: 38
1649 11:03:56.366241 [Byte1]: 38
1650 11:03:56.370474
1651 11:03:56.370557 Set Vref, RX VrefLevel [Byte0]: 39
1652 11:03:56.373903 [Byte1]: 39
1653 11:03:56.377990
1654 11:03:56.378075 Set Vref, RX VrefLevel [Byte0]: 40
1655 11:03:56.381594 [Byte1]: 40
1656 11:03:56.386311
1657 11:03:56.386401 Set Vref, RX VrefLevel [Byte0]: 41
1658 11:03:56.389504 [Byte1]: 41
1659 11:03:56.393439
1660 11:03:56.393552 Set Vref, RX VrefLevel [Byte0]: 42
1661 11:03:56.396972 [Byte1]: 42
1662 11:03:56.401493
1663 11:03:56.401584 Set Vref, RX VrefLevel [Byte0]: 43
1664 11:03:56.404512 [Byte1]: 43
1665 11:03:56.408760
1666 11:03:56.408839 Set Vref, RX VrefLevel [Byte0]: 44
1667 11:03:56.411908 [Byte1]: 44
1668 11:03:56.416597
1669 11:03:56.416680 Set Vref, RX VrefLevel [Byte0]: 45
1670 11:03:56.420203 [Byte1]: 45
1671 11:03:56.423997
1672 11:03:56.424079 Set Vref, RX VrefLevel [Byte0]: 46
1673 11:03:56.428159 [Byte1]: 46
1674 11:03:56.431726
1675 11:03:56.431805 Set Vref, RX VrefLevel [Byte0]: 47
1676 11:03:56.435497 [Byte1]: 47
1677 11:03:56.439774
1678 11:03:56.439857 Set Vref, RX VrefLevel [Byte0]: 48
1679 11:03:56.442889 [Byte1]: 48
1680 11:03:56.446838
1681 11:03:56.446918 Set Vref, RX VrefLevel [Byte0]: 49
1682 11:03:56.450911 [Byte1]: 49
1683 11:03:56.454872
1684 11:03:56.454956 Set Vref, RX VrefLevel [Byte0]: 50
1685 11:03:56.458207 [Byte1]: 50
1686 11:03:56.462119
1687 11:03:56.462199 Set Vref, RX VrefLevel [Byte0]: 51
1688 11:03:56.465388 [Byte1]: 51
1689 11:03:56.469985
1690 11:03:56.470068 Set Vref, RX VrefLevel [Byte0]: 52
1691 11:03:56.473039 [Byte1]: 52
1692 11:03:56.477692
1693 11:03:56.477779 Set Vref, RX VrefLevel [Byte0]: 53
1694 11:03:56.481011 [Byte1]: 53
1695 11:03:56.485768
1696 11:03:56.485859 Set Vref, RX VrefLevel [Byte0]: 54
1697 11:03:56.488552 [Byte1]: 54
1698 11:03:56.493093
1699 11:03:56.493205 Set Vref, RX VrefLevel [Byte0]: 55
1700 11:03:56.496477 [Byte1]: 55
1701 11:03:56.500412
1702 11:03:56.500493 Set Vref, RX VrefLevel [Byte0]: 56
1703 11:03:56.503800 [Byte1]: 56
1704 11:03:56.509322
1705 11:03:56.509408 Set Vref, RX VrefLevel [Byte0]: 57
1706 11:03:56.512160 [Byte1]: 57
1707 11:03:56.515629
1708 11:03:56.515710 Set Vref, RX VrefLevel [Byte0]: 58
1709 11:03:56.519875 [Byte1]: 58
1710 11:03:56.523611
1711 11:03:56.523695 Set Vref, RX VrefLevel [Byte0]: 59
1712 11:03:56.526919 [Byte1]: 59
1713 11:03:56.531251
1714 11:03:56.531333 Set Vref, RX VrefLevel [Byte0]: 60
1715 11:03:56.534215 [Byte1]: 60
1716 11:03:56.539141
1717 11:03:56.539225 Set Vref, RX VrefLevel [Byte0]: 61
1718 11:03:56.541924 [Byte1]: 61
1719 11:03:56.547690
1720 11:03:56.547781 Set Vref, RX VrefLevel [Byte0]: 62
1721 11:03:56.550057 [Byte1]: 62
1722 11:03:56.553917
1723 11:03:56.554013 Set Vref, RX VrefLevel [Byte0]: 63
1724 11:03:56.557738 [Byte1]: 63
1725 11:03:56.561679
1726 11:03:56.561763 Set Vref, RX VrefLevel [Byte0]: 64
1727 11:03:56.565086 [Byte1]: 64
1728 11:03:56.569424
1729 11:03:56.569529 Set Vref, RX VrefLevel [Byte0]: 65
1730 11:03:56.572733 [Byte1]: 65
1731 11:03:56.577029
1732 11:03:56.577160 Set Vref, RX VrefLevel [Byte0]: 66
1733 11:03:56.580384 [Byte1]: 66
1734 11:03:56.585312
1735 11:03:56.585413 Set Vref, RX VrefLevel [Byte0]: 67
1736 11:03:56.588048 [Byte1]: 67
1737 11:03:56.592129
1738 11:03:56.592212 Set Vref, RX VrefLevel [Byte0]: 68
1739 11:03:56.595579 [Byte1]: 68
1740 11:03:56.600133
1741 11:03:56.600217 Set Vref, RX VrefLevel [Byte0]: 69
1742 11:03:56.603248 [Byte1]: 69
1743 11:03:56.607521
1744 11:03:56.607602 Set Vref, RX VrefLevel [Byte0]: 70
1745 11:03:56.610824 [Byte1]: 70
1746 11:03:56.615359
1747 11:03:56.615462 Set Vref, RX VrefLevel [Byte0]: 71
1748 11:03:56.618713 [Byte1]: 71
1749 11:03:56.623401
1750 11:03:56.623483 Set Vref, RX VrefLevel [Byte0]: 72
1751 11:03:56.626388 [Byte1]: 72
1752 11:03:56.630476
1753 11:03:56.630560 Set Vref, RX VrefLevel [Byte0]: 73
1754 11:03:56.634212 [Byte1]: 73
1755 11:03:56.638912
1756 11:03:56.639000 Set Vref, RX VrefLevel [Byte0]: 74
1757 11:03:56.641627 [Byte1]: 74
1758 11:03:56.645715
1759 11:03:56.645798 Set Vref, RX VrefLevel [Byte0]: 75
1760 11:03:56.649422 [Byte1]: 75
1761 11:03:56.653401
1762 11:03:56.653489 Set Vref, RX VrefLevel [Byte0]: 76
1763 11:03:56.656602 [Byte1]: 76
1764 11:03:56.661324
1765 11:03:56.661411 Set Vref, RX VrefLevel [Byte0]: 77
1766 11:03:56.664233 [Byte1]: 77
1767 11:03:56.668851
1768 11:03:56.668936 Set Vref, RX VrefLevel [Byte0]: 78
1769 11:03:56.672272 [Byte1]: 78
1770 11:03:56.676197
1771 11:03:56.676284 Final RX Vref Byte 0 = 57 to rank0
1772 11:03:56.680002 Final RX Vref Byte 1 = 60 to rank0
1773 11:03:56.683193 Final RX Vref Byte 0 = 57 to rank1
1774 11:03:56.686293 Final RX Vref Byte 1 = 60 to rank1==
1775 11:03:56.689997 Dram Type= 6, Freq= 0, CH_1, rank 0
1776 11:03:56.693805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1777 11:03:56.696409 ==
1778 11:03:56.696497 DQS Delay:
1779 11:03:56.696560 DQS0 = 0, DQS1 = 0
1780 11:03:56.699678 DQM Delay:
1781 11:03:56.699755 DQM0 = 83, DQM1 = 74
1782 11:03:56.703508 DQ Delay:
1783 11:03:56.703590 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1784 11:03:56.706522 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =76
1785 11:03:56.709876 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1786 11:03:56.713091 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =76
1787 11:03:56.713213
1788 11:03:56.716355
1789 11:03:56.723413 [DQSOSCAuto] RK0, (LSB)MR18= 0x3004, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 397 ps
1790 11:03:56.726654 CH1 RK0: MR19=606, MR18=3004
1791 11:03:56.733635 CH1_RK0: MR19=0x606, MR18=0x3004, DQSOSC=397, MR23=63, INC=93, DEC=62
1792 11:03:56.733762
1793 11:03:56.736697 ----->DramcWriteLeveling(PI) begin...
1794 11:03:56.736788 ==
1795 11:03:56.739966 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 11:03:56.743580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1797 11:03:56.743663 ==
1798 11:03:56.746940 Write leveling (Byte 0): 28 => 28
1799 11:03:56.750171 Write leveling (Byte 1): 30 => 30
1800 11:03:56.753763 DramcWriteLeveling(PI) end<-----
1801 11:03:56.753847
1802 11:03:56.753906 ==
1803 11:03:56.756877 Dram Type= 6, Freq= 0, CH_1, rank 1
1804 11:03:56.760806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1805 11:03:56.760890 ==
1806 11:03:56.763699 [Gating] SW mode calibration
1807 11:03:56.770347 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1808 11:03:56.776934 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1809 11:03:56.780345 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1810 11:03:56.783469 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1811 11:03:56.787239 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1812 11:03:56.793792 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 11:03:56.797159 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 11:03:56.801276 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 11:03:56.807080 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:03:56.810357 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:03:56.813968 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:03:56.820853 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 11:03:56.823836 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:03:56.828232 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 11:03:56.834261 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:03:56.837091 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:03:56.841234 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:03:56.844160 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:03:56.851186 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1826 11:03:56.854270 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 11:03:56.859189 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:03:56.864112 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 11:03:56.867450 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 11:03:56.870956 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 11:03:56.877563 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 11:03:56.881073 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 11:03:56.884671 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 11:03:56.891250 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1835 11:03:56.894267 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1836 11:03:56.897542 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 11:03:56.901340 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 11:03:56.908252 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 11:03:56.911358 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 11:03:56.914699 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 11:03:56.921047 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 11:03:56.924715 0 10 4 | B1->B0 | 2f2f 2a2a | 1 1 | (1 1) (1 0)
1843 11:03:56.928203 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1844 11:03:56.935328 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 11:03:56.937897 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 11:03:56.941353 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 11:03:56.948592 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 11:03:56.951707 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 11:03:56.955199 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1850 11:03:56.958287 0 11 4 | B1->B0 | 2929 3b3b | 0 0 | (0 0) (0 0)
1851 11:03:56.965281 0 11 8 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
1852 11:03:56.968401 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 11:03:56.971528 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 11:03:56.979270 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 11:03:56.981855 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 11:03:56.984684 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 11:03:56.991622 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1858 11:03:56.994839 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1859 11:03:56.999048 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1860 11:03:57.005710 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 11:03:57.008720 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 11:03:57.011602 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 11:03:57.019292 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 11:03:57.023358 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:03:57.025951 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 11:03:57.028497 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 11:03:57.035434 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 11:03:57.038770 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 11:03:57.041949 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 11:03:57.048740 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 11:03:57.051993 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 11:03:57.055407 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 11:03:57.062414 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 11:03:57.065451 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1875 11:03:57.069444 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 11:03:57.072422 Total UI for P1: 0, mck2ui 16
1877 11:03:57.075766 best dqsien dly found for B0: ( 0, 14, 4)
1878 11:03:57.078812 Total UI for P1: 0, mck2ui 16
1879 11:03:57.082531 best dqsien dly found for B1: ( 0, 14, 6)
1880 11:03:57.085998 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1881 11:03:57.089753 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1882 11:03:57.089838
1883 11:03:57.092208 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1884 11:03:57.095564 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1885 11:03:57.098970 [Gating] SW calibration Done
1886 11:03:57.099058 ==
1887 11:03:57.102275 Dram Type= 6, Freq= 0, CH_1, rank 1
1888 11:03:57.106186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1889 11:03:57.109519 ==
1890 11:03:57.109608 RX Vref Scan: 0
1891 11:03:57.109670
1892 11:03:57.113006 RX Vref 0 -> 0, step: 1
1893 11:03:57.113109
1894 11:03:57.116062 RX Delay -130 -> 252, step: 16
1895 11:03:57.119480 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1896 11:03:57.122891 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1897 11:03:57.126042 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1898 11:03:57.129342 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
1899 11:03:57.135889 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1900 11:03:57.140457 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1901 11:03:57.143001 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1902 11:03:57.146368 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1903 11:03:57.149731 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1904 11:03:57.153113 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1905 11:03:57.159954 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1906 11:03:57.162913 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1907 11:03:57.166371 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1908 11:03:57.170035 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1909 11:03:57.173242 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1910 11:03:57.180139 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1911 11:03:57.180286 ==
1912 11:03:57.183161 Dram Type= 6, Freq= 0, CH_1, rank 1
1913 11:03:57.186382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1914 11:03:57.186491 ==
1915 11:03:57.186577 DQS Delay:
1916 11:03:57.190099 DQS0 = 0, DQS1 = 0
1917 11:03:57.190199 DQM Delay:
1918 11:03:57.193618 DQM0 = 78, DQM1 = 77
1919 11:03:57.193722 DQ Delay:
1920 11:03:57.196965 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1921 11:03:57.200084 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =69
1922 11:03:57.203376 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1923 11:03:57.206833 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1924 11:03:57.206951
1925 11:03:57.207037
1926 11:03:57.207117 ==
1927 11:03:57.210389 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 11:03:57.213347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 11:03:57.213433 ==
1930 11:03:57.213496
1931 11:03:57.213550
1932 11:03:57.217414 TX Vref Scan disable
1933 11:03:57.220014 == TX Byte 0 ==
1934 11:03:57.223492 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1935 11:03:57.227048 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1936 11:03:57.230053 == TX Byte 1 ==
1937 11:03:57.234250 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1938 11:03:57.236706 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1939 11:03:57.236829 ==
1940 11:03:57.240254 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 11:03:57.244227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 11:03:57.247732 ==
1943 11:03:57.258221 TX Vref=22, minBit 8, minWin=27, winSum=445
1944 11:03:57.261299 TX Vref=24, minBit 1, minWin=27, winSum=446
1945 11:03:57.264716 TX Vref=26, minBit 1, minWin=27, winSum=449
1946 11:03:57.268907 TX Vref=28, minBit 15, minWin=27, winSum=450
1947 11:03:57.271850 TX Vref=30, minBit 0, minWin=28, winSum=452
1948 11:03:57.275055 TX Vref=32, minBit 0, minWin=28, winSum=454
1949 11:03:57.281840 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 32
1950 11:03:57.282006
1951 11:03:57.285027 Final TX Range 1 Vref 32
1952 11:03:57.285165
1953 11:03:57.285289 ==
1954 11:03:57.288427 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 11:03:57.291997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 11:03:57.292101 ==
1957 11:03:57.292190
1958 11:03:57.292270
1959 11:03:57.295138 TX Vref Scan disable
1960 11:03:57.299793 == TX Byte 0 ==
1961 11:03:57.301822 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1962 11:03:57.305730 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1963 11:03:57.308140 == TX Byte 1 ==
1964 11:03:57.313031 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1965 11:03:57.315417 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1966 11:03:57.315521
1967 11:03:57.318743 [DATLAT]
1968 11:03:57.318849 Freq=800, CH1 RK1
1969 11:03:57.318934
1970 11:03:57.321972 DATLAT Default: 0xa
1971 11:03:57.322066 0, 0xFFFF, sum = 0
1972 11:03:57.325303 1, 0xFFFF, sum = 0
1973 11:03:57.325400 2, 0xFFFF, sum = 0
1974 11:03:57.328311 3, 0xFFFF, sum = 0
1975 11:03:57.328404 4, 0xFFFF, sum = 0
1976 11:03:57.331927 5, 0xFFFF, sum = 0
1977 11:03:57.332024 6, 0xFFFF, sum = 0
1978 11:03:57.335034 7, 0xFFFF, sum = 0
1979 11:03:57.335123 8, 0xFFFF, sum = 0
1980 11:03:57.338597 9, 0x0, sum = 1
1981 11:03:57.338707 10, 0x0, sum = 2
1982 11:03:57.341671 11, 0x0, sum = 3
1983 11:03:57.341772 12, 0x0, sum = 4
1984 11:03:57.345106 best_step = 10
1985 11:03:57.345230
1986 11:03:57.345336 ==
1987 11:03:57.348645 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 11:03:57.351844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 11:03:57.351933 ==
1990 11:03:57.355736 RX Vref Scan: 0
1991 11:03:57.355844
1992 11:03:57.355918 RX Vref 0 -> 0, step: 1
1993 11:03:57.355990
1994 11:03:57.358627 RX Delay -95 -> 252, step: 8
1995 11:03:57.361989 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1996 11:03:57.369054 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
1997 11:03:57.372159 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
1998 11:03:57.375544 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
1999 11:03:57.379179 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2000 11:03:57.382730 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2001 11:03:57.389228 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2002 11:03:57.392153 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2003 11:03:57.396148 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2004 11:03:57.399786 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2005 11:03:57.402168 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2006 11:03:57.409279 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2007 11:03:57.412266 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
2008 11:03:57.416005 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2009 11:03:57.419408 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2010 11:03:57.422173 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2011 11:03:57.425560 ==
2012 11:03:57.425644 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 11:03:57.433307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 11:03:57.433404 ==
2015 11:03:57.433468 DQS Delay:
2016 11:03:57.435641 DQS0 = 0, DQS1 = 0
2017 11:03:57.435718 DQM Delay:
2018 11:03:57.435776 DQM0 = 80, DQM1 = 76
2019 11:03:57.439083 DQ Delay:
2020 11:03:57.442640 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2021 11:03:57.445755 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2022 11:03:57.449100 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2023 11:03:57.452691 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
2024 11:03:57.452798
2025 11:03:57.452859
2026 11:03:57.459475 [DQSOSCAuto] RK1, (LSB)MR18= 0x2934, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
2027 11:03:57.463780 CH1 RK1: MR19=606, MR18=2934
2028 11:03:57.469850 CH1_RK1: MR19=0x606, MR18=0x2934, DQSOSC=396, MR23=63, INC=94, DEC=62
2029 11:03:57.472937 [RxdqsGatingPostProcess] freq 800
2030 11:03:57.476303 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2031 11:03:57.479261 Pre-setting of DQS Precalculation
2032 11:03:57.486037 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2033 11:03:57.492883 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2034 11:03:57.499708 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2035 11:03:57.499814
2036 11:03:57.499873
2037 11:03:57.503356 [Calibration Summary] 1600 Mbps
2038 11:03:57.503435 CH 0, Rank 0
2039 11:03:57.506251 SW Impedance : PASS
2040 11:03:57.510050 DUTY Scan : NO K
2041 11:03:57.510130 ZQ Calibration : PASS
2042 11:03:57.512760 Jitter Meter : NO K
2043 11:03:57.512862 CBT Training : PASS
2044 11:03:57.516722 Write leveling : PASS
2045 11:03:57.519714 RX DQS gating : PASS
2046 11:03:57.519795 RX DQ/DQS(RDDQC) : PASS
2047 11:03:57.523809 TX DQ/DQS : PASS
2048 11:03:57.527037 RX DATLAT : PASS
2049 11:03:57.527117 RX DQ/DQS(Engine): PASS
2050 11:03:57.529759 TX OE : NO K
2051 11:03:57.529841 All Pass.
2052 11:03:57.529941
2053 11:03:57.532985 CH 0, Rank 1
2054 11:03:57.533062 SW Impedance : PASS
2055 11:03:57.536570 DUTY Scan : NO K
2056 11:03:57.539812 ZQ Calibration : PASS
2057 11:03:57.539919 Jitter Meter : NO K
2058 11:03:57.543217 CBT Training : PASS
2059 11:03:57.546850 Write leveling : PASS
2060 11:03:57.546934 RX DQS gating : PASS
2061 11:03:57.549866 RX DQ/DQS(RDDQC) : PASS
2062 11:03:57.549945 TX DQ/DQS : PASS
2063 11:03:57.553192 RX DATLAT : PASS
2064 11:03:57.556213 RX DQ/DQS(Engine): PASS
2065 11:03:57.556293 TX OE : NO K
2066 11:03:57.559998 All Pass.
2067 11:03:57.560078
2068 11:03:57.560137 CH 1, Rank 0
2069 11:03:57.563071 SW Impedance : PASS
2070 11:03:57.563148 DUTY Scan : NO K
2071 11:03:57.566459 ZQ Calibration : PASS
2072 11:03:57.570196 Jitter Meter : NO K
2073 11:03:57.570279 CBT Training : PASS
2074 11:03:57.573483 Write leveling : PASS
2075 11:03:57.577005 RX DQS gating : PASS
2076 11:03:57.577090 RX DQ/DQS(RDDQC) : PASS
2077 11:03:57.580000 TX DQ/DQS : PASS
2078 11:03:57.580078 RX DATLAT : PASS
2079 11:03:57.583737 RX DQ/DQS(Engine): PASS
2080 11:03:57.587006 TX OE : NO K
2081 11:03:57.587085 All Pass.
2082 11:03:57.587145
2083 11:03:57.587198 CH 1, Rank 1
2084 11:03:57.590186 SW Impedance : PASS
2085 11:03:57.593757 DUTY Scan : NO K
2086 11:03:57.593836 ZQ Calibration : PASS
2087 11:03:57.597103 Jitter Meter : NO K
2088 11:03:57.600306 CBT Training : PASS
2089 11:03:57.600383 Write leveling : PASS
2090 11:03:57.603683 RX DQS gating : PASS
2091 11:03:57.607458 RX DQ/DQS(RDDQC) : PASS
2092 11:03:57.607540 TX DQ/DQS : PASS
2093 11:03:57.610794 RX DATLAT : PASS
2094 11:03:57.610880 RX DQ/DQS(Engine): PASS
2095 11:03:57.613690 TX OE : NO K
2096 11:03:57.613768 All Pass.
2097 11:03:57.613827
2098 11:03:57.616989 DramC Write-DBI off
2099 11:03:57.620990 PER_BANK_REFRESH: Hybrid Mode
2100 11:03:57.621093 TX_TRACKING: ON
2101 11:03:57.623883 [GetDramInforAfterCalByMRR] Vendor 6.
2102 11:03:57.626987 [GetDramInforAfterCalByMRR] Revision 606.
2103 11:03:57.630478 [GetDramInforAfterCalByMRR] Revision 2 0.
2104 11:03:57.634061 MR0 0x3b3b
2105 11:03:57.634148 MR8 0x5151
2106 11:03:57.637757 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2107 11:03:57.637863
2108 11:03:57.640569 MR0 0x3b3b
2109 11:03:57.640646 MR8 0x5151
2110 11:03:57.643684 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 11:03:57.643763
2112 11:03:57.654009 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2113 11:03:57.657290 [FAST_K] Save calibration result to emmc
2114 11:03:57.660641 [FAST_K] Save calibration result to emmc
2115 11:03:57.660724 dram_init: config_dvfs: 1
2116 11:03:57.667159 dramc_set_vcore_voltage set vcore to 662500
2117 11:03:57.667252 Read voltage for 1200, 2
2118 11:03:57.671382 Vio18 = 0
2119 11:03:57.671464 Vcore = 662500
2120 11:03:57.671523 Vdram = 0
2121 11:03:57.674244 Vddq = 0
2122 11:03:57.674349 Vmddr = 0
2123 11:03:57.677248 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2124 11:03:57.684042 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2125 11:03:57.687140 MEM_TYPE=3, freq_sel=15
2126 11:03:57.690684 sv_algorithm_assistance_LP4_1600
2127 11:03:57.693767 ============ PULL DRAM RESETB DOWN ============
2128 11:03:57.697086 ========== PULL DRAM RESETB DOWN end =========
2129 11:03:57.700615 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2130 11:03:57.704090 ===================================
2131 11:03:57.707220 LPDDR4 DRAM CONFIGURATION
2132 11:03:57.711085 ===================================
2133 11:03:57.713950 EX_ROW_EN[0] = 0x0
2134 11:03:57.714032 EX_ROW_EN[1] = 0x0
2135 11:03:57.717531 LP4Y_EN = 0x0
2136 11:03:57.717638 WORK_FSP = 0x0
2137 11:03:57.720803 WL = 0x4
2138 11:03:57.720881 RL = 0x4
2139 11:03:57.724178 BL = 0x2
2140 11:03:57.724261 RPST = 0x0
2141 11:03:57.727771 RD_PRE = 0x0
2142 11:03:57.727854 WR_PRE = 0x1
2143 11:03:57.730995 WR_PST = 0x0
2144 11:03:57.731130 DBI_WR = 0x0
2145 11:03:57.733964 DBI_RD = 0x0
2146 11:03:57.734037 OTF = 0x1
2147 11:03:57.737169 ===================================
2148 11:03:57.740626 ===================================
2149 11:03:57.744129 ANA top config
2150 11:03:57.747802 ===================================
2151 11:03:57.750793 DLL_ASYNC_EN = 0
2152 11:03:57.750875 ALL_SLAVE_EN = 0
2153 11:03:57.754351 NEW_RANK_MODE = 1
2154 11:03:57.757455 DLL_IDLE_MODE = 1
2155 11:03:57.761132 LP45_APHY_COMB_EN = 1
2156 11:03:57.761258 TX_ODT_DIS = 1
2157 11:03:57.764427 NEW_8X_MODE = 1
2158 11:03:57.767644 ===================================
2159 11:03:57.771063 ===================================
2160 11:03:57.775035 data_rate = 2400
2161 11:03:57.777748 CKR = 1
2162 11:03:57.782023 DQ_P2S_RATIO = 8
2163 11:03:57.784242 ===================================
2164 11:03:57.784327 CA_P2S_RATIO = 8
2165 11:03:57.787861 DQ_CA_OPEN = 0
2166 11:03:57.791135 DQ_SEMI_OPEN = 0
2167 11:03:57.794630 CA_SEMI_OPEN = 0
2168 11:03:57.797932 CA_FULL_RATE = 0
2169 11:03:57.801096 DQ_CKDIV4_EN = 0
2170 11:03:57.801212 CA_CKDIV4_EN = 0
2171 11:03:57.805229 CA_PREDIV_EN = 0
2172 11:03:57.808124 PH8_DLY = 17
2173 11:03:57.811107 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2174 11:03:57.814790 DQ_AAMCK_DIV = 4
2175 11:03:57.818348 CA_AAMCK_DIV = 4
2176 11:03:57.818439 CA_ADMCK_DIV = 4
2177 11:03:57.821455 DQ_TRACK_CA_EN = 0
2178 11:03:57.824806 CA_PICK = 1200
2179 11:03:57.828129 CA_MCKIO = 1200
2180 11:03:57.831386 MCKIO_SEMI = 0
2181 11:03:57.834963 PLL_FREQ = 2366
2182 11:03:57.838259 DQ_UI_PI_RATIO = 32
2183 11:03:57.838347 CA_UI_PI_RATIO = 0
2184 11:03:57.841347 ===================================
2185 11:03:57.844628 ===================================
2186 11:03:57.847968 memory_type:LPDDR4
2187 11:03:57.851844 GP_NUM : 10
2188 11:03:57.851934 SRAM_EN : 1
2189 11:03:57.854952 MD32_EN : 0
2190 11:03:57.858298 ===================================
2191 11:03:57.861695 [ANA_INIT] >>>>>>>>>>>>>>
2192 11:03:57.861782 <<<<<< [CONFIGURE PHASE]: ANA_TX
2193 11:03:57.865404 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2194 11:03:57.868601 ===================================
2195 11:03:57.872231 data_rate = 2400,PCW = 0X5b00
2196 11:03:57.875008 ===================================
2197 11:03:57.878355 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2198 11:03:57.885531 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2199 11:03:57.888560 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2200 11:03:57.895003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2201 11:03:57.898488 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2202 11:03:57.901750 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2203 11:03:57.904965 [ANA_INIT] flow start
2204 11:03:57.905065 [ANA_INIT] PLL >>>>>>>>
2205 11:03:57.909140 [ANA_INIT] PLL <<<<<<<<
2206 11:03:57.912360 [ANA_INIT] MIDPI >>>>>>>>
2207 11:03:57.912448 [ANA_INIT] MIDPI <<<<<<<<
2208 11:03:57.915492 [ANA_INIT] DLL >>>>>>>>
2209 11:03:57.918655 [ANA_INIT] DLL <<<<<<<<
2210 11:03:57.918744 [ANA_INIT] flow end
2211 11:03:57.922323 ============ LP4 DIFF to SE enter ============
2212 11:03:57.929730 ============ LP4 DIFF to SE exit ============
2213 11:03:57.929837 [ANA_INIT] <<<<<<<<<<<<<
2214 11:03:57.932103 [Flow] Enable top DCM control >>>>>
2215 11:03:57.936094 [Flow] Enable top DCM control <<<<<
2216 11:03:57.938919 Enable DLL master slave shuffle
2217 11:03:57.945398 ==============================================================
2218 11:03:57.945508 Gating Mode config
2219 11:03:57.952283 ==============================================================
2220 11:03:57.956110 Config description:
2221 11:03:57.962453 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2222 11:03:57.969506 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2223 11:03:57.975848 SELPH_MODE 0: By rank 1: By Phase
2224 11:03:57.979151 ==============================================================
2225 11:03:57.982859 GAT_TRACK_EN = 1
2226 11:03:57.986194 RX_GATING_MODE = 2
2227 11:03:57.989543 RX_GATING_TRACK_MODE = 2
2228 11:03:57.992471 SELPH_MODE = 1
2229 11:03:57.995805 PICG_EARLY_EN = 1
2230 11:03:57.999312 VALID_LAT_VALUE = 1
2231 11:03:58.005951 ==============================================================
2232 11:03:58.009318 Enter into Gating configuration >>>>
2233 11:03:58.012838 Exit from Gating configuration <<<<
2234 11:03:58.012921 Enter into DVFS_PRE_config >>>>>
2235 11:03:58.027033 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2236 11:03:58.030241 Exit from DVFS_PRE_config <<<<<
2237 11:03:58.032884 Enter into PICG configuration >>>>
2238 11:03:58.032968 Exit from PICG configuration <<<<
2239 11:03:58.036477 [RX_INPUT] configuration >>>>>
2240 11:03:58.039714 [RX_INPUT] configuration <<<<<
2241 11:03:58.046470 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2242 11:03:58.049580 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2243 11:03:58.056800 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2244 11:03:58.063509 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2245 11:03:58.069848 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2246 11:03:58.076877 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2247 11:03:58.079640 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2248 11:03:58.083516 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2249 11:03:58.086974 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2250 11:03:58.093884 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2251 11:03:58.096939 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2252 11:03:58.100175 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2253 11:03:58.103420 ===================================
2254 11:03:58.106654 LPDDR4 DRAM CONFIGURATION
2255 11:03:58.110236 ===================================
2256 11:03:58.110320 EX_ROW_EN[0] = 0x0
2257 11:03:58.113714 EX_ROW_EN[1] = 0x0
2258 11:03:58.113794 LP4Y_EN = 0x0
2259 11:03:58.117080 WORK_FSP = 0x0
2260 11:03:58.117201 WL = 0x4
2261 11:03:58.121077 RL = 0x4
2262 11:03:58.121201 BL = 0x2
2263 11:03:58.123495 RPST = 0x0
2264 11:03:58.123572 RD_PRE = 0x0
2265 11:03:58.126820 WR_PRE = 0x1
2266 11:03:58.131829 WR_PST = 0x0
2267 11:03:58.131913 DBI_WR = 0x0
2268 11:03:58.134043 DBI_RD = 0x0
2269 11:03:58.134122 OTF = 0x1
2270 11:03:58.137433 ===================================
2271 11:03:58.140791 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2272 11:03:58.143705 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2273 11:03:58.150307 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2274 11:03:58.153763 ===================================
2275 11:03:58.153849 LPDDR4 DRAM CONFIGURATION
2276 11:03:58.156934 ===================================
2277 11:03:58.160513 EX_ROW_EN[0] = 0x10
2278 11:03:58.164505 EX_ROW_EN[1] = 0x0
2279 11:03:58.164613 LP4Y_EN = 0x0
2280 11:03:58.167254 WORK_FSP = 0x0
2281 11:03:58.167351 WL = 0x4
2282 11:03:58.170761 RL = 0x4
2283 11:03:58.170863 BL = 0x2
2284 11:03:58.174041 RPST = 0x0
2285 11:03:58.174135 RD_PRE = 0x0
2286 11:03:58.177630 WR_PRE = 0x1
2287 11:03:58.177731 WR_PST = 0x0
2288 11:03:58.181023 DBI_WR = 0x0
2289 11:03:58.181126 DBI_RD = 0x0
2290 11:03:58.183959 OTF = 0x1
2291 11:03:58.187633 ===================================
2292 11:03:58.194441 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2293 11:03:58.194563 ==
2294 11:03:58.197513 Dram Type= 6, Freq= 0, CH_0, rank 0
2295 11:03:58.201156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2296 11:03:58.201239 ==
2297 11:03:58.204048 [Duty_Offset_Calibration]
2298 11:03:58.204126 B0:2 B1:-1 CA:1
2299 11:03:58.204184
2300 11:03:58.207323 [DutyScan_Calibration_Flow] k_type=0
2301 11:03:58.216661
2302 11:03:58.216789 ==CLK 0==
2303 11:03:58.219955 Final CLK duty delay cell = -4
2304 11:03:58.223245 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2305 11:03:58.226668 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2306 11:03:58.229976 [-4] AVG Duty = 4937%(X100)
2307 11:03:58.230106
2308 11:03:58.233623 CH0 CLK Duty spec in!! Max-Min= 125%
2309 11:03:58.236846 [DutyScan_Calibration_Flow] ====Done====
2310 11:03:58.236942
2311 11:03:58.240360 [DutyScan_Calibration_Flow] k_type=1
2312 11:03:58.254542
2313 11:03:58.254689 ==DQS 0 ==
2314 11:03:58.258463 Final DQS duty delay cell = -4
2315 11:03:58.261578 [-4] MAX Duty = 5000%(X100), DQS PI = 44
2316 11:03:58.264532 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2317 11:03:58.268180 [-4] AVG Duty = 4938%(X100)
2318 11:03:58.268280
2319 11:03:58.268366 ==DQS 1 ==
2320 11:03:58.271345 Final DQS duty delay cell = -4
2321 11:03:58.275321 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2322 11:03:58.278295 [-4] MIN Duty = 5000%(X100), DQS PI = 48
2323 11:03:58.282079 [-4] AVG Duty = 5062%(X100)
2324 11:03:58.282164
2325 11:03:58.285110 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2326 11:03:58.285224
2327 11:03:58.289294 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2328 11:03:58.291707 [DutyScan_Calibration_Flow] ====Done====
2329 11:03:58.291783
2330 11:03:58.294934 [DutyScan_Calibration_Flow] k_type=3
2331 11:03:58.311697
2332 11:03:58.311844 ==DQM 0 ==
2333 11:03:58.315243 Final DQM duty delay cell = 0
2334 11:03:58.318508 [0] MAX Duty = 4969%(X100), DQS PI = 30
2335 11:03:58.322304 [0] MIN Duty = 4875%(X100), DQS PI = 10
2336 11:03:58.322414 [0] AVG Duty = 4922%(X100)
2337 11:03:58.326105
2338 11:03:58.326203 ==DQM 1 ==
2339 11:03:58.328630 Final DQM duty delay cell = 0
2340 11:03:58.332294 [0] MAX Duty = 5124%(X100), DQS PI = 32
2341 11:03:58.335832 [0] MIN Duty = 4969%(X100), DQS PI = 10
2342 11:03:58.335932 [0] AVG Duty = 5046%(X100)
2343 11:03:58.336047
2344 11:03:58.342581 CH0 DQM 0 Duty spec in!! Max-Min= 94%
2345 11:03:58.342676
2346 11:03:58.345577 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2347 11:03:58.349047 [DutyScan_Calibration_Flow] ====Done====
2348 11:03:58.349170
2349 11:03:58.353009 [DutyScan_Calibration_Flow] k_type=2
2350 11:03:58.367746
2351 11:03:58.367873 ==DQ 0 ==
2352 11:03:58.370857 Final DQ duty delay cell = -4
2353 11:03:58.374431 [-4] MAX Duty = 5031%(X100), DQS PI = 38
2354 11:03:58.377868 [-4] MIN Duty = 4844%(X100), DQS PI = 18
2355 11:03:58.381280 [-4] AVG Duty = 4937%(X100)
2356 11:03:58.381390
2357 11:03:58.381449 ==DQ 1 ==
2358 11:03:58.384158 Final DQ duty delay cell = 0
2359 11:03:58.388011 [0] MAX Duty = 5031%(X100), DQS PI = 18
2360 11:03:58.391032 [0] MIN Duty = 4907%(X100), DQS PI = 44
2361 11:03:58.391118 [0] AVG Duty = 4969%(X100)
2362 11:03:58.394117
2363 11:03:58.397759 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2364 11:03:58.397844
2365 11:03:58.401053 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2366 11:03:58.404676 [DutyScan_Calibration_Flow] ====Done====
2367 11:03:58.404758 ==
2368 11:03:58.407555 Dram Type= 6, Freq= 0, CH_1, rank 0
2369 11:03:58.410912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2370 11:03:58.410998 ==
2371 11:03:58.414662 [Duty_Offset_Calibration]
2372 11:03:58.414742 B0:1 B1:1 CA:2
2373 11:03:58.414800
2374 11:03:58.417789 [DutyScan_Calibration_Flow] k_type=0
2375 11:03:58.427610
2376 11:03:58.427726 ==CLK 0==
2377 11:03:58.431654 Final CLK duty delay cell = 0
2378 11:03:58.434582 [0] MAX Duty = 5156%(X100), DQS PI = 24
2379 11:03:58.438662 [0] MIN Duty = 4938%(X100), DQS PI = 40
2380 11:03:58.438752 [0] AVG Duty = 5047%(X100)
2381 11:03:58.441992
2382 11:03:58.442079 CH1 CLK Duty spec in!! Max-Min= 218%
2383 11:03:58.449432 [DutyScan_Calibration_Flow] ====Done====
2384 11:03:58.449566
2385 11:03:58.451732 [DutyScan_Calibration_Flow] k_type=1
2386 11:03:58.467330
2387 11:03:58.467457 ==DQS 0 ==
2388 11:03:58.470539 Final DQS duty delay cell = 0
2389 11:03:58.473956 [0] MAX Duty = 5031%(X100), DQS PI = 18
2390 11:03:58.477368 [0] MIN Duty = 4844%(X100), DQS PI = 50
2391 11:03:58.477460 [0] AVG Duty = 4937%(X100)
2392 11:03:58.480795
2393 11:03:58.480874 ==DQS 1 ==
2394 11:03:58.483989 Final DQS duty delay cell = 0
2395 11:03:58.487635 [0] MAX Duty = 5062%(X100), DQS PI = 36
2396 11:03:58.490640 [0] MIN Duty = 4907%(X100), DQS PI = 16
2397 11:03:58.490758 [0] AVG Duty = 4984%(X100)
2398 11:03:58.494137
2399 11:03:58.497672 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2400 11:03:58.497790
2401 11:03:58.501016 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2402 11:03:58.504154 [DutyScan_Calibration_Flow] ====Done====
2403 11:03:58.504255
2404 11:03:58.507513 [DutyScan_Calibration_Flow] k_type=3
2405 11:03:58.523856
2406 11:03:58.523982 ==DQM 0 ==
2407 11:03:58.527073 Final DQM duty delay cell = 0
2408 11:03:58.530404 [0] MAX Duty = 5093%(X100), DQS PI = 18
2409 11:03:58.534500 [0] MIN Duty = 4876%(X100), DQS PI = 50
2410 11:03:58.534598 [0] AVG Duty = 4984%(X100)
2411 11:03:58.537685
2412 11:03:58.537785 ==DQM 1 ==
2413 11:03:58.541106 Final DQM duty delay cell = 0
2414 11:03:58.543968 [0] MAX Duty = 5125%(X100), DQS PI = 0
2415 11:03:58.547556 [0] MIN Duty = 4969%(X100), DQS PI = 4
2416 11:03:58.547654 [0] AVG Duty = 5047%(X100)
2417 11:03:58.547716
2418 11:03:58.551142 CH1 DQM 0 Duty spec in!! Max-Min= 217%
2419 11:03:58.554890
2420 11:03:58.557374 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2421 11:03:58.561017 [DutyScan_Calibration_Flow] ====Done====
2422 11:03:58.561110
2423 11:03:58.564542 [DutyScan_Calibration_Flow] k_type=2
2424 11:03:58.580943
2425 11:03:58.581056 ==DQ 0 ==
2426 11:03:58.583966 Final DQ duty delay cell = 0
2427 11:03:58.586944 [0] MAX Duty = 5124%(X100), DQS PI = 20
2428 11:03:58.590486 [0] MIN Duty = 4907%(X100), DQS PI = 50
2429 11:03:58.590618 [0] AVG Duty = 5015%(X100)
2430 11:03:58.590725
2431 11:03:58.593773 ==DQ 1 ==
2432 11:03:58.597593 Final DQ duty delay cell = 0
2433 11:03:58.600491 [0] MAX Duty = 5093%(X100), DQS PI = 38
2434 11:03:58.603756 [0] MIN Duty = 5000%(X100), DQS PI = 50
2435 11:03:58.603870 [0] AVG Duty = 5046%(X100)
2436 11:03:58.603960
2437 11:03:58.606962 CH1 DQ 0 Duty spec in!! Max-Min= 217%
2438 11:03:58.607073
2439 11:03:58.610516 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2440 11:03:58.617219 [DutyScan_Calibration_Flow] ====Done====
2441 11:03:58.620391 nWR fixed to 30
2442 11:03:58.620544 [ModeRegInit_LP4] CH0 RK0
2443 11:03:58.623837 [ModeRegInit_LP4] CH0 RK1
2444 11:03:58.627326 [ModeRegInit_LP4] CH1 RK0
2445 11:03:58.627439 [ModeRegInit_LP4] CH1 RK1
2446 11:03:58.630444 match AC timing 7
2447 11:03:58.634694 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2448 11:03:58.637361 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2449 11:03:58.643901 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2450 11:03:58.647555 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2451 11:03:58.654042 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2452 11:03:58.654164 ==
2453 11:03:58.657502 Dram Type= 6, Freq= 0, CH_0, rank 0
2454 11:03:58.660980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2455 11:03:58.661071 ==
2456 11:03:58.664100 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2457 11:03:58.670794 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2458 11:03:58.680249 [CA 0] Center 40 (10~71) winsize 62
2459 11:03:58.683605 [CA 1] Center 39 (9~70) winsize 62
2460 11:03:58.687100 [CA 2] Center 36 (6~67) winsize 62
2461 11:03:58.690839 [CA 3] Center 35 (5~66) winsize 62
2462 11:03:58.694078 [CA 4] Center 35 (5~65) winsize 61
2463 11:03:58.697528 [CA 5] Center 34 (4~65) winsize 62
2464 11:03:58.697620
2465 11:03:58.700964 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2466 11:03:58.701052
2467 11:03:58.703980 [CATrainingPosCal] consider 1 rank data
2468 11:03:58.707299 u2DelayCellTimex100 = 270/100 ps
2469 11:03:58.711065 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2470 11:03:58.713738 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2471 11:03:58.720337 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2472 11:03:58.723813 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2473 11:03:58.727229 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2474 11:03:58.730844 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2475 11:03:58.730938
2476 11:03:58.733885 CA PerBit enable=1, Macro0, CA PI delay=34
2477 11:03:58.733968
2478 11:03:58.737159 [CBTSetCACLKResult] CA Dly = 34
2479 11:03:58.737258 CS Dly: 7 (0~38)
2480 11:03:58.737319 ==
2481 11:03:58.740482 Dram Type= 6, Freq= 0, CH_0, rank 1
2482 11:03:58.747126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2483 11:03:58.747279 ==
2484 11:03:58.751373 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2485 11:03:58.757501 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2486 11:03:58.766025 [CA 0] Center 39 (9~70) winsize 62
2487 11:03:58.769371 [CA 1] Center 39 (9~70) winsize 62
2488 11:03:58.773914 [CA 2] Center 36 (6~67) winsize 62
2489 11:03:58.776525 [CA 3] Center 35 (5~66) winsize 62
2490 11:03:58.779714 [CA 4] Center 34 (4~65) winsize 62
2491 11:03:58.782826 [CA 5] Center 34 (4~64) winsize 61
2492 11:03:58.782914
2493 11:03:58.786344 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2494 11:03:58.786431
2495 11:03:58.789431 [CATrainingPosCal] consider 2 rank data
2496 11:03:58.793382 u2DelayCellTimex100 = 270/100 ps
2497 11:03:58.796992 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2498 11:03:58.800425 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2499 11:03:58.806147 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2500 11:03:58.809611 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2501 11:03:58.813479 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2502 11:03:58.816417 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2503 11:03:58.816521
2504 11:03:58.819646 CA PerBit enable=1, Macro0, CA PI delay=34
2505 11:03:58.819748
2506 11:03:58.823529 [CBTSetCACLKResult] CA Dly = 34
2507 11:03:58.823639 CS Dly: 8 (0~41)
2508 11:03:58.823724
2509 11:03:58.827076 ----->DramcWriteLeveling(PI) begin...
2510 11:03:58.827171 ==
2511 11:03:58.829646 Dram Type= 6, Freq= 0, CH_0, rank 0
2512 11:03:58.836359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 11:03:58.836502 ==
2514 11:03:58.840241 Write leveling (Byte 0): 31 => 31
2515 11:03:58.843017 Write leveling (Byte 1): 30 => 30
2516 11:03:58.843103 DramcWriteLeveling(PI) end<-----
2517 11:03:58.843163
2518 11:03:58.846562 ==
2519 11:03:58.850413 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 11:03:58.853148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 11:03:58.853275 ==
2522 11:03:58.856712 [Gating] SW mode calibration
2523 11:03:58.863913 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2524 11:03:58.867158 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2525 11:03:58.873745 0 15 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
2526 11:03:58.877501 0 15 4 | B1->B0 | 2323 3232 | 1 1 | (0 0) (1 1)
2527 11:03:58.880475 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2528 11:03:58.886915 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 11:03:58.891258 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 11:03:58.893704 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 11:03:58.896957 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 11:03:58.903388 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 11:03:58.907033 1 0 0 | B1->B0 | 3232 2d2d | 0 1 | (0 1) (1 0)
2534 11:03:58.910435 1 0 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2535 11:03:58.917058 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 11:03:58.920156 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 11:03:58.923556 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 11:03:58.930693 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 11:03:58.933881 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 11:03:58.937504 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 11:03:58.944471 1 1 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2542 11:03:58.947234 1 1 4 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
2543 11:03:58.950532 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 11:03:58.954038 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 11:03:58.960575 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 11:03:58.964112 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 11:03:58.967322 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 11:03:58.974636 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 11:03:58.977367 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2550 11:03:58.981025 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2551 11:03:58.987923 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 11:03:58.991945 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 11:03:58.994710 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 11:03:59.001844 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 11:03:59.004278 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 11:03:59.007737 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 11:03:59.014746 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 11:03:59.017988 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 11:03:59.020969 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 11:03:59.024260 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 11:03:59.032317 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 11:03:59.034624 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 11:03:59.038130 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 11:03:59.044781 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2565 11:03:59.048763 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2566 11:03:59.051227 Total UI for P1: 0, mck2ui 16
2567 11:03:59.054818 best dqsien dly found for B0: ( 1, 3, 28)
2568 11:03:59.058578 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2569 11:03:59.065478 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 11:03:59.065580 Total UI for P1: 0, mck2ui 16
2571 11:03:59.068130 best dqsien dly found for B1: ( 1, 4, 2)
2572 11:03:59.071803 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2573 11:03:59.075061 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2574 11:03:59.078949
2575 11:03:59.081808 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2576 11:03:59.085394 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2577 11:03:59.088940 [Gating] SW calibration Done
2578 11:03:59.089027 ==
2579 11:03:59.091704 Dram Type= 6, Freq= 0, CH_0, rank 0
2580 11:03:59.095690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2581 11:03:59.095776 ==
2582 11:03:59.095836 RX Vref Scan: 0
2583 11:03:59.095891
2584 11:03:59.098424 RX Vref 0 -> 0, step: 1
2585 11:03:59.098500
2586 11:03:59.102379 RX Delay -40 -> 252, step: 8
2587 11:03:59.105233 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2588 11:03:59.108446 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2589 11:03:59.111633 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2590 11:03:59.118361 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2591 11:03:59.121751 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2592 11:03:59.125271 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2593 11:03:59.128502 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2594 11:03:59.132005 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2595 11:03:59.138636 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2596 11:03:59.141932 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2597 11:03:59.145557 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2598 11:03:59.148936 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2599 11:03:59.152163 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2600 11:03:59.159120 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2601 11:03:59.162199 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2602 11:03:59.165396 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2603 11:03:59.165484 ==
2604 11:03:59.169043 Dram Type= 6, Freq= 0, CH_0, rank 0
2605 11:03:59.172747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2606 11:03:59.172835 ==
2607 11:03:59.175810 DQS Delay:
2608 11:03:59.175890 DQS0 = 0, DQS1 = 0
2609 11:03:59.175949 DQM Delay:
2610 11:03:59.178988 DQM0 = 115, DQM1 = 107
2611 11:03:59.179068 DQ Delay:
2612 11:03:59.183227 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2613 11:03:59.186367 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2614 11:03:59.189290 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2615 11:03:59.195609 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2616 11:03:59.195703
2617 11:03:59.195761
2618 11:03:59.195815 ==
2619 11:03:59.198937 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 11:03:59.202434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 11:03:59.202515 ==
2622 11:03:59.202588
2623 11:03:59.202643
2624 11:03:59.205769 TX Vref Scan disable
2625 11:03:59.205845 == TX Byte 0 ==
2626 11:03:59.212403 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2627 11:03:59.215748 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2628 11:03:59.215825 == TX Byte 1 ==
2629 11:03:59.222746 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2630 11:03:59.225954 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2631 11:03:59.226031 ==
2632 11:03:59.229613 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 11:03:59.233080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 11:03:59.233197 ==
2635 11:03:59.245689 TX Vref=22, minBit 1, minWin=25, winSum=417
2636 11:03:59.248748 TX Vref=24, minBit 1, minWin=25, winSum=419
2637 11:03:59.251976 TX Vref=26, minBit 0, minWin=26, winSum=428
2638 11:03:59.255319 TX Vref=28, minBit 5, minWin=25, winSum=427
2639 11:03:59.258668 TX Vref=30, minBit 1, minWin=26, winSum=433
2640 11:03:59.261730 TX Vref=32, minBit 0, minWin=26, winSum=431
2641 11:03:59.268325 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 30
2642 11:03:59.268407
2643 11:03:59.272407 Final TX Range 1 Vref 30
2644 11:03:59.272484
2645 11:03:59.272542 ==
2646 11:03:59.275056 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 11:03:59.278807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 11:03:59.278885 ==
2649 11:03:59.278944
2650 11:03:59.278998
2651 11:03:59.282339 TX Vref Scan disable
2652 11:03:59.285358 == TX Byte 0 ==
2653 11:03:59.288944 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2654 11:03:59.292032 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2655 11:03:59.295382 == TX Byte 1 ==
2656 11:03:59.299184 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2657 11:03:59.302485 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2658 11:03:59.302583
2659 11:03:59.305459 [DATLAT]
2660 11:03:59.305534 Freq=1200, CH0 RK0
2661 11:03:59.305592
2662 11:03:59.308797 DATLAT Default: 0xd
2663 11:03:59.308873 0, 0xFFFF, sum = 0
2664 11:03:59.312708 1, 0xFFFF, sum = 0
2665 11:03:59.312803 2, 0xFFFF, sum = 0
2666 11:03:59.315399 3, 0xFFFF, sum = 0
2667 11:03:59.315507 4, 0xFFFF, sum = 0
2668 11:03:59.318761 5, 0xFFFF, sum = 0
2669 11:03:59.318838 6, 0xFFFF, sum = 0
2670 11:03:59.322352 7, 0xFFFF, sum = 0
2671 11:03:59.322429 8, 0xFFFF, sum = 0
2672 11:03:59.325885 9, 0xFFFF, sum = 0
2673 11:03:59.325962 10, 0xFFFF, sum = 0
2674 11:03:59.329039 11, 0xFFFF, sum = 0
2675 11:03:59.329177 12, 0x0, sum = 1
2676 11:03:59.332509 13, 0x0, sum = 2
2677 11:03:59.332585 14, 0x0, sum = 3
2678 11:03:59.335583 15, 0x0, sum = 4
2679 11:03:59.335660 best_step = 13
2680 11:03:59.335758
2681 11:03:59.335859 ==
2682 11:03:59.339111 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 11:03:59.342773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 11:03:59.346010 ==
2685 11:03:59.346085 RX Vref Scan: 1
2686 11:03:59.346142
2687 11:03:59.349153 Set Vref Range= 32 -> 127
2688 11:03:59.349242
2689 11:03:59.349302 RX Vref 32 -> 127, step: 1
2690 11:03:59.352601
2691 11:03:59.352676 RX Delay -21 -> 252, step: 4
2692 11:03:59.352736
2693 11:03:59.356149 Set Vref, RX VrefLevel [Byte0]: 32
2694 11:03:59.359486 [Byte1]: 32
2695 11:03:59.363027
2696 11:03:59.363102 Set Vref, RX VrefLevel [Byte0]: 33
2697 11:03:59.369691 [Byte1]: 33
2698 11:03:59.369766
2699 11:03:59.373481 Set Vref, RX VrefLevel [Byte0]: 34
2700 11:03:59.376698 [Byte1]: 34
2701 11:03:59.376773
2702 11:03:59.379916 Set Vref, RX VrefLevel [Byte0]: 35
2703 11:03:59.383101 [Byte1]: 35
2704 11:03:59.387365
2705 11:03:59.387440 Set Vref, RX VrefLevel [Byte0]: 36
2706 11:03:59.390268 [Byte1]: 36
2707 11:03:59.395129
2708 11:03:59.395209 Set Vref, RX VrefLevel [Byte0]: 37
2709 11:03:59.398021 [Byte1]: 37
2710 11:03:59.402913
2711 11:03:59.402988 Set Vref, RX VrefLevel [Byte0]: 38
2712 11:03:59.406106 [Byte1]: 38
2713 11:03:59.411304
2714 11:03:59.411379 Set Vref, RX VrefLevel [Byte0]: 39
2715 11:03:59.414215 [Byte1]: 39
2716 11:03:59.418521
2717 11:03:59.418596 Set Vref, RX VrefLevel [Byte0]: 40
2718 11:03:59.422268 [Byte1]: 40
2719 11:03:59.426712
2720 11:03:59.426788 Set Vref, RX VrefLevel [Byte0]: 41
2721 11:03:59.429873 [Byte1]: 41
2722 11:03:59.434471
2723 11:03:59.434549 Set Vref, RX VrefLevel [Byte0]: 42
2724 11:03:59.437856 [Byte1]: 42
2725 11:03:59.442309
2726 11:03:59.442384 Set Vref, RX VrefLevel [Byte0]: 43
2727 11:03:59.445713 [Byte1]: 43
2728 11:03:59.450526
2729 11:03:59.450601 Set Vref, RX VrefLevel [Byte0]: 44
2730 11:03:59.453629 [Byte1]: 44
2731 11:03:59.458385
2732 11:03:59.458461 Set Vref, RX VrefLevel [Byte0]: 45
2733 11:03:59.461977 [Byte1]: 45
2734 11:03:59.466152
2735 11:03:59.466227 Set Vref, RX VrefLevel [Byte0]: 46
2736 11:03:59.469452 [Byte1]: 46
2737 11:03:59.474161
2738 11:03:59.474237 Set Vref, RX VrefLevel [Byte0]: 47
2739 11:03:59.477913 [Byte1]: 47
2740 11:03:59.482370
2741 11:03:59.482447 Set Vref, RX VrefLevel [Byte0]: 48
2742 11:03:59.485306 [Byte1]: 48
2743 11:03:59.489980
2744 11:03:59.490056 Set Vref, RX VrefLevel [Byte0]: 49
2745 11:03:59.493420 [Byte1]: 49
2746 11:03:59.498098
2747 11:03:59.498174 Set Vref, RX VrefLevel [Byte0]: 50
2748 11:03:59.501703 [Byte1]: 50
2749 11:03:59.506237
2750 11:03:59.506312 Set Vref, RX VrefLevel [Byte0]: 51
2751 11:03:59.509337 [Byte1]: 51
2752 11:03:59.513787
2753 11:03:59.513926 Set Vref, RX VrefLevel [Byte0]: 52
2754 11:03:59.517047 [Byte1]: 52
2755 11:03:59.521550
2756 11:03:59.521627 Set Vref, RX VrefLevel [Byte0]: 53
2757 11:03:59.524927 [Byte1]: 53
2758 11:03:59.529724
2759 11:03:59.529912 Set Vref, RX VrefLevel [Byte0]: 54
2760 11:03:59.533478 [Byte1]: 54
2761 11:03:59.537627
2762 11:03:59.537718 Set Vref, RX VrefLevel [Byte0]: 55
2763 11:03:59.541098 [Byte1]: 55
2764 11:03:59.545402
2765 11:03:59.545490 Set Vref, RX VrefLevel [Byte0]: 56
2766 11:03:59.548629 [Byte1]: 56
2767 11:03:59.553466
2768 11:03:59.553572 Set Vref, RX VrefLevel [Byte0]: 57
2769 11:03:59.556729 [Byte1]: 57
2770 11:03:59.561170
2771 11:03:59.561287 Set Vref, RX VrefLevel [Byte0]: 58
2772 11:03:59.564808 [Byte1]: 58
2773 11:03:59.569024
2774 11:03:59.569105 Set Vref, RX VrefLevel [Byte0]: 59
2775 11:03:59.572708 [Byte1]: 59
2776 11:03:59.577161
2777 11:03:59.577278 Set Vref, RX VrefLevel [Byte0]: 60
2778 11:03:59.580740 [Byte1]: 60
2779 11:03:59.585394
2780 11:03:59.585523 Set Vref, RX VrefLevel [Byte0]: 61
2781 11:03:59.588528 [Byte1]: 61
2782 11:03:59.592908
2783 11:03:59.592985 Set Vref, RX VrefLevel [Byte0]: 62
2784 11:03:59.596465 [Byte1]: 62
2785 11:03:59.601663
2786 11:03:59.601741 Set Vref, RX VrefLevel [Byte0]: 63
2787 11:03:59.604506 [Byte1]: 63
2788 11:03:59.608649
2789 11:03:59.608726 Set Vref, RX VrefLevel [Byte0]: 64
2790 11:03:59.612597 [Byte1]: 64
2791 11:03:59.616796
2792 11:03:59.616876 Set Vref, RX VrefLevel [Byte0]: 65
2793 11:03:59.620607 [Byte1]: 65
2794 11:03:59.625162
2795 11:03:59.625266 Set Vref, RX VrefLevel [Byte0]: 66
2796 11:03:59.627922 [Byte1]: 66
2797 11:03:59.632497
2798 11:03:59.632660 Final RX Vref Byte 0 = 52 to rank0
2799 11:03:59.636119 Final RX Vref Byte 1 = 51 to rank0
2800 11:03:59.639665 Final RX Vref Byte 0 = 52 to rank1
2801 11:03:59.642810 Final RX Vref Byte 1 = 51 to rank1==
2802 11:03:59.645999 Dram Type= 6, Freq= 0, CH_0, rank 0
2803 11:03:59.649736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2804 11:03:59.653022 ==
2805 11:03:59.653101 DQS Delay:
2806 11:03:59.653173 DQS0 = 0, DQS1 = 0
2807 11:03:59.656569 DQM Delay:
2808 11:03:59.656646 DQM0 = 115, DQM1 = 106
2809 11:03:59.659492 DQ Delay:
2810 11:03:59.663498 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
2811 11:03:59.666149 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =122
2812 11:03:59.669314 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
2813 11:03:59.672816 DQ12 =114, DQ13 =112, DQ14 =120, DQ15 =114
2814 11:03:59.672893
2815 11:03:59.672953
2816 11:03:59.680252 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
2817 11:03:59.683214 CH0 RK0: MR19=403, MR18=2F2
2818 11:03:59.689620 CH0_RK0: MR19=0x403, MR18=0x2F2, DQSOSC=409, MR23=63, INC=39, DEC=26
2819 11:03:59.689706
2820 11:03:59.692865 ----->DramcWriteLeveling(PI) begin...
2821 11:03:59.692943 ==
2822 11:03:59.696179 Dram Type= 6, Freq= 0, CH_0, rank 1
2823 11:03:59.700417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2824 11:03:59.700499 ==
2825 11:03:59.703649 Write leveling (Byte 0): 32 => 32
2826 11:03:59.706150 Write leveling (Byte 1): 29 => 29
2827 11:03:59.710325 DramcWriteLeveling(PI) end<-----
2828 11:03:59.710405
2829 11:03:59.710464 ==
2830 11:03:59.713549 Dram Type= 6, Freq= 0, CH_0, rank 1
2831 11:03:59.717011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2832 11:03:59.717090 ==
2833 11:03:59.720014 [Gating] SW mode calibration
2834 11:03:59.726369 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2835 11:03:59.733515 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2836 11:03:59.737301 0 15 0 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
2837 11:03:59.740746 0 15 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2838 11:03:59.746798 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 11:03:59.750055 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 11:03:59.754109 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 11:03:59.760618 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 11:03:59.763176 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2843 11:03:59.766711 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2844 11:03:59.773337 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2845 11:03:59.777242 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2846 11:03:59.780317 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 11:03:59.787103 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 11:03:59.790226 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 11:03:59.793520 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 11:03:59.800339 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
2851 11:03:59.803598 1 0 28 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
2852 11:03:59.807124 1 1 0 | B1->B0 | 3231 4242 | 1 0 | (1 1) (0 0)
2853 11:03:59.811861 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2854 11:03:59.818078 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 11:03:59.820484 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 11:03:59.823705 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 11:03:59.830691 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 11:03:59.833763 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 11:03:59.837079 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2860 11:03:59.844465 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2861 11:03:59.847075 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 11:03:59.850883 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 11:03:59.857468 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 11:03:59.860609 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 11:03:59.864053 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 11:03:59.867514 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 11:03:59.874054 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 11:03:59.877184 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 11:03:59.880940 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 11:03:59.887702 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 11:03:59.890715 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 11:03:59.894154 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 11:03:59.900890 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 11:03:59.904086 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 11:03:59.909099 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2876 11:03:59.914051 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2877 11:03:59.914137 Total UI for P1: 0, mck2ui 16
2878 11:03:59.921229 best dqsien dly found for B0: ( 1, 3, 28)
2879 11:03:59.924467 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 11:03:59.927456 Total UI for P1: 0, mck2ui 16
2881 11:03:59.931042 best dqsien dly found for B1: ( 1, 4, 0)
2882 11:03:59.934500 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2883 11:03:59.937808 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2884 11:03:59.937887
2885 11:03:59.941241 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2886 11:03:59.944505 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2887 11:03:59.948157 [Gating] SW calibration Done
2888 11:03:59.948237 ==
2889 11:03:59.951244 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 11:03:59.954649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 11:03:59.954727 ==
2892 11:03:59.957755 RX Vref Scan: 0
2893 11:03:59.957845
2894 11:03:59.957903 RX Vref 0 -> 0, step: 1
2895 11:03:59.957958
2896 11:03:59.961848 RX Delay -40 -> 252, step: 8
2897 11:03:59.965083 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2898 11:03:59.971352 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2899 11:03:59.974637 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2900 11:03:59.977977 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2901 11:03:59.981494 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2902 11:03:59.984830 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2903 11:03:59.991644 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2904 11:03:59.994975 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2905 11:03:59.999166 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2906 11:04:00.001647 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2907 11:04:00.005040 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2908 11:04:00.008678 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2909 11:04:00.015027 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2910 11:04:00.018936 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2911 11:04:00.021778 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2912 11:04:00.025096 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2913 11:04:00.025205 ==
2914 11:04:00.028311 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 11:04:00.035147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 11:04:00.035240 ==
2917 11:04:00.035318 DQS Delay:
2918 11:04:00.035392 DQS0 = 0, DQS1 = 0
2919 11:04:00.039023 DQM Delay:
2920 11:04:00.039106 DQM0 = 115, DQM1 = 105
2921 11:04:00.041886 DQ Delay:
2922 11:04:00.044991 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2923 11:04:00.048952 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
2924 11:04:00.052151 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =95
2925 11:04:00.055695 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2926 11:04:00.055779
2927 11:04:00.055857
2928 11:04:00.055947 ==
2929 11:04:00.059508 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 11:04:00.063049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 11:04:00.063132 ==
2932 11:04:00.063210
2933 11:04:00.063282
2934 11:04:00.065088 TX Vref Scan disable
2935 11:04:00.068664 == TX Byte 0 ==
2936 11:04:00.071938 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2937 11:04:00.076253 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2938 11:04:00.079345 == TX Byte 1 ==
2939 11:04:00.082251 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2940 11:04:00.085499 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2941 11:04:00.085586 ==
2942 11:04:00.090177 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 11:04:00.091872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 11:04:00.095067 ==
2945 11:04:00.105656 TX Vref=22, minBit 3, minWin=25, winSum=422
2946 11:04:00.109085 TX Vref=24, minBit 1, minWin=26, winSum=428
2947 11:04:00.112265 TX Vref=26, minBit 3, minWin=25, winSum=434
2948 11:04:00.115805 TX Vref=28, minBit 0, minWin=27, winSum=436
2949 11:04:00.119891 TX Vref=30, minBit 12, minWin=26, winSum=438
2950 11:04:00.126724 TX Vref=32, minBit 12, minWin=26, winSum=437
2951 11:04:00.129009 [TxChooseVref] Worse bit 0, Min win 27, Win sum 436, Final Vref 28
2952 11:04:00.129100
2953 11:04:00.132808 Final TX Range 1 Vref 28
2954 11:04:00.132928
2955 11:04:00.133019 ==
2956 11:04:00.136530 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 11:04:00.139164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 11:04:00.139257 ==
2959 11:04:00.142530
2960 11:04:00.142622
2961 11:04:00.142714 TX Vref Scan disable
2962 11:04:00.145739 == TX Byte 0 ==
2963 11:04:00.149081 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2964 11:04:00.152609 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2965 11:04:00.155931 == TX Byte 1 ==
2966 11:04:00.158832 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2967 11:04:00.162356 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2968 11:04:00.162484
2969 11:04:00.166532 [DATLAT]
2970 11:04:00.166625 Freq=1200, CH0 RK1
2971 11:04:00.166705
2972 11:04:00.169327 DATLAT Default: 0xd
2973 11:04:00.169414 0, 0xFFFF, sum = 0
2974 11:04:00.172523 1, 0xFFFF, sum = 0
2975 11:04:00.172609 2, 0xFFFF, sum = 0
2976 11:04:00.175805 3, 0xFFFF, sum = 0
2977 11:04:00.175924 4, 0xFFFF, sum = 0
2978 11:04:00.179055 5, 0xFFFF, sum = 0
2979 11:04:00.179146 6, 0xFFFF, sum = 0
2980 11:04:00.182563 7, 0xFFFF, sum = 0
2981 11:04:00.185812 8, 0xFFFF, sum = 0
2982 11:04:00.185913 9, 0xFFFF, sum = 0
2983 11:04:00.189486 10, 0xFFFF, sum = 0
2984 11:04:00.189588 11, 0xFFFF, sum = 0
2985 11:04:00.192900 12, 0x0, sum = 1
2986 11:04:00.192984 13, 0x0, sum = 2
2987 11:04:00.193078 14, 0x0, sum = 3
2988 11:04:00.196370 15, 0x0, sum = 4
2989 11:04:00.196481 best_step = 13
2990 11:04:00.196573
2991 11:04:00.199233 ==
2992 11:04:00.199312 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 11:04:00.206130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 11:04:00.206217 ==
2995 11:04:00.206282 RX Vref Scan: 0
2996 11:04:00.206337
2997 11:04:00.209039 RX Vref 0 -> 0, step: 1
2998 11:04:00.209130
2999 11:04:00.212293 RX Delay -21 -> 252, step: 4
3000 11:04:00.215896 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3001 11:04:00.219564 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3002 11:04:00.225737 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3003 11:04:00.229313 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3004 11:04:00.232746 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3005 11:04:00.236622 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3006 11:04:00.239352 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3007 11:04:00.246263 iDelay=195, Bit 7, Center 120 (51 ~ 190) 140
3008 11:04:00.249505 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3009 11:04:00.252830 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3010 11:04:00.255998 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3011 11:04:00.259808 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3012 11:04:00.262929 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3013 11:04:00.269152 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3014 11:04:00.272516 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3015 11:04:00.276146 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3016 11:04:00.276230 ==
3017 11:04:00.279184 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 11:04:00.282726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 11:04:00.286637 ==
3020 11:04:00.286721 DQS Delay:
3021 11:04:00.286799 DQS0 = 0, DQS1 = 0
3022 11:04:00.289312 DQM Delay:
3023 11:04:00.289395 DQM0 = 114, DQM1 = 104
3024 11:04:00.292656 DQ Delay:
3025 11:04:00.295832 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3026 11:04:00.299415 DQ4 =114, DQ5 =104, DQ6 =122, DQ7 =120
3027 11:04:00.302659 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3028 11:04:00.305998 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =112
3029 11:04:00.306175
3030 11:04:00.306284
3031 11:04:00.313037 [DQSOSCAuto] RK1, (LSB)MR18= 0x9fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 406 ps
3032 11:04:00.315910 CH0 RK1: MR19=403, MR18=9FA
3033 11:04:00.322665 CH0_RK1: MR19=0x403, MR18=0x9FA, DQSOSC=406, MR23=63, INC=39, DEC=26
3034 11:04:00.325882 [RxdqsGatingPostProcess] freq 1200
3035 11:04:00.333055 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3036 11:04:00.333214 best DQS0 dly(2T, 0.5T) = (0, 11)
3037 11:04:00.336347 best DQS1 dly(2T, 0.5T) = (0, 12)
3038 11:04:00.339494 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3039 11:04:00.342411 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3040 11:04:00.346902 best DQS0 dly(2T, 0.5T) = (0, 11)
3041 11:04:00.349137 best DQS1 dly(2T, 0.5T) = (0, 12)
3042 11:04:00.352815 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3043 11:04:00.356024 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3044 11:04:00.359148 Pre-setting of DQS Precalculation
3045 11:04:00.363139 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3046 11:04:00.363221 ==
3047 11:04:00.366006 Dram Type= 6, Freq= 0, CH_1, rank 0
3048 11:04:00.373111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 11:04:00.373243 ==
3050 11:04:00.376253 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3051 11:04:00.382533 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3052 11:04:00.391598 [CA 0] Center 38 (9~68) winsize 60
3053 11:04:00.394687 [CA 1] Center 38 (8~68) winsize 61
3054 11:04:00.398416 [CA 2] Center 35 (5~65) winsize 61
3055 11:04:00.401851 [CA 3] Center 34 (4~65) winsize 62
3056 11:04:00.404531 [CA 4] Center 34 (4~65) winsize 62
3057 11:04:00.408125 [CA 5] Center 33 (3~64) winsize 62
3058 11:04:00.408270
3059 11:04:00.411754 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3060 11:04:00.411830
3061 11:04:00.415003 [CATrainingPosCal] consider 1 rank data
3062 11:04:00.418171 u2DelayCellTimex100 = 270/100 ps
3063 11:04:00.421739 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3064 11:04:00.424630 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3065 11:04:00.431866 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3066 11:04:00.434667 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3067 11:04:00.439272 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3068 11:04:00.441512 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3069 11:04:00.441626
3070 11:04:00.445151 CA PerBit enable=1, Macro0, CA PI delay=33
3071 11:04:00.445228
3072 11:04:00.448437 [CBTSetCACLKResult] CA Dly = 33
3073 11:04:00.448515 CS Dly: 6 (0~37)
3074 11:04:00.448574 ==
3075 11:04:00.451358 Dram Type= 6, Freq= 0, CH_1, rank 1
3076 11:04:00.458362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 11:04:00.458451 ==
3078 11:04:00.461432 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3079 11:04:00.468018 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3080 11:04:00.477323 [CA 0] Center 38 (8~68) winsize 61
3081 11:04:00.479998 [CA 1] Center 38 (8~68) winsize 61
3082 11:04:00.483853 [CA 2] Center 35 (5~65) winsize 61
3083 11:04:00.487293 [CA 3] Center 34 (4~65) winsize 62
3084 11:04:00.490308 [CA 4] Center 34 (4~65) winsize 62
3085 11:04:00.493984 [CA 5] Center 33 (3~64) winsize 62
3086 11:04:00.494085
3087 11:04:00.497011 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3088 11:04:00.497129
3089 11:04:00.500154 [CATrainingPosCal] consider 2 rank data
3090 11:04:00.503674 u2DelayCellTimex100 = 270/100 ps
3091 11:04:00.507204 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3092 11:04:00.510520 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3093 11:04:00.516982 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3094 11:04:00.520956 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3095 11:04:00.523922 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3096 11:04:00.526927 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3097 11:04:00.527022
3098 11:04:00.530451 CA PerBit enable=1, Macro0, CA PI delay=33
3099 11:04:00.530544
3100 11:04:00.533802 [CBTSetCACLKResult] CA Dly = 33
3101 11:04:00.533895 CS Dly: 7 (0~40)
3102 11:04:00.533977
3103 11:04:00.537357 ----->DramcWriteLeveling(PI) begin...
3104 11:04:00.537450 ==
3105 11:04:00.540551 Dram Type= 6, Freq= 0, CH_1, rank 0
3106 11:04:00.546894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 11:04:00.547012 ==
3108 11:04:00.550679 Write leveling (Byte 0): 26 => 26
3109 11:04:00.553984 Write leveling (Byte 1): 30 => 30
3110 11:04:00.554063 DramcWriteLeveling(PI) end<-----
3111 11:04:00.557466
3112 11:04:00.557559 ==
3113 11:04:00.560871 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 11:04:00.563692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 11:04:00.563770 ==
3116 11:04:00.567018 [Gating] SW mode calibration
3117 11:04:00.573935 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3118 11:04:00.577073 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3119 11:04:00.583743 0 15 0 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
3120 11:04:00.588422 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 11:04:00.590695 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 11:04:00.597322 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 11:04:00.600661 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 11:04:00.603678 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 11:04:00.610767 0 15 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3126 11:04:00.613817 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3127 11:04:00.618499 1 0 0 | B1->B0 | 2424 2b2b | 0 1 | (1 0) (1 0)
3128 11:04:00.623773 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3129 11:04:00.627114 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 11:04:00.630716 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 11:04:00.633759 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 11:04:00.640419 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 11:04:00.644472 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 11:04:00.647394 1 0 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3135 11:04:00.654126 1 1 0 | B1->B0 | 3e3e 3333 | 0 0 | (0 0) (0 0)
3136 11:04:00.657129 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 11:04:00.660951 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 11:04:00.667403 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 11:04:00.670678 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 11:04:00.674244 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 11:04:00.681373 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 11:04:00.684297 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 11:04:00.687506 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3144 11:04:00.694395 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 11:04:00.698003 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 11:04:00.701169 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 11:04:00.704271 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 11:04:00.711224 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 11:04:00.714369 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 11:04:00.717931 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 11:04:00.724143 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 11:04:00.727571 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 11:04:00.731630 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 11:04:00.737705 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 11:04:00.741484 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 11:04:00.744299 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 11:04:00.751075 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3158 11:04:00.755231 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3159 11:04:00.757589 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 11:04:00.760770 Total UI for P1: 0, mck2ui 16
3161 11:04:00.764200 best dqsien dly found for B0: ( 1, 3, 26)
3162 11:04:00.768124 Total UI for P1: 0, mck2ui 16
3163 11:04:00.771056 best dqsien dly found for B1: ( 1, 3, 30)
3164 11:04:00.774382 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3165 11:04:00.777536 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3166 11:04:00.777616
3167 11:04:00.780901 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3168 11:04:00.788025 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3169 11:04:00.788144 [Gating] SW calibration Done
3170 11:04:00.788235 ==
3171 11:04:00.791013 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 11:04:00.797949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 11:04:00.798066 ==
3174 11:04:00.798154 RX Vref Scan: 0
3175 11:04:00.798237
3176 11:04:00.802142 RX Vref 0 -> 0, step: 1
3177 11:04:00.802241
3178 11:04:00.804247 RX Delay -40 -> 252, step: 8
3179 11:04:00.807713 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3180 11:04:00.810895 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3181 11:04:00.815376 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3182 11:04:00.820987 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3183 11:04:00.824594 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3184 11:04:00.828021 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3185 11:04:00.830973 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3186 11:04:00.834636 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3187 11:04:00.838118 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3188 11:04:00.844505 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3189 11:04:00.847790 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3190 11:04:00.850783 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3191 11:04:00.854462 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3192 11:04:00.860991 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3193 11:04:00.864434 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3194 11:04:00.867590 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3195 11:04:00.867671 ==
3196 11:04:00.871579 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 11:04:00.874420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 11:04:00.874501 ==
3199 11:04:00.878140 DQS Delay:
3200 11:04:00.878265 DQS0 = 0, DQS1 = 0
3201 11:04:00.878375 DQM Delay:
3202 11:04:00.881282 DQM0 = 115, DQM1 = 108
3203 11:04:00.881383 DQ Delay:
3204 11:04:00.884307 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3205 11:04:00.887798 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =111
3206 11:04:00.891395 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3207 11:04:00.897528 DQ12 =123, DQ13 =115, DQ14 =111, DQ15 =111
3208 11:04:00.897624
3209 11:04:00.897685
3210 11:04:00.897740 ==
3211 11:04:00.901280 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 11:04:00.904848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 11:04:00.904929 ==
3214 11:04:00.904988
3215 11:04:00.905043
3216 11:04:00.907876 TX Vref Scan disable
3217 11:04:00.907953 == TX Byte 0 ==
3218 11:04:00.914586 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3219 11:04:00.917699 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3220 11:04:00.917780 == TX Byte 1 ==
3221 11:04:00.924610 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3222 11:04:00.928362 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3223 11:04:00.928447 ==
3224 11:04:00.931376 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 11:04:00.935066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 11:04:00.935148 ==
3227 11:04:00.947346 TX Vref=22, minBit 2, minWin=24, winSum=405
3228 11:04:00.950480 TX Vref=24, minBit 3, minWin=25, winSum=414
3229 11:04:00.953859 TX Vref=26, minBit 1, minWin=25, winSum=422
3230 11:04:00.957697 TX Vref=28, minBit 15, minWin=25, winSum=425
3231 11:04:00.960648 TX Vref=30, minBit 1, minWin=26, winSum=425
3232 11:04:00.964642 TX Vref=32, minBit 0, minWin=26, winSum=424
3233 11:04:00.970614 [TxChooseVref] Worse bit 1, Min win 26, Win sum 425, Final Vref 30
3234 11:04:00.970709
3235 11:04:00.973858 Final TX Range 1 Vref 30
3236 11:04:00.973962
3237 11:04:00.974049 ==
3238 11:04:00.977296 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 11:04:00.980812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 11:04:00.980917 ==
3241 11:04:00.981002
3242 11:04:00.983945
3243 11:04:00.984038 TX Vref Scan disable
3244 11:04:00.987514 == TX Byte 0 ==
3245 11:04:00.990644 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3246 11:04:00.994496 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3247 11:04:00.997317 == TX Byte 1 ==
3248 11:04:01.000729 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3249 11:04:01.003889 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3250 11:04:01.003968
3251 11:04:01.007404 [DATLAT]
3252 11:04:01.007481 Freq=1200, CH1 RK0
3253 11:04:01.007540
3254 11:04:01.011027 DATLAT Default: 0xd
3255 11:04:01.011126 0, 0xFFFF, sum = 0
3256 11:04:01.014058 1, 0xFFFF, sum = 0
3257 11:04:01.014154 2, 0xFFFF, sum = 0
3258 11:04:01.017297 3, 0xFFFF, sum = 0
3259 11:04:01.017392 4, 0xFFFF, sum = 0
3260 11:04:01.021379 5, 0xFFFF, sum = 0
3261 11:04:01.021486 6, 0xFFFF, sum = 0
3262 11:04:01.024398 7, 0xFFFF, sum = 0
3263 11:04:01.024502 8, 0xFFFF, sum = 0
3264 11:04:01.027578 9, 0xFFFF, sum = 0
3265 11:04:01.030949 10, 0xFFFF, sum = 0
3266 11:04:01.031046 11, 0xFFFF, sum = 0
3267 11:04:01.034163 12, 0x0, sum = 1
3268 11:04:01.034241 13, 0x0, sum = 2
3269 11:04:01.034301 14, 0x0, sum = 3
3270 11:04:01.037312 15, 0x0, sum = 4
3271 11:04:01.037412 best_step = 13
3272 11:04:01.037502
3273 11:04:01.037583 ==
3274 11:04:01.040543 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 11:04:01.047644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 11:04:01.047752 ==
3277 11:04:01.047837 RX Vref Scan: 1
3278 11:04:01.047920
3279 11:04:01.051267 Set Vref Range= 32 -> 127
3280 11:04:01.051357
3281 11:04:01.054094 RX Vref 32 -> 127, step: 1
3282 11:04:01.054187
3283 11:04:01.057976 RX Delay -21 -> 252, step: 4
3284 11:04:01.058072
3285 11:04:01.060885 Set Vref, RX VrefLevel [Byte0]: 32
3286 11:04:01.060980 [Byte1]: 32
3287 11:04:01.065736
3288 11:04:01.065830 Set Vref, RX VrefLevel [Byte0]: 33
3289 11:04:01.068811 [Byte1]: 33
3290 11:04:01.073412
3291 11:04:01.073519 Set Vref, RX VrefLevel [Byte0]: 34
3292 11:04:01.076553 [Byte1]: 34
3293 11:04:01.081778
3294 11:04:01.081884 Set Vref, RX VrefLevel [Byte0]: 35
3295 11:04:01.085204 [Byte1]: 35
3296 11:04:01.089748
3297 11:04:01.089848 Set Vref, RX VrefLevel [Byte0]: 36
3298 11:04:01.092832 [Byte1]: 36
3299 11:04:01.097350
3300 11:04:01.097449 Set Vref, RX VrefLevel [Byte0]: 37
3301 11:04:01.100264 [Byte1]: 37
3302 11:04:01.104901
3303 11:04:01.104998 Set Vref, RX VrefLevel [Byte0]: 38
3304 11:04:01.108389 [Byte1]: 38
3305 11:04:01.112909
3306 11:04:01.113014 Set Vref, RX VrefLevel [Byte0]: 39
3307 11:04:01.116221 [Byte1]: 39
3308 11:04:01.121324
3309 11:04:01.121419 Set Vref, RX VrefLevel [Byte0]: 40
3310 11:04:01.124378 [Byte1]: 40
3311 11:04:01.128785
3312 11:04:01.128881 Set Vref, RX VrefLevel [Byte0]: 41
3313 11:04:01.132030 [Byte1]: 41
3314 11:04:01.136804
3315 11:04:01.136899 Set Vref, RX VrefLevel [Byte0]: 42
3316 11:04:01.140921 [Byte1]: 42
3317 11:04:01.144755
3318 11:04:01.144854 Set Vref, RX VrefLevel [Byte0]: 43
3319 11:04:01.147873 [Byte1]: 43
3320 11:04:01.152598
3321 11:04:01.152695 Set Vref, RX VrefLevel [Byte0]: 44
3322 11:04:01.156312 [Byte1]: 44
3323 11:04:01.160908
3324 11:04:01.161003 Set Vref, RX VrefLevel [Byte0]: 45
3325 11:04:01.163945 [Byte1]: 45
3326 11:04:01.168656
3327 11:04:01.168748 Set Vref, RX VrefLevel [Byte0]: 46
3328 11:04:01.171818 [Byte1]: 46
3329 11:04:01.176324
3330 11:04:01.176418 Set Vref, RX VrefLevel [Byte0]: 47
3331 11:04:01.179855 [Byte1]: 47
3332 11:04:01.184437
3333 11:04:01.184517 Set Vref, RX VrefLevel [Byte0]: 48
3334 11:04:01.187952 [Byte1]: 48
3335 11:04:01.192900
3336 11:04:01.192993 Set Vref, RX VrefLevel [Byte0]: 49
3337 11:04:01.195576 [Byte1]: 49
3338 11:04:01.200237
3339 11:04:01.200330 Set Vref, RX VrefLevel [Byte0]: 50
3340 11:04:01.204263 [Byte1]: 50
3341 11:04:01.208474
3342 11:04:01.208570 Set Vref, RX VrefLevel [Byte0]: 51
3343 11:04:01.211990 [Byte1]: 51
3344 11:04:01.216155
3345 11:04:01.216249 Set Vref, RX VrefLevel [Byte0]: 52
3346 11:04:01.219390 [Byte1]: 52
3347 11:04:01.223882
3348 11:04:01.223973 Set Vref, RX VrefLevel [Byte0]: 53
3349 11:04:01.227527 [Byte1]: 53
3350 11:04:01.231676
3351 11:04:01.231753 Set Vref, RX VrefLevel [Byte0]: 54
3352 11:04:01.235459 [Byte1]: 54
3353 11:04:01.240845
3354 11:04:01.240922 Set Vref, RX VrefLevel [Byte0]: 55
3355 11:04:01.243281 [Byte1]: 55
3356 11:04:01.248405
3357 11:04:01.248482 Set Vref, RX VrefLevel [Byte0]: 56
3358 11:04:01.251289 [Byte1]: 56
3359 11:04:01.255683
3360 11:04:01.255763 Set Vref, RX VrefLevel [Byte0]: 57
3361 11:04:01.259014 [Byte1]: 57
3362 11:04:01.263276
3363 11:04:01.263383 Set Vref, RX VrefLevel [Byte0]: 58
3364 11:04:01.266722 [Byte1]: 58
3365 11:04:01.271417
3366 11:04:01.271498 Set Vref, RX VrefLevel [Byte0]: 59
3367 11:04:01.274862 [Byte1]: 59
3368 11:04:01.279865
3369 11:04:01.279947 Set Vref, RX VrefLevel [Byte0]: 60
3370 11:04:01.282717 [Byte1]: 60
3371 11:04:01.287338
3372 11:04:01.290638 Set Vref, RX VrefLevel [Byte0]: 61
3373 11:04:01.293551 [Byte1]: 61
3374 11:04:01.293656
3375 11:04:01.297111 Set Vref, RX VrefLevel [Byte0]: 62
3376 11:04:01.301279 [Byte1]: 62
3377 11:04:01.301375
3378 11:04:01.304254 Set Vref, RX VrefLevel [Byte0]: 63
3379 11:04:01.307166 [Byte1]: 63
3380 11:04:01.312915
3381 11:04:01.313014 Set Vref, RX VrefLevel [Byte0]: 64
3382 11:04:01.314353 [Byte1]: 64
3383 11:04:01.319654
3384 11:04:01.319764 Set Vref, RX VrefLevel [Byte0]: 65
3385 11:04:01.322650 [Byte1]: 65
3386 11:04:01.326700
3387 11:04:01.326795 Set Vref, RX VrefLevel [Byte0]: 66
3388 11:04:01.330317 [Byte1]: 66
3389 11:04:01.335365
3390 11:04:01.335466 Set Vref, RX VrefLevel [Byte0]: 67
3391 11:04:01.338640 [Byte1]: 67
3392 11:04:01.342988
3393 11:04:01.343089 Set Vref, RX VrefLevel [Byte0]: 68
3394 11:04:01.346396 [Byte1]: 68
3395 11:04:01.350737
3396 11:04:01.350831 Set Vref, RX VrefLevel [Byte0]: 69
3397 11:04:01.354408 [Byte1]: 69
3398 11:04:01.358434
3399 11:04:01.358528 Set Vref, RX VrefLevel [Byte0]: 70
3400 11:04:01.362246 [Byte1]: 70
3401 11:04:01.366735
3402 11:04:01.366829 Final RX Vref Byte 0 = 55 to rank0
3403 11:04:01.369904 Final RX Vref Byte 1 = 47 to rank0
3404 11:04:01.373456 Final RX Vref Byte 0 = 55 to rank1
3405 11:04:01.376581 Final RX Vref Byte 1 = 47 to rank1==
3406 11:04:01.380394 Dram Type= 6, Freq= 0, CH_1, rank 0
3407 11:04:01.383450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3408 11:04:01.386507 ==
3409 11:04:01.386622 DQS Delay:
3410 11:04:01.386708 DQS0 = 0, DQS1 = 0
3411 11:04:01.389934 DQM Delay:
3412 11:04:01.390026 DQM0 = 115, DQM1 = 107
3413 11:04:01.393267 DQ Delay:
3414 11:04:01.396736 DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =112
3415 11:04:01.399793 DQ4 =116, DQ5 =124, DQ6 =126, DQ7 =112
3416 11:04:01.403141 DQ8 =96, DQ9 =96, DQ10 =108, DQ11 =102
3417 11:04:01.407390 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =114
3418 11:04:01.407482
3419 11:04:01.407566
3420 11:04:01.414113 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
3421 11:04:01.416702 CH1 RK0: MR19=403, MR18=2E6
3422 11:04:01.423680 CH1_RK0: MR19=0x403, MR18=0x2E6, DQSOSC=409, MR23=63, INC=39, DEC=26
3423 11:04:01.423762
3424 11:04:01.426633 ----->DramcWriteLeveling(PI) begin...
3425 11:04:01.426711 ==
3426 11:04:01.430515 Dram Type= 6, Freq= 0, CH_1, rank 1
3427 11:04:01.433293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3428 11:04:01.433370 ==
3429 11:04:01.436446 Write leveling (Byte 0): 27 => 27
3430 11:04:01.440854 Write leveling (Byte 1): 30 => 30
3431 11:04:01.443602 DramcWriteLeveling(PI) end<-----
3432 11:04:01.443701
3433 11:04:01.443785 ==
3434 11:04:01.446458 Dram Type= 6, Freq= 0, CH_1, rank 1
3435 11:04:01.449956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3436 11:04:01.453461 ==
3437 11:04:01.453556 [Gating] SW mode calibration
3438 11:04:01.463031 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3439 11:04:01.466555 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3440 11:04:01.470103 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3441 11:04:01.476602 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 11:04:01.479932 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 11:04:01.483506 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 11:04:01.489914 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 11:04:01.493885 0 15 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
3446 11:04:01.496342 0 15 24 | B1->B0 | 3434 2a2a | 1 1 | (1 0) (1 0)
3447 11:04:01.503192 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 11:04:01.506412 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 11:04:01.510103 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 11:04:01.516247 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 11:04:01.519797 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 11:04:01.523217 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 11:04:01.529584 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3454 11:04:01.533069 1 0 24 | B1->B0 | 2424 3b3b | 0 0 | (0 0) (0 0)
3455 11:04:01.536271 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3456 11:04:01.543114 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 11:04:01.546218 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 11:04:01.549548 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 11:04:01.553043 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 11:04:01.560086 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 11:04:01.563039 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3462 11:04:01.566847 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3463 11:04:01.572930 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3464 11:04:01.576157 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 11:04:01.579570 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 11:04:01.586325 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 11:04:01.589561 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 11:04:01.592999 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 11:04:01.599437 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 11:04:01.602929 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 11:04:01.606215 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 11:04:01.612986 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 11:04:01.616749 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 11:04:01.619720 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 11:04:01.626328 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 11:04:01.629729 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 11:04:01.633195 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3478 11:04:01.636406 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3479 11:04:01.643413 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3480 11:04:01.647894 Total UI for P1: 0, mck2ui 16
3481 11:04:01.649825 best dqsien dly found for B0: ( 1, 3, 22)
3482 11:04:01.653236 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 11:04:01.656397 Total UI for P1: 0, mck2ui 16
3484 11:04:01.660230 best dqsien dly found for B1: ( 1, 3, 28)
3485 11:04:01.663202 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3486 11:04:01.667418 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3487 11:04:01.667501
3488 11:04:01.670033 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3489 11:04:01.674231 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3490 11:04:01.676440 [Gating] SW calibration Done
3491 11:04:01.676517 ==
3492 11:04:01.680053 Dram Type= 6, Freq= 0, CH_1, rank 1
3493 11:04:01.683798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 11:04:01.687011 ==
3495 11:04:01.687090 RX Vref Scan: 0
3496 11:04:01.687149
3497 11:04:01.689909 RX Vref 0 -> 0, step: 1
3498 11:04:01.690010
3499 11:04:01.693141 RX Delay -40 -> 252, step: 8
3500 11:04:01.696793 iDelay=192, Bit 0, Center 111 (40 ~ 183) 144
3501 11:04:01.699937 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3502 11:04:01.703822 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3503 11:04:01.706411 iDelay=192, Bit 3, Center 111 (40 ~ 183) 144
3504 11:04:01.713590 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3505 11:04:01.716655 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3506 11:04:01.719697 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3507 11:04:01.723539 iDelay=192, Bit 7, Center 107 (40 ~ 175) 136
3508 11:04:01.726877 iDelay=192, Bit 8, Center 95 (24 ~ 167) 144
3509 11:04:01.729956 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3510 11:04:01.736505 iDelay=192, Bit 10, Center 107 (40 ~ 175) 136
3511 11:04:01.740176 iDelay=192, Bit 11, Center 99 (32 ~ 167) 136
3512 11:04:01.743318 iDelay=192, Bit 12, Center 111 (40 ~ 183) 144
3513 11:04:01.746647 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3514 11:04:01.750025 iDelay=192, Bit 14, Center 115 (48 ~ 183) 136
3515 11:04:01.756604 iDelay=192, Bit 15, Center 115 (48 ~ 183) 136
3516 11:04:01.756769 ==
3517 11:04:01.759774 Dram Type= 6, Freq= 0, CH_1, rank 1
3518 11:04:01.764276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 11:04:01.764364 ==
3520 11:04:01.764426 DQS Delay:
3521 11:04:01.766540 DQS0 = 0, DQS1 = 0
3522 11:04:01.766617 DQM Delay:
3523 11:04:01.769929 DQM0 = 112, DQM1 = 107
3524 11:04:01.770010 DQ Delay:
3525 11:04:01.773297 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =111
3526 11:04:01.776617 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =107
3527 11:04:01.780420 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
3528 11:04:01.783820 DQ12 =111, DQ13 =119, DQ14 =115, DQ15 =115
3529 11:04:01.783907
3530 11:04:01.783967
3531 11:04:01.786387 ==
3532 11:04:01.786464 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 11:04:01.793395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 11:04:01.793509 ==
3535 11:04:01.793585
3536 11:04:01.793654
3537 11:04:01.796829 TX Vref Scan disable
3538 11:04:01.796905 == TX Byte 0 ==
3539 11:04:01.799789 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3540 11:04:01.806642 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3541 11:04:01.806738 == TX Byte 1 ==
3542 11:04:01.810019 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3543 11:04:01.817042 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3544 11:04:01.817159 ==
3545 11:04:01.820531 Dram Type= 6, Freq= 0, CH_1, rank 1
3546 11:04:01.823150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3547 11:04:01.823229 ==
3548 11:04:01.835419 TX Vref=22, minBit 1, minWin=25, winSum=416
3549 11:04:01.838598 TX Vref=24, minBit 0, minWin=26, winSum=419
3550 11:04:01.842118 TX Vref=26, minBit 3, minWin=25, winSum=424
3551 11:04:01.845123 TX Vref=28, minBit 0, minWin=26, winSum=428
3552 11:04:01.848491 TX Vref=30, minBit 4, minWin=26, winSum=430
3553 11:04:01.852080 TX Vref=32, minBit 2, minWin=26, winSum=431
3554 11:04:01.859025 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 32
3555 11:04:01.859226
3556 11:04:01.861928 Final TX Range 1 Vref 32
3557 11:04:01.862053
3558 11:04:01.862141 ==
3559 11:04:01.865777 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 11:04:01.869208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 11:04:01.869383 ==
3562 11:04:01.869502
3563 11:04:01.869585
3564 11:04:01.872588 TX Vref Scan disable
3565 11:04:01.875816 == TX Byte 0 ==
3566 11:04:01.879736 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3567 11:04:01.882935 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3568 11:04:01.886281 == TX Byte 1 ==
3569 11:04:01.889427 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3570 11:04:01.893094 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3571 11:04:01.893406
3572 11:04:01.893545 [DATLAT]
3573 11:04:01.896515 Freq=1200, CH1 RK1
3574 11:04:01.896716
3575 11:04:01.899496 DATLAT Default: 0xd
3576 11:04:01.899697 0, 0xFFFF, sum = 0
3577 11:04:01.903232 1, 0xFFFF, sum = 0
3578 11:04:01.903437 2, 0xFFFF, sum = 0
3579 11:04:01.906232 3, 0xFFFF, sum = 0
3580 11:04:01.906429 4, 0xFFFF, sum = 0
3581 11:04:01.909269 5, 0xFFFF, sum = 0
3582 11:04:01.909471 6, 0xFFFF, sum = 0
3583 11:04:01.912630 7, 0xFFFF, sum = 0
3584 11:04:01.912812 8, 0xFFFF, sum = 0
3585 11:04:01.916273 9, 0xFFFF, sum = 0
3586 11:04:01.916416 10, 0xFFFF, sum = 0
3587 11:04:01.919765 11, 0xFFFF, sum = 0
3588 11:04:01.919872 12, 0x0, sum = 1
3589 11:04:01.923074 13, 0x0, sum = 2
3590 11:04:01.923179 14, 0x0, sum = 3
3591 11:04:01.926602 15, 0x0, sum = 4
3592 11:04:01.926709 best_step = 13
3593 11:04:01.926795
3594 11:04:01.926878 ==
3595 11:04:01.929825 Dram Type= 6, Freq= 0, CH_1, rank 1
3596 11:04:01.933260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3597 11:04:01.933366 ==
3598 11:04:01.936388 RX Vref Scan: 0
3599 11:04:01.936486
3600 11:04:01.939515 RX Vref 0 -> 0, step: 1
3601 11:04:01.939615
3602 11:04:01.939703 RX Delay -21 -> 252, step: 4
3603 11:04:01.946885 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3604 11:04:01.950117 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3605 11:04:01.953684 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3606 11:04:01.957280 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3607 11:04:01.960330 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3608 11:04:01.967080 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3609 11:04:01.970335 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3610 11:04:01.973796 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3611 11:04:01.977230 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3612 11:04:01.980386 iDelay=191, Bit 9, Center 96 (31 ~ 162) 132
3613 11:04:01.987140 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3614 11:04:01.990446 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3615 11:04:01.994696 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3616 11:04:01.997379 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3617 11:04:02.000948 iDelay=191, Bit 14, Center 116 (55 ~ 178) 124
3618 11:04:02.007813 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3619 11:04:02.007937 ==
3620 11:04:02.010722 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 11:04:02.013962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 11:04:02.014067 ==
3623 11:04:02.014154 DQS Delay:
3624 11:04:02.017297 DQS0 = 0, DQS1 = 0
3625 11:04:02.017397 DQM Delay:
3626 11:04:02.021028 DQM0 = 113, DQM1 = 108
3627 11:04:02.021168 DQ Delay:
3628 11:04:02.023992 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3629 11:04:02.027147 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3630 11:04:02.030678 DQ8 =96, DQ9 =96, DQ10 =110, DQ11 =100
3631 11:04:02.035664 DQ12 =114, DQ13 =118, DQ14 =116, DQ15 =116
3632 11:04:02.035772
3633 11:04:02.035854
3634 11:04:02.043875 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa02, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3635 11:04:02.047481 CH1 RK1: MR19=304, MR18=FA02
3636 11:04:02.050966 CH1_RK1: MR19=0x304, MR18=0xFA02, DQSOSC=409, MR23=63, INC=39, DEC=26
3637 11:04:02.054488 [RxdqsGatingPostProcess] freq 1200
3638 11:04:02.060471 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3639 11:04:02.063911 best DQS0 dly(2T, 0.5T) = (0, 11)
3640 11:04:02.067431 best DQS1 dly(2T, 0.5T) = (0, 11)
3641 11:04:02.071559 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3642 11:04:02.073910 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3643 11:04:02.077306 best DQS0 dly(2T, 0.5T) = (0, 11)
3644 11:04:02.080483 best DQS1 dly(2T, 0.5T) = (0, 11)
3645 11:04:02.084593 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3646 11:04:02.084698 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3647 11:04:02.087539 Pre-setting of DQS Precalculation
3648 11:04:02.094065 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3649 11:04:02.100957 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3650 11:04:02.107723 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3651 11:04:02.107849
3652 11:04:02.107938
3653 11:04:02.110865 [Calibration Summary] 2400 Mbps
3654 11:04:02.114171 CH 0, Rank 0
3655 11:04:02.114269 SW Impedance : PASS
3656 11:04:02.117612 DUTY Scan : NO K
3657 11:04:02.117708 ZQ Calibration : PASS
3658 11:04:02.120728 Jitter Meter : NO K
3659 11:04:02.124639 CBT Training : PASS
3660 11:04:02.124769 Write leveling : PASS
3661 11:04:02.127568 RX DQS gating : PASS
3662 11:04:02.130987 RX DQ/DQS(RDDQC) : PASS
3663 11:04:02.131084 TX DQ/DQS : PASS
3664 11:04:02.134113 RX DATLAT : PASS
3665 11:04:02.137903 RX DQ/DQS(Engine): PASS
3666 11:04:02.138004 TX OE : NO K
3667 11:04:02.138087 All Pass.
3668 11:04:02.140908
3669 11:04:02.141001 CH 0, Rank 1
3670 11:04:02.144662 SW Impedance : PASS
3671 11:04:02.144758 DUTY Scan : NO K
3672 11:04:02.148186 ZQ Calibration : PASS
3673 11:04:02.148287 Jitter Meter : NO K
3674 11:04:02.151106 CBT Training : PASS
3675 11:04:02.154803 Write leveling : PASS
3676 11:04:02.154907 RX DQS gating : PASS
3677 11:04:02.158258 RX DQ/DQS(RDDQC) : PASS
3678 11:04:02.161186 TX DQ/DQS : PASS
3679 11:04:02.161289 RX DATLAT : PASS
3680 11:04:02.164914 RX DQ/DQS(Engine): PASS
3681 11:04:02.167954 TX OE : NO K
3682 11:04:02.168055 All Pass.
3683 11:04:02.168140
3684 11:04:02.168221 CH 1, Rank 0
3685 11:04:02.171149 SW Impedance : PASS
3686 11:04:02.175332 DUTY Scan : NO K
3687 11:04:02.175454 ZQ Calibration : PASS
3688 11:04:02.178194 Jitter Meter : NO K
3689 11:04:02.181051 CBT Training : PASS
3690 11:04:02.181192 Write leveling : PASS
3691 11:04:02.184914 RX DQS gating : PASS
3692 11:04:02.185019 RX DQ/DQS(RDDQC) : PASS
3693 11:04:02.187636 TX DQ/DQS : PASS
3694 11:04:02.191204 RX DATLAT : PASS
3695 11:04:02.191307 RX DQ/DQS(Engine): PASS
3696 11:04:02.194355 TX OE : NO K
3697 11:04:02.194456 All Pass.
3698 11:04:02.194543
3699 11:04:02.198181 CH 1, Rank 1
3700 11:04:02.198281 SW Impedance : PASS
3701 11:04:02.201398 DUTY Scan : NO K
3702 11:04:02.204966 ZQ Calibration : PASS
3703 11:04:02.205073 Jitter Meter : NO K
3704 11:04:02.207957 CBT Training : PASS
3705 11:04:02.211546 Write leveling : PASS
3706 11:04:02.211650 RX DQS gating : PASS
3707 11:04:02.214517 RX DQ/DQS(RDDQC) : PASS
3708 11:04:02.218097 TX DQ/DQS : PASS
3709 11:04:02.218195 RX DATLAT : PASS
3710 11:04:02.222167 RX DQ/DQS(Engine): PASS
3711 11:04:02.225267 TX OE : NO K
3712 11:04:02.225351 All Pass.
3713 11:04:02.225414
3714 11:04:02.225503 DramC Write-DBI off
3715 11:04:02.227986 PER_BANK_REFRESH: Hybrid Mode
3716 11:04:02.231600 TX_TRACKING: ON
3717 11:04:02.237989 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3718 11:04:02.241441 [FAST_K] Save calibration result to emmc
3719 11:04:02.247556 dramc_set_vcore_voltage set vcore to 650000
3720 11:04:02.247673 Read voltage for 600, 5
3721 11:04:02.251704 Vio18 = 0
3722 11:04:02.251806 Vcore = 650000
3723 11:04:02.251892 Vdram = 0
3724 11:04:02.251975 Vddq = 0
3725 11:04:02.254481 Vmddr = 0
3726 11:04:02.258045 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3727 11:04:02.264749 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3728 11:04:02.267481 MEM_TYPE=3, freq_sel=19
3729 11:04:02.267586 sv_algorithm_assistance_LP4_1600
3730 11:04:02.274200 ============ PULL DRAM RESETB DOWN ============
3731 11:04:02.277754 ========== PULL DRAM RESETB DOWN end =========
3732 11:04:02.282148 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3733 11:04:02.284755 ===================================
3734 11:04:02.287524 LPDDR4 DRAM CONFIGURATION
3735 11:04:02.290927 ===================================
3736 11:04:02.294052 EX_ROW_EN[0] = 0x0
3737 11:04:02.294167 EX_ROW_EN[1] = 0x0
3738 11:04:02.297709 LP4Y_EN = 0x0
3739 11:04:02.297812 WORK_FSP = 0x0
3740 11:04:02.301018 WL = 0x2
3741 11:04:02.301142 RL = 0x2
3742 11:04:02.304327 BL = 0x2
3743 11:04:02.304427 RPST = 0x0
3744 11:04:02.307653 RD_PRE = 0x0
3745 11:04:02.307752 WR_PRE = 0x1
3746 11:04:02.311230 WR_PST = 0x0
3747 11:04:02.311334 DBI_WR = 0x0
3748 11:04:02.314633 DBI_RD = 0x0
3749 11:04:02.314731 OTF = 0x1
3750 11:04:02.317630 ===================================
3751 11:04:02.320914 ===================================
3752 11:04:02.325006 ANA top config
3753 11:04:02.327735 ===================================
3754 11:04:02.331131 DLL_ASYNC_EN = 0
3755 11:04:02.331235 ALL_SLAVE_EN = 1
3756 11:04:02.334174 NEW_RANK_MODE = 1
3757 11:04:02.338012 DLL_IDLE_MODE = 1
3758 11:04:02.340682 LP45_APHY_COMB_EN = 1
3759 11:04:02.340827 TX_ODT_DIS = 1
3760 11:04:02.344563 NEW_8X_MODE = 1
3761 11:04:02.347716 ===================================
3762 11:04:02.350892 ===================================
3763 11:04:02.354139 data_rate = 1200
3764 11:04:02.357985 CKR = 1
3765 11:04:02.361424 DQ_P2S_RATIO = 8
3766 11:04:02.364832 ===================================
3767 11:04:02.367541 CA_P2S_RATIO = 8
3768 11:04:02.367643 DQ_CA_OPEN = 0
3769 11:04:02.370788 DQ_SEMI_OPEN = 0
3770 11:04:02.374461 CA_SEMI_OPEN = 0
3771 11:04:02.378123 CA_FULL_RATE = 0
3772 11:04:02.380916 DQ_CKDIV4_EN = 1
3773 11:04:02.384201 CA_CKDIV4_EN = 1
3774 11:04:02.384311 CA_PREDIV_EN = 0
3775 11:04:02.387521 PH8_DLY = 0
3776 11:04:02.391027 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3777 11:04:02.394464 DQ_AAMCK_DIV = 4
3778 11:04:02.397543 CA_AAMCK_DIV = 4
3779 11:04:02.397648 CA_ADMCK_DIV = 4
3780 11:04:02.400731 DQ_TRACK_CA_EN = 0
3781 11:04:02.404270 CA_PICK = 600
3782 11:04:02.407951 CA_MCKIO = 600
3783 11:04:02.410918 MCKIO_SEMI = 0
3784 11:04:02.414498 PLL_FREQ = 2288
3785 11:04:02.417516 DQ_UI_PI_RATIO = 32
3786 11:04:02.417631 CA_UI_PI_RATIO = 0
3787 11:04:02.421898 ===================================
3788 11:04:02.424765 ===================================
3789 11:04:02.428255 memory_type:LPDDR4
3790 11:04:02.431933 GP_NUM : 10
3791 11:04:02.432050 SRAM_EN : 1
3792 11:04:02.434754 MD32_EN : 0
3793 11:04:02.438062 ===================================
3794 11:04:02.441039 [ANA_INIT] >>>>>>>>>>>>>>
3795 11:04:02.444476 <<<<<< [CONFIGURE PHASE]: ANA_TX
3796 11:04:02.448223 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3797 11:04:02.451039 ===================================
3798 11:04:02.451162 data_rate = 1200,PCW = 0X5800
3799 11:04:02.454454 ===================================
3800 11:04:02.457762 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3801 11:04:02.464788 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3802 11:04:02.471753 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3803 11:04:02.475536 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3804 11:04:02.477740 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3805 11:04:02.481315 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3806 11:04:02.484373 [ANA_INIT] flow start
3807 11:04:02.484501 [ANA_INIT] PLL >>>>>>>>
3808 11:04:02.487747 [ANA_INIT] PLL <<<<<<<<
3809 11:04:02.491494 [ANA_INIT] MIDPI >>>>>>>>
3810 11:04:02.491609 [ANA_INIT] MIDPI <<<<<<<<
3811 11:04:02.495221 [ANA_INIT] DLL >>>>>>>>
3812 11:04:02.498018 [ANA_INIT] flow end
3813 11:04:02.501212 ============ LP4 DIFF to SE enter ============
3814 11:04:02.504503 ============ LP4 DIFF to SE exit ============
3815 11:04:02.508104 [ANA_INIT] <<<<<<<<<<<<<
3816 11:04:02.511709 [Flow] Enable top DCM control >>>>>
3817 11:04:02.514827 [Flow] Enable top DCM control <<<<<
3818 11:04:02.517792 Enable DLL master slave shuffle
3819 11:04:02.521791 ==============================================================
3820 11:04:02.525156 Gating Mode config
3821 11:04:02.532163 ==============================================================
3822 11:04:02.532289 Config description:
3823 11:04:02.541159 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3824 11:04:02.547886 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3825 11:04:02.551634 SELPH_MODE 0: By rank 1: By Phase
3826 11:04:02.557967 ==============================================================
3827 11:04:02.561565 GAT_TRACK_EN = 1
3828 11:04:02.564638 RX_GATING_MODE = 2
3829 11:04:02.568135 RX_GATING_TRACK_MODE = 2
3830 11:04:02.571930 SELPH_MODE = 1
3831 11:04:02.574925 PICG_EARLY_EN = 1
3832 11:04:02.578122 VALID_LAT_VALUE = 1
3833 11:04:02.581499 ==============================================================
3834 11:04:02.585223 Enter into Gating configuration >>>>
3835 11:04:02.588413 Exit from Gating configuration <<<<
3836 11:04:02.591337 Enter into DVFS_PRE_config >>>>>
3837 11:04:02.601551 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3838 11:04:02.604690 Exit from DVFS_PRE_config <<<<<
3839 11:04:02.608281 Enter into PICG configuration >>>>
3840 11:04:02.611641 Exit from PICG configuration <<<<
3841 11:04:02.614887 [RX_INPUT] configuration >>>>>
3842 11:04:02.618704 [RX_INPUT] configuration <<<<<
3843 11:04:02.621259 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3844 11:04:02.628028 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3845 11:04:02.634922 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3846 11:04:02.641791 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3847 11:04:02.648509 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3848 11:04:02.652217 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3849 11:04:02.658345 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3850 11:04:02.662288 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3851 11:04:02.664861 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3852 11:04:02.668881 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3853 11:04:02.672057 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3854 11:04:02.679184 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3855 11:04:02.682276 ===================================
3856 11:04:02.685018 LPDDR4 DRAM CONFIGURATION
3857 11:04:02.688629 ===================================
3858 11:04:02.688733 EX_ROW_EN[0] = 0x0
3859 11:04:02.692695 EX_ROW_EN[1] = 0x0
3860 11:04:02.692809 LP4Y_EN = 0x0
3861 11:04:02.694966 WORK_FSP = 0x0
3862 11:04:02.695070 WL = 0x2
3863 11:04:02.698599 RL = 0x2
3864 11:04:02.698684 BL = 0x2
3865 11:04:02.702787 RPST = 0x0
3866 11:04:02.702870 RD_PRE = 0x0
3867 11:04:02.705005 WR_PRE = 0x1
3868 11:04:02.705109 WR_PST = 0x0
3869 11:04:02.708283 DBI_WR = 0x0
3870 11:04:02.708360 DBI_RD = 0x0
3871 11:04:02.712079 OTF = 0x1
3872 11:04:02.715006 ===================================
3873 11:04:02.718474 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3874 11:04:02.721630 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3875 11:04:02.728642 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3876 11:04:02.732652 ===================================
3877 11:04:02.732764 LPDDR4 DRAM CONFIGURATION
3878 11:04:02.735739 ===================================
3879 11:04:02.738442 EX_ROW_EN[0] = 0x10
3880 11:04:02.742255 EX_ROW_EN[1] = 0x0
3881 11:04:02.742356 LP4Y_EN = 0x0
3882 11:04:02.745216 WORK_FSP = 0x0
3883 11:04:02.745312 WL = 0x2
3884 11:04:02.748424 RL = 0x2
3885 11:04:02.748519 BL = 0x2
3886 11:04:02.752045 RPST = 0x0
3887 11:04:02.752142 RD_PRE = 0x0
3888 11:04:02.756148 WR_PRE = 0x1
3889 11:04:02.756253 WR_PST = 0x0
3890 11:04:02.758490 DBI_WR = 0x0
3891 11:04:02.758595 DBI_RD = 0x0
3892 11:04:02.761938 OTF = 0x1
3893 11:04:02.765730 ===================================
3894 11:04:02.772394 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3895 11:04:02.775808 nWR fixed to 30
3896 11:04:02.775921 [ModeRegInit_LP4] CH0 RK0
3897 11:04:02.778703 [ModeRegInit_LP4] CH0 RK1
3898 11:04:02.782027 [ModeRegInit_LP4] CH1 RK0
3899 11:04:02.782131 [ModeRegInit_LP4] CH1 RK1
3900 11:04:02.785701 match AC timing 17
3901 11:04:02.789189 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3902 11:04:02.792047 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3903 11:04:02.799355 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3904 11:04:02.802069 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3905 11:04:02.808885 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3906 11:04:02.809039 ==
3907 11:04:02.812549 Dram Type= 6, Freq= 0, CH_0, rank 0
3908 11:04:02.815687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3909 11:04:02.815799 ==
3910 11:04:02.822042 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3911 11:04:02.825429 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3912 11:04:02.829916 [CA 0] Center 36 (6~66) winsize 61
3913 11:04:02.833300 [CA 1] Center 36 (6~66) winsize 61
3914 11:04:02.836354 [CA 2] Center 34 (4~65) winsize 62
3915 11:04:02.839450 [CA 3] Center 34 (4~65) winsize 62
3916 11:04:02.842903 [CA 4] Center 33 (3~64) winsize 62
3917 11:04:02.846972 [CA 5] Center 33 (3~64) winsize 62
3918 11:04:02.847076
3919 11:04:02.849924 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3920 11:04:02.850026
3921 11:04:02.852885 [CATrainingPosCal] consider 1 rank data
3922 11:04:02.856156 u2DelayCellTimex100 = 270/100 ps
3923 11:04:02.859673 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3924 11:04:02.863160 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3925 11:04:02.869560 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3926 11:04:02.873093 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3927 11:04:02.876147 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3928 11:04:02.880309 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3929 11:04:02.880417
3930 11:04:02.883573 CA PerBit enable=1, Macro0, CA PI delay=33
3931 11:04:02.883691
3932 11:04:02.886855 [CBTSetCACLKResult] CA Dly = 33
3933 11:04:02.886937 CS Dly: 4 (0~35)
3934 11:04:02.887012 ==
3935 11:04:02.889468 Dram Type= 6, Freq= 0, CH_0, rank 1
3936 11:04:02.896195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3937 11:04:02.896289 ==
3938 11:04:02.899584 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3939 11:04:02.906511 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3940 11:04:02.909832 [CA 0] Center 36 (6~66) winsize 61
3941 11:04:02.913066 [CA 1] Center 36 (6~66) winsize 61
3942 11:04:02.916398 [CA 2] Center 34 (4~65) winsize 62
3943 11:04:02.919733 [CA 3] Center 34 (4~64) winsize 61
3944 11:04:02.923306 [CA 4] Center 33 (3~64) winsize 62
3945 11:04:02.926534 [CA 5] Center 33 (3~64) winsize 62
3946 11:04:02.926648
3947 11:04:02.930365 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3948 11:04:02.930474
3949 11:04:02.933019 [CATrainingPosCal] consider 2 rank data
3950 11:04:02.936810 u2DelayCellTimex100 = 270/100 ps
3951 11:04:02.939820 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3952 11:04:02.943108 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3953 11:04:02.950071 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3954 11:04:02.954143 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3955 11:04:02.956446 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3956 11:04:02.960394 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3957 11:04:02.960509
3958 11:04:02.963259 CA PerBit enable=1, Macro0, CA PI delay=33
3959 11:04:02.963365
3960 11:04:02.966471 [CBTSetCACLKResult] CA Dly = 33
3961 11:04:02.966647 CS Dly: 4 (0~36)
3962 11:04:02.966748
3963 11:04:02.969903 ----->DramcWriteLeveling(PI) begin...
3964 11:04:02.973442 ==
3965 11:04:02.973545 Dram Type= 6, Freq= 0, CH_0, rank 0
3966 11:04:02.979644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3967 11:04:02.979754 ==
3968 11:04:02.982978 Write leveling (Byte 0): 33 => 33
3969 11:04:02.986738 Write leveling (Byte 1): 29 => 29
3970 11:04:02.989801 DramcWriteLeveling(PI) end<-----
3971 11:04:02.989910
3972 11:04:02.989995 ==
3973 11:04:02.993131 Dram Type= 6, Freq= 0, CH_0, rank 0
3974 11:04:02.996723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3975 11:04:02.996826 ==
3976 11:04:02.999965 [Gating] SW mode calibration
3977 11:04:03.006263 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3978 11:04:03.010047 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3979 11:04:03.016539 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3980 11:04:03.019629 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3981 11:04:03.023042 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 11:04:03.030042 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3983 11:04:03.033681 0 9 16 | B1->B0 | 3131 2525 | 1 1 | (0 1) (1 0)
3984 11:04:03.037615 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3985 11:04:03.043261 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 11:04:03.046640 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 11:04:03.049955 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 11:04:03.056346 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 11:04:03.059733 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 11:04:03.063279 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3991 11:04:03.070301 0 10 16 | B1->B0 | 3232 4141 | 0 0 | (0 0) (0 0)
3992 11:04:03.073090 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 11:04:03.076888 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 11:04:03.083076 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 11:04:03.086652 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 11:04:03.089959 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 11:04:03.093039 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 11:04:03.099597 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 11:04:03.103538 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4000 11:04:03.106278 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 11:04:03.112752 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 11:04:03.117246 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 11:04:03.119565 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 11:04:03.126317 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 11:04:03.129529 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 11:04:03.132935 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 11:04:03.139705 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 11:04:03.143320 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 11:04:03.146503 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 11:04:03.152971 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 11:04:03.156588 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 11:04:03.160391 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 11:04:03.167413 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 11:04:03.170271 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4015 11:04:03.173222 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4016 11:04:03.176386 Total UI for P1: 0, mck2ui 16
4017 11:04:03.180114 best dqsien dly found for B0: ( 0, 13, 12)
4018 11:04:03.183557 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 11:04:03.186972 Total UI for P1: 0, mck2ui 16
4020 11:04:03.190020 best dqsien dly found for B1: ( 0, 13, 16)
4021 11:04:03.193171 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4022 11:04:03.199736 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4023 11:04:03.199855
4024 11:04:03.203049 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4025 11:04:03.206610 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4026 11:04:03.209575 [Gating] SW calibration Done
4027 11:04:03.209676 ==
4028 11:04:03.213275 Dram Type= 6, Freq= 0, CH_0, rank 0
4029 11:04:03.216519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4030 11:04:03.216618 ==
4031 11:04:03.216702 RX Vref Scan: 0
4032 11:04:03.219958
4033 11:04:03.220055 RX Vref 0 -> 0, step: 1
4034 11:04:03.220138
4035 11:04:03.224009 RX Delay -230 -> 252, step: 16
4036 11:04:03.226807 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4037 11:04:03.232996 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4038 11:04:03.236812 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4039 11:04:03.240530 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4040 11:04:03.243442 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4041 11:04:03.246945 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4042 11:04:03.253316 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4043 11:04:03.256928 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4044 11:04:03.260307 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4045 11:04:03.263469 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4046 11:04:03.266669 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4047 11:04:03.273647 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4048 11:04:03.277003 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4049 11:04:03.280452 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4050 11:04:03.283865 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4051 11:04:03.290212 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4052 11:04:03.290329 ==
4053 11:04:03.293819 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 11:04:03.297137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 11:04:03.297252 ==
4056 11:04:03.297338 DQS Delay:
4057 11:04:03.300093 DQS0 = 0, DQS1 = 0
4058 11:04:03.300189 DQM Delay:
4059 11:04:03.303633 DQM0 = 40, DQM1 = 31
4060 11:04:03.303732 DQ Delay:
4061 11:04:03.307018 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4062 11:04:03.310004 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4063 11:04:03.313429 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4064 11:04:03.316883 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4065 11:04:03.316981
4066 11:04:03.317064
4067 11:04:03.317175 ==
4068 11:04:03.320292 Dram Type= 6, Freq= 0, CH_0, rank 0
4069 11:04:03.323309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4070 11:04:03.323408 ==
4071 11:04:03.323492
4072 11:04:03.326827
4073 11:04:03.326927 TX Vref Scan disable
4074 11:04:03.330086 == TX Byte 0 ==
4075 11:04:03.333723 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4076 11:04:03.336841 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4077 11:04:03.340404 == TX Byte 1 ==
4078 11:04:03.343744 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4079 11:04:03.346710 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4080 11:04:03.346812 ==
4081 11:04:03.350693 Dram Type= 6, Freq= 0, CH_0, rank 0
4082 11:04:03.356755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4083 11:04:03.356862 ==
4084 11:04:03.356947
4085 11:04:03.357026
4086 11:04:03.357103 TX Vref Scan disable
4087 11:04:03.361349 == TX Byte 0 ==
4088 11:04:03.364632 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4089 11:04:03.368185 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4090 11:04:03.371618 == TX Byte 1 ==
4091 11:04:03.375125 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4092 11:04:03.377799 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4093 11:04:03.382218
4094 11:04:03.382319 [DATLAT]
4095 11:04:03.382404 Freq=600, CH0 RK0
4096 11:04:03.382487
4097 11:04:03.385035 DATLAT Default: 0x9
4098 11:04:03.385158 0, 0xFFFF, sum = 0
4099 11:04:03.387889 1, 0xFFFF, sum = 0
4100 11:04:03.387990 2, 0xFFFF, sum = 0
4101 11:04:03.392141 3, 0xFFFF, sum = 0
4102 11:04:03.392243 4, 0xFFFF, sum = 0
4103 11:04:03.394520 5, 0xFFFF, sum = 0
4104 11:04:03.397938 6, 0xFFFF, sum = 0
4105 11:04:03.398042 7, 0xFFFF, sum = 0
4106 11:04:03.398129 8, 0x0, sum = 1
4107 11:04:03.400984 9, 0x0, sum = 2
4108 11:04:03.401099 10, 0x0, sum = 3
4109 11:04:03.404319 11, 0x0, sum = 4
4110 11:04:03.404416 best_step = 9
4111 11:04:03.404502
4112 11:04:03.404583 ==
4113 11:04:03.408245 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 11:04:03.414498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 11:04:03.414607 ==
4116 11:04:03.414693 RX Vref Scan: 1
4117 11:04:03.414774
4118 11:04:03.418294 RX Vref 0 -> 0, step: 1
4119 11:04:03.418390
4120 11:04:03.421081 RX Delay -195 -> 252, step: 8
4121 11:04:03.421217
4122 11:04:03.424467 Set Vref, RX VrefLevel [Byte0]: 52
4123 11:04:03.428029 [Byte1]: 51
4124 11:04:03.428131
4125 11:04:03.431170 Final RX Vref Byte 0 = 52 to rank0
4126 11:04:03.434673 Final RX Vref Byte 1 = 51 to rank0
4127 11:04:03.438566 Final RX Vref Byte 0 = 52 to rank1
4128 11:04:03.441232 Final RX Vref Byte 1 = 51 to rank1==
4129 11:04:03.444677 Dram Type= 6, Freq= 0, CH_0, rank 0
4130 11:04:03.447877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 11:04:03.447977 ==
4132 11:04:03.451259 DQS Delay:
4133 11:04:03.451358 DQS0 = 0, DQS1 = 0
4134 11:04:03.451445 DQM Delay:
4135 11:04:03.454781 DQM0 = 42, DQM1 = 33
4136 11:04:03.454878 DQ Delay:
4137 11:04:03.458699 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4138 11:04:03.461670 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4139 11:04:03.464994 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4140 11:04:03.467978 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4141 11:04:03.468079
4142 11:04:03.468163
4143 11:04:03.478850 [DQSOSCAuto] RK0, (LSB)MR18= 0x4322, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
4144 11:04:03.478969 CH0 RK0: MR19=808, MR18=4322
4145 11:04:03.484661 CH0_RK0: MR19=0x808, MR18=0x4322, DQSOSC=397, MR23=63, INC=166, DEC=110
4146 11:04:03.484785
4147 11:04:03.488405 ----->DramcWriteLeveling(PI) begin...
4148 11:04:03.488508 ==
4149 11:04:03.491487 Dram Type= 6, Freq= 0, CH_0, rank 1
4150 11:04:03.499175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 11:04:03.499291 ==
4152 11:04:03.502018 Write leveling (Byte 0): 31 => 31
4153 11:04:03.504951 Write leveling (Byte 1): 32 => 32
4154 11:04:03.505052 DramcWriteLeveling(PI) end<-----
4155 11:04:03.505179
4156 11:04:03.508273 ==
4157 11:04:03.511606 Dram Type= 6, Freq= 0, CH_0, rank 1
4158 11:04:03.515080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 11:04:03.515183 ==
4160 11:04:03.518822 [Gating] SW mode calibration
4161 11:04:03.524993 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4162 11:04:03.528323 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4163 11:04:03.535406 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4164 11:04:03.538325 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4165 11:04:03.541581 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4166 11:04:03.548437 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
4167 11:04:03.551652 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
4168 11:04:03.555054 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 11:04:03.561356 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 11:04:03.564964 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 11:04:03.568071 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 11:04:03.571754 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 11:04:03.578404 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 11:04:03.581513 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
4175 11:04:03.585409 0 10 16 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
4176 11:04:03.591715 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 11:04:03.595258 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 11:04:03.598762 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 11:04:03.605525 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 11:04:03.608455 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 11:04:03.612176 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 11:04:03.618600 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4183 11:04:03.622287 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 11:04:03.625929 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 11:04:03.628831 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 11:04:03.635857 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 11:04:03.638496 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 11:04:03.641961 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 11:04:03.648794 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 11:04:03.651740 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 11:04:03.655376 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 11:04:03.662620 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 11:04:03.665906 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 11:04:03.668899 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 11:04:03.675788 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 11:04:03.679396 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 11:04:03.683438 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 11:04:03.688992 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4199 11:04:03.692670 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4200 11:04:03.695324 Total UI for P1: 0, mck2ui 16
4201 11:04:03.699608 best dqsien dly found for B0: ( 0, 13, 12)
4202 11:04:03.702256 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 11:04:03.705883 Total UI for P1: 0, mck2ui 16
4204 11:04:03.709208 best dqsien dly found for B1: ( 0, 13, 16)
4205 11:04:03.712211 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4206 11:04:03.715835 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4207 11:04:03.715937
4208 11:04:03.719338 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4209 11:04:03.725662 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4210 11:04:03.725773 [Gating] SW calibration Done
4211 11:04:03.725859 ==
4212 11:04:03.729109 Dram Type= 6, Freq= 0, CH_0, rank 1
4213 11:04:03.735931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4214 11:04:03.736040 ==
4215 11:04:03.736127 RX Vref Scan: 0
4216 11:04:03.736210
4217 11:04:03.739126 RX Vref 0 -> 0, step: 1
4218 11:04:03.739223
4219 11:04:03.742419 RX Delay -230 -> 252, step: 16
4220 11:04:03.746293 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4221 11:04:03.749632 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4222 11:04:03.752414 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4223 11:04:03.758996 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4224 11:04:03.762387 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4225 11:04:03.765719 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4226 11:04:03.768947 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4227 11:04:03.772716 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4228 11:04:03.778993 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4229 11:04:03.782131 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4230 11:04:03.785917 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4231 11:04:03.789305 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4232 11:04:03.795631 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4233 11:04:03.799130 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4234 11:04:03.802710 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4235 11:04:03.805930 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4236 11:04:03.806032 ==
4237 11:04:03.809238 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 11:04:03.816623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 11:04:03.816730 ==
4240 11:04:03.816818 DQS Delay:
4241 11:04:03.819521 DQS0 = 0, DQS1 = 0
4242 11:04:03.819620 DQM Delay:
4243 11:04:03.819705 DQM0 = 41, DQM1 = 31
4244 11:04:03.823175 DQ Delay:
4245 11:04:03.826060 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4246 11:04:03.829330 DQ4 =41, DQ5 =25, DQ6 =57, DQ7 =57
4247 11:04:03.833205 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4248 11:04:03.836024 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4249 11:04:03.836127
4250 11:04:03.836212
4251 11:04:03.836294 ==
4252 11:04:03.839396 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 11:04:03.842541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 11:04:03.842642 ==
4255 11:04:03.842727
4256 11:04:03.842808
4257 11:04:03.846355 TX Vref Scan disable
4258 11:04:03.846455 == TX Byte 0 ==
4259 11:04:03.853619 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4260 11:04:03.856254 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4261 11:04:03.856356 == TX Byte 1 ==
4262 11:04:03.862862 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4263 11:04:03.866956 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4264 11:04:03.867060 ==
4265 11:04:03.869542 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 11:04:03.872750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 11:04:03.872850 ==
4268 11:04:03.872935
4269 11:04:03.873015
4270 11:04:03.876131 TX Vref Scan disable
4271 11:04:03.879240 == TX Byte 0 ==
4272 11:04:03.882990 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4273 11:04:03.885973 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4274 11:04:03.889154 == TX Byte 1 ==
4275 11:04:03.893517 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4276 11:04:03.895932 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4277 11:04:03.896031
4278 11:04:03.899445 [DATLAT]
4279 11:04:03.899544 Freq=600, CH0 RK1
4280 11:04:03.899630
4281 11:04:03.903041 DATLAT Default: 0x9
4282 11:04:03.903140 0, 0xFFFF, sum = 0
4283 11:04:03.906399 1, 0xFFFF, sum = 0
4284 11:04:03.906501 2, 0xFFFF, sum = 0
4285 11:04:03.910095 3, 0xFFFF, sum = 0
4286 11:04:03.910195 4, 0xFFFF, sum = 0
4287 11:04:03.912838 5, 0xFFFF, sum = 0
4288 11:04:03.912956 6, 0xFFFF, sum = 0
4289 11:04:03.916106 7, 0xFFFF, sum = 0
4290 11:04:03.916204 8, 0x0, sum = 1
4291 11:04:03.920062 9, 0x0, sum = 2
4292 11:04:03.920161 10, 0x0, sum = 3
4293 11:04:03.922967 11, 0x0, sum = 4
4294 11:04:03.923066 best_step = 9
4295 11:04:03.923150
4296 11:04:03.923231 ==
4297 11:04:03.926046 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 11:04:03.930023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 11:04:03.933567 ==
4300 11:04:03.933666 RX Vref Scan: 0
4301 11:04:03.933750
4302 11:04:03.936216 RX Vref 0 -> 0, step: 1
4303 11:04:03.936312
4304 11:04:03.939808 RX Delay -195 -> 252, step: 8
4305 11:04:03.942814 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4306 11:04:03.946115 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4307 11:04:03.952865 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4308 11:04:03.956740 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4309 11:04:03.960149 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4310 11:04:03.962798 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4311 11:04:03.966903 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4312 11:04:03.972855 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4313 11:04:03.976337 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4314 11:04:03.979668 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4315 11:04:03.983588 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4316 11:04:03.989823 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4317 11:04:03.993349 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4318 11:04:03.996261 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4319 11:04:03.999600 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4320 11:04:04.006233 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4321 11:04:04.006320 ==
4322 11:04:04.009496 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 11:04:04.012970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 11:04:04.013065 ==
4325 11:04:04.013168 DQS Delay:
4326 11:04:04.016453 DQS0 = 0, DQS1 = 0
4327 11:04:04.016529 DQM Delay:
4328 11:04:04.019605 DQM0 = 39, DQM1 = 32
4329 11:04:04.019705 DQ Delay:
4330 11:04:04.023578 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4331 11:04:04.026610 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4332 11:04:04.029693 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =20
4333 11:04:04.033128 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4334 11:04:04.033239
4335 11:04:04.033323
4336 11:04:04.039731 [DQSOSCAuto] RK1, (LSB)MR18= 0x5234, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4337 11:04:04.043191 CH0 RK1: MR19=808, MR18=5234
4338 11:04:04.049660 CH0_RK1: MR19=0x808, MR18=0x5234, DQSOSC=394, MR23=63, INC=168, DEC=112
4339 11:04:04.053249 [RxdqsGatingPostProcess] freq 600
4340 11:04:04.059865 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4341 11:04:04.062699 Pre-setting of DQS Precalculation
4342 11:04:04.066344 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4343 11:04:04.066446 ==
4344 11:04:04.070023 Dram Type= 6, Freq= 0, CH_1, rank 0
4345 11:04:04.072985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 11:04:04.073086 ==
4347 11:04:04.079627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4348 11:04:04.086837 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4349 11:04:04.090035 [CA 0] Center 35 (5~66) winsize 62
4350 11:04:04.092919 [CA 1] Center 35 (5~66) winsize 62
4351 11:04:04.096562 [CA 2] Center 34 (3~65) winsize 63
4352 11:04:04.099592 [CA 3] Center 33 (3~64) winsize 62
4353 11:04:04.103816 [CA 4] Center 34 (3~65) winsize 63
4354 11:04:04.106342 [CA 5] Center 33 (3~64) winsize 62
4355 11:04:04.106419
4356 11:04:04.109901 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4357 11:04:04.109978
4358 11:04:04.112998 [CATrainingPosCal] consider 1 rank data
4359 11:04:04.116284 u2DelayCellTimex100 = 270/100 ps
4360 11:04:04.119677 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4361 11:04:04.123220 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4362 11:04:04.126363 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4363 11:04:04.129946 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4364 11:04:04.133413 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4365 11:04:04.136124 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4366 11:04:04.136223
4367 11:04:04.143271 CA PerBit enable=1, Macro0, CA PI delay=33
4368 11:04:04.143390
4369 11:04:04.143477 [CBTSetCACLKResult] CA Dly = 33
4370 11:04:04.146312 CS Dly: 5 (0~36)
4371 11:04:04.146411 ==
4372 11:04:04.149922 Dram Type= 6, Freq= 0, CH_1, rank 1
4373 11:04:04.152799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 11:04:04.152898 ==
4375 11:04:04.159841 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4376 11:04:04.166871 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4377 11:04:04.169841 [CA 0] Center 35 (5~66) winsize 62
4378 11:04:04.173208 [CA 1] Center 35 (5~66) winsize 62
4379 11:04:04.176450 [CA 2] Center 34 (3~65) winsize 63
4380 11:04:04.180287 [CA 3] Center 34 (3~65) winsize 63
4381 11:04:04.183292 [CA 4] Center 34 (3~65) winsize 63
4382 11:04:04.186461 [CA 5] Center 33 (3~64) winsize 62
4383 11:04:04.186563
4384 11:04:04.190381 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4385 11:04:04.190479
4386 11:04:04.192980 [CATrainingPosCal] consider 2 rank data
4387 11:04:04.196513 u2DelayCellTimex100 = 270/100 ps
4388 11:04:04.199776 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4389 11:04:04.203729 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4390 11:04:04.207054 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4391 11:04:04.209791 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4392 11:04:04.213166 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4393 11:04:04.216284 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4394 11:04:04.216364
4395 11:04:04.223157 CA PerBit enable=1, Macro0, CA PI delay=33
4396 11:04:04.223241
4397 11:04:04.223302 [CBTSetCACLKResult] CA Dly = 33
4398 11:04:04.226725 CS Dly: 5 (0~36)
4399 11:04:04.226831
4400 11:04:04.229681 ----->DramcWriteLeveling(PI) begin...
4401 11:04:04.229760 ==
4402 11:04:04.233096 Dram Type= 6, Freq= 0, CH_1, rank 0
4403 11:04:04.237077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 11:04:04.237206 ==
4405 11:04:04.239833 Write leveling (Byte 0): 31 => 31
4406 11:04:04.243263 Write leveling (Byte 1): 32 => 32
4407 11:04:04.246875 DramcWriteLeveling(PI) end<-----
4408 11:04:04.246953
4409 11:04:04.247013 ==
4410 11:04:04.249742 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 11:04:04.253655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 11:04:04.253735 ==
4413 11:04:04.256996 [Gating] SW mode calibration
4414 11:04:04.263484 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4415 11:04:04.270057 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4416 11:04:04.273558 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4417 11:04:04.280552 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4418 11:04:04.283566 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 11:04:04.287133 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4420 11:04:04.290590 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4421 11:04:04.296836 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 11:04:04.299874 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4423 11:04:04.303360 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 11:04:04.310250 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 11:04:04.313313 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 11:04:04.316917 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 11:04:04.323622 0 10 12 | B1->B0 | 2929 2d2d | 0 0 | (0 0) (0 0)
4428 11:04:04.327187 0 10 16 | B1->B0 | 3838 4343 | 0 1 | (0 0) (0 0)
4429 11:04:04.330315 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 11:04:04.336789 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 11:04:04.340725 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 11:04:04.343395 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 11:04:04.351367 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 11:04:04.353368 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 11:04:04.356836 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4436 11:04:04.363951 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 11:04:04.366742 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 11:04:04.370056 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 11:04:04.373921 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 11:04:04.380146 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 11:04:04.383472 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 11:04:04.388074 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 11:04:04.393577 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 11:04:04.396917 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 11:04:04.400409 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 11:04:04.407864 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 11:04:04.410474 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 11:04:04.413822 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 11:04:04.420806 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 11:04:04.423708 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 11:04:04.427841 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4452 11:04:04.433709 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 11:04:04.433845 Total UI for P1: 0, mck2ui 16
4454 11:04:04.440320 best dqsien dly found for B0: ( 0, 13, 12)
4455 11:04:04.440429 Total UI for P1: 0, mck2ui 16
4456 11:04:04.443610 best dqsien dly found for B1: ( 0, 13, 14)
4457 11:04:04.450842 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4458 11:04:04.453617 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4459 11:04:04.453696
4460 11:04:04.456895 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4461 11:04:04.461534 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4462 11:04:04.463986 [Gating] SW calibration Done
4463 11:04:04.464063 ==
4464 11:04:04.466872 Dram Type= 6, Freq= 0, CH_1, rank 0
4465 11:04:04.470171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4466 11:04:04.470271 ==
4467 11:04:04.474028 RX Vref Scan: 0
4468 11:04:04.474129
4469 11:04:04.474212 RX Vref 0 -> 0, step: 1
4470 11:04:04.474295
4471 11:04:04.477222 RX Delay -230 -> 252, step: 16
4472 11:04:04.480511 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4473 11:04:04.487026 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4474 11:04:04.490458 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4475 11:04:04.494332 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4476 11:04:04.497052 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4477 11:04:04.501241 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4478 11:04:04.507180 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4479 11:04:04.510553 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4480 11:04:04.513563 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4481 11:04:04.517343 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4482 11:04:04.523645 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4483 11:04:04.527328 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4484 11:04:04.530837 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4485 11:04:04.533622 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4486 11:04:04.540536 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4487 11:04:04.543604 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4488 11:04:04.543683 ==
4489 11:04:04.547105 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 11:04:04.550273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 11:04:04.550351 ==
4492 11:04:04.550410 DQS Delay:
4493 11:04:04.554072 DQS0 = 0, DQS1 = 0
4494 11:04:04.554149 DQM Delay:
4495 11:04:04.557827 DQM0 = 43, DQM1 = 35
4496 11:04:04.557903 DQ Delay:
4497 11:04:04.560518 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4498 11:04:04.564072 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4499 11:04:04.567310 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4500 11:04:04.570758 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4501 11:04:04.570838
4502 11:04:04.570899
4503 11:04:04.570953 ==
4504 11:04:04.574324 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 11:04:04.577123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 11:04:04.577218 ==
4507 11:04:04.580569
4508 11:04:04.580644
4509 11:04:04.580704 TX Vref Scan disable
4510 11:04:04.583990 == TX Byte 0 ==
4511 11:04:04.587464 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4512 11:04:04.590678 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4513 11:04:04.594539 == TX Byte 1 ==
4514 11:04:04.598190 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4515 11:04:04.601625 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4516 11:04:04.601719 ==
4517 11:04:04.603918 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 11:04:04.610744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 11:04:04.610824 ==
4520 11:04:04.610883
4521 11:04:04.610937
4522 11:04:04.610989 TX Vref Scan disable
4523 11:04:04.615929 == TX Byte 0 ==
4524 11:04:04.618628 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4525 11:04:04.622015 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4526 11:04:04.625247 == TX Byte 1 ==
4527 11:04:04.628961 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4528 11:04:04.632120 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4529 11:04:04.632197
4530 11:04:04.635296 [DATLAT]
4531 11:04:04.635372 Freq=600, CH1 RK0
4532 11:04:04.635432
4533 11:04:04.639028 DATLAT Default: 0x9
4534 11:04:04.639103 0, 0xFFFF, sum = 0
4535 11:04:04.642078 1, 0xFFFF, sum = 0
4536 11:04:04.642156 2, 0xFFFF, sum = 0
4537 11:04:04.645454 3, 0xFFFF, sum = 0
4538 11:04:04.645532 4, 0xFFFF, sum = 0
4539 11:04:04.649362 5, 0xFFFF, sum = 0
4540 11:04:04.649440 6, 0xFFFF, sum = 0
4541 11:04:04.652112 7, 0xFFFF, sum = 0
4542 11:04:04.652189 8, 0x0, sum = 1
4543 11:04:04.655485 9, 0x0, sum = 2
4544 11:04:04.655571 10, 0x0, sum = 3
4545 11:04:04.658725 11, 0x0, sum = 4
4546 11:04:04.658803 best_step = 9
4547 11:04:04.658863
4548 11:04:04.658918 ==
4549 11:04:04.662322 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 11:04:04.668436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 11:04:04.668517 ==
4552 11:04:04.668578 RX Vref Scan: 1
4553 11:04:04.668633
4554 11:04:04.671821 RX Vref 0 -> 0, step: 1
4555 11:04:04.671898
4556 11:04:04.675369 RX Delay -195 -> 252, step: 8
4557 11:04:04.675445
4558 11:04:04.678849 Set Vref, RX VrefLevel [Byte0]: 55
4559 11:04:04.681952 [Byte1]: 47
4560 11:04:04.682030
4561 11:04:04.685499 Final RX Vref Byte 0 = 55 to rank0
4562 11:04:04.688300 Final RX Vref Byte 1 = 47 to rank0
4563 11:04:04.692109 Final RX Vref Byte 0 = 55 to rank1
4564 11:04:04.695372 Final RX Vref Byte 1 = 47 to rank1==
4565 11:04:04.698308 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 11:04:04.702205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 11:04:04.702306 ==
4568 11:04:04.705110 DQS Delay:
4569 11:04:04.705230 DQS0 = 0, DQS1 = 0
4570 11:04:04.705315 DQM Delay:
4571 11:04:04.708572 DQM0 = 40, DQM1 = 31
4572 11:04:04.708672 DQ Delay:
4573 11:04:04.711667 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4574 11:04:04.715206 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4575 11:04:04.718771 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =24
4576 11:04:04.721697 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =36
4577 11:04:04.721798
4578 11:04:04.721882
4579 11:04:04.731830 [DQSOSCAuto] RK0, (LSB)MR18= 0x480c, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4580 11:04:04.731939 CH1 RK0: MR19=808, MR18=480C
4581 11:04:04.738747 CH1_RK0: MR19=0x808, MR18=0x480C, DQSOSC=396, MR23=63, INC=167, DEC=111
4582 11:04:04.738853
4583 11:04:04.741867 ----->DramcWriteLeveling(PI) begin...
4584 11:04:04.741967 ==
4585 11:04:04.745307 Dram Type= 6, Freq= 0, CH_1, rank 1
4586 11:04:04.752207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 11:04:04.752325 ==
4588 11:04:04.755343 Write leveling (Byte 0): 28 => 28
4589 11:04:04.758424 Write leveling (Byte 1): 29 => 29
4590 11:04:04.758523 DramcWriteLeveling(PI) end<-----
4591 11:04:04.761624
4592 11:04:04.761720 ==
4593 11:04:04.766380 Dram Type= 6, Freq= 0, CH_1, rank 1
4594 11:04:04.768865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 11:04:04.768964 ==
4596 11:04:04.772116 [Gating] SW mode calibration
4597 11:04:04.778961 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4598 11:04:04.782012 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4599 11:04:04.788442 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4600 11:04:04.792056 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 11:04:04.795270 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4602 11:04:04.802029 0 9 12 | B1->B0 | 2f2f 2b2b | 0 0 | (0 0) (0 0)
4603 11:04:04.805283 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4604 11:04:04.808588 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 11:04:04.815092 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 11:04:04.818477 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 11:04:04.822728 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 11:04:04.825803 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 11:04:04.831828 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4610 11:04:04.835578 0 10 12 | B1->B0 | 2e2e 4141 | 0 0 | (0 0) (0 0)
4611 11:04:04.838482 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4612 11:04:04.845140 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 11:04:04.848898 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 11:04:04.851947 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 11:04:04.858826 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 11:04:04.862003 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 11:04:04.865582 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 11:04:04.872234 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4619 11:04:04.875666 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 11:04:04.879012 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 11:04:04.885734 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 11:04:04.889256 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 11:04:04.891997 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 11:04:04.898922 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 11:04:04.902060 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 11:04:04.905456 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 11:04:04.908758 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 11:04:04.915330 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 11:04:04.918883 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 11:04:04.922203 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 11:04:04.929038 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 11:04:04.932642 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 11:04:04.935948 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 11:04:04.942104 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4635 11:04:04.945596 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 11:04:04.949027 Total UI for P1: 0, mck2ui 16
4637 11:04:04.952170 best dqsien dly found for B0: ( 0, 13, 12)
4638 11:04:04.955758 Total UI for P1: 0, mck2ui 16
4639 11:04:04.958815 best dqsien dly found for B1: ( 0, 13, 14)
4640 11:04:04.962654 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4641 11:04:04.965822 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4642 11:04:04.965923
4643 11:04:04.969282 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4644 11:04:04.972494 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4645 11:04:04.975724 [Gating] SW calibration Done
4646 11:04:04.975824 ==
4647 11:04:04.979072 Dram Type= 6, Freq= 0, CH_1, rank 1
4648 11:04:04.982201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4649 11:04:04.986298 ==
4650 11:04:04.986397 RX Vref Scan: 0
4651 11:04:04.986484
4652 11:04:04.988815 RX Vref 0 -> 0, step: 1
4653 11:04:04.988913
4654 11:04:04.992097 RX Delay -230 -> 252, step: 16
4655 11:04:04.996015 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4656 11:04:04.998898 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4657 11:04:05.002560 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4658 11:04:05.005399 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4659 11:04:05.012428 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4660 11:04:05.015766 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4661 11:04:05.018809 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4662 11:04:05.022622 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4663 11:04:05.029444 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4664 11:04:05.032573 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4665 11:04:05.035956 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4666 11:04:05.039327 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4667 11:04:05.042452 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4668 11:04:05.049645 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4669 11:04:05.052606 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4670 11:04:05.056303 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4671 11:04:05.056405 ==
4672 11:04:05.059644 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 11:04:05.062797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 11:04:05.066012 ==
4675 11:04:05.066109 DQS Delay:
4676 11:04:05.066194 DQS0 = 0, DQS1 = 0
4677 11:04:05.069327 DQM Delay:
4678 11:04:05.069424 DQM0 = 41, DQM1 = 35
4679 11:04:05.069508 DQ Delay:
4680 11:04:05.072974 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4681 11:04:05.076543 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =33
4682 11:04:05.079482 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4683 11:04:05.083305 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4684 11:04:05.083381
4685 11:04:05.083439
4686 11:04:05.086331 ==
4687 11:04:05.089349 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 11:04:05.092523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 11:04:05.092622 ==
4690 11:04:05.092695
4691 11:04:05.092749
4692 11:04:05.095811 TX Vref Scan disable
4693 11:04:05.095885 == TX Byte 0 ==
4694 11:04:05.102553 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4695 11:04:05.106023 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4696 11:04:05.106121 == TX Byte 1 ==
4697 11:04:05.112654 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4698 11:04:05.115787 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4699 11:04:05.115886 ==
4700 11:04:05.119358 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 11:04:05.122659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 11:04:05.122762 ==
4703 11:04:05.122846
4704 11:04:05.122927
4705 11:04:05.126287 TX Vref Scan disable
4706 11:04:05.128975 == TX Byte 0 ==
4707 11:04:05.132433 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4708 11:04:05.136486 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4709 11:04:05.139168 == TX Byte 1 ==
4710 11:04:05.142455 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4711 11:04:05.145837 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4712 11:04:05.145937
4713 11:04:05.149165 [DATLAT]
4714 11:04:05.149261 Freq=600, CH1 RK1
4715 11:04:05.149346
4716 11:04:05.152510 DATLAT Default: 0x9
4717 11:04:05.152620 0, 0xFFFF, sum = 0
4718 11:04:05.155725 1, 0xFFFF, sum = 0
4719 11:04:05.155824 2, 0xFFFF, sum = 0
4720 11:04:05.159043 3, 0xFFFF, sum = 0
4721 11:04:05.159142 4, 0xFFFF, sum = 0
4722 11:04:05.163306 5, 0xFFFF, sum = 0
4723 11:04:05.163405 6, 0xFFFF, sum = 0
4724 11:04:05.165969 7, 0xFFFF, sum = 0
4725 11:04:05.166067 8, 0x0, sum = 1
4726 11:04:05.169490 9, 0x0, sum = 2
4727 11:04:05.169592 10, 0x0, sum = 3
4728 11:04:05.172370 11, 0x0, sum = 4
4729 11:04:05.172467 best_step = 9
4730 11:04:05.172551
4731 11:04:05.172633 ==
4732 11:04:05.175949 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 11:04:05.179373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 11:04:05.179473 ==
4735 11:04:05.182732 RX Vref Scan: 0
4736 11:04:05.182831
4737 11:04:05.186092 RX Vref 0 -> 0, step: 1
4738 11:04:05.186188
4739 11:04:05.186273 RX Delay -179 -> 252, step: 8
4740 11:04:05.193886 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4741 11:04:05.197099 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4742 11:04:05.200905 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4743 11:04:05.204220 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4744 11:04:05.210692 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4745 11:04:05.213871 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4746 11:04:05.217146 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4747 11:04:05.221021 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4748 11:04:05.224167 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4749 11:04:05.230923 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4750 11:04:05.235078 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4751 11:04:05.237390 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4752 11:04:05.241374 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4753 11:04:05.247287 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4754 11:04:05.250725 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4755 11:04:05.254476 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4756 11:04:05.254552 ==
4757 11:04:05.257880 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 11:04:05.261483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 11:04:05.261560 ==
4760 11:04:05.263991 DQS Delay:
4761 11:04:05.264066 DQS0 = 0, DQS1 = 0
4762 11:04:05.267288 DQM Delay:
4763 11:04:05.267363 DQM0 = 39, DQM1 = 33
4764 11:04:05.267421 DQ Delay:
4765 11:04:05.270556 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4766 11:04:05.274109 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =36
4767 11:04:05.277548 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =24
4768 11:04:05.280925 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4769 11:04:05.281000
4770 11:04:05.281058
4771 11:04:05.291161 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a48, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
4772 11:04:05.294320 CH1 RK1: MR19=808, MR18=3A48
4773 11:04:05.297977 CH1_RK1: MR19=0x808, MR18=0x3A48, DQSOSC=396, MR23=63, INC=167, DEC=111
4774 11:04:05.300785 [RxdqsGatingPostProcess] freq 600
4775 11:04:05.307660 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4776 11:04:05.311080 Pre-setting of DQS Precalculation
4777 11:04:05.314302 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4778 11:04:05.321073 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4779 11:04:05.331363 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4780 11:04:05.331456
4781 11:04:05.331515
4782 11:04:05.334133 [Calibration Summary] 1200 Mbps
4783 11:04:05.334209 CH 0, Rank 0
4784 11:04:05.338151 SW Impedance : PASS
4785 11:04:05.338226 DUTY Scan : NO K
4786 11:04:05.341212 ZQ Calibration : PASS
4787 11:04:05.344748 Jitter Meter : NO K
4788 11:04:05.344825 CBT Training : PASS
4789 11:04:05.347746 Write leveling : PASS
4790 11:04:05.347822 RX DQS gating : PASS
4791 11:04:05.352010 RX DQ/DQS(RDDQC) : PASS
4792 11:04:05.354775 TX DQ/DQS : PASS
4793 11:04:05.354925 RX DATLAT : PASS
4794 11:04:05.357485 RX DQ/DQS(Engine): PASS
4795 11:04:05.361622 TX OE : NO K
4796 11:04:05.361727 All Pass.
4797 11:04:05.361813
4798 11:04:05.361895 CH 0, Rank 1
4799 11:04:05.364277 SW Impedance : PASS
4800 11:04:05.368208 DUTY Scan : NO K
4801 11:04:05.368309 ZQ Calibration : PASS
4802 11:04:05.371159 Jitter Meter : NO K
4803 11:04:05.374146 CBT Training : PASS
4804 11:04:05.374246 Write leveling : PASS
4805 11:04:05.377450 RX DQS gating : PASS
4806 11:04:05.380852 RX DQ/DQS(RDDQC) : PASS
4807 11:04:05.380966 TX DQ/DQS : PASS
4808 11:04:05.384699 RX DATLAT : PASS
4809 11:04:05.384799 RX DQ/DQS(Engine): PASS
4810 11:04:05.387744 TX OE : NO K
4811 11:04:05.387844 All Pass.
4812 11:04:05.387928
4813 11:04:05.391433 CH 1, Rank 0
4814 11:04:05.391535 SW Impedance : PASS
4815 11:04:05.394429 DUTY Scan : NO K
4816 11:04:05.397578 ZQ Calibration : PASS
4817 11:04:05.397682 Jitter Meter : NO K
4818 11:04:05.401211 CBT Training : PASS
4819 11:04:05.404276 Write leveling : PASS
4820 11:04:05.404382 RX DQS gating : PASS
4821 11:04:05.407829 RX DQ/DQS(RDDQC) : PASS
4822 11:04:05.411301 TX DQ/DQS : PASS
4823 11:04:05.411407 RX DATLAT : PASS
4824 11:04:05.414433 RX DQ/DQS(Engine): PASS
4825 11:04:05.418045 TX OE : NO K
4826 11:04:05.418150 All Pass.
4827 11:04:05.418236
4828 11:04:05.418349 CH 1, Rank 1
4829 11:04:05.421104 SW Impedance : PASS
4830 11:04:05.424195 DUTY Scan : NO K
4831 11:04:05.424294 ZQ Calibration : PASS
4832 11:04:05.428039 Jitter Meter : NO K
4833 11:04:05.428139 CBT Training : PASS
4834 11:04:05.431105 Write leveling : PASS
4835 11:04:05.434836 RX DQS gating : PASS
4836 11:04:05.434938 RX DQ/DQS(RDDQC) : PASS
4837 11:04:05.437732 TX DQ/DQS : PASS
4838 11:04:05.441280 RX DATLAT : PASS
4839 11:04:05.441383 RX DQ/DQS(Engine): PASS
4840 11:04:05.444352 TX OE : NO K
4841 11:04:05.444433 All Pass.
4842 11:04:05.444496
4843 11:04:05.447606 DramC Write-DBI off
4844 11:04:05.451120 PER_BANK_REFRESH: Hybrid Mode
4845 11:04:05.451199 TX_TRACKING: ON
4846 11:04:05.461224 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4847 11:04:05.464863 [FAST_K] Save calibration result to emmc
4848 11:04:05.468351 dramc_set_vcore_voltage set vcore to 662500
4849 11:04:05.471016 Read voltage for 933, 3
4850 11:04:05.471113 Vio18 = 0
4851 11:04:05.471200 Vcore = 662500
4852 11:04:05.474260 Vdram = 0
4853 11:04:05.474355 Vddq = 0
4854 11:04:05.474440 Vmddr = 0
4855 11:04:05.481725 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4856 11:04:05.484402 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4857 11:04:05.487498 MEM_TYPE=3, freq_sel=17
4858 11:04:05.491075 sv_algorithm_assistance_LP4_1600
4859 11:04:05.494637 ============ PULL DRAM RESETB DOWN ============
4860 11:04:05.498280 ========== PULL DRAM RESETB DOWN end =========
4861 11:04:05.504675 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4862 11:04:05.507870 ===================================
4863 11:04:05.507980 LPDDR4 DRAM CONFIGURATION
4864 11:04:05.510988 ===================================
4865 11:04:05.514819 EX_ROW_EN[0] = 0x0
4866 11:04:05.517780 EX_ROW_EN[1] = 0x0
4867 11:04:05.517879 LP4Y_EN = 0x0
4868 11:04:05.521751 WORK_FSP = 0x0
4869 11:04:05.521847 WL = 0x3
4870 11:04:05.524434 RL = 0x3
4871 11:04:05.524531 BL = 0x2
4872 11:04:05.528119 RPST = 0x0
4873 11:04:05.528217 RD_PRE = 0x0
4874 11:04:05.531269 WR_PRE = 0x1
4875 11:04:05.531368 WR_PST = 0x0
4876 11:04:05.534978 DBI_WR = 0x0
4877 11:04:05.535081 DBI_RD = 0x0
4878 11:04:05.538066 OTF = 0x1
4879 11:04:05.541222 ===================================
4880 11:04:05.544994 ===================================
4881 11:04:05.545095 ANA top config
4882 11:04:05.547701 ===================================
4883 11:04:05.551038 DLL_ASYNC_EN = 0
4884 11:04:05.554719 ALL_SLAVE_EN = 1
4885 11:04:05.554819 NEW_RANK_MODE = 1
4886 11:04:05.558251 DLL_IDLE_MODE = 1
4887 11:04:05.561786 LP45_APHY_COMB_EN = 1
4888 11:04:05.564740 TX_ODT_DIS = 1
4889 11:04:05.568320 NEW_8X_MODE = 1
4890 11:04:05.571367 ===================================
4891 11:04:05.574703 ===================================
4892 11:04:05.574803 data_rate = 1866
4893 11:04:05.577977 CKR = 1
4894 11:04:05.581407 DQ_P2S_RATIO = 8
4895 11:04:05.585626 ===================================
4896 11:04:05.587920 CA_P2S_RATIO = 8
4897 11:04:05.591098 DQ_CA_OPEN = 0
4898 11:04:05.594753 DQ_SEMI_OPEN = 0
4899 11:04:05.594855 CA_SEMI_OPEN = 0
4900 11:04:05.598280 CA_FULL_RATE = 0
4901 11:04:05.601471 DQ_CKDIV4_EN = 1
4902 11:04:05.604863 CA_CKDIV4_EN = 1
4903 11:04:05.607984 CA_PREDIV_EN = 0
4904 11:04:05.608083 PH8_DLY = 0
4905 11:04:05.611067 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4906 11:04:05.614784 DQ_AAMCK_DIV = 4
4907 11:04:05.617911 CA_AAMCK_DIV = 4
4908 11:04:05.621422 CA_ADMCK_DIV = 4
4909 11:04:05.624571 DQ_TRACK_CA_EN = 0
4910 11:04:05.628019 CA_PICK = 933
4911 11:04:05.628162 CA_MCKIO = 933
4912 11:04:05.631248 MCKIO_SEMI = 0
4913 11:04:05.634431 PLL_FREQ = 3732
4914 11:04:05.638202 DQ_UI_PI_RATIO = 32
4915 11:04:05.641281 CA_UI_PI_RATIO = 0
4916 11:04:05.644490 ===================================
4917 11:04:05.648295 ===================================
4918 11:04:05.651094 memory_type:LPDDR4
4919 11:04:05.651239 GP_NUM : 10
4920 11:04:05.655510 SRAM_EN : 1
4921 11:04:05.655610 MD32_EN : 0
4922 11:04:05.657900 ===================================
4923 11:04:05.661339 [ANA_INIT] >>>>>>>>>>>>>>
4924 11:04:05.664910 <<<<<< [CONFIGURE PHASE]: ANA_TX
4925 11:04:05.668520 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4926 11:04:05.671301 ===================================
4927 11:04:05.675397 data_rate = 1866,PCW = 0X8f00
4928 11:04:05.678224 ===================================
4929 11:04:05.681419 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4930 11:04:05.685019 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4931 11:04:05.691668 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4932 11:04:05.694858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4933 11:04:05.698339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4934 11:04:05.701781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4935 11:04:05.704718 [ANA_INIT] flow start
4936 11:04:05.708188 [ANA_INIT] PLL >>>>>>>>
4937 11:04:05.708286 [ANA_INIT] PLL <<<<<<<<
4938 11:04:05.711680 [ANA_INIT] MIDPI >>>>>>>>
4939 11:04:05.714866 [ANA_INIT] MIDPI <<<<<<<<
4940 11:04:05.718371 [ANA_INIT] DLL >>>>>>>>
4941 11:04:05.718470 [ANA_INIT] flow end
4942 11:04:05.721897 ============ LP4 DIFF to SE enter ============
4943 11:04:05.728471 ============ LP4 DIFF to SE exit ============
4944 11:04:05.728573 [ANA_INIT] <<<<<<<<<<<<<
4945 11:04:05.731218 [Flow] Enable top DCM control >>>>>
4946 11:04:05.734824 [Flow] Enable top DCM control <<<<<
4947 11:04:05.738308 Enable DLL master slave shuffle
4948 11:04:05.744997 ==============================================================
4949 11:04:05.745124 Gating Mode config
4950 11:04:05.751283 ==============================================================
4951 11:04:05.754631 Config description:
4952 11:04:05.761986 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4953 11:04:05.768205 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4954 11:04:05.774950 SELPH_MODE 0: By rank 1: By Phase
4955 11:04:05.778386 ==============================================================
4956 11:04:05.781751 GAT_TRACK_EN = 1
4957 11:04:05.785018 RX_GATING_MODE = 2
4958 11:04:05.788445 RX_GATING_TRACK_MODE = 2
4959 11:04:05.791335 SELPH_MODE = 1
4960 11:04:05.794824 PICG_EARLY_EN = 1
4961 11:04:05.798175 VALID_LAT_VALUE = 1
4962 11:04:05.805425 ==============================================================
4963 11:04:05.808004 Enter into Gating configuration >>>>
4964 11:04:05.811880 Exit from Gating configuration <<<<
4965 11:04:05.814589 Enter into DVFS_PRE_config >>>>>
4966 11:04:05.824659 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4967 11:04:05.828013 Exit from DVFS_PRE_config <<<<<
4968 11:04:05.831710 Enter into PICG configuration >>>>
4969 11:04:05.835042 Exit from PICG configuration <<<<
4970 11:04:05.835141 [RX_INPUT] configuration >>>>>
4971 11:04:05.838500 [RX_INPUT] configuration <<<<<
4972 11:04:05.844599 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4973 11:04:05.851435 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4974 11:04:05.854607 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4975 11:04:05.861679 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4976 11:04:05.868363 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4977 11:04:05.875431 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4978 11:04:05.878178 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4979 11:04:05.881570 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4980 11:04:05.888236 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4981 11:04:05.892134 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4982 11:04:05.894934 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4983 11:04:05.898198 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4984 11:04:05.901320 ===================================
4985 11:04:05.904770 LPDDR4 DRAM CONFIGURATION
4986 11:04:05.908238 ===================================
4987 11:04:05.911300 EX_ROW_EN[0] = 0x0
4988 11:04:05.911399 EX_ROW_EN[1] = 0x0
4989 11:04:05.914668 LP4Y_EN = 0x0
4990 11:04:05.914766 WORK_FSP = 0x0
4991 11:04:05.918111 WL = 0x3
4992 11:04:05.918208 RL = 0x3
4993 11:04:05.921361 BL = 0x2
4994 11:04:05.921457 RPST = 0x0
4995 11:04:05.924649 RD_PRE = 0x0
4996 11:04:05.924746 WR_PRE = 0x1
4997 11:04:05.928099 WR_PST = 0x0
4998 11:04:05.928195 DBI_WR = 0x0
4999 11:04:05.931856 DBI_RD = 0x0
5000 11:04:05.931951 OTF = 0x1
5001 11:04:05.934542 ===================================
5002 11:04:05.942508 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5003 11:04:05.945208 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5004 11:04:05.948493 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5005 11:04:05.951254 ===================================
5006 11:04:05.954917 LPDDR4 DRAM CONFIGURATION
5007 11:04:05.958521 ===================================
5008 11:04:05.961745 EX_ROW_EN[0] = 0x10
5009 11:04:05.961907 EX_ROW_EN[1] = 0x0
5010 11:04:05.965254 LP4Y_EN = 0x0
5011 11:04:05.965418 WORK_FSP = 0x0
5012 11:04:05.968950 WL = 0x3
5013 11:04:05.969070 RL = 0x3
5014 11:04:05.971994 BL = 0x2
5015 11:04:05.972095 RPST = 0x0
5016 11:04:05.974588 RD_PRE = 0x0
5017 11:04:05.974675 WR_PRE = 0x1
5018 11:04:05.978569 WR_PST = 0x0
5019 11:04:05.978683 DBI_WR = 0x0
5020 11:04:05.981243 DBI_RD = 0x0
5021 11:04:05.981324 OTF = 0x1
5022 11:04:05.984719 ===================================
5023 11:04:05.991924 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5024 11:04:05.995667 nWR fixed to 30
5025 11:04:05.999318 [ModeRegInit_LP4] CH0 RK0
5026 11:04:05.999434 [ModeRegInit_LP4] CH0 RK1
5027 11:04:06.002708 [ModeRegInit_LP4] CH1 RK0
5028 11:04:06.005958 [ModeRegInit_LP4] CH1 RK1
5029 11:04:06.006082 match AC timing 9
5030 11:04:06.012687 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5031 11:04:06.015991 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5032 11:04:06.019954 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5033 11:04:06.026212 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5034 11:04:06.029592 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5035 11:04:06.029669 ==
5036 11:04:06.033308 Dram Type= 6, Freq= 0, CH_0, rank 0
5037 11:04:06.036158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5038 11:04:06.036233 ==
5039 11:04:06.042582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5040 11:04:06.049785 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5041 11:04:06.053034 [CA 0] Center 38 (8~69) winsize 62
5042 11:04:06.056007 [CA 1] Center 37 (7~68) winsize 62
5043 11:04:06.059844 [CA 2] Center 35 (5~66) winsize 62
5044 11:04:06.062691 [CA 3] Center 35 (5~66) winsize 62
5045 11:04:06.065870 [CA 4] Center 34 (4~64) winsize 61
5046 11:04:06.069842 [CA 5] Center 34 (4~64) winsize 61
5047 11:04:06.069953
5048 11:04:06.072752 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5049 11:04:06.072828
5050 11:04:06.075937 [CATrainingPosCal] consider 1 rank data
5051 11:04:06.079867 u2DelayCellTimex100 = 270/100 ps
5052 11:04:06.082953 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5053 11:04:06.086381 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5054 11:04:06.089270 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5055 11:04:06.094031 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5056 11:04:06.096233 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5057 11:04:06.099314 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5058 11:04:06.099390
5059 11:04:06.103375 CA PerBit enable=1, Macro0, CA PI delay=34
5060 11:04:06.103451
5061 11:04:06.106085 [CBTSetCACLKResult] CA Dly = 34
5062 11:04:06.109471 CS Dly: 6 (0~37)
5063 11:04:06.109548 ==
5064 11:04:06.112707 Dram Type= 6, Freq= 0, CH_0, rank 1
5065 11:04:06.115842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5066 11:04:06.115919 ==
5067 11:04:06.122566 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5068 11:04:06.129561 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5069 11:04:06.132909 [CA 0] Center 38 (8~69) winsize 62
5070 11:04:06.135906 [CA 1] Center 38 (7~69) winsize 63
5071 11:04:06.139516 [CA 2] Center 35 (5~66) winsize 62
5072 11:04:06.143892 [CA 3] Center 35 (4~66) winsize 63
5073 11:04:06.145994 [CA 4] Center 33 (3~64) winsize 62
5074 11:04:06.149733 [CA 5] Center 33 (3~64) winsize 62
5075 11:04:06.149809
5076 11:04:06.152471 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5077 11:04:06.152547
5078 11:04:06.155936 [CATrainingPosCal] consider 2 rank data
5079 11:04:06.159587 u2DelayCellTimex100 = 270/100 ps
5080 11:04:06.162994 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5081 11:04:06.166109 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5082 11:04:06.170209 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5083 11:04:06.172972 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5084 11:04:06.176137 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5085 11:04:06.179536 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5086 11:04:06.179613
5087 11:04:06.182765 CA PerBit enable=1, Macro0, CA PI delay=34
5088 11:04:06.182843
5089 11:04:06.186248 [CBTSetCACLKResult] CA Dly = 34
5090 11:04:06.189610 CS Dly: 7 (0~39)
5091 11:04:06.189689
5092 11:04:06.192923 ----->DramcWriteLeveling(PI) begin...
5093 11:04:06.193000 ==
5094 11:04:06.196735 Dram Type= 6, Freq= 0, CH_0, rank 0
5095 11:04:06.200625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5096 11:04:06.200701 ==
5097 11:04:06.203216 Write leveling (Byte 0): 32 => 32
5098 11:04:06.206458 Write leveling (Byte 1): 28 => 28
5099 11:04:06.209575 DramcWriteLeveling(PI) end<-----
5100 11:04:06.209650
5101 11:04:06.209709 ==
5102 11:04:06.213062 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 11:04:06.216292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 11:04:06.216368 ==
5105 11:04:06.219541 [Gating] SW mode calibration
5106 11:04:06.226825 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5107 11:04:06.232995 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5108 11:04:06.236182 0 14 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5109 11:04:06.239569 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5110 11:04:06.246411 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 11:04:06.250318 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 11:04:06.253087 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 11:04:06.260025 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 11:04:06.262992 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 11:04:06.266432 0 14 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5116 11:04:06.273203 0 15 0 | B1->B0 | 2f2f 2929 | 1 1 | (1 1) (1 0)
5117 11:04:06.276296 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 11:04:06.279946 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 11:04:06.287279 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 11:04:06.289874 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 11:04:06.292671 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 11:04:06.299945 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 11:04:06.303099 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5124 11:04:06.306382 1 0 0 | B1->B0 | 3030 3f3f | 0 0 | (0 0) (0 0)
5125 11:04:06.312896 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 11:04:06.316558 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 11:04:06.319987 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 11:04:06.323243 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 11:04:06.330135 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 11:04:06.332926 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 11:04:06.336433 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5132 11:04:06.343271 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5133 11:04:06.346944 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 11:04:06.349600 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 11:04:06.356216 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 11:04:06.360072 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 11:04:06.362888 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 11:04:06.370800 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 11:04:06.373259 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 11:04:06.376720 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 11:04:06.383576 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 11:04:06.387078 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 11:04:06.390330 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 11:04:06.393333 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 11:04:06.400024 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 11:04:06.403251 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 11:04:06.406494 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 11:04:06.413295 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5149 11:04:06.417019 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5150 11:04:06.420128 Total UI for P1: 0, mck2ui 16
5151 11:04:06.423244 best dqsien dly found for B0: ( 1, 3, 0)
5152 11:04:06.427041 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 11:04:06.430111 Total UI for P1: 0, mck2ui 16
5154 11:04:06.433569 best dqsien dly found for B1: ( 1, 3, 2)
5155 11:04:06.437053 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5156 11:04:06.440044 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5157 11:04:06.440148
5158 11:04:06.443974 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5159 11:04:06.450270 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5160 11:04:06.450350 [Gating] SW calibration Done
5161 11:04:06.450411 ==
5162 11:04:06.453972 Dram Type= 6, Freq= 0, CH_0, rank 0
5163 11:04:06.461016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 11:04:06.461148 ==
5165 11:04:06.461215 RX Vref Scan: 0
5166 11:04:06.461272
5167 11:04:06.464013 RX Vref 0 -> 0, step: 1
5168 11:04:06.464091
5169 11:04:06.467056 RX Delay -80 -> 252, step: 8
5170 11:04:06.470159 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5171 11:04:06.474493 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5172 11:04:06.477284 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5173 11:04:06.480318 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5174 11:04:06.483965 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5175 11:04:06.490682 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5176 11:04:06.494621 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5177 11:04:06.497025 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5178 11:04:06.500822 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5179 11:04:06.503563 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5180 11:04:06.510501 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5181 11:04:06.513481 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5182 11:04:06.517067 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5183 11:04:06.520410 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5184 11:04:06.523637 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5185 11:04:06.527014 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5186 11:04:06.527113 ==
5187 11:04:06.530894 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 11:04:06.536792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 11:04:06.536878 ==
5190 11:04:06.536938 DQS Delay:
5191 11:04:06.540399 DQS0 = 0, DQS1 = 0
5192 11:04:06.540475 DQM Delay:
5193 11:04:06.543701 DQM0 = 98, DQM1 = 88
5194 11:04:06.543778 DQ Delay:
5195 11:04:06.546830 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5196 11:04:06.550634 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5197 11:04:06.553513 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5198 11:04:06.557006 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5199 11:04:06.557103
5200 11:04:06.557190
5201 11:04:06.557246 ==
5202 11:04:06.560294 Dram Type= 6, Freq= 0, CH_0, rank 0
5203 11:04:06.563880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5204 11:04:06.563956 ==
5205 11:04:06.564015
5206 11:04:06.564069
5207 11:04:06.566903 TX Vref Scan disable
5208 11:04:06.570336 == TX Byte 0 ==
5209 11:04:06.573670 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5210 11:04:06.577070 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5211 11:04:06.580421 == TX Byte 1 ==
5212 11:04:06.583946 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5213 11:04:06.586986 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5214 11:04:06.587099 ==
5215 11:04:06.590341 Dram Type= 6, Freq= 0, CH_0, rank 0
5216 11:04:06.593580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5217 11:04:06.596992 ==
5218 11:04:06.597096
5219 11:04:06.597195
5220 11:04:06.597268 TX Vref Scan disable
5221 11:04:06.600884 == TX Byte 0 ==
5222 11:04:06.603809 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5223 11:04:06.607427 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5224 11:04:06.610636 == TX Byte 1 ==
5225 11:04:06.614039 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5226 11:04:06.617486 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5227 11:04:06.620800
5228 11:04:06.620874 [DATLAT]
5229 11:04:06.620933 Freq=933, CH0 RK0
5230 11:04:06.620988
5231 11:04:06.623771 DATLAT Default: 0xd
5232 11:04:06.623847 0, 0xFFFF, sum = 0
5233 11:04:06.627616 1, 0xFFFF, sum = 0
5234 11:04:06.627718 2, 0xFFFF, sum = 0
5235 11:04:06.630886 3, 0xFFFF, sum = 0
5236 11:04:06.630983 4, 0xFFFF, sum = 0
5237 11:04:06.635042 5, 0xFFFF, sum = 0
5238 11:04:06.635135 6, 0xFFFF, sum = 0
5239 11:04:06.638408 7, 0xFFFF, sum = 0
5240 11:04:06.638506 8, 0xFFFF, sum = 0
5241 11:04:06.640983 9, 0xFFFF, sum = 0
5242 11:04:06.641085 10, 0x0, sum = 1
5243 11:04:06.644113 11, 0x0, sum = 2
5244 11:04:06.644216 12, 0x0, sum = 3
5245 11:04:06.647930 13, 0x0, sum = 4
5246 11:04:06.648008 best_step = 11
5247 11:04:06.648084
5248 11:04:06.648174 ==
5249 11:04:06.650920 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 11:04:06.657641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 11:04:06.657719 ==
5252 11:04:06.657796 RX Vref Scan: 1
5253 11:04:06.657868
5254 11:04:06.661028 RX Vref 0 -> 0, step: 1
5255 11:04:06.661153
5256 11:04:06.664174 RX Delay -61 -> 252, step: 4
5257 11:04:06.664291
5258 11:04:06.667481 Set Vref, RX VrefLevel [Byte0]: 52
5259 11:04:06.670831 [Byte1]: 51
5260 11:04:06.670914
5261 11:04:06.674228 Final RX Vref Byte 0 = 52 to rank0
5262 11:04:06.677843 Final RX Vref Byte 1 = 51 to rank0
5263 11:04:06.681071 Final RX Vref Byte 0 = 52 to rank1
5264 11:04:06.684161 Final RX Vref Byte 1 = 51 to rank1==
5265 11:04:06.687325 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 11:04:06.691163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 11:04:06.691242 ==
5268 11:04:06.694415 DQS Delay:
5269 11:04:06.694537 DQS0 = 0, DQS1 = 0
5270 11:04:06.694670 DQM Delay:
5271 11:04:06.697472 DQM0 = 97, DQM1 = 87
5272 11:04:06.697547 DQ Delay:
5273 11:04:06.701097 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =96
5274 11:04:06.703932 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =104
5275 11:04:06.707341 DQ8 =78, DQ9 =76, DQ10 =86, DQ11 =80
5276 11:04:06.710932 DQ12 =94, DQ13 =88, DQ14 =98, DQ15 =98
5277 11:04:06.711010
5278 11:04:06.711088
5279 11:04:06.721717 [DQSOSCAuto] RK0, (LSB)MR18= 0x1601, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5280 11:04:06.724288 CH0 RK0: MR19=505, MR18=1601
5281 11:04:06.727689 CH0_RK0: MR19=0x505, MR18=0x1601, DQSOSC=414, MR23=63, INC=63, DEC=42
5282 11:04:06.727764
5283 11:04:06.731122 ----->DramcWriteLeveling(PI) begin...
5284 11:04:06.731221 ==
5285 11:04:06.734934 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 11:04:06.740773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 11:04:06.740852 ==
5288 11:04:06.744397 Write leveling (Byte 0): 32 => 32
5289 11:04:06.747497 Write leveling (Byte 1): 31 => 31
5290 11:04:06.747575 DramcWriteLeveling(PI) end<-----
5291 11:04:06.751370
5292 11:04:06.751447 ==
5293 11:04:06.754371 Dram Type= 6, Freq= 0, CH_0, rank 1
5294 11:04:06.758108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 11:04:06.758187 ==
5296 11:04:06.761422 [Gating] SW mode calibration
5297 11:04:06.767641 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5298 11:04:06.771067 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5299 11:04:06.777829 0 14 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
5300 11:04:06.780971 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 11:04:06.784162 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 11:04:06.791283 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 11:04:06.794575 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 11:04:06.798461 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 11:04:06.804766 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5306 11:04:06.808268 0 14 28 | B1->B0 | 3333 3131 | 0 1 | (0 0) (0 0)
5307 11:04:06.811144 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
5308 11:04:06.814945 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 11:04:06.821231 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 11:04:06.824820 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 11:04:06.828503 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 11:04:06.834994 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 11:04:06.838119 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 11:04:06.841442 0 15 28 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
5315 11:04:06.848307 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5316 11:04:06.851215 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 11:04:06.854713 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 11:04:06.861689 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 11:04:06.865029 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 11:04:06.868002 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 11:04:06.874610 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 11:04:06.877950 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5323 11:04:06.881598 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5324 11:04:06.888071 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 11:04:06.891448 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 11:04:06.894899 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 11:04:06.898013 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 11:04:06.904751 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 11:04:06.907872 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 11:04:06.911938 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 11:04:06.918316 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 11:04:06.921594 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 11:04:06.925463 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 11:04:06.932038 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 11:04:06.934696 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 11:04:06.937987 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5337 11:04:06.944999 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 11:04:06.948238 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5339 11:04:06.951447 Total UI for P1: 0, mck2ui 16
5340 11:04:06.955187 best dqsien dly found for B0: ( 1, 2, 26)
5341 11:04:06.958176 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 11:04:06.961355 Total UI for P1: 0, mck2ui 16
5343 11:04:06.965009 best dqsien dly found for B1: ( 1, 2, 28)
5344 11:04:06.967988 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5345 11:04:06.971708 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5346 11:04:06.971782
5347 11:04:06.975331 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5348 11:04:06.981381 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5349 11:04:06.981457 [Gating] SW calibration Done
5350 11:04:06.981515 ==
5351 11:04:06.985504 Dram Type= 6, Freq= 0, CH_0, rank 1
5352 11:04:06.991380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5353 11:04:06.991459 ==
5354 11:04:06.991537 RX Vref Scan: 0
5355 11:04:06.991610
5356 11:04:06.994726 RX Vref 0 -> 0, step: 1
5357 11:04:06.994825
5358 11:04:06.998129 RX Delay -80 -> 252, step: 8
5359 11:04:07.001631 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5360 11:04:07.005045 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5361 11:04:07.008611 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5362 11:04:07.011641 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5363 11:04:07.015133 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5364 11:04:07.021748 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5365 11:04:07.025353 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5366 11:04:07.028258 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5367 11:04:07.031887 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5368 11:04:07.034976 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5369 11:04:07.041603 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5370 11:04:07.044867 iDelay=200, Bit 11, Center 75 (-16 ~ 167) 184
5371 11:04:07.048182 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5372 11:04:07.052178 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5373 11:04:07.055170 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5374 11:04:07.059231 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5375 11:04:07.059309 ==
5376 11:04:07.062619 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 11:04:07.068449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 11:04:07.068525 ==
5379 11:04:07.068584 DQS Delay:
5380 11:04:07.071725 DQS0 = 0, DQS1 = 0
5381 11:04:07.071800 DQM Delay:
5382 11:04:07.071858 DQM0 = 96, DQM1 = 87
5383 11:04:07.075360 DQ Delay:
5384 11:04:07.078757 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5385 11:04:07.082293 DQ4 =95, DQ5 =87, DQ6 =103, DQ7 =103
5386 11:04:07.085329 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =75
5387 11:04:07.088661 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5388 11:04:07.088738
5389 11:04:07.088814
5390 11:04:07.088887 ==
5391 11:04:07.092328 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 11:04:07.095191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 11:04:07.095270 ==
5394 11:04:07.095348
5395 11:04:07.095419
5396 11:04:07.098546 TX Vref Scan disable
5397 11:04:07.098623 == TX Byte 0 ==
5398 11:04:07.105421 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5399 11:04:07.108451 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5400 11:04:07.108530 == TX Byte 1 ==
5401 11:04:07.115360 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5402 11:04:07.118443 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5403 11:04:07.118521 ==
5404 11:04:07.121729 Dram Type= 6, Freq= 0, CH_0, rank 1
5405 11:04:07.125167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5406 11:04:07.125245 ==
5407 11:04:07.125323
5408 11:04:07.125396
5409 11:04:07.128560 TX Vref Scan disable
5410 11:04:07.132406 == TX Byte 0 ==
5411 11:04:07.135731 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5412 11:04:07.138460 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5413 11:04:07.141718 == TX Byte 1 ==
5414 11:04:07.145279 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5415 11:04:07.148557 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5416 11:04:07.148658
5417 11:04:07.151972 [DATLAT]
5418 11:04:07.152050 Freq=933, CH0 RK1
5419 11:04:07.152127
5420 11:04:07.155933 DATLAT Default: 0xb
5421 11:04:07.156011 0, 0xFFFF, sum = 0
5422 11:04:07.158555 1, 0xFFFF, sum = 0
5423 11:04:07.158633 2, 0xFFFF, sum = 0
5424 11:04:07.162087 3, 0xFFFF, sum = 0
5425 11:04:07.162166 4, 0xFFFF, sum = 0
5426 11:04:07.165335 5, 0xFFFF, sum = 0
5427 11:04:07.165414 6, 0xFFFF, sum = 0
5428 11:04:07.168530 7, 0xFFFF, sum = 0
5429 11:04:07.168609 8, 0xFFFF, sum = 0
5430 11:04:07.172354 9, 0xFFFF, sum = 0
5431 11:04:07.172433 10, 0x0, sum = 1
5432 11:04:07.175053 11, 0x0, sum = 2
5433 11:04:07.175147 12, 0x0, sum = 3
5434 11:04:07.178807 13, 0x0, sum = 4
5435 11:04:07.178886 best_step = 11
5436 11:04:07.178962
5437 11:04:07.179034 ==
5438 11:04:07.182123 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 11:04:07.188528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 11:04:07.188606 ==
5441 11:04:07.188699 RX Vref Scan: 0
5442 11:04:07.188785
5443 11:04:07.191701 RX Vref 0 -> 0, step: 1
5444 11:04:07.191778
5445 11:04:07.195212 RX Delay -61 -> 252, step: 4
5446 11:04:07.198349 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5447 11:04:07.201613 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5448 11:04:07.208360 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5449 11:04:07.211778 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5450 11:04:07.215493 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5451 11:04:07.218503 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5452 11:04:07.221918 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5453 11:04:07.225841 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5454 11:04:07.228901 iDelay=199, Bit 8, Center 78 (-9 ~ 166) 176
5455 11:04:07.235588 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5456 11:04:07.238945 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5457 11:04:07.242168 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5458 11:04:07.245340 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5459 11:04:07.249206 iDelay=199, Bit 13, Center 90 (3 ~ 178) 176
5460 11:04:07.255030 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5461 11:04:07.258746 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5462 11:04:07.258824 ==
5463 11:04:07.261989 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 11:04:07.265619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 11:04:07.265698 ==
5466 11:04:07.265775 DQS Delay:
5467 11:04:07.269079 DQS0 = 0, DQS1 = 0
5468 11:04:07.269190 DQM Delay:
5469 11:04:07.272491 DQM0 = 95, DQM1 = 87
5470 11:04:07.272569 DQ Delay:
5471 11:04:07.275326 DQ0 =96, DQ1 =96, DQ2 =94, DQ3 =94
5472 11:04:07.278770 DQ4 =94, DQ5 =84, DQ6 =106, DQ7 =102
5473 11:04:07.282170 DQ8 =78, DQ9 =80, DQ10 =88, DQ11 =80
5474 11:04:07.285368 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =94
5475 11:04:07.285446
5476 11:04:07.285523
5477 11:04:07.295820 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b09, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5478 11:04:07.295898 CH0 RK1: MR19=505, MR18=1B09
5479 11:04:07.301995 CH0_RK1: MR19=0x505, MR18=0x1B09, DQSOSC=413, MR23=63, INC=63, DEC=42
5480 11:04:07.305728 [RxdqsGatingPostProcess] freq 933
5481 11:04:07.312095 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5482 11:04:07.315320 best DQS0 dly(2T, 0.5T) = (0, 11)
5483 11:04:07.318828 best DQS1 dly(2T, 0.5T) = (0, 11)
5484 11:04:07.321826 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5485 11:04:07.325151 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5486 11:04:07.325231 best DQS0 dly(2T, 0.5T) = (0, 10)
5487 11:04:07.328557 best DQS1 dly(2T, 0.5T) = (0, 10)
5488 11:04:07.332622 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5489 11:04:07.335356 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5490 11:04:07.338481 Pre-setting of DQS Precalculation
5491 11:04:07.345158 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5492 11:04:07.345237 ==
5493 11:04:07.348986 Dram Type= 6, Freq= 0, CH_1, rank 0
5494 11:04:07.351819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5495 11:04:07.351897 ==
5496 11:04:07.359041 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5497 11:04:07.361887 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5498 11:04:07.366369 [CA 0] Center 36 (6~67) winsize 62
5499 11:04:07.369996 [CA 1] Center 36 (6~67) winsize 62
5500 11:04:07.373006 [CA 2] Center 34 (4~64) winsize 61
5501 11:04:07.376602 [CA 3] Center 33 (3~64) winsize 62
5502 11:04:07.379550 [CA 4] Center 34 (4~64) winsize 61
5503 11:04:07.383018 [CA 5] Center 33 (2~64) winsize 63
5504 11:04:07.383112
5505 11:04:07.386850 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5506 11:04:07.386926
5507 11:04:07.389501 [CATrainingPosCal] consider 1 rank data
5508 11:04:07.393293 u2DelayCellTimex100 = 270/100 ps
5509 11:04:07.396420 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5510 11:04:07.399683 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5511 11:04:07.406502 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5512 11:04:07.409705 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5513 11:04:07.413638 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5514 11:04:07.416737 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5515 11:04:07.416814
5516 11:04:07.419810 CA PerBit enable=1, Macro0, CA PI delay=33
5517 11:04:07.419888
5518 11:04:07.424298 [CBTSetCACLKResult] CA Dly = 33
5519 11:04:07.424376 CS Dly: 4 (0~35)
5520 11:04:07.424453 ==
5521 11:04:07.426654 Dram Type= 6, Freq= 0, CH_1, rank 1
5522 11:04:07.433601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 11:04:07.433679 ==
5524 11:04:07.436393 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5525 11:04:07.443366 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5526 11:04:07.446594 [CA 0] Center 36 (6~67) winsize 62
5527 11:04:07.450504 [CA 1] Center 36 (6~67) winsize 62
5528 11:04:07.453154 [CA 2] Center 33 (3~64) winsize 62
5529 11:04:07.456563 [CA 3] Center 33 (3~64) winsize 62
5530 11:04:07.460280 [CA 4] Center 34 (4~65) winsize 62
5531 11:04:07.463566 [CA 5] Center 32 (2~63) winsize 62
5532 11:04:07.463644
5533 11:04:07.466406 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5534 11:04:07.466484
5535 11:04:07.470115 [CATrainingPosCal] consider 2 rank data
5536 11:04:07.473094 u2DelayCellTimex100 = 270/100 ps
5537 11:04:07.476640 CA0 delay=36 (6~67),Diff = 4 PI (24 cell)
5538 11:04:07.480505 CA1 delay=36 (6~67),Diff = 4 PI (24 cell)
5539 11:04:07.483315 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5540 11:04:07.490217 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5541 11:04:07.493241 CA4 delay=34 (4~64),Diff = 2 PI (12 cell)
5542 11:04:07.496806 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5543 11:04:07.496884
5544 11:04:07.500004 CA PerBit enable=1, Macro0, CA PI delay=32
5545 11:04:07.500082
5546 11:04:07.503471 [CBTSetCACLKResult] CA Dly = 32
5547 11:04:07.503549 CS Dly: 5 (0~37)
5548 11:04:07.503626
5549 11:04:07.506667 ----->DramcWriteLeveling(PI) begin...
5550 11:04:07.506747 ==
5551 11:04:07.510332 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 11:04:07.517052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 11:04:07.517155 ==
5554 11:04:07.520286 Write leveling (Byte 0): 28 => 28
5555 11:04:07.523523 Write leveling (Byte 1): 31 => 31
5556 11:04:07.523601 DramcWriteLeveling(PI) end<-----
5557 11:04:07.523678
5558 11:04:07.526872 ==
5559 11:04:07.530101 Dram Type= 6, Freq= 0, CH_1, rank 0
5560 11:04:07.533354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 11:04:07.533432 ==
5562 11:04:07.536942 [Gating] SW mode calibration
5563 11:04:07.543475 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5564 11:04:07.546927 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5565 11:04:07.553330 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5566 11:04:07.557344 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 11:04:07.560415 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 11:04:07.566917 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 11:04:07.570186 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 11:04:07.573234 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 11:04:07.580092 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 11:04:07.583185 0 14 28 | B1->B0 | 2f2f 3131 | 0 0 | (0 1) (0 1)
5573 11:04:07.587248 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 11:04:07.593354 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 11:04:07.596644 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 11:04:07.599916 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 11:04:07.603637 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 11:04:07.610316 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 11:04:07.614007 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 11:04:07.616772 0 15 28 | B1->B0 | 3131 3232 | 0 0 | (0 0) (0 0)
5581 11:04:07.623709 1 0 0 | B1->B0 | 4141 4242 | 0 1 | (0 0) (0 0)
5582 11:04:07.626919 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 11:04:07.630318 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 11:04:07.636617 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 11:04:07.640241 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 11:04:07.643319 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 11:04:07.650809 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 11:04:07.654182 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5589 11:04:07.656933 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5590 11:04:07.664119 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 11:04:07.667278 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 11:04:07.670662 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 11:04:07.674412 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 11:04:07.680321 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 11:04:07.683652 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 11:04:07.686984 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 11:04:07.693500 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 11:04:07.697168 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 11:04:07.700377 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 11:04:07.707072 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 11:04:07.710318 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 11:04:07.713532 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 11:04:07.720461 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5604 11:04:07.723619 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5605 11:04:07.727324 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 11:04:07.730323 Total UI for P1: 0, mck2ui 16
5607 11:04:07.733848 best dqsien dly found for B0: ( 1, 2, 26)
5608 11:04:07.737357 Total UI for P1: 0, mck2ui 16
5609 11:04:07.740689 best dqsien dly found for B1: ( 1, 2, 28)
5610 11:04:07.743970 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5611 11:04:07.747007 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5612 11:04:07.747083
5613 11:04:07.753748 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5614 11:04:07.757057 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5615 11:04:07.757173 [Gating] SW calibration Done
5616 11:04:07.760662 ==
5617 11:04:07.760762 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 11:04:07.766752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 11:04:07.766828 ==
5620 11:04:07.766888 RX Vref Scan: 0
5621 11:04:07.766943
5622 11:04:07.770157 RX Vref 0 -> 0, step: 1
5623 11:04:07.770232
5624 11:04:07.773988 RX Delay -80 -> 252, step: 8
5625 11:04:07.777589 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5626 11:04:07.780131 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5627 11:04:07.784024 iDelay=208, Bit 2, Center 83 (-8 ~ 175) 184
5628 11:04:07.787307 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5629 11:04:07.794120 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5630 11:04:07.797306 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5631 11:04:07.800525 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5632 11:04:07.804281 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5633 11:04:07.807057 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5634 11:04:07.810409 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5635 11:04:07.817112 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5636 11:04:07.820252 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5637 11:04:07.824340 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5638 11:04:07.827336 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5639 11:04:07.830243 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5640 11:04:07.834018 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5641 11:04:07.837065 ==
5642 11:04:07.837188 Dram Type= 6, Freq= 0, CH_1, rank 0
5643 11:04:07.843917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5644 11:04:07.843993 ==
5645 11:04:07.844053 DQS Delay:
5646 11:04:07.847754 DQS0 = 0, DQS1 = 0
5647 11:04:07.847842 DQM Delay:
5648 11:04:07.850693 DQM0 = 96, DQM1 = 88
5649 11:04:07.850768 DQ Delay:
5650 11:04:07.854351 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5651 11:04:07.857566 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5652 11:04:07.860620 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =87
5653 11:04:07.864014 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5654 11:04:07.864128
5655 11:04:07.864188
5656 11:04:07.864242 ==
5657 11:04:07.867263 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 11:04:07.870916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 11:04:07.870991 ==
5660 11:04:07.871050
5661 11:04:07.871104
5662 11:04:07.874131 TX Vref Scan disable
5663 11:04:07.877441 == TX Byte 0 ==
5664 11:04:07.880641 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5665 11:04:07.883998 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5666 11:04:07.887412 == TX Byte 1 ==
5667 11:04:07.890784 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5668 11:04:07.894251 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5669 11:04:07.894327 ==
5670 11:04:07.897433 Dram Type= 6, Freq= 0, CH_1, rank 0
5671 11:04:07.900874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5672 11:04:07.900945 ==
5673 11:04:07.903850
5674 11:04:07.903919
5675 11:04:07.903976 TX Vref Scan disable
5676 11:04:07.908042 == TX Byte 0 ==
5677 11:04:07.910848 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5678 11:04:07.914276 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5679 11:04:07.917361 == TX Byte 1 ==
5680 11:04:07.921015 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5681 11:04:07.924427 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5682 11:04:07.924502
5683 11:04:07.927477 [DATLAT]
5684 11:04:07.927552 Freq=933, CH1 RK0
5685 11:04:07.927610
5686 11:04:07.931157 DATLAT Default: 0xd
5687 11:04:07.931234 0, 0xFFFF, sum = 0
5688 11:04:07.934293 1, 0xFFFF, sum = 0
5689 11:04:07.934371 2, 0xFFFF, sum = 0
5690 11:04:07.937523 3, 0xFFFF, sum = 0
5691 11:04:07.937599 4, 0xFFFF, sum = 0
5692 11:04:07.941073 5, 0xFFFF, sum = 0
5693 11:04:07.941160 6, 0xFFFF, sum = 0
5694 11:04:07.944202 7, 0xFFFF, sum = 0
5695 11:04:07.944278 8, 0xFFFF, sum = 0
5696 11:04:07.947577 9, 0xFFFF, sum = 0
5697 11:04:07.947652 10, 0x0, sum = 1
5698 11:04:07.950725 11, 0x0, sum = 2
5699 11:04:07.950801 12, 0x0, sum = 3
5700 11:04:07.954260 13, 0x0, sum = 4
5701 11:04:07.954348 best_step = 11
5702 11:04:07.954407
5703 11:04:07.954461 ==
5704 11:04:07.957865 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 11:04:07.964325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 11:04:07.964401 ==
5707 11:04:07.964460 RX Vref Scan: 1
5708 11:04:07.964515
5709 11:04:07.967348 RX Vref 0 -> 0, step: 1
5710 11:04:07.967424
5711 11:04:07.970995 RX Delay -69 -> 252, step: 4
5712 11:04:07.971070
5713 11:04:07.974307 Set Vref, RX VrefLevel [Byte0]: 55
5714 11:04:07.977896 [Byte1]: 47
5715 11:04:07.977972
5716 11:04:07.980591 Final RX Vref Byte 0 = 55 to rank0
5717 11:04:07.984782 Final RX Vref Byte 1 = 47 to rank0
5718 11:04:07.987314 Final RX Vref Byte 0 = 55 to rank1
5719 11:04:07.990731 Final RX Vref Byte 1 = 47 to rank1==
5720 11:04:07.994394 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 11:04:07.997411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 11:04:07.997487 ==
5723 11:04:08.000747 DQS Delay:
5724 11:04:08.000837 DQS0 = 0, DQS1 = 0
5725 11:04:08.000936 DQM Delay:
5726 11:04:08.004257 DQM0 = 97, DQM1 = 89
5727 11:04:08.004333 DQ Delay:
5728 11:04:08.007927 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =96
5729 11:04:08.011253 DQ4 =96, DQ5 =110, DQ6 =108, DQ7 =92
5730 11:04:08.015174 DQ8 =80, DQ9 =76, DQ10 =92, DQ11 =84
5731 11:04:08.018263 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =94
5732 11:04:08.018339
5733 11:04:08.018414
5734 11:04:08.027764 [DQSOSCAuto] RK0, (LSB)MR18= 0x1bf7, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 413 ps
5735 11:04:08.031135 CH1 RK0: MR19=504, MR18=1BF7
5736 11:04:08.034495 CH1_RK0: MR19=0x504, MR18=0x1BF7, DQSOSC=413, MR23=63, INC=63, DEC=42
5737 11:04:08.034571
5738 11:04:08.038299 ----->DramcWriteLeveling(PI) begin...
5739 11:04:08.040802 ==
5740 11:04:08.040879 Dram Type= 6, Freq= 0, CH_1, rank 1
5741 11:04:08.047529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 11:04:08.047606 ==
5743 11:04:08.051371 Write leveling (Byte 0): 30 => 30
5744 11:04:08.054691 Write leveling (Byte 1): 30 => 30
5745 11:04:08.057635 DramcWriteLeveling(PI) end<-----
5746 11:04:08.057710
5747 11:04:08.057769 ==
5748 11:04:08.061073 Dram Type= 6, Freq= 0, CH_1, rank 1
5749 11:04:08.064573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 11:04:08.064650 ==
5751 11:04:08.068207 [Gating] SW mode calibration
5752 11:04:08.075482 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5753 11:04:08.078215 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5754 11:04:08.084633 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 11:04:08.088756 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 11:04:08.091397 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 11:04:08.097869 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5758 11:04:08.101681 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 11:04:08.104927 0 14 20 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
5760 11:04:08.111876 0 14 24 | B1->B0 | 3232 2f2f | 1 0 | (1 1) (0 1)
5761 11:04:08.114881 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (1 0)
5762 11:04:08.118062 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 11:04:08.121398 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 11:04:08.128378 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 11:04:08.131845 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 11:04:08.135074 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 11:04:08.141442 0 15 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5768 11:04:08.144986 0 15 24 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
5769 11:04:08.148598 0 15 28 | B1->B0 | 3939 4343 | 0 0 | (1 1) (0 0)
5770 11:04:08.155424 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 11:04:08.158064 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 11:04:08.161763 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 11:04:08.168157 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 11:04:08.171909 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 11:04:08.175115 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 11:04:08.181981 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5777 11:04:08.185322 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 11:04:08.188287 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5779 11:04:08.195047 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 11:04:08.198283 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 11:04:08.202018 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 11:04:08.206114 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 11:04:08.212524 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 11:04:08.214865 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 11:04:08.218386 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 11:04:08.224981 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 11:04:08.228129 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 11:04:08.231702 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 11:04:08.238454 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 11:04:08.241923 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 11:04:08.245255 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5792 11:04:08.251980 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5793 11:04:08.254937 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 11:04:08.258387 Total UI for P1: 0, mck2ui 16
5795 11:04:08.261802 best dqsien dly found for B0: ( 1, 2, 22)
5796 11:04:08.265447 Total UI for P1: 0, mck2ui 16
5797 11:04:08.268489 best dqsien dly found for B1: ( 1, 2, 24)
5798 11:04:08.271822 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5799 11:04:08.275513 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5800 11:04:08.275590
5801 11:04:08.278527 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5802 11:04:08.281828 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5803 11:04:08.285160 [Gating] SW calibration Done
5804 11:04:08.285236 ==
5805 11:04:08.288711 Dram Type= 6, Freq= 0, CH_1, rank 1
5806 11:04:08.291885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5807 11:04:08.291962 ==
5808 11:04:08.295175 RX Vref Scan: 0
5809 11:04:08.295251
5810 11:04:08.298322 RX Vref 0 -> 0, step: 1
5811 11:04:08.298396
5812 11:04:08.298455 RX Delay -80 -> 252, step: 8
5813 11:04:08.317970 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5814 11:04:08.318068 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5815 11:04:08.318129 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5816 11:04:08.318185 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5817 11:04:08.318843 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5818 11:04:08.321991 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5819 11:04:08.328641 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5820 11:04:08.331874 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5821 11:04:08.334923 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5822 11:04:08.338451 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5823 11:04:08.341480 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5824 11:04:08.345186 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5825 11:04:08.352008 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5826 11:04:08.355268 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5827 11:04:08.358595 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5828 11:04:08.361869 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5829 11:04:08.361944 ==
5830 11:04:08.365104 Dram Type= 6, Freq= 0, CH_1, rank 1
5831 11:04:08.368801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5832 11:04:08.371791 ==
5833 11:04:08.371866 DQS Delay:
5834 11:04:08.371925 DQS0 = 0, DQS1 = 0
5835 11:04:08.375601 DQM Delay:
5836 11:04:08.375678 DQM0 = 94, DQM1 = 89
5837 11:04:08.375738 DQ Delay:
5838 11:04:08.378364 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5839 11:04:08.381741 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5840 11:04:08.385425 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5841 11:04:08.388875 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5842 11:04:08.388951
5843 11:04:08.391952
5844 11:04:08.392026 ==
5845 11:04:08.395418 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 11:04:08.398460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 11:04:08.398537 ==
5848 11:04:08.398595
5849 11:04:08.398649
5850 11:04:08.402514 TX Vref Scan disable
5851 11:04:08.402600 == TX Byte 0 ==
5852 11:04:08.406145 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5853 11:04:08.411804 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5854 11:04:08.411880 == TX Byte 1 ==
5855 11:04:08.415651 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5856 11:04:08.422232 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5857 11:04:08.422308 ==
5858 11:04:08.425176 Dram Type= 6, Freq= 0, CH_1, rank 1
5859 11:04:08.428927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5860 11:04:08.429002 ==
5861 11:04:08.429060
5862 11:04:08.429113
5863 11:04:08.432104 TX Vref Scan disable
5864 11:04:08.435465 == TX Byte 0 ==
5865 11:04:08.439039 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5866 11:04:08.442244 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5867 11:04:08.445709 == TX Byte 1 ==
5868 11:04:08.448839 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5869 11:04:08.452285 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5870 11:04:08.452362
5871 11:04:08.452421 [DATLAT]
5872 11:04:08.455830 Freq=933, CH1 RK1
5873 11:04:08.455904
5874 11:04:08.455961 DATLAT Default: 0xb
5875 11:04:08.458878 0, 0xFFFF, sum = 0
5876 11:04:08.463110 1, 0xFFFF, sum = 0
5877 11:04:08.463185 2, 0xFFFF, sum = 0
5878 11:04:08.465498 3, 0xFFFF, sum = 0
5879 11:04:08.465574 4, 0xFFFF, sum = 0
5880 11:04:08.469437 5, 0xFFFF, sum = 0
5881 11:04:08.469513 6, 0xFFFF, sum = 0
5882 11:04:08.471943 7, 0xFFFF, sum = 0
5883 11:04:08.472018 8, 0xFFFF, sum = 0
5884 11:04:08.475656 9, 0xFFFF, sum = 0
5885 11:04:08.475743 10, 0x0, sum = 1
5886 11:04:08.479503 11, 0x0, sum = 2
5887 11:04:08.479578 12, 0x0, sum = 3
5888 11:04:08.482114 13, 0x0, sum = 4
5889 11:04:08.482190 best_step = 11
5890 11:04:08.482247
5891 11:04:08.482301 ==
5892 11:04:08.485389 Dram Type= 6, Freq= 0, CH_1, rank 1
5893 11:04:08.488954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5894 11:04:08.489029 ==
5895 11:04:08.492545 RX Vref Scan: 0
5896 11:04:08.492620
5897 11:04:08.492677 RX Vref 0 -> 0, step: 1
5898 11:04:08.495620
5899 11:04:08.495693 RX Delay -61 -> 252, step: 4
5900 11:04:08.503458 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5901 11:04:08.506326 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5902 11:04:08.509717 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5903 11:04:08.513055 iDelay=199, Bit 3, Center 90 (-1 ~ 182) 184
5904 11:04:08.516301 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5905 11:04:08.519867 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5906 11:04:08.526619 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5907 11:04:08.529879 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5908 11:04:08.533289 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5909 11:04:08.536956 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5910 11:04:08.539877 iDelay=199, Bit 10, Center 92 (3 ~ 182) 180
5911 11:04:08.543704 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5912 11:04:08.549774 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5913 11:04:08.553095 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5914 11:04:08.557009 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5915 11:04:08.559754 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5916 11:04:08.559829 ==
5917 11:04:08.563441 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 11:04:08.570052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 11:04:08.570128 ==
5920 11:04:08.570187 DQS Delay:
5921 11:04:08.570240 DQS0 = 0, DQS1 = 0
5922 11:04:08.573231 DQM Delay:
5923 11:04:08.573305 DQM0 = 94, DQM1 = 90
5924 11:04:08.576423 DQ Delay:
5925 11:04:08.580460 DQ0 =98, DQ1 =88, DQ2 =84, DQ3 =90
5926 11:04:08.583498 DQ4 =96, DQ5 =104, DQ6 =104, DQ7 =90
5927 11:04:08.586400 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
5928 11:04:08.589840 DQ12 =94, DQ13 =100, DQ14 =100, DQ15 =96
5929 11:04:08.589915
5930 11:04:08.589973
5931 11:04:08.596619 [DQSOSCAuto] RK1, (LSB)MR18= 0x141d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 415 ps
5932 11:04:08.599810 CH1 RK1: MR19=505, MR18=141D
5933 11:04:08.607029 CH1_RK1: MR19=0x505, MR18=0x141D, DQSOSC=412, MR23=63, INC=63, DEC=42
5934 11:04:08.609951 [RxdqsGatingPostProcess] freq 933
5935 11:04:08.613572 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5936 11:04:08.616796 best DQS0 dly(2T, 0.5T) = (0, 10)
5937 11:04:08.620064 best DQS1 dly(2T, 0.5T) = (0, 10)
5938 11:04:08.623436 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5939 11:04:08.626542 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5940 11:04:08.630123 best DQS0 dly(2T, 0.5T) = (0, 10)
5941 11:04:08.633538 best DQS1 dly(2T, 0.5T) = (0, 10)
5942 11:04:08.636679 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5943 11:04:08.639945 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5944 11:04:08.643553 Pre-setting of DQS Precalculation
5945 11:04:08.646955 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5946 11:04:08.653607 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5947 11:04:08.663625 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5948 11:04:08.663702
5949 11:04:08.663760
5950 11:04:08.663814 [Calibration Summary] 1866 Mbps
5951 11:04:08.667410 CH 0, Rank 0
5952 11:04:08.667485 SW Impedance : PASS
5953 11:04:08.671227 DUTY Scan : NO K
5954 11:04:08.673278 ZQ Calibration : PASS
5955 11:04:08.673390 Jitter Meter : NO K
5956 11:04:08.676939 CBT Training : PASS
5957 11:04:08.680451 Write leveling : PASS
5958 11:04:08.680526 RX DQS gating : PASS
5959 11:04:08.684106 RX DQ/DQS(RDDQC) : PASS
5960 11:04:08.687019 TX DQ/DQS : PASS
5961 11:04:08.687159 RX DATLAT : PASS
5962 11:04:08.690343 RX DQ/DQS(Engine): PASS
5963 11:04:08.693539 TX OE : NO K
5964 11:04:08.693616 All Pass.
5965 11:04:08.693675
5966 11:04:08.693732 CH 0, Rank 1
5967 11:04:08.696798 SW Impedance : PASS
5968 11:04:08.700244 DUTY Scan : NO K
5969 11:04:08.700318 ZQ Calibration : PASS
5970 11:04:08.703524 Jitter Meter : NO K
5971 11:04:08.703599 CBT Training : PASS
5972 11:04:08.707265 Write leveling : PASS
5973 11:04:08.710393 RX DQS gating : PASS
5974 11:04:08.710469 RX DQ/DQS(RDDQC) : PASS
5975 11:04:08.713419 TX DQ/DQS : PASS
5976 11:04:08.716656 RX DATLAT : PASS
5977 11:04:08.716730 RX DQ/DQS(Engine): PASS
5978 11:04:08.720362 TX OE : NO K
5979 11:04:08.720437 All Pass.
5980 11:04:08.720496
5981 11:04:08.724052 CH 1, Rank 0
5982 11:04:08.724128 SW Impedance : PASS
5983 11:04:08.727002 DUTY Scan : NO K
5984 11:04:08.730106 ZQ Calibration : PASS
5985 11:04:08.730181 Jitter Meter : NO K
5986 11:04:08.733851 CBT Training : PASS
5987 11:04:08.737026 Write leveling : PASS
5988 11:04:08.737101 RX DQS gating : PASS
5989 11:04:08.740595 RX DQ/DQS(RDDQC) : PASS
5990 11:04:08.740670 TX DQ/DQS : PASS
5991 11:04:08.743622 RX DATLAT : PASS
5992 11:04:08.746816 RX DQ/DQS(Engine): PASS
5993 11:04:08.746892 TX OE : NO K
5994 11:04:08.751019 All Pass.
5995 11:04:08.751093
5996 11:04:08.751151 CH 1, Rank 1
5997 11:04:08.754108 SW Impedance : PASS
5998 11:04:08.754184 DUTY Scan : NO K
5999 11:04:08.756996 ZQ Calibration : PASS
6000 11:04:08.760403 Jitter Meter : NO K
6001 11:04:08.760478 CBT Training : PASS
6002 11:04:08.763703 Write leveling : PASS
6003 11:04:08.766836 RX DQS gating : PASS
6004 11:04:08.766911 RX DQ/DQS(RDDQC) : PASS
6005 11:04:08.770427 TX DQ/DQS : PASS
6006 11:04:08.773435 RX DATLAT : PASS
6007 11:04:08.773511 RX DQ/DQS(Engine): PASS
6008 11:04:08.776903 TX OE : NO K
6009 11:04:08.777006 All Pass.
6010 11:04:08.777127
6011 11:04:08.780572 DramC Write-DBI off
6012 11:04:08.784251 PER_BANK_REFRESH: Hybrid Mode
6013 11:04:08.784327 TX_TRACKING: ON
6014 11:04:08.793706 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6015 11:04:08.796984 [FAST_K] Save calibration result to emmc
6016 11:04:08.800155 dramc_set_vcore_voltage set vcore to 650000
6017 11:04:08.803553 Read voltage for 400, 6
6018 11:04:08.803652 Vio18 = 0
6019 11:04:08.803738 Vcore = 650000
6020 11:04:08.807039 Vdram = 0
6021 11:04:08.807134 Vddq = 0
6022 11:04:08.807207 Vmddr = 0
6023 11:04:08.813407 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6024 11:04:08.816772 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6025 11:04:08.820468 MEM_TYPE=3, freq_sel=20
6026 11:04:08.823887 sv_algorithm_assistance_LP4_800
6027 11:04:08.827452 ============ PULL DRAM RESETB DOWN ============
6028 11:04:08.830461 ========== PULL DRAM RESETB DOWN end =========
6029 11:04:08.837023 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6030 11:04:08.840440 ===================================
6031 11:04:08.840517 LPDDR4 DRAM CONFIGURATION
6032 11:04:08.843860 ===================================
6033 11:04:08.847103 EX_ROW_EN[0] = 0x0
6034 11:04:08.847178 EX_ROW_EN[1] = 0x0
6035 11:04:08.850642 LP4Y_EN = 0x0
6036 11:04:08.853715 WORK_FSP = 0x0
6037 11:04:08.853789 WL = 0x2
6038 11:04:08.857026 RL = 0x2
6039 11:04:08.857173 BL = 0x2
6040 11:04:08.860554 RPST = 0x0
6041 11:04:08.860651 RD_PRE = 0x0
6042 11:04:08.863644 WR_PRE = 0x1
6043 11:04:08.863718 WR_PST = 0x0
6044 11:04:08.867046 DBI_WR = 0x0
6045 11:04:08.867121 DBI_RD = 0x0
6046 11:04:08.870306 OTF = 0x1
6047 11:04:08.873841 ===================================
6048 11:04:08.876932 ===================================
6049 11:04:08.877006 ANA top config
6050 11:04:08.880307 ===================================
6051 11:04:08.883957 DLL_ASYNC_EN = 0
6052 11:04:08.887198 ALL_SLAVE_EN = 1
6053 11:04:08.887311 NEW_RANK_MODE = 1
6054 11:04:08.890675 DLL_IDLE_MODE = 1
6055 11:04:08.894898 LP45_APHY_COMB_EN = 1
6056 11:04:08.897470 TX_ODT_DIS = 1
6057 11:04:08.897545 NEW_8X_MODE = 1
6058 11:04:08.900517 ===================================
6059 11:04:08.904171 ===================================
6060 11:04:08.907164 data_rate = 800
6061 11:04:08.910188 CKR = 1
6062 11:04:08.913706 DQ_P2S_RATIO = 4
6063 11:04:08.917338 ===================================
6064 11:04:08.920610 CA_P2S_RATIO = 4
6065 11:04:08.924184 DQ_CA_OPEN = 0
6066 11:04:08.924258 DQ_SEMI_OPEN = 1
6067 11:04:08.926917 CA_SEMI_OPEN = 1
6068 11:04:08.930717 CA_FULL_RATE = 0
6069 11:04:08.933854 DQ_CKDIV4_EN = 0
6070 11:04:08.937306 CA_CKDIV4_EN = 1
6071 11:04:08.940458 CA_PREDIV_EN = 0
6072 11:04:08.940532 PH8_DLY = 0
6073 11:04:08.944099 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6074 11:04:08.947429 DQ_AAMCK_DIV = 0
6075 11:04:08.950802 CA_AAMCK_DIV = 0
6076 11:04:08.954034 CA_ADMCK_DIV = 4
6077 11:04:08.957431 DQ_TRACK_CA_EN = 0
6078 11:04:08.957505 CA_PICK = 800
6079 11:04:08.960646 CA_MCKIO = 400
6080 11:04:08.964042 MCKIO_SEMI = 400
6081 11:04:08.967464 PLL_FREQ = 3016
6082 11:04:08.970915 DQ_UI_PI_RATIO = 32
6083 11:04:08.973924 CA_UI_PI_RATIO = 32
6084 11:04:08.977500 ===================================
6085 11:04:08.980360 ===================================
6086 11:04:08.980434 memory_type:LPDDR4
6087 11:04:08.984513 GP_NUM : 10
6088 11:04:08.987876 SRAM_EN : 1
6089 11:04:08.987950 MD32_EN : 0
6090 11:04:08.990580 ===================================
6091 11:04:08.993963 [ANA_INIT] >>>>>>>>>>>>>>
6092 11:04:08.997232 <<<<<< [CONFIGURE PHASE]: ANA_TX
6093 11:04:09.000559 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6094 11:04:09.004433 ===================================
6095 11:04:09.007343 data_rate = 800,PCW = 0X7400
6096 11:04:09.010802 ===================================
6097 11:04:09.014004 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6098 11:04:09.017280 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6099 11:04:09.031006 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6100 11:04:09.034191 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6101 11:04:09.037443 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6102 11:04:09.040769 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6103 11:04:09.044721 [ANA_INIT] flow start
6104 11:04:09.044796 [ANA_INIT] PLL >>>>>>>>
6105 11:04:09.047810 [ANA_INIT] PLL <<<<<<<<
6106 11:04:09.050808 [ANA_INIT] MIDPI >>>>>>>>
6107 11:04:09.054341 [ANA_INIT] MIDPI <<<<<<<<
6108 11:04:09.054415 [ANA_INIT] DLL >>>>>>>>
6109 11:04:09.057358 [ANA_INIT] flow end
6110 11:04:09.061203 ============ LP4 DIFF to SE enter ============
6111 11:04:09.064720 ============ LP4 DIFF to SE exit ============
6112 11:04:09.067445 [ANA_INIT] <<<<<<<<<<<<<
6113 11:04:09.070818 [Flow] Enable top DCM control >>>>>
6114 11:04:09.074289 [Flow] Enable top DCM control <<<<<
6115 11:04:09.077409 Enable DLL master slave shuffle
6116 11:04:09.080957 ==============================================================
6117 11:04:09.084369 Gating Mode config
6118 11:04:09.090596 ==============================================================
6119 11:04:09.090672 Config description:
6120 11:04:09.100822 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6121 11:04:09.107221 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6122 11:04:09.114916 SELPH_MODE 0: By rank 1: By Phase
6123 11:04:09.118018 ==============================================================
6124 11:04:09.121103 GAT_TRACK_EN = 0
6125 11:04:09.124681 RX_GATING_MODE = 2
6126 11:04:09.128010 RX_GATING_TRACK_MODE = 2
6127 11:04:09.130682 SELPH_MODE = 1
6128 11:04:09.134315 PICG_EARLY_EN = 1
6129 11:04:09.138085 VALID_LAT_VALUE = 1
6130 11:04:09.140794 ==============================================================
6131 11:04:09.143865 Enter into Gating configuration >>>>
6132 11:04:09.147654 Exit from Gating configuration <<<<
6133 11:04:09.151528 Enter into DVFS_PRE_config >>>>>
6134 11:04:09.164735 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6135 11:04:09.164812 Exit from DVFS_PRE_config <<<<<
6136 11:04:09.167425 Enter into PICG configuration >>>>
6137 11:04:09.170905 Exit from PICG configuration <<<<
6138 11:04:09.173971 [RX_INPUT] configuration >>>>>
6139 11:04:09.177440 [RX_INPUT] configuration <<<<<
6140 11:04:09.183958 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6141 11:04:09.187584 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6142 11:04:09.193971 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6143 11:04:09.200658 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6144 11:04:09.207693 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6145 11:04:09.214086 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6146 11:04:09.217695 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6147 11:04:09.220503 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6148 11:04:09.223897 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6149 11:04:09.230690 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6150 11:04:09.233983 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6151 11:04:09.237512 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6152 11:04:09.240729 ===================================
6153 11:04:09.244637 LPDDR4 DRAM CONFIGURATION
6154 11:04:09.247607 ===================================
6155 11:04:09.247683 EX_ROW_EN[0] = 0x0
6156 11:04:09.251183 EX_ROW_EN[1] = 0x0
6157 11:04:09.251258 LP4Y_EN = 0x0
6158 11:04:09.253957 WORK_FSP = 0x0
6159 11:04:09.258080 WL = 0x2
6160 11:04:09.258155 RL = 0x2
6161 11:04:09.261211 BL = 0x2
6162 11:04:09.261293 RPST = 0x0
6163 11:04:09.264657 RD_PRE = 0x0
6164 11:04:09.264733 WR_PRE = 0x1
6165 11:04:09.267394 WR_PST = 0x0
6166 11:04:09.267469 DBI_WR = 0x0
6167 11:04:09.270791 DBI_RD = 0x0
6168 11:04:09.270866 OTF = 0x1
6169 11:04:09.274050 ===================================
6170 11:04:09.277682 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6171 11:04:09.281415 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6172 11:04:09.287739 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6173 11:04:09.290789 ===================================
6174 11:04:09.295035 LPDDR4 DRAM CONFIGURATION
6175 11:04:09.297880 ===================================
6176 11:04:09.297956 EX_ROW_EN[0] = 0x10
6177 11:04:09.301046 EX_ROW_EN[1] = 0x0
6178 11:04:09.301159 LP4Y_EN = 0x0
6179 11:04:09.304188 WORK_FSP = 0x0
6180 11:04:09.304304 WL = 0x2
6181 11:04:09.307757 RL = 0x2
6182 11:04:09.307848 BL = 0x2
6183 11:04:09.311219 RPST = 0x0
6184 11:04:09.311295 RD_PRE = 0x0
6185 11:04:09.314288 WR_PRE = 0x1
6186 11:04:09.314363 WR_PST = 0x0
6187 11:04:09.317903 DBI_WR = 0x0
6188 11:04:09.317979 DBI_RD = 0x0
6189 11:04:09.321157 OTF = 0x1
6190 11:04:09.324178 ===================================
6191 11:04:09.331769 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6192 11:04:09.334454 nWR fixed to 30
6193 11:04:09.338135 [ModeRegInit_LP4] CH0 RK0
6194 11:04:09.338210 [ModeRegInit_LP4] CH0 RK1
6195 11:04:09.341146 [ModeRegInit_LP4] CH1 RK0
6196 11:04:09.344390 [ModeRegInit_LP4] CH1 RK1
6197 11:04:09.344465 match AC timing 19
6198 11:04:09.351157 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6199 11:04:09.354597 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6200 11:04:09.357748 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6201 11:04:09.364584 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6202 11:04:09.367780 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6203 11:04:09.367859 ==
6204 11:04:09.371147 Dram Type= 6, Freq= 0, CH_0, rank 0
6205 11:04:09.375017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6206 11:04:09.375094 ==
6207 11:04:09.381645 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6208 11:04:09.388534 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6209 11:04:09.388610 [CA 0] Center 36 (8~64) winsize 57
6210 11:04:09.391356 [CA 1] Center 36 (8~64) winsize 57
6211 11:04:09.395183 [CA 2] Center 36 (8~64) winsize 57
6212 11:04:09.398167 [CA 3] Center 36 (8~64) winsize 57
6213 11:04:09.401670 [CA 4] Center 36 (8~64) winsize 57
6214 11:04:09.404560 [CA 5] Center 36 (8~64) winsize 57
6215 11:04:09.404635
6216 11:04:09.407919 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6217 11:04:09.407995
6218 11:04:09.411375 [CATrainingPosCal] consider 1 rank data
6219 11:04:09.415352 u2DelayCellTimex100 = 270/100 ps
6220 11:04:09.418477 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 11:04:09.422033 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 11:04:09.425229 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 11:04:09.431732 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 11:04:09.435662 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 11:04:09.438398 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 11:04:09.438474
6227 11:04:09.441702 CA PerBit enable=1, Macro0, CA PI delay=36
6228 11:04:09.441777
6229 11:04:09.444997 [CBTSetCACLKResult] CA Dly = 36
6230 11:04:09.445072 CS Dly: 1 (0~32)
6231 11:04:09.445169 ==
6232 11:04:09.448287 Dram Type= 6, Freq= 0, CH_0, rank 1
6233 11:04:09.455067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6234 11:04:09.455143 ==
6235 11:04:09.458219 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6236 11:04:09.465605 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6237 11:04:09.468115 [CA 0] Center 36 (8~64) winsize 57
6238 11:04:09.471607 [CA 1] Center 36 (8~64) winsize 57
6239 11:04:09.474744 [CA 2] Center 36 (8~64) winsize 57
6240 11:04:09.478038 [CA 3] Center 36 (8~64) winsize 57
6241 11:04:09.481322 [CA 4] Center 36 (8~64) winsize 57
6242 11:04:09.484670 [CA 5] Center 36 (8~64) winsize 57
6243 11:04:09.484746
6244 11:04:09.488711 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6245 11:04:09.488800
6246 11:04:09.491665 [CATrainingPosCal] consider 2 rank data
6247 11:04:09.494629 u2DelayCellTimex100 = 270/100 ps
6248 11:04:09.498220 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 11:04:09.501572 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 11:04:09.504966 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 11:04:09.508243 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 11:04:09.511890 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 11:04:09.515066 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 11:04:09.515141
6255 11:04:09.521533 CA PerBit enable=1, Macro0, CA PI delay=36
6256 11:04:09.521608
6257 11:04:09.521708 [CBTSetCACLKResult] CA Dly = 36
6258 11:04:09.525005 CS Dly: 1 (0~32)
6259 11:04:09.525082
6260 11:04:09.528498 ----->DramcWriteLeveling(PI) begin...
6261 11:04:09.528575 ==
6262 11:04:09.531935 Dram Type= 6, Freq= 0, CH_0, rank 0
6263 11:04:09.535686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6264 11:04:09.535763 ==
6265 11:04:09.538299 Write leveling (Byte 0): 40 => 8
6266 11:04:09.541566 Write leveling (Byte 1): 32 => 0
6267 11:04:09.545730 DramcWriteLeveling(PI) end<-----
6268 11:04:09.545806
6269 11:04:09.545868 ==
6270 11:04:09.548541 Dram Type= 6, Freq= 0, CH_0, rank 0
6271 11:04:09.551510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6272 11:04:09.551587 ==
6273 11:04:09.555342 [Gating] SW mode calibration
6274 11:04:09.561696 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6275 11:04:09.568332 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6276 11:04:09.572018 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6277 11:04:09.574926 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6278 11:04:09.581886 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 11:04:09.585297 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6280 11:04:09.589071 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 11:04:09.594978 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 11:04:09.598296 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 11:04:09.601576 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 11:04:09.608488 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6285 11:04:09.611657 Total UI for P1: 0, mck2ui 16
6286 11:04:09.614904 best dqsien dly found for B0: ( 0, 14, 24)
6287 11:04:09.615000 Total UI for P1: 0, mck2ui 16
6288 11:04:09.621768 best dqsien dly found for B1: ( 0, 14, 24)
6289 11:04:09.625212 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6290 11:04:09.628293 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6291 11:04:09.628387
6292 11:04:09.631918 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6293 11:04:09.635023 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6294 11:04:09.639018 [Gating] SW calibration Done
6295 11:04:09.639116 ==
6296 11:04:09.642089 Dram Type= 6, Freq= 0, CH_0, rank 0
6297 11:04:09.645195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6298 11:04:09.645293 ==
6299 11:04:09.648821 RX Vref Scan: 0
6300 11:04:09.648916
6301 11:04:09.649001 RX Vref 0 -> 0, step: 1
6302 11:04:09.649083
6303 11:04:09.651677 RX Delay -410 -> 252, step: 16
6304 11:04:09.658692 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6305 11:04:09.661940 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6306 11:04:09.665025 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6307 11:04:09.668720 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6308 11:04:09.675195 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6309 11:04:09.678795 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6310 11:04:09.681780 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6311 11:04:09.685308 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6312 11:04:09.691738 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6313 11:04:09.695101 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6314 11:04:09.698406 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6315 11:04:09.701852 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6316 11:04:09.708499 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6317 11:04:09.712042 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6318 11:04:09.715383 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6319 11:04:09.718679 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6320 11:04:09.718769 ==
6321 11:04:09.721980 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 11:04:09.728665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 11:04:09.728742 ==
6324 11:04:09.728800 DQS Delay:
6325 11:04:09.732064 DQS0 = 43, DQS1 = 51
6326 11:04:09.732138 DQM Delay:
6327 11:04:09.735346 DQM0 = 14, DQM1 = 11
6328 11:04:09.735421 DQ Delay:
6329 11:04:09.738661 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =8
6330 11:04:09.741874 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6331 11:04:09.741964 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6332 11:04:09.745344 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6333 11:04:09.749003
6334 11:04:09.749099
6335 11:04:09.749202 ==
6336 11:04:09.753230 Dram Type= 6, Freq= 0, CH_0, rank 0
6337 11:04:09.755103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 11:04:09.755197 ==
6339 11:04:09.755279
6340 11:04:09.755363
6341 11:04:09.758885 TX Vref Scan disable
6342 11:04:09.758980 == TX Byte 0 ==
6343 11:04:09.762180 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6344 11:04:09.769038 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6345 11:04:09.769171 == TX Byte 1 ==
6346 11:04:09.772010 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6347 11:04:09.778487 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6348 11:04:09.778583 ==
6349 11:04:09.781813 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 11:04:09.785497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 11:04:09.785592 ==
6352 11:04:09.785676
6353 11:04:09.785760
6354 11:04:09.788959 TX Vref Scan disable
6355 11:04:09.789056 == TX Byte 0 ==
6356 11:04:09.795556 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6357 11:04:09.798930 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6358 11:04:09.799005 == TX Byte 1 ==
6359 11:04:09.801949 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6360 11:04:09.808944 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6361 11:04:09.809019
6362 11:04:09.809078 [DATLAT]
6363 11:04:09.812074 Freq=400, CH0 RK0
6364 11:04:09.812149
6365 11:04:09.812207 DATLAT Default: 0xf
6366 11:04:09.815399 0, 0xFFFF, sum = 0
6367 11:04:09.815475 1, 0xFFFF, sum = 0
6368 11:04:09.818823 2, 0xFFFF, sum = 0
6369 11:04:09.818898 3, 0xFFFF, sum = 0
6370 11:04:09.822116 4, 0xFFFF, sum = 0
6371 11:04:09.822191 5, 0xFFFF, sum = 0
6372 11:04:09.825869 6, 0xFFFF, sum = 0
6373 11:04:09.825946 7, 0xFFFF, sum = 0
6374 11:04:09.828849 8, 0xFFFF, sum = 0
6375 11:04:09.828924 9, 0xFFFF, sum = 0
6376 11:04:09.832009 10, 0xFFFF, sum = 0
6377 11:04:09.832086 11, 0xFFFF, sum = 0
6378 11:04:09.835449 12, 0xFFFF, sum = 0
6379 11:04:09.835525 13, 0x0, sum = 1
6380 11:04:09.838794 14, 0x0, sum = 2
6381 11:04:09.838870 15, 0x0, sum = 3
6382 11:04:09.842065 16, 0x0, sum = 4
6383 11:04:09.842179 best_step = 14
6384 11:04:09.842237
6385 11:04:09.842291 ==
6386 11:04:09.845269 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 11:04:09.851864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 11:04:09.851941 ==
6389 11:04:09.852000 RX Vref Scan: 1
6390 11:04:09.852054
6391 11:04:09.855732 RX Vref 0 -> 0, step: 1
6392 11:04:09.855806
6393 11:04:09.858758 RX Delay -343 -> 252, step: 8
6394 11:04:09.858833
6395 11:04:09.862015 Set Vref, RX VrefLevel [Byte0]: 52
6396 11:04:09.865804 [Byte1]: 51
6397 11:04:09.865879
6398 11:04:09.868805 Final RX Vref Byte 0 = 52 to rank0
6399 11:04:09.872531 Final RX Vref Byte 1 = 51 to rank0
6400 11:04:09.875675 Final RX Vref Byte 0 = 52 to rank1
6401 11:04:09.878821 Final RX Vref Byte 1 = 51 to rank1==
6402 11:04:09.882206 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 11:04:09.885417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 11:04:09.885492 ==
6405 11:04:09.889410 DQS Delay:
6406 11:04:09.889485 DQS0 = 44, DQS1 = 60
6407 11:04:09.891917 DQM Delay:
6408 11:04:09.891992 DQM0 = 11, DQM1 = 14
6409 11:04:09.892050 DQ Delay:
6410 11:04:09.895455 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6411 11:04:09.899518 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6412 11:04:09.902300 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6413 11:04:09.905736 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =28
6414 11:04:09.905810
6415 11:04:09.905870
6416 11:04:09.915636 [DQSOSCAuto] RK0, (LSB)MR18= 0x8d5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6417 11:04:09.915711 CH0 RK0: MR19=C0C, MR18=8D5D
6418 11:04:09.922407 CH0_RK0: MR19=0xC0C, MR18=0x8D5D, DQSOSC=392, MR23=63, INC=384, DEC=256
6419 11:04:09.922482 ==
6420 11:04:09.925927 Dram Type= 6, Freq= 0, CH_0, rank 1
6421 11:04:09.932269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 11:04:09.932344 ==
6423 11:04:09.935888 [Gating] SW mode calibration
6424 11:04:09.942519 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6425 11:04:09.945906 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6426 11:04:09.952342 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6427 11:04:09.955646 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6428 11:04:09.960596 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 11:04:09.962849 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6430 11:04:09.969259 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 11:04:09.972631 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 11:04:09.975921 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 11:04:09.982480 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 11:04:09.985822 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6435 11:04:09.989335 Total UI for P1: 0, mck2ui 16
6436 11:04:09.992728 best dqsien dly found for B0: ( 0, 14, 24)
6437 11:04:09.995899 Total UI for P1: 0, mck2ui 16
6438 11:04:09.999707 best dqsien dly found for B1: ( 0, 14, 24)
6439 11:04:10.002574 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6440 11:04:10.005796 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6441 11:04:10.005903
6442 11:04:10.009719 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6443 11:04:10.012470 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6444 11:04:10.015707 [Gating] SW calibration Done
6445 11:04:10.015804 ==
6446 11:04:10.019349 Dram Type= 6, Freq= 0, CH_0, rank 1
6447 11:04:10.026149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 11:04:10.026242 ==
6449 11:04:10.026316 RX Vref Scan: 0
6450 11:04:10.026404
6451 11:04:10.029353 RX Vref 0 -> 0, step: 1
6452 11:04:10.029446
6453 11:04:10.032996 RX Delay -410 -> 252, step: 16
6454 11:04:10.036272 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6455 11:04:10.039484 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6456 11:04:10.042305 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6457 11:04:10.049797 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6458 11:04:10.052597 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6459 11:04:10.055865 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6460 11:04:10.059293 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6461 11:04:10.065659 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6462 11:04:10.069137 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6463 11:04:10.072391 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6464 11:04:10.075677 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6465 11:04:10.082441 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6466 11:04:10.085904 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6467 11:04:10.089480 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6468 11:04:10.092751 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6469 11:04:10.099272 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6470 11:04:10.099348 ==
6471 11:04:10.102819 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 11:04:10.106546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 11:04:10.106621 ==
6474 11:04:10.106680 DQS Delay:
6475 11:04:10.109382 DQS0 = 51, DQS1 = 51
6476 11:04:10.109457 DQM Delay:
6477 11:04:10.112954 DQM0 = 18, DQM1 = 10
6478 11:04:10.113052 DQ Delay:
6479 11:04:10.116331 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6480 11:04:10.119269 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6481 11:04:10.122748 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6482 11:04:10.126047 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6483 11:04:10.126122
6484 11:04:10.126180
6485 11:04:10.126233 ==
6486 11:04:10.129917 Dram Type= 6, Freq= 0, CH_0, rank 1
6487 11:04:10.133241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6488 11:04:10.133334 ==
6489 11:04:10.133417
6490 11:04:10.133497
6491 11:04:10.136316 TX Vref Scan disable
6492 11:04:10.140224 == TX Byte 0 ==
6493 11:04:10.143171 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6494 11:04:10.146151 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6495 11:04:10.146226 == TX Byte 1 ==
6496 11:04:10.152639 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6497 11:04:10.156135 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6498 11:04:10.156234 ==
6499 11:04:10.159856 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 11:04:10.163450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 11:04:10.163526 ==
6502 11:04:10.163585
6503 11:04:10.163642
6504 11:04:10.166683 TX Vref Scan disable
6505 11:04:10.169932 == TX Byte 0 ==
6506 11:04:10.172922 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6507 11:04:10.176693 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6508 11:04:10.179710 == TX Byte 1 ==
6509 11:04:10.183422 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6510 11:04:10.186887 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6511 11:04:10.186962
6512 11:04:10.187021 [DATLAT]
6513 11:04:10.190201 Freq=400, CH0 RK1
6514 11:04:10.190277
6515 11:04:10.190335 DATLAT Default: 0xe
6516 11:04:10.192993 0, 0xFFFF, sum = 0
6517 11:04:10.193125 1, 0xFFFF, sum = 0
6518 11:04:10.196036 2, 0xFFFF, sum = 0
6519 11:04:10.196159 3, 0xFFFF, sum = 0
6520 11:04:10.199758 4, 0xFFFF, sum = 0
6521 11:04:10.199859 5, 0xFFFF, sum = 0
6522 11:04:10.202930 6, 0xFFFF, sum = 0
6523 11:04:10.206524 7, 0xFFFF, sum = 0
6524 11:04:10.206601 8, 0xFFFF, sum = 0
6525 11:04:10.210238 9, 0xFFFF, sum = 0
6526 11:04:10.210328 10, 0xFFFF, sum = 0
6527 11:04:10.212893 11, 0xFFFF, sum = 0
6528 11:04:10.212993 12, 0xFFFF, sum = 0
6529 11:04:10.216445 13, 0x0, sum = 1
6530 11:04:10.216521 14, 0x0, sum = 2
6531 11:04:10.219904 15, 0x0, sum = 3
6532 11:04:10.219980 16, 0x0, sum = 4
6533 11:04:10.220040 best_step = 14
6534 11:04:10.222875
6535 11:04:10.222948 ==
6536 11:04:10.226068 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 11:04:10.229513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 11:04:10.229588 ==
6539 11:04:10.229647 RX Vref Scan: 0
6540 11:04:10.229702
6541 11:04:10.232760 RX Vref 0 -> 0, step: 1
6542 11:04:10.232835
6543 11:04:10.236082 RX Delay -343 -> 252, step: 8
6544 11:04:10.243525 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6545 11:04:10.246614 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6546 11:04:10.250232 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6547 11:04:10.253437 iDelay=217, Bit 3, Center -32 (-271 ~ 208) 480
6548 11:04:10.260207 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6549 11:04:10.263733 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6550 11:04:10.266998 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6551 11:04:10.270206 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6552 11:04:10.276593 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6553 11:04:10.280277 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6554 11:04:10.284026 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6555 11:04:10.286862 iDelay=217, Bit 11, Center -52 (-287 ~ 184) 472
6556 11:04:10.293411 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6557 11:04:10.297000 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6558 11:04:10.300282 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6559 11:04:10.303736 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6560 11:04:10.306767 ==
6561 11:04:10.310560 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 11:04:10.313345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 11:04:10.313420 ==
6564 11:04:10.313479 DQS Delay:
6565 11:04:10.317062 DQS0 = 48, DQS1 = 56
6566 11:04:10.317174 DQM Delay:
6567 11:04:10.319915 DQM0 = 13, DQM1 = 11
6568 11:04:10.319990 DQ Delay:
6569 11:04:10.323411 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =16
6570 11:04:10.326516 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =16
6571 11:04:10.330079 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6572 11:04:10.333386 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =20
6573 11:04:10.333461
6574 11:04:10.333518
6575 11:04:10.339802 [DQSOSCAuto] RK1, (LSB)MR18= 0x996d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6576 11:04:10.343258 CH0 RK1: MR19=C0C, MR18=996D
6577 11:04:10.349759 CH0_RK1: MR19=0xC0C, MR18=0x996D, DQSOSC=390, MR23=63, INC=388, DEC=258
6578 11:04:10.353556 [RxdqsGatingPostProcess] freq 400
6579 11:04:10.356804 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6580 11:04:10.359717 best DQS0 dly(2T, 0.5T) = (0, 10)
6581 11:04:10.363224 best DQS1 dly(2T, 0.5T) = (0, 10)
6582 11:04:10.366679 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6583 11:04:10.370431 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6584 11:04:10.373473 best DQS0 dly(2T, 0.5T) = (0, 10)
6585 11:04:10.376340 best DQS1 dly(2T, 0.5T) = (0, 10)
6586 11:04:10.379916 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6587 11:04:10.383254 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6588 11:04:10.386886 Pre-setting of DQS Precalculation
6589 11:04:10.390474 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6590 11:04:10.393232 ==
6591 11:04:10.393306 Dram Type= 6, Freq= 0, CH_1, rank 0
6592 11:04:10.399905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6593 11:04:10.399980 ==
6594 11:04:10.403403 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6595 11:04:10.409948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6596 11:04:10.413607 [CA 0] Center 36 (8~64) winsize 57
6597 11:04:10.416881 [CA 1] Center 36 (8~64) winsize 57
6598 11:04:10.419832 [CA 2] Center 36 (8~64) winsize 57
6599 11:04:10.423514 [CA 3] Center 36 (8~64) winsize 57
6600 11:04:10.426565 [CA 4] Center 36 (8~64) winsize 57
6601 11:04:10.430228 [CA 5] Center 36 (8~64) winsize 57
6602 11:04:10.430302
6603 11:04:10.433343 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6604 11:04:10.433449
6605 11:04:10.436365 [CATrainingPosCal] consider 1 rank data
6606 11:04:10.439859 u2DelayCellTimex100 = 270/100 ps
6607 11:04:10.443242 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 11:04:10.446569 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 11:04:10.449899 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 11:04:10.453002 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 11:04:10.456665 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 11:04:10.459634 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 11:04:10.463253
6614 11:04:10.466985 CA PerBit enable=1, Macro0, CA PI delay=36
6615 11:04:10.467060
6616 11:04:10.469757 [CBTSetCACLKResult] CA Dly = 36
6617 11:04:10.469831 CS Dly: 1 (0~32)
6618 11:04:10.469890 ==
6619 11:04:10.473897 Dram Type= 6, Freq= 0, CH_1, rank 1
6620 11:04:10.476781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6621 11:04:10.476857 ==
6622 11:04:10.483775 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6623 11:04:10.490050 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6624 11:04:10.493403 [CA 0] Center 36 (8~64) winsize 57
6625 11:04:10.497429 [CA 1] Center 36 (8~64) winsize 57
6626 11:04:10.500398 [CA 2] Center 36 (8~64) winsize 57
6627 11:04:10.503374 [CA 3] Center 36 (8~64) winsize 57
6628 11:04:10.503449 [CA 4] Center 36 (8~64) winsize 57
6629 11:04:10.506888 [CA 5] Center 36 (8~64) winsize 57
6630 11:04:10.506964
6631 11:04:10.513340 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6632 11:04:10.513417
6633 11:04:10.517375 [CATrainingPosCal] consider 2 rank data
6634 11:04:10.520154 u2DelayCellTimex100 = 270/100 ps
6635 11:04:10.523450 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 11:04:10.526578 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 11:04:10.529900 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 11:04:10.533621 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 11:04:10.536917 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 11:04:10.540514 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 11:04:10.540616
6642 11:04:10.543553 CA PerBit enable=1, Macro0, CA PI delay=36
6643 11:04:10.543646
6644 11:04:10.546609 [CBTSetCACLKResult] CA Dly = 36
6645 11:04:10.550241 CS Dly: 1 (0~32)
6646 11:04:10.550334
6647 11:04:10.553392 ----->DramcWriteLeveling(PI) begin...
6648 11:04:10.553484 ==
6649 11:04:10.557236 Dram Type= 6, Freq= 0, CH_1, rank 0
6650 11:04:10.560650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 11:04:10.560741 ==
6652 11:04:10.563644 Write leveling (Byte 0): 40 => 8
6653 11:04:10.566717 Write leveling (Byte 1): 40 => 8
6654 11:04:10.570069 DramcWriteLeveling(PI) end<-----
6655 11:04:10.570161
6656 11:04:10.570246 ==
6657 11:04:10.573455 Dram Type= 6, Freq= 0, CH_1, rank 0
6658 11:04:10.577154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 11:04:10.577267 ==
6660 11:04:10.580092 [Gating] SW mode calibration
6661 11:04:10.586962 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6662 11:04:10.593647 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6663 11:04:10.596845 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6664 11:04:10.600695 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6665 11:04:10.606911 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 11:04:10.610716 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6667 11:04:10.613774 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 11:04:10.616996 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 11:04:10.623422 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 11:04:10.626767 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 11:04:10.630738 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6672 11:04:10.633485 Total UI for P1: 0, mck2ui 16
6673 11:04:10.636944 best dqsien dly found for B0: ( 0, 14, 24)
6674 11:04:10.640130 Total UI for P1: 0, mck2ui 16
6675 11:04:10.644118 best dqsien dly found for B1: ( 0, 14, 24)
6676 11:04:10.647200 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6677 11:04:10.650294 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6678 11:04:10.650370
6679 11:04:10.657249 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6680 11:04:10.660455 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6681 11:04:10.663524 [Gating] SW calibration Done
6682 11:04:10.663601 ==
6683 11:04:10.667276 Dram Type= 6, Freq= 0, CH_1, rank 0
6684 11:04:10.670272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6685 11:04:10.670349 ==
6686 11:04:10.670408 RX Vref Scan: 0
6687 11:04:10.670464
6688 11:04:10.673977 RX Vref 0 -> 0, step: 1
6689 11:04:10.674053
6690 11:04:10.676985 RX Delay -410 -> 252, step: 16
6691 11:04:10.680563 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6692 11:04:10.683679 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6693 11:04:10.690898 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6694 11:04:10.693975 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6695 11:04:10.697253 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6696 11:04:10.700865 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6697 11:04:10.707471 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6698 11:04:10.710677 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6699 11:04:10.714132 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6700 11:04:10.717059 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6701 11:04:10.724041 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6702 11:04:10.727384 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6703 11:04:10.730786 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6704 11:04:10.734249 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6705 11:04:10.741225 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6706 11:04:10.744107 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6707 11:04:10.744182 ==
6708 11:04:10.747571 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 11:04:10.751004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 11:04:10.751079 ==
6711 11:04:10.754184 DQS Delay:
6712 11:04:10.754259 DQS0 = 51, DQS1 = 59
6713 11:04:10.757542 DQM Delay:
6714 11:04:10.757635 DQM0 = 18, DQM1 = 16
6715 11:04:10.757719 DQ Delay:
6716 11:04:10.760707 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6717 11:04:10.764332 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6718 11:04:10.767978 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6719 11:04:10.771404 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6720 11:04:10.771494
6721 11:04:10.771579
6722 11:04:10.771662 ==
6723 11:04:10.774473 Dram Type= 6, Freq= 0, CH_1, rank 0
6724 11:04:10.780741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 11:04:10.780821 ==
6726 11:04:10.780900
6727 11:04:10.780991
6728 11:04:10.781079 TX Vref Scan disable
6729 11:04:10.784151 == TX Byte 0 ==
6730 11:04:10.787906 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6731 11:04:10.790877 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6732 11:04:10.794220 == TX Byte 1 ==
6733 11:04:10.797926 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6734 11:04:10.801041 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6735 11:04:10.801124 ==
6736 11:04:10.803851 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 11:04:10.810709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 11:04:10.810788 ==
6739 11:04:10.810865
6740 11:04:10.810937
6741 11:04:10.811008 TX Vref Scan disable
6742 11:04:10.814283 == TX Byte 0 ==
6743 11:04:10.817430 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6744 11:04:10.820879 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6745 11:04:10.824416 == TX Byte 1 ==
6746 11:04:10.828289 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6747 11:04:10.831198 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6748 11:04:10.831276
6749 11:04:10.834528 [DATLAT]
6750 11:04:10.834606 Freq=400, CH1 RK0
6751 11:04:10.834684
6752 11:04:10.838206 DATLAT Default: 0xf
6753 11:04:10.838284 0, 0xFFFF, sum = 0
6754 11:04:10.841042 1, 0xFFFF, sum = 0
6755 11:04:10.841142 2, 0xFFFF, sum = 0
6756 11:04:10.844101 3, 0xFFFF, sum = 0
6757 11:04:10.844180 4, 0xFFFF, sum = 0
6758 11:04:10.847742 5, 0xFFFF, sum = 0
6759 11:04:10.847822 6, 0xFFFF, sum = 0
6760 11:04:10.851023 7, 0xFFFF, sum = 0
6761 11:04:10.851103 8, 0xFFFF, sum = 0
6762 11:04:10.854716 9, 0xFFFF, sum = 0
6763 11:04:10.854795 10, 0xFFFF, sum = 0
6764 11:04:10.857517 11, 0xFFFF, sum = 0
6765 11:04:10.861272 12, 0xFFFF, sum = 0
6766 11:04:10.861352 13, 0x0, sum = 1
6767 11:04:10.861431 14, 0x0, sum = 2
6768 11:04:10.864012 15, 0x0, sum = 3
6769 11:04:10.864091 16, 0x0, sum = 4
6770 11:04:10.867992 best_step = 14
6771 11:04:10.868070
6772 11:04:10.868155 ==
6773 11:04:10.870626 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 11:04:10.874495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 11:04:10.874574 ==
6776 11:04:10.877602 RX Vref Scan: 1
6777 11:04:10.877679
6778 11:04:10.877757 RX Vref 0 -> 0, step: 1
6779 11:04:10.877867
6780 11:04:10.880765 RX Delay -359 -> 252, step: 8
6781 11:04:10.880854
6782 11:04:10.884136 Set Vref, RX VrefLevel [Byte0]: 55
6783 11:04:10.887567 [Byte1]: 47
6784 11:04:10.892129
6785 11:04:10.895950 Final RX Vref Byte 0 = 55 to rank0
6786 11:04:10.896029 Final RX Vref Byte 1 = 47 to rank0
6787 11:04:10.899202 Final RX Vref Byte 0 = 55 to rank1
6788 11:04:10.902798 Final RX Vref Byte 1 = 47 to rank1==
6789 11:04:10.905438 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 11:04:10.912739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 11:04:10.912830 ==
6792 11:04:10.912933 DQS Delay:
6793 11:04:10.915349 DQS0 = 48, DQS1 = 60
6794 11:04:10.915427 DQM Delay:
6795 11:04:10.915504 DQM0 = 12, DQM1 = 12
6796 11:04:10.918779 DQ Delay:
6797 11:04:10.922138 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6798 11:04:10.922219 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6799 11:04:10.925500 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6800 11:04:10.928566 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =16
6801 11:04:10.928644
6802 11:04:10.932489
6803 11:04:10.938712 [DQSOSCAuto] RK0, (LSB)MR18= 0x983e, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
6804 11:04:10.942079 CH1 RK0: MR19=C0C, MR18=983E
6805 11:04:10.948777 CH1_RK0: MR19=0xC0C, MR18=0x983E, DQSOSC=390, MR23=63, INC=388, DEC=258
6806 11:04:10.948852 ==
6807 11:04:10.951803 Dram Type= 6, Freq= 0, CH_1, rank 1
6808 11:04:10.955261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 11:04:10.955337 ==
6810 11:04:10.958716 [Gating] SW mode calibration
6811 11:04:10.965155 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6812 11:04:10.972216 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6813 11:04:10.975173 0 11 0 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
6814 11:04:10.978667 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6815 11:04:10.985653 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 11:04:10.988633 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6817 11:04:10.992032 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 11:04:10.995277 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 11:04:11.002281 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 11:04:11.005394 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 11:04:11.008794 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6822 11:04:11.012101 Total UI for P1: 0, mck2ui 16
6823 11:04:11.015156 best dqsien dly found for B0: ( 0, 14, 24)
6824 11:04:11.018631 Total UI for P1: 0, mck2ui 16
6825 11:04:11.022323 best dqsien dly found for B1: ( 0, 14, 24)
6826 11:04:11.025492 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6827 11:04:11.029451 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6828 11:04:11.029529
6829 11:04:11.035688 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6830 11:04:11.039299 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6831 11:04:11.042052 [Gating] SW calibration Done
6832 11:04:11.042163 ==
6833 11:04:11.045700 Dram Type= 6, Freq= 0, CH_1, rank 1
6834 11:04:11.048782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 11:04:11.048883 ==
6836 11:04:11.048978 RX Vref Scan: 0
6837 11:04:11.049069
6838 11:04:11.052380 RX Vref 0 -> 0, step: 1
6839 11:04:11.052448
6840 11:04:11.055650 RX Delay -410 -> 252, step: 16
6841 11:04:11.059166 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6842 11:04:11.062502 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6843 11:04:11.069001 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6844 11:04:11.072271 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6845 11:04:11.075500 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6846 11:04:11.078935 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6847 11:04:11.085461 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6848 11:04:11.088809 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6849 11:04:11.092798 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6850 11:04:11.096115 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6851 11:04:11.102472 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6852 11:04:11.105378 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6853 11:04:11.109263 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6854 11:04:11.112489 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6855 11:04:11.119450 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6856 11:04:11.122158 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6857 11:04:11.122236 ==
6858 11:04:11.125666 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 11:04:11.128741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 11:04:11.128820 ==
6861 11:04:11.132316 DQS Delay:
6862 11:04:11.132400 DQS0 = 43, DQS1 = 51
6863 11:04:11.135830 DQM Delay:
6864 11:04:11.135908 DQM0 = 10, DQM1 = 10
6865 11:04:11.135986 DQ Delay:
6866 11:04:11.139202 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6867 11:04:11.143090 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6868 11:04:11.145507 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6869 11:04:11.149042 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6870 11:04:11.149142
6871 11:04:11.149233
6872 11:04:11.149306 ==
6873 11:04:11.152319 Dram Type= 6, Freq= 0, CH_1, rank 1
6874 11:04:11.155753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 11:04:11.159029 ==
6876 11:04:11.159107
6877 11:04:11.159184
6878 11:04:11.159256 TX Vref Scan disable
6879 11:04:11.162257 == TX Byte 0 ==
6880 11:04:11.165611 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6881 11:04:11.169011 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6882 11:04:11.172810 == TX Byte 1 ==
6883 11:04:11.175946 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6884 11:04:11.179079 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6885 11:04:11.179158 ==
6886 11:04:11.182346 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 11:04:11.188853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 11:04:11.188932 ==
6889 11:04:11.189028
6890 11:04:11.189123
6891 11:04:11.189234 TX Vref Scan disable
6892 11:04:11.192639 == TX Byte 0 ==
6893 11:04:11.195673 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6894 11:04:11.199096 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6895 11:04:11.202716 == TX Byte 1 ==
6896 11:04:11.205695 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6897 11:04:11.208884 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6898 11:04:11.208962
6899 11:04:11.212179 [DATLAT]
6900 11:04:11.212304 Freq=400, CH1 RK1
6901 11:04:11.212398
6902 11:04:11.215908 DATLAT Default: 0xe
6903 11:04:11.215986 0, 0xFFFF, sum = 0
6904 11:04:11.218972 1, 0xFFFF, sum = 0
6905 11:04:11.219052 2, 0xFFFF, sum = 0
6906 11:04:11.222253 3, 0xFFFF, sum = 0
6907 11:04:11.222351 4, 0xFFFF, sum = 0
6908 11:04:11.225705 5, 0xFFFF, sum = 0
6909 11:04:11.225781 6, 0xFFFF, sum = 0
6910 11:04:11.229283 7, 0xFFFF, sum = 0
6911 11:04:11.229361 8, 0xFFFF, sum = 0
6912 11:04:11.232176 9, 0xFFFF, sum = 0
6913 11:04:11.232273 10, 0xFFFF, sum = 0
6914 11:04:11.235954 11, 0xFFFF, sum = 0
6915 11:04:11.239028 12, 0xFFFF, sum = 0
6916 11:04:11.239126 13, 0x0, sum = 1
6917 11:04:11.239205 14, 0x0, sum = 2
6918 11:04:11.242520 15, 0x0, sum = 3
6919 11:04:11.242626 16, 0x0, sum = 4
6920 11:04:11.245800 best_step = 14
6921 11:04:11.245878
6922 11:04:11.245954 ==
6923 11:04:11.249538 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 11:04:11.252411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 11:04:11.252516 ==
6926 11:04:11.255909 RX Vref Scan: 0
6927 11:04:11.255987
6928 11:04:11.256064 RX Vref 0 -> 0, step: 1
6929 11:04:11.256155
6930 11:04:11.259694 RX Delay -343 -> 252, step: 8
6931 11:04:11.267395 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6932 11:04:11.270651 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6933 11:04:11.274054 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6934 11:04:11.277716 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6935 11:04:11.284557 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6936 11:04:11.287506 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6937 11:04:11.290744 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6938 11:04:11.294008 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6939 11:04:11.300507 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6940 11:04:11.303877 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6941 11:04:11.307364 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6942 11:04:11.310437 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6943 11:04:11.317291 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6944 11:04:11.320464 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6945 11:04:11.323891 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6946 11:04:11.327313 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6947 11:04:11.330854 ==
6948 11:04:11.333941 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 11:04:11.337107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 11:04:11.337222 ==
6951 11:04:11.337297 DQS Delay:
6952 11:04:11.341100 DQS0 = 52, DQS1 = 60
6953 11:04:11.341199 DQM Delay:
6954 11:04:11.343751 DQM0 = 12, DQM1 = 13
6955 11:04:11.343827 DQ Delay:
6956 11:04:11.347218 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6957 11:04:11.350749 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6958 11:04:11.353981 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6959 11:04:11.357584 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6960 11:04:11.357661
6961 11:04:11.357720
6962 11:04:11.364075 [DQSOSCAuto] RK1, (LSB)MR18= 0x7f95, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 393 ps
6963 11:04:11.367491 CH1 RK1: MR19=C0C, MR18=7F95
6964 11:04:11.374346 CH1_RK1: MR19=0xC0C, MR18=0x7F95, DQSOSC=391, MR23=63, INC=386, DEC=257
6965 11:04:11.377294 [RxdqsGatingPostProcess] freq 400
6966 11:04:11.380691 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6967 11:04:11.384164 best DQS0 dly(2T, 0.5T) = (0, 10)
6968 11:04:11.387361 best DQS1 dly(2T, 0.5T) = (0, 10)
6969 11:04:11.390526 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6970 11:04:11.394001 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6971 11:04:11.397787 best DQS0 dly(2T, 0.5T) = (0, 10)
6972 11:04:11.401445 best DQS1 dly(2T, 0.5T) = (0, 10)
6973 11:04:11.404103 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6974 11:04:11.407282 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6975 11:04:11.411262 Pre-setting of DQS Precalculation
6976 11:04:11.414229 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6977 11:04:11.421364 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6978 11:04:11.430689 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6979 11:04:11.430766
6980 11:04:11.430826
6981 11:04:11.434428 [Calibration Summary] 800 Mbps
6982 11:04:11.434503 CH 0, Rank 0
6983 11:04:11.437477 SW Impedance : PASS
6984 11:04:11.437570 DUTY Scan : NO K
6985 11:04:11.441104 ZQ Calibration : PASS
6986 11:04:11.441220 Jitter Meter : NO K
6987 11:04:11.444286 CBT Training : PASS
6988 11:04:11.447915 Write leveling : PASS
6989 11:04:11.447991 RX DQS gating : PASS
6990 11:04:11.451015 RX DQ/DQS(RDDQC) : PASS
6991 11:04:11.454169 TX DQ/DQS : PASS
6992 11:04:11.454244 RX DATLAT : PASS
6993 11:04:11.458126 RX DQ/DQS(Engine): PASS
6994 11:04:11.461728 TX OE : NO K
6995 11:04:11.461804 All Pass.
6996 11:04:11.461862
6997 11:04:11.461916 CH 0, Rank 1
6998 11:04:11.464639 SW Impedance : PASS
6999 11:04:11.467358 DUTY Scan : NO K
7000 11:04:11.467433 ZQ Calibration : PASS
7001 11:04:11.471029 Jitter Meter : NO K
7002 11:04:11.474178 CBT Training : PASS
7003 11:04:11.474253 Write leveling : NO K
7004 11:04:11.477690 RX DQS gating : PASS
7005 11:04:11.481380 RX DQ/DQS(RDDQC) : PASS
7006 11:04:11.481456 TX DQ/DQS : PASS
7007 11:04:11.484280 RX DATLAT : PASS
7008 11:04:11.484379 RX DQ/DQS(Engine): PASS
7009 11:04:11.487632 TX OE : NO K
7010 11:04:11.487708 All Pass.
7011 11:04:11.487767
7012 11:04:11.491331 CH 1, Rank 0
7013 11:04:11.491414 SW Impedance : PASS
7014 11:04:11.494279 DUTY Scan : NO K
7015 11:04:11.497450 ZQ Calibration : PASS
7016 11:04:11.497525 Jitter Meter : NO K
7017 11:04:11.500872 CBT Training : PASS
7018 11:04:11.505097 Write leveling : PASS
7019 11:04:11.505195 RX DQS gating : PASS
7020 11:04:11.507421 RX DQ/DQS(RDDQC) : PASS
7021 11:04:11.511060 TX DQ/DQS : PASS
7022 11:04:11.511136 RX DATLAT : PASS
7023 11:04:11.514563 RX DQ/DQS(Engine): PASS
7024 11:04:11.517888 TX OE : NO K
7025 11:04:11.517964 All Pass.
7026 11:04:11.518023
7027 11:04:11.518077 CH 1, Rank 1
7028 11:04:11.521056 SW Impedance : PASS
7029 11:04:11.524547 DUTY Scan : NO K
7030 11:04:11.524622 ZQ Calibration : PASS
7031 11:04:11.527549 Jitter Meter : NO K
7032 11:04:11.527648 CBT Training : PASS
7033 11:04:11.530881 Write leveling : NO K
7034 11:04:11.534173 RX DQS gating : PASS
7035 11:04:11.534250 RX DQ/DQS(RDDQC) : PASS
7036 11:04:11.537523 TX DQ/DQS : PASS
7037 11:04:11.541500 RX DATLAT : PASS
7038 11:04:11.541576 RX DQ/DQS(Engine): PASS
7039 11:04:11.544613 TX OE : NO K
7040 11:04:11.544688 All Pass.
7041 11:04:11.544748
7042 11:04:11.547954 DramC Write-DBI off
7043 11:04:11.551002 PER_BANK_REFRESH: Hybrid Mode
7044 11:04:11.551095 TX_TRACKING: ON
7045 11:04:11.560927 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7046 11:04:11.564957 [FAST_K] Save calibration result to emmc
7047 11:04:11.567725 dramc_set_vcore_voltage set vcore to 725000
7048 11:04:11.571022 Read voltage for 1600, 0
7049 11:04:11.571097 Vio18 = 0
7050 11:04:11.571156 Vcore = 725000
7051 11:04:11.574902 Vdram = 0
7052 11:04:11.574975 Vddq = 0
7053 11:04:11.575053 Vmddr = 0
7054 11:04:11.581168 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7055 11:04:11.584602 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7056 11:04:11.587807 MEM_TYPE=3, freq_sel=13
7057 11:04:11.591494 sv_algorithm_assistance_LP4_3733
7058 11:04:11.594372 ============ PULL DRAM RESETB DOWN ============
7059 11:04:11.598340 ========== PULL DRAM RESETB DOWN end =========
7060 11:04:11.604902 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7061 11:04:11.608215 ===================================
7062 11:04:11.608290 LPDDR4 DRAM CONFIGURATION
7063 11:04:11.611209 ===================================
7064 11:04:11.615136 EX_ROW_EN[0] = 0x0
7065 11:04:11.618796 EX_ROW_EN[1] = 0x0
7066 11:04:11.618880 LP4Y_EN = 0x0
7067 11:04:11.621226 WORK_FSP = 0x1
7068 11:04:11.621302 WL = 0x5
7069 11:04:11.624345 RL = 0x5
7070 11:04:11.624421 BL = 0x2
7071 11:04:11.628543 RPST = 0x0
7072 11:04:11.628639 RD_PRE = 0x0
7073 11:04:11.630944 WR_PRE = 0x1
7074 11:04:11.631044 WR_PST = 0x1
7075 11:04:11.634489 DBI_WR = 0x0
7076 11:04:11.634583 DBI_RD = 0x0
7077 11:04:11.638227 OTF = 0x1
7078 11:04:11.641344 ===================================
7079 11:04:11.644231 ===================================
7080 11:04:11.644313 ANA top config
7081 11:04:11.648182 ===================================
7082 11:04:11.651090 DLL_ASYNC_EN = 0
7083 11:04:11.654415 ALL_SLAVE_EN = 0
7084 11:04:11.654517 NEW_RANK_MODE = 1
7085 11:04:11.657953 DLL_IDLE_MODE = 1
7086 11:04:11.661270 LP45_APHY_COMB_EN = 1
7087 11:04:11.664296 TX_ODT_DIS = 0
7088 11:04:11.668047 NEW_8X_MODE = 1
7089 11:04:11.670937 ===================================
7090 11:04:11.674714 ===================================
7091 11:04:11.674793 data_rate = 3200
7092 11:04:11.677856 CKR = 1
7093 11:04:11.681715 DQ_P2S_RATIO = 8
7094 11:04:11.684967 ===================================
7095 11:04:11.688308 CA_P2S_RATIO = 8
7096 11:04:11.691024 DQ_CA_OPEN = 0
7097 11:04:11.694438 DQ_SEMI_OPEN = 0
7098 11:04:11.694516 CA_SEMI_OPEN = 0
7099 11:04:11.698110 CA_FULL_RATE = 0
7100 11:04:11.701076 DQ_CKDIV4_EN = 0
7101 11:04:11.704338 CA_CKDIV4_EN = 0
7102 11:04:11.707800 CA_PREDIV_EN = 0
7103 11:04:11.711172 PH8_DLY = 12
7104 11:04:11.711303 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7105 11:04:11.715020 DQ_AAMCK_DIV = 4
7106 11:04:11.717870 CA_AAMCK_DIV = 4
7107 11:04:11.721306 CA_ADMCK_DIV = 4
7108 11:04:11.724774 DQ_TRACK_CA_EN = 0
7109 11:04:11.727944 CA_PICK = 1600
7110 11:04:11.728023 CA_MCKIO = 1600
7111 11:04:11.731989 MCKIO_SEMI = 0
7112 11:04:11.734758 PLL_FREQ = 3068
7113 11:04:11.737844 DQ_UI_PI_RATIO = 32
7114 11:04:11.741114 CA_UI_PI_RATIO = 0
7115 11:04:11.744712 ===================================
7116 11:04:11.747683 ===================================
7117 11:04:11.751252 memory_type:LPDDR4
7118 11:04:11.751326 GP_NUM : 10
7119 11:04:11.754772 SRAM_EN : 1
7120 11:04:11.754846 MD32_EN : 0
7121 11:04:11.758298 ===================================
7122 11:04:11.761512 [ANA_INIT] >>>>>>>>>>>>>>
7123 11:04:11.764455 <<<<<< [CONFIGURE PHASE]: ANA_TX
7124 11:04:11.768667 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7125 11:04:11.771407 ===================================
7126 11:04:11.774963 data_rate = 3200,PCW = 0X7600
7127 11:04:11.777961 ===================================
7128 11:04:11.781439 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7129 11:04:11.784785 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7130 11:04:11.792118 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7131 11:04:11.794460 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7132 11:04:11.798065 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7133 11:04:11.801379 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7134 11:04:11.805048 [ANA_INIT] flow start
7135 11:04:11.808571 [ANA_INIT] PLL >>>>>>>>
7136 11:04:11.808645 [ANA_INIT] PLL <<<<<<<<
7137 11:04:11.811208 [ANA_INIT] MIDPI >>>>>>>>
7138 11:04:11.814807 [ANA_INIT] MIDPI <<<<<<<<
7139 11:04:11.818121 [ANA_INIT] DLL >>>>>>>>
7140 11:04:11.818195 [ANA_INIT] DLL <<<<<<<<
7141 11:04:11.821398 [ANA_INIT] flow end
7142 11:04:11.824806 ============ LP4 DIFF to SE enter ============
7143 11:04:11.827985 ============ LP4 DIFF to SE exit ============
7144 11:04:11.832106 [ANA_INIT] <<<<<<<<<<<<<
7145 11:04:11.834653 [Flow] Enable top DCM control >>>>>
7146 11:04:11.837882 [Flow] Enable top DCM control <<<<<
7147 11:04:11.841838 Enable DLL master slave shuffle
7148 11:04:11.844644 ==============================================================
7149 11:04:11.848230 Gating Mode config
7150 11:04:11.854808 ==============================================================
7151 11:04:11.854883 Config description:
7152 11:04:11.865944 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7153 11:04:11.871677 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7154 11:04:11.878449 SELPH_MODE 0: By rank 1: By Phase
7155 11:04:11.881863 ==============================================================
7156 11:04:11.885449 GAT_TRACK_EN = 1
7157 11:04:11.888560 RX_GATING_MODE = 2
7158 11:04:11.891556 RX_GATING_TRACK_MODE = 2
7159 11:04:11.895003 SELPH_MODE = 1
7160 11:04:11.898555 PICG_EARLY_EN = 1
7161 11:04:11.901386 VALID_LAT_VALUE = 1
7162 11:04:11.905254 ==============================================================
7163 11:04:11.909241 Enter into Gating configuration >>>>
7164 11:04:11.911726 Exit from Gating configuration <<<<
7165 11:04:11.914971 Enter into DVFS_PRE_config >>>>>
7166 11:04:11.928074 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7167 11:04:11.928150 Exit from DVFS_PRE_config <<<<<
7168 11:04:11.932058 Enter into PICG configuration >>>>
7169 11:04:11.935010 Exit from PICG configuration <<<<
7170 11:04:11.938442 [RX_INPUT] configuration >>>>>
7171 11:04:11.941501 [RX_INPUT] configuration <<<<<
7172 11:04:11.948236 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7173 11:04:11.951692 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7174 11:04:11.958631 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7175 11:04:11.965031 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7176 11:04:11.971728 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7177 11:04:11.978803 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7178 11:04:11.982076 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7179 11:04:11.985379 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7180 11:04:11.988405 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7181 11:04:11.995281 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7182 11:04:11.998989 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7183 11:04:12.002417 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7184 11:04:12.005336 ===================================
7185 11:04:12.008580 LPDDR4 DRAM CONFIGURATION
7186 11:04:12.011582 ===================================
7187 11:04:12.011659 EX_ROW_EN[0] = 0x0
7188 11:04:12.015667 EX_ROW_EN[1] = 0x0
7189 11:04:12.015743 LP4Y_EN = 0x0
7190 11:04:12.018160 WORK_FSP = 0x1
7191 11:04:12.018236 WL = 0x5
7192 11:04:12.021655 RL = 0x5
7193 11:04:12.024957 BL = 0x2
7194 11:04:12.025032 RPST = 0x0
7195 11:04:12.028302 RD_PRE = 0x0
7196 11:04:12.028378 WR_PRE = 0x1
7197 11:04:12.031749 WR_PST = 0x1
7198 11:04:12.031824 DBI_WR = 0x0
7199 11:04:12.035616 DBI_RD = 0x0
7200 11:04:12.035692 OTF = 0x1
7201 11:04:12.038338 ===================================
7202 11:04:12.042106 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7203 11:04:12.048397 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7204 11:04:12.051619 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7205 11:04:12.055037 ===================================
7206 11:04:12.058532 LPDDR4 DRAM CONFIGURATION
7207 11:04:12.061662 ===================================
7208 11:04:12.061738 EX_ROW_EN[0] = 0x10
7209 11:04:12.065026 EX_ROW_EN[1] = 0x0
7210 11:04:12.065103 LP4Y_EN = 0x0
7211 11:04:12.068451 WORK_FSP = 0x1
7212 11:04:12.068526 WL = 0x5
7213 11:04:12.071858 RL = 0x5
7214 11:04:12.071932 BL = 0x2
7215 11:04:12.074885 RPST = 0x0
7216 11:04:12.074959 RD_PRE = 0x0
7217 11:04:12.078263 WR_PRE = 0x1
7218 11:04:12.078339 WR_PST = 0x1
7219 11:04:12.081834 DBI_WR = 0x0
7220 11:04:12.081908 DBI_RD = 0x0
7221 11:04:12.084939 OTF = 0x1
7222 11:04:12.088971 ===================================
7223 11:04:12.095424 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7224 11:04:12.095499 ==
7225 11:04:12.098469 Dram Type= 6, Freq= 0, CH_0, rank 0
7226 11:04:12.101844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7227 11:04:12.101922 ==
7228 11:04:12.105557 [Duty_Offset_Calibration]
7229 11:04:12.105633 B0:2 B1:-1 CA:1
7230 11:04:12.105692
7231 11:04:12.108491 [DutyScan_Calibration_Flow] k_type=0
7232 11:04:12.118617
7233 11:04:12.118693 ==CLK 0==
7234 11:04:12.122031 Final CLK duty delay cell = -4
7235 11:04:12.125088 [-4] MAX Duty = 5000%(X100), DQS PI = 6
7236 11:04:12.128544 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7237 11:04:12.132138 [-4] AVG Duty = 4922%(X100)
7238 11:04:12.132214
7239 11:04:12.135561 CH0 CLK Duty spec in!! Max-Min= 156%
7240 11:04:12.138484 [DutyScan_Calibration_Flow] ====Done====
7241 11:04:12.138560
7242 11:04:12.141708 [DutyScan_Calibration_Flow] k_type=1
7243 11:04:12.157795
7244 11:04:12.157870 ==DQS 0 ==
7245 11:04:12.161993 Final DQS duty delay cell = 0
7246 11:04:12.164865 [0] MAX Duty = 5125%(X100), DQS PI = 22
7247 11:04:12.167944 [0] MIN Duty = 5000%(X100), DQS PI = 14
7248 11:04:12.171289 [0] AVG Duty = 5062%(X100)
7249 11:04:12.171364
7250 11:04:12.171422 ==DQS 1 ==
7251 11:04:12.174888 Final DQS duty delay cell = -4
7252 11:04:12.178074 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7253 11:04:12.182036 [-4] MIN Duty = 5031%(X100), DQS PI = 6
7254 11:04:12.184805 [-4] AVG Duty = 5062%(X100)
7255 11:04:12.184880
7256 11:04:12.187939 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7257 11:04:12.188014
7258 11:04:12.191631 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7259 11:04:12.195063 [DutyScan_Calibration_Flow] ====Done====
7260 11:04:12.195138
7261 11:04:12.199022 [DutyScan_Calibration_Flow] k_type=3
7262 11:04:12.215207
7263 11:04:12.215282 ==DQM 0 ==
7264 11:04:12.218698 Final DQM duty delay cell = 0
7265 11:04:12.222091 [0] MAX Duty = 5000%(X100), DQS PI = 20
7266 11:04:12.225093 [0] MIN Duty = 4875%(X100), DQS PI = 6
7267 11:04:12.225187 [0] AVG Duty = 4937%(X100)
7268 11:04:12.228783
7269 11:04:12.228890 ==DQM 1 ==
7270 11:04:12.231871 Final DQM duty delay cell = 0
7271 11:04:12.235535 [0] MAX Duty = 5187%(X100), DQS PI = 58
7272 11:04:12.238586 [0] MIN Duty = 4969%(X100), DQS PI = 18
7273 11:04:12.238661 [0] AVG Duty = 5078%(X100)
7274 11:04:12.242027
7275 11:04:12.245426 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7276 11:04:12.245501
7277 11:04:12.248462 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7278 11:04:12.252010 [DutyScan_Calibration_Flow] ====Done====
7279 11:04:12.252084
7280 11:04:12.255089 [DutyScan_Calibration_Flow] k_type=2
7281 11:04:12.272588
7282 11:04:12.272663 ==DQ 0 ==
7283 11:04:12.275571 Final DQ duty delay cell = 0
7284 11:04:12.279078 [0] MAX Duty = 5156%(X100), DQS PI = 0
7285 11:04:12.283672 [0] MIN Duty = 5031%(X100), DQS PI = 12
7286 11:04:12.283746 [0] AVG Duty = 5093%(X100)
7287 11:04:12.283804
7288 11:04:12.285910 ==DQ 1 ==
7289 11:04:12.288910 Final DQ duty delay cell = 0
7290 11:04:12.292503 [0] MAX Duty = 5031%(X100), DQS PI = 38
7291 11:04:12.296243 [0] MIN Duty = 4907%(X100), DQS PI = 18
7292 11:04:12.296317 [0] AVG Duty = 4969%(X100)
7293 11:04:12.296377
7294 11:04:12.299061 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7295 11:04:12.302391
7296 11:04:12.305662 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7297 11:04:12.309003 [DutyScan_Calibration_Flow] ====Done====
7298 11:04:12.309077 ==
7299 11:04:12.312801 Dram Type= 6, Freq= 0, CH_1, rank 0
7300 11:04:12.316199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7301 11:04:12.316276 ==
7302 11:04:12.319066 [Duty_Offset_Calibration]
7303 11:04:12.319141 B0:1 B1:1 CA:2
7304 11:04:12.319200
7305 11:04:12.323127 [DutyScan_Calibration_Flow] k_type=0
7306 11:04:12.332781
7307 11:04:12.332926 ==CLK 0==
7308 11:04:12.335852 Final CLK duty delay cell = 0
7309 11:04:12.339231 [0] MAX Duty = 5156%(X100), DQS PI = 24
7310 11:04:12.342741 [0] MIN Duty = 4938%(X100), DQS PI = 50
7311 11:04:12.342822 [0] AVG Duty = 5047%(X100)
7312 11:04:12.346045
7313 11:04:12.349429 CH1 CLK Duty spec in!! Max-Min= 218%
7314 11:04:12.352488 [DutyScan_Calibration_Flow] ====Done====
7315 11:04:12.352563
7316 11:04:12.356283 [DutyScan_Calibration_Flow] k_type=1
7317 11:04:12.372928
7318 11:04:12.373007 ==DQS 0 ==
7319 11:04:12.375899 Final DQS duty delay cell = 0
7320 11:04:12.379142 [0] MAX Duty = 5062%(X100), DQS PI = 20
7321 11:04:12.382486 [0] MIN Duty = 4813%(X100), DQS PI = 50
7322 11:04:12.382561 [0] AVG Duty = 4937%(X100)
7323 11:04:12.385830
7324 11:04:12.385904 ==DQS 1 ==
7325 11:04:12.389124 Final DQS duty delay cell = 0
7326 11:04:12.392257 [0] MAX Duty = 5031%(X100), DQS PI = 34
7327 11:04:12.395709 [0] MIN Duty = 4938%(X100), DQS PI = 12
7328 11:04:12.399327 [0] AVG Duty = 4984%(X100)
7329 11:04:12.399402
7330 11:04:12.402625 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7331 11:04:12.402700
7332 11:04:12.405656 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7333 11:04:12.409126 [DutyScan_Calibration_Flow] ====Done====
7334 11:04:12.409230
7335 11:04:12.412268 [DutyScan_Calibration_Flow] k_type=3
7336 11:04:12.429434
7337 11:04:12.429535 ==DQM 0 ==
7338 11:04:12.432516 Final DQM duty delay cell = 0
7339 11:04:12.435885 [0] MAX Duty = 5156%(X100), DQS PI = 20
7340 11:04:12.439919 [0] MIN Duty = 4844%(X100), DQS PI = 50
7341 11:04:12.440013 [0] AVG Duty = 5000%(X100)
7342 11:04:12.442704
7343 11:04:12.442795 ==DQM 1 ==
7344 11:04:12.446331 Final DQM duty delay cell = 0
7345 11:04:12.449804 [0] MAX Duty = 5156%(X100), DQS PI = 60
7346 11:04:12.453222 [0] MIN Duty = 4907%(X100), DQS PI = 18
7347 11:04:12.453316 [0] AVG Duty = 5031%(X100)
7348 11:04:12.453400
7349 11:04:12.459505 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7350 11:04:12.459596
7351 11:04:12.462874 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7352 11:04:12.466151 [DutyScan_Calibration_Flow] ====Done====
7353 11:04:12.466241
7354 11:04:12.469401 [DutyScan_Calibration_Flow] k_type=2
7355 11:04:12.486734
7356 11:04:12.486810 ==DQ 0 ==
7357 11:04:12.489916 Final DQ duty delay cell = 0
7358 11:04:12.493195 [0] MAX Duty = 5156%(X100), DQS PI = 20
7359 11:04:12.496292 [0] MIN Duty = 4907%(X100), DQS PI = 52
7360 11:04:12.496385 [0] AVG Duty = 5031%(X100)
7361 11:04:12.496469
7362 11:04:12.499866 ==DQ 1 ==
7363 11:04:12.502871 Final DQ duty delay cell = 0
7364 11:04:12.506078 [0] MAX Duty = 5093%(X100), DQS PI = 26
7365 11:04:12.510276 [0] MIN Duty = 5031%(X100), DQS PI = 0
7366 11:04:12.510375 [0] AVG Duty = 5062%(X100)
7367 11:04:12.510458
7368 11:04:12.513227 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7369 11:04:12.513312
7370 11:04:12.516666 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7371 11:04:12.523264 [DutyScan_Calibration_Flow] ====Done====
7372 11:04:12.526468 nWR fixed to 30
7373 11:04:12.526544 [ModeRegInit_LP4] CH0 RK0
7374 11:04:12.529524 [ModeRegInit_LP4] CH0 RK1
7375 11:04:12.533259 [ModeRegInit_LP4] CH1 RK0
7376 11:04:12.533333 [ModeRegInit_LP4] CH1 RK1
7377 11:04:12.536047 match AC timing 5
7378 11:04:12.539321 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7379 11:04:12.542990 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7380 11:04:12.549668 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7381 11:04:12.553087 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7382 11:04:12.559805 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7383 11:04:12.559883 [MiockJmeterHQA]
7384 11:04:12.559943
7385 11:04:12.563160 [DramcMiockJmeter] u1RxGatingPI = 0
7386 11:04:12.563235 0 : 4252, 4027
7387 11:04:12.566951 4 : 4368, 4140
7388 11:04:12.567060 8 : 4257, 4029
7389 11:04:12.569793 12 : 4363, 4137
7390 11:04:12.569868 16 : 4253, 4027
7391 11:04:12.573323 20 : 4253, 4026
7392 11:04:12.573401 24 : 4252, 4027
7393 11:04:12.573462 28 : 4255, 4029
7394 11:04:12.576796 32 : 4363, 4138
7395 11:04:12.576871 36 : 4249, 4027
7396 11:04:12.580415 40 : 4252, 4027
7397 11:04:12.580490 44 : 4252, 4027
7398 11:04:12.583355 48 : 4252, 4029
7399 11:04:12.583430 52 : 4250, 4027
7400 11:04:12.586372 56 : 4363, 4138
7401 11:04:12.586448 60 : 4360, 4137
7402 11:04:12.586508 64 : 4250, 4027
7403 11:04:12.590307 68 : 4249, 4027
7404 11:04:12.590383 72 : 4250, 4027
7405 11:04:12.593337 76 : 4250, 4027
7406 11:04:12.593412 80 : 4252, 4029
7407 11:04:12.596692 84 : 4360, 4138
7408 11:04:12.596767 88 : 4249, 4027
7409 11:04:12.596826 92 : 4250, 4027
7410 11:04:12.600065 96 : 4250, 2978
7411 11:04:12.600140 100 : 4252, 0
7412 11:04:12.603487 104 : 4249, 0
7413 11:04:12.603563 108 : 4250, 0
7414 11:04:12.603622 112 : 4250, 0
7415 11:04:12.607063 116 : 4361, 0
7416 11:04:12.607140 120 : 4361, 0
7417 11:04:12.610133 124 : 4363, 0
7418 11:04:12.610232 128 : 4249, 0
7419 11:04:12.610326 132 : 4250, 0
7420 11:04:12.613383 136 : 4363, 0
7421 11:04:12.613458 140 : 4250, 0
7422 11:04:12.616950 144 : 4249, 0
7423 11:04:12.617025 148 : 4250, 0
7424 11:04:12.617085 152 : 4250, 0
7425 11:04:12.620030 156 : 4249, 0
7426 11:04:12.620105 160 : 4250, 0
7427 11:04:12.620164 164 : 4253, 0
7428 11:04:12.623298 168 : 4249, 0
7429 11:04:12.623374 172 : 4250, 0
7430 11:04:12.626849 176 : 4253, 0
7431 11:04:12.626924 180 : 4249, 0
7432 11:04:12.626983 184 : 4360, 0
7433 11:04:12.629760 188 : 4361, 0
7434 11:04:12.629855 192 : 4250, 0
7435 11:04:12.633712 196 : 4249, 0
7436 11:04:12.633788 200 : 4250, 0
7437 11:04:12.633847 204 : 4250, 0
7438 11:04:12.636766 208 : 4252, 0
7439 11:04:12.636841 212 : 4250, 141
7440 11:04:12.640058 216 : 4361, 3936
7441 11:04:12.640134 220 : 4249, 4027
7442 11:04:12.643160 224 : 4360, 4137
7443 11:04:12.643237 228 : 4361, 4137
7444 11:04:12.647126 232 : 4250, 4027
7445 11:04:12.647202 236 : 4249, 4027
7446 11:04:12.647261 240 : 4363, 4140
7447 11:04:12.649816 244 : 4250, 4027
7448 11:04:12.649891 248 : 4250, 4027
7449 11:04:12.653374 252 : 4249, 4027
7450 11:04:12.653449 256 : 4249, 4027
7451 11:04:12.656813 260 : 4250, 4026
7452 11:04:12.656887 264 : 4250, 4027
7453 11:04:12.659794 268 : 4360, 4138
7454 11:04:12.659869 272 : 4250, 4027
7455 11:04:12.663818 276 : 4250, 4026
7456 11:04:12.663893 280 : 4361, 4137
7457 11:04:12.666465 284 : 4250, 4027
7458 11:04:12.666540 288 : 4249, 4027
7459 11:04:12.666598 292 : 4363, 4140
7460 11:04:12.670617 296 : 4250, 4027
7461 11:04:12.670691 300 : 4250, 4027
7462 11:04:12.673714 304 : 4250, 4027
7463 11:04:12.673789 308 : 4249, 4027
7464 11:04:12.676958 312 : 4250, 4026
7465 11:04:12.677033 316 : 4250, 4027
7466 11:04:12.680196 320 : 4361, 4138
7467 11:04:12.680272 324 : 4250, 4027
7468 11:04:12.683446 328 : 4250, 4026
7469 11:04:12.683521 332 : 4361, 2883
7470 11:04:12.686983 336 : 4250, 28
7471 11:04:12.687058
7472 11:04:12.687116 MIOCK jitter meter ch=0
7473 11:04:12.687170
7474 11:04:12.690113 1T = (336-100) = 236 dly cells
7475 11:04:12.697078 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7476 11:04:12.697176 ==
7477 11:04:12.700300 Dram Type= 6, Freq= 0, CH_0, rank 0
7478 11:04:12.703543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7479 11:04:12.703619 ==
7480 11:04:12.710427 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7481 11:04:12.713900 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7482 11:04:12.716999 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7483 11:04:12.723386 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7484 11:04:12.732779 [CA 0] Center 44 (14~75) winsize 62
7485 11:04:12.736080 [CA 1] Center 44 (13~75) winsize 63
7486 11:04:12.739591 [CA 2] Center 40 (11~69) winsize 59
7487 11:04:12.742774 [CA 3] Center 39 (10~69) winsize 60
7488 11:04:12.747137 [CA 4] Center 37 (7~68) winsize 62
7489 11:04:12.749476 [CA 5] Center 37 (7~67) winsize 61
7490 11:04:12.749551
7491 11:04:12.753324 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7492 11:04:12.753398
7493 11:04:12.756706 [CATrainingPosCal] consider 1 rank data
7494 11:04:12.760087 u2DelayCellTimex100 = 275/100 ps
7495 11:04:12.763533 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7496 11:04:12.769905 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7497 11:04:12.772825 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7498 11:04:12.776498 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7499 11:04:12.779790 CA4 delay=37 (7~68),Diff = 0 PI (0 cell)
7500 11:04:12.782952 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7501 11:04:12.783026
7502 11:04:12.786211 CA PerBit enable=1, Macro0, CA PI delay=37
7503 11:04:12.786285
7504 11:04:12.789401 [CBTSetCACLKResult] CA Dly = 37
7505 11:04:12.793330 CS Dly: 11 (0~42)
7506 11:04:12.796149 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7507 11:04:12.799766 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7508 11:04:12.799841 ==
7509 11:04:12.802881 Dram Type= 6, Freq= 0, CH_0, rank 1
7510 11:04:12.806982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7511 11:04:12.809800 ==
7512 11:04:12.812856 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7513 11:04:12.816316 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7514 11:04:12.822671 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7515 11:04:12.825958 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7516 11:04:12.836683 [CA 0] Center 44 (14~75) winsize 62
7517 11:04:12.840093 [CA 1] Center 44 (14~75) winsize 62
7518 11:04:12.843896 [CA 2] Center 40 (11~69) winsize 59
7519 11:04:12.846883 [CA 3] Center 39 (10~69) winsize 60
7520 11:04:12.850022 [CA 4] Center 37 (8~67) winsize 60
7521 11:04:12.853130 [CA 5] Center 37 (7~67) winsize 61
7522 11:04:12.853206
7523 11:04:12.856999 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7524 11:04:12.857073
7525 11:04:12.860289 [CATrainingPosCal] consider 2 rank data
7526 11:04:12.863645 u2DelayCellTimex100 = 275/100 ps
7527 11:04:12.866751 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7528 11:04:12.873711 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7529 11:04:12.876685 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7530 11:04:12.880345 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7531 11:04:12.883354 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7532 11:04:12.886905 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7533 11:04:12.886979
7534 11:04:12.890223 CA PerBit enable=1, Macro0, CA PI delay=37
7535 11:04:12.890298
7536 11:04:12.893571 [CBTSetCACLKResult] CA Dly = 37
7537 11:04:12.897100 CS Dly: 12 (0~44)
7538 11:04:12.900209 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7539 11:04:12.903612 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7540 11:04:12.903706
7541 11:04:12.906950 ----->DramcWriteLeveling(PI) begin...
7542 11:04:12.907044 ==
7543 11:04:12.910124 Dram Type= 6, Freq= 0, CH_0, rank 0
7544 11:04:12.913360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7545 11:04:12.916995 ==
7546 11:04:12.917069 Write leveling (Byte 0): 34 => 34
7547 11:04:12.920914 Write leveling (Byte 1): 27 => 27
7548 11:04:12.924186 DramcWriteLeveling(PI) end<-----
7549 11:04:12.924259
7550 11:04:12.924316 ==
7551 11:04:12.926878 Dram Type= 6, Freq= 0, CH_0, rank 0
7552 11:04:12.933650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7553 11:04:12.933725 ==
7554 11:04:12.933782 [Gating] SW mode calibration
7555 11:04:12.943308 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7556 11:04:12.946713 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7557 11:04:12.950088 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7558 11:04:12.956919 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7559 11:04:12.960050 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7560 11:04:12.963732 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7561 11:04:12.970351 1 4 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7562 11:04:12.973453 1 4 20 | B1->B0 | 2323 3232 | 1 1 | (1 1) (1 1)
7563 11:04:12.976871 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7564 11:04:12.983891 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7565 11:04:12.987097 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7566 11:04:12.990559 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7567 11:04:12.997065 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7568 11:04:13.000161 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7569 11:04:13.003361 1 5 16 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
7570 11:04:13.010483 1 5 20 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
7571 11:04:13.013746 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
7572 11:04:13.017197 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7573 11:04:13.023601 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 11:04:13.026507 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 11:04:13.030250 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 11:04:13.036862 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 11:04:13.039965 1 6 16 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
7578 11:04:13.043268 1 6 20 | B1->B0 | 2d2c 4646 | 1 0 | (0 0) (0 0)
7579 11:04:13.050126 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7580 11:04:13.053189 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7581 11:04:13.056743 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 11:04:13.060399 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 11:04:13.066954 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7584 11:04:13.070217 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7585 11:04:13.073601 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7586 11:04:13.080198 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7587 11:04:13.083161 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7588 11:04:13.087025 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 11:04:13.093935 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 11:04:13.096965 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 11:04:13.100052 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 11:04:13.106622 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 11:04:13.110205 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 11:04:13.113629 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 11:04:13.120334 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 11:04:13.123807 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 11:04:13.127467 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 11:04:13.133484 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 11:04:13.137002 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 11:04:13.140099 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 11:04:13.143272 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7602 11:04:13.150333 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7603 11:04:13.153424 Total UI for P1: 0, mck2ui 16
7604 11:04:13.156687 best dqsien dly found for B0: ( 1, 9, 16)
7605 11:04:13.160107 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 11:04:13.163599 Total UI for P1: 0, mck2ui 16
7607 11:04:13.166630 best dqsien dly found for B1: ( 1, 9, 20)
7608 11:04:13.170221 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7609 11:04:13.173588 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7610 11:04:13.173662
7611 11:04:13.176950 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7612 11:04:13.180326 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7613 11:04:13.183513 [Gating] SW calibration Done
7614 11:04:13.183587 ==
7615 11:04:13.187434 Dram Type= 6, Freq= 0, CH_0, rank 0
7616 11:04:13.193681 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7617 11:04:13.193757 ==
7618 11:04:13.193815 RX Vref Scan: 0
7619 11:04:13.193869
7620 11:04:13.196956 RX Vref 0 -> 0, step: 1
7621 11:04:13.197030
7622 11:04:13.200276 RX Delay 0 -> 252, step: 8
7623 11:04:13.203737 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7624 11:04:13.207047 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7625 11:04:13.210486 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7626 11:04:13.213649 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7627 11:04:13.220307 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7628 11:04:13.223378 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7629 11:04:13.227298 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7630 11:04:13.231220 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7631 11:04:13.233520 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7632 11:04:13.237036 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7633 11:04:13.243894 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7634 11:04:13.247132 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7635 11:04:13.250345 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7636 11:04:13.253923 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7637 11:04:13.260234 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7638 11:04:13.264152 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7639 11:04:13.264227 ==
7640 11:04:13.267107 Dram Type= 6, Freq= 0, CH_0, rank 0
7641 11:04:13.270259 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7642 11:04:13.270334 ==
7643 11:04:13.270391 DQS Delay:
7644 11:04:13.273835 DQS0 = 0, DQS1 = 0
7645 11:04:13.273910 DQM Delay:
7646 11:04:13.277213 DQM0 = 132, DQM1 = 125
7647 11:04:13.277287 DQ Delay:
7648 11:04:13.280268 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7649 11:04:13.283580 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7650 11:04:13.287050 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =123
7651 11:04:13.291425 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7652 11:04:13.293630
7653 11:04:13.293704
7654 11:04:13.293762 ==
7655 11:04:13.297076 Dram Type= 6, Freq= 0, CH_0, rank 0
7656 11:04:13.300307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7657 11:04:13.300401 ==
7658 11:04:13.300488
7659 11:04:13.300569
7660 11:04:13.303807 TX Vref Scan disable
7661 11:04:13.303907 == TX Byte 0 ==
7662 11:04:13.310145 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7663 11:04:13.313526 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7664 11:04:13.313622 == TX Byte 1 ==
7665 11:04:13.320609 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7666 11:04:13.323920 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7667 11:04:13.323995 ==
7668 11:04:13.327726 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 11:04:13.330211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 11:04:13.330286 ==
7671 11:04:13.344693
7672 11:04:13.348660 TX Vref early break, caculate TX vref
7673 11:04:13.351401 TX Vref=16, minBit 8, minWin=20, winSum=358
7674 11:04:13.355230 TX Vref=18, minBit 1, minWin=23, winSum=374
7675 11:04:13.357711 TX Vref=20, minBit 7, minWin=23, winSum=386
7676 11:04:13.361554 TX Vref=22, minBit 8, minWin=23, winSum=393
7677 11:04:13.364779 TX Vref=24, minBit 4, minWin=24, winSum=406
7678 11:04:13.371398 TX Vref=26, minBit 8, minWin=25, winSum=418
7679 11:04:13.374651 TX Vref=28, minBit 4, minWin=25, winSum=423
7680 11:04:13.378130 TX Vref=30, minBit 3, minWin=25, winSum=420
7681 11:04:13.381328 TX Vref=32, minBit 0, minWin=25, winSum=409
7682 11:04:13.385299 TX Vref=34, minBit 4, minWin=23, winSum=397
7683 11:04:13.391199 [TxChooseVref] Worse bit 4, Min win 25, Win sum 423, Final Vref 28
7684 11:04:13.391371
7685 11:04:13.395052 Final TX Range 0 Vref 28
7686 11:04:13.395277
7687 11:04:13.395374 ==
7688 11:04:13.397949 Dram Type= 6, Freq= 0, CH_0, rank 0
7689 11:04:13.401314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7690 11:04:13.401468 ==
7691 11:04:13.401548
7692 11:04:13.401619
7693 11:04:13.404507 TX Vref Scan disable
7694 11:04:13.411501 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7695 11:04:13.411605 == TX Byte 0 ==
7696 11:04:13.414872 u2DelayCellOfst[0]=14 cells (4 PI)
7697 11:04:13.418312 u2DelayCellOfst[1]=21 cells (6 PI)
7698 11:04:13.421919 u2DelayCellOfst[2]=10 cells (3 PI)
7699 11:04:13.424601 u2DelayCellOfst[3]=14 cells (4 PI)
7700 11:04:13.428228 u2DelayCellOfst[4]=10 cells (3 PI)
7701 11:04:13.431325 u2DelayCellOfst[5]=0 cells (0 PI)
7702 11:04:13.431401 u2DelayCellOfst[6]=21 cells (6 PI)
7703 11:04:13.434766 u2DelayCellOfst[7]=21 cells (6 PI)
7704 11:04:13.441656 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7705 11:04:13.444717 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7706 11:04:13.444856 == TX Byte 1 ==
7707 11:04:13.448414 u2DelayCellOfst[8]=0 cells (0 PI)
7708 11:04:13.451527 u2DelayCellOfst[9]=0 cells (0 PI)
7709 11:04:13.455504 u2DelayCellOfst[10]=7 cells (2 PI)
7710 11:04:13.458134 u2DelayCellOfst[11]=0 cells (0 PI)
7711 11:04:13.461708 u2DelayCellOfst[12]=10 cells (3 PI)
7712 11:04:13.464966 u2DelayCellOfst[13]=10 cells (3 PI)
7713 11:04:13.468540 u2DelayCellOfst[14]=14 cells (4 PI)
7714 11:04:13.471704 u2DelayCellOfst[15]=10 cells (3 PI)
7715 11:04:13.475358 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7716 11:04:13.478447 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7717 11:04:13.481657 DramC Write-DBI on
7718 11:04:13.481738 ==
7719 11:04:13.484884 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 11:04:13.488344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 11:04:13.488425 ==
7722 11:04:13.488484
7723 11:04:13.488539
7724 11:04:13.492159 TX Vref Scan disable
7725 11:04:13.494835 == TX Byte 0 ==
7726 11:04:13.498091 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7727 11:04:13.501761 == TX Byte 1 ==
7728 11:04:13.505352 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7729 11:04:13.505450 DramC Write-DBI off
7730 11:04:13.505570
7731 11:04:13.508108 [DATLAT]
7732 11:04:13.508202 Freq=1600, CH0 RK0
7733 11:04:13.508292
7734 11:04:13.511673 DATLAT Default: 0xf
7735 11:04:13.511777 0, 0xFFFF, sum = 0
7736 11:04:13.514872 1, 0xFFFF, sum = 0
7737 11:04:13.514970 2, 0xFFFF, sum = 0
7738 11:04:13.518109 3, 0xFFFF, sum = 0
7739 11:04:13.518197 4, 0xFFFF, sum = 0
7740 11:04:13.521455 5, 0xFFFF, sum = 0
7741 11:04:13.521569 6, 0xFFFF, sum = 0
7742 11:04:13.524950 7, 0xFFFF, sum = 0
7743 11:04:13.525029 8, 0xFFFF, sum = 0
7744 11:04:13.528106 9, 0xFFFF, sum = 0
7745 11:04:13.528210 10, 0xFFFF, sum = 0
7746 11:04:13.531649 11, 0xFFFF, sum = 0
7747 11:04:13.534727 12, 0xFFFF, sum = 0
7748 11:04:13.534823 13, 0xFFFF, sum = 0
7749 11:04:13.538317 14, 0x0, sum = 1
7750 11:04:13.538415 15, 0x0, sum = 2
7751 11:04:13.538500 16, 0x0, sum = 3
7752 11:04:13.541683 17, 0x0, sum = 4
7753 11:04:13.541779 best_step = 15
7754 11:04:13.541863
7755 11:04:13.541976 ==
7756 11:04:13.544969 Dram Type= 6, Freq= 0, CH_0, rank 0
7757 11:04:13.552177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7758 11:04:13.552292 ==
7759 11:04:13.552415 RX Vref Scan: 1
7760 11:04:13.552498
7761 11:04:13.555217 Set Vref Range= 24 -> 127
7762 11:04:13.555309
7763 11:04:13.558372 RX Vref 24 -> 127, step: 1
7764 11:04:13.558476
7765 11:04:13.561575 RX Delay 11 -> 252, step: 4
7766 11:04:13.561700
7767 11:04:13.564996 Set Vref, RX VrefLevel [Byte0]: 24
7768 11:04:13.568574 [Byte1]: 24
7769 11:04:13.568676
7770 11:04:13.571578 Set Vref, RX VrefLevel [Byte0]: 25
7771 11:04:13.574881 [Byte1]: 25
7772 11:04:13.574968
7773 11:04:13.578514 Set Vref, RX VrefLevel [Byte0]: 26
7774 11:04:13.581614 [Byte1]: 26
7775 11:04:13.581750
7776 11:04:13.584971 Set Vref, RX VrefLevel [Byte0]: 27
7777 11:04:13.588300 [Byte1]: 27
7778 11:04:13.592476
7779 11:04:13.592553 Set Vref, RX VrefLevel [Byte0]: 28
7780 11:04:13.595868 [Byte1]: 28
7781 11:04:13.599911
7782 11:04:13.599985 Set Vref, RX VrefLevel [Byte0]: 29
7783 11:04:13.603071 [Byte1]: 29
7784 11:04:13.607991
7785 11:04:13.608066 Set Vref, RX VrefLevel [Byte0]: 30
7786 11:04:13.610778 [Byte1]: 30
7787 11:04:13.615457
7788 11:04:13.615562 Set Vref, RX VrefLevel [Byte0]: 31
7789 11:04:13.618832 [Byte1]: 31
7790 11:04:13.622588
7791 11:04:13.622667 Set Vref, RX VrefLevel [Byte0]: 32
7792 11:04:13.626219 [Byte1]: 32
7793 11:04:13.630748
7794 11:04:13.630824 Set Vref, RX VrefLevel [Byte0]: 33
7795 11:04:13.633829 [Byte1]: 33
7796 11:04:13.638242
7797 11:04:13.638319 Set Vref, RX VrefLevel [Byte0]: 34
7798 11:04:13.641229 [Byte1]: 34
7799 11:04:13.645447
7800 11:04:13.645523 Set Vref, RX VrefLevel [Byte0]: 35
7801 11:04:13.648708 [Byte1]: 35
7802 11:04:13.653372
7803 11:04:13.653448 Set Vref, RX VrefLevel [Byte0]: 36
7804 11:04:13.656987 [Byte1]: 36
7805 11:04:13.660527
7806 11:04:13.660604 Set Vref, RX VrefLevel [Byte0]: 37
7807 11:04:13.663945 [Byte1]: 37
7808 11:04:13.668437
7809 11:04:13.668515 Set Vref, RX VrefLevel [Byte0]: 38
7810 11:04:13.671612 [Byte1]: 38
7811 11:04:13.675893
7812 11:04:13.675973 Set Vref, RX VrefLevel [Byte0]: 39
7813 11:04:13.679373 [Byte1]: 39
7814 11:04:13.683411
7815 11:04:13.683488 Set Vref, RX VrefLevel [Byte0]: 40
7816 11:04:13.687107 [Byte1]: 40
7817 11:04:13.691407
7818 11:04:13.691484 Set Vref, RX VrefLevel [Byte0]: 41
7819 11:04:13.694321 [Byte1]: 41
7820 11:04:13.699127
7821 11:04:13.699204 Set Vref, RX VrefLevel [Byte0]: 42
7822 11:04:13.701987 [Byte1]: 42
7823 11:04:13.706765
7824 11:04:13.706840 Set Vref, RX VrefLevel [Byte0]: 43
7825 11:04:13.709641 [Byte1]: 43
7826 11:04:13.714227
7827 11:04:13.714302 Set Vref, RX VrefLevel [Byte0]: 44
7828 11:04:13.717627 [Byte1]: 44
7829 11:04:13.722553
7830 11:04:13.722629 Set Vref, RX VrefLevel [Byte0]: 45
7831 11:04:13.725422 [Byte1]: 45
7832 11:04:13.729603
7833 11:04:13.729678 Set Vref, RX VrefLevel [Byte0]: 46
7834 11:04:13.732330 [Byte1]: 46
7835 11:04:13.737003
7836 11:04:13.737077 Set Vref, RX VrefLevel [Byte0]: 47
7837 11:04:13.743476 [Byte1]: 47
7838 11:04:13.743551
7839 11:04:13.746909 Set Vref, RX VrefLevel [Byte0]: 48
7840 11:04:13.750240 [Byte1]: 48
7841 11:04:13.750316
7842 11:04:13.753914 Set Vref, RX VrefLevel [Byte0]: 49
7843 11:04:13.757489 [Byte1]: 49
7844 11:04:13.757565
7845 11:04:13.760147 Set Vref, RX VrefLevel [Byte0]: 50
7846 11:04:13.763594 [Byte1]: 50
7847 11:04:13.767351
7848 11:04:13.767425 Set Vref, RX VrefLevel [Byte0]: 51
7849 11:04:13.770837 [Byte1]: 51
7850 11:04:13.775417
7851 11:04:13.775492 Set Vref, RX VrefLevel [Byte0]: 52
7852 11:04:13.778309 [Byte1]: 52
7853 11:04:13.782523
7854 11:04:13.782597 Set Vref, RX VrefLevel [Byte0]: 53
7855 11:04:13.785969 [Byte1]: 53
7856 11:04:13.790855
7857 11:04:13.790930 Set Vref, RX VrefLevel [Byte0]: 54
7858 11:04:13.793583 [Byte1]: 54
7859 11:04:13.797844
7860 11:04:13.797919 Set Vref, RX VrefLevel [Byte0]: 55
7861 11:04:13.801045 [Byte1]: 55
7862 11:04:13.806053
7863 11:04:13.806128 Set Vref, RX VrefLevel [Byte0]: 56
7864 11:04:13.808867 [Byte1]: 56
7865 11:04:13.813260
7866 11:04:13.813335 Set Vref, RX VrefLevel [Byte0]: 57
7867 11:04:13.816483 [Byte1]: 57
7868 11:04:13.820921
7869 11:04:13.820997 Set Vref, RX VrefLevel [Byte0]: 58
7870 11:04:13.823828 [Byte1]: 58
7871 11:04:13.828397
7872 11:04:13.828472 Set Vref, RX VrefLevel [Byte0]: 59
7873 11:04:13.831762 [Byte1]: 59
7874 11:04:13.836104
7875 11:04:13.836179 Set Vref, RX VrefLevel [Byte0]: 60
7876 11:04:13.839065 [Byte1]: 60
7877 11:04:13.843411
7878 11:04:13.843484 Set Vref, RX VrefLevel [Byte0]: 61
7879 11:04:13.846706 [Byte1]: 61
7880 11:04:13.851496
7881 11:04:13.851571 Set Vref, RX VrefLevel [Byte0]: 62
7882 11:04:13.854177 [Byte1]: 62
7883 11:04:13.858700
7884 11:04:13.858774 Set Vref, RX VrefLevel [Byte0]: 63
7885 11:04:13.862631 [Byte1]: 63
7886 11:04:13.866067
7887 11:04:13.866141 Set Vref, RX VrefLevel [Byte0]: 64
7888 11:04:13.869661 [Byte1]: 64
7889 11:04:13.874381
7890 11:04:13.874456 Set Vref, RX VrefLevel [Byte0]: 65
7891 11:04:13.877076 [Byte1]: 65
7892 11:04:13.882020
7893 11:04:13.882095 Set Vref, RX VrefLevel [Byte0]: 66
7894 11:04:13.884945 [Byte1]: 66
7895 11:04:13.889014
7896 11:04:13.889089 Set Vref, RX VrefLevel [Byte0]: 67
7897 11:04:13.892240 [Byte1]: 67
7898 11:04:13.896608
7899 11:04:13.896683 Set Vref, RX VrefLevel [Byte0]: 68
7900 11:04:13.900323 [Byte1]: 68
7901 11:04:13.904879
7902 11:04:13.904953 Set Vref, RX VrefLevel [Byte0]: 69
7903 11:04:13.907453 [Byte1]: 69
7904 11:04:13.912244
7905 11:04:13.912355 Set Vref, RX VrefLevel [Byte0]: 70
7906 11:04:13.915292 [Byte1]: 70
7907 11:04:13.919604
7908 11:04:13.919680 Set Vref, RX VrefLevel [Byte0]: 71
7909 11:04:13.922972 [Byte1]: 71
7910 11:04:13.927614
7911 11:04:13.927689 Set Vref, RX VrefLevel [Byte0]: 72
7912 11:04:13.930606 [Byte1]: 72
7913 11:04:13.934602
7914 11:04:13.934681 Set Vref, RX VrefLevel [Byte0]: 73
7915 11:04:13.937858 [Byte1]: 73
7916 11:04:13.942374
7917 11:04:13.942449 Set Vref, RX VrefLevel [Byte0]: 74
7918 11:04:13.946130 [Byte1]: 74
7919 11:04:13.950444
7920 11:04:13.950519 Final RX Vref Byte 0 = 56 to rank0
7921 11:04:13.953755 Final RX Vref Byte 1 = 62 to rank0
7922 11:04:13.957364 Final RX Vref Byte 0 = 56 to rank1
7923 11:04:13.960695 Final RX Vref Byte 1 = 62 to rank1==
7924 11:04:13.963490 Dram Type= 6, Freq= 0, CH_0, rank 0
7925 11:04:13.966927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7926 11:04:13.970216 ==
7927 11:04:13.970292 DQS Delay:
7928 11:04:13.970351 DQS0 = 0, DQS1 = 0
7929 11:04:13.973762 DQM Delay:
7930 11:04:13.973837 DQM0 = 128, DQM1 = 122
7931 11:04:13.977305 DQ Delay:
7932 11:04:13.980575 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =126
7933 11:04:13.983819 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =136
7934 11:04:13.987362 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7935 11:04:13.990585 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =132
7936 11:04:13.990661
7937 11:04:13.990719
7938 11:04:13.990772
7939 11:04:13.993662 [DramC_TX_OE_Calibration] TA2
7940 11:04:13.996937 Original DQ_B0 (3 6) =30, OEN = 27
7941 11:04:14.000406 Original DQ_B1 (3 6) =30, OEN = 27
7942 11:04:14.000481 24, 0x0, End_B0=24 End_B1=24
7943 11:04:14.003791 25, 0x0, End_B0=25 End_B1=25
7944 11:04:14.007136 26, 0x0, End_B0=26 End_B1=26
7945 11:04:14.010280 27, 0x0, End_B0=27 End_B1=27
7946 11:04:14.013764 28, 0x0, End_B0=28 End_B1=28
7947 11:04:14.013843 29, 0x0, End_B0=29 End_B1=29
7948 11:04:14.017047 30, 0x0, End_B0=30 End_B1=30
7949 11:04:14.020417 31, 0x4141, End_B0=30 End_B1=30
7950 11:04:14.023598 Byte0 end_step=30 best_step=27
7951 11:04:14.026877 Byte1 end_step=30 best_step=27
7952 11:04:14.030124 Byte0 TX OE(2T, 0.5T) = (3, 3)
7953 11:04:14.030199 Byte1 TX OE(2T, 0.5T) = (3, 3)
7954 11:04:14.030257
7955 11:04:14.030311
7956 11:04:14.040703 [DQSOSCAuto] RK0, (LSB)MR18= 0x1409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7957 11:04:14.043746 CH0 RK0: MR19=303, MR18=1409
7958 11:04:14.047265 CH0_RK0: MR19=0x303, MR18=0x1409, DQSOSC=399, MR23=63, INC=23, DEC=15
7959 11:04:14.050436
7960 11:04:14.053756 ----->DramcWriteLeveling(PI) begin...
7961 11:04:14.053832 ==
7962 11:04:14.056956 Dram Type= 6, Freq= 0, CH_0, rank 1
7963 11:04:14.060392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7964 11:04:14.060468 ==
7965 11:04:14.063652 Write leveling (Byte 0): 33 => 33
7966 11:04:14.067717 Write leveling (Byte 1): 26 => 26
7967 11:04:14.070352 DramcWriteLeveling(PI) end<-----
7968 11:04:14.070427
7969 11:04:14.070486 ==
7970 11:04:14.073901 Dram Type= 6, Freq= 0, CH_0, rank 1
7971 11:04:14.077855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7972 11:04:14.077955 ==
7973 11:04:14.080591 [Gating] SW mode calibration
7974 11:04:14.087209 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7975 11:04:14.090692 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7976 11:04:14.098120 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7977 11:04:14.100727 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7978 11:04:14.104434 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7979 11:04:14.110553 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
7980 11:04:14.113956 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7981 11:04:14.118224 1 4 20 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
7982 11:04:14.124663 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7983 11:04:14.127363 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7984 11:04:14.130794 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7985 11:04:14.137313 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7986 11:04:14.140907 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7987 11:04:14.143989 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
7988 11:04:14.151554 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7989 11:04:14.154230 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
7990 11:04:14.157640 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 11:04:14.161041 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 11:04:14.167761 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 11:04:14.171166 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 11:04:14.174515 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7995 11:04:14.181243 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7996 11:04:14.184223 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7997 11:04:14.188013 1 6 20 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
7998 11:04:14.194642 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7999 11:04:14.197516 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8000 11:04:14.200925 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 11:04:14.207828 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 11:04:14.211424 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8003 11:04:14.214280 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8004 11:04:14.221109 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8005 11:04:14.224460 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8006 11:04:14.228090 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8007 11:04:14.234231 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 11:04:14.237603 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 11:04:14.241621 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 11:04:14.244483 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 11:04:14.251356 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 11:04:14.254947 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 11:04:14.257718 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 11:04:14.264532 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 11:04:14.268413 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 11:04:14.271044 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 11:04:14.277779 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 11:04:14.281976 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8019 11:04:14.284492 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8020 11:04:14.291254 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8021 11:04:14.291330 Total UI for P1: 0, mck2ui 16
8022 11:04:14.297859 best dqsien dly found for B0: ( 1, 9, 10)
8023 11:04:14.301206 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8024 11:04:14.304572 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8025 11:04:14.307805 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 11:04:14.311584 Total UI for P1: 0, mck2ui 16
8027 11:04:14.314707 best dqsien dly found for B1: ( 1, 9, 22)
8028 11:04:14.318030 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8029 11:04:14.321418 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
8030 11:04:14.324771
8031 11:04:14.327909 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8032 11:04:14.331253 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
8033 11:04:14.335244 [Gating] SW calibration Done
8034 11:04:14.335343 ==
8035 11:04:14.338425 Dram Type= 6, Freq= 0, CH_0, rank 1
8036 11:04:14.341890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8037 11:04:14.341966 ==
8038 11:04:14.342025 RX Vref Scan: 0
8039 11:04:14.344915
8040 11:04:14.344989 RX Vref 0 -> 0, step: 1
8041 11:04:14.345047
8042 11:04:14.348918 RX Delay 0 -> 252, step: 8
8043 11:04:14.351720 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8044 11:04:14.354984 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8045 11:04:14.361260 iDelay=200, Bit 2, Center 127 (64 ~ 191) 128
8046 11:04:14.364669 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8047 11:04:14.368176 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8048 11:04:14.371523 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8049 11:04:14.375036 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8050 11:04:14.378111 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8051 11:04:14.385020 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8052 11:04:14.388782 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8053 11:04:14.391237 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8054 11:04:14.394853 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8055 11:04:14.398714 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8056 11:04:14.405466 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8057 11:04:14.408878 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8058 11:04:14.412423 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8059 11:04:14.412498 ==
8060 11:04:14.415567 Dram Type= 6, Freq= 0, CH_0, rank 1
8061 11:04:14.419367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8062 11:04:14.419443 ==
8063 11:04:14.421945 DQS Delay:
8064 11:04:14.422036 DQS0 = 0, DQS1 = 0
8065 11:04:14.425059 DQM Delay:
8066 11:04:14.425191 DQM0 = 130, DQM1 = 125
8067 11:04:14.425252 DQ Delay:
8068 11:04:14.428575 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8069 11:04:14.432599 DQ4 =131, DQ5 =115, DQ6 =139, DQ7 =139
8070 11:04:14.438474 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8071 11:04:14.441961 DQ12 =127, DQ13 =131, DQ14 =139, DQ15 =131
8072 11:04:14.442039
8073 11:04:14.442117
8074 11:04:14.442207 ==
8075 11:04:14.445619 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 11:04:14.449096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 11:04:14.449217 ==
8078 11:04:14.449295
8079 11:04:14.449368
8080 11:04:14.452148 TX Vref Scan disable
8081 11:04:14.455419 == TX Byte 0 ==
8082 11:04:14.458914 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8083 11:04:14.462386 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8084 11:04:14.465382 == TX Byte 1 ==
8085 11:04:14.468895 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8086 11:04:14.472072 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8087 11:04:14.472150 ==
8088 11:04:14.476138 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 11:04:14.478640 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 11:04:14.478718 ==
8091 11:04:14.495176
8092 11:04:14.498098 TX Vref early break, caculate TX vref
8093 11:04:14.501930 TX Vref=16, minBit 0, minWin=22, winSum=369
8094 11:04:14.504965 TX Vref=18, minBit 9, minWin=22, winSum=380
8095 11:04:14.508589 TX Vref=20, minBit 3, minWin=23, winSum=393
8096 11:04:14.511410 TX Vref=22, minBit 3, minWin=24, winSum=404
8097 11:04:14.514662 TX Vref=24, minBit 9, minWin=24, winSum=406
8098 11:04:14.521110 TX Vref=26, minBit 3, minWin=25, winSum=416
8099 11:04:14.524991 TX Vref=28, minBit 1, minWin=26, winSum=421
8100 11:04:14.528013 TX Vref=30, minBit 1, minWin=25, winSum=417
8101 11:04:14.531231 TX Vref=32, minBit 1, minWin=25, winSum=410
8102 11:04:14.534835 TX Vref=34, minBit 13, minWin=23, winSum=399
8103 11:04:14.539789 TX Vref=36, minBit 8, minWin=23, winSum=392
8104 11:04:14.544561 [TxChooseVref] Worse bit 1, Min win 26, Win sum 421, Final Vref 28
8105 11:04:14.544636
8106 11:04:14.547996 Final TX Range 0 Vref 28
8107 11:04:14.548070
8108 11:04:14.548128 ==
8109 11:04:14.552098 Dram Type= 6, Freq= 0, CH_0, rank 1
8110 11:04:14.554689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8111 11:04:14.554764 ==
8112 11:04:14.554822
8113 11:04:14.554876
8114 11:04:14.557910 TX Vref Scan disable
8115 11:04:14.565466 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8116 11:04:14.565542 == TX Byte 0 ==
8117 11:04:14.568634 u2DelayCellOfst[0]=14 cells (4 PI)
8118 11:04:14.571862 u2DelayCellOfst[1]=21 cells (6 PI)
8119 11:04:14.574771 u2DelayCellOfst[2]=10 cells (3 PI)
8120 11:04:14.577895 u2DelayCellOfst[3]=10 cells (3 PI)
8121 11:04:14.581429 u2DelayCellOfst[4]=10 cells (3 PI)
8122 11:04:14.585228 u2DelayCellOfst[5]=0 cells (0 PI)
8123 11:04:14.588685 u2DelayCellOfst[6]=21 cells (6 PI)
8124 11:04:14.591633 u2DelayCellOfst[7]=21 cells (6 PI)
8125 11:04:14.594805 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8126 11:04:14.598340 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8127 11:04:14.601547 == TX Byte 1 ==
8128 11:04:14.604881 u2DelayCellOfst[8]=0 cells (0 PI)
8129 11:04:14.604956 u2DelayCellOfst[9]=0 cells (0 PI)
8130 11:04:14.608453 u2DelayCellOfst[10]=3 cells (1 PI)
8131 11:04:14.611791 u2DelayCellOfst[11]=0 cells (0 PI)
8132 11:04:14.614875 u2DelayCellOfst[12]=10 cells (3 PI)
8133 11:04:14.618866 u2DelayCellOfst[13]=10 cells (3 PI)
8134 11:04:14.621741 u2DelayCellOfst[14]=14 cells (4 PI)
8135 11:04:14.625239 u2DelayCellOfst[15]=10 cells (3 PI)
8136 11:04:14.628491 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8137 11:04:14.635692 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8138 11:04:14.635794 DramC Write-DBI on
8139 11:04:14.635871 ==
8140 11:04:14.639192 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 11:04:14.642219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 11:04:14.642296 ==
8143 11:04:14.645304
8144 11:04:14.645381
8145 11:04:14.645459 TX Vref Scan disable
8146 11:04:14.648696 == TX Byte 0 ==
8147 11:04:14.651994 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8148 11:04:14.655518 == TX Byte 1 ==
8149 11:04:14.658299 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8150 11:04:14.662066 DramC Write-DBI off
8151 11:04:14.662145
8152 11:04:14.662222 [DATLAT]
8153 11:04:14.662294 Freq=1600, CH0 RK1
8154 11:04:14.662364
8155 11:04:14.664913 DATLAT Default: 0xf
8156 11:04:14.664992 0, 0xFFFF, sum = 0
8157 11:04:14.668565 1, 0xFFFF, sum = 0
8158 11:04:14.668643 2, 0xFFFF, sum = 0
8159 11:04:14.671568 3, 0xFFFF, sum = 0
8160 11:04:14.674946 4, 0xFFFF, sum = 0
8161 11:04:14.675046 5, 0xFFFF, sum = 0
8162 11:04:14.678560 6, 0xFFFF, sum = 0
8163 11:04:14.678639 7, 0xFFFF, sum = 0
8164 11:04:14.682045 8, 0xFFFF, sum = 0
8165 11:04:14.682123 9, 0xFFFF, sum = 0
8166 11:04:14.685092 10, 0xFFFF, sum = 0
8167 11:04:14.685216 11, 0xFFFF, sum = 0
8168 11:04:14.688494 12, 0xFFFF, sum = 0
8169 11:04:14.688572 13, 0xFFFF, sum = 0
8170 11:04:14.692208 14, 0x0, sum = 1
8171 11:04:14.692311 15, 0x0, sum = 2
8172 11:04:14.694884 16, 0x0, sum = 3
8173 11:04:14.694988 17, 0x0, sum = 4
8174 11:04:14.698384 best_step = 15
8175 11:04:14.698459
8176 11:04:14.698517 ==
8177 11:04:14.702201 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 11:04:14.705086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 11:04:14.705191 ==
8180 11:04:14.705270 RX Vref Scan: 0
8181 11:04:14.705343
8182 11:04:14.709366 RX Vref 0 -> 0, step: 1
8183 11:04:14.709444
8184 11:04:14.712412 RX Delay 11 -> 252, step: 4
8185 11:04:14.715704 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8186 11:04:14.721753 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8187 11:04:14.725285 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8188 11:04:14.728524 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8189 11:04:14.731745 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8190 11:04:14.735486 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8191 11:04:14.738500 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8192 11:04:14.745609 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8193 11:04:14.748545 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8194 11:04:14.752013 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8195 11:04:14.755077 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8196 11:04:14.758648 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8197 11:04:14.765055 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8198 11:04:14.768494 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8199 11:04:14.772109 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8200 11:04:14.775564 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8201 11:04:14.775640 ==
8202 11:04:14.778630 Dram Type= 6, Freq= 0, CH_0, rank 1
8203 11:04:14.785191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8204 11:04:14.785267 ==
8205 11:04:14.785325 DQS Delay:
8206 11:04:14.788629 DQS0 = 0, DQS1 = 0
8207 11:04:14.788704 DQM Delay:
8208 11:04:14.788763 DQM0 = 126, DQM1 = 122
8209 11:04:14.792554 DQ Delay:
8210 11:04:14.795452 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8211 11:04:14.798715 DQ4 =124, DQ5 =114, DQ6 =134, DQ7 =134
8212 11:04:14.801898 DQ8 =112, DQ9 =112, DQ10 =122, DQ11 =116
8213 11:04:14.805277 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8214 11:04:14.805352
8215 11:04:14.805411
8216 11:04:14.805465
8217 11:04:14.808799 [DramC_TX_OE_Calibration] TA2
8218 11:04:14.812598 Original DQ_B0 (3 6) =30, OEN = 27
8219 11:04:14.815691 Original DQ_B1 (3 6) =30, OEN = 27
8220 11:04:14.818959 24, 0x0, End_B0=24 End_B1=24
8221 11:04:14.819035 25, 0x0, End_B0=25 End_B1=25
8222 11:04:14.822385 26, 0x0, End_B0=26 End_B1=26
8223 11:04:14.825324 27, 0x0, End_B0=27 End_B1=27
8224 11:04:14.828877 28, 0x0, End_B0=28 End_B1=28
8225 11:04:14.828957 29, 0x0, End_B0=29 End_B1=29
8226 11:04:14.832129 30, 0x0, End_B0=30 End_B1=30
8227 11:04:14.835447 31, 0x4545, End_B0=30 End_B1=30
8228 11:04:14.839494 Byte0 end_step=30 best_step=27
8229 11:04:14.842695 Byte1 end_step=30 best_step=27
8230 11:04:14.845888 Byte0 TX OE(2T, 0.5T) = (3, 3)
8231 11:04:14.845964 Byte1 TX OE(2T, 0.5T) = (3, 3)
8232 11:04:14.846023
8233 11:04:14.846078
8234 11:04:14.855849 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
8235 11:04:14.859054 CH0 RK1: MR19=303, MR18=1A0F
8236 11:04:14.862324 CH0_RK1: MR19=0x303, MR18=0x1A0F, DQSOSC=396, MR23=63, INC=23, DEC=15
8237 11:04:14.865997 [RxdqsGatingPostProcess] freq 1600
8238 11:04:14.872069 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8239 11:04:14.875536 best DQS0 dly(2T, 0.5T) = (1, 1)
8240 11:04:14.879653 best DQS1 dly(2T, 0.5T) = (1, 1)
8241 11:04:14.882265 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8242 11:04:14.885659 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8243 11:04:14.888812 best DQS0 dly(2T, 0.5T) = (1, 1)
8244 11:04:14.892156 best DQS1 dly(2T, 0.5T) = (1, 1)
8245 11:04:14.895662 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8246 11:04:14.895737 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8247 11:04:14.899283 Pre-setting of DQS Precalculation
8248 11:04:14.905694 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8249 11:04:14.905773 ==
8250 11:04:14.908786 Dram Type= 6, Freq= 0, CH_1, rank 0
8251 11:04:14.912612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8252 11:04:14.912689 ==
8253 11:04:14.919312 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8254 11:04:14.922566 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8255 11:04:14.926062 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8256 11:04:14.932494 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8257 11:04:14.941639 [CA 0] Center 42 (13~71) winsize 59
8258 11:04:14.944722 [CA 1] Center 42 (13~71) winsize 59
8259 11:04:14.948053 [CA 2] Center 37 (9~66) winsize 58
8260 11:04:14.952069 [CA 3] Center 36 (7~66) winsize 60
8261 11:04:14.955060 [CA 4] Center 36 (7~66) winsize 60
8262 11:04:14.958115 [CA 5] Center 36 (7~65) winsize 59
8263 11:04:14.958191
8264 11:04:14.961645 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8265 11:04:14.961721
8266 11:04:14.964817 [CATrainingPosCal] consider 1 rank data
8267 11:04:14.968747 u2DelayCellTimex100 = 275/100 ps
8268 11:04:14.971686 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8269 11:04:14.978237 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8270 11:04:14.982062 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8271 11:04:14.984885 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8272 11:04:14.988060 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8273 11:04:14.991702 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8274 11:04:14.991778
8275 11:04:14.994748 CA PerBit enable=1, Macro0, CA PI delay=36
8276 11:04:14.994824
8277 11:04:14.998351 [CBTSetCACLKResult] CA Dly = 36
8278 11:04:14.998427 CS Dly: 8 (0~39)
8279 11:04:15.005440 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8280 11:04:15.008203 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8281 11:04:15.008279 ==
8282 11:04:15.012350 Dram Type= 6, Freq= 0, CH_1, rank 1
8283 11:04:15.014911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8284 11:04:15.014988 ==
8285 11:04:15.021331 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8286 11:04:15.025257 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8287 11:04:15.031823 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8288 11:04:15.034878 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8289 11:04:15.045554 [CA 0] Center 43 (14~72) winsize 59
8290 11:04:15.048000 [CA 1] Center 43 (14~72) winsize 59
8291 11:04:15.051465 [CA 2] Center 37 (8~67) winsize 60
8292 11:04:15.054545 [CA 3] Center 37 (8~67) winsize 60
8293 11:04:15.057849 [CA 4] Center 38 (8~68) winsize 61
8294 11:04:15.061109 [CA 5] Center 37 (8~66) winsize 59
8295 11:04:15.061224
8296 11:04:15.064789 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8297 11:04:15.064864
8298 11:04:15.067918 [CATrainingPosCal] consider 2 rank data
8299 11:04:15.070901 u2DelayCellTimex100 = 275/100 ps
8300 11:04:15.075296 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8301 11:04:15.081103 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8302 11:04:15.084232 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8303 11:04:15.088190 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8304 11:04:15.091261 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8305 11:04:15.096220 CA5 delay=36 (8~65),Diff = 0 PI (0 cell)
8306 11:04:15.096294
8307 11:04:15.097889 CA PerBit enable=1, Macro0, CA PI delay=36
8308 11:04:15.097963
8309 11:04:15.101385 [CBTSetCACLKResult] CA Dly = 36
8310 11:04:15.104898 CS Dly: 10 (0~44)
8311 11:04:15.108019 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8312 11:04:15.111181 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8313 11:04:15.111254
8314 11:04:15.114677 ----->DramcWriteLeveling(PI) begin...
8315 11:04:15.114752 ==
8316 11:04:15.118143 Dram Type= 6, Freq= 0, CH_1, rank 0
8317 11:04:15.121420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 11:04:15.121494 ==
8319 11:04:15.124816 Write leveling (Byte 0): 23 => 23
8320 11:04:15.127909 Write leveling (Byte 1): 29 => 29
8321 11:04:15.131169 DramcWriteLeveling(PI) end<-----
8322 11:04:15.131242
8323 11:04:15.131299 ==
8324 11:04:15.134513 Dram Type= 6, Freq= 0, CH_1, rank 0
8325 11:04:15.141509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 11:04:15.141582 ==
8327 11:04:15.141639 [Gating] SW mode calibration
8328 11:04:15.151486 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8329 11:04:15.154749 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8330 11:04:15.157859 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 11:04:15.164595 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 11:04:15.168594 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 11:04:15.171502 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 11:04:15.178095 1 4 16 | B1->B0 | 2727 2424 | 1 0 | (0 0) (0 0)
8335 11:04:15.181544 1 4 20 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
8336 11:04:15.184700 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 11:04:15.191495 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 11:04:15.194997 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 11:04:15.198218 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8340 11:04:15.205368 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8341 11:04:15.208473 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8342 11:04:15.211636 1 5 16 | B1->B0 | 2d2d 3333 | 1 1 | (1 0) (1 0)
8343 11:04:15.215031 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 11:04:15.221978 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 11:04:15.225419 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 11:04:15.228334 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 11:04:15.234831 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 11:04:15.238280 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 11:04:15.242220 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 11:04:15.248696 1 6 16 | B1->B0 | 3e3e 3434 | 1 1 | (0 0) (0 0)
8351 11:04:15.251665 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 11:04:15.255371 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 11:04:15.261685 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 11:04:15.265424 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 11:04:15.268379 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 11:04:15.275454 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 11:04:15.278218 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8358 11:04:15.281952 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8359 11:04:15.285453 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8360 11:04:15.291800 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 11:04:15.295213 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 11:04:15.298550 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 11:04:15.305454 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 11:04:15.308331 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 11:04:15.312139 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 11:04:15.319298 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 11:04:15.322113 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 11:04:15.325598 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 11:04:15.332356 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 11:04:15.335426 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 11:04:15.339022 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 11:04:15.345949 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 11:04:15.348872 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 11:04:15.352473 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8375 11:04:15.356090 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 11:04:15.359264 Total UI for P1: 0, mck2ui 16
8377 11:04:15.362422 best dqsien dly found for B0: ( 1, 9, 16)
8378 11:04:15.366611 Total UI for P1: 0, mck2ui 16
8379 11:04:15.368974 best dqsien dly found for B1: ( 1, 9, 16)
8380 11:04:15.372063 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8381 11:04:15.375647 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8382 11:04:15.379136
8383 11:04:15.382368 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8384 11:04:15.385608 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8385 11:04:15.389362 [Gating] SW calibration Done
8386 11:04:15.389437 ==
8387 11:04:15.392346 Dram Type= 6, Freq= 0, CH_1, rank 0
8388 11:04:15.395549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8389 11:04:15.395623 ==
8390 11:04:15.395681 RX Vref Scan: 0
8391 11:04:15.398790
8392 11:04:15.398869 RX Vref 0 -> 0, step: 1
8393 11:04:15.398927
8394 11:04:15.402381 RX Delay 0 -> 252, step: 8
8395 11:04:15.406002 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8396 11:04:15.408977 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8397 11:04:15.416149 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8398 11:04:15.419302 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8399 11:04:15.422382 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8400 11:04:15.426052 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8401 11:04:15.428833 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8402 11:04:15.432469 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8403 11:04:15.438877 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8404 11:04:15.442327 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8405 11:04:15.445741 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8406 11:04:15.448948 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8407 11:04:15.453573 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8408 11:04:15.459334 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8409 11:04:15.462822 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8410 11:04:15.465846 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8411 11:04:15.465921 ==
8412 11:04:15.469423 Dram Type= 6, Freq= 0, CH_1, rank 0
8413 11:04:15.472198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8414 11:04:15.475834 ==
8415 11:04:15.475908 DQS Delay:
8416 11:04:15.475966 DQS0 = 0, DQS1 = 0
8417 11:04:15.479041 DQM Delay:
8418 11:04:15.479116 DQM0 = 133, DQM1 = 126
8419 11:04:15.482271 DQ Delay:
8420 11:04:15.486251 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8421 11:04:15.488900 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8422 11:04:15.492775 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8423 11:04:15.496005 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8424 11:04:15.496081
8425 11:04:15.496138
8426 11:04:15.496192 ==
8427 11:04:15.499524 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 11:04:15.502354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 11:04:15.502429 ==
8430 11:04:15.502487
8431 11:04:15.502541
8432 11:04:15.505994 TX Vref Scan disable
8433 11:04:15.509338 == TX Byte 0 ==
8434 11:04:15.512859 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8435 11:04:15.516672 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8436 11:04:15.519556 == TX Byte 1 ==
8437 11:04:15.522278 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8438 11:04:15.525804 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8439 11:04:15.525878 ==
8440 11:04:15.529518 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 11:04:15.532845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 11:04:15.532920 ==
8443 11:04:15.548536
8444 11:04:15.551673 TX Vref early break, caculate TX vref
8445 11:04:15.554882 TX Vref=16, minBit 8, minWin=20, winSum=365
8446 11:04:15.558213 TX Vref=18, minBit 8, minWin=21, winSum=375
8447 11:04:15.561600 TX Vref=20, minBit 5, minWin=22, winSum=383
8448 11:04:15.564907 TX Vref=22, minBit 8, minWin=22, winSum=397
8449 11:04:15.568516 TX Vref=24, minBit 8, minWin=23, winSum=402
8450 11:04:15.575203 TX Vref=26, minBit 5, minWin=24, winSum=411
8451 11:04:15.578187 TX Vref=28, minBit 5, minWin=25, winSum=416
8452 11:04:15.581575 TX Vref=30, minBit 9, minWin=25, winSum=418
8453 11:04:15.584951 TX Vref=32, minBit 15, minWin=24, winSum=412
8454 11:04:15.588692 TX Vref=34, minBit 8, minWin=24, winSum=401
8455 11:04:15.591726 TX Vref=36, minBit 8, minWin=23, winSum=391
8456 11:04:15.598312 [TxChooseVref] Worse bit 9, Min win 25, Win sum 418, Final Vref 30
8457 11:04:15.598389
8458 11:04:15.601847 Final TX Range 0 Vref 30
8459 11:04:15.601923
8460 11:04:15.601982 ==
8461 11:04:15.604925 Dram Type= 6, Freq= 0, CH_1, rank 0
8462 11:04:15.608739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8463 11:04:15.608817 ==
8464 11:04:15.608876
8465 11:04:15.608930
8466 11:04:15.612392 TX Vref Scan disable
8467 11:04:15.618733 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8468 11:04:15.618858 == TX Byte 0 ==
8469 11:04:15.622211 u2DelayCellOfst[0]=17 cells (5 PI)
8470 11:04:15.625346 u2DelayCellOfst[1]=10 cells (3 PI)
8471 11:04:15.628566 u2DelayCellOfst[2]=0 cells (0 PI)
8472 11:04:15.632012 u2DelayCellOfst[3]=7 cells (2 PI)
8473 11:04:15.635629 u2DelayCellOfst[4]=7 cells (2 PI)
8474 11:04:15.638450 u2DelayCellOfst[5]=17 cells (5 PI)
8475 11:04:15.641825 u2DelayCellOfst[6]=17 cells (5 PI)
8476 11:04:15.645084 u2DelayCellOfst[7]=7 cells (2 PI)
8477 11:04:15.648730 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8478 11:04:15.651560 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8479 11:04:15.651639 == TX Byte 1 ==
8480 11:04:15.655067 u2DelayCellOfst[8]=0 cells (0 PI)
8481 11:04:15.658503 u2DelayCellOfst[9]=3 cells (1 PI)
8482 11:04:15.661648 u2DelayCellOfst[10]=7 cells (2 PI)
8483 11:04:15.665313 u2DelayCellOfst[11]=3 cells (1 PI)
8484 11:04:15.668598 u2DelayCellOfst[12]=10 cells (3 PI)
8485 11:04:15.671630 u2DelayCellOfst[13]=14 cells (4 PI)
8486 11:04:15.675236 u2DelayCellOfst[14]=14 cells (4 PI)
8487 11:04:15.678209 u2DelayCellOfst[15]=14 cells (4 PI)
8488 11:04:15.682174 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8489 11:04:15.688473 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8490 11:04:15.688559 DramC Write-DBI on
8491 11:04:15.688619 ==
8492 11:04:15.691953 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 11:04:15.695137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 11:04:15.695222 ==
8495 11:04:15.695283
8496 11:04:15.698822
8497 11:04:15.698900 TX Vref Scan disable
8498 11:04:15.701853 == TX Byte 0 ==
8499 11:04:15.705439 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8500 11:04:15.708730 == TX Byte 1 ==
8501 11:04:15.712160 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8502 11:04:15.712258 DramC Write-DBI off
8503 11:04:15.712346
8504 11:04:15.715046 [DATLAT]
8505 11:04:15.715141 Freq=1600, CH1 RK0
8506 11:04:15.715228
8507 11:04:15.719103 DATLAT Default: 0xf
8508 11:04:15.719191 0, 0xFFFF, sum = 0
8509 11:04:15.722152 1, 0xFFFF, sum = 0
8510 11:04:15.722250 2, 0xFFFF, sum = 0
8511 11:04:15.726054 3, 0xFFFF, sum = 0
8512 11:04:15.726158 4, 0xFFFF, sum = 0
8513 11:04:15.728406 5, 0xFFFF, sum = 0
8514 11:04:15.728501 6, 0xFFFF, sum = 0
8515 11:04:15.732666 7, 0xFFFF, sum = 0
8516 11:04:15.732764 8, 0xFFFF, sum = 0
8517 11:04:15.735390 9, 0xFFFF, sum = 0
8518 11:04:15.735487 10, 0xFFFF, sum = 0
8519 11:04:15.739116 11, 0xFFFF, sum = 0
8520 11:04:15.742283 12, 0xFFFF, sum = 0
8521 11:04:15.742382 13, 0xFFFF, sum = 0
8522 11:04:15.745489 14, 0x0, sum = 1
8523 11:04:15.745585 15, 0x0, sum = 2
8524 11:04:15.745671 16, 0x0, sum = 3
8525 11:04:15.748927 17, 0x0, sum = 4
8526 11:04:15.749020 best_step = 15
8527 11:04:15.749103
8528 11:04:15.751959 ==
8529 11:04:15.752051 Dram Type= 6, Freq= 0, CH_1, rank 0
8530 11:04:15.759423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8531 11:04:15.759508 ==
8532 11:04:15.759568 RX Vref Scan: 1
8533 11:04:15.759623
8534 11:04:15.762463 Set Vref Range= 24 -> 127
8535 11:04:15.762540
8536 11:04:15.765875 RX Vref 24 -> 127, step: 1
8537 11:04:15.765952
8538 11:04:15.768805 RX Delay 11 -> 252, step: 4
8539 11:04:15.768906
8540 11:04:15.772110 Set Vref, RX VrefLevel [Byte0]: 24
8541 11:04:15.775557 [Byte1]: 24
8542 11:04:15.775657
8543 11:04:15.778745 Set Vref, RX VrefLevel [Byte0]: 25
8544 11:04:15.781916 [Byte1]: 25
8545 11:04:15.781994
8546 11:04:15.785397 Set Vref, RX VrefLevel [Byte0]: 26
8547 11:04:15.788998 [Byte1]: 26
8548 11:04:15.789075
8549 11:04:15.792568 Set Vref, RX VrefLevel [Byte0]: 27
8550 11:04:15.796089 [Byte1]: 27
8551 11:04:15.799585
8552 11:04:15.799665 Set Vref, RX VrefLevel [Byte0]: 28
8553 11:04:15.802919 [Byte1]: 28
8554 11:04:15.807145
8555 11:04:15.807227 Set Vref, RX VrefLevel [Byte0]: 29
8556 11:04:15.810916 [Byte1]: 29
8557 11:04:15.814890
8558 11:04:15.814975 Set Vref, RX VrefLevel [Byte0]: 30
8559 11:04:15.818321 [Byte1]: 30
8560 11:04:15.822691
8561 11:04:15.822776 Set Vref, RX VrefLevel [Byte0]: 31
8562 11:04:15.826085 [Byte1]: 31
8563 11:04:15.830185
8564 11:04:15.830265 Set Vref, RX VrefLevel [Byte0]: 32
8565 11:04:15.833513 [Byte1]: 32
8566 11:04:15.837806
8567 11:04:15.837885 Set Vref, RX VrefLevel [Byte0]: 33
8568 11:04:15.840762 [Byte1]: 33
8569 11:04:15.845392
8570 11:04:15.845481 Set Vref, RX VrefLevel [Byte0]: 34
8571 11:04:15.848952 [Byte1]: 34
8572 11:04:15.853049
8573 11:04:15.853173 Set Vref, RX VrefLevel [Byte0]: 35
8574 11:04:15.856296 [Byte1]: 35
8575 11:04:15.860308
8576 11:04:15.860386 Set Vref, RX VrefLevel [Byte0]: 36
8577 11:04:15.863514 [Byte1]: 36
8578 11:04:15.868885
8579 11:04:15.868967 Set Vref, RX VrefLevel [Byte0]: 37
8580 11:04:15.871106 [Byte1]: 37
8581 11:04:15.875627
8582 11:04:15.875706 Set Vref, RX VrefLevel [Byte0]: 38
8583 11:04:15.879307 [Byte1]: 38
8584 11:04:15.883702
8585 11:04:15.883781 Set Vref, RX VrefLevel [Byte0]: 39
8586 11:04:15.886747 [Byte1]: 39
8587 11:04:15.891269
8588 11:04:15.891374 Set Vref, RX VrefLevel [Byte0]: 40
8589 11:04:15.894154 [Byte1]: 40
8590 11:04:15.898893
8591 11:04:15.898985 Set Vref, RX VrefLevel [Byte0]: 41
8592 11:04:15.901980 [Byte1]: 41
8593 11:04:15.905854
8594 11:04:15.905939 Set Vref, RX VrefLevel [Byte0]: 42
8595 11:04:15.909384 [Byte1]: 42
8596 11:04:15.913592
8597 11:04:15.913676 Set Vref, RX VrefLevel [Byte0]: 43
8598 11:04:15.916773 [Byte1]: 43
8599 11:04:15.921883
8600 11:04:15.921971 Set Vref, RX VrefLevel [Byte0]: 44
8601 11:04:15.924531 [Byte1]: 44
8602 11:04:15.928874
8603 11:04:15.928964 Set Vref, RX VrefLevel [Byte0]: 45
8604 11:04:15.932277 [Byte1]: 45
8605 11:04:15.936583
8606 11:04:15.936666 Set Vref, RX VrefLevel [Byte0]: 46
8607 11:04:15.940100 [Byte1]: 46
8608 11:04:15.944187
8609 11:04:15.944270 Set Vref, RX VrefLevel [Byte0]: 47
8610 11:04:15.947521 [Byte1]: 47
8611 11:04:15.951658
8612 11:04:15.951741 Set Vref, RX VrefLevel [Byte0]: 48
8613 11:04:15.955412 [Byte1]: 48
8614 11:04:15.959335
8615 11:04:15.959418 Set Vref, RX VrefLevel [Byte0]: 49
8616 11:04:15.962673 [Byte1]: 49
8617 11:04:15.967200
8618 11:04:15.967280 Set Vref, RX VrefLevel [Byte0]: 50
8619 11:04:15.970345 [Byte1]: 50
8620 11:04:15.974500
8621 11:04:15.974585 Set Vref, RX VrefLevel [Byte0]: 51
8622 11:04:15.978162 [Byte1]: 51
8623 11:04:15.982676
8624 11:04:15.982755 Set Vref, RX VrefLevel [Byte0]: 52
8625 11:04:15.985817 [Byte1]: 52
8626 11:04:15.990143
8627 11:04:15.990226 Set Vref, RX VrefLevel [Byte0]: 53
8628 11:04:15.993143 [Byte1]: 53
8629 11:04:15.997528
8630 11:04:15.997605 Set Vref, RX VrefLevel [Byte0]: 54
8631 11:04:16.000587 [Byte1]: 54
8632 11:04:16.004987
8633 11:04:16.005106 Set Vref, RX VrefLevel [Byte0]: 55
8634 11:04:16.008420 [Byte1]: 55
8635 11:04:16.012894
8636 11:04:16.013038 Set Vref, RX VrefLevel [Byte0]: 56
8637 11:04:16.016372 [Byte1]: 56
8638 11:04:16.020155
8639 11:04:16.020239 Set Vref, RX VrefLevel [Byte0]: 57
8640 11:04:16.024043 [Byte1]: 57
8641 11:04:16.028241
8642 11:04:16.028320 Set Vref, RX VrefLevel [Byte0]: 58
8643 11:04:16.032326 [Byte1]: 58
8644 11:04:16.035540
8645 11:04:16.035618 Set Vref, RX VrefLevel [Byte0]: 59
8646 11:04:16.038677 [Byte1]: 59
8647 11:04:16.043425
8648 11:04:16.043513 Set Vref, RX VrefLevel [Byte0]: 60
8649 11:04:16.046694 [Byte1]: 60
8650 11:04:16.050528
8651 11:04:16.050606 Set Vref, RX VrefLevel [Byte0]: 61
8652 11:04:16.053965 [Byte1]: 61
8653 11:04:16.058766
8654 11:04:16.058855 Set Vref, RX VrefLevel [Byte0]: 62
8655 11:04:16.061531 [Byte1]: 62
8656 11:04:16.066511
8657 11:04:16.066598 Set Vref, RX VrefLevel [Byte0]: 63
8658 11:04:16.069350 [Byte1]: 63
8659 11:04:16.074293
8660 11:04:16.074378 Set Vref, RX VrefLevel [Byte0]: 64
8661 11:04:16.077074 [Byte1]: 64
8662 11:04:16.082056
8663 11:04:16.082143 Set Vref, RX VrefLevel [Byte0]: 65
8664 11:04:16.084572 [Byte1]: 65
8665 11:04:16.088757
8666 11:04:16.088839 Set Vref, RX VrefLevel [Byte0]: 66
8667 11:04:16.092109 [Byte1]: 66
8668 11:04:16.096468
8669 11:04:16.096550 Set Vref, RX VrefLevel [Byte0]: 67
8670 11:04:16.099554 [Byte1]: 67
8671 11:04:16.103787
8672 11:04:16.103868 Set Vref, RX VrefLevel [Byte0]: 68
8673 11:04:16.107561 [Byte1]: 68
8674 11:04:16.111469
8675 11:04:16.111552 Set Vref, RX VrefLevel [Byte0]: 69
8676 11:04:16.115357 [Byte1]: 69
8677 11:04:16.119295
8678 11:04:16.119377 Set Vref, RX VrefLevel [Byte0]: 70
8679 11:04:16.122547 [Byte1]: 70
8680 11:04:16.126947
8681 11:04:16.127030 Set Vref, RX VrefLevel [Byte0]: 71
8682 11:04:16.130208 [Byte1]: 71
8683 11:04:16.134352
8684 11:04:16.134432 Set Vref, RX VrefLevel [Byte0]: 72
8685 11:04:16.137933 [Byte1]: 72
8686 11:04:16.141891
8687 11:04:16.141981 Set Vref, RX VrefLevel [Byte0]: 73
8688 11:04:16.145882 [Byte1]: 73
8689 11:04:16.149999
8690 11:04:16.150079 Set Vref, RX VrefLevel [Byte0]: 74
8691 11:04:16.153040 [Byte1]: 74
8692 11:04:16.157518
8693 11:04:16.157606 Set Vref, RX VrefLevel [Byte0]: 75
8694 11:04:16.161055 [Byte1]: 75
8695 11:04:16.165162
8696 11:04:16.165291 Final RX Vref Byte 0 = 59 to rank0
8697 11:04:16.168417 Final RX Vref Byte 1 = 57 to rank0
8698 11:04:16.172219 Final RX Vref Byte 0 = 59 to rank1
8699 11:04:16.174695 Final RX Vref Byte 1 = 57 to rank1==
8700 11:04:16.178352 Dram Type= 6, Freq= 0, CH_1, rank 0
8701 11:04:16.184820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8702 11:04:16.184912 ==
8703 11:04:16.184973 DQS Delay:
8704 11:04:16.185027 DQS0 = 0, DQS1 = 0
8705 11:04:16.188555 DQM Delay:
8706 11:04:16.188632 DQM0 = 131, DQM1 = 124
8707 11:04:16.191247 DQ Delay:
8708 11:04:16.195138 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =128
8709 11:04:16.198078 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8710 11:04:16.201363 DQ8 =110, DQ9 =112, DQ10 =126, DQ11 =118
8711 11:04:16.204961 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8712 11:04:16.205064
8713 11:04:16.205182
8714 11:04:16.205237
8715 11:04:16.208056 [DramC_TX_OE_Calibration] TA2
8716 11:04:16.211464 Original DQ_B0 (3 6) =30, OEN = 27
8717 11:04:16.215356 Original DQ_B1 (3 6) =30, OEN = 27
8718 11:04:16.218153 24, 0x0, End_B0=24 End_B1=24
8719 11:04:16.218236 25, 0x0, End_B0=25 End_B1=25
8720 11:04:16.221574 26, 0x0, End_B0=26 End_B1=26
8721 11:04:16.225557 27, 0x0, End_B0=27 End_B1=27
8722 11:04:16.228597 28, 0x0, End_B0=28 End_B1=28
8723 11:04:16.228679 29, 0x0, End_B0=29 End_B1=29
8724 11:04:16.231650 30, 0x0, End_B0=30 End_B1=30
8725 11:04:16.235257 31, 0x4141, End_B0=30 End_B1=30
8726 11:04:16.239099 Byte0 end_step=30 best_step=27
8727 11:04:16.241928 Byte1 end_step=30 best_step=27
8728 11:04:16.245218 Byte0 TX OE(2T, 0.5T) = (3, 3)
8729 11:04:16.245293 Byte1 TX OE(2T, 0.5T) = (3, 3)
8730 11:04:16.245353
8731 11:04:16.245408
8732 11:04:16.255125 [DQSOSCAuto] RK0, (LSB)MR18= 0x1701, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
8733 11:04:16.258777 CH1 RK0: MR19=303, MR18=1701
8734 11:04:16.262346 CH1_RK0: MR19=0x303, MR18=0x1701, DQSOSC=398, MR23=63, INC=23, DEC=15
8735 11:04:16.265349
8736 11:04:16.268650 ----->DramcWriteLeveling(PI) begin...
8737 11:04:16.268733 ==
8738 11:04:16.271962 Dram Type= 6, Freq= 0, CH_1, rank 1
8739 11:04:16.275356 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8740 11:04:16.275437 ==
8741 11:04:16.278691 Write leveling (Byte 0): 25 => 25
8742 11:04:16.281632 Write leveling (Byte 1): 29 => 29
8743 11:04:16.285288 DramcWriteLeveling(PI) end<-----
8744 11:04:16.285404
8745 11:04:16.285467 ==
8746 11:04:16.288494 Dram Type= 6, Freq= 0, CH_1, rank 1
8747 11:04:16.291901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8748 11:04:16.291985 ==
8749 11:04:16.295814 [Gating] SW mode calibration
8750 11:04:16.301791 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8751 11:04:16.308367 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8752 11:04:16.312196 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 11:04:16.316163 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 11:04:16.319269 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8755 11:04:16.325231 1 4 12 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8756 11:04:16.328822 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 11:04:16.332267 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 11:04:16.338434 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 11:04:16.341862 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 11:04:16.345074 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 11:04:16.352035 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8762 11:04:16.355786 1 5 8 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 1)
8763 11:04:16.359161 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
8764 11:04:16.365550 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 11:04:16.368623 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 11:04:16.372238 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 11:04:16.378980 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 11:04:16.381802 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 11:04:16.385448 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 11:04:16.392352 1 6 8 | B1->B0 | 2424 3838 | 0 1 | (0 0) (0 0)
8771 11:04:16.395533 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8772 11:04:16.398801 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 11:04:16.402053 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 11:04:16.409383 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 11:04:16.412301 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 11:04:16.415550 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 11:04:16.421995 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8778 11:04:16.425316 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8779 11:04:16.428576 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8780 11:04:16.435253 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8781 11:04:16.439146 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 11:04:16.442749 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 11:04:16.448699 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 11:04:16.452243 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 11:04:16.454985 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 11:04:16.461634 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 11:04:16.465215 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 11:04:16.468899 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 11:04:16.475085 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 11:04:16.478756 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 11:04:16.482101 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 11:04:16.488420 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 11:04:16.492666 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8794 11:04:16.495430 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8795 11:04:16.499356 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8796 11:04:16.502065 Total UI for P1: 0, mck2ui 16
8797 11:04:16.505467 best dqsien dly found for B0: ( 1, 9, 6)
8798 11:04:16.512264 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8799 11:04:16.516050 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 11:04:16.519139 Total UI for P1: 0, mck2ui 16
8801 11:04:16.522297 best dqsien dly found for B1: ( 1, 9, 14)
8802 11:04:16.525507 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8803 11:04:16.529315 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8804 11:04:16.529411
8805 11:04:16.532506 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8806 11:04:16.535782 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8807 11:04:16.539168 [Gating] SW calibration Done
8808 11:04:16.539271 ==
8809 11:04:16.542298 Dram Type= 6, Freq= 0, CH_1, rank 1
8810 11:04:16.545455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8811 11:04:16.549440 ==
8812 11:04:16.549540 RX Vref Scan: 0
8813 11:04:16.549628
8814 11:04:16.552012 RX Vref 0 -> 0, step: 1
8815 11:04:16.552104
8816 11:04:16.552190 RX Delay 0 -> 252, step: 8
8817 11:04:16.559346 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8818 11:04:16.562617 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8819 11:04:16.565837 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8820 11:04:16.568895 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8821 11:04:16.572291 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8822 11:04:16.579182 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8823 11:04:16.582347 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8824 11:04:16.585714 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8825 11:04:16.589008 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8826 11:04:16.592241 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8827 11:04:16.599515 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8828 11:04:16.602593 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8829 11:04:16.605872 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8830 11:04:16.609518 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8831 11:04:16.612794 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8832 11:04:16.619584 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8833 11:04:16.619683 ==
8834 11:04:16.622472 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 11:04:16.625901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 11:04:16.625980 ==
8837 11:04:16.626040 DQS Delay:
8838 11:04:16.629807 DQS0 = 0, DQS1 = 0
8839 11:04:16.629885 DQM Delay:
8840 11:04:16.633305 DQM0 = 131, DQM1 = 128
8841 11:04:16.633383 DQ Delay:
8842 11:04:16.635768 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8843 11:04:16.639129 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =127
8844 11:04:16.643032 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8845 11:04:16.645716 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8846 11:04:16.645795
8847 11:04:16.645853
8848 11:04:16.649147 ==
8849 11:04:16.649239 Dram Type= 6, Freq= 0, CH_1, rank 1
8850 11:04:16.655813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8851 11:04:16.655904 ==
8852 11:04:16.655964
8853 11:04:16.656018
8854 11:04:16.659523 TX Vref Scan disable
8855 11:04:16.659600 == TX Byte 0 ==
8856 11:04:16.663074 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8857 11:04:16.669689 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8858 11:04:16.669792 == TX Byte 1 ==
8859 11:04:16.672697 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8860 11:04:16.679573 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8861 11:04:16.679676 ==
8862 11:04:16.682429 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 11:04:16.685573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 11:04:16.685665 ==
8865 11:04:16.699872
8866 11:04:16.703563 TX Vref early break, caculate TX vref
8867 11:04:16.707090 TX Vref=16, minBit 8, minWin=22, winSum=379
8868 11:04:16.710320 TX Vref=18, minBit 8, minWin=22, winSum=385
8869 11:04:16.713942 TX Vref=20, minBit 8, minWin=22, winSum=396
8870 11:04:16.716619 TX Vref=22, minBit 8, minWin=24, winSum=402
8871 11:04:16.719795 TX Vref=24, minBit 8, minWin=24, winSum=414
8872 11:04:16.726503 TX Vref=26, minBit 6, minWin=25, winSum=416
8873 11:04:16.730363 TX Vref=28, minBit 0, minWin=25, winSum=417
8874 11:04:16.733264 TX Vref=30, minBit 0, minWin=25, winSum=417
8875 11:04:16.736722 TX Vref=32, minBit 8, minWin=24, winSum=414
8876 11:04:16.740212 TX Vref=34, minBit 8, minWin=24, winSum=405
8877 11:04:16.743660 TX Vref=36, minBit 0, minWin=23, winSum=394
8878 11:04:16.750283 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
8879 11:04:16.750380
8880 11:04:16.754292 Final TX Range 0 Vref 28
8881 11:04:16.754372
8882 11:04:16.754430 ==
8883 11:04:16.756754 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 11:04:16.760175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 11:04:16.760257 ==
8886 11:04:16.760316
8887 11:04:16.760370
8888 11:04:16.764178 TX Vref Scan disable
8889 11:04:16.770386 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8890 11:04:16.770487 == TX Byte 0 ==
8891 11:04:16.773139 u2DelayCellOfst[0]=17 cells (5 PI)
8892 11:04:16.777040 u2DelayCellOfst[1]=10 cells (3 PI)
8893 11:04:16.780309 u2DelayCellOfst[2]=0 cells (0 PI)
8894 11:04:16.783853 u2DelayCellOfst[3]=7 cells (2 PI)
8895 11:04:16.786930 u2DelayCellOfst[4]=10 cells (3 PI)
8896 11:04:16.789827 u2DelayCellOfst[5]=17 cells (5 PI)
8897 11:04:16.793379 u2DelayCellOfst[6]=17 cells (5 PI)
8898 11:04:16.797299 u2DelayCellOfst[7]=3 cells (1 PI)
8899 11:04:16.799982 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8900 11:04:16.803404 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8901 11:04:16.803484 == TX Byte 1 ==
8902 11:04:16.807051 u2DelayCellOfst[8]=0 cells (0 PI)
8903 11:04:16.810018 u2DelayCellOfst[9]=0 cells (0 PI)
8904 11:04:16.813318 u2DelayCellOfst[10]=7 cells (2 PI)
8905 11:04:16.816963 u2DelayCellOfst[11]=0 cells (0 PI)
8906 11:04:16.820088 u2DelayCellOfst[12]=10 cells (3 PI)
8907 11:04:16.824003 u2DelayCellOfst[13]=10 cells (3 PI)
8908 11:04:16.827133 u2DelayCellOfst[14]=14 cells (4 PI)
8909 11:04:16.830001 u2DelayCellOfst[15]=14 cells (4 PI)
8910 11:04:16.833995 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8911 11:04:16.836974 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8912 11:04:16.840507 DramC Write-DBI on
8913 11:04:16.840586 ==
8914 11:04:16.843921 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 11:04:16.846965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 11:04:16.847043 ==
8917 11:04:16.847102
8918 11:04:16.847155
8919 11:04:16.850535 TX Vref Scan disable
8920 11:04:16.853631 == TX Byte 0 ==
8921 11:04:16.857162 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8922 11:04:16.860289 == TX Byte 1 ==
8923 11:04:16.863736 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8924 11:04:16.863819 DramC Write-DBI off
8925 11:04:16.863877
8926 11:04:16.867507 [DATLAT]
8927 11:04:16.867587 Freq=1600, CH1 RK1
8928 11:04:16.867647
8929 11:04:16.870374 DATLAT Default: 0xf
8930 11:04:16.870451 0, 0xFFFF, sum = 0
8931 11:04:16.873863 1, 0xFFFF, sum = 0
8932 11:04:16.873941 2, 0xFFFF, sum = 0
8933 11:04:16.877366 3, 0xFFFF, sum = 0
8934 11:04:16.877449 4, 0xFFFF, sum = 0
8935 11:04:16.880545 5, 0xFFFF, sum = 0
8936 11:04:16.880622 6, 0xFFFF, sum = 0
8937 11:04:16.884151 7, 0xFFFF, sum = 0
8938 11:04:16.884228 8, 0xFFFF, sum = 0
8939 11:04:16.887044 9, 0xFFFF, sum = 0
8940 11:04:16.887120 10, 0xFFFF, sum = 0
8941 11:04:16.890477 11, 0xFFFF, sum = 0
8942 11:04:16.893617 12, 0xFFFF, sum = 0
8943 11:04:16.893697 13, 0xFFFF, sum = 0
8944 11:04:16.897162 14, 0x0, sum = 1
8945 11:04:16.897241 15, 0x0, sum = 2
8946 11:04:16.897301 16, 0x0, sum = 3
8947 11:04:16.900367 17, 0x0, sum = 4
8948 11:04:16.900445 best_step = 15
8949 11:04:16.900503
8950 11:04:16.904281 ==
8951 11:04:16.904358 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 11:04:16.910266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 11:04:16.910360 ==
8954 11:04:16.910476 RX Vref Scan: 0
8955 11:04:16.910533
8956 11:04:16.914101 RX Vref 0 -> 0, step: 1
8957 11:04:16.914178
8958 11:04:16.917816 RX Delay 11 -> 252, step: 4
8959 11:04:16.920814 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8960 11:04:16.924118 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8961 11:04:16.930839 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8962 11:04:16.933840 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8963 11:04:16.937185 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8964 11:04:16.940854 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8965 11:04:16.944033 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8966 11:04:16.947679 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8967 11:04:16.954173 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8968 11:04:16.957679 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8969 11:04:16.960996 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8970 11:04:16.963778 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8971 11:04:16.967148 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8972 11:04:16.974060 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8973 11:04:16.977531 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8974 11:04:16.980924 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8975 11:04:16.981030 ==
8976 11:04:16.984048 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 11:04:16.988098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 11:04:16.988191 ==
8979 11:04:16.990913 DQS Delay:
8980 11:04:16.990993 DQS0 = 0, DQS1 = 0
8981 11:04:16.994566 DQM Delay:
8982 11:04:16.994645 DQM0 = 129, DQM1 = 126
8983 11:04:16.997456 DQ Delay:
8984 11:04:17.000562 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
8985 11:04:17.004348 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126
8986 11:04:17.007366 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =120
8987 11:04:17.010743 DQ12 =134, DQ13 =134, DQ14 =132, DQ15 =136
8988 11:04:17.010829
8989 11:04:17.010890
8990 11:04:17.010944
8991 11:04:17.013977 [DramC_TX_OE_Calibration] TA2
8992 11:04:17.017251 Original DQ_B0 (3 6) =30, OEN = 27
8993 11:04:17.020636 Original DQ_B1 (3 6) =30, OEN = 27
8994 11:04:17.020736 24, 0x0, End_B0=24 End_B1=24
8995 11:04:17.023942 25, 0x0, End_B0=25 End_B1=25
8996 11:04:17.027167 26, 0x0, End_B0=26 End_B1=26
8997 11:04:17.030666 27, 0x0, End_B0=27 End_B1=27
8998 11:04:17.034218 28, 0x0, End_B0=28 End_B1=28
8999 11:04:17.034308 29, 0x0, End_B0=29 End_B1=29
9000 11:04:17.037519 30, 0x0, End_B0=30 End_B1=30
9001 11:04:17.040665 31, 0x4141, End_B0=30 End_B1=30
9002 11:04:17.044071 Byte0 end_step=30 best_step=27
9003 11:04:17.047691 Byte1 end_step=30 best_step=27
9004 11:04:17.047790 Byte0 TX OE(2T, 0.5T) = (3, 3)
9005 11:04:17.050671 Byte1 TX OE(2T, 0.5T) = (3, 3)
9006 11:04:17.050754
9007 11:04:17.050814
9008 11:04:17.061260 [DQSOSCAuto] RK1, (LSB)MR18= 0x1116, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9009 11:04:17.064087 CH1 RK1: MR19=303, MR18=1116
9010 11:04:17.067595 CH1_RK1: MR19=0x303, MR18=0x1116, DQSOSC=398, MR23=63, INC=23, DEC=15
9011 11:04:17.070901 [RxdqsGatingPostProcess] freq 1600
9012 11:04:17.077802 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9013 11:04:17.080876 best DQS0 dly(2T, 0.5T) = (1, 1)
9014 11:04:17.084677 best DQS1 dly(2T, 0.5T) = (1, 1)
9015 11:04:17.088023 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9016 11:04:17.091968 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9017 11:04:17.092126 best DQS0 dly(2T, 0.5T) = (1, 1)
9018 11:04:17.094739 best DQS1 dly(2T, 0.5T) = (1, 1)
9019 11:04:17.098026 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9020 11:04:17.101334 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9021 11:04:17.104463 Pre-setting of DQS Precalculation
9022 11:04:17.111347 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9023 11:04:17.118230 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9024 11:04:17.124754 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9025 11:04:17.124862
9026 11:04:17.124922
9027 11:04:17.127857 [Calibration Summary] 3200 Mbps
9028 11:04:17.127938 CH 0, Rank 0
9029 11:04:17.131167 SW Impedance : PASS
9030 11:04:17.135157 DUTY Scan : NO K
9031 11:04:17.135269 ZQ Calibration : PASS
9032 11:04:17.137504 Jitter Meter : NO K
9033 11:04:17.141144 CBT Training : PASS
9034 11:04:17.141266 Write leveling : PASS
9035 11:04:17.144460 RX DQS gating : PASS
9036 11:04:17.144560 RX DQ/DQS(RDDQC) : PASS
9037 11:04:17.148014 TX DQ/DQS : PASS
9038 11:04:17.151425 RX DATLAT : PASS
9039 11:04:17.151559 RX DQ/DQS(Engine): PASS
9040 11:04:17.154583 TX OE : PASS
9041 11:04:17.154663 All Pass.
9042 11:04:17.154722
9043 11:04:17.158198 CH 0, Rank 1
9044 11:04:17.158304 SW Impedance : PASS
9045 11:04:17.161284 DUTY Scan : NO K
9046 11:04:17.165048 ZQ Calibration : PASS
9047 11:04:17.165191 Jitter Meter : NO K
9048 11:04:17.168126 CBT Training : PASS
9049 11:04:17.171302 Write leveling : PASS
9050 11:04:17.171386 RX DQS gating : PASS
9051 11:04:17.174759 RX DQ/DQS(RDDQC) : PASS
9052 11:04:17.178042 TX DQ/DQS : PASS
9053 11:04:17.178143 RX DATLAT : PASS
9054 11:04:17.181428 RX DQ/DQS(Engine): PASS
9055 11:04:17.181524 TX OE : PASS
9056 11:04:17.185000 All Pass.
9057 11:04:17.185098
9058 11:04:17.185206 CH 1, Rank 0
9059 11:04:17.188613 SW Impedance : PASS
9060 11:04:17.188693 DUTY Scan : NO K
9061 11:04:17.191630 ZQ Calibration : PASS
9062 11:04:17.194491 Jitter Meter : NO K
9063 11:04:17.194570 CBT Training : PASS
9064 11:04:17.198524 Write leveling : PASS
9065 11:04:17.201501 RX DQS gating : PASS
9066 11:04:17.201584 RX DQ/DQS(RDDQC) : PASS
9067 11:04:17.205028 TX DQ/DQS : PASS
9068 11:04:17.207845 RX DATLAT : PASS
9069 11:04:17.207976 RX DQ/DQS(Engine): PASS
9070 11:04:17.211113 TX OE : PASS
9071 11:04:17.211237 All Pass.
9072 11:04:17.211298
9073 11:04:17.214843 CH 1, Rank 1
9074 11:04:17.214955 SW Impedance : PASS
9075 11:04:17.218142 DUTY Scan : NO K
9076 11:04:17.221246 ZQ Calibration : PASS
9077 11:04:17.221349 Jitter Meter : NO K
9078 11:04:17.225043 CBT Training : PASS
9079 11:04:17.225128 Write leveling : PASS
9080 11:04:17.228134 RX DQS gating : PASS
9081 11:04:17.231271 RX DQ/DQS(RDDQC) : PASS
9082 11:04:17.231379 TX DQ/DQS : PASS
9083 11:04:17.234549 RX DATLAT : PASS
9084 11:04:17.238306 RX DQ/DQS(Engine): PASS
9085 11:04:17.238450 TX OE : PASS
9086 11:04:17.241690 All Pass.
9087 11:04:17.241795
9088 11:04:17.241886 DramC Write-DBI on
9089 11:04:17.244852 PER_BANK_REFRESH: Hybrid Mode
9090 11:04:17.244953 TX_TRACKING: ON
9091 11:04:17.254743 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9092 11:04:17.261963 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9093 11:04:17.271534 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9094 11:04:17.274967 [FAST_K] Save calibration result to emmc
9095 11:04:17.278207 sync common calibartion params.
9096 11:04:17.278289 sync cbt_mode0:1, 1:1
9097 11:04:17.281632 dram_init: ddr_geometry: 2
9098 11:04:17.285174 dram_init: ddr_geometry: 2
9099 11:04:17.285256 dram_init: ddr_geometry: 2
9100 11:04:17.288137 0:dram_rank_size:100000000
9101 11:04:17.291593 1:dram_rank_size:100000000
9102 11:04:17.295076 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9103 11:04:17.298306 DFS_SHUFFLE_HW_MODE: ON
9104 11:04:17.301671 dramc_set_vcore_voltage set vcore to 725000
9105 11:04:17.304951 Read voltage for 1600, 0
9106 11:04:17.305055 Vio18 = 0
9107 11:04:17.308073 Vcore = 725000
9108 11:04:17.308163 Vdram = 0
9109 11:04:17.308300 Vddq = 0
9110 11:04:17.308401 Vmddr = 0
9111 11:04:17.312007 switch to 3200 Mbps bootup
9112 11:04:17.315484 [DramcRunTimeConfig]
9113 11:04:17.315566 PHYPLL
9114 11:04:17.318504 DPM_CONTROL_AFTERK: ON
9115 11:04:17.318584 PER_BANK_REFRESH: ON
9116 11:04:17.322181 REFRESH_OVERHEAD_REDUCTION: ON
9117 11:04:17.325058 CMD_PICG_NEW_MODE: OFF
9118 11:04:17.325179 XRTWTW_NEW_MODE: ON
9119 11:04:17.328744 XRTRTR_NEW_MODE: ON
9120 11:04:17.328821 TX_TRACKING: ON
9121 11:04:17.331997 RDSEL_TRACKING: OFF
9122 11:04:17.332075 DQS Precalculation for DVFS: ON
9123 11:04:17.335015 RX_TRACKING: OFF
9124 11:04:17.335093 HW_GATING DBG: ON
9125 11:04:17.338696 ZQCS_ENABLE_LP4: ON
9126 11:04:17.341579 RX_PICG_NEW_MODE: ON
9127 11:04:17.341657 TX_PICG_NEW_MODE: ON
9128 11:04:17.345369 ENABLE_RX_DCM_DPHY: ON
9129 11:04:17.348676 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9130 11:04:17.348795 DUMMY_READ_FOR_TRACKING: OFF
9131 11:04:17.352661 !!! SPM_CONTROL_AFTERK: OFF
9132 11:04:17.355301 !!! SPM could not control APHY
9133 11:04:17.358882 IMPEDANCE_TRACKING: ON
9134 11:04:17.358964 TEMP_SENSOR: ON
9135 11:04:17.361630 HW_SAVE_FOR_SR: OFF
9136 11:04:17.361710 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9137 11:04:17.368411 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9138 11:04:17.368508 Read ODT Tracking: ON
9139 11:04:17.371750 Refresh Rate DeBounce: ON
9140 11:04:17.375010 DFS_NO_QUEUE_FLUSH: ON
9141 11:04:17.375094 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9142 11:04:17.378512 ENABLE_DFS_RUNTIME_MRW: OFF
9143 11:04:17.382717 DDR_RESERVE_NEW_MODE: ON
9144 11:04:17.382802 MR_CBT_SWITCH_FREQ: ON
9145 11:04:17.385104 =========================
9146 11:04:17.405113 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9147 11:04:17.408394 dram_init: ddr_geometry: 2
9148 11:04:17.426318 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9149 11:04:17.429394 dram_init: dram init end (result: 0)
9150 11:04:17.436410 DRAM-K: Full calibration passed in 24537 msecs
9151 11:04:17.439487 MRC: failed to locate region type 0.
9152 11:04:17.439583 DRAM rank0 size:0x100000000,
9153 11:04:17.442873 DRAM rank1 size=0x100000000
9154 11:04:17.453746 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9155 11:04:17.459677 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9156 11:04:17.466604 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9157 11:04:17.473029 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9158 11:04:17.476181 DRAM rank0 size:0x100000000,
9159 11:04:17.479440 DRAM rank1 size=0x100000000
9160 11:04:17.479525 CBMEM:
9161 11:04:17.483202 IMD: root @ 0xfffff000 254 entries.
9162 11:04:17.486384 IMD: root @ 0xffffec00 62 entries.
9163 11:04:17.489536 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9164 11:04:17.492738 WARNING: RO_VPD is uninitialized or empty.
9165 11:04:17.499813 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9166 11:04:17.507100 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9167 11:04:17.518946 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9168 11:04:17.530447 BS: romstage times (exec / console): total (unknown) / 24011 ms
9169 11:04:17.530563
9170 11:04:17.530626
9171 11:04:17.540375 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9172 11:04:17.543924 ARM64: Exception handlers installed.
9173 11:04:17.547073 ARM64: Testing exception
9174 11:04:17.550681 ARM64: Done test exception
9175 11:04:17.550765 Enumerating buses...
9176 11:04:17.553944 Show all devs... Before device enumeration.
9177 11:04:17.557353 Root Device: enabled 1
9178 11:04:17.561403 CPU_CLUSTER: 0: enabled 1
9179 11:04:17.561487 CPU: 00: enabled 1
9180 11:04:17.563607 Compare with tree...
9181 11:04:17.563684 Root Device: enabled 1
9182 11:04:17.566878 CPU_CLUSTER: 0: enabled 1
9183 11:04:17.571108 CPU: 00: enabled 1
9184 11:04:17.571194 Root Device scanning...
9185 11:04:17.574795 scan_static_bus for Root Device
9186 11:04:17.577839 CPU_CLUSTER: 0 enabled
9187 11:04:17.580838 scan_static_bus for Root Device done
9188 11:04:17.584387 scan_bus: bus Root Device finished in 8 msecs
9189 11:04:17.584473 done
9190 11:04:17.590443 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9191 11:04:17.593805 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9192 11:04:17.600716 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9193 11:04:17.604226 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9194 11:04:17.607410 Allocating resources...
9195 11:04:17.607495 Reading resources...
9196 11:04:17.613713 Root Device read_resources bus 0 link: 0
9197 11:04:17.613810 DRAM rank0 size:0x100000000,
9198 11:04:17.617244 DRAM rank1 size=0x100000000
9199 11:04:17.620802 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9200 11:04:17.624398 CPU: 00 missing read_resources
9201 11:04:17.627314 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9202 11:04:17.633744 Root Device read_resources bus 0 link: 0 done
9203 11:04:17.633852 Done reading resources.
9204 11:04:17.640418 Show resources in subtree (Root Device)...After reading.
9205 11:04:17.645036 Root Device child on link 0 CPU_CLUSTER: 0
9206 11:04:17.647115 CPU_CLUSTER: 0 child on link 0 CPU: 00
9207 11:04:17.657357 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9208 11:04:17.657539 CPU: 00
9209 11:04:17.660636 Root Device assign_resources, bus 0 link: 0
9210 11:04:17.664446 CPU_CLUSTER: 0 missing set_resources
9211 11:04:17.668066 Root Device assign_resources, bus 0 link: 0 done
9212 11:04:17.670892 Done setting resources.
9213 11:04:17.677495 Show resources in subtree (Root Device)...After assigning values.
9214 11:04:17.680898 Root Device child on link 0 CPU_CLUSTER: 0
9215 11:04:17.684406 CPU_CLUSTER: 0 child on link 0 CPU: 00
9216 11:04:17.693954 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9217 11:04:17.694073 CPU: 00
9218 11:04:17.697558 Done allocating resources.
9219 11:04:17.700805 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9220 11:04:17.704319 Enabling resources...
9221 11:04:17.704425 done.
9222 11:04:17.707219 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9223 11:04:17.710763 Initializing devices...
9224 11:04:17.710866 Root Device init
9225 11:04:17.714151 init hardware done!
9226 11:04:17.717868 0x00000018: ctrlr->caps
9227 11:04:17.717966 52.000 MHz: ctrlr->f_max
9228 11:04:17.720822 0.400 MHz: ctrlr->f_min
9229 11:04:17.723944 0x40ff8080: ctrlr->voltages
9230 11:04:17.724030 sclk: 390625
9231 11:04:17.724090 Bus Width = 1
9232 11:04:17.727586 sclk: 390625
9233 11:04:17.727664 Bus Width = 1
9234 11:04:17.730523 Early init status = 3
9235 11:04:17.734896 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9236 11:04:17.738160 in-header: 03 fc 00 00 01 00 00 00
9237 11:04:17.741499 in-data: 00
9238 11:04:17.744532 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9239 11:04:17.749807 in-header: 03 fd 00 00 00 00 00 00
9240 11:04:17.753503 in-data:
9241 11:04:17.756149 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9242 11:04:17.760788 in-header: 03 fc 00 00 01 00 00 00
9243 11:04:17.764019 in-data: 00
9244 11:04:17.767544 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9245 11:04:17.773375 in-header: 03 fd 00 00 00 00 00 00
9246 11:04:17.776429 in-data:
9247 11:04:17.779369 [SSUSB] Setting up USB HOST controller...
9248 11:04:17.782549 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9249 11:04:17.786607 [SSUSB] phy power-on done.
9250 11:04:17.789581 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9251 11:04:17.796122 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9252 11:04:17.799875 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9253 11:04:17.806204 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9254 11:04:17.813019 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9255 11:04:17.820065 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9256 11:04:17.826434 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9257 11:04:17.833451 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9258 11:04:17.833560 SPM: binary array size = 0x9dc
9259 11:04:17.839737 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9260 11:04:17.846708 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9261 11:04:17.853170 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9262 11:04:17.856080 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9263 11:04:17.859880 configure_display: Starting display init
9264 11:04:17.896061 anx7625_power_on_init: Init interface.
9265 11:04:17.900064 anx7625_disable_pd_protocol: Disabled PD feature.
9266 11:04:17.903054 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9267 11:04:17.930985 anx7625_start_dp_work: Secure OCM version=00
9268 11:04:17.934141 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9269 11:04:17.948759 sp_tx_get_edid_block: EDID Block = 1
9270 11:04:18.051097 Extracted contents:
9271 11:04:18.054858 header: 00 ff ff ff ff ff ff 00
9272 11:04:18.058280 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9273 11:04:18.061444 version: 01 04
9274 11:04:18.064853 basic params: 95 1f 11 78 0a
9275 11:04:18.068036 chroma info: 76 90 94 55 54 90 27 21 50 54
9276 11:04:18.071362 established: 00 00 00
9277 11:04:18.077749 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9278 11:04:18.081107 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9279 11:04:18.088034 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9280 11:04:18.094276 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9281 11:04:18.101209 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9282 11:04:18.105305 extensions: 00
9283 11:04:18.105400 checksum: fb
9284 11:04:18.105493
9285 11:04:18.107598 Manufacturer: IVO Model 57d Serial Number 0
9286 11:04:18.111234 Made week 0 of 2020
9287 11:04:18.111319 EDID version: 1.4
9288 11:04:18.115310 Digital display
9289 11:04:18.118205 6 bits per primary color channel
9290 11:04:18.118288 DisplayPort interface
9291 11:04:18.121344 Maximum image size: 31 cm x 17 cm
9292 11:04:18.121425 Gamma: 220%
9293 11:04:18.124633 Check DPMS levels
9294 11:04:18.128029 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9295 11:04:18.131183 First detailed timing is preferred timing
9296 11:04:18.134451 Established timings supported:
9297 11:04:18.138167 Standard timings supported:
9298 11:04:18.138263 Detailed timings
9299 11:04:18.144770 Hex of detail: 383680a07038204018303c0035ae10000019
9300 11:04:18.148083 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9301 11:04:18.151180 0780 0798 07c8 0820 hborder 0
9302 11:04:18.157973 0438 043b 0447 0458 vborder 0
9303 11:04:18.158071 -hsync -vsync
9304 11:04:18.161515 Did detailed timing
9305 11:04:18.164642 Hex of detail: 000000000000000000000000000000000000
9306 11:04:18.168559 Manufacturer-specified data, tag 0
9307 11:04:18.174363 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9308 11:04:18.174458 ASCII string: InfoVision
9309 11:04:18.181215 Hex of detail: 000000fe00523134304e574635205248200a
9310 11:04:18.181314 ASCII string: R140NWF5 RH
9311 11:04:18.184244 Checksum
9312 11:04:18.184345 Checksum: 0xfb (valid)
9313 11:04:18.191161 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9314 11:04:18.191259 DSI data_rate: 832800000 bps
9315 11:04:18.198836 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9316 11:04:18.202496 anx7625_parse_edid: pixelclock(138800).
9317 11:04:18.205277 hactive(1920), hsync(48), hfp(24), hbp(88)
9318 11:04:18.209319 vactive(1080), vsync(12), vfp(3), vbp(17)
9319 11:04:18.212150 anx7625_dsi_config: config dsi.
9320 11:04:18.218947 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9321 11:04:18.233299 anx7625_dsi_config: success to config DSI
9322 11:04:18.237077 anx7625_dp_start: MIPI phy setup OK.
9323 11:04:18.240079 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9324 11:04:18.243461 mtk_ddp_mode_set invalid vrefresh 60
9325 11:04:18.246720 main_disp_path_setup
9326 11:04:18.246803 ovl_layer_smi_id_en
9327 11:04:18.250187 ovl_layer_smi_id_en
9328 11:04:18.250268 ccorr_config
9329 11:04:18.250327 aal_config
9330 11:04:18.253267 gamma_config
9331 11:04:18.253345 postmask_config
9332 11:04:18.256601 dither_config
9333 11:04:18.259954 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9334 11:04:18.266481 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9335 11:04:18.270107 Root Device init finished in 553 msecs
9336 11:04:18.270205 CPU_CLUSTER: 0 init
9337 11:04:18.279847 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9338 11:04:18.283514 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9339 11:04:18.286611 APU_MBOX 0x190000b0 = 0x10001
9340 11:04:18.290662 APU_MBOX 0x190001b0 = 0x10001
9341 11:04:18.293436 APU_MBOX 0x190005b0 = 0x10001
9342 11:04:18.296597 APU_MBOX 0x190006b0 = 0x10001
9343 11:04:18.299966 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9344 11:04:18.312111 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9345 11:04:18.325282 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9346 11:04:18.331090 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9347 11:04:18.343308 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9348 11:04:18.352230 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9349 11:04:18.355316 CPU_CLUSTER: 0 init finished in 81 msecs
9350 11:04:18.358441 Devices initialized
9351 11:04:18.362056 Show all devs... After init.
9352 11:04:18.362139 Root Device: enabled 1
9353 11:04:18.365219 CPU_CLUSTER: 0: enabled 1
9354 11:04:18.368646 CPU: 00: enabled 1
9355 11:04:18.371838 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9356 11:04:18.375476 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9357 11:04:18.378537 ELOG: NV offset 0x57f000 size 0x1000
9358 11:04:18.385343 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9359 11:04:18.391968 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9360 11:04:18.395127 ELOG: Event(17) added with size 13 at 2024-07-10 11:04:18 UTC
9361 11:04:18.398911 out: cmd=0x121: 03 db 21 01 00 00 00 00
9362 11:04:18.403416 in-header: 03 f9 00 00 2c 00 00 00
9363 11:04:18.416597 in-data: 44 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9364 11:04:18.423459 ELOG: Event(A1) added with size 10 at 2024-07-10 11:04:18 UTC
9365 11:04:18.430465 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9366 11:04:18.436516 ELOG: Event(A0) added with size 9 at 2024-07-10 11:04:18 UTC
9367 11:04:18.439855 elog_add_boot_reason: Logged dev mode boot
9368 11:04:18.443483 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9369 11:04:18.446807 Finalize devices...
9370 11:04:18.446894 Devices finalized
9371 11:04:18.453887 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9372 11:04:18.456655 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9373 11:04:18.459915 in-header: 03 07 00 00 08 00 00 00
9374 11:04:18.463359 in-data: aa e4 47 04 13 02 00 00
9375 11:04:18.466928 Chrome EC: UHEPI supported
9376 11:04:18.473623 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9377 11:04:18.477015 in-header: 03 a9 00 00 08 00 00 00
9378 11:04:18.479867 in-data: 84 60 60 08 00 00 00 00
9379 11:04:18.484154 ELOG: Event(91) added with size 10 at 2024-07-10 11:04:18 UTC
9380 11:04:18.490011 Chrome EC: clear events_b mask to 0x0000000020004000
9381 11:04:18.496951 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9382 11:04:18.500873 in-header: 03 fd 00 00 00 00 00 00
9383 11:04:18.503695 in-data:
9384 11:04:18.507199 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9385 11:04:18.510200 Writing coreboot table at 0xffe64000
9386 11:04:18.514332 0. 000000000010a000-0000000000113fff: RAMSTAGE
9387 11:04:18.517085 1. 0000000040000000-00000000400fffff: RAM
9388 11:04:18.523551 2. 0000000040100000-000000004032afff: RAMSTAGE
9389 11:04:18.527168 3. 000000004032b000-00000000545fffff: RAM
9390 11:04:18.531837 4. 0000000054600000-000000005465ffff: BL31
9391 11:04:18.534492 5. 0000000054660000-00000000ffe63fff: RAM
9392 11:04:18.540557 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9393 11:04:18.543667 7. 0000000100000000-000000023fffffff: RAM
9394 11:04:18.547061 Passing 5 GPIOs to payload:
9395 11:04:18.550504 NAME | PORT | POLARITY | VALUE
9396 11:04:18.554219 EC in RW | 0x000000aa | low | undefined
9397 11:04:18.560376 EC interrupt | 0x00000005 | low | undefined
9398 11:04:18.564190 TPM interrupt | 0x000000ab | high | undefined
9399 11:04:18.570467 SD card detect | 0x00000011 | high | undefined
9400 11:04:18.573847 speaker enable | 0x00000093 | high | undefined
9401 11:04:18.577737 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9402 11:04:18.580655 in-header: 03 f9 00 00 02 00 00 00
9403 11:04:18.583717 in-data: 02 00
9404 11:04:18.583798 ADC[4]: Raw value=899852 ID=7
9405 11:04:18.587059 ADC[3]: Raw value=212967 ID=1
9406 11:04:18.590800 RAM Code: 0x71
9407 11:04:18.590883 ADC[6]: Raw value=74557 ID=0
9408 11:04:18.593544 ADC[5]: Raw value=211860 ID=1
9409 11:04:18.596995 SKU Code: 0x1
9410 11:04:18.600414 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b9b6
9411 11:04:18.603484 coreboot table: 964 bytes.
9412 11:04:18.606984 IMD ROOT 0. 0xfffff000 0x00001000
9413 11:04:18.609931 IMD SMALL 1. 0xffffe000 0x00001000
9414 11:04:18.613252 RO MCACHE 2. 0xffffc000 0x00001104
9415 11:04:18.616819 CONSOLE 3. 0xfff7c000 0x00080000
9416 11:04:18.620488 FMAP 4. 0xfff7b000 0x00000452
9417 11:04:18.623712 TIME STAMP 5. 0xfff7a000 0x00000910
9418 11:04:18.626748 VBOOT WORK 6. 0xfff66000 0x00014000
9419 11:04:18.630258 RAMOOPS 7. 0xffe66000 0x00100000
9420 11:04:18.633271 COREBOOT 8. 0xffe64000 0x00002000
9421 11:04:18.633353 IMD small region:
9422 11:04:18.638095 IMD ROOT 0. 0xffffec00 0x00000400
9423 11:04:18.643732 VPD 1. 0xffffeb80 0x0000006c
9424 11:04:18.646991 MMC STATUS 2. 0xffffeb60 0x00000004
9425 11:04:18.649886 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9426 11:04:18.656464 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9427 11:04:18.696968 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9428 11:04:18.700292 Checking segment from ROM address 0x40100000
9429 11:04:18.703723 Checking segment from ROM address 0x4010001c
9430 11:04:18.710138 Loading segment from ROM address 0x40100000
9431 11:04:18.710242 code (compression=0)
9432 11:04:18.720624 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9433 11:04:18.727725 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9434 11:04:18.727836 it's not compressed!
9435 11:04:18.734046 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9436 11:04:18.737106 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9437 11:04:18.757494 Loading segment from ROM address 0x4010001c
9438 11:04:18.757623 Entry Point 0x80000000
9439 11:04:18.760726 Loaded segments
9440 11:04:18.763813 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9441 11:04:18.770789 Jumping to boot code at 0x80000000(0xffe64000)
9442 11:04:18.777142 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9443 11:04:18.783858 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9444 11:04:18.792042 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9445 11:04:18.795254 Checking segment from ROM address 0x40100000
9446 11:04:18.798615 Checking segment from ROM address 0x4010001c
9447 11:04:18.805304 Loading segment from ROM address 0x40100000
9448 11:04:18.805404 code (compression=1)
9449 11:04:18.812193 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9450 11:04:18.822049 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9451 11:04:18.822171 using LZMA
9452 11:04:18.830611 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9453 11:04:18.837109 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9454 11:04:18.840254 Loading segment from ROM address 0x4010001c
9455 11:04:18.840347 Entry Point 0x54601000
9456 11:04:18.843633 Loaded segments
9457 11:04:18.846909 NOTICE: MT8192 bl31_setup
9458 11:04:18.853795 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9459 11:04:18.857103 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9460 11:04:18.860182 WARNING: region 0:
9461 11:04:18.863597 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9462 11:04:18.863681 WARNING: region 1:
9463 11:04:18.870219 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9464 11:04:18.873596 WARNING: region 2:
9465 11:04:18.877035 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9466 11:04:18.880726 WARNING: region 3:
9467 11:04:18.883780 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9468 11:04:18.886935 WARNING: region 4:
9469 11:04:18.893982 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9470 11:04:18.894087 WARNING: region 5:
9471 11:04:18.897496 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 11:04:18.900346 WARNING: region 6:
9473 11:04:18.903999 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 11:04:18.907162 WARNING: region 7:
9475 11:04:18.911003 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9476 11:04:18.917075 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9477 11:04:18.920335 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9478 11:04:18.923851 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9479 11:04:18.930381 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9480 11:04:18.933952 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9481 11:04:18.937619 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9482 11:04:18.943805 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9483 11:04:18.947882 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9484 11:04:18.950542 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9485 11:04:18.957142 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9486 11:04:18.960853 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9487 11:04:18.967129 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9488 11:04:18.970506 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9489 11:04:18.973810 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9490 11:04:18.980194 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9491 11:04:18.983554 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9492 11:04:18.986963 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9493 11:04:18.993637 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9494 11:04:18.997415 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9495 11:04:19.003646 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9496 11:04:19.006824 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9497 11:04:19.010176 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9498 11:04:19.017544 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9499 11:04:19.020243 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9500 11:04:19.027260 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9501 11:04:19.030266 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9502 11:04:19.033683 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9503 11:04:19.040245 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9504 11:04:19.043804 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9505 11:04:19.050439 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9506 11:04:19.054067 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9507 11:04:19.057066 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9508 11:04:19.064564 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9509 11:04:19.067071 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9510 11:04:19.070546 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9511 11:04:19.073658 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9512 11:04:19.076871 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9513 11:04:19.083493 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9514 11:04:19.087391 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9515 11:04:19.090414 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9516 11:04:19.093844 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9517 11:04:19.100515 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9518 11:04:19.103635 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9519 11:04:19.107122 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9520 11:04:19.110686 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9521 11:04:19.117913 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9522 11:04:19.120978 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9523 11:04:19.124354 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9524 11:04:19.130447 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9525 11:04:19.134133 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9526 11:04:19.140577 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9527 11:04:19.143934 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9528 11:04:19.147210 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9529 11:04:19.153996 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9530 11:04:19.157598 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9531 11:04:19.163912 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9532 11:04:19.167192 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9533 11:04:19.171014 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9534 11:04:19.177263 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9535 11:04:19.180840 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9536 11:04:19.186939 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9537 11:04:19.190997 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9538 11:04:19.197385 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9539 11:04:19.200767 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9540 11:04:19.207243 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9541 11:04:19.211528 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9542 11:04:19.213743 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9543 11:04:19.220545 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9544 11:04:19.224258 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9545 11:04:19.230805 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9546 11:04:19.234385 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9547 11:04:19.237299 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9548 11:04:19.244061 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9549 11:04:19.247578 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9550 11:04:19.253972 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9551 11:04:19.258359 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9552 11:04:19.265072 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9553 11:04:19.267402 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9554 11:04:19.274051 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9555 11:04:19.277175 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9556 11:04:19.280741 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9557 11:04:19.286942 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9558 11:04:19.290558 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9559 11:04:19.297271 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9560 11:04:19.300114 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9561 11:04:19.307295 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9562 11:04:19.310191 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9563 11:04:19.313675 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9564 11:04:19.320375 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9565 11:04:19.323709 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9566 11:04:19.330585 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9567 11:04:19.334139 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9568 11:04:19.340965 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9569 11:04:19.344281 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9570 11:04:19.350301 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9571 11:04:19.354226 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9572 11:04:19.357135 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9573 11:04:19.360687 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9574 11:04:19.367588 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9575 11:04:19.370892 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9576 11:04:19.373952 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9577 11:04:19.380971 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9578 11:04:19.384031 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9579 11:04:19.387928 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9580 11:04:19.394192 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9581 11:04:19.397371 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9582 11:04:19.403885 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9583 11:04:19.407414 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9584 11:04:19.410479 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9585 11:04:19.417218 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9586 11:04:19.420987 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9587 11:04:19.427060 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9588 11:04:19.430420 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9589 11:04:19.435301 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9590 11:04:19.440421 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9591 11:04:19.443829 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9592 11:04:19.446980 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9593 11:04:19.454021 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9594 11:04:19.457423 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9595 11:04:19.460862 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9596 11:04:19.463857 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9597 11:04:19.471119 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9598 11:04:19.473778 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9599 11:04:19.477045 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9600 11:04:19.483975 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9601 11:04:19.487022 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9602 11:04:19.490571 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9603 11:04:19.497557 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9604 11:04:19.500642 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9605 11:04:19.507449 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9606 11:04:19.510242 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9607 11:04:19.513710 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9608 11:04:19.520253 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9609 11:04:19.524225 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9610 11:04:19.526941 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9611 11:04:19.533738 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9612 11:04:19.537053 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9613 11:04:19.543552 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9614 11:04:19.547296 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9615 11:04:19.550084 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9616 11:04:19.556947 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9617 11:04:19.560609 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9618 11:04:19.566778 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9619 11:04:19.570503 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9620 11:04:19.574409 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9621 11:04:19.580584 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9622 11:04:19.583763 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9623 11:04:19.590638 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9624 11:04:19.594120 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9625 11:04:19.597239 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9626 11:04:19.604421 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9627 11:04:19.607287 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9628 11:04:19.610382 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9629 11:04:19.617158 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9630 11:04:19.620590 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9631 11:04:19.627226 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9632 11:04:19.630274 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9633 11:04:19.633831 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9634 11:04:19.641598 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9635 11:04:19.644243 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9636 11:04:19.647392 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9637 11:04:19.653792 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9638 11:04:19.657813 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9639 11:04:19.663694 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9640 11:04:19.667034 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9641 11:04:19.670203 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9642 11:04:19.677413 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9643 11:04:19.680808 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9644 11:04:19.687707 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9645 11:04:19.690536 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9646 11:04:19.694336 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9647 11:04:19.700760 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9648 11:04:19.703987 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9649 11:04:19.707164 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9650 11:04:19.713868 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9651 11:04:19.717538 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9652 11:04:19.724416 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9653 11:04:19.727231 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9654 11:04:19.730834 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9655 11:04:19.737129 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9656 11:04:19.740689 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9657 11:04:19.747234 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9658 11:04:19.750628 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9659 11:04:19.753917 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9660 11:04:19.760702 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9661 11:04:19.764226 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9662 11:04:19.767390 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9663 11:04:19.774161 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9664 11:04:19.777397 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9665 11:04:19.784467 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9666 11:04:19.787660 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9667 11:04:19.794320 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9668 11:04:19.797257 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9669 11:04:19.801257 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9670 11:04:19.807534 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9671 11:04:19.810718 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9672 11:04:19.814019 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9673 11:04:19.821002 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9674 11:04:19.824291 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9675 11:04:19.831438 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9676 11:04:19.834367 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9677 11:04:19.840836 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9678 11:04:19.844121 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9679 11:04:19.847996 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9680 11:04:19.854272 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9681 11:04:19.857675 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9682 11:04:19.864069 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9683 11:04:19.867249 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9684 11:04:19.871135 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9685 11:04:19.877806 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9686 11:04:19.880702 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9687 11:04:19.888133 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9688 11:04:19.890922 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9689 11:04:19.894640 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9690 11:04:19.900774 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9691 11:04:19.904252 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9692 11:04:19.910886 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9693 11:04:19.914467 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9694 11:04:19.917557 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9695 11:04:19.924437 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9696 11:04:19.927722 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9697 11:04:19.934074 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9698 11:04:19.937922 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9699 11:04:19.944312 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9700 11:04:19.947590 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9701 11:04:19.950855 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9702 11:04:19.957853 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9703 11:04:19.961070 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9704 11:04:19.967721 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9705 11:04:19.970940 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9706 11:04:19.974068 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9707 11:04:19.977489 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9708 11:04:19.981047 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9709 11:04:19.987384 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9710 11:04:19.991151 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9711 11:04:19.994671 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9712 11:04:20.000883 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9713 11:04:20.004446 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9714 11:04:20.008170 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9715 11:04:20.014725 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9716 11:04:20.017704 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9717 11:04:20.024290 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9718 11:04:20.027351 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9719 11:04:20.031262 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9720 11:04:20.038083 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9721 11:04:20.040874 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9722 11:04:20.044231 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9723 11:04:20.051343 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9724 11:04:20.054513 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9725 11:04:20.057925 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9726 11:04:20.064419 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9727 11:04:20.067942 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9728 11:04:20.074653 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9729 11:04:20.077920 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9730 11:04:20.080820 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9731 11:04:20.087744 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9732 11:04:20.090985 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9733 11:04:20.094624 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9734 11:04:20.101635 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9735 11:04:20.104378 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9736 11:04:20.107808 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9737 11:04:20.114222 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9738 11:04:20.118092 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9739 11:04:20.121249 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9740 11:04:20.127879 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9741 11:04:20.131060 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9742 11:04:20.137954 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9743 11:04:20.140859 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9744 11:04:20.144610 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9745 11:04:20.148239 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9746 11:04:20.154741 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9747 11:04:20.157939 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9748 11:04:20.161103 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9749 11:04:20.164737 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9750 11:04:20.168485 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9751 11:04:20.174670 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9752 11:04:20.177788 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9753 11:04:20.181129 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9754 11:04:20.184710 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9755 11:04:20.191009 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9756 11:04:20.194431 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9757 11:04:20.197738 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9758 11:04:20.204511 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9759 11:04:20.208179 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9760 11:04:20.215165 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9761 11:04:20.217694 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9762 11:04:20.221278 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9763 11:04:20.228031 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9764 11:04:20.231506 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9765 11:04:20.234831 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9766 11:04:20.241458 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9767 11:04:20.244896 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9768 11:04:20.251376 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9769 11:04:20.255337 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9770 11:04:20.261716 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9771 11:04:20.264843 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9772 11:04:20.268222 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9773 11:04:20.274833 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9774 11:04:20.278217 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9775 11:04:20.282300 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9776 11:04:20.288546 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9777 11:04:20.291624 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9778 11:04:20.298615 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9779 11:04:20.302063 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9780 11:04:20.308393 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9781 11:04:20.311558 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9782 11:04:20.314729 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9783 11:04:20.321509 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9784 11:04:20.325354 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9785 11:04:20.331649 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9786 11:04:20.335008 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9787 11:04:20.338553 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9788 11:04:20.344871 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9789 11:04:20.348511 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9790 11:04:20.351805 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9791 11:04:20.358491 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9792 11:04:20.362156 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9793 11:04:20.368163 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9794 11:04:20.372089 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9795 11:04:20.378369 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9796 11:04:20.381615 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9797 11:04:20.384775 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9798 11:04:20.392038 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9799 11:04:20.395144 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9800 11:04:20.401424 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9801 11:04:20.405300 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9802 11:04:20.408188 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9803 11:04:20.415586 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9804 11:04:20.418256 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9805 11:04:20.425316 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9806 11:04:20.428056 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9807 11:04:20.431724 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9808 11:04:20.438388 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9809 11:04:20.442286 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9810 11:04:20.448010 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9811 11:04:20.451426 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9812 11:04:20.458270 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9813 11:04:20.461573 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9814 11:04:20.464565 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9815 11:04:20.471640 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9816 11:04:20.475165 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9817 11:04:20.478061 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9818 11:04:20.484933 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9819 11:04:20.488059 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9820 11:04:20.494830 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9821 11:04:20.498962 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9822 11:04:20.502636 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9823 11:04:20.507875 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9824 11:04:20.511718 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9825 11:04:20.517787 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9826 11:04:20.521403 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9827 11:04:20.528366 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9828 11:04:20.531436 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9829 11:04:20.534901 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9830 11:04:20.541426 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9831 11:04:20.545452 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9832 11:04:20.551660 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9833 11:04:20.554657 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9834 11:04:20.557941 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9835 11:04:20.564626 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9836 11:04:20.568039 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9837 11:04:20.575149 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9838 11:04:20.578029 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9839 11:04:20.581684 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9840 11:04:20.588142 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9841 11:04:20.591385 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9842 11:04:20.598234 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9843 11:04:20.601721 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9844 11:04:20.608011 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9845 11:04:20.611750 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9846 11:04:20.614736 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9847 11:04:20.621522 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9848 11:04:20.624958 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9849 11:04:20.632267 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9850 11:04:20.634879 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9851 11:04:20.641743 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9852 11:04:20.645071 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9853 11:04:20.648542 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9854 11:04:20.654943 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9855 11:04:20.658025 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9856 11:04:20.664799 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9857 11:04:20.668326 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9858 11:04:20.674803 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9859 11:04:20.678611 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9860 11:04:20.685305 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9861 11:04:20.688162 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9862 11:04:20.692058 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9863 11:04:20.698338 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9864 11:04:20.701906 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9865 11:04:20.708092 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9866 11:04:20.711516 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9867 11:04:20.717935 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9868 11:04:20.721431 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9869 11:04:20.724905 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9870 11:04:20.731073 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9871 11:04:20.735433 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9872 11:04:20.741093 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9873 11:04:20.745001 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9874 11:04:20.751461 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9875 11:04:20.754591 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9876 11:04:20.761020 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9877 11:04:20.764836 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9878 11:04:20.767767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9879 11:04:20.775474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9880 11:04:20.777451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9881 11:04:20.785364 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9882 11:04:20.787630 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9883 11:04:20.794419 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9884 11:04:20.797452 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9885 11:04:20.800794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9886 11:04:20.808142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9887 11:04:20.810731 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9888 11:04:20.817929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9889 11:04:20.820907 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9890 11:04:20.827674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9891 11:04:20.831073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9892 11:04:20.838408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9893 11:04:20.840979 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9894 11:04:20.847976 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9895 11:04:20.851257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9896 11:04:20.857660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9897 11:04:20.861004 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9898 11:04:20.867679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9899 11:04:20.871365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9900 11:04:20.878048 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9901 11:04:20.881244 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9902 11:04:20.888034 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9903 11:04:20.891316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9904 11:04:20.897823 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9905 11:04:20.900948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9906 11:04:20.907874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9907 11:04:20.911233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9908 11:04:20.918110 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9909 11:04:20.921016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9910 11:04:20.924282 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9911 11:04:20.928154 INFO: [APUAPC] vio 0
9912 11:04:20.934130 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9913 11:04:20.937638 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9914 11:04:20.940726 INFO: [APUAPC] D0_APC_0: 0x400510
9915 11:04:20.944143 INFO: [APUAPC] D0_APC_1: 0x0
9916 11:04:20.948202 INFO: [APUAPC] D0_APC_2: 0x1540
9917 11:04:20.951131 INFO: [APUAPC] D0_APC_3: 0x0
9918 11:04:20.954850 INFO: [APUAPC] D1_APC_0: 0xffffffff
9919 11:04:20.957758 INFO: [APUAPC] D1_APC_1: 0xffffffff
9920 11:04:20.961335 INFO: [APUAPC] D1_APC_2: 0x3fffff
9921 11:04:20.961417 INFO: [APUAPC] D1_APC_3: 0x0
9922 11:04:20.964650 INFO: [APUAPC] D2_APC_0: 0xffffffff
9923 11:04:20.967811 INFO: [APUAPC] D2_APC_1: 0xffffffff
9924 11:04:20.970940 INFO: [APUAPC] D2_APC_2: 0x3fffff
9925 11:04:20.974801 INFO: [APUAPC] D2_APC_3: 0x0
9926 11:04:20.977974 INFO: [APUAPC] D3_APC_0: 0xffffffff
9927 11:04:20.980747 INFO: [APUAPC] D3_APC_1: 0xffffffff
9928 11:04:20.984666 INFO: [APUAPC] D3_APC_2: 0x3fffff
9929 11:04:20.988068 INFO: [APUAPC] D3_APC_3: 0x0
9930 11:04:20.991107 INFO: [APUAPC] D4_APC_0: 0xffffffff
9931 11:04:20.994127 INFO: [APUAPC] D4_APC_1: 0xffffffff
9932 11:04:20.997499 INFO: [APUAPC] D4_APC_2: 0x3fffff
9933 11:04:21.000703 INFO: [APUAPC] D4_APC_3: 0x0
9934 11:04:21.004114 INFO: [APUAPC] D5_APC_0: 0xffffffff
9935 11:04:21.007348 INFO: [APUAPC] D5_APC_1: 0xffffffff
9936 11:04:21.010997 INFO: [APUAPC] D5_APC_2: 0x3fffff
9937 11:04:21.014028 INFO: [APUAPC] D5_APC_3: 0x0
9938 11:04:21.017759 INFO: [APUAPC] D6_APC_0: 0xffffffff
9939 11:04:21.020909 INFO: [APUAPC] D6_APC_1: 0xffffffff
9940 11:04:21.024263 INFO: [APUAPC] D6_APC_2: 0x3fffff
9941 11:04:21.027370 INFO: [APUAPC] D6_APC_3: 0x0
9942 11:04:21.031149 INFO: [APUAPC] D7_APC_0: 0xffffffff
9943 11:04:21.034829 INFO: [APUAPC] D7_APC_1: 0xffffffff
9944 11:04:21.037931 INFO: [APUAPC] D7_APC_2: 0x3fffff
9945 11:04:21.041045 INFO: [APUAPC] D7_APC_3: 0x0
9946 11:04:21.044344 INFO: [APUAPC] D8_APC_0: 0xffffffff
9947 11:04:21.047952 INFO: [APUAPC] D8_APC_1: 0xffffffff
9948 11:04:21.051188 INFO: [APUAPC] D8_APC_2: 0x3fffff
9949 11:04:21.054244 INFO: [APUAPC] D8_APC_3: 0x0
9950 11:04:21.057259 INFO: [APUAPC] D9_APC_0: 0xffffffff
9951 11:04:21.060674 INFO: [APUAPC] D9_APC_1: 0xffffffff
9952 11:04:21.064923 INFO: [APUAPC] D9_APC_2: 0x3fffff
9953 11:04:21.067629 INFO: [APUAPC] D9_APC_3: 0x0
9954 11:04:21.071109 INFO: [APUAPC] D10_APC_0: 0xffffffff
9955 11:04:21.074764 INFO: [APUAPC] D10_APC_1: 0xffffffff
9956 11:04:21.077731 INFO: [APUAPC] D10_APC_2: 0x3fffff
9957 11:04:21.080688 INFO: [APUAPC] D10_APC_3: 0x0
9958 11:04:21.083990 INFO: [APUAPC] D11_APC_0: 0xffffffff
9959 11:04:21.087653 INFO: [APUAPC] D11_APC_1: 0xffffffff
9960 11:04:21.091090 INFO: [APUAPC] D11_APC_2: 0x3fffff
9961 11:04:21.094267 INFO: [APUAPC] D11_APC_3: 0x0
9962 11:04:21.097547 INFO: [APUAPC] D12_APC_0: 0xffffffff
9963 11:04:21.100717 INFO: [APUAPC] D12_APC_1: 0xffffffff
9964 11:04:21.104089 INFO: [APUAPC] D12_APC_2: 0x3fffff
9965 11:04:21.108021 INFO: [APUAPC] D12_APC_3: 0x0
9966 11:04:21.110950 INFO: [APUAPC] D13_APC_0: 0xffffffff
9967 11:04:21.113763 INFO: [APUAPC] D13_APC_1: 0xffffffff
9968 11:04:21.117452 INFO: [APUAPC] D13_APC_2: 0x3fffff
9969 11:04:21.120823 INFO: [APUAPC] D13_APC_3: 0x0
9970 11:04:21.124223 INFO: [APUAPC] D14_APC_0: 0xffffffff
9971 11:04:21.127476 INFO: [APUAPC] D14_APC_1: 0xffffffff
9972 11:04:21.130812 INFO: [APUAPC] D14_APC_2: 0x3fffff
9973 11:04:21.133804 INFO: [APUAPC] D14_APC_3: 0x0
9974 11:04:21.137090 INFO: [APUAPC] D15_APC_0: 0xffffffff
9975 11:04:21.140943 INFO: [APUAPC] D15_APC_1: 0xffffffff
9976 11:04:21.144145 INFO: [APUAPC] D15_APC_2: 0x3fffff
9977 11:04:21.147703 INFO: [APUAPC] D15_APC_3: 0x0
9978 11:04:21.150918 INFO: [APUAPC] APC_CON: 0x4
9979 11:04:21.151001 INFO: [NOCDAPC] D0_APC_0: 0x0
9980 11:04:21.154008 INFO: [NOCDAPC] D0_APC_1: 0x0
9981 11:04:21.157194 INFO: [NOCDAPC] D1_APC_0: 0x0
9982 11:04:21.160866 INFO: [NOCDAPC] D1_APC_1: 0xfff
9983 11:04:21.163993 INFO: [NOCDAPC] D2_APC_0: 0x0
9984 11:04:21.167571 INFO: [NOCDAPC] D2_APC_1: 0xfff
9985 11:04:21.171035 INFO: [NOCDAPC] D3_APC_0: 0x0
9986 11:04:21.173970 INFO: [NOCDAPC] D3_APC_1: 0xfff
9987 11:04:21.177730 INFO: [NOCDAPC] D4_APC_0: 0x0
9988 11:04:21.181415 INFO: [NOCDAPC] D4_APC_1: 0xfff
9989 11:04:21.181498 INFO: [NOCDAPC] D5_APC_0: 0x0
9990 11:04:21.184600 INFO: [NOCDAPC] D5_APC_1: 0xfff
9991 11:04:21.187759 INFO: [NOCDAPC] D6_APC_0: 0x0
9992 11:04:21.190997 INFO: [NOCDAPC] D6_APC_1: 0xfff
9993 11:04:21.194321 INFO: [NOCDAPC] D7_APC_0: 0x0
9994 11:04:21.197757 INFO: [NOCDAPC] D7_APC_1: 0xfff
9995 11:04:21.201076 INFO: [NOCDAPC] D8_APC_0: 0x0
9996 11:04:21.204191 INFO: [NOCDAPC] D8_APC_1: 0xfff
9997 11:04:21.208022 INFO: [NOCDAPC] D9_APC_0: 0x0
9998 11:04:21.211002 INFO: [NOCDAPC] D9_APC_1: 0xfff
9999 11:04:21.211081 INFO: [NOCDAPC] D10_APC_0: 0x0
10000 11:04:21.214790 INFO: [NOCDAPC] D10_APC_1: 0xfff
10001 11:04:21.218039 INFO: [NOCDAPC] D11_APC_0: 0x0
10002 11:04:21.221006 INFO: [NOCDAPC] D11_APC_1: 0xfff
10003 11:04:21.224066 INFO: [NOCDAPC] D12_APC_0: 0x0
10004 11:04:21.227337 INFO: [NOCDAPC] D12_APC_1: 0xfff
10005 11:04:21.231102 INFO: [NOCDAPC] D13_APC_0: 0x0
10006 11:04:21.233917 INFO: [NOCDAPC] D13_APC_1: 0xfff
10007 11:04:21.237783 INFO: [NOCDAPC] D14_APC_0: 0x0
10008 11:04:21.240668 INFO: [NOCDAPC] D14_APC_1: 0xfff
10009 11:04:21.244199 INFO: [NOCDAPC] D15_APC_0: 0x0
10010 11:04:21.247200 INFO: [NOCDAPC] D15_APC_1: 0xfff
10011 11:04:21.250990 INFO: [NOCDAPC] APC_CON: 0x4
10012 11:04:21.253906 INFO: [APUAPC] set_apusys_apc done
10013 11:04:21.257787 INFO: [DEVAPC] devapc_init done
10014 11:04:21.261460 INFO: GICv3 without legacy support detected.
10015 11:04:21.264484 INFO: ARM GICv3 driver initialized in EL3
10016 11:04:21.267461 INFO: Maximum SPI INTID supported: 639
10017 11:04:21.270569 INFO: BL31: Initializing runtime services
10018 11:04:21.277331 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10019 11:04:21.280315 INFO: SPM: enable CPC mode
10020 11:04:21.287553 INFO: mcdi ready for mcusys-off-idle and system suspend
10021 11:04:21.290464 INFO: BL31: Preparing for EL3 exit to normal world
10022 11:04:21.294053 INFO: Entry point address = 0x80000000
10023 11:04:21.296882 INFO: SPSR = 0x8
10024 11:04:21.301375
10025 11:04:21.301482
10026 11:04:21.301574
10027 11:04:21.305384 Starting depthcharge on Spherion...
10028 11:04:21.305478
10029 11:04:21.305562 Wipe memory regions:
10030 11:04:21.305643
10031 11:04:21.306460 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10032 11:04:21.306583 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10033 11:04:21.306688 Setting prompt string to ['asurada:']
10034 11:04:21.306784 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10035 11:04:21.308106 [0x00000040000000, 0x00000054600000)
10036 11:04:21.430256
10037 11:04:21.430392 [0x00000054660000, 0x00000080000000)
10038 11:04:21.690282
10039 11:04:21.690419 [0x000000821a7280, 0x000000ffe64000)
10040 11:04:22.435098
10041 11:04:22.435234 [0x00000100000000, 0x00000240000000)
10042 11:04:24.325429
10043 11:04:24.328845 Initializing XHCI USB controller at 0x11200000.
10044 11:04:25.367723
10045 11:04:25.370969 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10046 11:04:25.371056
10047 11:04:25.371116
10048 11:04:25.371378 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10049 11:04:25.371451 Sending line: 'tftpboot 192.168.201.1 14786807/tftp-deploy-8zc7obp1/kernel/image.itb 14786807/tftp-deploy-8zc7obp1/kernel/cmdline '
10051 11:04:25.471981 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10052 11:04:25.472135 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10053 11:04:25.476595 asurada: tftpboot 192.168.201.1 14786807/tftp-deploy-8zc7obp1/kernel/image.ittp-deploy-8zc7obp1/kernel/cmdline
10054 11:04:25.476674
10055 11:04:25.476734 Waiting for link
10056 11:04:25.634440
10057 11:04:25.634556 R8152: Initializing
10058 11:04:25.634616
10059 11:04:25.637538 Version 6 (ocp_data = 5c30)
10060 11:04:25.637615
10061 11:04:25.640987 R8152: Done initializing
10062 11:04:25.641065
10063 11:04:25.641156 Adding net device
10064 11:04:27.641593
10065 11:04:27.641708 done.
10066 11:04:27.641769
10067 11:04:27.641856 MAC: 00:24:32:30:78:52
10068 11:04:27.641910
10069 11:04:27.644492 Sending DHCP discover... done.
10070 11:04:27.644569
10071 11:04:27.647813 Waiting for reply... done.
10072 11:04:27.647891
10073 11:04:27.650972 Sending DHCP request... done.
10074 11:04:27.651049
10075 11:04:27.655886 Waiting for reply... done.
10076 11:04:27.655963
10077 11:04:27.656023 My ip is 192.168.201.14
10078 11:04:27.656078
10079 11:04:27.658989 The DHCP server ip is 192.168.201.1
10080 11:04:27.659066
10081 11:04:27.665282 TFTP server IP predefined by user: 192.168.201.1
10082 11:04:27.665362
10083 11:04:27.672666 Bootfile predefined by user: 14786807/tftp-deploy-8zc7obp1/kernel/image.itb
10084 11:04:27.672748
10085 11:04:27.672807 Sending tftp read request... done.
10086 11:04:27.675268
10087 11:04:27.679044 Waiting for the transfer...
10088 11:04:27.679120
10089 11:04:28.254306 00000000 ################################################################
10090 11:04:28.254419
10091 11:04:28.825301 00080000 ################################################################
10092 11:04:28.825410
10093 11:04:29.406082 00100000 ################################################################
10094 11:04:29.406197
10095 11:04:29.988551 00180000 ################################################################
10096 11:04:29.988667
10097 11:04:30.558234 00200000 ################################################################
10098 11:04:30.558351
10099 11:04:31.185409 00280000 ################################################################
10100 11:04:31.185951
10101 11:04:31.847131 00300000 ################################################################
10102 11:04:31.847532
10103 11:04:32.504496 00380000 ################################################################
10104 11:04:32.504680
10105 11:04:33.182475 00400000 ################################################################
10106 11:04:33.182907
10107 11:04:33.858889 00480000 ################################################################
10108 11:04:33.859327
10109 11:04:34.559773 00500000 ################################################################
10110 11:04:34.560214
10111 11:04:35.243851 00580000 ################################################################
10112 11:04:35.244306
10113 11:04:35.930136 00600000 ################################################################
10114 11:04:35.930654
10115 11:04:36.572925 00680000 ################################################################
10116 11:04:36.573065
10117 11:04:37.222637 00700000 ################################################################
10118 11:04:37.223077
10119 11:04:37.857227 00780000 ################################################################
10120 11:04:37.857710
10121 11:04:38.522603 00800000 ################################################################
10122 11:04:38.523063
10123 11:04:39.214320 00880000 ################################################################
10124 11:04:39.214760
10125 11:04:39.908130 00900000 ################################################################
10126 11:04:39.908688
10127 11:04:40.617848 00980000 ################################################################
10128 11:04:40.618287
10129 11:04:41.325418 00a00000 ################################################################
10130 11:04:41.325954
10131 11:04:42.035516 00a80000 ################################################################
10132 11:04:42.036081
10133 11:04:42.712822 00b00000 ################################################################
10134 11:04:42.712936
10135 11:04:43.259131 00b80000 ################################################################
10136 11:04:43.259242
10137 11:04:43.818721 00c00000 ################################################################
10138 11:04:43.818833
10139 11:04:44.387545 00c80000 ################################################################
10140 11:04:44.387668
10141 11:04:44.946529 00d00000 ################################################################
10142 11:04:44.946653
10143 11:04:45.499127 00d80000 ################################################################
10144 11:04:45.499253
10145 11:04:46.041689 00e00000 ################################################################
10146 11:04:46.041816
10147 11:04:46.586396 00e80000 ################################################################
10148 11:04:46.586521
10149 11:04:47.151522 00f00000 ################################################################
10150 11:04:47.151690
10151 11:04:47.718080 00f80000 ################################################################
10152 11:04:47.718204
10153 11:04:48.287307 01000000 ################################################################
10154 11:04:48.287432
10155 11:04:48.830280 01080000 ################################################################
10156 11:04:48.830404
10157 11:04:49.390360 01100000 ################################################################
10158 11:04:49.390483
10159 11:04:49.967623 01180000 ################################################################
10160 11:04:49.967747
10161 11:04:50.527174 01200000 ################################################################
10162 11:04:50.527302
10163 11:04:51.079282 01280000 ################################################################
10164 11:04:51.079406
10165 11:04:51.622268 01300000 ################################################################
10166 11:04:51.622391
10167 11:04:52.164762 01380000 ################################################################
10168 11:04:52.164892
10169 11:04:52.706577 01400000 ################################################################
10170 11:04:52.706699
10171 11:04:53.253259 01480000 ################################################################
10172 11:04:53.253389
10173 11:04:53.806764 01500000 ################################################################
10174 11:04:53.806886
10175 11:04:54.350420 01580000 ################################################################
10176 11:04:54.350544
10177 11:04:54.891780 01600000 ################################################################
10178 11:04:54.891907
10179 11:04:55.426935 01680000 ################################################################
10180 11:04:55.427060
10181 11:04:55.953460 01700000 ################################################################
10182 11:04:55.953576
10183 11:04:56.481288 01780000 ################################################################
10184 11:04:56.481409
10185 11:04:57.020776 01800000 ################################################################
10186 11:04:57.020921
10187 11:04:57.563813 01880000 ################################################################
10188 11:04:57.563936
10189 11:04:58.116948 01900000 ################################################################
10190 11:04:58.117087
10191 11:04:58.671815 01980000 ################################################################
10192 11:04:58.671938
10193 11:04:59.231073 01a00000 ################################################################
10194 11:04:59.231198
10195 11:04:59.930347 01a80000 ################################################################
10196 11:04:59.930878
10197 11:05:00.631510 01b00000 ################################################################
10198 11:05:00.631970
10199 11:05:01.348940 01b80000 ################################################################
10200 11:05:01.349518
10201 11:05:02.050321 01c00000 ################################################################
10202 11:05:02.050834
10203 11:05:02.717912 01c80000 ################################################################
10204 11:05:02.718354
10205 11:05:03.336560 01d00000 ################################################################
10206 11:05:03.336674
10207 11:05:03.883929 01d80000 ################################################################
10208 11:05:03.884040
10209 11:05:04.439567 01e00000 ################################################################
10210 11:05:04.439679
10211 11:05:04.979825 01e80000 ################################################################
10212 11:05:04.979934
10213 11:05:05.530846 01f00000 ################################################################
10214 11:05:05.530965
10215 11:05:06.072420 01f80000 ################################################################
10216 11:05:06.072534
10217 11:05:06.636219 02000000 ################################################################
10218 11:05:06.636402
10219 11:05:07.197381 02080000 ################################################################
10220 11:05:07.197512
10221 11:05:07.751531 02100000 ################################################################
10222 11:05:07.751664
10223 11:05:08.293317 02180000 ################################################################
10224 11:05:08.293442
10225 11:05:08.834199 02200000 ################################################################
10226 11:05:08.834332
10227 11:05:09.375142 02280000 ################################################################
10228 11:05:09.375267
10229 11:05:09.914497 02300000 ################################################################
10230 11:05:09.914630
10231 11:05:10.448028 02380000 ################################################################
10232 11:05:10.448144
10233 11:05:10.993581 02400000 ################################################################
10234 11:05:10.993766
10235 11:05:11.532418 02480000 ################################################################
10236 11:05:11.532605
10237 11:05:12.090657 02500000 ################################################################
10238 11:05:12.090790
10239 11:05:12.628563 02580000 ################################################################
10240 11:05:12.628705
10241 11:05:13.158487 02600000 ################################################################
10242 11:05:13.158625
10243 11:05:13.686923 02680000 ################################################################
10244 11:05:13.687075
10245 11:05:14.209797 02700000 ################################################################
10246 11:05:14.209917
10247 11:05:14.735498 02780000 ################################################################
10248 11:05:14.735633
10249 11:05:15.277699 02800000 ################################################################
10250 11:05:15.277840
10251 11:05:15.800646 02880000 ################################################################
10252 11:05:15.800787
10253 11:05:16.318454 02900000 ################################################################
10254 11:05:16.318577
10255 11:05:16.836726 02980000 ################################################################
10256 11:05:16.836848
10257 11:05:17.371533 02a00000 ################################################################
10258 11:05:17.371648
10259 11:05:17.906793 02a80000 ################################################################
10260 11:05:17.906919
10261 11:05:18.468875 02b00000 ################################################################
10262 11:05:18.469002
10263 11:05:19.006914 02b80000 ################################################################
10264 11:05:19.007031
10265 11:05:19.534448 02c00000 ################################################################
10266 11:05:19.534597
10267 11:05:20.084231 02c80000 ################################################################
10268 11:05:20.084361
10269 11:05:20.609726 02d00000 ################################################################
10270 11:05:20.609849
10271 11:05:21.157196 02d80000 ################################################################
10272 11:05:21.157325
10273 11:05:21.685574 02e00000 ################################################################
10274 11:05:21.685712
10275 11:05:22.222893 02e80000 ################################################################
10276 11:05:22.223026
10277 11:05:22.770034 02f00000 ################################################################
10278 11:05:22.770173
10279 11:05:23.305266 02f80000 ################################################################
10280 11:05:23.305414
10281 11:05:23.839695 03000000 ################################################################
10282 11:05:23.839858
10283 11:05:24.393782 03080000 ################################################################
10284 11:05:24.393938
10285 11:05:24.927786 03100000 ################################################################
10286 11:05:24.927916
10287 11:05:25.453332 03180000 ################################################################
10288 11:05:25.453450
10289 11:05:25.984813 03200000 ################################################################
10290 11:05:25.984962
10291 11:05:26.516997 03280000 ################################################################
10292 11:05:26.517197
10293 11:05:27.035306 03300000 ################################################################
10294 11:05:27.035439
10295 11:05:27.380691 03380000 ########################################### done.
10296 11:05:27.380865
10297 11:05:27.383364 The bootfile was 54351434 bytes long.
10298 11:05:27.383482
10299 11:05:27.386700 Sending tftp read request... done.
10300 11:05:27.386809
10301 11:05:27.386900 Waiting for the transfer...
10302 11:05:27.386984
10303 11:05:27.390114 00000000 # done.
10304 11:05:27.390220
10305 11:05:27.396762 Command line loaded dynamically from TFTP file: 14786807/tftp-deploy-8zc7obp1/kernel/cmdline
10306 11:05:27.396883
10307 11:05:27.410567 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10308 11:05:27.410728
10309 11:05:27.413754 Loading FIT.
10310 11:05:27.413855
10311 11:05:27.417172 Image ramdisk-1 has 41185889 bytes.
10312 11:05:27.417274
10313 11:05:27.417371 Image fdt-1 has 47258 bytes.
10314 11:05:27.417454
10315 11:05:27.420323 Image kernel-1 has 13116259 bytes.
10316 11:05:27.420428
10317 11:05:27.430510 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10318 11:05:27.430649
10319 11:05:27.447150 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10320 11:05:27.447274
10321 11:05:27.454306 Choosing best match conf-1 for compat google,spherion-rev2.
10322 11:05:27.457460
10323 11:05:27.461940 Connected to device vid:did:rid of 1ae0:0028:00
10324 11:05:27.470383
10325 11:05:27.473273 tpm_get_response: command 0x17b, return code 0x0
10326 11:05:27.473385
10327 11:05:27.477222 ec_init: CrosEC protocol v3 supported (256, 248)
10328 11:05:27.481353
10329 11:05:27.484502 tpm_cleanup: add release locality here.
10330 11:05:27.484610
10331 11:05:27.484701 Shutting down all USB controllers.
10332 11:05:27.484788
10333 11:05:27.488051 Removing current net device
10334 11:05:27.488151
10335 11:05:27.494730 Exiting depthcharge with code 4 at timestamp: 95487993
10336 11:05:27.494841
10337 11:05:27.498098 LZMA decompressing kernel-1 to 0x821a6718
10338 11:05:27.498204
10339 11:05:27.501216 LZMA decompressing kernel-1 to 0x40000000
10340 11:05:29.117083
10341 11:05:29.117261 jumping to kernel
10342 11:05:29.118072 end: 2.2.4 bootloader-commands (duration 00:01:08) [common]
10343 11:05:29.118216 start: 2.2.5 auto-login-action (timeout 00:03:12) [common]
10344 11:05:29.118320 Setting prompt string to ['Linux version [0-9]']
10345 11:05:29.118424 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10346 11:05:29.118529 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10347 11:05:29.197767
10348 11:05:29.200964 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10349 11:05:29.204854 start: 2.2.5.1 login-action (timeout 00:03:12) [common]
10350 11:05:29.204995 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10351 11:05:29.205109 Setting prompt string to []
10352 11:05:29.205246 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10353 11:05:29.205384 Using line separator: #'\n'#
10354 11:05:29.205490 No login prompt set.
10355 11:05:29.205592 Parsing kernel messages
10356 11:05:29.205674 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10357 11:05:29.205828 [login-action] Waiting for messages, (timeout 00:03:12)
10358 11:05:29.205984 Waiting using forced prompt support (timeout 00:01:36)
10359 11:05:29.224895 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j261272-arm64-gcc-12-defconfig-arm64-chromebook-bgdbp) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024
10360 11:05:29.227956 [ 0.000000] random: crng init done
10361 11:05:29.231674 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10362 11:05:29.234609 [ 0.000000] efi: UEFI not found.
10363 11:05:29.244804 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10364 11:05:29.251191 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10365 11:05:29.261444 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10366 11:05:29.271489 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10367 11:05:29.278313 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10368 11:05:29.281481 [ 0.000000] printk: bootconsole [mtk8250] enabled
10369 11:05:29.289090 [ 0.000000] NUMA: No NUMA configuration found
10370 11:05:29.295417 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10371 11:05:29.302402 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10372 11:05:29.302510 [ 0.000000] Zone ranges:
10373 11:05:29.308730 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10374 11:05:29.312076 [ 0.000000] DMA32 empty
10375 11:05:29.318794 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10376 11:05:29.322076 [ 0.000000] Movable zone start for each node
10377 11:05:29.325624 [ 0.000000] Early memory node ranges
10378 11:05:29.332056 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10379 11:05:29.338974 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10380 11:05:29.345308 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10381 11:05:29.352235 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10382 11:05:29.359053 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10383 11:05:29.365468 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10384 11:05:29.422395 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10385 11:05:29.429342 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10386 11:05:29.435665 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10387 11:05:29.439410 [ 0.000000] psci: probing for conduit method from DT.
10388 11:05:29.446004 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10389 11:05:29.448994 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10390 11:05:29.455734 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10391 11:05:29.459013 [ 0.000000] psci: SMC Calling Convention v1.2
10392 11:05:29.465772 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10393 11:05:29.469090 [ 0.000000] Detected VIPT I-cache on CPU0
10394 11:05:29.476495 [ 0.000000] CPU features: detected: GIC system register CPU interface
10395 11:05:29.482740 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10396 11:05:29.489358 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10397 11:05:29.495733 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10398 11:05:29.502930 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10399 11:05:29.509085 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10400 11:05:29.516125 [ 0.000000] alternatives: applying boot alternatives
10401 11:05:29.519757 [ 0.000000] Fallback order for Node 0: 0
10402 11:05:29.525999 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10403 11:05:29.529060 [ 0.000000] Policy zone: Normal
10404 11:05:29.546200 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10405 11:05:29.555440 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10406 11:05:29.566685 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10407 11:05:29.576621 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10408 11:05:29.583214 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10409 11:05:29.586491 <6>[ 0.000000] software IO TLB: area num 8.
10410 11:05:29.644159 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10411 11:05:29.793560 <6>[ 0.000000] Memory: 7923836K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 428932K reserved, 32768K cma-reserved)
10412 11:05:29.800530 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10413 11:05:29.806553 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10414 11:05:29.809971 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10415 11:05:29.816954 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10416 11:05:29.824131 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10417 11:05:29.827413 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10418 11:05:29.836999 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10419 11:05:29.843977 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10420 11:05:29.846979 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10421 11:05:29.854578 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10422 11:05:29.857602 <6>[ 0.000000] GICv3: 608 SPIs implemented
10423 11:05:29.864523 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10424 11:05:29.867774 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10425 11:05:29.870937 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10426 11:05:29.881576 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10427 11:05:29.890954 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10428 11:05:29.904770 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10429 11:05:29.910782 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10430 11:05:29.920533 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10431 11:05:29.933502 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10432 11:05:29.940012 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10433 11:05:29.946843 <6>[ 0.009180] Console: colour dummy device 80x25
10434 11:05:29.956958 <6>[ 0.013900] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10435 11:05:29.960114 <6>[ 0.024341] pid_max: default: 32768 minimum: 301
10436 11:05:29.966944 <6>[ 0.029214] LSM: Security Framework initializing
10437 11:05:29.973920 <6>[ 0.034182] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10438 11:05:29.983298 <6>[ 0.042042] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10439 11:05:29.989742 <6>[ 0.051480] cblist_init_generic: Setting adjustable number of callback queues.
10440 11:05:29.996711 <6>[ 0.058921] cblist_init_generic: Setting shift to 3 and lim to 1.
10441 11:05:30.003357 <6>[ 0.065260] cblist_init_generic: Setting adjustable number of callback queues.
10442 11:05:30.010559 <6>[ 0.072687] cblist_init_generic: Setting shift to 3 and lim to 1.
10443 11:05:30.016522 <6>[ 0.079087] rcu: Hierarchical SRCU implementation.
10444 11:05:30.022926 <6>[ 0.084102] rcu: Max phase no-delay instances is 1000.
10445 11:05:30.026554 <6>[ 0.091124] EFI services will not be available.
10446 11:05:30.033763 <6>[ 0.096081] smp: Bringing up secondary CPUs ...
10447 11:05:30.040700 <6>[ 0.101137] Detected VIPT I-cache on CPU1
10448 11:05:30.048041 <6>[ 0.101209] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10449 11:05:30.054517 <6>[ 0.101240] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10450 11:05:30.057765 <6>[ 0.101585] Detected VIPT I-cache on CPU2
10451 11:05:30.064494 <6>[ 0.101639] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10452 11:05:30.071179 <6>[ 0.101656] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10453 11:05:30.077547 <6>[ 0.101917] Detected VIPT I-cache on CPU3
10454 11:05:30.084490 <6>[ 0.101965] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10455 11:05:30.090541 <6>[ 0.101980] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10456 11:05:30.094098 <6>[ 0.102288] CPU features: detected: Spectre-v4
10457 11:05:30.100860 <6>[ 0.102294] CPU features: detected: Spectre-BHB
10458 11:05:30.103915 <6>[ 0.102300] Detected PIPT I-cache on CPU4
10459 11:05:30.110798 <6>[ 0.102360] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10460 11:05:30.117424 <6>[ 0.102377] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10461 11:05:30.121059 <6>[ 0.102669] Detected PIPT I-cache on CPU5
10462 11:05:30.130689 <6>[ 0.102733] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10463 11:05:30.137081 <6>[ 0.102748] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10464 11:05:30.140794 <6>[ 0.103034] Detected PIPT I-cache on CPU6
10465 11:05:30.147106 <6>[ 0.103100] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10466 11:05:30.154013 <6>[ 0.103116] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10467 11:05:30.156965 <6>[ 0.103414] Detected PIPT I-cache on CPU7
10468 11:05:30.167460 <6>[ 0.103478] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10469 11:05:30.173821 <6>[ 0.103494] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10470 11:05:30.177708 <6>[ 0.103541] smp: Brought up 1 node, 8 CPUs
10471 11:05:30.180687 <6>[ 0.244865] SMP: Total of 8 processors activated.
10472 11:05:30.186993 <6>[ 0.249786] CPU features: detected: 32-bit EL0 Support
10473 11:05:30.197411 <6>[ 0.255148] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10474 11:05:30.204006 <6>[ 0.264003] CPU features: detected: Common not Private translations
10475 11:05:30.207329 <6>[ 0.270520] CPU features: detected: CRC32 instructions
10476 11:05:30.213907 <6>[ 0.275904] CPU features: detected: RCpc load-acquire (LDAPR)
10477 11:05:30.220331 <6>[ 0.281864] CPU features: detected: LSE atomic instructions
10478 11:05:30.227272 <6>[ 0.287681] CPU features: detected: Privileged Access Never
10479 11:05:30.229896 <6>[ 0.293461] CPU features: detected: RAS Extension Support
10480 11:05:30.236712 <6>[ 0.299069] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10481 11:05:30.243538 <6>[ 0.306292] CPU: All CPU(s) started at EL2
10482 11:05:30.250559 <6>[ 0.310608] alternatives: applying system-wide alternatives
10483 11:05:30.258910 <6>[ 0.321477] devtmpfs: initialized
10484 11:05:30.270922 <6>[ 0.330287] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10485 11:05:30.280856 <6>[ 0.340245] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10486 11:05:30.288015 <6>[ 0.348489] pinctrl core: initialized pinctrl subsystem
10487 11:05:30.290704 <6>[ 0.355161] DMI not present or invalid.
10488 11:05:30.297351 <6>[ 0.359576] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10489 11:05:30.307212 <6>[ 0.366338] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10490 11:05:30.313967 <6>[ 0.373922] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10491 11:05:30.323912 <6>[ 0.382152] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10492 11:05:30.327123 <6>[ 0.390398] audit: initializing netlink subsys (disabled)
10493 11:05:30.337240 <5>[ 0.396095] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10494 11:05:30.343658 <6>[ 0.396808] thermal_sys: Registered thermal governor 'step_wise'
10495 11:05:30.350706 <6>[ 0.404063] thermal_sys: Registered thermal governor 'power_allocator'
10496 11:05:30.354213 <6>[ 0.410313] cpuidle: using governor menu
10497 11:05:30.360581 <6>[ 0.421276] NET: Registered PF_QIPCRTR protocol family
10498 11:05:30.367144 <6>[ 0.426795] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10499 11:05:30.370392 <6>[ 0.433893] ASID allocator initialised with 32768 entries
10500 11:05:30.377468 <6>[ 0.440478] Serial: AMBA PL011 UART driver
10501 11:05:30.386703 <4>[ 0.449814] Trying to register duplicate clock ID: 134
10502 11:05:30.444856 <6>[ 0.511122] KASLR enabled
10503 11:05:30.459423 <6>[ 0.518783] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10504 11:05:30.466363 <6>[ 0.525796] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10505 11:05:30.472810 <6>[ 0.532284] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10506 11:05:30.479498 <6>[ 0.539287] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10507 11:05:30.486050 <6>[ 0.545776] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10508 11:05:30.492987 <6>[ 0.552779] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10509 11:05:30.499396 <6>[ 0.559266] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10510 11:05:30.506300 <6>[ 0.566269] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10511 11:05:30.509654 <6>[ 0.573794] ACPI: Interpreter disabled.
10512 11:05:30.517192 <6>[ 0.580226] iommu: Default domain type: Translated
10513 11:05:30.524198 <6>[ 0.585336] iommu: DMA domain TLB invalidation policy: strict mode
10514 11:05:30.527390 <5>[ 0.591988] SCSI subsystem initialized
10515 11:05:30.533940 <6>[ 0.596150] usbcore: registered new interface driver usbfs
10516 11:05:30.540457 <6>[ 0.601883] usbcore: registered new interface driver hub
10517 11:05:30.543881 <6>[ 0.607434] usbcore: registered new device driver usb
10518 11:05:30.550685 <6>[ 0.613533] pps_core: LinuxPPS API ver. 1 registered
10519 11:05:30.561092 <6>[ 0.618727] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10520 11:05:30.563895 <6>[ 0.628071] PTP clock support registered
10521 11:05:30.567244 <6>[ 0.632314] EDAC MC: Ver: 3.0.0
10522 11:05:30.574724 <6>[ 0.637483] FPGA manager framework
10523 11:05:30.578490 <6>[ 0.641170] Advanced Linux Sound Architecture Driver Initialized.
10524 11:05:30.581901 <6>[ 0.647958] vgaarb: loaded
10525 11:05:30.588744 <6>[ 0.651058] clocksource: Switched to clocksource arch_sys_counter
10526 11:05:30.595215 <5>[ 0.657492] VFS: Disk quotas dquot_6.6.0
10527 11:05:30.601729 <6>[ 0.661675] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10528 11:05:30.605244 <6>[ 0.668863] pnp: PnP ACPI: disabled
10529 11:05:30.612702 <6>[ 0.675553] NET: Registered PF_INET protocol family
10530 11:05:30.622859 <6>[ 0.681148] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10531 11:05:30.634055 <6>[ 0.693464] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10532 11:05:30.643908 <6>[ 0.702278] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10533 11:05:30.650888 <6>[ 0.710248] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10534 11:05:30.657403 <6>[ 0.718952] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10535 11:05:30.669659 <6>[ 0.728707] TCP: Hash tables configured (established 65536 bind 65536)
10536 11:05:30.675510 <6>[ 0.735577] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10537 11:05:30.682083 <6>[ 0.742775] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10538 11:05:30.688924 <6>[ 0.750475] NET: Registered PF_UNIX/PF_LOCAL protocol family
10539 11:05:30.695517 <6>[ 0.756633] RPC: Registered named UNIX socket transport module.
10540 11:05:30.699084 <6>[ 0.762787] RPC: Registered udp transport module.
10541 11:05:30.705937 <6>[ 0.767719] RPC: Registered tcp transport module.
10542 11:05:30.712304 <6>[ 0.772650] RPC: Registered tcp NFSv4.1 backchannel transport module.
10543 11:05:30.715508 <6>[ 0.779317] PCI: CLS 0 bytes, default 64
10544 11:05:30.719094 <6>[ 0.783643] Unpacking initramfs...
10545 11:05:30.735874 <6>[ 0.795584] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10546 11:05:30.746530 <6>[ 0.804227] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10547 11:05:30.749477 <6>[ 0.813053] kvm [1]: IPA Size Limit: 40 bits
10548 11:05:30.755895 <6>[ 0.817578] kvm [1]: GICv3: no GICV resource entry
10549 11:05:30.759390 <6>[ 0.822596] kvm [1]: disabling GICv2 emulation
10550 11:05:30.766051 <6>[ 0.827285] kvm [1]: GIC system register CPU interface enabled
10551 11:05:30.772609 <6>[ 0.835100] kvm [1]: vgic interrupt IRQ18
10552 11:05:30.776290 <6>[ 0.839475] kvm [1]: VHE mode initialized successfully
10553 11:05:30.782824 <5>[ 0.845829] Initialise system trusted keyrings
10554 11:05:30.789425 <6>[ 0.850635] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10555 11:05:30.797779 <6>[ 0.860601] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10556 11:05:30.804613 <5>[ 0.866988] NFS: Registering the id_resolver key type
10557 11:05:30.807994 <5>[ 0.872283] Key type id_resolver registered
10558 11:05:30.814798 <5>[ 0.876697] Key type id_legacy registered
10559 11:05:30.820787 <6>[ 0.880977] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10560 11:05:30.827686 <6>[ 0.887898] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10561 11:05:30.834581 <6>[ 0.895604] 9p: Installing v9fs 9p2000 file system support
10562 11:05:30.870580 <5>[ 0.933157] Key type asymmetric registered
10563 11:05:30.873443 <5>[ 0.937486] Asymmetric key parser 'x509' registered
10564 11:05:30.884007 <6>[ 0.942628] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10565 11:05:30.886792 <6>[ 0.950246] io scheduler mq-deadline registered
10566 11:05:30.890444 <6>[ 0.955005] io scheduler kyber registered
10567 11:05:30.909432 <6>[ 0.972160] EINJ: ACPI disabled.
10568 11:05:30.941783 <4>[ 0.998234] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10569 11:05:30.952081 <4>[ 1.008974] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10570 11:05:30.967460 <6>[ 1.029999] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10571 11:05:30.975162 <6>[ 1.037954] printk: console [ttyS0] disabled
10572 11:05:31.002952 <6>[ 1.062589] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10573 11:05:31.009641 <6>[ 1.072060] printk: console [ttyS0] enabled
10574 11:05:31.012871 <6>[ 1.072060] printk: console [ttyS0] enabled
10575 11:05:31.019586 <6>[ 1.080955] printk: bootconsole [mtk8250] disabled
10576 11:05:31.022993 <6>[ 1.080955] printk: bootconsole [mtk8250] disabled
10577 11:05:31.029591 <6>[ 1.092199] SuperH (H)SCI(F) driver initialized
10578 11:05:31.032830 <6>[ 1.097469] msm_serial: driver initialized
10579 11:05:31.047415 <6>[ 1.106471] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10580 11:05:31.057575 <6>[ 1.115026] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10581 11:05:31.063577 <6>[ 1.123567] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10582 11:05:31.074026 <6>[ 1.132194] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10583 11:05:31.080175 <6>[ 1.140901] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10584 11:05:31.090677 <6>[ 1.149614] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10585 11:05:31.100237 <6>[ 1.158154] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10586 11:05:31.107111 <6>[ 1.166975] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10587 11:05:31.116646 <6>[ 1.175518] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10588 11:05:31.128839 <6>[ 1.190988] loop: module loaded
10589 11:05:31.134618 <6>[ 1.196954] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10590 11:05:31.158088 <4>[ 1.220146] mtk-pmic-keys: Failed to locate of_node [id: -1]
10591 11:05:31.163835 <6>[ 1.226943] megasas: 07.719.03.00-rc1
10592 11:05:31.173597 <6>[ 1.236497] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10593 11:05:31.180256 <6>[ 1.238460] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10594 11:05:31.195243 <6>[ 1.257780] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10595 11:05:31.252165 <6>[ 1.308197] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10596 11:05:32.464700 <6>[ 2.527474] Freeing initrd memory: 40220K
10597 11:05:32.475827 <6>[ 2.539160] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10598 11:05:32.486703 <6>[ 2.549933] tun: Universal TUN/TAP device driver, 1.6
10599 11:05:32.490048 <6>[ 2.555991] thunder_xcv, ver 1.0
10600 11:05:32.493751 <6>[ 2.559494] thunder_bgx, ver 1.0
10601 11:05:32.497171 <6>[ 2.562985] nicpf, ver 1.0
10602 11:05:32.507223 <6>[ 2.566997] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10603 11:05:32.510476 <6>[ 2.574472] hns3: Copyright (c) 2017 Huawei Corporation.
10604 11:05:32.517322 <6>[ 2.580058] hclge is initializing
10605 11:05:32.520685 <6>[ 2.583633] e1000: Intel(R) PRO/1000 Network Driver
10606 11:05:32.527063 <6>[ 2.588762] e1000: Copyright (c) 1999-2006 Intel Corporation.
10607 11:05:32.530905 <6>[ 2.594774] e1000e: Intel(R) PRO/1000 Network Driver
10608 11:05:32.537321 <6>[ 2.599991] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10609 11:05:32.543888 <6>[ 2.606176] igb: Intel(R) Gigabit Ethernet Network Driver
10610 11:05:32.550393 <6>[ 2.611826] igb: Copyright (c) 2007-2014 Intel Corporation.
10611 11:05:32.557396 <6>[ 2.617661] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10612 11:05:32.563907 <6>[ 2.624179] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10613 11:05:32.566826 <6>[ 2.630640] sky2: driver version 1.30
10614 11:05:32.573621 <6>[ 2.635576] usbcore: registered new device driver r8152-cfgselector
10615 11:05:32.580225 <6>[ 2.642113] usbcore: registered new interface driver r8152
10616 11:05:32.586702 <6>[ 2.647929] VFIO - User Level meta-driver version: 0.3
10617 11:05:32.593671 <6>[ 2.656181] usbcore: registered new interface driver usb-storage
10618 11:05:32.599872 <6>[ 2.662629] usbcore: registered new device driver onboard-usb-hub
10619 11:05:32.608498 <6>[ 2.671780] mt6397-rtc mt6359-rtc: registered as rtc0
10620 11:05:32.618471 <6>[ 2.677245] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-10T11:05:32 UTC (1720609532)
10621 11:05:32.622080 <6>[ 2.686828] i2c_dev: i2c /dev entries driver
10622 11:05:32.636238 <4>[ 2.698849] cpu cpu0: supply cpu not found, using dummy regulator
10623 11:05:32.642577 <4>[ 2.705278] cpu cpu1: supply cpu not found, using dummy regulator
10624 11:05:32.649508 <4>[ 2.711700] cpu cpu2: supply cpu not found, using dummy regulator
10625 11:05:32.655924 <4>[ 2.718103] cpu cpu3: supply cpu not found, using dummy regulator
10626 11:05:32.662465 <4>[ 2.724500] cpu cpu4: supply cpu not found, using dummy regulator
10627 11:05:32.669349 <4>[ 2.730893] cpu cpu5: supply cpu not found, using dummy regulator
10628 11:05:32.675764 <4>[ 2.737293] cpu cpu6: supply cpu not found, using dummy regulator
10629 11:05:32.683134 <4>[ 2.743709] cpu cpu7: supply cpu not found, using dummy regulator
10630 11:05:32.701663 <6>[ 2.764335] cpu cpu0: EM: created perf domain
10631 11:05:32.704297 <6>[ 2.769269] cpu cpu4: EM: created perf domain
10632 11:05:32.711971 <6>[ 2.774874] sdhci: Secure Digital Host Controller Interface driver
10633 11:05:32.719031 <6>[ 2.781307] sdhci: Copyright(c) Pierre Ossman
10634 11:05:32.725165 <6>[ 2.786259] Synopsys Designware Multimedia Card Interface Driver
10635 11:05:32.732015 <6>[ 2.792908] sdhci-pltfm: SDHCI platform and OF driver helper
10636 11:05:32.735048 <6>[ 2.793030] mmc0: CQHCI version 5.10
10637 11:05:32.742001 <6>[ 2.802914] ledtrig-cpu: registered to indicate activity on CPUs
10638 11:05:32.748445 <6>[ 2.809867] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10639 11:05:32.755327 <6>[ 2.816914] usbcore: registered new interface driver usbhid
10640 11:05:32.758857 <6>[ 2.822736] usbhid: USB HID core driver
10641 11:05:32.765279 <6>[ 2.826933] spi_master spi0: will run message pump with realtime priority
10642 11:05:32.811224 <6>[ 2.868024] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10643 11:05:32.830420 <6>[ 2.883661] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10644 11:05:32.834091 <6>[ 2.892390] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17014
10645 11:05:32.842508 <6>[ 2.905241] cros-ec-spi spi0.0: Chrome EC device registered
10646 11:05:32.849617 <6>[ 2.911233] mmc0: Command Queue Engine enabled
10647 11:05:32.855885 <6>[ 2.915986] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10648 11:05:32.859097 <6>[ 2.923655] mmcblk0: mmc0:0001 DA4128 116 GiB
10649 11:05:32.871886 <6>[ 2.934719] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10650 11:05:32.879702 <6>[ 2.942397] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10651 11:05:32.890121 <6>[ 2.947258] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10652 11:05:32.893002 <6>[ 2.948362] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10653 11:05:32.899930 <6>[ 2.958313] NET: Registered PF_PACKET protocol family
10654 11:05:32.906228 <6>[ 2.962865] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10655 11:05:32.909657 <6>[ 2.967529] 9pnet: Installing 9P2000 support
10656 11:05:32.916403 <5>[ 2.978568] Key type dns_resolver registered
10657 11:05:32.919669 <6>[ 2.983698] registered taskstats version 1
10658 11:05:32.925697 <5>[ 2.988080] Loading compiled-in X.509 certificates
10659 11:05:32.955406 <4>[ 3.011638] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10660 11:05:32.965371 <4>[ 3.022388] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10661 11:05:32.980890 <6>[ 3.044233] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10662 11:05:32.987948 <6>[ 3.051009] xhci-mtk 11200000.usb: xHCI Host Controller
10663 11:05:32.994714 <6>[ 3.056510] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10664 11:05:33.004665 <6>[ 3.064346] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10665 11:05:33.011623 <6>[ 3.073777] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10666 11:05:33.018179 <6>[ 3.080031] xhci-mtk 11200000.usb: xHCI Host Controller
10667 11:05:33.024828 <6>[ 3.085534] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10668 11:05:33.031392 <6>[ 3.093189] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10669 11:05:33.037941 <6>[ 3.101001] hub 1-0:1.0: USB hub found
10670 11:05:33.041260 <6>[ 3.105023] hub 1-0:1.0: 1 port detected
10671 11:05:33.047844 <6>[ 3.109311] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10672 11:05:33.055378 <6>[ 3.118071] hub 2-0:1.0: USB hub found
10673 11:05:33.058218 <6>[ 3.122094] hub 2-0:1.0: 1 port detected
10674 11:05:33.065901 <6>[ 3.129050] mtk-msdc 11f70000.mmc: Got CD GPIO
10675 11:05:33.078056 <6>[ 3.137940] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10676 11:05:33.088036 <6>[ 3.146353] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10677 11:05:33.094981 <6>[ 3.154694] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10678 11:05:33.104612 <6>[ 3.163041] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10679 11:05:33.111367 <6>[ 3.171382] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10680 11:05:33.121410 <6>[ 3.179723] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10681 11:05:33.127856 <6>[ 3.188065] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10682 11:05:33.137621 <6>[ 3.196404] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10683 11:05:33.144692 <6>[ 3.204746] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10684 11:05:33.154170 <6>[ 3.213084] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10685 11:05:33.160810 <6>[ 3.221424] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10686 11:05:33.170858 <6>[ 3.229773] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10687 11:05:33.177582 <6>[ 3.238112] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10688 11:05:33.187630 <6>[ 3.246456] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10689 11:05:33.194341 <6>[ 3.254795] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10690 11:05:33.200890 <6>[ 3.263558] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10691 11:05:33.207462 <6>[ 3.270691] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10692 11:05:33.214308 <6>[ 3.277437] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10693 11:05:33.224976 <6>[ 3.284235] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10694 11:05:33.231746 <6>[ 3.291172] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10695 11:05:33.237441 <6>[ 3.298037] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10696 11:05:33.247980 <6>[ 3.307176] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10697 11:05:33.257533 <6>[ 3.316296] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10698 11:05:33.267680 <6>[ 3.325590] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10699 11:05:33.277435 <6>[ 3.335060] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10700 11:05:33.284154 <6>[ 3.344527] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10701 11:05:33.294160 <6>[ 3.353648] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10702 11:05:33.304104 <6>[ 3.363114] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10703 11:05:33.313718 <6>[ 3.372236] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10704 11:05:33.323844 <6>[ 3.381532] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10705 11:05:33.333700 <6>[ 3.391692] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10706 11:05:33.343585 <6>[ 3.403533] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10707 11:05:33.471362 <6>[ 3.531336] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10708 11:05:33.626166 <6>[ 3.689422] hub 1-1:1.0: USB hub found
10709 11:05:33.629506 <6>[ 3.693936] hub 1-1:1.0: 4 ports detected
10710 11:05:33.641112 <6>[ 3.703949] hub 1-1:1.0: USB hub found
10711 11:05:33.644016 <6>[ 3.708259] hub 1-1:1.0: 4 ports detected
10712 11:05:33.751595 <6>[ 3.811539] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10713 11:05:33.778390 <6>[ 3.841465] hub 2-1:1.0: USB hub found
10714 11:05:33.781478 <6>[ 3.845967] hub 2-1:1.0: 3 ports detected
10715 11:05:33.793664 <6>[ 3.857027] hub 2-1:1.0: USB hub found
10716 11:05:33.797789 <6>[ 3.861521] hub 2-1:1.0: 3 ports detected
10717 11:05:33.963628 <6>[ 4.023379] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10718 11:05:34.096013 <6>[ 4.159168] hub 1-1.4:1.0: USB hub found
10719 11:05:34.099322 <6>[ 4.163822] hub 1-1.4:1.0: 2 ports detected
10720 11:05:34.111374 <6>[ 4.174538] hub 1-1.4:1.0: USB hub found
10721 11:05:34.114652 <6>[ 4.179059] hub 1-1.4:1.0: 2 ports detected
10722 11:05:34.183505 <6>[ 4.243470] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10723 11:05:34.292214 <6>[ 4.352008] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10724 11:05:34.328285 <4>[ 4.388472] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10725 11:05:34.338626 <4>[ 4.397661] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10726 11:05:34.373681 <6>[ 4.436913] r8152 2-1.3:1.0 eth0: v1.12.13
10727 11:05:34.427884 <6>[ 4.487407] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10728 11:05:34.623736 <6>[ 4.683236] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10729 11:05:36.048145 <6>[ 6.111163] r8152 2-1.3:1.0 eth0: carrier on
10730 11:05:36.092232 <5>[ 6.139178] Sending DHCP requests ., OK
10731 11:05:36.098602 <6>[ 6.159448] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10732 11:05:36.102074 <6>[ 6.167737] IP-Config: Complete:
10733 11:05:36.115478 <6>[ 6.171238] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10734 11:05:36.121586 <6>[ 6.181957] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10735 11:05:36.128258 <6>[ 6.190576] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10736 11:05:36.135198 <6>[ 6.190586] nameserver0=192.168.201.1
10737 11:05:36.138328 <6>[ 6.202693] clk: Disabling unused clocks
10738 11:05:36.141703 <6>[ 6.208227] ALSA device list:
10739 11:05:36.145041 <6>[ 6.211482] No soundcards found.
10740 11:05:36.156295 <6>[ 6.219183] Freeing unused kernel memory: 8512K
10741 11:05:36.159139 <6>[ 6.224117] Run /init as init process
10742 11:05:36.191846 <6>[ 6.255548] NET: Registered PF_INET6 protocol family
10743 11:05:36.198929 <6>[ 6.262297] Segment Routing with IPv6
10744 11:05:36.202149 <6>[ 6.266246] In-situ OAM (IOAM) with IPv6
10745 11:05:36.243200 <30>[ 6.279854] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10746 11:05:36.249444 <30>[ 6.312884] systemd[1]: Detected architecture arm64.
10747 11:05:36.249520
10748 11:05:36.253235 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10749 11:05:36.256012
10750 11:05:36.271656 <30>[ 6.335359] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10751 11:05:36.388472 <30>[ 6.448894] systemd[1]: Queued start job for default target graphical.target.
10752 11:05:36.441572 <30>[ 6.501261] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10753 11:05:36.447951 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10754 11:05:36.467314 <30>[ 6.527656] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10755 11:05:36.474105 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10756 11:05:36.496433 <30>[ 6.556764] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10757 11:05:36.506654 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10758 11:05:36.523562 <30>[ 6.583771] systemd[1]: Created slice user.slice - User and Session Slice.
10759 11:05:36.530092 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10760 11:05:36.551136 <30>[ 6.607926] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10761 11:05:36.560869 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10762 11:05:36.579593 <30>[ 6.636039] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10763 11:05:36.586097 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10764 11:05:36.613064 <30>[ 6.663358] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10765 11:05:36.622910 <30>[ 6.683127] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10766 11:05:36.629780 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10767 11:05:36.647935 <30>[ 6.707673] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10768 11:05:36.654171 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10769 11:05:36.671309 <30>[ 6.731358] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10770 11:05:36.681654 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10771 11:05:36.695648 <30>[ 6.759420] systemd[1]: Reached target paths.target - Path Units.
10772 11:05:36.705890 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10773 11:05:36.723727 <30>[ 6.783665] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10774 11:05:36.730122 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10775 11:05:36.743735 <30>[ 6.807305] systemd[1]: Reached target slices.target - Slice Units.
10776 11:05:36.754348 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10777 11:05:36.768266 <30>[ 6.831806] systemd[1]: Reached target swap.target - Swaps.
10778 11:05:36.775022 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10779 11:05:36.795529 <30>[ 6.855824] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10780 11:05:36.805435 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10781 11:05:36.824001 <30>[ 6.883736] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10782 11:05:36.833527 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10783 11:05:36.852366 <30>[ 6.912661] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10784 11:05:36.862385 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10785 11:05:36.879394 <30>[ 6.939858] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10786 11:05:36.889808 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10787 11:05:36.907783 <30>[ 6.967899] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10788 11:05:36.914105 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10789 11:05:36.931459 <30>[ 6.991945] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10790 11:05:36.941469 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10791 11:05:36.960495 <30>[ 7.020681] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10792 11:05:36.970339 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10793 11:05:36.987878 <30>[ 7.048431] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10794 11:05:36.997912 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10795 11:05:37.047172 <30>[ 7.107568] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10796 11:05:37.054182 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10797 11:05:37.075330 <30>[ 7.135233] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10798 11:05:37.081567 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10799 11:05:37.103342 <30>[ 7.163491] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10800 11:05:37.110065 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10801 11:05:37.134486 <30>[ 7.187792] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10802 11:05:37.171448 <30>[ 7.231708] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10803 11:05:37.181093 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10804 11:05:37.204493 <30>[ 7.264634] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10805 11:05:37.211289 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10806 11:05:37.236793 <30>[ 7.296680] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10807 11:05:37.249831 Starting [0;1;39mmodpr<6>[ 7.308010] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10808 11:05:37.253424 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10809 11:05:37.276654 <30>[ 7.336893] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10810 11:05:37.283339 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10811 11:05:37.339599 <30>[ 7.399808] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10812 11:05:37.346381 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10813 11:05:37.372947 <30>[ 7.432664] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10814 11:05:37.379340 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10815 11:05:37.407938 <30>[ 7.468228] systemd[1]: Starting systemd-journald.service - Journal Service...
10816 11:05:37.414825 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10817 11:05:37.433736 <30>[ 7.494152] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10818 11:05:37.440445 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10819 11:05:37.465531 <30>[ 7.522589] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10820 11:05:37.472089 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10821 11:05:37.495809 <30>[ 7.555939] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10822 11:05:37.505861 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10823 11:05:37.526042 <30>[ 7.586353] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10824 11:05:37.532725 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10825 11:05:37.556657 <30>[ 7.617165] systemd[1]: Started systemd-journald.service - Journal Service.
10826 11:05:37.563532 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10827 11:05:37.585657 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10828 11:05:37.604793 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10829 11:05:37.624480 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10830 11:05:37.644193 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10831 11:05:37.664686 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10832 11:05:37.689653 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10833 11:05:37.714499 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10834 11:05:37.734385 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10835 11:05:37.761331 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10836 11:05:37.781756 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10837 11:05:37.801311 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10838 11:05:37.821610 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10839 11:05:37.835435 See 'systemctl status systemd-remount-fs.service' for details.
10840 11:05:37.856480 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10841 11:05:37.882169 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10842 11:05:37.915524 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10843 11:05:37.936178 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10844 11:05:37.956805 <46>[ 8.017272] systemd-journald[193]: Received client request to flush runtime journal.
10845 11:05:37.963492 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10846 11:05:37.991309 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10847 11:05:38.011335 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10848 11:05:38.037266 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10849 11:05:38.060768 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10850 11:05:38.081013 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10851 11:05:38.100517 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10852 11:05:38.120344 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10853 11:05:38.163585 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10854 11:05:38.187369 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10855 11:05:38.203488 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10856 11:05:38.219418 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10857 11:05:38.256397 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10858 11:05:38.282192 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10859 11:05:38.306111 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10860 11:05:38.327728 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10861 11:05:38.367970 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10862 11:05:38.444922 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10863 11:05:38.470402 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10864 11:05:38.499802 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10865 11:05:38.536176 <5>[ 8.596863] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10866 11:05:38.572769 [[0;32m OK [<5>[ 8.633058] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10867 11:05:38.582428 0m] Started [0;<5>[ 8.641860] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10868 11:05:38.592992 1;39msystemd-tim<4>[ 8.651347] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10869 11:05:38.599186 esyncd.…0m - N<6>[ 8.661487] cfg80211: failed to load regulatory.db
10870 11:05:38.602928 etwork Time Synchronization.
10871 11:05:38.623474 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10872 11:05:38.640940 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10873 11:05:38.706688 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10874 11:05:38.731725 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10875 11:05:38.754900 [[0;32m OK [0m] Started [0;1;39msystemd-tmp<6>[ 8.815684] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10876 11:05:38.765334 files-c… Clean<6>[ 8.823699] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10877 11:05:38.771893 <6>[ 8.827049] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10878 11:05:38.781256 <6>[ 8.833680] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10879 11:05:38.788213 <6>[ 8.847400] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10880 11:05:38.797823 <3>[ 8.851313] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10881 11:05:38.808213 up of Temporary <6>[ 8.858338] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10882 11:05:38.808292 Directories.
10883 11:05:38.817942 <3>[ 8.866434] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10884 11:05:38.824430 <3>[ 8.866444] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10885 11:05:38.831337 <3>[ 8.868348] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10886 11:05:38.841178 <6>[ 8.872199] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10887 11:05:38.847523 <4>[ 8.875848] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10888 11:05:38.857967 <3>[ 8.885206] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10889 11:05:38.864310 <6>[ 8.893725] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10890 11:05:38.874985 <3>[ 8.901962] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10891 11:05:38.881769 <6>[ 8.908602] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10892 11:05:38.887710 <6>[ 8.909370] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10893 11:05:38.894544 <6>[ 8.911790] remoteproc remoteproc0: scp is available
10894 11:05:38.901011 <6>[ 8.911855] remoteproc remoteproc0: powering up scp
10895 11:05:38.907808 <6>[ 8.911860] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10896 11:05:38.914166 <6>[ 8.911879] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10897 11:05:38.920965 <3>[ 8.917716] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10898 11:05:38.930935 <6>[ 8.925774] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10899 11:05:38.937877 <3>[ 8.933842] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10900 11:05:38.941019 <6>[ 8.934848] mc: Linux media interface: v0.10
10901 11:05:38.951519 <4>[ 8.938985] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10902 11:05:38.957740 <6>[ 8.941916] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10903 11:05:38.965248 <4>[ 8.951156] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10904 11:05:38.971441 <6>[ 8.956184] videodev: Linux video capture interface: v2.00
10905 11:05:38.978354 <3>[ 8.957660] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10906 11:05:38.988119 <6>[ 8.957724] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10907 11:05:38.995323 <3>[ 8.967129] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10908 11:05:39.002150 <6>[ 8.971915] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10909 11:05:39.012158 <3>[ 8.976731] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10910 11:05:39.019459 <6>[ 8.983893] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10911 11:05:39.025556 <3>[ 8.990395] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10912 11:05:39.035389 <4>[ 9.001786] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10913 11:05:39.038853 <4>[ 9.001786] Fallback method does not support PEC.
10914 11:05:39.045721 <6>[ 9.006613] pci_bus 0000:00: root bus resource [bus 00-ff]
10915 11:05:39.052013 <3>[ 9.008146] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10916 11:05:39.062119 <3>[ 9.008174] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10917 11:05:39.068653 <3>[ 9.008178] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10918 11:05:39.078686 <3>[ 9.008184] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10919 11:05:39.085466 <3>[ 9.008188] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10920 11:05:39.095297 <3>[ 9.027520] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10921 11:05:39.101930 <6>[ 9.032631] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10922 11:05:39.109298 <6>[ 9.033451] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10923 11:05:39.119282 <6>[ 9.033460] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10924 11:05:39.126138 <3>[ 9.037943] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 11:05:39.136544 <6>[ 9.039228] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10926 11:05:39.144029 <6>[ 9.047319] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10927 11:05:39.147032 <6>[ 9.056392] remoteproc remoteproc0: remote processor scp is now up
10928 11:05:39.157111 <6>[ 9.064477] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10929 11:05:39.163282 <3>[ 9.073217] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 11:05:39.170233 <6>[ 9.080244] pci 0000:00:00.0: supports D1 D2
10931 11:05:39.179903 <6>[ 9.082551] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10932 11:05:39.189869 <6>[ 9.124975] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10933 11:05:39.196732 <6>[ 9.130642] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10934 11:05:39.203459 <6>[ 9.131643] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10935 11:05:39.213032 <6>[ 9.139468] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10936 11:05:39.219977 <6>[ 9.146932] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10937 11:05:39.226676 <6>[ 9.176680] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10938 11:05:39.236645 <6>[ 9.177261] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10939 11:05:39.243253 <3>[ 9.178515] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 11:05:39.253464 <6>[ 9.190041] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10941 11:05:39.260103 <6>[ 9.195888] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10942 11:05:39.266428 <6>[ 9.195904] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10943 11:05:39.269870 <6>[ 9.196567] Bluetooth: Core ver 2.22
10944 11:05:39.276433 <6>[ 9.196680] NET: Registered PF_BLUETOOTH protocol family
10945 11:05:39.283127 <6>[ 9.196683] Bluetooth: HCI device and connection manager initialized
10946 11:05:39.286722 <6>[ 9.196713] Bluetooth: HCI socket layer initialized
10947 11:05:39.292969 <6>[ 9.196722] Bluetooth: L2CAP socket layer initialized
10948 11:05:39.299664 <6>[ 9.196733] Bluetooth: SCO socket layer initialized
10949 11:05:39.306700 <6>[ 9.212407] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10950 11:05:39.309682 <6>[ 9.217219] pci 0000:01:00.0: supports D1 D2
10951 11:05:39.320845 <3>[ 9.225778] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 11:05:39.330753 <6>[ 9.226392] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10953 11:05:39.336024 <6>[ 9.226523] usbcore: registered new interface driver uvcvideo
10954 11:05:39.343036 <6>[ 9.233414] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10955 11:05:39.349635 <6>[ 9.235274] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10956 11:05:39.356296 <6>[ 9.242373] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10957 11:05:39.362584 <6>[ 9.248063] usbcore: registered new interface driver btusb
10958 11:05:39.373008 <4>[ 9.248889] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10959 11:05:39.379111 <3>[ 9.248901] Bluetooth: hci0: Failed to load firmware file (-2)
10960 11:05:39.385764 <3>[ 9.248905] Bluetooth: hci0: Failed to set up firmware (-2)
10961 11:05:39.396175 <4>[ 9.248907] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10962 11:05:39.402425 <6>[ 9.257392] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10963 11:05:39.412229 <6>[ 9.472555] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10964 11:05:39.419264 <6>[ 9.472567] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10965 11:05:39.429055 <6>[ 9.472581] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10966 11:05:39.435604 <6>[ 9.472594] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10967 11:05:39.442080 <6>[ 9.472606] pci 0000:00:00.0: PCI bridge to [bus 01]
10968 11:05:39.448889 <6>[ 9.472611] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10969 11:05:39.455416 <6>[ 9.472768] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10970 11:05:39.462148 [[0;32m OK [<6>[ 9.524913] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10971 11:05:39.469106 0m] Reached targ<6>[ 9.532721] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10972 11:05:39.475578 et [0;1;39mtime-set.target[0m - System Time Set.
10973 11:05:39.499302 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10974 11:05:39.522338 [[0;32m OK [0m] Reached target [0;1;39mtime<6>[ 9.582883] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10975 11:05:39.529088 rs.target[0m - <6>[ 9.590748] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10976 11:05:39.529173 Timer Units.
10977 11:05:39.539328 <3>[ 9.591454] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 11:05:39.549338 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10979 11:05:39.555537 <6>[ 9.617674] mt7921e 0000:01:00.0: ASIC revision: 79610010
10980 11:05:39.562666 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10981 11:05:39.577391 <3>[ 9.637646] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10982 11:05:39.583918 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10983 11:05:39.625866 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10984 11:05:39.657007 <6>[ 9.717549] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10985 11:05:39.660445 <6>[ 9.717549]
10986 11:05:39.672089 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10987 11:05:39.681671 <3>[ 9.741290] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10988 11:05:39.696136 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10989 11:05:39.719519 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus Sy<3>[ 9.776974] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10990 11:05:39.719597 stem Message Bus.
10991 11:05:39.751832 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10992 11:05:39.771388 <3>[ 9.831506] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10993 11:05:39.806888 [[0;32m OK [0m] Started [0;<3>[ 9.865484] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10994 11:05:39.809687 1;39msystemd-logind.service[0m - User Login Management.
10995 11:05:39.834115 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10996 11:05:39.850478 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10997 11:05:39.870605 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10998 11:05:39.907596 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10999 11:05:39.926281 <6>[ 9.987001] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11000 11:05:39.936330 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11001 11:05:39.954073 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11002 11:05:39.968616 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11003 11:05:39.988567 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11004 11:05:40.041239 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11005 11:05:40.066139 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11006 11:05:40.090930 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11007 11:05:40.172513 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11008 11:05:40.191969 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11009 11:05:40.216570 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11010 11:05:40.255177
11011 11:05:40.258444 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11012 11:05:40.258521
11013 11:05:40.262164 debian-bookworm-arm64 login: root (automatic login)
11014 11:05:40.262262
11015 11:05:40.279449 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 10 10:43:20 UTC 2024 aarch64
11016 11:05:40.279531
11017 11:05:40.286051 The programs included with the Debian GNU/Linux system are free software;
11018 11:05:40.292644 the exact distribution terms for each program are described in the
11019 11:05:40.296291 individual files in /usr/share/doc/*/copyright.
11020 11:05:40.296389
11021 11:05:40.302941 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11022 11:05:40.306207 permitted by applicable law.
11023 11:05:40.306579 Matched prompt #10: / #
11025 11:05:40.306761 Setting prompt string to ['/ #']
11026 11:05:40.306848 end: 2.2.5.1 login-action (duration 00:00:11) [common]
11028 11:05:40.307021 end: 2.2.5 auto-login-action (duration 00:00:11) [common]
11029 11:05:40.307098 start: 2.2.6 expect-shell-connection (timeout 00:03:01) [common]
11030 11:05:40.307157 Setting prompt string to ['/ #']
11031 11:05:40.307211 Forcing a shell prompt, looking for ['/ #']
11032 11:05:40.307265 Sending line: ''
11034 11:05:40.357540 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11035 11:05:40.357609 Waiting using forced prompt support (timeout 00:02:30)
11036 11:05:40.362525 / #
11037 11:05:40.362804 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11038 11:05:40.362889 start: 2.2.7 export-device-env (timeout 00:03:01) [common]
11039 11:05:40.362975 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11040 11:05:40.363054 end: 2.2 depthcharge-retry (duration 00:01:59) [common]
11041 11:05:40.363134 end: 2 depthcharge-action (duration 00:01:59) [common]
11042 11:05:40.363213 start: 3 lava-test-retry (timeout 00:07:39) [common]
11043 11:05:40.363293 start: 3.1 lava-test-shell (timeout 00:07:39) [common]
11044 11:05:40.363365 Using namespace: common
11045 11:05:40.363427 Sending line: '#'
11047 11:05:40.463842 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11048 11:05:40.468758 / # #
11049 11:05:40.469008 Using /lava-14786807
11050 11:05:40.469070 Sending line: 'export SHELL=/bin/sh'
11052 11:05:40.574499 / # export SHELL=/bin/sh
11053 11:05:40.574789 Sending line: '. /lava-14786807/environment'
11055 11:05:40.679885 / # . /lava-14786807/environment
11056 11:05:40.680143 Sending line: '/lava-14786807/bin/lava-test-runner /lava-14786807/0'
11058 11:05:40.780567 Test shell timeout: 10s (minimum of the action and connection timeout)
11059 11:05:40.785350 / # /lava-14786807/bin/lava-test-runner /lava-14786807/0
11060 11:05:40.802962 <6>[ 10.867119] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11061 11:05:40.810545 + export TESTRUN_ID=0_v4l2-compliance-uvc
11062 11:05:40.813334 + cd /lava-14786807/0/tests/0_v4l2-compliance-uvc
11063 11:05:40.813434 + cat uuid
11064 11:05:40.816631 + UUID=14786807_1.5.2.3.1
11065 11:05:40.816724 + set +x
11066 11:05:40.823411 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 14786807_1.5.2.3.1>
11067 11:05:40.823684 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 14786807_1.5.2.3.1
11068 11:05:40.823777 Starting test lava.0_v4l2-compliance-uvc (14786807_1.5.2.3.1)
11069 11:05:40.823882 Skipping test definition patterns.
11070 11:05:40.826710 + /usr/bin/v4l2-parser.sh -d uvcvideo
11071 11:05:40.833148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11072 11:05:40.833228 device: /dev/video0
11073 11:05:40.833452 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11075 11:05:47.334997 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11076 11:05:47.346241 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11077 11:05:47.354564
11078 11:05:47.372874 Compliance test for uvcvideo device /dev/video0:
11079 11:05:47.380178
11080 11:05:47.397021 Driver Info:
11081 11:05:47.408925 Driver name : uvcvideo
11082 11:05:47.426085 Card type : HD User Facing: HD User Facing
11083 11:05:47.439417 Bus info : usb-11200000.usb-1.4.1
11084 11:05:47.450095 Driver version : 6.1.96
11085 11:05:47.461268 Capabilities : 0x84a00001
11086 11:05:47.477870 Metadata Capture
11087 11:05:47.489392 Streaming
11088 11:05:47.503403 Extended Pix Format
11089 11:05:47.514188 Device Capabilities
11090 11:05:47.524979 Device Caps : 0x04200001
11091 11:05:47.540009 Streaming
11092 11:05:47.553875 Extended Pix Format
11093 11:05:47.568493 Media Driver Info:
11094 11:05:47.579794 Driver name : uvcvideo
11095 11:05:47.593848 Model : HD User Facing: HD User Facing
11096 11:05:47.605358 Serial : 200901010001
11097 11:05:47.620519 Bus info : usb-11200000.usb-1.4.1
11098 11:05:47.629174 Media version : 6.1.96
11099 11:05:47.642933 Hardware revision: 0x00009758 (38744)
11100 11:05:47.652543 Driver version : 6.1.96
11101 11:05:47.664098 Interface Info:
11102 11:05:47.678450 <LAVA_SIGNAL_TESTSET START Interface-Info>
11103 11:05:47.678526 ID : 0x03000002
11104 11:05:47.678759 Received signal: <TESTSET> START Interface-Info
11105 11:05:47.678823 Starting test_set Interface-Info
11106 11:05:47.690257 Type : V4L Video
11107 11:05:47.699773 Entity Info:
11108 11:05:47.707240 <LAVA_SIGNAL_TESTSET STOP>
11109 11:05:47.707482 Received signal: <TESTSET> STOP
11110 11:05:47.707545 Closing test_set Interface-Info
11111 11:05:47.716351 <LAVA_SIGNAL_TESTSET START Entity-Info>
11112 11:05:47.716594 Received signal: <TESTSET> START Entity-Info
11113 11:05:47.716659 Starting test_set Entity-Info
11114 11:05:47.719260 ID : 0x00000001 (1)
11115 11:05:47.729303 Name : HD User Facing: HD User Facing
11116 11:05:47.737798 Function : V4L2 I/O
11117 11:05:47.748897 Flags : default
11118 11:05:47.759336 Pad 0x01000007 : 0: Sink
11119 11:05:47.781491 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11120 11:05:47.781598
11121 11:05:47.793017 Required ioctls:
11122 11:05:47.799849 <LAVA_SIGNAL_TESTSET STOP>
11123 11:05:47.800094 Received signal: <TESTSET> STOP
11124 11:05:47.800159 Closing test_set Entity-Info
11125 11:05:47.809040 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11126 11:05:47.809343 Received signal: <TESTSET> START Required-ioctls
11127 11:05:47.809406 Starting test_set Required-ioctls
11128 11:05:47.812429 test MC information (see 'Media Driver Info' above): OK
11129 11:05:47.836967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11130 11:05:47.837213 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11132 11:05:47.840748 test VIDIOC_QUERYCAP: OK
11133 11:05:47.861757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11134 11:05:47.862001 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11136 11:05:47.864841 test invalid ioctls: OK
11137 11:05:47.886267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11138 11:05:47.886343
11139 11:05:47.886568 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11141 11:05:47.896474 Allow for multiple opens:
11142 11:05:47.902559 <LAVA_SIGNAL_TESTSET STOP>
11143 11:05:47.902801 Received signal: <TESTSET> STOP
11144 11:05:47.902865 Closing test_set Required-ioctls
11145 11:05:47.912519 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11146 11:05:47.912761 Received signal: <TESTSET> START Allow-for-multiple-opens
11147 11:05:47.912823 Starting test_set Allow-for-multiple-opens
11148 11:05:47.915530 test second /dev/video0 open: OK
11149 11:05:47.937189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11150 11:05:47.937430 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11152 11:05:47.939883 test VIDIOC_QUERYCAP: OK
11153 11:05:47.962441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11154 11:05:47.962663 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11156 11:05:47.965758 test VIDIOC_G/S_PRIORITY: OK
11157 11:05:47.992696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11158 11:05:47.992963 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11160 11:05:47.996056 test for unlimited opens: OK
11161 11:05:48.015969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11162 11:05:48.016072
11163 11:05:48.016322 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11165 11:05:48.025399 Debug ioctls:
11166 11:05:48.031661 <LAVA_SIGNAL_TESTSET STOP>
11167 11:05:48.031900 Received signal: <TESTSET> STOP
11168 11:05:48.031961 Closing test_set Allow-for-multiple-opens
11169 11:05:48.041976 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11170 11:05:48.042217 Received signal: <TESTSET> START Debug-ioctls
11171 11:05:48.042294 Starting test_set Debug-ioctls
11172 11:05:48.045345 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11173 11:05:48.065821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11174 11:05:48.066069 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11176 11:05:48.072552 test VIDIOC_LOG_STATUS: OK (Not Supported)
11177 11:05:48.091658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11178 11:05:48.091735
11179 11:05:48.091959 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11181 11:05:48.101839 Input ioctls:
11182 11:05:48.108640 <LAVA_SIGNAL_TESTSET STOP>
11183 11:05:48.108912 Received signal: <TESTSET> STOP
11184 11:05:48.109000 Closing test_set Debug-ioctls
11185 11:05:48.119245 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11186 11:05:48.119488 Received signal: <TESTSET> START Input-ioctls
11187 11:05:48.119550 Starting test_set Input-ioctls
11188 11:05:48.122280 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11189 11:05:48.152760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11190 11:05:48.153008 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11192 11:05:48.155517 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11193 11:05:48.173579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11194 11:05:48.173848 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11196 11:05:48.180180 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11197 11:05:48.203930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11198 11:05:48.204176 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11200 11:05:48.211001 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11201 11:05:48.229106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11202 11:05:48.229389 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11204 11:05:48.232478 test VIDIOC_G/S/ENUMINPUT: OK
11205 11:05:48.254534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11206 11:05:48.254777 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11208 11:05:48.258105 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11209 11:05:48.280291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11210 11:05:48.280542 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11212 11:05:48.283768 Inputs: 1 Audio Inputs: 0 Tuners: 0
11213 11:05:48.290007
11214 11:05:48.308351 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11215 11:05:48.331354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11216 11:05:48.331634 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11218 11:05:48.337478 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11219 11:05:48.354837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11220 11:05:48.355104 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11222 11:05:48.361255 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11223 11:05:48.386918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11224 11:05:48.387195 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11226 11:05:48.393287 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11227 11:05:48.412512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11228 11:05:48.412763 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11230 11:05:48.418766 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11231 11:05:48.434224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11232 11:05:48.434325
11233 11:05:48.434582 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11235 11:05:48.454699 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11236 11:05:48.475220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11237 11:05:48.475469 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11239 11:05:48.481913 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11240 11:05:48.502503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11241 11:05:48.502745 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11243 11:05:48.506124 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11244 11:05:48.524096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11245 11:05:48.524355 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11247 11:05:48.527035 test VIDIOC_G/S_EDID: OK (Not Supported)
11248 11:05:48.547920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11249 11:05:48.548020
11250 11:05:48.548276 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11252 11:05:48.561565 Control ioctls (Input 0):
11253 11:05:48.568988 <LAVA_SIGNAL_TESTSET STOP>
11254 11:05:48.569248 Received signal: <TESTSET> STOP
11255 11:05:48.569312 Closing test_set Input-ioctls
11256 11:05:48.578023 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11257 11:05:48.578266 Received signal: <TESTSET> START Control-ioctls-Input-0
11258 11:05:48.578327 Starting test_set Control-ioctls-Input-0
11259 11:05:48.581472 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11260 11:05:48.606917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11261 11:05:48.607012 test VIDIOC_QUERYCTRL: OK
11262 11:05:48.607275 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11264 11:05:48.626604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11265 11:05:48.626851 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11267 11:05:48.630055 test VIDIOC_G/S_CTRL: OK
11268 11:05:48.653624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11269 11:05:48.653928 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11271 11:05:48.656784 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11272 11:05:48.683353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11273 11:05:48.683633 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11275 11:05:48.689715 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11276 11:05:48.712720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11277 11:05:48.713002 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11279 11:05:48.716400 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11280 11:05:48.734778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11281 11:05:48.735030 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11283 11:05:48.738298 Standard Controls: 16 Private Controls: 0
11284 11:05:48.746749
11285 11:05:48.759882 Format ioctls (Input 0):
11286 11:05:48.767312 <LAVA_SIGNAL_TESTSET STOP>
11287 11:05:48.767558 Received signal: <TESTSET> STOP
11288 11:05:48.767619 Closing test_set Control-ioctls-Input-0
11289 11:05:48.776840 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11290 11:05:48.777107 Received signal: <TESTSET> START Format-ioctls-Input-0
11291 11:05:48.777211 Starting test_set Format-ioctls-Input-0
11292 11:05:48.779979 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11293 11:05:48.807070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11294 11:05:48.807320 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11296 11:05:48.810389 test VIDIOC_G/S_PARM: OK
11297 11:05:48.829383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11298 11:05:48.829629 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11300 11:05:48.832716 test VIDIOC_G_FBUF: OK (Not Supported)
11301 11:05:48.854628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11302 11:05:48.854874 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11304 11:05:48.857762 test VIDIOC_G_FMT: OK
11305 11:05:48.877534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11306 11:05:48.877778 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11308 11:05:48.880793 test VIDIOC_TRY_FMT: OK
11309 11:05:48.901536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11310 11:05:48.901778 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11312 11:05:48.908353 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
11313 11:05:48.913412 test VIDIOC_S_FMT: OK
11314 11:05:48.939969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11315 11:05:48.940209 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11317 11:05:48.943215 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11318 11:05:48.964518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11319 11:05:48.964760 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11321 11:05:48.968000 test Cropping: OK (Not Supported)
11322 11:05:48.993894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11323 11:05:48.994144 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11325 11:05:48.996771 test Composing: OK (Not Supported)
11326 11:05:49.019651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11327 11:05:49.019895 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11329 11:05:49.023178 test Scaling: OK (Not Supported)
11330 11:05:49.043245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11331 11:05:49.043328
11332 11:05:49.043578 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11334 11:05:49.055011 Codec ioctls (Input 0):
11335 11:05:49.065247 <LAVA_SIGNAL_TESTSET STOP>
11336 11:05:49.065492 Received signal: <TESTSET> STOP
11337 11:05:49.065554 Closing test_set Format-ioctls-Input-0
11338 11:05:49.076237 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11339 11:05:49.076477 Received signal: <TESTSET> START Codec-ioctls-Input-0
11340 11:05:49.076538 Starting test_set Codec-ioctls-Input-0
11341 11:05:49.079435 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11342 11:05:49.101110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11343 11:05:49.101415 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11345 11:05:49.107720 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11346 11:05:49.129414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11347 11:05:49.129663 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11349 11:05:49.136096 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11350 11:05:49.154416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11351 11:05:49.154497
11352 11:05:49.154722 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11354 11:05:49.165141 Buffer ioctls (Input 0):
11355 11:05:49.170791 <LAVA_SIGNAL_TESTSET STOP>
11356 11:05:49.171033 Received signal: <TESTSET> STOP
11357 11:05:49.171097 Closing test_set Codec-ioctls-Input-0
11358 11:05:49.181081 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11359 11:05:49.181396 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11360 11:05:49.181487 Starting test_set Buffer-ioctls-Input-0
11361 11:05:49.184039 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11362 11:05:49.208668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11363 11:05:49.208913 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11365 11:05:49.211861 test CREATE_BUFS maximum buffers: OK
11366 11:05:49.230146 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11368 11:05:49.233061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11369 11:05:49.233163 test VIDIOC_EXPBUF: OK
11370 11:05:49.256498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11371 11:05:49.256742 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11373 11:05:49.259714 test Requests: OK (Not Supported)
11374 11:05:49.280441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11375 11:05:49.280521
11376 11:05:49.280747 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11378 11:05:49.289576 Test input 0:
11379 11:05:49.303942
11380 11:05:49.316805 Streaming ioctls:
11381 11:05:49.324023 <LAVA_SIGNAL_TESTSET STOP>
11382 11:05:49.324297 Received signal: <TESTSET> STOP
11383 11:05:49.324388 Closing test_set Buffer-ioctls-Input-0
11384 11:05:49.334269 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11385 11:05:49.334509 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11386 11:05:49.334570 Starting test_set Streaming-ioctls_Test-input-0
11387 11:05:49.337191 test read/write: OK (Not Supported)
11388 11:05:49.359444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11389 11:05:49.359695 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11391 11:05:49.362619 test blocking wait: OK
11392 11:05:49.383573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11393 11:05:49.383876 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11395 11:05:49.390272 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11396 11:05:49.393421 test MMAP (no poll): FAIL
11397 11:05:49.419884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11398 11:05:49.420134 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11400 11:05:49.426861 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11401 11:05:49.434546 test MMAP (select): FAIL
11402 11:05:49.464047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11403 11:05:49.464292 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11405 11:05:49.470715 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11406 11:05:49.476240 test MMAP (epoll): FAIL
11407 11:05:49.503546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11408 11:05:49.503624
11409 11:05:49.503848 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11411 11:05:49.517165
11412 11:05:49.695987
11413 11:05:49.706874 test USERPTR (no poll): OK
11414 11:05:49.732094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11415 11:05:49.732171
11416 11:05:49.732397 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11418 11:05:49.744737
11419 11:05:49.922069
11420 11:05:49.930674 test USERPTR (select): OK
11421 11:05:49.958907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11422 11:05:49.959156 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11424 11:05:49.965704 test DMABUF: Cannot test, specify --expbuf-device
11425 11:05:49.970057
11426 11:05:49.991101 Total for uvcvideo device /dev/video0: 54, Succeeded: 51, Failed: 3, Warnings: 3
11427 11:05:49.994374 <LAVA_TEST_RUNNER EXIT>
11428 11:05:49.994639 ok: lava_test_shell seems to have completed
11429 11:05:49.994711 Marking unfinished test run as failed
11431 11:05:49.995526 device-presence: pass
MC-information-see-Media-Driver-Info-above:
set: Required-ioctls
result: pass
VIDIOC_QUERYCAP:
set: Allow-for-multiple-opens
result: pass
invalid-ioctls:
set: Required-ioctls
result: pass
second-/dev/video0-open:
set: Allow-for-multiple-opens
result: pass
VIDIOC_G/S_PRIORITY:
set: Allow-for-multiple-opens
result: pass
for-unlimited-opens:
set: Allow-for-multiple-opens
result: pass
VIDIOC_DBG_G/S_REGISTER:
set: Debug-ioctls
result: pass
VIDIOC_LOG_STATUS:
set: Debug-ioctls
result: pass
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
set: Input-ioctls
result: pass
VIDIOC_G/S_FREQUENCY:
set: Input-ioctls
result: pass
VIDIOC_S_HW_FREQ_SEEK:
set: Input-ioctls
result: pass
VIDIOC_ENUMAUDIO:
set: Input-ioctls
result: pass
VIDIOC_G/S/ENUMINPUT:
set: Input-ioctls
result: pass
VIDIOC_G/S_AUDIO:
set: Input-ioctls
result: pass
VIDIOC_G/S_MODULATOR:
set: Input-ioctls
result: pass
VIDIOC_ENUMAUDOUT:
set: Input-ioctls
result: pass
VIDIOC_G/S/ENUMOUTPUT:
set: Input-ioctls
result: pass
VIDIOC_G/S_AUDOUT:
set: Input-ioctls
result: pass
VIDIOC_ENUM/G/S/QUERY_STD:
set: Input-ioctls
result: pass
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
set: Input-ioctls
result: pass
VIDIOC_DV_TIMINGS_CAP:
set: Input-ioctls
result: pass
VIDIOC_G/S_EDID:
set: Input-ioctls
result: pass
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
set: Control-ioctls-Input-0
result: pass
VIDIOC_QUERYCTRL:
set: Control-ioctls-Input-0
result: pass
VIDIOC_G/S_CTRL:
set: Control-ioctls-Input-0
result: pass
VIDIOC_G/S/TRY_EXT_CTRLS:
set: Control-ioctls-Input-0
result: pass
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
set: Control-ioctls-Input-0
result: pass
VIDIOC_G/S_JPEGCOMP:
set: Control-ioctls-Input-0
result: pass
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
set: Format-ioctls-Input-0
result: pass
VIDIOC_G/S_PARM:
set: Format-ioctls-Input-0
result: pass
VIDIOC_G_FBUF:
set: Format-ioctls-Input-0
result: pass
VIDIOC_G_FMT:
set: Format-ioctls-Input-0
result: pass
VIDIOC_TRY_FMT:
set: Format-ioctls-Input-0
result: pass
VIDIOC_S_FMT:
set: Format-ioctls-Input-0
result: pass
VIDIOC_G_SLICED_VBI_CAP:
set: Format-ioctls-Input-0
result: pass
Cropping:
set: Format-ioctls-Input-0
result: pass
Composing:
set: Format-ioctls-Input-0
result: pass
Scaling:
set: Format-ioctls-Input-0
result: pass
VIDIOC_TRY_ENCODER_CMD:
set: Codec-ioctls-Input-0
result: pass
VIDIOC_G_ENC_INDEX:
set: Codec-ioctls-Input-0
result: pass
VIDIOC_TRY_DECODER_CMD:
set: Codec-ioctls-Input-0
result: pass
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
set: Buffer-ioctls-Input-0
result: pass
CREATE_BUFS-maximum-buffers:
set: Buffer-ioctls-Input-0
result: pass
VIDIOC_EXPBUF:
set: Buffer-ioctls-Input-0
result: pass
Requests:
set: Buffer-ioctls-Input-0
result: pass
read/write:
set: Streaming-ioctls_Test-input-0
result: pass
blocking-wait:
set: Streaming-ioctls_Test-input-0
result: pass
MMAP-no-poll:
set: Streaming-ioctls_Test-input-0
result: fail
MMAP-select:
set: Streaming-ioctls_Test-input-0
result: fail
MMAP-epoll:
set: Streaming-ioctls_Test-input-0
result: fail
USERPTR-no-poll:
set: Streaming-ioctls_Test-input-0
result: pass
USERPTR-select:
set: Streaming-ioctls_Test-input-0
result: pass
11432 11:05:49.995657 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11433 11:05:49.995772 end: 3 lava-test-retry (duration 00:00:10) [common]
11434 11:05:49.995857 start: 4 finalize (timeout 00:07:30) [common]
11435 11:05:49.995939 start: 4.1 power-off (timeout 00:00:30) [common]
11436 11:05:49.996066 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
11437 11:05:52.078265 >> Command sent successfully.
11438 11:05:52.082447 Returned 0 in 2 seconds
11439 11:05:52.082585 end: 4.1 power-off (duration 00:00:02) [common]
11441 11:05:52.082805 start: 4.2 read-feedback (timeout 00:07:28) [common]
11442 11:05:52.082940 Listened to connection for namespace 'common' for up to 1s
11443 11:05:53.083029 Finalising connection for namespace 'common'
11444 11:05:53.083186 Disconnecting from shell: Finalise
11445 11:05:53.083280 / #
11446 11:05:53.183536 end: 4.2 read-feedback (duration 00:00:01) [common]
11447 11:05:53.183662 end: 4 finalize (duration 00:00:03) [common]
11448 11:05:53.183761 Cleaning after the job
11449 11:05:53.183858 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786807/tftp-deploy-8zc7obp1/ramdisk
11450 11:05:53.188767 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786807/tftp-deploy-8zc7obp1/kernel
11451 11:05:53.203541 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786807/tftp-deploy-8zc7obp1/dtb
11452 11:05:53.203731 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14786807/tftp-deploy-8zc7obp1/modules
11453 11:05:53.209909 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14786807
11454 11:05:53.276427 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14786807
11455 11:05:53.276607 Job finished correctly