Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 47
- Errors: 2
- Kernel Errors: 26
- Boot result: FAIL
1 06:52:45.332051 lava-dispatcher, installed at version: 2024.01
2 06:52:45.332248 start: 0 validate
3 06:52:45.332379 Start time: 2024-04-30 06:52:45.332371+00:00 (UTC)
4 06:52:45.332501 Using caching service: 'http://localhost/cache/?uri=%s'
5 06:52:45.332628 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 06:52:45.591275 Using caching service: 'http://localhost/cache/?uri=%s'
7 06:52:45.591454 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fchrome-platform%2Ffor-kernelci%2Fv6.9-rc4-22-g2fbe479c0024e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 06:53:13.937585 Using caching service: 'http://localhost/cache/?uri=%s'
9 06:53:13.937741 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fchrome-platform%2Ffor-kernelci%2Fv6.9-rc4-22-g2fbe479c0024e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 06:53:14.188190 Using caching service: 'http://localhost/cache/?uri=%s'
11 06:53:14.188387 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fchrome-platform%2Ffor-kernelci%2Fv6.9-rc4-22-g2fbe479c0024e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 06:53:17.437125 validate duration: 32.10
14 06:53:17.437442 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 06:53:17.437545 start: 1.1 download-retry (timeout 00:10:00) [common]
16 06:53:17.437657 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 06:53:17.437861 Not decompressing ramdisk as can be used compressed.
18 06:53:17.437983 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 06:53:17.438068 saving as /var/lib/lava/dispatcher/tmp/13580668/tftp-deploy-jo2e459g/ramdisk/rootfs.cpio.gz
20 06:53:17.438134 total size: 8181887 (7 MB)
21 06:53:17.687034 progress 0 % (0 MB)
22 06:53:17.689496 progress 5 % (0 MB)
23 06:53:17.691853 progress 10 % (0 MB)
24 06:53:17.694219 progress 15 % (1 MB)
25 06:53:17.696465 progress 20 % (1 MB)
26 06:53:17.698979 progress 25 % (1 MB)
27 06:53:17.701352 progress 30 % (2 MB)
28 06:53:17.703664 progress 35 % (2 MB)
29 06:53:17.705841 progress 40 % (3 MB)
30 06:53:17.708336 progress 45 % (3 MB)
31 06:53:17.710596 progress 50 % (3 MB)
32 06:53:17.712968 progress 55 % (4 MB)
33 06:53:17.715106 progress 60 % (4 MB)
34 06:53:17.717529 progress 65 % (5 MB)
35 06:53:17.719725 progress 70 % (5 MB)
36 06:53:17.722037 progress 75 % (5 MB)
37 06:53:17.724144 progress 80 % (6 MB)
38 06:53:17.726409 progress 85 % (6 MB)
39 06:53:17.728507 progress 90 % (7 MB)
40 06:53:17.730741 progress 95 % (7 MB)
41 06:53:17.732842 progress 100 % (7 MB)
42 06:53:17.733050 7 MB downloaded in 0.29 s (26.46 MB/s)
43 06:53:17.733212 end: 1.1.1 http-download (duration 00:00:00) [common]
45 06:53:17.733469 end: 1.1 download-retry (duration 00:00:00) [common]
46 06:53:17.733559 start: 1.2 download-retry (timeout 00:10:00) [common]
47 06:53:17.733644 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 06:53:17.733789 downloading http://storage.kernelci.org/chrome-platform/for-kernelci/v6.9-rc4-22-g2fbe479c0024e/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 06:53:17.733871 saving as /var/lib/lava/dispatcher/tmp/13580668/tftp-deploy-jo2e459g/kernel/Image
50 06:53:17.733975 total size: 60361216 (57 MB)
51 06:53:17.734071 No compression specified
52 06:53:17.735415 progress 0 % (0 MB)
53 06:53:17.751279 progress 5 % (2 MB)
54 06:53:17.766836 progress 10 % (5 MB)
55 06:53:17.782335 progress 15 % (8 MB)
56 06:53:17.798025 progress 20 % (11 MB)
57 06:53:17.813818 progress 25 % (14 MB)
58 06:53:17.829579 progress 30 % (17 MB)
59 06:53:17.845260 progress 35 % (20 MB)
60 06:53:17.860787 progress 40 % (23 MB)
61 06:53:17.876577 progress 45 % (25 MB)
62 06:53:17.892260 progress 50 % (28 MB)
63 06:53:17.908112 progress 55 % (31 MB)
64 06:53:17.923912 progress 60 % (34 MB)
65 06:53:17.939650 progress 65 % (37 MB)
66 06:53:17.955350 progress 70 % (40 MB)
67 06:53:17.970995 progress 75 % (43 MB)
68 06:53:17.986712 progress 80 % (46 MB)
69 06:53:18.002449 progress 85 % (48 MB)
70 06:53:18.018195 progress 90 % (51 MB)
71 06:53:18.033906 progress 95 % (54 MB)
72 06:53:18.049401 progress 100 % (57 MB)
73 06:53:18.049570 57 MB downloaded in 0.32 s (182.40 MB/s)
74 06:53:18.049726 end: 1.2.1 http-download (duration 00:00:00) [common]
76 06:53:18.049964 end: 1.2 download-retry (duration 00:00:00) [common]
77 06:53:18.050055 start: 1.3 download-retry (timeout 00:09:59) [common]
78 06:53:18.050152 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 06:53:18.050289 downloading http://storage.kernelci.org/chrome-platform/for-kernelci/v6.9-rc4-22-g2fbe479c0024e/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 06:53:18.050360 saving as /var/lib/lava/dispatcher/tmp/13580668/tftp-deploy-jo2e459g/dtb/mt8192-asurada-spherion-r0.dtb
81 06:53:18.050421 total size: 65280 (0 MB)
82 06:53:18.050483 No compression specified
83 06:53:18.051571 progress 50 % (0 MB)
84 06:53:18.093317 progress 100 % (0 MB)
85 06:53:18.093653 0 MB downloaded in 0.04 s (1.44 MB/s)
86 06:53:18.093857 end: 1.3.1 http-download (duration 00:00:00) [common]
88 06:53:18.094224 end: 1.3 download-retry (duration 00:00:00) [common]
89 06:53:18.094340 start: 1.4 download-retry (timeout 00:09:59) [common]
90 06:53:18.094431 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 06:53:18.094568 downloading http://storage.kernelci.org/chrome-platform/for-kernelci/v6.9-rc4-22-g2fbe479c0024e/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 06:53:18.094639 saving as /var/lib/lava/dispatcher/tmp/13580668/tftp-deploy-jo2e459g/modules/modules.tar
93 06:53:18.094700 total size: 9982080 (9 MB)
94 06:53:18.094762 Using unxz to decompress xz
95 06:53:18.098852 progress 0 % (0 MB)
96 06:53:18.125729 progress 5 % (0 MB)
97 06:53:18.156002 progress 10 % (0 MB)
98 06:53:18.186847 progress 15 % (1 MB)
99 06:53:18.217559 progress 20 % (1 MB)
100 06:53:18.247534 progress 25 % (2 MB)
101 06:53:18.276961 progress 30 % (2 MB)
102 06:53:18.306092 progress 35 % (3 MB)
103 06:53:18.336316 progress 40 % (3 MB)
104 06:53:18.369294 progress 45 % (4 MB)
105 06:53:18.400501 progress 50 % (4 MB)
106 06:53:18.431138 progress 55 % (5 MB)
107 06:53:18.461057 progress 60 % (5 MB)
108 06:53:18.493237 progress 65 % (6 MB)
109 06:53:18.524973 progress 70 % (6 MB)
110 06:53:18.562290 progress 75 % (7 MB)
111 06:53:18.594741 progress 80 % (7 MB)
112 06:53:18.623889 progress 85 % (8 MB)
113 06:53:18.655103 progress 90 % (8 MB)
114 06:53:18.684830 progress 95 % (9 MB)
115 06:53:18.713799 progress 100 % (9 MB)
116 06:53:18.719464 9 MB downloaded in 0.62 s (15.24 MB/s)
117 06:53:18.719717 end: 1.4.1 http-download (duration 00:00:01) [common]
119 06:53:18.719986 end: 1.4 download-retry (duration 00:00:01) [common]
120 06:53:18.720079 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 06:53:18.720180 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 06:53:18.720261 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 06:53:18.720347 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 06:53:18.720578 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu
125 06:53:18.720714 makedir: /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin
126 06:53:18.720818 makedir: /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/tests
127 06:53:18.720916 makedir: /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/results
128 06:53:18.721038 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-add-keys
129 06:53:18.721187 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-add-sources
130 06:53:18.721326 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-background-process-start
131 06:53:18.721456 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-background-process-stop
132 06:53:18.721587 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-common-functions
133 06:53:18.721712 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-echo-ipv4
134 06:53:18.721837 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-install-packages
135 06:53:18.721962 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-installed-packages
136 06:53:18.722086 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-os-build
137 06:53:18.722221 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-probe-channel
138 06:53:18.722348 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-probe-ip
139 06:53:18.722473 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-target-ip
140 06:53:18.722597 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-target-mac
141 06:53:18.722720 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-target-storage
142 06:53:18.722847 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-test-case
143 06:53:18.722971 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-test-event
144 06:53:18.723094 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-test-feedback
145 06:53:18.723218 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-test-raise
146 06:53:18.723343 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-test-reference
147 06:53:18.723466 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-test-runner
148 06:53:18.723594 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-test-set
149 06:53:18.723718 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-test-shell
150 06:53:18.723845 Updating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-install-packages (oe)
151 06:53:18.723994 Updating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/bin/lava-installed-packages (oe)
152 06:53:18.724115 Creating /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/environment
153 06:53:18.724215 LAVA metadata
154 06:53:18.724289 - LAVA_JOB_ID=13580668
155 06:53:18.724353 - LAVA_DISPATCHER_IP=192.168.201.1
156 06:53:18.724458 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 06:53:18.724525 skipped lava-vland-overlay
158 06:53:18.724598 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 06:53:18.724675 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 06:53:18.724737 skipped lava-multinode-overlay
161 06:53:18.724811 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 06:53:18.724893 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 06:53:18.724977 Loading test definitions
164 06:53:18.725099 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 06:53:18.725231 Using /lava-13580668 at stage 0
166 06:53:18.725573 uuid=13580668_1.5.2.3.1 testdef=None
167 06:53:18.725664 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 06:53:18.725751 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 06:53:18.726288 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 06:53:18.726508 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 06:53:18.727152 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 06:53:18.727385 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 06:53:18.728011 runner path: /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/0/tests/0_dmesg test_uuid 13580668_1.5.2.3.1
176 06:53:18.728170 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 06:53:18.728382 Creating lava-test-runner.conf files
179 06:53:18.728444 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13580668/lava-overlay-i2i7bryu/lava-13580668/0 for stage 0
180 06:53:18.728533 - 0_dmesg
181 06:53:18.728628 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 06:53:18.728710 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 06:53:18.735935 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 06:53:18.736063 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 06:53:18.736154 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 06:53:18.736243 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 06:53:18.736331 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 06:53:18.985054 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 06:53:18.985464 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 06:53:18.985617 extracting modules file /var/lib/lava/dispatcher/tmp/13580668/tftp-deploy-jo2e459g/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13580668/extract-overlay-ramdisk-293xcfpy/ramdisk
191 06:53:19.260267 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 06:53:19.260436 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 06:53:19.260532 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13580668/compress-overlay-8h5uiyac/overlay-1.5.2.4.tar.gz to ramdisk
194 06:53:19.260608 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13580668/compress-overlay-8h5uiyac/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13580668/extract-overlay-ramdisk-293xcfpy/ramdisk
195 06:53:19.267491 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 06:53:19.267621 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 06:53:19.267715 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 06:53:19.267803 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 06:53:19.267882 Building ramdisk /var/lib/lava/dispatcher/tmp/13580668/extract-overlay-ramdisk-293xcfpy/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13580668/extract-overlay-ramdisk-293xcfpy/ramdisk
200 06:53:19.663621 >> 163620 blocks
201 06:53:22.230787 rename /var/lib/lava/dispatcher/tmp/13580668/extract-overlay-ramdisk-293xcfpy/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13580668/tftp-deploy-jo2e459g/ramdisk/ramdisk.cpio.gz
202 06:53:22.231225 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 06:53:22.231349 start: 1.5.8 prepare-kernel (timeout 00:09:55) [common]
204 06:53:22.231450 start: 1.5.8.1 prepare-fit (timeout 00:09:55) [common]
205 06:53:22.231558 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13580668/tftp-deploy-jo2e459g/kernel/Image'
206 06:53:38.786497 Returned 0 in 16 seconds
207 06:53:38.887085 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13580668/tftp-deploy-jo2e459g/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13580668/tftp-deploy-jo2e459g/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13580668/tftp-deploy-jo2e459g/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13580668/tftp-deploy-jo2e459g/kernel/image.itb
208 06:53:39.308824 output: FIT description: Kernel Image image with one or more FDT blobs
209 06:53:39.309217 output: Created: Tue Apr 30 07:53:39 2024
210 06:53:39.309304 output: Image 0 (kernel-1)
211 06:53:39.309377 output: Description:
212 06:53:39.309442 output: Created: Tue Apr 30 07:53:39 2024
213 06:53:39.309504 output: Type: Kernel Image
214 06:53:39.309571 output: Compression: lzma compressed
215 06:53:39.309630 output: Data Size: 13676132 Bytes = 13355.60 KiB = 13.04 MiB
216 06:53:39.309687 output: Architecture: AArch64
217 06:53:39.309747 output: OS: Linux
218 06:53:39.309803 output: Load Address: 0x00000000
219 06:53:39.309858 output: Entry Point: 0x00000000
220 06:53:39.309921 output: Hash algo: crc32
221 06:53:39.309978 output: Hash value: ed2316ce
222 06:53:39.310037 output: Image 1 (fdt-1)
223 06:53:39.310099 output: Description: mt8192-asurada-spherion-r0
224 06:53:39.310154 output: Created: Tue Apr 30 07:53:39 2024
225 06:53:39.310207 output: Type: Flat Device Tree
226 06:53:39.310259 output: Compression: uncompressed
227 06:53:39.310321 output: Data Size: 65280 Bytes = 63.75 KiB = 0.06 MiB
228 06:53:39.310375 output: Architecture: AArch64
229 06:53:39.310427 output: Hash algo: crc32
230 06:53:39.310492 output: Hash value: 81319159
231 06:53:39.310546 output: Image 2 (ramdisk-1)
232 06:53:39.310597 output: Description: unavailable
233 06:53:39.310655 output: Created: Tue Apr 30 07:53:39 2024
234 06:53:39.310708 output: Type: RAMDisk Image
235 06:53:39.310759 output: Compression: Unknown Compression
236 06:53:39.310811 output: Data Size: 23529346 Bytes = 22977.88 KiB = 22.44 MiB
237 06:53:39.310874 output: Architecture: AArch64
238 06:53:39.310927 output: OS: Linux
239 06:53:39.310979 output: Load Address: unavailable
240 06:53:39.311040 output: Entry Point: unavailable
241 06:53:39.311093 output: Hash algo: crc32
242 06:53:39.311145 output: Hash value: 0ee13694
243 06:53:39.311208 output: Default Configuration: 'conf-1'
244 06:53:39.311288 output: Configuration 0 (conf-1)
245 06:53:39.311363 output: Description: mt8192-asurada-spherion-r0
246 06:53:39.311424 output: Kernel: kernel-1
247 06:53:39.311477 output: Init Ramdisk: ramdisk-1
248 06:53:39.311555 output: FDT: fdt-1
249 06:53:39.311624 output: Loadables: kernel-1
250 06:53:39.311678 output:
251 06:53:39.311886 end: 1.5.8.1 prepare-fit (duration 00:00:17) [common]
252 06:53:39.312001 end: 1.5.8 prepare-kernel (duration 00:00:17) [common]
253 06:53:39.312105 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 06:53:39.312204 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 06:53:39.312288 No LXC device requested
256 06:53:39.312378 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 06:53:39.312465 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 06:53:39.312552 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 06:53:39.312622 Checking files for TFTP limit of 4294967296 bytes.
260 06:53:39.313146 end: 1 tftp-deploy (duration 00:00:22) [common]
261 06:53:39.313297 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 06:53:39.313395 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 06:53:39.313530 substitutions:
264 06:53:39.313601 - {DTB}: 13580668/tftp-deploy-jo2e459g/dtb/mt8192-asurada-spherion-r0.dtb
265 06:53:39.313670 - {INITRD}: 13580668/tftp-deploy-jo2e459g/ramdisk/ramdisk.cpio.gz
266 06:53:39.313730 - {KERNEL}: 13580668/tftp-deploy-jo2e459g/kernel/Image
267 06:53:39.313788 - {LAVA_MAC}: None
268 06:53:39.313851 - {PRESEED_CONFIG}: None
269 06:53:39.313908 - {PRESEED_LOCAL}: None
270 06:53:39.313962 - {RAMDISK}: 13580668/tftp-deploy-jo2e459g/ramdisk/ramdisk.cpio.gz
271 06:53:39.314017 - {ROOT_PART}: None
272 06:53:39.314077 - {ROOT}: None
273 06:53:39.314131 - {SERVER_IP}: 192.168.201.1
274 06:53:39.314196 - {TEE}: None
275 06:53:39.314280 Parsed boot commands:
276 06:53:39.314339 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 06:53:39.314525 Parsed boot commands: tftpboot 192.168.201.1 13580668/tftp-deploy-jo2e459g/kernel/image.itb 13580668/tftp-deploy-jo2e459g/kernel/cmdline
278 06:53:39.314625 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 06:53:39.314717 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 06:53:39.314817 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 06:53:39.314904 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 06:53:39.314981 Not connected, no need to disconnect.
283 06:53:39.315057 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 06:53:39.315139 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 06:53:39.315215 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 06:53:39.319026 Setting prompt string to ['lava-test: # ']
287 06:53:39.319442 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 06:53:39.319568 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 06:53:39.319670 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 06:53:39.319785 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 06:53:39.320004 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 06:53:44.452442 >> Command sent successfully.
293 06:53:44.454805 Returned 0 in 5 seconds
294 06:53:44.555155 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 06:53:44.555474 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 06:53:44.555579 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 06:53:44.555670 Setting prompt string to 'Starting depthcharge on Spherion...'
299 06:53:44.555738 Changing prompt to 'Starting depthcharge on Spherion...'
300 06:53:44.555804 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 06:53:44.556069 [Enter `^Ec?' for help]
302 06:53:44.728651
303 06:53:44.728828
304 06:53:44.728934 F0: 102B 0000
305 06:53:44.729028
306 06:53:44.729126 F3: 1001 0000 [0200]
307 06:53:44.732089
308 06:53:44.732168 F3: 1001 0000
309 06:53:44.732239
310 06:53:44.732305 F7: 102D 0000
311 06:53:44.732363
312 06:53:44.735593 F1: 0000 0000
313 06:53:44.735684
314 06:53:44.735746 V0: 0000 0000 [0001]
315 06:53:44.735812
316 06:53:44.738771 00: 0007 8000
317 06:53:44.738855
318 06:53:44.738918 01: 0000 0000
319 06:53:44.738979
320 06:53:44.742277 BP: 0C00 0209 [0000]
321 06:53:44.742352
322 06:53:44.742414 G0: 1182 0000
323 06:53:44.742482
324 06:53:44.742540 EC: 0000 0021 [4000]
325 06:53:44.745790
326 06:53:44.745862 S7: 0000 0000 [0000]
327 06:53:44.745937
328 06:53:44.749680 CC: 0000 0000 [0001]
329 06:53:44.749767
330 06:53:44.749829 T0: 0000 0040 [010F]
331 06:53:44.749888
332 06:53:44.749953 Jump to BL
333 06:53:44.750008
334 06:53:44.776183
335 06:53:44.776320
336 06:53:44.776414
337 06:53:44.782702 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 06:53:44.786542 ARM64: Exception handlers installed.
339 06:53:44.789932 ARM64: Testing exception
340 06:53:44.793758 ARM64: Done test exception
341 06:53:44.800094 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 06:53:44.810374 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 06:53:44.817197 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 06:53:44.827030 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 06:53:44.833672 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 06:53:44.840522 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 06:53:44.852834 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 06:53:44.859362 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 06:53:44.878900 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 06:53:44.882167 WDT: Last reset was cold boot
351 06:53:44.884925 SPI1(PAD0) initialized at 2873684 Hz
352 06:53:44.888932 SPI5(PAD0) initialized at 992727 Hz
353 06:53:44.891816 VBOOT: Loading verstage.
354 06:53:44.898965 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 06:53:44.901969 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 06:53:44.905434 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 06:53:44.908450 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 06:53:44.916059 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 06:53:44.922971 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 06:53:44.933395 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 06:53:44.933485
362 06:53:44.933550
363 06:53:44.943814 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 06:53:44.946804 ARM64: Exception handlers installed.
365 06:53:44.950362 ARM64: Testing exception
366 06:53:44.950453 ARM64: Done test exception
367 06:53:44.957142 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 06:53:44.960555 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 06:53:44.975544 Probing TPM: . done!
370 06:53:44.975649 TPM ready after 0 ms
371 06:53:44.982620 Connected to device vid:did:rid of 1ae0:0028:00
372 06:53:44.989092 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 06:53:45.046433 Initialized TPM device CR50 revision 0
374 06:53:45.058275 tlcl_send_startup: Startup return code is 0
375 06:53:45.058380 TPM: setup succeeded
376 06:53:45.069489 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 06:53:45.078450 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 06:53:45.092327 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 06:53:45.099671 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 06:53:45.102964 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 06:53:45.109035 in-header: 03 07 00 00 08 00 00 00
382 06:53:45.113146 in-data: aa e4 47 04 13 02 00 00
383 06:53:45.116516 Chrome EC: UHEPI supported
384 06:53:45.123897 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 06:53:45.127449 in-header: 03 ad 00 00 08 00 00 00
386 06:53:45.127539 in-data: 00 20 20 08 00 00 00 00
387 06:53:45.131075 Phase 1
388 06:53:45.134836 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 06:53:45.138520 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 06:53:45.146150 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 06:53:45.150400 Recovery requested (1009000e)
392 06:53:45.159594 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 06:53:45.163167 tlcl_extend: response is 0
394 06:53:45.174339 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 06:53:45.178126 tlcl_extend: response is 0
396 06:53:45.185274 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 06:53:45.204718 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 06:53:45.211357 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 06:53:45.211441
400 06:53:45.211504
401 06:53:45.222439 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 06:53:45.225829 ARM64: Exception handlers installed.
403 06:53:45.225912 ARM64: Testing exception
404 06:53:45.228962 ARM64: Done test exception
405 06:53:45.250254 pmic_efuse_setting: Set efuses in 11 msecs
406 06:53:45.253835 pmwrap_interface_init: Select PMIF_VLD_RDY
407 06:53:45.260390 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 06:53:45.263881 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 06:53:45.267667 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 06:53:45.274320 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 06:53:45.278157 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 06:53:45.281718 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 06:53:45.289439 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 06:53:45.293109 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 06:53:45.296835 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 06:53:45.304178 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 06:53:45.307692 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 06:53:45.311675 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 06:53:45.314974 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 06:53:45.322096 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 06:53:45.330021 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 06:53:45.333519 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 06:53:45.340525 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 06:53:45.344626 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 06:53:45.352025 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 06:53:45.355515 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 06:53:45.363214 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 06:53:45.366810 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 06:53:45.373923 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 06:53:45.377823 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 06:53:45.385072 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 06:53:45.389160 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 06:53:45.396398 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 06:53:45.400109 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 06:53:45.403245 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 06:53:45.407635 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 06:53:45.414930 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 06:53:45.418653 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 06:53:45.425882 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 06:53:45.429755 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 06:53:45.432961 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 06:53:45.440158 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 06:53:45.444133 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 06:53:45.448022 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 06:53:45.454980 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 06:53:45.458921 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 06:53:45.462948 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 06:53:45.466408 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 06:53:45.469991 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 06:53:45.477423 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 06:53:45.481152 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 06:53:45.484668 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 06:53:45.488328 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 06:53:45.491900 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 06:53:45.495678 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 06:53:45.499365 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 06:53:45.506657 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 06:53:45.513954 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 06:53:45.521934 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 06:53:45.525630 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 06:53:45.532866 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 06:53:45.543794 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 06:53:45.547658 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 06:53:45.551105 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 06:53:45.554395 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 06:53:45.563128 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x1f
467 06:53:45.566845 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 06:53:45.575778 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 06:53:45.579042 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 06:53:45.588328 [RTC]rtc_get_frequency_meter,154: input=15, output=791
471 06:53:45.598039 [RTC]rtc_get_frequency_meter,154: input=23, output=978
472 06:53:45.607039 [RTC]rtc_get_frequency_meter,154: input=19, output=884
473 06:53:45.617061 [RTC]rtc_get_frequency_meter,154: input=17, output=837
474 06:53:45.626071 [RTC]rtc_get_frequency_meter,154: input=16, output=812
475 06:53:45.635919 [RTC]rtc_get_frequency_meter,154: input=15, output=790
476 06:53:45.645165 [RTC]rtc_get_frequency_meter,154: input=16, output=813
477 06:53:45.648493 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 06:53:45.655518 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 06:53:45.658980 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 06:53:45.662595 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 06:53:45.666369 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 06:53:45.669517 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 06:53:45.673305 ADC[4]: Raw value=901328 ID=7
484 06:53:45.677053 ADC[3]: Raw value=213336 ID=1
485 06:53:45.677558 RAM Code: 0x71
486 06:53:45.680874 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 06:53:45.688803 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 06:53:45.696230 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 06:53:45.703608 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 06:53:45.707024 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 06:53:45.710899 in-header: 03 07 00 00 08 00 00 00
492 06:53:45.714370 in-data: aa e4 47 04 13 02 00 00
493 06:53:45.718002 Chrome EC: UHEPI supported
494 06:53:45.721631 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 06:53:45.725996 in-header: 03 ed 00 00 08 00 00 00
496 06:53:45.729645 in-data: 80 20 60 08 00 00 00 00
497 06:53:45.733130 MRC: failed to locate region type 0.
498 06:53:45.740422 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 06:53:45.744170 DRAM-K: Running full calibration
500 06:53:45.747741 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 06:53:45.751449 header.status = 0x0
502 06:53:45.754946 header.version = 0x6 (expected: 0x6)
503 06:53:45.758611 header.size = 0xd00 (expected: 0xd00)
504 06:53:45.759034 header.flags = 0x0
505 06:53:45.765813 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 06:53:45.783884 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 06:53:45.790908 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 06:53:45.794415 dram_init: ddr_geometry: 2
509 06:53:45.794838 [EMI] MDL number = 2
510 06:53:45.798612 [EMI] Get MDL freq = 0
511 06:53:45.799033 dram_init: ddr_type: 0
512 06:53:45.801715 is_discrete_lpddr4: 1
513 06:53:45.805895 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 06:53:45.806351
515 06:53:45.806679
516 06:53:45.807022 [Bian_co] ETT version 0.0.0.1
517 06:53:45.813058 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 06:53:45.813669
519 06:53:45.816821 dramc_set_vcore_voltage set vcore to 650000
520 06:53:45.817276 Read voltage for 800, 4
521 06:53:45.820428 Vio18 = 0
522 06:53:45.820915 Vcore = 650000
523 06:53:45.821296 Vdram = 0
524 06:53:45.821620 Vddq = 0
525 06:53:45.823924 Vmddr = 0
526 06:53:45.824352 dram_init: config_dvfs: 1
527 06:53:45.831544 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 06:53:45.834859 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 06:53:45.838320 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 06:53:45.845280 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 06:53:45.848257 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 06:53:45.851850 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 06:53:45.852275 MEM_TYPE=3, freq_sel=18
534 06:53:45.854892 sv_algorithm_assistance_LP4_1600
535 06:53:45.861617 ============ PULL DRAM RESETB DOWN ============
536 06:53:45.864985 ========== PULL DRAM RESETB DOWN end =========
537 06:53:45.868707 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 06:53:45.871660 ===================================
539 06:53:45.875166 LPDDR4 DRAM CONFIGURATION
540 06:53:45.878403 ===================================
541 06:53:45.878823 EX_ROW_EN[0] = 0x0
542 06:53:45.881523 EX_ROW_EN[1] = 0x0
543 06:53:45.885152 LP4Y_EN = 0x0
544 06:53:45.885638 WORK_FSP = 0x0
545 06:53:45.888430 WL = 0x2
546 06:53:45.888844 RL = 0x2
547 06:53:45.892207 BL = 0x2
548 06:53:45.892649 RPST = 0x0
549 06:53:45.895053 RD_PRE = 0x0
550 06:53:45.895474 WR_PRE = 0x1
551 06:53:45.898541 WR_PST = 0x0
552 06:53:45.898971 DBI_WR = 0x0
553 06:53:45.901736 DBI_RD = 0x0
554 06:53:45.902173 OTF = 0x1
555 06:53:45.905351 ===================================
556 06:53:45.908595 ===================================
557 06:53:45.911769 ANA top config
558 06:53:45.915277 ===================================
559 06:53:45.915801 DLL_ASYNC_EN = 0
560 06:53:45.918764 ALL_SLAVE_EN = 1
561 06:53:45.922645 NEW_RANK_MODE = 1
562 06:53:45.925364 DLL_IDLE_MODE = 1
563 06:53:45.925794 LP45_APHY_COMB_EN = 1
564 06:53:45.929268 TX_ODT_DIS = 1
565 06:53:45.932011 NEW_8X_MODE = 1
566 06:53:45.935306 ===================================
567 06:53:45.938416 ===================================
568 06:53:45.942489 data_rate = 1600
569 06:53:45.945507 CKR = 1
570 06:53:45.948621 DQ_P2S_RATIO = 8
571 06:53:45.952032 ===================================
572 06:53:45.952460 CA_P2S_RATIO = 8
573 06:53:45.955272 DQ_CA_OPEN = 0
574 06:53:45.958853 DQ_SEMI_OPEN = 0
575 06:53:45.961987 CA_SEMI_OPEN = 0
576 06:53:45.965602 CA_FULL_RATE = 0
577 06:53:45.966025 DQ_CKDIV4_EN = 1
578 06:53:45.968617 CA_CKDIV4_EN = 1
579 06:53:45.972490 CA_PREDIV_EN = 0
580 06:53:45.975330 PH8_DLY = 0
581 06:53:45.978445 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 06:53:45.982359 DQ_AAMCK_DIV = 4
583 06:53:45.982785 CA_AAMCK_DIV = 4
584 06:53:45.985468 CA_ADMCK_DIV = 4
585 06:53:45.988840 DQ_TRACK_CA_EN = 0
586 06:53:45.991942 CA_PICK = 800
587 06:53:45.995814 CA_MCKIO = 800
588 06:53:45.999203 MCKIO_SEMI = 0
589 06:53:46.002660 PLL_FREQ = 3068
590 06:53:46.003176 DQ_UI_PI_RATIO = 32
591 06:53:46.006588 CA_UI_PI_RATIO = 0
592 06:53:46.010130 ===================================
593 06:53:46.014345 ===================================
594 06:53:46.014788 memory_type:LPDDR4
595 06:53:46.017859 GP_NUM : 10
596 06:53:46.018283 SRAM_EN : 1
597 06:53:46.021468 MD32_EN : 0
598 06:53:46.025451 ===================================
599 06:53:46.025898 [ANA_INIT] >>>>>>>>>>>>>>
600 06:53:46.029488 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 06:53:46.032910 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 06:53:46.036430 ===================================
603 06:53:46.040215 data_rate = 1600,PCW = 0X7600
604 06:53:46.043392 ===================================
605 06:53:46.046647 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 06:53:46.050541 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 06:53:46.056770 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 06:53:46.060371 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 06:53:46.063388 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 06:53:46.067561 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 06:53:46.070510 [ANA_INIT] flow start
612 06:53:46.073901 [ANA_INIT] PLL >>>>>>>>
613 06:53:46.074368 [ANA_INIT] PLL <<<<<<<<
614 06:53:46.077129 [ANA_INIT] MIDPI >>>>>>>>
615 06:53:46.080117 [ANA_INIT] MIDPI <<<<<<<<
616 06:53:46.084005 [ANA_INIT] DLL >>>>>>>>
617 06:53:46.084423 [ANA_INIT] flow end
618 06:53:46.087335 ============ LP4 DIFF to SE enter ============
619 06:53:46.094206 ============ LP4 DIFF to SE exit ============
620 06:53:46.094648 [ANA_INIT] <<<<<<<<<<<<<
621 06:53:46.096925 [Flow] Enable top DCM control >>>>>
622 06:53:46.100491 [Flow] Enable top DCM control <<<<<
623 06:53:46.103697 Enable DLL master slave shuffle
624 06:53:46.110854 ==============================================================
625 06:53:46.111572 Gating Mode config
626 06:53:46.117598 ==============================================================
627 06:53:46.118202 Config description:
628 06:53:46.127339 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 06:53:46.134111 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 06:53:46.141031 SELPH_MODE 0: By rank 1: By Phase
631 06:53:46.144041 ==============================================================
632 06:53:46.147621 GAT_TRACK_EN = 1
633 06:53:46.151317 RX_GATING_MODE = 2
634 06:53:46.154443 RX_GATING_TRACK_MODE = 2
635 06:53:46.157507 SELPH_MODE = 1
636 06:53:46.161093 PICG_EARLY_EN = 1
637 06:53:46.164215 VALID_LAT_VALUE = 1
638 06:53:46.167622 ==============================================================
639 06:53:46.170927 Enter into Gating configuration >>>>
640 06:53:46.174238 Exit from Gating configuration <<<<
641 06:53:46.178002 Enter into DVFS_PRE_config >>>>>
642 06:53:46.191091 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 06:53:46.194512 Exit from DVFS_PRE_config <<<<<
644 06:53:46.195100 Enter into PICG configuration >>>>
645 06:53:46.197730 Exit from PICG configuration <<<<
646 06:53:46.201435 [RX_INPUT] configuration >>>>>
647 06:53:46.204663 [RX_INPUT] configuration <<<<<
648 06:53:46.211267 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 06:53:46.214688 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 06:53:46.222068 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 06:53:46.228800 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 06:53:46.235476 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 06:53:46.238903 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 06:53:46.245605 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 06:53:46.248801 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 06:53:46.252221 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 06:53:46.255181 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 06:53:46.258612 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 06:53:46.265572 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 06:53:46.268432 ===================================
661 06:53:46.272027 LPDDR4 DRAM CONFIGURATION
662 06:53:46.272642 ===================================
663 06:53:46.275151 EX_ROW_EN[0] = 0x0
664 06:53:46.278414 EX_ROW_EN[1] = 0x0
665 06:53:46.278836 LP4Y_EN = 0x0
666 06:53:46.282059 WORK_FSP = 0x0
667 06:53:46.282651 WL = 0x2
668 06:53:46.285167 RL = 0x2
669 06:53:46.285752 BL = 0x2
670 06:53:46.288654 RPST = 0x0
671 06:53:46.289097 RD_PRE = 0x0
672 06:53:46.291844 WR_PRE = 0x1
673 06:53:46.292283 WR_PST = 0x0
674 06:53:46.295611 DBI_WR = 0x0
675 06:53:46.296061 DBI_RD = 0x0
676 06:53:46.299023 OTF = 0x1
677 06:53:46.302105 ===================================
678 06:53:46.305563 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 06:53:46.308933 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 06:53:46.315335 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 06:53:46.318836 ===================================
682 06:53:46.319275 LPDDR4 DRAM CONFIGURATION
683 06:53:46.322318 ===================================
684 06:53:46.325866 EX_ROW_EN[0] = 0x10
685 06:53:46.328931 EX_ROW_EN[1] = 0x0
686 06:53:46.329477 LP4Y_EN = 0x0
687 06:53:46.332744 WORK_FSP = 0x0
688 06:53:46.333170 WL = 0x2
689 06:53:46.335692 RL = 0x2
690 06:53:46.336120 BL = 0x2
691 06:53:46.339019 RPST = 0x0
692 06:53:46.339446 RD_PRE = 0x0
693 06:53:46.342031 WR_PRE = 0x1
694 06:53:46.342491 WR_PST = 0x0
695 06:53:46.345792 DBI_WR = 0x0
696 06:53:46.346303 DBI_RD = 0x0
697 06:53:46.349022 OTF = 0x1
698 06:53:46.352430 ===================================
699 06:53:46.359017 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 06:53:46.362464 nWR fixed to 40
701 06:53:46.362912 [ModeRegInit_LP4] CH0 RK0
702 06:53:46.365775 [ModeRegInit_LP4] CH0 RK1
703 06:53:46.369067 [ModeRegInit_LP4] CH1 RK0
704 06:53:46.369577 [ModeRegInit_LP4] CH1 RK1
705 06:53:46.372504 match AC timing 13
706 06:53:46.375717 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 06:53:46.379226 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 06:53:46.385501 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 06:53:46.389183 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 06:53:46.395827 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 06:53:46.396306 [EMI DOE] emi_dcm 0
712 06:53:46.398901 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 06:53:46.402700 ==
714 06:53:46.403161 Dram Type= 6, Freq= 0, CH_0, rank 0
715 06:53:46.409338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 06:53:46.409918 ==
717 06:53:46.412483 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 06:53:46.419398 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 06:53:46.428525 [CA 0] Center 37 (7~68) winsize 62
720 06:53:46.432315 [CA 1] Center 37 (6~68) winsize 63
721 06:53:46.435605 [CA 2] Center 35 (4~66) winsize 63
722 06:53:46.439109 [CA 3] Center 34 (4~65) winsize 62
723 06:53:46.442369 [CA 4] Center 34 (3~65) winsize 63
724 06:53:46.445463 [CA 5] Center 33 (3~64) winsize 62
725 06:53:46.445911
726 06:53:46.449041 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 06:53:46.449617
728 06:53:46.452049 [CATrainingPosCal] consider 1 rank data
729 06:53:46.455571 u2DelayCellTimex100 = 270/100 ps
730 06:53:46.459038 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 06:53:46.462264 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 06:53:46.466130 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
733 06:53:46.472372 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 06:53:46.475733 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 06:53:46.478795 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 06:53:46.479457
737 06:53:46.482439 CA PerBit enable=1, Macro0, CA PI delay=33
738 06:53:46.482887
739 06:53:46.485688 [CBTSetCACLKResult] CA Dly = 33
740 06:53:46.486117 CS Dly: 5 (0~36)
741 06:53:46.486457 ==
742 06:53:46.489188 Dram Type= 6, Freq= 0, CH_0, rank 1
743 06:53:46.495657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 06:53:46.496089 ==
745 06:53:46.499253 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 06:53:46.505913 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 06:53:46.515087 [CA 0] Center 37 (7~68) winsize 62
748 06:53:46.518090 [CA 1] Center 37 (6~68) winsize 63
749 06:53:46.521520 [CA 2] Center 35 (4~66) winsize 63
750 06:53:46.525435 [CA 3] Center 35 (4~66) winsize 63
751 06:53:46.528320 [CA 4] Center 33 (3~64) winsize 62
752 06:53:46.532203 [CA 5] Center 33 (3~64) winsize 62
753 06:53:46.532827
754 06:53:46.535285 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 06:53:46.535961
756 06:53:46.538276 [CATrainingPosCal] consider 2 rank data
757 06:53:46.541892 u2DelayCellTimex100 = 270/100 ps
758 06:53:46.545086 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 06:53:46.548447 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
760 06:53:46.555166 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
761 06:53:46.558766 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 06:53:46.561897 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 06:53:46.565424 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 06:53:46.565895
765 06:53:46.568787 CA PerBit enable=1, Macro0, CA PI delay=33
766 06:53:46.569266
767 06:53:46.572095 [CBTSetCACLKResult] CA Dly = 33
768 06:53:46.572539 CS Dly: 6 (0~38)
769 06:53:46.572931
770 06:53:46.575265 ----->DramcWriteLeveling(PI) begin...
771 06:53:46.575726 ==
772 06:53:46.579047 Dram Type= 6, Freq= 0, CH_0, rank 0
773 06:53:46.585685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 06:53:46.586167 ==
775 06:53:46.586574 Write leveling (Byte 0): 28 => 28
776 06:53:46.589498 Write leveling (Byte 1): 28 => 28
777 06:53:46.593034 DramcWriteLeveling(PI) end<-----
778 06:53:46.593522
779 06:53:46.593924 ==
780 06:53:46.596762 Dram Type= 6, Freq= 0, CH_0, rank 0
781 06:53:46.600032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 06:53:46.600395 ==
783 06:53:46.603560 [Gating] SW mode calibration
784 06:53:46.610433 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 06:53:46.617318 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 06:53:46.621024 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 06:53:46.623817 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 06:53:46.630301 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 06:53:46.633972 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 06:53:46.637064 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 06:53:46.643983 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 06:53:46.647492 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 06:53:46.650319 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 06:53:46.657081 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 06:53:46.660467 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 06:53:46.664103 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 06:53:46.670674 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 06:53:46.674486 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 06:53:46.677726 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 06:53:46.680649 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 06:53:46.687999 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 06:53:46.690867 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 06:53:46.694221 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 06:53:46.700857 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
805 06:53:46.704216 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 06:53:46.707649 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 06:53:46.714365 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 06:53:46.717854 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 06:53:46.721075 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 06:53:46.727763 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 06:53:46.731106 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 06:53:46.734163 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
813 06:53:46.740818 0 9 12 | B1->B0 | 2525 2f2f | 0 1 | (0 0) (1 1)
814 06:53:46.744439 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 06:53:46.747501 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 06:53:46.751232 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 06:53:46.757796 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 06:53:46.761520 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 06:53:46.764987 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 06:53:46.771461 0 10 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
821 06:53:46.774941 0 10 12 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
822 06:53:46.777970 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 06:53:46.784868 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 06:53:46.788151 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 06:53:46.791764 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 06:53:46.798526 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 06:53:46.801575 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 06:53:46.804827 0 11 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
829 06:53:46.811425 0 11 12 | B1->B0 | 3535 4141 | 1 0 | (0 0) (0 0)
830 06:53:46.815056 0 11 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
831 06:53:46.818056 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 06:53:46.821062 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 06:53:46.827672 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 06:53:46.831176 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 06:53:46.834511 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 06:53:46.841396 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 06:53:46.844624 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 06:53:46.848178 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 06:53:46.854972 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 06:53:46.858433 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 06:53:46.861399 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 06:53:46.868287 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 06:53:46.871289 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 06:53:46.874776 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 06:53:46.881814 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 06:53:46.884857 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 06:53:46.888254 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 06:53:46.891701 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 06:53:46.898755 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 06:53:46.901682 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 06:53:46.905081 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 06:53:46.911715 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 06:53:46.915061 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 06:53:46.918583 Total UI for P1: 0, mck2ui 16
855 06:53:46.921639 best dqsien dly found for B0: ( 0, 14, 10)
856 06:53:46.925314 Total UI for P1: 0, mck2ui 16
857 06:53:46.929151 best dqsien dly found for B1: ( 0, 14, 10)
858 06:53:46.932170 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
859 06:53:46.935555 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 06:53:46.935915
861 06:53:46.938738 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
862 06:53:46.942187 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 06:53:46.945899 [Gating] SW calibration Done
864 06:53:46.946199 ==
865 06:53:46.948534 Dram Type= 6, Freq= 0, CH_0, rank 0
866 06:53:46.951914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 06:53:46.952218 ==
868 06:53:46.955697 RX Vref Scan: 0
869 06:53:46.956023
870 06:53:46.958725 RX Vref 0 -> 0, step: 1
871 06:53:46.959026
872 06:53:46.959265 RX Delay -130 -> 252, step: 16
873 06:53:46.965444 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 06:53:46.969085 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 06:53:46.972430 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 06:53:46.975624 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 06:53:46.978774 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 06:53:46.985596 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 06:53:46.988783 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
880 06:53:46.992140 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 06:53:46.995746 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 06:53:46.999147 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 06:53:47.005859 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 06:53:47.009279 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 06:53:47.012180 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 06:53:47.015443 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
887 06:53:47.018763 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 06:53:47.026054 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 06:53:47.026354 ==
890 06:53:47.028956 Dram Type= 6, Freq= 0, CH_0, rank 0
891 06:53:47.032632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 06:53:47.032934 ==
893 06:53:47.033191 DQS Delay:
894 06:53:47.035722 DQS0 = 0, DQS1 = 0
895 06:53:47.036022 DQM Delay:
896 06:53:47.039416 DQM0 = 85, DQM1 = 77
897 06:53:47.039715 DQ Delay:
898 06:53:47.042339 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 06:53:47.045960 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
900 06:53:47.049267 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
901 06:53:47.052314 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
902 06:53:47.052613
903 06:53:47.052848
904 06:53:47.053066 ==
905 06:53:47.056109 Dram Type= 6, Freq= 0, CH_0, rank 0
906 06:53:47.059161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 06:53:47.059465 ==
908 06:53:47.059703
909 06:53:47.059922
910 06:53:47.062572 TX Vref Scan disable
911 06:53:47.065932 == TX Byte 0 ==
912 06:53:47.069135 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
913 06:53:47.072800 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
914 06:53:47.075936 == TX Byte 1 ==
915 06:53:47.079473 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
916 06:53:47.082573 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
917 06:53:47.082879 ==
918 06:53:47.086002 Dram Type= 6, Freq= 0, CH_0, rank 0
919 06:53:47.089849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 06:53:47.090154 ==
921 06:53:47.103996 TX Vref=22, minBit 5, minWin=26, winSum=436
922 06:53:47.107594 TX Vref=24, minBit 0, minWin=27, winSum=443
923 06:53:47.110729 TX Vref=26, minBit 5, minWin=27, winSum=445
924 06:53:47.114052 TX Vref=28, minBit 4, minWin=28, winSum=455
925 06:53:47.117580 TX Vref=30, minBit 3, minWin=27, winSum=449
926 06:53:47.120926 TX Vref=32, minBit 2, minWin=28, winSum=453
927 06:53:47.127617 [TxChooseVref] Worse bit 4, Min win 28, Win sum 455, Final Vref 28
928 06:53:47.127925
929 06:53:47.131215 Final TX Range 1 Vref 28
930 06:53:47.131556
931 06:53:47.131818 ==
932 06:53:47.134345 Dram Type= 6, Freq= 0, CH_0, rank 0
933 06:53:47.137315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 06:53:47.137622 ==
935 06:53:47.137861
936 06:53:47.138095
937 06:53:47.140951 TX Vref Scan disable
938 06:53:47.144047 == TX Byte 0 ==
939 06:53:47.147859 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
940 06:53:47.150996 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
941 06:53:47.154402 == TX Byte 1 ==
942 06:53:47.157343 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 06:53:47.160728 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 06:53:47.160805
945 06:53:47.164108 [DATLAT]
946 06:53:47.164209 Freq=800, CH0 RK0
947 06:53:47.164294
948 06:53:47.167996 DATLAT Default: 0xa
949 06:53:47.168074 0, 0xFFFF, sum = 0
950 06:53:47.170923 1, 0xFFFF, sum = 0
951 06:53:47.171022 2, 0xFFFF, sum = 0
952 06:53:47.174380 3, 0xFFFF, sum = 0
953 06:53:47.174484 4, 0xFFFF, sum = 0
954 06:53:47.177726 5, 0xFFFF, sum = 0
955 06:53:47.177830 6, 0xFFFF, sum = 0
956 06:53:47.180838 7, 0xFFFF, sum = 0
957 06:53:47.180991 8, 0xFFFF, sum = 0
958 06:53:47.184275 9, 0x0, sum = 1
959 06:53:47.184421 10, 0x0, sum = 2
960 06:53:47.187944 11, 0x0, sum = 3
961 06:53:47.188069 12, 0x0, sum = 4
962 06:53:47.191208 best_step = 10
963 06:53:47.191345
964 06:53:47.191450 ==
965 06:53:47.194585 Dram Type= 6, Freq= 0, CH_0, rank 0
966 06:53:47.198235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 06:53:47.198318 ==
968 06:53:47.198383 RX Vref Scan: 1
969 06:53:47.201078
970 06:53:47.201159 Set Vref Range= 32 -> 127
971 06:53:47.201263
972 06:53:47.204366 RX Vref 32 -> 127, step: 1
973 06:53:47.204449
974 06:53:47.207983 RX Delay -95 -> 252, step: 8
975 06:53:47.208065
976 06:53:47.211519 Set Vref, RX VrefLevel [Byte0]: 32
977 06:53:47.214399 [Byte1]: 32
978 06:53:47.214483
979 06:53:47.218000 Set Vref, RX VrefLevel [Byte0]: 33
980 06:53:47.221572 [Byte1]: 33
981 06:53:47.221654
982 06:53:47.224914 Set Vref, RX VrefLevel [Byte0]: 34
983 06:53:47.228754 [Byte1]: 34
984 06:53:47.228868
985 06:53:47.232049 Set Vref, RX VrefLevel [Byte0]: 35
986 06:53:47.235162 [Byte1]: 35
987 06:53:47.239145
988 06:53:47.239247 Set Vref, RX VrefLevel [Byte0]: 36
989 06:53:47.242454 [Byte1]: 36
990 06:53:47.246696
991 06:53:47.246798 Set Vref, RX VrefLevel [Byte0]: 37
992 06:53:47.250668 [Byte1]: 37
993 06:53:47.254431
994 06:53:47.254558 Set Vref, RX VrefLevel [Byte0]: 38
995 06:53:47.258009 [Byte1]: 38
996 06:53:47.262789
997 06:53:47.262936 Set Vref, RX VrefLevel [Byte0]: 39
998 06:53:47.265825 [Byte1]: 39
999 06:53:47.270017
1000 06:53:47.270257 Set Vref, RX VrefLevel [Byte0]: 40
1001 06:53:47.273587 [Byte1]: 40
1002 06:53:47.277397
1003 06:53:47.277600 Set Vref, RX VrefLevel [Byte0]: 41
1004 06:53:47.281034 [Byte1]: 41
1005 06:53:47.285417
1006 06:53:47.285716 Set Vref, RX VrefLevel [Byte0]: 42
1007 06:53:47.288403 [Byte1]: 42
1008 06:53:47.292822
1009 06:53:47.293390 Set Vref, RX VrefLevel [Byte0]: 43
1010 06:53:47.295822 [Byte1]: 43
1011 06:53:47.300055
1012 06:53:47.300470 Set Vref, RX VrefLevel [Byte0]: 44
1013 06:53:47.303390 [Byte1]: 44
1014 06:53:47.307740
1015 06:53:47.308324 Set Vref, RX VrefLevel [Byte0]: 45
1016 06:53:47.311218 [Byte1]: 45
1017 06:53:47.315331
1018 06:53:47.315720 Set Vref, RX VrefLevel [Byte0]: 46
1019 06:53:47.318989 [Byte1]: 46
1020 06:53:47.323201
1021 06:53:47.323589 Set Vref, RX VrefLevel [Byte0]: 47
1022 06:53:47.326048 [Byte1]: 47
1023 06:53:47.330489
1024 06:53:47.331018 Set Vref, RX VrefLevel [Byte0]: 48
1025 06:53:47.334388 [Byte1]: 48
1026 06:53:47.337757
1027 06:53:47.341477 Set Vref, RX VrefLevel [Byte0]: 49
1028 06:53:47.344875 [Byte1]: 49
1029 06:53:47.345361
1030 06:53:47.347899 Set Vref, RX VrefLevel [Byte0]: 50
1031 06:53:47.351033 [Byte1]: 50
1032 06:53:47.351490
1033 06:53:47.354405 Set Vref, RX VrefLevel [Byte0]: 51
1034 06:53:47.357984 [Byte1]: 51
1035 06:53:47.358461
1036 06:53:47.361696 Set Vref, RX VrefLevel [Byte0]: 52
1037 06:53:47.364670 [Byte1]: 52
1038 06:53:47.368426
1039 06:53:47.368823 Set Vref, RX VrefLevel [Byte0]: 53
1040 06:53:47.372252 [Byte1]: 53
1041 06:53:47.376449
1042 06:53:47.376831 Set Vref, RX VrefLevel [Byte0]: 54
1043 06:53:47.379440 [Byte1]: 54
1044 06:53:47.383591
1045 06:53:47.384153 Set Vref, RX VrefLevel [Byte0]: 55
1046 06:53:47.387152 [Byte1]: 55
1047 06:53:47.391251
1048 06:53:47.391631 Set Vref, RX VrefLevel [Byte0]: 56
1049 06:53:47.394981 [Byte1]: 56
1050 06:53:47.399125
1051 06:53:47.399506 Set Vref, RX VrefLevel [Byte0]: 57
1052 06:53:47.402199 [Byte1]: 57
1053 06:53:47.406328
1054 06:53:47.406706 Set Vref, RX VrefLevel [Byte0]: 58
1055 06:53:47.409858 [Byte1]: 58
1056 06:53:47.413871
1057 06:53:47.414248 Set Vref, RX VrefLevel [Byte0]: 59
1058 06:53:47.417451 [Byte1]: 59
1059 06:53:47.422204
1060 06:53:47.422663 Set Vref, RX VrefLevel [Byte0]: 60
1061 06:53:47.424845 [Byte1]: 60
1062 06:53:47.429048
1063 06:53:47.429486 Set Vref, RX VrefLevel [Byte0]: 61
1064 06:53:47.432712 [Byte1]: 61
1065 06:53:47.437059
1066 06:53:47.437595 Set Vref, RX VrefLevel [Byte0]: 62
1067 06:53:47.440394 [Byte1]: 62
1068 06:53:47.444824
1069 06:53:47.445201 Set Vref, RX VrefLevel [Byte0]: 63
1070 06:53:47.448023 [Byte1]: 63
1071 06:53:47.452284
1072 06:53:47.452665 Set Vref, RX VrefLevel [Byte0]: 64
1073 06:53:47.455465 [Byte1]: 64
1074 06:53:47.460021
1075 06:53:47.460497 Set Vref, RX VrefLevel [Byte0]: 65
1076 06:53:47.463140 [Byte1]: 65
1077 06:53:47.466988
1078 06:53:47.467481 Set Vref, RX VrefLevel [Byte0]: 66
1079 06:53:47.470711 [Byte1]: 66
1080 06:53:47.475100
1081 06:53:47.475466 Set Vref, RX VrefLevel [Byte0]: 67
1082 06:53:47.478127 [Byte1]: 67
1083 06:53:47.482096
1084 06:53:47.482672 Set Vref, RX VrefLevel [Byte0]: 68
1085 06:53:47.485668 [Byte1]: 68
1086 06:53:47.489995
1087 06:53:47.490465 Set Vref, RX VrefLevel [Byte0]: 69
1088 06:53:47.493596 [Byte1]: 69
1089 06:53:47.497928
1090 06:53:47.498448 Set Vref, RX VrefLevel [Byte0]: 70
1091 06:53:47.500653 [Byte1]: 70
1092 06:53:47.505184
1093 06:53:47.505769 Set Vref, RX VrefLevel [Byte0]: 71
1094 06:53:47.508415 [Byte1]: 71
1095 06:53:47.513196
1096 06:53:47.513693 Set Vref, RX VrefLevel [Byte0]: 72
1097 06:53:47.516309 [Byte1]: 72
1098 06:53:47.520714
1099 06:53:47.521270 Set Vref, RX VrefLevel [Byte0]: 73
1100 06:53:47.523509 [Byte1]: 73
1101 06:53:47.528032
1102 06:53:47.528426 Set Vref, RX VrefLevel [Byte0]: 74
1103 06:53:47.531230 [Byte1]: 74
1104 06:53:47.535535
1105 06:53:47.536137 Set Vref, RX VrefLevel [Byte0]: 75
1106 06:53:47.539117 [Byte1]: 75
1107 06:53:47.543331
1108 06:53:47.543842 Set Vref, RX VrefLevel [Byte0]: 76
1109 06:53:47.546351 [Byte1]: 76
1110 06:53:47.551065
1111 06:53:47.551440 Final RX Vref Byte 0 = 62 to rank0
1112 06:53:47.554159 Final RX Vref Byte 1 = 57 to rank0
1113 06:53:47.557624 Final RX Vref Byte 0 = 62 to rank1
1114 06:53:47.560709 Final RX Vref Byte 1 = 57 to rank1==
1115 06:53:47.564566 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 06:53:47.571117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 06:53:47.571664 ==
1118 06:53:47.572161 DQS Delay:
1119 06:53:47.572609 DQS0 = 0, DQS1 = 0
1120 06:53:47.574112 DQM Delay:
1121 06:53:47.574487 DQM0 = 87, DQM1 = 79
1122 06:53:47.577857 DQ Delay:
1123 06:53:47.578291 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1124 06:53:47.581071 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1125 06:53:47.584236 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1126 06:53:47.587491 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =88
1127 06:53:47.588038
1128 06:53:47.590701
1129 06:53:47.598172 [DQSOSCAuto] RK0, (LSB)MR18= 0x2810, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
1130 06:53:47.601195 CH0 RK0: MR19=606, MR18=2810
1131 06:53:47.608097 CH0_RK0: MR19=0x606, MR18=0x2810, DQSOSC=399, MR23=63, INC=92, DEC=61
1132 06:53:47.608485
1133 06:53:47.611118 ----->DramcWriteLeveling(PI) begin...
1134 06:53:47.611498 ==
1135 06:53:47.614747 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 06:53:47.617659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 06:53:47.618139 ==
1138 06:53:47.621339 Write leveling (Byte 0): 31 => 31
1139 06:53:47.624239 Write leveling (Byte 1): 28 => 28
1140 06:53:47.628326 DramcWriteLeveling(PI) end<-----
1141 06:53:47.628701
1142 06:53:47.628995 ==
1143 06:53:47.631484 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 06:53:47.634403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 06:53:47.634781 ==
1146 06:53:47.637917 [Gating] SW mode calibration
1147 06:53:47.644790 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 06:53:47.651223 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 06:53:47.654498 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1150 06:53:47.657793 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1151 06:53:47.661601 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 06:53:47.705448 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 06:53:47.706236 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 06:53:47.706632 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 06:53:47.707007 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 06:53:47.707406 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 06:53:47.707941 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 06:53:47.708400 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 06:53:47.708843 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 06:53:47.709330 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 06:53:47.709645 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 06:53:47.745759 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 06:53:47.746163 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 06:53:47.746931 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 06:53:47.747405 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 06:53:47.747820 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1167 06:53:47.748136 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1168 06:53:47.748612 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 06:53:47.749094 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 06:53:47.750120 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 06:53:47.750560 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 06:53:47.756965 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 06:53:47.760148 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 06:53:47.763054 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 06:53:47.770289 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1176 06:53:47.773252 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1177 06:53:47.776720 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 06:53:47.780192 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 06:53:47.786767 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 06:53:47.790293 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 06:53:47.793484 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 06:53:47.800019 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
1183 06:53:47.803731 0 10 8 | B1->B0 | 3131 2525 | 0 0 | (1 0) (0 0)
1184 06:53:47.807394 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1185 06:53:47.813751 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 06:53:47.817042 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 06:53:47.820710 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 06:53:47.826847 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 06:53:47.830530 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 06:53:47.834616 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
1191 06:53:47.838163 0 11 8 | B1->B0 | 2d2d 3f3f | 0 0 | (0 0) (0 0)
1192 06:53:47.841950 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1193 06:53:47.845979 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 06:53:47.853078 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 06:53:47.856117 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 06:53:47.859613 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 06:53:47.863851 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 06:53:47.870561 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 06:53:47.874040 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 06:53:47.877109 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1201 06:53:47.883857 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 06:53:47.887273 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 06:53:47.890826 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 06:53:47.897344 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 06:53:47.900463 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 06:53:47.903691 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 06:53:47.907177 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 06:53:47.914022 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 06:53:47.917565 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 06:53:47.920457 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 06:53:47.927442 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 06:53:47.930453 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 06:53:47.934288 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 06:53:47.940835 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 06:53:47.943862 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1216 06:53:47.947227 Total UI for P1: 0, mck2ui 16
1217 06:53:47.950675 best dqsien dly found for B0: ( 0, 14, 6)
1218 06:53:47.954189 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 06:53:47.957702 Total UI for P1: 0, mck2ui 16
1220 06:53:47.960709 best dqsien dly found for B1: ( 0, 14, 8)
1221 06:53:47.964341 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1222 06:53:47.967775 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1223 06:53:47.968066
1224 06:53:47.971249 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1225 06:53:47.974994 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1226 06:53:47.978084 [Gating] SW calibration Done
1227 06:53:47.978456 ==
1228 06:53:47.981642 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 06:53:47.988318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 06:53:47.988781 ==
1231 06:53:47.989454 RX Vref Scan: 0
1232 06:53:47.989906
1233 06:53:47.991500 RX Vref 0 -> 0, step: 1
1234 06:53:47.992238
1235 06:53:47.994843 RX Delay -130 -> 252, step: 16
1236 06:53:47.998181 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1237 06:53:48.001153 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1238 06:53:48.004828 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1239 06:53:48.008084 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
1240 06:53:48.014603 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1241 06:53:48.017713 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1242 06:53:48.021478 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1243 06:53:48.024268 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1244 06:53:48.028187 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1245 06:53:48.034614 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1246 06:53:48.037833 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1247 06:53:48.041504 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1248 06:53:48.044289 iDelay=206, Bit 12, Center 69 (-50 ~ 189) 240
1249 06:53:48.047679 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1250 06:53:48.054304 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1251 06:53:48.057817 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1252 06:53:48.057939 ==
1253 06:53:48.061175 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 06:53:48.064561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 06:53:48.064746 ==
1256 06:53:48.067988 DQS Delay:
1257 06:53:48.068132 DQS0 = 0, DQS1 = 0
1258 06:53:48.068229 DQM Delay:
1259 06:53:48.070831 DQM0 = 84, DQM1 = 75
1260 06:53:48.070978 DQ Delay:
1261 06:53:48.074560 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1262 06:53:48.078078 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1263 06:53:48.081011 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1264 06:53:48.084830 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1265 06:53:48.084936
1266 06:53:48.085026
1267 06:53:48.085119 ==
1268 06:53:48.087847 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 06:53:48.091044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 06:53:48.094562 ==
1271 06:53:48.094643
1272 06:53:48.094706
1273 06:53:48.094764 TX Vref Scan disable
1274 06:53:48.098443 == TX Byte 0 ==
1275 06:53:48.101305 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1276 06:53:48.105000 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1277 06:53:48.107967 == TX Byte 1 ==
1278 06:53:48.111450 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1279 06:53:48.114584 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1280 06:53:48.114665 ==
1281 06:53:48.117916 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 06:53:48.125023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 06:53:48.125122 ==
1284 06:53:48.137318 TX Vref=22, minBit 3, minWin=27, winSum=447
1285 06:53:48.140384 TX Vref=24, minBit 3, minWin=27, winSum=447
1286 06:53:48.143396 TX Vref=26, minBit 9, minWin=27, winSum=450
1287 06:53:48.147068 TX Vref=28, minBit 3, minWin=27, winSum=455
1288 06:53:48.150222 TX Vref=30, minBit 5, minWin=28, winSum=458
1289 06:53:48.153645 TX Vref=32, minBit 4, minWin=28, winSum=455
1290 06:53:48.160375 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 30
1291 06:53:48.160457
1292 06:53:48.164267 Final TX Range 1 Vref 30
1293 06:53:48.164348
1294 06:53:48.164411 ==
1295 06:53:48.167350 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 06:53:48.170914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 06:53:48.171022 ==
1298 06:53:48.171117
1299 06:53:48.171189
1300 06:53:48.174124 TX Vref Scan disable
1301 06:53:48.177444 == TX Byte 0 ==
1302 06:53:48.180466 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1303 06:53:48.184076 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1304 06:53:48.187703 == TX Byte 1 ==
1305 06:53:48.190575 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1306 06:53:48.194165 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1307 06:53:48.194244
1308 06:53:48.197400 [DATLAT]
1309 06:53:48.197479 Freq=800, CH0 RK1
1310 06:53:48.197542
1311 06:53:48.200496 DATLAT Default: 0xa
1312 06:53:48.200576 0, 0xFFFF, sum = 0
1313 06:53:48.204020 1, 0xFFFF, sum = 0
1314 06:53:48.204102 2, 0xFFFF, sum = 0
1315 06:53:48.207230 3, 0xFFFF, sum = 0
1316 06:53:48.207311 4, 0xFFFF, sum = 0
1317 06:53:48.210821 5, 0xFFFF, sum = 0
1318 06:53:48.210903 6, 0xFFFF, sum = 0
1319 06:53:48.214467 7, 0xFFFF, sum = 0
1320 06:53:48.214548 8, 0xFFFF, sum = 0
1321 06:53:48.217360 9, 0x0, sum = 1
1322 06:53:48.217441 10, 0x0, sum = 2
1323 06:53:48.220920 11, 0x0, sum = 3
1324 06:53:48.221001 12, 0x0, sum = 4
1325 06:53:48.224808 best_step = 10
1326 06:53:48.224887
1327 06:53:48.224948 ==
1328 06:53:48.227548 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 06:53:48.231118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 06:53:48.231197 ==
1331 06:53:48.231260 RX Vref Scan: 0
1332 06:53:48.234507
1333 06:53:48.234587 RX Vref 0 -> 0, step: 1
1334 06:53:48.234649
1335 06:53:48.237741 RX Delay -95 -> 252, step: 8
1336 06:53:48.241367 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1337 06:53:48.247841 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1338 06:53:48.251077 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1339 06:53:48.254571 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1340 06:53:48.257717 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1341 06:53:48.261126 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1342 06:53:48.267769 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1343 06:53:48.271329 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1344 06:53:48.275006 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1345 06:53:48.277857 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1346 06:53:48.281404 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1347 06:53:48.285132 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1348 06:53:48.291537 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1349 06:53:48.294834 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1350 06:53:48.298648 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1351 06:53:48.301875 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1352 06:53:48.301955 ==
1353 06:53:48.305153 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 06:53:48.311735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 06:53:48.311815 ==
1356 06:53:48.311877 DQS Delay:
1357 06:53:48.314943 DQS0 = 0, DQS1 = 0
1358 06:53:48.315024 DQM Delay:
1359 06:53:48.315086 DQM0 = 87, DQM1 = 78
1360 06:53:48.318480 DQ Delay:
1361 06:53:48.321373 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1362 06:53:48.325065 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1363 06:53:48.328278 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1364 06:53:48.331735 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1365 06:53:48.331815
1366 06:53:48.331876
1367 06:53:48.338300 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1368 06:53:48.342062 CH0 RK1: MR19=606, MR18=2E17
1369 06:53:48.348936 CH0_RK1: MR19=0x606, MR18=0x2E17, DQSOSC=398, MR23=63, INC=93, DEC=62
1370 06:53:48.351812 [RxdqsGatingPostProcess] freq 800
1371 06:53:48.355470 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 06:53:48.358612 Pre-setting of DQS Precalculation
1373 06:53:48.365629 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 06:53:48.365712 ==
1375 06:53:48.368792 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 06:53:48.372521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 06:53:48.372602 ==
1378 06:53:48.375812 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 06:53:48.382199 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 06:53:48.392277 [CA 0] Center 36 (6~66) winsize 61
1381 06:53:48.395708 [CA 1] Center 36 (6~66) winsize 61
1382 06:53:48.398757 [CA 2] Center 35 (5~65) winsize 61
1383 06:53:48.402066 [CA 3] Center 33 (3~64) winsize 62
1384 06:53:48.405478 [CA 4] Center 34 (4~65) winsize 62
1385 06:53:48.408555 [CA 5] Center 33 (3~64) winsize 62
1386 06:53:48.408636
1387 06:53:48.412442 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1388 06:53:48.412523
1389 06:53:48.415631 [CATrainingPosCal] consider 1 rank data
1390 06:53:48.419144 u2DelayCellTimex100 = 270/100 ps
1391 06:53:48.422274 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1392 06:53:48.425888 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1393 06:53:48.428826 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1394 06:53:48.435676 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1395 06:53:48.439164 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1396 06:53:48.442150 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 06:53:48.442230
1398 06:53:48.445591 CA PerBit enable=1, Macro0, CA PI delay=33
1399 06:53:48.445672
1400 06:53:48.448904 [CBTSetCACLKResult] CA Dly = 33
1401 06:53:48.448984 CS Dly: 4 (0~35)
1402 06:53:48.449047 ==
1403 06:53:48.452233 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 06:53:48.459499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 06:53:48.459581 ==
1406 06:53:48.462334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 06:53:48.469074 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 06:53:48.478059 [CA 0] Center 36 (6~66) winsize 61
1409 06:53:48.481625 [CA 1] Center 36 (6~66) winsize 61
1410 06:53:48.484979 [CA 2] Center 33 (3~64) winsize 62
1411 06:53:48.487962 [CA 3] Center 33 (3~64) winsize 62
1412 06:53:48.491882 [CA 4] Center 34 (4~65) winsize 62
1413 06:53:48.494849 [CA 5] Center 33 (3~64) winsize 62
1414 06:53:48.494938
1415 06:53:48.498547 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1416 06:53:48.498628
1417 06:53:48.502224 [CATrainingPosCal] consider 2 rank data
1418 06:53:48.505762 u2DelayCellTimex100 = 270/100 ps
1419 06:53:48.509702 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1420 06:53:48.512806 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1421 06:53:48.516601 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1422 06:53:48.520712 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1423 06:53:48.524167 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1424 06:53:48.527785 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1425 06:53:48.527876
1426 06:53:48.531496 CA PerBit enable=1, Macro0, CA PI delay=33
1427 06:53:48.531578
1428 06:53:48.535821 [CBTSetCACLKResult] CA Dly = 33
1429 06:53:48.535904 CS Dly: 5 (0~37)
1430 06:53:48.535972
1431 06:53:48.539018 ----->DramcWriteLeveling(PI) begin...
1432 06:53:48.539101 ==
1433 06:53:48.542485 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 06:53:48.545437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 06:53:48.549146 ==
1436 06:53:48.549264 Write leveling (Byte 0): 26 => 26
1437 06:53:48.552266 Write leveling (Byte 1): 31 => 31
1438 06:53:48.555706 DramcWriteLeveling(PI) end<-----
1439 06:53:48.555780
1440 06:53:48.555841 ==
1441 06:53:48.559210 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 06:53:48.566190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 06:53:48.566298 ==
1444 06:53:48.566390 [Gating] SW mode calibration
1445 06:53:48.575729 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 06:53:48.579276 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 06:53:48.582818 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 06:53:48.589370 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 06:53:48.592646 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 06:53:48.596297 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 06:53:48.602493 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 06:53:48.606431 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 06:53:48.609386 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 06:53:48.616388 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 06:53:48.619315 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 06:53:48.622687 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 06:53:48.626144 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 06:53:48.632909 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 06:53:48.636344 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 06:53:48.639807 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1461 06:53:48.646526 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 06:53:48.649515 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 06:53:48.653104 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 06:53:48.659925 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1465 06:53:48.663500 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1466 06:53:48.666269 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 06:53:48.673135 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 06:53:48.676531 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 06:53:48.679833 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 06:53:48.686293 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 06:53:48.689656 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 06:53:48.693295 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 06:53:48.696264 0 9 8 | B1->B0 | 2323 2525 | 1 1 | (1 1) (1 1)
1474 06:53:48.702897 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1475 06:53:48.706694 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 06:53:48.710097 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1477 06:53:48.716212 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 06:53:48.719731 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1479 06:53:48.723358 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 06:53:48.730097 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 06:53:48.733577 0 10 8 | B1->B0 | 2e2e 2f2f | 0 1 | (0 0) (1 0)
1482 06:53:48.736567 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 06:53:48.743308 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 06:53:48.746901 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 06:53:48.750158 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 06:53:48.756668 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 06:53:48.760102 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 06:53:48.763592 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1489 06:53:48.767016 0 11 8 | B1->B0 | 3030 3030 | 1 0 | (0 0) (1 1)
1490 06:53:48.773861 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 06:53:48.776950 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 06:53:48.780507 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 06:53:48.786859 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 06:53:48.790557 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 06:53:48.793620 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 06:53:48.800519 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 06:53:48.803660 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 06:53:48.807346 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 06:53:48.814097 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 06:53:48.816816 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 06:53:48.820359 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 06:53:48.826958 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 06:53:48.830505 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 06:53:48.833714 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 06:53:48.837158 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 06:53:48.843474 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 06:53:48.847083 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 06:53:48.850487 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 06:53:48.857266 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 06:53:48.861034 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 06:53:48.863977 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 06:53:48.870616 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 06:53:48.874095 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1514 06:53:48.877422 Total UI for P1: 0, mck2ui 16
1515 06:53:48.880678 best dqsien dly found for B1: ( 0, 14, 6)
1516 06:53:48.884132 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 06:53:48.887079 Total UI for P1: 0, mck2ui 16
1518 06:53:48.890596 best dqsien dly found for B0: ( 0, 14, 8)
1519 06:53:48.893800 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1520 06:53:48.897837 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1521 06:53:48.897918
1522 06:53:48.900512 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1523 06:53:48.907576 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1524 06:53:48.907776 [Gating] SW calibration Done
1525 06:53:48.907884 ==
1526 06:53:48.910765 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 06:53:48.917554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 06:53:48.917642 ==
1529 06:53:48.917705 RX Vref Scan: 0
1530 06:53:48.917765
1531 06:53:48.920561 RX Vref 0 -> 0, step: 1
1532 06:53:48.920642
1533 06:53:48.924247 RX Delay -130 -> 252, step: 16
1534 06:53:48.927710 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1535 06:53:48.930862 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1536 06:53:48.934093 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1537 06:53:48.937416 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1538 06:53:48.943948 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1539 06:53:48.947645 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1540 06:53:48.950700 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1541 06:53:48.954315 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1542 06:53:48.957725 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1543 06:53:48.964405 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1544 06:53:48.967540 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1545 06:53:48.971234 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1546 06:53:48.974215 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1547 06:53:48.977273 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1548 06:53:48.984525 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1549 06:53:48.987448 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1550 06:53:48.987529 ==
1551 06:53:48.991055 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 06:53:48.994571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 06:53:48.994652 ==
1554 06:53:48.997583 DQS Delay:
1555 06:53:48.997664 DQS0 = 0, DQS1 = 0
1556 06:53:48.997728 DQM Delay:
1557 06:53:49.001335 DQM0 = 84, DQM1 = 76
1558 06:53:49.001432 DQ Delay:
1559 06:53:49.004291 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1560 06:53:49.007867 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1561 06:53:49.011182 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1562 06:53:49.014543 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1563 06:53:49.014658
1564 06:53:49.014752
1565 06:53:49.014841 ==
1566 06:53:49.017572 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 06:53:49.021020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 06:53:49.024640 ==
1569 06:53:49.024773
1570 06:53:49.024843
1571 06:53:49.024934 TX Vref Scan disable
1572 06:53:49.027851 == TX Byte 0 ==
1573 06:53:49.031168 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1574 06:53:49.034697 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1575 06:53:49.038198 == TX Byte 1 ==
1576 06:53:49.041052 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1577 06:53:49.044520 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1578 06:53:49.044605 ==
1579 06:53:49.047805 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 06:53:49.054981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 06:53:49.055064 ==
1582 06:53:49.067251 TX Vref=22, minBit 4, minWin=27, winSum=442
1583 06:53:49.070882 TX Vref=24, minBit 0, minWin=27, winSum=441
1584 06:53:49.073941 TX Vref=26, minBit 8, minWin=27, winSum=449
1585 06:53:49.077497 TX Vref=28, minBit 9, minWin=27, winSum=450
1586 06:53:49.081153 TX Vref=30, minBit 2, minWin=28, winSum=453
1587 06:53:49.084314 TX Vref=32, minBit 9, minWin=27, winSum=452
1588 06:53:49.091131 [TxChooseVref] Worse bit 2, Min win 28, Win sum 453, Final Vref 30
1589 06:53:49.091216
1590 06:53:49.094613 Final TX Range 1 Vref 30
1591 06:53:49.094697
1592 06:53:49.094761 ==
1593 06:53:49.098367 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 06:53:49.101186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 06:53:49.101276 ==
1596 06:53:49.101357
1597 06:53:49.101420
1598 06:53:49.104363 TX Vref Scan disable
1599 06:53:49.107941 == TX Byte 0 ==
1600 06:53:49.111558 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1601 06:53:49.114833 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1602 06:53:49.117618 == TX Byte 1 ==
1603 06:53:49.121225 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1604 06:53:49.124950 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1605 06:53:49.125033
1606 06:53:49.125097 [DATLAT]
1607 06:53:49.128122 Freq=800, CH1 RK0
1608 06:53:49.128204
1609 06:53:49.131306 DATLAT Default: 0xa
1610 06:53:49.131387 0, 0xFFFF, sum = 0
1611 06:53:49.135141 1, 0xFFFF, sum = 0
1612 06:53:49.135225 2, 0xFFFF, sum = 0
1613 06:53:49.138447 3, 0xFFFF, sum = 0
1614 06:53:49.138555 4, 0xFFFF, sum = 0
1615 06:53:49.141273 5, 0xFFFF, sum = 0
1616 06:53:49.141356 6, 0xFFFF, sum = 0
1617 06:53:49.144895 7, 0xFFFF, sum = 0
1618 06:53:49.144976 8, 0xFFFF, sum = 0
1619 06:53:49.148136 9, 0x0, sum = 1
1620 06:53:49.148217 10, 0x0, sum = 2
1621 06:53:49.151160 11, 0x0, sum = 3
1622 06:53:49.151241 12, 0x0, sum = 4
1623 06:53:49.151305 best_step = 10
1624 06:53:49.154832
1625 06:53:49.154939 ==
1626 06:53:49.158011 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 06:53:49.161454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 06:53:49.161578 ==
1629 06:53:49.161670 RX Vref Scan: 1
1630 06:53:49.161756
1631 06:53:49.164465 Set Vref Range= 32 -> 127
1632 06:53:49.164560
1633 06:53:49.168258 RX Vref 32 -> 127, step: 1
1634 06:53:49.168339
1635 06:53:49.171324 RX Delay -95 -> 252, step: 8
1636 06:53:49.171405
1637 06:53:49.174910 Set Vref, RX VrefLevel [Byte0]: 32
1638 06:53:49.177887 [Byte1]: 32
1639 06:53:49.177957
1640 06:53:49.181476 Set Vref, RX VrefLevel [Byte0]: 33
1641 06:53:49.184919 [Byte1]: 33
1642 06:53:49.184988
1643 06:53:49.188139 Set Vref, RX VrefLevel [Byte0]: 34
1644 06:53:49.191558 [Byte1]: 34
1645 06:53:49.195145
1646 06:53:49.195213 Set Vref, RX VrefLevel [Byte0]: 35
1647 06:53:49.198210 [Byte1]: 35
1648 06:53:49.202627
1649 06:53:49.202729 Set Vref, RX VrefLevel [Byte0]: 36
1650 06:53:49.206258 [Byte1]: 36
1651 06:53:49.210307
1652 06:53:49.210377 Set Vref, RX VrefLevel [Byte0]: 37
1653 06:53:49.213514 [Byte1]: 37
1654 06:53:49.217696
1655 06:53:49.217765 Set Vref, RX VrefLevel [Byte0]: 38
1656 06:53:49.220752 [Byte1]: 38
1657 06:53:49.225762
1658 06:53:49.225830 Set Vref, RX VrefLevel [Byte0]: 39
1659 06:53:49.228695 [Byte1]: 39
1660 06:53:49.232976
1661 06:53:49.233047 Set Vref, RX VrefLevel [Byte0]: 40
1662 06:53:49.235990 [Byte1]: 40
1663 06:53:49.240432
1664 06:53:49.240501 Set Vref, RX VrefLevel [Byte0]: 41
1665 06:53:49.243616 [Byte1]: 41
1666 06:53:49.248323
1667 06:53:49.248391 Set Vref, RX VrefLevel [Byte0]: 42
1668 06:53:49.251441 [Byte1]: 42
1669 06:53:49.255500
1670 06:53:49.255568 Set Vref, RX VrefLevel [Byte0]: 43
1671 06:53:49.258967 [Byte1]: 43
1672 06:53:49.263438
1673 06:53:49.263513 Set Vref, RX VrefLevel [Byte0]: 44
1674 06:53:49.266779 [Byte1]: 44
1675 06:53:49.270634
1676 06:53:49.270701 Set Vref, RX VrefLevel [Byte0]: 45
1677 06:53:49.274085 [Byte1]: 45
1678 06:53:49.278614
1679 06:53:49.278683 Set Vref, RX VrefLevel [Byte0]: 46
1680 06:53:49.281635 [Byte1]: 46
1681 06:53:49.286096
1682 06:53:49.286165 Set Vref, RX VrefLevel [Byte0]: 47
1683 06:53:49.289392 [Byte1]: 47
1684 06:53:49.293611
1685 06:53:49.293691 Set Vref, RX VrefLevel [Byte0]: 48
1686 06:53:49.297084 [Byte1]: 48
1687 06:53:49.301325
1688 06:53:49.301403 Set Vref, RX VrefLevel [Byte0]: 49
1689 06:53:49.304504 [Byte1]: 49
1690 06:53:49.308900
1691 06:53:49.308971 Set Vref, RX VrefLevel [Byte0]: 50
1692 06:53:49.311901 [Byte1]: 50
1693 06:53:49.316721
1694 06:53:49.316791 Set Vref, RX VrefLevel [Byte0]: 51
1695 06:53:49.319857 [Byte1]: 51
1696 06:53:49.324061
1697 06:53:49.324136 Set Vref, RX VrefLevel [Byte0]: 52
1698 06:53:49.327182 [Byte1]: 52
1699 06:53:49.331594
1700 06:53:49.331662 Set Vref, RX VrefLevel [Byte0]: 53
1701 06:53:49.335040 [Byte1]: 53
1702 06:53:49.339228
1703 06:53:49.339294 Set Vref, RX VrefLevel [Byte0]: 54
1704 06:53:49.342421 [Byte1]: 54
1705 06:53:49.346594
1706 06:53:49.346661 Set Vref, RX VrefLevel [Byte0]: 55
1707 06:53:49.350415 [Byte1]: 55
1708 06:53:49.354608
1709 06:53:49.354675 Set Vref, RX VrefLevel [Byte0]: 56
1710 06:53:49.357522 [Byte1]: 56
1711 06:53:49.361898
1712 06:53:49.361980 Set Vref, RX VrefLevel [Byte0]: 57
1713 06:53:49.365363 [Byte1]: 57
1714 06:53:49.369498
1715 06:53:49.369582 Set Vref, RX VrefLevel [Byte0]: 58
1716 06:53:49.372958 [Byte1]: 58
1717 06:53:49.377388
1718 06:53:49.377469 Set Vref, RX VrefLevel [Byte0]: 59
1719 06:53:49.380935 [Byte1]: 59
1720 06:53:49.384564
1721 06:53:49.384644 Set Vref, RX VrefLevel [Byte0]: 60
1722 06:53:49.388009 [Byte1]: 60
1723 06:53:49.392195
1724 06:53:49.392275 Set Vref, RX VrefLevel [Byte0]: 61
1725 06:53:49.395456 [Byte1]: 61
1726 06:53:49.399871
1727 06:53:49.399952 Set Vref, RX VrefLevel [Byte0]: 62
1728 06:53:49.403136 [Byte1]: 62
1729 06:53:49.407342
1730 06:53:49.407422 Set Vref, RX VrefLevel [Byte0]: 63
1731 06:53:49.410634 [Byte1]: 63
1732 06:53:49.414885
1733 06:53:49.414965 Set Vref, RX VrefLevel [Byte0]: 64
1734 06:53:49.418499 [Byte1]: 64
1735 06:53:49.422690
1736 06:53:49.422771 Set Vref, RX VrefLevel [Byte0]: 65
1737 06:53:49.425944 [Byte1]: 65
1738 06:53:49.430454
1739 06:53:49.430535 Set Vref, RX VrefLevel [Byte0]: 66
1740 06:53:49.433527 [Byte1]: 66
1741 06:53:49.437753
1742 06:53:49.437837 Set Vref, RX VrefLevel [Byte0]: 67
1743 06:53:49.441338 [Byte1]: 67
1744 06:53:49.445611
1745 06:53:49.445688 Set Vref, RX VrefLevel [Byte0]: 68
1746 06:53:49.448592 [Byte1]: 68
1747 06:53:49.452891
1748 06:53:49.452988 Set Vref, RX VrefLevel [Byte0]: 69
1749 06:53:49.456612 [Byte1]: 69
1750 06:53:49.460947
1751 06:53:49.461017 Set Vref, RX VrefLevel [Byte0]: 70
1752 06:53:49.464057 [Byte1]: 70
1753 06:53:49.468185
1754 06:53:49.468268 Set Vref, RX VrefLevel [Byte0]: 71
1755 06:53:49.471704 [Byte1]: 71
1756 06:53:49.475882
1757 06:53:49.475966 Set Vref, RX VrefLevel [Byte0]: 72
1758 06:53:49.479352 [Byte1]: 72
1759 06:53:49.483531
1760 06:53:49.483616 Set Vref, RX VrefLevel [Byte0]: 73
1761 06:53:49.486969 [Byte1]: 73
1762 06:53:49.491315
1763 06:53:49.491399 Set Vref, RX VrefLevel [Byte0]: 74
1764 06:53:49.494572 [Byte1]: 74
1765 06:53:49.498759
1766 06:53:49.498839 Set Vref, RX VrefLevel [Byte0]: 75
1767 06:53:49.501708 [Byte1]: 75
1768 06:53:49.506507
1769 06:53:49.506587 Set Vref, RX VrefLevel [Byte0]: 76
1770 06:53:49.509624 [Byte1]: 76
1771 06:53:49.513944
1772 06:53:49.514024 Set Vref, RX VrefLevel [Byte0]: 77
1773 06:53:49.517038 [Byte1]: 77
1774 06:53:49.521303
1775 06:53:49.521568 Set Vref, RX VrefLevel [Byte0]: 78
1776 06:53:49.524662 [Byte1]: 78
1777 06:53:49.529125
1778 06:53:49.529219 Final RX Vref Byte 0 = 67 to rank0
1779 06:53:49.532504 Final RX Vref Byte 1 = 58 to rank0
1780 06:53:49.535474 Final RX Vref Byte 0 = 67 to rank1
1781 06:53:49.539146 Final RX Vref Byte 1 = 58 to rank1==
1782 06:53:49.542770 Dram Type= 6, Freq= 0, CH_1, rank 0
1783 06:53:49.548734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1784 06:53:49.548817 ==
1785 06:53:49.548895 DQS Delay:
1786 06:53:49.548958 DQS0 = 0, DQS1 = 0
1787 06:53:49.552444 DQM Delay:
1788 06:53:49.552519 DQM0 = 83, DQM1 = 74
1789 06:53:49.556096 DQ Delay:
1790 06:53:49.559197 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1791 06:53:49.559275 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =76
1792 06:53:49.562149 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1793 06:53:49.565740 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1794 06:53:49.565818
1795 06:53:49.569159
1796 06:53:49.575903 [DQSOSCAuto] RK0, (LSB)MR18= 0x26fb, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1797 06:53:49.579375 CH1 RK0: MR19=605, MR18=26FB
1798 06:53:49.586015 CH1_RK0: MR19=0x605, MR18=0x26FB, DQSOSC=400, MR23=63, INC=92, DEC=61
1799 06:53:49.586100
1800 06:53:49.589454 ----->DramcWriteLeveling(PI) begin...
1801 06:53:49.589536 ==
1802 06:53:49.593288 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 06:53:49.596240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1804 06:53:49.596319 ==
1805 06:53:49.599411 Write leveling (Byte 0): 28 => 28
1806 06:53:49.602794 Write leveling (Byte 1): 27 => 27
1807 06:53:49.605916 DramcWriteLeveling(PI) end<-----
1808 06:53:49.605991
1809 06:53:49.606059 ==
1810 06:53:49.609418 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 06:53:49.613055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 06:53:49.613147 ==
1813 06:53:49.616308 [Gating] SW mode calibration
1814 06:53:49.622932 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1815 06:53:49.629389 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1816 06:53:49.632748 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1817 06:53:49.636163 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1818 06:53:49.640026 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 06:53:49.646566 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 06:53:49.649582 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 06:53:49.653233 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 06:53:49.659741 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 06:53:49.663100 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 06:53:49.666661 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 06:53:49.673598 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 06:53:49.676866 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 06:53:49.679809 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 06:53:49.686645 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 06:53:49.689803 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1830 06:53:49.693337 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 06:53:49.696884 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 06:53:49.703161 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1833 06:53:49.706876 0 8 4 | B1->B0 | 2423 2323 | 1 0 | (1 0) (1 0)
1834 06:53:49.709960 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 06:53:49.716542 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 06:53:49.720217 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 06:53:49.723281 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 06:53:49.730212 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 06:53:49.733230 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 06:53:49.737123 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 06:53:49.743904 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1842 06:53:49.747173 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1843 06:53:49.750306 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 06:53:49.756964 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1845 06:53:49.760145 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 06:53:49.763392 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 06:53:49.770523 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 06:53:49.773949 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1849 06:53:49.776865 0 10 4 | B1->B0 | 3030 2e2e | 0 1 | (0 0) (1 0)
1850 06:53:49.780073 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1851 06:53:49.787395 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1852 06:53:49.790327 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 06:53:49.793551 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 06:53:49.800705 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 06:53:49.804284 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 06:53:49.807086 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 06:53:49.814068 0 11 4 | B1->B0 | 2a2a 3636 | 0 0 | (0 0) (0 0)
1858 06:53:49.817223 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1859 06:53:49.820854 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 06:53:49.827695 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 06:53:49.830878 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 06:53:49.833976 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 06:53:49.837419 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 06:53:49.844165 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 06:53:49.847732 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1866 06:53:49.850948 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 06:53:49.857522 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 06:53:49.860536 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 06:53:49.864196 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 06:53:49.870900 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 06:53:49.873911 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 06:53:49.877803 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 06:53:49.884660 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 06:53:49.887646 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 06:53:49.891000 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 06:53:49.897751 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 06:53:49.900750 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 06:53:49.904288 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 06:53:49.907610 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 06:53:49.914210 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1881 06:53:49.917435 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1882 06:53:49.921139 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1883 06:53:49.923970 Total UI for P1: 0, mck2ui 16
1884 06:53:49.927732 best dqsien dly found for B0: ( 0, 14, 2)
1885 06:53:49.934633 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 06:53:49.934736 Total UI for P1: 0, mck2ui 16
1887 06:53:49.941200 best dqsien dly found for B1: ( 0, 14, 8)
1888 06:53:49.944633 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1889 06:53:49.948143 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1890 06:53:49.948244
1891 06:53:49.950957 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1892 06:53:49.954573 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1893 06:53:49.958039 [Gating] SW calibration Done
1894 06:53:49.958141 ==
1895 06:53:49.961448 Dram Type= 6, Freq= 0, CH_1, rank 1
1896 06:53:49.964503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1897 06:53:49.964616 ==
1898 06:53:49.968300 RX Vref Scan: 0
1899 06:53:49.968372
1900 06:53:49.968432 RX Vref 0 -> 0, step: 1
1901 06:53:49.968506
1902 06:53:49.971057 RX Delay -130 -> 252, step: 16
1903 06:53:49.974899 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1904 06:53:49.981482 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1905 06:53:49.984840 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1906 06:53:49.988350 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1907 06:53:49.991376 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1908 06:53:49.994744 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1909 06:53:49.998615 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1910 06:53:50.004995 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1911 06:53:50.008355 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1912 06:53:50.011689 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1913 06:53:50.015065 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1914 06:53:50.018102 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1915 06:53:50.024937 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1916 06:53:50.027994 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1917 06:53:50.031594 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1918 06:53:50.034676 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1919 06:53:50.034780 ==
1920 06:53:50.038321 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 06:53:50.045128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 06:53:50.045295 ==
1923 06:53:50.045369 DQS Delay:
1924 06:53:50.045430 DQS0 = 0, DQS1 = 0
1925 06:53:50.048159 DQM Delay:
1926 06:53:50.048294 DQM0 = 81, DQM1 = 78
1927 06:53:50.051817 DQ Delay:
1928 06:53:50.055112 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1929 06:53:50.055262 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1930 06:53:50.058378 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1931 06:53:50.061743 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1932 06:53:50.065159
1933 06:53:50.065379
1934 06:53:50.065483 ==
1935 06:53:50.068084 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 06:53:50.071624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 06:53:50.071790 ==
1938 06:53:50.071899
1939 06:53:50.071992
1940 06:53:50.075058 TX Vref Scan disable
1941 06:53:50.075229 == TX Byte 0 ==
1942 06:53:50.081916 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1943 06:53:50.085031 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1944 06:53:50.085168 == TX Byte 1 ==
1945 06:53:50.189865 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1946 06:53:50.190074 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1947 06:53:50.190180 ==
1948 06:53:50.190314 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 06:53:50.190424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 06:53:50.190542 ==
1951 06:53:50.190661 TX Vref=22, minBit 1, minWin=27, winSum=443
1952 06:53:50.190752 TX Vref=24, minBit 8, minWin=27, winSum=442
1953 06:53:50.190838 TX Vref=26, minBit 1, minWin=27, winSum=444
1954 06:53:50.190926 TX Vref=28, minBit 11, minWin=27, winSum=445
1955 06:53:50.191010 TX Vref=30, minBit 13, minWin=27, winSum=448
1956 06:53:50.191100 TX Vref=32, minBit 0, minWin=28, winSum=448
1957 06:53:50.191185 [TxChooseVref] Worse bit 0, Min win 28, Win sum 448, Final Vref 32
1958 06:53:50.191269
1959 06:53:50.191359 Final TX Range 1 Vref 32
1960 06:53:50.191441
1961 06:53:50.191528 ==
1962 06:53:50.191611 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 06:53:50.191694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 06:53:50.191789 ==
1965 06:53:50.191881
1966 06:53:50.191977
1967 06:53:50.192070 TX Vref Scan disable
1968 06:53:50.192159 == TX Byte 0 ==
1969 06:53:50.192255 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1970 06:53:50.192329 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1971 06:53:50.192390 == TX Byte 1 ==
1972 06:53:50.192445 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1973 06:53:50.192499 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1974 06:53:50.192553
1975 06:53:50.192604 [DATLAT]
1976 06:53:50.192662 Freq=800, CH1 RK1
1977 06:53:50.192715
1978 06:53:50.192767 DATLAT Default: 0xa
1979 06:53:50.192820 0, 0xFFFF, sum = 0
1980 06:53:50.192873 1, 0xFFFF, sum = 0
1981 06:53:50.192935 2, 0xFFFF, sum = 0
1982 06:53:50.192989 3, 0xFFFF, sum = 0
1983 06:53:50.193042 4, 0xFFFF, sum = 0
1984 06:53:50.193095 5, 0xFFFF, sum = 0
1985 06:53:50.193152 6, 0xFFFF, sum = 0
1986 06:53:50.193236 7, 0xFFFF, sum = 0
1987 06:53:50.193325 8, 0xFFFF, sum = 0
1988 06:53:50.195802 9, 0x0, sum = 1
1989 06:53:50.195907 10, 0x0, sum = 2
1990 06:53:50.198592 11, 0x0, sum = 3
1991 06:53:50.198690 12, 0x0, sum = 4
1992 06:53:50.201986 best_step = 10
1993 06:53:50.202083
1994 06:53:50.202156 ==
1995 06:53:50.205566 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 06:53:50.208795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 06:53:50.208923 ==
1998 06:53:50.212059 RX Vref Scan: 0
1999 06:53:50.212167
2000 06:53:50.212268 RX Vref 0 -> 0, step: 1
2001 06:53:50.212361
2002 06:53:50.215639 RX Delay -95 -> 252, step: 8
2003 06:53:50.222379 iDelay=201, Bit 0, Center 84 (-23 ~ 192) 216
2004 06:53:50.225505 iDelay=201, Bit 1, Center 72 (-39 ~ 184) 224
2005 06:53:50.229092 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2006 06:53:50.232342 iDelay=201, Bit 3, Center 80 (-31 ~ 192) 224
2007 06:53:50.235491 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2008 06:53:50.242728 iDelay=201, Bit 5, Center 92 (-15 ~ 200) 216
2009 06:53:50.245827 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2010 06:53:50.249575 iDelay=201, Bit 7, Center 76 (-31 ~ 184) 216
2011 06:53:50.252516 iDelay=201, Bit 8, Center 64 (-55 ~ 184) 240
2012 06:53:50.256063 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2013 06:53:50.259467 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2014 06:53:50.265927 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2015 06:53:50.269149 iDelay=201, Bit 12, Center 84 (-31 ~ 200) 232
2016 06:53:50.272702 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2017 06:53:50.276298 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2018 06:53:50.279512 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2019 06:53:50.282996 ==
2020 06:53:50.286357 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 06:53:50.289520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 06:53:50.289695 ==
2023 06:53:50.289824 DQS Delay:
2024 06:53:50.292944 DQS0 = 0, DQS1 = 0
2025 06:53:50.293061 DQM Delay:
2026 06:53:50.295985 DQM0 = 80, DQM1 = 76
2027 06:53:50.296122 DQ Delay:
2028 06:53:50.299645 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =80
2029 06:53:50.303204 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
2030 06:53:50.306246 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2031 06:53:50.309511 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
2032 06:53:50.309653
2033 06:53:50.309750
2034 06:53:50.316015 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f2a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
2035 06:53:50.319556 CH1 RK1: MR19=606, MR18=1F2A
2036 06:53:50.326333 CH1_RK1: MR19=0x606, MR18=0x1F2A, DQSOSC=399, MR23=63, INC=92, DEC=61
2037 06:53:50.329888 [RxdqsGatingPostProcess] freq 800
2038 06:53:50.332926 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2039 06:53:50.336292 Pre-setting of DQS Precalculation
2040 06:53:50.343347 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2041 06:53:50.349715 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2042 06:53:50.356463 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2043 06:53:50.356595
2044 06:53:50.356688
2045 06:53:50.360067 [Calibration Summary] 1600 Mbps
2046 06:53:50.360180 CH 0, Rank 0
2047 06:53:50.363171 SW Impedance : PASS
2048 06:53:50.366531 DUTY Scan : NO K
2049 06:53:50.366639 ZQ Calibration : PASS
2050 06:53:50.369695 Jitter Meter : NO K
2051 06:53:50.373134 CBT Training : PASS
2052 06:53:50.373241 Write leveling : PASS
2053 06:53:50.376224 RX DQS gating : PASS
2054 06:53:50.380124 RX DQ/DQS(RDDQC) : PASS
2055 06:53:50.380224 TX DQ/DQS : PASS
2056 06:53:50.383139 RX DATLAT : PASS
2057 06:53:50.383239 RX DQ/DQS(Engine): PASS
2058 06:53:50.386260 TX OE : NO K
2059 06:53:50.386337 All Pass.
2060 06:53:50.386426
2061 06:53:50.389883 CH 0, Rank 1
2062 06:53:50.390019 SW Impedance : PASS
2063 06:53:50.392754 DUTY Scan : NO K
2064 06:53:50.396024 ZQ Calibration : PASS
2065 06:53:50.396132 Jitter Meter : NO K
2066 06:53:50.399648 CBT Training : PASS
2067 06:53:50.403212 Write leveling : PASS
2068 06:53:50.403312 RX DQS gating : PASS
2069 06:53:50.406197 RX DQ/DQS(RDDQC) : PASS
2070 06:53:50.409671 TX DQ/DQS : PASS
2071 06:53:50.409772 RX DATLAT : PASS
2072 06:53:50.413227 RX DQ/DQS(Engine): PASS
2073 06:53:50.416257 TX OE : NO K
2074 06:53:50.416356 All Pass.
2075 06:53:50.416445
2076 06:53:50.416534 CH 1, Rank 0
2077 06:53:50.419733 SW Impedance : PASS
2078 06:53:50.423363 DUTY Scan : NO K
2079 06:53:50.423468 ZQ Calibration : PASS
2080 06:53:50.426334 Jitter Meter : NO K
2081 06:53:50.426433 CBT Training : PASS
2082 06:53:50.429803 Write leveling : PASS
2083 06:53:50.433606 RX DQS gating : PASS
2084 06:53:50.433712 RX DQ/DQS(RDDQC) : PASS
2085 06:53:50.436684 TX DQ/DQS : PASS
2086 06:53:50.440223 RX DATLAT : PASS
2087 06:53:50.440372 RX DQ/DQS(Engine): PASS
2088 06:53:50.443268 TX OE : NO K
2089 06:53:50.443397 All Pass.
2090 06:53:50.443506
2091 06:53:50.446434 CH 1, Rank 1
2092 06:53:50.446552 SW Impedance : PASS
2093 06:53:50.450091 DUTY Scan : NO K
2094 06:53:50.453104 ZQ Calibration : PASS
2095 06:53:50.453295 Jitter Meter : NO K
2096 06:53:50.456819 CBT Training : PASS
2097 06:53:50.456968 Write leveling : PASS
2098 06:53:50.460133 RX DQS gating : PASS
2099 06:53:50.463377 RX DQ/DQS(RDDQC) : PASS
2100 06:53:50.463525 TX DQ/DQS : PASS
2101 06:53:50.466832 RX DATLAT : PASS
2102 06:53:50.470105 RX DQ/DQS(Engine): PASS
2103 06:53:50.470197 TX OE : NO K
2104 06:53:50.473175 All Pass.
2105 06:53:50.473289
2106 06:53:50.473385 DramC Write-DBI off
2107 06:53:50.476952 PER_BANK_REFRESH: Hybrid Mode
2108 06:53:50.477053 TX_TRACKING: ON
2109 06:53:50.480532 [GetDramInforAfterCalByMRR] Vendor 6.
2110 06:53:50.486503 [GetDramInforAfterCalByMRR] Revision 606.
2111 06:53:50.490282 [GetDramInforAfterCalByMRR] Revision 2 0.
2112 06:53:50.490384 MR0 0x3b3b
2113 06:53:50.490478 MR8 0x5151
2114 06:53:50.493404 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 06:53:50.493481
2116 06:53:50.496740 MR0 0x3b3b
2117 06:53:50.496813 MR8 0x5151
2118 06:53:50.500255 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 06:53:50.500355
2120 06:53:50.510160 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2121 06:53:50.513693 [FAST_K] Save calibration result to emmc
2122 06:53:50.516975 [FAST_K] Save calibration result to emmc
2123 06:53:50.520046 dram_init: config_dvfs: 1
2124 06:53:50.523663 dramc_set_vcore_voltage set vcore to 662500
2125 06:53:50.526973 Read voltage for 1200, 2
2126 06:53:50.527049 Vio18 = 0
2127 06:53:50.527111 Vcore = 662500
2128 06:53:50.530359 Vdram = 0
2129 06:53:50.530458 Vddq = 0
2130 06:53:50.530547 Vmddr = 0
2131 06:53:50.537055 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2132 06:53:50.540739 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2133 06:53:50.543858 MEM_TYPE=3, freq_sel=15
2134 06:53:50.547477 sv_algorithm_assistance_LP4_1600
2135 06:53:50.550615 ============ PULL DRAM RESETB DOWN ============
2136 06:53:50.554149 ========== PULL DRAM RESETB DOWN end =========
2137 06:53:50.560250 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2138 06:53:50.563944 ===================================
2139 06:53:50.564119 LPDDR4 DRAM CONFIGURATION
2140 06:53:50.567592 ===================================
2141 06:53:50.570581 EX_ROW_EN[0] = 0x0
2142 06:53:50.570687 EX_ROW_EN[1] = 0x0
2143 06:53:50.573921 LP4Y_EN = 0x0
2144 06:53:50.574001 WORK_FSP = 0x0
2145 06:53:50.577375 WL = 0x4
2146 06:53:50.577497 RL = 0x4
2147 06:53:50.580685 BL = 0x2
2148 06:53:50.580794 RPST = 0x0
2149 06:53:50.583858 RD_PRE = 0x0
2150 06:53:50.587406 WR_PRE = 0x1
2151 06:53:50.587512 WR_PST = 0x0
2152 06:53:50.590919 DBI_WR = 0x0
2153 06:53:50.591021 DBI_RD = 0x0
2154 06:53:50.594020 OTF = 0x1
2155 06:53:50.597604 ===================================
2156 06:53:50.600993 ===================================
2157 06:53:50.601102 ANA top config
2158 06:53:50.604155 ===================================
2159 06:53:50.607125 DLL_ASYNC_EN = 0
2160 06:53:50.610930 ALL_SLAVE_EN = 0
2161 06:53:50.611038 NEW_RANK_MODE = 1
2162 06:53:50.614221 DLL_IDLE_MODE = 1
2163 06:53:50.617151 LP45_APHY_COMB_EN = 1
2164 06:53:50.620436 TX_ODT_DIS = 1
2165 06:53:50.620536 NEW_8X_MODE = 1
2166 06:53:50.624055 ===================================
2167 06:53:50.627365 ===================================
2168 06:53:50.630767 data_rate = 2400
2169 06:53:50.633805 CKR = 1
2170 06:53:50.637111 DQ_P2S_RATIO = 8
2171 06:53:50.640553 ===================================
2172 06:53:50.644401 CA_P2S_RATIO = 8
2173 06:53:50.647341 DQ_CA_OPEN = 0
2174 06:53:50.647447 DQ_SEMI_OPEN = 0
2175 06:53:50.650559 CA_SEMI_OPEN = 0
2176 06:53:50.654323 CA_FULL_RATE = 0
2177 06:53:50.657466 DQ_CKDIV4_EN = 0
2178 06:53:50.661141 CA_CKDIV4_EN = 0
2179 06:53:50.661293 CA_PREDIV_EN = 0
2180 06:53:50.664359 PH8_DLY = 17
2181 06:53:50.667579 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2182 06:53:50.671249 DQ_AAMCK_DIV = 4
2183 06:53:50.674145 CA_AAMCK_DIV = 4
2184 06:53:50.677826 CA_ADMCK_DIV = 4
2185 06:53:50.677930 DQ_TRACK_CA_EN = 0
2186 06:53:50.680878 CA_PICK = 1200
2187 06:53:50.684679 CA_MCKIO = 1200
2188 06:53:50.687805 MCKIO_SEMI = 0
2189 06:53:50.690715 PLL_FREQ = 2366
2190 06:53:50.694148 DQ_UI_PI_RATIO = 32
2191 06:53:50.698018 CA_UI_PI_RATIO = 0
2192 06:53:50.701203 ===================================
2193 06:53:50.704175 ===================================
2194 06:53:50.704281 memory_type:LPDDR4
2195 06:53:50.707775 GP_NUM : 10
2196 06:53:50.711334 SRAM_EN : 1
2197 06:53:50.711426 MD32_EN : 0
2198 06:53:50.714329 ===================================
2199 06:53:50.717989 [ANA_INIT] >>>>>>>>>>>>>>
2200 06:53:50.721130 <<<<<< [CONFIGURE PHASE]: ANA_TX
2201 06:53:50.724416 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2202 06:53:50.728013 ===================================
2203 06:53:50.728097 data_rate = 2400,PCW = 0X5b00
2204 06:53:50.731245 ===================================
2205 06:53:50.734622 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2206 06:53:50.741342 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2207 06:53:50.747808 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2208 06:53:50.751486 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2209 06:53:50.754671 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2210 06:53:50.758259 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2211 06:53:50.761432 [ANA_INIT] flow start
2212 06:53:50.764410 [ANA_INIT] PLL >>>>>>>>
2213 06:53:50.764486 [ANA_INIT] PLL <<<<<<<<
2214 06:53:50.768109 [ANA_INIT] MIDPI >>>>>>>>
2215 06:53:50.771240 [ANA_INIT] MIDPI <<<<<<<<
2216 06:53:50.771336 [ANA_INIT] DLL >>>>>>>>
2217 06:53:50.774852 [ANA_INIT] DLL <<<<<<<<
2218 06:53:50.778011 [ANA_INIT] flow end
2219 06:53:50.781653 ============ LP4 DIFF to SE enter ============
2220 06:53:50.784680 ============ LP4 DIFF to SE exit ============
2221 06:53:50.787957 [ANA_INIT] <<<<<<<<<<<<<
2222 06:53:50.791624 [Flow] Enable top DCM control >>>>>
2223 06:53:50.794780 [Flow] Enable top DCM control <<<<<
2224 06:53:50.797953 Enable DLL master slave shuffle
2225 06:53:50.801555 ==============================================================
2226 06:53:50.805061 Gating Mode config
2227 06:53:50.807970 ==============================================================
2228 06:53:50.811291 Config description:
2229 06:53:50.821367 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2230 06:53:50.828361 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2231 06:53:50.831470 SELPH_MODE 0: By rank 1: By Phase
2232 06:53:50.838252 ==============================================================
2233 06:53:50.841863 GAT_TRACK_EN = 1
2234 06:53:50.844954 RX_GATING_MODE = 2
2235 06:53:50.848645 RX_GATING_TRACK_MODE = 2
2236 06:53:50.848720 SELPH_MODE = 1
2237 06:53:50.851634 PICG_EARLY_EN = 1
2238 06:53:50.855349 VALID_LAT_VALUE = 1
2239 06:53:50.861704 ==============================================================
2240 06:53:50.865094 Enter into Gating configuration >>>>
2241 06:53:50.868613 Exit from Gating configuration <<<<
2242 06:53:50.872247 Enter into DVFS_PRE_config >>>>>
2243 06:53:50.881816 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2244 06:53:50.885789 Exit from DVFS_PRE_config <<<<<
2245 06:53:50.888731 Enter into PICG configuration >>>>
2246 06:53:50.891937 Exit from PICG configuration <<<<
2247 06:53:50.895221 [RX_INPUT] configuration >>>>>
2248 06:53:50.898328 [RX_INPUT] configuration <<<<<
2249 06:53:50.901732 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2250 06:53:50.909019 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2251 06:53:50.915231 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2252 06:53:50.918898 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2253 06:53:50.925268 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2254 06:53:50.932112 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2255 06:53:50.935267 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2256 06:53:50.938966 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2257 06:53:50.945509 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2258 06:53:50.948693 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2259 06:53:50.952290 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2260 06:53:50.959165 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2261 06:53:50.962460 ===================================
2262 06:53:50.962542 LPDDR4 DRAM CONFIGURATION
2263 06:53:50.965509 ===================================
2264 06:53:50.968836 EX_ROW_EN[0] = 0x0
2265 06:53:50.968917 EX_ROW_EN[1] = 0x0
2266 06:53:50.972513 LP4Y_EN = 0x0
2267 06:53:50.972593 WORK_FSP = 0x0
2268 06:53:50.975816 WL = 0x4
2269 06:53:50.975897 RL = 0x4
2270 06:53:50.979285 BL = 0x2
2271 06:53:50.982354 RPST = 0x0
2272 06:53:50.982435 RD_PRE = 0x0
2273 06:53:50.985965 WR_PRE = 0x1
2274 06:53:50.986044 WR_PST = 0x0
2275 06:53:50.989376 DBI_WR = 0x0
2276 06:53:50.989447 DBI_RD = 0x0
2277 06:53:50.992547 OTF = 0x1
2278 06:53:50.996193 ===================================
2279 06:53:50.999307 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2280 06:53:51.002811 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2281 06:53:51.006498 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2282 06:53:51.009374 ===================================
2283 06:53:51.012600 LPDDR4 DRAM CONFIGURATION
2284 06:53:51.016079 ===================================
2285 06:53:51.019257 EX_ROW_EN[0] = 0x10
2286 06:53:51.019322 EX_ROW_EN[1] = 0x0
2287 06:53:51.022852 LP4Y_EN = 0x0
2288 06:53:51.022916 WORK_FSP = 0x0
2289 06:53:51.025911 WL = 0x4
2290 06:53:51.025976 RL = 0x4
2291 06:53:51.029331 BL = 0x2
2292 06:53:51.029398 RPST = 0x0
2293 06:53:51.032938 RD_PRE = 0x0
2294 06:53:51.033008 WR_PRE = 0x1
2295 06:53:51.035857 WR_PST = 0x0
2296 06:53:51.035922 DBI_WR = 0x0
2297 06:53:51.039369 DBI_RD = 0x0
2298 06:53:51.039439 OTF = 0x1
2299 06:53:51.042601 ===================================
2300 06:53:51.049427 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2301 06:53:51.049499 ==
2302 06:53:51.053177 Dram Type= 6, Freq= 0, CH_0, rank 0
2303 06:53:51.056268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2304 06:53:51.059750 ==
2305 06:53:51.059822 [Duty_Offset_Calibration]
2306 06:53:51.063166 B0:2 B1:-1 CA:1
2307 06:53:51.063236
2308 06:53:51.066277 [DutyScan_Calibration_Flow] k_type=0
2309 06:53:51.074270
2310 06:53:51.074351 ==CLK 0==
2311 06:53:51.077340 Final CLK duty delay cell = -4
2312 06:53:51.080597 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2313 06:53:51.083689 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2314 06:53:51.087204 [-4] AVG Duty = 4953%(X100)
2315 06:53:51.087291
2316 06:53:51.090536 CH0 CLK Duty spec in!! Max-Min= 156%
2317 06:53:51.094102 [DutyScan_Calibration_Flow] ====Done====
2318 06:53:51.094217
2319 06:53:51.097339 [DutyScan_Calibration_Flow] k_type=1
2320 06:53:51.112868
2321 06:53:51.112994 ==DQS 0 ==
2322 06:53:51.116294 Final DQS duty delay cell = 0
2323 06:53:51.119477 [0] MAX Duty = 5125%(X100), DQS PI = 48
2324 06:53:51.123094 [0] MIN Duty = 5000%(X100), DQS PI = 12
2325 06:53:51.123167 [0] AVG Duty = 5062%(X100)
2326 06:53:51.126212
2327 06:53:51.126290 ==DQS 1 ==
2328 06:53:51.129819 Final DQS duty delay cell = -4
2329 06:53:51.132791 [-4] MAX Duty = 5124%(X100), DQS PI = 18
2330 06:53:51.136464 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2331 06:53:51.139607 [-4] AVG Duty = 5062%(X100)
2332 06:53:51.139678
2333 06:53:51.143216 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2334 06:53:51.143296
2335 06:53:51.146218 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2336 06:53:51.149773 [DutyScan_Calibration_Flow] ====Done====
2337 06:53:51.149845
2338 06:53:51.152685 [DutyScan_Calibration_Flow] k_type=3
2339 06:53:51.169787
2340 06:53:51.169872 ==DQM 0 ==
2341 06:53:51.173358 Final DQM duty delay cell = 0
2342 06:53:51.176055 [0] MAX Duty = 5000%(X100), DQS PI = 54
2343 06:53:51.179921 [0] MIN Duty = 4875%(X100), DQS PI = 4
2344 06:53:51.179992 [0] AVG Duty = 4937%(X100)
2345 06:53:51.182873
2346 06:53:51.182942 ==DQM 1 ==
2347 06:53:51.186487 Final DQM duty delay cell = 0
2348 06:53:51.190250 [0] MAX Duty = 5156%(X100), DQS PI = 62
2349 06:53:51.193072 [0] MIN Duty = 4969%(X100), DQS PI = 58
2350 06:53:51.193175 [0] AVG Duty = 5062%(X100)
2351 06:53:51.193265
2352 06:53:51.199644 CH0 DQM 0 Duty spec in!! Max-Min= 125%
2353 06:53:51.199725
2354 06:53:51.203150 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2355 06:53:51.206771 [DutyScan_Calibration_Flow] ====Done====
2356 06:53:51.206852
2357 06:53:51.209607 [DutyScan_Calibration_Flow] k_type=2
2358 06:53:51.225382
2359 06:53:51.225463 ==DQ 0 ==
2360 06:53:51.228989 Final DQ duty delay cell = -4
2361 06:53:51.232079 [-4] MAX Duty = 5031%(X100), DQS PI = 0
2362 06:53:51.235830 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2363 06:53:51.238842 [-4] AVG Duty = 4969%(X100)
2364 06:53:51.238923
2365 06:53:51.238986 ==DQ 1 ==
2366 06:53:51.242140 Final DQ duty delay cell = 0
2367 06:53:51.245159 [0] MAX Duty = 5031%(X100), DQS PI = 18
2368 06:53:51.248964 [0] MIN Duty = 4907%(X100), DQS PI = 46
2369 06:53:51.249045 [0] AVG Duty = 4969%(X100)
2370 06:53:51.252295
2371 06:53:51.255551 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2372 06:53:51.255630
2373 06:53:51.258589 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2374 06:53:51.262047 [DutyScan_Calibration_Flow] ====Done====
2375 06:53:51.262131 ==
2376 06:53:51.265661 Dram Type= 6, Freq= 0, CH_1, rank 0
2377 06:53:51.268656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2378 06:53:51.268737 ==
2379 06:53:51.271932 [Duty_Offset_Calibration]
2380 06:53:51.272013 B0:1 B1:1 CA:2
2381 06:53:51.272113
2382 06:53:51.275284 [DutyScan_Calibration_Flow] k_type=0
2383 06:53:51.285724
2384 06:53:51.285804 ==CLK 0==
2385 06:53:51.288800 Final CLK duty delay cell = 0
2386 06:53:51.292219 [0] MAX Duty = 5156%(X100), DQS PI = 24
2387 06:53:51.295413 [0] MIN Duty = 4938%(X100), DQS PI = 48
2388 06:53:51.298782 [0] AVG Duty = 5047%(X100)
2389 06:53:51.298863
2390 06:53:51.302168 CH1 CLK Duty spec in!! Max-Min= 218%
2391 06:53:51.305596 [DutyScan_Calibration_Flow] ====Done====
2392 06:53:51.305677
2393 06:53:51.308936 [DutyScan_Calibration_Flow] k_type=1
2394 06:53:51.325276
2395 06:53:51.325393 ==DQS 0 ==
2396 06:53:51.328465 Final DQS duty delay cell = 0
2397 06:53:51.331821 [0] MAX Duty = 5031%(X100), DQS PI = 18
2398 06:53:51.334967 [0] MIN Duty = 4844%(X100), DQS PI = 48
2399 06:53:51.335046 [0] AVG Duty = 4937%(X100)
2400 06:53:51.338526
2401 06:53:51.338651 ==DQS 1 ==
2402 06:53:51.341667 Final DQS duty delay cell = 0
2403 06:53:51.345061 [0] MAX Duty = 5062%(X100), DQS PI = 36
2404 06:53:51.348320 [0] MIN Duty = 4907%(X100), DQS PI = 30
2405 06:53:51.348389 [0] AVG Duty = 4984%(X100)
2406 06:53:51.351417
2407 06:53:51.355357 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2408 06:53:51.355451
2409 06:53:51.358460 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2410 06:53:51.362087 [DutyScan_Calibration_Flow] ====Done====
2411 06:53:51.362173
2412 06:53:51.365031 [DutyScan_Calibration_Flow] k_type=3
2413 06:53:51.381368
2414 06:53:51.381463 ==DQM 0 ==
2415 06:53:51.384935 Final DQM duty delay cell = 0
2416 06:53:51.388243 [0] MAX Duty = 5093%(X100), DQS PI = 18
2417 06:53:51.391784 [0] MIN Duty = 4876%(X100), DQS PI = 48
2418 06:53:51.394858 [0] AVG Duty = 4984%(X100)
2419 06:53:51.394930
2420 06:53:51.394990 ==DQM 1 ==
2421 06:53:51.397962 Final DQM duty delay cell = 0
2422 06:53:51.401488 [0] MAX Duty = 5156%(X100), DQS PI = 62
2423 06:53:51.404704 [0] MIN Duty = 4938%(X100), DQS PI = 20
2424 06:53:51.408137 [0] AVG Duty = 5047%(X100)
2425 06:53:51.408217
2426 06:53:51.411451 CH1 DQM 0 Duty spec in!! Max-Min= 217%
2427 06:53:51.411547
2428 06:53:51.414728 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2429 06:53:51.418575 [DutyScan_Calibration_Flow] ====Done====
2430 06:53:51.418670
2431 06:53:51.421373 [DutyScan_Calibration_Flow] k_type=2
2432 06:53:51.438191
2433 06:53:51.438301 ==DQ 0 ==
2434 06:53:51.441194 Final DQ duty delay cell = 0
2435 06:53:51.444835 [0] MAX Duty = 5124%(X100), DQS PI = 18
2436 06:53:51.448543 [0] MIN Duty = 4938%(X100), DQS PI = 50
2437 06:53:51.448625 [0] AVG Duty = 5031%(X100)
2438 06:53:51.448688
2439 06:53:51.451487 ==DQ 1 ==
2440 06:53:51.455076 Final DQ duty delay cell = 0
2441 06:53:51.458159 [0] MAX Duty = 5093%(X100), DQS PI = 40
2442 06:53:51.461178 [0] MIN Duty = 5000%(X100), DQS PI = 2
2443 06:53:51.461269 [0] AVG Duty = 5046%(X100)
2444 06:53:51.461333
2445 06:53:51.464960 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2446 06:53:51.465042
2447 06:53:51.467984 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2448 06:53:51.474700 [DutyScan_Calibration_Flow] ====Done====
2449 06:53:51.477956 nWR fixed to 30
2450 06:53:51.478031 [ModeRegInit_LP4] CH0 RK0
2451 06:53:51.481752 [ModeRegInit_LP4] CH0 RK1
2452 06:53:51.484769 [ModeRegInit_LP4] CH1 RK0
2453 06:53:51.484851 [ModeRegInit_LP4] CH1 RK1
2454 06:53:51.488448 match AC timing 7
2455 06:53:51.491620 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2456 06:53:51.495219 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2457 06:53:51.502054 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2458 06:53:51.504957 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2459 06:53:51.511518 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2460 06:53:51.511618 ==
2461 06:53:51.514843 Dram Type= 6, Freq= 0, CH_0, rank 0
2462 06:53:51.518461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2463 06:53:51.518587 ==
2464 06:53:51.524730 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2465 06:53:51.528262 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2466 06:53:51.538218 [CA 0] Center 40 (10~71) winsize 62
2467 06:53:51.541598 [CA 1] Center 39 (9~70) winsize 62
2468 06:53:51.544815 [CA 2] Center 36 (6~67) winsize 62
2469 06:53:51.548307 [CA 3] Center 35 (5~66) winsize 62
2470 06:53:51.551435 [CA 4] Center 34 (4~65) winsize 62
2471 06:53:51.555271 [CA 5] Center 34 (4~64) winsize 61
2472 06:53:51.555381
2473 06:53:51.558075 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2474 06:53:51.558185
2475 06:53:51.561216 [CATrainingPosCal] consider 1 rank data
2476 06:53:51.565003 u2DelayCellTimex100 = 270/100 ps
2477 06:53:51.568146 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2478 06:53:51.571300 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2479 06:53:51.578056 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2480 06:53:51.581727 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2481 06:53:51.584857 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2482 06:53:51.588591 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2483 06:53:51.588672
2484 06:53:51.591609 CA PerBit enable=1, Macro0, CA PI delay=34
2485 06:53:51.591709
2486 06:53:51.594992 [CBTSetCACLKResult] CA Dly = 34
2487 06:53:51.595081 CS Dly: 7 (0~38)
2488 06:53:51.595173 ==
2489 06:53:51.598492 Dram Type= 6, Freq= 0, CH_0, rank 1
2490 06:53:51.605534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2491 06:53:51.605615 ==
2492 06:53:51.608546 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2493 06:53:51.615012 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2494 06:53:51.623985 [CA 0] Center 39 (9~70) winsize 62
2495 06:53:51.626997 [CA 1] Center 40 (10~70) winsize 61
2496 06:53:51.630824 [CA 2] Center 36 (6~67) winsize 62
2497 06:53:51.634089 [CA 3] Center 35 (5~66) winsize 62
2498 06:53:51.637026 [CA 4] Center 34 (4~65) winsize 62
2499 06:53:51.640991 [CA 5] Center 34 (4~64) winsize 61
2500 06:53:51.641068
2501 06:53:51.644122 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2502 06:53:51.644198
2503 06:53:51.647770 [CATrainingPosCal] consider 2 rank data
2504 06:53:51.651175 u2DelayCellTimex100 = 270/100 ps
2505 06:53:51.654011 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2506 06:53:51.657359 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2507 06:53:51.663911 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2508 06:53:51.667608 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2509 06:53:51.670688 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2510 06:53:51.674238 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2511 06:53:51.674313
2512 06:53:51.677475 CA PerBit enable=1, Macro0, CA PI delay=34
2513 06:53:51.677548
2514 06:53:51.680895 [CBTSetCACLKResult] CA Dly = 34
2515 06:53:51.680994 CS Dly: 8 (0~41)
2516 06:53:51.681093
2517 06:53:51.684556 ----->DramcWriteLeveling(PI) begin...
2518 06:53:51.687848 ==
2519 06:53:51.687934 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 06:53:51.693980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 06:53:51.694058 ==
2522 06:53:51.697758 Write leveling (Byte 0): 31 => 31
2523 06:53:51.701196 Write leveling (Byte 1): 29 => 29
2524 06:53:51.701306 DramcWriteLeveling(PI) end<-----
2525 06:53:51.704235
2526 06:53:51.704339 ==
2527 06:53:51.707873 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 06:53:51.710903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2529 06:53:51.711017 ==
2530 06:53:51.714403 [Gating] SW mode calibration
2531 06:53:51.721395 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2532 06:53:51.724361 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2533 06:53:51.731006 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 06:53:51.734097 0 15 4 | B1->B0 | 2524 3333 | 1 1 | (0 0) (1 1)
2535 06:53:51.737513 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2536 06:53:51.744311 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 06:53:51.747575 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 06:53:51.751106 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 06:53:51.757495 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 06:53:51.761274 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 06:53:51.764195 1 0 0 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
2542 06:53:51.770946 1 0 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (1 0)
2543 06:53:51.774343 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 06:53:51.778008 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 06:53:51.781316 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 06:53:51.787872 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 06:53:51.791233 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 06:53:51.794960 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 06:53:51.800959 1 1 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2550 06:53:51.804702 1 1 4 | B1->B0 | 3939 4444 | 0 0 | (0 0) (1 1)
2551 06:53:51.808328 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 06:53:51.814649 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 06:53:51.817811 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 06:53:51.821576 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 06:53:51.827822 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 06:53:51.831399 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 06:53:51.834600 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2558 06:53:51.838302 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2559 06:53:51.844959 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 06:53:51.848532 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 06:53:51.851343 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 06:53:51.857993 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 06:53:51.861549 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 06:53:51.864899 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 06:53:51.871463 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 06:53:51.875198 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 06:53:51.878362 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 06:53:51.885148 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 06:53:51.888614 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 06:53:51.891592 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 06:53:51.898293 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 06:53:51.901876 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 06:53:51.905143 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2574 06:53:51.908397 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2575 06:53:51.915438 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 06:53:51.918533 Total UI for P1: 0, mck2ui 16
2577 06:53:51.921995 best dqsien dly found for B0: ( 1, 4, 2)
2578 06:53:51.925563 Total UI for P1: 0, mck2ui 16
2579 06:53:51.928662 best dqsien dly found for B1: ( 1, 4, 2)
2580 06:53:51.932479 best DQS0 dly(MCK, UI, PI) = (1, 4, 2)
2581 06:53:51.935429 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2582 06:53:51.935506
2583 06:53:51.938995 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 2)
2584 06:53:51.942221 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2585 06:53:51.945840 [Gating] SW calibration Done
2586 06:53:51.945913 ==
2587 06:53:51.948693 Dram Type= 6, Freq= 0, CH_0, rank 0
2588 06:53:51.952415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2589 06:53:51.952500 ==
2590 06:53:51.955769 RX Vref Scan: 0
2591 06:53:51.955874
2592 06:53:51.955976 RX Vref 0 -> 0, step: 1
2593 06:53:51.956079
2594 06:53:51.958986 RX Delay -40 -> 252, step: 8
2595 06:53:51.962477 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2596 06:53:51.969129 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2597 06:53:51.972227 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2598 06:53:51.975789 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2599 06:53:51.979222 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2600 06:53:51.982590 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2601 06:53:51.985446 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2602 06:53:51.992263 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2603 06:53:51.995743 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2604 06:53:51.998752 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2605 06:53:52.002124 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2606 06:53:52.005828 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2607 06:53:52.012774 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2608 06:53:52.015670 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2609 06:53:52.019092 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2610 06:53:52.022835 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2611 06:53:52.022941 ==
2612 06:53:52.026316 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 06:53:52.029199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 06:53:52.032800 ==
2615 06:53:52.032881 DQS Delay:
2616 06:53:52.032945 DQS0 = 0, DQS1 = 0
2617 06:53:52.035886 DQM Delay:
2618 06:53:52.035966 DQM0 = 116, DQM1 = 107
2619 06:53:52.039024 DQ Delay:
2620 06:53:52.042606 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2621 06:53:52.046441 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2622 06:53:52.049102 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2623 06:53:52.052872 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2624 06:53:52.052953
2625 06:53:52.053015
2626 06:53:52.053073 ==
2627 06:53:52.055852 Dram Type= 6, Freq= 0, CH_0, rank 0
2628 06:53:52.059310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2629 06:53:52.059392 ==
2630 06:53:52.059455
2631 06:53:52.059513
2632 06:53:52.062728 TX Vref Scan disable
2633 06:53:52.066333 == TX Byte 0 ==
2634 06:53:52.069373 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2635 06:53:52.073081 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2636 06:53:52.075850 == TX Byte 1 ==
2637 06:53:52.079626 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2638 06:53:52.082943 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2639 06:53:52.083014 ==
2640 06:53:52.085837 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 06:53:52.089381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 06:53:52.089464 ==
2643 06:53:52.102769 TX Vref=22, minBit 5, minWin=24, winSum=416
2644 06:53:52.105916 TX Vref=24, minBit 7, minWin=24, winSum=424
2645 06:53:52.109720 TX Vref=26, minBit 1, minWin=26, winSum=429
2646 06:53:52.112613 TX Vref=28, minBit 3, minWin=26, winSum=436
2647 06:53:52.116407 TX Vref=30, minBit 1, minWin=26, winSum=435
2648 06:53:52.119353 TX Vref=32, minBit 1, minWin=26, winSum=434
2649 06:53:52.126358 [TxChooseVref] Worse bit 3, Min win 26, Win sum 436, Final Vref 28
2650 06:53:52.126435
2651 06:53:52.129373 Final TX Range 1 Vref 28
2652 06:53:52.129448
2653 06:53:52.129509 ==
2654 06:53:52.132836 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 06:53:52.136302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 06:53:52.136388 ==
2657 06:53:52.136471
2658 06:53:52.136547
2659 06:53:52.139526 TX Vref Scan disable
2660 06:53:52.143055 == TX Byte 0 ==
2661 06:53:52.146118 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2662 06:53:52.149849 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2663 06:53:52.152896 == TX Byte 1 ==
2664 06:53:52.156102 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2665 06:53:52.159712 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2666 06:53:52.159788
2667 06:53:52.162657 [DATLAT]
2668 06:53:52.162730 Freq=1200, CH0 RK0
2669 06:53:52.162810
2670 06:53:52.166110 DATLAT Default: 0xd
2671 06:53:52.166189 0, 0xFFFF, sum = 0
2672 06:53:52.169429 1, 0xFFFF, sum = 0
2673 06:53:52.169510 2, 0xFFFF, sum = 0
2674 06:53:52.172713 3, 0xFFFF, sum = 0
2675 06:53:52.172813 4, 0xFFFF, sum = 0
2676 06:53:52.176325 5, 0xFFFF, sum = 0
2677 06:53:52.176409 6, 0xFFFF, sum = 0
2678 06:53:52.179897 7, 0xFFFF, sum = 0
2679 06:53:52.179971 8, 0xFFFF, sum = 0
2680 06:53:52.182880 9, 0xFFFF, sum = 0
2681 06:53:52.182953 10, 0xFFFF, sum = 0
2682 06:53:52.186510 11, 0xFFFF, sum = 0
2683 06:53:52.186583 12, 0x0, sum = 1
2684 06:53:52.189997 13, 0x0, sum = 2
2685 06:53:52.190075 14, 0x0, sum = 3
2686 06:53:52.192887 15, 0x0, sum = 4
2687 06:53:52.192961 best_step = 13
2688 06:53:52.193038
2689 06:53:52.193134 ==
2690 06:53:52.196444 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 06:53:52.203229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 06:53:52.203305 ==
2693 06:53:52.203383 RX Vref Scan: 1
2694 06:53:52.203462
2695 06:53:52.206736 Set Vref Range= 32 -> 127
2696 06:53:52.206813
2697 06:53:52.209690 RX Vref 32 -> 127, step: 1
2698 06:53:52.209764
2699 06:53:52.209840 RX Delay -21 -> 252, step: 4
2700 06:53:52.209916
2701 06:53:52.213296 Set Vref, RX VrefLevel [Byte0]: 32
2702 06:53:52.216708 [Byte1]: 32
2703 06:53:52.220694
2704 06:53:52.220767 Set Vref, RX VrefLevel [Byte0]: 33
2705 06:53:52.224538 [Byte1]: 33
2706 06:53:52.228909
2707 06:53:52.228987 Set Vref, RX VrefLevel [Byte0]: 34
2708 06:53:52.232397 [Byte1]: 34
2709 06:53:52.236922
2710 06:53:52.236997 Set Vref, RX VrefLevel [Byte0]: 35
2711 06:53:52.240382 [Byte1]: 35
2712 06:53:52.244601
2713 06:53:52.244675 Set Vref, RX VrefLevel [Byte0]: 36
2714 06:53:52.248095 [Byte1]: 36
2715 06:53:52.252556
2716 06:53:52.252649 Set Vref, RX VrefLevel [Byte0]: 37
2717 06:53:52.256096 [Byte1]: 37
2718 06:53:52.260822
2719 06:53:52.260896 Set Vref, RX VrefLevel [Byte0]: 38
2720 06:53:52.264023 [Byte1]: 38
2721 06:53:52.268208
2722 06:53:52.268289 Set Vref, RX VrefLevel [Byte0]: 39
2723 06:53:52.271808 [Byte1]: 39
2724 06:53:52.276321
2725 06:53:52.276402 Set Vref, RX VrefLevel [Byte0]: 40
2726 06:53:52.279683 [Byte1]: 40
2727 06:53:52.284318
2728 06:53:52.284398 Set Vref, RX VrefLevel [Byte0]: 41
2729 06:53:52.287752 [Byte1]: 41
2730 06:53:52.292294
2731 06:53:52.292374 Set Vref, RX VrefLevel [Byte0]: 42
2732 06:53:52.295797 [Byte1]: 42
2733 06:53:52.300254
2734 06:53:52.300334 Set Vref, RX VrefLevel [Byte0]: 43
2735 06:53:52.303378 [Byte1]: 43
2736 06:53:52.308369
2737 06:53:52.308449 Set Vref, RX VrefLevel [Byte0]: 44
2738 06:53:52.311502 [Byte1]: 44
2739 06:53:52.316080
2740 06:53:52.316160 Set Vref, RX VrefLevel [Byte0]: 45
2741 06:53:52.319614 [Byte1]: 45
2742 06:53:52.324033
2743 06:53:52.324118 Set Vref, RX VrefLevel [Byte0]: 46
2744 06:53:52.327482 [Byte1]: 46
2745 06:53:52.331853
2746 06:53:52.331934 Set Vref, RX VrefLevel [Byte0]: 47
2747 06:53:52.335228 [Byte1]: 47
2748 06:53:52.339558
2749 06:53:52.339638 Set Vref, RX VrefLevel [Byte0]: 48
2750 06:53:52.343049 [Byte1]: 48
2751 06:53:52.347956
2752 06:53:52.348043 Set Vref, RX VrefLevel [Byte0]: 49
2753 06:53:52.350828 [Byte1]: 49
2754 06:53:52.355845
2755 06:53:52.355925 Set Vref, RX VrefLevel [Byte0]: 50
2756 06:53:52.358700 [Byte1]: 50
2757 06:53:52.363540
2758 06:53:52.363620 Set Vref, RX VrefLevel [Byte0]: 51
2759 06:53:52.367136 [Byte1]: 51
2760 06:53:52.371733
2761 06:53:52.371831 Set Vref, RX VrefLevel [Byte0]: 52
2762 06:53:52.374590 [Byte1]: 52
2763 06:53:52.379666
2764 06:53:52.379738 Set Vref, RX VrefLevel [Byte0]: 53
2765 06:53:52.382670 [Byte1]: 53
2766 06:53:52.387464
2767 06:53:52.387533 Set Vref, RX VrefLevel [Byte0]: 54
2768 06:53:52.390720 [Byte1]: 54
2769 06:53:52.395350
2770 06:53:52.395423 Set Vref, RX VrefLevel [Byte0]: 55
2771 06:53:52.398854 [Byte1]: 55
2772 06:53:52.403083
2773 06:53:52.403179 Set Vref, RX VrefLevel [Byte0]: 56
2774 06:53:52.406695 [Byte1]: 56
2775 06:53:52.411439
2776 06:53:52.411511 Set Vref, RX VrefLevel [Byte0]: 57
2777 06:53:52.414601 [Byte1]: 57
2778 06:53:52.419030
2779 06:53:52.419099 Set Vref, RX VrefLevel [Byte0]: 58
2780 06:53:52.422600 [Byte1]: 58
2781 06:53:52.426843
2782 06:53:52.426912 Set Vref, RX VrefLevel [Byte0]: 59
2783 06:53:52.430498 [Byte1]: 59
2784 06:53:52.434677
2785 06:53:52.434748 Set Vref, RX VrefLevel [Byte0]: 60
2786 06:53:52.438182 [Byte1]: 60
2787 06:53:52.442882
2788 06:53:52.442983 Set Vref, RX VrefLevel [Byte0]: 61
2789 06:53:52.446151 [Byte1]: 61
2790 06:53:52.450732
2791 06:53:52.450804 Set Vref, RX VrefLevel [Byte0]: 62
2792 06:53:52.454005 [Byte1]: 62
2793 06:53:52.458951
2794 06:53:52.459026 Set Vref, RX VrefLevel [Byte0]: 63
2795 06:53:52.461873 [Byte1]: 63
2796 06:53:52.466686
2797 06:53:52.466769 Set Vref, RX VrefLevel [Byte0]: 64
2798 06:53:52.469892 [Byte1]: 64
2799 06:53:52.474752
2800 06:53:52.474826 Set Vref, RX VrefLevel [Byte0]: 65
2801 06:53:52.477936 [Byte1]: 65
2802 06:53:52.482604
2803 06:53:52.482722 Set Vref, RX VrefLevel [Byte0]: 66
2804 06:53:52.485644 [Byte1]: 66
2805 06:53:52.490438
2806 06:53:52.490508 Set Vref, RX VrefLevel [Byte0]: 67
2807 06:53:52.493481 [Byte1]: 67
2808 06:53:52.498523
2809 06:53:52.498621 Set Vref, RX VrefLevel [Byte0]: 68
2810 06:53:52.502076 [Byte1]: 68
2811 06:53:52.506153
2812 06:53:52.506233 Final RX Vref Byte 0 = 54 to rank0
2813 06:53:52.509653 Final RX Vref Byte 1 = 51 to rank0
2814 06:53:52.513018 Final RX Vref Byte 0 = 54 to rank1
2815 06:53:52.516326 Final RX Vref Byte 1 = 51 to rank1==
2816 06:53:52.519805 Dram Type= 6, Freq= 0, CH_0, rank 0
2817 06:53:52.522761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2818 06:53:52.526268 ==
2819 06:53:52.526375 DQS Delay:
2820 06:53:52.526466 DQS0 = 0, DQS1 = 0
2821 06:53:52.530173 DQM Delay:
2822 06:53:52.530253 DQM0 = 115, DQM1 = 104
2823 06:53:52.533017 DQ Delay:
2824 06:53:52.536650 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
2825 06:53:52.539895 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2826 06:53:52.543068 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2827 06:53:52.546727 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =112
2828 06:53:52.546824
2829 06:53:52.546922
2830 06:53:52.553322 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcec, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 411 ps
2831 06:53:52.557045 CH0 RK0: MR19=303, MR18=FCEC
2832 06:53:52.563439 CH0_RK0: MR19=0x303, MR18=0xFCEC, DQSOSC=411, MR23=63, INC=38, DEC=25
2833 06:53:52.563520
2834 06:53:52.566653 ----->DramcWriteLeveling(PI) begin...
2835 06:53:52.566735 ==
2836 06:53:52.569991 Dram Type= 6, Freq= 0, CH_0, rank 1
2837 06:53:52.573092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2838 06:53:52.573172 ==
2839 06:53:52.576631 Write leveling (Byte 0): 33 => 33
2840 06:53:52.580405 Write leveling (Byte 1): 27 => 27
2841 06:53:52.583207 DramcWriteLeveling(PI) end<-----
2842 06:53:52.583280
2843 06:53:52.583341 ==
2844 06:53:52.586493 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 06:53:52.590089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 06:53:52.590170 ==
2847 06:53:52.593553 [Gating] SW mode calibration
2848 06:53:52.600103 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2849 06:53:52.606834 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2850 06:53:52.610284 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2851 06:53:52.617082 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2852 06:53:52.619997 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 06:53:52.623649 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 06:53:52.629937 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 06:53:52.633933 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 06:53:52.636989 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2857 06:53:52.640483 0 15 28 | B1->B0 | 3434 2424 | 1 1 | (1 1) (1 0)
2858 06:53:52.646856 1 0 0 | B1->B0 | 2f2f 2828 | 1 1 | (1 0) (1 0)
2859 06:53:52.650328 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 06:53:52.653939 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 06:53:52.660677 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 06:53:52.663669 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 06:53:52.666939 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 06:53:52.673773 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2865 06:53:52.677116 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2866 06:53:52.680474 1 1 0 | B1->B0 | 2d2c 3d3d | 1 1 | (0 0) (0 0)
2867 06:53:52.687079 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2868 06:53:52.690234 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 06:53:52.693785 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 06:53:52.700589 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 06:53:52.703685 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 06:53:52.707240 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 06:53:52.710601 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2874 06:53:52.717178 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2875 06:53:52.720788 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 06:53:52.723850 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 06:53:52.730572 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 06:53:52.733917 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 06:53:52.737194 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 06:53:52.744123 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 06:53:52.747633 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 06:53:52.750727 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 06:53:52.757812 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 06:53:52.761213 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 06:53:52.764521 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 06:53:52.767385 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 06:53:52.774143 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 06:53:52.777986 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2889 06:53:52.780780 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2890 06:53:52.787597 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2891 06:53:52.790821 Total UI for P1: 0, mck2ui 16
2892 06:53:52.794285 best dqsien dly found for B0: ( 1, 3, 26)
2893 06:53:52.797381 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2894 06:53:52.801129 Total UI for P1: 0, mck2ui 16
2895 06:53:52.804063 best dqsien dly found for B1: ( 1, 4, 0)
2896 06:53:52.807302 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2897 06:53:52.810813 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2898 06:53:52.810913
2899 06:53:52.814474 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2900 06:53:52.817805 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2901 06:53:52.820744 [Gating] SW calibration Done
2902 06:53:52.820845 ==
2903 06:53:52.824180 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 06:53:52.827841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2905 06:53:52.830763 ==
2906 06:53:52.830838 RX Vref Scan: 0
2907 06:53:52.830900
2908 06:53:52.833997 RX Vref 0 -> 0, step: 1
2909 06:53:52.834076
2910 06:53:52.834138 RX Delay -40 -> 252, step: 8
2911 06:53:52.840853 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2912 06:53:52.844454 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2913 06:53:52.847914 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2914 06:53:52.850967 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2915 06:53:52.854703 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2916 06:53:52.861403 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2917 06:53:52.864912 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2918 06:53:52.867868 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2919 06:53:52.871306 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2920 06:53:52.874450 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2921 06:53:52.878028 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2922 06:53:52.884861 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2923 06:53:52.887879 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2924 06:53:52.891460 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2925 06:53:52.895157 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2926 06:53:52.897786 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2927 06:53:52.901658 ==
2928 06:53:52.904936 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 06:53:52.907844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 06:53:52.907928 ==
2931 06:53:52.907987 DQS Delay:
2932 06:53:52.911549 DQS0 = 0, DQS1 = 0
2933 06:53:52.911616 DQM Delay:
2934 06:53:52.914683 DQM0 = 115, DQM1 = 106
2935 06:53:52.914750 DQ Delay:
2936 06:53:52.918084 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2937 06:53:52.921894 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2938 06:53:52.924698 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2939 06:53:52.928426 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2940 06:53:52.928504
2941 06:53:52.928569
2942 06:53:52.928628 ==
2943 06:53:52.931381 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 06:53:52.938404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 06:53:52.938480 ==
2946 06:53:52.938540
2947 06:53:52.938596
2948 06:53:52.938654 TX Vref Scan disable
2949 06:53:52.941339 == TX Byte 0 ==
2950 06:53:52.944769 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2951 06:53:52.947923 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2952 06:53:52.951392 == TX Byte 1 ==
2953 06:53:52.954959 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2954 06:53:52.958012 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2955 06:53:52.961973 ==
2956 06:53:52.964998 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 06:53:52.967967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 06:53:52.968043 ==
2959 06:53:52.979850 TX Vref=22, minBit 0, minWin=25, winSum=421
2960 06:53:52.983453 TX Vref=24, minBit 0, minWin=25, winSum=422
2961 06:53:52.986429 TX Vref=26, minBit 0, minWin=26, winSum=432
2962 06:53:52.990090 TX Vref=28, minBit 2, minWin=26, winSum=437
2963 06:53:52.993173 TX Vref=30, minBit 2, minWin=26, winSum=431
2964 06:53:52.996278 TX Vref=32, minBit 2, minWin=26, winSum=435
2965 06:53:53.002991 [TxChooseVref] Worse bit 2, Min win 26, Win sum 437, Final Vref 28
2966 06:53:53.003071
2967 06:53:53.006335 Final TX Range 1 Vref 28
2968 06:53:53.006410
2969 06:53:53.006488 ==
2970 06:53:53.010001 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 06:53:53.013073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 06:53:53.013148 ==
2973 06:53:53.013280
2974 06:53:53.013358
2975 06:53:53.016578 TX Vref Scan disable
2976 06:53:53.019900 == TX Byte 0 ==
2977 06:53:53.023421 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2978 06:53:53.026595 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2979 06:53:53.030142 == TX Byte 1 ==
2980 06:53:53.032993 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2981 06:53:53.036520 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2982 06:53:53.036591
2983 06:53:53.039671 [DATLAT]
2984 06:53:53.039741 Freq=1200, CH0 RK1
2985 06:53:53.039824
2986 06:53:53.043452 DATLAT Default: 0xd
2987 06:53:53.043524 0, 0xFFFF, sum = 0
2988 06:53:53.046651 1, 0xFFFF, sum = 0
2989 06:53:53.046724 2, 0xFFFF, sum = 0
2990 06:53:53.050109 3, 0xFFFF, sum = 0
2991 06:53:53.050215 4, 0xFFFF, sum = 0
2992 06:53:53.053511 5, 0xFFFF, sum = 0
2993 06:53:53.053614 6, 0xFFFF, sum = 0
2994 06:53:53.056447 7, 0xFFFF, sum = 0
2995 06:53:53.056545 8, 0xFFFF, sum = 0
2996 06:53:53.060211 9, 0xFFFF, sum = 0
2997 06:53:53.060286 10, 0xFFFF, sum = 0
2998 06:53:53.063527 11, 0xFFFF, sum = 0
2999 06:53:53.063602 12, 0x0, sum = 1
3000 06:53:53.066677 13, 0x0, sum = 2
3001 06:53:53.066779 14, 0x0, sum = 3
3002 06:53:53.069766 15, 0x0, sum = 4
3003 06:53:53.069849 best_step = 13
3004 06:53:53.069929
3005 06:53:53.070010 ==
3006 06:53:53.073468 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 06:53:53.080224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 06:53:53.080299 ==
3009 06:53:53.080379 RX Vref Scan: 0
3010 06:53:53.080453
3011 06:53:53.083659 RX Vref 0 -> 0, step: 1
3012 06:53:53.083758
3013 06:53:53.087111 RX Delay -21 -> 252, step: 4
3014 06:53:53.090132 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3015 06:53:53.093632 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3016 06:53:53.099954 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3017 06:53:53.103577 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3018 06:53:53.106807 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3019 06:53:53.110376 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3020 06:53:53.113667 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3021 06:53:53.116980 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3022 06:53:53.123678 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3023 06:53:53.126853 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3024 06:53:53.130381 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3025 06:53:53.133395 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3026 06:53:53.137021 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3027 06:53:53.143504 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3028 06:53:53.147026 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3029 06:53:53.150351 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3030 06:53:53.150424 ==
3031 06:53:53.153786 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 06:53:53.156811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 06:53:53.156926 ==
3034 06:53:53.160023 DQS Delay:
3035 06:53:53.160121 DQS0 = 0, DQS1 = 0
3036 06:53:53.163658 DQM Delay:
3037 06:53:53.163733 DQM0 = 114, DQM1 = 104
3038 06:53:53.163813 DQ Delay:
3039 06:53:53.170583 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3040 06:53:53.173553 DQ4 =114, DQ5 =104, DQ6 =122, DQ7 =122
3041 06:53:53.177268 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3042 06:53:53.180337 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3043 06:53:53.180433
3044 06:53:53.180532
3045 06:53:53.186965 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3046 06:53:53.190725 CH0 RK1: MR19=403, MR18=2F4
3047 06:53:53.197195 CH0_RK1: MR19=0x403, MR18=0x2F4, DQSOSC=409, MR23=63, INC=39, DEC=26
3048 06:53:53.200255 [RxdqsGatingPostProcess] freq 1200
3049 06:53:53.203913 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3050 06:53:53.207269 best DQS0 dly(2T, 0.5T) = (0, 12)
3051 06:53:53.210874 best DQS1 dly(2T, 0.5T) = (0, 12)
3052 06:53:53.214000 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3053 06:53:53.217664 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3054 06:53:53.220693 best DQS0 dly(2T, 0.5T) = (0, 11)
3055 06:53:53.224214 best DQS1 dly(2T, 0.5T) = (0, 12)
3056 06:53:53.227662 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3057 06:53:53.230886 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3058 06:53:53.234320 Pre-setting of DQS Precalculation
3059 06:53:53.236917 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3060 06:53:53.237016 ==
3061 06:53:53.240580 Dram Type= 6, Freq= 0, CH_1, rank 0
3062 06:53:53.243664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 06:53:53.247356 ==
3064 06:53:53.250465 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3065 06:53:53.257447 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3066 06:53:53.265090 [CA 0] Center 38 (9~68) winsize 60
3067 06:53:53.268593 [CA 1] Center 38 (8~68) winsize 61
3068 06:53:53.272195 [CA 2] Center 35 (5~65) winsize 61
3069 06:53:53.275027 [CA 3] Center 34 (4~65) winsize 62
3070 06:53:53.278765 [CA 4] Center 34 (4~65) winsize 62
3071 06:53:53.281952 [CA 5] Center 34 (4~64) winsize 61
3072 06:53:53.282022
3073 06:53:53.285068 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3074 06:53:53.285141
3075 06:53:53.288716 [CATrainingPosCal] consider 1 rank data
3076 06:53:53.292456 u2DelayCellTimex100 = 270/100 ps
3077 06:53:53.295498 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3078 06:53:53.299082 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3079 06:53:53.301822 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3080 06:53:53.309114 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3081 06:53:53.312030 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3082 06:53:53.315265 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3083 06:53:53.315346
3084 06:53:53.318875 CA PerBit enable=1, Macro0, CA PI delay=34
3085 06:53:53.318948
3086 06:53:53.322007 [CBTSetCACLKResult] CA Dly = 34
3087 06:53:53.322105 CS Dly: 6 (0~37)
3088 06:53:53.322201 ==
3089 06:53:53.325293 Dram Type= 6, Freq= 0, CH_1, rank 1
3090 06:53:53.331975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3091 06:53:53.332084 ==
3092 06:53:53.335411 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3093 06:53:53.342206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3094 06:53:53.350694 [CA 0] Center 38 (8~68) winsize 61
3095 06:53:53.354268 [CA 1] Center 38 (9~68) winsize 60
3096 06:53:53.357462 [CA 2] Center 34 (4~65) winsize 62
3097 06:53:53.360999 [CA 3] Center 34 (3~65) winsize 63
3098 06:53:53.364487 [CA 4] Center 34 (4~65) winsize 62
3099 06:53:53.367323 [CA 5] Center 33 (3~64) winsize 62
3100 06:53:53.367395
3101 06:53:53.371355 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3102 06:53:53.371432
3103 06:53:53.374084 [CATrainingPosCal] consider 2 rank data
3104 06:53:53.377913 u2DelayCellTimex100 = 270/100 ps
3105 06:53:53.380653 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3106 06:53:53.384445 CA1 delay=38 (9~68),Diff = 4 PI (19 cell)
3107 06:53:53.388195 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3108 06:53:53.394913 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3109 06:53:53.397930 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3110 06:53:53.400891 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3111 06:53:53.400958
3112 06:53:53.404357 CA PerBit enable=1, Macro0, CA PI delay=34
3113 06:53:53.404450
3114 06:53:53.408033 [CBTSetCACLKResult] CA Dly = 34
3115 06:53:53.408103 CS Dly: 7 (0~40)
3116 06:53:53.408165
3117 06:53:53.411114 ----->DramcWriteLeveling(PI) begin...
3118 06:53:53.411190 ==
3119 06:53:53.414842 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 06:53:53.421489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 06:53:53.421559 ==
3122 06:53:53.424981 Write leveling (Byte 0): 25 => 25
3123 06:53:53.425074 Write leveling (Byte 1): 30 => 30
3124 06:53:53.427906 DramcWriteLeveling(PI) end<-----
3125 06:53:53.427974
3126 06:53:53.428034 ==
3127 06:53:53.431547 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 06:53:53.438274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 06:53:53.438349 ==
3130 06:53:53.441363 [Gating] SW mode calibration
3131 06:53:53.448805 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3132 06:53:53.451488 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3133 06:53:53.458503 0 15 0 | B1->B0 | 2929 2424 | 0 1 | (0 0) (0 0)
3134 06:53:53.461422 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 06:53:53.464983 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 06:53:53.471506 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 06:53:53.474753 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 06:53:53.478293 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 06:53:53.481485 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 06:53:53.488505 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3141 06:53:53.491981 1 0 0 | B1->B0 | 2424 2828 | 0 0 | (1 0) (1 0)
3142 06:53:53.495100 1 0 4 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
3143 06:53:53.501972 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 06:53:53.505549 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 06:53:53.508376 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 06:53:53.515602 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 06:53:53.518474 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 06:53:53.522210 1 0 28 | B1->B0 | 2e2e 2a2a | 0 0 | (0 0) (0 0)
3149 06:53:53.528773 1 1 0 | B1->B0 | 4343 3636 | 0 0 | (0 0) (0 0)
3150 06:53:53.532159 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 06:53:53.535380 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 06:53:53.538828 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 06:53:53.545476 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 06:53:53.548648 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 06:53:53.551803 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 06:53:53.558420 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 06:53:53.561776 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3158 06:53:53.565167 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 06:53:53.571891 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 06:53:53.575380 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 06:53:53.578508 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 06:53:53.585672 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 06:53:53.588617 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 06:53:53.592117 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 06:53:53.598972 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 06:53:53.602347 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 06:53:53.605358 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 06:53:53.609074 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 06:53:53.615849 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 06:53:53.619162 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 06:53:53.622310 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 06:53:53.629201 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3173 06:53:53.632300 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 06:53:53.635763 Total UI for P1: 0, mck2ui 16
3175 06:53:53.639216 best dqsien dly found for B0: ( 1, 3, 28)
3176 06:53:53.642309 Total UI for P1: 0, mck2ui 16
3177 06:53:53.645886 best dqsien dly found for B1: ( 1, 3, 30)
3178 06:53:53.649397 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3179 06:53:53.652573 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3180 06:53:53.652645
3181 06:53:53.656082 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3182 06:53:53.659121 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3183 06:53:53.662608 [Gating] SW calibration Done
3184 06:53:53.662679 ==
3185 06:53:53.665826 Dram Type= 6, Freq= 0, CH_1, rank 0
3186 06:53:53.669228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3187 06:53:53.669329 ==
3188 06:53:53.672731 RX Vref Scan: 0
3189 06:53:53.672808
3190 06:53:53.676212 RX Vref 0 -> 0, step: 1
3191 06:53:53.676308
3192 06:53:53.676395 RX Delay -40 -> 252, step: 8
3193 06:53:53.682770 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3194 06:53:53.685820 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3195 06:53:53.689366 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3196 06:53:53.692548 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3197 06:53:53.696102 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3198 06:53:53.702494 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3199 06:53:53.705864 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3200 06:53:53.709229 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3201 06:53:53.713066 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3202 06:53:53.716044 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3203 06:53:53.719593 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3204 06:53:53.726206 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3205 06:53:53.729355 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3206 06:53:53.733104 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3207 06:53:53.736109 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3208 06:53:53.742563 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3209 06:53:53.742637 ==
3210 06:53:53.746120 Dram Type= 6, Freq= 0, CH_1, rank 0
3211 06:53:53.749577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3212 06:53:53.749646 ==
3213 06:53:53.749705 DQS Delay:
3214 06:53:53.752704 DQS0 = 0, DQS1 = 0
3215 06:53:53.752772 DQM Delay:
3216 06:53:53.756332 DQM0 = 116, DQM1 = 109
3217 06:53:53.756402 DQ Delay:
3218 06:53:53.759424 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3219 06:53:53.763252 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3220 06:53:53.766122 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3221 06:53:53.769844 DQ12 =119, DQ13 =115, DQ14 =115, DQ15 =115
3222 06:53:53.769926
3223 06:53:53.769990
3224 06:53:53.770048 ==
3225 06:53:53.773053 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 06:53:53.779424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 06:53:53.779509 ==
3228 06:53:53.779574
3229 06:53:53.779633
3230 06:53:53.779689 TX Vref Scan disable
3231 06:53:53.783049 == TX Byte 0 ==
3232 06:53:53.786243 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3233 06:53:53.789750 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3234 06:53:53.793342 == TX Byte 1 ==
3235 06:53:53.796502 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3236 06:53:53.800031 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3237 06:53:53.803280 ==
3238 06:53:53.806496 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 06:53:53.809947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 06:53:53.810019 ==
3241 06:53:53.821371 TX Vref=22, minBit 1, minWin=25, winSum=410
3242 06:53:53.824347 TX Vref=24, minBit 3, minWin=25, winSum=414
3243 06:53:53.827867 TX Vref=26, minBit 13, minWin=25, winSum=422
3244 06:53:53.831665 TX Vref=28, minBit 1, minWin=25, winSum=423
3245 06:53:53.834417 TX Vref=30, minBit 1, minWin=26, winSum=427
3246 06:53:53.837995 TX Vref=32, minBit 13, minWin=25, winSum=426
3247 06:53:53.844728 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 30
3248 06:53:53.844808
3249 06:53:53.848461 Final TX Range 1 Vref 30
3250 06:53:53.848541
3251 06:53:53.848601 ==
3252 06:53:53.851302 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 06:53:53.854653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 06:53:53.854749 ==
3255 06:53:53.854840
3256 06:53:53.858193
3257 06:53:53.858268 TX Vref Scan disable
3258 06:53:53.861156 == TX Byte 0 ==
3259 06:53:53.865154 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3260 06:53:53.868550 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3261 06:53:53.871545 == TX Byte 1 ==
3262 06:53:53.874649 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3263 06:53:53.878410 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3264 06:53:53.878488
3265 06:53:53.881823 [DATLAT]
3266 06:53:53.881905 Freq=1200, CH1 RK0
3267 06:53:53.881970
3268 06:53:53.885128 DATLAT Default: 0xd
3269 06:53:53.885281 0, 0xFFFF, sum = 0
3270 06:53:53.888176 1, 0xFFFF, sum = 0
3271 06:53:53.888279 2, 0xFFFF, sum = 0
3272 06:53:53.892014 3, 0xFFFF, sum = 0
3273 06:53:53.892118 4, 0xFFFF, sum = 0
3274 06:53:53.894858 5, 0xFFFF, sum = 0
3275 06:53:53.894960 6, 0xFFFF, sum = 0
3276 06:53:53.898709 7, 0xFFFF, sum = 0
3277 06:53:53.898832 8, 0xFFFF, sum = 0
3278 06:53:53.902256 9, 0xFFFF, sum = 0
3279 06:53:53.902360 10, 0xFFFF, sum = 0
3280 06:53:53.905036 11, 0xFFFF, sum = 0
3281 06:53:53.905133 12, 0x0, sum = 1
3282 06:53:53.908325 13, 0x0, sum = 2
3283 06:53:53.908402 14, 0x0, sum = 3
3284 06:53:53.911854 15, 0x0, sum = 4
3285 06:53:53.911954 best_step = 13
3286 06:53:53.912042
3287 06:53:53.912126 ==
3288 06:53:53.915001 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 06:53:53.922033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 06:53:53.922136 ==
3291 06:53:53.922229 RX Vref Scan: 1
3292 06:53:53.922317
3293 06:53:53.925182 Set Vref Range= 32 -> 127
3294 06:53:53.925301
3295 06:53:53.928428 RX Vref 32 -> 127, step: 1
3296 06:53:53.928502
3297 06:53:53.928570 RX Delay -21 -> 252, step: 4
3298 06:53:53.928629
3299 06:53:53.931965 Set Vref, RX VrefLevel [Byte0]: 32
3300 06:53:53.935168 [Byte1]: 32
3301 06:53:53.940138
3302 06:53:53.940210 Set Vref, RX VrefLevel [Byte0]: 33
3303 06:53:53.943088 [Byte1]: 33
3304 06:53:53.948128
3305 06:53:53.948197 Set Vref, RX VrefLevel [Byte0]: 34
3306 06:53:53.951043 [Byte1]: 34
3307 06:53:53.955713
3308 06:53:53.955784 Set Vref, RX VrefLevel [Byte0]: 35
3309 06:53:53.959228 [Byte1]: 35
3310 06:53:53.963293
3311 06:53:53.963371 Set Vref, RX VrefLevel [Byte0]: 36
3312 06:53:53.966823 [Byte1]: 36
3313 06:53:53.971257
3314 06:53:53.971359 Set Vref, RX VrefLevel [Byte0]: 37
3315 06:53:53.974652 [Byte1]: 37
3316 06:53:53.979516
3317 06:53:53.979608 Set Vref, RX VrefLevel [Byte0]: 38
3318 06:53:53.982441 [Byte1]: 38
3319 06:53:53.987262
3320 06:53:53.987335 Set Vref, RX VrefLevel [Byte0]: 39
3321 06:53:53.990722 [Byte1]: 39
3322 06:53:53.995177
3323 06:53:53.995257 Set Vref, RX VrefLevel [Byte0]: 40
3324 06:53:53.998599 [Byte1]: 40
3325 06:53:54.003141
3326 06:53:54.003247 Set Vref, RX VrefLevel [Byte0]: 41
3327 06:53:54.006393 [Byte1]: 41
3328 06:53:54.011051
3329 06:53:54.011241 Set Vref, RX VrefLevel [Byte0]: 42
3330 06:53:54.014106 [Byte1]: 42
3331 06:53:54.018862
3332 06:53:54.018959 Set Vref, RX VrefLevel [Byte0]: 43
3333 06:53:54.022318 [Byte1]: 43
3334 06:53:54.026500
3335 06:53:54.026580 Set Vref, RX VrefLevel [Byte0]: 44
3336 06:53:54.030183 [Byte1]: 44
3337 06:53:54.034614
3338 06:53:54.034694 Set Vref, RX VrefLevel [Byte0]: 45
3339 06:53:54.038055 [Byte1]: 45
3340 06:53:54.042561
3341 06:53:54.042632 Set Vref, RX VrefLevel [Byte0]: 46
3342 06:53:54.045669 [Byte1]: 46
3343 06:53:54.050673
3344 06:53:54.050768 Set Vref, RX VrefLevel [Byte0]: 47
3345 06:53:54.054161 [Byte1]: 47
3346 06:53:54.058332
3347 06:53:54.058401 Set Vref, RX VrefLevel [Byte0]: 48
3348 06:53:54.062149 [Byte1]: 48
3349 06:53:54.066742
3350 06:53:54.066905 Set Vref, RX VrefLevel [Byte0]: 49
3351 06:53:54.069590 [Byte1]: 49
3352 06:53:54.074431
3353 06:53:54.074544 Set Vref, RX VrefLevel [Byte0]: 50
3354 06:53:54.077425 [Byte1]: 50
3355 06:53:54.082456
3356 06:53:54.082536 Set Vref, RX VrefLevel [Byte0]: 51
3357 06:53:54.085476 [Byte1]: 51
3358 06:53:54.090316
3359 06:53:54.090422 Set Vref, RX VrefLevel [Byte0]: 52
3360 06:53:54.093201 [Byte1]: 52
3361 06:53:54.098428
3362 06:53:54.098509 Set Vref, RX VrefLevel [Byte0]: 53
3363 06:53:54.101348 [Byte1]: 53
3364 06:53:54.105909
3365 06:53:54.105990 Set Vref, RX VrefLevel [Byte0]: 54
3366 06:53:54.109262 [Byte1]: 54
3367 06:53:54.114095
3368 06:53:54.114182 Set Vref, RX VrefLevel [Byte0]: 55
3369 06:53:54.117350 [Byte1]: 55
3370 06:53:54.121537
3371 06:53:54.121617 Set Vref, RX VrefLevel [Byte0]: 56
3372 06:53:54.125135 [Byte1]: 56
3373 06:53:54.129492
3374 06:53:54.129575 Set Vref, RX VrefLevel [Byte0]: 57
3375 06:53:54.132999 [Byte1]: 57
3376 06:53:54.137653
3377 06:53:54.137733 Set Vref, RX VrefLevel [Byte0]: 58
3378 06:53:54.140859 [Byte1]: 58
3379 06:53:54.145239
3380 06:53:54.145336 Set Vref, RX VrefLevel [Byte0]: 59
3381 06:53:54.148607 [Byte1]: 59
3382 06:53:54.153509
3383 06:53:54.153589 Set Vref, RX VrefLevel [Byte0]: 60
3384 06:53:54.156878 [Byte1]: 60
3385 06:53:54.161331
3386 06:53:54.161411 Set Vref, RX VrefLevel [Byte0]: 61
3387 06:53:54.164737 [Byte1]: 61
3388 06:53:54.169675
3389 06:53:54.169753 Set Vref, RX VrefLevel [Byte0]: 62
3390 06:53:54.172445 [Byte1]: 62
3391 06:53:54.177317
3392 06:53:54.177396 Set Vref, RX VrefLevel [Byte0]: 63
3393 06:53:54.180309 [Byte1]: 63
3394 06:53:54.184905
3395 06:53:54.185011 Set Vref, RX VrefLevel [Byte0]: 64
3396 06:53:54.188281 [Byte1]: 64
3397 06:53:54.192945
3398 06:53:54.193026 Set Vref, RX VrefLevel [Byte0]: 65
3399 06:53:54.196186 [Byte1]: 65
3400 06:53:54.200893
3401 06:53:54.201000 Set Vref, RX VrefLevel [Byte0]: 66
3402 06:53:54.204621 [Byte1]: 66
3403 06:53:54.208931
3404 06:53:54.209011 Set Vref, RX VrefLevel [Byte0]: 67
3405 06:53:54.212239 [Byte1]: 67
3406 06:53:54.216962
3407 06:53:54.217037 Set Vref, RX VrefLevel [Byte0]: 68
3408 06:53:54.219821 [Byte1]: 68
3409 06:53:54.224812
3410 06:53:54.224882 Set Vref, RX VrefLevel [Byte0]: 69
3411 06:53:54.228195 [Byte1]: 69
3412 06:53:54.232830
3413 06:53:54.232900 Set Vref, RX VrefLevel [Byte0]: 70
3414 06:53:54.236040 [Byte1]: 70
3415 06:53:54.240365
3416 06:53:54.240431 Set Vref, RX VrefLevel [Byte0]: 71
3417 06:53:54.243867 [Byte1]: 71
3418 06:53:54.248662
3419 06:53:54.248731 Final RX Vref Byte 0 = 55 to rank0
3420 06:53:54.252094 Final RX Vref Byte 1 = 53 to rank0
3421 06:53:54.255879 Final RX Vref Byte 0 = 55 to rank1
3422 06:53:54.258715 Final RX Vref Byte 1 = 53 to rank1==
3423 06:53:54.262268 Dram Type= 6, Freq= 0, CH_1, rank 0
3424 06:53:54.265282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3425 06:53:54.268455 ==
3426 06:53:54.268549 DQS Delay:
3427 06:53:54.268638 DQS0 = 0, DQS1 = 0
3428 06:53:54.272225 DQM Delay:
3429 06:53:54.272324 DQM0 = 115, DQM1 = 110
3430 06:53:54.275727 DQ Delay:
3431 06:53:54.278631 DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =114
3432 06:53:54.282127 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3433 06:53:54.285780 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =106
3434 06:53:54.288939 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =114
3435 06:53:54.289036
3436 06:53:54.289123
3437 06:53:54.295353 [DQSOSCAuto] RK0, (LSB)MR18= 0xffe4, (MSB)MR19= 0x303, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
3438 06:53:54.298849 CH1 RK0: MR19=303, MR18=FFE4
3439 06:53:54.305599 CH1_RK0: MR19=0x303, MR18=0xFFE4, DQSOSC=410, MR23=63, INC=39, DEC=26
3440 06:53:54.305699
3441 06:53:54.309167 ----->DramcWriteLeveling(PI) begin...
3442 06:53:54.309302 ==
3443 06:53:54.312415 Dram Type= 6, Freq= 0, CH_1, rank 1
3444 06:53:54.315295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3445 06:53:54.315367 ==
3446 06:53:54.318681 Write leveling (Byte 0): 26 => 26
3447 06:53:54.322247 Write leveling (Byte 1): 27 => 27
3448 06:53:54.325739 DramcWriteLeveling(PI) end<-----
3449 06:53:54.325811
3450 06:53:54.325877 ==
3451 06:53:54.329204 Dram Type= 6, Freq= 0, CH_1, rank 1
3452 06:53:54.331965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3453 06:53:54.335406 ==
3454 06:53:54.335499 [Gating] SW mode calibration
3455 06:53:54.342232 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3456 06:53:54.348775 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3457 06:53:54.352393 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
3458 06:53:54.358997 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 06:53:54.362032 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 06:53:54.365503 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 06:53:54.372093 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 06:53:54.375272 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 06:53:54.378812 0 15 24 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
3464 06:53:54.385917 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (1 0)
3465 06:53:54.388680 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 06:53:54.392372 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 06:53:54.395534 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 06:53:54.402565 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 06:53:54.405609 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 06:53:54.409194 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 06:53:54.415330 1 0 24 | B1->B0 | 2525 3c3c | 0 0 | (0 0) (1 1)
3472 06:53:54.419217 1 0 28 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
3473 06:53:54.422525 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 06:53:54.429027 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 06:53:54.432534 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 06:53:54.435727 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 06:53:54.442525 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 06:53:54.445833 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 06:53:54.448810 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3480 06:53:54.455695 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3481 06:53:54.458799 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 06:53:54.462008 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 06:53:54.468935 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 06:53:54.472408 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 06:53:54.475654 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 06:53:54.482132 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 06:53:54.485686 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 06:53:54.488810 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 06:53:54.495620 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 06:53:54.498895 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 06:53:54.502528 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 06:53:54.505412 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 06:53:54.511962 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 06:53:54.515587 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3495 06:53:54.518783 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3496 06:53:54.525689 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3497 06:53:54.528813 Total UI for P1: 0, mck2ui 16
3498 06:53:54.532331 best dqsien dly found for B0: ( 1, 3, 22)
3499 06:53:54.535311 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 06:53:54.539137 Total UI for P1: 0, mck2ui 16
3501 06:53:54.541982 best dqsien dly found for B1: ( 1, 3, 28)
3502 06:53:54.545661 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3503 06:53:54.549060 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3504 06:53:54.549158
3505 06:53:54.551972 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3506 06:53:54.555342 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3507 06:53:54.558673 [Gating] SW calibration Done
3508 06:53:54.558781 ==
3509 06:53:54.562020 Dram Type= 6, Freq= 0, CH_1, rank 1
3510 06:53:54.565260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3511 06:53:54.568544 ==
3512 06:53:54.568642 RX Vref Scan: 0
3513 06:53:54.568728
3514 06:53:54.571998 RX Vref 0 -> 0, step: 1
3515 06:53:54.572096
3516 06:53:54.575480 RX Delay -40 -> 252, step: 8
3517 06:53:54.578490 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3518 06:53:54.582028 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3519 06:53:54.585506 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3520 06:53:54.588611 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3521 06:53:54.595385 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3522 06:53:54.598863 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3523 06:53:54.601805 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3524 06:53:54.605283 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3525 06:53:54.608843 iDelay=200, Bit 8, Center 103 (32 ~ 175) 144
3526 06:53:54.615628 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3527 06:53:54.618696 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3528 06:53:54.621811 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3529 06:53:54.625558 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3530 06:53:54.628892 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3531 06:53:54.635306 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3532 06:53:54.638646 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3533 06:53:54.638727 ==
3534 06:53:54.642088 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 06:53:54.645254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 06:53:54.645334 ==
3537 06:53:54.645397 DQS Delay:
3538 06:53:54.648512 DQS0 = 0, DQS1 = 0
3539 06:53:54.648592 DQM Delay:
3540 06:53:54.652322 DQM0 = 114, DQM1 = 111
3541 06:53:54.652402 DQ Delay:
3542 06:53:54.655680 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3543 06:53:54.658903 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =107
3544 06:53:54.662070 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3545 06:53:54.665353 DQ12 =115, DQ13 =123, DQ14 =119, DQ15 =119
3546 06:53:54.668610
3547 06:53:54.668690
3548 06:53:54.668753 ==
3549 06:53:54.671875 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 06:53:54.675326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 06:53:54.675408 ==
3552 06:53:54.675473
3553 06:53:54.675531
3554 06:53:54.678629 TX Vref Scan disable
3555 06:53:54.678709 == TX Byte 0 ==
3556 06:53:54.685675 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3557 06:53:54.688519 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3558 06:53:54.688624 == TX Byte 1 ==
3559 06:53:54.695290 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3560 06:53:54.699107 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3561 06:53:54.699217 ==
3562 06:53:54.701824 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 06:53:54.705514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 06:53:54.705622 ==
3565 06:53:54.718099 TX Vref=22, minBit 1, minWin=25, winSum=419
3566 06:53:54.721117 TX Vref=24, minBit 0, minWin=25, winSum=421
3567 06:53:54.724656 TX Vref=26, minBit 3, minWin=25, winSum=424
3568 06:53:54.727780 TX Vref=28, minBit 3, minWin=26, winSum=433
3569 06:53:54.731468 TX Vref=30, minBit 2, minWin=26, winSum=432
3570 06:53:54.734405 TX Vref=32, minBit 3, minWin=26, winSum=434
3571 06:53:54.741124 [TxChooseVref] Worse bit 3, Min win 26, Win sum 434, Final Vref 32
3572 06:53:54.741254
3573 06:53:54.744357 Final TX Range 1 Vref 32
3574 06:53:54.744459
3575 06:53:54.744550 ==
3576 06:53:54.747886 Dram Type= 6, Freq= 0, CH_1, rank 1
3577 06:53:54.751054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3578 06:53:54.751162 ==
3579 06:53:54.751300
3580 06:53:54.751389
3581 06:53:54.754587 TX Vref Scan disable
3582 06:53:54.758166 == TX Byte 0 ==
3583 06:53:54.761196 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3584 06:53:54.764652 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3585 06:53:54.768017 == TX Byte 1 ==
3586 06:53:54.771571 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3587 06:53:54.774435 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3588 06:53:54.774515
3589 06:53:54.778086 [DATLAT]
3590 06:53:54.778161 Freq=1200, CH1 RK1
3591 06:53:54.778223
3592 06:53:54.781412 DATLAT Default: 0xd
3593 06:53:54.781483 0, 0xFFFF, sum = 0
3594 06:53:54.784729 1, 0xFFFF, sum = 0
3595 06:53:54.784804 2, 0xFFFF, sum = 0
3596 06:53:54.788117 3, 0xFFFF, sum = 0
3597 06:53:54.788201 4, 0xFFFF, sum = 0
3598 06:53:54.791501 5, 0xFFFF, sum = 0
3599 06:53:54.791571 6, 0xFFFF, sum = 0
3600 06:53:54.794937 7, 0xFFFF, sum = 0
3601 06:53:54.795020 8, 0xFFFF, sum = 0
3602 06:53:54.797784 9, 0xFFFF, sum = 0
3603 06:53:54.797855 10, 0xFFFF, sum = 0
3604 06:53:54.801483 11, 0xFFFF, sum = 0
3605 06:53:54.801591 12, 0x0, sum = 1
3606 06:53:54.804717 13, 0x0, sum = 2
3607 06:53:54.804826 14, 0x0, sum = 3
3608 06:53:54.808168 15, 0x0, sum = 4
3609 06:53:54.808278 best_step = 13
3610 06:53:54.808367
3611 06:53:54.808459 ==
3612 06:53:54.811650 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 06:53:54.818150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 06:53:54.818252 ==
3615 06:53:54.818346 RX Vref Scan: 0
3616 06:53:54.818443
3617 06:53:54.821090 RX Vref 0 -> 0, step: 1
3618 06:53:54.821186
3619 06:53:54.824413 RX Delay -21 -> 252, step: 4
3620 06:53:54.827953 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3621 06:53:54.830962 iDelay=191, Bit 1, Center 108 (39 ~ 178) 140
3622 06:53:54.838434 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3623 06:53:54.841203 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3624 06:53:54.844929 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3625 06:53:54.847820 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3626 06:53:54.851435 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3627 06:53:54.857716 iDelay=191, Bit 7, Center 112 (47 ~ 178) 132
3628 06:53:54.861039 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3629 06:53:54.864325 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3630 06:53:54.867802 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3631 06:53:54.871170 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3632 06:53:54.874815 iDelay=191, Bit 12, Center 116 (51 ~ 182) 132
3633 06:53:54.881154 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3634 06:53:54.884606 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3635 06:53:54.887636 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3636 06:53:54.887734 ==
3637 06:53:54.891336 Dram Type= 6, Freq= 0, CH_1, rank 1
3638 06:53:54.894608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3639 06:53:54.897700 ==
3640 06:53:54.897801 DQS Delay:
3641 06:53:54.897889 DQS0 = 0, DQS1 = 0
3642 06:53:54.901042 DQM Delay:
3643 06:53:54.901150 DQM0 = 113, DQM1 = 110
3644 06:53:54.904660 DQ Delay:
3645 06:53:54.907882 DQ0 =112, DQ1 =108, DQ2 =104, DQ3 =112
3646 06:53:54.911647 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =112
3647 06:53:54.914590 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3648 06:53:54.917687 DQ12 =116, DQ13 =120, DQ14 =118, DQ15 =120
3649 06:53:54.917786
3650 06:53:54.917883
3651 06:53:54.924432 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa01, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3652 06:53:54.927624 CH1 RK1: MR19=304, MR18=FA01
3653 06:53:54.934229 CH1_RK1: MR19=0x304, MR18=0xFA01, DQSOSC=409, MR23=63, INC=39, DEC=26
3654 06:53:54.938067 [RxdqsGatingPostProcess] freq 1200
3655 06:53:54.944673 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3656 06:53:54.944774 best DQS0 dly(2T, 0.5T) = (0, 11)
3657 06:53:54.948149 best DQS1 dly(2T, 0.5T) = (0, 11)
3658 06:53:54.951280 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3659 06:53:54.954227 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3660 06:53:54.957538 best DQS0 dly(2T, 0.5T) = (0, 11)
3661 06:53:54.961362 best DQS1 dly(2T, 0.5T) = (0, 11)
3662 06:53:54.964286 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3663 06:53:54.967844 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3664 06:53:54.970974 Pre-setting of DQS Precalculation
3665 06:53:54.977413 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3666 06:53:54.984093 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3667 06:53:54.990761 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3668 06:53:54.990864
3669 06:53:54.990954
3670 06:53:54.994423 [Calibration Summary] 2400 Mbps
3671 06:53:54.994523 CH 0, Rank 0
3672 06:53:54.997310 SW Impedance : PASS
3673 06:53:55.000499 DUTY Scan : NO K
3674 06:53:55.000601 ZQ Calibration : PASS
3675 06:53:55.004120 Jitter Meter : NO K
3676 06:53:55.007804 CBT Training : PASS
3677 06:53:55.007904 Write leveling : PASS
3678 06:53:55.011012 RX DQS gating : PASS
3679 06:53:55.011123 RX DQ/DQS(RDDQC) : PASS
3680 06:53:55.014113 TX DQ/DQS : PASS
3681 06:53:55.017696 RX DATLAT : PASS
3682 06:53:55.017794 RX DQ/DQS(Engine): PASS
3683 06:53:55.020810 TX OE : NO K
3684 06:53:55.020907 All Pass.
3685 06:53:55.021007
3686 06:53:55.024108 CH 0, Rank 1
3687 06:53:55.024208 SW Impedance : PASS
3688 06:53:55.027381 DUTY Scan : NO K
3689 06:53:55.031186 ZQ Calibration : PASS
3690 06:53:55.031292 Jitter Meter : NO K
3691 06:53:55.034376 CBT Training : PASS
3692 06:53:55.037916 Write leveling : PASS
3693 06:53:55.038016 RX DQS gating : PASS
3694 06:53:55.041044 RX DQ/DQS(RDDQC) : PASS
3695 06:53:55.044037 TX DQ/DQS : PASS
3696 06:53:55.044141 RX DATLAT : PASS
3697 06:53:55.047730 RX DQ/DQS(Engine): PASS
3698 06:53:55.047841 TX OE : NO K
3699 06:53:55.050596 All Pass.
3700 06:53:55.050697
3701 06:53:55.050789 CH 1, Rank 0
3702 06:53:55.054181 SW Impedance : PASS
3703 06:53:55.054285 DUTY Scan : NO K
3704 06:53:55.057357 ZQ Calibration : PASS
3705 06:53:55.060614 Jitter Meter : NO K
3706 06:53:55.060715 CBT Training : PASS
3707 06:53:55.064050 Write leveling : PASS
3708 06:53:55.067860 RX DQS gating : PASS
3709 06:53:55.067968 RX DQ/DQS(RDDQC) : PASS
3710 06:53:55.070869 TX DQ/DQS : PASS
3711 06:53:55.074599 RX DATLAT : PASS
3712 06:53:55.074707 RX DQ/DQS(Engine): PASS
3713 06:53:55.077515 TX OE : NO K
3714 06:53:55.077625 All Pass.
3715 06:53:55.077717
3716 06:53:55.081125 CH 1, Rank 1
3717 06:53:55.081238 SW Impedance : PASS
3718 06:53:55.084036 DUTY Scan : NO K
3719 06:53:55.087337 ZQ Calibration : PASS
3720 06:53:55.087438 Jitter Meter : NO K
3721 06:53:55.090811 CBT Training : PASS
3722 06:53:55.094357 Write leveling : PASS
3723 06:53:55.094463 RX DQS gating : PASS
3724 06:53:55.097288 RX DQ/DQS(RDDQC) : PASS
3725 06:53:55.097392 TX DQ/DQS : PASS
3726 06:53:55.100638 RX DATLAT : PASS
3727 06:53:55.104512 RX DQ/DQS(Engine): PASS
3728 06:53:55.104615 TX OE : NO K
3729 06:53:55.107339 All Pass.
3730 06:53:55.107448
3731 06:53:55.107546 DramC Write-DBI off
3732 06:53:55.110866 PER_BANK_REFRESH: Hybrid Mode
3733 06:53:55.114101 TX_TRACKING: ON
3734 06:53:55.120942 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3735 06:53:55.124423 [FAST_K] Save calibration result to emmc
3736 06:53:55.127299 dramc_set_vcore_voltage set vcore to 650000
3737 06:53:55.130450 Read voltage for 600, 5
3738 06:53:55.130552 Vio18 = 0
3739 06:53:55.134086 Vcore = 650000
3740 06:53:55.134194 Vdram = 0
3741 06:53:55.134287 Vddq = 0
3742 06:53:55.137301 Vmddr = 0
3743 06:53:55.140756 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3744 06:53:55.147129 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3745 06:53:55.147237 MEM_TYPE=3, freq_sel=19
3746 06:53:55.151105 sv_algorithm_assistance_LP4_1600
3747 06:53:55.157488 ============ PULL DRAM RESETB DOWN ============
3748 06:53:55.160794 ========== PULL DRAM RESETB DOWN end =========
3749 06:53:55.163781 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3750 06:53:55.167362 ===================================
3751 06:53:55.170519 LPDDR4 DRAM CONFIGURATION
3752 06:53:55.173942 ===================================
3753 06:53:55.174054 EX_ROW_EN[0] = 0x0
3754 06:53:55.177553 EX_ROW_EN[1] = 0x0
3755 06:53:55.180602 LP4Y_EN = 0x0
3756 06:53:55.180674 WORK_FSP = 0x0
3757 06:53:55.184128 WL = 0x2
3758 06:53:55.184196 RL = 0x2
3759 06:53:55.187418 BL = 0x2
3760 06:53:55.187523 RPST = 0x0
3761 06:53:55.190953 RD_PRE = 0x0
3762 06:53:55.191054 WR_PRE = 0x1
3763 06:53:55.194228 WR_PST = 0x0
3764 06:53:55.194329 DBI_WR = 0x0
3765 06:53:55.197696 DBI_RD = 0x0
3766 06:53:55.197795 OTF = 0x1
3767 06:53:55.200476 ===================================
3768 06:53:55.204043 ===================================
3769 06:53:55.207356 ANA top config
3770 06:53:55.210929 ===================================
3771 06:53:55.211003 DLL_ASYNC_EN = 0
3772 06:53:55.213990 ALL_SLAVE_EN = 1
3773 06:53:55.217614 NEW_RANK_MODE = 1
3774 06:53:55.220594 DLL_IDLE_MODE = 1
3775 06:53:55.223732 LP45_APHY_COMB_EN = 1
3776 06:53:55.223834 TX_ODT_DIS = 1
3777 06:53:55.227017 NEW_8X_MODE = 1
3778 06:53:55.230471 ===================================
3779 06:53:55.233858 ===================================
3780 06:53:55.237007 data_rate = 1200
3781 06:53:55.240572 CKR = 1
3782 06:53:55.244210 DQ_P2S_RATIO = 8
3783 06:53:55.247198 ===================================
3784 06:53:55.247283 CA_P2S_RATIO = 8
3785 06:53:55.250896 DQ_CA_OPEN = 0
3786 06:53:55.253706 DQ_SEMI_OPEN = 0
3787 06:53:55.257460 CA_SEMI_OPEN = 0
3788 06:53:55.260418 CA_FULL_RATE = 0
3789 06:53:55.263945 DQ_CKDIV4_EN = 1
3790 06:53:55.264051 CA_CKDIV4_EN = 1
3791 06:53:55.267380 CA_PREDIV_EN = 0
3792 06:53:55.270497 PH8_DLY = 0
3793 06:53:55.273630 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3794 06:53:55.277101 DQ_AAMCK_DIV = 4
3795 06:53:55.280832 CA_AAMCK_DIV = 4
3796 06:53:55.280916 CA_ADMCK_DIV = 4
3797 06:53:55.283662 DQ_TRACK_CA_EN = 0
3798 06:53:55.287219 CA_PICK = 600
3799 06:53:55.291049 CA_MCKIO = 600
3800 06:53:55.294144 MCKIO_SEMI = 0
3801 06:53:55.297086 PLL_FREQ = 2288
3802 06:53:55.297170 DQ_UI_PI_RATIO = 32
3803 06:53:55.300655 CA_UI_PI_RATIO = 0
3804 06:53:55.304294 ===================================
3805 06:53:55.307180 ===================================
3806 06:53:55.310827 memory_type:LPDDR4
3807 06:53:55.314291 GP_NUM : 10
3808 06:53:55.314375 SRAM_EN : 1
3809 06:53:55.317156 MD32_EN : 0
3810 06:53:55.320923 ===================================
3811 06:53:55.324142 [ANA_INIT] >>>>>>>>>>>>>>
3812 06:53:55.324225 <<<<<< [CONFIGURE PHASE]: ANA_TX
3813 06:53:55.327037 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3814 06:53:55.330746 ===================================
3815 06:53:55.334304 data_rate = 1200,PCW = 0X5800
3816 06:53:55.337172 ===================================
3817 06:53:55.340719 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3818 06:53:55.347351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3819 06:53:55.354283 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3820 06:53:55.357315 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3821 06:53:55.361066 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3822 06:53:55.364164 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3823 06:53:55.367338 [ANA_INIT] flow start
3824 06:53:55.367423 [ANA_INIT] PLL >>>>>>>>
3825 06:53:55.371146 [ANA_INIT] PLL <<<<<<<<
3826 06:53:55.374391 [ANA_INIT] MIDPI >>>>>>>>
3827 06:53:55.374476 [ANA_INIT] MIDPI <<<<<<<<
3828 06:53:55.377366 [ANA_INIT] DLL >>>>>>>>
3829 06:53:55.380608 [ANA_INIT] flow end
3830 06:53:55.384072 ============ LP4 DIFF to SE enter ============
3831 06:53:55.387089 ============ LP4 DIFF to SE exit ============
3832 06:53:55.390668 [ANA_INIT] <<<<<<<<<<<<<
3833 06:53:55.394383 [Flow] Enable top DCM control >>>>>
3834 06:53:55.397413 [Flow] Enable top DCM control <<<<<
3835 06:53:55.400993 Enable DLL master slave shuffle
3836 06:53:55.403952 ==============================================================
3837 06:53:55.407560 Gating Mode config
3838 06:53:55.414119 ==============================================================
3839 06:53:55.414202 Config description:
3840 06:53:55.424296 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3841 06:53:55.430987 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3842 06:53:55.434220 SELPH_MODE 0: By rank 1: By Phase
3843 06:53:55.440659 ==============================================================
3844 06:53:55.444302 GAT_TRACK_EN = 1
3845 06:53:55.447420 RX_GATING_MODE = 2
3846 06:53:55.451133 RX_GATING_TRACK_MODE = 2
3847 06:53:55.453817 SELPH_MODE = 1
3848 06:53:55.457768 PICG_EARLY_EN = 1
3849 06:53:55.460738 VALID_LAT_VALUE = 1
3850 06:53:55.463917 ==============================================================
3851 06:53:55.467267 Enter into Gating configuration >>>>
3852 06:53:55.470659 Exit from Gating configuration <<<<
3853 06:53:55.474418 Enter into DVFS_PRE_config >>>>>
3854 06:53:55.484359 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3855 06:53:55.487331 Exit from DVFS_PRE_config <<<<<
3856 06:53:55.490649 Enter into PICG configuration >>>>
3857 06:53:55.494146 Exit from PICG configuration <<<<
3858 06:53:55.497469 [RX_INPUT] configuration >>>>>
3859 06:53:55.500655 [RX_INPUT] configuration <<<<<
3860 06:53:55.504336 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3861 06:53:55.510788 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3862 06:53:55.517265 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3863 06:53:55.523832 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3864 06:53:55.530920 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3865 06:53:55.534078 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3866 06:53:55.540780 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3867 06:53:55.544395 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3868 06:53:55.547325 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3869 06:53:55.550557 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3870 06:53:55.557499 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3871 06:53:55.560598 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3872 06:53:55.564595 ===================================
3873 06:53:55.567350 LPDDR4 DRAM CONFIGURATION
3874 06:53:55.570970 ===================================
3875 06:53:55.571084 EX_ROW_EN[0] = 0x0
3876 06:53:55.574273 EX_ROW_EN[1] = 0x0
3877 06:53:55.574359 LP4Y_EN = 0x0
3878 06:53:55.577398 WORK_FSP = 0x0
3879 06:53:55.577485 WL = 0x2
3880 06:53:55.580460 RL = 0x2
3881 06:53:55.580545 BL = 0x2
3882 06:53:55.583989 RPST = 0x0
3883 06:53:55.584127 RD_PRE = 0x0
3884 06:53:55.587686 WR_PRE = 0x1
3885 06:53:55.587794 WR_PST = 0x0
3886 06:53:55.590632 DBI_WR = 0x0
3887 06:53:55.590718 DBI_RD = 0x0
3888 06:53:55.594059 OTF = 0x1
3889 06:53:55.597522 ===================================
3890 06:53:55.601103 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3891 06:53:55.604463 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3892 06:53:55.611065 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3893 06:53:55.614119 ===================================
3894 06:53:55.614231 LPDDR4 DRAM CONFIGURATION
3895 06:53:55.617540 ===================================
3896 06:53:55.620812 EX_ROW_EN[0] = 0x10
3897 06:53:55.624346 EX_ROW_EN[1] = 0x0
3898 06:53:55.624435 LP4Y_EN = 0x0
3899 06:53:55.627498 WORK_FSP = 0x0
3900 06:53:55.627579 WL = 0x2
3901 06:53:55.630812 RL = 0x2
3902 06:53:55.630944 BL = 0x2
3903 06:53:55.634190 RPST = 0x0
3904 06:53:55.634272 RD_PRE = 0x0
3905 06:53:55.638025 WR_PRE = 0x1
3906 06:53:55.638132 WR_PST = 0x0
3907 06:53:55.640876 DBI_WR = 0x0
3908 06:53:55.640963 DBI_RD = 0x0
3909 06:53:55.644493 OTF = 0x1
3910 06:53:55.647504 ===================================
3911 06:53:55.654309 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3912 06:53:55.657933 nWR fixed to 30
3913 06:53:55.658020 [ModeRegInit_LP4] CH0 RK0
3914 06:53:55.661517 [ModeRegInit_LP4] CH0 RK1
3915 06:53:55.664280 [ModeRegInit_LP4] CH1 RK0
3916 06:53:55.667984 [ModeRegInit_LP4] CH1 RK1
3917 06:53:55.668095 match AC timing 17
3918 06:53:55.671061 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3919 06:53:55.674617 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3920 06:53:55.681228 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3921 06:53:55.684281 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3922 06:53:55.690755 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3923 06:53:55.690839 ==
3924 06:53:55.694533 Dram Type= 6, Freq= 0, CH_0, rank 0
3925 06:53:55.697853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3926 06:53:55.697938 ==
3927 06:53:55.704597 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3928 06:53:55.707970 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3929 06:53:55.712624 [CA 0] Center 36 (6~67) winsize 62
3930 06:53:55.715788 [CA 1] Center 36 (6~66) winsize 61
3931 06:53:55.718751 [CA 2] Center 34 (4~65) winsize 62
3932 06:53:55.722192 [CA 3] Center 34 (4~65) winsize 62
3933 06:53:55.725574 [CA 4] Center 33 (3~64) winsize 62
3934 06:53:55.728825 [CA 5] Center 33 (3~64) winsize 62
3935 06:53:55.728935
3936 06:53:55.732023 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3937 06:53:55.732129
3938 06:53:55.735836 [CATrainingPosCal] consider 1 rank data
3939 06:53:55.739168 u2DelayCellTimex100 = 270/100 ps
3940 06:53:55.742395 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3941 06:53:55.745336 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3942 06:53:55.752039 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3943 06:53:55.755435 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3944 06:53:55.758649 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3945 06:53:55.762097 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3946 06:53:55.762178
3947 06:53:55.765756 CA PerBit enable=1, Macro0, CA PI delay=33
3948 06:53:55.765844
3949 06:53:55.768599 [CBTSetCACLKResult] CA Dly = 33
3950 06:53:55.768684 CS Dly: 4 (0~35)
3951 06:53:55.772490 ==
3952 06:53:55.772572 Dram Type= 6, Freq= 0, CH_0, rank 1
3953 06:53:55.779200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3954 06:53:55.779308 ==
3955 06:53:55.782215 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3956 06:53:55.788710 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3957 06:53:55.792362 [CA 0] Center 36 (6~66) winsize 61
3958 06:53:55.795422 [CA 1] Center 36 (6~66) winsize 61
3959 06:53:55.798870 [CA 2] Center 34 (4~65) winsize 62
3960 06:53:55.802478 [CA 3] Center 34 (4~65) winsize 62
3961 06:53:55.805843 [CA 4] Center 33 (3~64) winsize 62
3962 06:53:55.809130 [CA 5] Center 33 (3~64) winsize 62
3963 06:53:55.809225
3964 06:53:55.812322 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3965 06:53:55.812406
3966 06:53:55.815440 [CATrainingPosCal] consider 2 rank data
3967 06:53:55.819259 u2DelayCellTimex100 = 270/100 ps
3968 06:53:55.822186 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3969 06:53:55.825850 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3970 06:53:55.832266 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3971 06:53:55.835946 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3972 06:53:55.839307 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3973 06:53:55.842042 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3974 06:53:55.842125
3975 06:53:55.845709 CA PerBit enable=1, Macro0, CA PI delay=33
3976 06:53:55.845795
3977 06:53:55.849098 [CBTSetCACLKResult] CA Dly = 33
3978 06:53:55.849222 CS Dly: 4 (0~36)
3979 06:53:55.849292
3980 06:53:55.852099 ----->DramcWriteLeveling(PI) begin...
3981 06:53:55.855498 ==
3982 06:53:55.858730 Dram Type= 6, Freq= 0, CH_0, rank 0
3983 06:53:55.862498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3984 06:53:55.862575 ==
3985 06:53:55.865390 Write leveling (Byte 0): 33 => 33
3986 06:53:55.869087 Write leveling (Byte 1): 29 => 29
3987 06:53:55.872203 DramcWriteLeveling(PI) end<-----
3988 06:53:55.872312
3989 06:53:55.872411 ==
3990 06:53:55.875664 Dram Type= 6, Freq= 0, CH_0, rank 0
3991 06:53:55.878781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3992 06:53:55.878857 ==
3993 06:53:55.882324 [Gating] SW mode calibration
3994 06:53:55.888914 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3995 06:53:55.892527 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3996 06:53:55.898698 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3997 06:53:55.902518 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3998 06:53:55.905863 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3999 06:53:55.912495 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 06:53:55.915779 0 9 16 | B1->B0 | 3030 2d2d | 0 0 | (0 1) (1 0)
4001 06:53:55.919025 0 9 20 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
4002 06:53:55.925518 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 06:53:55.928883 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 06:53:55.932569 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 06:53:55.939122 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 06:53:55.942194 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 06:53:55.945723 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 06:53:55.952182 0 10 16 | B1->B0 | 3232 3a3a | 0 0 | (0 0) (0 0)
4009 06:53:55.955666 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 06:53:55.958872 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 06:53:55.965441 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 06:53:55.968875 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 06:53:55.972193 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 06:53:55.975517 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 06:53:55.982112 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 06:53:55.985696 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4017 06:53:55.988905 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4018 06:53:55.995612 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 06:53:55.999160 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 06:53:56.002146 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 06:53:56.008844 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 06:53:56.012077 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 06:53:56.015566 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 06:53:56.022572 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 06:53:56.025623 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 06:53:56.028808 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 06:53:56.035902 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 06:53:56.038678 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 06:53:56.042143 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 06:53:56.049072 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 06:53:56.052482 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 06:53:56.055552 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 06:53:56.059147 Total UI for P1: 0, mck2ui 16
4034 06:53:56.062150 best dqsien dly found for B0: ( 0, 13, 14)
4035 06:53:56.065789 Total UI for P1: 0, mck2ui 16
4036 06:53:56.068886 best dqsien dly found for B1: ( 0, 13, 14)
4037 06:53:56.072163 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4038 06:53:56.075743 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4039 06:53:56.075853
4040 06:53:56.078743 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4041 06:53:56.085410 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4042 06:53:56.085489 [Gating] SW calibration Done
4043 06:53:56.085557 ==
4044 06:53:56.088499 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 06:53:56.095774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 06:53:56.095883 ==
4047 06:53:56.095977 RX Vref Scan: 0
4048 06:53:56.096066
4049 06:53:56.098652 RX Vref 0 -> 0, step: 1
4050 06:53:56.098729
4051 06:53:56.102223 RX Delay -230 -> 252, step: 16
4052 06:53:56.105372 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4053 06:53:56.108935 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4054 06:53:56.115129 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4055 06:53:56.118797 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4056 06:53:56.121672 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4057 06:53:56.125575 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4058 06:53:56.128430 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4059 06:53:56.135246 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4060 06:53:56.138836 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4061 06:53:56.141935 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4062 06:53:56.145177 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4063 06:53:56.152279 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4064 06:53:56.155429 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4065 06:53:56.158451 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4066 06:53:56.162036 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4067 06:53:56.168548 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4068 06:53:56.168631 ==
4069 06:53:56.172160 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 06:53:56.175612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 06:53:56.175698 ==
4072 06:53:56.175785 DQS Delay:
4073 06:53:56.178519 DQS0 = 0, DQS1 = 0
4074 06:53:56.178605 DQM Delay:
4075 06:53:56.181656 DQM0 = 42, DQM1 = 32
4076 06:53:56.181741 DQ Delay:
4077 06:53:56.185349 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4078 06:53:56.188110 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4079 06:53:56.191581 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4080 06:53:56.195009 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4081 06:53:56.195113
4082 06:53:56.195193
4083 06:53:56.195254 ==
4084 06:53:56.198396 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 06:53:56.201622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 06:53:56.201696 ==
4087 06:53:56.201758
4088 06:53:56.201816
4089 06:53:56.204787 TX Vref Scan disable
4090 06:53:56.208330 == TX Byte 0 ==
4091 06:53:56.211735 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4092 06:53:56.214871 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4093 06:53:56.218485 == TX Byte 1 ==
4094 06:53:56.221434 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4095 06:53:56.225110 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4096 06:53:56.225181 ==
4097 06:53:56.228092 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 06:53:56.235108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 06:53:56.235186 ==
4100 06:53:56.235249
4101 06:53:56.235308
4102 06:53:56.235364 TX Vref Scan disable
4103 06:53:56.239063 == TX Byte 0 ==
4104 06:53:56.242698 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4105 06:53:56.249499 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4106 06:53:56.249575 == TX Byte 1 ==
4107 06:53:56.252587 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4108 06:53:56.259049 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4109 06:53:56.259137
4110 06:53:56.259240 [DATLAT]
4111 06:53:56.259340 Freq=600, CH0 RK0
4112 06:53:56.259439
4113 06:53:56.263006 DATLAT Default: 0x9
4114 06:53:56.263092 0, 0xFFFF, sum = 0
4115 06:53:56.265863 1, 0xFFFF, sum = 0
4116 06:53:56.265949 2, 0xFFFF, sum = 0
4117 06:53:56.269552 3, 0xFFFF, sum = 0
4118 06:53:56.269640 4, 0xFFFF, sum = 0
4119 06:53:56.272748 5, 0xFFFF, sum = 0
4120 06:53:56.276102 6, 0xFFFF, sum = 0
4121 06:53:56.276211 7, 0xFFFF, sum = 0
4122 06:53:56.276299 8, 0x0, sum = 1
4123 06:53:56.279290 9, 0x0, sum = 2
4124 06:53:56.279377 10, 0x0, sum = 3
4125 06:53:56.282819 11, 0x0, sum = 4
4126 06:53:56.282907 best_step = 9
4127 06:53:56.282993
4128 06:53:56.283075 ==
4129 06:53:56.285843 Dram Type= 6, Freq= 0, CH_0, rank 0
4130 06:53:56.292530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 06:53:56.292617 ==
4132 06:53:56.292702 RX Vref Scan: 1
4133 06:53:56.292784
4134 06:53:56.295873 RX Vref 0 -> 0, step: 1
4135 06:53:56.295959
4136 06:53:56.299464 RX Delay -195 -> 252, step: 8
4137 06:53:56.299547
4138 06:53:56.302807 Set Vref, RX VrefLevel [Byte0]: 54
4139 06:53:56.305902 [Byte1]: 51
4140 06:53:56.305984
4141 06:53:56.309435 Final RX Vref Byte 0 = 54 to rank0
4142 06:53:56.312445 Final RX Vref Byte 1 = 51 to rank0
4143 06:53:56.316014 Final RX Vref Byte 0 = 54 to rank1
4144 06:53:56.319145 Final RX Vref Byte 1 = 51 to rank1==
4145 06:53:56.322999 Dram Type= 6, Freq= 0, CH_0, rank 0
4146 06:53:56.326330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 06:53:56.326418 ==
4148 06:53:56.329690 DQS Delay:
4149 06:53:56.329798 DQS0 = 0, DQS1 = 0
4150 06:53:56.329892 DQM Delay:
4151 06:53:56.332581 DQM0 = 42, DQM1 = 34
4152 06:53:56.332681 DQ Delay:
4153 06:53:56.336256 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4154 06:53:56.339409 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4155 06:53:56.342812 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =32
4156 06:53:56.345908 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4157 06:53:56.345991
4158 06:53:56.346057
4159 06:53:56.355915 [DQSOSCAuto] RK0, (LSB)MR18= 0x4120, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
4160 06:53:56.356000 CH0 RK0: MR19=808, MR18=4120
4161 06:53:56.362702 CH0_RK0: MR19=0x808, MR18=0x4120, DQSOSC=397, MR23=63, INC=166, DEC=110
4162 06:53:56.362786
4163 06:53:56.366414 ----->DramcWriteLeveling(PI) begin...
4164 06:53:56.366499 ==
4165 06:53:56.369432 Dram Type= 6, Freq= 0, CH_0, rank 1
4166 06:53:56.376101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 06:53:56.376195 ==
4168 06:53:56.379566 Write leveling (Byte 0): 35 => 35
4169 06:53:56.383237 Write leveling (Byte 1): 31 => 31
4170 06:53:56.383320 DramcWriteLeveling(PI) end<-----
4171 06:53:56.383385
4172 06:53:56.386252 ==
4173 06:53:56.389904 Dram Type= 6, Freq= 0, CH_0, rank 1
4174 06:53:56.392531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 06:53:56.392638 ==
4176 06:53:56.396111 [Gating] SW mode calibration
4177 06:53:56.403077 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4178 06:53:56.406425 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4179 06:53:56.413304 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4180 06:53:56.416047 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4181 06:53:56.419602 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4182 06:53:56.426341 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
4183 06:53:56.429549 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4184 06:53:56.432646 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 06:53:56.439692 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 06:53:56.442558 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 06:53:56.446055 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 06:53:56.452665 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 06:53:56.456559 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4190 06:53:56.459437 0 10 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
4191 06:53:56.462996 0 10 16 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
4192 06:53:56.469617 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 06:53:56.472577 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 06:53:56.476174 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 06:53:56.482886 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 06:53:56.485974 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 06:53:56.489708 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 06:53:56.495793 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4199 06:53:56.499395 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4200 06:53:56.503006 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 06:53:56.509237 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 06:53:56.512182 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 06:53:56.515784 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 06:53:56.522286 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 06:53:56.525626 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 06:53:56.529154 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 06:53:56.535895 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 06:53:56.539095 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 06:53:56.542450 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 06:53:56.548580 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 06:53:56.552389 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 06:53:56.555269 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 06:53:56.561977 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 06:53:56.565418 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4215 06:53:56.569212 Total UI for P1: 0, mck2ui 16
4216 06:53:56.572126 best dqsien dly found for B0: ( 0, 13, 10)
4217 06:53:56.575373 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4218 06:53:56.581956 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 06:53:56.582055 Total UI for P1: 0, mck2ui 16
4220 06:53:56.589004 best dqsien dly found for B1: ( 0, 13, 14)
4221 06:53:56.591951 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4222 06:53:56.595440 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4223 06:53:56.595541
4224 06:53:56.598551 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4225 06:53:56.602306 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4226 06:53:56.605443 [Gating] SW calibration Done
4227 06:53:56.605553 ==
4228 06:53:56.608532 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 06:53:56.612159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 06:53:56.612268 ==
4231 06:53:56.615654 RX Vref Scan: 0
4232 06:53:56.615763
4233 06:53:56.615873 RX Vref 0 -> 0, step: 1
4234 06:53:56.615974
4235 06:53:56.619021 RX Delay -230 -> 252, step: 16
4236 06:53:56.622019 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4237 06:53:56.628595 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4238 06:53:56.631893 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4239 06:53:56.635324 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4240 06:53:56.639134 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4241 06:53:56.645650 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4242 06:53:56.648853 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4243 06:53:56.652445 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4244 06:53:56.655745 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4245 06:53:56.658657 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4246 06:53:56.665155 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4247 06:53:56.668579 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4248 06:53:56.671809 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4249 06:53:56.675432 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4250 06:53:56.681937 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4251 06:53:56.685607 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4252 06:53:56.685691 ==
4253 06:53:56.688582 Dram Type= 6, Freq= 0, CH_0, rank 1
4254 06:53:56.691837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4255 06:53:56.691937 ==
4256 06:53:56.695663 DQS Delay:
4257 06:53:56.695744 DQS0 = 0, DQS1 = 0
4258 06:53:56.695815 DQM Delay:
4259 06:53:56.698649 DQM0 = 37, DQM1 = 32
4260 06:53:56.698752 DQ Delay:
4261 06:53:56.702019 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4262 06:53:56.705340 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4263 06:53:56.708443 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4264 06:53:56.711985 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4265 06:53:56.712086
4266 06:53:56.712185
4267 06:53:56.712273 ==
4268 06:53:56.715107 Dram Type= 6, Freq= 0, CH_0, rank 1
4269 06:53:56.722084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4270 06:53:56.722192 ==
4271 06:53:56.722283
4272 06:53:56.722381
4273 06:53:56.722477 TX Vref Scan disable
4274 06:53:56.725874 == TX Byte 0 ==
4275 06:53:56.728978 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4276 06:53:56.732486 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4277 06:53:56.735513 == TX Byte 1 ==
4278 06:53:56.739207 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4279 06:53:56.745980 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4280 06:53:56.746060 ==
4281 06:53:56.748837 Dram Type= 6, Freq= 0, CH_0, rank 1
4282 06:53:56.752457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 06:53:56.752535 ==
4284 06:53:56.752624
4285 06:53:56.752721
4286 06:53:56.755478 TX Vref Scan disable
4287 06:53:56.758952 == TX Byte 0 ==
4288 06:53:56.762288 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4289 06:53:56.765702 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4290 06:53:56.768788 == TX Byte 1 ==
4291 06:53:56.771838 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4292 06:53:56.775637 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4293 06:53:56.775749
4294 06:53:56.775843 [DATLAT]
4295 06:53:56.778808 Freq=600, CH0 RK1
4296 06:53:56.778917
4297 06:53:56.779011 DATLAT Default: 0x9
4298 06:53:56.782158 0, 0xFFFF, sum = 0
4299 06:53:56.782242 1, 0xFFFF, sum = 0
4300 06:53:56.785585 2, 0xFFFF, sum = 0
4301 06:53:56.788771 3, 0xFFFF, sum = 0
4302 06:53:56.788873 4, 0xFFFF, sum = 0
4303 06:53:56.791987 5, 0xFFFF, sum = 0
4304 06:53:56.792089 6, 0xFFFF, sum = 0
4305 06:53:56.795846 7, 0xFFFF, sum = 0
4306 06:53:56.795949 8, 0x0, sum = 1
4307 06:53:56.796044 9, 0x0, sum = 2
4308 06:53:56.799277 10, 0x0, sum = 3
4309 06:53:56.799379 11, 0x0, sum = 4
4310 06:53:56.802316 best_step = 9
4311 06:53:56.802388
4312 06:53:56.802446 ==
4313 06:53:56.805436 Dram Type= 6, Freq= 0, CH_0, rank 1
4314 06:53:56.809419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 06:53:56.809495 ==
4316 06:53:56.812387 RX Vref Scan: 0
4317 06:53:56.812482
4318 06:53:56.812569 RX Vref 0 -> 0, step: 1
4319 06:53:56.812656
4320 06:53:56.815305 RX Delay -195 -> 252, step: 8
4321 06:53:56.822823 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4322 06:53:56.826328 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4323 06:53:56.829364 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4324 06:53:56.832724 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4325 06:53:56.839929 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4326 06:53:56.842823 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4327 06:53:56.846043 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4328 06:53:56.849608 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4329 06:53:56.852701 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4330 06:53:56.859289 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4331 06:53:56.862575 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4332 06:53:56.866536 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4333 06:53:56.869474 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4334 06:53:56.876230 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4335 06:53:56.879625 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4336 06:53:56.882818 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4337 06:53:56.882915 ==
4338 06:53:56.885741 Dram Type= 6, Freq= 0, CH_0, rank 1
4339 06:53:56.889288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4340 06:53:56.892416 ==
4341 06:53:56.892487 DQS Delay:
4342 06:53:56.892546 DQS0 = 0, DQS1 = 0
4343 06:53:56.895957 DQM Delay:
4344 06:53:56.896028 DQM0 = 40, DQM1 = 33
4345 06:53:56.899353 DQ Delay:
4346 06:53:56.899448 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4347 06:53:56.902534 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4348 06:53:56.905662 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4349 06:53:56.909529 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4350 06:53:56.912392
4351 06:53:56.912487
4352 06:53:56.919057 [DQSOSCAuto] RK1, (LSB)MR18= 0x4d30, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4353 06:53:56.922670 CH0 RK1: MR19=808, MR18=4D30
4354 06:53:56.929615 CH0_RK1: MR19=0x808, MR18=0x4D30, DQSOSC=395, MR23=63, INC=168, DEC=112
4355 06:53:56.932430 [RxdqsGatingPostProcess] freq 600
4356 06:53:56.936147 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4357 06:53:56.939486 Pre-setting of DQS Precalculation
4358 06:53:56.942452 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4359 06:53:56.946039 ==
4360 06:53:56.949156 Dram Type= 6, Freq= 0, CH_1, rank 0
4361 06:53:56.952312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4362 06:53:56.952411 ==
4363 06:53:56.955882 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4364 06:53:56.962796 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4365 06:53:56.966218 [CA 0] Center 35 (5~66) winsize 62
4366 06:53:56.969568 [CA 1] Center 35 (5~66) winsize 62
4367 06:53:56.972952 [CA 2] Center 33 (3~64) winsize 62
4368 06:53:56.976301 [CA 3] Center 33 (3~64) winsize 62
4369 06:53:56.979364 [CA 4] Center 34 (3~65) winsize 63
4370 06:53:56.983034 [CA 5] Center 33 (2~64) winsize 63
4371 06:53:56.983106
4372 06:53:56.986236 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4373 06:53:56.986319
4374 06:53:56.989578 [CATrainingPosCal] consider 1 rank data
4375 06:53:56.992968 u2DelayCellTimex100 = 270/100 ps
4376 06:53:56.996757 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4377 06:53:56.999413 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4378 06:53:57.006623 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4379 06:53:57.009825 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4380 06:53:57.013160 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4381 06:53:57.016448 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4382 06:53:57.016564
4383 06:53:57.019851 CA PerBit enable=1, Macro0, CA PI delay=33
4384 06:53:57.019924
4385 06:53:57.023359 [CBTSetCACLKResult] CA Dly = 33
4386 06:53:57.023432 CS Dly: 3 (0~34)
4387 06:53:57.023510 ==
4388 06:53:57.026549 Dram Type= 6, Freq= 0, CH_1, rank 1
4389 06:53:57.033316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 06:53:57.033392 ==
4391 06:53:57.036324 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4392 06:53:57.042902 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4393 06:53:57.046349 [CA 0] Center 35 (5~66) winsize 62
4394 06:53:57.050159 [CA 1] Center 35 (5~66) winsize 62
4395 06:53:57.052916 [CA 2] Center 34 (3~65) winsize 63
4396 06:53:57.056760 [CA 3] Center 34 (3~65) winsize 63
4397 06:53:57.059890 [CA 4] Center 34 (3~65) winsize 63
4398 06:53:57.062793 [CA 5] Center 33 (3~64) winsize 62
4399 06:53:57.062894
4400 06:53:57.066460 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4401 06:53:57.066534
4402 06:53:57.069462 [CATrainingPosCal] consider 2 rank data
4403 06:53:57.073313 u2DelayCellTimex100 = 270/100 ps
4404 06:53:57.076356 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4405 06:53:57.079655 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4406 06:53:57.086753 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4407 06:53:57.089613 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4408 06:53:57.093225 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4409 06:53:57.096594 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4410 06:53:57.096698
4411 06:53:57.099478 CA PerBit enable=1, Macro0, CA PI delay=33
4412 06:53:57.099585
4413 06:53:57.103021 [CBTSetCACLKResult] CA Dly = 33
4414 06:53:57.103105 CS Dly: 4 (0~36)
4415 06:53:57.103206
4416 06:53:57.106479 ----->DramcWriteLeveling(PI) begin...
4417 06:53:57.109972 ==
4418 06:53:57.113009 Dram Type= 6, Freq= 0, CH_1, rank 0
4419 06:53:57.116313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 06:53:57.116420 ==
4421 06:53:57.119948 Write leveling (Byte 0): 31 => 31
4422 06:53:57.123119 Write leveling (Byte 1): 30 => 30
4423 06:53:57.126078 DramcWriteLeveling(PI) end<-----
4424 06:53:57.126161
4425 06:53:57.126243 ==
4426 06:53:57.129551 Dram Type= 6, Freq= 0, CH_1, rank 0
4427 06:53:57.132733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4428 06:53:57.132813 ==
4429 06:53:57.136263 [Gating] SW mode calibration
4430 06:53:57.143027 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4431 06:53:57.146189 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4432 06:53:57.153032 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4433 06:53:57.156369 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4434 06:53:57.159424 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4435 06:53:57.166264 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
4436 06:53:57.169602 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4437 06:53:57.173337 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 06:53:57.179642 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4439 06:53:57.183195 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 06:53:57.186233 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4441 06:53:57.192820 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4442 06:53:57.196587 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4443 06:53:57.199583 0 10 12 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
4444 06:53:57.206500 0 10 16 | B1->B0 | 3e3e 4040 | 0 0 | (0 0) (0 0)
4445 06:53:57.209941 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 06:53:57.213379 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 06:53:57.219722 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 06:53:57.223025 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 06:53:57.226768 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 06:53:57.230034 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 06:53:57.236680 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4452 06:53:57.239740 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4453 06:53:57.243326 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 06:53:57.249979 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 06:53:57.253012 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 06:53:57.256231 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 06:53:57.262892 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 06:53:57.266512 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 06:53:57.269775 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 06:53:57.276017 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 06:53:57.279504 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 06:53:57.283254 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 06:53:57.289813 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 06:53:57.292970 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 06:53:57.296283 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 06:53:57.303159 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 06:53:57.306032 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 06:53:57.309557 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 06:53:57.312779 Total UI for P1: 0, mck2ui 16
4470 06:53:57.316180 best dqsien dly found for B0: ( 0, 13, 14)
4471 06:53:57.319686 Total UI for P1: 0, mck2ui 16
4472 06:53:57.322735 best dqsien dly found for B1: ( 0, 13, 14)
4473 06:53:57.326378 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4474 06:53:57.329669 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4475 06:53:57.329746
4476 06:53:57.336320 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4477 06:53:57.339474 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4478 06:53:57.339573 [Gating] SW calibration Done
4479 06:53:57.343102 ==
4480 06:53:57.343174 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 06:53:57.349339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 06:53:57.349417 ==
4483 06:53:57.349479 RX Vref Scan: 0
4484 06:53:57.349538
4485 06:53:57.352614 RX Vref 0 -> 0, step: 1
4486 06:53:57.352709
4487 06:53:57.356370 RX Delay -230 -> 252, step: 16
4488 06:53:57.359445 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4489 06:53:57.362891 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4490 06:53:57.369280 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4491 06:53:57.372758 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4492 06:53:57.375791 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4493 06:53:57.379277 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4494 06:53:57.382923 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4495 06:53:57.389574 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4496 06:53:57.392583 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4497 06:53:57.396282 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4498 06:53:57.399964 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4499 06:53:57.406170 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4500 06:53:57.409379 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4501 06:53:57.412896 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4502 06:53:57.416616 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4503 06:53:57.419463 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4504 06:53:57.422787 ==
4505 06:53:57.426263 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 06:53:57.429307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 06:53:57.429410 ==
4508 06:53:57.429524 DQS Delay:
4509 06:53:57.433033 DQS0 = 0, DQS1 = 0
4510 06:53:57.433134 DQM Delay:
4511 06:53:57.436113 DQM0 = 43, DQM1 = 35
4512 06:53:57.436206 DQ Delay:
4513 06:53:57.439450 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4514 06:53:57.443185 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =41
4515 06:53:57.446465 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =33
4516 06:53:57.449472 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4517 06:53:57.449578
4518 06:53:57.449673
4519 06:53:57.449765 ==
4520 06:53:57.452591 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 06:53:57.456230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 06:53:57.456332 ==
4523 06:53:57.456425
4524 06:53:57.456513
4525 06:53:57.459356 TX Vref Scan disable
4526 06:53:57.462581 == TX Byte 0 ==
4527 06:53:57.465816 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4528 06:53:57.469305 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4529 06:53:57.472446 == TX Byte 1 ==
4530 06:53:57.476287 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4531 06:53:57.479881 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4532 06:53:57.479999 ==
4533 06:53:57.482594 Dram Type= 6, Freq= 0, CH_1, rank 0
4534 06:53:57.485873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4535 06:53:57.489323 ==
4536 06:53:57.489425
4537 06:53:57.489531
4538 06:53:57.489620 TX Vref Scan disable
4539 06:53:57.493700 == TX Byte 0 ==
4540 06:53:57.496819 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4541 06:53:57.500005 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4542 06:53:57.503791 == TX Byte 1 ==
4543 06:53:57.506836 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4544 06:53:57.510369 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4545 06:53:57.513665
4546 06:53:57.513741 [DATLAT]
4547 06:53:57.513803 Freq=600, CH1 RK0
4548 06:53:57.513862
4549 06:53:57.516810 DATLAT Default: 0x9
4550 06:53:57.516905 0, 0xFFFF, sum = 0
4551 06:53:57.520209 1, 0xFFFF, sum = 0
4552 06:53:57.520286 2, 0xFFFF, sum = 0
4553 06:53:57.523332 3, 0xFFFF, sum = 0
4554 06:53:57.523438 4, 0xFFFF, sum = 0
4555 06:53:57.526389 5, 0xFFFF, sum = 0
4556 06:53:57.529682 6, 0xFFFF, sum = 0
4557 06:53:57.529759 7, 0xFFFF, sum = 0
4558 06:53:57.529822 8, 0x0, sum = 1
4559 06:53:57.533356 9, 0x0, sum = 2
4560 06:53:57.533437 10, 0x0, sum = 3
4561 06:53:57.536881 11, 0x0, sum = 4
4562 06:53:57.536983 best_step = 9
4563 06:53:57.537075
4564 06:53:57.537162 ==
4565 06:53:57.539868 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 06:53:57.546587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 06:53:57.546668 ==
4568 06:53:57.546731 RX Vref Scan: 1
4569 06:53:57.546790
4570 06:53:57.550077 RX Vref 0 -> 0, step: 1
4571 06:53:57.550147
4572 06:53:57.553325 RX Delay -195 -> 252, step: 8
4573 06:53:57.553396
4574 06:53:57.556576 Set Vref, RX VrefLevel [Byte0]: 55
4575 06:53:57.559984 [Byte1]: 53
4576 06:53:57.560059
4577 06:53:57.562940 Final RX Vref Byte 0 = 55 to rank0
4578 06:53:57.566766 Final RX Vref Byte 1 = 53 to rank0
4579 06:53:57.569697 Final RX Vref Byte 0 = 55 to rank1
4580 06:53:57.573123 Final RX Vref Byte 1 = 53 to rank1==
4581 06:53:57.576727 Dram Type= 6, Freq= 0, CH_1, rank 0
4582 06:53:57.579927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 06:53:57.580010 ==
4584 06:53:57.582992 DQS Delay:
4585 06:53:57.583069 DQS0 = 0, DQS1 = 0
4586 06:53:57.583130 DQM Delay:
4587 06:53:57.586306 DQM0 = 41, DQM1 = 33
4588 06:53:57.586377 DQ Delay:
4589 06:53:57.590107 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4590 06:53:57.593447 DQ4 =40, DQ5 =52, DQ6 =52, DQ7 =36
4591 06:53:57.596480 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4592 06:53:57.600202 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4593 06:53:57.600299
4594 06:53:57.600388
4595 06:53:57.609664 [DQSOSCAuto] RK0, (LSB)MR18= 0x450c, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4596 06:53:57.613021 CH1 RK0: MR19=808, MR18=450C
4597 06:53:57.616215 CH1_RK0: MR19=0x808, MR18=0x450C, DQSOSC=396, MR23=63, INC=167, DEC=111
4598 06:53:57.616314
4599 06:53:57.619787 ----->DramcWriteLeveling(PI) begin...
4600 06:53:57.623046 ==
4601 06:53:57.626151 Dram Type= 6, Freq= 0, CH_1, rank 1
4602 06:53:57.629645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 06:53:57.629755 ==
4604 06:53:57.633193 Write leveling (Byte 0): 30 => 30
4605 06:53:57.637025 Write leveling (Byte 1): 30 => 30
4606 06:53:57.639909 DramcWriteLeveling(PI) end<-----
4607 06:53:57.640009
4608 06:53:57.640099 ==
4609 06:53:57.643192 Dram Type= 6, Freq= 0, CH_1, rank 1
4610 06:53:57.646302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 06:53:57.646400 ==
4612 06:53:57.649824 [Gating] SW mode calibration
4613 06:53:57.656589 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4614 06:53:57.660256 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4615 06:53:57.666476 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4616 06:53:57.669794 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4617 06:53:57.673205 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4618 06:53:57.680145 0 9 12 | B1->B0 | 3333 2b2b | 1 1 | (1 1) (1 0)
4619 06:53:57.683050 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
4620 06:53:57.686615 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4621 06:53:57.692997 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 06:53:57.696635 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 06:53:57.699944 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 06:53:57.706241 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 06:53:57.709622 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 06:53:57.712841 0 10 12 | B1->B0 | 3232 4141 | 0 0 | (1 1) (1 1)
4627 06:53:57.719350 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4628 06:53:57.723150 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 06:53:57.726019 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 06:53:57.733273 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 06:53:57.736213 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 06:53:57.739404 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 06:53:57.746296 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 06:53:57.750013 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4635 06:53:57.752827 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 06:53:57.759665 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 06:53:57.762718 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 06:53:57.766446 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 06:53:57.772615 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 06:53:57.776237 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 06:53:57.779663 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 06:53:57.783144 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 06:53:57.789749 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 06:53:57.793454 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 06:53:57.796156 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 06:53:57.802744 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 06:53:57.806356 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 06:53:57.809517 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 06:53:57.816007 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 06:53:57.819589 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4651 06:53:57.822918 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 06:53:57.825933 Total UI for P1: 0, mck2ui 16
4653 06:53:57.829772 best dqsien dly found for B0: ( 0, 13, 12)
4654 06:53:57.832685 Total UI for P1: 0, mck2ui 16
4655 06:53:57.835930 best dqsien dly found for B1: ( 0, 13, 14)
4656 06:53:57.839477 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4657 06:53:57.842867 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4658 06:53:57.842946
4659 06:53:57.849629 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4660 06:53:57.853259 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4661 06:53:57.853333 [Gating] SW calibration Done
4662 06:53:57.856539 ==
4663 06:53:57.859592 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 06:53:57.863267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 06:53:57.863374 ==
4666 06:53:57.863466 RX Vref Scan: 0
4667 06:53:57.863566
4668 06:53:57.866133 RX Vref 0 -> 0, step: 1
4669 06:53:57.866232
4670 06:53:57.869263 RX Delay -230 -> 252, step: 16
4671 06:53:57.872868 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4672 06:53:57.875926 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4673 06:53:57.882908 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4674 06:53:57.886032 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4675 06:53:57.889638 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4676 06:53:57.893090 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4677 06:53:57.895805 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4678 06:53:57.902961 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4679 06:53:57.906063 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4680 06:53:57.909333 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4681 06:53:57.912858 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4682 06:53:57.919459 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4683 06:53:57.922306 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4684 06:53:57.925858 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4685 06:53:57.929779 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4686 06:53:57.936327 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4687 06:53:57.936426 ==
4688 06:53:57.939449 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 06:53:57.942358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 06:53:57.942430 ==
4691 06:53:57.942509 DQS Delay:
4692 06:53:57.946219 DQS0 = 0, DQS1 = 0
4693 06:53:57.946335 DQM Delay:
4694 06:53:57.949094 DQM0 = 40, DQM1 = 37
4695 06:53:57.949197 DQ Delay:
4696 06:53:57.952487 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4697 06:53:57.955817 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =33
4698 06:53:57.958914 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4699 06:53:57.962475 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4700 06:53:57.962574
4701 06:53:57.962718
4702 06:53:57.962822 ==
4703 06:53:57.965437 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 06:53:57.969319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 06:53:57.969435 ==
4706 06:53:57.969511
4707 06:53:57.972636
4708 06:53:57.972735 TX Vref Scan disable
4709 06:53:57.975642 == TX Byte 0 ==
4710 06:53:57.978734 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4711 06:53:57.982389 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4712 06:53:57.985582 == TX Byte 1 ==
4713 06:53:57.989303 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4714 06:53:57.992593 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4715 06:53:57.992688 ==
4716 06:53:57.995566 Dram Type= 6, Freq= 0, CH_1, rank 1
4717 06:53:58.002422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4718 06:53:58.002499 ==
4719 06:53:58.002561
4720 06:53:58.002618
4721 06:53:58.002690 TX Vref Scan disable
4722 06:53:58.006721 == TX Byte 0 ==
4723 06:53:58.010024 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4724 06:53:58.016854 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4725 06:53:58.016958 == TX Byte 1 ==
4726 06:53:58.019924 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4727 06:53:58.026529 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4728 06:53:58.026632
4729 06:53:58.026721 [DATLAT]
4730 06:53:58.026809 Freq=600, CH1 RK1
4731 06:53:58.026896
4732 06:53:58.029954 DATLAT Default: 0x9
4733 06:53:58.030030 0, 0xFFFF, sum = 0
4734 06:53:58.033563 1, 0xFFFF, sum = 0
4735 06:53:58.033637 2, 0xFFFF, sum = 0
4736 06:53:58.036591 3, 0xFFFF, sum = 0
4737 06:53:58.036693 4, 0xFFFF, sum = 0
4738 06:53:58.039917 5, 0xFFFF, sum = 0
4739 06:53:58.043117 6, 0xFFFF, sum = 0
4740 06:53:58.043191 7, 0xFFFF, sum = 0
4741 06:53:58.043252 8, 0x0, sum = 1
4742 06:53:58.046636 9, 0x0, sum = 2
4743 06:53:58.046711 10, 0x0, sum = 3
4744 06:53:58.050531 11, 0x0, sum = 4
4745 06:53:58.050604 best_step = 9
4746 06:53:58.050698
4747 06:53:58.050790 ==
4748 06:53:58.053457 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 06:53:58.060071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 06:53:58.060176 ==
4751 06:53:58.060270 RX Vref Scan: 0
4752 06:53:58.060356
4753 06:53:58.063551 RX Vref 0 -> 0, step: 1
4754 06:53:58.063629
4755 06:53:58.066876 RX Delay -179 -> 252, step: 8
4756 06:53:58.070087 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4757 06:53:58.076857 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4758 06:53:58.079892 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4759 06:53:58.083428 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4760 06:53:58.086529 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4761 06:53:58.090172 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4762 06:53:58.096766 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4763 06:53:58.099903 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4764 06:53:58.103127 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4765 06:53:58.106720 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4766 06:53:58.113459 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4767 06:53:58.116634 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4768 06:53:58.119960 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4769 06:53:58.123264 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4770 06:53:58.126639 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4771 06:53:58.133187 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4772 06:53:58.133299 ==
4773 06:53:58.136534 Dram Type= 6, Freq= 0, CH_1, rank 1
4774 06:53:58.139774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4775 06:53:58.139874 ==
4776 06:53:58.139971 DQS Delay:
4777 06:53:58.143246 DQS0 = 0, DQS1 = 0
4778 06:53:58.143323 DQM Delay:
4779 06:53:58.146689 DQM0 = 37, DQM1 = 32
4780 06:53:58.146802 DQ Delay:
4781 06:53:58.149959 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4782 06:53:58.153326 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4783 06:53:58.156325 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4784 06:53:58.160043 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4785 06:53:58.160123
4786 06:53:58.160185
4787 06:53:58.169774 [DQSOSCAuto] RK1, (LSB)MR18= 0x3644, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4788 06:53:58.169886 CH1 RK1: MR19=808, MR18=3644
4789 06:53:58.176184 CH1_RK1: MR19=0x808, MR18=0x3644, DQSOSC=396, MR23=63, INC=167, DEC=111
4790 06:53:58.179736 [RxdqsGatingPostProcess] freq 600
4791 06:53:58.186343 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4792 06:53:58.190011 Pre-setting of DQS Precalculation
4793 06:53:58.192945 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4794 06:53:58.199559 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4795 06:53:58.209291 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4796 06:53:58.209393
4797 06:53:58.209490
4798 06:53:58.212907 [Calibration Summary] 1200 Mbps
4799 06:53:58.213011 CH 0, Rank 0
4800 06:53:58.215928 SW Impedance : PASS
4801 06:53:58.216026 DUTY Scan : NO K
4802 06:53:58.219533 ZQ Calibration : PASS
4803 06:53:58.219632 Jitter Meter : NO K
4804 06:53:58.222835 CBT Training : PASS
4805 06:53:58.226381 Write leveling : PASS
4806 06:53:58.226462 RX DQS gating : PASS
4807 06:53:58.229450 RX DQ/DQS(RDDQC) : PASS
4808 06:53:58.232626 TX DQ/DQS : PASS
4809 06:53:58.232729 RX DATLAT : PASS
4810 06:53:58.236046 RX DQ/DQS(Engine): PASS
4811 06:53:58.239403 TX OE : NO K
4812 06:53:58.239502 All Pass.
4813 06:53:58.239589
4814 06:53:58.239685 CH 0, Rank 1
4815 06:53:58.242784 SW Impedance : PASS
4816 06:53:58.246297 DUTY Scan : NO K
4817 06:53:58.246395 ZQ Calibration : PASS
4818 06:53:58.249016 Jitter Meter : NO K
4819 06:53:58.252426 CBT Training : PASS
4820 06:53:58.252499 Write leveling : PASS
4821 06:53:58.255899 RX DQS gating : PASS
4822 06:53:58.259362 RX DQ/DQS(RDDQC) : PASS
4823 06:53:58.259459 TX DQ/DQS : PASS
4824 06:53:58.262518 RX DATLAT : PASS
4825 06:53:58.265741 RX DQ/DQS(Engine): PASS
4826 06:53:58.265826 TX OE : NO K
4827 06:53:58.265889 All Pass.
4828 06:53:58.269031
4829 06:53:58.269124 CH 1, Rank 0
4830 06:53:58.272195 SW Impedance : PASS
4831 06:53:58.272301 DUTY Scan : NO K
4832 06:53:58.275800 ZQ Calibration : PASS
4833 06:53:58.275901 Jitter Meter : NO K
4834 06:53:58.279018 CBT Training : PASS
4835 06:53:58.282397 Write leveling : PASS
4836 06:53:58.282467 RX DQS gating : PASS
4837 06:53:58.285922 RX DQ/DQS(RDDQC) : PASS
4838 06:53:58.288782 TX DQ/DQS : PASS
4839 06:53:58.288878 RX DATLAT : PASS
4840 06:53:58.292231 RX DQ/DQS(Engine): PASS
4841 06:53:58.296278 TX OE : NO K
4842 06:53:58.296350 All Pass.
4843 06:53:58.296410
4844 06:53:58.296481 CH 1, Rank 1
4845 06:53:58.299233 SW Impedance : PASS
4846 06:53:58.302804 DUTY Scan : NO K
4847 06:53:58.302892 ZQ Calibration : PASS
4848 06:53:58.305991 Jitter Meter : NO K
4849 06:53:58.309533 CBT Training : PASS
4850 06:53:58.309605 Write leveling : PASS
4851 06:53:58.312854 RX DQS gating : PASS
4852 06:53:58.312951 RX DQ/DQS(RDDQC) : PASS
4853 06:53:58.315647 TX DQ/DQS : PASS
4854 06:53:58.319363 RX DATLAT : PASS
4855 06:53:58.319462 RX DQ/DQS(Engine): PASS
4856 06:53:58.322573 TX OE : NO K
4857 06:53:58.322644 All Pass.
4858 06:53:58.322720
4859 06:53:58.325545 DramC Write-DBI off
4860 06:53:58.329166 PER_BANK_REFRESH: Hybrid Mode
4861 06:53:58.329305 TX_TRACKING: ON
4862 06:53:58.339103 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4863 06:53:58.342108 [FAST_K] Save calibration result to emmc
4864 06:53:58.345576 dramc_set_vcore_voltage set vcore to 662500
4865 06:53:58.349252 Read voltage for 933, 3
4866 06:53:58.349337 Vio18 = 0
4867 06:53:58.349424 Vcore = 662500
4868 06:53:58.352415 Vdram = 0
4869 06:53:58.352484 Vddq = 0
4870 06:53:58.352557 Vmddr = 0
4871 06:53:58.359022 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4872 06:53:58.362580 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4873 06:53:58.365458 MEM_TYPE=3, freq_sel=17
4874 06:53:58.368904 sv_algorithm_assistance_LP4_1600
4875 06:53:58.372409 ============ PULL DRAM RESETB DOWN ============
4876 06:53:58.375801 ========== PULL DRAM RESETB DOWN end =========
4877 06:53:58.382417 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4878 06:53:58.385434 ===================================
4879 06:53:58.389199 LPDDR4 DRAM CONFIGURATION
4880 06:53:58.392365 ===================================
4881 06:53:58.392444 EX_ROW_EN[0] = 0x0
4882 06:53:58.395976 EX_ROW_EN[1] = 0x0
4883 06:53:58.396052 LP4Y_EN = 0x0
4884 06:53:58.399095 WORK_FSP = 0x0
4885 06:53:58.399168 WL = 0x3
4886 06:53:58.402176 RL = 0x3
4887 06:53:58.402281 BL = 0x2
4888 06:53:58.406210 RPST = 0x0
4889 06:53:58.406291 RD_PRE = 0x0
4890 06:53:58.408917 WR_PRE = 0x1
4891 06:53:58.409013 WR_PST = 0x0
4892 06:53:58.412853 DBI_WR = 0x0
4893 06:53:58.412949 DBI_RD = 0x0
4894 06:53:58.415907 OTF = 0x1
4895 06:53:58.419361 ===================================
4896 06:53:58.422378 ===================================
4897 06:53:58.422475 ANA top config
4898 06:53:58.425532 ===================================
4899 06:53:58.429085 DLL_ASYNC_EN = 0
4900 06:53:58.432159 ALL_SLAVE_EN = 1
4901 06:53:58.435790 NEW_RANK_MODE = 1
4902 06:53:58.435868 DLL_IDLE_MODE = 1
4903 06:53:58.438842 LP45_APHY_COMB_EN = 1
4904 06:53:58.442644 TX_ODT_DIS = 1
4905 06:53:58.445449 NEW_8X_MODE = 1
4906 06:53:58.449105 ===================================
4907 06:53:58.452407 ===================================
4908 06:53:58.456011 data_rate = 1866
4909 06:53:58.456112 CKR = 1
4910 06:53:58.458886 DQ_P2S_RATIO = 8
4911 06:53:58.462444 ===================================
4912 06:53:58.465605 CA_P2S_RATIO = 8
4913 06:53:58.469233 DQ_CA_OPEN = 0
4914 06:53:58.472418 DQ_SEMI_OPEN = 0
4915 06:53:58.472528 CA_SEMI_OPEN = 0
4916 06:53:58.476095 CA_FULL_RATE = 0
4917 06:53:58.479284 DQ_CKDIV4_EN = 1
4918 06:53:58.482787 CA_CKDIV4_EN = 1
4919 06:53:58.485885 CA_PREDIV_EN = 0
4920 06:53:58.489434 PH8_DLY = 0
4921 06:53:58.489532 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4922 06:53:58.492763 DQ_AAMCK_DIV = 4
4923 06:53:58.495854 CA_AAMCK_DIV = 4
4924 06:53:58.499072 CA_ADMCK_DIV = 4
4925 06:53:58.502301 DQ_TRACK_CA_EN = 0
4926 06:53:58.506056 CA_PICK = 933
4927 06:53:58.506160 CA_MCKIO = 933
4928 06:53:58.509320 MCKIO_SEMI = 0
4929 06:53:58.512558 PLL_FREQ = 3732
4930 06:53:58.515798 DQ_UI_PI_RATIO = 32
4931 06:53:58.518964 CA_UI_PI_RATIO = 0
4932 06:53:58.522273 ===================================
4933 06:53:58.525573 ===================================
4934 06:53:58.529189 memory_type:LPDDR4
4935 06:53:58.529337 GP_NUM : 10
4936 06:53:58.532694 SRAM_EN : 1
4937 06:53:58.532803 MD32_EN : 0
4938 06:53:58.536110 ===================================
4939 06:53:58.539343 [ANA_INIT] >>>>>>>>>>>>>>
4940 06:53:58.542803 <<<<<< [CONFIGURE PHASE]: ANA_TX
4941 06:53:58.545827 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4942 06:53:58.549426 ===================================
4943 06:53:58.552759 data_rate = 1866,PCW = 0X8f00
4944 06:53:58.555847 ===================================
4945 06:53:58.559469 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4946 06:53:58.562664 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4947 06:53:58.569682 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4948 06:53:58.572963 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4949 06:53:58.575930 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4950 06:53:58.582676 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4951 06:53:58.582781 [ANA_INIT] flow start
4952 06:53:58.586295 [ANA_INIT] PLL >>>>>>>>
4953 06:53:58.586399 [ANA_INIT] PLL <<<<<<<<
4954 06:53:58.589338 [ANA_INIT] MIDPI >>>>>>>>
4955 06:53:58.592896 [ANA_INIT] MIDPI <<<<<<<<
4956 06:53:58.595927 [ANA_INIT] DLL >>>>>>>>
4957 06:53:58.596031 [ANA_INIT] flow end
4958 06:53:58.598981 ============ LP4 DIFF to SE enter ============
4959 06:53:58.605906 ============ LP4 DIFF to SE exit ============
4960 06:53:58.606016 [ANA_INIT] <<<<<<<<<<<<<
4961 06:53:58.609749 [Flow] Enable top DCM control >>>>>
4962 06:53:58.612944 [Flow] Enable top DCM control <<<<<
4963 06:53:58.615792 Enable DLL master slave shuffle
4964 06:53:58.622996 ==============================================================
4965 06:53:58.623101 Gating Mode config
4966 06:53:58.629053 ==============================================================
4967 06:53:58.632710 Config description:
4968 06:53:58.642236 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4969 06:53:58.649084 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4970 06:53:58.652712 SELPH_MODE 0: By rank 1: By Phase
4971 06:53:58.659309 ==============================================================
4972 06:53:58.662657 GAT_TRACK_EN = 1
4973 06:53:58.666096 RX_GATING_MODE = 2
4974 06:53:58.666192 RX_GATING_TRACK_MODE = 2
4975 06:53:58.668956 SELPH_MODE = 1
4976 06:53:58.672566 PICG_EARLY_EN = 1
4977 06:53:58.675740 VALID_LAT_VALUE = 1
4978 06:53:58.682578 ==============================================================
4979 06:53:58.686171 Enter into Gating configuration >>>>
4980 06:53:58.689391 Exit from Gating configuration <<<<
4981 06:53:58.692865 Enter into DVFS_PRE_config >>>>>
4982 06:53:58.702619 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4983 06:53:58.706272 Exit from DVFS_PRE_config <<<<<
4984 06:53:58.709351 Enter into PICG configuration >>>>
4985 06:53:58.712463 Exit from PICG configuration <<<<
4986 06:53:58.715966 [RX_INPUT] configuration >>>>>
4987 06:53:58.716067 [RX_INPUT] configuration <<<<<
4988 06:53:58.722444 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4989 06:53:58.729467 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4990 06:53:58.736362 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4991 06:53:58.739142 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4992 06:53:58.745812 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4993 06:53:58.752343 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4994 06:53:58.756014 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4995 06:53:58.759176 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4996 06:53:58.765709 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4997 06:53:58.769291 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4998 06:53:58.772485 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4999 06:53:58.779448 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5000 06:53:58.782582 ===================================
5001 06:53:58.782674 LPDDR4 DRAM CONFIGURATION
5002 06:53:58.786157 ===================================
5003 06:53:58.789074 EX_ROW_EN[0] = 0x0
5004 06:53:58.789176 EX_ROW_EN[1] = 0x0
5005 06:53:58.792697 LP4Y_EN = 0x0
5006 06:53:58.792795 WORK_FSP = 0x0
5007 06:53:58.795869 WL = 0x3
5008 06:53:58.795939 RL = 0x3
5009 06:53:58.799569 BL = 0x2
5010 06:53:58.802525 RPST = 0x0
5011 06:53:58.802621 RD_PRE = 0x0
5012 06:53:58.805705 WR_PRE = 0x1
5013 06:53:58.805776 WR_PST = 0x0
5014 06:53:58.809304 DBI_WR = 0x0
5015 06:53:58.809394 DBI_RD = 0x0
5016 06:53:58.812237 OTF = 0x1
5017 06:53:58.816047 ===================================
5018 06:53:58.819442 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5019 06:53:58.822552 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5020 06:53:58.825892 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5021 06:53:58.829024 ===================================
5022 06:53:58.832344 LPDDR4 DRAM CONFIGURATION
5023 06:53:58.836188 ===================================
5024 06:53:58.838861 EX_ROW_EN[0] = 0x10
5025 06:53:58.838944 EX_ROW_EN[1] = 0x0
5026 06:53:58.842610 LP4Y_EN = 0x0
5027 06:53:58.842679 WORK_FSP = 0x0
5028 06:53:58.845748 WL = 0x3
5029 06:53:58.845840 RL = 0x3
5030 06:53:58.849347 BL = 0x2
5031 06:53:58.849431 RPST = 0x0
5032 06:53:58.852406 RD_PRE = 0x0
5033 06:53:58.852506 WR_PRE = 0x1
5034 06:53:58.855717 WR_PST = 0x0
5035 06:53:58.859495 DBI_WR = 0x0
5036 06:53:58.859576 DBI_RD = 0x0
5037 06:53:58.862284 OTF = 0x1
5038 06:53:58.866071 ===================================
5039 06:53:58.869010 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5040 06:53:58.874438 nWR fixed to 30
5041 06:53:58.877304 [ModeRegInit_LP4] CH0 RK0
5042 06:53:58.877387 [ModeRegInit_LP4] CH0 RK1
5043 06:53:58.880874 [ModeRegInit_LP4] CH1 RK0
5044 06:53:58.884136 [ModeRegInit_LP4] CH1 RK1
5045 06:53:58.884235 match AC timing 9
5046 06:53:58.890981 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5047 06:53:58.894635 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5048 06:53:58.897137 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5049 06:53:58.904318 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5050 06:53:58.907149 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5051 06:53:58.907272 ==
5052 06:53:58.911089 Dram Type= 6, Freq= 0, CH_0, rank 0
5053 06:53:58.914053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5054 06:53:58.914152 ==
5055 06:53:58.921306 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5056 06:53:58.927894 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5057 06:53:58.930710 [CA 0] Center 38 (7~69) winsize 63
5058 06:53:58.934076 [CA 1] Center 38 (7~69) winsize 63
5059 06:53:58.937640 [CA 2] Center 35 (5~66) winsize 62
5060 06:53:58.940604 [CA 3] Center 35 (5~65) winsize 61
5061 06:53:58.944485 [CA 4] Center 34 (4~64) winsize 61
5062 06:53:58.947378 [CA 5] Center 33 (3~64) winsize 62
5063 06:53:58.947449
5064 06:53:58.951142 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5065 06:53:58.951211
5066 06:53:58.954056 [CATrainingPosCal] consider 1 rank data
5067 06:53:58.957589 u2DelayCellTimex100 = 270/100 ps
5068 06:53:58.961213 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5069 06:53:58.964096 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5070 06:53:58.967899 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5071 06:53:58.970853 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5072 06:53:58.974554 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5073 06:53:58.977585 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5074 06:53:58.977661
5075 06:53:58.984332 CA PerBit enable=1, Macro0, CA PI delay=33
5076 06:53:58.984432
5077 06:53:58.984528 [CBTSetCACLKResult] CA Dly = 33
5078 06:53:58.987469 CS Dly: 6 (0~37)
5079 06:53:58.987547 ==
5080 06:53:58.990890 Dram Type= 6, Freq= 0, CH_0, rank 1
5081 06:53:58.994249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5082 06:53:58.994324 ==
5083 06:53:59.000754 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5084 06:53:59.007391 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5085 06:53:59.010965 [CA 0] Center 38 (8~69) winsize 62
5086 06:53:59.014473 [CA 1] Center 38 (7~69) winsize 63
5087 06:53:59.017467 [CA 2] Center 35 (5~66) winsize 62
5088 06:53:59.021306 [CA 3] Center 35 (4~66) winsize 63
5089 06:53:59.024060 [CA 4] Center 34 (4~64) winsize 61
5090 06:53:59.027614 [CA 5] Center 33 (3~64) winsize 62
5091 06:53:59.027723
5092 06:53:59.030945 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5093 06:53:59.031060
5094 06:53:59.034589 [CATrainingPosCal] consider 2 rank data
5095 06:53:59.037556 u2DelayCellTimex100 = 270/100 ps
5096 06:53:59.040922 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5097 06:53:59.044231 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5098 06:53:59.047447 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5099 06:53:59.050491 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5100 06:53:59.054194 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5101 06:53:59.057712 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5102 06:53:59.057785
5103 06:53:59.064174 CA PerBit enable=1, Macro0, CA PI delay=33
5104 06:53:59.064256
5105 06:53:59.067199 [CBTSetCACLKResult] CA Dly = 33
5106 06:53:59.067294 CS Dly: 7 (0~39)
5107 06:53:59.067380
5108 06:53:59.070827 ----->DramcWriteLeveling(PI) begin...
5109 06:53:59.070902 ==
5110 06:53:59.073961 Dram Type= 6, Freq= 0, CH_0, rank 0
5111 06:53:59.077610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5112 06:53:59.077688 ==
5113 06:53:59.080733 Write leveling (Byte 0): 32 => 32
5114 06:53:59.084250 Write leveling (Byte 1): 25 => 25
5115 06:53:59.087352 DramcWriteLeveling(PI) end<-----
5116 06:53:59.087435
5117 06:53:59.087496 ==
5118 06:53:59.090485 Dram Type= 6, Freq= 0, CH_0, rank 0
5119 06:53:59.097272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5120 06:53:59.097346 ==
5121 06:53:59.097427 [Gating] SW mode calibration
5122 06:53:59.107235 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5123 06:53:59.110812 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5124 06:53:59.114301 0 14 0 | B1->B0 | 2323 2a2a | 1 0 | (1 1) (0 0)
5125 06:53:59.120837 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5126 06:53:59.123835 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 06:53:59.127603 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 06:53:59.134202 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 06:53:59.137394 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 06:53:59.140779 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 06:53:59.147381 0 14 28 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
5132 06:53:59.150729 0 15 0 | B1->B0 | 3030 2525 | 0 0 | (0 0) (0 1)
5133 06:53:59.154238 0 15 4 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
5134 06:53:59.160658 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 06:53:59.164303 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 06:53:59.167738 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 06:53:59.174422 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 06:53:59.177635 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 06:53:59.180574 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5140 06:53:59.184268 1 0 0 | B1->B0 | 3434 3a3a | 0 0 | (0 0) (0 0)
5141 06:53:59.190925 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5142 06:53:59.194789 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 06:53:59.197675 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 06:53:59.204380 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 06:53:59.207451 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 06:53:59.211102 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 06:53:59.217526 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 06:53:59.221000 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5149 06:53:59.224497 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5150 06:53:59.231391 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 06:53:59.234477 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 06:53:59.237603 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 06:53:59.240911 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 06:53:59.247600 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 06:53:59.251464 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 06:53:59.254314 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 06:53:59.261201 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 06:53:59.264743 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 06:53:59.267753 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 06:53:59.274274 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 06:53:59.277632 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 06:53:59.280855 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 06:53:59.287393 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5164 06:53:59.290655 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5165 06:53:59.294220 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5166 06:53:59.297711 Total UI for P1: 0, mck2ui 16
5167 06:53:59.300861 best dqsien dly found for B0: ( 1, 2, 30)
5168 06:53:59.307808 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 06:53:59.307885 Total UI for P1: 0, mck2ui 16
5170 06:53:59.314531 best dqsien dly found for B1: ( 1, 3, 0)
5171 06:53:59.317583 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5172 06:53:59.320865 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5173 06:53:59.320969
5174 06:53:59.323783 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5175 06:53:59.327081 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5176 06:53:59.330641 [Gating] SW calibration Done
5177 06:53:59.330745 ==
5178 06:53:59.334286 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 06:53:59.337359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 06:53:59.337445 ==
5181 06:53:59.340631 RX Vref Scan: 0
5182 06:53:59.340729
5183 06:53:59.340828 RX Vref 0 -> 0, step: 1
5184 06:53:59.340917
5185 06:53:59.344299 RX Delay -80 -> 252, step: 8
5186 06:53:59.347166 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5187 06:53:59.354405 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5188 06:53:59.357380 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5189 06:53:59.361161 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5190 06:53:59.363986 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5191 06:53:59.367206 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5192 06:53:59.370656 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5193 06:53:59.374222 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5194 06:53:59.380740 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5195 06:53:59.384093 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5196 06:53:59.387607 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5197 06:53:59.390919 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5198 06:53:59.393885 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5199 06:53:59.400964 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5200 06:53:59.403927 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5201 06:53:59.407789 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5202 06:53:59.407892 ==
5203 06:53:59.410746 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 06:53:59.414332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 06:53:59.414406 ==
5206 06:53:59.417582 DQS Delay:
5207 06:53:59.417677 DQS0 = 0, DQS1 = 0
5208 06:53:59.417764 DQM Delay:
5209 06:53:59.420769 DQM0 = 98, DQM1 = 88
5210 06:53:59.420859 DQ Delay:
5211 06:53:59.424157 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5212 06:53:59.427309 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5213 06:53:59.430629 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5214 06:53:59.434209 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5215 06:53:59.434286
5216 06:53:59.434347
5217 06:53:59.434403 ==
5218 06:53:59.437474 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 06:53:59.443910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 06:53:59.443985 ==
5221 06:53:59.444046
5222 06:53:59.444103
5223 06:53:59.444157 TX Vref Scan disable
5224 06:53:59.448330 == TX Byte 0 ==
5225 06:53:59.451148 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5226 06:53:59.454675 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5227 06:53:59.457837 == TX Byte 1 ==
5228 06:53:59.460862 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5229 06:53:59.467561 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5230 06:53:59.467641 ==
5231 06:53:59.471328 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 06:53:59.474852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 06:53:59.474931 ==
5234 06:53:59.474993
5235 06:53:59.475051
5236 06:53:59.477867 TX Vref Scan disable
5237 06:53:59.477940 == TX Byte 0 ==
5238 06:53:59.484645 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5239 06:53:59.487600 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5240 06:53:59.487700 == TX Byte 1 ==
5241 06:53:59.494550 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5242 06:53:59.497585 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5243 06:53:59.497685
5244 06:53:59.497774 [DATLAT]
5245 06:53:59.501061 Freq=933, CH0 RK0
5246 06:53:59.501158
5247 06:53:59.501279 DATLAT Default: 0xd
5248 06:53:59.504723 0, 0xFFFF, sum = 0
5249 06:53:59.504798 1, 0xFFFF, sum = 0
5250 06:53:59.507981 2, 0xFFFF, sum = 0
5251 06:53:59.508080 3, 0xFFFF, sum = 0
5252 06:53:59.511125 4, 0xFFFF, sum = 0
5253 06:53:59.511198 5, 0xFFFF, sum = 0
5254 06:53:59.514999 6, 0xFFFF, sum = 0
5255 06:53:59.515074 7, 0xFFFF, sum = 0
5256 06:53:59.518058 8, 0xFFFF, sum = 0
5257 06:53:59.520928 9, 0xFFFF, sum = 0
5258 06:53:59.521024 10, 0x0, sum = 1
5259 06:53:59.521113 11, 0x0, sum = 2
5260 06:53:59.524751 12, 0x0, sum = 3
5261 06:53:59.524851 13, 0x0, sum = 4
5262 06:53:59.527824 best_step = 11
5263 06:53:59.527917
5264 06:53:59.528004 ==
5265 06:53:59.531427 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 06:53:59.534310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 06:53:59.534386 ==
5268 06:53:59.537967 RX Vref Scan: 1
5269 06:53:59.538039
5270 06:53:59.538103 RX Vref 0 -> 0, step: 1
5271 06:53:59.538160
5272 06:53:59.541105 RX Delay -61 -> 252, step: 4
5273 06:53:59.541202
5274 06:53:59.544394 Set Vref, RX VrefLevel [Byte0]: 54
5275 06:53:59.547534 [Byte1]: 51
5276 06:53:59.552205
5277 06:53:59.552303 Final RX Vref Byte 0 = 54 to rank0
5278 06:53:59.555520 Final RX Vref Byte 1 = 51 to rank0
5279 06:53:59.558358 Final RX Vref Byte 0 = 54 to rank1
5280 06:53:59.561544 Final RX Vref Byte 1 = 51 to rank1==
5281 06:53:59.565524 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 06:53:59.571599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 06:53:59.571701 ==
5284 06:53:59.571792 DQS Delay:
5285 06:53:59.571884 DQS0 = 0, DQS1 = 0
5286 06:53:59.575065 DQM Delay:
5287 06:53:59.575169 DQM0 = 97, DQM1 = 88
5288 06:53:59.578353 DQ Delay:
5289 06:53:59.581735 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5290 06:53:59.585367 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =102
5291 06:53:59.588579 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =82
5292 06:53:59.591543 DQ12 =94, DQ13 =92, DQ14 =100, DQ15 =98
5293 06:53:59.591627
5294 06:53:59.591689
5295 06:53:59.598097 [DQSOSCAuto] RK0, (LSB)MR18= 0x1400, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5296 06:53:59.601608 CH0 RK0: MR19=505, MR18=1400
5297 06:53:59.608787 CH0_RK0: MR19=0x505, MR18=0x1400, DQSOSC=415, MR23=63, INC=62, DEC=41
5298 06:53:59.608949
5299 06:53:59.611704 ----->DramcWriteLeveling(PI) begin...
5300 06:53:59.611808 ==
5301 06:53:59.614880 Dram Type= 6, Freq= 0, CH_0, rank 1
5302 06:53:59.618317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 06:53:59.618429 ==
5304 06:53:59.621361 Write leveling (Byte 0): 29 => 29
5305 06:53:59.624642 Write leveling (Byte 1): 26 => 26
5306 06:53:59.628499 DramcWriteLeveling(PI) end<-----
5307 06:53:59.628600
5308 06:53:59.628692 ==
5309 06:53:59.631482 Dram Type= 6, Freq= 0, CH_0, rank 1
5310 06:53:59.634976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 06:53:59.635076 ==
5312 06:53:59.638256 [Gating] SW mode calibration
5313 06:53:59.644783 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5314 06:53:59.651589 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5315 06:53:59.654626 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5316 06:53:59.661809 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 06:53:59.664584 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 06:53:59.667937 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 06:53:59.674350 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 06:53:59.677778 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 06:53:59.680980 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5322 06:53:59.687986 0 14 28 | B1->B0 | 3232 2a2a | 1 0 | (1 0) (1 0)
5323 06:53:59.691020 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5324 06:53:59.694723 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 06:53:59.698355 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 06:53:59.704848 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 06:53:59.707772 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 06:53:59.711278 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 06:53:59.717899 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 06:53:59.721424 0 15 28 | B1->B0 | 2a2a 3b3b | 0 1 | (0 0) (0 0)
5331 06:53:59.724724 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5332 06:53:59.731406 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 06:53:59.734700 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 06:53:59.737783 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 06:53:59.744783 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 06:53:59.748130 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 06:53:59.751154 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 06:53:59.758335 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5339 06:53:59.761560 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5340 06:53:59.764933 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 06:53:59.771627 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 06:53:59.774718 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 06:53:59.778320 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 06:53:59.781725 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 06:53:59.787997 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 06:53:59.791646 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 06:53:59.794803 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 06:53:59.801794 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 06:53:59.804681 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 06:53:59.808221 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 06:53:59.815057 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 06:53:59.817856 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 06:53:59.821398 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 06:53:59.828246 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5355 06:53:59.828348 Total UI for P1: 0, mck2ui 16
5356 06:53:59.835019 best dqsien dly found for B0: ( 1, 2, 26)
5357 06:53:59.838008 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5358 06:53:59.841882 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 06:53:59.844852 Total UI for P1: 0, mck2ui 16
5360 06:53:59.848181 best dqsien dly found for B1: ( 1, 2, 30)
5361 06:53:59.851259 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5362 06:53:59.854785 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5363 06:53:59.854883
5364 06:53:59.857830 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5365 06:53:59.864552 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5366 06:53:59.864649 [Gating] SW calibration Done
5367 06:53:59.868090 ==
5368 06:53:59.868185 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 06:53:59.874733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 06:53:59.874819 ==
5371 06:53:59.874879 RX Vref Scan: 0
5372 06:53:59.874936
5373 06:53:59.877931 RX Vref 0 -> 0, step: 1
5374 06:53:59.878005
5375 06:53:59.881494 RX Delay -80 -> 252, step: 8
5376 06:53:59.884565 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5377 06:53:59.888240 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5378 06:53:59.891335 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5379 06:53:59.895202 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5380 06:53:59.901403 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5381 06:53:59.904583 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5382 06:53:59.908330 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5383 06:53:59.911452 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5384 06:53:59.914699 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5385 06:53:59.918202 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5386 06:53:59.924347 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5387 06:53:59.927816 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5388 06:53:59.931570 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5389 06:53:59.934539 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5390 06:53:59.937701 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5391 06:53:59.941313 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5392 06:53:59.944899 ==
5393 06:53:59.948022 Dram Type= 6, Freq= 0, CH_0, rank 1
5394 06:53:59.951686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5395 06:53:59.951758 ==
5396 06:53:59.951818 DQS Delay:
5397 06:53:59.954421 DQS0 = 0, DQS1 = 0
5398 06:53:59.954516 DQM Delay:
5399 06:53:59.958358 DQM0 = 98, DQM1 = 88
5400 06:53:59.958429 DQ Delay:
5401 06:53:59.961404 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5402 06:53:59.964601 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5403 06:53:59.968194 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =79
5404 06:53:59.971490 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =95
5405 06:53:59.971569
5406 06:53:59.971630
5407 06:53:59.971687 ==
5408 06:53:59.974415 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 06:53:59.978121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 06:53:59.978198 ==
5411 06:53:59.978259
5412 06:53:59.978316
5413 06:53:59.981102 TX Vref Scan disable
5414 06:53:59.985071 == TX Byte 0 ==
5415 06:53:59.988139 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5416 06:53:59.991280 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5417 06:53:59.994673 == TX Byte 1 ==
5418 06:53:59.997812 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5419 06:54:00.001542 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5420 06:54:00.001653 ==
5421 06:54:00.005074 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 06:54:00.007993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 06:54:00.011165 ==
5424 06:54:00.011260
5425 06:54:00.011346
5426 06:54:00.011434 TX Vref Scan disable
5427 06:54:00.014787 == TX Byte 0 ==
5428 06:54:00.018321 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5429 06:54:00.021851 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5430 06:54:00.025074 == TX Byte 1 ==
5431 06:54:00.028088 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5432 06:54:00.031411 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5433 06:54:00.034970
5434 06:54:00.035046 [DATLAT]
5435 06:54:00.035109 Freq=933, CH0 RK1
5436 06:54:00.035167
5437 06:54:00.037898 DATLAT Default: 0xb
5438 06:54:00.037972 0, 0xFFFF, sum = 0
5439 06:54:00.041791 1, 0xFFFF, sum = 0
5440 06:54:00.041887 2, 0xFFFF, sum = 0
5441 06:54:00.044582 3, 0xFFFF, sum = 0
5442 06:54:00.044657 4, 0xFFFF, sum = 0
5443 06:54:00.048449 5, 0xFFFF, sum = 0
5444 06:54:00.048524 6, 0xFFFF, sum = 0
5445 06:54:00.051427 7, 0xFFFF, sum = 0
5446 06:54:00.054551 8, 0xFFFF, sum = 0
5447 06:54:00.054622 9, 0xFFFF, sum = 0
5448 06:54:00.058123 10, 0x0, sum = 1
5449 06:54:00.058196 11, 0x0, sum = 2
5450 06:54:00.058255 12, 0x0, sum = 3
5451 06:54:00.062035 13, 0x0, sum = 4
5452 06:54:00.062142 best_step = 11
5453 06:54:00.062232
5454 06:54:00.062316 ==
5455 06:54:00.064850 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 06:54:00.071201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 06:54:00.071275 ==
5458 06:54:00.071337 RX Vref Scan: 0
5459 06:54:00.071397
5460 06:54:00.075066 RX Vref 0 -> 0, step: 1
5461 06:54:00.075136
5462 06:54:00.078117 RX Delay -61 -> 252, step: 4
5463 06:54:00.081255 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5464 06:54:00.087966 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5465 06:54:00.091653 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5466 06:54:00.094795 iDelay=199, Bit 3, Center 96 (3 ~ 190) 188
5467 06:54:00.097878 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5468 06:54:00.101652 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5469 06:54:00.104505 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5470 06:54:00.111238 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5471 06:54:00.114887 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5472 06:54:00.118263 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5473 06:54:00.121346 iDelay=199, Bit 10, Center 90 (3 ~ 178) 176
5474 06:54:00.124880 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5475 06:54:00.128041 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5476 06:54:00.134842 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5477 06:54:00.138114 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5478 06:54:00.141318 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5479 06:54:00.141397 ==
5480 06:54:00.144862 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 06:54:00.147667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 06:54:00.147750 ==
5483 06:54:00.151402 DQS Delay:
5484 06:54:00.151511 DQS0 = 0, DQS1 = 0
5485 06:54:00.151605 DQM Delay:
5486 06:54:00.154690 DQM0 = 96, DQM1 = 87
5487 06:54:00.154788 DQ Delay:
5488 06:54:00.157596 DQ0 =96, DQ1 =96, DQ2 =94, DQ3 =96
5489 06:54:00.161279 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =102
5490 06:54:00.164387 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =78
5491 06:54:00.167611 DQ12 =90, DQ13 =92, DQ14 =96, DQ15 =94
5492 06:54:00.167692
5493 06:54:00.167758
5494 06:54:00.177893 [DQSOSCAuto] RK1, (LSB)MR18= 0x1503, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 415 ps
5495 06:54:00.180952 CH0 RK1: MR19=505, MR18=1503
5496 06:54:00.184449 CH0_RK1: MR19=0x505, MR18=0x1503, DQSOSC=415, MR23=63, INC=62, DEC=41
5497 06:54:00.187635 [RxdqsGatingPostProcess] freq 933
5498 06:54:00.195034 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5499 06:54:00.197720 best DQS0 dly(2T, 0.5T) = (0, 10)
5500 06:54:00.201185 best DQS1 dly(2T, 0.5T) = (0, 11)
5501 06:54:00.204432 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5502 06:54:00.207708 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5503 06:54:00.210911 best DQS0 dly(2T, 0.5T) = (0, 10)
5504 06:54:00.214203 best DQS1 dly(2T, 0.5T) = (0, 10)
5505 06:54:00.218024 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5506 06:54:00.218130 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5507 06:54:00.221475 Pre-setting of DQS Precalculation
5508 06:54:00.227907 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5509 06:54:00.227988 ==
5510 06:54:00.231613 Dram Type= 6, Freq= 0, CH_1, rank 0
5511 06:54:00.234823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5512 06:54:00.234895 ==
5513 06:54:00.241169 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5514 06:54:00.247963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5515 06:54:00.251398 [CA 0] Center 36 (6~67) winsize 62
5516 06:54:00.254514 [CA 1] Center 37 (7~67) winsize 61
5517 06:54:00.257589 [CA 2] Center 34 (4~65) winsize 62
5518 06:54:00.261338 [CA 3] Center 33 (3~64) winsize 62
5519 06:54:00.264742 [CA 4] Center 34 (3~65) winsize 63
5520 06:54:00.267781 [CA 5] Center 33 (3~64) winsize 62
5521 06:54:00.267884
5522 06:54:00.270845 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5523 06:54:00.270942
5524 06:54:00.274607 [CATrainingPosCal] consider 1 rank data
5525 06:54:00.277570 u2DelayCellTimex100 = 270/100 ps
5526 06:54:00.281302 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5527 06:54:00.284296 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5528 06:54:00.287988 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5529 06:54:00.291160 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5530 06:54:00.294591 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5531 06:54:00.297842 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5532 06:54:00.297941
5533 06:54:00.300846 CA PerBit enable=1, Macro0, CA PI delay=33
5534 06:54:00.304620
5535 06:54:00.304727 [CBTSetCACLKResult] CA Dly = 33
5536 06:54:00.307619 CS Dly: 4 (0~35)
5537 06:54:00.307714 ==
5538 06:54:00.311055 Dram Type= 6, Freq= 0, CH_1, rank 1
5539 06:54:00.314080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5540 06:54:00.314196 ==
5541 06:54:00.321137 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5542 06:54:00.327864 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5543 06:54:00.330750 [CA 0] Center 37 (7~67) winsize 61
5544 06:54:00.334341 [CA 1] Center 37 (7~67) winsize 61
5545 06:54:00.337894 [CA 2] Center 34 (3~65) winsize 63
5546 06:54:00.341124 [CA 3] Center 33 (3~64) winsize 62
5547 06:54:00.344276 [CA 4] Center 34 (4~65) winsize 62
5548 06:54:00.347547 [CA 5] Center 33 (3~64) winsize 62
5549 06:54:00.347656
5550 06:54:00.350999 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5551 06:54:00.351098
5552 06:54:00.354247 [CATrainingPosCal] consider 2 rank data
5553 06:54:00.357784 u2DelayCellTimex100 = 270/100 ps
5554 06:54:00.361322 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5555 06:54:00.364567 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5556 06:54:00.367712 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5557 06:54:00.370807 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5558 06:54:00.374547 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5559 06:54:00.377548 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5560 06:54:00.377663
5561 06:54:00.381310 CA PerBit enable=1, Macro0, CA PI delay=33
5562 06:54:00.384388
5563 06:54:00.384492 [CBTSetCACLKResult] CA Dly = 33
5564 06:54:00.387443 CS Dly: 5 (0~38)
5565 06:54:00.387553
5566 06:54:00.391234 ----->DramcWriteLeveling(PI) begin...
5567 06:54:00.391335 ==
5568 06:54:00.394161 Dram Type= 6, Freq= 0, CH_1, rank 0
5569 06:54:00.398012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5570 06:54:00.398143 ==
5571 06:54:00.401123 Write leveling (Byte 0): 25 => 25
5572 06:54:00.403976 Write leveling (Byte 1): 27 => 27
5573 06:54:00.407251 DramcWriteLeveling(PI) end<-----
5574 06:54:00.407351
5575 06:54:00.407438 ==
5576 06:54:00.410756 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 06:54:00.414577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 06:54:00.417786 ==
5579 06:54:00.417860 [Gating] SW mode calibration
5580 06:54:00.424339 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5581 06:54:00.430618 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5582 06:54:00.434366 0 14 0 | B1->B0 | 2f2f 3131 | 0 1 | (0 0) (1 1)
5583 06:54:00.440626 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5584 06:54:00.444179 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 06:54:00.447272 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 06:54:00.453797 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 06:54:00.457719 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 06:54:00.460804 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 06:54:00.467273 0 14 28 | B1->B0 | 2f2f 3131 | 0 0 | (1 0) (0 0)
5590 06:54:00.471087 0 15 0 | B1->B0 | 2626 2525 | 1 1 | (1 0) (1 0)
5591 06:54:00.473877 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 06:54:00.480394 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 06:54:00.483807 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 06:54:00.487415 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 06:54:00.490981 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 06:54:00.497310 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5597 06:54:00.501090 0 15 28 | B1->B0 | 2e2e 2828 | 0 0 | (0 0) (0 0)
5598 06:54:00.504051 1 0 0 | B1->B0 | 4242 3d3d | 0 0 | (0 0) (0 0)
5599 06:54:00.510889 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 06:54:00.513727 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 06:54:00.517363 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 06:54:00.524305 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 06:54:00.527355 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 06:54:00.530740 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 06:54:00.537414 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5606 06:54:00.540516 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 06:54:00.543742 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 06:54:00.550635 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 06:54:00.553852 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 06:54:00.557332 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 06:54:00.564197 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 06:54:00.567559 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 06:54:00.570640 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 06:54:00.577460 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 06:54:00.580951 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 06:54:00.583819 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 06:54:00.590577 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 06:54:00.594067 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 06:54:00.597303 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 06:54:00.600347 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 06:54:00.607272 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5622 06:54:00.610842 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 06:54:00.613860 Total UI for P1: 0, mck2ui 16
5624 06:54:00.617594 best dqsien dly found for B0: ( 1, 2, 28)
5625 06:54:00.620540 Total UI for P1: 0, mck2ui 16
5626 06:54:00.623679 best dqsien dly found for B1: ( 1, 2, 28)
5627 06:54:00.627415 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5628 06:54:00.630527 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5629 06:54:00.630596
5630 06:54:00.633661 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5631 06:54:00.637328 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5632 06:54:00.640603 [Gating] SW calibration Done
5633 06:54:00.640685 ==
5634 06:54:00.643827 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 06:54:00.650310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 06:54:00.650387 ==
5637 06:54:00.650451 RX Vref Scan: 0
5638 06:54:00.650511
5639 06:54:00.653961 RX Vref 0 -> 0, step: 1
5640 06:54:00.654042
5641 06:54:00.656834 RX Delay -80 -> 252, step: 8
5642 06:54:00.660533 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5643 06:54:00.663587 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5644 06:54:00.667292 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5645 06:54:00.670792 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5646 06:54:00.673598 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5647 06:54:00.680740 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5648 06:54:00.683930 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5649 06:54:00.687220 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5650 06:54:00.690455 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5651 06:54:00.694234 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5652 06:54:00.700512 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5653 06:54:00.703799 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5654 06:54:00.706968 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5655 06:54:00.710457 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5656 06:54:00.714038 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5657 06:54:00.717223 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5658 06:54:00.717309 ==
5659 06:54:00.720668 Dram Type= 6, Freq= 0, CH_1, rank 0
5660 06:54:00.727185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5661 06:54:00.727268 ==
5662 06:54:00.727352 DQS Delay:
5663 06:54:00.730255 DQS0 = 0, DQS1 = 0
5664 06:54:00.730337 DQM Delay:
5665 06:54:00.730403 DQM0 = 95, DQM1 = 88
5666 06:54:00.733878 DQ Delay:
5667 06:54:00.737102 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5668 06:54:00.740746 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5669 06:54:00.743706 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5670 06:54:00.746869 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5671 06:54:00.746952
5672 06:54:00.747022
5673 06:54:00.747083 ==
5674 06:54:00.750696 Dram Type= 6, Freq= 0, CH_1, rank 0
5675 06:54:00.753698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5676 06:54:00.753781 ==
5677 06:54:00.753846
5678 06:54:00.753907
5679 06:54:00.756939 TX Vref Scan disable
5680 06:54:00.760319 == TX Byte 0 ==
5681 06:54:00.764039 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5682 06:54:00.767015 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5683 06:54:00.770643 == TX Byte 1 ==
5684 06:54:00.773829 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5685 06:54:00.777091 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5686 06:54:00.777173 ==
5687 06:54:00.780572 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 06:54:00.783715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 06:54:00.783825 ==
5690 06:54:00.787503
5691 06:54:00.787610
5692 06:54:00.787702 TX Vref Scan disable
5693 06:54:00.790294 == TX Byte 0 ==
5694 06:54:00.793693 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5695 06:54:00.800377 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5696 06:54:00.800480 == TX Byte 1 ==
5697 06:54:00.804025 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5698 06:54:00.806899 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5699 06:54:00.810500
5700 06:54:00.810609 [DATLAT]
5701 06:54:00.810702 Freq=933, CH1 RK0
5702 06:54:00.810799
5703 06:54:00.814058 DATLAT Default: 0xd
5704 06:54:00.814130 0, 0xFFFF, sum = 0
5705 06:54:00.817247 1, 0xFFFF, sum = 0
5706 06:54:00.817333 2, 0xFFFF, sum = 0
5707 06:54:00.820646 3, 0xFFFF, sum = 0
5708 06:54:00.820729 4, 0xFFFF, sum = 0
5709 06:54:00.823534 5, 0xFFFF, sum = 0
5710 06:54:00.823608 6, 0xFFFF, sum = 0
5711 06:54:00.826883 7, 0xFFFF, sum = 0
5712 06:54:00.830517 8, 0xFFFF, sum = 0
5713 06:54:00.830589 9, 0xFFFF, sum = 0
5714 06:54:00.833438 10, 0x0, sum = 1
5715 06:54:00.833530 11, 0x0, sum = 2
5716 06:54:00.833596 12, 0x0, sum = 3
5717 06:54:00.837005 13, 0x0, sum = 4
5718 06:54:00.837102 best_step = 11
5719 06:54:00.837198
5720 06:54:00.837292 ==
5721 06:54:00.840214 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 06:54:00.846928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 06:54:00.847031 ==
5724 06:54:00.847130 RX Vref Scan: 1
5725 06:54:00.847192
5726 06:54:00.850555 RX Vref 0 -> 0, step: 1
5727 06:54:00.850626
5728 06:54:00.853906 RX Delay -69 -> 252, step: 4
5729 06:54:00.853986
5730 06:54:00.856748 Set Vref, RX VrefLevel [Byte0]: 55
5731 06:54:00.860027 [Byte1]: 53
5732 06:54:00.860093
5733 06:54:00.863975 Final RX Vref Byte 0 = 55 to rank0
5734 06:54:00.867039 Final RX Vref Byte 1 = 53 to rank0
5735 06:54:00.870028 Final RX Vref Byte 0 = 55 to rank1
5736 06:54:00.873780 Final RX Vref Byte 1 = 53 to rank1==
5737 06:54:00.876932 Dram Type= 6, Freq= 0, CH_1, rank 0
5738 06:54:00.880248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 06:54:00.880355 ==
5740 06:54:00.883963 DQS Delay:
5741 06:54:00.884044 DQS0 = 0, DQS1 = 0
5742 06:54:00.886757 DQM Delay:
5743 06:54:00.886838 DQM0 = 98, DQM1 = 91
5744 06:54:00.886902 DQ Delay:
5745 06:54:00.890437 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =98
5746 06:54:00.893940 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5747 06:54:00.897105 DQ8 =80, DQ9 =80, DQ10 =94, DQ11 =88
5748 06:54:00.900208 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5749 06:54:00.900317
5750 06:54:00.900383
5751 06:54:00.910029 [DQSOSCAuto] RK0, (LSB)MR18= 0x10ed, (MSB)MR19= 0x504, tDQSOscB0 = 428 ps tDQSOscB1 = 416 ps
5752 06:54:00.913696 CH1 RK0: MR19=504, MR18=10ED
5753 06:54:00.920474 CH1_RK0: MR19=0x504, MR18=0x10ED, DQSOSC=416, MR23=63, INC=62, DEC=41
5754 06:54:00.920557
5755 06:54:00.923667 ----->DramcWriteLeveling(PI) begin...
5756 06:54:00.923750 ==
5757 06:54:00.926681 Dram Type= 6, Freq= 0, CH_1, rank 1
5758 06:54:00.929929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 06:54:00.930030 ==
5760 06:54:00.933250 Write leveling (Byte 0): 26 => 26
5761 06:54:00.936620 Write leveling (Byte 1): 28 => 28
5762 06:54:00.939975 DramcWriteLeveling(PI) end<-----
5763 06:54:00.940060
5764 06:54:00.940126 ==
5765 06:54:00.943436 Dram Type= 6, Freq= 0, CH_1, rank 1
5766 06:54:00.947012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 06:54:00.947089 ==
5768 06:54:00.950006 [Gating] SW mode calibration
5769 06:54:00.956903 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5770 06:54:00.963371 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5771 06:54:00.966896 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5772 06:54:00.969818 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 06:54:00.976728 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 06:54:00.979840 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 06:54:00.983412 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 06:54:00.989916 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 06:54:00.993538 0 14 24 | B1->B0 | 3131 2f2f | 0 1 | (0 0) (1 1)
5778 06:54:00.996574 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
5779 06:54:01.003585 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5780 06:54:01.006758 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 06:54:01.009869 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 06:54:01.013488 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 06:54:01.020280 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 06:54:01.023713 0 15 20 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5785 06:54:01.026837 0 15 24 | B1->B0 | 2929 3636 | 0 0 | (0 0) (0 0)
5786 06:54:01.033481 0 15 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5787 06:54:01.036493 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 06:54:01.040014 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 06:54:01.046798 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 06:54:01.049925 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 06:54:01.053653 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 06:54:01.059752 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 06:54:01.063482 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5794 06:54:01.066444 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 06:54:01.072953 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 06:54:01.076286 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 06:54:01.079866 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 06:54:01.086661 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 06:54:01.089733 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 06:54:01.093461 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 06:54:01.099790 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 06:54:01.103546 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 06:54:01.106502 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 06:54:01.113236 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 06:54:01.116661 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 06:54:01.119794 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 06:54:01.126582 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 06:54:01.129855 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5809 06:54:01.132849 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5810 06:54:01.136252 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 06:54:01.139625 Total UI for P1: 0, mck2ui 16
5812 06:54:01.143169 best dqsien dly found for B0: ( 1, 2, 22)
5813 06:54:01.146038 Total UI for P1: 0, mck2ui 16
5814 06:54:01.149704 best dqsien dly found for B1: ( 1, 2, 26)
5815 06:54:01.152698 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5816 06:54:01.156132 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5817 06:54:01.159864
5818 06:54:01.162733 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5819 06:54:01.166335 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5820 06:54:01.169927 [Gating] SW calibration Done
5821 06:54:01.170021 ==
5822 06:54:01.172991 Dram Type= 6, Freq= 0, CH_1, rank 1
5823 06:54:01.176198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5824 06:54:01.176298 ==
5825 06:54:01.176387 RX Vref Scan: 0
5826 06:54:01.179684
5827 06:54:01.179784 RX Vref 0 -> 0, step: 1
5828 06:54:01.179873
5829 06:54:01.182630 RX Delay -80 -> 252, step: 8
5830 06:54:01.186185 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5831 06:54:01.189861 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5832 06:54:01.196601 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5833 06:54:01.199578 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5834 06:54:01.203184 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5835 06:54:01.205871 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5836 06:54:01.209047 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5837 06:54:01.212772 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5838 06:54:01.219162 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5839 06:54:01.222834 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5840 06:54:01.225942 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5841 06:54:01.229483 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5842 06:54:01.232452 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5843 06:54:01.236014 iDelay=200, Bit 13, Center 99 (0 ~ 199) 200
5844 06:54:01.242576 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5845 06:54:01.245771 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5846 06:54:01.245853 ==
5847 06:54:01.249374 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 06:54:01.252888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 06:54:01.252973 ==
5850 06:54:01.256136 DQS Delay:
5851 06:54:01.256218 DQS0 = 0, DQS1 = 0
5852 06:54:01.256282 DQM Delay:
5853 06:54:01.258997 DQM0 = 94, DQM1 = 89
5854 06:54:01.259079 DQ Delay:
5855 06:54:01.262619 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5856 06:54:01.266201 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5857 06:54:01.269203 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5858 06:54:01.272563 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5859 06:54:01.272672
5860 06:54:01.272778
5861 06:54:01.272863 ==
5862 06:54:01.276185 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 06:54:01.282522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 06:54:01.282604 ==
5865 06:54:01.282668
5866 06:54:01.282739
5867 06:54:01.282810 TX Vref Scan disable
5868 06:54:01.285902 == TX Byte 0 ==
5869 06:54:01.288884 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5870 06:54:01.292307 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5871 06:54:01.295736 == TX Byte 1 ==
5872 06:54:01.299058 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5873 06:54:01.302567 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5874 06:54:01.305725 ==
5875 06:54:01.309114 Dram Type= 6, Freq= 0, CH_1, rank 1
5876 06:54:01.312624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5877 06:54:01.312704 ==
5878 06:54:01.312765
5879 06:54:01.312822
5880 06:54:01.315762 TX Vref Scan disable
5881 06:54:01.315832 == TX Byte 0 ==
5882 06:54:01.322261 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5883 06:54:01.325985 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5884 06:54:01.326057 == TX Byte 1 ==
5885 06:54:01.332073 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5886 06:54:01.335742 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5887 06:54:01.335890
5888 06:54:01.335994 [DATLAT]
5889 06:54:01.339172 Freq=933, CH1 RK1
5890 06:54:01.339244
5891 06:54:01.339319 DATLAT Default: 0xb
5892 06:54:01.342120 0, 0xFFFF, sum = 0
5893 06:54:01.342194 1, 0xFFFF, sum = 0
5894 06:54:01.345583 2, 0xFFFF, sum = 0
5895 06:54:01.345683 3, 0xFFFF, sum = 0
5896 06:54:01.349142 4, 0xFFFF, sum = 0
5897 06:54:01.349246 5, 0xFFFF, sum = 0
5898 06:54:01.352575 6, 0xFFFF, sum = 0
5899 06:54:01.352674 7, 0xFFFF, sum = 0
5900 06:54:01.356079 8, 0xFFFF, sum = 0
5901 06:54:01.359119 9, 0xFFFF, sum = 0
5902 06:54:01.359200 10, 0x0, sum = 1
5903 06:54:01.359263 11, 0x0, sum = 2
5904 06:54:01.362695 12, 0x0, sum = 3
5905 06:54:01.362778 13, 0x0, sum = 4
5906 06:54:01.365820 best_step = 11
5907 06:54:01.365894
5908 06:54:01.365952 ==
5909 06:54:01.369119 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 06:54:01.372646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 06:54:01.372716 ==
5912 06:54:01.375801 RX Vref Scan: 0
5913 06:54:01.375877
5914 06:54:01.375939 RX Vref 0 -> 0, step: 1
5915 06:54:01.375998
5916 06:54:01.378888 RX Delay -61 -> 252, step: 4
5917 06:54:01.385948 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5918 06:54:01.389433 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5919 06:54:01.392995 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5920 06:54:01.396106 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5921 06:54:01.399717 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5922 06:54:01.402512 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5923 06:54:01.409675 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5924 06:54:01.412880 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5925 06:54:01.416288 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5926 06:54:01.419349 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5927 06:54:01.422865 iDelay=199, Bit 10, Center 90 (-5 ~ 186) 192
5928 06:54:01.429439 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5929 06:54:01.433124 iDelay=199, Bit 12, Center 96 (7 ~ 186) 180
5930 06:54:01.436094 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5931 06:54:01.439734 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5932 06:54:01.442633 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5933 06:54:01.442733 ==
5934 06:54:01.446030 Dram Type= 6, Freq= 0, CH_1, rank 1
5935 06:54:01.453180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5936 06:54:01.453291 ==
5937 06:54:01.453359 DQS Delay:
5938 06:54:01.453419 DQS0 = 0, DQS1 = 0
5939 06:54:01.456214 DQM Delay:
5940 06:54:01.456292 DQM0 = 94, DQM1 = 90
5941 06:54:01.459749 DQ Delay:
5942 06:54:01.459856 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5943 06:54:01.463080 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =90
5944 06:54:01.466132 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =82
5945 06:54:01.469854 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =98
5946 06:54:01.473060
5947 06:54:01.473165
5948 06:54:01.479656 [DQSOSCAuto] RK1, (LSB)MR18= 0xd16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5949 06:54:01.483177 CH1 RK1: MR19=505, MR18=D16
5950 06:54:01.489539 CH1_RK1: MR19=0x505, MR18=0xD16, DQSOSC=414, MR23=63, INC=63, DEC=42
5951 06:54:01.489625 [RxdqsGatingPostProcess] freq 933
5952 06:54:01.496626 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5953 06:54:01.499642 best DQS0 dly(2T, 0.5T) = (0, 10)
5954 06:54:01.502755 best DQS1 dly(2T, 0.5T) = (0, 10)
5955 06:54:01.506399 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5956 06:54:01.509599 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5957 06:54:01.513178 best DQS0 dly(2T, 0.5T) = (0, 10)
5958 06:54:01.516167 best DQS1 dly(2T, 0.5T) = (0, 10)
5959 06:54:01.519975 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5960 06:54:01.523233 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5961 06:54:01.526144 Pre-setting of DQS Precalculation
5962 06:54:01.529799 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5963 06:54:01.536426 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5964 06:54:01.542603 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5965 06:54:01.546315
5966 06:54:01.546429
5967 06:54:01.546523 [Calibration Summary] 1866 Mbps
5968 06:54:01.549713 CH 0, Rank 0
5969 06:54:01.549794 SW Impedance : PASS
5970 06:54:01.552635 DUTY Scan : NO K
5971 06:54:01.556299 ZQ Calibration : PASS
5972 06:54:01.556376 Jitter Meter : NO K
5973 06:54:01.559929 CBT Training : PASS
5974 06:54:01.562733 Write leveling : PASS
5975 06:54:01.562812 RX DQS gating : PASS
5976 06:54:01.566151 RX DQ/DQS(RDDQC) : PASS
5977 06:54:01.569885 TX DQ/DQS : PASS
5978 06:54:01.569965 RX DATLAT : PASS
5979 06:54:01.572679 RX DQ/DQS(Engine): PASS
5980 06:54:01.575793 TX OE : NO K
5981 06:54:01.575870 All Pass.
5982 06:54:01.575937
5983 06:54:01.575998 CH 0, Rank 1
5984 06:54:01.579553 SW Impedance : PASS
5985 06:54:01.582472 DUTY Scan : NO K
5986 06:54:01.582555 ZQ Calibration : PASS
5987 06:54:01.586181 Jitter Meter : NO K
5988 06:54:01.589182 CBT Training : PASS
5989 06:54:01.589269 Write leveling : PASS
5990 06:54:01.592643 RX DQS gating : PASS
5991 06:54:01.592730 RX DQ/DQS(RDDQC) : PASS
5992 06:54:01.596050 TX DQ/DQS : PASS
5993 06:54:01.599226 RX DATLAT : PASS
5994 06:54:01.599304 RX DQ/DQS(Engine): PASS
5995 06:54:01.602757 TX OE : NO K
5996 06:54:01.602837 All Pass.
5997 06:54:01.602900
5998 06:54:01.605581 CH 1, Rank 0
5999 06:54:01.605659 SW Impedance : PASS
6000 06:54:01.609320 DUTY Scan : NO K
6001 06:54:01.612440 ZQ Calibration : PASS
6002 06:54:01.612518 Jitter Meter : NO K
6003 06:54:01.615891 CBT Training : PASS
6004 06:54:01.618961 Write leveling : PASS
6005 06:54:01.619045 RX DQS gating : PASS
6006 06:54:01.622421 RX DQ/DQS(RDDQC) : PASS
6007 06:54:01.625719 TX DQ/DQS : PASS
6008 06:54:01.625800 RX DATLAT : PASS
6009 06:54:01.628997 RX DQ/DQS(Engine): PASS
6010 06:54:01.632402 TX OE : NO K
6011 06:54:01.632485 All Pass.
6012 06:54:01.632571
6013 06:54:01.632660 CH 1, Rank 1
6014 06:54:01.635930 SW Impedance : PASS
6015 06:54:01.638827 DUTY Scan : NO K
6016 06:54:01.638907 ZQ Calibration : PASS
6017 06:54:01.642008 Jitter Meter : NO K
6018 06:54:01.645527 CBT Training : PASS
6019 06:54:01.645602 Write leveling : PASS
6020 06:54:01.648685 RX DQS gating : PASS
6021 06:54:01.652081 RX DQ/DQS(RDDQC) : PASS
6022 06:54:01.652163 TX DQ/DQS : PASS
6023 06:54:01.655064 RX DATLAT : PASS
6024 06:54:01.655145 RX DQ/DQS(Engine): PASS
6025 06:54:01.658690 TX OE : NO K
6026 06:54:01.658772 All Pass.
6027 06:54:01.658840
6028 06:54:01.662250 DramC Write-DBI off
6029 06:54:01.665150 PER_BANK_REFRESH: Hybrid Mode
6030 06:54:01.665236 TX_TRACKING: ON
6031 06:54:01.675329 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6032 06:54:01.678430 [FAST_K] Save calibration result to emmc
6033 06:54:01.682223 dramc_set_vcore_voltage set vcore to 650000
6034 06:54:01.685295 Read voltage for 400, 6
6035 06:54:01.685371 Vio18 = 0
6036 06:54:01.685437 Vcore = 650000
6037 06:54:01.688799 Vdram = 0
6038 06:54:01.688875 Vddq = 0
6039 06:54:01.688937 Vmddr = 0
6040 06:54:01.695560 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6041 06:54:01.698727 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6042 06:54:01.702250 MEM_TYPE=3, freq_sel=20
6043 06:54:01.705602 sv_algorithm_assistance_LP4_800
6044 06:54:01.708859 ============ PULL DRAM RESETB DOWN ============
6045 06:54:01.712068 ========== PULL DRAM RESETB DOWN end =========
6046 06:54:01.718884 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6047 06:54:01.721766 ===================================
6048 06:54:01.725568 LPDDR4 DRAM CONFIGURATION
6049 06:54:01.728839 ===================================
6050 06:54:01.728926 EX_ROW_EN[0] = 0x0
6051 06:54:01.732077 EX_ROW_EN[1] = 0x0
6052 06:54:01.732151 LP4Y_EN = 0x0
6053 06:54:01.735358 WORK_FSP = 0x0
6054 06:54:01.735450 WL = 0x2
6055 06:54:01.738875 RL = 0x2
6056 06:54:01.738971 BL = 0x2
6057 06:54:01.742041 RPST = 0x0
6058 06:54:01.742117 RD_PRE = 0x0
6059 06:54:01.745580 WR_PRE = 0x1
6060 06:54:01.745681 WR_PST = 0x0
6061 06:54:01.748622 DBI_WR = 0x0
6062 06:54:01.748695 DBI_RD = 0x0
6063 06:54:01.752167 OTF = 0x1
6064 06:54:01.755529 ===================================
6065 06:54:01.758477 ===================================
6066 06:54:01.758586 ANA top config
6067 06:54:01.762193 ===================================
6068 06:54:01.765672 DLL_ASYNC_EN = 0
6069 06:54:01.768730 ALL_SLAVE_EN = 1
6070 06:54:01.772270 NEW_RANK_MODE = 1
6071 06:54:01.772377 DLL_IDLE_MODE = 1
6072 06:54:01.775289 LP45_APHY_COMB_EN = 1
6073 06:54:01.778812 TX_ODT_DIS = 1
6074 06:54:01.782431 NEW_8X_MODE = 1
6075 06:54:01.785559 ===================================
6076 06:54:01.789275 ===================================
6077 06:54:01.792156 data_rate = 800
6078 06:54:01.792265 CKR = 1
6079 06:54:01.795247 DQ_P2S_RATIO = 4
6080 06:54:01.798903 ===================================
6081 06:54:01.801905 CA_P2S_RATIO = 4
6082 06:54:01.805690 DQ_CA_OPEN = 0
6083 06:54:01.808528 DQ_SEMI_OPEN = 1
6084 06:54:01.812341 CA_SEMI_OPEN = 1
6085 06:54:01.812480 CA_FULL_RATE = 0
6086 06:54:01.815167 DQ_CKDIV4_EN = 0
6087 06:54:01.819019 CA_CKDIV4_EN = 1
6088 06:54:01.822191 CA_PREDIV_EN = 0
6089 06:54:01.825532 PH8_DLY = 0
6090 06:54:01.828869 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6091 06:54:01.828978 DQ_AAMCK_DIV = 0
6092 06:54:01.831980 CA_AAMCK_DIV = 0
6093 06:54:01.835562 CA_ADMCK_DIV = 4
6094 06:54:01.838967 DQ_TRACK_CA_EN = 0
6095 06:54:01.842272 CA_PICK = 800
6096 06:54:01.845440 CA_MCKIO = 400
6097 06:54:01.845523 MCKIO_SEMI = 400
6098 06:54:01.848765 PLL_FREQ = 3016
6099 06:54:01.852267 DQ_UI_PI_RATIO = 32
6100 06:54:01.855213 CA_UI_PI_RATIO = 32
6101 06:54:01.858605 ===================================
6102 06:54:01.861851 ===================================
6103 06:54:01.865561 memory_type:LPDDR4
6104 06:54:01.865645 GP_NUM : 10
6105 06:54:01.868644 SRAM_EN : 1
6106 06:54:01.872014 MD32_EN : 0
6107 06:54:01.875184 ===================================
6108 06:54:01.875285 [ANA_INIT] >>>>>>>>>>>>>>
6109 06:54:01.878408 <<<<<< [CONFIGURE PHASE]: ANA_TX
6110 06:54:01.882075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6111 06:54:01.885570 ===================================
6112 06:54:01.888458 data_rate = 800,PCW = 0X7400
6113 06:54:01.892000 ===================================
6114 06:54:01.895066 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6115 06:54:01.901692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6116 06:54:01.912332 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6117 06:54:01.915287 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6118 06:54:01.921786 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6119 06:54:01.925141 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6120 06:54:01.925246 [ANA_INIT] flow start
6121 06:54:01.928684 [ANA_INIT] PLL >>>>>>>>
6122 06:54:01.932058 [ANA_INIT] PLL <<<<<<<<
6123 06:54:01.932162 [ANA_INIT] MIDPI >>>>>>>>
6124 06:54:01.935415 [ANA_INIT] MIDPI <<<<<<<<
6125 06:54:01.938249 [ANA_INIT] DLL >>>>>>>>
6126 06:54:01.938334 [ANA_INIT] flow end
6127 06:54:01.941965 ============ LP4 DIFF to SE enter ============
6128 06:54:01.948580 ============ LP4 DIFF to SE exit ============
6129 06:54:01.948685 [ANA_INIT] <<<<<<<<<<<<<
6130 06:54:01.952079 [Flow] Enable top DCM control >>>>>
6131 06:54:01.954970 [Flow] Enable top DCM control <<<<<
6132 06:54:01.958741 Enable DLL master slave shuffle
6133 06:54:01.964933 ==============================================================
6134 06:54:01.965041 Gating Mode config
6135 06:54:01.972040 ==============================================================
6136 06:54:01.975486 Config description:
6137 06:54:01.985345 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6138 06:54:01.991681 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6139 06:54:01.995219 SELPH_MODE 0: By rank 1: By Phase
6140 06:54:02.002235 ==============================================================
6141 06:54:02.005045 GAT_TRACK_EN = 0
6142 06:54:02.005145 RX_GATING_MODE = 2
6143 06:54:02.008694 RX_GATING_TRACK_MODE = 2
6144 06:54:02.011829 SELPH_MODE = 1
6145 06:54:02.015041 PICG_EARLY_EN = 1
6146 06:54:02.018150 VALID_LAT_VALUE = 1
6147 06:54:02.025467 ==============================================================
6148 06:54:02.028321 Enter into Gating configuration >>>>
6149 06:54:02.031742 Exit from Gating configuration <<<<
6150 06:54:02.035363 Enter into DVFS_PRE_config >>>>>
6151 06:54:02.045097 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6152 06:54:02.048777 Exit from DVFS_PRE_config <<<<<
6153 06:54:02.051788 Enter into PICG configuration >>>>
6154 06:54:02.055082 Exit from PICG configuration <<<<
6155 06:54:02.058647 [RX_INPUT] configuration >>>>>
6156 06:54:02.058723 [RX_INPUT] configuration <<<<<
6157 06:54:02.064905 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6158 06:54:02.071511 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6159 06:54:02.078105 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6160 06:54:02.081767 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6161 06:54:02.088313 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6162 06:54:02.094938 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6163 06:54:02.098345 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6164 06:54:02.101954 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6165 06:54:02.108771 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6166 06:54:02.111621 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6167 06:54:02.115405 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6168 06:54:02.121515 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6169 06:54:02.125271 ===================================
6170 06:54:02.125353 LPDDR4 DRAM CONFIGURATION
6171 06:54:02.128485 ===================================
6172 06:54:02.131943 EX_ROW_EN[0] = 0x0
6173 06:54:02.132047 EX_ROW_EN[1] = 0x0
6174 06:54:02.135096 LP4Y_EN = 0x0
6175 06:54:02.135199 WORK_FSP = 0x0
6176 06:54:02.138323 WL = 0x2
6177 06:54:02.141789 RL = 0x2
6178 06:54:02.141869 BL = 0x2
6179 06:54:02.145284 RPST = 0x0
6180 06:54:02.145366 RD_PRE = 0x0
6181 06:54:02.148110 WR_PRE = 0x1
6182 06:54:02.148186 WR_PST = 0x0
6183 06:54:02.151523 DBI_WR = 0x0
6184 06:54:02.151627 DBI_RD = 0x0
6185 06:54:02.155325 OTF = 0x1
6186 06:54:02.158521 ===================================
6187 06:54:02.161335 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6188 06:54:02.165032 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6189 06:54:02.171204 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6190 06:54:02.171318 ===================================
6191 06:54:02.175112 LPDDR4 DRAM CONFIGURATION
6192 06:54:02.178280 ===================================
6193 06:54:02.181176 EX_ROW_EN[0] = 0x10
6194 06:54:02.181291 EX_ROW_EN[1] = 0x0
6195 06:54:02.184930 LP4Y_EN = 0x0
6196 06:54:02.185032 WORK_FSP = 0x0
6197 06:54:02.188333 WL = 0x2
6198 06:54:02.188415 RL = 0x2
6199 06:54:02.191512 BL = 0x2
6200 06:54:02.194615 RPST = 0x0
6201 06:54:02.194715 RD_PRE = 0x0
6202 06:54:02.197916 WR_PRE = 0x1
6203 06:54:02.197993 WR_PST = 0x0
6204 06:54:02.201319 DBI_WR = 0x0
6205 06:54:02.201395 DBI_RD = 0x0
6206 06:54:02.204884 OTF = 0x1
6207 06:54:02.207649 ===================================
6208 06:54:02.211384 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6209 06:54:02.216413 nWR fixed to 30
6210 06:54:02.220041 [ModeRegInit_LP4] CH0 RK0
6211 06:54:02.220116 [ModeRegInit_LP4] CH0 RK1
6212 06:54:02.223586 [ModeRegInit_LP4] CH1 RK0
6213 06:54:02.226650 [ModeRegInit_LP4] CH1 RK1
6214 06:54:02.226724 match AC timing 19
6215 06:54:02.233215 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6216 06:54:02.236789 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6217 06:54:02.239975 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6218 06:54:02.246496 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6219 06:54:02.250248 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6220 06:54:02.250346 ==
6221 06:54:02.253168 Dram Type= 6, Freq= 0, CH_0, rank 0
6222 06:54:02.256837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6223 06:54:02.256940 ==
6224 06:54:02.263457 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6225 06:54:02.270339 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6226 06:54:02.273362 [CA 0] Center 36 (8~64) winsize 57
6227 06:54:02.276726 [CA 1] Center 36 (8~64) winsize 57
6228 06:54:02.276862 [CA 2] Center 36 (8~64) winsize 57
6229 06:54:02.280403 [CA 3] Center 36 (8~64) winsize 57
6230 06:54:02.283182 [CA 4] Center 36 (8~64) winsize 57
6231 06:54:02.286543 [CA 5] Center 36 (8~64) winsize 57
6232 06:54:02.286651
6233 06:54:02.290062 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6234 06:54:02.293336
6235 06:54:02.297004 [CATrainingPosCal] consider 1 rank data
6236 06:54:02.297106 u2DelayCellTimex100 = 270/100 ps
6237 06:54:02.299872 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 06:54:02.306960 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 06:54:02.310098 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 06:54:02.313454 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 06:54:02.316899 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 06:54:02.320129 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 06:54:02.320250
6244 06:54:02.323656 CA PerBit enable=1, Macro0, CA PI delay=36
6245 06:54:02.323756
6246 06:54:02.326730 [CBTSetCACLKResult] CA Dly = 36
6247 06:54:02.326843 CS Dly: 1 (0~32)
6248 06:54:02.330035 ==
6249 06:54:02.333123 Dram Type= 6, Freq= 0, CH_0, rank 1
6250 06:54:02.336842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6251 06:54:02.336946 ==
6252 06:54:02.339676 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6253 06:54:02.346726 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6254 06:54:02.349897 [CA 0] Center 36 (8~64) winsize 57
6255 06:54:02.353172 [CA 1] Center 36 (8~64) winsize 57
6256 06:54:02.356786 [CA 2] Center 36 (8~64) winsize 57
6257 06:54:02.360084 [CA 3] Center 36 (8~64) winsize 57
6258 06:54:02.363015 [CA 4] Center 36 (8~64) winsize 57
6259 06:54:02.366537 [CA 5] Center 36 (8~64) winsize 57
6260 06:54:02.366636
6261 06:54:02.369683 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6262 06:54:02.369759
6263 06:54:02.373200 [CATrainingPosCal] consider 2 rank data
6264 06:54:02.376521 u2DelayCellTimex100 = 270/100 ps
6265 06:54:02.379975 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 06:54:02.382965 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 06:54:02.386649 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 06:54:02.389870 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 06:54:02.393371 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 06:54:02.399948 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 06:54:02.400054
6272 06:54:02.403457 CA PerBit enable=1, Macro0, CA PI delay=36
6273 06:54:02.403556
6274 06:54:02.406536 [CBTSetCACLKResult] CA Dly = 36
6275 06:54:02.406637 CS Dly: 1 (0~32)
6276 06:54:02.406726
6277 06:54:02.409670 ----->DramcWriteLeveling(PI) begin...
6278 06:54:02.409754 ==
6279 06:54:02.413025 Dram Type= 6, Freq= 0, CH_0, rank 0
6280 06:54:02.419826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6281 06:54:02.419936 ==
6282 06:54:02.420039 Write leveling (Byte 0): 40 => 8
6283 06:54:02.423121 Write leveling (Byte 1): 32 => 0
6284 06:54:02.426645 DramcWriteLeveling(PI) end<-----
6285 06:54:02.426745
6286 06:54:02.426836 ==
6287 06:54:02.429714 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 06:54:02.436450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 06:54:02.436529 ==
6290 06:54:02.439704 [Gating] SW mode calibration
6291 06:54:02.446497 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6292 06:54:02.449855 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6293 06:54:02.456430 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6294 06:54:02.459983 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6295 06:54:02.463177 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6296 06:54:02.466350 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6297 06:54:02.473194 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6298 06:54:02.476304 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6299 06:54:02.480091 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 06:54:02.486685 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6301 06:54:02.489842 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6302 06:54:02.493552 Total UI for P1: 0, mck2ui 16
6303 06:54:02.496343 best dqsien dly found for B0: ( 0, 14, 24)
6304 06:54:02.499565 Total UI for P1: 0, mck2ui 16
6305 06:54:02.502965 best dqsien dly found for B1: ( 0, 14, 24)
6306 06:54:02.506381 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6307 06:54:02.509969 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6308 06:54:02.510067
6309 06:54:02.513027 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6310 06:54:02.516162 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6311 06:54:02.519810 [Gating] SW calibration Done
6312 06:54:02.519907 ==
6313 06:54:02.523006 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 06:54:02.529552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 06:54:02.529639 ==
6316 06:54:02.529705 RX Vref Scan: 0
6317 06:54:02.529766
6318 06:54:02.533331 RX Vref 0 -> 0, step: 1
6319 06:54:02.533412
6320 06:54:02.536119 RX Delay -410 -> 252, step: 16
6321 06:54:02.539673 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6322 06:54:02.542813 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6323 06:54:02.546031 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6324 06:54:02.552865 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6325 06:54:02.556190 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6326 06:54:02.559898 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6327 06:54:02.562805 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6328 06:54:02.569669 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6329 06:54:02.572545 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6330 06:54:02.576271 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6331 06:54:02.582786 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6332 06:54:02.585894 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6333 06:54:02.589711 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6334 06:54:02.592535 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6335 06:54:02.599383 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6336 06:54:02.602918 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6337 06:54:02.603027 ==
6338 06:54:02.606453 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 06:54:02.609413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 06:54:02.609489 ==
6341 06:54:02.609578 DQS Delay:
6342 06:54:02.612602 DQS0 = 35, DQS1 = 51
6343 06:54:02.612714 DQM Delay:
6344 06:54:02.616427 DQM0 = 7, DQM1 = 10
6345 06:54:02.616534 DQ Delay:
6346 06:54:02.620081 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6347 06:54:02.622934 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6348 06:54:02.626168 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6349 06:54:02.629560 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6350 06:54:02.629660
6351 06:54:02.629733
6352 06:54:02.629793 ==
6353 06:54:02.633106 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 06:54:02.636387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 06:54:02.636493 ==
6356 06:54:02.636587
6357 06:54:02.636674
6358 06:54:02.639363 TX Vref Scan disable
6359 06:54:02.642890 == TX Byte 0 ==
6360 06:54:02.646443 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6361 06:54:02.649351 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6362 06:54:02.652739 == TX Byte 1 ==
6363 06:54:02.656005 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6364 06:54:02.659497 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6365 06:54:02.659605 ==
6366 06:54:02.663145 Dram Type= 6, Freq= 0, CH_0, rank 0
6367 06:54:02.665958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6368 06:54:02.666033 ==
6369 06:54:02.669535
6370 06:54:02.669615
6371 06:54:02.669682 TX Vref Scan disable
6372 06:54:02.672493 == TX Byte 0 ==
6373 06:54:02.676308 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6374 06:54:02.679110 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6375 06:54:02.682717 == TX Byte 1 ==
6376 06:54:02.686582 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6377 06:54:02.689633 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6378 06:54:02.689708
6379 06:54:02.692668 [DATLAT]
6380 06:54:02.692773 Freq=400, CH0 RK0
6381 06:54:02.692864
6382 06:54:02.696369 DATLAT Default: 0xf
6383 06:54:02.696463 0, 0xFFFF, sum = 0
6384 06:54:02.699338 1, 0xFFFF, sum = 0
6385 06:54:02.699437 2, 0xFFFF, sum = 0
6386 06:54:02.702494 3, 0xFFFF, sum = 0
6387 06:54:02.702593 4, 0xFFFF, sum = 0
6388 06:54:02.705866 5, 0xFFFF, sum = 0
6389 06:54:02.705972 6, 0xFFFF, sum = 0
6390 06:54:02.709498 7, 0xFFFF, sum = 0
6391 06:54:02.709597 8, 0xFFFF, sum = 0
6392 06:54:02.712537 9, 0xFFFF, sum = 0
6393 06:54:02.712609 10, 0xFFFF, sum = 0
6394 06:54:02.716009 11, 0xFFFF, sum = 0
6395 06:54:02.716106 12, 0xFFFF, sum = 0
6396 06:54:02.719361 13, 0x0, sum = 1
6397 06:54:02.719459 14, 0x0, sum = 2
6398 06:54:02.722670 15, 0x0, sum = 3
6399 06:54:02.722768 16, 0x0, sum = 4
6400 06:54:02.726305 best_step = 14
6401 06:54:02.726398
6402 06:54:02.726485 ==
6403 06:54:02.729503 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 06:54:02.733013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 06:54:02.733111 ==
6406 06:54:02.736030 RX Vref Scan: 1
6407 06:54:02.736124
6408 06:54:02.736212 RX Vref 0 -> 0, step: 1
6409 06:54:02.736306
6410 06:54:02.739186 RX Delay -343 -> 252, step: 8
6411 06:54:02.739282
6412 06:54:02.742748 Set Vref, RX VrefLevel [Byte0]: 54
6413 06:54:02.746207 [Byte1]: 51
6414 06:54:02.750506
6415 06:54:02.750597 Final RX Vref Byte 0 = 54 to rank0
6416 06:54:02.753603 Final RX Vref Byte 1 = 51 to rank0
6417 06:54:02.757305 Final RX Vref Byte 0 = 54 to rank1
6418 06:54:02.760316 Final RX Vref Byte 1 = 51 to rank1==
6419 06:54:02.763801 Dram Type= 6, Freq= 0, CH_0, rank 0
6420 06:54:02.770308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 06:54:02.770406 ==
6422 06:54:02.770468 DQS Delay:
6423 06:54:02.770525 DQS0 = 44, DQS1 = 60
6424 06:54:02.773777 DQM Delay:
6425 06:54:02.773865 DQM0 = 11, DQM1 = 14
6426 06:54:02.776953 DQ Delay:
6427 06:54:02.780546 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6428 06:54:02.780660 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6429 06:54:02.784071 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6430 06:54:02.787048 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6431 06:54:02.787159
6432 06:54:02.790180
6433 06:54:02.796911 [DQSOSCAuto] RK0, (LSB)MR18= 0x8857, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6434 06:54:02.800536 CH0 RK0: MR19=C0C, MR18=8857
6435 06:54:02.807255 CH0_RK0: MR19=0xC0C, MR18=0x8857, DQSOSC=392, MR23=63, INC=384, DEC=256
6436 06:54:02.807355 ==
6437 06:54:02.810391 Dram Type= 6, Freq= 0, CH_0, rank 1
6438 06:54:02.813908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 06:54:02.813979 ==
6440 06:54:02.817017 [Gating] SW mode calibration
6441 06:54:02.823723 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6442 06:54:02.827234 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6443 06:54:02.833796 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6444 06:54:02.837379 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6445 06:54:02.840544 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6446 06:54:02.847511 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6447 06:54:02.850380 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 06:54:02.854080 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 06:54:02.860854 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 06:54:02.863619 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 06:54:02.867205 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6452 06:54:02.870446 Total UI for P1: 0, mck2ui 16
6453 06:54:02.874068 best dqsien dly found for B0: ( 0, 14, 24)
6454 06:54:02.876980 Total UI for P1: 0, mck2ui 16
6455 06:54:02.880332 best dqsien dly found for B1: ( 0, 14, 24)
6456 06:54:02.883562 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6457 06:54:02.887204 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6458 06:54:02.887288
6459 06:54:02.893934 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6460 06:54:02.897067 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6461 06:54:02.897144 [Gating] SW calibration Done
6462 06:54:02.900309 ==
6463 06:54:02.903744 Dram Type= 6, Freq= 0, CH_0, rank 1
6464 06:54:02.906954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 06:54:02.907037 ==
6466 06:54:02.907101 RX Vref Scan: 0
6467 06:54:02.907161
6468 06:54:02.910530 RX Vref 0 -> 0, step: 1
6469 06:54:02.910615
6470 06:54:02.913606 RX Delay -410 -> 252, step: 16
6471 06:54:02.917041 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6472 06:54:02.920540 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6473 06:54:02.927477 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6474 06:54:02.930458 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6475 06:54:02.933793 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6476 06:54:02.937051 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6477 06:54:02.943929 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6478 06:54:02.946869 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6479 06:54:02.950432 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6480 06:54:02.953642 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6481 06:54:02.960374 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6482 06:54:02.963919 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6483 06:54:02.967336 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6484 06:54:02.970514 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6485 06:54:02.977121 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6486 06:54:02.980290 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6487 06:54:02.980373 ==
6488 06:54:02.984090 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 06:54:02.987070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 06:54:02.987148 ==
6491 06:54:02.990336 DQS Delay:
6492 06:54:02.990416 DQS0 = 43, DQS1 = 51
6493 06:54:02.993868 DQM Delay:
6494 06:54:02.993942 DQM0 = 11, DQM1 = 10
6495 06:54:02.994002 DQ Delay:
6496 06:54:02.996845 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6497 06:54:03.000451 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6498 06:54:03.003799 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6499 06:54:03.006888 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6500 06:54:03.006976
6501 06:54:03.007051
6502 06:54:03.007111 ==
6503 06:54:03.010206 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 06:54:03.013836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 06:54:03.017422 ==
6506 06:54:03.017499
6507 06:54:03.017562
6508 06:54:03.017622 TX Vref Scan disable
6509 06:54:03.020287 == TX Byte 0 ==
6510 06:54:03.023955 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6511 06:54:03.026858 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6512 06:54:03.030395 == TX Byte 1 ==
6513 06:54:03.033501 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6514 06:54:03.037363 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6515 06:54:03.037439 ==
6516 06:54:03.040156 Dram Type= 6, Freq= 0, CH_0, rank 1
6517 06:54:03.046935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 06:54:03.047012 ==
6519 06:54:03.047074
6520 06:54:03.047131
6521 06:54:03.047186 TX Vref Scan disable
6522 06:54:03.050039 == TX Byte 0 ==
6523 06:54:03.053738 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6524 06:54:03.057323 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6525 06:54:03.060213 == TX Byte 1 ==
6526 06:54:03.063891 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6527 06:54:03.066998 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6528 06:54:03.067070
6529 06:54:03.070086 [DATLAT]
6530 06:54:03.070157 Freq=400, CH0 RK1
6531 06:54:03.070218
6532 06:54:03.073415 DATLAT Default: 0xe
6533 06:54:03.073484 0, 0xFFFF, sum = 0
6534 06:54:03.076805 1, 0xFFFF, sum = 0
6535 06:54:03.076875 2, 0xFFFF, sum = 0
6536 06:54:03.080248 3, 0xFFFF, sum = 0
6537 06:54:03.080316 4, 0xFFFF, sum = 0
6538 06:54:03.083723 5, 0xFFFF, sum = 0
6539 06:54:03.083800 6, 0xFFFF, sum = 0
6540 06:54:03.087013 7, 0xFFFF, sum = 0
6541 06:54:03.087083 8, 0xFFFF, sum = 0
6542 06:54:03.090303 9, 0xFFFF, sum = 0
6543 06:54:03.090376 10, 0xFFFF, sum = 0
6544 06:54:03.093386 11, 0xFFFF, sum = 0
6545 06:54:03.093456 12, 0xFFFF, sum = 0
6546 06:54:03.097039 13, 0x0, sum = 1
6547 06:54:03.097141 14, 0x0, sum = 2
6548 06:54:03.100629 15, 0x0, sum = 3
6549 06:54:03.100708 16, 0x0, sum = 4
6550 06:54:03.103717 best_step = 14
6551 06:54:03.103794
6552 06:54:03.103854 ==
6553 06:54:03.107117 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 06:54:03.109990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 06:54:03.110073 ==
6556 06:54:03.113676 RX Vref Scan: 0
6557 06:54:03.113748
6558 06:54:03.113815 RX Vref 0 -> 0, step: 1
6559 06:54:03.113873
6560 06:54:03.116856 RX Delay -343 -> 252, step: 8
6561 06:54:03.124766 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6562 06:54:03.127779 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6563 06:54:03.130958 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6564 06:54:03.137879 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6565 06:54:03.141010 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6566 06:54:03.144589 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6567 06:54:03.147713 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6568 06:54:03.151492 iDelay=217, Bit 7, Center -24 (-263 ~ 216) 480
6569 06:54:03.158033 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6570 06:54:03.161333 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6571 06:54:03.164110 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6572 06:54:03.170986 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6573 06:54:03.174037 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6574 06:54:03.177616 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6575 06:54:03.181150 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6576 06:54:03.187406 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6577 06:54:03.187486 ==
6578 06:54:03.191019 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 06:54:03.193903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 06:54:03.193979 ==
6581 06:54:03.194055 DQS Delay:
6582 06:54:03.197585 DQS0 = 48, DQS1 = 60
6583 06:54:03.197664 DQM Delay:
6584 06:54:03.201056 DQM0 = 14, DQM1 = 13
6585 06:54:03.201159 DQ Delay:
6586 06:54:03.204095 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6587 06:54:03.207417 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =24
6588 06:54:03.211016 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6589 06:54:03.214382 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6590 06:54:03.214472
6591 06:54:03.214534
6592 06:54:03.220854 [DQSOSCAuto] RK1, (LSB)MR18= 0x9164, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6593 06:54:03.224194 CH0 RK1: MR19=C0C, MR18=9164
6594 06:54:03.230717 CH0_RK1: MR19=0xC0C, MR18=0x9164, DQSOSC=391, MR23=63, INC=386, DEC=257
6595 06:54:03.234258 [RxdqsGatingPostProcess] freq 400
6596 06:54:03.240438 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6597 06:54:03.244188 best DQS0 dly(2T, 0.5T) = (0, 10)
6598 06:54:03.244265 best DQS1 dly(2T, 0.5T) = (0, 10)
6599 06:54:03.247175 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6600 06:54:03.250743 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6601 06:54:03.253822 best DQS0 dly(2T, 0.5T) = (0, 10)
6602 06:54:03.257331 best DQS1 dly(2T, 0.5T) = (0, 10)
6603 06:54:03.260227 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6604 06:54:03.264204 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6605 06:54:03.267622 Pre-setting of DQS Precalculation
6606 06:54:03.273845 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6607 06:54:03.273922 ==
6608 06:54:03.277585 Dram Type= 6, Freq= 0, CH_1, rank 0
6609 06:54:03.280553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6610 06:54:03.280676 ==
6611 06:54:03.287162 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6612 06:54:03.290709 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6613 06:54:03.293654 [CA 0] Center 36 (8~64) winsize 57
6614 06:54:03.297373 [CA 1] Center 36 (8~64) winsize 57
6615 06:54:03.300326 [CA 2] Center 36 (8~64) winsize 57
6616 06:54:03.303892 [CA 3] Center 36 (8~64) winsize 57
6617 06:54:03.307576 [CA 4] Center 36 (8~64) winsize 57
6618 06:54:03.310337 [CA 5] Center 36 (8~64) winsize 57
6619 06:54:03.310425
6620 06:54:03.314014 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6621 06:54:03.314097
6622 06:54:03.317009 [CATrainingPosCal] consider 1 rank data
6623 06:54:03.320680 u2DelayCellTimex100 = 270/100 ps
6624 06:54:03.324035 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 06:54:03.327068 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 06:54:03.330859 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 06:54:03.337300 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 06:54:03.340290 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 06:54:03.344020 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 06:54:03.344102
6631 06:54:03.346969 CA PerBit enable=1, Macro0, CA PI delay=36
6632 06:54:03.347062
6633 06:54:03.350656 [CBTSetCACLKResult] CA Dly = 36
6634 06:54:03.350730 CS Dly: 1 (0~32)
6635 06:54:03.350792 ==
6636 06:54:03.353526 Dram Type= 6, Freq= 0, CH_1, rank 1
6637 06:54:03.360537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6638 06:54:03.360637 ==
6639 06:54:03.364078 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6640 06:54:03.370611 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6641 06:54:03.374052 [CA 0] Center 36 (8~64) winsize 57
6642 06:54:03.377254 [CA 1] Center 36 (8~64) winsize 57
6643 06:54:03.380937 [CA 2] Center 36 (8~64) winsize 57
6644 06:54:03.383983 [CA 3] Center 36 (8~64) winsize 57
6645 06:54:03.387219 [CA 4] Center 36 (8~64) winsize 57
6646 06:54:03.390375 [CA 5] Center 36 (8~64) winsize 57
6647 06:54:03.390458
6648 06:54:03.394143 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6649 06:54:03.394220
6650 06:54:03.397192 [CATrainingPosCal] consider 2 rank data
6651 06:54:03.400555 u2DelayCellTimex100 = 270/100 ps
6652 06:54:03.404007 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 06:54:03.407526 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 06:54:03.410559 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 06:54:03.413810 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 06:54:03.417529 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 06:54:03.420869 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 06:54:03.420952
6659 06:54:03.427158 CA PerBit enable=1, Macro0, CA PI delay=36
6660 06:54:03.427241
6661 06:54:03.427306 [CBTSetCACLKResult] CA Dly = 36
6662 06:54:03.430361 CS Dly: 1 (0~32)
6663 06:54:03.430438
6664 06:54:03.434085 ----->DramcWriteLeveling(PI) begin...
6665 06:54:03.434170 ==
6666 06:54:03.436948 Dram Type= 6, Freq= 0, CH_1, rank 0
6667 06:54:03.440579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6668 06:54:03.440658 ==
6669 06:54:03.444203 Write leveling (Byte 0): 40 => 8
6670 06:54:03.447290 Write leveling (Byte 1): 40 => 8
6671 06:54:03.450804 DramcWriteLeveling(PI) end<-----
6672 06:54:03.450880
6673 06:54:03.450942 ==
6674 06:54:03.453780 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 06:54:03.457412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 06:54:03.457485 ==
6677 06:54:03.460442 [Gating] SW mode calibration
6678 06:54:03.467542 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6679 06:54:03.474464 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6680 06:54:03.477118 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6681 06:54:03.484017 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6682 06:54:03.487494 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6683 06:54:03.490677 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6684 06:54:03.493954 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6685 06:54:03.500938 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6686 06:54:03.503906 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 06:54:03.507484 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6688 06:54:03.513776 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6689 06:54:03.517110 Total UI for P1: 0, mck2ui 16
6690 06:54:03.520720 best dqsien dly found for B0: ( 0, 14, 24)
6691 06:54:03.520801 Total UI for P1: 0, mck2ui 16
6692 06:54:03.527766 best dqsien dly found for B1: ( 0, 14, 24)
6693 06:54:03.530804 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6694 06:54:03.534118 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6695 06:54:03.534201
6696 06:54:03.537950 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6697 06:54:03.540890 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6698 06:54:03.544450 [Gating] SW calibration Done
6699 06:54:03.544527 ==
6700 06:54:03.547567 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 06:54:03.551184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 06:54:03.551260 ==
6703 06:54:03.554028 RX Vref Scan: 0
6704 06:54:03.554102
6705 06:54:03.554172 RX Vref 0 -> 0, step: 1
6706 06:54:03.554231
6707 06:54:03.557755 RX Delay -410 -> 252, step: 16
6708 06:54:03.564180 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6709 06:54:03.567357 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6710 06:54:03.570741 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6711 06:54:03.574561 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6712 06:54:03.581041 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6713 06:54:03.584256 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6714 06:54:03.587273 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6715 06:54:03.590948 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6716 06:54:03.597254 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6717 06:54:03.601100 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6718 06:54:03.604133 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6719 06:54:03.607581 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6720 06:54:03.614103 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6721 06:54:03.617632 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6722 06:54:03.620764 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6723 06:54:03.624488 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6724 06:54:03.624603 ==
6725 06:54:03.627757 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 06:54:03.634378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 06:54:03.634473 ==
6728 06:54:03.634540 DQS Delay:
6729 06:54:03.637425 DQS0 = 51, DQS1 = 59
6730 06:54:03.637533 DQM Delay:
6731 06:54:03.637644 DQM0 = 19, DQM1 = 16
6732 06:54:03.641294 DQ Delay:
6733 06:54:03.644399 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6734 06:54:03.647500 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6735 06:54:03.650913 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6736 06:54:03.654599 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6737 06:54:03.654682
6738 06:54:03.654745
6739 06:54:03.654804 ==
6740 06:54:03.657421 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 06:54:03.660981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 06:54:03.661059 ==
6743 06:54:03.661165
6744 06:54:03.661252
6745 06:54:03.664046 TX Vref Scan disable
6746 06:54:03.664157 == TX Byte 0 ==
6747 06:54:03.670651 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6748 06:54:03.674297 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6749 06:54:03.674379 == TX Byte 1 ==
6750 06:54:03.677565 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 06:54:03.684006 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 06:54:03.684096 ==
6753 06:54:03.687916 Dram Type= 6, Freq= 0, CH_1, rank 0
6754 06:54:03.690888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6755 06:54:03.690976 ==
6756 06:54:03.691039
6757 06:54:03.691098
6758 06:54:03.693916 TX Vref Scan disable
6759 06:54:03.693990 == TX Byte 0 ==
6760 06:54:03.701093 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6761 06:54:03.704123 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6762 06:54:03.704197 == TX Byte 1 ==
6763 06:54:03.710721 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6764 06:54:03.713988 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6765 06:54:03.714078
6766 06:54:03.714142 [DATLAT]
6767 06:54:03.717569 Freq=400, CH1 RK0
6768 06:54:03.717677
6769 06:54:03.717774 DATLAT Default: 0xf
6770 06:54:03.720897 0, 0xFFFF, sum = 0
6771 06:54:03.720970 1, 0xFFFF, sum = 0
6772 06:54:03.724073 2, 0xFFFF, sum = 0
6773 06:54:03.724146 3, 0xFFFF, sum = 0
6774 06:54:03.728024 4, 0xFFFF, sum = 0
6775 06:54:03.728136 5, 0xFFFF, sum = 0
6776 06:54:03.730758 6, 0xFFFF, sum = 0
6777 06:54:03.730833 7, 0xFFFF, sum = 0
6778 06:54:03.734479 8, 0xFFFF, sum = 0
6779 06:54:03.734554 9, 0xFFFF, sum = 0
6780 06:54:03.737867 10, 0xFFFF, sum = 0
6781 06:54:03.737966 11, 0xFFFF, sum = 0
6782 06:54:03.740950 12, 0xFFFF, sum = 0
6783 06:54:03.741029 13, 0x0, sum = 1
6784 06:54:03.744059 14, 0x0, sum = 2
6785 06:54:03.744141 15, 0x0, sum = 3
6786 06:54:03.747359 16, 0x0, sum = 4
6787 06:54:03.747435 best_step = 14
6788 06:54:03.747496
6789 06:54:03.747556 ==
6790 06:54:03.750726 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 06:54:03.757891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 06:54:03.757985 ==
6793 06:54:03.758050 RX Vref Scan: 1
6794 06:54:03.758111
6795 06:54:03.760825 RX Vref 0 -> 0, step: 1
6796 06:54:03.760895
6797 06:54:03.764368 RX Delay -359 -> 252, step: 8
6798 06:54:03.764435
6799 06:54:03.767556 Set Vref, RX VrefLevel [Byte0]: 55
6800 06:54:03.771150 [Byte1]: 53
6801 06:54:03.771219
6802 06:54:03.774113 Final RX Vref Byte 0 = 55 to rank0
6803 06:54:03.777797 Final RX Vref Byte 1 = 53 to rank0
6804 06:54:03.780691 Final RX Vref Byte 0 = 55 to rank1
6805 06:54:03.784194 Final RX Vref Byte 1 = 53 to rank1==
6806 06:54:03.787410 Dram Type= 6, Freq= 0, CH_1, rank 0
6807 06:54:03.790891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 06:54:03.794001 ==
6809 06:54:03.794079 DQS Delay:
6810 06:54:03.794141 DQS0 = 48, DQS1 = 60
6811 06:54:03.797596 DQM Delay:
6812 06:54:03.797669 DQM0 = 12, DQM1 = 13
6813 06:54:03.800554 DQ Delay:
6814 06:54:03.800633 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6815 06:54:03.804397 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6816 06:54:03.807410 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6817 06:54:03.810512 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6818 06:54:03.810585
6819 06:54:03.810646
6820 06:54:03.820749 [DQSOSCAuto] RK0, (LSB)MR18= 0x8d36, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6821 06:54:03.823778 CH1 RK0: MR19=C0C, MR18=8D36
6822 06:54:03.830984 CH1_RK0: MR19=0xC0C, MR18=0x8D36, DQSOSC=392, MR23=63, INC=384, DEC=256
6823 06:54:03.831123 ==
6824 06:54:03.834085 Dram Type= 6, Freq= 0, CH_1, rank 1
6825 06:54:03.837483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 06:54:03.837581 ==
6827 06:54:03.840534 [Gating] SW mode calibration
6828 06:54:03.847518 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6829 06:54:03.850731 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6830 06:54:03.857377 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6831 06:54:03.860897 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6832 06:54:03.864143 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6833 06:54:03.870583 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6834 06:54:03.874299 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6835 06:54:03.877405 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6836 06:54:03.884050 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 06:54:03.887174 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6838 06:54:03.890799 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6839 06:54:03.893906 Total UI for P1: 0, mck2ui 16
6840 06:54:03.897576 best dqsien dly found for B0: ( 0, 14, 24)
6841 06:54:03.900776 Total UI for P1: 0, mck2ui 16
6842 06:54:03.904132 best dqsien dly found for B1: ( 0, 14, 24)
6843 06:54:03.907574 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6844 06:54:03.910750 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6845 06:54:03.910825
6846 06:54:03.917382 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6847 06:54:03.920553 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6848 06:54:03.920629 [Gating] SW calibration Done
6849 06:54:03.923772 ==
6850 06:54:03.923841 Dram Type= 6, Freq= 0, CH_1, rank 1
6851 06:54:03.930421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 06:54:03.930503 ==
6853 06:54:03.930568 RX Vref Scan: 0
6854 06:54:03.930629
6855 06:54:03.934266 RX Vref 0 -> 0, step: 1
6856 06:54:03.934340
6857 06:54:03.937313 RX Delay -410 -> 252, step: 16
6858 06:54:03.940602 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6859 06:54:03.944004 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6860 06:54:03.950646 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6861 06:54:03.954159 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6862 06:54:03.957374 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6863 06:54:03.960624 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6864 06:54:03.967387 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6865 06:54:03.970722 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6866 06:54:03.974006 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6867 06:54:03.977370 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6868 06:54:03.983861 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6869 06:54:03.987555 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6870 06:54:03.990511 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6871 06:54:03.994140 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6872 06:54:04.001014 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6873 06:54:04.003856 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6874 06:54:04.003934 ==
6875 06:54:04.007646 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 06:54:04.010583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 06:54:04.010668 ==
6878 06:54:04.014064 DQS Delay:
6879 06:54:04.014158 DQS0 = 43, DQS1 = 51
6880 06:54:04.017280 DQM Delay:
6881 06:54:04.017356 DQM0 = 10, DQM1 = 13
6882 06:54:04.017427 DQ Delay:
6883 06:54:04.020983 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6884 06:54:04.023968 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6885 06:54:04.027426 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6886 06:54:04.030340 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6887 06:54:04.030417
6888 06:54:04.030482
6889 06:54:04.030547 ==
6890 06:54:04.034021 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 06:54:04.037130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 06:54:04.040993 ==
6893 06:54:04.041074
6894 06:54:04.041167
6895 06:54:04.041250 TX Vref Scan disable
6896 06:54:04.043917 == TX Byte 0 ==
6897 06:54:04.047463 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6898 06:54:04.050357 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6899 06:54:04.054194 == TX Byte 1 ==
6900 06:54:04.057161 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6901 06:54:04.060968 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6902 06:54:04.061044 ==
6903 06:54:04.064309 Dram Type= 6, Freq= 0, CH_1, rank 1
6904 06:54:04.067297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 06:54:04.070401 ==
6906 06:54:04.070477
6907 06:54:04.070541
6908 06:54:04.070599 TX Vref Scan disable
6909 06:54:04.074282 == TX Byte 0 ==
6910 06:54:04.077303 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6911 06:54:04.080380 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6912 06:54:04.084006 == TX Byte 1 ==
6913 06:54:04.087497 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6914 06:54:04.090654 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6915 06:54:04.090736
6916 06:54:04.090802 [DATLAT]
6917 06:54:04.094178 Freq=400, CH1 RK1
6918 06:54:04.094259
6919 06:54:04.094322 DATLAT Default: 0xe
6920 06:54:04.097446 0, 0xFFFF, sum = 0
6921 06:54:04.101058 1, 0xFFFF, sum = 0
6922 06:54:04.101169 2, 0xFFFF, sum = 0
6923 06:54:04.103996 3, 0xFFFF, sum = 0
6924 06:54:04.104087 4, 0xFFFF, sum = 0
6925 06:54:04.107937 5, 0xFFFF, sum = 0
6926 06:54:04.108015 6, 0xFFFF, sum = 0
6927 06:54:04.110948 7, 0xFFFF, sum = 0
6928 06:54:04.111024 8, 0xFFFF, sum = 0
6929 06:54:04.113769 9, 0xFFFF, sum = 0
6930 06:54:04.113851 10, 0xFFFF, sum = 0
6931 06:54:04.117598 11, 0xFFFF, sum = 0
6932 06:54:04.117678 12, 0xFFFF, sum = 0
6933 06:54:04.120465 13, 0x0, sum = 1
6934 06:54:04.120568 14, 0x0, sum = 2
6935 06:54:04.123854 15, 0x0, sum = 3
6936 06:54:04.123970 16, 0x0, sum = 4
6937 06:54:04.127514 best_step = 14
6938 06:54:04.127590
6939 06:54:04.127689 ==
6940 06:54:04.130633 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 06:54:04.134055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 06:54:04.134140 ==
6943 06:54:04.134204 RX Vref Scan: 0
6944 06:54:04.137160
6945 06:54:04.137267 RX Vref 0 -> 0, step: 1
6946 06:54:04.137330
6947 06:54:04.140870 RX Delay -343 -> 252, step: 8
6948 06:54:04.148278 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6949 06:54:04.151369 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6950 06:54:04.154703 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6951 06:54:04.157780 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6952 06:54:04.164534 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6953 06:54:04.168002 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6954 06:54:04.171527 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6955 06:54:04.175239 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6956 06:54:04.181288 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6957 06:54:04.184610 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6958 06:54:04.188012 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6959 06:54:04.191255 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6960 06:54:04.198094 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6961 06:54:04.201563 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6962 06:54:04.204803 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6963 06:54:04.211170 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6964 06:54:04.211255 ==
6965 06:54:04.214702 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 06:54:04.218253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 06:54:04.218338 ==
6968 06:54:04.218403 DQS Delay:
6969 06:54:04.221111 DQS0 = 52, DQS1 = 56
6970 06:54:04.221183 DQM Delay:
6971 06:54:04.224850 DQM0 = 13, DQM1 = 9
6972 06:54:04.224921 DQ Delay:
6973 06:54:04.227905 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6974 06:54:04.231484 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6975 06:54:04.234369 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6976 06:54:04.237974 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6977 06:54:04.238049
6978 06:54:04.238116
6979 06:54:04.244659 [DQSOSCAuto] RK1, (LSB)MR18= 0x7086, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 395 ps
6980 06:54:04.247708 CH1 RK1: MR19=C0C, MR18=7086
6981 06:54:04.254426 CH1_RK1: MR19=0xC0C, MR18=0x7086, DQSOSC=393, MR23=63, INC=382, DEC=254
6982 06:54:04.257971 [RxdqsGatingPostProcess] freq 400
6983 06:54:04.261142 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6984 06:54:04.264761 best DQS0 dly(2T, 0.5T) = (0, 10)
6985 06:54:04.267936 best DQS1 dly(2T, 0.5T) = (0, 10)
6986 06:54:04.271511 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6987 06:54:04.274362 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6988 06:54:04.277843 best DQS0 dly(2T, 0.5T) = (0, 10)
6989 06:54:04.281327 best DQS1 dly(2T, 0.5T) = (0, 10)
6990 06:54:04.284529 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6991 06:54:04.287646 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6992 06:54:04.291274 Pre-setting of DQS Precalculation
6993 06:54:04.294775 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6994 06:54:04.304482 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6995 06:54:04.311291 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6996 06:54:04.311407
6997 06:54:04.311476
6998 06:54:04.314751 [Calibration Summary] 800 Mbps
6999 06:54:04.314847 CH 0, Rank 0
7000 06:54:04.317960 SW Impedance : PASS
7001 06:54:04.318038 DUTY Scan : NO K
7002 06:54:04.321500 ZQ Calibration : PASS
7003 06:54:04.324758 Jitter Meter : NO K
7004 06:54:04.324838 CBT Training : PASS
7005 06:54:04.328291 Write leveling : PASS
7006 06:54:04.328365 RX DQS gating : PASS
7007 06:54:04.331025 RX DQ/DQS(RDDQC) : PASS
7008 06:54:04.334662 TX DQ/DQS : PASS
7009 06:54:04.334770 RX DATLAT : PASS
7010 06:54:04.337940 RX DQ/DQS(Engine): PASS
7011 06:54:04.341377 TX OE : NO K
7012 06:54:04.341456 All Pass.
7013 06:54:04.341522
7014 06:54:04.341583 CH 0, Rank 1
7015 06:54:04.344402 SW Impedance : PASS
7016 06:54:04.347839 DUTY Scan : NO K
7017 06:54:04.347914 ZQ Calibration : PASS
7018 06:54:04.351029 Jitter Meter : NO K
7019 06:54:04.354775 CBT Training : PASS
7020 06:54:04.354857 Write leveling : NO K
7021 06:54:04.357643 RX DQS gating : PASS
7022 06:54:04.361276 RX DQ/DQS(RDDQC) : PASS
7023 06:54:04.361353 TX DQ/DQS : PASS
7024 06:54:04.364735 RX DATLAT : PASS
7025 06:54:04.367741 RX DQ/DQS(Engine): PASS
7026 06:54:04.367814 TX OE : NO K
7027 06:54:04.367882 All Pass.
7028 06:54:04.371524
7029 06:54:04.371598 CH 1, Rank 0
7030 06:54:04.374399 SW Impedance : PASS
7031 06:54:04.374473 DUTY Scan : NO K
7032 06:54:04.377845 ZQ Calibration : PASS
7033 06:54:04.377922 Jitter Meter : NO K
7034 06:54:04.380907 CBT Training : PASS
7035 06:54:04.384508 Write leveling : PASS
7036 06:54:04.384613 RX DQS gating : PASS
7037 06:54:04.388001 RX DQ/DQS(RDDQC) : PASS
7038 06:54:04.390959 TX DQ/DQS : PASS
7039 06:54:04.391042 RX DATLAT : PASS
7040 06:54:04.394826 RX DQ/DQS(Engine): PASS
7041 06:54:04.397798 TX OE : NO K
7042 06:54:04.397875 All Pass.
7043 06:54:04.397939
7044 06:54:04.398005 CH 1, Rank 1
7045 06:54:04.401203 SW Impedance : PASS
7046 06:54:04.404660 DUTY Scan : NO K
7047 06:54:04.404739 ZQ Calibration : PASS
7048 06:54:04.407725 Jitter Meter : NO K
7049 06:54:04.411110 CBT Training : PASS
7050 06:54:04.411184 Write leveling : NO K
7051 06:54:04.414566 RX DQS gating : PASS
7052 06:54:04.418114 RX DQ/DQS(RDDQC) : PASS
7053 06:54:04.418197 TX DQ/DQS : PASS
7054 06:54:04.421164 RX DATLAT : PASS
7055 06:54:04.421247 RX DQ/DQS(Engine): PASS
7056 06:54:04.424668 TX OE : NO K
7057 06:54:04.424744 All Pass.
7058 06:54:04.424806
7059 06:54:04.427857 DramC Write-DBI off
7060 06:54:04.431142 PER_BANK_REFRESH: Hybrid Mode
7061 06:54:04.431223 TX_TRACKING: ON
7062 06:54:04.440909 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7063 06:54:04.444280 [FAST_K] Save calibration result to emmc
7064 06:54:04.447798 dramc_set_vcore_voltage set vcore to 725000
7065 06:54:04.451113 Read voltage for 1600, 0
7066 06:54:04.451192 Vio18 = 0
7067 06:54:04.451256 Vcore = 725000
7068 06:54:04.454800 Vdram = 0
7069 06:54:04.454875 Vddq = 0
7070 06:54:04.454937 Vmddr = 0
7071 06:54:04.461261 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7072 06:54:04.464317 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7073 06:54:04.467867 MEM_TYPE=3, freq_sel=13
7074 06:54:04.470990 sv_algorithm_assistance_LP4_3733
7075 06:54:04.474558 ============ PULL DRAM RESETB DOWN ============
7076 06:54:04.478146 ========== PULL DRAM RESETB DOWN end =========
7077 06:54:04.484328 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7078 06:54:04.488014 ===================================
7079 06:54:04.491044 LPDDR4 DRAM CONFIGURATION
7080 06:54:04.494317 ===================================
7081 06:54:04.494396 EX_ROW_EN[0] = 0x0
7082 06:54:04.497962 EX_ROW_EN[1] = 0x0
7083 06:54:04.498045 LP4Y_EN = 0x0
7084 06:54:04.501080 WORK_FSP = 0x1
7085 06:54:04.501189 WL = 0x5
7086 06:54:04.504529 RL = 0x5
7087 06:54:04.504611 BL = 0x2
7088 06:54:04.507971 RPST = 0x0
7089 06:54:04.508054 RD_PRE = 0x0
7090 06:54:04.510944 WR_PRE = 0x1
7091 06:54:04.511045 WR_PST = 0x1
7092 06:54:04.514250 DBI_WR = 0x0
7093 06:54:04.514356 DBI_RD = 0x0
7094 06:54:04.517608 OTF = 0x1
7095 06:54:04.521121 ===================================
7096 06:54:04.523980 ===================================
7097 06:54:04.524058 ANA top config
7098 06:54:04.527479 ===================================
7099 06:54:04.530599 DLL_ASYNC_EN = 0
7100 06:54:04.534124 ALL_SLAVE_EN = 0
7101 06:54:04.537788 NEW_RANK_MODE = 1
7102 06:54:04.540804 DLL_IDLE_MODE = 1
7103 06:54:04.540881 LP45_APHY_COMB_EN = 1
7104 06:54:04.544080 TX_ODT_DIS = 0
7105 06:54:04.547648 NEW_8X_MODE = 1
7106 06:54:04.551199 ===================================
7107 06:54:04.554602 ===================================
7108 06:54:04.557536 data_rate = 3200
7109 06:54:04.561201 CKR = 1
7110 06:54:04.561297 DQ_P2S_RATIO = 8
7111 06:54:04.564037 ===================================
7112 06:54:04.567812 CA_P2S_RATIO = 8
7113 06:54:04.570518 DQ_CA_OPEN = 0
7114 06:54:04.574296 DQ_SEMI_OPEN = 0
7115 06:54:04.577283 CA_SEMI_OPEN = 0
7116 06:54:04.581038 CA_FULL_RATE = 0
7117 06:54:04.581140 DQ_CKDIV4_EN = 0
7118 06:54:04.584130 CA_CKDIV4_EN = 0
7119 06:54:04.587826 CA_PREDIV_EN = 0
7120 06:54:04.590690 PH8_DLY = 12
7121 06:54:04.594553 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7122 06:54:04.597466 DQ_AAMCK_DIV = 4
7123 06:54:04.597551 CA_AAMCK_DIV = 4
7124 06:54:04.600946 CA_ADMCK_DIV = 4
7125 06:54:04.604153 DQ_TRACK_CA_EN = 0
7126 06:54:04.607725 CA_PICK = 1600
7127 06:54:04.610993 CA_MCKIO = 1600
7128 06:54:04.614537 MCKIO_SEMI = 0
7129 06:54:04.617739 PLL_FREQ = 3068
7130 06:54:04.617814 DQ_UI_PI_RATIO = 32
7131 06:54:04.620663 CA_UI_PI_RATIO = 0
7132 06:54:04.624247 ===================================
7133 06:54:04.627761 ===================================
7134 06:54:04.630895 memory_type:LPDDR4
7135 06:54:04.634515 GP_NUM : 10
7136 06:54:04.634600 SRAM_EN : 1
7137 06:54:04.637550 MD32_EN : 0
7138 06:54:04.640828 ===================================
7139 06:54:04.640908 [ANA_INIT] >>>>>>>>>>>>>>
7140 06:54:04.643848 <<<<<< [CONFIGURE PHASE]: ANA_TX
7141 06:54:04.647729 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7142 06:54:04.650685 ===================================
7143 06:54:04.653957 data_rate = 3200,PCW = 0X7600
7144 06:54:04.657173 ===================================
7145 06:54:04.661019 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7146 06:54:04.667611 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7147 06:54:04.673803 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7148 06:54:04.677408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7149 06:54:04.680544 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7150 06:54:04.684225 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7151 06:54:04.687534 [ANA_INIT] flow start
7152 06:54:04.687618 [ANA_INIT] PLL >>>>>>>>
7153 06:54:04.690830 [ANA_INIT] PLL <<<<<<<<
7154 06:54:04.694033 [ANA_INIT] MIDPI >>>>>>>>
7155 06:54:04.694116 [ANA_INIT] MIDPI <<<<<<<<
7156 06:54:04.696991 [ANA_INIT] DLL >>>>>>>>
7157 06:54:04.700737 [ANA_INIT] DLL <<<<<<<<
7158 06:54:04.700849 [ANA_INIT] flow end
7159 06:54:04.706995 ============ LP4 DIFF to SE enter ============
7160 06:54:04.710819 ============ LP4 DIFF to SE exit ============
7161 06:54:04.710896 [ANA_INIT] <<<<<<<<<<<<<
7162 06:54:04.713756 [Flow] Enable top DCM control >>>>>
7163 06:54:04.717480 [Flow] Enable top DCM control <<<<<
7164 06:54:04.720558 Enable DLL master slave shuffle
7165 06:54:04.727041 ==============================================================
7166 06:54:04.727125 Gating Mode config
7167 06:54:04.733681 ==============================================================
7168 06:54:04.737035 Config description:
7169 06:54:04.747165 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7170 06:54:04.753984 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7171 06:54:04.757016 SELPH_MODE 0: By rank 1: By Phase
7172 06:54:04.763724 ==============================================================
7173 06:54:04.767192 GAT_TRACK_EN = 1
7174 06:54:04.770344 RX_GATING_MODE = 2
7175 06:54:04.770417 RX_GATING_TRACK_MODE = 2
7176 06:54:04.773715 SELPH_MODE = 1
7177 06:54:04.777364 PICG_EARLY_EN = 1
7178 06:54:04.780139 VALID_LAT_VALUE = 1
7179 06:54:04.787335 ==============================================================
7180 06:54:04.790393 Enter into Gating configuration >>>>
7181 06:54:04.793755 Exit from Gating configuration <<<<
7182 06:54:04.796828 Enter into DVFS_PRE_config >>>>>
7183 06:54:04.807173 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7184 06:54:04.810140 Exit from DVFS_PRE_config <<<<<
7185 06:54:04.813637 Enter into PICG configuration >>>>
7186 06:54:04.816801 Exit from PICG configuration <<<<
7187 06:54:04.820310 [RX_INPUT] configuration >>>>>
7188 06:54:04.823816 [RX_INPUT] configuration <<<<<
7189 06:54:04.826834 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7190 06:54:04.834003 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7191 06:54:04.840283 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7192 06:54:04.846899 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7193 06:54:04.850386 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7194 06:54:04.857268 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7195 06:54:04.860158 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7196 06:54:04.866926 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7197 06:54:04.870078 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7198 06:54:04.873754 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7199 06:54:04.877103 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7200 06:54:04.883872 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7201 06:54:04.887289 ===================================
7202 06:54:04.887373 LPDDR4 DRAM CONFIGURATION
7203 06:54:04.890100 ===================================
7204 06:54:04.893703 EX_ROW_EN[0] = 0x0
7205 06:54:04.897058 EX_ROW_EN[1] = 0x0
7206 06:54:04.897163 LP4Y_EN = 0x0
7207 06:54:04.900526 WORK_FSP = 0x1
7208 06:54:04.900602 WL = 0x5
7209 06:54:04.903536 RL = 0x5
7210 06:54:04.903634 BL = 0x2
7211 06:54:04.907287 RPST = 0x0
7212 06:54:04.907386 RD_PRE = 0x0
7213 06:54:04.910146 WR_PRE = 0x1
7214 06:54:04.910224 WR_PST = 0x1
7215 06:54:04.913844 DBI_WR = 0x0
7216 06:54:04.913920 DBI_RD = 0x0
7217 06:54:04.916651 OTF = 0x1
7218 06:54:04.920241 ===================================
7219 06:54:04.923912 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7220 06:54:04.926651 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7221 06:54:04.933422 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7222 06:54:04.936874 ===================================
7223 06:54:04.936951 LPDDR4 DRAM CONFIGURATION
7224 06:54:04.939998 ===================================
7225 06:54:04.943782 EX_ROW_EN[0] = 0x10
7226 06:54:04.943895 EX_ROW_EN[1] = 0x0
7227 06:54:04.947373 LP4Y_EN = 0x0
7228 06:54:04.947470 WORK_FSP = 0x1
7229 06:54:04.950232 WL = 0x5
7230 06:54:04.950314 RL = 0x5
7231 06:54:04.953643 BL = 0x2
7232 06:54:04.956753 RPST = 0x0
7233 06:54:04.956836 RD_PRE = 0x0
7234 06:54:04.960386 WR_PRE = 0x1
7235 06:54:04.960467 WR_PST = 0x1
7236 06:54:04.963561 DBI_WR = 0x0
7237 06:54:04.963642 DBI_RD = 0x0
7238 06:54:04.967003 OTF = 0x1
7239 06:54:04.969981 ===================================
7240 06:54:04.973884 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7241 06:54:04.976787 ==
7242 06:54:04.980197 Dram Type= 6, Freq= 0, CH_0, rank 0
7243 06:54:04.983795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7244 06:54:04.983903 ==
7245 06:54:04.986963 [Duty_Offset_Calibration]
7246 06:54:04.987046 B0:2 B1:-1 CA:1
7247 06:54:04.987110
7248 06:54:04.990286 [DutyScan_Calibration_Flow] k_type=0
7249 06:54:04.999249
7250 06:54:04.999330 ==CLK 0==
7251 06:54:05.002523 Final CLK duty delay cell = -4
7252 06:54:05.005796 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7253 06:54:05.009543 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7254 06:54:05.013276 [-4] AVG Duty = 4937%(X100)
7255 06:54:05.013358
7256 06:54:05.016243 CH0 CLK Duty spec in!! Max-Min= 187%
7257 06:54:05.019176 [DutyScan_Calibration_Flow] ====Done====
7258 06:54:05.019258
7259 06:54:05.022820 [DutyScan_Calibration_Flow] k_type=1
7260 06:54:05.038844
7261 06:54:05.038925 ==DQS 0 ==
7262 06:54:05.042172 Final DQS duty delay cell = 0
7263 06:54:05.045968 [0] MAX Duty = 5125%(X100), DQS PI = 56
7264 06:54:05.048852 [0] MIN Duty = 5000%(X100), DQS PI = 14
7265 06:54:05.048948 [0] AVG Duty = 5062%(X100)
7266 06:54:05.052289
7267 06:54:05.052369 ==DQS 1 ==
7268 06:54:05.055967 Final DQS duty delay cell = -4
7269 06:54:05.058665 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7270 06:54:05.062411 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7271 06:54:05.065352 [-4] AVG Duty = 5046%(X100)
7272 06:54:05.065449
7273 06:54:05.068576 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7274 06:54:05.068657
7275 06:54:05.072111 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7276 06:54:05.075917 [DutyScan_Calibration_Flow] ====Done====
7277 06:54:05.075998
7278 06:54:05.078848 [DutyScan_Calibration_Flow] k_type=3
7279 06:54:05.096430
7280 06:54:05.096516 ==DQM 0 ==
7281 06:54:05.099642 Final DQM duty delay cell = 0
7282 06:54:05.103226 [0] MAX Duty = 5000%(X100), DQS PI = 18
7283 06:54:05.106099 [0] MIN Duty = 4875%(X100), DQS PI = 6
7284 06:54:05.106184 [0] AVG Duty = 4937%(X100)
7285 06:54:05.109565
7286 06:54:05.109649 ==DQM 1 ==
7287 06:54:05.113000 Final DQM duty delay cell = 0
7288 06:54:05.116338 [0] MAX Duty = 5218%(X100), DQS PI = 58
7289 06:54:05.119578 [0] MIN Duty = 4969%(X100), DQS PI = 20
7290 06:54:05.119662 [0] AVG Duty = 5093%(X100)
7291 06:54:05.123175
7292 06:54:05.126127 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7293 06:54:05.126236
7294 06:54:05.129680 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7295 06:54:05.133610 [DutyScan_Calibration_Flow] ====Done====
7296 06:54:05.133691
7297 06:54:05.136357 [DutyScan_Calibration_Flow] k_type=2
7298 06:54:05.153267
7299 06:54:05.153349 ==DQ 0 ==
7300 06:54:05.156541 Final DQ duty delay cell = 0
7301 06:54:05.160042 [0] MAX Duty = 5156%(X100), DQS PI = 0
7302 06:54:05.163528 [0] MIN Duty = 5031%(X100), DQS PI = 4
7303 06:54:05.163609 [0] AVG Duty = 5093%(X100)
7304 06:54:05.163672
7305 06:54:05.166712 ==DQ 1 ==
7306 06:54:05.170095 Final DQ duty delay cell = 0
7307 06:54:05.173177 [0] MAX Duty = 5031%(X100), DQS PI = 14
7308 06:54:05.176999 [0] MIN Duty = 4907%(X100), DQS PI = 18
7309 06:54:05.177080 [0] AVG Duty = 4969%(X100)
7310 06:54:05.177143
7311 06:54:05.179923 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7312 06:54:05.180004
7313 06:54:05.183594 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7314 06:54:05.190253 [DutyScan_Calibration_Flow] ====Done====
7315 06:54:05.190336 ==
7316 06:54:05.193129 Dram Type= 6, Freq= 0, CH_1, rank 0
7317 06:54:05.196348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7318 06:54:05.196429 ==
7319 06:54:05.199825 [Duty_Offset_Calibration]
7320 06:54:05.199905 B0:1 B1:1 CA:2
7321 06:54:05.199968
7322 06:54:05.203286 [DutyScan_Calibration_Flow] k_type=0
7323 06:54:05.213406
7324 06:54:05.213489 ==CLK 0==
7325 06:54:05.216973 Final CLK duty delay cell = 0
7326 06:54:05.220377 [0] MAX Duty = 5187%(X100), DQS PI = 24
7327 06:54:05.223839 [0] MIN Duty = 4938%(X100), DQS PI = 50
7328 06:54:05.223921 [0] AVG Duty = 5062%(X100)
7329 06:54:05.223986
7330 06:54:05.226836 CH1 CLK Duty spec in!! Max-Min= 249%
7331 06:54:05.233489 [DutyScan_Calibration_Flow] ====Done====
7332 06:54:05.233566
7333 06:54:05.237229 [DutyScan_Calibration_Flow] k_type=1
7334 06:54:05.253085
7335 06:54:05.253165 ==DQS 0 ==
7336 06:54:05.256630 Final DQS duty delay cell = 0
7337 06:54:05.260264 [0] MAX Duty = 5062%(X100), DQS PI = 22
7338 06:54:05.263208 [0] MIN Duty = 4813%(X100), DQS PI = 52
7339 06:54:05.266645 [0] AVG Duty = 4937%(X100)
7340 06:54:05.266759
7341 06:54:05.266852 ==DQS 1 ==
7342 06:54:05.269606 Final DQS duty delay cell = 0
7343 06:54:05.273056 [0] MAX Duty = 5031%(X100), DQS PI = 54
7344 06:54:05.276754 [0] MIN Duty = 4938%(X100), DQS PI = 12
7345 06:54:05.279956 [0] AVG Duty = 4984%(X100)
7346 06:54:05.280062
7347 06:54:05.283573 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7348 06:54:05.283646
7349 06:54:05.286446 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7350 06:54:05.289564 [DutyScan_Calibration_Flow] ====Done====
7351 06:54:05.289639
7352 06:54:05.293317 [DutyScan_Calibration_Flow] k_type=3
7353 06:54:05.310456
7354 06:54:05.310541 ==DQM 0 ==
7355 06:54:05.313334 Final DQM duty delay cell = 0
7356 06:54:05.316637 [0] MAX Duty = 5156%(X100), DQS PI = 20
7357 06:54:05.320442 [0] MIN Duty = 4813%(X100), DQS PI = 50
7358 06:54:05.323336 [0] AVG Duty = 4984%(X100)
7359 06:54:05.323419
7360 06:54:05.323483 ==DQM 1 ==
7361 06:54:05.326733 Final DQM duty delay cell = 0
7362 06:54:05.330288 [0] MAX Duty = 5125%(X100), DQS PI = 10
7363 06:54:05.333118 [0] MIN Duty = 4907%(X100), DQS PI = 20
7364 06:54:05.336743 [0] AVG Duty = 5016%(X100)
7365 06:54:05.336824
7366 06:54:05.339848 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7367 06:54:05.339929
7368 06:54:05.343351 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7369 06:54:05.346712 [DutyScan_Calibration_Flow] ====Done====
7370 06:54:05.346791
7371 06:54:05.349927 [DutyScan_Calibration_Flow] k_type=2
7372 06:54:05.367317
7373 06:54:05.367399 ==DQ 0 ==
7374 06:54:05.370557 Final DQ duty delay cell = 0
7375 06:54:05.374018 [0] MAX Duty = 5156%(X100), DQS PI = 20
7376 06:54:05.377237 [0] MIN Duty = 4907%(X100), DQS PI = 52
7377 06:54:05.377332 [0] AVG Duty = 5031%(X100)
7378 06:54:05.380447
7379 06:54:05.380566 ==DQ 1 ==
7380 06:54:05.384239 Final DQ duty delay cell = 0
7381 06:54:05.387260 [0] MAX Duty = 5093%(X100), DQS PI = 6
7382 06:54:05.390225 [0] MIN Duty = 5031%(X100), DQS PI = 0
7383 06:54:05.390306 [0] AVG Duty = 5062%(X100)
7384 06:54:05.390368
7385 06:54:05.394067 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7386 06:54:05.394163
7387 06:54:05.396917 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7388 06:54:05.403744 [DutyScan_Calibration_Flow] ====Done====
7389 06:54:05.407311 nWR fixed to 30
7390 06:54:05.407391 [ModeRegInit_LP4] CH0 RK0
7391 06:54:05.410720 [ModeRegInit_LP4] CH0 RK1
7392 06:54:05.414022 [ModeRegInit_LP4] CH1 RK0
7393 06:54:05.414102 [ModeRegInit_LP4] CH1 RK1
7394 06:54:05.417036 match AC timing 5
7395 06:54:05.420631 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7396 06:54:05.423935 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7397 06:54:05.430548 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7398 06:54:05.434185 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7399 06:54:05.440806 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7400 06:54:05.440903 [MiockJmeterHQA]
7401 06:54:05.440995
7402 06:54:05.443622 [DramcMiockJmeter] u1RxGatingPI = 0
7403 06:54:05.443717 0 : 4363, 4137
7404 06:54:05.447298 4 : 4252, 4027
7405 06:54:05.447395 8 : 4253, 4026
7406 06:54:05.450414 12 : 4365, 4140
7407 06:54:05.450512 16 : 4252, 4027
7408 06:54:05.453433 20 : 4252, 4027
7409 06:54:05.453513 24 : 4252, 4027
7410 06:54:05.456953 28 : 4255, 4029
7411 06:54:05.457050 32 : 4363, 4137
7412 06:54:05.457115 36 : 4252, 4027
7413 06:54:05.460604 40 : 4363, 4138
7414 06:54:05.460685 44 : 4252, 4027
7415 06:54:05.463592 48 : 4252, 4027
7416 06:54:05.463722 52 : 4255, 4029
7417 06:54:05.466968 56 : 4361, 4137
7418 06:54:05.467100 60 : 4250, 4026
7419 06:54:05.467232 64 : 4360, 4138
7420 06:54:05.470451 68 : 4250, 4026
7421 06:54:05.470566 72 : 4250, 4027
7422 06:54:05.473625 76 : 4252, 4030
7423 06:54:05.473706 80 : 4253, 4029
7424 06:54:05.477072 84 : 4361, 4137
7425 06:54:05.477174 88 : 4250, 4026
7426 06:54:05.480239 92 : 4360, 4137
7427 06:54:05.480319 96 : 4255, 3071
7428 06:54:05.480381 100 : 4250, 0
7429 06:54:05.483782 104 : 4250, 0
7430 06:54:05.483882 108 : 4250, 0
7431 06:54:05.487269 112 : 4250, 0
7432 06:54:05.487381 116 : 4250, 0
7433 06:54:05.487473 120 : 4250, 0
7434 06:54:05.490637 124 : 4253, 0
7435 06:54:05.490753 128 : 4250, 0
7436 06:54:05.490853 132 : 4360, 0
7437 06:54:05.493764 136 : 4250, 0
7438 06:54:05.493846 140 : 4250, 0
7439 06:54:05.497000 144 : 4360, 0
7440 06:54:05.497107 148 : 4250, 0
7441 06:54:05.497196 152 : 4250, 0
7442 06:54:05.500434 156 : 4249, 0
7443 06:54:05.500551 160 : 4250, 0
7444 06:54:05.503569 164 : 4253, 0
7445 06:54:05.503677 168 : 4361, 0
7446 06:54:05.503767 172 : 4250, 0
7447 06:54:05.507297 176 : 4250, 0
7448 06:54:05.507411 180 : 4252, 0
7449 06:54:05.507508 184 : 4360, 0
7450 06:54:05.510429 188 : 4360, 0
7451 06:54:05.510539 192 : 4250, 0
7452 06:54:05.513892 196 : 4249, 0
7453 06:54:05.514003 200 : 4361, 0
7454 06:54:05.514093 204 : 4250, 0
7455 06:54:05.516964 208 : 4249, 0
7456 06:54:05.517070 212 : 4250, 42
7457 06:54:05.520697 216 : 4250, 3509
7458 06:54:05.520816 220 : 4250, 4026
7459 06:54:05.523569 224 : 4250, 4027
7460 06:54:05.523641 228 : 4250, 4027
7461 06:54:05.527258 232 : 4250, 4026
7462 06:54:05.527370 236 : 4253, 4029
7463 06:54:05.527462 240 : 4250, 4027
7464 06:54:05.530565 244 : 4361, 4137
7465 06:54:05.530664 248 : 4361, 4137
7466 06:54:05.533716 252 : 4250, 4027
7467 06:54:05.533813 256 : 4363, 4140
7468 06:54:05.536994 260 : 4361, 4137
7469 06:54:05.537098 264 : 4250, 4027
7470 06:54:05.540568 268 : 4250, 4027
7471 06:54:05.540674 272 : 4252, 4029
7472 06:54:05.543811 276 : 4250, 4026
7473 06:54:05.543887 280 : 4250, 4027
7474 06:54:05.547284 284 : 4250, 4026
7475 06:54:05.547385 288 : 4250, 4026
7476 06:54:05.550879 292 : 4250, 4027
7477 06:54:05.550954 296 : 4361, 4137
7478 06:54:05.551016 300 : 4361, 4137
7479 06:54:05.553833 304 : 4250, 4027
7480 06:54:05.553932 308 : 4363, 4140
7481 06:54:05.556871 312 : 4361, 4137
7482 06:54:05.556970 316 : 4250, 4027
7483 06:54:05.560560 320 : 4250, 4027
7484 06:54:05.560677 324 : 4252, 4029
7485 06:54:05.563935 328 : 4250, 4027
7486 06:54:05.564034 332 : 4250, 2899
7487 06:54:05.566905 336 : 4250, 72
7488 06:54:05.566989
7489 06:54:05.567051 MIOCK jitter meter ch=0
7490 06:54:05.567114
7491 06:54:05.570525 1T = (336-100) = 236 dly cells
7492 06:54:05.576842 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7493 06:54:05.576925 ==
7494 06:54:05.580538 Dram Type= 6, Freq= 0, CH_0, rank 0
7495 06:54:05.583652 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7496 06:54:05.583734 ==
7497 06:54:05.590082 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7498 06:54:05.594030 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7499 06:54:05.597047 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7500 06:54:05.603743 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7501 06:54:05.613529 [CA 0] Center 44 (14~75) winsize 62
7502 06:54:05.616491 [CA 1] Center 44 (14~75) winsize 62
7503 06:54:05.620251 [CA 2] Center 40 (11~69) winsize 59
7504 06:54:05.623187 [CA 3] Center 39 (10~69) winsize 60
7505 06:54:05.626990 [CA 4] Center 38 (8~68) winsize 61
7506 06:54:05.629866 [CA 5] Center 37 (7~67) winsize 61
7507 06:54:05.629938
7508 06:54:05.633218 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7509 06:54:05.633304
7510 06:54:05.636592 [CATrainingPosCal] consider 1 rank data
7511 06:54:05.639777 u2DelayCellTimex100 = 275/100 ps
7512 06:54:05.643478 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7513 06:54:05.649842 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7514 06:54:05.653158 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7515 06:54:05.656968 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7516 06:54:05.660335 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7517 06:54:05.663298 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7518 06:54:05.663372
7519 06:54:05.667083 CA PerBit enable=1, Macro0, CA PI delay=37
7520 06:54:05.667159
7521 06:54:05.669874 [CBTSetCACLKResult] CA Dly = 37
7522 06:54:05.673154 CS Dly: 11 (0~42)
7523 06:54:05.676746 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7524 06:54:05.680007 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7525 06:54:05.680086 ==
7526 06:54:05.683091 Dram Type= 6, Freq= 0, CH_0, rank 1
7527 06:54:05.686923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 06:54:05.689999 ==
7529 06:54:05.693548 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7530 06:54:05.696526 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7531 06:54:05.703402 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7532 06:54:05.709892 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7533 06:54:05.717312 [CA 0] Center 43 (13~74) winsize 62
7534 06:54:05.720382 [CA 1] Center 43 (13~74) winsize 62
7535 06:54:05.723683 [CA 2] Center 39 (10~69) winsize 60
7536 06:54:05.727347 [CA 3] Center 38 (9~68) winsize 60
7537 06:54:05.730370 [CA 4] Center 37 (7~67) winsize 61
7538 06:54:05.733768 [CA 5] Center 37 (7~67) winsize 61
7539 06:54:05.733845
7540 06:54:05.737200 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7541 06:54:05.737280
7542 06:54:05.740706 [CATrainingPosCal] consider 2 rank data
7543 06:54:05.743862 u2DelayCellTimex100 = 275/100 ps
7544 06:54:05.747520 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7545 06:54:05.754206 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7546 06:54:05.757357 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7547 06:54:05.760765 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7548 06:54:05.763658 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7549 06:54:05.767198 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7550 06:54:05.767301
7551 06:54:05.770387 CA PerBit enable=1, Macro0, CA PI delay=37
7552 06:54:05.770512
7553 06:54:05.773569 [CBTSetCACLKResult] CA Dly = 37
7554 06:54:05.777403 CS Dly: 11 (0~43)
7555 06:54:05.780937 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7556 06:54:05.783696 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7557 06:54:05.783778
7558 06:54:05.787283 ----->DramcWriteLeveling(PI) begin...
7559 06:54:05.787383 ==
7560 06:54:05.790445 Dram Type= 6, Freq= 0, CH_0, rank 0
7561 06:54:05.797218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7562 06:54:05.797298 ==
7563 06:54:05.800262 Write leveling (Byte 0): 33 => 33
7564 06:54:05.800337 Write leveling (Byte 1): 27 => 27
7565 06:54:05.803879 DramcWriteLeveling(PI) end<-----
7566 06:54:05.803955
7567 06:54:05.804017 ==
7568 06:54:05.807042 Dram Type= 6, Freq= 0, CH_0, rank 0
7569 06:54:05.813538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7570 06:54:05.813618 ==
7571 06:54:05.817160 [Gating] SW mode calibration
7572 06:54:05.823899 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7573 06:54:05.826948 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7574 06:54:05.833681 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 06:54:05.837373 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 06:54:05.840982 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 06:54:05.843834 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 06:54:05.850612 1 4 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7579 06:54:05.853949 1 4 20 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
7580 06:54:05.857003 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7581 06:54:05.863754 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7582 06:54:05.867471 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7583 06:54:05.870854 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7584 06:54:05.877307 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7585 06:54:05.880580 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7586 06:54:05.883621 1 5 16 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
7587 06:54:05.890606 1 5 20 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
7588 06:54:05.893674 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
7589 06:54:05.897069 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 06:54:05.903789 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 06:54:05.906737 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 06:54:05.910492 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 06:54:05.916860 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 06:54:05.920511 1 6 16 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
7595 06:54:05.923506 1 6 20 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7596 06:54:05.930212 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7597 06:54:05.933297 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 06:54:05.936525 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 06:54:05.943560 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 06:54:05.946701 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 06:54:05.950252 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 06:54:05.956728 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 06:54:05.960051 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7604 06:54:05.963615 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7605 06:54:05.970483 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 06:54:05.973621 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 06:54:05.976502 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 06:54:05.979819 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 06:54:05.986679 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 06:54:05.990127 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 06:54:05.993592 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 06:54:05.999854 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 06:54:06.003416 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 06:54:06.006431 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 06:54:06.013064 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 06:54:06.016542 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 06:54:06.019704 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7618 06:54:06.026398 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7619 06:54:06.030243 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7620 06:54:06.033375 Total UI for P1: 0, mck2ui 16
7621 06:54:06.036286 best dqsien dly found for B0: ( 1, 9, 14)
7622 06:54:06.039980 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7623 06:54:06.046567 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 06:54:06.046642 Total UI for P1: 0, mck2ui 16
7625 06:54:06.053040 best dqsien dly found for B1: ( 1, 9, 22)
7626 06:54:06.056857 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7627 06:54:06.060216 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7628 06:54:06.060322
7629 06:54:06.063193 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7630 06:54:06.066621 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7631 06:54:06.069537 [Gating] SW calibration Done
7632 06:54:06.069621 ==
7633 06:54:06.073243 Dram Type= 6, Freq= 0, CH_0, rank 0
7634 06:54:06.076254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7635 06:54:06.076321 ==
7636 06:54:06.080010 RX Vref Scan: 0
7637 06:54:06.080077
7638 06:54:06.080137 RX Vref 0 -> 0, step: 1
7639 06:54:06.080193
7640 06:54:06.083624 RX Delay 0 -> 252, step: 8
7641 06:54:06.086746 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7642 06:54:06.093167 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7643 06:54:06.096863 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7644 06:54:06.099665 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7645 06:54:06.103286 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7646 06:54:06.106468 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7647 06:54:06.113255 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7648 06:54:06.116902 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7649 06:54:06.119876 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7650 06:54:06.122863 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7651 06:54:06.126685 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7652 06:54:06.133751 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7653 06:54:06.136671 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7654 06:54:06.139970 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
7655 06:54:06.143420 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7656 06:54:06.146582 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7657 06:54:06.146684 ==
7658 06:54:06.149958 Dram Type= 6, Freq= 0, CH_0, rank 0
7659 06:54:06.156720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7660 06:54:06.156837 ==
7661 06:54:06.156936 DQS Delay:
7662 06:54:06.160088 DQS0 = 0, DQS1 = 0
7663 06:54:06.160190 DQM Delay:
7664 06:54:06.163125 DQM0 = 132, DQM1 = 123
7665 06:54:06.163231 DQ Delay:
7666 06:54:06.166609 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7667 06:54:06.169938 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7668 06:54:06.173575 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7669 06:54:06.176646 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =135
7670 06:54:06.176746
7671 06:54:06.176841
7672 06:54:06.176936 ==
7673 06:54:06.180199 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 06:54:06.183382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 06:54:06.186835 ==
7676 06:54:06.186933
7677 06:54:06.187037
7678 06:54:06.187150 TX Vref Scan disable
7679 06:54:06.190319 == TX Byte 0 ==
7680 06:54:06.193180 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7681 06:54:06.196868 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7682 06:54:06.199693 == TX Byte 1 ==
7683 06:54:06.203366 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7684 06:54:06.206879 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7685 06:54:06.209920 ==
7686 06:54:06.213223 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 06:54:06.216368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7688 06:54:06.216477 ==
7689 06:54:06.229176
7690 06:54:06.232849 TX Vref early break, caculate TX vref
7691 06:54:06.236217 TX Vref=16, minBit 12, minWin=21, winSum=358
7692 06:54:06.239973 TX Vref=18, minBit 4, minWin=22, winSum=370
7693 06:54:06.242833 TX Vref=20, minBit 4, minWin=23, winSum=383
7694 06:54:06.245908 TX Vref=22, minBit 4, minWin=23, winSum=392
7695 06:54:06.249619 TX Vref=24, minBit 0, minWin=24, winSum=403
7696 06:54:06.256227 TX Vref=26, minBit 1, minWin=25, winSum=415
7697 06:54:06.259448 TX Vref=28, minBit 0, minWin=26, winSum=423
7698 06:54:06.262762 TX Vref=30, minBit 0, minWin=25, winSum=418
7699 06:54:06.265800 TX Vref=32, minBit 10, minWin=24, winSum=409
7700 06:54:06.269386 TX Vref=34, minBit 4, minWin=24, winSum=397
7701 06:54:06.276017 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 28
7702 06:54:06.276097
7703 06:54:06.279382 Final TX Range 0 Vref 28
7704 06:54:06.279459
7705 06:54:06.279520 ==
7706 06:54:06.283038 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 06:54:06.286253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 06:54:06.286338 ==
7709 06:54:06.286401
7710 06:54:06.286472
7711 06:54:06.289824 TX Vref Scan disable
7712 06:54:06.295926 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7713 06:54:06.296017 == TX Byte 0 ==
7714 06:54:06.299760 u2DelayCellOfst[0]=14 cells (4 PI)
7715 06:54:06.302537 u2DelayCellOfst[1]=21 cells (6 PI)
7716 06:54:06.306006 u2DelayCellOfst[2]=10 cells (3 PI)
7717 06:54:06.309783 u2DelayCellOfst[3]=14 cells (4 PI)
7718 06:54:06.312594 u2DelayCellOfst[4]=10 cells (3 PI)
7719 06:54:06.315950 u2DelayCellOfst[5]=0 cells (0 PI)
7720 06:54:06.319170 u2DelayCellOfst[6]=21 cells (6 PI)
7721 06:54:06.322410 u2DelayCellOfst[7]=21 cells (6 PI)
7722 06:54:06.325816 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7723 06:54:06.329186 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7724 06:54:06.332638 == TX Byte 1 ==
7725 06:54:06.332739 u2DelayCellOfst[8]=0 cells (0 PI)
7726 06:54:06.336352 u2DelayCellOfst[9]=0 cells (0 PI)
7727 06:54:06.339408 u2DelayCellOfst[10]=7 cells (2 PI)
7728 06:54:06.342680 u2DelayCellOfst[11]=0 cells (0 PI)
7729 06:54:06.346424 u2DelayCellOfst[12]=10 cells (3 PI)
7730 06:54:06.349309 u2DelayCellOfst[13]=10 cells (3 PI)
7731 06:54:06.352577 u2DelayCellOfst[14]=17 cells (5 PI)
7732 06:54:06.356108 u2DelayCellOfst[15]=10 cells (3 PI)
7733 06:54:06.359061 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7734 06:54:06.366279 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7735 06:54:06.366360 DramC Write-DBI on
7736 06:54:06.366423 ==
7737 06:54:06.369305 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 06:54:06.372998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 06:54:06.373081 ==
7740 06:54:06.376138
7741 06:54:06.376219
7742 06:54:06.376282 TX Vref Scan disable
7743 06:54:06.379654 == TX Byte 0 ==
7744 06:54:06.382775 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7745 06:54:06.385928 == TX Byte 1 ==
7746 06:54:06.389049 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7747 06:54:06.389179 DramC Write-DBI off
7748 06:54:06.392645
7749 06:54:06.392718 [DATLAT]
7750 06:54:06.392779 Freq=1600, CH0 RK0
7751 06:54:06.392876
7752 06:54:06.396055 DATLAT Default: 0xf
7753 06:54:06.396173 0, 0xFFFF, sum = 0
7754 06:54:06.399351 1, 0xFFFF, sum = 0
7755 06:54:06.399453 2, 0xFFFF, sum = 0
7756 06:54:06.402947 3, 0xFFFF, sum = 0
7757 06:54:06.403063 4, 0xFFFF, sum = 0
7758 06:54:06.405979 5, 0xFFFF, sum = 0
7759 06:54:06.406079 6, 0xFFFF, sum = 0
7760 06:54:06.409381 7, 0xFFFF, sum = 0
7761 06:54:06.409488 8, 0xFFFF, sum = 0
7762 06:54:06.412955 9, 0xFFFF, sum = 0
7763 06:54:06.415966 10, 0xFFFF, sum = 0
7764 06:54:06.416069 11, 0xFFFF, sum = 0
7765 06:54:06.419747 12, 0xFFFF, sum = 0
7766 06:54:06.419860 13, 0xFFFF, sum = 0
7767 06:54:06.422547 14, 0x0, sum = 1
7768 06:54:06.422644 15, 0x0, sum = 2
7769 06:54:06.425966 16, 0x0, sum = 3
7770 06:54:06.426041 17, 0x0, sum = 4
7771 06:54:06.426105 best_step = 15
7772 06:54:06.429349
7773 06:54:06.429462 ==
7774 06:54:06.432938 Dram Type= 6, Freq= 0, CH_0, rank 0
7775 06:54:06.435765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7776 06:54:06.435872 ==
7777 06:54:06.435963 RX Vref Scan: 1
7778 06:54:06.436075
7779 06:54:06.439293 Set Vref Range= 24 -> 127
7780 06:54:06.439423
7781 06:54:06.442502 RX Vref 24 -> 127, step: 1
7782 06:54:06.442587
7783 06:54:06.446126 RX Delay 11 -> 252, step: 4
7784 06:54:06.446227
7785 06:54:06.449100 Set Vref, RX VrefLevel [Byte0]: 24
7786 06:54:06.452526 [Byte1]: 24
7787 06:54:06.452602
7788 06:54:06.456154 Set Vref, RX VrefLevel [Byte0]: 25
7789 06:54:06.459284 [Byte1]: 25
7790 06:54:06.459402
7791 06:54:06.462753 Set Vref, RX VrefLevel [Byte0]: 26
7792 06:54:06.465807 [Byte1]: 26
7793 06:54:06.469677
7794 06:54:06.469755 Set Vref, RX VrefLevel [Byte0]: 27
7795 06:54:06.472615 [Byte1]: 27
7796 06:54:06.477698
7797 06:54:06.477783 Set Vref, RX VrefLevel [Byte0]: 28
7798 06:54:06.480772 [Byte1]: 28
7799 06:54:06.484911
7800 06:54:06.485021 Set Vref, RX VrefLevel [Byte0]: 29
7801 06:54:06.488309 [Byte1]: 29
7802 06:54:06.492536
7803 06:54:06.492639 Set Vref, RX VrefLevel [Byte0]: 30
7804 06:54:06.495804 [Byte1]: 30
7805 06:54:06.499729
7806 06:54:06.499832 Set Vref, RX VrefLevel [Byte0]: 31
7807 06:54:06.503253 [Byte1]: 31
7808 06:54:06.507373
7809 06:54:06.507449 Set Vref, RX VrefLevel [Byte0]: 32
7810 06:54:06.510960 [Byte1]: 32
7811 06:54:06.514987
7812 06:54:06.515068 Set Vref, RX VrefLevel [Byte0]: 33
7813 06:54:06.518699 [Byte1]: 33
7814 06:54:06.523094
7815 06:54:06.523165 Set Vref, RX VrefLevel [Byte0]: 34
7816 06:54:06.526056 [Byte1]: 34
7817 06:54:06.530286
7818 06:54:06.530357 Set Vref, RX VrefLevel [Byte0]: 35
7819 06:54:06.533866 [Byte1]: 35
7820 06:54:06.538270
7821 06:54:06.538372 Set Vref, RX VrefLevel [Byte0]: 36
7822 06:54:06.541746 [Byte1]: 36
7823 06:54:06.545818
7824 06:54:06.545891 Set Vref, RX VrefLevel [Byte0]: 37
7825 06:54:06.549385 [Byte1]: 37
7826 06:54:06.553591
7827 06:54:06.553672 Set Vref, RX VrefLevel [Byte0]: 38
7828 06:54:06.556737 [Byte1]: 38
7829 06:54:06.560945
7830 06:54:06.561018 Set Vref, RX VrefLevel [Byte0]: 39
7831 06:54:06.564007 [Byte1]: 39
7832 06:54:06.568836
7833 06:54:06.568946 Set Vref, RX VrefLevel [Byte0]: 40
7834 06:54:06.571844 [Byte1]: 40
7835 06:54:06.576064
7836 06:54:06.576146 Set Vref, RX VrefLevel [Byte0]: 41
7837 06:54:06.579813 [Byte1]: 41
7838 06:54:06.584019
7839 06:54:06.584099 Set Vref, RX VrefLevel [Byte0]: 42
7840 06:54:06.586937 [Byte1]: 42
7841 06:54:06.591232
7842 06:54:06.591358 Set Vref, RX VrefLevel [Byte0]: 43
7843 06:54:06.594500 [Byte1]: 43
7844 06:54:06.599174
7845 06:54:06.599277 Set Vref, RX VrefLevel [Byte0]: 44
7846 06:54:06.602345 [Byte1]: 44
7847 06:54:06.606957
7848 06:54:06.607043 Set Vref, RX VrefLevel [Byte0]: 45
7849 06:54:06.609752 [Byte1]: 45
7850 06:54:06.614024
7851 06:54:06.614133 Set Vref, RX VrefLevel [Byte0]: 46
7852 06:54:06.617443 [Byte1]: 46
7853 06:54:06.622244
7854 06:54:06.622320 Set Vref, RX VrefLevel [Byte0]: 47
7855 06:54:06.625441 [Byte1]: 47
7856 06:54:06.629587
7857 06:54:06.629677 Set Vref, RX VrefLevel [Byte0]: 48
7858 06:54:06.632871 [Byte1]: 48
7859 06:54:06.637129
7860 06:54:06.637257 Set Vref, RX VrefLevel [Byte0]: 49
7861 06:54:06.640613 [Byte1]: 49
7862 06:54:06.644716
7863 06:54:06.644848 Set Vref, RX VrefLevel [Byte0]: 50
7864 06:54:06.647913 [Byte1]: 50
7865 06:54:06.652309
7866 06:54:06.652384 Set Vref, RX VrefLevel [Byte0]: 51
7867 06:54:06.655714 [Byte1]: 51
7868 06:54:06.659778
7869 06:54:06.659873 Set Vref, RX VrefLevel [Byte0]: 52
7870 06:54:06.663300 [Byte1]: 52
7871 06:54:06.667549
7872 06:54:06.670512 Set Vref, RX VrefLevel [Byte0]: 53
7873 06:54:06.674192 [Byte1]: 53
7874 06:54:06.674265
7875 06:54:06.677058 Set Vref, RX VrefLevel [Byte0]: 54
7876 06:54:06.680471 [Byte1]: 54
7877 06:54:06.680580
7878 06:54:06.684137 Set Vref, RX VrefLevel [Byte0]: 55
7879 06:54:06.687241 [Byte1]: 55
7880 06:54:06.687336
7881 06:54:06.691040 Set Vref, RX VrefLevel [Byte0]: 56
7882 06:54:06.693975 [Byte1]: 56
7883 06:54:06.697930
7884 06:54:06.698005 Set Vref, RX VrefLevel [Byte0]: 57
7885 06:54:06.701303 [Byte1]: 57
7886 06:54:06.705530
7887 06:54:06.705665 Set Vref, RX VrefLevel [Byte0]: 58
7888 06:54:06.709038 [Byte1]: 58
7889 06:54:06.713186
7890 06:54:06.713288 Set Vref, RX VrefLevel [Byte0]: 59
7891 06:54:06.716530 [Byte1]: 59
7892 06:54:06.720534
7893 06:54:06.720643 Set Vref, RX VrefLevel [Byte0]: 60
7894 06:54:06.724176 [Byte1]: 60
7895 06:54:06.728553
7896 06:54:06.728626 Set Vref, RX VrefLevel [Byte0]: 61
7897 06:54:06.731494 [Byte1]: 61
7898 06:54:06.735839
7899 06:54:06.735920 Set Vref, RX VrefLevel [Byte0]: 62
7900 06:54:06.739133 [Byte1]: 62
7901 06:54:06.743744
7902 06:54:06.743843 Set Vref, RX VrefLevel [Byte0]: 63
7903 06:54:06.747076 [Byte1]: 63
7904 06:54:06.751041
7905 06:54:06.751123 Set Vref, RX VrefLevel [Byte0]: 64
7906 06:54:06.754575 [Byte1]: 64
7907 06:54:06.759041
7908 06:54:06.759147 Set Vref, RX VrefLevel [Byte0]: 65
7909 06:54:06.762304 [Byte1]: 65
7910 06:54:06.766553
7911 06:54:06.766664 Set Vref, RX VrefLevel [Byte0]: 66
7912 06:54:06.769999 [Byte1]: 66
7913 06:54:06.773933
7914 06:54:06.774036 Set Vref, RX VrefLevel [Byte0]: 67
7915 06:54:06.777275 [Byte1]: 67
7916 06:54:06.781485
7917 06:54:06.781590 Set Vref, RX VrefLevel [Byte0]: 68
7918 06:54:06.785105 [Byte1]: 68
7919 06:54:06.789359
7920 06:54:06.789436 Set Vref, RX VrefLevel [Byte0]: 69
7921 06:54:06.792309 [Byte1]: 69
7922 06:54:06.797140
7923 06:54:06.797266 Set Vref, RX VrefLevel [Byte0]: 70
7924 06:54:06.800179 [Byte1]: 70
7925 06:54:06.804961
7926 06:54:06.805058 Set Vref, RX VrefLevel [Byte0]: 71
7927 06:54:06.807642 [Byte1]: 71
7928 06:54:06.812297
7929 06:54:06.812422 Set Vref, RX VrefLevel [Byte0]: 72
7930 06:54:06.815671 [Byte1]: 72
7931 06:54:06.819518
7932 06:54:06.819618 Set Vref, RX VrefLevel [Byte0]: 73
7933 06:54:06.822988 [Byte1]: 73
7934 06:54:06.827595
7935 06:54:06.827668 Set Vref, RX VrefLevel [Byte0]: 74
7936 06:54:06.830443 [Byte1]: 74
7937 06:54:06.834641
7938 06:54:06.834727 Set Vref, RX VrefLevel [Byte0]: 75
7939 06:54:06.838381 [Byte1]: 75
7940 06:54:06.842644
7941 06:54:06.842729 Final RX Vref Byte 0 = 62 to rank0
7942 06:54:06.845961 Final RX Vref Byte 1 = 62 to rank0
7943 06:54:06.849143 Final RX Vref Byte 0 = 62 to rank1
7944 06:54:06.852489 Final RX Vref Byte 1 = 62 to rank1==
7945 06:54:06.856089 Dram Type= 6, Freq= 0, CH_0, rank 0
7946 06:54:06.859553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7947 06:54:06.862551 ==
7948 06:54:06.862626 DQS Delay:
7949 06:54:06.862725 DQS0 = 0, DQS1 = 0
7950 06:54:06.865609 DQM Delay:
7951 06:54:06.865682 DQM0 = 129, DQM1 = 121
7952 06:54:06.869071 DQ Delay:
7953 06:54:06.872280 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7954 06:54:06.875482 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7955 06:54:06.878982 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7956 06:54:06.882190 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
7957 06:54:06.882284
7958 06:54:06.882378
7959 06:54:06.882452
7960 06:54:06.885470 [DramC_TX_OE_Calibration] TA2
7961 06:54:06.889341 Original DQ_B0 (3 6) =30, OEN = 27
7962 06:54:06.892203 Original DQ_B1 (3 6) =30, OEN = 27
7963 06:54:06.895681 24, 0x0, End_B0=24 End_B1=24
7964 06:54:06.895759 25, 0x0, End_B0=25 End_B1=25
7965 06:54:06.898870 26, 0x0, End_B0=26 End_B1=26
7966 06:54:06.902365 27, 0x0, End_B0=27 End_B1=27
7967 06:54:06.905390 28, 0x0, End_B0=28 End_B1=28
7968 06:54:06.905466 29, 0x0, End_B0=29 End_B1=29
7969 06:54:06.909291 30, 0x0, End_B0=30 End_B1=30
7970 06:54:06.912669 31, 0x4141, End_B0=30 End_B1=30
7971 06:54:06.915882 Byte0 end_step=30 best_step=27
7972 06:54:06.919200 Byte1 end_step=30 best_step=27
7973 06:54:06.922160 Byte0 TX OE(2T, 0.5T) = (3, 3)
7974 06:54:06.922273 Byte1 TX OE(2T, 0.5T) = (3, 3)
7975 06:54:06.925841
7976 06:54:06.925911
7977 06:54:06.932374 [DQSOSCAuto] RK0, (LSB)MR18= 0x1206, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
7978 06:54:06.935956 CH0 RK0: MR19=303, MR18=1206
7979 06:54:06.942388 CH0_RK0: MR19=0x303, MR18=0x1206, DQSOSC=400, MR23=63, INC=23, DEC=15
7980 06:54:06.942468
7981 06:54:06.945457 ----->DramcWriteLeveling(PI) begin...
7982 06:54:06.945531 ==
7983 06:54:06.949323 Dram Type= 6, Freq= 0, CH_0, rank 1
7984 06:54:06.952437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7985 06:54:06.952509 ==
7986 06:54:06.955558 Write leveling (Byte 0): 33 => 33
7987 06:54:06.959001 Write leveling (Byte 1): 26 => 26
7988 06:54:06.962151 DramcWriteLeveling(PI) end<-----
7989 06:54:06.962223
7990 06:54:06.962304 ==
7991 06:54:06.965798 Dram Type= 6, Freq= 0, CH_0, rank 1
7992 06:54:06.968815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7993 06:54:06.968930 ==
7994 06:54:06.971820 [Gating] SW mode calibration
7995 06:54:06.978922 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7996 06:54:06.985752 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7997 06:54:06.989083 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7998 06:54:06.992293 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7999 06:54:06.999008 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8000 06:54:07.001888 1 4 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
8001 06:54:07.005613 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8002 06:54:07.012231 1 4 20 | B1->B0 | 2a2a 3434 | 0 1 | (1 1) (1 1)
8003 06:54:07.015286 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8004 06:54:07.018774 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8005 06:54:07.025372 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8006 06:54:07.029220 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8007 06:54:07.032100 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8008 06:54:07.038942 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
8009 06:54:07.041832 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8010 06:54:07.045780 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8011 06:54:07.051882 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8012 06:54:07.055293 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 06:54:07.058894 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 06:54:07.061883 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 06:54:07.068786 1 6 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
8016 06:54:07.072351 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8017 06:54:07.075584 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8018 06:54:07.082232 1 6 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
8019 06:54:07.085130 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 06:54:07.088767 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 06:54:07.095559 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 06:54:07.098860 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8023 06:54:07.102372 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8024 06:54:07.108889 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8025 06:54:07.112148 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8026 06:54:07.115607 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8027 06:54:07.122193 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8028 06:54:07.125573 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 06:54:07.129158 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 06:54:07.135527 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 06:54:07.139019 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 06:54:07.142707 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 06:54:07.145681 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 06:54:07.152511 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 06:54:07.155526 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 06:54:07.159183 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 06:54:07.165851 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 06:54:07.169146 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 06:54:07.172214 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8040 06:54:07.178832 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8041 06:54:07.178913 Total UI for P1: 0, mck2ui 16
8042 06:54:07.185512 best dqsien dly found for B0: ( 1, 9, 8)
8043 06:54:07.189219 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8044 06:54:07.192552 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8045 06:54:07.199148 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 06:54:07.199257 Total UI for P1: 0, mck2ui 16
8047 06:54:07.205798 best dqsien dly found for B1: ( 1, 9, 18)
8048 06:54:07.208999 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8049 06:54:07.212339 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8050 06:54:07.212426
8051 06:54:07.215691 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8052 06:54:07.219085 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8053 06:54:07.222555 [Gating] SW calibration Done
8054 06:54:07.222662 ==
8055 06:54:07.226204 Dram Type= 6, Freq= 0, CH_0, rank 1
8056 06:54:07.228814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8057 06:54:07.228905 ==
8058 06:54:07.232572 RX Vref Scan: 0
8059 06:54:07.232676
8060 06:54:07.232789 RX Vref 0 -> 0, step: 1
8061 06:54:07.232880
8062 06:54:07.235443 RX Delay 0 -> 252, step: 8
8063 06:54:07.238803 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8064 06:54:07.245408 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8065 06:54:07.249061 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8066 06:54:07.252217 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8067 06:54:07.255865 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8068 06:54:07.259092 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8069 06:54:07.262551 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8070 06:54:07.269192 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8071 06:54:07.272401 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8072 06:54:07.275768 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8073 06:54:07.279041 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8074 06:54:07.282564 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8075 06:54:07.288955 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8076 06:54:07.292550 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8077 06:54:07.295363 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8078 06:54:07.298840 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8079 06:54:07.298943 ==
8080 06:54:07.302678 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 06:54:07.309056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 06:54:07.309161 ==
8083 06:54:07.309270 DQS Delay:
8084 06:54:07.312699 DQS0 = 0, DQS1 = 0
8085 06:54:07.312804 DQM Delay:
8086 06:54:07.312899 DQM0 = 131, DQM1 = 124
8087 06:54:07.315697 DQ Delay:
8088 06:54:07.319012 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =127
8089 06:54:07.322334 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8090 06:54:07.325436 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8091 06:54:07.328671 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8092 06:54:07.328775
8093 06:54:07.328864
8094 06:54:07.328952 ==
8095 06:54:07.332238 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 06:54:07.335564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 06:54:07.339167 ==
8098 06:54:07.339251
8099 06:54:07.339315
8100 06:54:07.339374 TX Vref Scan disable
8101 06:54:07.342571 == TX Byte 0 ==
8102 06:54:07.345969 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8103 06:54:07.348975 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8104 06:54:07.352757 == TX Byte 1 ==
8105 06:54:07.355838 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8106 06:54:07.358957 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8107 06:54:07.359055 ==
8108 06:54:07.362358 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 06:54:07.368814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 06:54:07.368926 ==
8111 06:54:07.383183
8112 06:54:07.386000 TX Vref early break, caculate TX vref
8113 06:54:07.389620 TX Vref=16, minBit 8, minWin=22, winSum=371
8114 06:54:07.392862 TX Vref=18, minBit 9, minWin=22, winSum=381
8115 06:54:07.395828 TX Vref=20, minBit 3, minWin=23, winSum=390
8116 06:54:07.399376 TX Vref=22, minBit 9, minWin=23, winSum=398
8117 06:54:07.403167 TX Vref=24, minBit 8, minWin=24, winSum=409
8118 06:54:07.409495 TX Vref=26, minBit 3, minWin=25, winSum=417
8119 06:54:07.412727 TX Vref=28, minBit 4, minWin=25, winSum=419
8120 06:54:07.416030 TX Vref=30, minBit 4, minWin=25, winSum=417
8121 06:54:07.419522 TX Vref=32, minBit 0, minWin=25, winSum=412
8122 06:54:07.422527 TX Vref=34, minBit 0, minWin=24, winSum=401
8123 06:54:07.425928 TX Vref=36, minBit 0, minWin=24, winSum=395
8124 06:54:07.432633 [TxChooseVref] Worse bit 4, Min win 25, Win sum 419, Final Vref 28
8125 06:54:07.432714
8126 06:54:07.436297 Final TX Range 0 Vref 28
8127 06:54:07.436402
8128 06:54:07.436493 ==
8129 06:54:07.439723 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 06:54:07.442401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 06:54:07.442484 ==
8132 06:54:07.442549
8133 06:54:07.442611
8134 06:54:07.445772 TX Vref Scan disable
8135 06:54:07.452913 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8136 06:54:07.452999 == TX Byte 0 ==
8137 06:54:07.455996 u2DelayCellOfst[0]=14 cells (4 PI)
8138 06:54:07.459383 u2DelayCellOfst[1]=21 cells (6 PI)
8139 06:54:07.462449 u2DelayCellOfst[2]=14 cells (4 PI)
8140 06:54:07.466180 u2DelayCellOfst[3]=10 cells (3 PI)
8141 06:54:07.469281 u2DelayCellOfst[4]=10 cells (3 PI)
8142 06:54:07.472326 u2DelayCellOfst[5]=0 cells (0 PI)
8143 06:54:07.476255 u2DelayCellOfst[6]=21 cells (6 PI)
8144 06:54:07.479619 u2DelayCellOfst[7]=17 cells (5 PI)
8145 06:54:07.482684 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8146 06:54:07.485704 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8147 06:54:07.489222 == TX Byte 1 ==
8148 06:54:07.492314 u2DelayCellOfst[8]=0 cells (0 PI)
8149 06:54:07.495911 u2DelayCellOfst[9]=0 cells (0 PI)
8150 06:54:07.495987 u2DelayCellOfst[10]=7 cells (2 PI)
8151 06:54:07.498995 u2DelayCellOfst[11]=0 cells (0 PI)
8152 06:54:07.502594 u2DelayCellOfst[12]=10 cells (3 PI)
8153 06:54:07.505712 u2DelayCellOfst[13]=10 cells (3 PI)
8154 06:54:07.509100 u2DelayCellOfst[14]=14 cells (4 PI)
8155 06:54:07.512577 u2DelayCellOfst[15]=10 cells (3 PI)
8156 06:54:07.515875 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8157 06:54:07.522549 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8158 06:54:07.522630 DramC Write-DBI on
8159 06:54:07.522696 ==
8160 06:54:07.526145 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 06:54:07.532323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 06:54:07.532407 ==
8163 06:54:07.532473
8164 06:54:07.532535
8165 06:54:07.532593 TX Vref Scan disable
8166 06:54:07.536743 == TX Byte 0 ==
8167 06:54:07.539664 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8168 06:54:07.543373 == TX Byte 1 ==
8169 06:54:07.546426 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8170 06:54:07.549816 DramC Write-DBI off
8171 06:54:07.549897
8172 06:54:07.549961 [DATLAT]
8173 06:54:07.550018 Freq=1600, CH0 RK1
8174 06:54:07.550075
8175 06:54:07.553300 DATLAT Default: 0xf
8176 06:54:07.553384 0, 0xFFFF, sum = 0
8177 06:54:07.556596 1, 0xFFFF, sum = 0
8178 06:54:07.556673 2, 0xFFFF, sum = 0
8179 06:54:07.559690 3, 0xFFFF, sum = 0
8180 06:54:07.559798 4, 0xFFFF, sum = 0
8181 06:54:07.562822 5, 0xFFFF, sum = 0
8182 06:54:07.566488 6, 0xFFFF, sum = 0
8183 06:54:07.566591 7, 0xFFFF, sum = 0
8184 06:54:07.569638 8, 0xFFFF, sum = 0
8185 06:54:07.569739 9, 0xFFFF, sum = 0
8186 06:54:07.573110 10, 0xFFFF, sum = 0
8187 06:54:07.573229 11, 0xFFFF, sum = 0
8188 06:54:07.576260 12, 0xFFFF, sum = 0
8189 06:54:07.576365 13, 0xFFFF, sum = 0
8190 06:54:07.579711 14, 0x0, sum = 1
8191 06:54:07.579820 15, 0x0, sum = 2
8192 06:54:07.583350 16, 0x0, sum = 3
8193 06:54:07.583463 17, 0x0, sum = 4
8194 06:54:07.586582 best_step = 15
8195 06:54:07.586656
8196 06:54:07.586717 ==
8197 06:54:07.589471 Dram Type= 6, Freq= 0, CH_0, rank 1
8198 06:54:07.593021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8199 06:54:07.593122 ==
8200 06:54:07.593215 RX Vref Scan: 0
8201 06:54:07.596186
8202 06:54:07.596261 RX Vref 0 -> 0, step: 1
8203 06:54:07.596323
8204 06:54:07.599670 RX Delay 11 -> 252, step: 4
8205 06:54:07.602646 iDelay=195, Bit 0, Center 126 (71 ~ 182) 112
8206 06:54:07.609515 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8207 06:54:07.613070 iDelay=195, Bit 2, Center 122 (67 ~ 178) 112
8208 06:54:07.616256 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8209 06:54:07.619586 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8210 06:54:07.623226 iDelay=195, Bit 5, Center 116 (63 ~ 170) 108
8211 06:54:07.626258 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8212 06:54:07.632944 iDelay=195, Bit 7, Center 136 (83 ~ 190) 108
8213 06:54:07.636331 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8214 06:54:07.639904 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8215 06:54:07.643536 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8216 06:54:07.646286 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8217 06:54:07.652924 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8218 06:54:07.656680 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
8219 06:54:07.659527 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8220 06:54:07.663274 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8221 06:54:07.665997 ==
8222 06:54:07.666070 Dram Type= 6, Freq= 0, CH_0, rank 1
8223 06:54:07.672935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 06:54:07.673041 ==
8225 06:54:07.673141 DQS Delay:
8226 06:54:07.675957 DQS0 = 0, DQS1 = 0
8227 06:54:07.676026 DQM Delay:
8228 06:54:07.679712 DQM0 = 127, DQM1 = 122
8229 06:54:07.679784 DQ Delay:
8230 06:54:07.682705 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8231 06:54:07.686335 DQ4 =128, DQ5 =116, DQ6 =138, DQ7 =136
8232 06:54:07.689349 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8233 06:54:07.692674 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
8234 06:54:07.692752
8235 06:54:07.692847
8236 06:54:07.692940
8237 06:54:07.696287 [DramC_TX_OE_Calibration] TA2
8238 06:54:07.699561 Original DQ_B0 (3 6) =30, OEN = 27
8239 06:54:07.702713 Original DQ_B1 (3 6) =30, OEN = 27
8240 06:54:07.706240 24, 0x0, End_B0=24 End_B1=24
8241 06:54:07.709363 25, 0x0, End_B0=25 End_B1=25
8242 06:54:07.709447 26, 0x0, End_B0=26 End_B1=26
8243 06:54:07.713316 27, 0x0, End_B0=27 End_B1=27
8244 06:54:07.716289 28, 0x0, End_B0=28 End_B1=28
8245 06:54:07.720017 29, 0x0, End_B0=29 End_B1=29
8246 06:54:07.720099 30, 0x0, End_B0=30 End_B1=30
8247 06:54:07.723025 31, 0x4141, End_B0=30 End_B1=30
8248 06:54:07.726174 Byte0 end_step=30 best_step=27
8249 06:54:07.729388 Byte1 end_step=30 best_step=27
8250 06:54:07.732803 Byte0 TX OE(2T, 0.5T) = (3, 3)
8251 06:54:07.735845 Byte1 TX OE(2T, 0.5T) = (3, 3)
8252 06:54:07.735922
8253 06:54:07.735985
8254 06:54:07.742850 [DQSOSCAuto] RK1, (LSB)MR18= 0x1309, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 400 ps
8255 06:54:07.746462 CH0 RK1: MR19=303, MR18=1309
8256 06:54:07.752493 CH0_RK1: MR19=0x303, MR18=0x1309, DQSOSC=400, MR23=63, INC=23, DEC=15
8257 06:54:07.756111 [RxdqsGatingPostProcess] freq 1600
8258 06:54:07.759539 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8259 06:54:07.763228 best DQS0 dly(2T, 0.5T) = (1, 1)
8260 06:54:07.766292 best DQS1 dly(2T, 0.5T) = (1, 1)
8261 06:54:07.769545 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8262 06:54:07.773025 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8263 06:54:07.775990 best DQS0 dly(2T, 0.5T) = (1, 1)
8264 06:54:07.779547 best DQS1 dly(2T, 0.5T) = (1, 1)
8265 06:54:07.782846 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8266 06:54:07.786164 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8267 06:54:07.789675 Pre-setting of DQS Precalculation
8268 06:54:07.792532 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8269 06:54:07.792611 ==
8270 06:54:07.796282 Dram Type= 6, Freq= 0, CH_1, rank 0
8271 06:54:07.799178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8272 06:54:07.802680 ==
8273 06:54:07.806017 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8274 06:54:07.809065 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8275 06:54:07.816291 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8276 06:54:07.819379 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8277 06:54:07.829519 [CA 0] Center 43 (15~72) winsize 58
8278 06:54:07.832961 [CA 1] Center 43 (14~72) winsize 59
8279 06:54:07.835970 [CA 2] Center 38 (10~67) winsize 58
8280 06:54:07.839487 [CA 3] Center 36 (7~66) winsize 60
8281 06:54:07.842990 [CA 4] Center 38 (8~68) winsize 61
8282 06:54:07.846052 [CA 5] Center 36 (7~66) winsize 60
8283 06:54:07.846128
8284 06:54:07.849446 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8285 06:54:07.849519
8286 06:54:07.852848 [CATrainingPosCal] consider 1 rank data
8287 06:54:07.856342 u2DelayCellTimex100 = 275/100 ps
8288 06:54:07.859657 CA0 delay=43 (15~72),Diff = 7 PI (24 cell)
8289 06:54:07.865916 CA1 delay=43 (14~72),Diff = 7 PI (24 cell)
8290 06:54:07.869801 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
8291 06:54:07.873237 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8292 06:54:07.876280 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8293 06:54:07.879464 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8294 06:54:07.879539
8295 06:54:07.883186 CA PerBit enable=1, Macro0, CA PI delay=36
8296 06:54:07.883293
8297 06:54:07.886468 [CBTSetCACLKResult] CA Dly = 36
8298 06:54:07.886550 CS Dly: 9 (0~40)
8299 06:54:07.892928 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8300 06:54:07.896234 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8301 06:54:07.896336 ==
8302 06:54:07.899924 Dram Type= 6, Freq= 0, CH_1, rank 1
8303 06:54:07.903101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 06:54:07.903206 ==
8305 06:54:07.909978 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8306 06:54:07.912806 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8307 06:54:07.919961 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8308 06:54:07.922828 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8309 06:54:07.932528 [CA 0] Center 43 (14~72) winsize 59
8310 06:54:07.935987 [CA 1] Center 43 (15~72) winsize 58
8311 06:54:07.939315 [CA 2] Center 38 (9~67) winsize 59
8312 06:54:07.942534 [CA 3] Center 37 (8~66) winsize 59
8313 06:54:07.945871 [CA 4] Center 38 (9~68) winsize 60
8314 06:54:07.949317 [CA 5] Center 36 (7~66) winsize 60
8315 06:54:07.949399
8316 06:54:07.952969 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8317 06:54:07.953041
8318 06:54:07.956220 [CATrainingPosCal] consider 2 rank data
8319 06:54:07.959198 u2DelayCellTimex100 = 275/100 ps
8320 06:54:07.962558 CA0 delay=43 (15~72),Diff = 7 PI (24 cell)
8321 06:54:07.969696 CA1 delay=43 (15~72),Diff = 7 PI (24 cell)
8322 06:54:07.972802 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
8323 06:54:07.975854 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8324 06:54:07.979673 CA4 delay=38 (9~68),Diff = 2 PI (7 cell)
8325 06:54:07.982907 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8326 06:54:07.983002
8327 06:54:07.986344 CA PerBit enable=1, Macro0, CA PI delay=36
8328 06:54:07.986413
8329 06:54:07.989321 [CBTSetCACLKResult] CA Dly = 36
8330 06:54:07.992838 CS Dly: 11 (0~45)
8331 06:54:07.996024 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8332 06:54:07.999792 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8333 06:54:07.999899
8334 06:54:08.002782 ----->DramcWriteLeveling(PI) begin...
8335 06:54:08.002866 ==
8336 06:54:08.006256 Dram Type= 6, Freq= 0, CH_1, rank 0
8337 06:54:08.009822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 06:54:08.009905 ==
8339 06:54:08.013147 Write leveling (Byte 0): 24 => 24
8340 06:54:08.016045 Write leveling (Byte 1): 28 => 28
8341 06:54:08.019692 DramcWriteLeveling(PI) end<-----
8342 06:54:08.019767
8343 06:54:08.019829 ==
8344 06:54:08.022917 Dram Type= 6, Freq= 0, CH_1, rank 0
8345 06:54:08.026725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8346 06:54:08.029589 ==
8347 06:54:08.029660 [Gating] SW mode calibration
8348 06:54:08.039648 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8349 06:54:08.043019 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8350 06:54:08.046251 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 06:54:08.053030 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 06:54:08.056430 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 06:54:08.059703 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 06:54:08.066358 1 4 16 | B1->B0 | 2727 2323 | 1 0 | (0 0) (0 0)
8355 06:54:08.069546 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8356 06:54:08.073107 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8357 06:54:08.079609 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8358 06:54:08.083362 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8359 06:54:08.086496 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 06:54:08.093043 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 06:54:08.096541 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8362 06:54:08.099678 1 5 16 | B1->B0 | 2c2c 3333 | 1 0 | (1 0) (0 1)
8363 06:54:08.106336 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8364 06:54:08.109522 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 06:54:08.112965 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 06:54:08.116439 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 06:54:08.123218 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 06:54:08.126337 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 06:54:08.129746 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 06:54:08.136259 1 6 16 | B1->B0 | 3a3a 3737 | 0 0 | (0 0) (1 1)
8371 06:54:08.139929 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 06:54:08.142796 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 06:54:08.149982 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 06:54:08.153019 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 06:54:08.156741 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 06:54:08.163351 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 06:54:08.166454 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8378 06:54:08.169744 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8379 06:54:08.176121 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8380 06:54:08.179876 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 06:54:08.182881 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 06:54:08.189783 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 06:54:08.192973 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 06:54:08.196537 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 06:54:08.203156 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 06:54:08.206585 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 06:54:08.209761 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 06:54:08.213120 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 06:54:08.219764 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 06:54:08.223261 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 06:54:08.226631 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 06:54:08.233381 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 06:54:08.236877 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8394 06:54:08.239573 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8395 06:54:08.246227 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 06:54:08.246339 Total UI for P1: 0, mck2ui 16
8397 06:54:08.252970 best dqsien dly found for B0: ( 1, 9, 14)
8398 06:54:08.253081 Total UI for P1: 0, mck2ui 16
8399 06:54:08.259831 best dqsien dly found for B1: ( 1, 9, 14)
8400 06:54:08.263290 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8401 06:54:08.266409 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8402 06:54:08.266515
8403 06:54:08.269966 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8404 06:54:08.272916 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8405 06:54:08.276662 [Gating] SW calibration Done
8406 06:54:08.276765 ==
8407 06:54:08.279625 Dram Type= 6, Freq= 0, CH_1, rank 0
8408 06:54:08.283023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8409 06:54:08.283125 ==
8410 06:54:08.286620 RX Vref Scan: 0
8411 06:54:08.286724
8412 06:54:08.286816 RX Vref 0 -> 0, step: 1
8413 06:54:08.286915
8414 06:54:08.289315 RX Delay 0 -> 252, step: 8
8415 06:54:08.292991 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8416 06:54:08.299549 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8417 06:54:08.302873 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8418 06:54:08.306426 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8419 06:54:08.310030 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8420 06:54:08.312868 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8421 06:54:08.316649 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8422 06:54:08.323050 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8423 06:54:08.326540 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8424 06:54:08.329941 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8425 06:54:08.333502 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8426 06:54:08.337039 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8427 06:54:08.343521 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8428 06:54:08.346440 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8429 06:54:08.349762 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8430 06:54:08.353007 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8431 06:54:08.353108 ==
8432 06:54:08.356414 Dram Type= 6, Freq= 0, CH_1, rank 0
8433 06:54:08.363097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8434 06:54:08.363201 ==
8435 06:54:08.363294 DQS Delay:
8436 06:54:08.366464 DQS0 = 0, DQS1 = 0
8437 06:54:08.366564 DQM Delay:
8438 06:54:08.369922 DQM0 = 134, DQM1 = 127
8439 06:54:08.370028 DQ Delay:
8440 06:54:08.372973 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8441 06:54:08.376763 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8442 06:54:08.379565 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8443 06:54:08.383230 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8444 06:54:08.383341
8445 06:54:08.383431
8446 06:54:08.383521 ==
8447 06:54:08.386757 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 06:54:08.389815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 06:54:08.393443 ==
8450 06:54:08.393528
8451 06:54:08.393592
8452 06:54:08.393652 TX Vref Scan disable
8453 06:54:08.396477 == TX Byte 0 ==
8454 06:54:08.399552 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8455 06:54:08.402918 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8456 06:54:08.406273 == TX Byte 1 ==
8457 06:54:08.409878 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8458 06:54:08.413101 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8459 06:54:08.413203 ==
8460 06:54:08.416837 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 06:54:08.423147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 06:54:08.423230 ==
8463 06:54:08.435205
8464 06:54:08.438241 TX Vref early break, caculate TX vref
8465 06:54:08.441883 TX Vref=16, minBit 5, minWin=21, winSum=364
8466 06:54:08.445313 TX Vref=18, minBit 8, minWin=21, winSum=372
8467 06:54:08.448267 TX Vref=20, minBit 8, minWin=21, winSum=384
8468 06:54:08.452004 TX Vref=22, minBit 8, minWin=23, winSum=400
8469 06:54:08.455421 TX Vref=24, minBit 8, minWin=23, winSum=401
8470 06:54:08.461811 TX Vref=26, minBit 10, minWin=24, winSum=414
8471 06:54:08.465101 TX Vref=28, minBit 9, minWin=25, winSum=419
8472 06:54:08.468632 TX Vref=30, minBit 11, minWin=24, winSum=416
8473 06:54:08.472317 TX Vref=32, minBit 11, minWin=24, winSum=412
8474 06:54:08.475050 TX Vref=34, minBit 11, minWin=23, winSum=397
8475 06:54:08.481807 [TxChooseVref] Worse bit 9, Min win 25, Win sum 419, Final Vref 28
8476 06:54:08.481890
8477 06:54:08.485406 Final TX Range 0 Vref 28
8478 06:54:08.485497
8479 06:54:08.485567 ==
8480 06:54:08.489075 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 06:54:08.491938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 06:54:08.492047 ==
8483 06:54:08.492141
8484 06:54:08.492228
8485 06:54:08.495054 TX Vref Scan disable
8486 06:54:08.501842 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8487 06:54:08.501923 == TX Byte 0 ==
8488 06:54:08.505558 u2DelayCellOfst[0]=17 cells (5 PI)
8489 06:54:08.508704 u2DelayCellOfst[1]=14 cells (4 PI)
8490 06:54:08.511716 u2DelayCellOfst[2]=0 cells (0 PI)
8491 06:54:08.515340 u2DelayCellOfst[3]=7 cells (2 PI)
8492 06:54:08.518714 u2DelayCellOfst[4]=7 cells (2 PI)
8493 06:54:08.521986 u2DelayCellOfst[5]=17 cells (5 PI)
8494 06:54:08.524989 u2DelayCellOfst[6]=17 cells (5 PI)
8495 06:54:08.525095 u2DelayCellOfst[7]=7 cells (2 PI)
8496 06:54:08.531759 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8497 06:54:08.535344 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8498 06:54:08.535429 == TX Byte 1 ==
8499 06:54:08.538617 u2DelayCellOfst[8]=0 cells (0 PI)
8500 06:54:08.541904 u2DelayCellOfst[9]=7 cells (2 PI)
8501 06:54:08.545349 u2DelayCellOfst[10]=10 cells (3 PI)
8502 06:54:08.548338 u2DelayCellOfst[11]=7 cells (2 PI)
8503 06:54:08.551682 u2DelayCellOfst[12]=14 cells (4 PI)
8504 06:54:08.555377 u2DelayCellOfst[13]=17 cells (5 PI)
8505 06:54:08.558285 u2DelayCellOfst[14]=17 cells (5 PI)
8506 06:54:08.561840 u2DelayCellOfst[15]=17 cells (5 PI)
8507 06:54:08.565309 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8508 06:54:08.571958 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8509 06:54:08.572042 DramC Write-DBI on
8510 06:54:08.572107 ==
8511 06:54:08.574984 Dram Type= 6, Freq= 0, CH_1, rank 0
8512 06:54:08.578448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8513 06:54:08.578531 ==
8514 06:54:08.578595
8515 06:54:08.581764
8516 06:54:08.581846 TX Vref Scan disable
8517 06:54:08.585183 == TX Byte 0 ==
8518 06:54:08.588459 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8519 06:54:08.591845 == TX Byte 1 ==
8520 06:54:08.595364 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8521 06:54:08.595473 DramC Write-DBI off
8522 06:54:08.595567
8523 06:54:08.598626 [DATLAT]
8524 06:54:08.598708 Freq=1600, CH1 RK0
8525 06:54:08.598772
8526 06:54:08.602283 DATLAT Default: 0xf
8527 06:54:08.602365 0, 0xFFFF, sum = 0
8528 06:54:08.605062 1, 0xFFFF, sum = 0
8529 06:54:08.605172 2, 0xFFFF, sum = 0
8530 06:54:08.608849 3, 0xFFFF, sum = 0
8531 06:54:08.608932 4, 0xFFFF, sum = 0
8532 06:54:08.611649 5, 0xFFFF, sum = 0
8533 06:54:08.611732 6, 0xFFFF, sum = 0
8534 06:54:08.615201 7, 0xFFFF, sum = 0
8535 06:54:08.615309 8, 0xFFFF, sum = 0
8536 06:54:08.618262 9, 0xFFFF, sum = 0
8537 06:54:08.622030 10, 0xFFFF, sum = 0
8538 06:54:08.622113 11, 0xFFFF, sum = 0
8539 06:54:08.625236 12, 0xFFFF, sum = 0
8540 06:54:08.625318 13, 0xFFFF, sum = 0
8541 06:54:08.628552 14, 0x0, sum = 1
8542 06:54:08.628634 15, 0x0, sum = 2
8543 06:54:08.631795 16, 0x0, sum = 3
8544 06:54:08.631878 17, 0x0, sum = 4
8545 06:54:08.631942 best_step = 15
8546 06:54:08.634938
8547 06:54:08.635019 ==
8548 06:54:08.638325 Dram Type= 6, Freq= 0, CH_1, rank 0
8549 06:54:08.641718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8550 06:54:08.641801 ==
8551 06:54:08.641864 RX Vref Scan: 1
8552 06:54:08.641924
8553 06:54:08.644783 Set Vref Range= 24 -> 127
8554 06:54:08.644865
8555 06:54:08.648367 RX Vref 24 -> 127, step: 1
8556 06:54:08.648474
8557 06:54:08.651755 RX Delay 11 -> 252, step: 4
8558 06:54:08.651837
8559 06:54:08.655148 Set Vref, RX VrefLevel [Byte0]: 24
8560 06:54:08.658350 [Byte1]: 24
8561 06:54:08.658432
8562 06:54:08.661663 Set Vref, RX VrefLevel [Byte0]: 25
8563 06:54:08.664752 [Byte1]: 25
8564 06:54:08.664834
8565 06:54:08.668108 Set Vref, RX VrefLevel [Byte0]: 26
8566 06:54:08.671550 [Byte1]: 26
8567 06:54:08.675086
8568 06:54:08.675169 Set Vref, RX VrefLevel [Byte0]: 27
8569 06:54:08.678295 [Byte1]: 27
8570 06:54:08.682676
8571 06:54:08.682758 Set Vref, RX VrefLevel [Byte0]: 28
8572 06:54:08.686106 [Byte1]: 28
8573 06:54:08.690315
8574 06:54:08.690396 Set Vref, RX VrefLevel [Byte0]: 29
8575 06:54:08.693884 [Byte1]: 29
8576 06:54:08.698207
8577 06:54:08.698290 Set Vref, RX VrefLevel [Byte0]: 30
8578 06:54:08.701164 [Byte1]: 30
8579 06:54:08.705380
8580 06:54:08.705483 Set Vref, RX VrefLevel [Byte0]: 31
8581 06:54:08.708699 [Byte1]: 31
8582 06:54:08.713418
8583 06:54:08.713518 Set Vref, RX VrefLevel [Byte0]: 32
8584 06:54:08.716565 [Byte1]: 32
8585 06:54:08.720780
8586 06:54:08.720878 Set Vref, RX VrefLevel [Byte0]: 33
8587 06:54:08.724371 [Byte1]: 33
8588 06:54:08.728611
8589 06:54:08.728709 Set Vref, RX VrefLevel [Byte0]: 34
8590 06:54:08.731604 [Byte1]: 34
8591 06:54:08.736023
8592 06:54:08.736123 Set Vref, RX VrefLevel [Byte0]: 35
8593 06:54:08.739020 [Byte1]: 35
8594 06:54:08.743857
8595 06:54:08.743925 Set Vref, RX VrefLevel [Byte0]: 36
8596 06:54:08.747226 [Byte1]: 36
8597 06:54:08.751226
8598 06:54:08.751301 Set Vref, RX VrefLevel [Byte0]: 37
8599 06:54:08.754311 [Byte1]: 37
8600 06:54:08.759071
8601 06:54:08.759170 Set Vref, RX VrefLevel [Byte0]: 38
8602 06:54:08.761922 [Byte1]: 38
8603 06:54:08.766699
8604 06:54:08.766786 Set Vref, RX VrefLevel [Byte0]: 39
8605 06:54:08.769551 [Byte1]: 39
8606 06:54:08.774327
8607 06:54:08.774428 Set Vref, RX VrefLevel [Byte0]: 40
8608 06:54:08.777671 [Byte1]: 40
8609 06:54:08.781714
8610 06:54:08.781786 Set Vref, RX VrefLevel [Byte0]: 41
8611 06:54:08.784982 [Byte1]: 41
8612 06:54:08.789402
8613 06:54:08.789470 Set Vref, RX VrefLevel [Byte0]: 42
8614 06:54:08.792608 [Byte1]: 42
8615 06:54:08.796738
8616 06:54:08.796815 Set Vref, RX VrefLevel [Byte0]: 43
8617 06:54:08.800028 [Byte1]: 43
8618 06:54:08.804953
8619 06:54:08.805061 Set Vref, RX VrefLevel [Byte0]: 44
8620 06:54:08.807919 [Byte1]: 44
8621 06:54:08.812405
8622 06:54:08.812531 Set Vref, RX VrefLevel [Byte0]: 45
8623 06:54:08.815448 [Byte1]: 45
8624 06:54:08.819504
8625 06:54:08.819631 Set Vref, RX VrefLevel [Byte0]: 46
8626 06:54:08.823134 [Byte1]: 46
8627 06:54:08.827500
8628 06:54:08.827597 Set Vref, RX VrefLevel [Byte0]: 47
8629 06:54:08.830712 [Byte1]: 47
8630 06:54:08.834715
8631 06:54:08.834789 Set Vref, RX VrefLevel [Byte0]: 48
8632 06:54:08.838274 [Byte1]: 48
8633 06:54:08.842882
8634 06:54:08.842960 Set Vref, RX VrefLevel [Byte0]: 49
8635 06:54:08.845933 [Byte1]: 49
8636 06:54:08.850605
8637 06:54:08.850684 Set Vref, RX VrefLevel [Byte0]: 50
8638 06:54:08.853902 [Byte1]: 50
8639 06:54:08.858317
8640 06:54:08.858396 Set Vref, RX VrefLevel [Byte0]: 51
8641 06:54:08.861010 [Byte1]: 51
8642 06:54:08.865588
8643 06:54:08.865669 Set Vref, RX VrefLevel [Byte0]: 52
8644 06:54:08.868724 [Byte1]: 52
8645 06:54:08.873590
8646 06:54:08.873670 Set Vref, RX VrefLevel [Byte0]: 53
8647 06:54:08.876329 [Byte1]: 53
8648 06:54:08.880620
8649 06:54:08.880700 Set Vref, RX VrefLevel [Byte0]: 54
8650 06:54:08.884342 [Byte1]: 54
8651 06:54:08.888113
8652 06:54:08.888250 Set Vref, RX VrefLevel [Byte0]: 55
8653 06:54:08.891986 [Byte1]: 55
8654 06:54:08.895956
8655 06:54:08.896036 Set Vref, RX VrefLevel [Byte0]: 56
8656 06:54:08.899286 [Byte1]: 56
8657 06:54:08.903715
8658 06:54:08.903795 Set Vref, RX VrefLevel [Byte0]: 57
8659 06:54:08.906815 [Byte1]: 57
8660 06:54:08.911485
8661 06:54:08.911565 Set Vref, RX VrefLevel [Byte0]: 58
8662 06:54:08.914343 [Byte1]: 58
8663 06:54:08.919450
8664 06:54:08.919529 Set Vref, RX VrefLevel [Byte0]: 59
8665 06:54:08.921883 [Byte1]: 59
8666 06:54:08.926634
8667 06:54:08.926715 Set Vref, RX VrefLevel [Byte0]: 60
8668 06:54:08.929382 [Byte1]: 60
8669 06:54:08.934111
8670 06:54:08.934190 Set Vref, RX VrefLevel [Byte0]: 61
8671 06:54:08.937164 [Byte1]: 61
8672 06:54:08.941526
8673 06:54:08.941606 Set Vref, RX VrefLevel [Byte0]: 62
8674 06:54:08.944963 [Byte1]: 62
8675 06:54:08.949278
8676 06:54:08.949374 Set Vref, RX VrefLevel [Byte0]: 63
8677 06:54:08.952768 [Byte1]: 63
8678 06:54:08.957096
8679 06:54:08.957226 Set Vref, RX VrefLevel [Byte0]: 64
8680 06:54:08.959916 [Byte1]: 64
8681 06:54:08.964585
8682 06:54:08.964664 Set Vref, RX VrefLevel [Byte0]: 65
8683 06:54:08.967974 [Byte1]: 65
8684 06:54:08.972310
8685 06:54:08.972392 Set Vref, RX VrefLevel [Byte0]: 66
8686 06:54:08.975256 [Byte1]: 66
8687 06:54:08.979917
8688 06:54:08.979996 Set Vref, RX VrefLevel [Byte0]: 67
8689 06:54:08.982891 [Byte1]: 67
8690 06:54:08.987255
8691 06:54:08.987335 Set Vref, RX VrefLevel [Byte0]: 68
8692 06:54:08.990275 [Byte1]: 68
8693 06:54:08.994798
8694 06:54:08.994880 Set Vref, RX VrefLevel [Byte0]: 69
8695 06:54:08.998240 [Byte1]: 69
8696 06:54:09.002521
8697 06:54:09.002601 Set Vref, RX VrefLevel [Byte0]: 70
8698 06:54:09.005576 [Byte1]: 70
8699 06:54:09.010098
8700 06:54:09.010225 Set Vref, RX VrefLevel [Byte0]: 71
8701 06:54:09.013242 [Byte1]: 71
8702 06:54:09.017953
8703 06:54:09.018035 Set Vref, RX VrefLevel [Byte0]: 72
8704 06:54:09.021408 [Byte1]: 72
8705 06:54:09.025353
8706 06:54:09.025432 Set Vref, RX VrefLevel [Byte0]: 73
8707 06:54:09.028753 [Byte1]: 73
8708 06:54:09.032870
8709 06:54:09.032950 Final RX Vref Byte 0 = 59 to rank0
8710 06:54:09.036030 Final RX Vref Byte 1 = 56 to rank0
8711 06:54:09.039465 Final RX Vref Byte 0 = 59 to rank1
8712 06:54:09.043075 Final RX Vref Byte 1 = 56 to rank1==
8713 06:54:09.046192 Dram Type= 6, Freq= 0, CH_1, rank 0
8714 06:54:09.052774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8715 06:54:09.052857 ==
8716 06:54:09.052921 DQS Delay:
8717 06:54:09.052981 DQS0 = 0, DQS1 = 0
8718 06:54:09.056124 DQM Delay:
8719 06:54:09.056205 DQM0 = 131, DQM1 = 124
8720 06:54:09.059598 DQ Delay:
8721 06:54:09.062605 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =128
8722 06:54:09.065948 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8723 06:54:09.069565 DQ8 =110, DQ9 =114, DQ10 =128, DQ11 =118
8724 06:54:09.072837 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8725 06:54:09.072919
8726 06:54:09.072982
8727 06:54:09.073042
8728 06:54:09.076065 [DramC_TX_OE_Calibration] TA2
8729 06:54:09.079525 Original DQ_B0 (3 6) =30, OEN = 27
8730 06:54:09.082598 Original DQ_B1 (3 6) =30, OEN = 27
8731 06:54:09.086191 24, 0x0, End_B0=24 End_B1=24
8732 06:54:09.086274 25, 0x0, End_B0=25 End_B1=25
8733 06:54:09.089804 26, 0x0, End_B0=26 End_B1=26
8734 06:54:09.092984 27, 0x0, End_B0=27 End_B1=27
8735 06:54:09.096384 28, 0x0, End_B0=28 End_B1=28
8736 06:54:09.096467 29, 0x0, End_B0=29 End_B1=29
8737 06:54:09.099538 30, 0x0, End_B0=30 End_B1=30
8738 06:54:09.102468 31, 0x5151, End_B0=30 End_B1=30
8739 06:54:09.106264 Byte0 end_step=30 best_step=27
8740 06:54:09.109309 Byte1 end_step=30 best_step=27
8741 06:54:09.112506 Byte0 TX OE(2T, 0.5T) = (3, 3)
8742 06:54:09.112617 Byte1 TX OE(2T, 0.5T) = (3, 3)
8743 06:54:09.115984
8744 06:54:09.116062
8745 06:54:09.123189 [DQSOSCAuto] RK0, (LSB)MR18= 0x1600, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 398 ps
8746 06:54:09.125987 CH1 RK0: MR19=303, MR18=1600
8747 06:54:09.132572 CH1_RK0: MR19=0x303, MR18=0x1600, DQSOSC=398, MR23=63, INC=23, DEC=15
8748 06:54:09.132657
8749 06:54:09.136145 ----->DramcWriteLeveling(PI) begin...
8750 06:54:09.136250 ==
8751 06:54:09.139464 Dram Type= 6, Freq= 0, CH_1, rank 1
8752 06:54:09.142797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8753 06:54:09.142895 ==
8754 06:54:09.145821 Write leveling (Byte 0): 25 => 25
8755 06:54:09.149328 Write leveling (Byte 1): 27 => 27
8756 06:54:09.152789 DramcWriteLeveling(PI) end<-----
8757 06:54:09.152872
8758 06:54:09.152936 ==
8759 06:54:09.155814 Dram Type= 6, Freq= 0, CH_1, rank 1
8760 06:54:09.159370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8761 06:54:09.159451 ==
8762 06:54:09.162823 [Gating] SW mode calibration
8763 06:54:09.169176 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8764 06:54:09.175845 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8765 06:54:09.179206 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 06:54:09.182689 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 06:54:09.189181 1 4 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
8768 06:54:09.192848 1 4 12 | B1->B0 | 2d2d 3434 | 0 1 | (1 1) (1 1)
8769 06:54:09.195806 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 06:54:09.202568 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 06:54:09.205733 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 06:54:09.209225 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 06:54:09.215976 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 06:54:09.219252 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8775 06:54:09.222739 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
8776 06:54:09.229382 1 5 12 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (0 0)
8777 06:54:09.233114 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8778 06:54:09.235614 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 06:54:09.242450 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 06:54:09.245950 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 06:54:09.249164 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 06:54:09.252791 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 06:54:09.259525 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8784 06:54:09.262249 1 6 12 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8785 06:54:09.265535 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 06:54:09.272211 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 06:54:09.275713 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 06:54:09.279248 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 06:54:09.285679 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 06:54:09.289152 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8791 06:54:09.292536 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8792 06:54:09.299329 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8793 06:54:09.302400 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8794 06:54:09.305861 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 06:54:09.312707 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 06:54:09.315850 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 06:54:09.319536 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 06:54:09.326198 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 06:54:09.329249 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 06:54:09.332290 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 06:54:09.339027 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 06:54:09.342456 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 06:54:09.345473 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 06:54:09.352529 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 06:54:09.355646 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 06:54:09.358692 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8807 06:54:09.365496 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8808 06:54:09.368784 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8809 06:54:09.372243 Total UI for P1: 0, mck2ui 16
8810 06:54:09.375839 best dqsien dly found for B0: ( 1, 9, 6)
8811 06:54:09.379177 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 06:54:09.382531 Total UI for P1: 0, mck2ui 16
8813 06:54:09.385973 best dqsien dly found for B1: ( 1, 9, 10)
8814 06:54:09.388808 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8815 06:54:09.392504 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8816 06:54:09.392613
8817 06:54:09.395670 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8818 06:54:09.399074 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8819 06:54:09.402216 [Gating] SW calibration Done
8820 06:54:09.402343 ==
8821 06:54:09.405488 Dram Type= 6, Freq= 0, CH_1, rank 1
8822 06:54:09.408917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8823 06:54:09.412554 ==
8824 06:54:09.412635 RX Vref Scan: 0
8825 06:54:09.412698
8826 06:54:09.415991 RX Vref 0 -> 0, step: 1
8827 06:54:09.416074
8828 06:54:09.416154 RX Delay 0 -> 252, step: 8
8829 06:54:09.422727 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8830 06:54:09.425931 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8831 06:54:09.429457 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8832 06:54:09.432551 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8833 06:54:09.436116 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8834 06:54:09.442424 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8835 06:54:09.445918 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8836 06:54:09.449012 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8837 06:54:09.452635 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8838 06:54:09.456067 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8839 06:54:09.463110 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8840 06:54:09.465774 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8841 06:54:09.469193 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8842 06:54:09.472868 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8843 06:54:09.475890 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8844 06:54:09.482597 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8845 06:54:09.482677 ==
8846 06:54:09.486060 Dram Type= 6, Freq= 0, CH_1, rank 1
8847 06:54:09.489442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8848 06:54:09.489515 ==
8849 06:54:09.489575 DQS Delay:
8850 06:54:09.492884 DQS0 = 0, DQS1 = 0
8851 06:54:09.492972 DQM Delay:
8852 06:54:09.496131 DQM0 = 132, DQM1 = 127
8853 06:54:09.496232 DQ Delay:
8854 06:54:09.499686 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8855 06:54:09.502761 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8856 06:54:09.506165 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8857 06:54:09.509447 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8858 06:54:09.509527
8859 06:54:09.509590
8860 06:54:09.512957 ==
8861 06:54:09.515962 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 06:54:09.519608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 06:54:09.519704 ==
8864 06:54:09.519768
8865 06:54:09.519827
8866 06:54:09.522651 TX Vref Scan disable
8867 06:54:09.522745 == TX Byte 0 ==
8868 06:54:09.525741 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8869 06:54:09.532438 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8870 06:54:09.532556 == TX Byte 1 ==
8871 06:54:09.536150 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8872 06:54:09.542420 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8873 06:54:09.542515 ==
8874 06:54:09.546089 Dram Type= 6, Freq= 0, CH_1, rank 1
8875 06:54:09.549042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8876 06:54:09.549157 ==
8877 06:54:09.564416
8878 06:54:09.568181 TX Vref early break, caculate TX vref
8879 06:54:09.571448 TX Vref=16, minBit 8, minWin=22, winSum=380
8880 06:54:09.574492 TX Vref=18, minBit 8, minWin=23, winSum=387
8881 06:54:09.577894 TX Vref=20, minBit 5, minWin=24, winSum=396
8882 06:54:09.581145 TX Vref=22, minBit 8, minWin=24, winSum=404
8883 06:54:09.584283 TX Vref=24, minBit 9, minWin=24, winSum=409
8884 06:54:09.590755 TX Vref=26, minBit 15, minWin=24, winSum=418
8885 06:54:09.593866 TX Vref=28, minBit 0, minWin=25, winSum=421
8886 06:54:09.597535 TX Vref=30, minBit 0, minWin=25, winSum=422
8887 06:54:09.600931 TX Vref=32, minBit 0, minWin=25, winSum=414
8888 06:54:09.603952 TX Vref=34, minBit 5, minWin=24, winSum=406
8889 06:54:09.607785 TX Vref=36, minBit 0, minWin=24, winSum=401
8890 06:54:09.613789 TX Vref=38, minBit 8, minWin=22, winSum=391
8891 06:54:09.617585 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 30
8892 06:54:09.617670
8893 06:54:09.620649 Final TX Range 0 Vref 30
8894 06:54:09.620732
8895 06:54:09.620796 ==
8896 06:54:09.624111 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 06:54:09.627223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 06:54:09.630646 ==
8899 06:54:09.630755
8900 06:54:09.630851
8901 06:54:09.630951 TX Vref Scan disable
8902 06:54:09.637675 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8903 06:54:09.637756 == TX Byte 0 ==
8904 06:54:09.641217 u2DelayCellOfst[0]=14 cells (4 PI)
8905 06:54:09.644333 u2DelayCellOfst[1]=10 cells (3 PI)
8906 06:54:09.647392 u2DelayCellOfst[2]=0 cells (0 PI)
8907 06:54:09.651028 u2DelayCellOfst[3]=7 cells (2 PI)
8908 06:54:09.654188 u2DelayCellOfst[4]=7 cells (2 PI)
8909 06:54:09.657815 u2DelayCellOfst[5]=17 cells (5 PI)
8910 06:54:09.660830 u2DelayCellOfst[6]=17 cells (5 PI)
8911 06:54:09.664589 u2DelayCellOfst[7]=7 cells (2 PI)
8912 06:54:09.667595 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8913 06:54:09.670681 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8914 06:54:09.674645 == TX Byte 1 ==
8915 06:54:09.677644 u2DelayCellOfst[8]=0 cells (0 PI)
8916 06:54:09.681162 u2DelayCellOfst[9]=3 cells (1 PI)
8917 06:54:09.681283 u2DelayCellOfst[10]=10 cells (3 PI)
8918 06:54:09.684367 u2DelayCellOfst[11]=7 cells (2 PI)
8919 06:54:09.687993 u2DelayCellOfst[12]=14 cells (4 PI)
8920 06:54:09.691039 u2DelayCellOfst[13]=14 cells (4 PI)
8921 06:54:09.694528 u2DelayCellOfst[14]=17 cells (5 PI)
8922 06:54:09.697882 u2DelayCellOfst[15]=17 cells (5 PI)
8923 06:54:09.704000 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8924 06:54:09.707666 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8925 06:54:09.707779 DramC Write-DBI on
8926 06:54:09.707883 ==
8927 06:54:09.711227 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 06:54:09.717751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 06:54:09.717867 ==
8930 06:54:09.717976
8931 06:54:09.718065
8932 06:54:09.718153 TX Vref Scan disable
8933 06:54:09.721613 == TX Byte 0 ==
8934 06:54:09.724837 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8935 06:54:09.728163 == TX Byte 1 ==
8936 06:54:09.731353 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8937 06:54:09.734521 DramC Write-DBI off
8938 06:54:09.734626
8939 06:54:09.734717 [DATLAT]
8940 06:54:09.734815 Freq=1600, CH1 RK1
8941 06:54:09.734905
8942 06:54:09.737990 DATLAT Default: 0xf
8943 06:54:09.738087 0, 0xFFFF, sum = 0
8944 06:54:09.741121 1, 0xFFFF, sum = 0
8945 06:54:09.744657 2, 0xFFFF, sum = 0
8946 06:54:09.744765 3, 0xFFFF, sum = 0
8947 06:54:09.747865 4, 0xFFFF, sum = 0
8948 06:54:09.747971 5, 0xFFFF, sum = 0
8949 06:54:09.751397 6, 0xFFFF, sum = 0
8950 06:54:09.751496 7, 0xFFFF, sum = 0
8951 06:54:09.754692 8, 0xFFFF, sum = 0
8952 06:54:09.754800 9, 0xFFFF, sum = 0
8953 06:54:09.758135 10, 0xFFFF, sum = 0
8954 06:54:09.758234 11, 0xFFFF, sum = 0
8955 06:54:09.761111 12, 0xFFFF, sum = 0
8956 06:54:09.761221 13, 0xFFFF, sum = 0
8957 06:54:09.765069 14, 0x0, sum = 1
8958 06:54:09.765168 15, 0x0, sum = 2
8959 06:54:09.768031 16, 0x0, sum = 3
8960 06:54:09.768102 17, 0x0, sum = 4
8961 06:54:09.771877 best_step = 15
8962 06:54:09.771954
8963 06:54:09.772033 ==
8964 06:54:09.775037 Dram Type= 6, Freq= 0, CH_1, rank 1
8965 06:54:09.777879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8966 06:54:09.777951 ==
8967 06:54:09.778018 RX Vref Scan: 0
8968 06:54:09.781530
8969 06:54:09.781598 RX Vref 0 -> 0, step: 1
8970 06:54:09.781670
8971 06:54:09.785174 RX Delay 11 -> 252, step: 4
8972 06:54:09.788023 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8973 06:54:09.795185 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8974 06:54:09.798223 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
8975 06:54:09.802080 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8976 06:54:09.804906 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8977 06:54:09.808448 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
8978 06:54:09.811475 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8979 06:54:09.818094 iDelay=191, Bit 7, Center 126 (75 ~ 178) 104
8980 06:54:09.821303 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8981 06:54:09.824691 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8982 06:54:09.828236 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8983 06:54:09.831442 iDelay=191, Bit 11, Center 118 (63 ~ 174) 112
8984 06:54:09.838504 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8985 06:54:09.841608 iDelay=191, Bit 13, Center 136 (83 ~ 190) 108
8986 06:54:09.844780 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8987 06:54:09.848003 iDelay=191, Bit 15, Center 136 (83 ~ 190) 108
8988 06:54:09.848096 ==
8989 06:54:09.851345 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 06:54:09.858299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 06:54:09.858414 ==
8992 06:54:09.858497 DQS Delay:
8993 06:54:09.861728 DQS0 = 0, DQS1 = 0
8994 06:54:09.861810 DQM Delay:
8995 06:54:09.861894 DQM0 = 129, DQM1 = 126
8996 06:54:09.864821 DQ Delay:
8997 06:54:09.868535 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
8998 06:54:09.871487 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
8999 06:54:09.875112 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =118
9000 06:54:09.878358 DQ12 =134, DQ13 =136, DQ14 =132, DQ15 =136
9001 06:54:09.878441
9002 06:54:09.878523
9003 06:54:09.878601
9004 06:54:09.881991 [DramC_TX_OE_Calibration] TA2
9005 06:54:09.884948 Original DQ_B0 (3 6) =30, OEN = 27
9006 06:54:09.888850 Original DQ_B1 (3 6) =30, OEN = 27
9007 06:54:09.891835 24, 0x0, End_B0=24 End_B1=24
9008 06:54:09.891912 25, 0x0, End_B0=25 End_B1=25
9009 06:54:09.895283 26, 0x0, End_B0=26 End_B1=26
9010 06:54:09.898875 27, 0x0, End_B0=27 End_B1=27
9011 06:54:09.901787 28, 0x0, End_B0=28 End_B1=28
9012 06:54:09.901892 29, 0x0, End_B0=29 End_B1=29
9013 06:54:09.905352 30, 0x0, End_B0=30 End_B1=30
9014 06:54:09.908059 31, 0x4545, End_B0=30 End_B1=30
9015 06:54:09.911586 Byte0 end_step=30 best_step=27
9016 06:54:09.914666 Byte1 end_step=30 best_step=27
9017 06:54:09.918247 Byte0 TX OE(2T, 0.5T) = (3, 3)
9018 06:54:09.918345 Byte1 TX OE(2T, 0.5T) = (3, 3)
9019 06:54:09.921866
9020 06:54:09.921971
9021 06:54:09.928488 [DQSOSCAuto] RK1, (LSB)MR18= 0xe13, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
9022 06:54:09.931344 CH1 RK1: MR19=303, MR18=E13
9023 06:54:09.938310 CH1_RK1: MR19=0x303, MR18=0xE13, DQSOSC=400, MR23=63, INC=23, DEC=15
9024 06:54:09.938419 [RxdqsGatingPostProcess] freq 1600
9025 06:54:09.944504 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9026 06:54:09.948038 best DQS0 dly(2T, 0.5T) = (1, 1)
9027 06:54:09.951614 best DQS1 dly(2T, 0.5T) = (1, 1)
9028 06:54:09.955000 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9029 06:54:09.958065 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9030 06:54:09.961479 best DQS0 dly(2T, 0.5T) = (1, 1)
9031 06:54:09.964650 best DQS1 dly(2T, 0.5T) = (1, 1)
9032 06:54:09.967993 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9033 06:54:09.971534 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9034 06:54:09.971615 Pre-setting of DQS Precalculation
9035 06:54:09.977850 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9036 06:54:09.984635 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9037 06:54:09.991372 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9038 06:54:09.991453
9039 06:54:09.991522
9040 06:54:09.994966 [Calibration Summary] 3200 Mbps
9041 06:54:09.998278 CH 0, Rank 0
9042 06:54:09.998352 SW Impedance : PASS
9043 06:54:10.001660 DUTY Scan : NO K
9044 06:54:10.005188 ZQ Calibration : PASS
9045 06:54:10.005310 Jitter Meter : NO K
9046 06:54:10.008081 CBT Training : PASS
9047 06:54:10.008161 Write leveling : PASS
9048 06:54:10.011641 RX DQS gating : PASS
9049 06:54:10.015109 RX DQ/DQS(RDDQC) : PASS
9050 06:54:10.015219 TX DQ/DQS : PASS
9051 06:54:10.017850 RX DATLAT : PASS
9052 06:54:10.021786 RX DQ/DQS(Engine): PASS
9053 06:54:10.021865 TX OE : PASS
9054 06:54:10.024630 All Pass.
9055 06:54:10.024724
9056 06:54:10.024816 CH 0, Rank 1
9057 06:54:10.028340 SW Impedance : PASS
9058 06:54:10.028440 DUTY Scan : NO K
9059 06:54:10.031286 ZQ Calibration : PASS
9060 06:54:10.034741 Jitter Meter : NO K
9061 06:54:10.034816 CBT Training : PASS
9062 06:54:10.037861 Write leveling : PASS
9063 06:54:10.041364 RX DQS gating : PASS
9064 06:54:10.041434 RX DQ/DQS(RDDQC) : PASS
9065 06:54:10.044486 TX DQ/DQS : PASS
9066 06:54:10.048113 RX DATLAT : PASS
9067 06:54:10.048195 RX DQ/DQS(Engine): PASS
9068 06:54:10.051521 TX OE : PASS
9069 06:54:10.051605 All Pass.
9070 06:54:10.051686
9071 06:54:10.051764 CH 1, Rank 0
9072 06:54:10.055075 SW Impedance : PASS
9073 06:54:10.058197 DUTY Scan : NO K
9074 06:54:10.058297 ZQ Calibration : PASS
9075 06:54:10.061342 Jitter Meter : NO K
9076 06:54:10.065397 CBT Training : PASS
9077 06:54:10.065480 Write leveling : PASS
9078 06:54:10.068299 RX DQS gating : PASS
9079 06:54:10.071456 RX DQ/DQS(RDDQC) : PASS
9080 06:54:10.071556 TX DQ/DQS : PASS
9081 06:54:10.074987 RX DATLAT : PASS
9082 06:54:10.078507 RX DQ/DQS(Engine): PASS
9083 06:54:10.078633 TX OE : PASS
9084 06:54:10.078730 All Pass.
9085 06:54:10.081792
9086 06:54:10.081874 CH 1, Rank 1
9087 06:54:10.084658 SW Impedance : PASS
9088 06:54:10.084741 DUTY Scan : NO K
9089 06:54:10.088431 ZQ Calibration : PASS
9090 06:54:10.088514 Jitter Meter : NO K
9091 06:54:10.091389 CBT Training : PASS
9092 06:54:10.095001 Write leveling : PASS
9093 06:54:10.095086 RX DQS gating : PASS
9094 06:54:10.098046 RX DQ/DQS(RDDQC) : PASS
9095 06:54:10.101600 TX DQ/DQS : PASS
9096 06:54:10.101683 RX DATLAT : PASS
9097 06:54:10.104807 RX DQ/DQS(Engine): PASS
9098 06:54:10.108208 TX OE : PASS
9099 06:54:10.108320 All Pass.
9100 06:54:10.108402
9101 06:54:10.111265 DramC Write-DBI on
9102 06:54:10.111361 PER_BANK_REFRESH: Hybrid Mode
9103 06:54:10.115003 TX_TRACKING: ON
9104 06:54:10.121471 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9105 06:54:10.131646 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9106 06:54:10.138201 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9107 06:54:10.141581 [FAST_K] Save calibration result to emmc
9108 06:54:10.144595 sync common calibartion params.
9109 06:54:10.148273 sync cbt_mode0:1, 1:1
9110 06:54:10.148353 dram_init: ddr_geometry: 2
9111 06:54:10.151259 dram_init: ddr_geometry: 2
9112 06:54:10.154914 dram_init: ddr_geometry: 2
9113 06:54:10.155010 0:dram_rank_size:100000000
9114 06:54:10.157936 1:dram_rank_size:100000000
9115 06:54:10.165204 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9116 06:54:10.167880 DFS_SHUFFLE_HW_MODE: ON
9117 06:54:10.171813 dramc_set_vcore_voltage set vcore to 725000
9118 06:54:10.171895 Read voltage for 1600, 0
9119 06:54:10.174687 Vio18 = 0
9120 06:54:10.174781 Vcore = 725000
9121 06:54:10.174842 Vdram = 0
9122 06:54:10.178225 Vddq = 0
9123 06:54:10.178305 Vmddr = 0
9124 06:54:10.181800 switch to 3200 Mbps bootup
9125 06:54:10.181925 [DramcRunTimeConfig]
9126 06:54:10.182066 PHYPLL
9127 06:54:10.185143 DPM_CONTROL_AFTERK: ON
9128 06:54:10.188398 PER_BANK_REFRESH: ON
9129 06:54:10.188540 REFRESH_OVERHEAD_REDUCTION: ON
9130 06:54:10.191387 CMD_PICG_NEW_MODE: OFF
9131 06:54:10.194829 XRTWTW_NEW_MODE: ON
9132 06:54:10.194912 XRTRTR_NEW_MODE: ON
9133 06:54:10.198430 TX_TRACKING: ON
9134 06:54:10.198511 RDSEL_TRACKING: OFF
9135 06:54:10.201673 DQS Precalculation for DVFS: ON
9136 06:54:10.201753 RX_TRACKING: OFF
9137 06:54:10.204785 HW_GATING DBG: ON
9138 06:54:10.204864 ZQCS_ENABLE_LP4: ON
9139 06:54:10.208282 RX_PICG_NEW_MODE: ON
9140 06:54:10.211255 TX_PICG_NEW_MODE: ON
9141 06:54:10.211348 ENABLE_RX_DCM_DPHY: ON
9142 06:54:10.214954 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9143 06:54:10.217958 DUMMY_READ_FOR_TRACKING: OFF
9144 06:54:10.221619 !!! SPM_CONTROL_AFTERK: OFF
9145 06:54:10.221715 !!! SPM could not control APHY
9146 06:54:10.224588 IMPEDANCE_TRACKING: ON
9147 06:54:10.228341 TEMP_SENSOR: ON
9148 06:54:10.228450 HW_SAVE_FOR_SR: OFF
9149 06:54:10.231524 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9150 06:54:10.234679 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9151 06:54:10.238414 Read ODT Tracking: ON
9152 06:54:10.238494 Refresh Rate DeBounce: ON
9153 06:54:10.241588 DFS_NO_QUEUE_FLUSH: ON
9154 06:54:10.244958 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9155 06:54:10.247862 ENABLE_DFS_RUNTIME_MRW: OFF
9156 06:54:10.247944 DDR_RESERVE_NEW_MODE: ON
9157 06:54:10.251520 MR_CBT_SWITCH_FREQ: ON
9158 06:54:10.254547 =========================
9159 06:54:10.272979 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9160 06:54:10.275820 dram_init: ddr_geometry: 2
9161 06:54:10.293963 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9162 06:54:10.297561 dram_init: dram init end (result: 0)
9163 06:54:10.304398 DRAM-K: Full calibration passed in 24550 msecs
9164 06:54:10.307432 MRC: failed to locate region type 0.
9165 06:54:10.307509 DRAM rank0 size:0x100000000,
9166 06:54:10.310806 DRAM rank1 size=0x100000000
9167 06:54:10.320686 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9168 06:54:10.327402 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9169 06:54:10.334120 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9170 06:54:10.340913 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9171 06:54:10.344120 DRAM rank0 size:0x100000000,
9172 06:54:10.347935 DRAM rank1 size=0x100000000
9173 06:54:10.348016 CBMEM:
9174 06:54:10.351171 IMD: root @ 0xfffff000 254 entries.
9175 06:54:10.354271 IMD: root @ 0xffffec00 62 entries.
9176 06:54:10.357768 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9177 06:54:10.360965 WARNING: RO_VPD is uninitialized or empty.
9178 06:54:10.367695 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9179 06:54:10.374332 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9180 06:54:10.387233 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9181 06:54:10.398775 BS: romstage times (exec / console): total (unknown) / 24056 ms
9182 06:54:10.398863
9183 06:54:10.398927
9184 06:54:10.408331 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9185 06:54:10.411964 ARM64: Exception handlers installed.
9186 06:54:10.414984 ARM64: Testing exception
9187 06:54:10.418477 ARM64: Done test exception
9188 06:54:10.418558 Enumerating buses...
9189 06:54:10.421669 Show all devs... Before device enumeration.
9190 06:54:10.425094 Root Device: enabled 1
9191 06:54:10.428385 CPU_CLUSTER: 0: enabled 1
9192 06:54:10.428465 CPU: 00: enabled 1
9193 06:54:10.431783 Compare with tree...
9194 06:54:10.431863 Root Device: enabled 1
9195 06:54:10.435005 CPU_CLUSTER: 0: enabled 1
9196 06:54:10.438114 CPU: 00: enabled 1
9197 06:54:10.438196 Root Device scanning...
9198 06:54:10.441764 scan_static_bus for Root Device
9199 06:54:10.444782 CPU_CLUSTER: 0 enabled
9200 06:54:10.448326 scan_static_bus for Root Device done
9201 06:54:10.451877 scan_bus: bus Root Device finished in 8 msecs
9202 06:54:10.451957 done
9203 06:54:10.458068 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9204 06:54:10.461617 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9205 06:54:10.468195 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9206 06:54:10.471785 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9207 06:54:10.474981 Allocating resources...
9208 06:54:10.475091 Reading resources...
9209 06:54:10.481585 Root Device read_resources bus 0 link: 0
9210 06:54:10.481660 DRAM rank0 size:0x100000000,
9211 06:54:10.484782 DRAM rank1 size=0x100000000
9212 06:54:10.488247 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9213 06:54:10.491517 CPU: 00 missing read_resources
9214 06:54:10.495235 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9215 06:54:10.501510 Root Device read_resources bus 0 link: 0 done
9216 06:54:10.501592 Done reading resources.
9217 06:54:10.508294 Show resources in subtree (Root Device)...After reading.
9218 06:54:10.511284 Root Device child on link 0 CPU_CLUSTER: 0
9219 06:54:10.514905 CPU_CLUSTER: 0 child on link 0 CPU: 00
9220 06:54:10.524621 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9221 06:54:10.524702 CPU: 00
9222 06:54:10.528369 Root Device assign_resources, bus 0 link: 0
9223 06:54:10.532075 CPU_CLUSTER: 0 missing set_resources
9224 06:54:10.534880 Root Device assign_resources, bus 0 link: 0 done
9225 06:54:10.538568 Done setting resources.
9226 06:54:10.544687 Show resources in subtree (Root Device)...After assigning values.
9227 06:54:10.548101 Root Device child on link 0 CPU_CLUSTER: 0
9228 06:54:10.551581 CPU_CLUSTER: 0 child on link 0 CPU: 00
9229 06:54:10.561577 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9230 06:54:10.561664 CPU: 00
9231 06:54:10.564901 Done allocating resources.
9232 06:54:10.568353 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9233 06:54:10.571733 Enabling resources...
9234 06:54:10.571813 done.
9235 06:54:10.575345 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9236 06:54:10.578493 Initializing devices...
9237 06:54:10.581811 Root Device init
9238 06:54:10.581891 init hardware done!
9239 06:54:10.585350 0x00000018: ctrlr->caps
9240 06:54:10.585432 52.000 MHz: ctrlr->f_max
9241 06:54:10.588310 0.400 MHz: ctrlr->f_min
9242 06:54:10.591469 0x40ff8080: ctrlr->voltages
9243 06:54:10.591551 sclk: 390625
9244 06:54:10.594913 Bus Width = 1
9245 06:54:10.594994 sclk: 390625
9246 06:54:10.595056 Bus Width = 1
9247 06:54:10.598307 Early init status = 3
9248 06:54:10.601789 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9249 06:54:10.605886 in-header: 03 fc 00 00 01 00 00 00
9250 06:54:10.608948 in-data: 00
9251 06:54:10.612648 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9252 06:54:10.617511 in-header: 03 fd 00 00 00 00 00 00
9253 06:54:10.621278 in-data:
9254 06:54:10.624711 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9255 06:54:10.629024 in-header: 03 fc 00 00 01 00 00 00
9256 06:54:10.632271 in-data: 00
9257 06:54:10.635716 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9258 06:54:10.641223 in-header: 03 fd 00 00 00 00 00 00
9259 06:54:10.644847 in-data:
9260 06:54:10.647833 [SSUSB] Setting up USB HOST controller...
9261 06:54:10.650892 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9262 06:54:10.654558 [SSUSB] phy power-on done.
9263 06:54:10.658166 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9264 06:54:10.664367 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9265 06:54:10.667755 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9266 06:54:10.674812 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9267 06:54:10.680827 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9268 06:54:10.687624 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9269 06:54:10.694591 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9270 06:54:10.700938 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9271 06:54:10.701021 SPM: binary array size = 0x9dc
9272 06:54:10.707460 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9273 06:54:10.714140 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9274 06:54:10.720813 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9275 06:54:10.724685 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9276 06:54:10.727561 configure_display: Starting display init
9277 06:54:10.764392 anx7625_power_on_init: Init interface.
9278 06:54:10.768150 anx7625_disable_pd_protocol: Disabled PD feature.
9279 06:54:10.771071 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9280 06:54:10.798999 anx7625_start_dp_work: Secure OCM version=00
9281 06:54:10.801813 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9282 06:54:10.816684 sp_tx_get_edid_block: EDID Block = 1
9283 06:54:10.919513 Extracted contents:
9284 06:54:10.922773 header: 00 ff ff ff ff ff ff 00
9285 06:54:10.926107 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9286 06:54:10.929218 version: 01 04
9287 06:54:10.932721 basic params: 95 1f 11 78 0a
9288 06:54:10.936541 chroma info: 76 90 94 55 54 90 27 21 50 54
9289 06:54:10.939654 established: 00 00 00
9290 06:54:10.943087 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9291 06:54:10.949361 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9292 06:54:10.956101 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9293 06:54:10.962829 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9294 06:54:10.969586 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9295 06:54:10.972712 extensions: 00
9296 06:54:10.972794 checksum: fb
9297 06:54:10.972857
9298 06:54:10.976481 Manufacturer: IVO Model 57d Serial Number 0
9299 06:54:10.979449 Made week 0 of 2020
9300 06:54:10.979525 EDID version: 1.4
9301 06:54:10.982816 Digital display
9302 06:54:10.986623 6 bits per primary color channel
9303 06:54:10.986713 DisplayPort interface
9304 06:54:10.989435 Maximum image size: 31 cm x 17 cm
9305 06:54:10.989518 Gamma: 220%
9306 06:54:10.992697 Check DPMS levels
9307 06:54:10.996283 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9308 06:54:10.999645 First detailed timing is preferred timing
9309 06:54:11.002539 Established timings supported:
9310 06:54:11.005882 Standard timings supported:
9311 06:54:11.005964 Detailed timings
9312 06:54:11.012604 Hex of detail: 383680a07038204018303c0035ae10000019
9313 06:54:11.016337 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9314 06:54:11.019179 0780 0798 07c8 0820 hborder 0
9315 06:54:11.025940 0438 043b 0447 0458 vborder 0
9316 06:54:11.026034 -hsync -vsync
9317 06:54:11.029631 Did detailed timing
9318 06:54:11.032594 Hex of detail: 000000000000000000000000000000000000
9319 06:54:11.035787 Manufacturer-specified data, tag 0
9320 06:54:11.042487 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9321 06:54:11.042568 ASCII string: InfoVision
9322 06:54:11.049326 Hex of detail: 000000fe00523134304e574635205248200a
9323 06:54:11.049406 ASCII string: R140NWF5 RH
9324 06:54:11.052699 Checksum
9325 06:54:11.052799 Checksum: 0xfb (valid)
9326 06:54:11.059077 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9327 06:54:11.062664 DSI data_rate: 832800000 bps
9328 06:54:11.065639 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9329 06:54:11.069145 anx7625_parse_edid: pixelclock(138800).
9330 06:54:11.075802 hactive(1920), hsync(48), hfp(24), hbp(88)
9331 06:54:11.079515 vactive(1080), vsync(12), vfp(3), vbp(17)
9332 06:54:11.082541 anx7625_dsi_config: config dsi.
9333 06:54:11.089137 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9334 06:54:11.101432 anx7625_dsi_config: success to config DSI
9335 06:54:11.104779 anx7625_dp_start: MIPI phy setup OK.
9336 06:54:11.108191 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9337 06:54:11.111838 mtk_ddp_mode_set invalid vrefresh 60
9338 06:54:11.115105 main_disp_path_setup
9339 06:54:11.115185 ovl_layer_smi_id_en
9340 06:54:11.118528 ovl_layer_smi_id_en
9341 06:54:11.118609 ccorr_config
9342 06:54:11.118672 aal_config
9343 06:54:11.121565 gamma_config
9344 06:54:11.121646 postmask_config
9345 06:54:11.124742 dither_config
9346 06:54:11.128191 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9347 06:54:11.134698 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9348 06:54:11.138381 Root Device init finished in 554 msecs
9349 06:54:11.138461 CPU_CLUSTER: 0 init
9350 06:54:11.147955 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9351 06:54:11.151479 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9352 06:54:11.155096 APU_MBOX 0x190000b0 = 0x10001
9353 06:54:11.157897 APU_MBOX 0x190001b0 = 0x10001
9354 06:54:11.161539 APU_MBOX 0x190005b0 = 0x10001
9355 06:54:11.164495 APU_MBOX 0x190006b0 = 0x10001
9356 06:54:11.168070 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9357 06:54:11.180229 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9358 06:54:11.193114 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9359 06:54:11.199136 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9360 06:54:11.211543 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9361 06:54:11.219929 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9362 06:54:11.223562 CPU_CLUSTER: 0 init finished in 81 msecs
9363 06:54:11.226704 Devices initialized
9364 06:54:11.230126 Show all devs... After init.
9365 06:54:11.230237 Root Device: enabled 1
9366 06:54:11.233536 CPU_CLUSTER: 0: enabled 1
9367 06:54:11.236910 CPU: 00: enabled 1
9368 06:54:11.240050 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9369 06:54:11.243280 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9370 06:54:11.247060 ELOG: NV offset 0x57f000 size 0x1000
9371 06:54:11.253534 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9372 06:54:11.260069 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9373 06:54:11.263655 ELOG: Event(17) added with size 13 at 2024-04-30 06:54:10 UTC
9374 06:54:11.266472 out: cmd=0x121: 03 db 21 01 00 00 00 00
9375 06:54:11.271598 in-header: 03 f0 00 00 2c 00 00 00
9376 06:54:11.284852 in-data: 6f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9377 06:54:11.291798 ELOG: Event(A1) added with size 10 at 2024-04-30 06:54:11 UTC
9378 06:54:11.298330 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9379 06:54:11.304766 ELOG: Event(A0) added with size 9 at 2024-04-30 06:54:11 UTC
9380 06:54:11.308262 elog_add_boot_reason: Logged dev mode boot
9381 06:54:11.312082 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9382 06:54:11.314933 Finalize devices...
9383 06:54:11.315015 Devices finalized
9384 06:54:11.321200 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9385 06:54:11.325066 Writing coreboot table at 0xffe64000
9386 06:54:11.328032 0. 000000000010a000-0000000000113fff: RAMSTAGE
9387 06:54:11.331507 1. 0000000040000000-00000000400fffff: RAM
9388 06:54:11.334761 2. 0000000040100000-000000004032afff: RAMSTAGE
9389 06:54:11.341755 3. 000000004032b000-00000000545fffff: RAM
9390 06:54:11.344674 4. 0000000054600000-000000005465ffff: BL31
9391 06:54:11.348235 5. 0000000054660000-00000000ffe63fff: RAM
9392 06:54:11.351821 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9393 06:54:11.358424 7. 0000000100000000-000000023fffffff: RAM
9394 06:54:11.358506 Passing 5 GPIOs to payload:
9395 06:54:11.365028 NAME | PORT | POLARITY | VALUE
9396 06:54:11.368063 EC in RW | 0x000000aa | low | undefined
9397 06:54:11.375168 EC interrupt | 0x00000005 | low | undefined
9398 06:54:11.378093 TPM interrupt | 0x000000ab | high | undefined
9399 06:54:11.381656 SD card detect | 0x00000011 | high | undefined
9400 06:54:11.388114 speaker enable | 0x00000093 | high | undefined
9401 06:54:11.391143 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9402 06:54:11.394964 in-header: 03 f9 00 00 02 00 00 00
9403 06:54:11.395071 in-data: 02 00
9404 06:54:11.398495 ADC[4]: Raw value=899852 ID=7
9405 06:54:11.401202 ADC[3]: Raw value=213336 ID=1
9406 06:54:11.401304 RAM Code: 0x71
9407 06:54:11.404864 ADC[6]: Raw value=74557 ID=0
9408 06:54:11.407708 ADC[5]: Raw value=212229 ID=1
9409 06:54:11.407805 SKU Code: 0x1
9410 06:54:11.415160 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum e385
9411 06:54:11.418011 coreboot table: 964 bytes.
9412 06:54:11.421653 IMD ROOT 0. 0xfffff000 0x00001000
9413 06:54:11.424662 IMD SMALL 1. 0xffffe000 0x00001000
9414 06:54:11.428610 RO MCACHE 2. 0xffffc000 0x00001104
9415 06:54:11.431420 CONSOLE 3. 0xfff7c000 0x00080000
9416 06:54:11.435054 FMAP 4. 0xfff7b000 0x00000452
9417 06:54:11.438176 TIME STAMP 5. 0xfff7a000 0x00000910
9418 06:54:11.441787 VBOOT WORK 6. 0xfff66000 0x00014000
9419 06:54:11.444666 RAMOOPS 7. 0xffe66000 0x00100000
9420 06:54:11.448118 COREBOOT 8. 0xffe64000 0x00002000
9421 06:54:11.448193 IMD small region:
9422 06:54:11.451613 IMD ROOT 0. 0xffffec00 0x00000400
9423 06:54:11.454689 VPD 1. 0xffffeb80 0x0000006c
9424 06:54:11.458314 MMC STATUS 2. 0xffffeb60 0x00000004
9425 06:54:11.464635 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9426 06:54:11.464713 Probing TPM: done!
9427 06:54:11.471283 Connected to device vid:did:rid of 1ae0:0028:00
9428 06:54:11.478322 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9429 06:54:11.481896 Initialized TPM device CR50 revision 0
9430 06:54:11.485892 Checking cr50 for pending updates
9431 06:54:11.491027 Reading cr50 TPM mode
9432 06:54:11.499768 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9433 06:54:11.506584 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9434 06:54:11.546433 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9435 06:54:11.549905 Checking segment from ROM address 0x40100000
9436 06:54:11.552975 Checking segment from ROM address 0x4010001c
9437 06:54:11.560082 Loading segment from ROM address 0x40100000
9438 06:54:11.560182 code (compression=0)
9439 06:54:11.566838 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9440 06:54:11.576696 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9441 06:54:11.576782 it's not compressed!
9442 06:54:11.583638 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9443 06:54:11.586757 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9444 06:54:11.607247 Loading segment from ROM address 0x4010001c
9445 06:54:11.607347 Entry Point 0x80000000
9446 06:54:11.610436 Loaded segments
9447 06:54:11.613452 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9448 06:54:11.620117 Jumping to boot code at 0x80000000(0xffe64000)
9449 06:54:11.626913 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9450 06:54:11.633306 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9451 06:54:11.641568 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9452 06:54:11.644551 Checking segment from ROM address 0x40100000
9453 06:54:11.648191 Checking segment from ROM address 0x4010001c
9454 06:54:11.654995 Loading segment from ROM address 0x40100000
9455 06:54:11.655095 code (compression=1)
9456 06:54:11.661402 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9457 06:54:11.671351 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9458 06:54:11.671448 using LZMA
9459 06:54:11.679783 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9460 06:54:11.686164 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9461 06:54:11.689971 Loading segment from ROM address 0x4010001c
9462 06:54:11.690052 Entry Point 0x54601000
9463 06:54:11.693042 Loaded segments
9464 06:54:11.696809 NOTICE: MT8192 bl31_setup
9465 06:54:11.703120 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9466 06:54:11.706379 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9467 06:54:11.710113 WARNING: region 0:
9468 06:54:11.713377 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9469 06:54:11.713475 WARNING: region 1:
9470 06:54:11.720392 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9471 06:54:11.723275 WARNING: region 2:
9472 06:54:11.726904 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9473 06:54:11.730079 WARNING: region 3:
9474 06:54:11.733435 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9475 06:54:11.737114 WARNING: region 4:
9476 06:54:11.740508 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9477 06:54:11.743739 WARNING: region 5:
9478 06:54:11.747253 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 06:54:11.750404 WARNING: region 6:
9480 06:54:11.753935 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 06:54:11.754017 WARNING: region 7:
9482 06:54:11.760608 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 06:54:11.767006 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9484 06:54:11.770196 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9485 06:54:11.773669 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9486 06:54:11.780489 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9487 06:54:11.783659 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9488 06:54:11.787241 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9489 06:54:11.793297 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9490 06:54:11.797195 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9491 06:54:11.800235 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9492 06:54:11.807344 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9493 06:54:11.810292 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9494 06:54:11.813919 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9495 06:54:11.820543 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9496 06:54:11.823497 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9497 06:54:11.830633 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9498 06:54:11.834047 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9499 06:54:11.837529 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9500 06:54:11.843770 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9501 06:54:11.847060 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9502 06:54:11.850515 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9503 06:54:11.857357 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9504 06:54:11.860733 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9505 06:54:11.867290 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9506 06:54:11.871054 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9507 06:54:11.874057 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9508 06:54:11.880665 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9509 06:54:11.884432 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9510 06:54:11.887710 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9511 06:54:11.894237 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9512 06:54:11.897750 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9513 06:54:11.904080 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9514 06:54:11.907504 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9515 06:54:11.911011 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9516 06:54:11.914257 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9517 06:54:11.920889 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9518 06:54:11.924439 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9519 06:54:11.928131 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9520 06:54:11.931524 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9521 06:54:11.937971 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9522 06:54:11.940940 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9523 06:54:11.944623 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9524 06:54:11.947662 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9525 06:54:11.954351 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9526 06:54:11.958039 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9527 06:54:11.961326 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9528 06:54:11.964486 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9529 06:54:11.971506 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9530 06:54:11.974657 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9531 06:54:11.978322 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9532 06:54:11.984496 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9533 06:54:11.988022 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9534 06:54:11.994864 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9535 06:54:11.998426 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9536 06:54:12.001292 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9537 06:54:12.007954 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9538 06:54:12.011585 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9539 06:54:12.018118 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9540 06:54:12.021490 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9541 06:54:12.024989 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9542 06:54:12.031695 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9543 06:54:12.034855 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9544 06:54:12.041666 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9545 06:54:12.045150 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9546 06:54:12.051603 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9547 06:54:12.055020 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9548 06:54:12.061734 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9549 06:54:12.064965 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9550 06:54:12.068421 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9551 06:54:12.074703 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9552 06:54:12.078555 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9553 06:54:12.085152 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9554 06:54:12.088267 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9555 06:54:12.091774 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9556 06:54:12.098335 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9557 06:54:12.101551 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9558 06:54:12.108541 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9559 06:54:12.111640 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9560 06:54:12.118260 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9561 06:54:12.121547 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9562 06:54:12.128502 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9563 06:54:12.132121 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9564 06:54:12.135041 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9565 06:54:12.141791 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9566 06:54:12.145598 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9567 06:54:12.151916 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9568 06:54:12.155310 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9569 06:54:12.158462 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9570 06:54:12.165457 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9571 06:54:12.169002 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9572 06:54:12.175721 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9573 06:54:12.178547 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9574 06:54:12.185775 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9575 06:54:12.189089 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9576 06:54:12.192448 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9577 06:54:12.198954 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9578 06:54:12.202601 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9579 06:54:12.209160 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9580 06:54:12.212529 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9581 06:54:12.216046 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9582 06:54:12.219050 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9583 06:54:12.222762 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9584 06:54:12.229010 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9585 06:54:12.232644 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9586 06:54:12.239373 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9587 06:54:12.243196 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9588 06:54:12.245706 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9589 06:54:12.252583 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9590 06:54:12.255797 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9591 06:54:12.263079 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9592 06:54:12.265837 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9593 06:54:12.269122 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9594 06:54:12.276309 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9595 06:54:12.279302 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9596 06:54:12.286294 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9597 06:54:12.289889 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9598 06:54:12.292930 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9599 06:54:12.296470 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9600 06:54:12.302728 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9601 06:54:12.306619 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9602 06:54:12.309664 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9603 06:54:12.316658 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9604 06:54:12.319583 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9605 06:54:12.323269 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9606 06:54:12.326450 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9607 06:54:12.333042 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9608 06:54:12.336764 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9609 06:54:12.340387 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9610 06:54:12.347029 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9611 06:54:12.350389 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9612 06:54:12.356858 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9613 06:54:12.359819 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9614 06:54:12.363467 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9615 06:54:12.370056 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9616 06:54:12.373620 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9617 06:54:12.376535 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9618 06:54:12.383803 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9619 06:54:12.387031 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9620 06:54:12.393392 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9621 06:54:12.396754 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9622 06:54:12.400282 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9623 06:54:12.406881 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9624 06:54:12.410548 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9625 06:54:12.416753 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9626 06:54:12.420317 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9627 06:54:12.423984 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9628 06:54:12.430282 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9629 06:54:12.434019 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9630 06:54:12.437030 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9631 06:54:12.443725 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9632 06:54:12.447388 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9633 06:54:12.453800 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9634 06:54:12.456990 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9635 06:54:12.460366 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9636 06:54:12.467621 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9637 06:54:12.470551 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9638 06:54:12.473969 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9639 06:54:12.480489 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9640 06:54:12.484221 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9641 06:54:12.490500 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9642 06:54:12.494190 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9643 06:54:12.497348 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9644 06:54:12.504214 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9645 06:54:12.507259 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9646 06:54:12.514409 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9647 06:54:12.517278 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9648 06:54:12.520656 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9649 06:54:12.527201 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9650 06:54:12.530872 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9651 06:54:12.533819 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9652 06:54:12.540465 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9653 06:54:12.544271 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9654 06:54:12.550775 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9655 06:54:12.553892 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9656 06:54:12.557439 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9657 06:54:12.564387 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9658 06:54:12.567168 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9659 06:54:12.570785 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9660 06:54:12.577278 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9661 06:54:12.580488 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9662 06:54:12.587522 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9663 06:54:12.590528 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9664 06:54:12.593882 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9665 06:54:12.600613 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9666 06:54:12.604107 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9667 06:54:12.610350 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9668 06:54:12.613582 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9669 06:54:12.616995 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9670 06:54:12.623875 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9671 06:54:12.626797 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9672 06:54:12.633748 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9673 06:54:12.636977 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9674 06:54:12.640423 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9675 06:54:12.647101 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9676 06:54:12.650376 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9677 06:54:12.656954 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9678 06:54:12.660828 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9679 06:54:12.663613 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9680 06:54:12.670379 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9681 06:54:12.673823 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9682 06:54:12.680449 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9683 06:54:12.683825 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9684 06:54:12.687290 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9685 06:54:12.694070 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9686 06:54:12.697102 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9687 06:54:12.704235 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9688 06:54:12.707423 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9689 06:54:12.713731 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9690 06:54:12.717329 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9691 06:54:12.720640 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9692 06:54:12.726826 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9693 06:54:12.730768 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9694 06:54:12.737139 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9695 06:54:12.740566 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9696 06:54:12.744145 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9697 06:54:12.750206 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9698 06:54:12.753767 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9699 06:54:12.760307 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9700 06:54:12.763994 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9701 06:54:12.770173 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9702 06:54:12.773434 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9703 06:54:12.777012 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9704 06:54:12.783569 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9705 06:54:12.787273 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9706 06:54:12.793817 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9707 06:54:12.797235 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9708 06:54:12.800460 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9709 06:54:12.807084 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9710 06:54:12.810181 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9711 06:54:12.816968 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9712 06:54:12.820335 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9713 06:54:12.823941 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9714 06:54:12.827394 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9715 06:54:12.830672 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9716 06:54:12.837061 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9717 06:54:12.840256 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9718 06:54:12.843790 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9719 06:54:12.850506 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9720 06:54:12.853679 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9721 06:54:12.857319 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9722 06:54:12.864202 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9723 06:54:12.867146 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9724 06:54:12.873799 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9725 06:54:12.877045 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9726 06:54:12.880609 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9727 06:54:12.887113 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9728 06:54:12.890685 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9729 06:54:12.893936 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9730 06:54:12.900577 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9731 06:54:12.904271 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9732 06:54:12.907198 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9733 06:54:12.913987 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9734 06:54:12.916925 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9735 06:54:12.923619 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9736 06:54:12.927078 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9737 06:54:12.930646 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9738 06:54:12.936969 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9739 06:54:12.940219 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9740 06:54:12.943431 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9741 06:54:12.950425 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9742 06:54:12.953528 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9743 06:54:12.956922 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9744 06:54:12.963746 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9745 06:54:12.966843 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9746 06:54:12.970381 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9747 06:54:12.977101 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9748 06:54:12.980830 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9749 06:54:12.987548 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9750 06:54:12.990514 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9751 06:54:12.994095 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9752 06:54:12.997346 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9753 06:54:13.003912 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9754 06:54:13.006974 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9755 06:54:13.010305 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9756 06:54:13.013914 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9757 06:54:13.020223 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9758 06:54:13.023731 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9759 06:54:13.027446 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9760 06:54:13.030743 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9761 06:54:13.036946 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9762 06:54:13.040475 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9763 06:54:13.044066 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9764 06:54:13.047262 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9765 06:54:13.053918 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9766 06:54:13.057141 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9767 06:54:13.063831 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9768 06:54:13.066867 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9769 06:54:13.073927 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9770 06:54:13.077061 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9771 06:54:13.080357 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9772 06:54:13.087060 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9773 06:54:13.090794 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9774 06:54:13.093642 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9775 06:54:13.100434 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9776 06:54:13.103663 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9777 06:54:13.110718 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9778 06:54:13.114342 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9779 06:54:13.120290 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9780 06:54:13.124221 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9781 06:54:13.126999 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9782 06:54:13.133882 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9783 06:54:13.136797 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9784 06:54:13.143644 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9785 06:54:13.147167 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9786 06:54:13.150263 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9787 06:54:13.156912 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9788 06:54:13.160386 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9789 06:54:13.166967 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9790 06:54:13.170341 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9791 06:54:13.173819 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9792 06:54:13.180456 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9793 06:54:13.183533 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9794 06:54:13.190182 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9795 06:54:13.193787 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9796 06:54:13.197195 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9797 06:54:13.203968 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9798 06:54:13.207220 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9799 06:54:13.213511 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9800 06:54:13.217076 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9801 06:54:13.219963 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9802 06:54:13.227272 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9803 06:54:13.230454 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9804 06:54:13.236934 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9805 06:54:13.240627 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9806 06:54:13.243690 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9807 06:54:13.250540 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9808 06:54:13.253895 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9809 06:54:13.260206 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9810 06:54:13.263649 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9811 06:54:13.267033 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9812 06:54:13.274074 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9813 06:54:13.276934 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9814 06:54:13.283521 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9815 06:54:13.287040 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9816 06:54:13.290556 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9817 06:54:13.297143 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9818 06:54:13.300748 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9819 06:54:13.307075 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9820 06:54:13.310098 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9821 06:54:13.313694 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9822 06:54:13.320274 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9823 06:54:13.323836 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9824 06:54:13.330171 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9825 06:54:13.333631 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9826 06:54:13.340138 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9827 06:54:13.343214 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9828 06:54:13.346944 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9829 06:54:13.353360 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9830 06:54:13.357136 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9831 06:54:13.363953 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9832 06:54:13.366771 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9833 06:54:13.369743 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9834 06:54:13.376920 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9835 06:54:13.380396 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9836 06:54:13.383317 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9837 06:54:13.390175 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9838 06:54:13.393717 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9839 06:54:13.400093 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9840 06:54:13.403560 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9841 06:54:13.410016 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9842 06:54:13.413430 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9843 06:54:13.420388 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9844 06:54:13.423822 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9845 06:54:13.427342 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9846 06:54:13.433407 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9847 06:54:13.437041 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9848 06:54:13.443702 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9849 06:54:13.446734 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9850 06:54:13.453706 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9851 06:54:13.456526 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9852 06:54:13.459978 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9853 06:54:13.466843 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9854 06:54:13.470087 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9855 06:54:13.476610 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9856 06:54:13.479982 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9857 06:54:13.487289 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9858 06:54:13.490198 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9859 06:54:13.493360 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9860 06:54:13.499820 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9861 06:54:13.503264 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9862 06:54:13.509889 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9863 06:54:13.513153 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9864 06:54:13.519866 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9865 06:54:13.523047 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9866 06:54:13.526635 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9867 06:54:13.533145 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9868 06:54:13.536720 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9869 06:54:13.543577 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9870 06:54:13.546652 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9871 06:54:13.553353 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9872 06:54:13.556445 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9873 06:54:13.559964 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9874 06:54:13.566533 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9875 06:54:13.569662 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9876 06:54:13.576521 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9877 06:54:13.580130 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9878 06:54:13.586322 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9879 06:54:13.590064 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9880 06:54:13.593684 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9881 06:54:13.600005 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9882 06:54:13.603128 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9883 06:54:13.609820 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9884 06:54:13.613124 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9885 06:54:13.616499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9886 06:54:13.623529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9887 06:54:13.626560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9888 06:54:13.633572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9889 06:54:13.636491 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9890 06:54:13.642991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9891 06:54:13.646329 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9892 06:54:13.653479 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9893 06:54:13.656322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9894 06:54:13.663134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9895 06:54:13.666929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9896 06:54:13.673288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9897 06:54:13.676967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9898 06:54:13.682963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9899 06:54:13.686516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9900 06:54:13.690139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9901 06:54:13.696409 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9902 06:54:13.700088 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9903 06:54:13.706791 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9904 06:54:13.709854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9905 06:54:13.716348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9906 06:54:13.719955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9907 06:54:13.726757 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9908 06:54:13.730076 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9909 06:54:13.736465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9910 06:54:13.739979 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9911 06:54:13.746721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9912 06:54:13.750406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9913 06:54:13.756517 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9914 06:54:13.760011 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9915 06:54:13.766577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9916 06:54:13.769995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9917 06:54:13.776734 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9918 06:54:13.776846 INFO: [APUAPC] vio 0
9919 06:54:13.783159 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9920 06:54:13.786770 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9921 06:54:13.789705 INFO: [APUAPC] D0_APC_0: 0x400510
9922 06:54:13.793455 INFO: [APUAPC] D0_APC_1: 0x0
9923 06:54:13.796320 INFO: [APUAPC] D0_APC_2: 0x1540
9924 06:54:13.799738 INFO: [APUAPC] D0_APC_3: 0x0
9925 06:54:13.803163 INFO: [APUAPC] D1_APC_0: 0xffffffff
9926 06:54:13.807015 INFO: [APUAPC] D1_APC_1: 0xffffffff
9927 06:54:13.809661 INFO: [APUAPC] D1_APC_2: 0x3fffff
9928 06:54:13.813314 INFO: [APUAPC] D1_APC_3: 0x0
9929 06:54:13.816340 INFO: [APUAPC] D2_APC_0: 0xffffffff
9930 06:54:13.819972 INFO: [APUAPC] D2_APC_1: 0xffffffff
9931 06:54:13.823679 INFO: [APUAPC] D2_APC_2: 0x3fffff
9932 06:54:13.823752 INFO: [APUAPC] D2_APC_3: 0x0
9933 06:54:13.829693 INFO: [APUAPC] D3_APC_0: 0xffffffff
9934 06:54:13.833295 INFO: [APUAPC] D3_APC_1: 0xffffffff
9935 06:54:13.836580 INFO: [APUAPC] D3_APC_2: 0x3fffff
9936 06:54:13.836668 INFO: [APUAPC] D3_APC_3: 0x0
9937 06:54:13.839912 INFO: [APUAPC] D4_APC_0: 0xffffffff
9938 06:54:13.843687 INFO: [APUAPC] D4_APC_1: 0xffffffff
9939 06:54:13.846749 INFO: [APUAPC] D4_APC_2: 0x3fffff
9940 06:54:13.849921 INFO: [APUAPC] D4_APC_3: 0x0
9941 06:54:13.853361 INFO: [APUAPC] D5_APC_0: 0xffffffff
9942 06:54:13.856925 INFO: [APUAPC] D5_APC_1: 0xffffffff
9943 06:54:13.860126 INFO: [APUAPC] D5_APC_2: 0x3fffff
9944 06:54:13.863041 INFO: [APUAPC] D5_APC_3: 0x0
9945 06:54:13.866359 INFO: [APUAPC] D6_APC_0: 0xffffffff
9946 06:54:13.870297 INFO: [APUAPC] D6_APC_1: 0xffffffff
9947 06:54:13.873470 INFO: [APUAPC] D6_APC_2: 0x3fffff
9948 06:54:13.876979 INFO: [APUAPC] D6_APC_3: 0x0
9949 06:54:13.879867 INFO: [APUAPC] D7_APC_0: 0xffffffff
9950 06:54:13.883741 INFO: [APUAPC] D7_APC_1: 0xffffffff
9951 06:54:13.886771 INFO: [APUAPC] D7_APC_2: 0x3fffff
9952 06:54:13.889959 INFO: [APUAPC] D7_APC_3: 0x0
9953 06:54:13.893381 INFO: [APUAPC] D8_APC_0: 0xffffffff
9954 06:54:13.897001 INFO: [APUAPC] D8_APC_1: 0xffffffff
9955 06:54:13.899854 INFO: [APUAPC] D8_APC_2: 0x3fffff
9956 06:54:13.903382 INFO: [APUAPC] D8_APC_3: 0x0
9957 06:54:13.906889 INFO: [APUAPC] D9_APC_0: 0xffffffff
9958 06:54:13.909797 INFO: [APUAPC] D9_APC_1: 0xffffffff
9959 06:54:13.913496 INFO: [APUAPC] D9_APC_2: 0x3fffff
9960 06:54:13.916500 INFO: [APUAPC] D9_APC_3: 0x0
9961 06:54:13.920263 INFO: [APUAPC] D10_APC_0: 0xffffffff
9962 06:54:13.923329 INFO: [APUAPC] D10_APC_1: 0xffffffff
9963 06:54:13.927108 INFO: [APUAPC] D10_APC_2: 0x3fffff
9964 06:54:13.930009 INFO: [APUAPC] D10_APC_3: 0x0
9965 06:54:13.933471 INFO: [APUAPC] D11_APC_0: 0xffffffff
9966 06:54:13.936601 INFO: [APUAPC] D11_APC_1: 0xffffffff
9967 06:54:13.940252 INFO: [APUAPC] D11_APC_2: 0x3fffff
9968 06:54:13.943397 INFO: [APUAPC] D11_APC_3: 0x0
9969 06:54:13.947012 INFO: [APUAPC] D12_APC_0: 0xffffffff
9970 06:54:13.950433 INFO: [APUAPC] D12_APC_1: 0xffffffff
9971 06:54:13.953531 INFO: [APUAPC] D12_APC_2: 0x3fffff
9972 06:54:13.956609 INFO: [APUAPC] D12_APC_3: 0x0
9973 06:54:13.960202 INFO: [APUAPC] D13_APC_0: 0xffffffff
9974 06:54:13.964043 INFO: [APUAPC] D13_APC_1: 0xffffffff
9975 06:54:13.966912 INFO: [APUAPC] D13_APC_2: 0x3fffff
9976 06:54:13.970110 INFO: [APUAPC] D13_APC_3: 0x0
9977 06:54:13.973515 INFO: [APUAPC] D14_APC_0: 0xffffffff
9978 06:54:13.976534 INFO: [APUAPC] D14_APC_1: 0xffffffff
9979 06:54:13.980166 INFO: [APUAPC] D14_APC_2: 0x3fffff
9980 06:54:13.983922 INFO: [APUAPC] D14_APC_3: 0x0
9981 06:54:13.986869 INFO: [APUAPC] D15_APC_0: 0xffffffff
9982 06:54:13.989816 INFO: [APUAPC] D15_APC_1: 0xffffffff
9983 06:54:13.993370 INFO: [APUAPC] D15_APC_2: 0x3fffff
9984 06:54:13.996981 INFO: [APUAPC] D15_APC_3: 0x0
9985 06:54:14.000375 INFO: [APUAPC] APC_CON: 0x4
9986 06:54:14.003682 INFO: [NOCDAPC] D0_APC_0: 0x0
9987 06:54:14.003756 INFO: [NOCDAPC] D0_APC_1: 0x0
9988 06:54:14.006929 INFO: [NOCDAPC] D1_APC_0: 0x0
9989 06:54:14.010160 INFO: [NOCDAPC] D1_APC_1: 0xfff
9990 06:54:14.013812 INFO: [NOCDAPC] D2_APC_0: 0x0
9991 06:54:14.017094 INFO: [NOCDAPC] D2_APC_1: 0xfff
9992 06:54:14.020190 INFO: [NOCDAPC] D3_APC_0: 0x0
9993 06:54:14.023767 INFO: [NOCDAPC] D3_APC_1: 0xfff
9994 06:54:14.027063 INFO: [NOCDAPC] D4_APC_0: 0x0
9995 06:54:14.030759 INFO: [NOCDAPC] D4_APC_1: 0xfff
9996 06:54:14.030842 INFO: [NOCDAPC] D5_APC_0: 0x0
9997 06:54:14.033668 INFO: [NOCDAPC] D5_APC_1: 0xfff
9998 06:54:14.037249 INFO: [NOCDAPC] D6_APC_0: 0x0
9999 06:54:14.040399 INFO: [NOCDAPC] D6_APC_1: 0xfff
10000 06:54:14.044054 INFO: [NOCDAPC] D7_APC_0: 0x0
10001 06:54:14.047087 INFO: [NOCDAPC] D7_APC_1: 0xfff
10002 06:54:14.050318 INFO: [NOCDAPC] D8_APC_0: 0x0
10003 06:54:14.053668 INFO: [NOCDAPC] D8_APC_1: 0xfff
10004 06:54:14.056823 INFO: [NOCDAPC] D9_APC_0: 0x0
10005 06:54:14.060459 INFO: [NOCDAPC] D9_APC_1: 0xfff
10006 06:54:14.060569 INFO: [NOCDAPC] D10_APC_0: 0x0
10007 06:54:14.063899 INFO: [NOCDAPC] D10_APC_1: 0xfff
10008 06:54:14.066948 INFO: [NOCDAPC] D11_APC_0: 0x0
10009 06:54:14.070096 INFO: [NOCDAPC] D11_APC_1: 0xfff
10010 06:54:14.073767 INFO: [NOCDAPC] D12_APC_0: 0x0
10011 06:54:14.077217 INFO: [NOCDAPC] D12_APC_1: 0xfff
10012 06:54:14.080294 INFO: [NOCDAPC] D13_APC_0: 0x0
10013 06:54:14.083973 INFO: [NOCDAPC] D13_APC_1: 0xfff
10014 06:54:14.086912 INFO: [NOCDAPC] D14_APC_0: 0x0
10015 06:54:14.090344 INFO: [NOCDAPC] D14_APC_1: 0xfff
10016 06:54:14.094041 INFO: [NOCDAPC] D15_APC_0: 0x0
10017 06:54:14.097087 INFO: [NOCDAPC] D15_APC_1: 0xfff
10018 06:54:14.100120 INFO: [NOCDAPC] APC_CON: 0x4
10019 06:54:14.103767 INFO: [APUAPC] set_apusys_apc done
10020 06:54:14.106887 INFO: [DEVAPC] devapc_init done
10021 06:54:14.110305 INFO: GICv3 without legacy support detected.
10022 06:54:14.113962 INFO: ARM GICv3 driver initialized in EL3
10023 06:54:14.117557 INFO: Maximum SPI INTID supported: 639
10024 06:54:14.120408 INFO: BL31: Initializing runtime services
10025 06:54:14.127444 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10026 06:54:14.130234 INFO: SPM: enable CPC mode
10027 06:54:14.133600 INFO: mcdi ready for mcusys-off-idle and system suspend
10028 06:54:14.140190 INFO: BL31: Preparing for EL3 exit to normal world
10029 06:54:14.143768 INFO: Entry point address = 0x80000000
10030 06:54:14.143852 INFO: SPSR = 0x8
10031 06:54:14.151658
10032 06:54:14.151759
10033 06:54:14.151850
10034 06:54:14.154502 Starting depthcharge on Spherion...
10035 06:54:14.154580
10036 06:54:14.154677 Wipe memory regions:
10037 06:54:14.154738
10038 06:54:14.155431 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10039 06:54:14.155535 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10040 06:54:14.155616 Setting prompt string to ['asurada:']
10041 06:54:14.155690 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10042 06:54:14.157598 [0x00000040000000, 0x00000054600000)
10043 06:54:14.279853
10044 06:54:14.279984 [0x00000054660000, 0x00000080000000)
10045 06:54:14.540508
10046 06:54:14.540653 [0x000000821a7280, 0x000000ffe64000)
10047 06:54:15.285543
10048 06:54:15.285674 [0x00000100000000, 0x00000240000000)
10049 06:54:17.175925
10050 06:54:17.179374 Initializing XHCI USB controller at 0x11200000.
10051 06:54:18.219577
10052 06:54:18.222263 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10053 06:54:18.222698
10054 06:54:18.223021
10055 06:54:18.223321
10056 06:54:18.224137 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10058 06:54:18.325294 asurada: tftpboot 192.168.201.1 13580668/tftp-deploy-jo2e459g/kernel/image.itb 13580668/tftp-deploy-jo2e459g/kernel/cmdline
10059 06:54:18.325872 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10060 06:54:18.326289 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10061 06:54:18.330959 tftpboot 192.168.201.1 13580668/tftp-deploy-jo2e459g/kernel/image.itp-deploy-jo2e459g/kernel/cmdline
10062 06:54:18.331379
10063 06:54:18.331752 Waiting for link
10064 06:54:18.488933
10065 06:54:18.489436 R8152: Initializing
10066 06:54:18.489770
10067 06:54:18.492405 Version 6 (ocp_data = 5c30)
10068 06:54:18.492809
10069 06:54:18.495336 R8152: Done initializing
10070 06:54:18.495743
10071 06:54:18.496118 Adding net device
10072 06:54:20.407506
10073 06:54:20.407639 done.
10074 06:54:20.407705
10075 06:54:20.407763 MAC: 00:24:32:30:78:52
10076 06:54:20.407820
10077 06:54:20.410758 Sending DHCP discover... done.
10078 06:54:20.410838
10079 06:54:24.098276 Waiting for reply... done.
10080 06:54:24.098432
10081 06:54:24.098544 Sending DHCP request... done.
10082 06:54:24.101726
10083 06:54:24.105559 Waiting for reply... done.
10084 06:54:24.105658
10085 06:54:24.105750 My ip is 192.168.201.14
10086 06:54:24.105837
10087 06:54:24.108866 The DHCP server ip is 192.168.201.1
10088 06:54:24.108952
10089 06:54:24.115579 TFTP server IP predefined by user: 192.168.201.1
10090 06:54:24.115664
10091 06:54:24.122228 Bootfile predefined by user: 13580668/tftp-deploy-jo2e459g/kernel/image.itb
10092 06:54:24.122304
10093 06:54:24.122365 Sending tftp read request... done.
10094 06:54:24.125610
10095 06:54:24.129111 Waiting for the transfer...
10096 06:54:24.129192
10097 06:54:24.770882 00000000 ################################################################
10098 06:54:24.771034
10099 06:54:25.440551 00080000 ################################################################
10100 06:54:25.440701
10101 06:54:26.079998 00100000 ################################################################
10102 06:54:26.080153
10103 06:54:26.721902 00180000 ################################################################
10104 06:54:26.722046
10105 06:54:27.361119 00200000 ################################################################
10106 06:54:27.361301
10107 06:54:28.013672 00280000 ################################################################
10108 06:54:28.013820
10109 06:54:28.652354 00300000 ################################################################
10110 06:54:28.652569
10111 06:54:29.290133 00380000 ################################################################
10112 06:54:29.290274
10113 06:54:29.834242 00400000 ################################################################
10114 06:54:29.834386
10115 06:54:30.476639 00480000 ################################################################
10116 06:54:30.476771
10117 06:54:31.143357 00500000 ################################################################
10118 06:54:31.143500
10119 06:54:31.803534 00580000 ################################################################
10120 06:54:31.803679
10121 06:54:32.443535 00600000 ################################################################
10122 06:54:32.443682
10123 06:54:33.093456 00680000 ################################################################
10124 06:54:33.093589
10125 06:54:33.733642 00700000 ################################################################
10126 06:54:33.733790
10127 06:54:34.370334 00780000 ################################################################
10128 06:54:34.370493
10129 06:54:35.014334 00800000 ################################################################
10130 06:54:35.014474
10131 06:54:35.663200 00880000 ################################################################
10132 06:54:35.663341
10133 06:54:36.315351 00900000 ################################################################
10134 06:54:36.315494
10135 06:54:36.957582 00980000 ################################################################
10136 06:54:36.957719
10137 06:54:37.591582 00a00000 ################################################################
10138 06:54:37.591714
10139 06:54:38.226566 00a80000 ################################################################
10140 06:54:38.226734
10141 06:54:38.849709 00b00000 ################################################################
10142 06:54:38.849901
10143 06:54:39.493115 00b80000 ################################################################
10144 06:54:39.493320
10145 06:54:40.095567 00c00000 ################################################################
10146 06:54:40.095721
10147 06:54:40.719123 00c80000 ################################################################
10148 06:54:40.719311
10149 06:54:41.348433 00d00000 ################################################################
10150 06:54:41.348593
10151 06:54:41.904393 00d80000 ################################################################
10152 06:54:41.904561
10153 06:54:42.525498 00e00000 ################################################################
10154 06:54:42.525645
10155 06:54:43.144462 00e80000 ################################################################
10156 06:54:43.144633
10157 06:54:43.764281 00f00000 ################################################################
10158 06:54:43.764417
10159 06:54:44.375042 00f80000 ################################################################
10160 06:54:44.375219
10161 06:54:44.986994 01000000 ################################################################
10162 06:54:44.987127
10163 06:54:45.546551 01080000 ################################################################
10164 06:54:45.546700
10165 06:54:46.120657 01100000 ################################################################
10166 06:54:46.120833
10167 06:54:46.741453 01180000 ################################################################
10168 06:54:46.741607
10169 06:54:47.365881 01200000 ################################################################
10170 06:54:47.366186
10171 06:54:47.995306 01280000 ################################################################
10172 06:54:47.995459
10173 06:54:48.613655 01300000 ################################################################
10174 06:54:48.613805
10175 06:54:49.241154 01380000 ################################################################
10176 06:54:49.241335
10177 06:54:49.866085 01400000 ################################################################
10178 06:54:49.866247
10179 06:54:50.489865 01480000 ################################################################
10180 06:54:50.490016
10181 06:54:51.126623 01500000 ################################################################
10182 06:54:51.126769
10183 06:54:51.755519 01580000 ################################################################
10184 06:54:51.755678
10185 06:54:52.344674 01600000 ################################################################
10186 06:54:52.344839
10187 06:54:52.973113 01680000 ################################################################
10188 06:54:52.973289
10189 06:54:53.601676 01700000 ################################################################
10190 06:54:53.601840
10191 06:54:54.226166 01780000 ################################################################
10192 06:54:54.226292
10193 06:54:54.830630 01800000 ################################################################
10194 06:54:54.830779
10195 06:54:55.468240 01880000 ################################################################
10196 06:54:55.468393
10197 06:54:56.084037 01900000 ################################################################
10198 06:54:56.084187
10199 06:54:56.652777 01980000 ################################################################
10200 06:54:56.652921
10201 06:54:57.222540 01a00000 ################################################################
10202 06:54:57.222694
10203 06:54:57.862303 01a80000 ################################################################
10204 06:54:57.862462
10205 06:54:58.528047 01b00000 ################################################################
10206 06:54:58.528194
10207 06:54:59.188069 01b80000 ################################################################
10208 06:54:59.188208
10209 06:54:59.819505 01c00000 ################################################################
10210 06:54:59.819661
10211 06:55:00.452222 01c80000 ################################################################
10212 06:55:00.452364
10213 06:55:01.034808 01d00000 ################################################################
10214 06:55:01.034939
10215 06:55:01.586293 01d80000 ################################################################
10216 06:55:01.586449
10217 06:55:02.189266 01e00000 ################################################################
10218 06:55:02.189438
10219 06:55:02.847858 01e80000 ################################################################
10220 06:55:02.848008
10221 06:55:03.497793 01f00000 ################################################################
10222 06:55:03.497943
10223 06:55:04.141974 01f80000 ################################################################
10224 06:55:04.142117
10225 06:55:04.784249 02000000 ################################################################
10226 06:55:04.784401
10227 06:55:05.423290 02080000 ################################################################
10228 06:55:05.423441
10229 06:55:06.065735 02100000 ################################################################
10230 06:55:06.065881
10231 06:55:06.700159 02180000 ################################################################
10232 06:55:06.700302
10233 06:55:07.357194 02200000 ################################################################
10234 06:55:07.357363
10235 06:55:08.000832 02280000 ################################################################
10236 06:55:08.000981
10237 06:55:08.675205 02300000 ################################################################
10238 06:55:08.675375
10239 06:55:08.738427 02380000 ###### done.
10240 06:55:08.738583
10241 06:55:08.741711 The bootfile was 37272790 bytes long.
10242 06:55:08.741817
10243 06:55:08.744878 Sending tftp read request... done.
10244 06:55:08.744974
10245 06:55:08.745058 Waiting for the transfer...
10246 06:55:08.745117
10247 06:55:08.748754 00000000 # done.
10248 06:55:08.748838
10249 06:55:08.755143 Command line loaded dynamically from TFTP file: 13580668/tftp-deploy-jo2e459g/kernel/cmdline
10250 06:55:08.755226
10251 06:55:08.768196 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10252 06:55:08.768282
10253 06:55:08.771509 Loading FIT.
10254 06:55:08.771592
10255 06:55:08.775225 Image ramdisk-1 has 23529346 bytes.
10256 06:55:08.775308
10257 06:55:08.775372 Image fdt-1 has 65280 bytes.
10258 06:55:08.775432
10259 06:55:08.778466 Image kernel-1 has 13676132 bytes.
10260 06:55:08.778548
10261 06:55:08.788643 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10262 06:55:08.788726
10263 06:55:08.805192 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10264 06:55:08.805296
10265 06:55:08.811463 Choosing best match conf-1 for compat google,spherion-rev2.
10266 06:55:08.815942
10267 06:55:08.819951 Connected to device vid:did:rid of 1ae0:0028:00
10268 06:55:08.826925
10269 06:55:08.830300 tpm_get_response: command 0x17b, return code 0x0
10270 06:55:08.830383
10271 06:55:08.833559 ec_init: CrosEC protocol v3 supported (256, 248)
10272 06:55:08.837605
10273 06:55:08.841129 tpm_cleanup: add release locality here.
10274 06:55:08.841217
10275 06:55:08.841296 Shutting down all USB controllers.
10276 06:55:08.844830
10277 06:55:08.844910 Removing current net device
10278 06:55:08.844972
10279 06:55:08.851348 Exiting depthcharge with code 4 at timestamp: 84072032
10280 06:55:08.851428
10281 06:55:08.854388 LZMA decompressing kernel-1 to 0x821a6718
10282 06:55:08.854468
10283 06:55:08.857979 LZMA decompressing kernel-1 to 0x40000000
10284 06:55:10.566859
10285 06:55:10.567015 jumping to kernel
10286 06:55:10.567504 end: 2.2.4 bootloader-commands (duration 00:00:56) [common]
10287 06:55:10.567603 start: 2.2.5 auto-login-action (timeout 00:03:29) [common]
10288 06:55:10.567680 Setting prompt string to ['Linux version [0-9]']
10289 06:55:10.567750 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10290 06:55:10.567816 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10291 06:55:10.645750
10292 06:55:10.649185 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10293 06:55:10.652259 start: 2.2.5.1 login-action (timeout 00:03:29) [common]
10294 06:55:10.652353 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10295 06:55:10.652423 Setting prompt string to []
10296 06:55:10.652500 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10297 06:55:10.652578 Using line separator: #'\n'#
10298 06:55:10.652637 No login prompt set.
10299 06:55:10.652696 Parsing kernel messages
10300 06:55:10.652751 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10301 06:55:10.652849 [login-action] Waiting for messages, (timeout 00:03:29)
10302 06:55:10.652914 Waiting using forced prompt support (timeout 00:01:44)
10303 06:55:10.672093 [ 0.000000] Linux version 6.9.0-rc4 (KernelCI@build-j181641-arm64-gcc-10-defconfig-arm64-chromebook-xb9dh) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Apr 30 06:31:51 UTC 2024
10304 06:55:10.675501 [ 0.000000] KASLR enabled
10305 06:55:10.679202 [ 0.000000] random: crng init done
10306 06:55:10.682254 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10307 06:55:10.685652 [ 0.000000] efi: UEFI not found.
10308 06:55:10.695806 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10309 06:55:10.702363 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10310 06:55:10.712067 [ 0.000000] OF: reserved mem: 0x0000000050000000..0x00000000528fffff (41984 KiB) nomap non-reusable scp@50000000
10311 06:55:10.722139 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10312 06:55:10.731949 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10313 06:55:10.741950 [ 0.000000] OF: reserved mem: 0x00000000c0000000..0x00000000c3ffffff (65536 KiB) map non-reusable wifi@c0000000
10314 06:55:10.748715 [ 0.000000] OF: reserved mem: 0x00000000ffe66000..0x00000000fff65fff (1024 KiB) map non-reusable ramoops
10315 06:55:10.758850 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10316 06:55:10.762373 [ 0.000000] printk: legacy bootconsole [mtk8250] enabled
10317 06:55:10.770994 [ 0.000000] NUMA: No NUMA configuration found
10318 06:55:10.777974 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10319 06:55:10.784223 [ 0.000000] NUMA: NODE_DATA [mem 0x23efbb9c0-0x23efbdfff]
10320 06:55:10.784304 [ 0.000000] Zone ranges:
10321 06:55:10.791065 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10322 06:55:10.794345 [ 0.000000] DMA32 empty
10323 06:55:10.800931 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10324 06:55:10.804199 [ 0.000000] Movable zone start for each node
10325 06:55:10.807734 [ 0.000000] Early memory node ranges
10326 06:55:10.814115 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10327 06:55:10.820697 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10328 06:55:10.827442 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10329 06:55:10.834037 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10330 06:55:10.840956 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10331 06:55:10.847216 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10332 06:55:10.871671 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10333 06:55:10.910271 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10334 06:55:10.917016 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000 on node -1
10335 06:55:10.923683 [ 0.000000] psci: probing for conduit method from DT.
10336 06:55:10.927248 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10337 06:55:10.934025 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10338 06:55:10.936973 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10339 06:55:10.940503 [ 0.000000] psci: SMC Calling Convention v1.2
10340 06:55:10.947442 [ 0.000000] percpu: Embedded 24 pages/cpu s59112 r8192 d31000 u98304
10341 06:55:10.954172 [ 0.000000] Detected VIPT I-cache on CPU0
10342 06:55:10.960770 [ 0.000000] CPU features: detected: GIC system register CPU interface
10343 06:55:10.963853 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10344 06:55:10.970595 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10345 06:55:10.977185 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10346 06:55:10.983650 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10347 06:55:10.990666 [ 0.000000] alternatives: applying boot alternatives
10348 06:55:11.006804 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10349 06:55:11.017283 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10350 06:55:11.027196 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10351 06:55:11.036987 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10352 06:55:11.040423 <6>[ 0.000000] Fallback order for Node 0: 0
10353 06:55:11.047043 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10354 06:55:11.050060 <6>[ 0.000000] Policy zone: Normal
10355 06:55:11.057153 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10356 06:55:11.059926 <6>[ 0.000000] software IO TLB: area num 8.
10357 06:55:11.117663 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10358 06:55:11.262782 <6>[ 0.000000] Memory: 7934332K/8385536K available (18688K kernel code, 5122K rwdata, 24188K rodata, 10816K init, 755K bss, 418436K reserved, 32768K cma-reserved)
10359 06:55:11.269352 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10360 06:55:11.275926 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10361 06:55:11.279543 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10362 06:55:11.285908 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=8.
10363 06:55:11.293203 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10364 06:55:11.296256 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10365 06:55:11.306047 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10366 06:55:11.312740 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10367 06:55:11.319246 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
10368 06:55:11.326329 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
10369 06:55:11.332439 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10370 06:55:11.339626 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10371 06:55:11.342916 <6>[ 0.000000] GICv3: 608 SPIs implemented
10372 06:55:11.349543 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10373 06:55:11.353342 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10374 06:55:11.356333 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10375 06:55:11.366214 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10376 06:55:11.376190 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10377 06:55:11.389545 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10378 06:55:11.396490 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10379 06:55:11.406193 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10380 06:55:11.419661 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10381 06:55:11.425903 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10382 06:55:11.432964 <6>[ 0.009684] Console: colour dummy device 80x25
10383 06:55:11.443134 <6>[ 0.014413] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10384 06:55:11.449639 <6>[ 0.024856] pid_max: default: 32768 minimum: 301
10385 06:55:11.453062 <6>[ 0.029780] LSM: initializing lsm=capability
10386 06:55:11.459831 <6>[ 0.034404] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10387 06:55:11.469921 <6>[ 0.042216] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10388 06:55:11.476411 <6>[ 0.051101] spectre-v4 mitigation disabled by command-line option
10389 06:55:11.483204 <6>[ 0.058259] rcu: Hierarchical SRCU implementation.
10390 06:55:11.486453 <6>[ 0.063281] rcu: Max phase no-delay instances is 1000.
10391 06:55:11.494685 <6>[ 0.071097] EFI services will not be available.
10392 06:55:11.497938 <6>[ 0.076074] smp: Bringing up secondary CPUs ...
10393 06:55:11.507049 <6>[ 0.081184] Detected VIPT I-cache on CPU1
10394 06:55:11.514018 <6>[ 0.081244] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10395 06:55:11.520480 <6>[ 0.081277] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10396 06:55:11.523897 <6>[ 0.081655] Detected VIPT I-cache on CPU2
10397 06:55:11.530391 <6>[ 0.081696] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10398 06:55:11.537459 <6>[ 0.081717] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10399 06:55:11.544042 <6>[ 0.082024] Detected VIPT I-cache on CPU3
10400 06:55:11.550549 <6>[ 0.082059] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10401 06:55:11.556904 <6>[ 0.082074] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10402 06:55:11.560575 <6>[ 0.082416] CPU features: detected: Spectre-v4
10403 06:55:11.567037 <6>[ 0.082423] CPU features: detected: Spectre-BHB
10404 06:55:11.570124 <6>[ 0.082429] Detected PIPT I-cache on CPU4
10405 06:55:11.576595 <6>[ 0.082470] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10406 06:55:11.583379 <6>[ 0.082488] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10407 06:55:11.590405 <6>[ 0.082820] Detected PIPT I-cache on CPU5
10408 06:55:11.596928 <6>[ 0.082866] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10409 06:55:11.603387 <6>[ 0.082884] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10410 06:55:11.606593 <6>[ 0.083203] Detected PIPT I-cache on CPU6
10411 06:55:11.613608 <6>[ 0.083249] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10412 06:55:11.620673 <6>[ 0.083267] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10413 06:55:11.623673 <6>[ 0.083596] Detected PIPT I-cache on CPU7
10414 06:55:11.633756 <6>[ 0.083643] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10415 06:55:11.640420 <6>[ 0.083663] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10416 06:55:11.643753 <6>[ 0.083745] smp: Brought up 1 node, 8 CPUs
10417 06:55:11.647017 <6>[ 0.225055] SMP: Total of 8 processors activated.
10418 06:55:11.653558 <6>[ 0.229976] CPU: All CPU(s) started at EL2
10419 06:55:11.656661 <6>[ 0.234307] CPU features: detected: 32-bit EL0 Support
10420 06:55:11.666681 <6>[ 0.239661] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10421 06:55:11.673798 <6>[ 0.248464] CPU features: detected: Common not Private translations
10422 06:55:11.679965 <6>[ 0.254936] CPU features: detected: CRC32 instructions
10423 06:55:11.683506 <6>[ 0.260296] CPU features: detected: RCpc load-acquire (LDAPR)
10424 06:55:11.689914 <6>[ 0.266251] CPU features: detected: LSE atomic instructions
10425 06:55:11.696676 <6>[ 0.272031] CPU features: detected: Privileged Access Never
10426 06:55:11.703737 <6>[ 0.277847] CPU features: detected: RAS Extension Support
10427 06:55:11.710137 <6>[ 0.283490] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10428 06:55:11.716594 <6>[ 0.290733] spectre-bhb mitigation disabled by command line option
10429 06:55:11.719636 <6>[ 0.297144] alternatives: applying system-wide alternatives
10430 06:55:11.732572 <6>[ 0.305931] CPU features: detected: Hardware dirty bit management on CPU4-7
10431 06:55:11.735616 <6>[ 0.315216] devtmpfs: initialized
10432 06:55:11.752930 <6>[ 0.326121] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10433 06:55:11.762919 <6>[ 0.336083] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10434 06:55:11.769604 <6>[ 0.344126] pinctrl core: initialized pinctrl subsystem
10435 06:55:11.772328 <6>[ 0.351145] DMI not present or invalid.
10436 06:55:11.780779 <6>[ 0.357216] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10437 06:55:11.790905 <6>[ 0.364046] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10438 06:55:11.797593 <6>[ 0.371556] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10439 06:55:11.807497 <6>[ 0.379773] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10440 06:55:11.810797 <6>[ 0.388005] audit: initializing netlink subsys (disabled)
10441 06:55:11.820502 <5>[ 0.393708] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10442 06:55:11.827456 <6>[ 0.394652] thermal_sys: Registered thermal governor 'step_wise'
10443 06:55:11.834018 <6>[ 0.401673] thermal_sys: Registered thermal governor 'power_allocator'
10444 06:55:11.837621 <6>[ 0.407945] cpuidle: using governor menu
10445 06:55:11.843911 <6>[ 0.418921] NET: Registered PF_QIPCRTR protocol family
10446 06:55:11.850542 <6>[ 0.424422] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10447 06:55:11.857348 <6>[ 0.431535] ASID allocator initialised with 32768 entries
10448 06:55:11.860408 <6>[ 0.438516] Serial: AMBA PL011 UART driver
10449 06:55:11.890645 <6>[ 0.464064] platform 14010000.dsi: Fixed dependency cycle(s) with /soc/i2c@11cb0000/anx7625@58
10450 06:55:11.908338 <6>[ 0.481671] Modules: 2G module region forced by RANDOMIZE_MODULE_REGION_FULL
10451 06:55:11.911772 <6>[ 0.488944] Modules: 0 pages in range for non-PLT usage
10452 06:55:11.918549 <6>[ 0.488946] Modules: 509344 pages in range for PLT usage
10453 06:55:11.924725 <6>[ 0.494910] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10454 06:55:11.931924 <6>[ 0.507458] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10455 06:55:11.938187 <6>[ 0.513947] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10456 06:55:11.944604 <6>[ 0.520953] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10457 06:55:11.951870 <6>[ 0.527440] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10458 06:55:11.958355 <6>[ 0.534443] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10459 06:55:11.964956 <6>[ 0.540930] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10460 06:55:11.971277 <6>[ 0.547934] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10461 06:55:11.977734 <6>[ 0.554672] Demotion targets for Node 0: null
10462 06:55:11.981090 <6>[ 0.560346] ACPI: Interpreter disabled.
10463 06:55:11.989956 <6>[ 0.566847] iommu: Default domain type: Translated
10464 06:55:11.996490 <6>[ 0.571872] iommu: DMA domain TLB invalidation policy: strict mode
10465 06:55:11.999986 <5>[ 0.578723] SCSI subsystem initialized
10466 06:55:12.006439 <6>[ 0.582899] usbcore: registered new interface driver usbfs
10467 06:55:12.013084 <6>[ 0.588629] usbcore: registered new interface driver hub
10468 06:55:12.016597 <6>[ 0.594186] usbcore: registered new device driver usb
10469 06:55:12.024005 <6>[ 0.600438] pps_core: LinuxPPS API ver. 1 registered
10470 06:55:12.033757 <6>[ 0.605634] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10471 06:55:12.037089 <6>[ 0.614978] PTP clock support registered
10472 06:55:12.040264 <6>[ 0.619243] EDAC MC: Ver: 3.0.0
10473 06:55:12.046974 <6>[ 0.623127] scmi_core: SCMI protocol bus registered
10474 06:55:12.050046 <6>[ 0.629629] FPGA manager framework
10475 06:55:12.056672 <6>[ 0.633324] Advanced Linux Sound Architecture Driver Initialized.
10476 06:55:12.060473 <6>[ 0.640269] vgaarb: loaded
10477 06:55:12.067286 <6>[ 0.643525] clocksource: Switched to clocksource arch_sys_counter
10478 06:55:12.073814 <5>[ 0.649996] VFS: Disk quotas dquot_6.6.0
10479 06:55:12.080407 <6>[ 0.654176] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10480 06:55:12.083632 <6>[ 0.661381] pnp: PnP ACPI: disabled
10481 06:55:12.092604 <6>[ 0.668538] NET: Registered PF_INET protocol family
10482 06:55:12.101851 <6>[ 0.674113] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10483 06:55:12.113017 <6>[ 0.686449] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10484 06:55:12.123223 <6>[ 0.695253] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10485 06:55:12.129497 <6>[ 0.703222] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10486 06:55:12.136231 <6>[ 0.711586] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10487 06:55:12.148058 <6>[ 0.721301] TCP: Hash tables configured (established 65536 bind 65536)
10488 06:55:12.154716 <6>[ 0.728162] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10489 06:55:12.161263 <6>[ 0.735224] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10490 06:55:12.167697 <6>[ 0.742793] NET: Registered PF_UNIX/PF_LOCAL protocol family
10491 06:55:12.174532 <6>[ 0.748927] RPC: Registered named UNIX socket transport module.
10492 06:55:12.178288 <6>[ 0.755076] RPC: Registered udp transport module.
10493 06:55:12.184453 <6>[ 0.760009] RPC: Registered tcp transport module.
10494 06:55:12.187660 <6>[ 0.764942] RPC: Registered tcp-with-tls transport module.
10495 06:55:12.194637 <6>[ 0.770655] RPC: Registered tcp NFSv4.1 backchannel transport module.
10496 06:55:12.200939 <6>[ 0.777323] PCI: CLS 0 bytes, default 64
10497 06:55:12.204843 <6>[ 0.781696] Unpacking initramfs...
10498 06:55:12.211514 <6>[ 0.788205] kvm [1]: nv: 477 coarse grained trap handlers
10499 06:55:12.218101 <6>[ 0.794032] kvm [1]: IPA Size Limit: 40 bits
10500 06:55:12.221477 <6>[ 0.798560] kvm [1]: GICv3: no GICV resource entry
10501 06:55:12.228345 <6>[ 0.803580] kvm [1]: disabling GICv2 emulation
10502 06:55:12.231121 <6>[ 0.808269] kvm [1]: GIC system register CPU interface enabled
10503 06:55:12.237825 <6>[ 0.814343] kvm [1]: vgic interrupt IRQ18
10504 06:55:12.241011 <6>[ 0.818606] kvm [1]: VHE mode initialized successfully
10505 06:55:12.248103 <5>[ 0.825018] Initialise system trusted keyrings
10506 06:55:12.255006 <6>[ 0.829833] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10507 06:55:12.261496 <6>[ 0.836693] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10508 06:55:12.264777 <5>[ 0.842930] NFS: Registering the id_resolver key type
10509 06:55:12.271560 <5>[ 0.848232] Key type id_resolver registered
10510 06:55:12.274763 <5>[ 0.852649] Key type id_legacy registered
10511 06:55:12.281787 <6>[ 0.856902] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10512 06:55:12.287953 <6>[ 0.863824] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10513 06:55:12.294708 <6>[ 0.871555] 9p: Installing v9fs 9p2000 file system support
10514 06:55:12.334689 <5>[ 0.911045] Key type asymmetric registered
10515 06:55:12.337583 <5>[ 0.915378] Asymmetric key parser 'x509' registered
10516 06:55:12.347600 <6>[ 0.920522] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10517 06:55:12.350713 <6>[ 0.928137] io scheduler mq-deadline registered
10518 06:55:12.354191 <6>[ 0.932908] io scheduler kyber registered
10519 06:55:12.360661 <6>[ 0.937181] io scheduler bfq registered
10520 06:55:12.390321 <3>[ 0.967082] cannot find "mediatek,mt8192-fhctl"
10521 06:55:12.423549 <6>[ 0.997010] mtk-socinfo mtk-socinfo.0.auto: MediaTek Kompanio 820 (MT8192) SoC detected.
10522 06:55:12.438283 <6>[ 1.015073] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10523 06:55:12.446281 <6>[ 1.023359] printk: legacy console [ttyS0] disabled
10524 06:55:12.475284 <6>[ 1.048738] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 252, base_baud = 1625000) is a ST16650V2
10525 06:55:12.481756 <6>[ 1.058209] printk: legacy console [ttyS0] enabled
10526 06:55:12.485287 <6>[ 1.058209] printk: legacy console [ttyS0] enabled
10527 06:55:12.491798 <6>[ 1.068353] printk: legacy bootconsole [mtk8250] disabled
10528 06:55:12.498699 <6>[ 1.068353] printk: legacy bootconsole [mtk8250] disabled
10529 06:55:12.508173 <6>[ 1.085094] msm_serial: driver initialized
10530 06:55:12.511516 <6>[ 1.089830] SuperH (H)SCI(F) driver initialized
10531 06:55:12.518043 <6>[ 1.094824] STM32 USART driver initialized
10532 06:55:12.524851 <4>[ 1.101085] SPI driver tpm_tis_spi has no spi_device_id for atmel,attpm20p
10533 06:55:12.538786 <6>[ 1.115658] loop: module loaded
10534 06:55:12.545826 <4>[ 1.122375] mtk-pmic-keys: Failed to locate of_node [id: -1]
10535 06:55:12.551954 <6>[ 1.122987] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10536 06:55:12.555214 <6>[ 1.129358] megasas: 07.727.03.00-rc1
10537 06:55:12.563012 <6>[ 1.139761] vsram_others: Bringing 850000uV into 800000-800000uV
10538 06:55:12.573958 <6>[ 1.150933] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10539 06:55:12.590561 <6>[ 1.167056] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10540 06:55:12.660403 <6>[ 1.229848] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10541 06:55:13.205040 <6>[ 1.781523] Freeing initrd memory: 22972K
10542 06:55:13.223479 <6>[ 1.800207] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10543 06:55:13.233745 <6>[ 1.810833] tun: Universal TUN/TAP device driver, 1.6
10544 06:55:13.237110 <6>[ 1.817107] thunder_xcv, ver 1.0
10545 06:55:13.240642 <6>[ 1.820610] thunder_bgx, ver 1.0
10546 06:55:13.243860 <6>[ 1.824105] nicpf, ver 1.0
10547 06:55:13.254979 <6>[ 1.828227] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10548 06:55:13.258377 <6>[ 1.835704] hns3: Copyright (c) 2017 Huawei Corporation.
10549 06:55:13.261148 <6>[ 1.841286] hclge is initializing
10550 06:55:13.268400 <6>[ 1.844875] e1000: Intel(R) PRO/1000 Network Driver
10551 06:55:13.274928 <6>[ 1.850007] e1000: Copyright (c) 1999-2006 Intel Corporation.
10552 06:55:13.277880 <6>[ 1.856016] e1000e: Intel(R) PRO/1000 Network Driver
10553 06:55:13.284922 <6>[ 1.861233] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10554 06:55:13.291227 <6>[ 1.867413] igb: Intel(R) Gigabit Ethernet Network Driver
10555 06:55:13.298173 <6>[ 1.873064] igb: Copyright (c) 2007-2014 Intel Corporation.
10556 06:55:13.304596 <6>[ 1.878904] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10557 06:55:13.311220 <6>[ 1.885440] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10558 06:55:13.314569 <6>[ 1.891948] sky2: driver version 1.30
10559 06:55:13.321131 <6>[ 1.897158] usbcore: registered new device driver r8152-cfgselector
10560 06:55:13.327859 <6>[ 1.903690] usbcore: registered new interface driver r8152
10561 06:55:13.335067 <6>[ 1.909637] VFIO - User Level meta-driver version: 0.3
10562 06:55:13.341120 <6>[ 1.918110] usbcore: registered new interface driver usb-storage
10563 06:55:13.347763 <6>[ 1.924620] usbcore: registered new device driver onboard-usb-hub
10564 06:55:13.357513 <6>[ 1.934350] mt6397-rtc mt6359-rtc: registered as rtc0
10565 06:55:13.368028 <6>[ 1.939840] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-30T06:55:13 UTC (1714460113)
10566 06:55:13.370557 <6>[ 1.949652] i2c_dev: i2c /dev entries driver
10567 06:55:13.381657 <6>[ 1.955324] platform 14010000.dsi: Fixed dependency cycle(s) with /soc/i2c@11cb0000/anx7625@58
10568 06:55:13.392256 <6>[ 1.964242] i2c 3-0058: Fixed dependency cycle(s) with /soc/i2c@11cb0000/anx7625@58/aux-bus/panel
10569 06:55:13.398608 <6>[ 1.973379] i2c 3-0058: Fixed dependency cycle(s) with /soc/dsi@14010000
10570 06:55:13.415538 <6>[ 1.989010] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10571 06:55:13.422184 <4>[ 1.998229] cpu cpu0: supply cpu not found, using dummy regulator
10572 06:55:13.428828 <4>[ 2.004727] cpu cpu1: supply cpu not found, using dummy regulator
10573 06:55:13.435598 <4>[ 2.011135] cpu cpu2: supply cpu not found, using dummy regulator
10574 06:55:13.442392 <4>[ 2.017545] cpu cpu3: supply cpu not found, using dummy regulator
10575 06:55:13.448931 <4>[ 2.023953] cpu cpu4: supply cpu not found, using dummy regulator
10576 06:55:13.455870 <4>[ 2.030371] cpu cpu5: supply cpu not found, using dummy regulator
10577 06:55:13.462465 <4>[ 2.036773] cpu cpu6: supply cpu not found, using dummy regulator
10578 06:55:13.468721 <4>[ 2.043175] cpu cpu7: supply cpu not found, using dummy regulator
10579 06:55:13.487285 <6>[ 2.063869] cpu cpu0: EM: created perf domain
10580 06:55:13.490160 <6>[ 2.068736] cpu cpu4: EM: created perf domain
10581 06:55:13.497588 <6>[ 2.074710] sdhci: Secure Digital Host Controller Interface driver
10582 06:55:13.504397 <6>[ 2.081147] sdhci: Copyright(c) Pierre Ossman
10583 06:55:13.511562 <6>[ 2.086192] Synopsys Designware Multimedia Card Interface Driver
10584 06:55:13.517862 <6>[ 2.092886] sdhci-pltfm: SDHCI platform and OF driver helper
10585 06:55:13.521511 <6>[ 2.093018] mmc0: CQHCI version 5.10
10586 06:55:13.527947 <6>[ 2.103079] ledtrig-cpu: registered to indicate activity on CPUs
10587 06:55:13.534505 <6>[ 2.110366] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10588 06:55:13.541502 <6>[ 2.117499] usbcore: registered new interface driver usbhid
10589 06:55:13.544986 <6>[ 2.123323] usbhid: USB HID core driver
10590 06:55:13.551684 <6>[ 2.127702] spi_master spi0: will run message pump with realtime priority
10591 06:55:13.562556 <6>[ 2.135337] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10592 06:55:13.572777 <6>[ 2.144817] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10593 06:55:13.585823 <6>[ 2.159489] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10594 06:55:13.599105 <6>[ 2.162099] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10595 06:55:13.606153 <6>[ 2.171531] NET: Registered PF_PACKET protocol family
10596 06:55:13.609461 <6>[ 2.186900] 9pnet: Installing 9P2000 support
10597 06:55:13.623339 <6>[ 2.190351] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10598 06:55:13.626268 <5>[ 2.191453] Key type dns_resolver registered
10599 06:55:13.636577 <4>[ 2.192012] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10600 06:55:13.646104 <4>[ 2.192046] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10601 06:55:13.656321 <4>[ 2.192076] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10602 06:55:13.663155 <4>[ 2.192106] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10603 06:55:13.672887 <4>[ 2.192136] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10604 06:55:13.682797 <4>[ 2.192165] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10605 06:55:13.695719 <4>[ 2.192195] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10606 06:55:13.702254 <4>[ 2.192224] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10607 06:55:13.709103 <4>[ 2.192254] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10608 06:55:13.718516 <4>[ 2.192283] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10609 06:55:13.728623 <4>[ 2.192312] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10610 06:55:13.738672 <4>[ 2.192341] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10611 06:55:13.745638 <4>[ 2.192371] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10612 06:55:13.755808 <4>[ 2.192412] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10613 06:55:13.765347 <4>[ 2.192457] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10614 06:55:13.775816 <4>[ 2.192502] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10615 06:55:13.785292 <4>[ 2.192548] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10616 06:55:13.792430 <4>[ 2.192594] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10617 06:55:13.801959 <4>[ 2.192639] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10618 06:55:13.811958 <4>[ 2.192688] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10619 06:55:13.822230 <4>[ 2.192733] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10620 06:55:13.828808 <4>[ 2.192786] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10621 06:55:13.838631 <4>[ 2.192832] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10622 06:55:13.848881 <4>[ 2.192877] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10623 06:55:13.855721 <6>[ 2.193476] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17014
10624 06:55:13.859135 <6>[ 2.206306] cros-ec-spi spi0.0: Chrome EC device registered
10625 06:55:13.865888 <6>[ 2.209714] mmc0: Command Queue Engine enabled
10626 06:55:13.872177 <6>[ 2.212042] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
10627 06:55:13.878708 <6>[ 2.455197] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10628 06:55:13.885535 <6>[ 2.456419] registered taskstats version 1
10629 06:55:13.888541 <6>[ 2.462338] mmcblk0: mmc0:0001 DA4128 116 GiB
10630 06:55:13.895782 <5>[ 2.466358] Loading compiled-in X.509 certificates
10631 06:55:13.899145 <6>[ 2.475758] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10632 06:55:13.906510 <6>[ 2.483767] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10633 06:55:13.913801 <6>[ 2.490871] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10634 06:55:13.921460 <6>[ 2.498375] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10635 06:55:13.927812 <6>[ 2.503392] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10636 06:55:13.935451 <6>[ 2.512140] xhci-mtk 11200000.usb: xHCI Host Controller
10637 06:55:13.942335 <6>[ 2.517655] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10638 06:55:13.952154 <6>[ 2.525498] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000200010
10639 06:55:13.958541 <6>[ 2.534932] xhci-mtk 11200000.usb: irq 270, io mem 0x11200000
10640 06:55:13.965079 <6>[ 2.541005] xhci-mtk 11200000.usb: xHCI Host Controller
10641 06:55:13.971691 <6>[ 2.546480] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10642 06:55:13.978903 <6>[ 2.554135] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10643 06:55:13.985461 <6>[ 2.561811] hub 1-0:1.0: USB hub found
10644 06:55:13.988356 <6>[ 2.565819] hub 1-0:1.0: 1 port detected
10645 06:55:13.995141 <6>[ 2.570092] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10646 06:55:14.002204 <6>[ 2.578645] hub 2-0:1.0: USB hub found
10647 06:55:14.005191 <6>[ 2.582650] hub 2-0:1.0: 1 port detected
10648 06:55:14.027118 <3>[ 2.600831] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10649 06:55:14.038388 <6>[ 2.615075] mtk-msdc 11f70000.mmc: Got CD GPIO
10650 06:55:14.048619 <4>[ 2.621064] rt5682 1-001a: Using default DAI clk names: rt5682-dai-wclk, rt5682-dai-bclk
10651 06:55:14.058109 <3>[ 2.630676] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10652 06:55:14.082803 <3>[ 2.656301] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10653 06:55:14.106919 <3>[ 2.680225] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10654 06:55:14.130664 <3>[ 2.704420] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10655 06:55:14.398123 <6>[ 2.972121] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10656 06:55:14.426764 <6>[ 3.003612] hub 2-1:1.0: USB hub found
10657 06:55:14.430118 <6>[ 3.008104] hub 2-1:1.0: 3 ports detected
10658 06:55:14.462736 <3>[ 3.036034] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10659 06:55:14.468986 <6>[ 3.045768] hub 2-1:1.0: USB hub found
10660 06:55:14.472313 <6>[ 3.050216] hub 2-1:1.0: 3 ports detected
10661 06:55:14.499553 <3>[ 3.073035] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10662 06:55:14.550200 <6>[ 3.123708] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10663 06:55:14.701968 <6>[ 3.279267] hub 1-1:1.0: USB hub found
10664 06:55:14.705552 <6>[ 3.283651] hub 1-1:1.0: 4 ports detected
10665 06:55:14.730545 <3>[ 3.304154] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10666 06:55:14.750129 <6>[ 3.326920] hub 1-1:1.0: USB hub found
10667 06:55:14.753345 <6>[ 3.331243] hub 1-1:1.0: 4 ports detected
10668 06:55:14.786968 <3>[ 3.360596] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10669 06:55:14.793715 <6>[ 3.367765] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10670 06:55:14.898494 <6>[ 3.472370] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10671 06:55:14.936333 <4>[ 3.509846] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10672 06:55:14.946012 <4>[ 3.518980] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10673 06:55:14.984532 <6>[ 3.561656] r8152 2-1.3:1.0 eth0: v1.12.13
10674 06:55:15.009074 <3>[ 3.582457] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10675 06:55:15.074163 <6>[ 3.647894] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10676 06:55:15.207050 <6>[ 3.784033] hub 1-1.4:1.0: USB hub found
10677 06:55:15.210124 <6>[ 3.788789] hub 1-1.4:1.0: 2 ports detected
10678 06:55:15.246354 <3>[ 3.820429] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10679 06:55:15.275379 <6>[ 3.852522] hub 1-1.4:1.0: USB hub found
10680 06:55:15.279152 <6>[ 3.857283] hub 1-1.4:1.0: 2 ports detected
10681 06:55:15.310579 <3>[ 3.884538] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10682 06:55:15.578046 <6>[ 4.151874] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10683 06:55:15.717925 <3>[ 4.291840] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10684 06:55:15.769852 <6>[ 4.343820] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10685 06:55:15.906536 <3>[ 4.480289] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10686 06:55:16.722504 <6>[ 5.299732] r8152 2-1.3:1.0 eth0: carrier on
10687 06:55:18.858549 <5>[ 5.323624] Sending DHCP requests .., OK
10688 06:55:18.864938 <6>[ 7.440218] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10689 06:55:18.868183 <6>[ 7.448535] IP-Config: Complete:
10690 06:55:18.881291 <6>[ 7.452041] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10691 06:55:18.888303 <6>[ 7.462756] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10692 06:55:18.894388 <6>[ 7.471379] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10693 06:55:18.901070 <6>[ 7.471389] nameserver0=192.168.201.1
10694 06:55:18.904867 <6>[ 7.483610] clk: Disabling unused clocks
10695 06:55:18.911611 <6>[ 7.488669] PM: genpd: Disabling unused power domains
10696 06:55:18.914563 <6>[ 7.494029] ALSA device list:
10697 06:55:18.917898 <6>[ 7.497271] No soundcards found.
10698 06:55:18.928306 <6>[ 7.506042] Freeing unused kernel memory: 10816K
10699 06:55:18.932054 <6>[ 7.511059] Run /init as init process
10700 06:55:18.958715 Starting syslogd: OK
10701 06:55:18.962879 Starting klogd: OK
10702 06:55:18.973550 Running sysctl: OK
10703 06:55:18.979817 Populating /dev using udev: <30>[ 7.559326] udevd[173]: starting version 3.2.9
10704 06:55:18.990652 <27>[ 7.568193] udevd[173]: specified user 'tss' unknown
10705 06:55:18.997509 <27>[ 7.573707] udevd[173]: specified group 'tss' unknown
10706 06:55:19.003821 <30>[ 7.580292] udevd[174]: starting eudev-3.2.9
10707 06:55:19.034369 <27>[ 7.611793] udevd[174]: specified user 'tss' unknown
10708 06:55:19.040949 <27>[ 7.617208] udevd[174]: specified group 'tss' unknown
10709 06:55:19.147645 <6>[ 7.724976] pstore: Using crash dump compression: deflate
10710 06:55:19.161388 <6>[ 7.738922] pstore: Registered ramoops as persistent store backend
10711 06:55:19.167810 <6>[ 7.745521] ramoops: using 0x100000@0xffe66000, ecc: 0
10712 06:55:19.207288 <6>[ 7.781111] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10713 06:55:19.213680 <6>[ 7.787320] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10714 06:55:19.224268 <6>[ 7.788845] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10715 06:55:19.230324 <6>[ 7.804879] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10716 06:55:19.240631 <3>[ 7.805510] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10717 06:55:19.243877 <6>[ 7.820570] remoteproc remoteproc0: scp is available
10718 06:55:19.250149 <6>[ 7.826790] remoteproc remoteproc0: powering up scp
10719 06:55:19.257326 <6>[ 7.832078] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10720 06:55:19.263504 <6>[ 7.840544] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10721 06:55:19.276668 <6>[ 7.853709] mc: Linux media interface: v0.10
10722 06:55:19.291958 <6>[ 7.866015] mediatek-mipi-tx 11e50000.dsi-phy: can't get nvmem_cell_get, ignore it
10723 06:55:19.298624 <6>[ 7.867278] sbs-battery 8-000b: sbs-battery: battery gas gauge device registered
10724 06:55:19.310801 <6>[ 7.888259] Bluetooth: Core ver 2.22
10725 06:55:19.317550 <6>[ 7.894637] videodev: Linux video capture interface: v2.00
10726 06:55:19.333890 <6>[ 7.910941] NET: Registered PF_BLUETOOTH protocol family
10727 06:55:19.340367 <6>[ 7.916589] Bluetooth: HCI device and connection manager initialized
10728 06:55:19.350784 <4>[ 7.916924] sbs-battery 8-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10729 06:55:19.353372 <4>[ 7.916924] Fallback method does not support PEC.
10730 06:55:19.359708 <6>[ 7.923233] Bluetooth: HCI socket layer initialized
10731 06:55:19.363298 <6>[ 7.941983] Bluetooth: L2CAP socket layer initialized
10732 06:55:19.373134 <6>[ 7.943043] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10733 06:55:19.376845 <6>[ 7.947313] Bluetooth: SCO socket layer initialized
10734 06:55:19.383091 <6>[ 7.955598] pci_bus 0000:00: root bus resource [bus 00-ff]
10735 06:55:19.389730 <3>[ 7.956656] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10736 06:55:19.396242 <4>[ 7.960329] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
10737 06:55:19.406737 <6>[ 7.965472] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10738 06:55:19.413067 <4>[ 7.973416] elants_i2c 0-0010: supply vccio not found, using dummy regulator
10739 06:55:19.420117 <6>[ 7.980517] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10740 06:55:19.426907 <6>[ 7.980519] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10741 06:55:19.437398 <6>[ 7.980600] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10742 06:55:19.444034 <6>[ 7.980693] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400 PCIe Root Port
10743 06:55:19.450707 <6>[ 7.980732] pci 0000:00:00.0: BAR 0 [mem 0x00000000-0x00003fff 64bit pref]
10744 06:55:19.457982 <6>[ 7.980744] pci 0000:00:00.0: PCI bridge to [bus 00]
10745 06:55:19.464084 <6>[ 7.980755] pci 0000:00:00.0: bridge window [io 0x0000-0x0fff]
10746 06:55:19.470939 <6>[ 7.980762] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff]
10747 06:55:19.477529 <6>[ 7.980773] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff 64bit pref]
10748 06:55:19.484106 <6>[ 7.980874] pci 0000:00:00.0: supports D1 D2
10749 06:55:19.491229 <6>[ 7.980877] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10750 06:55:19.497734 <6>[ 7.983675] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10751 06:55:19.507100 <6>[ 7.983820] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000 PCIe Endpoint
10752 06:55:19.514130 <6>[ 7.983855] pci 0000:01:00.0: BAR 0 [mem 0x00000000-0x000fffff 64bit pref]
10753 06:55:19.521052 <6>[ 7.983875] pci 0000:01:00.0: BAR 2 [mem 0x00000000-0x00003fff 64bit pref]
10754 06:55:19.527139 <6>[ 7.983893] pci 0000:01:00.0: BAR 4 [mem 0x00000000-0x00000fff 64bit pref]
10755 06:55:19.533779 <6>[ 7.984029] pci 0000:01:00.0: supports D1 D2
10756 06:55:19.540379 <6>[ 7.984033] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10757 06:55:19.547424 <6>[ 7.992902] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/ovl@14005000
10758 06:55:19.553554 <6>[ 7.994918] remoteproc remoteproc0: remote processor scp is now up
10759 06:55:19.560527 <6>[ 7.995939] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10760 06:55:19.571021 <6>[ 7.996074] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]: assigned
10761 06:55:19.577128 <6>[ 7.996086] pci 0000:00:00.0: BAR 0 [mem 0x12200000-0x12203fff 64bit pref]: assigned
10762 06:55:19.587040 <6>[ 7.996117] pci 0000:01:00.0: BAR 0 [mem 0x12000000-0x120fffff 64bit pref]: assigned
10763 06:55:19.594018 <6>[ 7.996136] pci 0000:01:00.0: BAR 2 [mem 0x12100000-0x12103fff 64bit pref]: assigned
10764 06:55:19.600608 <6>[ 7.996158] pci 0000:01:00.0: BAR 4 [mem 0x12104000-0x12104fff 64bit pref]: assigned
10765 06:55:19.607129 <6>[ 7.996178] pci 0000:00:00.0: PCI bridge to [bus 01]
10766 06:55:19.613369 <6>[ 7.996196] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10767 06:55:19.620542 <6>[ 7.997084] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10768 06:55:19.630524 <3>[ 7.997369] power_supply sbs-8-000b: driver failed to report `time_to_empty_now' property: -5
10769 06:55:19.636869 <6>[ 8.001084] pcieport 0000:00:00.0: PME: Signaling with IRQ 277
10770 06:55:19.643546 <6>[ 8.002198] pcieport 0000:00:00.0: AER: enabled with IRQ 277
10771 06:55:19.650086 <6>[ 8.003509] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/ovl@14006000
10772 06:55:19.660177 <3>[ 8.020420] power_supply sbs-8-000b: driver failed to report `time_to_empty_now' property: -5
10773 06:55:19.666951 <6>[ 8.027969] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/rdma@14007000
10774 06:55:19.677011 <6>[ 8.027994] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/color@14009000
10775 06:55:19.683554 <6>[ 8.035278] panfrost 13000000.gpu: clock rate = 357999878
10776 06:55:19.689896 <6>[ 8.040446] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/ccorr@1400a000
10777 06:55:19.699824 <6>[ 8.049742] panfrost 13000000.gpu: mali-g57 id 0x9093 major 0x0 minor 0x0 status 0x0
10778 06:55:19.706491 <6>[ 8.053796] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/aal@1400b000
10779 06:55:19.716358 <6>[ 8.061790] panfrost 13000000.gpu: features: 00000000,000019f7, issues: 00000003,80000400
10780 06:55:19.726311 <6>[ 8.066312] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/gamma@1400c000
10781 06:55:19.736517 <6>[ 8.072369] elan_i2c 2-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10782 06:55:19.742880 <6>[ 8.072771] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-2/2-0015/input/input2
10783 06:55:19.756151 <6>[ 8.073341] panfrost 13000000.gpu: Features: L2:0x07130206 Shader:0x00000000 Tiler:0x00000809 Mem:0x101 MMU:0x00002830 AS:0xff JS:0x7
10784 06:55:19.766230 <6>[ 8.081487] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/dsi@14010000
10785 06:55:19.772907 <6>[ 8.088882] panfrost 13000000.gpu: shader_present=0x50045 l2_present=0x1
10786 06:55:19.780053 <6>[ 8.090045] [drm] Initialized panfrost 1.2.0 20180908 for 13000000.gpu on minor 0
10787 06:55:19.789428 <6>[ 8.096045] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/ovl@14014000
10788 06:55:19.799712 <6>[ 8.099868] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-0/0-0010/input/input3
10789 06:55:19.806329 <3>[ 8.106056] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10790 06:55:19.816185 <6>[ 8.110758] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/rdma@14015000
10791 06:55:19.823203 <3>[ 8.121925] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10792 06:55:19.829593 <6>[ 8.205236] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10793 06:55:19.836278 <6>[ 8.213227] usbcore: registered new interface driver btusb
10794 06:55:19.846266 <4>[ 8.219828] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1a_2_hdr.bin failed with error -2
10795 06:55:19.852902 <6>[ 8.222938] usbcore: registered new interface driver uvcvideo
10796 06:55:19.859807 <6>[ 8.243270] cros-ec-dev cros-ec-dev.12.auto: CrOS System Control Processor MCU detected
10797 06:55:19.866169 <3>[ 8.250995] Bluetooth: hci0: Failed to load firmware file (-2)
10798 06:55:19.876044 <6>[ 8.277873] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10799 06:55:19.882586 <5>[ 8.277971] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10800 06:55:19.889736 <3>[ 8.282249] Bluetooth: hci0: Failed to set up firmware (-2)
10801 06:55:19.899027 <4>[ 8.284994] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10802 06:55:19.905567 <6>[ 8.285649] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10803 06:55:19.915700 <6>[ 8.285654] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10804 06:55:19.926115 <3>[ 8.288704] debugfs: Directory '11210000.syscon:mt8192-afe-pcm' with parent 'mt8192_mt6359_rt1015p_rt5682' already present!
10805 06:55:19.931907 <4>[ 8.294444] rt5682 1-001a: ASoC: source widget I2S1 overwritten
10806 06:55:19.941914 <4>[ 8.299276] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10807 06:55:19.949009 <5>[ 8.309257] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10808 06:55:19.958498 <5>[ 8.532488] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10809 06:55:19.965562 <4>[ 8.540047] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10810 06:55:19.971673 <6>[ 8.548930] cfg80211: failed to load regulatory.db
10811 06:55:19.997868 <6>[ 8.572106] input: mt8192_mt6359_rt1015p_rt5682 Headset Jack as /devices/platform/sound/sound/card0/input4
10812 06:55:20.010619 <3>[ 8.588068] SVSB_GPU_LOW: cannot get "gpu" thermal zone
10813 06:55:20.016817 <3>[ 8.593724] mtk-svs 1100bc00.svs: error -ENODEV: svs bank resource setup fail
10814 06:55:20.026914 <6>[ 8.594911] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10815 06:55:20.033436 <6>[ 8.603954] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10816 06:55:20.040233 <6>[ 8.608662] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10817 06:55:20.050368 <6>[ 8.616868] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10818 06:55:20.053978 <6>[ 8.625532] mt7921e 0000:01:00.0: ASIC revision: 79610010
10819 06:55:20.063583 <6>[ 8.631460] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10820 06:55:20.070216 <6>[ 8.631467] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10821 06:55:20.079877 <6>[ 8.631471] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10822 06:55:20.086802 <6>[ 8.662127] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10823 06:55:20.096449 <6>[ 8.670466] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10824 06:55:20.103130 <6>[ 8.678805] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10825 06:55:20.113038 <6>[ 8.687145] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10826 06:55:20.119545 <6>[ 8.695482] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10827 06:55:20.129600 <6>[ 8.703821] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10828 06:55:20.136496 <6>[ 8.712161] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10829 06:55:20.146375 <6>[ 8.720507] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10830 06:55:20.152653 <6>[ 8.728856] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10831 06:55:20.162640 <6>[ 8.730407] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10832 06:55:20.166111 <6>[ 8.730407]
10833 06:55:20.172519 <6>[ 8.737206] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10834 06:55:20.333147 <6>[ 8.907194] panel-simple-dp-aux aux-3-0058: Detected IVO R140NWF5 RH (0x057d)
10835 06:55:20.344477 <6>[ 8.922361] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10836 06:55:20.360747 <6>[ 8.938481] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10837 06:55:20.366229 done
10838 06:55:20.372857 <6>[ 8.948765] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10839 06:55:20.385181 <6>[ 8.959321] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10840 06:55:20.393063 Saving random seed: <6>[ 8.970730] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10841 06:55:20.396689 OK
10842 06:55:20.406667 <6>[ 8.978471] mediatek-drm mediatek-drm.11.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops [mediatek_drm])
10843 06:55:20.416169 <6>[ 8.989091] mediatek-drm mediatek-drm.11.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops [mediatek_drm])
10844 06:55:20.426785 <6>[ 8.999628] mediatek-drm mediatek-drm.11.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops [mediatek_drm])
10845 06:55:20.436571 <6>[ 9.005714] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10846 06:55:20.446470 <6>[ 9.010339] mediatek-drm mediatek-drm.11.auto: bound 14009000.color (ops mtk_disp_color_component_ops [mediatek_drm])
10847 06:55:20.459833 <6>[ 9.029972] mediatek-drm mediatek-drm.11.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops [mediatek_drm])
10848 06:55:20.469481 <6>[ 9.040844] mediatek-drm mediatek-drm.11.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops [mediatek_drm])
10849 06:55:20.479423 Starting network<6>[ 9.051365] mediatek-drm mediatek-drm.11.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops [mediatek_drm])
10850 06:55:20.492567 : ip: RTNETLINK answers: File ex<6>[ 9.065719] mediatek-drm mediatek-drm.11.auto: bound 14010000.dsi (ops mtk_dsi_component_ops [mediatek_drm])
10851 06:55:20.503339 <6>[ 9.076585] mediatek-drm mediatek-drm.11.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops [mediatek_drm])
10852 06:55:20.516157 <6>[ 9.087107] mediatek-drm mediatek-drm.11.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops [mediatek_drm])
10853 06:55:20.516266 ists
10854 06:55:20.516357 FAIL
10855 06:55:20.525760 Star<6>[ 9.097849] mediatek-drm mediatek-drm.11.auto: Not creating crtc 1 because component 10 is disabled or missing
10856 06:55:20.532722 <6>[ 9.098555] NET: Registered PF_INET6 protocol family
10857 06:55:20.539295 <6>[ 9.110458] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.11.auto on minor 1
10858 06:55:20.545710 <6>[ 9.115301] Segment Routing with IPv6
10859 06:55:20.549370 ting dropbear ss<6>[ 9.127119] In-situ OAM (IOAM) with IPv6
10860 06:55:20.552148 hd: OK
10861 06:55:20.560260 /bin/sh: can't access tty; job control turned off
10862 06:55:20.560596 Matched prompt #10: / #
10864 06:55:20.560808 Setting prompt string to ['/ #']
10865 06:55:20.560898 end: 2.2.5.1 login-action (duration 00:00:10) [common]
10867 06:55:20.561084 end: 2.2.5 auto-login-action (duration 00:00:10) [common]
10868 06:55:20.561167 start: 2.2.6 expect-shell-connection (timeout 00:03:19) [common]
10869 06:55:20.561263 Setting prompt string to ['/ #']
10870 06:55:20.561337 Forcing a shell prompt, looking for ['/ #']
10872 06:55:20.611548 / #
10873 06:55:20.611653 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10874 06:55:20.611724 Waiting using forced prompt support (timeout 00:02:30)
10875 06:55:20.616829
10876 06:55:20.617098 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10877 06:55:20.617213 start: 2.2.7 export-device-env (timeout 00:03:19) [common]
10878 06:55:20.617363 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10879 06:55:20.617449 end: 2.2 depthcharge-retry (duration 00:01:41) [common]
10880 06:55:20.617531 end: 2 depthcharge-action (duration 00:01:41) [common]
10881 06:55:20.617618 start: 3 lava-test-retry (timeout 00:01:00) [common]
10882 06:55:20.617701 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10883 06:55:20.617773 Using namespace: common
10885 06:55:20.718099 / # #
10886 06:55:20.718223 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10887 06:55:20.722900 #
10888 06:55:20.723163 Using /lava-13580668
10890 06:55:20.823465 / # export SHELL=/bin/sh
10891 06:55:20.829269 export SHELL=/bin/sh
10893 06:55:20.929903 / # . /lava-13580668/environment
10894 06:55:20.937326 . /lava-13580668/environment
10896 06:55:21.039038 / # /lava-13580668/bin/lava-test-runner /lava-13580668/0
10897 06:55:21.039707 Test shell timeout: 10s (minimum of the action and connection timeout)
10898 06:55:21.041420 <6>[ 9.525315] Console: switching to colour frame buffer device 240x67
10899 06:55:21.041848 <6>[ 9.574385] mediatek-drm mediatek-drm.11.auto: [drm] fb0: mediatekdrmfb frame buffer device
10900 06:55:21.042209 <4>[ 9.583137] ttyS ttyS0: 1 input overrun(s)
10901 06:55:21.042552 /lava-13580668/bin/lava-test-run<6>[ 9.614625] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 1
10902 06:55:21.089610 <6>[ 9.625343] mtk-vcodec-dec 16000000.video-codec: Adding to iommu group 1
10903 06:55:21.090154
10904 06:55:21.090518 /bin/sh: /lava-13580668/bin/lava-test-run: not found
10905 06:55:21.091169 / # <6>[ 9.654139] mtk-vdec-comp 16010000.video-codec: Adding to iommu group 1
10906 06:55:21.091520 <6>[ 9.661750] mtk-vdec-comp 16025000.video-codec: Adding to iommu group 1
10907 06:55:21.261690 <6>[ 9.839645] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10908 06:55:49.387491 <6>[ 37.972108] vpu: disabling
10909 06:55:49.391569 <6>[ 37.975225] vproc2: disabling
10910 06:55:49.394178 <6>[ 37.978585] vproc1: disabling
10911 06:55:49.397506 <6>[ 37.982164] vaud18: disabling
10912 06:55:49.401967 <6>[ 37.985946] va09: disabling
10913 06:55:49.404614 <6>[ 37.989125] vsram_md: disabling
10914 06:55:49.415528 <6>[ 37.996595] pp1000_dpbrdg: disabling
10915 06:55:49.419040 <6>[ 38.000471] pp1800_dpbrdg: disabling
10916 06:55:49.422320 <6>[ 38.004345] pp3300_dpbrdg: disabling
10918 06:56:20.617990 end: 3.1 lava-test-shell (duration 00:01:00) [common]
10920 06:56:20.618176 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
10922 06:56:20.618324 end: 3 lava-test-retry (duration 00:01:00) [common]
10924 06:56:20.618534 Cleaning after the job
10925 06:56:20.618621 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13580668/tftp-deploy-jo2e459g/ramdisk
10926 06:56:20.620999 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13580668/tftp-deploy-jo2e459g/kernel
10927 06:56:20.631433 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13580668/tftp-deploy-jo2e459g/dtb
10928 06:56:20.631602 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13580668/tftp-deploy-jo2e459g/modules
10929 06:56:20.637466 start: 4.1 power-off (timeout 00:00:30) [common]
10930 06:56:20.637676 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
10931 06:56:20.713254 >> Command sent successfully.
10932 06:56:20.715596 Returned 0 in 0 seconds
10933 06:56:20.815985 end: 4.1 power-off (duration 00:00:00) [common]
10935 06:56:20.816311 start: 4.2 read-feedback (timeout 00:10:00) [common]
10936 06:56:20.816576 Listened to connection for namespace 'common' for up to 1s
10937 06:56:21.817279 Finalising connection for namespace 'common'
10938 06:56:21.817467 Disconnecting from shell: Finalise
10939 06:56:21.917799 end: 4.2 read-feedback (duration 00:00:01) [common]
10940 06:56:21.918010 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13580668
10941 06:56:21.967979 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13580668
10942 06:56:21.968222 TestError: A test failed to run, look at the error message.