Boot log: hip07-d05
- Kernel Errors: 0
- Boot result: FAIL
- Errors: 2
- Kernel Warnings: 0
- Warnings: 2
1 03:41:00.186373 Action timeout for pdu-reboot exceeds Job timeout
2 03:41:00.327801 lava-dispatcher, installed at version: 2022.11
3 03:41:00.328106 start: 0 validate
4 03:41:00.328605 Start time: 2023-01-19 03:41:00.328579+00:00 (UTC)
5 03:41:00.329034 Using caching service: 'http://localhost/cache/?uri=%s'
6 03:41:00.329444 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230114.0%2Farm64%2Frootfs.cpio.gz exists
7 03:41:00.646519 Using caching service: 'http://localhost/cache/?uri=%s'
8 03:41:00.647015 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv4.19.269-cip88-rt28-rebase%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
9 03:41:00.938275 Using caching service: 'http://localhost/cache/?uri=%s'
10 03:41:00.938953 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv4.19.269-cip88-rt28-rebase%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fhisilicon%2Fhip07-d05.dtb exists
11 03:41:01.231762 Using caching service: 'http://localhost/cache/?uri=%s'
12 03:41:01.232574 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv4.19.269-cip88-rt28-rebase%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
13 03:41:01.531192 validate duration: 1.20
15 03:41:01.532710 start: 1 tftp-deploy (timeout 00:10:00) [common]
16 03:41:01.533375 start: 1.1 download-retry (timeout 00:10:00) [common]
17 03:41:01.533975 start: 1.1.1 http-download (timeout 00:10:00) [common]
18 03:41:01.534648 Not decompressing ramdisk as can be used compressed.
19 03:41:01.535197 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230114.0/arm64/rootfs.cpio.gz
20 03:41:01.535666 saving as /var/lib/lava/dispatcher/tmp/8789805/tftp-deploy-qsd8wqq8/ramdisk/rootfs.cpio.gz
21 03:41:01.536190 total size: 8180135 (7MB)
22 03:41:01.539344 progress 0% (0MB)
23 03:41:01.559944 progress 5% (0MB)
24 03:41:01.591851 progress 10% (0MB)
25 03:41:01.601318 progress 15% (1MB)
26 03:41:01.608106 progress 20% (1MB)
27 03:41:01.614334 progress 25% (1MB)
28 03:41:01.620364 progress 30% (2MB)
29 03:41:01.626882 progress 35% (2MB)
30 03:41:01.632731 progress 40% (3MB)
31 03:41:01.639670 progress 45% (3MB)
32 03:41:01.648772 progress 50% (3MB)
33 03:41:01.656251 progress 55% (4MB)
34 03:41:01.661908 progress 60% (4MB)
35 03:41:01.667974 progress 65% (5MB)
36 03:41:01.673670 progress 70% (5MB)
37 03:41:01.679640 progress 75% (5MB)
38 03:41:01.685398 progress 80% (6MB)
39 03:41:01.691591 progress 85% (6MB)
40 03:41:01.697249 progress 90% (7MB)
41 03:41:01.703293 progress 95% (7MB)
42 03:41:01.708975 progress 100% (7MB)
43 03:41:01.709734 7MB downloaded in 0.17s (44.95MB/s)
44 03:41:01.710224 end: 1.1.1 http-download (duration 00:00:00) [common]
46 03:41:01.711054 end: 1.1 download-retry (duration 00:00:00) [common]
47 03:41:01.711390 start: 1.2 download-retry (timeout 00:10:00) [common]
48 03:41:01.711727 start: 1.2.1 http-download (timeout 00:10:00) [common]
49 03:41:01.712139 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v4.19.269-cip88-rt28-rebase/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
50 03:41:01.712367 saving as /var/lib/lava/dispatcher/tmp/8789805/tftp-deploy-qsd8wqq8/kernel/Image
51 03:41:01.712715 total size: 20867584 (19MB)
52 03:41:01.712984 No compression specified
53 03:41:01.716370 progress 0% (0MB)
54 03:41:01.766414 progress 5% (1MB)
55 03:41:01.781914 progress 10% (2MB)
56 03:41:01.797041 progress 15% (3MB)
57 03:41:01.811836 progress 20% (4MB)
58 03:41:01.826697 progress 25% (5MB)
59 03:41:01.841506 progress 30% (6MB)
60 03:41:01.855827 progress 35% (6MB)
61 03:41:01.870505 progress 40% (7MB)
62 03:41:01.885337 progress 45% (8MB)
63 03:41:01.900145 progress 50% (9MB)
64 03:41:01.914954 progress 55% (10MB)
65 03:41:01.929633 progress 60% (11MB)
66 03:41:01.944190 progress 65% (12MB)
67 03:41:01.960189 progress 70% (13MB)
68 03:41:01.975090 progress 75% (14MB)
69 03:41:01.989958 progress 80% (15MB)
70 03:41:02.004502 progress 85% (16MB)
71 03:41:02.018884 progress 90% (17MB)
72 03:41:02.032953 progress 95% (18MB)
73 03:41:02.047537 progress 100% (19MB)
74 03:41:02.048353 19MB downloaded in 0.34s (59.30MB/s)
75 03:41:02.048899 end: 1.2.1 http-download (duration 00:00:00) [common]
77 03:41:02.049707 end: 1.2 download-retry (duration 00:00:00) [common]
78 03:41:02.050035 start: 1.3 download-retry (timeout 00:09:59) [common]
79 03:41:02.050365 start: 1.3.1 http-download (timeout 00:09:59) [common]
80 03:41:02.050834 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v4.19.269-cip88-rt28-rebase/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/hisilicon/hip07-d05.dtb
81 03:41:02.051061 saving as /var/lib/lava/dispatcher/tmp/8789805/tftp-deploy-qsd8wqq8/dtb/hip07-d05.dtb
82 03:41:02.051328 total size: 34901 (0MB)
83 03:41:02.051591 No compression specified
84 03:41:02.054745 progress 93% (0MB)
85 03:41:02.055492 progress 100% (0MB)
86 03:41:02.055979 0MB downloaded in 0.00s (7.17MB/s)
87 03:41:02.056398 end: 1.3.1 http-download (duration 00:00:00) [common]
89 03:41:02.057242 end: 1.3 download-retry (duration 00:00:00) [common]
90 03:41:02.057562 start: 1.4 download-retry (timeout 00:09:59) [common]
91 03:41:02.057886 start: 1.4.1 http-download (timeout 00:09:59) [common]
92 03:41:02.058276 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v4.19.269-cip88-rt28-rebase/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
93 03:41:02.058495 saving as /var/lib/lava/dispatcher/tmp/8789805/tftp-deploy-qsd8wqq8/modules/modules.tar
94 03:41:02.058762 total size: 4214720 (4MB)
95 03:41:02.059027 Using unxz to decompress xz
96 03:41:02.067406 progress 0% (0MB)
97 03:41:02.084494 progress 5% (0MB)
98 03:41:02.106152 progress 10% (0MB)
99 03:41:02.134758 progress 15% (0MB)
100 03:41:02.164768 progress 20% (0MB)
101 03:41:02.195501 progress 25% (1MB)
102 03:41:02.218566 progress 30% (1MB)
103 03:41:02.246937 progress 35% (1MB)
104 03:41:02.269969 progress 40% (1MB)
105 03:41:02.293151 progress 45% (1MB)
106 03:41:02.321976 progress 50% (2MB)
107 03:41:02.346931 progress 55% (2MB)
108 03:41:02.375320 progress 60% (2MB)
109 03:41:02.398825 progress 65% (2MB)
110 03:41:02.423923 progress 70% (2MB)
111 03:41:02.445598 progress 75% (3MB)
112 03:41:02.468263 progress 80% (3MB)
113 03:41:02.494509 progress 85% (3MB)
114 03:41:02.514222 progress 90% (3MB)
115 03:41:02.543613 progress 95% (3MB)
116 03:41:02.567125 progress 100% (4MB)
117 03:41:02.578562 4MB downloaded in 0.52s (7.73MB/s)
118 03:41:02.579352 end: 1.4.1 http-download (duration 00:00:01) [common]
120 03:41:02.580253 end: 1.4 download-retry (duration 00:00:01) [common]
121 03:41:02.580734 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
122 03:41:02.581095 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
123 03:41:02.581426 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
124 03:41:02.581833 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
125 03:41:02.582546 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o
126 03:41:02.582994 makedir: /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin
127 03:41:02.583357 makedir: /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/tests
128 03:41:02.583712 makedir: /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/results
129 03:41:02.584094 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-add-keys
130 03:41:02.584664 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-add-sources
131 03:41:02.585166 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-background-process-start
132 03:41:02.585649 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-background-process-stop
133 03:41:02.586120 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-common-functions
134 03:41:02.586588 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-echo-ipv4
135 03:41:02.587063 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-install-packages
136 03:41:02.587542 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-installed-packages
137 03:41:02.588009 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-os-build
138 03:41:02.588479 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-probe-channel
139 03:41:02.589040 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-probe-ip
140 03:41:02.589514 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-target-ip
141 03:41:02.589988 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-target-mac
142 03:41:02.590465 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-target-storage
143 03:41:02.590957 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-test-case
144 03:41:02.591433 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-test-event
145 03:41:02.591906 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-test-feedback
146 03:41:02.592384 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-test-raise
147 03:41:02.592911 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-test-reference
148 03:41:02.593390 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-test-runner
149 03:41:02.593865 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-test-set
150 03:41:02.594336 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-test-shell
151 03:41:02.594831 Updating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-install-packages (oe)
152 03:41:02.595333 Updating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/bin/lava-installed-packages (oe)
153 03:41:02.595758 Creating /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/environment
154 03:41:02.596113 LAVA metadata
155 03:41:02.596365 - LAVA_JOB_ID=8789805
156 03:41:02.596679 - LAVA_DISPATCHER_IP=192.168.101.1
157 03:41:02.597155 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
158 03:41:02.597371 skipped lava-vland-overlay
159 03:41:02.597719 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
160 03:41:02.598067 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
161 03:41:02.598306 skipped lava-multinode-overlay
162 03:41:02.598670 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
163 03:41:02.599044 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
164 03:41:02.599327 Loading test definitions
165 03:41:02.599722 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
166 03:41:02.599986 Using /lava-8789805 at stage 0
167 03:41:02.601141 uuid=8789805_1.5.2.3.1 testdef=None
168 03:41:02.601549 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
169 03:41:02.601929 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
170 03:41:02.603651 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
172 03:41:02.604439 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
173 03:41:02.606452 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
175 03:41:02.607263 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
176 03:41:02.609174 runner path: /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/0/tests/0_dmesg test_uuid 8789805_1.5.2.3.1
177 03:41:02.609719 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
179 03:41:02.610509 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
180 03:41:02.610769 Using /lava-8789805 at stage 1
181 03:41:02.611766 uuid=8789805_1.5.2.3.5 testdef=None
182 03:41:02.612079 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
183 03:41:02.612408 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
184 03:41:02.614000 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
186 03:41:02.614780 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
187 03:41:02.616735 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
189 03:41:02.617526 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
190 03:41:02.619460 runner path: /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/1/tests/1_bootrr test_uuid 8789805_1.5.2.3.5
191 03:41:02.619977 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
193 03:41:02.620707 Creating lava-test-runner.conf files
194 03:41:02.620992 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/0 for stage 0
195 03:41:02.621407 - 0_dmesg
196 03:41:02.621753 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/8789805/lava-overlay-y0snk97o/lava-8789805/1 for stage 1
197 03:41:02.622122 - 1_bootrr
198 03:41:02.622501 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
199 03:41:02.622828 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
200 03:41:02.651828 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
201 03:41:02.652172 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
202 03:41:02.652503 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
203 03:41:02.652877 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
204 03:41:02.653220 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
205 03:41:03.237854 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
206 03:41:03.238915 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
207 03:41:03.239323 extracting modules file /var/lib/lava/dispatcher/tmp/8789805/tftp-deploy-qsd8wqq8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/8789805/extract-overlay-ramdisk-_1c92ae_/ramdisk
208 03:41:03.656180 end: 1.5.4 extract-modules (duration 00:00:00) [common]
209 03:41:03.656606 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
210 03:41:03.656879 [common] Applying overlay /var/lib/lava/dispatcher/tmp/8789805/compress-overlay-1btixgo0/overlay-1.5.2.4.tar.gz to ramdisk
211 03:41:03.657115 [common] Applying overlay /var/lib/lava/dispatcher/tmp/8789805/compress-overlay-1btixgo0/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/8789805/extract-overlay-ramdisk-_1c92ae_/ramdisk
212 03:41:03.683677 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
213 03:41:03.684040 start: 1.5.6 prepare-kernel (timeout 00:09:58) [common]
214 03:41:03.684369 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
215 03:41:03.684774 start: 1.5.7 configure-preseed-file (timeout 00:09:58) [common]
216 03:41:03.685100 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
217 03:41:03.685443 start: 1.5.8 compress-ramdisk (timeout 00:09:58) [common]
218 03:41:03.685722 Building ramdisk /var/lib/lava/dispatcher/tmp/8789805/extract-overlay-ramdisk-_1c92ae_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/8789805/extract-overlay-ramdisk-_1c92ae_/ramdisk
219 03:41:04.341954 >> 89240 blocks
220 03:41:06.896145 rename /var/lib/lava/dispatcher/tmp/8789805/extract-overlay-ramdisk-_1c92ae_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/8789805/tftp-deploy-qsd8wqq8/ramdisk/ramdisk.cpio.gz
221 03:41:06.897299 end: 1.5.8 compress-ramdisk (duration 00:00:03) [common]
222 03:41:06.897725 end: 1.5 prepare-tftp-overlay (duration 00:00:04) [common]
223 03:41:06.898052 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:55) [common]
224 03:41:06.898283 No LXC device requested
225 03:41:06.898569 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
226 03:41:06.898829 start: 1.7 deploy-device-env (timeout 00:09:55) [common]
227 03:41:06.899091 end: 1.7 deploy-device-env (duration 00:00:00) [common]
228 03:41:06.899295 Checking files for TFTP limit of 4294967296 bytes.
229 03:41:06.900943 end: 1 tftp-deploy (duration 00:00:05) [common]
230 03:41:06.901225 start: 2 grub-main-action (timeout 00:05:00) [common]
231 03:41:06.901519 start: 2.1 bootloader-from-media (timeout 00:05:00) [common]
232 03:41:06.901780 end: 2.1 bootloader-from-media (duration 00:00:00) [common]
233 03:41:06.902098 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
234 03:41:06.902437 substitutions:
235 03:41:06.902662 - {DTB}: 8789805/tftp-deploy-qsd8wqq8/dtb/hip07-d05.dtb
236 03:41:06.902845 - {INITRD}: 8789805/tftp-deploy-qsd8wqq8/ramdisk/ramdisk.cpio.gz
237 03:41:06.903054 - {KERNEL}: 8789805/tftp-deploy-qsd8wqq8/kernel/Image
238 03:41:06.903223 - {LAVA_MAC}: None
239 03:41:06.903391 - {PRESEED_CONFIG}: None
240 03:41:06.903556 - {PRESEED_LOCAL}: None
241 03:41:06.903764 - {RAMDISK}: 8789805/tftp-deploy-qsd8wqq8/ramdisk/ramdisk.cpio.gz
242 03:41:06.903929 - {ROOT_PART}: None
243 03:41:06.904092 - {ROOT}: None
244 03:41:06.904253 - {SERVER_IP}: 192.168.101.1
245 03:41:06.904606 - {TEE}: None
246 03:41:06.904823 Parsed boot commands:
247 03:41:06.904982 - linux (tftp,192.168.101.1)/8789805/tftp-deploy-qsd8wqq8/kernel/Image pcie_aspm=off pci=pcie_bus_perf root=/dev/ram0 ip=:::::eth0:dhcp
248 03:41:06.905195 - devicetree (tftp,192.168.101.1)/8789805/tftp-deploy-qsd8wqq8/dtb/hip07-d05.dtb
249 03:41:06.905359 - initrd (tftp,192.168.101.1)/8789805/tftp-deploy-qsd8wqq8/ramdisk/ramdisk.cpio.gz
250 03:41:06.905549 - boot
251 03:41:06.905774 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
252 03:41:06.906036 start: 2.3 connect-device (timeout 00:05:00) [common]
253 03:41:06.906234 [common] connect-device Connecting to device using '/usr/local/bin/d05-console.sh hip07-d05-cbg-0-bmc'
254 03:41:06.912349 Setting prompt string to ['lava-test: # ']
255 03:41:06.913148 end: 2.3 connect-device (duration 00:00:00) [common]
256 03:41:06.913466 start: 2.4 reset-device (timeout 00:05:00) [common]
257 03:41:06.913763 start: 2.4.1 pdu-reboot (timeout 00:05:00) [common]
258 03:41:06.914212 Calling: 'nice' '/usr/local/bin/d05-power.sh' 'hip07-d05-cbg-0-bmc' 'reset'
259 03:41:07.256445 >> Chassis Power Control: Down/Off
260 03:41:17.575640 >> Chassis Power Control: Up/On
261 03:41:27.579273 Returned 0 in 20 seconds
262 03:41:27.680760 end: 2.4.1 pdu-reboot (duration 00:00:21) [common]
264 03:41:27.681647 end: 2.4 reset-device (duration 00:00:21) [common]
265 03:41:27.681950 start: 2.5 bootloader-interrupt (timeout 00:04:39) [common]
266 03:41:27.682215 Setting prompt string to ['PCIE MEM CONFIG']
267 03:41:27.682429 bootloader-interrupt: Wait for prompt ['PCIE MEM CONFIG'] (timeout 00:05:00)
268 03:41:27.683162 Info: SOL payload already de-activated
269 03:41:27.683357 Never mind
270 03:41:27.683559 [SOL Session operational. Use ~? for help]
271 03:41:27.683764 [serdes_init]:SerDes0 init success!
272 03:41:27.683945 [serdes_hilink1_init]:hilink1_mode hccs0 8 lane 5G
273 03:41:29.445958 [serdes_cs_hw_calibration_optionV2_exec]:Macro1 CS1 LC Vco Cal done!(LCVCOCALDONE) in 0ms
274 03:41:29.446649 [SerdesCsCalib]:Macro1 CS1 PLL lock success!(0 ms)
275 03:41:31.776826 [serdes_init]:SerDes1 init success!
276 03:41:31.895831 Continue to dreset PCS
277 03:41:31.896362 Continue to dreset HLLC
278 03:41:32.866158 Continue to open PCS RX
279 03:41:32.866505 Wait for HLLC Training........OK
280 03:41:32.866702 Wait for HLLC1 Training........OK
281 03:41:32.895700 Wait for S1 HLLC Training........OK
282 03:41:32.895939 Wait for S1 HLLC1 Training........OK
283 03:41:32.896134 Open Secondary socket Window
284 03:41:32.896324 Djtag secondary 0x4004001d818 and 0x400d000d818 init
285 03:41:33.907034 Macro 0 Download Firmware Success!!
286 03:41:34.845529 Macro 1 Download Firmware Success!!
287 03:41:35.825655 Macro 0 Download Firmware Success!!
288 03:41:36.708567 Macro 1 Download Firmware Success!!
289 03:41:36.727463 [serdes_hilink0_init]:hilink0_mode hccs1 8 lane 16 bit
290 03:41:36.727760 Halt Macro 0 MCU!!
291 03:41:36.728031 Release Macro 0 MCU!!
292 03:41:36.785565 Temperature: 28 (0x1C)
293 03:41:36.885778 [serdes_init]:SerDes0 init success!
294 03:41:36.886194 [serdes_hilink1_init]:hilink1_mode hccs0 8 lane 16 bit
295 03:41:36.886391 Halt Macro 1 MCU!!
296 03:41:36.886579 Release Macro 1 MCU!!
297 03:41:36.945417 Temperature: 28 (0x1C)
298 03:41:37.056315 [serdes_init]:SerDes1 init success!
299 03:41:37.057212 [serdes_hilink0_init]:hilink0_mode hccs1 8 lane 16 bit
300 03:41:37.236133 Halt Macro 0 MCU!!
301 03:41:37.503380 Release Macro 0 MCU!!
302 03:41:39.198215 Temperature: 27 (0x1B)
303 03:41:39.855819 [serdes_init]:SerDes0 init success!
304 03:41:39.856279 [serdes_hilink1_init]:hilink1_mode hccs0 8 lane 16 bit
305 03:41:40.035670 Halt Macro 1 MCU!!
306 03:41:40.317905 Release Macro 1 MCU!!
307 03:41:41.955560 Temperature: 27 (0x1B)
308 03:41:42.697563 [serdes_init]:SerDes1 init success!
309 03:41:42.738127 Continue to dreset PCS
310 03:41:42.738585 Continue to dreset HLLC
311 03:41:42.738893 Continue to Enable CTLE
312 03:41:44.005605 Continue to open PCS RX
313 03:41:44.005986 Wait for HLLC Training........OK
314 03:41:44.006219 Wait for HLLC1 Training........OK
315 03:41:44.006451 Wait for S1 HLLC Training........OK
316 03:41:44.006680 Wait for S1 HLLC1 Training........OK
317 03:41:44.006912 S0 HLLC0 Interrupt status(0x4) = 0x0
318 03:41:44.007121 S0 HLLC1 Interrupt status(0x4) = 0x0
319 03:41:44.025649 S1 HLLC0 Interrupt status(0x4) = 0x0
320 03:41:44.025949 S1 HLLC1 Interrupt status(0x4) = 0x0
321 03:41:44.026222
322 03:41:44.026444 Config Secondary socket
323 03:41:44.026672 Open Secondary socket Window
324 03:41:44.026889 close NB CS2 to PA
325 03:41:44.027107 Config socket0 NA PA
326 03:41:44.027343 Enable socket0 PA 2+2 Mode
327 03:41:44.027559 Config Secondary socket PA
328 03:41:44.055621 clean S0 remap for PA....Done
329 03:41:44.055908 clean remap for PA....Done
330 03:41:44.056135 Enable socket1 PA 2+2 Mode
331 03:41:44.056357 Djtag Secondary 0x4006001d818 Init
332 03:41:44.056643 S1 Preinit
333 03:41:44.057326 S1 Preinit End
334 03:41:44.057803 Config Secondary socket AA&LLC
335 03:41:44.075509 close S1 NB CS2 to PA
336 03:41:44.075814 OK1OK2OK3Djtag Secondary 0x408d000d818 Init
337 03:41:44.076080 Visit S1 NB
338 03:41:44.076662 Visit S1 NB DONE
339 03:41:44.095634 S1 NA PCIE clean remap.........Done
340 03:41:44.096026 S1 NA PCIE MEM CONFIG.........Done
341 03:41:44.096282 S1 NB PCIE clean remap.........Done
342 03:41:44.096604 S1 NB PCIE MEM CONFIG.........Done
343 03:41:44.096887 NB/TB PLL Init
344 03:41:44.097139 TB PLL init....OK
345 03:41:44.097383 NB PLL init....OK
346 03:41:44.097642 [LPC] S1 MBIGEN CONFIG Done
347 03:41:44.149279 end: 2.5 bootloader-interrupt (duration 00:00:16) [common]
348 03:41:44.149695 start: 2.6 bootloader-commands (timeout 00:04:23) [common]
349 03:41:44.150003 Setting prompt string to ['grub>']
350 03:41:44.150279 bootloader-commands: Wait for prompt ['grub>'] (timeout 00:04:23)
351 03:41:44.150834 cadd-symbol-file /home/s00296804/Edk2/Build/D05Source/RELEASE_GCC49/AARCH64/HwPkg/Override/ArmPlatformPkg/Sec/Sec/DEBUG/ArmPlatformSec.dll 0xA4801800
352 03:41:44.151108 Trust Zone Configuration is disabled
353 03:41:44.151321
354 03:41:45.466728
355 03:41:45.467246 Boot firmware (version Hisilicon D05 UEFI 16.12 Release built at 05/15/2017 07:53)
356 03:41:45.467648
357 03:41:45.467944 init BMC.
358 03:41:45.505564 TempVer:0x20
359 03:41:45.505944 GetDeviceId return Success
360 03:41:45.506306 GetVariable Not Found!
361 03:41:45.506676 Get Default Setup Configration
362 03:41:45.507017 &&&Now config iBMC BIOS WDT [action:0 countdown:3928 timeruse 2!
363 03:41:45.675599 Memory Init PEIM Loaded
364 03:41:45.696905 GetVariable Not Found!
365 03:41:45.697579 Get Default Setup Configration
366 03:41:45.697868 -------------------
367 03:41:45.698165 Start RegisterTest:
368 03:41:45.698470 RegisterTest OK!
369 03:41:45.698734 -------------------
370 03:41:45.699052 socket[0] Totem B I2C0 init ok.
371 03:41:45.699342 socket[0] Totem B I2C1 init ok.
372 03:41:45.700244 socket[1] Totem B I2C0 init ok.
373 03:41:45.720473 socket[1] Totem B I2C1 init ok.
374 03:41:45.720845
375 03:41:45.721137 socket[0] channel[0] dimm[0] read from SPD, I2C Port:1 SlaveAddr:0x54
376 03:41:45.721418 ---------------------------------------------------------------------
377 03:41:45.721737 SPD_KEY_BYTE : DDR4
378 03:41:45.775744 SPD_KEY_BYTE2 AX_TCK_DDR4 : 0xD
379 03:41:45.776132 SPD_FTB_MIN_TCK_DDR4 : 0xD6
380 03:41:45.776401 DimmMaxFreq : 2401Mbps
381 03:41:45.777045 pGblData->Channel[0][0].Dimm[0].DramWidth : X4
382 03:41:45.788052 pGblData->Channel[0][0].Dimm[0].RankNum : 2
383 03:41:45.788400 pGblData->Channel[0][0].Dimm[0].ddrFreq : 2400Mbps
384 03:41:45.788876 pGblData->Channel[0][0].Dimm[0].minTck : 8330
385 03:41:45.789164 ---------------------------------------------------------------------
386 03:41:45.789418
387 03:41:45.865535 socket[0] channel[0] dimm[1] read from SPD, I2C Port:1 SlaveAddr:0x55
388 03:41:45.865892 ---------------------------------------------------------------------
389 03:41:45.876072 SPD_KEY_BYTE : Empty
390 03:41:45.876332 Socket[0] Channel[0] Dimm[1] is empty.
391 03:41:45.876657 ---------------------------------------------------------------------
392 03:41:45.876990 pGblData->Channel[0][0].RankPresent : 0x3
393 03:41:45.877278
394 03:41:45.877509
395 03:41:45.889498 socket[0] channel[1] dimm[0] read from SPD, I2C Port:0 SlaveAddr:0x54
396 03:41:45.889753 ---------------------------------------------------------------------
397 03:41:45.890013 SPD_KEY_BYTE : DDR4
398 03:41:45.890267 SPD_KEY_BYTE2 : RDIMM
399 03:41:45.905632 SPD_MODULE_ORG_DDR4 : 0x8
400 03:41:45.905978 SPD_MIN_TCK_DDR4 : 0x7
401 03:41:45.906242 SPD_MAX_TCK_DDR4 : 0xD
402 03:41:45.906480 SPD_FTB_MIN_TCK_DDR4 : 0xD6
403 03:41:45.906760 DimmMaxFreq : 2401Mbps
404 03:41:45.915667 pGblData->Channel[0][1].Dimm[0].DramWidth : X4
405 03:41:45.915969 pGblData->Channel[0][1].Dimm[0].RankNum : 2
406 03:41:45.916255 pGblData->Channel[0][1].Dimm[0].ddrFreq : 2400Mbps
407 03:41:45.916915 pGblData->Channel[0][1].Dimm[0].minTck : 8330
408 03:41:45.933076 ---------------------------------------------------------------------
409 03:41:45.933452
410 03:41:45.933791 socket[0] channel[1] dimm[1] read from SPD, I2C Port:0 SlaveAddr:0x55
411 03:41:45.934253 ---------------------------------------------------------------------
412 03:41:45.967434 SPD_KEY_BYTE : Empty
413 03:41:45.967779 Socket[0] Channel[1] Dimm[1] is empty.
414 03:41:45.985657 ---------------------------------------------------------------------
415 03:41:45.985972 pGblData->Channel[0][1].RankPresent : 0x3
416 03:41:45.986270
417 03:41:45.986589
418 03:41:45.986844 socket[0] channel[2] dimm[0] read from SPD, I2C Port:1 SlaveAddr:0x50
419 03:41:45.987126 ---------------------------------------------------------------------
420 03:41:45.995903 SPD_KEY_BYTE : DDR4
421 03:41:45.996242 SPD_KEY_BYTE2 : RDIMM
422 03:41:45.996588 SPD_MODULE_ORG_DDR4 : 0x8
423 03:41:45.996929 SPD_MIN_TCK_DDR4 : 0x7
424 03:41:45.997211 SPD_MAX_TCK_DDR4 : 0xD
425 03:41:46.010421 SPD_FTB_MIN_TCK_DDR4 : 0xD6
426 03:41:46.010753 DimmMaxFreq : 2401Mbps
427 03:41:46.011062 pGblData->Channel[0][2].Dimm[0].DramWidth : X4
428 03:41:46.011342 pGblData->Channel[0][2].Dimm[0].RankNum : 2
429 03:41:46.068940 pGblData->Channel[0][2].Dimm[0].ddrFreq : 2400Mbps
430 03:41:46.069571 pGblData->Channel[0][2].Dimm[0].minTck : 8330
431 03:41:46.085692 ---------------------------------------------------------------------
432 03:41:46.085994
433 03:41:46.086304 socket[0] channel[2] dimm[1] read from SPD, I2C Port:1 SlaveAddr:0x51
434 03:41:46.086611 ---------------------------------------------------------------------
435 03:41:46.086884 SPD_KEY_BYTE : Empty
436 03:41:46.087128 Socket[0] Channel[2] Dimm[1] is empty.
437 03:41:46.096807 ---------------------------------------------------------------------
438 03:41:46.097102 pGblData->Channel[0][2].RankPresent : 0x3
439 03:41:46.097309
440 03:41:46.097596
441 03:41:46.105828 socket[0] channel[3] dimm[0] read from SPD, I2C Port:0 SlaveAddr:0x50
442 03:41:46.106164 ---------------------------------------------------------------------
443 03:41:46.106425 SPD_KEY_BYTE : DDR4
444 03:41:46.106964 SPD_KEY_BYTE2 : RDIMM
445 03:41:46.126850 SPD_MODULE_ORG_DDR4 : 0x8
446 03:41:46.127134 SPD_MIN_TCK_DDR4 : 0x7
447 03:41:46.127411 SPD_MAX_TCK_DDR4 : 0xD
448 03:41:46.127736 SPD_FTB_MIN_TCK_DDR4 : 0xD6
449 03:41:46.127990 DimmMaxFreq : 2401Mbps
450 03:41:46.145880 pGblData->Channel[0][3].Dimm[0].DramWidth : X4
451 03:41:46.146159 pGblData->Channel[0][3].Dimm[0].RankNum : 2
452 03:41:46.146403 pGblData->Channel[0][3].Dimm[0].ddrFreq : 2400Mbps
453 03:41:46.146672 pGblData->Channel[0][3].Dimm[0].minTck : 8330
454 03:41:46.165875 ---------------------------------------------------------------------
455 03:41:46.166201
456 03:41:46.166508 socket[0] channel[3] dimm[1] read from SPD, I2C Port:0 SlaveAddr:0x51
457 03:41:46.166789 ---------------------------------------------------------------------
458 03:41:46.207601 SPD_KEY_BYTE : Empty
459 03:41:46.207957 Socket[0] Channel[3] Dimm[1] is empty.
460 03:41:46.208260 ---------------------------------------------------------------------
461 03:41:46.208583 pGblData->Channel[0][3].RankPresent : 0x3
462 03:41:46.208871
463 03:41:46.209175
464 03:41:46.246812 socket[1] channel[0] dimm[0] re : DDR4
465 03:41:46.247180 SPD_KEY_BYTE2 : RDIMM
466 03:41:46.247429 SPD_MODULE_ORG_DDR4 : 0x8
467 03:41:46.247651 SPD_MIN_TCK_DDR4 : 0x7
468 03:41:46.247879 SPD_MAX_TCK_DDR4 : 0xD
469 03:41:46.262385 SPD_FTB_MIN_TCK_DDR4 : 0xD6
470 03:41:46.262684 DimmMaxFreq : 2401Mbps
471 03:41:46.262997 pGblData->Channel[1][0].Dimm[0].DramWidth : X4
472 03:41:46.263311 pGblData->Channel[1][0].Dimm[0].RankNum : 2
473 03:41:46.276390 pGblData->Channel[1][0].Dimm[0].ddrFreq : 2400Mbps
474 03:41:46.276725 pGblData->Channel[1][0].Dimm[0].minTck : 8330
475 03:41:46.277038 ---------------------------------------------------------------------
476 03:41:46.277305
477 03:41:46.277611 socket[1] channel[0] dimm[1] read from SPD, I2C Port:1 SlaveAddr:0x55
478 03:41:46.325609 ---------------------------------------------------------------------
479 03:41:46.326436 SPD_KEY_BYTE : Empty
480 03:41:46.326783 Socket[1] Channel[0] Dimm[1] is empty.
481 03:41:46.344814 ---------------------------------------------------------------------
482 03:41:46.345119 pGblData->Channel[1][0].RankPresent : 0x3
483 03:41:46.345437
484 03:41:46.345722
485 03:41:46.346083 socket[1] channel[1] dimm[0] read from SPD, I2C Port:0 SlaveAddr:0x54
486 03:41:46.346342 ---------------------------------------------------------------------
487 03:41:46.366353 SPD_KEY_BYTE : DDR4
488 03:41:46.366676 SPD_KEY_BYTE2 : RDIMM
489 03:41:46.366995 SPD_MODULE_ORG_DDR4 : 0x8
490 03:41:46.367299 SPD_MIN_TCK_DDR4 : 0x7
491 03:41:46.367661 SPD_MAX_TCK_DDR4 : 0xD
492 03:41:46.388675 SPD_FTB_MIN_TCK_DDR4 : 0xD6
493 03:41:46.389041 DimmMaxFreq : 2401Mbps
494 03:41:46.389317 pGblData->Channel[1][1].Dimm[0].DramWidth : X4
495 03:41:46.389616 pGblData->Channel[1][1].Dimm[0].RankNum : 2
496 03:41:46.405697 pGblData->Channel[1][1].Dimm[0].ddrFreq : 2400Mbps
497 03:41:46.406009 pGblData->Channel[1][1].Dimm[0].minTck : 8330
498 03:41:46.406277 ---------------------------------------------------------------------
499 03:41:46.406570
500 03:41:46.406853 socket[1] channel[1] dimm[1] read from SPD, I2C Port:0 SlaveAddr:0x55
501 03:41:46.449115 ---------------------------------------------------------------------
502 03:41:46.449478 SPD_KEY_BYTE : Empty
503 03:41:46.449802 Socket[1] Channel[1] Dimm[1] is empty.
504 03:41:46.471044 ---------------------------------------------------------------------
505 03:41:46.471496 pGblData->Channel[1][1].RankPresent : 0x3
506 03:41:46.471808
507 03:41:46.472085
508 03:41:46.472361 socket[1] channel[2] dimm[0] read from SPD, I2C Port:1 SlaveAddr:0x50
509 03:41:46.473113 ---------------------------------------------------------------------
510 03:41:46.492913 SPD_KEY_BYTE : DDR4
511 03:41:46.493272 SPD_KEY_BYTE2 : RDIMM
512 03:41:46.493573 SPD_MODULE_ORG_DDR4 : 0x8
513 03:41:46.493852 SPD_MIN_TCK_DDR4 : 0x7
514 03:41:46.494121 SPD_MAX_TCK_DDR4 : 0xD
515 03:41:46.514755 SPD_FTB_MIN_TCK_DDR4 : 0xD6
516 03:41:46.515191 DimmMaxFreq : 2401Mbps
517 03:41:46.515487 pGblData->Channel[1][2].Dimm[0].DramWidth : X4
518 03:41:46.515765 pGblData->Channel[1][2].Dimm[0].RankNum : 2
519 03:41:46.528423 pGblData->Channel[1][2].Dimm[0].ddrFreq : 2400Mbps
520 03:41:46.528776 pGblData->Channel[1][2].Dimm[0].minTck : 8330
521 03:41:46.528992 ---------------------------------------------------------------------
522 03:41:46.529298
523 03:41:46.529527 socket[1] channel[2] dimm[1] read from SPD, I2C Port:1 SlaveAddr:0x51
524 03:41:46.587305 ---------------------------------------------------------------------
525 03:41:46.587673 SPD_KEY_BYTE : Empty
526 03:41:46.587995 Socket[1] Channel[2] Dimm[1] is empty.
527 03:41:46.605933 ---------------------------------------------------------------------
528 03:41:46.606235 pGblData->Channel[1][2].RankPresent : 0x3
529 03:41:46.606504
530 03:41:46.607098
531 03:41:46.607369 socket[1] channel[3] dimm[0] read from SPD, I2C Port:0 SlaveAddr:0x50
532 03:41:46.607626 ---------------------------------------------------------------------
533 03:41:46.627079 SPD_KEY_BYTE : DDR4
534 03:41:46.627423 SPD_KEY_BYTE2 : RDIMM
535 03:41:46.627753 SPD_MODULE_ORG_DDR4 : 0x8
536 03:41:46.628043 SPD_MIN_TCK_DDR4 : 0x7
537 03:41:46.628348 SPD_MAX_TCK_DDR4 : 0xD
538 03:41:46.668052 SPD_[3].Dimm[0].DramWidth : X4
539 03:41:46.668422 pGblData->Channel[1][3].Dimm[0].RankNum : 2
540 03:41:46.668926 pGblData->Channel[1][3].Dimm[0].ddrFreq : 2400Mbps
541 03:41:46.669260 pGblData->Channel[1][3].Dimm[0].minTck : 8330
542 03:41:46.724178 ---------------------------------------------------------------------
543 03:41:46.724494
544 03:41:46.725021 socket[1] channel[3] dimm[1] read from SPD, I2C Port:0 SlaveAddr:0x51
545 03:41:46.725319 ---------------------------------------------------------------------
546 03:41:46.737516 SPD_KEY_BYTE : Empty
547 03:41:46.737860 Socket[1] Channel[3] Dimm[1] is empty.
548 03:41:46.738143 ---------------------------------------------------------------------
549 03:41:46.738460 pGblData->Channel[1][3].RankPresent : 0x3
550 03:41:46.738721
551 03:41:46.755731 DimmMaxFreq : 2401Mbps
552 03:41:46.756091 GblData->Freq : 2400
553 03:41:46.756469 GblData->Tck : 8333
554 03:41:46.756896 GblData->DdrFreqIdx : 13
555 03:41:46.757169 Check dimm status ok!
556 03:41:46.757448 pGblData->MaxSPCNum = 2
557 03:41:46.757705 skt[0] ch[0] maxPORFreqIdx = 13
558 03:41:46.758038 skt[0] ch[1] maxPORFreqIdx = 13
559 03:41:46.767720 skt[0] ch[2] maxPORFreqIdx = 13
560 03:41:46.768020 skt[0] ch[3] maxPORFreqIdx = 13
561 03:41:46.768297 skt[1] ch[0] maxPORFreqIdx = 13
562 03:41:46.769013 skt[1] ch[1] maxPORFreqIdx = 13
563 03:41:46.769289 skt[1] ch[2] maxPORFreqIdx = 13
564 03:41:46.769594 skt[1] ch[3] maxPORFreqIdx = 13
565 03:41:46.769868 ---------------------------------------------------------------------
566 03:41:46.785707 ---------------------------------------------------------------------
567 03:41:46.786058 PORFreqTable result(max system ddr frequency):
568 03:41:46.786357 pGblData->DdrFreqIdx = 13
569 03:41:46.786642 pGblData->DevParaFreqIdx = 13
570 03:41:46.786910 pGblData->Tck = 8333
571 03:41:46.787164 pGblData->Freq = 2400
572 03:41:46.800540 ---------------------------------------------------------------------
573 03:41:46.800915 ---------------------------------------------------------------------
574 03:41:46.801204 Set ddr frequency ok!
575 03:41:46.801532 Get dimm spd information
576 03:41:46.801807
577 03:41:46.866911 socket[0] channel[0] dimm[0] i2c port[1] slaveAddr[0x54] SPD information:
578 03:41:47.513566 SPD_MIN_TRCD_DDR4: 0x6E
579 03:41:47.514473 SPD_FTB_TRCD_DDR4: 0x0
580 03:41:47.514752 SPD_MIN_TRRDL_DDR4: 0x28
581 03:41:47.515059 SPD_FTB_TRRDL_DDR4: 0x9C
582 03:41:47.515529 SPD_MIN_TRRDS_DDR4: 0x1B
583 03:41:47.515773 SPD_FTB_TRRDS_DDR4: 0xB5
584 03:41:47.516036 SPD_EXT_TRC_TRAS_DDR4: 0x11
585 03:41:47.516299 SPD_MIN_TRAS_DDR4: 0x0
586 03:41:47.516625 SPD_MIN_TRC_DDR4: 0x6E
587 03:41:47.516945 SPD_FTB_TRC_DDR4: 0x0
588 03:41:47.535742
589 03:41:47.536056 SPD_MIN_TRFC1_MSB_DDR4: 0xA
590 03:41:47.536331 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
591 03:41:47.536637 tRFC: 0xAF0
592 03:41:47.536964 tempCkNum: 0x55730
593 03:41:47.537234 SPD_MIN_TAA_DDR4: 0x6E
594 03:41:47.537539 SPD_FTB_TAA: 0x0
595 03:41:47.537834 SPD_TFAW_UPPER_DDR4: 0x0
596 03:41:47.538092 SPD_MIN_TFAW_DDR4: 0x68
597 03:41:47.538349 SPD_MIN_TRP_DDR4: 0x6E
598 03:41:47.538627 SPD_FTB_TRP_DDR4: 0x0
599 03:41:47.558059 SPD_MIN_TCCDL_DDR4: 0x28
600 03:41:47.558339 SPD_FTB_TCCDL_DDR4: 0x0
601 03:41:47.558619 ---------------------------------------------------------------------
602 03:41:47.558874 pGblData item skt ch dimm value
603 03:41:47.559139 ---------------------------------------------------------------------
604 03:41:47.579126 SDRAMCapacity 0 0 0 0x5
605 03:41:47.579428 BGNum 0 0 0 4
606 03:41:47.579708 BankNum 0 0 0 16
607 03:41:47.579973 ColBits 0 0 0 10
608 03:41:47.580248 RowBits 0 0 0 17
609 03:41:47.605805 SpdMirror 0 0 0 1
610 03:41:47.606129 SpdVdd 0 0 0 3
611 03:41:47.606397 PrimaryBusWidth 0 0 0 64
612 03:41:47.606680 ExtensionBusWidth 0 0 0 8
613 03:41:47.622887 RankSize 0 0 0 16384
614 03:41:47.623241 SpdRMId 0 0 0 0x3206
615 03:41:47.623512 SpdMMfgId 0 0 0 0xCE00
616 03:41:47.623807 SpdMMDate 0 0 0 0x2817
617 03:41:47.624041 SpdSerialNum 0 0 0 0x4F82936
618 03:41:47.644855 SpdMinTRCD 0 0 0 0x6E
619 03:41:47.645201 SpdMinTRCDFtb 0 0 0 0x0
620 03:41:47.645491 nRCD 0 0 0 0x35B6
621 03:41:47.645777 SpdMinTRRDL 0 0 0 0x28
622 03:41:47.672493 SpdMinTRRD 0 0 0 0x1B
623 03:41:47.672878 SpdMinTRAS 0 0 0 0x100
624 03:41:47.673180 SpdMinTRC 0 0 0 0x16E
625 03:41:47.673447 SpdMinTRCFtb 0 0 0 0x0
626 03:41:47.673746 SpdMinTRFC 0 0 0 0xAF0
627 03:41:47.688852 SpdMinTAA 0 0 0 0x6E
628 03:41:47.689191 SpdMinTAAFtb 0 0 0 0x0
629 03:41:47.689472 SpdMinTFAW 0 0 0 0x68
630 03:41:47.689753 SpdMinTRP 0 0 0 0x6E
631 03:41:47.690026 SpdMinTRPFtb 0 0 0 0x0
632 03:41:47.710797 nRP 0 0 0 0x35B6
633 03:41:47.711149 SpdMinTCCDL 0 0 0 0x28
634 03:41:47.711471 SpdMinTCCDLFtb 0 0 0 0x0
635 03:41:47.712001 SpdModuleAttr 0 0 0 0x0
636 03:41:47.732343 SpdAddrMap 0 0 0 0x1
637 03:41:47.732716 ---------------------------------------------------------------------
638 03:41:47.733005
639 03:41:47.733285 socket[0] channel[0] SPD information:
640 03:41:47.733587 ---------------------------------------------------------------------
641 03:41:47.733881 item skt ch value
642 03:41:47.754296 ---------------------------------------------------------------------
643 03:41:47.754647 nWR 0 0 0ps
644 03:41:47.755063 nRCD 0 0 13750ps
645 03:41:47.755328 nRRDL 0 0 4900ps
646 03:41:47.755630 nRRD 0 0 3300ps
647 03:41:47.755887 nRAS 0 0 32000ps
648 03:41:47.781461 nRC 0 0 45750ps
649 03:41:47.781776 nRFC 0 0 350000ps
650 03:41:47.782052 nWTR 0 0 0ps
651 03:41:47.782284 nRTP 0 0 0ps
652 03:41:47.782568 nAA 0 0 13750ps
653 03:41:47.782805 nFAW 0 0 13000ps
654 03:41:47.815753 nRP 0 0 13750ps
655 03:41:47.816071 nCCDL 0 0 5000ps
656 03:41:47.816532 ---------------------------------------------------------------------
657 03:41:47.816794
658 03:41:47.817032 socket[0] channel[1] dimm[0] i2c port[0] slaveAddr[0x54] SPD information:
659 03:41:48.522963 SPD_MIN_TRCD_DDR4: 0x6E
660 03:41:48.523403 SPD_FTB_TRCD_DDR4: 0x0
661 03:41:48.523678 SPD_MIN_TRRDL_DDR4: 0x28
662 03:41:48.523975 SPD_FTB_TRRDL_DDR4: 0x9C
663 03:41:48.524210 SPD_MIN_TRRDS_DDR4: 0x1B
664 03:41:48.525234 SPD_FTB_TRRDS_DDR4: 0xB5
665 03:41:48.525535 SPD_EXT_TRC_TRAS_DDR4: 0x11
666 03:41:48.525777 SPD_MIN_TRAS_DDR4: 0x0
667 03:41:48.526009 SPD_MIN_TRC_DDR4: 0x6E
668 03:41:48.526238 SPD_FTB_TRC_DDR4: 0x0
669 03:41:48.535656 SPD_MIN_TRFC1_MSB_DDR4: 0xA
670 03:41:48.535977 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
671 03:41:48.536242 tRFC: 0xAF0
672 03:41:48.536504 tempCkNum: 0x55730
673 03:41:48.536822 SPD_MIN_TAA_DDR4: 0x6E
674 03:41:48.537076 SPD_FTB_TAA: 0x0
675 03:41:48.537297 SPD_TFAW_UPPER_DDR4: 0x0
676 03:41:48.537567 SPD_MIN_TFAW_DDR4: 0x68
677 03:41:48.537800 SPD_MIN_TRP_DDR4: 0x6E
678 03:41:48.538022 SPD_FTB_TRP_DDR4: 0x0
679 03:41:48.548391 SPD_MIN_TCCDL_DDR4: 0x28
680 03:41:48.548736 SPD_FTB_TCCDL_DDR4: 0x0
681 03:41:48.549007 ---------------------------------------------------------------------
682 03:41:48.549327 pGblData item skt ch dimm value
683 03:41:48.549704 ---------------------------------------------------------------------
684 03:41:48.570090 SDRAMCapacity 0 1 0 0x5
685 03:41:48.570442 BGNum 0 1 0 4
686 03:41:48.570754 BankNum 0 1 0 16
687 03:41:48.571076 ColBits 0 1 0 10
688 03:41:48.571723 RowBits 0 1 0 17
689 03:41:48.591960 SpdMirror 0 1 0 1
690 03:41:48.592288 SpdVdd 0 1 0 3
691 03:41:48.592605 PrimaryBusWidth 0 1 0 64
692 03:41:48.592902 ExtensionBusWidth 0 1 0 8
693 03:41:48.613807 RankSize 0 1 0 16384
694 03:41:48.614116 SpdRMId 0 1 0 0x3206
695 03:41:48.614423 SpdMMfgId 0 1 0 0xCE00
696 03:41:48.614712 SpdMMDate 0 1 0 0x2817
697 03:41:48.615421 SpdSerialNum 0 1 0 0xE3F82936
698 03:41:48.639465 SpdMinTRCD 0 1 0 0x6E
699 03:41:48.639813 SpdMinTRCDFtb 0 1 0 0x0
700 03:41:48.640150 nRCD 0 1 0 0x35B6
701 03:41:48.640439 SpdMinTRRDL 0 1 0 0x28
702 03:41:48.657696 SpdMinTRRD 0 1 0 0x1B
703 03:41:48.658035 SpdMinTRAS 0 1 0 0x100
704 03:41:48.658346 SpdMinTRC 0 1 0 0x16E
705 03:41:48.658633 SpdMinTRCFtb 0 1 0 0x0
706 03:41:48.658868 SpdMinTRFC 0 1 0 0xAF0
707 03:41:48.679523 SpdMinTAA 0 1 0 0x6E
708 03:41:48.679821 SpdMinTAAFtb 0 1 0 0x0
709 03:41:48.680111 SpdMinTFAW 0 1 0 0x68
710 03:41:48.680421 SpdMinTRP 0 1 0 0x6E
711 03:41:48.681053 SpdMinTRPFtb 0 1 0 0x0
712 03:41:48.701415 nRP 0 1 0 0x35B6
713 03:41:48.701751 SpdMinTCCDL 0 1 0 0x28
714 03:41:48.702019 SpdMinTCCDLFtb 0 1 0 0x0
715 03:41:48.702326 SpdModuleAttr 0 1 0 0x0
716 03:41:48.723473 SpdAddrMap 0 1 0 0x1
717 03:41:48.723746 ---------------------------------------------------------------------
718 03:41:48.724009
719 03:41:48.724276 socket[0] channel[1] SPD information:
720 03:41:48.724551 ---------------------------------------------------------------------
721 03:41:48.724817 item skt ch value
722 03:41:48.803628 ---------------------------------------------------------------------
723 03:41:48.804071 nWR 0 1 0ps
724 03:41:48.804587 nRCD 0 1 13750ps
725 03:41:48.804916 nRRDL 0 1 4900ps
726 03:41:48.805182 nRRD 0 1 3300ps
727 03:41:48.805461 nRAS 0 1 32000ps
728 03:41:48.825862 nRC 0 1 45750ps
729 03:41:48.826240 nRFC 0 1 350000ps
730 03:41:48.826517 nWTR 0 1 0ps
731 03:41:48.836572 nRTP 0 1 0ps
732 03:41:48.836904 nAA 0 1 13750ps
733 03:41:48.837209 nFAW 0 1 13000ps
734 03:41:48.837491 nRP 0 1 13750ps
735 03:41:48.837767 nCCDL 0 1 5000ps
736 03:41:48.838045 ---------------------------------------------------------------------
737 03:41:48.838371
738 03:41:48.856205 socket[0] channel[2] dimm[0] i2c port[1] slaveAddr[0x50] SPD information:
739 03:41:49.497085 SPD_MIN_TRCD_DDR4: 0x6E
740 03:41:49.498234 SPD_FTB_TRCD_DDR4: 0x0
741 03:41:49.498567 SPD_MIN_TRRDL_DDR4: 0x28
742 03:41:49.498869 SPD_FTB_TRRDL_DDR4: 0x9C
743 03:41:49.499172 SPD_MIN_TRRDS_DDR4: 0x1B
744 03:41:49.499473 SPD_FTB_TRRDS_DDR4: 0xB5
745 03:41:49.499740 SPD_EXT_TRC_TRAS_DDR4: 0x11
746 03:41:49.500040 SPD_MIN_TRAS_DDR4: 0x0
747 03:41:49.500956 SPD_MIN_TRC_DDR4: 0x6E
748 03:41:49.501242 SPD_FTB_TRC_DDR4: 0x0
749 03:41:49.520042
750 03:41:49.520324 SPD_MIN_TRFC1_MSB_DDR4: 0xA
751 03:41:49.520697 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
752 03:41:49.521021 tRFC: 0xAF0
753 03:41:49.521301 tempCkNum: 0x55730
754 03:41:49.521610 SPD_MIN_TAA_DDR4: 0x6E
755 03:41:49.521874 SPD_FTB_TAA: 0x0
756 03:41:49.522137 SPD_TFAW_UPPER_DDR4: 0x0
757 03:41:49.522447 SPD_MIN_TFAW_DDR4: 0x68
758 03:41:49.522723 SPD_MIN_TRP_DDR4: 0x6E
759 03:41:49.522995 SPD_FTB_TRP_DDR4: 0x0
760 03:41:49.539400 SPD_MIN_TCCDL_DDR4: 0x28
761 03:41:49.539710 SPD_FTB_TCCDL_DDR4: 0x0
762 03:41:49.540020 ---------------------------------------------------------------------
763 03:41:49.540313 pGblData item skt ch dimm value
764 03:41:49.540644 ---------------------------------------------------------------------
765 03:41:49.561029 SDRAMCapacity 0 2 0 0x5
766 03:41:49.561392 BGNum 0 2 0 4
767 03:41:49.561704 BankNum 0 2 0 16
768 03:41:49.562025 ColBits 0 2 0 10
769 03:41:49.562330 RowBits 0 2 0 17
770 03:41:49.582938 SpdMirror 0 2 0 1
771 03:41:49.583242 SpdVdd 0 2 0 3
772 03:41:49.583512 PrimaryBusWidth 0 2 0 64
773 03:41:49.583774 ExtensionBusWidth 0 2 0 8
774 03:41:49.604864 RankSize 0 2 0 16384
775 03:41:49.605168 SpdRMId 0 2 0 0x3206
776 03:41:49.605473 SpdMMfgId 0 2 0 0xCE00
777 03:41:49.605769 SpdMMDate 0 2 0 0x2817
778 03:41:49.606144 SpdSerialNum 0 2 0 0xDFF32936
779 03:41:49.675740 SpdMinTRCD 0 2 0 0x6E
780 03:41:49.676082 SpdMinTRCDFtb 0 2 0 0x0
781 03:41:49.686672 nRCD 0 2 0 0x35B6
782 03:41:49.687055 SpdMinTRRDL 0 2 0 0x28
783 03:41:49.687344 SpdMinTRRD 0 2 0 0x1B
784 03:41:49.687609 SpdMinTRAS 0 2 0 0x100
785 03:41:49.687915 SpdMinTRC 0 2 0 0x16E
786 03:41:49.700076 SpdMinTRCFtb 0 2 0 0x0
787 03:41:49.700377 SpdMinTRFC 0 2 0 0xAF0
788 03:41:49.700746 SpdMinTAA 0 2 0 0x6E
789 03:41:49.701014 SpdMinTAAFtb 0 2 0 0x0
790 03:41:49.716847 SpdMinTFAW 0 2 0 0x68
791 03:41:49.717159 SpdMinTRP 0 2 0 0x6E
792 03:41:49.717468 SpdMinTRPFtb 0 2 0 0x0
793 03:41:49.717744 nRP 0 2 0 0x35B6
794 03:41:49.718019 SpdMinTCCDL 0 2 0 0x28
795 03:41:49.735800 SpdMinTCCDLFtb 0 2 0 0x0
796 03:41:49.736098 SpdModuleAttr 0 2 0 0x0
797 03:41:49.736392 SpdAddrMap 0 2 0 0x1
798 03:41:49.736736 ---------------------------------------------------------------------
799 03:41:49.737003
800 03:41:49.746023 socket[0] channel[2] SPD information:
801 03:41:49.746318 ---------------------------------------------------------------------
802 03:41:49.746605 item skt ch value
803 03:41:49.746910 ---------------------------------------------------------------------
804 03:41:49.747180 nWR 0 2 0ps
805 03:41:49.755809 nRCD 0 2 13750ps
806 03:41:49.756131 nRRDL 0 2 4900ps
807 03:41:49.756441 nRRD 0 2 3300ps
808 03:41:49.756765 nRAS 0 2 32000ps
809 03:41:49.757055 nRC 0 2 45750ps
810 03:41:49.757309 nRFC 0 2 350000ps
811 03:41:49.758085 nWTR 0 2 0ps
812 03:41:49.767677 nRTP 0 2 0ps
813 03:41:49.767983 nAA 0 2 13750ps
814 03:41:49.768254 nFAW 0 2 13000ps
815 03:41:49.768531 nRP 0 2 13750ps
816 03:41:49.769171 nCCDL 0 2 5000ps
817 03:41:49.769408 ---------------------------------------------------------------------
818 03:41:49.769649
819 03:41:49.842502 socket[0] channel[3] dimm[0] i2c port[0] slaveAddr[0x50] SPD information:
820 03:41:50.475735 SPD_MIN_TRCD_DDR4: 0x6E
821 03:41:50.478978 SPD_FTB_TRCD_DDR4: 0x0
822 03:41:50.479280 SPD_MIN_TRRDL_DDR4: 0x28
823 03:41:50.479577 SPD_FTB_TRRDL_DDR4: 0x9C
824 03:41:50.479894 SPD_MIN_TRRDS_DDR4: 0x1B
825 03:41:50.497756
826 03:41:50.498369 SPD_FTB_TRRDS_DDR4: 0xB5
827 03:41:50.498735 SPD_EXT_TRC_TRAS_DDR4: 0x11
828 03:41:50.499013 SPD_MIN_TRAS_DDR4: 0x0
829 03:41:50.499300 SPD_MIN_TRC_DDR4: 0x6E
830 03:41:50.499589 SPD_FTB_TRC_DDR4: 0x0
831 03:41:50.500011 SPD_MIN_TRFC1_MSB_DDR4: 0xA
832 03:41:50.500267 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
833 03:41:50.500494 tRFC: 0xAF0
834 03:41:50.500844 tempCkNum: 0x55730
835 03:41:50.501100 SPD_MIN_TAA_DDR4: 0x6E
836 03:41:50.519537 SPD_FTB_TAA: 0x0
837 03:41:50.519895 SPD_TFAW_UPPER_DDR4: 0x0
838 03:41:50.520168 SPD_MIN_TFAW_DDR4: 0x68
839 03:41:50.520451 SPD_MIN_TRP_DDR4: 0x6E
840 03:41:50.520775 SPD_FTB_TRP_DDR4: 0x0
841 03:41:50.521033 SPD_MIN_TCCDL_DDR4: 0x28
842 03:41:50.521342 SPD_FTB_TCCDL_DDR4: 0x0
843 03:41:50.521601 ---------------------------------------------------------------------
844 03:41:50.541185 pGblData item skt ch dimm value
845 03:41:50.541553 ---------------------------------------------------------------------
846 03:41:50.541875 SDRAMCapacity 0 3 0 0x5
847 03:41:50.542188 BGNum 0 3 0 4
848 03:41:50.563124 BankNum 0 3 0 16
849 03:41:50.563481 ColBits 0 3 0 10
850 03:41:50.563768 RowBits 0 3 0 17
851 03:41:50.564060 SpdMirror 0 3 0 1
852 03:41:50.564371 SpdVdd 0 3 0 3
853 03:41:50.585073 PrimaryBusWidth 0 3 0 64
854 03:41:50.585367 ExtensionBusWidth 0 3 0 8
855 03:41:50.585617 RankSize 0 3 0 16384
856 03:41:50.585878 SpdRMId 0 3 0 0x3206
857 03:41:50.586173 SpdMMfgId 0 3 0 0xCE00
858 03:41:50.607334 SpdMMDate 0 3 0 0x2817
859 03:41:50.607637 SpdSerialNum 0 3 0 0xF5F02936
860 03:41:50.607876 SpdMinTRCD 0 3 0 0x6E
861 03:41:50.608143 SpdMinTRCDFtb 0 3 0 0x0
862 03:41:50.636991 nRCD 0 3 0 0x35B6
863 03:41:50.637416 SpdMinTRRDL 0 3 0 0x28
864 03:41:50.637783 SpdMinTRRD 0 3 0 0x1B
865 03:41:50.638094 SpdMinTRAS 0 3 0 0x100
866 03:41:50.638444 SpdMinTRC 0 3 0 0x16E
867 03:41:50.657702 SpdMinTRCFtb 0 3 0 0x0
868 03:41:50.658040 SpdMinTRFC 0 3 0 0xAF0
869 03:41:50.658481 SpdMinTAA 0 3 0 0x6E
870 03:41:50.658766 SpdMinTAAFtb 0 3 0 0x0
871 03:41:50.675649 SpdMinTFAW 0 3 0 0x68
872 03:41:50.675969 SpdMinTRP 0 3 0 0x6E
873 03:41:50.676268 SpdMinTRPFtb 0 3 0 0x0
874 03:41:50.676614 nRP 0 3 0 0x35B6
875 03:41:50.676903 SpdMinTCCDL 0 3 0 0x28
876 03:41:50.732351 SpdMinTCCDLFtb 0 3 0 0x0
877 03:41:50.732770 SpdModuleAttr 0 3 0 0x0
878 03:41:50.733089 SpdAddrMap 0 3 0 0x1
879 03:41:50.733368 ---------------------------------------------------------------------
880 03:41:50.734065
881 03:41:50.746030 socket[0] channel[3] SPD information:
882 03:41:50.746349 ---------------------------------------------------------------------
883 03:41:50.746667 item skt ch value
884 03:41:50.746958 ---------------------------------------------------------------------
885 03:41:50.747272 nWR 0 3 0ps
886 03:41:50.756501 nRCD 0 3 13750ps
887 03:41:50.756889 nRRDL 0 3 4900ps
888 03:41:50.757391 nRRD 0 3 3300ps
889 03:41:50.757822 nRAS 0 3 32000ps
890 03:41:50.758127 nRC 0 3 45750ps
891 03:41:50.758414 nRFC 0 3 350000ps
892 03:41:50.758674 nWTR 0 3 0ps
893 03:41:50.769839 nRTP 0 3 0ps
894 03:41:50.770161 nAA 0 3 13750ps
895 03:41:50.770453 nFAW 0 3 13000ps
896 03:41:50.770760 nRP 0 3 13750ps
897 03:41:50.771076 nCCDL 0 3 5000ps
898 03:41:50.771348 ---------------------------------------------------------------------
899 03:41:50.771618
900 03:41:50.796358 socket[1] channel[0] dimm[0] i2c port[1] slaveAddr[0x54] SPD information:
901 03:41:51.476247 SPD_MIN_TRCD_DDR4: 0x6E
902 03:41:51.477520 SPD_FTB_TRCD_DDR4: 0x0
903 03:41:51.477885 SPD_MIN_TRRDL_DDR4: 0x28
904 03:41:51.478199 SPD_FTB_TRRDL_DDR4: 0x9C
905 03:41:51.478467 SPD_MIN_TRRDS_DDR4: 0x1B
906 03:41:51.478734 SPD_FTB_TRRDS_DDR4: 0xB5
907 03:41:51.478995 SPD_EXT_TRC_TRAS_DDR4: 0x11
908 03:41:51.479235 SPD_MIN_TRAS_DDR4: 0x0
909 03:41:51.479506 SPD_MIN_TRC_DDR4: 0x6E
910 03:41:51.479746 SPD_FTB_TRC_DDR4: 0x0
911 03:41:51.499782
912 03:41:51.500089 SPD_MIN_TRFC1_MSB_DDR4: 0xA
913 03:41:51.500426 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
914 03:41:51.500779 tRFC: 0xAF0
915 03:41:51.501390 tempCkNum: 0x55730
916 03:41:51.501660 SPD_MIN_TAA_DDR4: 0x6E
917 03:41:51.501938 SPD_FTB_TAA: 0x0
918 03:41:51.502251 SPD_TFAW_UPPER_DDR4: 0x0
919 03:41:51.502507 SPD_MIN_TFAW_DDR4: 0x68
920 03:41:51.502761 SPD_MIN_TRP_DDR4: 0x6E
921 03:41:51.503560 SPD_FTB_TRP_DDR4: 0x0
922 03:41:51.521553 SPD_MIN_TCCDL_DDR4: 0x28
923 03:41:51.521861 SPD_FTB_TCCDL_DDR4: 0x0
924 03:41:51.522333 ---------------------------------------------------------------------
925 03:41:51.522603 pGblData item skt ch dimm value
926 03:41:51.522888 ---------------------------------------------------------------------
927 03:41:51.543440 SDRAMCapacity 1 0 0 0x5
928 03:41:51.543749 BGNum 1 0 0 4
929 03:41:51.544037 BankNum 1 0 0 16
930 03:41:51.544312 ColBits 1 0 0 10
931 03:41:51.544996 RowBits 1 0 0 17
932 03:41:51.565562 SpdMirror 1 0 0 1
933 03:41:51.565913 SpdVdd 1 0 0 3
934 03:41:51.566245 PrimaryBusWidth 1 0 0 64
935 03:41:51.566505 ExtensionBusWidth 1 0 0 8
936 03:41:51.587356 RankSize 1 0 0 16384
937 03:41:51.587641 SpdRMId 1 0 0 0x3206
938 03:41:51.587881 SpdMMfgId 1 0 0 0xCE00
939 03:41:51.588114 SpdMMDate 1 0 0 0x2817
940 03:41:51.588350 SpdSerialNum 1 0 0 0xE2F32936
941 03:41:51.609194 SpdMinTRCD 1 0 0 0x6E
942 03:41:51.609529 SpdMinTRCDFtb 1 0 0 0x0
943 03:41:51.609796 nRCD 1 0 0 0x35B6
944 03:41:51.610090 SpdMinTRRDL 1 0 0 0x28
945 03:41:51.630935 SpdMinTRRD 1 0 0 0x1B
946 03:41:51.631274 SpdMinTRAS 1 0 0 0x100
947 03:41:51.631619 SpdMinTRC 1 0 0 0x16E
948 03:41:51.631893 SpdMinTRCFtb 1 0 0 0x0
949 03:41:51.632235 SpdMinTRFC 1 0 0 0xAF0
950 03:41:51.652802 SpdMinTAA 1 0 0 0x6E
951 03:41:51.653099 SpdMinTAAFtb 1 0 0 0x0
952 03:41:51.653426 SpdMinTFAW 1 0 0 0x68
953 03:41:51.653711 SpdMinTRP 1 0 0 0x6E
954 03:41:51.654016 SpdMinTRPFtb 1 0 0 0x0
955 03:41:51.674624 nRP 1 0 0 0x35B6
956 03:41:51.674933 SpdMinTCCDL 1 0 0 0x28
957 03:41:51.675270 SpdMinTCCDLFtb 1 0 0 0x0
958 03:41:51.675805 SpdModuleAttr 1 0 0 0x0
959 03:41:51.698964 SpdAddrMap 1 0 0 0x1
960 03:41:51.699273 ---------------------------------------------------------------------
961 03:41:51.700475
962 03:41:51.700829 socket[1] channel[0] SPD information:
963 03:41:51.701123 ---------------------------------------------------------------------
964 03:41:51.701408 item skt ch value
965 03:41:51.718434 ---------------------------------------------------------------------
966 03:41:51.718929 nWR 1 0 0ps
967 03:41:51.719360 nRCD 1 0 13750ps
968 03:41:51.719621 nRRDL 1 0 4900ps
969 03:41:51.719875 nRRD 1 0 3300ps
970 03:41:51.720172 nRAS 1 0 32000ps
971 03:41:51.740198 nRC 1 0 45750ps
972 03:41:51.740476 nRFC 1 0 350000ps
973 03:41:51.740766 nWTR 1 0 0ps
974 03:41:51.741000 nRTP 1 0 0ps
975 03:41:51.741264 nAA 1 0 13750ps
976 03:41:51.741511 nFAW 1 0 13000ps
977 03:41:51.775486 nRP 1 0 13750ps
978 03:41:51.775778 nCCDL 1 0 5000ps
979 03:41:51.776020 ---------------------------------------------------------------------
980 03:41:51.776283
981 03:41:51.776585 socket[1] channel[1] dimm[0] i2c port[0] slaveAddr[0x54] SPD information:
982 03:41:52.469310 SPD_MIN_TRCD_DDR4: 0x6E
983 03:41:52.470381 SPD_FTB_TRCD_DDR4: 0x0
984 03:41:52.470675 SPD_MIN_TRRDL_DDR4: 0x28
985 03:41:52.470985 SPD_FTB_TRRDL_DDR4: 0x9C
986 03:41:52.471280 SPD_MIN_TRRDS_DDR4: 0x1B
987 03:41:52.471892 SPD_FTB_TRRDS_DDR4: 0xB5
988 03:41:52.472167 SPD_EXT_TRC_TRAS_DDR4: 0x11
989 03:41:52.472454 SPD_MIN_TRAS_DDR4: 0x0
990 03:41:52.472784 SPD_MIN_TRC_DDR4: 0x6E
991 03:41:52.473066 SPD_FTB_TRC_DDR4: 0x0
992 03:41:52.491083
993 03:41:52.491373 SPD_MIN_TRFC1_MSB_DDR4: 0xA
994 03:41:52.491706 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
995 03:41:52.491995 tRFC: 0xAF0
996 03:41:52.492632 tempCkNum: 0x55730
997 03:41:52.492891 SPD_MIN_TAA_DDR4: 0x6E
998 03:41:52.493192 SPD_FTB_TAA: 0x0
999 03:41:52.493491 SPD_TFAW_UPPER_DDR4: 0x0
1000 03:41:52.494178 SPD_MIN_TFAW_DDR4: 0x68
1001 03:41:52.494458 SPD_MIN_TRP_DDR4: 0x6E
1002 03:41:52.494720 SPD_FTB_TRP_DDR4: 0x0
1003 03:41:52.512932 SPD_MIN_TCCDL_DDR4: 0x28
1004 03:41:52.513226 SPD_FTB_TCCDL_DDR4: 0x0
1005 03:41:52.513566 ---------------------------------------------------------------------
1006 03:41:52.513831 pGblData item skt ch dimm value
1007 03:41:52.514147 ---------------------------------------------------------------------
1008 03:41:52.534768 SDRAMCapacity 1 1 0 0x5
1009 03:41:52.535066 BGNum 1 1 0 4
1010 03:41:52.535346 BankNum 1 1 0 16
1011 03:41:52.535649 ColBits 1 1 0 10
1012 03:41:52.535900 RowBits 1 1 0 17
1013 03:41:52.579359 1 0 64
1014 03:41:52.579688 ExtensionBusWidth 1 1 0 8
1015 03:41:52.579996 RankSize 1 1 0 16384
1016 03:41:52.580316 SpdRMId 1 1 0 0x3206
1017 03:41:52.580960 SpdMMfgId 1 1 0 0xCE00
1018 03:41:52.596173 SpdMMDate 1 1 0 0x2817
1019 03:41:52.596551 SpdSerialNum 1 1 0 0x9AF22936
1020 03:41:52.596877 SpdMinTRCD 1 1 0 0x6E
1021 03:41:52.597161 SpdMinTRCDFtb 1 1 0 0x0
1022 03:41:52.611342 nRCD 1 1 0 0x35B6
1023 03:41:52.611636 SpdMinTRRDL 1 1 0 0x28
1024 03:41:52.611952 SpdMinTRRD 1 1 0 0x1B
1025 03:41:52.612237 SpdMinTRAS 1 1 0 0x100
1026 03:41:52.612508 SpdMinTRC 1 1 0 0x16E
1027 03:41:52.634211 SpdMinTRCFtb 1 1 0 0x0
1028 03:41:52.634514 SpdMinTRFC 1 1 0 0xAF0
1029 03:41:52.634849 SpdMinTAA 1 1 0 0x6E
1030 03:41:52.635128 SpdMinTAAFtb 1 1 0 0x0
1031 03:41:52.702117 SpdMinTFAW 1 1 0 0x68
1032 03:41:52.702505 SpdMinTRP 1 1 0 0x6E
1033 03:41:52.702796 SpdMinTRPFtb 1 1 0 0x0
1034 03:41:52.703101 nRP 1 1 0 0x35B6
1035 03:41:52.703457 SpdMinTCCDL 1 1 0 0x28
1036 03:41:52.716166 SpdMinTCCDLFtb 1 1 0 0x0
1037 03:41:52.716580 SpdModuleAttr 1 1 0 0x0
1038 03:41:52.716885 SpdAddrMap 1 1 0 0x1
1039 03:41:52.717152 ---------------------------------------------------------------------
1040 03:41:52.717471
1041 03:41:52.725624 socket[1] channel[1] SPD information:
1042 03:41:52.725936 ---------------------------------------------------------------------
1043 03:41:52.726236 item skt ch value
1044 03:41:52.726521 ---------------------------------------------------------------------
1045 03:41:52.726819 nWR 1 1 0ps
1046 03:41:52.735993 nRCD 1 1 13750ps
1047 03:41:52.736288 nRRDL 1 1 4900ps
1048 03:41:52.736596 nRRD 1 1 3300ps
1049 03:41:52.736890 nRAS 1 1 32000ps
1050 03:41:52.737151 nRC 1 1 45750ps
1051 03:41:52.737408 nRFC 1 1 350000ps
1052 03:41:52.738201 nWTR 1 1 0ps
1053 03:41:52.746867 nRTP 1 1 0ps
1054 03:41:52.747194 nAA 1 1 13750ps
1055 03:41:52.747472 nFAW 1 1 13000ps
1056 03:41:52.747735 nRP 1 1 13750ps
1057 03:41:52.747994 nCCDL 1 1 5000ps
1058 03:41:52.748295 ---------------------------------------------------------------------
1059 03:41:52.748605
1060 03:41:52.775550 socket[1] channel[2] dimm[0] i2c port[1] slaveAddr[0x50] SPD information:
1061 03:41:53.460556 SPD_MIN_TRCD_DDR4: 0x6E
1062 03:41:53.461536 SPD_FTB_TRCD_DDR4: 0x0
1063 03:41:53.461820 SPD_MIN_TRRDL_DDR4: 0x28
1064 03:41:53.462019 SPD_FTB_TRRDL_DDR4: 0x9C
1065 03:41:53.462250 SPD_MIN_TRRDS_DDR4: 0x1B
1066 03:41:53.462442 SPD_FTB_TRRDS_DDR4: 0xB5
1067 03:41:53.462665 SPD_EXT_TRC_TRAS_DDR4: 0x11
1068 03:41:53.462877 SPD_MIN_TRAS_DDR4: 0x0
1069 03:41:53.463062 SPD_MIN_TRC_DDR4: 0x6E
1070 03:41:53.463273 SPD_FTB_TRC_DDR4: 0x0
1071 03:41:53.482478
1072 03:41:53.482843 SPD_MIN_TRFC1_MSB_DDR4: 0xA
1073 03:41:53.483534 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
1074 03:41:53.484094 tRFC: 0xAF0
1075 03:41:53.484558 tempCkNum: 0x55730
1076 03:41:53.485060 SPD_MIN_TAA_DDR4: 0x6E
1077 03:41:53.485522 SPD_FTB_TAA: 0x0
1078 03:41:53.485965 SPD_TFAW_UPPER_DDR4: 0x0
1079 03:41:53.486189 SPD_MIN_TFAW_DDR4: 0x68
1080 03:41:53.486413 SPD_MIN_TRP_DDR4: 0x6E
1081 03:41:53.486662 SPD_FTB_TRP_DDR4: 0x0
1082 03:41:53.554507 SPD_MIN_TCCDL_DDR4: 0x28
1083 03:41:53.555331 SPD_FTB_TCCDL_DDR4: 0x0
1084 03:41:53.555651 ---------------------------------------------------------------------
1085 03:41:53.556161 pGblData item skt ch dimm value
1086 03:41:53.556590 ---------------------------------------------------------------------
1087 03:41:53.566297 SDRAMCapacity 1 2 0 0x5
1088 03:41:53.567012 BGNum 1 2 0 4
1089 03:41:53.567357 BankNum 1 2 0 16
1090 03:41:53.567755 ColBits 1 2 0 10
1091 03:41:53.568381 RowBits 1 2 0 17
1092 03:41:53.575787 SpdMirror 1 2 0 1
1093 03:41:53.576579 SpdVdd 1 2 0 3
1094 03:41:53.576948 PrimaryBusWidth 1 2 0 64
1095 03:41:53.577381 ExtensionBusWidth 1 2 0 8
1096 03:41:53.577977 RankSize 1 2 0 16384
1097 03:41:53.586244 SpdRMId 1 2 0 0x3206
1098 03:41:53.586930 SpdMMfgId 1 2 0 0xCE00
1099 03:41:53.587216 SpdMMDate 1 2 0 0x2817
1100 03:41:53.587705 SpdSerialNum 1 2 0 0x9BF22936
1101 03:41:53.597410 SpdMinTRCD 1 2 0 0x6E
1102 03:41:53.598006 SpdMinTRCDFtb 1 2 0 0x0
1103 03:41:53.598300 nRCD 1 2 0 0x35B6
1104 03:41:53.598741 SpdMinTRRDL 1 2 0 0x28
1105 03:41:53.615650 SpdMinTRRD 1 2 0 0x1B
1106 03:41:53.615972 SpdMinTRAS 1 2 0 0x100
1107 03:41:53.616232 SpdMinTRC 1 2 0 0x16E
1108 03:41:53.616432 SpdMinTRCFtb 1 2 0 0x0
1109 03:41:53.617094 SpdMinTRFC 1 2 0 0xAF0
1110 03:41:53.637067 SpdMinTAA 1 2 0 0x6E
1111 03:41:53.637707 SpdMinTAAFtb 1 2 0 0x0
1112 03:41:53.637949 SpdMinTFAW 1 2 0 0x68
1113 03:41:53.638209 SpdMinTRP 1 2 0 0x6E
1114 03:41:53.638432 SpdMinTRPFtb 1 2 0 0x0
1115 03:41:53.657812 nRP 1 2 0 0x35B6
1116 03:41:53.658152 SpdMinTCCDL 1 2 0 0x28
1117 03:41:53.658383 SpdMinTCCDLFtb 1 2 0 0x0
1118 03:41:53.658937 SpdModuleAttr 1 2 0 0x0
1119 03:41:53.681301 SpdAddrMap 1 2 0 0x1
1120 03:41:53.681568 ---------------------------------------------------------------------
1121 03:41:53.681988
1122 03:41:53.682189 socket[1] channel[2] SPD information:
1123 03:41:53.682410 ---------------------------------------------------------------------
1124 03:41:53.682637 item skt ch value
1125 03:41:53.701181 ---------------------------------------------------------------------
1126 03:41:53.701494 nWR 1 2 0ps
1127 03:41:53.701749 nRCD 1 2 13750ps
1128 03:41:53.701988 nRRDL 1 2 4900ps
1129 03:41:53.702226 nRRD 1 2 3300ps
1130 03:41:53.702453 nRAS 1 2 32000ps
1131 03:41:53.722889 nRC 1 2 45750ps
1132 03:41:53.723205 nRFC 1 2 350000ps
1133 03:41:53.723492 nWTR 1 2 0ps
1134 03:41:53.723775 nRTP 1 2 0ps
1135 03:41:53.724294 nAA 1 2 13750ps
1136 03:41:53.724631 nFAW 1 2 13000ps
1137 03:41:53.782471 nRP 1 2 13750ps
1138 03:41:53.783164 nCCDL 1 2 5000ps
1139 03:41:53.783456 ---------------------------------------------------------------------
1140 03:41:53.783707
1141 03:41:53.784016 socket[1] channel[3] dimm[0] i2c port[0] slaveAddr[0x50] SPD information:
1142 03:41:54.451954 SPD_MIN_TRCD_DDR4: 0x6E
1143 03:41:54.452490 SPD_FTB_TRCD_DDR4: 0x0
1144 03:41:54.453073 SPD_MIN_TRRDL_DDR4: 0x28
1145 03:41:54.453517 SPD_FTB_TRRDL_DDR4: 0x9C
1146 03:41:54.455063 SPD_MIN_TRRDS_DDR4: 0x1B
1147 03:41:54.455927 SPD_FTB_TRRDS_DDR4: 0xB5
1148 03:41:54.456566 SPD_EXT_TRC_TRAS_DDR4: 0x11
1149 03:41:54.457500 SPD_MIN_TRAS_DDR4: 0x0
1150 03:41:54.458231 SPD_MIN_TRC_DDR4: 0x6E
1151 03:41:54.459653 SPD_FTB_TRC_DDR4: 0x0
1152 03:41:54.473767
1153 03:41:54.474740 SPD_MIN_TRFC1_MSB_DDR4: 0xA
1154 03:41:54.475030 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
1155 03:41:54.475259 tRFC: 0xAF0
1156 03:41:54.475701 tempCkNum: 0x55730
1157 03:41:54.476488 SPD_MIN_TAA_DDR4: 0x6E
1158 03:41:54.480503 SPD_FTB_TAA: 0x0
1159 03:41:54.481603 SPD_TFAW_UPPER_DDR4: 0x0
1160 03:41:54.483169 SPD_MIN_TFAW_DDR4: 0x68
1161 03:41:54.484258 SPD_MIN_TRP_DDR4: 0x6E
1162 03:41:54.486166 SPD_FTB_TRP_DDR4: 0x0
1163 03:41:54.498173 SPD_MIN_TCCDL_DDR4: 0x28
1164 03:41:54.498987 SPD_FTB_TCCDL_DDR4: 0x0
1165 03:41:54.499391 ---------------------------------------------------------------------
1166 03:41:54.499834 pGblData item skt ch dimm value
1167 03:41:54.500279 ---------------------------------------------------------------------
1168 03:41:54.518502 SDRAMCapacity 1 3 0 0x5
1169 03:41:54.518982 BGNum 1 3 0 4
1170 03:41:54.519438 BankNum 1 3 0 16
1171 03:41:54.519994 ColBits 1 3 0 10
1172 03:41:54.520447 RowBits 1 3 0 17
1173 03:41:54.536654 SpdMirror 1 3 0 1
1174 03:41:54.537112 SpdVdd 1 3 0 3
1175 03:41:54.537513 PrimaryBusWidth 1 3 0 64
1176 03:41:54.537869 ExtensionBusWidth 1 3 0 8
1177 03:41:54.561104 RankSize 1 3 0 16384
1178 03:41:54.561959 SpdRMId 1 3 0 0x3206
1179 03:41:54.562379 SpdMMfgId 1 3 0 0xCE00
1180 03:41:54.562741 SpdMMDate 1 3 0 0x2817
1181 03:41:54.563146 SpdSerialNum 1 3 0 0x84E82936
1182 03:41:54.583250 SpdMinTRCD 1 3 0 0x6E
1183 03:41:54.584232 SpdMinTRCDFtb 1 3 0 0x0
1184 03:41:54.584616 nRCD 1 3 0 0x35B6
1185 03:41:54.585187 SpdMinTRRDL 1 3 0 0x28
1186 03:41:54.656340 SpdMinTRRD 1 3 0 0x1B
1187 03:41:54.657251 SpdMinTRAS 1 3 0 0x100
1188 03:41:54.657590 SpdMinTRC 1 3 0 0x16E
1189 03:41:54.658000 SpdMinTRCFtb 1 3 0 0x0
1190 03:41:54.658470 SpdMinTRFC 1 3 0 0xAF0
1191 03:41:54.665555 SpdMinTAA 1 3 0 0x6E
1192 03:41:54.666533 SpdMinTAAFtb 1 3 0 0x0
1193 03:41:54.666958 SpdMinTFAW 1 3 0 0x68
1194 03:41:54.667437 SpdMinTRP 1 3 0 0x6E
1195 03:41:54.668645 SpdMinTRPFtb 1 3 0 0x0
1196 03:41:54.676256 nRP 1 3 0 0x35B6
1197 03:41:54.677030 SpdMinTCCDL 1 3 0 0x28
1198 03:41:54.677389 SpdMinTCCDLFtb 1 3 0 0x0
1199 03:41:54.677878 SpdModuleAttr 1 3 0 0x0
1200 03:41:54.686997 SpdAddrMap 1 3 0 0x1
1201 03:41:54.687425 ---------------------------------------------------------------------
1202 03:41:54.687798
1203 03:41:54.688853 socket[1] channel[3] SPD information:
1204 03:41:54.689220 ---------------------------------------------------------------------
1205 03:41:54.689629 item skt ch value
1206 03:41:54.696003 ---------------------------------------------------------------------
1207 03:41:54.696291 nWR 1 3 0ps
1208 03:41:54.696819 nRCD 1 3 13750ps
1209 03:41:54.697277 nRRDL 1 3 4900ps
1210 03:41:54.698029 nRRD 1 3 3300ps
1211 03:41:54.698318 nRAS 1 3 32000ps
1212 03:41:54.714323 nRC 1 3 45750ps
1213 03:41:54.715115 nRFC 1 3 350000ps
1214 03:41:54.715432 nWTR 1 3 0ps
1215 03:41:54.715852 nRTP 1 3 0ps
1216 03:41:54.716327 nAA 1 3 13750ps
1217 03:41:54.716918 nFAW 1 3 13000ps
1218 03:41:54.736002 nRP 1 3 13750ps
1219 03:41:54.736362 nCCDL 1 3 5000ps
1220 03:41:54.736808 ---------------------------------------------------------------------
1221 03:41:54.737252 ---------------------------------------------------------------------
1222 03:41:54.760677 Socket Channel Dimm Present Rank0 Rank1 Rank2 Rank3
1223 03:41:54.761221 0 0 0 YES YES YES NOT NOT
1224 03:41:54.761661 0 0 1 NOT NOT NOT NOT NOT
1225 03:41:54.762118 0 0 2 NOT NOT NOT NOT NOT
1226 03:41:54.827374 0 1 0 YES YES YES NOT NOT
1227 03:41:54.827766 0 1 1 NOT NOT NOT NOT NOT
1228 03:41:54.828137 0 1 2 NOT NOT NOT NOT NOT
1229 03:41:54.837548 0 2 0 YES YES YES NOT NOT
1230 03:41:54.837889 0 2 1 NOT NOT NOT NOT NOT
1231 03:41:54.838535 0 2 2 NOT NOT NOT NOT NOT
1232 03:41:54.838827 0 3 0 YES YES YES NOT NOT
1233 03:41:54.848050 0 3 1 NOT NOT NOT NOT NOT
1234 03:41:54.848503 0 3 2 NOT NOT NOT NOT NOT
1235 03:41:54.848996 1 0 0 YES YES YES NOT NOT
1236 03:41:54.857328 1 0 1 NOT NOT NOT NOT NOT
1237 03:41:54.857673 1 0 2 NOT NOT NOT NOT NOT
1238 03:41:54.858005 1 1 0 YES YES YES NOT NOT
1239 03:41:54.867716 1 1 1 NOT NOT NOT NOT NOT
1240 03:41:54.868022 1 1 2 NOT NOT NOT NOT NOT
1241 03:41:54.868350 1 2 0 YES YES YES NOT NOT
1242 03:41:54.868648 1 2 1 NOT NOT NOT NOT NOT
1243 03:41:54.889858 1 2 2 NOT NOT NOT NOT NOT
1244 03:41:54.890161 1 3 0 YES YES YES NOT NOT
1245 03:41:54.890611 1 3 1 NOT NOT NOT NOT NOT
1246 03:41:54.911489 1 3 2 NOT NOT NOT NOT NOT
1247 03:41:54.912442 ---------------------------------------------------------------------
1248 03:41:54.913006 **********************************************************************
1249 03:41:54.913439 Socket[0] Channel[0] Base:[0x60340000] Speed:[2400]
1250 03:41:54.937838 **********************************************************************
1251 03:41:54.938110 ==========================
1252 03:41:54.938528 config parameters from SPD
1253 03:41:54.938904 ==========================
1254 03:41:54.939324 DDR PHY PLL config.....................................OK!
1255 03:41:54.939695 Top module cfg.........................................OK
1256 03:41:55.000142 ch[0] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
1257 03:41:55.000466 rank[0]: dmc_odt_config [0x603480A0]:wodt:0x1;rodt:0x2
1258 03:41:55.000977 rank[1]: dmc_odt_config [0x603480A4]:wodt:0x2;rodt:0x1
1259 03:41:55.001425 Dmc init static........................................OK
1260 03:41:55.015808 Phy init dynamic.......................................OK
1261 03:41:55.016183
1262 03:41:55.016606 [software pad_cal_0]: pvtr=0x1F; pvtn=0x1A; pvtp=0xC
1263 03:41:55.017046 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1C; pvtp=0xD
1264 03:41:55.017444 dimm[0] rcd init finished!
1265 03:41:55.017811 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1266 03:41:55.018210 rank[0] sdram init finished!
1267 03:41:55.026050 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1268 03:41:55.026420 rank[1] sdram init finished!
1269 03:41:55.026777 -----------------------------------------------------
1270 03:41:55.027138 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
1271 03:41:55.027484 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
1272 03:41:55.042217 -----------------------------------------------------
1273 03:41:55.042605 Dram init..............................................OK
1274 03:41:55.043029 socket[0] channel[0] rank[0] Phy gate leveling.....OK
1275 03:41:55.055656 socket[0] channel[0] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
1276 03:41:55.056009 lat_adj_start of rank 1 byte 1 is set to 0x00000001
1277 03:41:55.056378 lat_adj_start of rank 1 byte 6 is set to 0x00000001
1278 03:41:55.100167 lat_adj_start of rank 1 byte 7 is set to 0x00000001
1279 03:41:55.100588 OK
1280 03:41:55.100964 socket[0] channel[0] rank[0] Phy write leveling.....OK
1281 03:41:55.101316 socket[0] channel[0] rank[1] Phy write leveling.....OK
1282 03:41:55.127947 socket[0] channel[0] rank[0] Phy write leveling 2...OK
1283 03:41:55.128345 socket[0] channel[0] rank[1] Phy write leveling 2...OK
1284 03:41:55.128757 socket[0] channel[0] rank[0] Read data eye training start:
1285 03:41:55.215738 socket[0] channel[0] rank[0] Read data eye training end
1286 03:41:55.216283
1287 03:41:55.216726 socket[0] channel[0] rank[1] Read data eye training start:
1288 03:41:55.236711 socket[0] channel[0] rank[1] Read data eye training end
1289 03:41:55.237104
1290 03:41:55.237464 socket[0] channel[0] rank[0] Write data eye training start:
1291 03:41:55.305994 socket[0] channel[0] rank[0] Write data eye training end
1292 03:41:55.306402
1293 03:41:55.306778 socket[0] channel[0] rank[1] Write data eye training start:
1294 03:41:55.345503 socket[0] channel[0] rank[1] Write data eye training end
1295 03:41:55.345889
1296 03:41:55.346247 socket[0] channel[0] Rx vref training start
1297 03:41:55.717189 socket[0] channel[0] Rx vref training end
1298 03:41:55.717742
1299 03:41:55.718149 socket[0] channel[0] rank[0] Read data eye training start:
1300 03:41:55.755667 socket[0] channel[0] rank[0] Read data eye training end
1301 03:41:55.756070
1302 03:41:55.756399 socket[0] channel[0] rank[1] Read data eye training start:
1303 03:41:55.818653 socket[0] channel[0] rank[1] Read data eye training end
1304 03:41:55.819052
1305 03:41:55.819405 socket[0] channel[0] rank[0] RxPerBitTrainingExmbistOptimize start:
1306 03:41:55.819776 socket[0] channel[0] rank[0] RxPerBitTrainingExmbistOptimize end
1307 03:41:55.820138
1308 03:41:55.846017 socket[0] channel[0] rank[1] RxPerBitTrainingExmbistOptimize start:
1309 03:41:55.846405 socket[0] channel[0] rank[1] RxPerBitTrainingExmbistOptimize end
1310 03:41:55.847204
1311 03:41:55.847621 socket[0] channel[0] Tx vref training start
1312 03:41:57.335621 socket[0] channel[0] Tx vref training end
1313 03:41:57.335988
1314 03:41:57.336199 socket[0] channel[0] rank[0] Write data eye training start:
1315 03:41:57.385753 socket[0] channel[0] rank[0] Write data eye training end
1316 03:41:57.385991
1317 03:41:57.386202 socket[0] channel[0] rank[1] Write data eye training start:
1318 03:41:57.489377 socket[0] channel[0] rank[1] Write data eye training end
1319 03:41:57.489806
1320 03:41:57.490101 //----------------------------------
1321 03:41:57.490392 sfc test rank0
1322 03:41:57.505696 [0]wdata: 0x11111111 - 0x11111111 rdata
1323 03:41:57.505984 [1]wdata: 0x11111111 - 0x11111111 rdata
1324 03:41:57.506201 [2]wdata: 0x22222222 - 0x22222222 rdata
1325 03:41:57.506414 [3]wdata: 0x22222222 - 0x22222222 rdata
1326 03:41:57.506635 [4]wdata: 0x33333333 - 0x33333333 rdata
1327 03:41:57.506830 [5]wdata: 0x33333333 - 0x33333333 rdata
1328 03:41:57.515743 [6]wdata: 0x44444444 - 0x44444444 rdata
1329 03:41:57.516026 [7]wdata: 0x44444444 - 0x44444444 rdata
1330 03:41:57.516265 [8]wdata: 0x55555555 - 0x55555555 rdata
1331 03:41:57.516478 [9]wdata: 0x55555555 - 0x55555555 rdata
1332 03:41:57.516789 [10]wdata: 0x66666666 - 0x66666666 rdata
1333 03:41:57.517000 [11]wdata: 0x66666666 - 0x66666666 rdata
1334 03:41:57.526167 [12]wdata: 0x77777777 - 0x77777777 rdata
1335 03:41:57.526433 [13]wdata: 0x77777777 - 0x77777777 rdata
1336 03:41:57.526645 [14]wdata: 0x88888888 - 0x88888888 rdata
1337 03:41:57.526856 [15]wdata: 0x88888888 - 0x88888888 rdata
1338 03:41:57.527067 [16]wdata: 0x44332211 - 0x44332211 rdata
1339 03:41:57.527274 [17]wdata: 0x88776655 - 0x88776655 rdata
1340 03:41:57.527480 sfc test rank1
1341 03:41:57.535851 [0]wdata: 0x11111111 - 0x11111111 rdata
1342 03:41:57.536111 [1]wdata: 0x11111111 - 0x11111111 rdata
1343 03:41:57.536330 [2]wdata: 0x22222222 - 0x22222222 rdata
1344 03:41:57.536618 [3]wdata: 0x22222222 - 0x22222222 rdata
1345 03:41:57.536855 [4]wdata: 0x33333333 - 0x33333333 rdata
1346 03:41:57.537061 [5]wdata: 0x33333333 - 0x33333333 rdata
1347 03:41:57.553230 [6]wdata: 0x44444444 - 0x44444444 rdata
1348 03:41:57.553480 [7]wdata: 0x44444444 - 0x44444444 rdata
1349 03:41:57.553699 [8]wdata: 0x55555555 - 0x55555555 rdata
1350 03:41:57.553915 [9]wdata: 0x55555555 - 0x55555555 rdata
1351 03:41:57.554125 [10]wdata: 0x66666666 - 0x66666666 rdata
1352 03:41:57.554319 [11]wdata: 0x66666666 - 0x66666666 rdata
1353 03:41:57.587591 [12]wdata: 0x77777777 - 0x77777777 rdata
1354 03:41:57.587873 [13]wdata: 0x77777777 - 0x77777777 rdata
1355 03:41:57.588095 [14]wdata: 0x88888888 - 0x88888888 rdata
1356 03:41:57.588310 [15]wdata: 0x88888888 - 0x88888888 rdata
1357 03:41:57.588551 [16]wdata: 0x44332211 - 0x44332211 rdata
1358 03:41:57.588786 [17]wdata: 0x88776655 - 0x88776655 rdata
1359 03:41:57.598156 //----------------------------------
1360 03:41:57.598416 **********************************************************************
1361 03:41:57.598637 Socket[0] Channel[0] DDR Init Finished!
1362 03:41:57.598851 **********************************************************************
1363 03:41:57.615783 **********************************************************************
1364 03:41:57.616046 Socket[0] Channel[1] Base:[0x60350000] Speed:[2400]
1365 03:41:57.616259 **********************************************************************
1366 03:41:57.616476 ==========================
1367 03:41:57.616738 config parameters from SPD
1368 03:41:57.616946 ==========================
1369 03:41:57.641074 DDR PHY PLL config.....................................OK!
1370 03:41:57.641325 Top module cfg.........................................OK
1371 03:41:57.641545 ch[1] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
1372 03:41:57.641770 rank[0]: dmc_odt_config [0x603580A0]:wodt:0x1;rodt:0x2
1373 03:41:57.655673 rank[1]: dmc_odt_config [0x603580A4]:wodt:0x2;rodt:0x1
1374 03:41:57.655932 Dmc init static........................................OK
1375 03:41:57.656146 Phy init dynamic.......................................OK
1376 03:41:57.656360
1377 03:41:57.656599 [software pad_cal_0]: pvtr=0x1F; pvtn=0x1B; pvtp=0xC
1378 03:41:57.709382 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD
1379 03:41:57.725579 dimm[0] rcd init finished!
1380 03:41:57.725819 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1381 03:41:57.726046 rank[0] sdram init finished!
1382 03:41:57.726260 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1383 03:41:57.726480 rank[1] sdram init finished!
1384 03:41:57.726691 -----------------------------------------------------
1385 03:41:57.737178 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
1386 03:41:57.737437 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
1387 03:41:57.737655 -----------------------------------------------------
1388 03:41:57.737873 Dram init..............................................OK
1389 03:41:57.738085 socket[0] channel[1] rank[0] Phy gate leveling.....OK
1390 03:41:57.749369 socket[0] channel[1] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
1391 03:41:57.749637 lat_adj_start of rank 1 byte 1 is set to 0x00000001
1392 03:41:57.749861 lat_adj_start of rank 1 byte 6 is set to 0x00000001
1393 03:41:57.795916 lat_adj_start of rank 1 byte 7 is set to 0x00000001
1394 03:41:57.796166 OK
1395 03:41:57.796396 socket[0] channel[1] rank[0] Phy write leveling.....OK
1396 03:41:57.796635 socket[0] channel[1] rank[1] Phy write leveling.....OK
1397 03:41:57.815744 socket[0] channel[1] rank[0] Phy write leveling 2...OK
1398 03:41:57.815996 socket[0] channel[1] rank[1] Phy write leveling 2...OK
1399 03:41:57.816219 socket[0] channel[1] rank[0] Read data eye training start:
1400 03:41:57.865562 socket[0] channel[1] rank[0] Read data eye training end
1401 03:41:57.865831
1402 03:41:57.866057 socket[0] channel[1] rank[1] Read data eye training start:
1403 03:41:57.935702 socket[0] channel[1] rank[1] Read data eye training end
1404 03:41:57.935964
1405 03:41:57.936174 socket[0] channel[1] rank[0] Write data eye training start:
1406 03:41:57.986026 socket[0] channel[1] rank[0] Write data eye training end
1407 03:41:57.986283
1408 03:41:57.986501 socket[0] channel[1] rank[1] Write data eye training start:
1409 03:41:58.045532 socket[0] channel[1] rank[1] Write data eye training end
1410 03:41:58.045785
1411 03:41:58.045993 socket[0] channel[1] Rx vref training start
1412 03:41:58.395673 socket[0] channel[1] Rx vref training end
1413 03:41:58.396008
1414 03:41:58.396215 socket[0] channel[1] rank[0] Read data eye training start:
1415 03:41:58.455595 socket[0] channel[1] rank[0] Read data eye training end
1416 03:41:58.455836
1417 03:41:58.456043 socket[0] channel[1] rank[1] Read data eye training start:
1418 03:41:58.556869 socket[0] channel[1] rank[1] Read data eye training end
1419 03:41:58.557115
1420 03:41:58.576155 socket[0] channel[1] rank[0] RxPerBitTrainingExmbistOptimize start:
1421 03:41:58.576394 socket[0] channel[1] rank[0] RxPerBitTrainingExmbistOptimize end
1422 03:41:58.576628
1423 03:41:58.576848 socket[0] channel[1] rank[1] RxPerBitTrainingExmbistOptimize start:
1424 03:41:58.577046 socket[0] channel[1] rank[1] RxPerBitTrainingExmbistOptimize end
1425 03:41:58.577245
1426 03:41:58.577437 socket[0] channel[1] Tx vref training start
1427 03:42:00.086562 socket[0] channel[1] Tx vref training end
1428 03:42:00.086923
1429 03:42:00.087130 socket[0] channel[1] rank[0] Write data eye training start:
1430 03:42:00.129072 socket[0] channel[1] rank[0] Write data eye training end
1431 03:42:00.129353
1432 03:42:00.129562 socket[0] channel[1] rank[1] Write data eye training start:
1433 03:42:00.199069 socket[0] channel[1] rank[1] Write data eye training end
1434 03:42:00.199364
1435 03:42:00.199566 //----------------------------------
1436 03:42:00.199767 sfc test rank0
1437 03:42:00.199967 [0]wdata: 0x11111111 - 0x11111111 rdata
1438 03:42:00.200163 [1]wdata: 0x11111111 - 0x11111111 rdata
1439 03:42:00.200357 [2]wdata: 0x22222222 - 0x22222222 rdata
1440 03:42:00.220427 [3]wdata: 0x22222222 - 0x22222222 rdata
1441 03:42:00.220713 [4]wdata: 0x33333333 - 0x33333333 rdata
1442 03:42:00.220922 [5]wdata: 0x33333333 - 0x33333333 rdata
1443 03:42:00.221123 [6]wdata: 0x44444444 - 0x44444444 rdata
1444 03:42:00.221316 [7]wdata: 0x44444444 - 0x44444444 rdata
1445 03:42:00.221504 [8]wdata: 0x55555555 - 0x55555555 rdata
1446 03:42:00.242670 [9]wdata: 0x55555555 - 0x55555555 rdata
1447 03:42:00.242920 [10]wdata: 0x66666666 - 0x66666666 rdata
1448 03:42:00.243124 [11]wdata: 0x66666666 - 0x66666666 rdata
1449 03:42:00.243324 [12]wdata: 0x77777777 - 0x77777777 rdata
1450 03:42:00.243522 [13]wdata: 0x77777777 - 0x77777777 rdata
1451 03:42:00.243712 [14]wdata: 0x88888888 - 0x88888888 rdata
1452 03:42:00.264046 [15]wdata: 0x88888888 - 0x88888888 rdata
1453 03:42:00.264285 [16]wdata: 0x44332211 - 0x44332211 rdata
1454 03:42:00.264490 [17]wdata: 0x88776655 - 0x88776655 rdata
1455 03:42:00.264762 sfc test rank1
1456 03:42:00.264965 [0]wdata: 0x11111111 - 0x11111111 rdata
1457 03:42:00.265174 [1]wdata: 0x11111111 - 0x11111111 rdata
1458 03:42:00.265364 [2]wdata: 0x22222222 - 0x22222222 rdata
1459 03:42:00.285670 [3]wdata: 0x22222222 - 0x22222222 rdata
1460 03:42:00.285912 [4]wdata: 0x33333333 - 0x33333333 rdata
1461 03:42:00.286116 [5]wdata: 0x33333333 - 0x33333333 rdata
1462 03:42:00.286317 [6]wdata: 0x44444444 - 0x44444444 rdata
1463 03:42:00.286507 [7]wdata: 0x44444444 - 0x44444444 rdata
1464 03:42:00.286699 [8]wdata: 0x55555555 - 0x55555555 rdata
1465 03:42:00.305887 [9]wdata: 0x55555555 - 0x55555555 rdata
1466 03:42:00.306157 [10]wdata: 0x66666666 - 0x66666666 rdata
1467 03:42:00.306367 [11]wdata: 0x66666666 - 0x66666666 rdata
1468 03:42:00.306565 [12]wdata: 0x77777777 - 0x77777777 rdata
1469 03:42:00.306765 [13]wdata: 0x77777777 - 0x77777777 rdata
1470 03:42:00.306951 [14]wdata: 0x88888888 - 0x88888888 rdata
1471 03:42:00.329894 [15]wdata: 0x88888888 - 0x88888888 rdata
1472 03:42:00.330137 [16]wdata: 0x44332211 - 0x44332211 rdata
1473 03:42:00.330343 [17]wdata: 0x88776655 - 0x88776655 rdata
1474 03:42:00.330546 //----------------------------------
1475 03:42:00.331019 **********************************************************************
1476 03:42:00.350481 Socket[0] Channel[1] DDR Init Finished!
1477 03:42:00.350736 **********************************************************************
1478 03:42:00.350943 **********************************************************************
1479 03:42:00.351149 Socket[0] Channel[2] Base:[0x40340000] Speed:[2400]
1480 03:42:00.374164 **********************************************************************
1481 03:42:00.374421 ==========================
1482 03:42:00.374626 config parameters from SPD
1483 03:42:00.374820 ==========================
1484 03:42:00.375013 DDR PHY PLL config.....................................OK!
1485 03:42:00.375206 Top module cfg.........................................OK
1486 03:42:00.396205 ch[2] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
1487 03:42:00.396452 rank[0]: dmc_odt_config [0x403480A0]:wodt:0x1;rodt:0x2
1488 03:42:00.396713 rank[1]: dmc_odt_config [0x403480A4]:wodt:0x2;rodt:0x1
1489 03:42:00.396918 Dmc init static........................................OK
1490 03:42:00.409598 Phy init dynamic.......................................OK
1491 03:42:00.409838
1492 03:42:00.410047 [software pad_cal_0]: pvtr=0x1F; pvtn=0x1A; pvtp=0xC
1493 03:42:00.410250 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD
1494 03:42:00.431481 dimm[0] rcd init finished!
1495 03:42:00.431741 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1496 03:42:00.431947 rank[0] sdram init finished!
1497 03:42:00.432145 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1498 03:42:00.432342 rank[1] sdram init finished!
1499 03:42:00.432560 -----------------------------------------------------
1500 03:42:00.480411 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
1501 03:42:00.480717 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
1502 03:42:00.480923 -----------------------------------------------------
1503 03:42:00.481127 Dram init..............................................OK
1504 03:42:00.481325 socket[0] channel[2] rank[0] Phy gate leveling.....OK
1505 03:42:00.499726 socket[0] channel[2] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
1506 03:42:00.499968 lat_adj_start of rank 1 byte 1 is set to 0x00000001
1507 03:42:00.500171 lat_adj_start of rank 1 byte 2 is set to 0x00000001
1508 03:42:00.525729 lat_adj_start of rank 1 byte 3 is set to 0x00000001
1509 03:42:00.525977 lat_adj_start of rank 1 byte 4 is set to 0x00000001
1510 03:42:00.526185 lat_adj_start of rank 1 byte 5 is set to 0x00000001
1511 03:42:00.526385 lat_adj_start of rank 1 byte 6 is set to 0x00000001
1512 03:42:00.526587 lat_adj_start of rank 1 byte 7 is set to 0x00000001
1513 03:42:00.549133 OK
1514 03:42:00.549405 socket[0] channel[2] rank[0] Phy write leveling.....OK
1515 03:42:00.549613 socket[0] channel[2] rank[1] Phy write leveling.....OK
1516 03:42:00.585793 socket[0] channel[2] rank[0] Phy write leveling 2...OK
1517 03:42:00.586139 socket[0] channel[2] rank[1] Phy write leveling 2...OK
1518 03:42:00.586385 socket[0] channel[2] rank[0] Read data eye training start:
1519 03:42:00.625750 socket[0] channel[2] rank[0] Read data eye training end
1520 03:42:00.626026
1521 03:42:00.626234 socket[0] channel[2] rank[1] Read data eye training start:
1522 03:42:00.676216 socket[0] channel[2] rank[1] Read data eye training end
1523 03:42:00.676475
1524 03:42:00.676732 socket[0] channel[2] rank[0] Write data eye training start:
1525 03:42:00.735972 socket[0] channel[2] rank[0] Write data eye training end
1526 03:42:00.736217
1527 03:42:00.736428 socket[0] channel[2] rank[1] Write data eye training start:
1528 03:42:00.805836 socket[0] channel[2] rank[1] Write data eye training end
1529 03:42:00.806094
1530 03:42:00.806300 socket[0] channel[2] Rx vref training start
1531 03:42:01.165748 socket[0] channel[2] Rx vref training end
1532 03:42:01.166102
1533 03:42:01.166307 socket[0] channel[2] rank[0] Read data eye training start:
1534 03:42:01.199930 socket[0] channel[2] rank[0] Read data eye training end
1535 03:42:01.200235
1536 03:42:01.200441 socket[0] channel[2] rank[1] Read data eye training start:
1537 03:42:01.276986 socket[0] channel[2] rank[1] Read data eye training end
1538 03:42:01.277377
1539 03:42:01.277586 socket[0] channel[2] rank[0] RxPerBitTrainingExmbistOptimize start:
1540 03:42:01.277782 socket[0] channel[2] rank[0] RxPerBitTrainingExmbistOptimize end
1541 03:42:01.277978
1542 03:42:01.296588 socket[0] channel[2] rank[1] RxPerBitTrainingExmbistOptimize start:
1543 03:42:01.296885 socket[0] channel[2] rank[1] RxPerBitTrainingExmbistOptimize end
1544 03:42:01.297086
1545 03:42:01.297283 socket[0] channel[2] Tx vref training start
1546 03:42:02.817050 socket[0] channel[2] Tx vref training end
1547 03:42:02.817404
1548 03:42:02.817618 socket[0] channel[2] rank[0] Write data eye training start:
1549 03:42:02.875906 socket[0] channel[2] rank[0] Write data eye training end
1550 03:42:02.876166
1551 03:42:02.876370 socket[0] channel[2] rank[1] Write data eye training start:
1552 03:42:02.925733 socket[0] channel[2] rank[1] Write data eye training end
1553 03:42:02.925980
1554 03:42:02.926187 //----------------------------------
1555 03:42:02.926389 sfc test rank0
1556 03:42:02.950341 [0]wdata: 0x11111111 - 0x11111111 rdata
1557 03:42:02.950579 [1]wdata: 0x11111111 - 0x11111111 rdata
1558 03:42:02.950781 [2]wdata: 0x22222222 - 0x22222222 rdata
1559 03:42:02.950983 [3]wdata: 0x22222222 - 0x22222222 rdata
1560 03:42:02.951178 [4]wdata: 0x33333333 - 0x33333333 rdata
1561 03:42:02.951373 [5]wdata: 0x33333333 - 0x33333333 rdata
1562 03:42:02.972323 [6]wdata: 0x44444444 - 0x44444444 rdata
1563 03:42:02.972586 [7]wdata: 0x44444444 - 0x44444444 rdata
1564 03:42:02.972817 [8]wdata: 0x55555555 - 0x55555555 rdata
1565 03:42:02.973021 [9]wdata: 0x55555555 - 0x55555555 rdata
1566 03:42:02.973217 [10]wdata: 0x66666666 - 0x66666666 rdata
1567 03:42:02.973409 [11]wdata: 0x66666666 - 0x66666666 rdata
1568 03:42:02.994124 [12]wdata: 0x77777777 - 0x77777777 rdata
1569 03:42:02.994365 [13]wdata: 0x77777777 - 0x77777777 rdata
1570 03:42:02.994570 [14]wdata: 0x88888888 - 0x88888888 rdata
1571 03:42:02.994767 [15]wdata: 0x88888888 - 0x88888888 rdata
1572 03:42:02.994965 [16]wdata: 0x44332211 - 0x44332211 rdata
1573 03:42:02.995157 [17]wdata: 0x88776655 - 0x88776655 rdata
1574 03:42:02.995346 sfc test rank1
1575 03:42:03.022223 [0]wdata: 0x11111111 - 0x11111111 rdata
1576 03:42:03.022465 [1]wdata: 0x11111111 - 0x11111111 rdata
1577 03:42:03.022672 [2]wdata: 0x22222222 - 0x22222222 rdata
1578 03:42:03.022869 [3]wdata: 0x22222222 - 0x22222222 rdata
1579 03:42:03.023064 [4]wdata: 0x33333333 - 0x33333333 rdata
1580 03:42:03.023701 [5]wdata: 0x33333333 - 0x33333333 rdata
1581 03:42:03.037766 [6]wdata: 0x44444444 - 0x44444444 rdata
1582 03:42:03.038013 [7]wdata: 0x44444444 - 0x44444444 rdata
1583 03:42:03.038219 [8]wdata: 0x55555555 - 0x55555555 rdata
1584 03:42:03.038419 [9]wdata: 0x55555555 - 0x55555555 rdata
1585 03:42:03.038616 [10]wdata: 0x66666666 - 0x66666666 rdata
1586 03:42:03.038809 [11]wdata: 0x66666666 - 0x66666666 rdata
1587 03:42:03.059687 [12]wdata: 0x77777777 - 0x77777777 rdata
1588 03:42:03.059933 [13]wdata: 0x77777777 - 0x77777777 rdata
1589 03:42:03.060136 [14]wdata: 0x88888888 - 0x88888888 rdata
1590 03:42:03.060337 [15]wdata: 0x88888888 - 0x88888888 rdata
1591 03:42:03.060577 [16]wdata: 0x44332211 - 0x44332211 rdata
1592 03:42:03.060798 [17]wdata: 0x88776655 - 0x88776655 rdata
1593 03:42:03.081584 //----------------------------------
1594 03:42:03.081859 **********************************************************************
1595 03:42:03.082083 Socket[0] Channel[2] DDR Init Finished!
1596 03:42:03.082290 **********************************************************************
1597 03:42:03.104156 **********************************************************************
1598 03:42:03.104488 Socket[0] Channel[3] Base:[0x40350000] Speed:[2400]
1599 03:42:03.104763 **********************************************************************
1600 03:42:03.104968 ==========================
1601 03:42:03.105163 config parameters from SPD
1602 03:42:03.105353 ==========================
1603 03:42:03.126354 DDR PHY PLL config.....................................OK!
1604 03:42:03.126653 Top module cfg.........................................OK
1605 03:42:03.126861 ch[3] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
1606 03:42:03.127063 rank[0]: dmc_odt_config [0x403580A0]:wodt:0x1;rodt:0x2
1607 03:42:03.148671 rank[1]: dmc_odt_config [0x403580A4]:wodt:0x2;rodt:0x1
1608 03:42:03.148929 Dmc init static........................................OK
1609 03:42:03.167405 Phy init dynamic.......................................OK
1610 03:42:03.167650
1611 03:42:03.167847 [software pad_cal_0]: pvtr=0x1F; pvtn=0x1B; pvtp=0xC
1612 03:42:03.168047 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1C; pvtp=0xD
1613 03:42:03.185806 dimm[0] rcd init finished!
1614 03:42:03.186062 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1615 03:42:03.186260 rank[0] sdram init finished!
1616 03:42:03.186451 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1617 03:42:03.186639 rank[1] sdram init finished!
1618 03:42:03.186823 -----------------------------------------------------
1619 03:42:03.206656 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
1620 03:42:03.206898 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
1621 03:42:03.207099 -----------------------------------------------------
1622 03:42:03.207298 Dram init..............................................OK
1623 03:42:03.229893 socket[0] channel[3] rank[0] Phy gate leveling.....OK
1624 03:42:03.230142 socket[0] channel[3] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
1625 03:42:03.251885 lat_adj_start of rank 1 byte 1 is set to 0x00000001
1626 03:42:03.252132 lat_adj_start of rank 1 byte 2 is set to 0x00000001
1627 03:42:03.252337 lat_adj_start of rank 1 byte 3 is set to 0x00000001
1628 03:42:03.252581 lat_adj_start of rank 1 byte 4 is set to 0x00000001
1629 03:42:03.252806 lat_adj_start of rank 1 byte 5 is set to 0x00000001
1630 03:42:03.313254 lat_adj_start of rank 1 byte 6 is set to 0x00000001
1631 03:42:03.313565 lat_adj_start of rank 1 byte 7 is set to 0x00000001
1632 03:42:03.327682 OK
1633 03:42:03.327943 socket[0] channel[3] rank[0] Phy write leveling.....OK
1634 03:42:03.328151 socket[0] channel[3] rank[1] Phy write leveling.....OK
1635 03:42:03.328349 socket[0] channel[3] rank[0] Phy write leveling 2...OK
1636 03:42:03.328602 socket[0] channel[3] rank[1] Phy write leveling 2...OK
1637 03:42:03.368006 socket[0] channel[3] rank[0] Read data eye training start:
1638 03:42:03.368254 socket[0] channel[3] rank[0] Read data eye training end
1639 03:42:03.368460
1640 03:42:03.368736 socket[0] channel[3] rank[1] Read data eye training start:
1641 03:42:03.416953 socket[0] channel[3] rank[1] Read data eye training end
1642 03:42:03.417205
1643 03:42:03.417402 socket[0] channel[3] rank[0] Write data eye training start:
1644 03:42:03.506129 socket[0] channel[3] rank[0] Write data eye training end
1645 03:42:03.506487
1646 03:42:03.506696 socket[0] channel[3] rank[1] Write data eye training start:
1647 03:42:03.535655 socket[0] channel[3] rank[1] Write data eye training end
1648 03:42:03.535999
1649 03:42:03.536205 socket[0] channel[3] Rx vref training start
1650 03:42:03.885692 socket[0] channel[3] Rx vref training end
1651 03:42:03.886039
1652 03:42:03.886280 socket[0] channel[3] rank[0] Read data eye training start:
1653 03:42:03.955993 socket[0] channel[3] rank[0] Read data eye training end
1654 03:42:03.956249
1655 03:42:03.956454 socket[0] channel[3] rank[1] Read data eye training start:
1656 03:42:03.994455 socket[0] channel[3] rank[1] Read data eye training end
1657 03:42:03.994700
1658 03:42:03.995022 socket[0] channel[3] rank[0] RxPerBitTrainingExmbistOptimize start:
1659 03:42:03.995342 socket[0] channel[3] rank[0] RxPerBitTrainingExmbistOptimize end
1660 03:42:03.995650
1661 03:42:04.017756 socket[0] channel[3] rank[1] RxPerBitTrainingExmbistOptimize start:
1662 03:42:04.017995 socket[0] channel[3] rank[1] RxPerBitTrainingExmbistOptimize end
1663 03:42:04.018201
1664 03:42:04.018409 socket[0] channel[3] Tx vref training start
1665 03:42:05.508183 socket[0] channel[3] Tx vref training end
1666 03:42:05.508791
1667 03:42:05.509105 socket[0] channel[3] rank[0] Write data eye training start:
1668 03:42:05.565629 socket[0] channel[3] rank[0] Write data eye training end
1669 03:42:05.566054
1670 03:42:05.566509 socket[0] channel[3] rank[1] Write data eye training start:
1671 03:42:05.631188 socket[0] channel[3] rank[1] Write data eye training end
1672 03:42:05.631825
1673 03:42:05.632067 //----------------------------------
1674 03:42:05.632464 sfc test rank0
1675 03:42:05.632985 [0]wdata: 0x11111111 - 0x11111111 rdata
1676 03:42:05.633688 [1]wdata: 0x11111111 - 0x11111111 rdata
1677 03:42:05.634104 [2]wdata: 0x22222222 - 0x22222222 rdata
1678 03:42:05.653105 [3]wdata: 0x22222222 - 0x22222222 rdata
1679 03:42:05.653360 [4]wdata: 0x33333333 - 0x33333333 rdata
1680 03:42:05.653779 [5]wdata: 0x33333333 - 0x33333333 rdata
1681 03:42:05.654374 [6]wdata: 0x44444444 - 0x44444444 rdata
1682 03:42:05.654826 [7]wdata: 0x44444444 - 0x44444444 rdata
1683 03:42:05.655170 [8]wdata: 0x55555555 - 0x55555555 rdata
1684 03:42:05.674885 [9]wdata: 0x55555555 - 0x55555555 rdata
1685 03:42:05.675196 [10]wdata: 0x66666666 - 0x66666666 rdata
1686 03:42:05.675451 [11]wdata: 0x66666666 - 0x66666666 rdata
1687 03:42:05.675992 [12]wdata: 0x77777777 - 0x77777777 rdata
1688 03:42:05.676411 [13]wdata: 0x77777777 - 0x77777777 rdata
1689 03:42:05.676980 [14]wdata: 0x88888888 - 0x88888888 rdata
1690 03:42:05.696256 [15]wdata: 0x88888888 - 0x88888888 rdata
1691 03:42:05.696825 [16]wdata: 0x44332211 - 0x44332211 rdata
1692 03:42:05.697276 [17]wdata: 0x88776655 - 0x88776655 rdata
1693 03:42:05.697833 sfc test rank1
1694 03:42:05.698085 [0]wdata: 0x11111111 - 0x11111111 rdata
1695 03:42:05.698353 [1]wdata: 0x11111111 - 0x11111111 rdata
1696 03:42:05.698606 [2]wdata: 0x22222222 - 0x22222222 rdata
1697 03:42:05.718738 [3]wdata: 0x22222222 - 0x22222222 rdata
1698 03:42:05.719053 [4]wdata: 0x33333333 - 0x33333333 rdata
1699 03:42:05.719333 [5]wdata: 0x33333333 - 0x33333333 rdata
1700 03:42:05.719585 [6]wdata: 0x44444444 - 0x44444444 rdata
1701 03:42:05.719846 [7]wdata: 0x44444444 - 0x44444444 rdata
1702 03:42:05.720090 [8]wdata: 0x55555555 - 0x55555555 rdata
1703 03:42:05.742291 [9]wdata: 0x55555555 - 0x55555555 rdata
1704 03:42:05.742605 [10]wdata: 0x66666666 - 0x66666666 rdata
1705 03:42:05.744557 [11]wdata: 0x66666666 - 0x66666666 rdata
1706 03:42:05.744827 [12]wdata: 0x77777777 - 0x77777777 rdata
1707 03:42:05.745055 [13]wdata: 0x77777777 - 0x77777777 rdata
1708 03:42:05.745277 [14]wdata: 0x88888888 - 0x88888888 rdata
1709 03:42:05.762478 [15]wdata: 0x88888888 - 0x88888888 rdata
1710 03:42:05.763184 [16]wdata: 0x44332211 - 0x44332211 rdata
1711 03:42:05.763577 [17]wdata: 0x88776655 - 0x88776655 rdata
1712 03:42:05.764046 //----------------------------------
1713 03:42:05.764270 **********************************************************************
1714 03:42:05.783474 Socket[0] Channel[3] DDR Init Finished!
1715 03:42:05.783727 **********************************************************************
1716 03:42:05.783953 **********************************************************************
1717 03:42:05.784250 Socket[1] Channel[0] Base:[0x40060340000] Speed:[2400]
1718 03:42:05.805946 **********************************************************************
1719 03:42:05.806216 ==========================
1720 03:42:05.806489 config parameters from SPD
1721 03:42:05.806765 ==========================
1722 03:42:05.806996 DDR PHY PLL config.....................................OK!
1723 03:42:05.807186 Top module cfg.........................................OK
1724 03:42:05.837348 ch[0] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
1725 03:42:05.837715 rank[0]: dmc_odt_config [0x603480A0]:wodt:0x1;rodt:0x2
1726 03:42:05.837949 rank[1]: dmc_odt_config [0x603480A4]:wodt:0x2;rodt:0x1
1727 03:42:05.838254 Dmc init static........................................OK
1728 03:42:05.860565 Phy init dynamic.......................................OK
1729 03:42:05.861216
1730 03:42:05.861554 [software pad_cal_0]: pvtr=0x1F; pvtn=0x19; pvtp=0xB
1731 03:42:05.861875 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD
1732 03:42:05.918994 dimm[0] rcd init finished!
1733 03:42:05.919309 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1734 03:42:05.919728 rank[0] sdram init finished!
1735 03:42:05.919984 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1736 03:42:05.920252 rank[1] sdram init finished!
1737 03:42:05.920534 -----------------------------------------------------
1738 03:42:05.937476 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
1739 03:42:05.937945 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
1740 03:42:05.938201 -----------------------------------------------------
1741 03:42:05.938796 Dram init..............................................OK
1742 03:42:05.939028 socket[1] channel[0] rank[0] Phy gate leveling.....OK
1743 03:42:05.961470 socket[1] channel[0] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
1744 03:42:06.001519 lat_adj_start of rank 1 byte 1 is set to 0x00000001
1745 03:42:06.001843 lat_adj_start of rank 1 byte 6 is set to 0x00000001
1746 03:42:06.002245 lat_adj_start of rank 1 byte 7 is set to 0x00000001
1747 03:42:06.002472 OK
1748 03:42:06.016080 socket[1] channel[0] rank[0] Phy write leveling.....OK
1749 03:42:06.016377 socket[1] channel[0] rank[1] Phy write leveling.....OK
1750 03:42:06.016632 socket[1] channel[0] rank[0] Phy write leveling 2...OK
1751 03:42:06.017275 socket[1] channel[0] rank[1] Phy write leveling 2...OK
1752 03:42:06.035765 socket[1] channel[0] rank[0] Read data eye training start:
1753 03:42:06.125647 socket[1] channel[0] rank[0] Read data eye training end
1754 03:42:06.126029
1755 03:42:06.126553 socket[1] channel[0] rank[1] Read data eye training start:
1756 03:42:06.155630 socket[1] channel[0] rank[1] Read data eye training end
1757 03:42:06.155997
1758 03:42:06.156410 socket[1] channel[0] rank[0] Write data eye training start:
1759 03:42:06.305541 socket[1] channel[0] rank[0] Write data eye training end
1760 03:42:06.306424
1761 03:42:06.306730 socket[1] channel[0] rank[1] Write data eye training start:
1762 03:42:06.307127 socket[1] channel[0] rank[1] Write data eye training end
1763 03:42:06.307720
1764 03:42:06.308239 socket[1] channel[0] Rx vref training start
1765 03:42:06.656454 socket[1] channel[0] Rx vref training end
1766 03:42:06.657230
1767 03:42:06.657491 socket[1] channel[0] rank[0] Read data eye training start:
1768 03:42:06.706943 socket[1] channel[0] rank[0] Read data eye training end
1769 03:42:06.707208
1770 03:42:06.707407 socket[1] channel[0] rank[1] Read data eye training start:
1771 03:42:06.768064 socket[1] channel[0] rank[1] Read data eye training end
1772 03:42:06.768650
1773 03:42:06.768912 socket[1] channel[0] rank[0] RxPerBitTrainingExmbistOptimize start:
1774 03:42:06.806919 socket[1] channel[0] rank[0] RxPerBitTrainingExmbistOptimize end
1775 03:42:06.807224
1776 03:42:06.807441 socket[1] channel[0] rank[1] RxPerBitTrainingExmbistOptimize start:
1777 03:42:06.807633 socket[1] channel[0] rank[1] RxPerBitTrainingExmbistOptimize end
1778 03:42:06.808093
1779 03:42:06.808320 socket[1] channel[0] Tx vref training start
1780 03:42:08.586157 socket[1] channel[0] Tx vref training end
1781 03:42:08.586915
1782 03:42:08.587157 socket[1] channel[0] rank[0] Write data eye training start:
1783 03:42:08.655681 socket[1] channel[0] rank[0] Write data eye training end
1784 03:42:08.656197
1785 03:42:08.656403 socket[1] channel[0] rank[1] Write data eye training start:
1786 03:42:08.756849 socket[1] channel[0] rank[1] Write data eye training end
1787 03:42:08.757391
1788 03:42:08.757621 //----------------------------------
1789 03:42:08.757849 sfc test rank0
1790 03:42:08.775985 [0]wdata: 0x11111111 - 0x11111111 rdata
1791 03:42:08.776253 [1]wdata: 0x11111111 - 0x11111111 rdata
1792 03:42:08.776504 [2]wdata: 0x22222222 - 0x22222222 rdata
1793 03:42:08.776797 [3]wdata: 0x22222222 - 0x22222222 rdata
1794 03:42:08.777016 [4]wdata: 0x33333333 - 0x33333333 rdata
1795 03:42:08.777207 [5]wdata: 0x33333333 - 0x33333333 rdata
1796 03:42:08.786522 [6]wdata: 0x44444444 - 0x44444444 rdata
1797 03:42:08.786807 [7]wdata: 0x44444444 - 0x44444444 rdata
1798 03:42:08.787032 [8]wdata: 0x55555555 - 0x55555555 rdata
1799 03:42:08.787256 [9]wdata: 0x55555555 - 0x55555555 rdata
1800 03:42:08.787488 [10]wdata: 0x66666666 - 0x66666666 rdata
1801 03:42:08.787708 [11]wdata: 0x66666666 - 0x66666666 rdata
1802 03:42:08.805860 [12]wdata: 0x77777777 - 0x77777777 rdata
1803 03:42:08.806110 [13]wdata: 0x77777777 - 0x77777777 rdata
1804 03:42:08.806307 [14]wdata: 0x88888888 - 0x88888888 rdata
1805 03:42:08.806500 [15]wdata: 0x88888888 - 0x88888888 rdata
1806 03:42:08.806691 [16]wdata: 0x44332211 - 0x44332211 rdata
1807 03:42:08.806880 [17]wdata: 0x88776655 - 0x88776655 rdata
1808 03:42:08.807066 sfc test rank1
1809 03:42:08.816583 [0]wdata: 0x11111111 - 0x11111111 rdata
1810 03:42:08.816814 [1]wdata: 0x11111111 - 0x11111111 rdata
1811 03:42:08.817010 [2]wdata: 0x22222222 - 0x22222222 rdata
1812 03:42:08.817199 [3]wdata: 0x22222222 - 0x22222222 rdata
1813 03:42:08.817386 [4]wdata: 0x33333333 - 0x33333333 rdata
1814 03:42:08.817572 [5]wdata: 0x33333333 - 0x33333333 rdata
1815 03:42:08.835721 [6]wdata: 0x44444444 - 0x44444444 rdata
1816 03:42:08.835966 [7]wdata: 0x44444444 - 0x44444444 rdata
1817 03:42:08.836162 [8]wdata: 0x55555555 - 0x55555555 rdata
1818 03:42:08.836352 [9]wdata: 0x55555555 - 0x55555555 rdata
1819 03:42:08.836569 [10]wdata: 0x66666666 - 0x66666666 rdata
1820 03:42:08.836824 [11]wdata: 0x66666666 - 0x66666666 rdata
1821 03:42:08.846626 [12]wdata: 0x77777777 - 0x77777777 rdata
1822 03:42:08.846841 [13]wdata: 0x77777777 - 0x77777777 rdata
1823 03:42:08.847038 [14]wdata: 0x88888888 - 0x88888888 rdata
1824 03:42:08.847231 [15]wdata: 0x88888888 - 0x88888888 rdata
1825 03:42:08.847421 [16]wdata: 0x44332211 - 0x44332211 rdata
1826 03:42:08.847608 [17]wdata: 0x88776655 - 0x88776655 rdata
1827 03:42:08.870840 //----------------------------------
1828 03:42:08.871086 **********************************************************************
1829 03:42:08.871287 Socket[1] Channel[0] DDR Init Finished!
1830 03:42:08.871479 **********************************************************************
1831 03:42:08.890547 **********************************************************************
1832 03:42:08.890816 Socket[1] Channel[1] Base:[0x40060350000] Speed:[2400]
1833 03:42:08.891014 **********************************************************************
1834 03:42:08.891205 ==========================
1835 03:42:08.891394 config parameters from SPD
1836 03:42:08.891579 ==========================
1837 03:42:08.945536 DDR PHY PLL config.....................................OK!
1838 03:42:08.945805 Top module cfg.........................................OK
1839 03:42:08.955713 ch[1] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
1840 03:42:08.955981 rank[0]: dmc_odt_config [0x603580A0]:wodt:0x1;rodt:0x2
1841 03:42:08.956206 rank[1]: dmc_odt_config [0x603580A4]:wodt:0x2;rodt:0x1
1842 03:42:08.956753 Dmc init static........................................OK
1843 03:42:08.966042 Phy init dynamic.......................................OK
1844 03:42:08.966596
1845 03:42:08.967038 [software pad_cal_0]: pvtr=0x1F; pvtn=0x1A; pvtp=0xC
1846 03:42:08.967558 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD
1847 03:42:08.968310 dimm[0] rcd init finished!
1848 03:42:08.968904 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1849 03:42:08.969379 rank[0] sdram init finished!
1850 03:42:08.976296 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1851 03:42:08.976648 rank[1] sdram init finished!
1852 03:42:08.977149 -----------------------------------------------------
1853 03:42:08.977623 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
1854 03:42:08.978131 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
1855 03:42:09.005722 -----------------------------------------------------
1856 03:42:09.006855 Dram init..............................................OK
1857 03:42:09.042402 socket[1] channel[1] rank[0] Phy gate leveling.....OK
1858 03:42:09.042725 socket[1] channel[1] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
1859 03:42:09.067853 lat_adj_start of rank 1 byte 1 is set to 0x00000001
1860 03:42:09.068184 lat_adj_start of rank 1 byte 6 is set to 0x00000001
1861 03:42:09.068715 lat_adj_start of rank 1 byte 7 is set to 0x00000001
1862 03:42:09.145112 OK
1863 03:42:09.156102 socket[1] channel[1] rank[0] Phy write leveling.....OK
1864 03:42:09.156363 socket[1] channel[1] rank[1] Phy write leveling.....OK
1865 03:42:09.156589 socket[1] channel[1] rank[0] Phy write leveling 2...OK
1866 03:42:09.156802 socket[1] channel[1] rank[1] Phy write leveling 2...OK
1867 03:42:09.186332 socket[1] channel[1] rank[0] Read data eye training start:
1868 03:42:09.186615 socket[1] channel[1] rank[0] Read data eye training end
1869 03:42:09.186817
1870 03:42:09.187010 socket[1] channel[1] rank[1] Read data eye training start:
1871 03:42:09.283641 socket[1] channel[1] rank[1] Read data eye training end
1872 03:42:09.284227
1873 03:42:09.284482 socket[1] channel[1] rank[0] Write data eye training start:
1874 03:42:09.315521 socket[1] channel[1] rank[0] Write data eye training end
1875 03:42:09.315736
1876 03:42:09.315961 socket[1] channel[1] rank[1] Write data eye training start:
1877 03:42:09.415606 socket[1] channel[1] rank[1] Write data eye training end
1878 03:42:09.416164
1879 03:42:09.416414 socket[1] channel[1] Rx vref training start
1880 03:42:09.756379 socket[1] channel[1] Rx vref training end
1881 03:42:09.757273
1882 03:42:09.757490 socket[1] channel[1] rank[0] Read data eye training start:
1883 03:42:09.826408 socket[1] channel[1] rank[0] Read data eye training end
1884 03:42:09.827063
1885 03:42:09.827270 socket[1] channel[1] rank[1] Read data eye training start:
1886 03:42:09.865716 socket[1] channel[1] rank[1] Read data eye training end
1887 03:42:09.865968
1888 03:42:09.866164 socket[1] channel[1] rank[0] RxPerBitTrainingExmbistOptimize start:
1889 03:42:09.895876 socket[1] channel[1] rank[0] RxPerBitTrainingExmbistOptimize end
1890 03:42:09.896166
1891 03:42:09.896391 socket[1] channel[1] rank[1] RxPerBitTrainingExmbistOptimize start:
1892 03:42:09.896644 socket[1] channel[1] rank[1] RxPerBitTrainingExmbistOptimize end
1893 03:42:09.896889
1894 03:42:09.897102 socket[1] channel[1] Tx vref training start
1895 03:42:11.466815 socket[1] channel[1] Tx vref training end
1896 03:42:11.467678
1897 03:42:11.467947 socket[1] channel[1] rank[0] Write data eye training start:
1898 03:42:11.536113 socket[1] channel[1] rank[0] Write data eye training end
1899 03:42:11.536390
1900 03:42:11.536705 socket[1] channel[1] rank[1] Write data eye training start:
1901 03:42:11.592639 socket[1] channel[1] rank[1] Write data eye training end
1902 03:42:11.592934
1903 03:42:11.593145 //----------------------------------
1904 03:42:11.593407 sfc test rank0
1905 03:42:11.593651 [0]wdata: 0x11111111 - 0x11111111 rdata
1906 03:42:11.593902 [1]wdata: 0x11111111 - 0x11111111 rdata
1907 03:42:11.594154 [2]wdata: 0x22222222 - 0x22222222 rdata
1908 03:42:11.614545 [3]wdata: 0x22222222 - 0x22222222 rdata
1909 03:42:11.614890 [4]wdata: 0x33333333 - 0x33333333 rdata
1910 03:42:11.615201 [5]wdata: 0x33333333 - 0x33333333 rdata
1911 03:42:11.615492 [6]wdata: 0x44444444 - 0x44444444 rdata
1912 03:42:11.615749 [7]wdata: 0x44444444 - 0x44444444 rdata
1913 03:42:11.616000 [8]wdata: 0x55555555 - 0x55555555 rdata
1914 03:42:11.637919 [9]wdata: 0x55555555 - 0x55555555 rdata
1915 03:42:11.638317 [10]wdata: 0x66666666 - 0x66666666 rdata
1916 03:42:11.638604 [11]wdata: 0x66666666 - 0x66666666 rdata
1917 03:42:11.638972 [12]wdata: 0x77777777 - 0x77777777 rdata
1918 03:42:11.639310 [13]wdata: 0x77777777 - 0x77777777 rdata
1919 03:42:11.639643 [14]wdata: 0x88888888 - 0x88888888 rdata
1920 03:42:11.658410 [15]wdata: 0x88888888 - 0x88888888 rdata
1921 03:42:11.658720 [16]wdata: 0x44332211 - 0x44332211 rdata
1922 03:42:11.658957 [17]wdata: 0x88776655 - 0x88776655 rdata
1923 03:42:11.659217 sfc test rank1
1924 03:42:11.659470 [0]wdata: 0x11111111 - 0x11111111 rdata
1925 03:42:11.659760 [1]wdata: 0x11111111 - 0x11111111 rdata
1926 03:42:11.660000 [2]wdata: 0x22222222 - 0x22222222 rdata
1927 03:42:11.680078 [3]wdata: 0x22222222 - 0x22222222 rdata
1928 03:42:11.680379 [4]wdata: 0x33333333 - 0x33333333 rdata
1929 03:42:11.680656 [5]wdata: 0x33333333 - 0x33333333 rdata
1930 03:42:11.680938 [6]wdata: 0x44444444 - 0x44444444 rdata
1931 03:42:11.681199 [7]wdata: 0x44444444 - 0x44444444 rdata
1932 03:42:11.681462 [8]wdata: 0x55555555 - 0x55555555 rdata
1933 03:42:11.702004 [9]wdata: 0x55555555 - 0x55555555 rdata
1934 03:42:11.702281 [10]wdata: 0x66666666 - 0x66666666 rdata
1935 03:42:11.702554 [11]wdata: 0x66666666 - 0x66666666 rdata
1936 03:42:11.702814 [12]wdata: 0x77777777 - 0x77777777 rdata
1937 03:42:11.703074 [13]wdata: 0x77777777 - 0x77777777 rdata
1938 03:42:11.703321 [14]wdata: 0x88888888 - 0x88888888 rdata
1939 03:42:11.734974 [15]wdata: 0x88888888 - 0x88888888 rdata
1940 03:42:11.735292 [16]wdata: 0x44332211 - 0x44332211 rdata
1941 03:42:11.735557 [17]wdata: 0x88776655 - 0x88776655 rdata
1942 03:42:11.735800 //----------------------------------
1943 03:42:11.736065 **********************************************************************
1944 03:42:11.755817 Socket[1] Channel[1] DDR Init Finished!
1945 03:42:11.756165 **********************************************************************
1946 03:42:11.756438 **********************************************************************
1947 03:42:11.756723 Socket[1] Channel[2] Base:[0x40040340000] Speed:[2400]
1948 03:42:11.769310 **********************************************************************
1949 03:42:11.769615 ==========================
1950 03:42:11.769879 config parameters from SPD
1951 03:42:11.770139 ==========================
1952 03:42:11.770410 DDR PHY PLL config.....................................OK!
1953 03:42:11.770739 Top module cfg.........................................OK
1954 03:42:11.792610 ch[2] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
1955 03:42:11.793077 rank[0]: dmc_odt_config [0x403480A0]:wodt:0x1;rodt:0x2
1956 03:42:11.793425 rank[1]: dmc_odt_config [0x403480A4]:wodt:0x2;rodt:0x1
1957 03:42:11.793825 Dmc init static........................................OK
1958 03:42:11.806303 Phy init dynamic.......................................OK
1959 03:42:11.806667
1960 03:42:11.806989 [software pad_cal_0]: pvtr=0x1F; pvtn=0x1C; pvtp=0xC
1961 03:42:11.807299 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD
1962 03:42:11.859005 dimm[0] rcd init finished!
1963 03:42:11.859337 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1964 03:42:11.859598 rank[0] sdram init finished!
1965 03:42:11.875742 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1966 03:42:11.876054 rank[1] sdram init finished!
1967 03:42:11.876297 -----------------------------------------------------
1968 03:42:11.876579 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
1969 03:42:11.876900 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
1970 03:42:11.909149 -----------------------------------------------------
1971 03:42:11.909430 Dram init..............................................OK
1972 03:42:11.909669 socket[1] channel[2] rank[0] Phy gate leveling.....OK
1973 03:42:11.909920 socket[1] channel[2] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
1974 03:42:11.928490 lat_adj_start of rank 1 byte 1 is set to 0x00000001
1975 03:42:11.928842 lat_adj_start of rank 1 byte 2 is set to 0x00000001
1976 03:42:11.929075 lat_adj_start of rank 1 byte 3 is set to 0x00000001
1977 03:42:11.929353 lat_adj_start of rank 1 byte 4 is set to 0x00000001
1978 03:42:11.929632 lat_adj_start of rank 1 byte 5 is set to 0x00000001
1979 03:42:11.956064 lat_adj_start of rank 1 byte 6 is set to 0x00000001
1980 03:42:11.956376 lat_adj_start of rank 1 byte 7 is set to 0x00000001
1981 03:42:11.989840 OK
1982 03:42:11.990217 socket[1] channel[2] rank[0] Phy write leveling.....OK
1983 03:42:11.990515 socket[1] channel[2] rank[1] Phy write leveling.....OK
1984 03:42:12.016026 socket[1] channel[2] rank[0] Phy write leveling 2...OK
1985 03:42:12.016358 socket[1] channel[2] rank[1] Phy write leveling 2...OK
1986 03:42:12.016766 socket[1] channel[2] rank[0] Read data eye training start:
1987 03:42:12.065955 socket[1] channel[2] rank[0] Read data eye training end
1988 03:42:12.066257
1989 03:42:12.066510 socket[1] channel[2] rank[1] Read data eye training start:
1990 03:42:12.145852 socket[1] channel[2] rank[1] Read data eye training end
1991 03:42:12.146267
1992 03:42:12.146600 socket[1] channel[2] rank[0] Write data eye training start:
1993 03:42:12.195684 socket[1] channel[2] rank[0] Write data eye training end
1994 03:42:12.196135
1995 03:42:12.196584 socket[1] channel[2] rank[1] Write data eye training start:
1996 03:42:12.256377 socket[1] channel[2] rank[1] Write data eye training end
1997 03:42:12.256730
1998 03:42:12.256994 socket[1] channel[2] Rx vref training start
1999 03:42:12.615630 socket[1] channel[2] Rx vref training end
2000 03:42:12.616367
2001 03:42:12.616799 socket[1] channel[2] rank[0] Read data eye training start:
2002 03:42:12.685766 socket[1] channel[2] rank[0] Read data eye training end
2003 03:42:12.686416
2004 03:42:12.686721 socket[1] channel[2] rank[1] Read data eye training start:
2005 03:42:12.735883 socket[1] channel[2] rank[1] Read data eye training end
2006 03:42:12.736171
2007 03:42:12.736779 socket[1] channel[2] rank[0] RxPerBitTrainingExmbistOptimize start:
2008 03:42:12.800642 socket[1] channel[2] rank[0] RxPerBitTrainingExmbistOptimize end
2009 03:42:12.801436
2010 03:42:12.801730 socket[1] channel[2] rank[1] RxPerBitTrainingExmbistOptimize start:
2011 03:42:12.802002 socket[1] channel[2] rank[1] RxPerBitTrainingExmbistOptimize end
2012 03:42:12.802265
2013 03:42:12.802502 socket[1] channel[2] Tx vref training start
2014 03:42:14.505733 socket[1] channel[2] Tx vref training end
2015 03:42:14.506269
2016 03:42:14.506553 socket[1] channel[2] rank[0] Write data eye training start:
2017 03:42:14.607131 socket[1] channel[2] rank[0] Write data eye training end
2018 03:42:14.607490
2019 03:42:14.607836 socket[1] channel[2] rank[1] Write data eye training start:
2020 03:42:14.635756 socket[1] channel[2] rank[1] Write data eye training end
2021 03:42:14.636134
2022 03:42:14.636489 //----------------------------------
2023 03:42:14.636827 sfc test rank0
2024 03:42:14.656767 [0]wdata: 0x11111111 - 0x11111111 rdata
2025 03:42:14.657062 [1]wdata: 0x11111111 - 0x11111111 rdata
2026 03:42:14.657375 [2]wdata: 0x22222222 - 0x22222222 rdata
2027 03:42:14.657646 [3]wdata: 0x22222222 - 0x22222222 rdata
2028 03:42:14.657986 [4]wdata: 0x33333333 - 0x33333333 rdata
2029 03:42:14.658260 [5]wdata: 0x33333333 - 0x33333333 rdata
2030 03:42:14.679700 [6]wdata: 0x44444444 - 0x44444444 rdata
2031 03:42:14.680030 [7]wdata: 0x44444444 - 0x44444444 rdata
2032 03:42:14.680310 [8]wdata: 0x55555555 - 0x55555555 rdata
2033 03:42:14.680623 [9]wdata: 0x55555555 - 0x55555555 rdata
2034 03:42:14.680901 [10]wdata: 0x66666666 - 0x66666666 rdata
2035 03:42:14.681169 [11]wdata: 0x66666666 - 0x66666666 rdata
2036 03:42:14.701750 [12]wdata: 0x77777777 - 0x77777777 rdata
2037 03:42:14.702074 [13]wdata: 0x77777777 - 0x77777777 rdata
2038 03:42:14.702343 [14]wdata: 0x88888888 - 0x88888888 rdata
2039 03:42:14.702643 [15]wdata: 0x88888888 - 0x88888888 rdata
2040 03:42:14.702907 [16]wdata: 0x44332211 - 0x44332211 rdata
2041 03:42:14.703163 [17]wdata: 0x88776655 - 0x88776655 rdata
2042 03:42:14.703417 sfc test rank1
2043 03:42:14.723444 [0]wdata: 0x11111111 - 0x11111111 rdata
2044 03:42:14.723731 [1]wdata: 0x11111111 - 0x11111111 rdata
2045 03:42:14.724110 [2]wdata: 0x22222222 - 0x22222222 rdata
2046 03:42:14.724386 [3]wdata: 0x22222222 - 0x22222222 rdata
2047 03:42:14.724717 [4]wdata: 0x33333333 - 0x33333333 rdata
2048 03:42:14.724953 [5]wdata: 0x33333333 - 0x33333333 rdata
2049 03:42:14.746012 [6]wdata: 0x44444444 - 0x44444444 rdata
2050 03:42:14.746302 [7]wdata: 0x44444444 - 0x44444444 rdata
2051 03:42:14.746561 [8]wdata: 0x55555555 - 0x55555555 rdata
2052 03:42:14.746796 [9]wdata: 0x55555555 - 0x55555555 rdata
2053 03:42:14.747033 [10]wdata: 0x66666666 - 0x66666666 rdata
2054 03:42:14.747231 [11]wdata: 0x66666666 - 0x66666666 rdata
2055 03:42:14.766025 [12]wdata: 0x77777777 - 0x77777777 rdata
2056 03:42:14.766383 [13]wdata: 0x77777777 - 0x77777777 rdata
2057 03:42:14.766705 [14]wdata: 0x88888888 - 0x88888888 rdata
2058 03:42:14.766955 [15]wdata: 0x88888888 - 0x88888888 rdata
2059 03:42:14.767264 [16]wdata: 0x44332211 - 0x44332211 rdata
2060 03:42:14.767587 [17]wdata: 0x88776655 - 0x88776655 rdata
2061 03:42:14.789243 //----------------------------------
2062 03:42:14.789637 **********************************************************************
2063 03:42:14.789977 Socket[1] Channel[2] DDR Init Finished!
2064 03:42:14.790276 **********************************************************************
2065 03:42:14.811781 **********************************************************************
2066 03:42:14.812079 Socket[1] Channel[3] Base:[0x40040350000] Speed:[2400]
2067 03:42:14.812346 **********************************************************************
2068 03:42:14.812651 ==========================
2069 03:42:14.812918 config parameters from SPD
2070 03:42:14.813207 ==========================
2071 03:42:14.833887 DDR PHY PLL config.....................................OK!
2072 03:42:14.834223 Top module cfg.........................................OK
2073 03:42:14.834535 ch[3] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
2074 03:42:14.834816 rank[0]: dmc_odt_config [0x403580A0]:wodt:0x1;rodt:0x2
2075 03:42:14.846591 rank[1]: dmc_odt_config [0x403580A4]:wodt:0x2;rodt:0x1
2076 03:42:14.846880 Dmc init static........................................OK
2077 03:42:14.847115 Phy init dynamic.......................................OK
2078 03:42:14.847335
2079 03:42:14.847553 [software pad_cal_0]: pvtr=0x1F; pvtn=0x1B; pvtp=0xC
2080 03:42:14.869085 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD
2081 03:42:14.869362 dimm[0] rcd init finished!
2082 03:42:14.869583 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
2083 03:42:14.869807 rank[0] sdram init finished!
2084 03:42:14.891200 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
2085 03:42:14.891565 rank[1] sdram init finished!
2086 03:42:14.891841 -----------------------------------------------------
2087 03:42:14.892160 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
2088 03:42:14.892451 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
2089 03:42:14.916197 -----------------------------------------------------
2090 03:42:14.916621 Dram init..............................................OK
2091 03:42:14.962363 socket[1] channel[3] rank[0] Phy gate leveling.....OK
2092 03:42:14.962608 socket[1] channel[3] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
2093 03:42:14.982312 lat_adj_start of rank 1 byte 1 is set to 0x00000001
2094 03:42:14.982566 lat_adj_start of rank 1 byte 2 is set to 0x00000001
2095 03:42:14.982779 lat_adj_start of rank 1 byte 3 is set to 0x00000001
2096 03:42:14.982978 lat_adj_start of rank 1 byte 4 is set to 0x00000001
2097 03:42:14.983467 lat_adj_start of rank 1 byte 5 is set to 0x00000001
2098 03:42:15.005994 lat_adj_start of rank 1 byte 6 is set to 0x00000001
2099 03:42:15.006238 lat_adj_start of rank 1 byte 7 is set to 0x00000001
2100 03:42:15.042335 OK
2101 03:42:15.042573 socket[1] channel[3] rank[0] Phy write leveling.....OK
2102 03:42:15.042779 socket[1] channel[3] rank[1] Phy write leveling.....OK
2103 03:42:15.075213 socket[1] channel[3] rank[0] Phy write leveling 2...OK
2104 03:42:15.075558 socket[1] channel[3] rank[1] Phy write leveling 2...OK
2105 03:42:15.075816 socket[1] channel[3] rank[0] Read data eye training start:
2106 03:42:15.117505 socket[1] channel[3] rank[0] Read data eye training end
2107 03:42:15.117783
2108 03:42:15.118024 socket[1] channel[3] rank[1] Read data eye training start:
2109 03:42:15.196843 socket[1] channel[3] rank[1] Read data eye training end
2110 03:42:15.197118
2111 03:42:15.197325 socket[1] channel[3] rank[0] Write data eye training start:
2112 03:42:15.278393 socket[1] channel[3] rank[0] Write data eye training end
2113 03:42:15.278768
2114 03:42:15.278976 socket[1] channel[3] rank[1] Write data eye training start:
2115 03:42:15.307376 socket[1] channel[3] rank[1] Write data eye training end
2116 03:42:15.307626
2117 03:42:15.307831 socket[1] channel[3] Rx vref training start
2118 03:42:15.737765 socket[1] channel[3] Rx vref training end
2119 03:42:15.738076
2120 03:42:15.738326 socket[1] channel[3] rank[0] Read data eye training start:
2121 03:42:15.738532 socket[1] channel[3] rank[0] Read data eye training end
2122 03:42:15.738733
2123 03:42:15.738934 socket[1] channel[3] rank[1] Read data eye training start:
2124 03:42:15.807568 socket[1] channel[3] rank[1] Read data eye training end
2125 03:42:15.807805
2126 03:42:15.808009 socket[1] channel[3] rank[0] RxPerBitTrainingExmbistOptimize start:
2127 03:42:15.808208 socket[1] channel[3] rank[0] RxPerBitTrainingExmbistOptimize end
2128 03:42:15.808404
2129 03:42:15.829612 socket[1] channel[3] rank[1] RxPerBitTrainingExmbistOptimize start:
2130 03:42:15.829840 socket[1] channel[3] rank[1] RxPerBitTrainingExmbistOptimize end
2131 03:42:15.830046
2132 03:42:15.830252 socket[1] channel[3] Tx vref training start
2133 03:42:17.396008 socket[1] channel[3] Tx vref training end
2134 03:42:17.396364
2135 03:42:17.396583 socket[1] channel[3] rank[0] Write data eye training start:
2136 03:42:17.475896 socket[1] channel[3] rank[0] Write data eye training end
2137 03:42:17.476125
2138 03:42:17.476321 socket[1] channel[3] rank[1] Write data eye training start:
2139 03:42:17.536023 socket[1] channel[3] rank[1] Write data eye training end
2140 03:42:17.536262
2141 03:42:17.536469 //----------------------------------
2142 03:42:17.536714 sfc test rank0
2143 03:42:17.536913 [0]wdata: 0x11111111 - 0x11111111 rdata
2144 03:42:17.537109 [1]wdata: 0x11111111 - 0x11111111 rdata
2145 03:42:17.537302 [2]wdata: 0x22222222 - 0x22222222 rdata
2146 03:42:17.553422 [3]wdata: 0x22222222 - 0x22222222 rdata
2147 03:42:17.553659 [4]wdata: 0x33333333 - 0x33333333 rdata
2148 03:42:17.553865 [5]wdata: 0x33333333 - 0x33333333 rdata
2149 03:42:17.554103 [6]wdata: 0x44444444 - 0x44444444 rdata
2150 03:42:17.554306 [7]wdata: 0x44444444 - 0x44444444 rdata
2151 03:42:17.554502 [8]wdata: 0x55555555 - 0x55555555 rdata
2152 03:42:17.577894 [9]wdata: 0x55555555 - 0x55555555 rdata
2153 03:42:17.578174 [10]wdata: 0x66666666 - 0x66666666 rdata
2154 03:42:17.578382 [11]wdata: 0x66666666 - 0x66666666 rdata
2155 03:42:17.595938 [12]wdata: 0x77777777 - 0x77777777 rdata
2156 03:42:17.596175 [13]wdata: 0x77777777 - 0x77777777 rdata
2157 03:42:17.596383 [14]wdata: 0x88888888 - 0x88888888 rdata
2158 03:42:17.596609 [15]wdata: 0x88888888 - 0x88888888 rdata
2159 03:42:17.596827 [16]wdata: 0x44332211 - 0x44332211 rdata
2160 03:42:17.597023 [17]wdata: 0x88776655 - 0x88776655 rdata
2161 03:42:17.597217 sfc test rank1
2162 03:42:17.616613 [0]wdata: 0x11111111 - 0x11111111 rdata
2163 03:42:17.616868 [1]wdata: 0x11111111 - 0x11111111 rdata
2164 03:42:17.617076 [2]wdata: 0x22222222 - 0x22222222 rdata
2165 03:42:17.617275 [3]wdata: 0x22222222 - 0x22222222 rdata
2166 03:42:17.617470 [4]wdata: 0x33333333 - 0x33333333 rdata
2167 03:42:17.617665 [5]wdata: 0x33333333 - 0x33333333 rdata
2168 03:42:17.629894 [6]wdata: 0x44444444 - 0x44444444 rdata
2169 03:42:17.630148 [7]wdata: 0x44444444 - 0x44444444 rdata
2170 03:42:17.630355 [8]wdata: 0x55555555 - 0x55555555 rdata
2171 03:42:17.630556 [9]wdata: 0x55555555 - 0x55555555 rdata
2172 03:42:17.630754 [10]wdata: 0x66666666 - 0x66666666 rdata
2173 03:42:17.630949 [11]wdata: 0x66666666 - 0x66666666 rdata
2174 03:42:17.656417 [12]wdata: 0x77777777 - 0x77777777 rdata
2175 03:42:17.656748 [13]wdata: 0x77777777 - 0x77777777 rdata
2176 03:42:17.656994 [14]wdata: 0x88888888 - 0x88888888 rdata
2177 03:42:17.657232 [15]wdata: 0x88888888 - 0x88888888 rdata
2178 03:42:17.657539 [16]wdata: 0x44332211 - 0x44332211 rdata
2179 03:42:17.657773 [17]wdata: 0x88776655 - 0x88776655 rdata
2180 03:42:17.673675 //----------------------------------
2181 03:42:17.673993 **********************************************************************
2182 03:42:17.674267 Socket[1] Channel[3] DDR Init Finished!
2183 03:42:17.674528 **********************************************************************
2184 03:42:17.705798 ========================================================================================
2185 03:42:17.717711 | socekt 0 |
2186 03:42:17.718038 ========================================================================================
2187 03:42:17.718311 | Slot | Channel 0 | Channel 1 | Channel 2 | Channel 3 |
2188 03:42:17.735921 ========================================================================================
2189 03:42:17.736227 | 0 | Samsung | Samsung | Samsung | Samsung |
2190 03:42:17.736527 | | Montage | Montage | Montage | Montage |
2191 03:42:17.750130 | | 32GB(2RX4) | 32GB(2RX4) | 32GB(2RX4) | 32GB(2RX4) |
2192 03:42:17.750415 | | 2400 | 2400 | 2400 | 2400 |
2193 03:42:17.750684 | | ww282017 | ww282017 | ww282017 | ww282017 |
2194 03:42:17.771997 | | M393A4K40BB1-CRC | M393A4K40BB1-CRC | M393A4K40BB1-CRC | M393A4K40BB1-CRC |
2195 03:42:17.772259 | | | | | |
2196 03:42:17.772535 ----------------------------------------------------------------------------------------
2197 03:42:17.793884 | 1 | NO DIMM | NO DIMM | NO DIMM | NO DIMM |
2198 03:42:17.794142 | | | | | |
2199 03:42:17.820396 | | | | | |
2200 03:42:17.820730 | | | | | |
2201 03:42:17.821022 | | | | | |
2202 03:42:17.835767 | | | | | |
2203 03:42:17.836083 | | | | | |
2204 03:42:17.836368 ----------------------------------------------------------------------------------------
2205 03:42:17.856052 | 2 | NO DIMM | NO DIMM | NO DIMM | NO DIMM |
2206 03:42:17.920398 | | | | | |
2207 03:42:17.920723 | | | | | |
2208 03:42:17.920965 | | | | | |
2209 03:42:17.936754 | | | | | |
2210 03:42:17.937035 | | | | | |
2211 03:42:17.937291 | | | | | |
2212 03:42:17.953685 ----------------------------------------------------------------------------------------
2213 03:42:17.953993 ========================================================================================
2214 03:42:17.954231 | socekt 1 |
2215 03:42:17.965979 ========================================================================================
2216 03:42:17.966276 | Slot | Channel 0 | Channel 1 | Channel 2 | Channel 3 |
2217 03:42:17.966533 ========================================================================================
2218 03:42:17.976131 | 0 | Samsung | Samsung | Samsung | Samsung |
2219 03:42:17.976398 | | Montage | Montage | Montage | Montage |
2220 03:42:17.987833 | | 32GB(2RX4) | 32GB(2RX4) | 32GB(2RX4) | 32GB(2RX4) |
2221 03:42:17.988156 | | 2400 | 2400 | 2400 | 2400 |
2222 03:42:17.988426 | | ww282017 | ww282017 | ww282017 | ww282017 |
2223 03:42:18.005751 | | M393A4K40BB1-CRC | M393A4K40BB1-CRC | M393A4K40BB1-CRC | M393A4K40BB1-CRC |
2224 03:42:18.006061 | | | | | |
2225 03:42:18.006339 ----------------------------------------------------------------------------------------
2226 03:42:18.025675 | 1 | NO DIMM | NO DIMM | NO DIMM | NO DIMM |
2227 03:42:18.026023 | | | | | |
2228 03:42:18.026307 | | | | | |
2229 03:42:18.059755 | | | | | |
2230 03:42:18.060072 | | | | | |
2231 03:42:18.131618 | | | | | |
2232 03:42:18.131942 | | | | | |
2233 03:42:18.132206 ----------------------------------------------------------------------------------------
2234 03:42:18.146231 | 2 | NO DIMM | NO DIMM | NO DIMM | NO DIMM |
2235 03:42:18.146488 | | | | | |
2236 03:42:18.146735 | | | | | |
2237 03:42:18.159046 | | | | | |
2238 03:42:18.159366 | | | | | |
2239 03:42:18.159605 | | | | | |
2240 03:42:18.176896 | | | | | |
2241 03:42:18.177204 ----------------------------------------------------------------------------------------
2242 03:42:18.177484 socket[0] channel[0] rank[0] memory clean start.
2243 03:42:18.177757 socket[0] channel[1] rank[0] memory clean start.
2244 03:42:18.187246 socket[0] channel[2] rank[0] memory clean start.
2245 03:42:18.187579 socket[0] channel[3] rank[0] memory clean start.
2246 03:42:18.187855 socket[1] channel[0] rank[0] memory clean start.
2247 03:42:18.188148 socket[1] channel[1] rank[0] memory clean start.
2248 03:42:18.188408 socket[1] channel[2] rank[0] memory clean start.
2249 03:42:18.206665 socket[1] channel[3] rank[0] memory clean start.
2250 03:42:19.195922 all rank[0] memory clean ok!
2251 03:42:19.196386
2252 03:42:19.196663 socket[0] channel[0] rank[0] memory clean read start.
2253 03:42:19.196987 socket[0] channel[1] rank[0] memory clean read start.
2254 03:42:19.197247 socket[0] channel[2] rank[0] memory clean read start.
2255 03:42:19.197828 socket[0] channel[3] rank[0] memory clean read start.
2256 03:42:19.258096 socket[1] channel[0] rank[0] memory clean read start.
2257 03:42:19.258399 socket[1] channel[1] rank[0] memory clean read start.
2258 03:42:19.258634 socket[1] channel[2] rank[0] memory clean read start.
2259 03:42:19.258871 socket[1] channel[3] rank[0] memory clean read start.
2260 03:42:20.250112 all rank[0] memory clean read ok!
2261 03:42:20.250917
2262 03:42:20.251250 socket[0] channel[0] rank[1] memory clean start.
2263 03:42:20.251527 socket[0] channel[1] rank[1] memory clean start.
2264 03:42:20.251864 socket[0] channel[2] rank[1] memory clean start.
2265 03:42:20.252133 socket[0] channel[3] rank[1] memory clean start.
2266 03:42:20.279454 socket[1] channel[0] rank[1] memory clean start.
2267 03:42:20.279793 socket[1] channel[1] rank[1] memory clean start.
2268 03:42:20.280132 socket[1] channel[2] rank[1] memory clean start.
2269 03:42:20.280407 socket[1] channel[3] rank[1] memory clean start.
2270 03:42:21.303992 all rank[1] memory clean ok!
2271 03:42:21.304476
2272 03:42:21.304878 socket[0] channel[0] rank[1] memory clean read start.
2273 03:42:21.305200 socket[0] channel[1] rank[1] memory clean read start.
2274 03:42:21.305440 socket[0] channel[2] rank[1] memory clean read start.
2275 03:42:21.305743 socket[0] channel[3] rank[1] memory clean read start.
2276 03:42:21.325742 socket[1] channel[0] rank[1] memory clean read start.
2277 03:42:21.326169 socket[1] channel[1] rank[1] memory clean read start.
2278 03:42:21.326481 socket[1] channel[2] rank[1] memory clean read start.
2279 03:42:21.326800 socket[1] channel[3] rank[1] memory clean read start.
2280 03:42:22.346059 all rank[1] memory clean read ok!
2281 03:42:22.346567
2282 03:42:22.379202 RAM Diagnose or not ?
2283 03:42:22.379497 (Press 'Ctrl+t' or 'Ctrl+T' to Begin Memory Diagnose)
2284 03:42:22.379808 Now wait for 3 seconds...
2285 03:42:22.380119 Not Press 'Ctrl+t' or 'Ctrl+T', The RAM Diagnose Exit
2286 03:42:22.380368 Start config DAW.
2287 03:42:22.380720 Record Interrupts
2288 03:42:22.401075 Interrupt Status:[SocketId: 0] [DieId: 1] [DDRC0] = 0xB0111168
2289 03:42:22.401370 Interrupt Status:[SocketId: 0] [DieId: 1] [DDRC1] = 0xA0311168
2290 03:42:22.401609 Interrupt Status:[SocketId: 0] [DieId: 3] [DDRC0] = 0x10201051
2291 03:42:22.401821 Interrupt Status:[SocketId: 0] [DieId: 3] [DDRC1] = 0x301164
2292 03:42:22.422873 Interrupt Status:[SocketId: 0] [DieId: 1] [RASC0] = 0x16223
2293 03:42:22.423160 Interrupt Status:[SocketId: 0] [DieId: 1] [RASC1] = 0x403101
2294 03:42:22.423429 Interrupt Status:[SocketId: 0] [DieId: 3] [RASC0] = 0x613010
2295 03:42:22.423657 Interrupt Status:[SocketId: 0] [DieId: 3] [RASC1] = 0xB07112
2296 03:42:22.444834 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS0_INT0] = 0x8A
2297 03:42:22.445109 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS1_INT0] = 0x10
2298 03:42:22.445385 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS2_INT0] = 0x220
2299 03:42:22.445618 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS3_INT0] = 0x608
2300 03:42:22.494540 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS4_INT0] = 0x42
2301 03:42:22.494881 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS5_INT0] = 0x48
2302 03:42:22.510184 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS6_INT0] = 0x4
2303 03:42:22.510513 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS0_INT1] = 0x8089
2304 03:42:22.510795 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS1_INT1] = 0x1980
2305 03:42:22.511100 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS2_INT1] = 0x4A00C0
2306 03:42:22.526008 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS3_INT1] = 0x42A40C
2307 03:42:22.526331 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS5_INT1] = 0x404
2308 03:42:22.526616 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS6_INT1] = 0x7940
2309 03:42:22.526925 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS0_INT0] = 0x6
2310 03:42:22.541236 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS1_INT0] = 0x16
2311 03:42:22.541536 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS2_INT0] = 0x30
2312 03:42:22.541802 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS3_INT0] = 0x18
2313 03:42:22.542119 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS4_INT0] = 0x2
2314 03:42:22.556886 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS5_INT0] = 0x40
2315 03:42:22.557166 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS0_INT1] = 0x1400
2316 03:42:22.557447 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS1_INT1] = 0x22C4
2317 03:42:22.557675 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS2_INT1] = 0xC044
2318 03:42:22.575895 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS3_INT1] = 0x80820
2319 03:42:22.576179 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS4_INT1] = 0x904A
2320 03:42:22.576450 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS5_INT1] = 0x906
2321 03:42:22.576771 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS6_INT1] = 0x181
2322 03:42:22.586879 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS0_INT0] = 0x68
2323 03:42:22.587197 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS1_INT0] = 0xF4
2324 03:42:22.587451 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS2_INT0] = 0x7C
2325 03:42:22.587684 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS0_INT1] = 0x3CBC
2326 03:42:22.608764 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS1_INT1] = 0x2010
2327 03:42:22.609092 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS2_INT1] = 0x41
2328 03:42:22.609336 Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS0_INT0] = 0xEC
2329 03:42:22.609695 Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS1_INT0] = 0x3B
2330 03:42:22.641762 Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS2_INT0] = 0xF8
2331 03:42:22.642108 Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS0_INT1] = 0xB144
2332 03:42:22.642389 Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS1_INT1] = 0x316D
2333 03:42:22.642714 Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS2_INT1] = 0xE9B1
2334 03:42:22.663679 Interrupt Status:[SocketId: 0] [DieId: 1] [HHA0] = 0x88030
2335 03:42:22.664027 Interrupt Status:[SocketId: 0] [DieId: 1] [HHA1] = 0x400
2336 03:42:22.664347 Interrupt Status:[SocketId: 0] [DieId: 3] [HHA0] = 0x9121
2337 03:42:22.664653 Interrupt Status:[SocketId: 0] [DieId: 3] [HHA1] = 0x80200
2338 03:42:22.686278 Interrupt Status:[SocketId: 0] [DieId: 1] [LLC0] = 0x2A0
2339 03:42:22.686566 Interrupt Status:[SocketId: 0] [DieId: 1] [LLC1] = 0xA80
2340 03:42:22.686891 Interrupt Status:[SocketId: 0] [DieId: 1] [LLC3] = 0x20000
2341 03:42:22.687176 Interrupt Status:[SocketId: 0] [DieId: 3] [LLC0] = 0x400
2342 03:42:22.707657 Interrupt Status:[SocketId: 0] [DieId: 3] [LLC1] = 0x4020
2343 03:42:22.708028 Interrupt Status:[SocketId: 0] [DieId: 3] [LLC2] = 0x10001
2344 03:42:22.708403 Interrupt Status:[SocketId: 0] [DieId: 3] [LLC3] = 0x1280
2345 03:42:22.708800 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_CLUSTER0] = 0x3
2346 03:42:22.728395 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_CLUSTER1] = 0x4
2347 03:42:22.728968 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_CLUSTER2] = 0x3
2348 03:42:22.729320 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_CLUSTER3] = 0x2
2349 03:42:22.729619 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_POE] = 0x7
2350 03:42:22.748330 Interrupt Status:[SocketId: 0] [DieId: 3] [AA_CLUSTER2] = 0x4
2351 03:42:22.748951 Interrupt Status:[SocketId: 0] [DieId: 3] [AA_CLUSTER3] = 0x2
2352 03:42:22.749316 Interrupt Status:[SocketId: 0] [DieId: 3] [AA_POE] = 0x7
2353 03:42:22.767704 Interrupt Status:[SocketId: 0] [DieId: 0] [AA_SAS] = 0x3
2354 03:42:22.768257 Interrupt Status:[SocketId: 0] [DieId: 2] [AA_ALG] = 0x3
2355 03:42:22.768807 Interrupt Status:[SocketId: 0] [DieId: 2] [AA_PCIE] = 0x2
2356 03:42:22.769239 Interrupt Status:[SocketId: 0] [DieId: 2] [AA_SAS] = 0x1
2357 03:42:22.789265 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_SRAM] = 0x8
2358 03:42:22.789743 Interrupt Status:[SocketId: 0] [DieId: 3] [AA_SRAM] = 0xEB
2359 03:42:22.790239 Interrupt Status:[SocketId: 1] [DieId: 1] [DDRC0] = 0x9111115C
2360 03:42:22.790699 Interrupt Status:[SocketId: 1] [DieId: 1] [DDRC1] = 0xE1501004
2361 03:42:22.811057 Interrupt Status:[SocketId: 1] [DieId: 3] [DDRC0] = 0xC1001139
2362 03:42:22.811587 Interrupt Status:[SocketId: 1] [DieId: 3] [DDRC1] = 0xA0111040
2363 03:42:22.812075 Interrupt Status:[SocketId: 1] [DieId: 1] [RASC0] = 0xA10321
2364 03:42:22.812647 Interrupt Status:[SocketId: 1] [DieId: 1] [RASC1] = 0x207222
2365 03:42:22.830952 Interrupt Status:[SocketId: 1] [DieId: 3] [RASC0] = 0x31A023
2366 03:42:22.831502 Interrupt Status:[SocketId: 1] [DieId: 3] [RASC1] = 0x6110
2367 03:42:22.831982 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS0_INT0] = 0x60
2368 03:42:22.832580 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS1_INT0] = 0x20
2369 03:42:22.853024 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS2_INT0] = 0x80A
2370 03:42:22.853305 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS3_INT0] = 0x413
2371 03:42:22.853515 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS6_INT0] = 0x4
2372 03:42:22.853867 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS0_INT1] = 0x7E4
2373 03:42:22.874864 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS1_INT1] = 0x305
2374 03:42:22.875217 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS2_INT1] = 0x124800
2375 03:42:22.875578 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS3_INT1] = 0x823060
2376 03:42:22.897416 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS4_INT1] = 0x201
2377 03:42:22.897667 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS5_INT1] = 0xB5E
2378 03:42:22.915705 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS6_INT1] = 0x1D55
2379 03:42:22.915943 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS0_INT0] = 0x2
2380 03:42:22.916182 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS2_INT0] = 0x800
2381 03:42:22.916388 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS4_INT0] = 0x84
2382 03:42:22.929494 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS5_INT0] = 0x20
2383 03:42:22.929748 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS6_INT0] = 0xC
2384 03:42:22.929979 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS0_INT1] = 0x100
2385 03:42:22.930193 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS1_INT1] = 0x5CCD
2386 03:42:22.951345 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS2_INT1] = 0x2CACC
2387 03:42:22.951581 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS3_INT1] = 0x58388
2388 03:42:22.951836 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS4_INT1] = 0x4180
2389 03:42:22.952039 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS5_INT1] = 0x882
2390 03:42:22.973250 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS6_INT1] = 0xB104
2391 03:42:22.973516 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS0_INT0] = 0x60
2392 03:42:22.973734 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS1_INT0] = 0x3C
2393 03:42:22.973963 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS2_INT0] = 0xC8
2394 03:42:22.995364 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS0_INT1] = 0x810
2395 03:42:22.995602 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS1_INT1] = 0x3043
2396 03:42:22.995858 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS2_INT1] = 0x402D
2397 03:42:22.996064 Interrupt Status:[SocketId: 1] [DieId: 2] [I_CS0_INT0] = 0x8
2398 03:42:23.026663 Interrupt Status:[SocketId: 1] [DieId: 2] [I_CS2_INT0] = 0xE
2399 03:42:23.026902 Interrupt Status:[SocketId: 1] [DieId: 2] [I_CS0_INT1] = 0xA05C
2400 03:42:23.027164 Interrupt Status:[SocketId: 1] [DieId: 2] [I_CS1_INT1] = 0x4940
2401 03:42:23.027395 Interrupt Status:[SocketId: 1] [DieId: 2] [I_CS2_INT1] = 0x2D0D
2402 03:42:23.046667 Interrupt Status:[SocketId: 1] [DieId: 1] [HHA0] = 0xC019
2403 03:42:23.046950 Interrupt Status:[SocketId: 1] [DieId: 1] [HHA1] = 0x8A041
2404 03:42:23.047159 Interrupt Status:[SocketId: 1] [DieId: 3] [HHA0] = 0x30
2405 03:42:23.047412 Interrupt Status:[SocketId: 1] [DieId: 3] [HHA1] = 0x48002
2406 03:42:23.071562 Interrupt Status:[SocketId: 1] [DieId: 1] [LLC0] = 0x8220
2407 03:42:23.071804 Interrupt Status:[SocketId: 1] [DieId: 1] [LLC3] = 0x20
2408 03:42:23.072038 Interrupt Status:[SocketId: 1] [DieId: 3] [LLC0] = 0x1000
2409 03:42:23.072253 Interrupt Status:[SocketId: 1] [DieId: 3] [LLC2] = 0x20
2410 03:42:23.087875 Interrupt Status:[SocketId: 1] [DieId: 1] [AA_CLUSTER2] = 0x4
2411 03:42:23.088114 Interrupt Status:[SocketId: 1] [DieId: 1] [AA_CLUSTER3] = 0x3
2412 03:42:23.088394 Interrupt Status:[SocketId: 1] [DieId: 1] [AA_POE] = 0x6
2413 03:42:23.109858 Interrupt Status:[SocketId: 1] [DieId: 3] [AA_CLUSTER1] = 0x2
2414 03:42:23.110139 Interrupt Status:[SocketId: 1] [DieId: 3] [AA_CLUSTER3] = 0x1
2415 03:42:23.110348 Interrupt Status:[SocketId: 1] [DieId: 3] [AA_POE] = 0x2
2416 03:42:23.110595 Interrupt Status:[SocketId: 1] [DieId: 0] [AA_ALG] = 0x1
2417 03:42:23.168557 Interrupt Status:[SocketId: 1] [DieId: 0] [AA_PCIE] = 0x2
2418 03:42:23.168906 Interrupt Status:[SocketId: 1] [DieId: 2] [AA_ALG] = 0x1
2419 03:42:23.185802 Interrupt Status:[SocketId: 1] [DieId: 2] [AA_SAS] = 0x1
2420 03:42:23.186042 Interrupt Status:[SocketId: 1] [DieId: 1] [AA_SRAM] = 0xFD
2421 03:42:23.186275 Interrupt Status:[SocketId: 1] [DieId: 3] [AA_SRAM] = 0x7B
2422 03:42:23.186490 Clear Interrupts
2423 03:42:23.186692 Clear DDRC
2424 03:42:23.186934 Clear RASC
2425 03:42:23.187130 Clear CS
2426 03:42:23.187372 Clear SLLC
2427 03:42:23.187563 Clear HHA
2428 03:42:23.187779 Clear LLC
2429 03:42:23.187980 Clear AA
2430 03:42:23.197030 Clear SRAM
2431 03:42:23.197308 Clear DDRC
2432 03:42:23.197516 Clear RASC
2433 03:42:23.197763 Clear CS
2434 03:42:23.197963 Clear SLLC
2435 03:42:23.198200 Clear HHA
2436 03:42:23.198397 Clear LLC
2437 03:42:23.198626 Clear AA
2438 03:42:23.198845 Clear SRAM
2439 03:42:23.199036 Clear Interrupt End
2440 03:42:23.199276 Enable Channel Interleave for socket[0]
2441 03:42:23.199468 Enable Channel Interleave for socket[0]
2442 03:42:23.215682 Daw Cinfig :Skt 0 Ch: 3 , Base = 0x0, Size = 0x40000000, DieInterLeaveEn = 0
2443 03:42:23.215921 ColBits = 0xA
2444 03:42:23.216199 RowBits = 0x11
2445 03:42:23.216405 Banknum = 0x10
2446 03:42:23.216697 RankSize = 0x400000000
2447 03:42:23.216904 Ranknum = 0x2
2448 03:42:23.217133 DramWidth = 0x4
2449 03:42:23.217331 Size = 0x1000000000
2450 03:42:23.230571 Daw Config: Skt 0 Ch: 3 , Base = 0x1000000000, Size = 0x1000000000, DieInterLeaveEn = 0
2451 03:42:23.230812 LowMemory(<4G):Base=0x0, Size=0x40000000
2452 03:42:23.231048 HighMemory(>4G):Base=0x1040000000, Size=0x7C0000000
2453 03:42:23.231275 HighMemory(>4G):Base=0x1040000000, Size=0x7C0000000
2454 03:42:23.245709 HighMemory(>4G):Base=0x1800000000, Size=0x7FC000000
2455 03:42:23.245948 ColBits = 0xA
2456 03:42:23.246181 RowBits = 0x11
2457 03:42:23.246393 Banknum = 0x10
2458 03:42:23.246592 RankSize = 0x400000000
2459 03:42:23.246834 Ranknum = 0x2
2460 03:42:23.247030 DramWidth = 0x4
2461 03:42:23.247248 Size = 0x1000000000
2462 03:42:23.256053 Daw Config: Skt 0 Ch: 1 , Base = 0x2000000000, Size = 0x1000000000, DieInterLeaveEn = 0
2463 03:42:23.256294 HighMemory(>4G):Base=0x2000000000, Size=0xFFC000000
2464 03:42:23.256550 Enable Channel Interleave for socket[1]
2465 03:42:23.256780 Enable Channel Interleave for socket[1]
2466 03:42:23.265617 Daw Cinfig :Skt 1 Ch: 3 , Base = 0x0, Size = 0x40000000, DieInterLeaveEn = 0
2467 03:42:23.265856 ColBits = 0xA
2468 03:42:23.266080 RowBits = 0x11
2469 03:42:23.266302 Banknum = 0x10
2470 03:42:23.266526 RankSize = 0x400000000
2471 03:42:23.266775 Ranknum = 0x2
2472 03:42:23.266972 DramWidth = 0x4
2473 03:42:23.267208 Size = 0x1000000000
2474 03:42:23.279591 Daw Config: Skt 1 Ch: 3 , Base = 0x1000000000, Size = 0x1000000000, DieInterLeaveEn = 0
2475 03:42:23.279871 HighMemory(>4G):Base=0x41000000000, Size=0xFFC000000
2476 03:42:23.280119 ColBits = 0xA
2477 03:42:23.280351 RowBits = 0x11
2478 03:42:23.280579 Banknum = 0x10
2479 03:42:23.280838 RankSize = 0x400000000
2480 03:42:23.281035 Ranknum = 0x2
2481 03:42:23.281275 DramWidth = 0x4
2482 03:42:23.344838 Size = 0x1000000000
2483 03:42:23.345117 Daw Config: Skt 1 Ch: 1 , Base = 0x2000000000, Size = 0x1000000000, DieInterLeaveEn = 0
2484 03:42:23.345342 HighMemory(>4G):Base=0x42000000000, Size=0xFFC000000
2485 03:42:23.357161 Finish Config DAW.
2486 03:42:23.357424
2487 03:42:23.357646 Start config RAS or ECC.
2488 03:42:23.357848 pGblData->mem.rascBypass = 1
2489 03:42:23.375752 pGblData->mem.demandScrubMode = 0
2490 03:42:23.376019 pGblData->mem.patrolScrubMode = 0
2491 03:42:23.376232 skt[0] ch[0] ecc enable.
2492 03:42:23.376467 skt[0] ch[1] ecc enable.
2493 03:42:23.376718 skt[0] ch[2] ecc enable.
2494 03:42:23.376921 skt[0] ch[3] ecc enable.
2495 03:42:23.377162 skt[1] ch[0] ecc enable.
2496 03:42:23.377356 skt[1] ch[1] ecc enable.
2497 03:42:23.377580 skt[1] ch[2] ecc enable.
2498 03:42:23.386970 skt[1] ch[3] ecc enable.
2499 03:42:23.387236 Finish config RAS or ECC.
2500 03:42:23.387470
2501 03:42:23.387680 Clean ddrc or rasc interrupt OK
2502 03:42:23.387910 NOTICE: PL011_UART_BASE: 0x602b0000
2503 03:42:23.388163
2504 03:42:23.388361 NOTICE: BL1: 0x3fc8a000 - 0x3fc8b000 [size = 4096]
2505 03:42:23.388595 NOTICE: Booting Trusted Firmware
2506 03:42:23.415799
2507 03:42:23.416037 NOTICE: BL1: v1.1(release):50e18f8
2508 03:42:23.416270 NOTICE: BL1: Built : 08:50:23, Feb 25 2017
2509 03:42:23.416486 NOTICE: BL1: Booting BL2
2510 03:42:23.416741 NOTICE: BL2: v1.1(release):50e18f8
2511 03:42:23.416978 NOTICE: BL2: Built : 08:50:24, Feb 25 2017
2512 03:42:23.562093 NOTICE: BL1: Booting BL3-1
2513 03:42:23.943932 NOTICE: Before BL31 EL3 MMU
2514 03:42:23.944202
2515 03:42:23.944457 NOTICE: After BL31 EL3 MMU
2516 03:42:23.944712
2517 03:42:23.944950 NOTICE: BL3-1: v1.1(release):50e18f8
2518 03:42:23.945155 NOTICE: BL3-1: Built : 08:50:27, Feb 25 2017
2519 03:42:23.945380 NOTICE: [runtime_svc_init]:[94L] rt_svc_descs_num=0x1
2520 03:42:23.969701 NOTICE: [runtime_svc_init]:[109L] start_oen=4 end_oen=4 call_type=1 std_svc
2521 03:42:23.969968 NOTICE: [psci_init_aff_map]:[296L] mpidr = 0
2522 03:42:23.970178 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2523 03:42:23.970429 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 0
2524 03:42:23.970632 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10000
2525 03:42:23.990475 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2526 03:42:23.990715 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 1
2527 03:42:23.990963 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20000
2528 03:42:23.991170 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2529 03:42:23.991395 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 2
2530 03:42:24.009549 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30000
2531 03:42:24.009789 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2532 03:42:24.010051 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 3
2533 03:42:24.010258 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40000
2534 03:42:24.010513 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2535 03:42:24.031432 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 4
2536 03:42:24.031672 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50000
2537 03:42:24.031882 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2538 03:42:24.032131 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 5
2539 03:42:24.032335 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60000
2540 03:42:24.053280 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2541 03:42:24.053564 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 6
2542 03:42:24.053775 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70000
2543 03:42:24.054029 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2544 03:42:24.076803 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 7
2545 03:42:24.077043 NOTICE: [psci_init_aff_map]:[296L] mpidr = 0
2546 03:42:24.077305 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2547 03:42:24.077512 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 8
2548 03:42:24.077765 NOTICE: [psci_init_aff_map]:[296L] mpidr = 100
2549 03:42:24.097681 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2550 03:42:24.097954 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 9
2551 03:42:24.098167 NOTICE: [psci_init_aff_map]:[296L] mpidr = 200
2552 03:42:24.098408 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2553 03:42:24.098614 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 10
2554 03:42:24.118948 NOTICE: [psci_init_aff_map]:[296L] mpidr = 300
2555 03:42:24.119274 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2556 03:42:24.119559 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 11
2557 03:42:24.119877 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10000
2558 03:42:24.120207 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2559 03:42:24.140780 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 12
2560 03:42:24.141088 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10100
2561 03:42:24.141388 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2562 03:42:24.141735 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 13
2563 03:42:24.142059 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10200
2564 03:42:24.162736 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2565 03:42:24.163046 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 14
2566 03:42:24.163304 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10300
2567 03:42:24.163598 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2568 03:42:24.163929 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 15
2569 03:42:24.184567 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20000
2570 03:42:24.184901 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2571 03:42:24.185194 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 16
2572 03:42:24.185487 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20100
2573 03:42:24.185802 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2574 03:42:24.208396 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 17
2575 03:42:24.208744 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20200
2576 03:42:24.209018 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2577 03:42:24.209294 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 18
2578 03:42:24.209559 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20300
2579 03:42:24.228795 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2580 03:42:24.229083 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 19
2581 03:42:24.229385 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30000
2582 03:42:24.229683 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2583 03:42:24.251183 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 20
2584 03:42:24.251484 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30100
2585 03:42:24.251756 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2586 03:42:24.252047 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 21
2587 03:42:24.252338 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30200
2588 03:42:24.271941 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2589 03:42:24.272231 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 22
2590 03:42:24.272539 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30300
2591 03:42:24.272861 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2592 03:42:24.273130 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 23
2593 03:42:24.293900 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40000
2594 03:42:24.294220 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2595 03:42:24.294545 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 24
2596 03:42:24.294863 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40100
2597 03:42:24.295118 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2598 03:42:24.316241 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 25
2599 03:42:24.316596 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40200
2600 03:42:24.316957 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2601 03:42:24.317264 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 26
2602 03:42:24.317578 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40300
2603 03:42:24.338516 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2604 03:42:24.338843 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 27
2605 03:42:24.339161 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50000
2606 03:42:24.339478 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2607 03:42:24.339766 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 28
2608 03:42:24.404180 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50100
2609 03:42:24.404492 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2610 03:42:24.404822 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 29
2611 03:42:24.405083 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50200
2612 03:42:24.405344 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2613 03:42:24.416291
2614 03:42:24.416660 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 30
2615 03:42:24.416977 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50300
2616 03:42:24.417242 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2617 03:42:24.417499 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 31
2618 03:42:24.427685 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60000
2619 03:42:24.427956 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2620 03:42:24.428184 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 32
2621 03:42:24.428432 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60100
2622 03:42:24.428772 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2623 03:42:24.450721 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 33
2624 03:42:24.451074 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60200
2625 03:42:24.451382 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2626 03:42:24.451707 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 34
2627 03:42:24.452015 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60300
2628 03:42:24.465902 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2629 03:42:24.466249 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 35
2630 03:42:24.466568 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70000
2631 03:42:24.466832 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2632 03:42:24.467102 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 36
2633 03:42:24.476079 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70100
2634 03:42:24.476370 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2635 03:42:24.476662 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 37
2636 03:42:24.476983 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70200
2637 03:42:24.477321 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2638 03:42:24.490725 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 38
2639 03:42:24.491001 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70300
2640 03:42:24.491291 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2641 03:42:24.491586 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 39
2642 03:42:24.491868 NOTICE: [psci_init_aff_map]:[296L] mpidr = 0
2643 03:42:24.512603 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2644 03:42:24.512965 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 40
2645 03:42:24.513291 NOTICE: [psci_init_aff_map]:[296L] mpidr = 1
2646 03:42:24.513566 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2647 03:42:24.513844 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 41
2648 03:42:24.534532 NOTICE: [psci_init_aff_map]:[296L] mpidr = 2
2649 03:42:24.534879 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2650 03:42:24.535187 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 42
2651 03:42:24.535518 NOTICE: [psci_init_aff_map]:[296L] mpidr = 3
2652 03:42:24.535811 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2653 03:42:24.598222 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 43
2654 03:42:24.598527 NOTICE: [psci_init_aff_map]:[296L] mpidr = 100
2655 03:42:24.615876 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2656 03:42:24.616184 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 44
2657 03:42:24.616479 NOTICE: [psci_init_aff_map]:[296L] mpidr = 101
2658 03:42:24.616818 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2659 03:42:24.617129 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 45
2660 03:42:24.626243 NOTICE: [psci_init_aff_map]:[296L] mpidr = 102
2661 03:42:24.626526 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2662 03:42:24.626816 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 46
2663 03:42:24.627098 NOTICE: [psci_init_aff_map]:[296L] mpidr = 103
2664 03:42:24.627430 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2665 03:42:24.636532 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 47
2666 03:42:24.636870 NOTICE: [psci_init_aff_map]:[296L] mpidr = 200
2667 03:42:24.637138 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2668 03:42:24.637383 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 48
2669 03:42:24.637668 NOTICE: [psci_init_aff_map]:[296L] mpidr = 201
2670 03:42:24.656846 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2671 03:42:24.657147 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 49
2672 03:42:24.657457 NOTICE: [psci_init_aff_map]:[296L] mpidr = 202
2673 03:42:24.657796 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2674 03:42:24.658144 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 50
2675 03:42:24.678423 NOTICE: [psci_init_aff_map]:[296L] mpidr = 203
2676 03:42:24.678701 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2677 03:42:24.678944 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 51
2678 03:42:24.679210 NOTICE: [psci_init_aff_map]:[296L] mpidr = 300
2679 03:42:24.679472 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2680 03:42:24.696111 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 52
2681 03:42:24.696435 NOTICE: [psci_init_aff_map]:[296L] mpidr = 301
2682 03:42:24.696812 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2683 03:42:24.697119 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 53
2684 03:42:24.697450 NOTICE: [psci_init_aff_map]:[296L] mpidr = 302
2685 03:42:24.707983
2686 03:42:24.708308 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2687 03:42:24.708625 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 54
2688 03:42:24.708975 NOTICE: [psci_init_aff_map]:[296L] mpidr = 303
2689 03:42:24.709326 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2690 03:42:24.720502 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 55
2691 03:42:24.720851 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10000
2692 03:42:24.721152 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2693 03:42:24.721468 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 56
2694 03:42:24.721778 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10001
2695 03:42:24.778671 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2696 03:42:24.779066 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 57
2697 03:42:24.779419 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10002
2698 03:42:24.786749 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2699 03:42:24.787043 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 58
2700 03:42:24.787326 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10003
2701 03:42:24.787619 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2702 03:42:24.788247 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 59
2703 03:42:24.796502 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10100
2704 03:42:24.796862 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2705 03:42:24.797140 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 60
2706 03:42:24.797389 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10101
2707 03:42:24.805807 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2708 03:42:24.806113 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 61
2709 03:42:24.806388 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10102
2710 03:42:24.806655 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2711 03:42:24.806910 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 62
2712 03:42:24.818840 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10103
2713 03:42:24.819144 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2714 03:42:24.819391 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 63
2715 03:42:24.819652 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10200
2716 03:42:24.819924 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2717 03:42:24.836170 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 64
2718 03:42:24.836538 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10201
2719 03:42:24.836863 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2720 03:42:24.837144 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 65
2721 03:42:24.837413 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10202
2722 03:42:24.856063 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2723 03:42:24.856392 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 66
2724 03:42:24.856760 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10203
2725 03:42:24.857076 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2726 03:42:24.857392 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 67
2727 03:42:24.877671 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10300
2728 03:42:24.878002 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2729 03:42:24.878302 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 68
2730 03:42:24.878584 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10301
2731 03:42:24.878872 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2732 03:42:24.905808 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 69
2733 03:42:24.906092 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10302
2734 03:42:24.906364 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2735 03:42:24.906669 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 70
2736 03:42:24.970198 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10303
2737 03:42:24.970501 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2738 03:42:24.970784 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 71
2739 03:42:24.976194 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20000
2740 03:42:24.976452 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2741 03:42:24.976776 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 72
2742 03:42:24.977075 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20001
2743 03:42:24.977365 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2744 03:42:24.986821 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 73
2745 03:42:24.987088 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20002
2746 03:42:24.987379 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2747 03:42:24.987685 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 74
2748 03:42:24.987983 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20003
2749 03:42:24.996926 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2750 03:42:24.997222 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 75
2751 03:42:24.997503 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20100
2752 03:42:24.997776 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2753 03:42:25.006555 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 76
2754 03:42:25.006826 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20101
2755 03:42:25.007100 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2756 03:42:25.007372 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 77
2757 03:42:25.007650 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20102
2758 03:42:25.026147 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2759 03:42:25.026454 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 78
2760 03:42:25.026714 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20103
2761 03:42:25.026984 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2762 03:42:25.027279 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 79
2763 03:42:25.046465 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20200
2764 03:42:25.046782 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2765 03:42:25.047127 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 80
2766 03:42:25.047424 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20201
2767 03:42:25.047740 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2768 03:42:25.066852 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 81
2769 03:42:25.067187 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20202
2770 03:42:25.067493 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2771 03:42:25.067818 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 82
2772 03:42:25.068140 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20203
2773 03:42:25.092711 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2774 03:42:25.093002 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 83
2775 03:42:25.093285 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20300
2776 03:42:25.093541 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2777 03:42:25.093785 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 84
2778 03:42:25.108272 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20301
2779 03:42:25.108643 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2780 03:42:25.108968 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 85
2781 03:42:25.109258 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20302
2782 03:42:25.135926 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2783 03:42:25.136206 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 86
2784 03:42:25.136470 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20303
2785 03:42:25.136888 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2786 03:42:25.137221 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 87
2787 03:42:25.155818 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30000
2788 03:42:25.156176 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2789 03:42:25.156542 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 88
2790 03:42:25.156873 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30001
2791 03:42:25.157188 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2792 03:42:25.179914 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 89
2793 03:42:25.180253 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30002
2794 03:42:25.180555 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2795 03:42:25.180832 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 90
2796 03:42:25.181130 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30003
2797 03:42:25.196346 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2798 03:42:25.196736 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 91
2799 03:42:25.197082 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30100
2800 03:42:25.197550 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2801 03:42:25.197939 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 92
2802 03:42:25.218126 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30101
2803 03:42:25.218423 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2804 03:42:25.218693 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 93
2805 03:42:25.219038 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30102
2806 03:42:25.219286 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2807 03:42:25.248432 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 94
2808 03:42:25.248804 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30103
2809 03:42:25.249146 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2810 03:42:25.249405 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 95
2811 03:42:25.249702 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30200
2812 03:42:25.268144 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2813 03:42:25.268468 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 96
2814 03:42:25.268904 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30201
2815 03:42:25.269261 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2816 03:42:25.285956 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 97
2817 03:42:25.286288 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30202
2818 03:42:25.286577 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2819 03:42:25.286840 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 98
2820 03:42:25.287122 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30203
2821 03:42:25.305854 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2822 03:42:25.306142 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 99
2823 03:42:25.306422 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30300
2824 03:42:25.306710 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2825 03:42:25.306986 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 100
2826 03:42:25.337923 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30301
2827 03:42:25.338259 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2828 03:42:25.338528 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 101
2829 03:42:25.338766 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30302
2830 03:42:25.339047 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2831 03:42:25.354800 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 102
2832 03:42:25.355130 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30303
2833 03:42:25.355369 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2834 03:42:25.355632 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 103
2835 03:42:25.355909 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40000
2836 03:42:25.388488 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2837 03:42:25.388825 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 104
2838 03:42:25.389108 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40001
2839 03:42:25.389375 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2840 03:42:25.398533 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 105
2841 03:42:25.398838 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40002
2842 03:42:25.399122 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2843 03:42:25.399395 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 106
2844 03:42:25.399670 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40003
2845 03:42:25.416420 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2846 03:42:25.416757 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 107
2847 03:42:25.417038 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40100
2848 03:42:25.417284 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2849 03:42:25.417560 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 108
2850 03:42:25.437327 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40101
2851 03:42:25.437630 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2852 03:42:25.437910 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 109
2853 03:42:25.438146 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40102
2854 03:42:25.438422 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2855 03:42:25.455787 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 110
2856 03:42:25.456120 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40103
2857 03:42:25.456357 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2858 03:42:25.456650 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 111
2859 03:42:25.456940 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40200
2860 03:42:25.485828 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2861 03:42:25.486122 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 112
2862 03:42:25.486415 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40201
2863 03:42:25.486662 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2864 03:42:25.486960 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 113
2865 03:42:25.507039 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40202
2866 03:42:25.507318 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2867 03:42:25.507604 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 114
2868 03:42:25.507872 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40203
2869 03:42:25.525961 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2870 03:42:25.526215 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 115
2871 03:42:25.526478 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40300
2872 03:42:25.526729 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2873 03:42:25.526991 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 116
2874 03:42:25.585557 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40301
2875 03:42:25.585853 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2876 03:42:25.586122 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 117
2877 03:42:25.586395 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40302
2878 03:42:25.586662 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2879 03:42:25.596440 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 118
2880 03:42:25.596812 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40303
2881 03:42:25.597124 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2882 03:42:25.597362 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 119
2883 03:42:25.597617 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50000
2884 03:42:25.606166 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2885 03:42:25.606497 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 120
2886 03:42:25.606734 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50001
2887 03:42:25.607007 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2888 03:42:25.607242 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 121
2889 03:42:25.617878 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50002
2890 03:42:25.618170 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2891 03:42:25.618453 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 122
2892 03:42:25.618712 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50003
2893 03:42:25.636716 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2894 03:42:25.637045 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 123
2895 03:42:25.637303 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50100
2896 03:42:25.637580 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2897 03:42:25.637844 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 124
2898 03:42:25.657200 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50101
2899 03:42:25.657493 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2900 03:42:25.657777 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 125
2901 03:42:25.658086 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50102
2902 03:42:25.658318 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2903 03:42:25.676342 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 126
2904 03:42:25.676659 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50103
2905 03:42:25.676971 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2906 03:42:25.677245 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 127
2907 03:42:25.677507 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50200
2908 03:42:25.696857 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2909 03:42:25.697196 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 128
2910 03:42:25.697479 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50201
2911 03:42:25.697717 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2912 03:42:25.697999 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 129
2913 03:42:25.716045 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50202
2914 03:42:25.716374 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2915 03:42:25.738947 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 130
2916 03:42:25.739237 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50203
2917 03:42:25.739494 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2918 03:42:25.739763 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 131
2919 03:42:25.740062 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50300
2920 03:42:25.756962 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2921 03:42:25.757210 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 132
2922 03:42:25.757504 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50301
2923 03:42:25.757742 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2924 03:42:25.758004 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 133
2925 03:42:25.807777 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50302
2926 03:42:25.808060 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2927 03:42:25.808397 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 134
2928 03:42:25.808737 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50303
2929 03:42:25.809018 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2930 03:42:25.817621 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 135
2931 03:42:25.817955 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60000
2932 03:42:25.818217 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2933 03:42:25.818490 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 136
2934 03:42:25.818735 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60001
2935 03:42:25.826917 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2936 03:42:25.827211 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 137
2937 03:42:25.827495 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60002
2938 03:42:25.827737 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2939 03:42:25.845873 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 138
2940 03:42:25.846194 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60003
2941 03:42:25.846477 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2942 03:42:25.846750 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 139
2943 03:42:25.847025 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60100
2944 03:42:25.868375 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2945 03:42:25.868735 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 140
2946 03:42:25.869017 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60101
2947 03:42:25.869330 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2948 03:42:25.869727 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 141
2949 03:42:25.886271 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60102
2950 03:42:25.886541 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2951 03:42:25.886831 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 142
2952 03:42:25.887094 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60103
2953 03:42:25.887363 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2954 03:42:25.906880 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 143
2955 03:42:25.907181 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60200
2956 03:42:25.907466 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2957 03:42:25.907734 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 144
2958 03:42:25.927301 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60201
2959 03:42:25.927634 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2960 03:42:25.927920 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 145
2961 03:42:25.928162 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60202
2962 03:42:25.928428 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2963 03:42:25.978648 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 146
2964 03:42:25.978919 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60203
2965 03:42:25.979195 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2966 03:42:25.979459 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 147
2967 03:42:25.979735 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60300
2968 03:42:25.986790 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2969 03:42:25.987055 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 148
2970 03:42:25.987356 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60301
2971 03:42:25.987584 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2972 03:42:25.987861 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 149
2973 03:42:26.000085 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60302
2974 03:42:26.000402 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2975 03:42:26.000740 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 150
2976 03:42:26.001065 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60303
2977 03:42:26.001353 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2978 03:42:26.017676 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 151
2979 03:42:26.017957 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70000
2980 03:42:26.018236 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2981 03:42:26.018476 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 152
2982 03:42:26.019060 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70001
2983 03:42:26.036662 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2984 03:42:26.036978 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 153
2985 03:42:26.037280 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70002
2986 03:42:26.037567 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2987 03:42:26.065816 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 154
2988 03:42:26.066129 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70003
2989 03:42:26.066428 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2990 03:42:26.066705 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 155
2991 03:42:26.066969 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70100
2992 03:42:26.087391 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2993 03:42:26.087700 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 156
2994 03:42:26.088039 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70101
2995 03:42:26.088329 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2996 03:42:26.088641 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 157
2997 03:42:26.105851 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70102
2998 03:42:26.106116 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2999 03:42:26.106357 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 158
3000 03:42:26.106589 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70103
3001 03:42:26.106814 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3002 03:42:26.128279 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 159
3003 03:42:26.128563 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70200
3004 03:42:26.128936 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3005 03:42:26.129178 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 160
3006 03:42:26.129415 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70201
3007 03:42:26.184766 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3008 03:42:26.185023 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 161
3009 03:42:26.195779 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70202
3010 03:42:26.196046 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3011 03:42:26.196298 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 162
3012 03:42:26.196563 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70203
3013 03:42:26.196827 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3014 03:42:26.205906 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 163
3015 03:42:26.206152 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70300
3016 03:42:26.206394 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3017 03:42:26.206624 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 164
3018 03:42:26.206845 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70301
3019 03:42:26.217226 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3020 03:42:26.217464 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 165
3021 03:42:26.217692 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70302
3022 03:42:26.217906 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3023 03:42:26.225968 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 166
3024 03:42:26.226212 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70303
3025 03:42:26.226431 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3026 03:42:26.226659 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 167
3027 03:42:26.226867 NOTICE: [cm_prepare_el3_exit]:[262L] read_tpidr_el3 = 3fc5e800
3028 03:42:26.246933 NOTICE: [cm_prepare_el3_exit]:[319L] ctx add = 3fc7ef80
3029 03:42:26.247191
3030 03:42:26.247411 :486=170
3031 03:42:29.055802 [serdes_hilink2_init]:hilink2_mode pcie2 8 lane
3032 03:42:29.056187 Halt Macro 2 MCU!!
3033 03:42:29.135843 Macro 2 Download Firmware Success!!
3034 03:42:29.136099 Release Macro 2 MCU!!
3035 03:42:29.185724 Temperature: 29 (0x1D)
3036 03:42:29.255812 Temperature: 29 (0x1D)
3037 03:42:29.326289 [serdes_init]:SerDes2 init success!
3038 03:42:29.326545 Halt Macro 3 MCU!!
3039 03:42:29.346159 Macro 3 Download Firmware Success!!
3040 03:42:29.346404 Release Macro 3 MCU!!
3041 03:42:29.437729 Temperature: 30 (0x1E)
3042 03:42:29.438015 Temperature: 30 (0x1E)
3043 03:42:29.456157 [serdes_init]:SerDes3 init success!
3044 03:42:29.456419 Halt Macro 4 MCU!!
3045 03:42:29.475772 Macro 4 Download Firmware Success!!
3046 03:42:29.476023 Release Macro 4 MCU!!
3047 03:42:29.535803 Temperature: 30 (0x1E)
3048 03:42:29.585818 Temperature: 31 (0x1F)
3049 03:42:29.586119 [serdes_init]:SerDes4 init success!
3050 03:42:29.586356 [serdes_hilink5_init]:hilink5_mode sas1 4 lane
3051 03:42:29.586634 Halt Macro 5 MCU!!
3052 03:42:29.665807 Macro 5 Download Firmware Success!!
3053 03:42:29.666122 Release Macro 5 MCU!!
3054 03:42:29.736013 Temperature: 31 (0x1F)
3055 03:42:29.785967 Temperature: 31 (0x1F)
3056 03:42:29.805698 [serdes_init]:SerDes5 init success!
3057 03:42:29.805960 [serdes_hilink6_init] lane 0 =>sas1 lane 0
3058 03:42:29.806192 [serdes_hilink6_init] lane 1 =>sas1 lane 1
3059 03:42:29.806421 [serdes_hilink6_init] lane 2 =>sas1 lane 2
3060 03:42:29.806627 [serdes_hilink6_init] lane 3 =>sas1 lane 3
3061 03:42:29.807136 Halt Macro 6 MCU!!
3062 03:42:29.915703 Macro 6 Download Firmware Success!!
3063 03:42:29.915965 Release Macro 6 MCU!!
3064 03:42:29.965903 Temperature: 31 (0x1F)
3065 03:42:30.025744 Temperature: 31 (0x1F)
3066 03:42:30.025985 [serdes_init]:SerDes6 init success!
3067 03:42:30.026215 [serdes_hilink0_init]:hilink0_mode pcie5 8 lane
3068 03:42:30.026488 Halt Macro 0 MCU!!
3069 03:42:30.135601 Macro 0 Download Firmware Success!!
3070 03:42:30.135859 Release Macro 0 MCU!!
3071 03:42:30.185831 Temperature: 28 (0x1C)
3072 03:42:30.235906 Temperature: 28 (0x1C)
3073 03:42:30.307448 [serdes_init]:SerDes0 init success!
3074 03:42:30.307721 [serdes_hilink1_init]:hilink1_mode pcie4 8 lane
3075 03:42:30.307952 Halt Macro 1 MCU!!
3076 03:42:30.379175 Macro 1 Download Firmware Success!!
3077 03:42:30.379416 Release Macro 1 MCU!!
3078 03:42:30.446307 Temperature: 28 (0x1C)
3079 03:42:30.497031 Temperature: 28 (0x1C)
3080 03:42:30.565887 [serdes_init]:SerDes1 init success!
3081 03:42:30.566123 [serdes_hilink5_init]:hilink5_mode pcie6 1 lane and pcie7 1 lane
3082 03:42:30.566354 Halt Macro 5 MCU!!
3083 03:42:30.646200 Macro 5 Download Firmware Success!!
3084 03:42:30.646446 Release Macro 5 MCU!!
3085 03:42:30.766466 Temperature: 28 (0x1C)
3086 03:42:30.766722 Temperature: 28 (0x1C)
3087 03:42:30.790933 [serdes_init]:SerDes5 init success!
3088 03:42:30.791179 [serdes_hilink6_init] lane 0 =>sas5 lane 0
3089 03:42:30.791471 [serdes_hilink6_init] lane 1 =>sas5 lane 1
3090 03:42:30.791713 Halt Macro 6 MCU!!
3091 03:42:30.875810 Macro 6 Download Firmware Success!!
3092 03:42:30.876068 Release Macro 6 MCU!!
3093 03:42:30.955873 Temperature: 28 (0x1C)
3094 03:42:30.956171 Temperature: 28 (0x1C)
3095 03:42:31.027128 [serdes_init]:SerDes6 init success!
3096 03:42:31.027372 [serdes_hilink2_init]:hilink2_mode pcie2 8 lane
3097 03:42:31.027652 Halt Macro 2 MCU!!
3098 03:42:31.095835 Macro 2 Download Firmware Success!!
3099 03:42:31.096076 Release Macro 2 MCU!!
3100 03:42:31.145741 Temperature: 29 (0x1D)
3101 03:42:31.226211 Temperature: 29 (0x1D)
3102 03:42:31.275781 [serdes_init]:SerDes2 init success!
3103 03:42:31.276144 Halt Macro 3 MCU!!
3104 03:42:31.296656 Macro 3 Download Firmware Success!!
3105 03:42:31.297079 Release Macro 3 MCU!!
3106 03:42:31.362792 Temperature: 30 (0x1E)
3107 03:42:31.426084 Temperature: 30 (0x1E)
3108 03:42:31.426476 [serdes_init]:SerDes3 init success!
3109 03:42:31.426833 Halt Macro 4 MCU!!
3110 03:42:31.427194 Macro 4 Download Firmware Success!!
3111 03:42:31.427526 Release Macro 4 MCU!!
3112 03:42:31.506301 Temperature: 30 (0x1E)
3113 03:42:31.506717 Temperature: 30 (0x1E)
3114 03:42:31.537477 [serdes_init]:SerDes4 init success!
3115 03:42:31.537925 [serdes_hilink5_init]:hilink5_mode sas1 4 lane
3116 03:42:31.538323 Halt Macro 5 MCU!!
3117 03:42:31.657265 Macro 5 Download Firmware Success!!
3118 03:42:31.657647 Release Macro 5 MCU!!
3119 03:42:31.735819 Temperature: 30 (0x1E)
3120 03:42:31.736249 Temperature: 31 (0x1F)
3121 03:42:31.778056 [serdes_init]:SerDes5 init success!
3122 03:42:31.778526 [serdes_hilink6_init] lane 0 =>sas1 lane 0
3123 03:42:31.778901 [serdes_hilink6_init] lane 1 =>sas1 lane 1
3124 03:42:31.830583 [serdes_hilink6_init] lane 2 =>sas1 lane 2
3125 03:42:31.830968 [serdes_hilink6_init] lane 3 =>sas1 lane 3
3126 03:42:31.831366 Halt Macro 6 MCU!!
3127 03:42:31.906752 Macro 6 Download Firmware Success!!
3128 03:42:31.907144 Release Macro 6 MCU!!
3129 03:42:31.986139 Temperature: 31 (0x1F)
3130 03:42:31.986557 Temperature: 31 (0x1F)
3131 03:42:32.045905 [serdes_init]:SerDes6 init success!
3132 03:42:32.046387 [serdes_hilink0_init]:hilink0_mode pcie5 8 lane
3133 03:42:32.046775 Halt Macro 0 MCU!!
3134 03:42:32.225874 Macro 0 Download Firmware Success!!
3135 03:42:32.226182 Release Macro 0 MCU!!
3136 03:42:32.226443 Temperature: 27 (0x1B)
3137 03:42:32.295743 Temperature: 27 (0x1B)
3138 03:42:32.375748 [serdes_init]:SerDes0 init success!
3139 03:42:32.376039 [serdes_hilink1_init]:hilink1_mode pcie4 8 lane
3140 03:42:32.376305 Halt Macro 1 MCU!!
3141 03:42:32.506036 Macro 1 Download Firmware Success!!
3142 03:42:32.506428 Release Macro 1 MCU!!
3143 03:42:32.577056 Temperature: 27 (0x1B)
3144 03:42:32.625927 Temperature: 27 (0x1B)
3145 03:42:32.695888 [serdes_init]:SerDes1 init success!
3146 03:42:32.696217 [serdes_hilink5_init]:hilink5_mode pcie6 1 lane and pcie7 1 lane
3147 03:42:32.696566 Halt Macro 5 MCU!!
3148 03:42:32.835691 Macro 5 Download Firmware Success!!
3149 03:42:32.836014 Release Macro 5 MCU!!
3150 03:42:32.915844 Temperature: 27 (0x1B)
3151 03:42:32.916164 Temperature: 27 (0x1B)
3152 03:42:32.965943 [serdes_init]:SerDes5 init success!
3153 03:42:32.966384 [serdes_hilink6_init] lane 0 =>sas5 lane 0
3154 03:42:32.966757 [serdes_hilink6_init] lane 1 =>sas5 lane 1
3155 03:42:32.967131 Halt Macro 6 MCU!!
3156 03:42:33.127375 Macro 6 Download Firmware Success!!
3157 03:42:33.127792 Release Macro 6 MCU!!
3158 03:42:33.176850 Temperature: 27 (0x1B)
3159 03:42:33.266131 Temperature: 27 (0x1B)
3160 03:42:33.266461 [serdes_init]:SerDes6 init success!
3161 03:42:33.475728 InfoFromBmc.ProductName TaiShan 2280
3162 03:42:33.476057 InfoFromBmc.SerialNum 2102311TBJ10H8000087
3163 03:42:33.476339 InfoFromBmc.ManufactureType02 Huawei
3164 03:42:33.476656 InfoFromBmc.AssetTag
3165 03:42:33.497719 InfoFromBmc.SrNumType02 024APL10H8000090
3166 03:42:33.498165 InfoFromBmc.AssetTagType03
3167 03:42:33.498587 InfoFromBmc.SrNumType03 To be filled by O.E.M.
3168 03:42:33.515886 InfoFromBmc.VersionType03
3169 03:42:33.516341 InfoFromBmc.ChassisType03
3170 03:42:33.555947 InfoFromBmc.ManufacturerType03 Huawei
3171 03:42:33.556450 Create event for smbios table transfer success.
3172 03:42:33.556934 VerStr:1.12
3173 03:42:33.557308 Create event for miscellaneous ipmi operation success.
3174 03:42:42.516656 Locate gEfiPciIoProtocol Failed.
3175 03:42:42.586752 DawNum[0] = 2,DawNum[1] = 1,DawNum[2] =2,DawNum[3] =1
3176 03:42:42.587147 0 Base = 0x0, Size = 0x40000000
3177 03:42:42.587473 0 Base = 0x1000000000, Size = 0x1000000000
3178 03:42:42.587752 1 Base = 0x2000000000, Size = 0x1000000000
3179 03:42:42.588038 2 Base = 0x40000000000, Size = 0x40000000
3180 03:42:42.605987 2 Base = 0x41000000000, Size = 0x1000000000
3181 03:42:42.606378 3 Base = 0x42000000000, Size = 0x1000000000
3182 03:42:42.671166 [gmac_initialize]:[3650L] GpriData=0x3E8DE018
3183 03:42:42.686652 pPriv->ulMacSpeed:9
3184 03:42:42.687216 pPriv->ulMacDuplex:1
3185 03:42:42.687679 pPriv->ulPort:0
3186 03:42:42.688056 pPriv->ulGEBase:0xC7040000
3187 03:42:42.688472 pPriv->ulPpeCommonBase:0xC5070000
3188 03:42:42.689051 pPriv->ulPpeTNLBase:0xC5000000
3189 03:42:42.689492 pPriv->ulRCBCommonBase:0xC5080000
3190 03:42:42.689909 pPriv->ulRCBCommonEntryBase:0xC5080000
3191 03:42:42.708339 pPriv->ulRCBSramEntryBase:0xC5090000
3192 03:42:42.708872 pPriv->ulRingNum:0
3193 03:42:42.709277 pPriv->ulRingAddr:0
3194 03:42:42.709680 pPriv->ulMacAddr:0xA0 0xA3 0x3B 0xC1 0x40 0xE8
3195 03:42:42.791245 DSAF_init
3196 03:42:42.791685 tbl_tcam_data
3197 03:42:42.792070 0x3F196CA0:0xA0A33BC1 0x40E80000 0x00000000 0x00000001
3198 03:42:42.792483 0x3F196CB0:0x00000000
3199 03:42:42.793003 tbl_tcam_ucast
3200 03:42:42.793421 0x3F196CA8:0x00000000 0x00000001 0x00000000 0x00000001
3201 03:42:42.793844 0x3F196CB8:0x0000007F 0x00000000 0x0000007F 0x82000800
3202 03:42:42.817235 0x3F196CC8:0x00800000
3203 03:42:42.817722 ----ok
3204 03:42:42.818170 LocateProtocol mOemXgeStatusProtocol success.
3205 03:42:42.818594 RXRING = 0x3E8D9000
3206 03:42:42.819003 TXRING = 0x3E8D4000
3207 03:42:42.819412 pPriv->ulTxMask = 512
3208 03:42:42.819796 RXBUFF = 0x3E6D3000
3209 03:42:42.820209 TXBUFF = 0x3E4D2000
3210 03:42:42.820670 [gmac_initialize]:[3650L] GpriData=0x3E44C018
3211 03:42:42.853521 pPriv->ulMacSpeed:9
3212 03:42:42.854034 pPriv->ulMacDuplex:1
3213 03:42:42.854601 pPriv->ulPort:1
3214 03:42:42.855077 pPriv->ulGEBase:0xC7044000
3215 03:42:42.855545 pPriv->ulPpeCommonBase:0xC5070000
3216 03:42:42.855992 pPriv->ulPpeTNLBase:0xC5010000
3217 03:42:42.856423 pPriv->ulRCBCommonBase:0xC5080000
3218 03:42:42.856906 pPriv->ulRCBCommonEntryBase:0xC5080000
3219 03:42:42.875199 pPriv->ulRCBSramEntryBase:0xC5090000
3220 03:42:42.875674 pPriv->ulRingNum:16
3221 03:42:42.876099 pPriv->ulRingAddr:1048576
3222 03:42:42.876496 pPriv->ulMacAddr:0xA0 0xA3 0x3B 0xC1 0x40 0xE9
3223 03:42:42.876996 DSAF_init
3224 03:42:42.877386 tbl_tcam_data
3225 03:42:42.877793 0x3F196CA0:0xA0A33BC1 0x40E90001 0x00000000 0x00000001
3226 03:42:42.878182 0x3F196CB0:0x00000000
3227 03:42:42.878592 tbl_tcam_ucast
3228 03:42:42.928185 0x3F196CA8:0x00000000 0x00000001 0x00000000 0x00000001
3229 03:42:42.928563 0x3F196CB8:0x0000008F 0x00000000 0x0000008F 0xC13BA3A0
3230 03:42:42.928901 0x3F196CC8:0x0000E940
3231 03:42:42.946156 ----ok
3232 03:42:42.946589 LocateProtocol mOemXgeStatusProtocol success.
3233 03:42:42.946977 RXRING = 0x3E447000
3234 03:42:42.947356 TXRING = 0x3E442000
3235 03:42:42.947727 pPriv->ulTxMask = 512
3236 03:42:42.948084 RXBUFF = 0x3E241000
3237 03:42:42.948434 TXBUFF = 0x3E040000
3238 03:42:42.948851 [gmac_initialize]:[3650L] GpriData=0x3DFB8018
3239 03:42:42.959246 pPriv->ulMacSpeed:8
3240 03:42:42.959747 pPriv->ulMacDuplex:1
3241 03:42:42.960288 pPriv->ulPort:4
3242 03:42:42.960811 pPriv->ulGEBase:0xC7050000
3243 03:42:42.961342 pPriv->ulPpeCommonBase:0xC5070000
3244 03:42:42.961880 pPriv->ulPpeTNLBase:0xC5040000
3245 03:42:42.962395 pPriv->ulRCBCommonBase:0xC5080000
3246 03:42:42.963033 pPriv->ulRCBCommonEntryBase:0xC5080000
3247 03:42:42.986075 pPriv->ulRCBSramEntryBase:0xC5090000
3248 03:42:42.986578 pPriv->ulRingNum:64
3249 03:42:42.986922 pPriv->ulRingAddr:4194304
3250 03:42:42.987255 pPriv->ulMacAddr:0xA0 0xA3 0x3B 0xC1 0x40 0xE6
3251 03:42:42.987633 PhyID : 0x1410DD0
3252 03:42:42.988091 PhyAddr: 0x0
3253 03:42:42.988597 ETH_PhyInit 1928; Marvell 88E1512 detect!
3254 03:42:43.386289 MII_CTRL_REG = 0x3100
3255 03:42:43.386739 MII_STAT_REG = 0x7949
3256 03:42:43.441854 page 18, reg20:0x1
3257 03:42:43.442495 page 0, reg17:0x4000
3258 03:42:43.443002 Phy Init OK
3259 03:42:43.443522 DSAF_init
3260 03:42:43.444003 tbl_tcam_data
3261 03:42:43.444474 0x3F196CA0:0xA0A33BC1 0x40E60004 0x00000000 0x00000001
3262 03:42:43.467104 0x3F196CB0:0x00000000
3263 03:42:43.467691 tbl_tcam_ucast
3264 03:42:43.468185 0x3F196CA8:0x00000000 0x00000001 0x00000000 0x00000001
3265 03:42:43.468669 0x3F196CB8:0x000000BF 0x00000000 0x000000BF 0xAFAFAFAF
3266 03:42:43.469146 0x3F196CC8:0xAFAFAFAF
3267 03:42:43.469704 ----ok
3268 03:42:43.606749 RXRING = 0x3DFB3000
3269 03:42:43.607419 TXRING = 0x3DFAD000
3270 03:42:43.607853 pPriv->ulTxMask = 512
3271 03:42:43.608284 RXBUFF = 0x3DDAB000
3272 03:42:43.608889 TXBUFF = 0x3DBA9000
3273 03:42:43.609296 [gmac_initialize]:[3650L] GpriData=0x3DB21018
3274 03:42:43.638589 pPriv->ulMacSpeed:8
3275 03:42:43.639182 pPriv->ulMacDuplex:1
3276 03:42:43.639660 pPriv->ulPort:5
3277 03:42:43.640007 pPriv->ulGEBase:0xC7054000
3278 03:42:43.640340 pPriv->ulPpeCommonBase:0xC5070000
3279 03:42:43.640910 pPriv->ulPpeTNLBase:0xC5050000
3280 03:42:43.641402 pPriv->ulRCBCommonBase:0xC5080000
3281 03:42:43.641819 pPriv->ulRCBCommonEntryBase:0xC5080000
3282 03:42:43.666244 pPriv->ulRCBSramEntryBase:0xC5090000
3283 03:42:43.667164 pPriv->ulRingNum:80
3284 03:42:43.668132 pPriv->ulRingAddr:5242880
3285 03:42:43.668905 pPriv->ulMacAddr:0xA0 0xA3 0x3B 0xC1 0x40 0xE7
3286 03:42:43.696083 PhyID : 0x1410DD0
3287 03:42:43.696370 PhyAddr: 0x1
3288 03:42:43.696683 ETH_PhyInit 1928; Marvell 88E1512 detect!
3289 03:42:44.106413 MII_CTRL_REG = 0x3100
3290 03:42:44.107108 MII_STAT_REG = 0x7949
3291 03:42:44.146149 page 18, reg20:0x1
3292 03:42:44.146758 page 0, reg17:0x4000
3293 03:42:44.183611 Phy Init OK
3294 03:42:44.184029 DSAF_init
3295 03:42:44.184443 tbl_tcam_data
3296 03:42:44.184884 0x3F196CA0:0xA0A33BC1 0x40E70005 0x00000000 0x00000001
3297 03:42:44.185296 0x3F196CB0:0x00000000
3298 03:42:44.185657 tbl_tcam_ucast
3299 03:42:44.185988 0x3F196CA8:0x00000000 0x00000001 0x00000000 0x00000001
3300 03:42:44.186332 0x3F196CB8:0x000000CF 0x00000000 0x000000CF 0xAFAFAFAF
3301 03:42:44.280713 0x3F196CC8:0xAFAFAFAF
3302 03:42:44.281230 ----ok
3303 03:42:44.309333 RXRING = 0x3DB1C000
3304 03:42:44.309735 TXRING = 0x3DB17000
3305 03:42:44.310041 pPriv->ulTxMask = 512
3306 03:42:44.310341 RXBUFF = 0x3D916000
3307 03:42:44.310604 TXBUFF = 0x3D714000
3308 03:42:44.455997 SasDriverInitialize Ok!!!
3309 03:42:44.476405 [sas_init,2173]Card:1 init ok
3310 03:42:44.476960 [Higgs_StartPhy,185]Card:1 no cable on phy:0, default as electric cable
3311 03:42:45.081452 [Higgs_IntrInquiryOperation,219]Identify info:0x20010202,DevType:2--2,uiPhyContext:0x0
3312 03:42:45.081942 [Higgs_PhyCtrlUpDown,332]Higgs_PhyCtrlUpDown at uiPhyId = 0x0
3313 03:42:45.082393 [Higgs_PhyCtrlUpDown,346]uiPhyId:0x0, uiIrqVal:0x26
3314 03:42:45.082847 [Higgs_PhyUp,503]phyid:0,Rate is 11
3315 03:42:45.156115 [SAINI_ClearPortRsc,449]Card:1 port:0 clr port rsc,remove all device from device list of Disc
3316 03:42:45.156392 [SAINI_ExpanderBufferSwitch,1306]EXPANDER Buffer function is 2 !
3317 03:42:45.166535 [SAL_AbortSataDevIo,175]Now let's start AbortSataDev reset Io Card:1 msg:3D5CC9F0(uni id:0x0) to dev addr:0x500E004AAAAAAA00(sal dev:3D5D42D8) done func is NULL,v_pstMsg->stStatus.enDrvResp803
3318 03:42:45.178050 [SAL_AbortSataDevIo,175]Now let's start AbortSataDev reset Io Card:1 msg:3D5CCFD8(uni id:0x0) to dev addr:0x500E004AAAAAAA01(sal dev:3D5D4598) done func is NULL,v_pstMsg->stStatus.enDrvResp803
3319 03:42:45.196263 [SAL_AbortTaskSet,646]Now let's start abort SAS dev Io Card:1 msg:3D5CD5C0 to dev addr:0x500E004AAAAAAA1E(sal dev:3D5D4858),v_pstMsg->stStatus.enDrvResp803,pstMsg->pfnDone:31B85BF8
3320 03:42:45.196654 [SasScanDisk,838]Open Card:1 Phy:0 success!
3321 03:42:45.197021
3322 03:42:45.197321 Success to register SasDevice:Port 0 SasAddr 0x500E004AAAAAAA00, status = Success
3323 03:42:45.217748 Success to register SasDevice:Port 0 SasAddr 0x500E004AAAAAAA01, status = Success
3324 03:42:45.218107 SasDriverStart Ok!!!
3325 03:42:48.246641 SmiControllerDriverSupported - Status:Success
3326 03:42:48.247246 Install GopDevicePath Handle 0
3327 03:42:48.247918 Install GopDevicePath Handle 3D54D898
3328 03:42:48.248597 Install GopDevicePath Status Success
3329 03:42:48.249279 SmiGraphicsOutputSetMode +
3330 03:42:48.249975 Resetting Memory
3331 03:42:48.250628 setModeEx +
3332 03:42:48.251266 programModeRegisters +
3333 03:42:48.266528 [LPC] CRT_PLL1_750HS = 0x1D40A02
3334 03:42:48.266903 [LPC] CRT_PLL2_750HS = 0x206B851E
3335 03:42:48.267328 [LPC] SECONDARY_DISPLAY_CTRL = 0x2087106
3336 03:42:48.267742 setModeEx -
3337 03:42:48.322509 SmiGraphicsOutputSetMode x=640 y=480
3338 03:42:48.322978 SmiGraphicsOutputSetMode -
3339 03:42:48.323474 SmiGraphicsOutputConstructor -
3340 03:42:48.348715 [2J[01;01H[=3h[2J[01;01H[2J[01;01H[=3h[2J[01;01H[2J[01;01H[=3h[2J[01;01H[2J[01;01H[=3h[2J[01;01H[2J[01;01H[=3h[2J[01;01H[2J[01;01H[=3h[2J[01;01H[0m[35m[40mSmiGraphicsOutputQueryMode +
3341 03:42:48.349070 SmiGraphicsOutputQueryMode -
3342 03:42:48.376706 SmiGraphicsOutputQueryMode +
3343 03:42:48.377023 SmiGraphicsOutputQueryMode -
3344 03:42:48.426064 SmiGraphicsOutputQueryMode +
3345 03:42:48.426740 SmiGraphicsOutputQueryMode -
3346 03:42:48.427340 SmiGraphicsOutputQueryMode +
3347 03:42:48.427904 SmiGraphicsOutputQueryMode -
3348 03:42:48.486347 [2J[01;01H[=3h[2J[01;01H[0m[37m[40mSmiGraphicsOutputQueryMode +
3349 03:42:48.486670 SmiGraphicsOutputQueryMode -
3350 03:42:50.410629 [2J[01;01H[=3h[2J[01;01H[0m[35m[40mSmiControllerDriverSupported - Status:Unsupported
3351 03:42:50.411037 SmiControllerDriverSupported - Status:Unsupported
3352 03:42:50.427278 SmiControllerDriverSupported - Status:Unsupported
3353 03:42:50.427514 SmiControllerDriverSupported - Status:Unsupported
3354 03:42:50.427721 SmiControllerDriverSupported - Status:Unsupported
3355 03:42:50.427925 SmiControllerDriverSupported - Status:Unsupported
3356 03:42:50.428128 SmiControllerDriverSupported - Status:Unsupported
3357 03:42:50.526162 SmiControllerDriverSupported - Status:Unsupported
3358 03:42:51.434766 SmiControllerDriverSupported - Status:Unsupported
3359 03:42:51.435418 SmiControllerDriverSupported - Status:Unsupported
3360 03:42:51.435853 SmiControllerDriverSupported - Status:Unsupported
3361 03:42:51.436274 SmiControllerDriverSupported - Status:Unsupported
3362 03:42:51.466704 SmiControllerDriverSupported - Status:Unsupported
3363 03:42:51.467092 SmiControllerDriverSupported - Status:Unsupported
3364 03:42:51.467430 SmiControllerDriverSupported - Status:Unsupported
3365 03:42:51.467834 SmiControllerDriverSupported - Status:Unsupported
3366 03:42:52.386111 [0m[37m[40mPress Enter to boot OS immediately.
3367 03:42:52.386480 Press any other key in 10 seconds to stop automatical booting...
3368 03:43:02.876052 [2J[01;01HSmiGraphicsOutputQueryMode +
3369 03:43:02.876623 SmiGraphicsOutputQueryMode -
3370 03:43:10.737918 ..[0m[30m[47mWelcome to GRUB!
3371 03:43:10.738285
3372 03:43:10.738485
3373 03:43:10.767796 [0m[37m[40m[0m[30m[40m[2J[01;01H[0m[37m[40m[02;27HGNU GRUB version 2.02~beta3
3374 03:43:10.768071
3375 03:43:10.768281
3376 03:43:10.786350 Minimal BASH-like line editing is supported. For the first word, TAB
3377 03:43:10.786602
3378 03:43:10.786811 lists possible command completions. Anywhere else TAB lists possible
3379 03:43:10.787015
3380 03:43:10.787216 device or file completions.
3381 03:43:10.787415
3382 03:43:10.787609
3383 03:43:10.787800
3384 03:43:10.788735 Setting prompt string to ['grub>', 'error: missing (.*) symbol.']
3385 03:43:10.788963 Sending with 10 millisecond of delay
3387 03:43:18.904380 grub> linux (tftp,192.168.101.1)/8789805/tftp-deploy-qsd8wqq8/kernel/Image pcie_aspm=off pci=pcie_bus_perf root=/dev/ram0 ip=:::::eth0:dhcp
3388 03:43:18.915042 bootloader-commands: Wait for prompt ['grub>', 'error: missing (.*) symbol.'] (timeout 00:02:48)
3389 03:43:18.915799 [09;07Hl[09;08H[09;08Hi[09;09H[09;09Hn[09;10H[09;10Hu[09;11H[09;11Hx[09;12H[09;12H [09;13H[09;13H([09;14H[09;14Ht[09;15H[09;15Hf[09;16H[09;16Ht[09;17H[09;17Hp[09;18H[09;18H,[09;19H[09;19H1[09;20H[09;20H9[09;21H[09;21H2[09;22H[09;22H.[09;23H[09;23H1[09;24H[09;24H6[09;25H[09;25H8[09;26H[09;26H.[09;27H[09;27H1[09;28H[09;28H0[09;29H[09;29H1[09;30H[09;30H.[09;31H[09;31H1[09;32H[09;32H)[09;33H[09;33H/[09;34H[09;34H8[09;35H[09;35H8[09;36H[09;36H9[09;37H[09;37H8[09;38H[09;38H0[09;39H[09;39H5[09;40H[09;40H/[09;41H[09;41Ht[09;42H[09;42Hf[09;43H[09;43Ht[09;44H[09;44Hp[09;45H[09;45H-[09;46H[09;46Hd[09;47H[09;47He[09;48H[09;48Hp[09;49H[09;49Hl[09;50H[09;50Ho[09;51H[09;51Hy[09;52H[09;52H-[09;53H[09;53Hq[09;54H[09;54Hs[09;55H[09;55Hd[09;56H[09;56H8[09;57H[09;57Hw[09;58H[09;58Hq[09;59H[09;59Hq[09;60H[09;60H8[09;61H[09;61H/[09;62H[09;62Hk[09;63H[09;63He[09;64H[09;64Hr[09;65H[09;65Hn[09;66H[09;66He[09;67H[09;67Hl[09;68H[09;68H/[09;69H[09;69HI[09;70H[09;70Hm[09;71H[09;71Ha[09;72H[09;72Hg[09;73H[09;73He[09;74H[09;74H [09;75H[09;75Hp[09;76H[09;76Hc[09;77H[09;77Hi[09;78H[09;78He[09;79H[09;79H_
3390 03:43:18.916045
3391 03:43:18.916252 [09;80H[09;80Ha
3392 03:43:18.916453
3393 03:43:18.946808 [10;01H[10;01Hs[10;02H[10;02Hp[10;03H[10;03Hm[10;04H[10;04H=[10;05H[10;05Ho[10;06H[10;06Hf[10;07H[10;07Hf[10;08H[10;08H [10;09H[10;09Hp[10;10H[10;10Hc[10;11H[10;11Hi[10;12H[10;12H=[10;13H[10;13Hp[10;14H[10;14Hc[10;15H[10;15Hi[10;16H[10;16He[10;17H[10;17H_[10;18H[10;18Hb[10;19H[10;19Hu[10;20H[10;20Hs[10;21H[10;21H_[10;22H[10;22Hp[10;23H[10;23He[10;24H[10;24Hr[10;25H[10;25Hf[10;26H[10;26H [10;27H[10;27Hr[10;28H[10;28Ho[10;29H[10;29Ho[10;30H[10;30Ht[10;31H[10;31H=[10;32H[10;32H/[10;33H[10;33Hd[10;34H[10;34He[10;35H[10;35Hv[10;36H[10;36H/[10;37H[10;37Hr[10;38H[10;38Ha[10;39H[10;39Hm[10;40H[10;40H0[10;41H[10;41H [10;42H[10;42Hi[10;43H[10;43Hp[10;44H[10;44H=[10;45H[10;45H:[10;46H[10;46H:[10;47H[10;47H:[10;48H[10;48H:[10;49H[10;49H:[10;50H[10;50He[10;51H[10;51Ht[10;52H[10;52Hh[10;53H[10;53H0[10;54H[10;54H:[10;55H[10;55Hd[10;56H[10;56Hh[10;57H[10;57Hc[10;58H[10;58Hp[10;59H
3394 03:43:18.947211
3395 03:43:18.947413 error: File not found.
3396 03:43:18.947615
3397 03:43:18.948056 Sending with 10 millisecond of delay
3399 03:43:23.729384 grub> devicetree (tftp,192.168.101.1)/8789805/tftp-deploy-qsd8wqq8/dtb/hip07-d05.dtb
3400 03:43:23.739968 bootloader-commands: Wait for prompt ['grub>', 'error: missing (.*) symbol.'] (timeout 00:02:43)
3401 03:43:23.740377 [12;07Hd[12;08H[12;08He[12;09H[12;09Hv[12;10H[12;10Hi[12;11H[12;11Hc[12;12H[12;12He[12;13H[12;13Ht[12;14H[12;14Hr[12;15H[12;15He[12;16H[12;16He[12;17H[12;17H [12;18H[12;18H([12;19H[12;19Ht[12;20H[12;20Hf[12;21H[12;21Ht[12;22H[12;22Hp[12;23H[12;23H,[12;24H[12;24H1[12;25H[12;25H9[12;26H[12;26H2[12;27H[12;27H.[12;28H[12;28H1[12;29H[12;29H6[12;30H[12;30H8[12;31H[12;31H.[12;32H[12;32H1[12;33H[12;33H0[12;34H[12;34H1[12;35H[12;35H.[12;36H[12;36H1[12;37H[12;37H)[12;38H[12;38H/[12;39H[12;39H8[12;40H[12;40H7[12;41H[12;41H8[12;42H[12;42H9[12;43H[12;43H8[12;44H[12;44H0[12;45H[12;45H5[12;46H[12;46H/[12;47H[12;47Ht[12;48H[12;48Hf[12;49H[12;49Ht[12;50H[12;50Hp[12;51H[12;51H-[12;52H[12;52Hd[12;53H[12;53He[12;54H[12;54Hp[12;55H[12;55Hl[12;56H[12;56Ho[12;57H[12;57Hy[12;58H[12;58H-[12;59H[12;59Hq[12;60H[12;60Hs[12;61H[12;61Hd[12;62H[12;62H8[12;63H[12;63Hw[12;64H[12;64Hq[12;65H[12;65Hq[12;66H[12;66H8[12;67H[12;67H/[12;68H[12;68Hd[12;69H[12;69Ht[12;70H[12;70Hb[12;71H[12;71H/[12;72H[12;72Hh[12;73H[12;73Hi[12;74H[12;74Hp[12;75H[12;75H0[12;76H[12;76H7[12;77H[12;77H-[12;78H[12;78Hd[12;79H[12;79H0
3402 03:43:23.740640
3403 03:43:23.740852 [12;80H[12;80H5
3404 03:43:23.741041
3405 03:43:23.906129 [13;01H[13;01H.[13;02H[13;02Hd[13;03H[13;03Ht[13;04H[13;04Hb[13;05H
3406 03:43:23.906524
3407 03:43:23.956879 Sending with 10 millisecond of delay
3409 03:43:28.852581 grub> initrd (tftp,192.168.101.1)/8789805/tftp-deploy-qsd8wqq8/ramdisk/ramdisk.cpio.gz
3410 03:43:28.863168 bootloader-commands: Wait for prompt ['grub>', 'error: missing (.*) symbol.'] (timeout 00:02:38)
3411 03:43:28.863646 [14;07Hi[14;08H[14;08Hn[14;09H[14;09Hi[14;10H[14;10Ht[14;11H[14;11Hr[14;12H[14;12Hd[14;13H[14;13H [14;14H[14;14H([14;15H[14;15Ht[14;16H[14;16Hf[14;17H[14;17Ht[14;18H[14;18Hp[14;19H[14;19H,[14;20H[14;20H1[14;21H[14;21H9[14;22H[14;22H2[14;23H[14;23H.[14;24H[14;24H1[14;25H[14;25H6[14;26H[14;26H8[14;27H[14;27H.[14;28H[14;28H1[14;29H[14;29H0[14;30H[14;30H1[14;31H[14;31H.[14;32H[14;32H1[14;33H[14;33H)[14;34H[14;34H/[14;35H[14;35H8[14;36H[14;36H7[14;37H[14;37H8[14;38H[14;38H9[14;39H[14;39H8[14;40H[14;40H0[14;41H[14;41H5[14;42H[14;42H/[14;43H[14;43Ht[14;44H[14;44Hf[14;45H[14;45Ht[14;46H[14;46Hp[14;47H[14;47H-[14;48H[14;48Hd[14;49H[14;49He[14;50H[14;50Hp[14;51H[14;51Hl[14;52H[14;52Ho[14;53H[14;53Hy[14;54H[14;54H-[14;55H[14;55Hq[14;56H[14;56Hs[14;57H[14;57Hd[14;58H[14;58H8[14;59H[14;59Hw[14;60H[14;60Hq[14;61H[14;61Hq[14;62H[14;62H8[14;63H[14;63H/[14;64H[14;64Hr[14;65H[14;65Ha[14;66H[14;66Hm[14;67H[14;67Hd[14;68H[14;68Hi[14;69H[14;69Hs[14;70H[14;70Hk[14;71H[14;71H/[14;72H[14;72Hr[14;73H[14;73Ha[14;74H[14;74Hm[14;75H[14;75Hd[14;76H[14;76Hi[14;77H[14;77Hs[14;78H[14;78Hk[14;79H[14;79H.
3412 03:43:28.863960
3413 03:43:28.864191 [14;80H[14;80Hc
3414 03:43:28.864414
3415 03:43:28.996188 [15;01H[15;01Hp[15;02H[15;02Hi[15;03H[15;03Ho[15;04H[15;04H.[15;05H[15;05Hg[15;06H[15;06Hz[15;07H
3416 03:43:28.996470
3417 03:43:28.996758 error: you need to load the kernel first.
3418 03:43:28.996997
3419 03:43:28.997457 Sending with 10 millisecond of delay
3421 03:43:29.289818 grub> boot
3422 03:43:29.300382 end: 2.6 bootloader-commands (duration 00:01:45) [common]
3423 03:43:29.300796 start: 2.7 auto-login-action (timeout 00:02:38) [common]
3424 03:43:29.301063 Setting prompt string to ['Linux version [0-9]']
3425 03:43:29.301323 boot_message is being deprecated in favour of kernel-start-message in constants
3426 03:43:29.301571 Setting prompt string to ['Linux version']
3427 03:43:29.301847 Setting prompt string to ['Linux version', 'error: missing (.*) symbol.']
3428 03:43:29.302087 auto-login-action: Wait for prompt ['Linux version', 'error: missing (.*) symbol.'] (timeout 00:05:00)
3429 03:43:29.506176 [17;07Hb[17;08H[17;08Ho[17;09H[17;09Ho[17;10H[17;10Ht[17;11H
3430 03:43:29.506564
3431 03:43:29.506915 error: you need to load the kernel first.
3432 03:43:29.507260
3434 03:46:07.302688 end: 2.7 auto-login-action (duration 00:02:38) [common]
3436 03:46:07.304094 grub-main-action failed: 1 of 3 attempts. 'auto-login-action timed out after 158 seconds'
3438 03:46:07.305285 end: 2 grub-main-action (duration 00:05:00) [common]
3440 03:46:07.306534 Cleaning after the job
3441 03:46:07.306977 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8789805/tftp-deploy-qsd8wqq8/ramdisk
3442 03:46:07.311133 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8789805/tftp-deploy-qsd8wqq8/kernel
3443 03:46:07.316445 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8789805/tftp-deploy-qsd8wqq8/dtb
3444 03:46:07.317031 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8789805/tftp-deploy-qsd8wqq8/modules
3445 03:46:07.320962 start: 5.1 power-off (timeout 00:00:30) [common]
3446 03:46:07.321368 Calling: 'nice' '/usr/local/bin/d05-power.sh' 'hip07-d05-cbg-0-bmc' 'off'
3447 03:46:07.644163 >> Chassis Power Control: Down/Off
3448 03:46:17.661074 Returned 0 in 10 seconds
3449 03:46:17.762426 end: 5.1 power-off (duration 00:00:10) [common]
3451 03:46:17.763246 start: 5.2 read-feedback (timeout 00:09:50) [common]
3452 03:46:17.764118 Listened to connection for namespace 'common' for up to 1s
3453 03:46:17.764811 Listened to connection for namespace 'common' for up to 1s
3454 03:46:18.768725 Finalising connection for namespace 'common'
3455 03:46:18.769333 Disconnecting from shell: Finalise
3456 03:46:18.769684 grub> ���l�����dsm ��a� �� 8 �
3457 03:46:18.870930 end: 5.2 read-feedback (duration 00:00:01) [common]
3458 03:46:18.871340 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/8789805
3459 03:46:18.967102 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/8789805
3460 03:46:18.967658 JobError: Your job cannot terminate cleanly.