Boot log: asus-C436FA-Flip-hatch
- Kernel Errors: 0
- Boot result: FAIL
- Kernel Warnings: 0
- Warnings: 0
- Errors: 2
1 15:49:26.049331 lava-dispatcher, installed at version: 2022.06
2 15:49:26.049519 start: 0 validate
3 15:49:26.049648 Start time: 2022-09-17 15:49:26.049642+00:00 (UTC)
4 15:49:26.049773 Using caching service: 'http://localhost/cache/?uri=%s'
5 15:49:26.049899 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20220805.0%2Fx86%2Frootfs.cpio.gz exists
6 15:49:26.338073 Using caching service: 'http://localhost/cache/?uri=%s'
7 15:49:26.338833 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv4.4-st20-229-gb433f12afe250%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 15:49:26.633379 Using caching service: 'http://localhost/cache/?uri=%s'
9 15:49:26.634091 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv4.4-st20-229-gb433f12afe250%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 15:49:26.922870 validate duration: 0.87
12 15:49:26.924218 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 15:49:26.924798 start: 1.1 download-retry (timeout 00:10:00) [common]
14 15:49:26.925369 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 15:49:26.925957 Not decompressing ramdisk as can be used compressed.
16 15:49:26.926489 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20220805.0/x86/rootfs.cpio.gz
17 15:49:26.926875 saving as /var/lib/lava/dispatcher/tmp/7300485/tftp-deploy-buu_c0w0/ramdisk/rootfs.cpio.gz
18 15:49:26.927243 total size: 8415960 (8MB)
19 15:49:26.932368 progress 0% (0MB)
20 15:49:26.944563 progress 5% (0MB)
21 15:49:26.952888 progress 10% (0MB)
22 15:49:26.958590 progress 15% (1MB)
23 15:49:26.963189 progress 20% (1MB)
24 15:49:26.967172 progress 25% (2MB)
25 15:49:26.970627 progress 30% (2MB)
26 15:49:26.973528 progress 35% (2MB)
27 15:49:26.976507 progress 40% (3MB)
28 15:49:26.979197 progress 45% (3MB)
29 15:49:26.981831 progress 50% (4MB)
30 15:49:26.984188 progress 55% (4MB)
31 15:49:26.986557 progress 60% (4MB)
32 15:49:26.988549 progress 65% (5MB)
33 15:49:26.990690 progress 70% (5MB)
34 15:49:26.992762 progress 75% (6MB)
35 15:49:26.994882 progress 80% (6MB)
36 15:49:26.996881 progress 85% (6MB)
37 15:49:26.998919 progress 90% (7MB)
38 15:49:27.000774 progress 95% (7MB)
39 15:49:27.002866 progress 100% (8MB)
40 15:49:27.003139 8MB downloaded in 0.08s (105.74MB/s)
41 15:49:27.003295 end: 1.1.1 http-download (duration 00:00:00) [common]
43 15:49:27.003540 end: 1.1 download-retry (duration 00:00:00) [common]
44 15:49:27.003630 start: 1.2 download-retry (timeout 00:10:00) [common]
45 15:49:27.003719 start: 1.2.1 http-download (timeout 00:10:00) [common]
46 15:49:27.003827 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v4.4-st20-229-gb433f12afe250/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 15:49:27.003899 saving as /var/lib/lava/dispatcher/tmp/7300485/tftp-deploy-buu_c0w0/kernel/bzImage
48 15:49:27.003971 total size: 6815632 (6MB)
49 15:49:27.004065 No compression specified
50 15:49:27.005136 progress 0% (0MB)
51 15:49:27.006896 progress 5% (0MB)
52 15:49:27.008487 progress 10% (0MB)
53 15:49:27.010318 progress 15% (1MB)
54 15:49:27.011906 progress 20% (1MB)
55 15:49:27.013499 progress 25% (1MB)
56 15:49:27.015238 progress 30% (1MB)
57 15:49:27.016811 progress 35% (2MB)
58 15:49:27.018561 progress 40% (2MB)
59 15:49:27.020123 progress 45% (2MB)
60 15:49:27.021732 progress 50% (3MB)
61 15:49:27.023430 progress 55% (3MB)
62 15:49:27.024988 progress 60% (3MB)
63 15:49:27.026739 progress 65% (4MB)
64 15:49:27.028296 progress 70% (4MB)
65 15:49:27.029897 progress 75% (4MB)
66 15:49:27.031598 progress 80% (5MB)
67 15:49:27.033148 progress 85% (5MB)
68 15:49:27.034858 progress 90% (5MB)
69 15:49:27.036415 progress 95% (6MB)
70 15:49:27.038130 progress 100% (6MB)
71 15:49:27.038410 6MB downloaded in 0.03s (188.76MB/s)
72 15:49:27.038555 end: 1.2.1 http-download (duration 00:00:00) [common]
74 15:49:27.038800 end: 1.2 download-retry (duration 00:00:00) [common]
75 15:49:27.038891 start: 1.3 download-retry (timeout 00:10:00) [common]
76 15:49:27.038980 start: 1.3.1 http-download (timeout 00:10:00) [common]
77 15:49:27.039086 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v4.4-st20-229-gb433f12afe250/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 15:49:27.039155 saving as /var/lib/lava/dispatcher/tmp/7300485/tftp-deploy-buu_c0w0/modules/modules.tar
79 15:49:27.039218 total size: 51872 (0MB)
80 15:49:27.039280 Using unxz to decompress xz
81 15:49:27.042619 progress 63% (0MB)
82 15:49:27.042979 progress 100% (0MB)
83 15:49:27.046153 0MB downloaded in 0.01s (7.14MB/s)
84 15:49:27.046372 end: 1.3.1 http-download (duration 00:00:00) [common]
86 15:49:27.046631 end: 1.3 download-retry (duration 00:00:00) [common]
87 15:49:27.046729 start: 1.4 prepare-tftp-overlay (timeout 00:10:00) [common]
88 15:49:27.046823 start: 1.4.1 extract-nfsrootfs (timeout 00:10:00) [common]
89 15:49:27.046910 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
90 15:49:27.047001 start: 1.4.2 lava-overlay (timeout 00:10:00) [common]
91 15:49:27.047159 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j
92 15:49:27.047266 makedir: /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin
93 15:49:27.047350 makedir: /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/tests
94 15:49:27.047431 makedir: /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/results
95 15:49:27.047533 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-add-keys
96 15:49:27.047660 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-add-sources
97 15:49:27.047777 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-background-process-start
98 15:49:27.047890 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-background-process-stop
99 15:49:27.048006 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-common-functions
100 15:49:27.048119 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-echo-ipv4
101 15:49:27.048230 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-install-packages
102 15:49:27.048342 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-installed-packages
103 15:49:27.048451 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-os-build
104 15:49:27.048560 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-probe-channel
105 15:49:27.048670 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-probe-ip
106 15:49:27.048778 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-target-ip
107 15:49:27.048887 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-target-mac
108 15:49:27.048995 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-target-storage
109 15:49:27.049106 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-test-case
110 15:49:27.049214 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-test-event
111 15:49:27.049367 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-test-feedback
112 15:49:27.049480 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-test-raise
113 15:49:27.049596 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-test-reference
114 15:49:27.049706 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-test-runner
115 15:49:27.049814 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-test-set
116 15:49:27.049923 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-test-shell
117 15:49:27.050036 Updating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-install-packages (oe)
118 15:49:27.050149 Updating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/bin/lava-installed-packages (oe)
119 15:49:27.050250 Creating /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/environment
120 15:49:27.050342 LAVA metadata
121 15:49:27.050416 - LAVA_JOB_ID=7300485
122 15:49:27.050482 - LAVA_DISPATCHER_IP=192.168.201.1
123 15:49:27.050584 start: 1.4.2.1 lava-vland-overlay (timeout 00:10:00) [common]
124 15:49:27.050652 skipped lava-vland-overlay
125 15:49:27.050730 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
126 15:49:27.050815 start: 1.4.2.2 lava-multinode-overlay (timeout 00:10:00) [common]
127 15:49:27.050879 skipped lava-multinode-overlay
128 15:49:27.050956 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
129 15:49:27.051041 start: 1.4.2.3 test-definition (timeout 00:10:00) [common]
130 15:49:27.051118 Loading test definitions
131 15:49:27.051215 start: 1.4.2.3.1 inline-repo-action (timeout 00:10:00) [common]
132 15:49:27.051292 Using /lava-7300485 at stage 0
133 15:49:27.051557 uuid=7300485_1.4.2.3.1 testdef=None
134 15:49:27.051652 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
135 15:49:27.051748 start: 1.4.2.3.2 test-overlay (timeout 00:10:00) [common]
136 15:49:27.052231 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
138 15:49:27.052471 start: 1.4.2.3.3 test-install-overlay (timeout 00:10:00) [common]
139 15:49:27.053033 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
141 15:49:27.053308 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:10:00) [common]
142 15:49:27.053864 runner path: /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/0/tests/0_dmesg test_uuid 7300485_1.4.2.3.1
143 15:49:27.054017 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
145 15:49:27.054254 start: 1.4.2.3.5 inline-repo-action (timeout 00:10:00) [common]
146 15:49:27.054330 Using /lava-7300485 at stage 1
147 15:49:27.054575 uuid=7300485_1.4.2.3.5 testdef=None
148 15:49:27.054667 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
149 15:49:27.054758 start: 1.4.2.3.6 test-overlay (timeout 00:10:00) [common]
150 15:49:27.055192 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
152 15:49:27.055452 start: 1.4.2.3.7 test-install-overlay (timeout 00:10:00) [common]
153 15:49:27.056020 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
155 15:49:27.056264 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:10:00) [common]
156 15:49:27.056808 runner path: /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/1/tests/1_bootrr test_uuid 7300485_1.4.2.3.5
157 15:49:27.056952 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
159 15:49:27.057170 Creating lava-test-runner.conf files
160 15:49:27.057235 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/0 for stage 0
161 15:49:27.057377 - 0_dmesg
162 15:49:27.057454 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/7300485/lava-overlay-tkxrub3j/lava-7300485/1 for stage 1
163 15:49:27.057538 - 1_bootrr
164 15:49:27.057631 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
165 15:49:27.057722 start: 1.4.2.4 compress-overlay (timeout 00:10:00) [common]
166 15:49:27.063785 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
167 15:49:27.063967 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:10:00) [common]
168 15:49:27.064060 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
169 15:49:27.064149 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
170 15:49:27.064238 start: 1.4.3 extract-overlay-ramdisk (timeout 00:10:00) [common]
171 15:49:27.245325 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
172 15:49:27.245684 start: 1.4.4 extract-modules (timeout 00:10:00) [common]
173 15:49:27.245797 extracting modules file /var/lib/lava/dispatcher/tmp/7300485/tftp-deploy-buu_c0w0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/7300485/extract-overlay-ramdisk-94owsegj/ramdisk
174 15:49:27.249823 end: 1.4.4 extract-modules (duration 00:00:00) [common]
175 15:49:27.249937 start: 1.4.5 apply-overlay-tftp (timeout 00:10:00) [common]
176 15:49:27.250026 [common] Applying overlay /var/lib/lava/dispatcher/tmp/7300485/compress-overlay-vaopb23e/overlay-1.4.2.4.tar.gz to ramdisk
177 15:49:27.250104 [common] Applying overlay /var/lib/lava/dispatcher/tmp/7300485/compress-overlay-vaopb23e/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/7300485/extract-overlay-ramdisk-94owsegj/ramdisk
178 15:49:27.253817 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
179 15:49:27.253924 start: 1.4.6 configure-preseed-file (timeout 00:10:00) [common]
180 15:49:27.254018 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
181 15:49:27.254112 start: 1.4.7 compress-ramdisk (timeout 00:10:00) [common]
182 15:49:27.254192 Building ramdisk /var/lib/lava/dispatcher/tmp/7300485/extract-overlay-ramdisk-94owsegj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/7300485/extract-overlay-ramdisk-94owsegj/ramdisk
183 15:49:27.317664 >> 48006 blocks
184 15:49:28.049662 rename /var/lib/lava/dispatcher/tmp/7300485/extract-overlay-ramdisk-94owsegj/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/7300485/tftp-deploy-buu_c0w0/ramdisk/ramdisk.cpio.gz
185 15:49:28.050071 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
186 15:49:28.050195 start: 1.4.8 prepare-kernel (timeout 00:09:59) [common]
187 15:49:28.050300 start: 1.4.8.1 prepare-fit (timeout 00:09:59) [common]
188 15:49:28.050394 No mkimage arch provided, not using FIT.
189 15:49:28.050487 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
190 15:49:28.050574 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
191 15:49:28.050668 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
192 15:49:28.050763 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:59) [common]
193 15:49:28.050840 No LXC device requested
194 15:49:28.050921 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
195 15:49:28.051009 start: 1.6 deploy-device-env (timeout 00:09:59) [common]
196 15:49:28.051091 end: 1.6 deploy-device-env (duration 00:00:00) [common]
197 15:49:28.051163 Checking files for TFTP limit of 4294967296 bytes.
198 15:49:28.051547 end: 1 tftp-deploy (duration 00:00:01) [common]
199 15:49:28.051657 start: 2 depthcharge-action (timeout 00:05:00) [common]
200 15:49:28.051752 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
201 15:49:28.051884 substitutions:
202 15:49:28.051954 - {DTB}: None
203 15:49:28.052022 - {INITRD}: 7300485/tftp-deploy-buu_c0w0/ramdisk/ramdisk.cpio.gz
204 15:49:28.052084 - {KERNEL}: 7300485/tftp-deploy-buu_c0w0/kernel/bzImage
205 15:49:28.052145 - {LAVA_MAC}: None
206 15:49:28.052204 - {PRESEED_CONFIG}: None
207 15:49:28.052263 - {PRESEED_LOCAL}: None
208 15:49:28.052321 - {RAMDISK}: 7300485/tftp-deploy-buu_c0w0/ramdisk/ramdisk.cpio.gz
209 15:49:28.052380 - {ROOT_PART}: None
210 15:49:28.052439 - {ROOT}: None
211 15:49:28.052497 - {SERVER_IP}: 192.168.201.1
212 15:49:28.052553 - {TEE}: None
213 15:49:28.052611 Parsed boot commands:
214 15:49:28.052667 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
215 15:49:28.052820 Parsed boot commands: tftpboot 192.168.201.1 7300485/tftp-deploy-buu_c0w0/kernel/bzImage 7300485/tftp-deploy-buu_c0w0/kernel/cmdline 7300485/tftp-deploy-buu_c0w0/ramdisk/ramdisk.cpio.gz
216 15:49:28.052913 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
217 15:49:28.053013 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
218 15:49:28.053110 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
219 15:49:28.053203 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
220 15:49:28.053281 Not connected, no need to disconnect.
221 15:49:28.053364 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
222 15:49:28.053452 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
223 15:49:28.053521 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost asus-C436FA-Flip-hatch-cbg-3'
224 15:49:28.056177 Setting prompt string to ['lava-test: # ']
225 15:49:28.056462 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
226 15:49:28.056565 end: 2.2.1 reset-connection (duration 00:00:00) [common]
227 15:49:28.056670 start: 2.2.2 reset-device (timeout 00:05:00) [common]
228 15:49:28.056764 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
229 15:49:28.056939 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-3' '--port=1' '--command=reboot'
230 15:49:28.076102 >> Command sent successfully.
231 15:49:28.078007 Returned 0 in 0 seconds
232 15:49:28.179256 end: 2.2.2.1 pdu-reboot (duration 00:00:00) [common]
234 15:49:28.180734 end: 2.2.2 reset-device (duration 00:00:00) [common]
235 15:49:28.181415 start: 2.2.3 depthcharge-start (timeout 00:05:00) [common]
236 15:49:28.181898 Setting prompt string to 'Starting depthcharge on Helios...'
237 15:49:28.182318 Changing prompt to 'Starting depthcharge on Helios...'
238 15:49:28.182792 depthcharge-start: Wait for prompt Starting depthcharge on Helios... (timeout 00:05:00)
239 15:49:28.184225 [Enter `^Ec?' for help]
240 15:49:35.708647
241 15:49:35.709350
242 15:49:35.718440 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
243 15:49:35.721556 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
244 15:49:35.728158 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
245 15:49:35.731789 CPU: AES supported, TXT NOT supported, VT supported
246 15:49:35.738175 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
247 15:49:35.741630 PCH: device id 0284 (rev 00) is Cometlake-U Premium
248 15:49:35.748119 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
249 15:49:35.751847 VBOOT: Loading verstage.
250 15:49:35.754988 FMAP: Found \"FLASH\" version 1.1 at 0xc04000.
251 15:49:35.761360 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
252 15:49:35.767978 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
253 15:49:35.768576 CBFS @ c08000 size 3f8000
254 15:49:35.774320 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
255 15:49:35.778061 CBFS: Locating 'fallback/verstage'
256 15:49:35.781128 CBFS: Found @ offset 10fb80 size 1072c
257 15:49:35.785683
258 15:49:35.786284
259 15:49:35.795377 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
260 15:49:35.809688 Probing TPM: . done!
261 15:49:35.813171 TPM ready after 0 ms
262 15:49:35.816616 Connected to device vid:did:rid of 1ae0:0028:00
263 15:49:35.826872 Firmware version: B2-C:0 RO_A:0.0.10/29d77172 RW_B:0.3.23/cr50_v1.9308_87_mp.320-aa1dd98
264 15:49:35.830395 Initialized TPM device CR50 revision 0
265 15:49:35.862934 tlcl_send_startup: Startup return code is 0
266 15:49:35.863521 TPM: setup succeeded
267 15:49:35.875838 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
268 15:49:35.879205 Chrome EC: UHEPI supported
269 15:49:35.882736 Phase 1
270 15:49:35.885935 FMAP: area GBB found @ c05000 (12288 bytes)
271 15:49:35.892279 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
272 15:49:35.895728 Phase 2
273 15:49:35.896314 Phase 3
274 15:49:35.899531 FMAP: area GBB found @ c05000 (12288 bytes)
275 15:49:35.905515 VB2:vb2_report_dev_firmware() This is developer signed firmware
276 15:49:35.912374 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
277 15:49:35.915051 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
278 15:49:35.921708 VB2:vb2_verify_keyblock() Checking keyblock signature...
279 15:49:35.938317 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
280 15:49:35.941574 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
281 15:49:35.948419 VB2:vb2_verify_fw_preamble() Verifying preamble.
282 15:49:35.952642 Phase 4
283 15:49:35.956025 FMAP: area FW_MAIN_A found @ 410000 (3506112 bytes)
284 15:49:35.962190 VB2:vb2api_init_hash() HW crypto for hash_alg 2 not supported, using SW
285 15:49:36.141999 VB2:vb2_rsa_verify_digest() Digest check failed!
286 15:49:36.148912 VB2:vb2api_fail() Need recovery, reason: 0x1b / 0x7
287 15:49:36.149533 Saving nvdata
288 15:49:36.152196 Reboot requested (10020007)
289 15:49:36.155525 board_reset() called!
290 15:49:36.156121 full_reset() called!
291 15:49:40.675724
292 15:49:40.676311
293 15:49:40.685551 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
294 15:49:40.688915 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
295 15:49:40.695465 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
296 15:49:40.698933 CPU: AES supported, TXT NOT supported, VT supported
297 15:49:40.705336 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
298 15:49:40.712276 PCH: device id 0284 (rev 00) is Cometlake-U Premium
299 15:49:40.714985 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
300 15:49:40.718117 VBOOT: Loading verstage.
301 15:49:40.725005 FMAP: Found \"FLASH\" version 1.1 at 0xc04000.
302 15:49:40.728190 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
303 15:49:40.734989 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
304 15:49:40.735489 CBFS @ c08000 size 3f8000
305 15:49:40.741453 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
306 15:49:40.744968 CBFS: Locating 'fallback/verstage'
307 15:49:40.748212 CBFS: Found @ offset 10fb80 size 1072c
308 15:49:40.752269
309 15:49:40.752769
310 15:49:40.762096 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
311 15:49:40.776747 Probing TPM: . done!
312 15:49:40.780533 TPM ready after 0 ms
313 15:49:40.783782 Connected to device vid:did:rid of 1ae0:0028:00
314 15:49:40.794119 Firmware version: B2-C:0 RO_A:0.0.10/29d77172 RW_B:0.3.23/cr50_v1.9308_87_mp.320-aa1dd98
315 15:49:40.797029 Initialized TPM device CR50 revision 0
316 15:49:40.830180 tlcl_send_startup: Startup return code is 0
317 15:49:40.830798 TPM: setup succeeded
318 15:49:40.843033 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
319 15:49:40.846480 Chrome EC: UHEPI supported
320 15:49:40.849900 Phase 1
321 15:49:40.853094 FMAP: area GBB found @ c05000 (12288 bytes)
322 15:49:40.860197 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
323 15:49:40.866411 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x0
324 15:49:40.869880 Recovery requested (1009000e)
325 15:49:40.876067 Saving nvdata
326 15:49:40.882059 tlcl_extend: response is 0
327 15:49:40.890256 tlcl_extend: response is 0
328 15:49:40.897049 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
329 15:49:40.900632 CBFS @ c08000 size 3f8000
330 15:49:40.907196 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
331 15:49:40.910791 CBFS: Locating 'fallback/romstage'
332 15:49:40.913939 CBFS: Found @ offset 80 size 145fc
333 15:49:40.917097 Accumulated console time in verstage 98 ms
334 15:49:40.917706
335 15:49:40.918306
336 15:49:40.930343 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 romstage starting (log level: 8)...
337 15:49:40.936760 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
338 15:49:40.940259 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
339 15:49:40.943294 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
340 15:49:40.950204 gpe0_sts[1]: 00200000 gpe0_en[1]: 00000000
341 15:49:40.953415 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
342 15:49:40.956718 gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000
343 15:49:40.959965 TCO_STS: 0000 0000
344 15:49:40.963896 GEN_PMCON: e0015238 00000200
345 15:49:40.966765 GBLRST_CAUSE: 00000000 00000000
346 15:49:40.967365 prev_sleep_state 5
347 15:49:40.970062 Boot Count incremented to 31537
348 15:49:40.977391 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
349 15:49:40.980413 CBFS @ c08000 size 3f8000
350 15:49:40.987022 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
351 15:49:40.987620 CBFS: Locating 'fspm.bin'
352 15:49:40.993712 CBFS: Found @ offset 5ffc0 size 71000
353 15:49:40.996719 Chrome EC: UHEPI supported
354 15:49:41.003812 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
355 15:49:41.006859 Probing TPM: done!
356 15:49:41.013866 Connected to device vid:did:rid of 1ae0:0028:00
357 15:49:41.023204 Firmware version: B2-C:0 RO_A:0.0.10/29d77172 RW_B:0.3.23/cr50_v1.9308_87_mp.320-aa1dd98
358 15:49:41.029608 Initialized TPM device CR50 revision 0
359 15:49:41.038020 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
360 15:49:41.048306 MRC: Hash comparison successful. Using data from RECOVERY_MRC_CACHE
361 15:49:41.048894 MRC cache found, size 1948
362 15:49:41.051600 bootmode is set to: 2
363 15:49:41.054683 PRMRR disabled by config.
364 15:49:41.058182 SPD INDEX = 1
365 15:49:41.061495 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
366 15:49:41.064558 CBFS @ c08000 size 3f8000
367 15:49:41.071481 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
368 15:49:41.072092 CBFS: Locating 'spd.bin'
369 15:49:41.074604 CBFS: Found @ offset 5fb80 size 400
370 15:49:41.077973 SPD: module type is LPDDR3
371 15:49:41.081324 SPD: module part is
372 15:49:41.088185 SPD: banks 16, ranks 2, rows 15, columns 11, density 8192 Mb
373 15:49:41.091392 SPD: device width 4 bits, bus width 8 bits
374 15:49:41.094264 SPD: module size is 4096 MB (per channel)
375 15:49:41.097931 memory slot: 0 configuration done.
376 15:49:41.101467 memory slot: 2 configuration done.
377 15:49:41.152888 CBMEM:
378 15:49:41.156530 IMD: root @ 99fff000 254 entries.
379 15:49:41.160171 IMD: root @ 99ffec00 62 entries.
380 15:49:41.162519 External stage cache:
381 15:49:41.166255 IMD: root @ 9abff000 254 entries.
382 15:49:41.169573 IMD: root @ 9abfec00 62 entries.
383 15:49:41.176445 Chrome EC: clear events_b mask to 0x0000000020004000
384 15:49:41.188924 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
385 15:49:41.202046 tlcl_write: response is 0
386 15:49:41.211002 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
387 15:49:41.217632 MRC: TPM MRC hash updated successfully.
388 15:49:41.218336 2 DIMMs found
389 15:49:41.220685 SMM Memory Map
390 15:49:41.224430 SMRAM : 0x9a000000 0x1000000
391 15:49:41.227712 Subregion 0: 0x9a000000 0xa00000
392 15:49:41.230908 Subregion 1: 0x9aa00000 0x200000
393 15:49:41.234349 Subregion 2: 0x9ac00000 0x400000
394 15:49:41.237400 top_of_ram = 0x9a000000
395 15:49:41.240758 MTRR Range: Start=99000000 End=9a000000 (Size 1000000)
396 15:49:41.247234 MTRR Range: Start=9a000000 End=9b000000 (Size 1000000)
397 15:49:41.250214 MTRR Range: Start=ff000000 End=0 (Size 1000000)
398 15:49:41.257203 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
399 15:49:41.260815 CBFS @ c08000 size 3f8000
400 15:49:41.263646 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
401 15:49:41.267070 CBFS: Locating 'fallback/postcar'
402 15:49:41.273565 CBFS: Found @ offset 107000 size 4b44
403 15:49:41.280439 Decompressing stage fallback/postcar @ 0x99c0bfc0 (35640 bytes)
404 15:49:41.290247 Loading module at 99c0c000 with entry 99c0c000. filesize: 0x4818 memsize: 0x8af8
405 15:49:41.293710 Processing 180 relocs. Offset value of 0x97c0c000
406 15:49:41.301901 Accumulated console time in romstage 286 ms
407 15:49:41.302496
408 15:49:41.302889
409 15:49:41.312073 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 postcar starting (log level: 8)...
410 15:49:41.318522 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
411 15:49:41.321450 CBFS @ c08000 size 3f8000
412 15:49:41.324798 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
413 15:49:41.331399 CBFS: Locating 'fallback/ramstage'
414 15:49:41.334433 CBFS: Found @ offset 43380 size 1b9e8
415 15:49:41.341250 Decompressing stage fallback/ramstage @ 0x99baffc0 (372088 bytes)
416 15:49:41.373249 Loading module at 99bb0000 with entry 99bb0000. filesize: 0x40940 memsize: 0x5ad38
417 15:49:41.379925 Processing 3976 relocs. Offset value of 0x98db0000
418 15:49:41.383185 Accumulated console time in postcar 52 ms
419 15:49:41.383783
420 15:49:41.384178
421 15:49:41.393050 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 ramstage starting (log level: 8)...
422 15:49:41.400033 FMAP: area RO_VPD found @ c00000 (16384 bytes)
423 15:49:41.403214 WARNING: RO_VPD is uninitialized or empty.
424 15:49:41.406412 FMAP: area RW_VPD found @ af8000 (8192 bytes)
425 15:49:41.412913 FMAP: area RW_VPD found @ af8000 (8192 bytes)
426 15:49:41.413547 Normal boot.
427 15:49:41.419173 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
428 15:49:41.422774 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
429 15:49:41.425835 CBFS @ c08000 size 3f8000
430 15:49:41.432163 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
431 15:49:41.436128 CBFS: Locating 'cpu_microcode_blob.bin'
432 15:49:41.438815 CBFS: Found @ offset 14700 size 2ec00
433 15:49:41.442643 microcode: sig=0x806ec pf=0x4 revision=0xc9
434 15:49:41.445472 Skip microcode update
435 15:49:41.452545 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
436 15:49:41.453108 CBFS @ c08000 size 3f8000
437 15:49:41.458969 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
438 15:49:41.462146 CBFS: Locating 'fsps.bin'
439 15:49:41.465427 CBFS: Found @ offset d1fc0 size 35000
440 15:49:41.491957 Detected 4 core, 8 thread CPU.
441 15:49:41.495013 Setting up SMI for CPU
442 15:49:41.498130 IED base = 0x9ac00000
443 15:49:41.498745 IED size = 0x00400000
444 15:49:41.501952 Will perform SMM setup.
445 15:49:41.507957 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz.
446 15:49:41.514938 Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170
447 15:49:41.521491 Processing 16 relocs. Offset value of 0x00030000
448 15:49:41.522083 Attempting to start 7 APs
449 15:49:41.527589 Waiting for 10ms after sending INIT.
450 15:49:41.541461 Waiting for 1st SIPI to complete...done.
451 15:49:41.542057 AP: slot 5 apic_id 6.
452 15:49:41.545069 AP: slot 4 apic_id 5.
453 15:49:41.548278 AP: slot 7 apic_id 4.
454 15:49:41.548859 AP: slot 6 apic_id 7.
455 15:49:41.551092 AP: slot 2 apic_id 1.
456 15:49:41.554592 Waiting for 2nd SIPI to complete...done.
457 15:49:41.557752 AP: slot 1 apic_id 3.
458 15:49:41.561063 AP: slot 3 apic_id 2.
459 15:49:41.567834 Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8
460 15:49:41.574035 Processing 13 relocs. Offset value of 0x00038000
461 15:49:41.580646 SMM Module: stub loaded at 00038000. Will call 99bcb71d(00000000)
462 15:49:41.584631 Installing SMM handler to 0x9a000000
463 15:49:41.590909 Loading module at 9a010000 with entry 9a010a52. filesize: 0x7e88 memsize: 0xcf58
464 15:49:41.597616 Processing 658 relocs. Offset value of 0x9a010000
465 15:49:41.603775 Loading module at 9a008000 with entry 9a008000. filesize: 0x1a8 memsize: 0x1a8
466 15:49:41.607609 Processing 13 relocs. Offset value of 0x9a008000
467 15:49:41.613964 SMM Module: placing jmp sequence at 9a007c00 rel16 0x03fd
468 15:49:41.620480 SMM Module: placing jmp sequence at 9a007800 rel16 0x07fd
469 15:49:41.627366 SMM Module: placing jmp sequence at 9a007400 rel16 0x0bfd
470 15:49:41.630576 SMM Module: placing jmp sequence at 9a007000 rel16 0x0ffd
471 15:49:41.637334 SMM Module: placing jmp sequence at 9a006c00 rel16 0x13fd
472 15:49:41.643493 SMM Module: placing jmp sequence at 9a006800 rel16 0x17fd
473 15:49:41.649870 SMM Module: placing jmp sequence at 9a006400 rel16 0x1bfd
474 15:49:41.656663 SMM Module: stub loaded at 9a008000. Will call 9a010a52(00000000)
475 15:49:41.660210 Clearing SMI status registers
476 15:49:41.660795 SMI_STS: PM1
477 15:49:41.663185 PM1_STS: PWRBTN
478 15:49:41.663769 TCO_STS: SECOND_TO
479 15:49:41.666899 New SMBASE 0x9a000000
480 15:49:41.670070 In relocation handler: CPU 0
481 15:49:41.673572 New SMBASE=0x9a000000 IEDBASE=0x9ac00000
482 15:49:41.676750 Writing SMRR. base = 0x9a000006, mask=0xff000800
483 15:49:41.679725 Relocation complete.
484 15:49:41.682980 New SMBASE 0x99fff800
485 15:49:41.686432 In relocation handler: CPU 2
486 15:49:41.689872 New SMBASE=0x99fff800 IEDBASE=0x9ac00000
487 15:49:41.693014 Writing SMRR. base = 0x9a000006, mask=0xff000800
488 15:49:41.696447 Relocation complete.
489 15:49:41.699444 New SMBASE 0x99fff400
490 15:49:41.702767 In relocation handler: CPU 3
491 15:49:41.706150 New SMBASE=0x99fff400 IEDBASE=0x9ac00000
492 15:49:41.709646 Writing SMRR. base = 0x9a000006, mask=0xff000800
493 15:49:41.712851 Relocation complete.
494 15:49:41.716058 New SMBASE 0x99fffc00
495 15:49:41.719120 In relocation handler: CPU 1
496 15:49:41.722774 New SMBASE=0x99fffc00 IEDBASE=0x9ac00000
497 15:49:41.726202 Writing SMRR. base = 0x9a000006, mask=0xff000800
498 15:49:41.729216 Relocation complete.
499 15:49:41.732846 New SMBASE 0x99ffe800
500 15:49:41.736026 In relocation handler: CPU 6
501 15:49:41.738782 New SMBASE=0x99ffe800 IEDBASE=0x9ac00000
502 15:49:41.742206 Writing SMRR. base = 0x9a000006, mask=0xff000800
503 15:49:41.745477 Relocation complete.
504 15:49:41.748696 New SMBASE 0x99ffec00
505 15:49:41.752161 In relocation handler: CPU 5
506 15:49:41.755414 New SMBASE=0x99ffec00 IEDBASE=0x9ac00000
507 15:49:41.758803 Writing SMRR. base = 0x9a000006, mask=0xff000800
508 15:49:41.762159 Relocation complete.
509 15:49:41.765478 New SMBASE 0x99fff000
510 15:49:41.768949 In relocation handler: CPU 4
511 15:49:41.771786 New SMBASE=0x99fff000 IEDBASE=0x9ac00000
512 15:49:41.775771 Writing SMRR. base = 0x9a000006, mask=0xff000800
513 15:49:41.778620 Relocation complete.
514 15:49:41.781898 New SMBASE 0x99ffe400
515 15:49:41.784947 In relocation handler: CPU 7
516 15:49:41.788422 New SMBASE=0x99ffe400 IEDBASE=0x9ac00000
517 15:49:41.791777 Writing SMRR. base = 0x9a000006, mask=0xff000800
518 15:49:41.795007 Relocation complete.
519 15:49:41.797955 Initializing CPU #0
520 15:49:41.801215 CPU: vendor Intel device 806ec
521 15:49:41.804754 CPU: family 06, model 8e, stepping 0c
522 15:49:41.808331 Clearing out pending MCEs
523 15:49:41.808914 Setting up local APIC...
524 15:49:41.811737 apic_id: 0x00 done.
525 15:49:41.814664 Turbo is available but hidden
526 15:49:41.818027 Turbo is available and visible
527 15:49:41.821435 VMX status: enabled
528 15:49:41.824770 IA32_FEATURE_CONTROL status: locked
529 15:49:41.825387 Skip microcode update
530 15:49:41.828113 CPU #0 initialized
531 15:49:41.831297 Initializing CPU #2
532 15:49:41.831883 Initializing CPU #1
533 15:49:41.834324 Initializing CPU #3
534 15:49:41.837402 CPU: vendor Intel device 806ec
535 15:49:41.841079 CPU: family 06, model 8e, stepping 0c
536 15:49:41.844155 CPU: vendor Intel device 806ec
537 15:49:41.847533 CPU: family 06, model 8e, stepping 0c
538 15:49:41.851165 Clearing out pending MCEs
539 15:49:41.853977 Clearing out pending MCEs
540 15:49:41.854465 Setting up local APIC...
541 15:49:41.857548 Initializing CPU #4
542 15:49:41.860908 Initializing CPU #7
543 15:49:41.864156 CPU: vendor Intel device 806ec
544 15:49:41.867390 CPU: family 06, model 8e, stepping 0c
545 15:49:41.870260 CPU: vendor Intel device 806ec
546 15:49:41.873884 CPU: family 06, model 8e, stepping 0c
547 15:49:41.877308 Clearing out pending MCEs
548 15:49:41.877891 Clearing out pending MCEs
549 15:49:41.880363 Setting up local APIC...
550 15:49:41.883677 CPU: vendor Intel device 806ec
551 15:49:41.887417 CPU: family 06, model 8e, stepping 0c
552 15:49:41.890524 Clearing out pending MCEs
553 15:49:41.893891 Initializing CPU #6
554 15:49:41.894472 Initializing CPU #5
555 15:49:41.897061 CPU: vendor Intel device 806ec
556 15:49:41.900081 CPU: family 06, model 8e, stepping 0c
557 15:49:41.903797 CPU: vendor Intel device 806ec
558 15:49:41.910142 CPU: family 06, model 8e, stepping 0c
559 15:49:41.910729 Clearing out pending MCEs
560 15:49:41.913185 Clearing out pending MCEs
561 15:49:41.916519 Setting up local APIC...
562 15:49:41.919511 Setting up local APIC...
563 15:49:41.919964 Setting up local APIC...
564 15:49:41.923364 apic_id: 0x06 done.
565 15:49:41.926580 Setting up local APIC...
566 15:49:41.929984 apic_id: 0x01 done.
567 15:49:41.930569 VMX status: enabled
568 15:49:41.933094 apic_id: 0x07 done.
569 15:49:41.936555 IA32_FEATURE_CONTROL status: locked
570 15:49:41.939554 VMX status: enabled
571 15:49:41.940046 Skip microcode update
572 15:49:41.942671 IA32_FEATURE_CONTROL status: locked
573 15:49:41.946417 CPU #5 initialized
574 15:49:41.949078 Skip microcode update
575 15:49:41.949610 apic_id: 0x02 done.
576 15:49:41.952433 apic_id: 0x03 done.
577 15:49:41.952924 VMX status: enabled
578 15:49:41.955879 VMX status: enabled
579 15:49:41.959436 IA32_FEATURE_CONTROL status: locked
580 15:49:41.962482 IA32_FEATURE_CONTROL status: locked
581 15:49:41.965669 Skip microcode update
582 15:49:41.969160 Skip microcode update
583 15:49:41.969685 CPU #3 initialized
584 15:49:41.972638 CPU #1 initialized
585 15:49:41.973128 apic_id: 0x04 done.
586 15:49:41.975725 Setting up local APIC...
587 15:49:41.979003 CPU #6 initialized
588 15:49:41.979494 apic_id: 0x05 done.
589 15:49:41.982411 VMX status: enabled
590 15:49:41.985671 VMX status: enabled
591 15:49:41.989049 IA32_FEATURE_CONTROL status: locked
592 15:49:41.992202 IA32_FEATURE_CONTROL status: locked
593 15:49:41.996110 Skip microcode update
594 15:49:41.996711 VMX status: enabled
595 15:49:41.999081 Skip microcode update
596 15:49:41.999571 CPU #7 initialized
597 15:49:42.002417 CPU #4 initialized
598 15:49:42.005338 IA32_FEATURE_CONTROL status: locked
599 15:49:42.008873 Skip microcode update
600 15:49:42.009505 CPU #2 initialized
601 15:49:42.015653 bsp_do_flight_plan done after 457 msecs.
602 15:49:42.018906 CPU: frequency set to 4200 MHz
603 15:49:42.019563 Enabling SMIs.
604 15:49:42.022072 Locking SMM.
605 15:49:42.035507 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
606 15:49:42.038498 CBFS @ c08000 size 3f8000
607 15:49:42.045358 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
608 15:49:42.045855 CBFS: Locating 'vbt.bin'
609 15:49:42.048657 CBFS: Found @ offset 5f5c0 size 499
610 15:49:42.055259 Found a VBT of 4608 bytes after decompression
611 15:49:42.235349 Display FSP Version Info HOB
612 15:49:42.238436 Reference Code - CPU = 9.0.1e.30
613 15:49:42.241762 uCode Version = 0.0.0.ca
614 15:49:42.244824 TXT ACM version = ff.ff.ff.ffff
615 15:49:42.248586 Display FSP Version Info HOB
616 15:49:42.251460 Reference Code - ME = 9.0.1e.30
617 15:49:42.255024 MEBx version = 0.0.0.0
618 15:49:42.257958 ME Firmware Version = Consumer SKU
619 15:49:42.261857 Display FSP Version Info HOB
620 15:49:42.264680 Reference Code - CML PCH = 9.0.1e.30
621 15:49:42.268025 PCH-CRID Status = Disabled
622 15:49:42.270998 PCH-CRID Original Value = ff.ff.ff.ffff
623 15:49:42.274513 PCH-CRID New Value = ff.ff.ff.ffff
624 15:49:42.277592 OPROM - RST - RAID = ff.ff.ff.ffff
625 15:49:42.281170 ChipsetInit Base Version = ff.ff.ff.ffff
626 15:49:42.287676 ChipsetInit Oem Version = ff.ff.ff.ffff
627 15:49:42.288268 Display FSP Version Info HOB
628 15:49:42.294216 Reference Code - SA - System Agent = 9.0.1e.30
629 15:49:42.297894 Reference Code - MRC = 0.7.1.6c
630 15:49:42.300885 SA - PCIe Version = 9.0.1e.30
631 15:49:42.304047 SA-CRID Status = Disabled
632 15:49:42.307599 SA-CRID Original Value = 0.0.0.c
633 15:49:42.308249 SA-CRID New Value = 0.0.0.c
634 15:49:42.310607 OPROM - VBIOS = ff.ff.ff.ffff
635 15:49:42.314288 RTC Init
636 15:49:42.317694 Set power on after power failure.
637 15:49:42.318283 Disabling Deep S3
638 15:49:42.320700 Disabling Deep S3
639 15:49:42.324666 Disabling Deep S4
640 15:49:42.325255 Disabling Deep S4
641 15:49:42.326938 Disabling Deep S5
642 15:49:42.327424 Disabling Deep S5
643 15:49:42.333903 BS: BS_DEV_INIT_CHIPS times (ms): entry 36 run 190 exit 1
644 15:49:42.336912 Enumerating buses...
645 15:49:42.340251 Show all devs... Before device enumeration.
646 15:49:42.343622 Root Device: enabled 1
647 15:49:42.346581 CPU_CLUSTER: 0: enabled 1
648 15:49:42.347070 DOMAIN: 0000: enabled 1
649 15:49:42.349841 APIC: 00: enabled 1
650 15:49:42.353452 PCI: 00:00.0: enabled 1
651 15:49:42.356911 PCI: 00:02.0: enabled 1
652 15:49:42.357547 PCI: 00:04.0: enabled 0
653 15:49:42.359767 PCI: 00:05.0: enabled 0
654 15:49:42.363686 PCI: 00:12.0: enabled 1
655 15:49:42.364280 PCI: 00:12.5: enabled 0
656 15:49:42.366504 PCI: 00:12.6: enabled 0
657 15:49:42.369716 PCI: 00:14.0: enabled 1
658 15:49:42.372989 PCI: 00:14.1: enabled 0
659 15:49:42.373500 PCI: 00:14.3: enabled 1
660 15:49:42.376080 PCI: 00:14.5: enabled 0
661 15:49:42.379491 PCI: 00:15.0: enabled 1
662 15:49:42.383307 PCI: 00:15.1: enabled 1
663 15:49:42.383899 PCI: 00:15.2: enabled 0
664 15:49:42.386389 PCI: 00:15.3: enabled 0
665 15:49:42.389297 PCI: 00:16.0: enabled 1
666 15:49:42.392272 PCI: 00:16.1: enabled 0
667 15:49:42.392777 PCI: 00:16.2: enabled 0
668 15:49:42.395503 PCI: 00:16.3: enabled 0
669 15:49:42.399325 PCI: 00:16.4: enabled 0
670 15:49:42.402491 PCI: 00:16.5: enabled 0
671 15:49:42.403052 PCI: 00:17.0: enabled 1
672 15:49:42.405550 PCI: 00:19.0: enabled 1
673 15:49:42.408966 PCI: 00:19.1: enabled 0
674 15:49:42.412256 PCI: 00:19.2: enabled 0
675 15:49:42.412837 PCI: 00:1a.0: enabled 0
676 15:49:42.415672 PCI: 00:1c.0: enabled 0
677 15:49:42.418466 PCI: 00:1c.1: enabled 0
678 15:49:42.422025 PCI: 00:1c.2: enabled 0
679 15:49:42.422464 PCI: 00:1c.3: enabled 0
680 15:49:42.424878 PCI: 00:1c.4: enabled 0
681 15:49:42.428474 PCI: 00:1c.5: enabled 0
682 15:49:42.431730 PCI: 00:1c.6: enabled 0
683 15:49:42.432318 PCI: 00:1c.7: enabled 0
684 15:49:42.434837 PCI: 00:1d.0: enabled 1
685 15:49:42.438258 PCI: 00:1d.1: enabled 0
686 15:49:42.441565 PCI: 00:1d.2: enabled 0
687 15:49:42.442080 PCI: 00:1d.3: enabled 0
688 15:49:42.445002 PCI: 00:1d.4: enabled 0
689 15:49:42.447992 PCI: 00:1d.5: enabled 1
690 15:49:42.451464 PCI: 00:1e.0: enabled 1
691 15:49:42.452069 PCI: 00:1e.1: enabled 0
692 15:49:42.454471 PCI: 00:1e.2: enabled 1
693 15:49:42.457727 PCI: 00:1e.3: enabled 1
694 15:49:42.458218 PCI: 00:1f.0: enabled 1
695 15:49:42.461315 PCI: 00:1f.1: enabled 1
696 15:49:42.464629 PCI: 00:1f.2: enabled 1
697 15:49:42.467948 PCI: 00:1f.3: enabled 1
698 15:49:42.468549 PCI: 00:1f.4: enabled 1
699 15:49:42.470858 PCI: 00:1f.5: enabled 1
700 15:49:42.474280 PCI: 00:1f.6: enabled 0
701 15:49:42.477515 USB0 port 0: enabled 1
702 15:49:42.478005 I2C: 00:15: enabled 1
703 15:49:42.481098 I2C: 00:5d: enabled 1
704 15:49:42.484364 GENERIC: 0.0: enabled 1
705 15:49:42.484958 I2C: 00:1a: enabled 1
706 15:49:42.487288 I2C: 00:38: enabled 1
707 15:49:42.490469 I2C: 00:39: enabled 1
708 15:49:42.490957 I2C: 00:3a: enabled 1
709 15:49:42.494232 I2C: 00:3b: enabled 1
710 15:49:42.497619 PCI: 00:00.0: enabled 1
711 15:49:42.500641 SPI: 00: enabled 1
712 15:49:42.501247 SPI: 01: enabled 1
713 15:49:42.503909 PNP: 0c09.0: enabled 1
714 15:49:42.507287 USB2 port 0: enabled 1
715 15:49:42.507888 USB2 port 1: enabled 1
716 15:49:42.510231 USB2 port 2: enabled 0
717 15:49:42.513674 USB2 port 3: enabled 0
718 15:49:42.514263 USB2 port 5: enabled 0
719 15:49:42.517616 USB2 port 6: enabled 1
720 15:49:42.520152 USB2 port 9: enabled 1
721 15:49:42.523266 USB3 port 0: enabled 1
722 15:49:42.523755 USB3 port 1: enabled 1
723 15:49:42.526684 USB3 port 2: enabled 1
724 15:49:42.529831 USB3 port 3: enabled 1
725 15:49:42.530318 USB3 port 4: enabled 0
726 15:49:42.533423 APIC: 03: enabled 1
727 15:49:42.536909 APIC: 01: enabled 1
728 15:49:42.537532 APIC: 02: enabled 1
729 15:49:42.540074 APIC: 05: enabled 1
730 15:49:42.540561 APIC: 06: enabled 1
731 15:49:42.542835 APIC: 07: enabled 1
732 15:49:42.546619 APIC: 04: enabled 1
733 15:49:42.547213 Compare with tree...
734 15:49:42.549652 Root Device: enabled 1
735 15:49:42.553014 CPU_CLUSTER: 0: enabled 1
736 15:49:42.556371 APIC: 00: enabled 1
737 15:49:42.556859 APIC: 03: enabled 1
738 15:49:42.559944 APIC: 01: enabled 1
739 15:49:42.562429 APIC: 02: enabled 1
740 15:49:42.562919 APIC: 05: enabled 1
741 15:49:42.565702 APIC: 06: enabled 1
742 15:49:42.569213 APIC: 07: enabled 1
743 15:49:42.569841 APIC: 04: enabled 1
744 15:49:42.572560 DOMAIN: 0000: enabled 1
745 15:49:42.575960 PCI: 00:00.0: enabled 1
746 15:49:42.579080 PCI: 00:02.0: enabled 1
747 15:49:42.582297 PCI: 00:04.0: enabled 0
748 15:49:42.582907 PCI: 00:05.0: enabled 0
749 15:49:42.585679 PCI: 00:12.0: enabled 1
750 15:49:42.589007 PCI: 00:12.5: enabled 0
751 15:49:42.592148 PCI: 00:12.6: enabled 0
752 15:49:42.595553 PCI: 00:14.0: enabled 1
753 15:49:42.596146 USB0 port 0: enabled 1
754 15:49:42.598440 USB2 port 0: enabled 1
755 15:49:42.601978 USB2 port 1: enabled 1
756 15:49:42.605172 USB2 port 2: enabled 0
757 15:49:42.608697 USB2 port 3: enabled 0
758 15:49:42.612105 USB2 port 5: enabled 0
759 15:49:42.612695 USB2 port 6: enabled 1
760 15:49:42.615243 USB2 port 9: enabled 1
761 15:49:42.618385 USB3 port 0: enabled 1
762 15:49:42.621441 USB3 port 1: enabled 1
763 15:49:42.625116 USB3 port 2: enabled 1
764 15:49:42.628082 USB3 port 3: enabled 1
765 15:49:42.628682 USB3 port 4: enabled 0
766 15:49:42.631706 PCI: 00:14.1: enabled 0
767 15:49:42.634512 PCI: 00:14.3: enabled 1
768 15:49:42.638184 PCI: 00:14.5: enabled 0
769 15:49:42.641249 PCI: 00:15.0: enabled 1
770 15:49:42.641789 I2C: 00:15: enabled 1
771 15:49:42.644014 PCI: 00:15.1: enabled 1
772 15:49:42.647710 I2C: 00:5d: enabled 1
773 15:49:42.650837 GENERIC: 0.0: enabled 1
774 15:49:42.654159 PCI: 00:15.2: enabled 0
775 15:49:42.654649 PCI: 00:15.3: enabled 0
776 15:49:42.657381 PCI: 00:16.0: enabled 1
777 15:49:42.661246 PCI: 00:16.1: enabled 0
778 15:49:42.663972 PCI: 00:16.2: enabled 0
779 15:49:42.667396 PCI: 00:16.3: enabled 0
780 15:49:42.667889 PCI: 00:16.4: enabled 0
781 15:49:42.670809 PCI: 00:16.5: enabled 0
782 15:49:42.673778 PCI: 00:17.0: enabled 1
783 15:49:42.677193 PCI: 00:19.0: enabled 1
784 15:49:42.680516 I2C: 00:1a: enabled 1
785 15:49:42.681110 I2C: 00:38: enabled 1
786 15:49:42.683710 I2C: 00:39: enabled 1
787 15:49:42.686748 I2C: 00:3a: enabled 1
788 15:49:42.690604 I2C: 00:3b: enabled 1
789 15:49:42.693442 PCI: 00:19.1: enabled 0
790 15:49:42.694030 PCI: 00:19.2: enabled 0
791 15:49:42.696759 PCI: 00:1a.0: enabled 0
792 15:49:42.699974 PCI: 00:1c.0: enabled 0
793 15:49:42.703005 PCI: 00:1c.1: enabled 0
794 15:49:42.706441 PCI: 00:1c.2: enabled 0
795 15:49:42.706931 PCI: 00:1c.3: enabled 0
796 15:49:42.709697 PCI: 00:1c.4: enabled 0
797 15:49:42.712832 PCI: 00:1c.5: enabled 0
798 15:49:42.716268 PCI: 00:1c.6: enabled 0
799 15:49:42.719754 PCI: 00:1c.7: enabled 0
800 15:49:42.720337 PCI: 00:1d.0: enabled 1
801 15:49:42.723231 PCI: 00:1d.1: enabled 0
802 15:49:42.726459 PCI: 00:1d.2: enabled 0
803 15:49:42.729605 PCI: 00:1d.3: enabled 0
804 15:49:42.732972 PCI: 00:1d.4: enabled 0
805 15:49:42.733586 PCI: 00:1d.5: enabled 1
806 15:49:42.736210 PCI: 00:00.0: enabled 1
807 15:49:42.739125 PCI: 00:1e.0: enabled 1
808 15:49:42.742367 PCI: 00:1e.1: enabled 0
809 15:49:42.745737 PCI: 00:1e.2: enabled 1
810 15:49:42.746223 SPI: 00: enabled 1
811 15:49:42.749125 PCI: 00:1e.3: enabled 1
812 15:49:42.752155 SPI: 01: enabled 1
813 15:49:42.755655 PCI: 00:1f.0: enabled 1
814 15:49:42.756153 PNP: 0c09.0: enabled 1
815 15:49:42.759308 PCI: 00:1f.1: enabled 1
816 15:49:42.762127 PCI: 00:1f.2: enabled 1
817 15:49:42.765444 PCI: 00:1f.3: enabled 1
818 15:49:42.768815 PCI: 00:1f.4: enabled 1
819 15:49:42.769424 PCI: 00:1f.5: enabled 1
820 15:49:42.771857 PCI: 00:1f.6: enabled 0
821 15:49:42.775015 Root Device scanning...
822 15:49:42.778377 scan_static_bus for Root Device
823 15:49:42.781595 CPU_CLUSTER: 0 enabled
824 15:49:42.782201 DOMAIN: 0000 enabled
825 15:49:42.785374 DOMAIN: 0000 scanning...
826 15:49:42.788569 PCI: pci_scan_bus for bus 00
827 15:49:42.791691 PCI: 00:00.0 [8086/0000] ops
828 15:49:42.794586 PCI: 00:00.0 [8086/9b61] enabled
829 15:49:42.798447 PCI: 00:02.0 [8086/0000] bus ops
830 15:49:42.801352 PCI: 00:02.0 [8086/9b41] enabled
831 15:49:42.804441 PCI: 00:04.0 [8086/1903] disabled
832 15:49:42.808291 PCI: 00:08.0 [8086/1911] enabled
833 15:49:42.811477 PCI: 00:12.0 [8086/02f9] enabled
834 15:49:42.814587 PCI: 00:14.0 [8086/0000] bus ops
835 15:49:42.817800 PCI: 00:14.0 [8086/02ed] enabled
836 15:49:42.821047 PCI: 00:14.2 [8086/02ef] enabled
837 15:49:42.824451 PCI: 00:14.3 [8086/02f0] enabled
838 15:49:42.827385 PCI: 00:15.0 [8086/0000] bus ops
839 15:49:42.831227 PCI: 00:15.0 [8086/02e8] enabled
840 15:49:42.834533 PCI: 00:15.1 [8086/0000] bus ops
841 15:49:42.837884 PCI: 00:15.1 [8086/02e9] enabled
842 15:49:42.840521 PCI: 00:16.0 [8086/0000] ops
843 15:49:42.843732 PCI: 00:16.0 [8086/02e0] enabled
844 15:49:42.847213 PCI: 00:17.0 [8086/0000] ops
845 15:49:42.850442 PCI: 00:17.0 [8086/02d3] enabled
846 15:49:42.853736 PCI: 00:19.0 [8086/0000] bus ops
847 15:49:42.856851 PCI: 00:19.0 [8086/02c5] enabled
848 15:49:42.860482 PCI: 00:1d.0 [8086/0000] bus ops
849 15:49:42.863173 PCI: 00:1d.0 [8086/02b0] enabled
850 15:49:42.870058 PCI: Static device PCI: 00:1d.5 not found, disabling it.
851 15:49:42.873370 PCI: 00:1e.0 [8086/0000] ops
852 15:49:42.876245 PCI: 00:1e.0 [8086/02a8] enabled
853 15:49:42.880360 PCI: 00:1e.2 [8086/0000] bus ops
854 15:49:42.883475 PCI: 00:1e.2 [8086/02aa] enabled
855 15:49:42.886538 PCI: 00:1e.3 [8086/0000] bus ops
856 15:49:42.890168 PCI: 00:1e.3 [8086/02ab] enabled
857 15:49:42.892816 PCI: 00:1f.0 [8086/0000] bus ops
858 15:49:42.896001 PCI: 00:1f.0 [8086/0284] enabled
859 15:49:42.902682 PCI: Static device PCI: 00:1f.1 not found, disabling it.
860 15:49:42.906141 PCI: Static device PCI: 00:1f.2 not found, disabling it.
861 15:49:42.909395 PCI: 00:1f.3 [8086/0000] bus ops
862 15:49:42.916276 PCI: 00:1f.3 [8086/02c8] enabled
863 15:49:42.919333 PCI: 00:1f.4 [8086/0000] bus ops
864 15:49:42.922479 PCI: 00:1f.4 [8086/02a3] enabled
865 15:49:42.925591 PCI: 00:1f.5 [8086/0000] bus ops
866 15:49:42.929082 PCI: 00:1f.5 [8086/02a4] enabled
867 15:49:42.932557 PCI: Leftover static devices:
868 15:49:42.933140 PCI: 00:05.0
869 15:49:42.933572 PCI: 00:12.5
870 15:49:42.935795 PCI: 00:12.6
871 15:49:42.936381 PCI: 00:14.1
872 15:49:42.939004 PCI: 00:14.5
873 15:49:42.939491 PCI: 00:15.2
874 15:49:42.939880 PCI: 00:15.3
875 15:49:42.942110 PCI: 00:16.1
876 15:49:42.942630 PCI: 00:16.2
877 15:49:42.944945 PCI: 00:16.3
878 15:49:42.945470 PCI: 00:16.4
879 15:49:42.948527 PCI: 00:16.5
880 15:49:42.949110 PCI: 00:19.1
881 15:49:42.949559 PCI: 00:19.2
882 15:49:42.952133 PCI: 00:1a.0
883 15:49:42.952717 PCI: 00:1c.0
884 15:49:42.955187 PCI: 00:1c.1
885 15:49:42.955712 PCI: 00:1c.2
886 15:49:42.956254 PCI: 00:1c.3
887 15:49:42.958499 PCI: 00:1c.4
888 15:49:42.958988 PCI: 00:1c.5
889 15:49:42.961662 PCI: 00:1c.6
890 15:49:42.962249 PCI: 00:1c.7
891 15:49:42.965097 PCI: 00:1d.1
892 15:49:42.965765 PCI: 00:1d.2
893 15:49:42.966178 PCI: 00:1d.3
894 15:49:42.968171 PCI: 00:1d.4
895 15:49:42.968663 PCI: 00:1d.5
896 15:49:42.971282 PCI: 00:1e.1
897 15:49:42.971783 PCI: 00:1f.1
898 15:49:42.972212 PCI: 00:1f.2
899 15:49:42.974767 PCI: 00:1f.6
900 15:49:42.978516 PCI: Check your devicetree.cb.
901 15:49:42.981255 PCI: 00:02.0 scanning...
902 15:49:42.984432 scan_generic_bus for PCI: 00:02.0
903 15:49:42.987756 scan_generic_bus for PCI: 00:02.0 done
904 15:49:42.994639 scan_bus: scanning of bus PCI: 00:02.0 took 10193 usecs
905 15:49:42.995238 PCI: 00:14.0 scanning...
906 15:49:43.001234 scan_static_bus for PCI: 00:14.0
907 15:49:43.001856 USB0 port 0 enabled
908 15:49:43.003763 USB0 port 0 scanning...
909 15:49:43.007167 scan_static_bus for USB0 port 0
910 15:49:43.010395 USB2 port 0 enabled
911 15:49:43.010889 USB2 port 1 enabled
912 15:49:43.013839 USB2 port 2 disabled
913 15:49:43.017627 USB2 port 3 disabled
914 15:49:43.018216 USB2 port 5 disabled
915 15:49:43.020436 USB2 port 6 enabled
916 15:49:43.021035 USB2 port 9 enabled
917 15:49:43.023469 USB3 port 0 enabled
918 15:49:43.027288 USB3 port 1 enabled
919 15:49:43.027874 USB3 port 2 enabled
920 15:49:43.030766 USB3 port 3 enabled
921 15:49:43.033812 USB3 port 4 disabled
922 15:49:43.034309 USB2 port 0 scanning...
923 15:49:43.036759 scan_static_bus for USB2 port 0
924 15:49:43.043256 scan_static_bus for USB2 port 0 done
925 15:49:43.046691 scan_bus: scanning of bus USB2 port 0 took 9689 usecs
926 15:49:43.049818 USB2 port 1 scanning...
927 15:49:43.053262 scan_static_bus for USB2 port 1
928 15:49:43.056512 scan_static_bus for USB2 port 1 done
929 15:49:43.063209 scan_bus: scanning of bus USB2 port 1 took 9707 usecs
930 15:49:43.063849 USB2 port 6 scanning...
931 15:49:43.066554 scan_static_bus for USB2 port 6
932 15:49:43.073179 scan_static_bus for USB2 port 6 done
933 15:49:43.076644 scan_bus: scanning of bus USB2 port 6 took 9702 usecs
934 15:49:43.079491 USB2 port 9 scanning...
935 15:49:43.083425 scan_static_bus for USB2 port 9
936 15:49:43.086272 scan_static_bus for USB2 port 9 done
937 15:49:43.092939 scan_bus: scanning of bus USB2 port 9 took 9699 usecs
938 15:49:43.095763 USB3 port 0 scanning...
939 15:49:43.099293 scan_static_bus for USB3 port 0
940 15:49:43.102616 scan_static_bus for USB3 port 0 done
941 15:49:43.105791 scan_bus: scanning of bus USB3 port 0 took 9708 usecs
942 15:49:43.108985 USB3 port 1 scanning...
943 15:49:43.112134 scan_static_bus for USB3 port 1
944 15:49:43.115939 scan_static_bus for USB3 port 1 done
945 15:49:43.122098 scan_bus: scanning of bus USB3 port 1 took 9688 usecs
946 15:49:43.125480 USB3 port 2 scanning...
947 15:49:43.128744 scan_static_bus for USB3 port 2
948 15:49:43.132447 scan_static_bus for USB3 port 2 done
949 15:49:43.138979 scan_bus: scanning of bus USB3 port 2 took 9696 usecs
950 15:49:43.139573 USB3 port 3 scanning...
951 15:49:43.141513 scan_static_bus for USB3 port 3
952 15:49:43.148519 scan_static_bus for USB3 port 3 done
953 15:49:43.152028 scan_bus: scanning of bus USB3 port 3 took 9705 usecs
954 15:49:43.155516 scan_static_bus for USB0 port 0 done
955 15:49:43.161732 scan_bus: scanning of bus USB0 port 0 took 155393 usecs
956 15:49:43.164712 scan_static_bus for PCI: 00:14.0 done
957 15:49:43.171725 scan_bus: scanning of bus PCI: 00:14.0 took 173000 usecs
958 15:49:43.174257 PCI: 00:15.0 scanning...
959 15:49:43.177555 scan_generic_bus for PCI: 00:15.0
960 15:49:43.180743 bus: PCI: 00:15.0[0]->I2C: 01:15 enabled
961 15:49:43.184433 scan_generic_bus for PCI: 00:15.0 done
962 15:49:43.191125 scan_bus: scanning of bus PCI: 00:15.0 took 14288 usecs
963 15:49:43.194328 PCI: 00:15.1 scanning...
964 15:49:43.197475 scan_generic_bus for PCI: 00:15.1
965 15:49:43.200633 bus: PCI: 00:15.1[0]->I2C: 02:5d enabled
966 15:49:43.203750 bus: PCI: 00:15.1[0]->GENERIC: 0.0 enabled
967 15:49:43.210322 scan_generic_bus for PCI: 00:15.1 done
968 15:49:43.214011 scan_bus: scanning of bus PCI: 00:15.1 took 18646 usecs
969 15:49:43.217356 PCI: 00:19.0 scanning...
970 15:49:43.220563 scan_generic_bus for PCI: 00:19.0
971 15:49:43.223532 bus: PCI: 00:19.0[0]->I2C: 03:1a enabled
972 15:49:43.230000 bus: PCI: 00:19.0[0]->I2C: 03:38 enabled
973 15:49:43.233926 bus: PCI: 00:19.0[0]->I2C: 03:39 enabled
974 15:49:43.236975 bus: PCI: 00:19.0[0]->I2C: 03:3a enabled
975 15:49:43.240378 bus: PCI: 00:19.0[0]->I2C: 03:3b enabled
976 15:49:43.246294 scan_generic_bus for PCI: 00:19.0 done
977 15:49:43.249827 scan_bus: scanning of bus PCI: 00:19.0 took 30721 usecs
978 15:49:43.252883 PCI: 00:1d.0 scanning...
979 15:49:43.256506 do_pci_scan_bridge for PCI: 00:1d.0
980 15:49:43.259817 PCI: pci_scan_bus for bus 01
981 15:49:43.263114 PCI: 01:00.0 [1c5c/1327] enabled
982 15:49:43.266510 Enabling Common Clock Configuration
983 15:49:43.273043 L1 Sub-State supported from root port 29
984 15:49:43.273739 L1 Sub-State Support = 0xf
985 15:49:43.276379 CommonModeRestoreTime = 0x28
986 15:49:43.282491 Power On Value = 0x16, Power On Scale = 0x0
987 15:49:43.283069 ASPM: Enabled L1
988 15:49:43.289170 scan_bus: scanning of bus PCI: 00:1d.0 took 32774 usecs
989 15:49:43.292375 PCI: 00:1e.2 scanning...
990 15:49:43.295640 scan_generic_bus for PCI: 00:1e.2
991 15:49:43.299433 bus: PCI: 00:1e.2[0]->SPI: 00 enabled
992 15:49:43.302195 scan_generic_bus for PCI: 00:1e.2 done
993 15:49:43.308880 scan_bus: scanning of bus PCI: 00:1e.2 took 14002 usecs
994 15:49:43.312033 PCI: 00:1e.3 scanning...
995 15:49:43.315514 scan_generic_bus for PCI: 00:1e.3
996 15:49:43.318569 bus: PCI: 00:1e.3[0]->SPI: 01 enabled
997 15:49:43.321755 scan_generic_bus for PCI: 00:1e.3 done
998 15:49:43.328396 scan_bus: scanning of bus PCI: 00:1e.3 took 13994 usecs
999 15:49:43.331299 PCI: 00:1f.0 scanning...
1000 15:49:43.335269 scan_static_bus for PCI: 00:1f.0
1001 15:49:43.335884 PNP: 0c09.0 enabled
1002 15:49:43.337967 scan_static_bus for PCI: 00:1f.0 done
1003 15:49:43.345127 scan_bus: scanning of bus PCI: 00:1f.0 took 12037 usecs
1004 15:49:43.348747 PCI: 00:1f.3 scanning...
1005 15:49:43.354930 scan_bus: scanning of bus PCI: 00:1f.3 took 2860 usecs
1006 15:49:43.355523 PCI: 00:1f.4 scanning...
1007 15:49:43.361647 scan_generic_bus for PCI: 00:1f.4
1008 15:49:43.364506 scan_generic_bus for PCI: 00:1f.4 done
1009 15:49:43.367908 scan_bus: scanning of bus PCI: 00:1f.4 took 10195 usecs
1010 15:49:43.371260 PCI: 00:1f.5 scanning...
1011 15:49:43.374078 scan_generic_bus for PCI: 00:1f.5
1012 15:49:43.380457 scan_generic_bus for PCI: 00:1f.5 done
1013 15:49:43.384264 scan_bus: scanning of bus PCI: 00:1f.5 took 10193 usecs
1014 15:49:43.390651 scan_bus: scanning of bus DOMAIN: 0000 took 605025 usecs
1015 15:49:43.394214 scan_static_bus for Root Device done
1016 15:49:43.400690 scan_bus: scanning of bus Root Device took 624904 usecs
1017 15:49:43.401291 done
1018 15:49:43.403637 Chrome EC: UHEPI supported
1019 15:49:43.410259 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
1020 15:49:43.416695 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
1021 15:49:43.423129 SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
1022 15:49:43.430016 FMAP: area UNIFIED_MRC_CACHE found @ ad0000 (131072 bytes)
1023 15:49:43.433120 SPI flash protection: WPSW=0 SRP0=1
1024 15:49:43.436377 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1025 15:49:43.442848 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 9 exit 2
1026 15:49:43.445822 found VGA at PCI: 00:02.0
1027 15:49:43.449505 Setting up VGA for PCI: 00:02.0
1028 15:49:43.452607 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1029 15:49:43.459037 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1030 15:49:43.462522 Allocating resources...
1031 15:49:43.463117 Reading resources...
1032 15:49:43.469402 Root Device read_resources bus 0 link: 0
1033 15:49:43.472627 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1034 15:49:43.478991 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1035 15:49:43.481857 DOMAIN: 0000 read_resources bus 0 link: 0
1036 15:49:43.488673 PCI: 00:14.0 read_resources bus 0 link: 0
1037 15:49:43.491878 USB0 port 0 read_resources bus 0 link: 0
1038 15:49:43.500110 USB0 port 0 read_resources bus 0 link: 0 done
1039 15:49:43.502873 PCI: 00:14.0 read_resources bus 0 link: 0 done
1040 15:49:43.510570 PCI: 00:15.0 read_resources bus 1 link: 0
1041 15:49:43.513692 PCI: 00:15.0 read_resources bus 1 link: 0 done
1042 15:49:43.520432 PCI: 00:15.1 read_resources bus 2 link: 0
1043 15:49:43.523516 PCI: 00:15.1 read_resources bus 2 link: 0 done
1044 15:49:43.531155 PCI: 00:19.0 read_resources bus 3 link: 0
1045 15:49:43.537513 PCI: 00:19.0 read_resources bus 3 link: 0 done
1046 15:49:43.541250 PCI: 00:1d.0 read_resources bus 1 link: 0
1047 15:49:43.547348 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1048 15:49:43.550750 PCI: 00:1e.2 read_resources bus 4 link: 0
1049 15:49:43.557476 PCI: 00:1e.2 read_resources bus 4 link: 0 done
1050 15:49:43.560852 PCI: 00:1e.3 read_resources bus 5 link: 0
1051 15:49:43.567137 PCI: 00:1e.3 read_resources bus 5 link: 0 done
1052 15:49:43.570702 PCI: 00:1f.0 read_resources bus 0 link: 0
1053 15:49:43.576949 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1054 15:49:43.583437 DOMAIN: 0000 read_resources bus 0 link: 0 done
1055 15:49:43.586927 Root Device read_resources bus 0 link: 0 done
1056 15:49:43.590359 Done reading resources.
1057 15:49:43.597121 Show resources in subtree (Root Device)...After reading.
1058 15:49:43.600343 Root Device child on link 0 CPU_CLUSTER: 0
1059 15:49:43.602866 CPU_CLUSTER: 0 child on link 0 APIC: 00
1060 15:49:43.606453 APIC: 00
1061 15:49:43.607031 APIC: 03
1062 15:49:43.609770 APIC: 01
1063 15:49:43.610270 APIC: 02
1064 15:49:43.610663 APIC: 05
1065 15:49:43.612824 APIC: 06
1066 15:49:43.613410 APIC: 07
1067 15:49:43.613822 APIC: 04
1068 15:49:43.619680 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1069 15:49:43.629141 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1070 15:49:43.639185 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
1071 15:49:43.639771 PCI: 00:00.0
1072 15:49:43.688844 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1073 15:49:43.690043 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1074 15:49:43.690534 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1075 15:49:43.690928 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1076 15:49:43.691680 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1077 15:49:43.738429 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1078 15:49:43.739448 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1079 15:49:43.739875 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1080 15:49:43.740253 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1081 15:49:43.740614 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1082 15:49:43.788255 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1083 15:49:43.788925 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1084 15:49:43.789819 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1085 15:49:43.790279 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1086 15:49:43.790651 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1087 15:49:43.791000 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1088 15:49:43.799922 PCI: 00:02.0
1089 15:49:43.802863 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1090 15:49:43.812866 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1091 15:49:43.819342 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1092 15:49:43.822180 PCI: 00:04.0
1093 15:49:43.822671 PCI: 00:08.0
1094 15:49:43.832151 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1095 15:49:43.836014 PCI: 00:12.0
1096 15:49:43.845151 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1097 15:49:43.848218 PCI: 00:14.0 child on link 0 USB0 port 0
1098 15:49:43.858602 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1099 15:49:43.865242 USB0 port 0 child on link 0 USB2 port 0
1100 15:49:43.865910 USB2 port 0
1101 15:49:43.868405 USB2 port 1
1102 15:49:43.868988 USB2 port 2
1103 15:49:43.871477 USB2 port 3
1104 15:49:43.872064 USB2 port 5
1105 15:49:43.874570 USB2 port 6
1106 15:49:43.875167 USB2 port 9
1107 15:49:43.877636 USB3 port 0
1108 15:49:43.878122 USB3 port 1
1109 15:49:43.881466 USB3 port 2
1110 15:49:43.881951 USB3 port 3
1111 15:49:43.884743 USB3 port 4
1112 15:49:43.887954 PCI: 00:14.2
1113 15:49:43.897901 PCI: 00:14.2 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
1114 15:49:43.907727 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1115 15:49:43.908327 PCI: 00:14.3
1116 15:49:43.917373 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1117 15:49:43.920271 PCI: 00:15.0 child on link 0 I2C: 01:15
1118 15:49:43.930702 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1119 15:49:43.933947 I2C: 01:15
1120 15:49:43.936896 PCI: 00:15.1 child on link 0 I2C: 02:5d
1121 15:49:43.946499 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1122 15:49:43.950572 I2C: 02:5d
1123 15:49:43.951166 GENERIC: 0.0
1124 15:49:43.953328 PCI: 00:16.0
1125 15:49:43.963532 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1126 15:49:43.964136 PCI: 00:17.0
1127 15:49:43.973123 PCI: 00:17.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10
1128 15:49:43.983053 PCI: 00:17.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 14
1129 15:49:43.989450 PCI: 00:17.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
1130 15:49:43.999216 PCI: 00:17.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
1131 15:49:44.005711 PCI: 00:17.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
1132 15:49:44.015308 PCI: 00:17.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
1133 15:49:44.022211 PCI: 00:19.0 child on link 0 I2C: 03:1a
1134 15:49:44.031871 PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1135 15:49:44.032465 I2C: 03:1a
1136 15:49:44.034877 I2C: 03:38
1137 15:49:44.035374 I2C: 03:39
1138 15:49:44.035768 I2C: 03:3a
1139 15:49:44.037949 I2C: 03:3b
1140 15:49:44.041901 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1141 15:49:44.051336 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1142 15:49:44.061025 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1143 15:49:44.070784 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1144 15:49:44.071373 PCI: 01:00.0
1145 15:49:44.080895 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1146 15:49:44.084012 PCI: 00:1e.0
1147 15:49:44.093844 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1148 15:49:44.103874 PCI: 00:1e.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1149 15:49:44.110004 PCI: 00:1e.2 child on link 0 SPI: 00
1150 15:49:44.119550 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1151 15:49:44.120132 SPI: 00
1152 15:49:44.123135 PCI: 00:1e.3 child on link 0 SPI: 01
1153 15:49:44.132469 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1154 15:49:44.136033 SPI: 01
1155 15:49:44.139417 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1156 15:49:44.149153 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1157 15:49:44.155897 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1158 15:49:44.159027 PNP: 0c09.0
1159 15:49:44.168862 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1160 15:49:44.169484 PCI: 00:1f.3
1161 15:49:44.178256 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1162 15:49:44.188561 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1163 15:49:44.191312 PCI: 00:1f.4
1164 15:49:44.198157 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1165 15:49:44.208271 PCI: 00:1f.4 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
1166 15:49:44.210806 PCI: 00:1f.5
1167 15:49:44.221100 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1168 15:49:44.227237 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1169 15:49:44.234099 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
1170 15:49:44.240886 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
1171 15:49:44.244000 PCI: 00:02.0 20 * [0x0 - 0x3f] io
1172 15:49:44.246977 PCI: 00:17.0 20 * [0x40 - 0x5f] io
1173 15:49:44.250275 PCI: 00:17.0 18 * [0x60 - 0x67] io
1174 15:49:44.253500 PCI: 00:17.0 1c * [0x68 - 0x6b] io
1175 15:49:44.260302 DOMAIN: 0000 io: base: 6c size: 6c align: 6 gran: 0 limit: ffff done
1176 15:49:44.266628 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
1177 15:49:44.276746 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1178 15:49:44.283085 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1179 15:49:44.289913 PCI: 00:1d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
1180 15:49:44.293220 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1181 15:49:44.302595 PCI: 00:1d.0 mem: base: 4000 size: 100000 align: 20 gran: 20 limit: ffffffff done
1182 15:49:44.305761 PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
1183 15:49:44.312724 PCI: 00:02.0 10 * [0x10000000 - 0x10ffffff] mem
1184 15:49:44.316422 PCI: 00:1d.0 20 * [0x11000000 - 0x110fffff] mem
1185 15:49:44.322963 PCI: 00:1f.3 20 * [0x11100000 - 0x111fffff] mem
1186 15:49:44.325590 PCI: 00:14.0 10 * [0x11200000 - 0x1120ffff] mem
1187 15:49:44.332048 PCI: 00:14.3 10 * [0x11210000 - 0x11213fff] mem
1188 15:49:44.335930 PCI: 00:1f.3 10 * [0x11214000 - 0x11217fff] mem
1189 15:49:44.342173 PCI: 00:14.2 10 * [0x11218000 - 0x11219fff] mem
1190 15:49:44.345360 PCI: 00:17.0 10 * [0x1121a000 - 0x1121bfff] mem
1191 15:49:44.351848 PCI: 00:08.0 10 * [0x1121c000 - 0x1121cfff] mem
1192 15:49:44.354941 PCI: 00:12.0 10 * [0x1121d000 - 0x1121dfff] mem
1193 15:49:44.361859 PCI: 00:14.2 18 * [0x1121e000 - 0x1121efff] mem
1194 15:49:44.365018 PCI: 00:15.0 10 * [0x1121f000 - 0x1121ffff] mem
1195 15:49:44.371488 PCI: 00:15.1 10 * [0x11220000 - 0x11220fff] mem
1196 15:49:44.374928 PCI: 00:16.0 10 * [0x11221000 - 0x11221fff] mem
1197 15:49:44.381354 PCI: 00:19.0 10 * [0x11222000 - 0x11222fff] mem
1198 15:49:44.384365 PCI: 00:1e.0 18 * [0x11223000 - 0x11223fff] mem
1199 15:49:44.391602 PCI: 00:1e.2 10 * [0x11224000 - 0x11224fff] mem
1200 15:49:44.393918 PCI: 00:1e.3 10 * [0x11225000 - 0x11225fff] mem
1201 15:49:44.400876 PCI: 00:1f.5 10 * [0x11226000 - 0x11226fff] mem
1202 15:49:44.403722 PCI: 00:17.0 24 * [0x11227000 - 0x112277ff] mem
1203 15:49:44.407632 PCI: 00:17.0 14 * [0x11228000 - 0x112280ff] mem
1204 15:49:44.413445 PCI: 00:1f.4 10 * [0x11229000 - 0x112290ff] mem
1205 15:49:44.423184 DOMAIN: 0000 mem: base: 11229100 size: 11229100 align: 28 gran: 0 limit: ffffffff done
1206 15:49:44.426867 avoid_fixed_resources: DOMAIN: 0000
1207 15:49:44.433032 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
1208 15:49:44.436573 avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
1209 15:49:44.446276 constrain_resources: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)
1210 15:49:44.453029 constrain_resources: PCI: 00:00.0 09 base 00000000 limit 0009ffff mem (fixed)
1211 15:49:44.459436 constrain_resources: PCI: 00:00.0 0a base 000c0000 limit 99ffffff mem (fixed)
1212 15:49:44.469489 constrain_resources: PCI: 00:00.0 0b base 9a000000 limit 9affffff mem (fixed)
1213 15:49:44.476086 constrain_resources: PCI: 00:00.0 0c base 9b000000 limit 9f7fffff mem (fixed)
1214 15:49:44.482569 constrain_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1215 15:49:44.492302 constrain_resources: PCI: 00:1f.0 20 base 00001800 limit 000018ff io (fixed)
1216 15:49:44.498784 constrain_resources: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
1217 15:49:44.505784 avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001900 limit 0000ef9f
1218 15:49:44.511698 avoid_fixed_resources:@DOMAIN: 0000 10000100 base c0000000 limit dfffffff
1219 15:49:44.515398 Setting resources...
1220 15:49:44.522057 DOMAIN: 0000 io: base:1900 size:6c align:6 gran:0 limit:ef9f
1221 15:49:44.524980 PCI: 00:02.0 20 * [0x1c00 - 0x1c3f] io
1222 15:49:44.528314 PCI: 00:17.0 20 * [0x1c40 - 0x1c5f] io
1223 15:49:44.534630 PCI: 00:17.0 18 * [0x1c60 - 0x1c67] io
1224 15:49:44.537763 PCI: 00:17.0 1c * [0x1c68 - 0x1c6b] io
1225 15:49:44.544812 DOMAIN: 0000 io: next_base: 1c6c size: 6c align: 6 gran: 0 done
1226 15:49:44.551003 PCI: 00:1d.0 io: base:ef9f size:0 align:12 gran:12 limit:ef9f
1227 15:49:44.557956 PCI: 00:1d.0 io: next_base: ef9f size: 0 align: 12 gran: 12 done
1228 15:49:44.564320 DOMAIN: 0000 mem: base:c0000000 size:11229100 align:28 gran:0 limit:dfffffff
1229 15:49:44.570840 PCI: 00:02.0 18 * [0xc0000000 - 0xcfffffff] prefmem
1230 15:49:44.574330 PCI: 00:02.0 10 * [0xd0000000 - 0xd0ffffff] mem
1231 15:49:44.580228 PCI: 00:1d.0 20 * [0xd1000000 - 0xd10fffff] mem
1232 15:49:44.583536 PCI: 00:1f.3 20 * [0xd1100000 - 0xd11fffff] mem
1233 15:49:44.590662 PCI: 00:14.0 10 * [0xd1200000 - 0xd120ffff] mem
1234 15:49:44.593888 PCI: 00:14.3 10 * [0xd1210000 - 0xd1213fff] mem
1235 15:49:44.600405 PCI: 00:1f.3 10 * [0xd1214000 - 0xd1217fff] mem
1236 15:49:44.603728 PCI: 00:14.2 10 * [0xd1218000 - 0xd1219fff] mem
1237 15:49:44.609924 PCI: 00:17.0 10 * [0xd121a000 - 0xd121bfff] mem
1238 15:49:44.613482 PCI: 00:08.0 10 * [0xd121c000 - 0xd121cfff] mem
1239 15:49:44.616988 PCI: 00:12.0 10 * [0xd121d000 - 0xd121dfff] mem
1240 15:49:44.622937 PCI: 00:14.2 18 * [0xd121e000 - 0xd121efff] mem
1241 15:49:44.626183 PCI: 00:15.0 10 * [0xd121f000 - 0xd121ffff] mem
1242 15:49:44.633403 PCI: 00:15.1 10 * [0xd1220000 - 0xd1220fff] mem
1243 15:49:44.636409 PCI: 00:16.0 10 * [0xd1221000 - 0xd1221fff] mem
1244 15:49:44.642830 PCI: 00:19.0 10 * [0xd1222000 - 0xd1222fff] mem
1245 15:49:44.646237 PCI: 00:1e.0 18 * [0xd1223000 - 0xd1223fff] mem
1246 15:49:44.652313 PCI: 00:1e.2 10 * [0xd1224000 - 0xd1224fff] mem
1247 15:49:44.655802 PCI: 00:1e.3 10 * [0xd1225000 - 0xd1225fff] mem
1248 15:49:44.662500 PCI: 00:1f.5 10 * [0xd1226000 - 0xd1226fff] mem
1249 15:49:44.665439 PCI: 00:17.0 24 * [0xd1227000 - 0xd12277ff] mem
1250 15:49:44.672192 PCI: 00:17.0 14 * [0xd1228000 - 0xd12280ff] mem
1251 15:49:44.675596 PCI: 00:1f.4 10 * [0xd1229000 - 0xd12290ff] mem
1252 15:49:44.685158 DOMAIN: 0000 mem: next_base: d1229100 size: 11229100 align: 28 gran: 0 done
1253 15:49:44.691919 PCI: 00:1d.0 prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
1254 15:49:44.698285 PCI: 00:1d.0 prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
1255 15:49:44.704583 PCI: 00:1d.0 mem: base:d1000000 size:100000 align:20 gran:20 limit:d10fffff
1256 15:49:44.711435 PCI: 01:00.0 10 * [0xd1000000 - 0xd1003fff] mem
1257 15:49:44.718294 PCI: 00:1d.0 mem: next_base: d1004000 size: 100000 align: 20 gran: 20 done
1258 15:49:44.721001 Root Device assign_resources, bus 0 link: 0
1259 15:49:44.728453 DOMAIN: 0000 assign_resources, bus 0 link: 0
1260 15:49:44.734359 PCI: 00:02.0 10 <- [0x00d0000000 - 0x00d0ffffff] size 0x01000000 gran 0x18 mem64
1261 15:49:44.744434 PCI: 00:02.0 18 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64
1262 15:49:44.750864 PCI: 00:02.0 20 <- [0x0000001c00 - 0x0000001c3f] size 0x00000040 gran 0x06 io
1263 15:49:44.760378 PCI: 00:08.0 10 <- [0x00d121c000 - 0x00d121cfff] size 0x00001000 gran 0x0c mem64
1264 15:49:44.767080 PCI: 00:12.0 10 <- [0x00d121d000 - 0x00d121dfff] size 0x00001000 gran 0x0c mem64
1265 15:49:44.777049 PCI: 00:14.0 10 <- [0x00d1200000 - 0x00d120ffff] size 0x00010000 gran 0x10 mem64
1266 15:49:44.780694 PCI: 00:14.0 assign_resources, bus 0 link: 0
1267 15:49:44.786889 PCI: 00:14.0 assign_resources, bus 0 link: 0
1268 15:49:44.793536 PCI: 00:14.2 10 <- [0x00d1218000 - 0x00d1219fff] size 0x00002000 gran 0x0d mem64
1269 15:49:44.803057 PCI: 00:14.2 18 <- [0x00d121e000 - 0x00d121efff] size 0x00001000 gran 0x0c mem64
1270 15:49:44.810561 PCI: 00:14.3 10 <- [0x00d1210000 - 0x00d1213fff] size 0x00004000 gran 0x0e mem64
1271 15:49:44.819573 PCI: 00:15.0 10 <- [0x00d121f000 - 0x00d121ffff] size 0x00001000 gran 0x0c mem64
1272 15:49:44.823309 PCI: 00:15.0 assign_resources, bus 1 link: 0
1273 15:49:44.829719 PCI: 00:15.0 assign_resources, bus 1 link: 0
1274 15:49:44.836305 PCI: 00:15.1 10 <- [0x00d1220000 - 0x00d1220fff] size 0x00001000 gran 0x0c mem64
1275 15:49:44.842211 PCI: 00:15.1 assign_resources, bus 2 link: 0
1276 15:49:44.846004 PCI: 00:15.1 assign_resources, bus 2 link: 0
1277 15:49:44.855561 PCI: 00:16.0 10 <- [0x00d1221000 - 0x00d1221fff] size 0x00001000 gran 0x0c mem64
1278 15:49:44.862389 PCI: 00:17.0 10 <- [0x00d121a000 - 0x00d121bfff] size 0x00002000 gran 0x0d mem
1279 15:49:44.868643 PCI: 00:17.0 14 <- [0x00d1228000 - 0x00d12280ff] size 0x00000100 gran 0x08 mem
1280 15:49:44.878444 PCI: 00:17.0 18 <- [0x0000001c60 - 0x0000001c67] size 0x00000008 gran 0x03 io
1281 15:49:44.885119 PCI: 00:17.0 1c <- [0x0000001c68 - 0x0000001c6b] size 0x00000004 gran 0x02 io
1282 15:49:44.891911 PCI: 00:17.0 20 <- [0x0000001c40 - 0x0000001c5f] size 0x00000020 gran 0x05 io
1283 15:49:44.901784 PCI: 00:17.0 24 <- [0x00d1227000 - 0x00d12277ff] size 0x00000800 gran 0x0b mem
1284 15:49:44.908363 PCI: 00:19.0 10 <- [0x00d1222000 - 0x00d1222fff] size 0x00001000 gran 0x0c mem64
1285 15:49:44.914562 PCI: 00:19.0 assign_resources, bus 3 link: 0
1286 15:49:44.917976 PCI: 00:19.0 assign_resources, bus 3 link: 0
1287 15:49:44.927548 PCI: 00:1d.0 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus 01 io
1288 15:49:44.934272 PCI: 00:1d.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1289 15:49:44.943782 PCI: 00:1d.0 20 <- [0x00d1000000 - 0x00d10fffff] size 0x00100000 gran 0x14 bus 01 mem
1290 15:49:44.947224 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1291 15:49:44.956988 PCI: 01:00.0 10 <- [0x00d1000000 - 0x00d1003fff] size 0x00004000 gran 0x0e mem64
1292 15:49:44.960194 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1293 15:49:44.970162 PCI: 00:1e.0 18 <- [0x00d1223000 - 0x00d1223fff] size 0x00001000 gran 0x0c mem64
1294 15:49:44.976669 PCI: 00:1e.2 10 <- [0x00d1224000 - 0x00d1224fff] size 0x00001000 gran 0x0c mem64
1295 15:49:44.982904 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1296 15:49:44.986844 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1297 15:49:44.996188 PCI: 00:1e.3 10 <- [0x00d1225000 - 0x00d1225fff] size 0x00001000 gran 0x0c mem64
1298 15:49:44.999599 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1299 15:49:45.006362 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1300 15:49:45.009795 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1301 15:49:45.015787 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1302 15:49:45.018917 LPC: Trying to open IO window from 800 size 1ff
1303 15:49:45.029007 PCI: 00:1f.3 10 <- [0x00d1214000 - 0x00d1217fff] size 0x00004000 gran 0x0e mem64
1304 15:49:45.035242 PCI: 00:1f.3 20 <- [0x00d1100000 - 0x00d11fffff] size 0x00100000 gran 0x14 mem64
1305 15:49:45.045182 PCI: 00:1f.4 10 <- [0x00d1229000 - 0x00d12290ff] size 0x00000100 gran 0x08 mem64
1306 15:49:45.051533 PCI: 00:1f.5 10 <- [0x00d1226000 - 0x00d1226fff] size 0x00001000 gran 0x0c mem
1307 15:49:45.058563 DOMAIN: 0000 assign_resources, bus 0 link: 0
1308 15:49:45.061715 Root Device assign_resources, bus 0 link: 0
1309 15:49:45.064892 Done setting resources.
1310 15:49:45.071981 Show resources in subtree (Root Device)...After assigning values.
1311 15:49:45.075607 Root Device child on link 0 CPU_CLUSTER: 0
1312 15:49:45.078649 CPU_CLUSTER: 0 child on link 0 APIC: 00
1313 15:49:45.081750 APIC: 00
1314 15:49:45.082341 APIC: 03
1315 15:49:45.084449 APIC: 01
1316 15:49:45.084926 APIC: 02
1317 15:49:45.085341 APIC: 05
1318 15:49:45.088239 APIC: 06
1319 15:49:45.088810 APIC: 07
1320 15:49:45.089192 APIC: 04
1321 15:49:45.094906 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1322 15:49:45.104263 DOMAIN: 0000 resource base 1900 size 6c align 6 gran 0 limit ef9f flags 40040100 index 10000000
1323 15:49:45.114197 DOMAIN: 0000 resource base c0000000 size 11229100 align 28 gran 0 limit dfffffff flags 40040200 index 10000100
1324 15:49:45.117524 PCI: 00:00.0
1325 15:49:45.126964 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1326 15:49:45.137062 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1327 15:49:45.143463 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1328 15:49:45.153119 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1329 15:49:45.163113 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1330 15:49:45.173055 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1331 15:49:45.182605 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1332 15:49:45.192352 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1333 15:49:45.202430 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1334 15:49:45.208790 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1335 15:49:45.218706 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1336 15:49:45.228153 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1337 15:49:45.238241 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1338 15:49:45.248504 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1339 15:49:45.257996 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1340 15:49:45.267420 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1341 15:49:45.267916 PCI: 00:02.0
1342 15:49:45.277712 PCI: 00:02.0 resource base d0000000 size 1000000 align 24 gran 24 limit d0ffffff flags 60000201 index 10
1343 15:49:45.290805 PCI: 00:02.0 resource base c0000000 size 10000000 align 28 gran 28 limit cfffffff flags 60001201 index 18
1344 15:49:45.297309 PCI: 00:02.0 resource base 1c00 size 40 align 6 gran 6 limit 1c3f flags 60000100 index 20
1345 15:49:45.300581 PCI: 00:04.0
1346 15:49:45.301165 PCI: 00:08.0
1347 15:49:45.313830 PCI: 00:08.0 resource base d121c000 size 1000 align 12 gran 12 limit d121cfff flags 60000201 index 10
1348 15:49:45.314433 PCI: 00:12.0
1349 15:49:45.323661 PCI: 00:12.0 resource base d121d000 size 1000 align 12 gran 12 limit d121dfff flags 60000201 index 10
1350 15:49:45.329627 PCI: 00:14.0 child on link 0 USB0 port 0
1351 15:49:45.339775 PCI: 00:14.0 resource base d1200000 size 10000 align 16 gran 16 limit d120ffff flags 60000201 index 10
1352 15:49:45.342787 USB0 port 0 child on link 0 USB2 port 0
1353 15:49:45.346132 USB2 port 0
1354 15:49:45.346715 USB2 port 1
1355 15:49:45.349441 USB2 port 2
1356 15:49:45.349929 USB2 port 3
1357 15:49:45.352596 USB2 port 5
1358 15:49:45.353121 USB2 port 6
1359 15:49:45.355803 USB2 port 9
1360 15:49:45.356292 USB3 port 0
1361 15:49:45.359093 USB3 port 1
1362 15:49:45.359583 USB3 port 2
1363 15:49:45.362542 USB3 port 3
1364 15:49:45.366158 USB3 port 4
1365 15:49:45.366749 PCI: 00:14.2
1366 15:49:45.375213 PCI: 00:14.2 resource base d1218000 size 2000 align 13 gran 13 limit d1219fff flags 60000201 index 10
1367 15:49:45.385444 PCI: 00:14.2 resource base d121e000 size 1000 align 12 gran 12 limit d121efff flags 60000201 index 18
1368 15:49:45.388882 PCI: 00:14.3
1369 15:49:45.398645 PCI: 00:14.3 resource base d1210000 size 4000 align 14 gran 14 limit d1213fff flags 60000201 index 10
1370 15:49:45.402040 PCI: 00:15.0 child on link 0 I2C: 01:15
1371 15:49:45.411622 PCI: 00:15.0 resource base d121f000 size 1000 align 12 gran 12 limit d121ffff flags 60000201 index 10
1372 15:49:45.415103 I2C: 01:15
1373 15:49:45.417854 PCI: 00:15.1 child on link 0 I2C: 02:5d
1374 15:49:45.427761 PCI: 00:15.1 resource base d1220000 size 1000 align 12 gran 12 limit d1220fff flags 60000201 index 10
1375 15:49:45.430887 I2C: 02:5d
1376 15:49:45.431382 GENERIC: 0.0
1377 15:49:45.434570 PCI: 00:16.0
1378 15:49:45.444583 PCI: 00:16.0 resource base d1221000 size 1000 align 12 gran 12 limit d1221fff flags 60000201 index 10
1379 15:49:45.445170 PCI: 00:17.0
1380 15:49:45.456990 PCI: 00:17.0 resource base d121a000 size 2000 align 13 gran 13 limit d121bfff flags 60000200 index 10
1381 15:49:45.467297 PCI: 00:17.0 resource base d1228000 size 100 align 12 gran 8 limit d12280ff flags 60000200 index 14
1382 15:49:45.477213 PCI: 00:17.0 resource base 1c60 size 8 align 3 gran 3 limit 1c67 flags 60000100 index 18
1383 15:49:45.483483 PCI: 00:17.0 resource base 1c68 size 4 align 2 gran 2 limit 1c6b flags 60000100 index 1c
1384 15:49:45.492974 PCI: 00:17.0 resource base 1c40 size 20 align 5 gran 5 limit 1c5f flags 60000100 index 20
1385 15:49:45.503269 PCI: 00:17.0 resource base d1227000 size 800 align 12 gran 11 limit d12277ff flags 60000200 index 24
1386 15:49:45.506508 PCI: 00:19.0 child on link 0 I2C: 03:1a
1387 15:49:45.519656 PCI: 00:19.0 resource base d1222000 size 1000 align 12 gran 12 limit d1222fff flags 60000201 index 10
1388 15:49:45.520260 I2C: 03:1a
1389 15:49:45.522391 I2C: 03:38
1390 15:49:45.522888 I2C: 03:39
1391 15:49:45.525821 I2C: 03:3a
1392 15:49:45.526425 I2C: 03:3b
1393 15:49:45.528979 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1394 15:49:45.539396 PCI: 00:1d.0 resource base ef9f size 0 align 12 gran 12 limit ef9f flags 60080102 index 1c
1395 15:49:45.548952 PCI: 00:1d.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
1396 15:49:45.558762 PCI: 00:1d.0 resource base d1000000 size 100000 align 20 gran 20 limit d10fffff flags 60080202 index 20
1397 15:49:45.562458 PCI: 01:00.0
1398 15:49:45.572203 PCI: 01:00.0 resource base d1000000 size 4000 align 14 gran 14 limit d1003fff flags 60000201 index 10
1399 15:49:45.575138 PCI: 00:1e.0
1400 15:49:45.584753 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1401 15:49:45.594695 PCI: 00:1e.0 resource base d1223000 size 1000 align 12 gran 12 limit d1223fff flags 60000201 index 18
1402 15:49:45.597650 PCI: 00:1e.2 child on link 0 SPI: 00
1403 15:49:45.611287 PCI: 00:1e.2 resource base d1224000 size 1000 align 12 gran 12 limit d1224fff flags 60000201 index 10
1404 15:49:45.611909 SPI: 00
1405 15:49:45.614499 PCI: 00:1e.3 child on link 0 SPI: 01
1406 15:49:45.624649 PCI: 00:1e.3 resource base d1225000 size 1000 align 12 gran 12 limit d1225fff flags 60000201 index 10
1407 15:49:45.627879 SPI: 01
1408 15:49:45.631160 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1409 15:49:45.640689 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1410 15:49:45.647179 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1411 15:49:45.650647 PNP: 0c09.0
1412 15:49:45.660533 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1413 15:49:45.661154 PCI: 00:1f.3
1414 15:49:45.669807 PCI: 00:1f.3 resource base d1214000 size 4000 align 14 gran 14 limit d1217fff flags 60000201 index 10
1415 15:49:45.679741 PCI: 00:1f.3 resource base d1100000 size 100000 align 20 gran 20 limit d11fffff flags 60000201 index 20
1416 15:49:45.683022 PCI: 00:1f.4
1417 15:49:45.692784 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1418 15:49:45.702632 PCI: 00:1f.4 resource base d1229000 size 100 align 12 gran 8 limit d12290ff flags 60000201 index 10
1419 15:49:45.703224 PCI: 00:1f.5
1420 15:49:45.712822 PCI: 00:1f.5 resource base d1226000 size 1000 align 12 gran 12 limit d1226fff flags 60000200 index 10
1421 15:49:45.715990 Done allocating resources.
1422 15:49:45.722695 BS: BS_DEV_RESOURCES times (ms): entry 0 run 30 exit 0
1423 15:49:45.726001 Enabling resources...
1424 15:49:45.729225 PCI: 00:00.0 subsystem <- 8086/9b61
1425 15:49:45.732375 PCI: 00:00.0 cmd <- 06
1426 15:49:45.735976 PCI: 00:02.0 subsystem <- 8086/9b41
1427 15:49:45.738954 PCI: 00:02.0 cmd <- 03
1428 15:49:45.741885 PCI: 00:08.0 cmd <- 06
1429 15:49:45.745386 PCI: 00:12.0 subsystem <- 8086/02f9
1430 15:49:45.748381 PCI: 00:12.0 cmd <- 02
1431 15:49:45.751589 PCI: 00:14.0 subsystem <- 8086/02ed
1432 15:49:45.754923 PCI: 00:14.0 cmd <- 02
1433 15:49:45.755613 PCI: 00:14.2 cmd <- 02
1434 15:49:45.761346 PCI: 00:14.3 subsystem <- 8086/02f0
1435 15:49:45.761854 PCI: 00:14.3 cmd <- 02
1436 15:49:45.764630 PCI: 00:15.0 subsystem <- 8086/02e8
1437 15:49:45.767777 PCI: 00:15.0 cmd <- 02
1438 15:49:45.771150 PCI: 00:15.1 subsystem <- 8086/02e9
1439 15:49:45.774373 PCI: 00:15.1 cmd <- 02
1440 15:49:45.777545 PCI: 00:16.0 subsystem <- 8086/02e0
1441 15:49:45.780785 PCI: 00:16.0 cmd <- 02
1442 15:49:45.783994 PCI: 00:17.0 subsystem <- 8086/02d3
1443 15:49:45.787250 PCI: 00:17.0 cmd <- 03
1444 15:49:45.790769 PCI: 00:19.0 subsystem <- 8086/02c5
1445 15:49:45.793855 PCI: 00:19.0 cmd <- 02
1446 15:49:45.797107 PCI: 00:1d.0 bridge ctrl <- 0013
1447 15:49:45.800491 PCI: 00:1d.0 subsystem <- 8086/02b0
1448 15:49:45.803493 PCI: 00:1d.0 cmd <- 06
1449 15:49:45.806561 PCI: 00:1e.0 subsystem <- 8086/02a8
1450 15:49:45.810325 PCI: 00:1e.0 cmd <- 06
1451 15:49:45.813134 PCI: 00:1e.2 subsystem <- 8086/02aa
1452 15:49:45.816481 PCI: 00:1e.2 cmd <- 06
1453 15:49:45.819816 PCI: 00:1e.3 subsystem <- 8086/02ab
1454 15:49:45.823125 PCI: 00:1e.3 cmd <- 02
1455 15:49:45.826200 PCI: 00:1f.0 subsystem <- 8086/0284
1456 15:49:45.826303 PCI: 00:1f.0 cmd <- 407
1457 15:49:45.833139 PCI: 00:1f.3 subsystem <- 8086/02c8
1458 15:49:45.833233 PCI: 00:1f.3 cmd <- 02
1459 15:49:45.836260 PCI: 00:1f.4 subsystem <- 8086/02a3
1460 15:49:45.839919 PCI: 00:1f.4 cmd <- 03
1461 15:49:45.843157 PCI: 00:1f.5 subsystem <- 8086/02a4
1462 15:49:45.846109 PCI: 00:1f.5 cmd <- 406
1463 15:49:45.855713 PCI: 01:00.0 cmd <- 02
1464 15:49:45.860639 done.
1465 15:49:45.869461 ME: Version: 14.0.39.1367
1466 15:49:45.875922 BS: BS_DEV_ENABLE times (ms): entry 0 run 17 exit 8
1467 15:49:45.879489 Initializing devices...
1468 15:49:45.879587 Root Device init ...
1469 15:49:45.885572 Chrome EC: Set SMI mask to 0x0000000000000000
1470 15:49:45.889161 Chrome EC: clear events_b mask to 0x0000000000000000
1471 15:49:45.895688 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1472 15:49:45.902277 Chrome EC: Set S3 LAZY WAKE mask to 0x0000000014001006
1473 15:49:45.908818 Chrome EC: Set S0iX LAZY WAKE mask to 0x0000000014081006
1474 15:49:45.912274 Chrome EC: Set WAKE mask to 0x0000000000000000
1475 15:49:45.918421 Root Device init finished in 35137 usecs
1476 15:49:45.918518 CPU_CLUSTER: 0 init ...
1477 15:49:45.925617 CPU_CLUSTER: 0 init finished in 2443 usecs
1478 15:49:45.929872 PCI: 00:00.0 init ...
1479 15:49:45.933162 CPU TDP: 15 Watts
1480 15:49:45.936502 CPU PL2 = 64 Watts
1481 15:49:45.940139 PCI: 00:00.0 init finished in 7066 usecs
1482 15:49:45.942961 PCI: 00:02.0 init ...
1483 15:49:45.946099 PCI: 00:02.0 init finished in 2249 usecs
1484 15:49:45.949694 PCI: 00:08.0 init ...
1485 15:49:45.952696 PCI: 00:08.0 init finished in 2249 usecs
1486 15:49:45.956167 PCI: 00:12.0 init ...
1487 15:49:45.959458 PCI: 00:12.0 init finished in 2250 usecs
1488 15:49:45.963023 PCI: 00:14.0 init ...
1489 15:49:45.965748 PCI: 00:14.0 init finished in 2251 usecs
1490 15:49:45.969023 PCI: 00:14.2 init ...
1491 15:49:45.972742 PCI: 00:14.2 init finished in 2250 usecs
1492 15:49:45.976105 PCI: 00:14.3 init ...
1493 15:49:45.978854 PCI: 00:14.3 init finished in 2268 usecs
1494 15:49:45.982627 PCI: 00:15.0 init ...
1495 15:49:45.985421 DW I2C bus 0 at 0xd121f000 (400 KHz)
1496 15:49:45.992167 PCI: 00:15.0 init finished in 5971 usecs
1497 15:49:45.992254 PCI: 00:15.1 init ...
1498 15:49:45.998799 DW I2C bus 1 at 0xd1220000 (400 KHz)
1499 15:49:46.001917 PCI: 00:15.1 init finished in 5972 usecs
1500 15:49:46.005301 PCI: 00:16.0 init ...
1501 15:49:46.008991 PCI: 00:16.0 init finished in 2249 usecs
1502 15:49:46.011753 PCI: 00:19.0 init ...
1503 15:49:46.015606 DW I2C bus 4 at 0xd1222000 (400 KHz)
1504 15:49:46.018112 PCI: 00:19.0 init finished in 5971 usecs
1505 15:49:46.021810 PCI: 00:1d.0 init ...
1506 15:49:46.024622 Initializing PCH PCIe bridge.
1507 15:49:46.028288 PCI: 00:1d.0 init finished in 5280 usecs
1508 15:49:46.031875 PCI: 00:1f.0 init ...
1509 15:49:46.035099 IOAPIC: Initializing IOAPIC at 0xfec00000
1510 15:49:46.041799 IOAPIC: Bootstrap Processor Local APIC = 0x00
1511 15:49:46.041986 IOAPIC: ID = 0x02
1512 15:49:46.045386 IOAPIC: Dumping registers
1513 15:49:46.048208 reg 0x0000: 0x02000000
1514 15:49:46.052037 reg 0x0001: 0x00770020
1515 15:49:46.054343 reg 0x0002: 0x00000000
1516 15:49:46.057918 PCI: 00:1f.0 init finished in 23521 usecs
1517 15:49:46.061383 PCI: 00:1f.4 init ...
1518 15:49:46.064391 PCI: 00:1f.4 init finished in 2260 usecs
1519 15:49:46.076416 PCI: 01:00.0 init ...
1520 15:49:46.079725 PCI: 01:00.0 init finished in 2251 usecs
1521 15:49:46.084144 PNP: 0c09.0 init ...
1522 15:49:46.087024 Google Chrome EC uptime: 11.078 seconds
1523 15:49:46.093836 Google Chrome AP resets since EC boot: 0
1524 15:49:46.097031 Google Chrome most recent AP reset causes:
1525 15:49:46.103773 Google Chrome EC reset flags at last EC boot: reset-pin
1526 15:49:46.107145 PNP: 0c09.0 init finished in 20548 usecs
1527 15:49:46.110219 Devices initialized
1528 15:49:46.113240 Show all devs... After init.
1529 15:49:46.113774 Root Device: enabled 1
1530 15:49:46.116868 CPU_CLUSTER: 0: enabled 1
1531 15:49:46.120318 DOMAIN: 0000: enabled 1
1532 15:49:46.120904 APIC: 00: enabled 1
1533 15:49:46.123522 PCI: 00:00.0: enabled 1
1534 15:49:46.126504 PCI: 00:02.0: enabled 1
1535 15:49:46.129783 PCI: 00:04.0: enabled 0
1536 15:49:46.130281 PCI: 00:05.0: enabled 0
1537 15:49:46.132937 PCI: 00:12.0: enabled 1
1538 15:49:46.136443 PCI: 00:12.5: enabled 0
1539 15:49:46.139570 PCI: 00:12.6: enabled 0
1540 15:49:46.140063 PCI: 00:14.0: enabled 1
1541 15:49:46.142797 PCI: 00:14.1: enabled 0
1542 15:49:46.145946 PCI: 00:14.3: enabled 1
1543 15:49:46.149587 PCI: 00:14.5: enabled 0
1544 15:49:46.150187 PCI: 00:15.0: enabled 1
1545 15:49:46.152556 PCI: 00:15.1: enabled 1
1546 15:49:46.155710 PCI: 00:15.2: enabled 0
1547 15:49:46.158770 PCI: 00:15.3: enabled 0
1548 15:49:46.159260 PCI: 00:16.0: enabled 1
1549 15:49:46.162033 PCI: 00:16.1: enabled 0
1550 15:49:46.165396 PCI: 00:16.2: enabled 0
1551 15:49:46.169137 PCI: 00:16.3: enabled 0
1552 15:49:46.169758 PCI: 00:16.4: enabled 0
1553 15:49:46.172017 PCI: 00:16.5: enabled 0
1554 15:49:46.175581 PCI: 00:17.0: enabled 1
1555 15:49:46.178529 PCI: 00:19.0: enabled 1
1556 15:49:46.179145 PCI: 00:19.1: enabled 0
1557 15:49:46.181930 PCI: 00:19.2: enabled 0
1558 15:49:46.185517 PCI: 00:1a.0: enabled 0
1559 15:49:46.188698 PCI: 00:1c.0: enabled 0
1560 15:49:46.189334 PCI: 00:1c.1: enabled 0
1561 15:49:46.192170 PCI: 00:1c.2: enabled 0
1562 15:49:46.195464 PCI: 00:1c.3: enabled 0
1563 15:49:46.198650 PCI: 00:1c.4: enabled 0
1564 15:49:46.199237 PCI: 00:1c.5: enabled 0
1565 15:49:46.201991 PCI: 00:1c.6: enabled 0
1566 15:49:46.204827 PCI: 00:1c.7: enabled 0
1567 15:49:46.205357 PCI: 00:1d.0: enabled 1
1568 15:49:46.208221 PCI: 00:1d.1: enabled 0
1569 15:49:46.211801 PCI: 00:1d.2: enabled 0
1570 15:49:46.215060 PCI: 00:1d.3: enabled 0
1571 15:49:46.215643 PCI: 00:1d.4: enabled 0
1572 15:49:46.218077 PCI: 00:1d.5: enabled 0
1573 15:49:46.221380 PCI: 00:1e.0: enabled 1
1574 15:49:46.224784 PCI: 00:1e.1: enabled 0
1575 15:49:46.225401 PCI: 00:1e.2: enabled 1
1576 15:49:46.227966 PCI: 00:1e.3: enabled 1
1577 15:49:46.231291 PCI: 00:1f.0: enabled 1
1578 15:49:46.234993 PCI: 00:1f.1: enabled 0
1579 15:49:46.235575 PCI: 00:1f.2: enabled 0
1580 15:49:46.237468 PCI: 00:1f.3: enabled 1
1581 15:49:46.241053 PCI: 00:1f.4: enabled 1
1582 15:49:46.244169 PCI: 00:1f.5: enabled 1
1583 15:49:46.244752 PCI: 00:1f.6: enabled 0
1584 15:49:46.247568 USB0 port 0: enabled 1
1585 15:49:46.250889 I2C: 01:15: enabled 1
1586 15:49:46.251429 I2C: 02:5d: enabled 1
1587 15:49:46.254266 GENERIC: 0.0: enabled 1
1588 15:49:46.257213 I2C: 03:1a: enabled 1
1589 15:49:46.260681 I2C: 03:38: enabled 1
1590 15:49:46.261301 I2C: 03:39: enabled 1
1591 15:49:46.264025 I2C: 03:3a: enabled 1
1592 15:49:46.267116 I2C: 03:3b: enabled 1
1593 15:49:46.267603 PCI: 00:00.0: enabled 1
1594 15:49:46.270704 SPI: 00: enabled 1
1595 15:49:46.273446 SPI: 01: enabled 1
1596 15:49:46.273931 PNP: 0c09.0: enabled 1
1597 15:49:46.276875 USB2 port 0: enabled 1
1598 15:49:46.279829 USB2 port 1: enabled 1
1599 15:49:46.280316 USB2 port 2: enabled 0
1600 15:49:46.283783 USB2 port 3: enabled 0
1601 15:49:46.286400 USB2 port 5: enabled 0
1602 15:49:46.290017 USB2 port 6: enabled 1
1603 15:49:46.290506 USB2 port 9: enabled 1
1604 15:49:46.293377 USB3 port 0: enabled 1
1605 15:49:46.296516 USB3 port 1: enabled 1
1606 15:49:46.297108 USB3 port 2: enabled 1
1607 15:49:46.299568 USB3 port 3: enabled 1
1608 15:49:46.302760 USB3 port 4: enabled 0
1609 15:49:46.305970 APIC: 03: enabled 1
1610 15:49:46.306458 APIC: 01: enabled 1
1611 15:49:46.309452 APIC: 02: enabled 1
1612 15:49:46.310040 APIC: 05: enabled 1
1613 15:49:46.312968 APIC: 06: enabled 1
1614 15:49:46.316333 APIC: 07: enabled 1
1615 15:49:46.316927 APIC: 04: enabled 1
1616 15:49:46.319283 PCI: 00:08.0: enabled 1
1617 15:49:46.322595 PCI: 00:14.2: enabled 1
1618 15:49:46.323187 PCI: 01:00.0: enabled 1
1619 15:49:46.327400 Disabling ACPI via APMC:
1620 15:49:46.331242 done.
1621 15:49:46.334765 FMAP: area RW_ELOG found @ af0000 (16384 bytes)
1622 15:49:46.337896 ELOG: NV offset 0xaf0000 size 0x4000
1623 15:49:46.345417 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1624 15:49:46.352073 ELOG: Event(17) added with size 13 at 2022-09-17 15:49:37 UTC
1625 15:49:46.358131 POST: Unexpected post code in previous boot: 0x73
1626 15:49:46.364559 ELOG: Event(A3) added with size 11 at 2022-09-17 15:49:37 UTC
1627 15:49:46.371416 ELOG: Event(A6) added with size 13 at 2022-09-17 15:49:37 UTC
1628 15:49:46.378195 ELOG: Event(92) added with size 9 at 2022-09-17 15:49:37 UTC
1629 15:49:46.384540 ELOG: Event(93) added with size 9 at 2022-09-17 15:49:37 UTC
1630 15:49:46.387928 ELOG: Event(9A) added with size 9 at 2022-09-17 15:49:37 UTC
1631 15:49:46.394150 ELOG: Event(9E) added with size 10 at 2022-09-17 15:49:37 UTC
1632 15:49:46.401146 ELOG: Event(9F) added with size 14 at 2022-09-17 15:49:37 UTC
1633 15:49:46.407720 BS: BS_DEV_INIT times (ms): entry 0 run 27 exit 6
1634 15:49:46.414123 ELOG: Event(A1) added with size 10 at 2022-09-17 15:49:37 UTC
1635 15:49:46.420718 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1636 15:49:46.426880 ELOG: Event(A0) added with size 9 at 2022-09-17 15:49:37 UTC
1637 15:49:46.433228 elog_add_boot_reason: Logged dev mode boot
1638 15:49:46.433750 Finalize devices...
1639 15:49:46.437384 PCI: 00:17.0 final
1640 15:49:46.437984 Devices finalized
1641 15:49:46.443981 FMAP: area RW_NVRAM found @ afa000 (24576 bytes)
1642 15:49:46.450196 BS: BS_POST_DEVICE times (ms): entry 1 run 0 exit 0
1643 15:49:46.453104 ME: HFSTS1 : 0x90000245
1644 15:49:46.456485 ME: HFSTS2 : 0x3B850126
1645 15:49:46.459813 ME: HFSTS3 : 0x00000020
1646 15:49:46.466708 ME: HFSTS4 : 0x00004800
1647 15:49:46.470061 ME: HFSTS5 : 0x00000000
1648 15:49:46.473118 ME: HFSTS6 : 0x40400006
1649 15:49:46.476533 ME: Manufacturing Mode : NO
1650 15:49:46.479647 ME: FW Partition Table : OK
1651 15:49:46.482648 ME: Bringup Loader Failure : NO
1652 15:49:46.486356 ME: Firmware Init Complete : YES
1653 15:49:46.489480 ME: Boot Options Present : NO
1654 15:49:46.492580 ME: Update In Progress : NO
1655 15:49:46.495787 ME: D0i3 Support : YES
1656 15:49:46.499589 ME: Low Power State Enabled : NO
1657 15:49:46.502350 ME: CPU Replaced : NO
1658 15:49:46.506361 ME: CPU Replacement Valid : YES
1659 15:49:46.509360 ME: Current Working State : 5
1660 15:49:46.512697 ME: Current Operation State : 1
1661 15:49:46.515996 ME: Current Operation Mode : 0
1662 15:49:46.519255 ME: Error Code : 0
1663 15:49:46.522600 ME: CPU Debug Disabled : YES
1664 15:49:46.525927 ME: TXT Support : NO
1665 15:49:46.532517 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
1666 15:49:46.535548 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1667 15:49:46.539130 CBFS @ c08000 size 3f8000
1668 15:49:46.545312 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1669 15:49:46.548548 CBFS: Locating 'fallback/dsdt.aml'
1670 15:49:46.551572 CBFS: Found @ offset 10bb80 size 3fa5
1671 15:49:46.558219 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1672 15:49:46.561528 CBFS @ c08000 size 3f8000
1673 15:49:46.568269 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1674 15:49:46.568861 CBFS: Locating 'fallback/slic'
1675 15:49:46.573789 CBFS: 'fallback/slic' not found.
1676 15:49:46.579696 ACPI: Writing ACPI tables at 99b3e000.
1677 15:49:46.580251 ACPI: * FACS
1678 15:49:46.583172 ACPI: * DSDT
1679 15:49:46.586485 Ramoops buffer: 0x100000@0x99a3d000.
1680 15:49:46.590612 FMAP: area RO_VPD found @ c00000 (16384 bytes)
1681 15:49:46.596465 FMAP: area RW_VPD found @ af8000 (8192 bytes)
1682 15:49:46.599949 Google Chrome EC: version:
1683 15:49:46.603070 ro: helios_v2.0.2659-56403530b
1684 15:49:46.606431 rw: helios_v2.0.2849-c41de27e7d
1685 15:49:46.606924 running image: 1
1686 15:49:46.610915 ACPI: * FADT
1687 15:49:46.611517 SCI is IRQ9
1688 15:49:46.617104 ACPI: added table 1/32, length now 40
1689 15:49:46.617634 ACPI: * SSDT
1690 15:49:46.620377 Found 1 CPU(s) with 8 core(s) each.
1691 15:49:46.623956 Error: Could not locate 'wifi_sar' in VPD.
1692 15:49:46.630232 Checking CBFS for default SAR values
1693 15:49:46.633926 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1694 15:49:46.636761 CBFS @ c08000 size 3f8000
1695 15:49:46.643404 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1696 15:49:46.646811 CBFS: Locating 'wifi_sar_defaults.hex'
1697 15:49:46.650398 CBFS: Found @ offset 5fac0 size 77
1698 15:49:46.653403 \_SB.PCI0.WFA3: Intel WiFi PCI: 00:14.3
1699 15:49:46.659802 \_SB.PCI0.I2C0.D015: ELAN Touchpad at I2C: 01:15
1700 15:49:46.663180 \_SB.PCI0.I2C1.H05D: Goodix Touchscreen at I2C: 02:5d
1701 15:49:46.669648 \_SB.PCI0.I2C4.RT58: Realtek RT5682 at I2C: 03:1a
1702 15:49:46.672695 failed to find key in VPD: dsm_calib_r0_0
1703 15:49:46.682608 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_0 and dsm_calib_temp_0
1704 15:49:46.685848 \_SB.PCI0.I2C4.RTWL: Realtek RT1011 Codec address 038h
1705 15:49:46.692593 failed to find key in VPD: dsm_calib_r0_1
1706 15:49:46.699380 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_1 and dsm_calib_temp_0
1707 15:49:46.705538 \_SB.PCI0.I2C4.RTWR: Realtek RT1011 Codec address 039h
1708 15:49:46.708870 failed to find key in VPD: dsm_calib_r0_2
1709 15:49:46.718680 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_2 and dsm_calib_temp_0
1710 15:49:46.725028 \_SB.PCI0.I2C4.RTTL: Realtek RT1011 Codec address 03ah
1711 15:49:46.728732 failed to find key in VPD: dsm_calib_r0_3
1712 15:49:46.738544 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_3 and dsm_calib_temp_0
1713 15:49:46.741705 \_SB.PCI0.I2C4.RTTR: Realtek RT1011 Codec address 03bh
1714 15:49:46.748383 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1715 15:49:46.751700 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 01
1716 15:49:46.754785 EC returned error result code 1
1717 15:49:46.758246 EC returned error result code 1
1718 15:49:46.761384 EC returned error result code 1
1719 15:49:46.768886 PS2K: Bad resp from EC. Vivaldi disabled!
1720 15:49:46.771526 \_SB.PCI0.XHCI.RHUB.HS01: Left Type-C Port at USB2 port 0
1721 15:49:46.777909 \_SB.PCI0.XHCI.RHUB.HS02: Right Type-C Port 1 at USB2 port 1
1722 15:49:46.784315 \_SB.PCI0.XHCI.RHUB.HS07: Camera at USB2 port 6
1723 15:49:46.787959 \_SB.PCI0.XHCI.RHUB.HS10: Bluetooth at USB2 port 9
1724 15:49:46.794342 \_SB.PCI0.XHCI.RHUB.SS01: Left Type-C Port at USB3 port 0
1725 15:49:46.801104 \_SB.PCI0.XHCI.RHUB.SS02: Right Type-C Port 1 at USB3 port 1
1726 15:49:46.803951 \_SB.PCI0.XHCI.RHUB.SS03: Left Type-A Port at USB3 port 2
1727 15:49:46.811014 \_SB.PCI0.XHCI.RHUB.SS04: Right Type-A Port 1 at USB3 port 3
1728 15:49:46.814124 ACPI: added table 2/32, length now 44
1729 15:49:46.817788 ACPI: * MCFG
1730 15:49:46.820887 ACPI: added table 3/32, length now 48
1731 15:49:46.823921 ACPI: * TPM2
1732 15:49:46.826992 TPM2 log created at 99a2d000
1733 15:49:46.830310 ACPI: added table 4/32, length now 52
1734 15:49:46.830902 ACPI: * MADT
1735 15:49:46.833933 SCI is IRQ9
1736 15:49:46.837197 ACPI: added table 5/32, length now 56
1737 15:49:46.837826 current = 99b43ac0
1738 15:49:46.840617 ACPI: * DMAR
1739 15:49:46.843416 ACPI: added table 6/32, length now 60
1740 15:49:46.847200 ACPI: * IGD OpRegion
1741 15:49:46.847789 GMA: Found VBT in CBFS
1742 15:49:46.850346 GMA: Found valid VBT in CBFS
1743 15:49:46.857070 ACPI: added table 7/32, length now 64
1744 15:49:46.857753 ACPI: * HPET
1745 15:49:46.860040 ACPI: added table 8/32, length now 68
1746 15:49:46.862734 ACPI: done.
1747 15:49:46.863259 ACPI tables: 31744 bytes.
1748 15:49:46.866494 smbios_write_tables: 99a2c000
1749 15:49:46.869239 EC returned error result code 3
1750 15:49:46.876107 Couldn't obtain OEM name from CBI
1751 15:49:46.876596 Create SMBIOS type 17
1752 15:49:46.879280 PCI: 00:00.0 (Intel Cannonlake)
1753 15:49:46.882533 PCI: 00:14.3 (Intel WiFi)
1754 15:49:46.885616 SMBIOS tables: 939 bytes.
1755 15:49:46.888786 Writing table forward entry at 0x00000500
1756 15:49:46.895757 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4628
1757 15:49:46.898741 Writing coreboot table at 0x99b62000
1758 15:49:46.905451 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1759 15:49:46.908757 1. 0000000000001000-000000000009ffff: RAM
1760 15:49:46.915593 2. 00000000000a0000-00000000000fffff: RESERVED
1761 15:49:46.918315 3. 0000000000100000-0000000099a2bfff: RAM
1762 15:49:46.925148 4. 0000000099a2c000-0000000099baffff: CONFIGURATION TABLES
1763 15:49:46.928083 5. 0000000099bb0000-0000000099c0afff: RAMSTAGE
1764 15:49:46.934835 6. 0000000099c0b000-0000000099ffffff: CONFIGURATION TABLES
1765 15:49:46.941209 7. 000000009a000000-000000009f7fffff: RESERVED
1766 15:49:46.944721 8. 00000000e0000000-00000000efffffff: RESERVED
1767 15:49:46.951180 9. 00000000fc000000-00000000fc000fff: RESERVED
1768 15:49:46.954299 10. 00000000fe000000-00000000fe00ffff: RESERVED
1769 15:49:46.958008 11. 00000000fed10000-00000000fed17fff: RESERVED
1770 15:49:46.964441 12. 00000000fed80000-00000000fed83fff: RESERVED
1771 15:49:46.967459 13. 00000000fed90000-00000000fed91fff: RESERVED
1772 15:49:46.973896 14. 00000000feda0000-00000000feda1fff: RESERVED
1773 15:49:46.977621 15. 0000000100000000-000000045e7fffff: RAM
1774 15:49:46.980777 Graphics framebuffer located at 0xc0000000
1775 15:49:46.984254 Passing 5 GPIOs to payload:
1776 15:49:46.990541 NAME | PORT | POLARITY | VALUE
1777 15:49:46.996673 write protect | undefined | high | low
1778 15:49:47.000692 lid | undefined | high | high
1779 15:49:47.006858 power | undefined | high | low
1780 15:49:47.010041 oprom | undefined | high | low
1781 15:49:47.016991 EC in RW | 0x000000cb | high | low
1782 15:49:47.017522 Board ID: 4
1783 15:49:47.023241 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1784 15:49:47.026733 CBFS @ c08000 size 3f8000
1785 15:49:47.030181 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1786 15:49:47.036567 Wrote coreboot table at: 99b62000, 0x5bc bytes, checksum 4d87
1787 15:49:47.039843 coreboot table: 1492 bytes.
1788 15:49:47.042553 IMD ROOT 0. 99fff000 00001000
1789 15:49:47.045864 IMD SMALL 1. 99ffe000 00001000
1790 15:49:47.049533 FSP MEMORY 2. 99c4e000 003b0000
1791 15:49:47.052583 CONSOLE 3. 99c2e000 00020000
1792 15:49:47.056067 FMAP 4. 99c2d000 0000054e
1793 15:49:47.058987 TIME STAMP 5. 99c2c000 00000910
1794 15:49:47.062287 VBOOT WORK 6. 99c18000 00014000
1795 15:49:47.065645 MRC DATA 7. 99c16000 00001958
1796 15:49:47.069039 ROMSTG STCK 8. 99c15000 00001000
1797 15:49:47.071920 AFTER CAR 9. 99c0b000 0000a000
1798 15:49:47.075288 RAMSTAGE 10. 99baf000 0005c000
1799 15:49:47.078359 REFCODE 11. 99b7a000 00035000
1800 15:49:47.081930 SMM BACKUP 12. 99b6a000 00010000
1801 15:49:47.085095 COREBOOT 13. 99b62000 00008000
1802 15:49:47.088690 ACPI 14. 99b3e000 00024000
1803 15:49:47.094872 ACPI GNVS 15. 99b3d000 00001000
1804 15:49:47.097880 RAMOOPS 16. 99a3d000 00100000
1805 15:49:47.101619 TPM2 TCGLOG17. 99a2d000 00010000
1806 15:49:47.104578 SMBIOS 18. 99a2c000 00000800
1807 15:49:47.105074 IMD small region:
1808 15:49:47.107745 IMD ROOT 0. 99ffec00 00000400
1809 15:49:47.111431 FSP RUNTIME 1. 99ffebe0 00000004
1810 15:49:47.114391 EC HOSTEVENT 2. 99ffebc0 00000008
1811 15:49:47.117996 POWER STATE 3. 99ffeb80 00000040
1812 15:49:47.124230 ROMSTAGE 4. 99ffeb60 00000004
1813 15:49:47.127734 MEM INFO 5. 99ffe9a0 000001b9
1814 15:49:47.131279 VPD 6. 99ffe920 0000006c
1815 15:49:47.134377 MTRR: Physical address space:
1816 15:49:47.141152 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1817 15:49:47.144365 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1818 15:49:47.150414 0x00000000000c0000 - 0x000000009b000000 size 0x9af40000 type 6
1819 15:49:47.157572 0x000000009b000000 - 0x00000000c0000000 size 0x25000000 type 0
1820 15:49:47.163823 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 1
1821 15:49:47.170300 0x00000000d0000000 - 0x0000000100000000 size 0x30000000 type 0
1822 15:49:47.176665 0x0000000100000000 - 0x000000045e800000 size 0x35e800000 type 6
1823 15:49:47.180272 MTRR: Fixed MSR 0x250 0x0606060606060606
1824 15:49:47.183767 MTRR: Fixed MSR 0x258 0x0606060606060606
1825 15:49:47.189700 MTRR: Fixed MSR 0x259 0x0000000000000000
1826 15:49:47.193086 MTRR: Fixed MSR 0x268 0x0606060606060606
1827 15:49:47.196561 MTRR: Fixed MSR 0x269 0x0606060606060606
1828 15:49:47.199423 MTRR: Fixed MSR 0x26a 0x0606060606060606
1829 15:49:47.205788 MTRR: Fixed MSR 0x26b 0x0606060606060606
1830 15:49:47.209527 MTRR: Fixed MSR 0x26c 0x0606060606060606
1831 15:49:47.212490 MTRR: Fixed MSR 0x26d 0x0606060606060606
1832 15:49:47.216369 MTRR: Fixed MSR 0x26e 0x0606060606060606
1833 15:49:47.222276 MTRR: Fixed MSR 0x26f 0x0606060606060606
1834 15:49:47.226237 call enable_fixed_mtrr()
1835 15:49:47.229152 CPU physical address size: 39 bits
1836 15:49:47.232782 MTRR: default type WB/UC MTRR counts: 6/8.
1837 15:49:47.236070 MTRR: WB selected as default type.
1838 15:49:47.242466 MTRR: 0 base 0x000000009b000000 mask 0x0000007fff000000 type 0
1839 15:49:47.248728 MTRR: 1 base 0x000000009c000000 mask 0x0000007ffc000000 type 0
1840 15:49:47.255349 MTRR: 2 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
1841 15:49:47.261848 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 1
1842 15:49:47.268373 MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 0
1843 15:49:47.274821 MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
1844 15:49:47.278067 MTRR: Fixed MSR 0x250 0x0606060606060606
1845 15:49:47.281381 MTRR: Fixed MSR 0x258 0x0606060606060606
1846 15:49:47.287763 MTRR: Fixed MSR 0x259 0x0000000000000000
1847 15:49:47.290997 MTRR: Fixed MSR 0x268 0x0606060606060606
1848 15:49:47.294582 MTRR: Fixed MSR 0x269 0x0606060606060606
1849 15:49:47.297851 MTRR: Fixed MSR 0x26a 0x0606060606060606
1850 15:49:47.304436 MTRR: Fixed MSR 0x26b 0x0606060606060606
1851 15:49:47.307729 MTRR: Fixed MSR 0x26c 0x0606060606060606
1852 15:49:47.310645 MTRR: Fixed MSR 0x26d 0x0606060606060606
1853 15:49:47.313834 MTRR: Fixed MSR 0x26e 0x0606060606060606
1854 15:49:47.320717 MTRR: Fixed MSR 0x26f 0x0606060606060606
1855 15:49:47.321335
1856 15:49:47.321761 MTRR check
1857 15:49:47.324058 Fixed MTRRs : Enabled
1858 15:49:47.327161 Variable MTRRs: Enabled
1859 15:49:47.327757
1860 15:49:47.328166 call enable_fixed_mtrr()
1861 15:49:47.333705 BS: BS_WRITE_TABLES times (ms): entry 0 run 9 exit 2
1862 15:49:47.337385 CPU physical address size: 39 bits
1863 15:49:47.344000 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1864 15:49:47.347152 MTRR: Fixed MSR 0x250 0x0606060606060606
1865 15:49:47.350407 MTRR: Fixed MSR 0x250 0x0606060606060606
1866 15:49:47.356791 MTRR: Fixed MSR 0x258 0x0606060606060606
1867 15:49:47.359757 MTRR: Fixed MSR 0x259 0x0000000000000000
1868 15:49:47.363485 MTRR: Fixed MSR 0x268 0x0606060606060606
1869 15:49:47.366632 MTRR: Fixed MSR 0x269 0x0606060606060606
1870 15:49:47.369621 MTRR: Fixed MSR 0x26a 0x0606060606060606
1871 15:49:47.376124 MTRR: Fixed MSR 0x26b 0x0606060606060606
1872 15:49:47.379750 MTRR: Fixed MSR 0x26c 0x0606060606060606
1873 15:49:47.382593 MTRR: Fixed MSR 0x26d 0x0606060606060606
1874 15:49:47.385949 MTRR: Fixed MSR 0x26e 0x0606060606060606
1875 15:49:47.392291 MTRR: Fixed MSR 0x26f 0x0606060606060606
1876 15:49:47.395869 MTRR: Fixed MSR 0x258 0x0606060606060606
1877 15:49:47.399007 call enable_fixed_mtrr()
1878 15:49:47.402595 MTRR: Fixed MSR 0x259 0x0000000000000000
1879 15:49:47.405973 MTRR: Fixed MSR 0x268 0x0606060606060606
1880 15:49:47.412599 MTRR: Fixed MSR 0x269 0x0606060606060606
1881 15:49:47.415843 MTRR: Fixed MSR 0x26a 0x0606060606060606
1882 15:49:47.418887 MTRR: Fixed MSR 0x26b 0x0606060606060606
1883 15:49:47.422036 MTRR: Fixed MSR 0x26c 0x0606060606060606
1884 15:49:47.428462 MTRR: Fixed MSR 0x26d 0x0606060606060606
1885 15:49:47.431822 MTRR: Fixed MSR 0x26e 0x0606060606060606
1886 15:49:47.435105 MTRR: Fixed MSR 0x26f 0x0606060606060606
1887 15:49:47.438460 CPU physical address size: 39 bits
1888 15:49:47.442347 call enable_fixed_mtrr()
1889 15:49:47.445474 MTRR: Fixed MSR 0x250 0x0606060606060606
1890 15:49:47.451968 MTRR: Fixed MSR 0x250 0x0606060606060606
1891 15:49:47.455467 MTRR: Fixed MSR 0x258 0x0606060606060606
1892 15:49:47.458602 MTRR: Fixed MSR 0x259 0x0000000000000000
1893 15:49:47.461643 MTRR: Fixed MSR 0x268 0x0606060606060606
1894 15:49:47.465160 MTRR: Fixed MSR 0x269 0x0606060606060606
1895 15:49:47.471963 MTRR: Fixed MSR 0x26a 0x0606060606060606
1896 15:49:47.474753 MTRR: Fixed MSR 0x26b 0x0606060606060606
1897 15:49:47.477966 MTRR: Fixed MSR 0x26c 0x0606060606060606
1898 15:49:47.481688 MTRR: Fixed MSR 0x26d 0x0606060606060606
1899 15:49:47.488062 MTRR: Fixed MSR 0x26e 0x0606060606060606
1900 15:49:47.491114 MTRR: Fixed MSR 0x26f 0x0606060606060606
1901 15:49:47.494492 MTRR: Fixed MSR 0x258 0x0606060606060606
1902 15:49:47.501082 MTRR: Fixed MSR 0x259 0x0000000000000000
1903 15:49:47.504215 MTRR: Fixed MSR 0x268 0x0606060606060606
1904 15:49:47.507706 MTRR: Fixed MSR 0x269 0x0606060606060606
1905 15:49:47.510839 MTRR: Fixed MSR 0x26a 0x0606060606060606
1906 15:49:47.517339 MTRR: Fixed MSR 0x26b 0x0606060606060606
1907 15:49:47.520601 MTRR: Fixed MSR 0x26c 0x0606060606060606
1908 15:49:47.524069 MTRR: Fixed MSR 0x26d 0x0606060606060606
1909 15:49:47.527604 MTRR: Fixed MSR 0x26e 0x0606060606060606
1910 15:49:47.533746 MTRR: Fixed MSR 0x26f 0x0606060606060606
1911 15:49:47.534242 call enable_fixed_mtrr()
1912 15:49:47.537378 call enable_fixed_mtrr()
1913 15:49:47.540228 CPU physical address size: 39 bits
1914 15:49:47.544071 CPU physical address size: 39 bits
1915 15:49:47.547300 CBFS @ c08000 size 3f8000
1916 15:49:47.553925 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1917 15:49:47.557145 CBFS: Locating 'fallback/payload'
1918 15:49:47.560332 MTRR: Fixed MSR 0x250 0x0606060606060606
1919 15:49:47.563397 MTRR: Fixed MSR 0x250 0x0606060606060606
1920 15:49:47.569988 MTRR: Fixed MSR 0x258 0x0606060606060606
1921 15:49:47.573200 MTRR: Fixed MSR 0x259 0x0000000000000000
1922 15:49:47.576061 MTRR: Fixed MSR 0x268 0x0606060606060606
1923 15:49:47.583128 MTRR: Fixed MSR 0x269 0x0606060606060606
1924 15:49:47.586123 MTRR: Fixed MSR 0x26a 0x0606060606060606
1925 15:49:47.589501 MTRR: Fixed MSR 0x26b 0x0606060606060606
1926 15:49:47.592580 MTRR: Fixed MSR 0x26c 0x0606060606060606
1927 15:49:47.599411 MTRR: Fixed MSR 0x26d 0x0606060606060606
1928 15:49:47.602548 MTRR: Fixed MSR 0x26e 0x0606060606060606
1929 15:49:47.605878 MTRR: Fixed MSR 0x26f 0x0606060606060606
1930 15:49:47.609036 MTRR: Fixed MSR 0x258 0x0606060606060606
1931 15:49:47.612798 call enable_fixed_mtrr()
1932 15:49:47.615816 MTRR: Fixed MSR 0x259 0x0000000000000000
1933 15:49:47.622039 MTRR: Fixed MSR 0x268 0x0606060606060606
1934 15:49:47.625205 MTRR: Fixed MSR 0x269 0x0606060606060606
1935 15:49:47.629013 MTRR: Fixed MSR 0x26a 0x0606060606060606
1936 15:49:47.631877 MTRR: Fixed MSR 0x26b 0x0606060606060606
1937 15:49:47.638693 MTRR: Fixed MSR 0x26c 0x0606060606060606
1938 15:49:47.642045 MTRR: Fixed MSR 0x26d 0x0606060606060606
1939 15:49:47.645810 MTRR: Fixed MSR 0x26e 0x0606060606060606
1940 15:49:47.648688 MTRR: Fixed MSR 0x26f 0x0606060606060606
1941 15:49:47.655010 CPU physical address size: 39 bits
1942 15:49:47.655597 call enable_fixed_mtrr()
1943 15:49:47.658455 CPU physical address size: 39 bits
1944 15:49:47.664831 CPU physical address size: 39 bits
1945 15:49:47.668224 CBFS: Found @ offset 1c96c0 size 3f798
1946 15:49:47.671486 Checking segment from ROM address 0xffdd16f8
1947 15:49:47.677922 Checking segment from ROM address 0xffdd1714
1948 15:49:47.681247 Loading segment from ROM address 0xffdd16f8
1949 15:49:47.684208 code (compression=0)
1950 15:49:47.690854 New segment dstaddr 0x30000000 memsize 0x657430 srcaddr 0xffdd1730 filesize 0x3f760
1951 15:49:47.700500 Loading Segment: addr: 0x30000000 memsz: 0x0000000000657430 filesz: 0x000000000003f760
1952 15:49:47.701100 it's not compressed!
1953 15:49:47.794152 [ 0x30000000, 3003f760, 0x30657430) <- ffdd1730
1954 15:49:47.800725 Clearing Segment: addr: 0x000000003003f760 memsz: 0x0000000000617cd0
1955 15:49:47.803996 Loading segment from ROM address 0xffdd1714
1956 15:49:47.807159 Entry Point 0x30000000
1957 15:49:47.810796 Loaded segments
1958 15:49:47.816349 Finalizing chipset.
1959 15:49:47.819461 Finalizing SMM.
1960 15:49:47.822822 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 88 exit 5
1961 15:49:47.826160 mp_park_aps done after 0 msecs.
1962 15:49:47.832994 Jumping to boot code at 30000000(99b62000)
1963 15:49:47.839033 CPU0: stack: 99bf9000 - 99bfa000, lowest used address 99bf99d8, stack used: 1576 bytes
1964 15:49:47.839534
1965 15:49:47.842152 Starting depthcharge on Helios...
1966 15:49:47.843436 end: 2.2.3 depthcharge-start (duration 00:00:20) [common]
1967 15:49:47.844015 start: 2.2.4 bootloader-commands (timeout 00:04:40) [common]
1968 15:49:47.844473 Setting prompt string to ['hatch:']
1969 15:49:47.844923 bootloader-commands: Wait for prompt ['hatch:'] (timeout 00:04:40)
1970 15:49:47.852436 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
1971 15:49:47.858903 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
1972 15:49:47.865397 board_setup: Info: eMMC controller not present; skipping
1973 15:49:47.868728 New NVMe Controller 0x30053ac0 @ 00:1d:00
1974 15:49:47.875095 board_setup: Info: SDHCI controller not present; skipping
1975 15:49:47.881416 vboot_create_vbsd: creating legacy VbSharedDataHeader structure
1976 15:49:47.881909 Wipe memory regions:
1977 15:49:47.888172 [0x00000000001000, 0x000000000a0000)
1978 15:49:47.891579 [0x00000000100000, 0x00000030000000)
1979 15:49:47.958760 [0x00000030657430, 0x00000099a2c000)
1980 15:49:48.099184 [0x00000100000000, 0x0000045e800000)
1981 15:49:49.481470 R8152: Initializing
1982 15:49:49.484667 Version 9 (ocp_data = 6010)
1983 15:49:49.488888 R8152: Done initializing
1984 15:49:49.491832 Adding net device
1985 15:49:49.867048 [firmware-hatch-12672.B-collabora] Jul 21 2021 08:27:58
1986 15:49:49.867618
1987 15:49:49.868449 Setting prompt string to ['hatch:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n']
1989 15:49:49.970120 hatch: tftpboot 192.168.201.1 7300485/tftp-deploy-buu_c0w0/kernel/bzImage 7300485/tftp-deploy-buu_c0w0/kernel/cmdline 7300485/tftp-deploy-buu_c0w0/ramdisk/ramdisk.cpio.gz
1990 15:49:49.970755 Setting prompt string to 'Starting kernel'
1991 15:49:49.971243 Setting prompt string to ['Starting kernel']
1992 15:49:49.971664 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n']
1993 15:49:49.972094 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n'] (timeout 00:04:38)
1994 15:49:49.975821 tftpboot 192.168.201.1 7300485/tftp-deploy-buu_c0w0/kernel/bzImoy-buu_c0w0/kernel/cmdline 7300485/tftp-deploy-buu_c0w0/ramdisk/ramdisk.cpio.gz
1995 15:49:49.976361 Waiting for link
1996 15:49:50.176627 done.
1997 15:49:50.177220 MAC: f4:f5:e8:50:e5:3a
1998 15:49:50.179760 Sending DHCP discover... done.
1999 15:49:50.183267 Waiting for reply... done.
2000 15:49:50.186132 Sending DHCP request... done.
2001 15:49:50.189615 Waiting for reply... done.
2002 15:49:50.193148 My ip is 192.168.201.15
2003 15:49:50.196225 The DHCP server ip is 192.168.201.1
2004 15:49:50.199449 TFTP server IP predefined by user: 192.168.201.1
2005 15:49:50.206161 Bootfile predefined by user: 7300485/tftp-deploy-buu_c0w0/kernel/bzImage
2006 15:49:50.209547 Sending tftp read request... done.
2007 15:49:50.216903 Waiting for the transfer...
2008 15:49:50.594337 00000000 ################################################################
2009 15:49:50.904534 00080000 ################################################################
2010 15:49:51.183188 00100000 ################################################################
2011 15:49:51.441627 00180000 ################################################################
2012 15:49:51.710195 00200000 ################################################################
2013 15:49:51.977087 00280000 ################################################################
2014 15:49:52.244984 00300000 ################################################################
2015 15:49:52.509758 00380000 ################################################################
2016 15:49:52.800187 00400000 ################################################################
2017 15:49:53.063275 00480000 ################################################################
2018 15:49:53.365528 00500000 ################################################################
2019 15:49:53.646337 00580000 ################################################################
2020 15:49:53.941962 00600000 ################################################################ done.
2021 15:49:53.945033 The bootfile was 6815632 bytes long.
2022 15:49:53.948211 Sending tftp read request... done.
2023 15:49:53.951510 Waiting for the transfer...
2024 15:49:54.180420 00000000 ################################################################
2025 15:49:54.414303 00080000 ################################################################
2026 15:49:54.641468 00100000 ################################################################
2027 15:49:54.904493 00180000 ################################################################
2028 15:49:55.148800 00200000 ################################################################
2029 15:49:55.414065 00280000 ################################################################
2030 15:49:55.692112 00300000 ################################################################
2031 15:49:55.971452 00380000 ################################################################
2032 15:49:56.274916 00400000 ################################################################
2033 15:49:56.563680 00480000 ################################################################
2034 15:49:56.839489 00500000 ################################################################
2035 15:49:57.125009 00580000 ################################################################
2036 15:49:57.413666 00600000 ################################################################
2037 15:49:57.665317 00680000 ################################################################
2038 15:49:57.917478 00700000 ################################################################
2039 15:49:58.184652 00780000 ################################################################
2040 15:49:58.251591 00800000 #################### done.
2041 15:49:58.255207 Sending tftp read request... done.
2042 15:49:58.258165 Waiting for the transfer...
2043 15:49:58.261259 00000000 # done.
2044 15:49:58.271304 Command line loaded dynamically from TFTP file: 7300485/tftp-deploy-buu_c0w0/kernel/cmdline
2045 15:49:58.287645 The command line is: earlyprintk=uart8250,mmio32,0xfedc6000,115200n8 console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2046 15:49:58.294020 ec_init(0): CrosEC protocol v3 supported (256, 256)
2047 15:49:58.301163 Shutting down all USB controllers.
2048 15:49:58.301317 Removing current net device
2049 15:49:58.305032 Finalizing coreboot
2050 15:49:58.311480 Exiting depthcharge with code 4 at timestamp: 17750400
2051 15:49:58.311737
2052 15:49:58.311871 Starting kernel ...
2053 15:49:58.311991
2054 15:49:58.312106
2055 15:49:58.312515 end: 2.2.4 bootloader-commands (duration 00:00:10) [common]
2056 15:49:58.312699 start: 2.2.5 auto-login-action (timeout 00:04:30) [common]
2057 15:49:58.312840 Setting prompt string to ['Linux version [0-9]']
2058 15:49:58.312974 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n']
2059 15:49:58.313105 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n'] (timeout 00:05:00)
2061 15:54:28.313563 end: 2.2.5 auto-login-action (duration 00:04:30) [common]
2063 15:54:28.314610 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 270 seconds'
2065 15:54:28.315392 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2068 15:54:28.316731 end: 2 depthcharge-action (duration 00:05:00) [common]
2070 15:54:28.317745 Cleaning after the job
2071 15:54:28.318133 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/7300485/tftp-deploy-buu_c0w0/ramdisk
2072 15:54:28.320962 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/7300485/tftp-deploy-buu_c0w0/kernel
2073 15:54:28.323344 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/7300485/tftp-deploy-buu_c0w0/modules
2074 15:54:28.324331 start: 5.1 power-off (timeout 00:00:30) [common]
2075 15:54:28.325087 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-3' '--port=1' '--command=off'
2076 15:54:28.362026 >> Command sent successfully.
2077 15:54:28.363968 Returned 0 in 0 seconds
2078 15:54:28.464749 end: 5.1 power-off (duration 00:00:00) [common]
2080 15:54:28.465070 start: 5.2 read-feedback (timeout 00:10:00) [common]
2081 15:54:28.465355 Listened to connection for namespace 'common' for up to 1s
2082 15:54:29.470293 Finalising connection for namespace 'common'
2083 15:54:29.470486 Disconnecting from shell: Finalise
2084 15:54:29.571347 end: 5.2 read-feedback (duration 00:00:01) [common]
2085 15:54:29.571527 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/7300485
2086 15:54:29.576664 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/7300485
2087 15:54:29.576799 JobError: Your job cannot terminate cleanly.