Boot log: asus-C436FA-Flip-hatch
- Kernel Errors: 0
- Boot result: FAIL
- Kernel Warnings: 0
- Warnings: 0
- Errors: 2
1 15:43:30.773945 lava-dispatcher, installed at version: 2022.06
2 15:43:30.774176 start: 0 validate
3 15:43:30.774322 Start time: 2022-09-17 15:43:30.774313+00:00 (UTC)
4 15:43:30.774467 Using caching service: 'http://localhost/cache/?uri=%s'
5 15:43:30.774614 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-ltp%2F20220826.0%2Famd64%2Finitrd.cpio.gz exists
6 15:43:31.067149 Using caching service: 'http://localhost/cache/?uri=%s'
7 15:43:31.067391 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv4.4-st20-229-gb433f12afe250%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 15:43:31.357693 Using caching service: 'http://localhost/cache/?uri=%s'
9 15:43:31.358425 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-ltp%2F20220826.0%2Famd64%2Ffull.rootfs.tar.xz exists
10 15:43:31.640163 Using caching service: 'http://localhost/cache/?uri=%s'
11 15:43:31.640879 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv4.4-st20-229-gb433f12afe250%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 15:43:31.933874 validate duration: 1.16
14 15:43:31.934231 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 15:43:31.934360 start: 1.1 download-retry (timeout 00:10:00) [common]
16 15:43:31.934488 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 15:43:31.934638 Not decompressing ramdisk as can be used compressed.
18 15:43:31.934738 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-ltp/20220826.0/amd64/initrd.cpio.gz
19 15:43:31.934858 saving as /var/lib/lava/dispatcher/tmp/7300442/tftp-deploy-ux950rm4/ramdisk/initrd.cpio.gz
20 15:43:31.934929 total size: 5411075 (5MB)
21 15:43:31.936194 progress 0% (0MB)
22 15:43:31.937876 progress 5% (0MB)
23 15:43:31.939367 progress 10% (0MB)
24 15:43:31.940925 progress 15% (0MB)
25 15:43:31.942643 progress 20% (1MB)
26 15:43:31.944174 progress 25% (1MB)
27 15:43:31.945718 progress 30% (1MB)
28 15:43:31.947243 progress 35% (1MB)
29 15:43:31.948934 progress 40% (2MB)
30 15:43:31.950456 progress 45% (2MB)
31 15:43:31.951968 progress 50% (2MB)
32 15:43:31.953495 progress 55% (2MB)
33 15:43:31.955183 progress 60% (3MB)
34 15:43:31.956698 progress 65% (3MB)
35 15:43:31.958220 progress 70% (3MB)
36 15:43:31.959745 progress 75% (3MB)
37 15:43:31.961500 progress 80% (4MB)
38 15:43:31.963025 progress 85% (4MB)
39 15:43:31.964554 progress 90% (4MB)
40 15:43:31.966104 progress 95% (4MB)
41 15:43:31.967699 progress 100% (5MB)
42 15:43:31.967882 5MB downloaded in 0.03s (156.63MB/s)
43 15:43:31.968043 end: 1.1.1 http-download (duration 00:00:00) [common]
45 15:43:31.968312 end: 1.1 download-retry (duration 00:00:00) [common]
46 15:43:31.968408 start: 1.2 download-retry (timeout 00:10:00) [common]
47 15:43:31.968503 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 15:43:31.968612 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v4.4-st20-229-gb433f12afe250/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
49 15:43:31.968686 saving as /var/lib/lava/dispatcher/tmp/7300442/tftp-deploy-ux950rm4/kernel/bzImage
50 15:43:31.968754 total size: 6815632 (6MB)
51 15:43:31.968820 No compression specified
52 15:43:33.471541 progress 0% (0MB)
53 15:43:33.476750 progress 5% (0MB)
54 15:43:33.478666 progress 10% (0MB)
55 15:43:33.480608 progress 15% (1MB)
56 15:43:33.482431 progress 20% (1MB)
57 15:43:33.484194 progress 25% (1MB)
58 15:43:33.486137 progress 30% (1MB)
59 15:43:33.487891 progress 35% (2MB)
60 15:43:33.489839 progress 40% (2MB)
61 15:43:33.491573 progress 45% (2MB)
62 15:43:33.493320 progress 50% (3MB)
63 15:43:33.495221 progress 55% (3MB)
64 15:43:33.496955 progress 60% (3MB)
65 15:43:33.498908 progress 65% (4MB)
66 15:43:33.500688 progress 70% (4MB)
67 15:43:33.502570 progress 75% (4MB)
68 15:43:33.504579 progress 80% (5MB)
69 15:43:33.506376 progress 85% (5MB)
70 15:43:33.508313 progress 90% (5MB)
71 15:43:33.510140 progress 95% (6MB)
72 15:43:33.511907 progress 100% (6MB)
73 15:43:33.512221 6MB downloaded in 1.54s (4.21MB/s)
74 15:43:33.512389 end: 1.2.1 http-download (duration 00:00:02) [common]
76 15:43:33.512651 end: 1.2 download-retry (duration 00:00:02) [common]
77 15:43:33.512750 start: 1.3 download-retry (timeout 00:09:58) [common]
78 15:43:33.512877 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 15:43:33.512995 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-ltp/20220826.0/amd64/full.rootfs.tar.xz
80 15:43:33.513080 saving as /var/lib/lava/dispatcher/tmp/7300442/tftp-deploy-ux950rm4/nfsrootfs/full.rootfs.tar
81 15:43:33.513187 total size: 122682368 (116MB)
82 15:43:33.513255 Using unxz to decompress xz
83 15:43:33.517004 progress 0% (0MB)
84 15:43:34.010154 progress 5% (5MB)
85 15:43:34.508320 progress 10% (11MB)
86 15:43:35.008521 progress 15% (17MB)
87 15:43:35.517730 progress 20% (23MB)
88 15:43:35.868036 progress 25% (29MB)
89 15:43:36.239416 progress 30% (35MB)
90 15:43:36.499171 progress 35% (40MB)
91 15:43:36.743920 progress 40% (46MB)
92 15:43:37.124672 progress 45% (52MB)
93 15:43:37.515516 progress 50% (58MB)
94 15:43:37.888820 progress 55% (64MB)
95 15:43:38.270936 progress 60% (70MB)
96 15:43:38.633563 progress 65% (76MB)
97 15:43:39.047030 progress 70% (81MB)
98 15:43:39.501351 progress 75% (87MB)
99 15:43:39.957086 progress 80% (93MB)
100 15:43:40.086727 progress 85% (99MB)
101 15:43:40.275175 progress 90% (105MB)
102 15:43:40.652295 progress 95% (111MB)
103 15:43:41.068046 progress 100% (116MB)
104 15:43:41.075568 116MB downloaded in 7.56s (15.47MB/s)
105 15:43:41.075948 end: 1.3.1 http-download (duration 00:00:08) [common]
107 15:43:41.076400 end: 1.3 download-retry (duration 00:00:08) [common]
108 15:43:41.076553 start: 1.4 download-retry (timeout 00:09:51) [common]
109 15:43:41.076701 start: 1.4.1 http-download (timeout 00:09:51) [common]
110 15:43:41.076883 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v4.4-st20-229-gb433f12afe250/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
111 15:43:41.077007 saving as /var/lib/lava/dispatcher/tmp/7300442/tftp-deploy-ux950rm4/modules/modules.tar
112 15:43:41.077125 total size: 51872 (0MB)
113 15:43:41.077238 Using unxz to decompress xz
114 15:43:41.081457 progress 63% (0MB)
115 15:43:41.082031 progress 100% (0MB)
116 15:43:41.085652 0MB downloaded in 0.01s (5.81MB/s)
117 15:43:41.085966 end: 1.4.1 http-download (duration 00:00:00) [common]
119 15:43:41.086403 end: 1.4 download-retry (duration 00:00:00) [common]
120 15:43:41.086558 start: 1.5 prepare-tftp-overlay (timeout 00:09:51) [common]
121 15:43:41.086721 start: 1.5.1 extract-nfsrootfs (timeout 00:09:51) [common]
122 15:43:42.973352 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/7300442/extract-nfsrootfs-bp4laq2o
123 15:43:42.973572 end: 1.5.1 extract-nfsrootfs (duration 00:00:02) [common]
124 15:43:42.973687 start: 1.5.2 lava-overlay (timeout 00:09:49) [common]
125 15:43:42.973837 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq
126 15:43:42.973951 makedir: /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin
127 15:43:42.974049 makedir: /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/tests
128 15:43:42.974142 makedir: /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/results
129 15:43:42.974249 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-add-keys
130 15:43:42.974401 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-add-sources
131 15:43:42.974534 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-background-process-start
132 15:43:42.974664 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-background-process-stop
133 15:43:42.974790 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-common-functions
134 15:43:42.974915 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-echo-ipv4
135 15:43:42.975040 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-install-packages
136 15:43:42.975163 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-installed-packages
137 15:43:42.975285 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-os-build
138 15:43:42.975411 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-probe-channel
139 15:43:42.975533 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-probe-ip
140 15:43:42.975655 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-target-ip
141 15:43:42.975777 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-target-mac
142 15:43:42.975900 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-target-storage
143 15:43:42.976024 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-test-case
144 15:43:42.976149 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-test-event
145 15:43:42.976270 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-test-feedback
146 15:43:42.976393 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-test-raise
147 15:43:42.976514 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-test-reference
148 15:43:42.976635 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-test-runner
149 15:43:42.976756 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-test-set
150 15:43:42.976877 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-test-shell
151 15:43:42.976999 Updating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-install-packages (oe)
152 15:43:42.977161 Updating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/bin/lava-installed-packages (oe)
153 15:43:42.977271 Creating /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/environment
154 15:43:42.977367 LAVA metadata
155 15:43:42.977441 - LAVA_JOB_ID=7300442
156 15:43:42.977513 - LAVA_DISPATCHER_IP=192.168.201.1
157 15:43:42.977622 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:49) [common]
158 15:43:42.977698 skipped lava-vland-overlay
159 15:43:42.977784 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
160 15:43:42.977877 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
161 15:43:42.977947 skipped lava-multinode-overlay
162 15:43:42.978031 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
163 15:43:42.978124 start: 1.5.2.3 test-definition (timeout 00:09:49) [common]
164 15:43:42.978204 Loading test definitions
165 15:43:42.978304 start: 1.5.2.3.1 git-repo-action (timeout 00:09:49) [common]
166 15:43:42.978386 Using /lava-7300442 at stage 0
167 15:43:42.978492 Fetching tests from https://github.com/kernelci/test-definitions
168 15:43:42.978581 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/0/tests/0_ltp-mm'
169 15:43:48.094838 Running '/usr/bin/git checkout kernelci.org
170 15:43:48.181111 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/0/tests/0_ltp-mm/automated/linux/ltp/ltp.yaml
171 15:43:48.181907 uuid=7300442_1.5.2.3.1 testdef=None
172 15:43:48.182092 end: 1.5.2.3.1 git-repo-action (duration 00:00:05) [common]
174 15:43:48.182377 start: 1.5.2.3.2 test-overlay (timeout 00:09:44) [common]
175 15:43:48.183378 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
177 15:43:48.183759 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:44) [common]
178 15:43:48.185231 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
180 15:43:48.185654 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:44) [common]
181 15:43:48.186702 runner path: /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/0/tests/0_ltp-mm test_uuid 7300442_1.5.2.3.1
182 15:43:48.186809 SKIPFILE='skipfile-lkft.yaml'
183 15:43:48.186888 SKIP_INSTALL='true'
184 15:43:48.186959 TST_CMDFILES='mm'
185 15:43:48.187117 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
187 15:43:48.187364 Creating lava-test-runner.conf files
188 15:43:48.187441 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/7300442/lava-overlay-h3kn5pfq/lava-7300442/0 for stage 0
189 15:43:48.187536 - 0_ltp-mm
190 15:43:48.187647 end: 1.5.2.3 test-definition (duration 00:00:05) [common]
191 15:43:48.187753 start: 1.5.2.4 compress-overlay (timeout 00:09:44) [common]
192 15:43:56.175208 end: 1.5.2.4 compress-overlay (duration 00:00:08) [common]
193 15:43:56.175391 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
194 15:43:56.175503 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
195 15:43:56.175620 end: 1.5.2 lava-overlay (duration 00:00:13) [common]
196 15:43:56.175725 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
197 15:43:56.288991 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
198 15:43:56.289369 start: 1.5.4 extract-modules (timeout 00:09:36) [common]
199 15:43:56.289493 extracting modules file /var/lib/lava/dispatcher/tmp/7300442/tftp-deploy-ux950rm4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/7300442/extract-nfsrootfs-bp4laq2o
200 15:43:56.293967 extracting modules file /var/lib/lava/dispatcher/tmp/7300442/tftp-deploy-ux950rm4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/7300442/extract-overlay-ramdisk-7v31a4ws/ramdisk
201 15:43:56.298020 end: 1.5.4 extract-modules (duration 00:00:00) [common]
202 15:43:56.298145 start: 1.5.5 apply-overlay-tftp (timeout 00:09:36) [common]
203 15:43:56.298239 [common] Applying overlay to NFS
204 15:43:56.298318 [common] Applying overlay /var/lib/lava/dispatcher/tmp/7300442/compress-overlay-phk13a_9/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/7300442/extract-nfsrootfs-bp4laq2o
205 15:43:56.786294 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
206 15:43:56.786482 start: 1.5.6 configure-preseed-file (timeout 00:09:35) [common]
207 15:43:56.786591 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
208 15:43:56.786693 start: 1.5.7 compress-ramdisk (timeout 00:09:35) [common]
209 15:43:56.786788 Building ramdisk /var/lib/lava/dispatcher/tmp/7300442/extract-overlay-ramdisk-7v31a4ws/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/7300442/extract-overlay-ramdisk-7v31a4ws/ramdisk
210 15:43:56.823701 >> 24431 blocks
211 15:43:57.344629 rename /var/lib/lava/dispatcher/tmp/7300442/extract-overlay-ramdisk-7v31a4ws/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/7300442/tftp-deploy-ux950rm4/ramdisk/ramdisk.cpio.gz
212 15:43:57.345112 end: 1.5.7 compress-ramdisk (duration 00:00:01) [common]
213 15:43:57.345266 start: 1.5.8 prepare-kernel (timeout 00:09:35) [common]
214 15:43:57.345395 start: 1.5.8.1 prepare-fit (timeout 00:09:35) [common]
215 15:43:57.345520 No mkimage arch provided, not using FIT.
216 15:43:57.345638 end: 1.5.8.1 prepare-fit (duration 00:00:00) [common]
217 15:43:57.345751 end: 1.5.8 prepare-kernel (duration 00:00:00) [common]
218 15:43:57.345882 end: 1.5 prepare-tftp-overlay (duration 00:00:16) [common]
219 15:43:57.346013 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
220 15:43:57.346114 No LXC device requested
221 15:43:57.346232 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
222 15:43:57.346353 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
223 15:43:57.346467 end: 1.7 deploy-device-env (duration 00:00:00) [common]
224 15:43:57.346563 Checking files for TFTP limit of 4294967296 bytes.
225 15:43:57.347038 end: 1 tftp-deploy (duration 00:00:25) [common]
226 15:43:57.347166 start: 2 depthcharge-action (timeout 00:05:00) [common]
227 15:43:57.347293 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
228 15:43:57.347449 substitutions:
229 15:43:57.347539 - {DTB}: None
230 15:43:57.347631 - {INITRD}: 7300442/tftp-deploy-ux950rm4/ramdisk/ramdisk.cpio.gz
231 15:43:57.347719 - {KERNEL}: 7300442/tftp-deploy-ux950rm4/kernel/bzImage
232 15:43:57.347804 - {LAVA_MAC}: None
233 15:43:57.347889 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/7300442/extract-nfsrootfs-bp4laq2o
234 15:43:57.347975 - {NFS_SERVER_IP}: 192.168.201.1
235 15:43:57.348058 - {PRESEED_CONFIG}: None
236 15:43:57.348141 - {PRESEED_LOCAL}: None
237 15:43:57.348224 - {RAMDISK}: 7300442/tftp-deploy-ux950rm4/ramdisk/ramdisk.cpio.gz
238 15:43:57.348305 - {ROOT_PART}: None
239 15:43:57.348386 - {ROOT}: None
240 15:43:57.348467 - {SERVER_IP}: 192.168.201.1
241 15:43:57.348548 - {TEE}: None
242 15:43:57.348628 Parsed boot commands:
243 15:43:57.348708 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
244 15:43:57.348905 Parsed boot commands: tftpboot 192.168.201.1 7300442/tftp-deploy-ux950rm4/kernel/bzImage 7300442/tftp-deploy-ux950rm4/kernel/cmdline 7300442/tftp-deploy-ux950rm4/ramdisk/ramdisk.cpio.gz
245 15:43:57.349026 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
246 15:43:57.349155 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
247 15:43:57.349278 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
248 15:43:57.349394 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
249 15:43:57.349486 Not connected, no need to disconnect.
250 15:43:57.349599 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
251 15:43:57.349710 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
252 15:43:57.349799 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost asus-C436FA-Flip-hatch-cbg-4'
253 15:43:57.352856 Setting prompt string to ['lava-test: # ']
254 15:43:57.353185 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
255 15:43:57.353314 end: 2.2.1 reset-connection (duration 00:00:00) [common]
256 15:43:57.353440 start: 2.2.2 reset-device (timeout 00:05:00) [common]
257 15:43:57.353559 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
258 15:43:57.353770 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-4' '--port=1' '--command=reboot'
259 15:43:57.374680 >> Command sent successfully.
260 15:43:57.376691 Returned 0 in 0 seconds
261 15:43:57.477234 end: 2.2.2.1 pdu-reboot (duration 00:00:00) [common]
263 15:43:57.477618 end: 2.2.2 reset-device (duration 00:00:00) [common]
264 15:43:57.477748 start: 2.2.3 depthcharge-start (timeout 00:05:00) [common]
265 15:43:57.477855 Setting prompt string to 'Starting depthcharge on Helios...'
266 15:43:57.477940 Changing prompt to 'Starting depthcharge on Helios...'
267 15:43:57.478041 depthcharge-start: Wait for prompt Starting depthcharge on Helios... (timeout 00:05:00)
268 15:43:57.478358 [Enter `^Ec?' for help]
269 15:44:04.637603
270 15:44:04.638134
271 15:44:04.647310 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
272 15:44:04.650556 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
273 15:44:04.656988 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
274 15:44:04.660535 CPU: AES supported, TXT NOT supported, VT supported
275 15:44:04.666980 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
276 15:44:04.670434 PCH: device id 0284 (rev 00) is Cometlake-U Premium
277 15:44:04.677079 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
278 15:44:04.680286 VBOOT: Loading verstage.
279 15:44:04.683297 FMAP: Found \"FLASH\" version 1.1 at 0xc04000.
280 15:44:04.690480 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
281 15:44:04.696880 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
282 15:44:04.697415 CBFS @ c08000 size 3f8000
283 15:44:04.703310 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
284 15:44:04.706931 CBFS: Locating 'fallback/verstage'
285 15:44:04.709976 CBFS: Found @ offset 10fb80 size 1072c
286 15:44:04.714276
287 15:44:04.714778
288 15:44:04.724112 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
289 15:44:04.738358 Probing TPM: . done!
290 15:44:04.741729 TPM ready after 0 ms
291 15:44:04.744877 Connected to device vid:did:rid of 1ae0:0028:00
292 15:44:04.754996 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.7/cr50_v1.9308_87_mp.514-29d5b602
293 15:44:04.758828 Initialized TPM device CR50 revision 0
294 15:44:04.804031 tlcl_send_startup: Startup return code is 0
295 15:44:04.804494 TPM: setup succeeded
296 15:44:04.818018 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
297 15:44:04.821595 Chrome EC: UHEPI supported
298 15:44:04.825218 Phase 1
299 15:44:04.828278 FMAP: area GBB found @ c05000 (12288 bytes)
300 15:44:04.834981 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
301 15:44:04.838087 Phase 2
302 15:44:04.838214 Phase 3
303 15:44:04.841724 FMAP: area GBB found @ c05000 (12288 bytes)
304 15:44:04.848040 VB2:vb2_report_dev_firmware() This is developer signed firmware
305 15:44:04.855360 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
306 15:44:04.858218 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
307 15:44:04.864636 VB2:vb2_verify_keyblock() Checking keyblock signature...
308 15:44:04.880472 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
309 15:44:04.883510 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
310 15:44:04.890696 VB2:vb2_verify_fw_preamble() Verifying preamble.
311 15:44:04.894641 Phase 4
312 15:44:04.898042 FMAP: area FW_MAIN_A found @ 410000 (3506112 bytes)
313 15:44:04.904285 VB2:vb2api_init_hash() HW crypto for hash_alg 2 not supported, using SW
314 15:44:05.084447 VB2:vb2_rsa_verify_digest() Digest check failed!
315 15:44:05.091041 VB2:vb2api_fail() Need recovery, reason: 0x1b / 0x7
316 15:44:05.091587 Saving nvdata
317 15:44:05.094471 Reboot requested (10020007)
318 15:44:05.097959 board_reset() called!
319 15:44:05.098394 full_reset() called!
320 15:44:09.604366
321 15:44:09.604905
322 15:44:09.614567 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
323 15:44:09.617891 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
324 15:44:09.624177 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
325 15:44:09.627605 CPU: AES supported, TXT NOT supported, VT supported
326 15:44:09.634560 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
327 15:44:09.637915 PCH: device id 0284 (rev 00) is Cometlake-U Premium
328 15:44:09.644674 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
329 15:44:09.647898 VBOOT: Loading verstage.
330 15:44:09.650793 FMAP: Found \"FLASH\" version 1.1 at 0xc04000.
331 15:44:09.657451 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
332 15:44:09.664588 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
333 15:44:09.665208 CBFS @ c08000 size 3f8000
334 15:44:09.670441 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
335 15:44:09.674091 CBFS: Locating 'fallback/verstage'
336 15:44:09.677208 CBFS: Found @ offset 10fb80 size 1072c
337 15:44:09.681610
338 15:44:09.682141
339 15:44:09.691343 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
340 15:44:09.705792 Probing TPM: . done!
341 15:44:09.709294 TPM ready after 0 ms
342 15:44:09.712650 Connected to device vid:did:rid of 1ae0:0028:00
343 15:44:09.723038 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.7/cr50_v1.9308_87_mp.514-29d5b602
344 15:44:09.726011 Initialized TPM device CR50 revision 0
345 15:44:09.772288 tlcl_send_startup: Startup return code is 0
346 15:44:09.772872 TPM: setup succeeded
347 15:44:09.784765 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
348 15:44:09.788813 Chrome EC: UHEPI supported
349 15:44:09.791904 Phase 1
350 15:44:09.794832 FMAP: area GBB found @ c05000 (12288 bytes)
351 15:44:09.801636 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
352 15:44:09.808719 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x0
353 15:44:09.811395 Recovery requested (1009000e)
354 15:44:09.817681 Saving nvdata
355 15:44:09.823704 tlcl_extend: response is 0
356 15:44:09.832489 tlcl_extend: response is 0
357 15:44:09.839467 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
358 15:44:09.842643 CBFS @ c08000 size 3f8000
359 15:44:09.849473 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
360 15:44:09.852742 CBFS: Locating 'fallback/romstage'
361 15:44:09.856256 CBFS: Found @ offset 80 size 145fc
362 15:44:09.859429 Accumulated console time in verstage 98 ms
363 15:44:09.860016
364 15:44:09.860402
365 15:44:09.872750 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 romstage starting (log level: 8)...
366 15:44:09.879196 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
367 15:44:09.882514 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
368 15:44:09.885942 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
369 15:44:09.892775 gpe0_sts[1]: 00200000 gpe0_en[1]: 00000000
370 15:44:09.895736 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
371 15:44:09.899126 gpe0_sts[3]: 00000000 gpe0_en[3]: 00010000
372 15:44:09.902384 TCO_STS: 0000 0000
373 15:44:09.905989 GEN_PMCON: e0015238 00000200
374 15:44:09.908990 GBLRST_CAUSE: 00000000 00000000
375 15:44:09.909454 prev_sleep_state 5
376 15:44:09.911941 Boot Count incremented to 28939
377 15:44:09.919104 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
378 15:44:09.922479 CBFS @ c08000 size 3f8000
379 15:44:09.928933 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
380 15:44:09.929523 CBFS: Locating 'fspm.bin'
381 15:44:09.935707 CBFS: Found @ offset 5ffc0 size 71000
382 15:44:09.938722 Chrome EC: UHEPI supported
383 15:44:09.945626 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
384 15:44:09.948867 Probing TPM: done!
385 15:44:09.956039 Connected to device vid:did:rid of 1ae0:0028:00
386 15:44:09.966026 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.7/cr50_v1.9308_87_mp.514-29d5b602
387 15:44:09.971904 Initialized TPM device CR50 revision 0
388 15:44:09.982050 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
389 15:44:09.988599 MRC: Hash comparison successful. Using data from RECOVERY_MRC_CACHE
390 15:44:09.991367 MRC cache found, size 1948
391 15:44:09.994869 bootmode is set to: 2
392 15:44:09.998303 PRMRR disabled by config.
393 15:44:10.001431 SPD INDEX = 1
394 15:44:10.004615 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
395 15:44:10.008188 CBFS @ c08000 size 3f8000
396 15:44:10.014472 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
397 15:44:10.015008 CBFS: Locating 'spd.bin'
398 15:44:10.017990 CBFS: Found @ offset 5fb80 size 400
399 15:44:10.021570 SPD: module type is LPDDR3
400 15:44:10.024913 SPD: module part is
401 15:44:10.031192 SPD: banks 16, ranks 2, rows 15, columns 11, density 8192 Mb
402 15:44:10.034859 SPD: device width 4 bits, bus width 8 bits
403 15:44:10.037765 SPD: module size is 4096 MB (per channel)
404 15:44:10.041401 memory slot: 0 configuration done.
405 15:44:10.044801 memory slot: 2 configuration done.
406 15:44:10.096248 CBMEM:
407 15:44:10.099482 IMD: root @ 99fff000 254 entries.
408 15:44:10.102931 IMD: root @ 99ffec00 62 entries.
409 15:44:10.105855 External stage cache:
410 15:44:10.109496 IMD: root @ 9abff000 254 entries.
411 15:44:10.112725 IMD: root @ 9abfec00 62 entries.
412 15:44:10.115919 Chrome EC: clear events_b mask to 0x0000000020004000
413 15:44:10.133049 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
414 15:44:10.148468 tlcl_write: response is 0
415 15:44:10.157912 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
416 15:44:10.164796 MRC: TPM MRC hash updated successfully.
417 15:44:10.165412 2 DIMMs found
418 15:44:10.167830 SMM Memory Map
419 15:44:10.170968 SMRAM : 0x9a000000 0x1000000
420 15:44:10.174101 Subregion 0: 0x9a000000 0xa00000
421 15:44:10.177651 Subregion 1: 0x9aa00000 0x200000
422 15:44:10.180953 Subregion 2: 0x9ac00000 0x400000
423 15:44:10.184530 top_of_ram = 0x9a000000
424 15:44:10.187346 MTRR Range: Start=99000000 End=9a000000 (Size 1000000)
425 15:44:10.193977 MTRR Range: Start=9a000000 End=9b000000 (Size 1000000)
426 15:44:10.197439 MTRR Range: Start=ff000000 End=0 (Size 1000000)
427 15:44:10.204152 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
428 15:44:10.207377 CBFS @ c08000 size 3f8000
429 15:44:10.210493 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
430 15:44:10.213951 CBFS: Locating 'fallback/postcar'
431 15:44:10.220688 CBFS: Found @ offset 107000 size 4b44
432 15:44:10.223945 Decompressing stage fallback/postcar @ 0x99c0bfc0 (35640 bytes)
433 15:44:10.236330 Loading module at 99c0c000 with entry 99c0c000. filesize: 0x4818 memsize: 0x8af8
434 15:44:10.239365 Processing 180 relocs. Offset value of 0x97c0c000
435 15:44:10.247706 Accumulated console time in romstage 286 ms
436 15:44:10.248291
437 15:44:10.248787
438 15:44:10.257825 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 postcar starting (log level: 8)...
439 15:44:10.264806 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
440 15:44:10.268038 CBFS @ c08000 size 3f8000
441 15:44:10.274248 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
442 15:44:10.277820 CBFS: Locating 'fallback/ramstage'
443 15:44:10.280803 CBFS: Found @ offset 43380 size 1b9e8
444 15:44:10.287342 Decompressing stage fallback/ramstage @ 0x99baffc0 (372088 bytes)
445 15:44:10.319693 Loading module at 99bb0000 with entry 99bb0000. filesize: 0x40940 memsize: 0x5ad38
446 15:44:10.322741 Processing 3976 relocs. Offset value of 0x98db0000
447 15:44:10.329761 Accumulated console time in postcar 52 ms
448 15:44:10.330249
449 15:44:10.330633
450 15:44:10.339763 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 ramstage starting (log level: 8)...
451 15:44:10.346620 FMAP: area RO_VPD found @ c00000 (16384 bytes)
452 15:44:10.349701 WARNING: RO_VPD is uninitialized or empty.
453 15:44:10.352855 FMAP: area RW_VPD found @ af8000 (8192 bytes)
454 15:44:10.359260 FMAP: area RW_VPD found @ af8000 (8192 bytes)
455 15:44:10.359836 Normal boot.
456 15:44:10.366048 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
457 15:44:10.369172 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
458 15:44:10.373206 CBFS @ c08000 size 3f8000
459 15:44:10.379831 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
460 15:44:10.382835 CBFS: Locating 'cpu_microcode_blob.bin'
461 15:44:10.386023 CBFS: Found @ offset 14700 size 2ec00
462 15:44:10.389678 microcode: sig=0x806ec pf=0x4 revision=0xc9
463 15:44:10.392368 Skip microcode update
464 15:44:10.398809 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
465 15:44:10.399270 CBFS @ c08000 size 3f8000
466 15:44:10.405583 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
467 15:44:10.409389 CBFS: Locating 'fsps.bin'
468 15:44:10.412440 CBFS: Found @ offset d1fc0 size 35000
469 15:44:10.437921 Detected 4 core, 8 thread CPU.
470 15:44:10.441152 Setting up SMI for CPU
471 15:44:10.444989 IED base = 0x9ac00000
472 15:44:10.445603 IED size = 0x00400000
473 15:44:10.447726 Will perform SMM setup.
474 15:44:10.454503 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz.
475 15:44:10.461309 Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170
476 15:44:10.464604 Processing 16 relocs. Offset value of 0x00030000
477 15:44:10.468196 Attempting to start 7 APs
478 15:44:10.470997 Waiting for 10ms after sending INIT.
479 15:44:10.487761 Waiting for 1st SIPI to complete...done.
480 15:44:10.488340 AP: slot 2 apic_id 1.
481 15:44:10.494294 Waiting for 2nd SIPI to complete...done.
482 15:44:10.494983 AP: slot 6 apic_id 6.
483 15:44:10.497250 AP: slot 7 apic_id 7.
484 15:44:10.500634 AP: slot 1 apic_id 2.
485 15:44:10.501146 AP: slot 5 apic_id 4.
486 15:44:10.504148 AP: slot 4 apic_id 5.
487 15:44:10.507395 AP: slot 3 apic_id 3.
488 15:44:10.514105 Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8
489 15:44:10.520714 Processing 13 relocs. Offset value of 0x00038000
490 15:44:10.524518 SMM Module: stub loaded at 00038000. Will call 99bcb71d(00000000)
491 15:44:10.531017 Installing SMM handler to 0x9a000000
492 15:44:10.537637 Loading module at 9a010000 with entry 9a010a52. filesize: 0x7e88 memsize: 0xcf58
493 15:44:10.543908 Processing 658 relocs. Offset value of 0x9a010000
494 15:44:10.550460 Loading module at 9a008000 with entry 9a008000. filesize: 0x1a8 memsize: 0x1a8
495 15:44:10.553865 Processing 13 relocs. Offset value of 0x9a008000
496 15:44:10.560727 SMM Module: placing jmp sequence at 9a007c00 rel16 0x03fd
497 15:44:10.567731 SMM Module: placing jmp sequence at 9a007800 rel16 0x07fd
498 15:44:10.570520 SMM Module: placing jmp sequence at 9a007400 rel16 0x0bfd
499 15:44:10.577614 SMM Module: placing jmp sequence at 9a007000 rel16 0x0ffd
500 15:44:10.583874 SMM Module: placing jmp sequence at 9a006c00 rel16 0x13fd
501 15:44:10.590571 SMM Module: placing jmp sequence at 9a006800 rel16 0x17fd
502 15:44:10.593683 SMM Module: placing jmp sequence at 9a006400 rel16 0x1bfd
503 15:44:10.600542 SMM Module: stub loaded at 9a008000. Will call 9a010a52(00000000)
504 15:44:10.603456 Clearing SMI status registers
505 15:44:10.607250 SMI_STS: PM1
506 15:44:10.607827 PM1_STS: PWRBTN
507 15:44:10.610143 TCO_STS: SECOND_TO
508 15:44:10.613814 New SMBASE 0x9a000000
509 15:44:10.617411 In relocation handler: CPU 0
510 15:44:10.620387 New SMBASE=0x9a000000 IEDBASE=0x9ac00000
511 15:44:10.624110 Writing SMRR. base = 0x9a000006, mask=0xff000800
512 15:44:10.627353 Relocation complete.
513 15:44:10.630620 New SMBASE 0x99fff800
514 15:44:10.631103 In relocation handler: CPU 2
515 15:44:10.637512 New SMBASE=0x99fff800 IEDBASE=0x9ac00000
516 15:44:10.640557 Writing SMRR. base = 0x9a000006, mask=0xff000800
517 15:44:10.643707 Relocation complete.
518 15:44:10.644191 New SMBASE 0x99fff400
519 15:44:10.647144 In relocation handler: CPU 3
520 15:44:10.653779 New SMBASE=0x99fff400 IEDBASE=0x9ac00000
521 15:44:10.656888 Writing SMRR. base = 0x9a000006, mask=0xff000800
522 15:44:10.660491 Relocation complete.
523 15:44:10.660982 New SMBASE 0x99fffc00
524 15:44:10.663905 In relocation handler: CPU 1
525 15:44:10.670385 New SMBASE=0x99fffc00 IEDBASE=0x9ac00000
526 15:44:10.673409 Writing SMRR. base = 0x9a000006, mask=0xff000800
527 15:44:10.677332 Relocation complete.
528 15:44:10.677863 New SMBASE 0x99ffe400
529 15:44:10.680487 In relocation handler: CPU 7
530 15:44:10.683563 New SMBASE=0x99ffe400 IEDBASE=0x9ac00000
531 15:44:10.690072 Writing SMRR. base = 0x9a000006, mask=0xff000800
532 15:44:10.693411 Relocation complete.
533 15:44:10.693889 New SMBASE 0x99ffe800
534 15:44:10.696483 In relocation handler: CPU 6
535 15:44:10.700197 New SMBASE=0x99ffe800 IEDBASE=0x9ac00000
536 15:44:10.707124 Writing SMRR. base = 0x9a000006, mask=0xff000800
537 15:44:10.710283 Relocation complete.
538 15:44:10.710859 New SMBASE 0x99fff000
539 15:44:10.713162 In relocation handler: CPU 4
540 15:44:10.716568 New SMBASE=0x99fff000 IEDBASE=0x9ac00000
541 15:44:10.723422 Writing SMRR. base = 0x9a000006, mask=0xff000800
542 15:44:10.724150 Relocation complete.
543 15:44:10.726523 New SMBASE 0x99ffec00
544 15:44:10.729910 In relocation handler: CPU 5
545 15:44:10.733587 New SMBASE=0x99ffec00 IEDBASE=0x9ac00000
546 15:44:10.740243 Writing SMRR. base = 0x9a000006, mask=0xff000800
547 15:44:10.740838 Relocation complete.
548 15:44:10.743616 Initializing CPU #0
549 15:44:10.746333 CPU: vendor Intel device 806ec
550 15:44:10.749751 CPU: family 06, model 8e, stepping 0c
551 15:44:10.753399 Clearing out pending MCEs
552 15:44:10.756677 Setting up local APIC...
553 15:44:10.757306 apic_id: 0x00 done.
554 15:44:10.759691 Turbo is available but hidden
555 15:44:10.763461 Turbo is available and visible
556 15:44:10.766419 VMX status: enabled
557 15:44:10.769969 IA32_FEATURE_CONTROL status: locked
558 15:44:10.772869 Skip microcode update
559 15:44:10.773385 CPU #0 initialized
560 15:44:10.776852 Initializing CPU #2
561 15:44:10.777430 Initializing CPU #1
562 15:44:10.779952 Initializing CPU #3
563 15:44:10.783146 CPU: vendor Intel device 806ec
564 15:44:10.786807 CPU: family 06, model 8e, stepping 0c
565 15:44:10.789844 CPU: vendor Intel device 806ec
566 15:44:10.792722 CPU: family 06, model 8e, stepping 0c
567 15:44:10.796665 Clearing out pending MCEs
568 15:44:10.800460 Clearing out pending MCEs
569 15:44:10.803224 Setting up local APIC...
570 15:44:10.803764 Initializing CPU #7
571 15:44:10.806402 Initializing CPU #6
572 15:44:10.809589 CPU: vendor Intel device 806ec
573 15:44:10.812616 CPU: family 06, model 8e, stepping 0c
574 15:44:10.816289 CPU: vendor Intel device 806ec
575 15:44:10.819386 CPU: family 06, model 8e, stepping 0c
576 15:44:10.823023 Clearing out pending MCEs
577 15:44:10.826061 Clearing out pending MCEs
578 15:44:10.826500 Setting up local APIC...
579 15:44:10.829799 Initializing CPU #4
580 15:44:10.832422 Initializing CPU #5
581 15:44:10.836057 CPU: vendor Intel device 806ec
582 15:44:10.839497 CPU: family 06, model 8e, stepping 0c
583 15:44:10.839932 Clearing out pending MCEs
584 15:44:10.842752 Setting up local APIC...
585 15:44:10.845981 apic_id: 0x02 done.
586 15:44:10.848887 Setting up local APIC...
587 15:44:10.849161 VMX status: enabled
588 15:44:10.852320 apic_id: 0x03 done.
589 15:44:10.855415 IA32_FEATURE_CONTROL status: locked
590 15:44:10.858997 VMX status: enabled
591 15:44:10.859137 Skip microcode update
592 15:44:10.862049 IA32_FEATURE_CONTROL status: locked
593 15:44:10.865608 CPU #1 initialized
594 15:44:10.869190 Skip microcode update
595 15:44:10.869311 Setting up local APIC...
596 15:44:10.872116 CPU #3 initialized
597 15:44:10.875215 apic_id: 0x06 done.
598 15:44:10.875322 apic_id: 0x07 done.
599 15:44:10.878881 VMX status: enabled
600 15:44:10.878999 VMX status: enabled
601 15:44:10.885520 IA32_FEATURE_CONTROL status: locked
602 15:44:10.885622 apic_id: 0x01 done.
603 15:44:10.888598 CPU: vendor Intel device 806ec
604 15:44:10.891760 CPU: family 06, model 8e, stepping 0c
605 15:44:10.895364 CPU: vendor Intel device 806ec
606 15:44:10.898515 CPU: family 06, model 8e, stepping 0c
607 15:44:10.901672 Clearing out pending MCEs
608 15:44:10.905329 Clearing out pending MCEs
609 15:44:10.908861 IA32_FEATURE_CONTROL status: locked
610 15:44:10.911860 Skip microcode update
611 15:44:10.911959 Skip microcode update
612 15:44:10.914973 CPU #6 initialized
613 15:44:10.918524 CPU #7 initialized
614 15:44:10.918630 Setting up local APIC...
615 15:44:10.921553 VMX status: enabled
616 15:44:10.925071 Setting up local APIC...
617 15:44:10.928194 IA32_FEATURE_CONTROL status: locked
618 15:44:10.928298 apic_id: 0x05 done.
619 15:44:10.931766 apic_id: 0x04 done.
620 15:44:10.934876 VMX status: enabled
621 15:44:10.934979 VMX status: enabled
622 15:44:10.938400 IA32_FEATURE_CONTROL status: locked
623 15:44:10.944919 IA32_FEATURE_CONTROL status: locked
624 15:44:10.945028 Skip microcode update
625 15:44:10.948660 Skip microcode update
626 15:44:10.948840 CPU #4 initialized
627 15:44:10.951902 CPU #5 initialized
628 15:44:10.954747 Skip microcode update
629 15:44:10.954844 CPU #2 initialized
630 15:44:10.961524 bsp_do_flight_plan done after 466 msecs.
631 15:44:10.964950 CPU: frequency set to 4200 MHz
632 15:44:10.965113 Enabling SMIs.
633 15:44:10.965219 Locking SMM.
634 15:44:10.981419 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
635 15:44:10.985003 CBFS @ c08000 size 3f8000
636 15:44:10.991223 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
637 15:44:10.991436 CBFS: Locating 'vbt.bin'
638 15:44:10.994728 CBFS: Found @ offset 5f5c0 size 499
639 15:44:11.001331 Found a VBT of 4608 bytes after decompression
640 15:44:11.185792 Display FSP Version Info HOB
641 15:44:11.189425 Reference Code - CPU = 9.0.1e.30
642 15:44:11.192556 uCode Version = 0.0.0.ca
643 15:44:11.195599 TXT ACM version = ff.ff.ff.ffff
644 15:44:11.199023 Display FSP Version Info HOB
645 15:44:11.202044 Reference Code - ME = 9.0.1e.30
646 15:44:11.205742 MEBx version = 0.0.0.0
647 15:44:11.208827 ME Firmware Version = Consumer SKU
648 15:44:11.212498 Display FSP Version Info HOB
649 15:44:11.215417 Reference Code - CML PCH = 9.0.1e.30
650 15:44:11.219024 PCH-CRID Status = Disabled
651 15:44:11.222100 PCH-CRID Original Value = ff.ff.ff.ffff
652 15:44:11.225770 PCH-CRID New Value = ff.ff.ff.ffff
653 15:44:11.228893 OPROM - RST - RAID = ff.ff.ff.ffff
654 15:44:11.231928 ChipsetInit Base Version = ff.ff.ff.ffff
655 15:44:11.235403 ChipsetInit Oem Version = ff.ff.ff.ffff
656 15:44:11.238851 Display FSP Version Info HOB
657 15:44:11.245476 Reference Code - SA - System Agent = 9.0.1e.30
658 15:44:11.248916 Reference Code - MRC = 0.7.1.6c
659 15:44:11.249477 SA - PCIe Version = 9.0.1e.30
660 15:44:11.251969 SA-CRID Status = Disabled
661 15:44:11.255406 SA-CRID Original Value = 0.0.0.c
662 15:44:11.258826 SA-CRID New Value = 0.0.0.c
663 15:44:11.261766 OPROM - VBIOS = ff.ff.ff.ffff
664 15:44:11.265649 RTC Init
665 15:44:11.268690 Set power on after power failure.
666 15:44:11.269259 Disabling Deep S3
667 15:44:11.272039 Disabling Deep S3
668 15:44:11.272472 Disabling Deep S4
669 15:44:11.275306 Disabling Deep S4
670 15:44:11.275841 Disabling Deep S5
671 15:44:11.278753 Disabling Deep S5
672 15:44:11.285500 BS: BS_DEV_INIT_CHIPS times (ms): entry 36 run 195 exit 1
673 15:44:11.286050 Enumerating buses...
674 15:44:11.291824 Show all devs... Before device enumeration.
675 15:44:11.292275 Root Device: enabled 1
676 15:44:11.294902 CPU_CLUSTER: 0: enabled 1
677 15:44:11.298525 DOMAIN: 0000: enabled 1
678 15:44:11.301528 APIC: 00: enabled 1
679 15:44:11.301964 PCI: 00:00.0: enabled 1
680 15:44:11.305175 PCI: 00:02.0: enabled 1
681 15:44:11.308538 PCI: 00:04.0: enabled 0
682 15:44:11.311653 PCI: 00:05.0: enabled 0
683 15:44:11.312189 PCI: 00:12.0: enabled 1
684 15:44:11.314865 PCI: 00:12.5: enabled 0
685 15:44:11.318676 PCI: 00:12.6: enabled 0
686 15:44:11.321522 PCI: 00:14.0: enabled 1
687 15:44:11.321984 PCI: 00:14.1: enabled 0
688 15:44:11.324863 PCI: 00:14.3: enabled 1
689 15:44:11.328179 PCI: 00:14.5: enabled 0
690 15:44:11.328671 PCI: 00:15.0: enabled 1
691 15:44:11.331268 PCI: 00:15.1: enabled 1
692 15:44:11.334932 PCI: 00:15.2: enabled 0
693 15:44:11.337862 PCI: 00:15.3: enabled 0
694 15:44:11.338296 PCI: 00:16.0: enabled 1
695 15:44:11.341455 PCI: 00:16.1: enabled 0
696 15:44:11.345140 PCI: 00:16.2: enabled 0
697 15:44:11.348184 PCI: 00:16.3: enabled 0
698 15:44:11.348733 PCI: 00:16.4: enabled 0
699 15:44:11.351732 PCI: 00:16.5: enabled 0
700 15:44:11.354844 PCI: 00:17.0: enabled 1
701 15:44:11.355373 PCI: 00:19.0: enabled 1
702 15:44:11.358221 PCI: 00:19.1: enabled 0
703 15:44:11.361588 PCI: 00:19.2: enabled 0
704 15:44:11.364526 PCI: 00:1a.0: enabled 0
705 15:44:11.364966 PCI: 00:1c.0: enabled 0
706 15:44:11.368078 PCI: 00:1c.1: enabled 0
707 15:44:11.371208 PCI: 00:1c.2: enabled 0
708 15:44:11.374659 PCI: 00:1c.3: enabled 0
709 15:44:11.375094 PCI: 00:1c.4: enabled 0
710 15:44:11.378121 PCI: 00:1c.5: enabled 0
711 15:44:11.381087 PCI: 00:1c.6: enabled 0
712 15:44:11.384553 PCI: 00:1c.7: enabled 0
713 15:44:11.384987 PCI: 00:1d.0: enabled 1
714 15:44:11.387690 PCI: 00:1d.1: enabled 0
715 15:44:11.391330 PCI: 00:1d.2: enabled 0
716 15:44:11.391765 PCI: 00:1d.3: enabled 0
717 15:44:11.394482 PCI: 00:1d.4: enabled 0
718 15:44:11.398040 PCI: 00:1d.5: enabled 1
719 15:44:11.401212 PCI: 00:1e.0: enabled 1
720 15:44:11.401647 PCI: 00:1e.1: enabled 0
721 15:44:11.404212 PCI: 00:1e.2: enabled 1
722 15:44:11.407995 PCI: 00:1e.3: enabled 1
723 15:44:11.411511 PCI: 00:1f.0: enabled 1
724 15:44:11.412161 PCI: 00:1f.1: enabled 1
725 15:44:11.414473 PCI: 00:1f.2: enabled 1
726 15:44:11.417662 PCI: 00:1f.3: enabled 1
727 15:44:11.421232 PCI: 00:1f.4: enabled 1
728 15:44:11.421697 PCI: 00:1f.5: enabled 1
729 15:44:11.424448 PCI: 00:1f.6: enabled 0
730 15:44:11.427795 USB0 port 0: enabled 1
731 15:44:11.428373 I2C: 00:15: enabled 1
732 15:44:11.431148 I2C: 00:5d: enabled 1
733 15:44:11.434236 GENERIC: 0.0: enabled 1
734 15:44:11.437504 I2C: 00:1a: enabled 1
735 15:44:11.438034 I2C: 00:38: enabled 1
736 15:44:11.440875 I2C: 00:39: enabled 1
737 15:44:11.444603 I2C: 00:3a: enabled 1
738 15:44:11.445167 I2C: 00:3b: enabled 1
739 15:44:11.447737 PCI: 00:00.0: enabled 1
740 15:44:11.450774 SPI: 00: enabled 1
741 15:44:11.451306 SPI: 01: enabled 1
742 15:44:11.454108 PNP: 0c09.0: enabled 1
743 15:44:11.457948 USB2 port 0: enabled 1
744 15:44:11.458497 USB2 port 1: enabled 1
745 15:44:11.460722 USB2 port 2: enabled 0
746 15:44:11.464383 USB2 port 3: enabled 0
747 15:44:11.464923 USB2 port 5: enabled 0
748 15:44:11.467666 USB2 port 6: enabled 1
749 15:44:11.470636 USB2 port 9: enabled 1
750 15:44:11.471068 USB3 port 0: enabled 1
751 15:44:11.473697 USB3 port 1: enabled 1
752 15:44:11.477421 USB3 port 2: enabled 1
753 15:44:11.480688 USB3 port 3: enabled 1
754 15:44:11.481146 USB3 port 4: enabled 0
755 15:44:11.483903 APIC: 02: enabled 1
756 15:44:11.487243 APIC: 01: enabled 1
757 15:44:11.487785 APIC: 03: enabled 1
758 15:44:11.490916 APIC: 05: enabled 1
759 15:44:11.491458 APIC: 04: enabled 1
760 15:44:11.493771 APIC: 06: enabled 1
761 15:44:11.497300 APIC: 07: enabled 1
762 15:44:11.497842 Compare with tree...
763 15:44:11.500635 Root Device: enabled 1
764 15:44:11.503758 CPU_CLUSTER: 0: enabled 1
765 15:44:11.504194 APIC: 00: enabled 1
766 15:44:11.506920 APIC: 02: enabled 1
767 15:44:11.510592 APIC: 01: enabled 1
768 15:44:11.513753 APIC: 03: enabled 1
769 15:44:11.514301 APIC: 05: enabled 1
770 15:44:11.516976 APIC: 04: enabled 1
771 15:44:11.520343 APIC: 06: enabled 1
772 15:44:11.520882 APIC: 07: enabled 1
773 15:44:11.523683 DOMAIN: 0000: enabled 1
774 15:44:11.527311 PCI: 00:00.0: enabled 1
775 15:44:11.530097 PCI: 00:02.0: enabled 1
776 15:44:11.530642 PCI: 00:04.0: enabled 0
777 15:44:11.533602 PCI: 00:05.0: enabled 0
778 15:44:11.536645 PCI: 00:12.0: enabled 1
779 15:44:11.540203 PCI: 00:12.5: enabled 0
780 15:44:11.543201 PCI: 00:12.6: enabled 0
781 15:44:11.543655 PCI: 00:14.0: enabled 1
782 15:44:11.546923 USB0 port 0: enabled 1
783 15:44:11.550533 USB2 port 0: enabled 1
784 15:44:11.553446 USB2 port 1: enabled 1
785 15:44:11.556708 USB2 port 2: enabled 0
786 15:44:11.557221 USB2 port 3: enabled 0
787 15:44:11.559716 USB2 port 5: enabled 0
788 15:44:11.563282 USB2 port 6: enabled 1
789 15:44:11.566724 USB2 port 9: enabled 1
790 15:44:11.570252 USB3 port 0: enabled 1
791 15:44:11.573381 USB3 port 1: enabled 1
792 15:44:11.573820 USB3 port 2: enabled 1
793 15:44:11.576589 USB3 port 3: enabled 1
794 15:44:11.580040 USB3 port 4: enabled 0
795 15:44:11.583285 PCI: 00:14.1: enabled 0
796 15:44:11.586531 PCI: 00:14.3: enabled 1
797 15:44:11.587115 PCI: 00:14.5: enabled 0
798 15:44:11.590169 PCI: 00:15.0: enabled 1
799 15:44:11.593093 I2C: 00:15: enabled 1
800 15:44:11.596211 PCI: 00:15.1: enabled 1
801 15:44:11.596821 I2C: 00:5d: enabled 1
802 15:44:11.599805 GENERIC: 0.0: enabled 1
803 15:44:11.603097 PCI: 00:15.2: enabled 0
804 15:44:11.606186 PCI: 00:15.3: enabled 0
805 15:44:11.609831 PCI: 00:16.0: enabled 1
806 15:44:11.610268 PCI: 00:16.1: enabled 0
807 15:44:11.613173 PCI: 00:16.2: enabled 0
808 15:44:11.616081 PCI: 00:16.3: enabled 0
809 15:44:11.619724 PCI: 00:16.4: enabled 0
810 15:44:11.623206 PCI: 00:16.5: enabled 0
811 15:44:11.623647 PCI: 00:17.0: enabled 1
812 15:44:11.626383 PCI: 00:19.0: enabled 1
813 15:44:11.629974 I2C: 00:1a: enabled 1
814 15:44:11.632772 I2C: 00:38: enabled 1
815 15:44:11.636449 I2C: 00:39: enabled 1
816 15:44:11.637010 I2C: 00:3a: enabled 1
817 15:44:11.639594 I2C: 00:3b: enabled 1
818 15:44:11.642947 PCI: 00:19.1: enabled 0
819 15:44:11.645886 PCI: 00:19.2: enabled 0
820 15:44:11.646328 PCI: 00:1a.0: enabled 0
821 15:44:11.649418 PCI: 00:1c.0: enabled 0
822 15:44:11.652793 PCI: 00:1c.1: enabled 0
823 15:44:11.656061 PCI: 00:1c.2: enabled 0
824 15:44:11.659713 PCI: 00:1c.3: enabled 0
825 15:44:11.660157 PCI: 00:1c.4: enabled 0
826 15:44:11.662902 PCI: 00:1c.5: enabled 0
827 15:44:11.665823 PCI: 00:1c.6: enabled 0
828 15:44:11.668994 PCI: 00:1c.7: enabled 0
829 15:44:11.672619 PCI: 00:1d.0: enabled 1
830 15:44:11.673056 PCI: 00:1d.1: enabled 0
831 15:44:11.676268 PCI: 00:1d.2: enabled 0
832 15:44:11.679209 PCI: 00:1d.3: enabled 0
833 15:44:11.682741 PCI: 00:1d.4: enabled 0
834 15:44:11.683261 PCI: 00:1d.5: enabled 1
835 15:44:11.686118 PCI: 00:00.0: enabled 1
836 15:44:11.689148 PCI: 00:1e.0: enabled 1
837 15:44:11.692636 PCI: 00:1e.1: enabled 0
838 15:44:11.695863 PCI: 00:1e.2: enabled 1
839 15:44:11.696377 SPI: 00: enabled 1
840 15:44:11.699448 PCI: 00:1e.3: enabled 1
841 15:44:11.702568 SPI: 01: enabled 1
842 15:44:11.705745 PCI: 00:1f.0: enabled 1
843 15:44:11.706174 PNP: 0c09.0: enabled 1
844 15:44:11.709465 PCI: 00:1f.1: enabled 1
845 15:44:11.712617 PCI: 00:1f.2: enabled 1
846 15:44:11.716038 PCI: 00:1f.3: enabled 1
847 15:44:11.719411 PCI: 00:1f.4: enabled 1
848 15:44:11.719949 PCI: 00:1f.5: enabled 1
849 15:44:11.722777 PCI: 00:1f.6: enabled 0
850 15:44:11.725910 Root Device scanning...
851 15:44:11.729402 scan_static_bus for Root Device
852 15:44:11.732344 CPU_CLUSTER: 0 enabled
853 15:44:11.732780 DOMAIN: 0000 enabled
854 15:44:11.735892 DOMAIN: 0000 scanning...
855 15:44:11.739004 PCI: pci_scan_bus for bus 00
856 15:44:11.742758 PCI: 00:00.0 [8086/0000] ops
857 15:44:11.745730 PCI: 00:00.0 [8086/9b61] enabled
858 15:44:11.748888 PCI: 00:02.0 [8086/0000] bus ops
859 15:44:11.752558 PCI: 00:02.0 [8086/9b41] enabled
860 15:44:11.755686 PCI: 00:04.0 [8086/1903] disabled
861 15:44:11.758850 PCI: 00:08.0 [8086/1911] enabled
862 15:44:11.762424 PCI: 00:12.0 [8086/02f9] enabled
863 15:44:11.765466 PCI: 00:14.0 [8086/0000] bus ops
864 15:44:11.768995 PCI: 00:14.0 [8086/02ed] enabled
865 15:44:11.772408 PCI: 00:14.2 [8086/02ef] enabled
866 15:44:11.775310 PCI: 00:14.3 [8086/02f0] enabled
867 15:44:11.778971 PCI: 00:15.0 [8086/0000] bus ops
868 15:44:11.782054 PCI: 00:15.0 [8086/02e8] enabled
869 15:44:11.785545 PCI: 00:15.1 [8086/0000] bus ops
870 15:44:11.788849 PCI: 00:15.1 [8086/02e9] enabled
871 15:44:11.791949 PCI: 00:16.0 [8086/0000] ops
872 15:44:11.795808 PCI: 00:16.0 [8086/02e0] enabled
873 15:44:11.798639 PCI: 00:17.0 [8086/0000] ops
874 15:44:11.802368 PCI: 00:17.0 [8086/02d3] enabled
875 15:44:11.805427 PCI: 00:19.0 [8086/0000] bus ops
876 15:44:11.808537 PCI: 00:19.0 [8086/02c5] enabled
877 15:44:11.812191 PCI: 00:1d.0 [8086/0000] bus ops
878 15:44:11.815138 PCI: 00:1d.0 [8086/02b0] enabled
879 15:44:11.821806 PCI: Static device PCI: 00:1d.5 not found, disabling it.
880 15:44:11.822252 PCI: 00:1e.0 [8086/0000] ops
881 15:44:11.825475 PCI: 00:1e.0 [8086/02a8] enabled
882 15:44:11.828597 PCI: 00:1e.2 [8086/0000] bus ops
883 15:44:11.832084 PCI: 00:1e.2 [8086/02aa] enabled
884 15:44:11.835335 PCI: 00:1e.3 [8086/0000] bus ops
885 15:44:11.838581 PCI: 00:1e.3 [8086/02ab] enabled
886 15:44:11.841923 PCI: 00:1f.0 [8086/0000] bus ops
887 15:44:11.845373 PCI: 00:1f.0 [8086/0284] enabled
888 15:44:11.852050 PCI: Static device PCI: 00:1f.1 not found, disabling it.
889 15:44:11.858347 PCI: Static device PCI: 00:1f.2 not found, disabling it.
890 15:44:11.861853 PCI: 00:1f.3 [8086/0000] bus ops
891 15:44:11.864976 PCI: 00:1f.3 [8086/02c8] enabled
892 15:44:11.868229 PCI: 00:1f.4 [8086/0000] bus ops
893 15:44:11.871915 PCI: 00:1f.4 [8086/02a3] enabled
894 15:44:11.875075 PCI: 00:1f.5 [8086/0000] bus ops
895 15:44:11.878732 PCI: 00:1f.5 [8086/02a4] enabled
896 15:44:11.881702 PCI: Leftover static devices:
897 15:44:11.882193 PCI: 00:05.0
898 15:44:11.885218 PCI: 00:12.5
899 15:44:11.885663 PCI: 00:12.6
900 15:44:11.886003 PCI: 00:14.1
901 15:44:11.888312 PCI: 00:14.5
902 15:44:11.888768 PCI: 00:15.2
903 15:44:11.891816 PCI: 00:15.3
904 15:44:11.892242 PCI: 00:16.1
905 15:44:11.892583 PCI: 00:16.2
906 15:44:11.894877 PCI: 00:16.3
907 15:44:11.895331 PCI: 00:16.4
908 15:44:11.898498 PCI: 00:16.5
909 15:44:11.898930 PCI: 00:19.1
910 15:44:11.899273 PCI: 00:19.2
911 15:44:11.901546 PCI: 00:1a.0
912 15:44:11.901980 PCI: 00:1c.0
913 15:44:11.904679 PCI: 00:1c.1
914 15:44:11.905137 PCI: 00:1c.2
915 15:44:11.908364 PCI: 00:1c.3
916 15:44:11.908815 PCI: 00:1c.4
917 15:44:11.909192 PCI: 00:1c.5
918 15:44:11.911664 PCI: 00:1c.6
919 15:44:11.912174 PCI: 00:1c.7
920 15:44:11.915248 PCI: 00:1d.1
921 15:44:11.915756 PCI: 00:1d.2
922 15:44:11.916097 PCI: 00:1d.3
923 15:44:11.918244 PCI: 00:1d.4
924 15:44:11.918678 PCI: 00:1d.5
925 15:44:11.921372 PCI: 00:1e.1
926 15:44:11.921805 PCI: 00:1f.1
927 15:44:11.922147 PCI: 00:1f.2
928 15:44:11.924868 PCI: 00:1f.6
929 15:44:11.928117 PCI: Check your devicetree.cb.
930 15:44:11.931825 PCI: 00:02.0 scanning...
931 15:44:11.934511 scan_generic_bus for PCI: 00:02.0
932 15:44:11.938121 scan_generic_bus for PCI: 00:02.0 done
933 15:44:11.944884 scan_bus: scanning of bus PCI: 00:02.0 took 10189 usecs
934 15:44:11.945447 PCI: 00:14.0 scanning...
935 15:44:11.948600 scan_static_bus for PCI: 00:14.0
936 15:44:11.951805 USB0 port 0 enabled
937 15:44:11.954728 USB0 port 0 scanning...
938 15:44:11.958336 scan_static_bus for USB0 port 0
939 15:44:11.958773 USB2 port 0 enabled
940 15:44:11.961600 USB2 port 1 enabled
941 15:44:11.964870 USB2 port 2 disabled
942 15:44:11.965369 USB2 port 3 disabled
943 15:44:11.968134 USB2 port 5 disabled
944 15:44:11.971591 USB2 port 6 enabled
945 15:44:11.972091 USB2 port 9 enabled
946 15:44:11.974546 USB3 port 0 enabled
947 15:44:11.974998 USB3 port 1 enabled
948 15:44:11.978272 USB3 port 2 enabled
949 15:44:11.981281 USB3 port 3 enabled
950 15:44:11.981881 USB3 port 4 disabled
951 15:44:11.984620 USB2 port 0 scanning...
952 15:44:11.988219 scan_static_bus for USB2 port 0
953 15:44:11.991154 scan_static_bus for USB2 port 0 done
954 15:44:11.997901 scan_bus: scanning of bus USB2 port 0 took 9693 usecs
955 15:44:12.001415 USB2 port 1 scanning...
956 15:44:12.004406 scan_static_bus for USB2 port 1
957 15:44:12.008198 scan_static_bus for USB2 port 1 done
958 15:44:12.010986 scan_bus: scanning of bus USB2 port 1 took 9696 usecs
959 15:44:12.014380 USB2 port 6 scanning...
960 15:44:12.017740 scan_static_bus for USB2 port 6
961 15:44:12.020821 scan_static_bus for USB2 port 6 done
962 15:44:12.027763 scan_bus: scanning of bus USB2 port 6 took 9704 usecs
963 15:44:12.031015 USB2 port 9 scanning...
964 15:44:12.034227 scan_static_bus for USB2 port 9
965 15:44:12.037264 scan_static_bus for USB2 port 9 done
966 15:44:12.041249 scan_bus: scanning of bus USB2 port 9 took 9700 usecs
967 15:44:12.044420 USB3 port 0 scanning...
968 15:44:12.047830 scan_static_bus for USB3 port 0
969 15:44:12.050657 scan_static_bus for USB3 port 0 done
970 15:44:12.057302 scan_bus: scanning of bus USB3 port 0 took 9696 usecs
971 15:44:12.060685 USB3 port 1 scanning...
972 15:44:12.064100 scan_static_bus for USB3 port 1
973 15:44:12.067163 scan_static_bus for USB3 port 1 done
974 15:44:12.070759 scan_bus: scanning of bus USB3 port 1 took 9686 usecs
975 15:44:12.073788 USB3 port 2 scanning...
976 15:44:12.077461 scan_static_bus for USB3 port 2
977 15:44:12.080611 scan_static_bus for USB3 port 2 done
978 15:44:12.087530 scan_bus: scanning of bus USB3 port 2 took 9694 usecs
979 15:44:12.090289 USB3 port 3 scanning...
980 15:44:12.093669 scan_static_bus for USB3 port 3
981 15:44:12.096917 scan_static_bus for USB3 port 3 done
982 15:44:12.103707 scan_bus: scanning of bus USB3 port 3 took 9695 usecs
983 15:44:12.106745 scan_static_bus for USB0 port 0 done
984 15:44:12.110666 scan_bus: scanning of bus USB0 port 0 took 155260 usecs
985 15:44:12.113629 scan_static_bus for PCI: 00:14.0 done
986 15:44:12.120606 scan_bus: scanning of bus PCI: 00:14.0 took 172881 usecs
987 15:44:12.123299 PCI: 00:15.0 scanning...
988 15:44:12.127130 scan_generic_bus for PCI: 00:15.0
989 15:44:12.129962 bus: PCI: 00:15.0[0]->I2C: 01:15 enabled
990 15:44:12.133885 scan_generic_bus for PCI: 00:15.0 done
991 15:44:12.140116 scan_bus: scanning of bus PCI: 00:15.0 took 14285 usecs
992 15:44:12.143658 PCI: 00:15.1 scanning...
993 15:44:12.146738 scan_generic_bus for PCI: 00:15.1
994 15:44:12.149913 bus: PCI: 00:15.1[0]->I2C: 02:5d enabled
995 15:44:12.156385 bus: PCI: 00:15.1[0]->GENERIC: 0.0 enabled
996 15:44:12.159570 scan_generic_bus for PCI: 00:15.1 done
997 15:44:12.162892 scan_bus: scanning of bus PCI: 00:15.1 took 18603 usecs
998 15:44:12.166443 PCI: 00:19.0 scanning...
999 15:44:12.170205 scan_generic_bus for PCI: 00:19.0
1000 15:44:12.176230 bus: PCI: 00:19.0[0]->I2C: 03:1a enabled
1001 15:44:12.179970 bus: PCI: 00:19.0[0]->I2C: 03:38 enabled
1002 15:44:12.183351 bus: PCI: 00:19.0[0]->I2C: 03:39 enabled
1003 15:44:12.186487 bus: PCI: 00:19.0[0]->I2C: 03:3a enabled
1004 15:44:12.190020 bus: PCI: 00:19.0[0]->I2C: 03:3b enabled
1005 15:44:12.196665 scan_generic_bus for PCI: 00:19.0 done
1006 15:44:12.200281 scan_bus: scanning of bus PCI: 00:19.0 took 30722 usecs
1007 15:44:12.202976 PCI: 00:1d.0 scanning...
1008 15:44:12.206108 do_pci_scan_bridge for PCI: 00:1d.0
1009 15:44:12.210024 PCI: pci_scan_bus for bus 01
1010 15:44:12.212840 PCI: 01:00.0 [1c5c/1327] enabled
1011 15:44:12.215944 Enabling Common Clock Configuration
1012 15:44:12.222829 L1 Sub-State supported from root port 29
1013 15:44:12.223321 L1 Sub-State Support = 0xf
1014 15:44:12.226143 CommonModeRestoreTime = 0x28
1015 15:44:12.232568 Power On Value = 0x16, Power On Scale = 0x0
1016 15:44:12.233011 ASPM: Enabled L1
1017 15:44:12.239108 scan_bus: scanning of bus PCI: 00:1d.0 took 32770 usecs
1018 15:44:12.242959 PCI: 00:1e.2 scanning...
1019 15:44:12.245709 scan_generic_bus for PCI: 00:1e.2
1020 15:44:12.249314 bus: PCI: 00:1e.2[0]->SPI: 00 enabled
1021 15:44:12.252926 scan_generic_bus for PCI: 00:1e.2 done
1022 15:44:12.259172 scan_bus: scanning of bus PCI: 00:1e.2 took 14002 usecs
1023 15:44:12.259615 PCI: 00:1e.3 scanning...
1024 15:44:12.266163 scan_generic_bus for PCI: 00:1e.3
1025 15:44:12.269620 bus: PCI: 00:1e.3[0]->SPI: 01 enabled
1026 15:44:12.272765 scan_generic_bus for PCI: 00:1e.3 done
1027 15:44:12.279318 scan_bus: scanning of bus PCI: 00:1e.3 took 14006 usecs
1028 15:44:12.279854 PCI: 00:1f.0 scanning...
1029 15:44:12.282535 scan_static_bus for PCI: 00:1f.0
1030 15:44:12.286300 PNP: 0c09.0 enabled
1031 15:44:12.289511 scan_static_bus for PCI: 00:1f.0 done
1032 15:44:12.295795 scan_bus: scanning of bus PCI: 00:1f.0 took 12035 usecs
1033 15:44:12.299192 PCI: 00:1f.3 scanning...
1034 15:44:12.302651 scan_bus: scanning of bus PCI: 00:1f.3 took 2851 usecs
1035 15:44:12.305727 PCI: 00:1f.4 scanning...
1036 15:44:12.309388 scan_generic_bus for PCI: 00:1f.4
1037 15:44:12.312537 scan_generic_bus for PCI: 00:1f.4 done
1038 15:44:12.319332 scan_bus: scanning of bus PCI: 00:1f.4 took 10181 usecs
1039 15:44:12.322496 PCI: 00:1f.5 scanning...
1040 15:44:12.325495 scan_generic_bus for PCI: 00:1f.5
1041 15:44:12.329406 scan_generic_bus for PCI: 00:1f.5 done
1042 15:44:12.335744 scan_bus: scanning of bus PCI: 00:1f.5 took 10190 usecs
1043 15:44:12.338907 scan_bus: scanning of bus DOMAIN: 0000 took 604701 usecs
1044 15:44:12.345669 scan_static_bus for Root Device done
1045 15:44:12.348775 scan_bus: scanning of bus Root Device took 624610 usecs
1046 15:44:12.352596 done
1047 15:44:12.353166 Chrome EC: UHEPI supported
1048 15:44:12.358843 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
1049 15:44:12.365634 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
1050 15:44:12.372270 SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
1051 15:44:12.379019 FMAP: area UNIFIED_MRC_CACHE found @ ad0000 (131072 bytes)
1052 15:44:12.381974 SPI flash protection: WPSW=0 SRP0=0
1053 15:44:12.388983 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1054 15:44:12.392192 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 10 exit 2
1055 15:44:12.395240 found VGA at PCI: 00:02.0
1056 15:44:12.398735 Setting up VGA for PCI: 00:02.0
1057 15:44:12.402322 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1058 15:44:12.408733 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1059 15:44:12.411786 Allocating resources...
1060 15:44:12.412239 Reading resources...
1061 15:44:12.418890 Root Device read_resources bus 0 link: 0
1062 15:44:12.422048 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1063 15:44:12.428682 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1064 15:44:12.431926 DOMAIN: 0000 read_resources bus 0 link: 0
1065 15:44:12.438262 PCI: 00:14.0 read_resources bus 0 link: 0
1066 15:44:12.441906 USB0 port 0 read_resources bus 0 link: 0
1067 15:44:12.449562 USB0 port 0 read_resources bus 0 link: 0 done
1068 15:44:12.453107 PCI: 00:14.0 read_resources bus 0 link: 0 done
1069 15:44:12.460199 PCI: 00:15.0 read_resources bus 1 link: 0
1070 15:44:12.463461 PCI: 00:15.0 read_resources bus 1 link: 0 done
1071 15:44:12.470337 PCI: 00:15.1 read_resources bus 2 link: 0
1072 15:44:12.473654 PCI: 00:15.1 read_resources bus 2 link: 0 done
1073 15:44:12.480860 PCI: 00:19.0 read_resources bus 3 link: 0
1074 15:44:12.487926 PCI: 00:19.0 read_resources bus 3 link: 0 done
1075 15:44:12.491104 PCI: 00:1d.0 read_resources bus 1 link: 0
1076 15:44:12.497521 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1077 15:44:12.501116 PCI: 00:1e.2 read_resources bus 4 link: 0
1078 15:44:12.507439 PCI: 00:1e.2 read_resources bus 4 link: 0 done
1079 15:44:12.510906 PCI: 00:1e.3 read_resources bus 5 link: 0
1080 15:44:12.517731 PCI: 00:1e.3 read_resources bus 5 link: 0 done
1081 15:44:12.520824 PCI: 00:1f.0 read_resources bus 0 link: 0
1082 15:44:12.527627 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1083 15:44:12.534235 DOMAIN: 0000 read_resources bus 0 link: 0 done
1084 15:44:12.537732 Root Device read_resources bus 0 link: 0 done
1085 15:44:12.541230 Done reading resources.
1086 15:44:12.544120 Show resources in subtree (Root Device)...After reading.
1087 15:44:12.550828 Root Device child on link 0 CPU_CLUSTER: 0
1088 15:44:12.553991 CPU_CLUSTER: 0 child on link 0 APIC: 00
1089 15:44:12.554564 APIC: 00
1090 15:44:12.557396 APIC: 02
1091 15:44:12.557958 APIC: 01
1092 15:44:12.560365 APIC: 03
1093 15:44:12.560885 APIC: 05
1094 15:44:12.561293 APIC: 04
1095 15:44:12.563982 APIC: 06
1096 15:44:12.564420 APIC: 07
1097 15:44:12.567092 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1098 15:44:12.577310 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1099 15:44:12.627648 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
1100 15:44:12.628224 PCI: 00:00.0
1101 15:44:12.629205 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1102 15:44:12.629617 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1103 15:44:12.629978 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1104 15:44:12.630679 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1105 15:44:12.676954 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1106 15:44:12.677618 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1107 15:44:12.678512 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1108 15:44:12.678879 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1109 15:44:12.679202 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1110 15:44:12.699589 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1111 15:44:12.700166 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1112 15:44:12.703252 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1113 15:44:12.709546 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1114 15:44:12.719621 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1115 15:44:12.729544 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1116 15:44:12.739838 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1117 15:44:12.740426 PCI: 00:02.0
1118 15:44:12.752988 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1119 15:44:12.762392 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1120 15:44:12.768998 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1121 15:44:12.772735 PCI: 00:04.0
1122 15:44:12.773379 PCI: 00:08.0
1123 15:44:12.782536 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1124 15:44:12.785804 PCI: 00:12.0
1125 15:44:12.795375 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1126 15:44:12.798884 PCI: 00:14.0 child on link 0 USB0 port 0
1127 15:44:12.808521 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1128 15:44:12.812029 USB0 port 0 child on link 0 USB2 port 0
1129 15:44:12.815343 USB2 port 0
1130 15:44:12.815888 USB2 port 1
1131 15:44:12.818510 USB2 port 2
1132 15:44:12.822206 USB2 port 3
1133 15:44:12.822645 USB2 port 5
1134 15:44:12.825531 USB2 port 6
1135 15:44:12.825973 USB2 port 9
1136 15:44:12.828617 USB3 port 0
1137 15:44:12.829059 USB3 port 1
1138 15:44:12.831714 USB3 port 2
1139 15:44:12.832151 USB3 port 3
1140 15:44:12.835334 USB3 port 4
1141 15:44:12.835775 PCI: 00:14.2
1142 15:44:12.845020 PCI: 00:14.2 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
1143 15:44:12.855027 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1144 15:44:12.858589 PCI: 00:14.3
1145 15:44:12.868340 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1146 15:44:12.871823 PCI: 00:15.0 child on link 0 I2C: 01:15
1147 15:44:12.881705 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1148 15:44:12.884675 I2C: 01:15
1149 15:44:12.888256 PCI: 00:15.1 child on link 0 I2C: 02:5d
1150 15:44:12.898143 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1151 15:44:12.898735 I2C: 02:5d
1152 15:44:12.901577 GENERIC: 0.0
1153 15:44:12.902165 PCI: 00:16.0
1154 15:44:12.911155 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1155 15:44:12.914600 PCI: 00:17.0
1156 15:44:12.924306 PCI: 00:17.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10
1157 15:44:12.930954 PCI: 00:17.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 14
1158 15:44:12.940667 PCI: 00:17.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
1159 15:44:12.947400 PCI: 00:17.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
1160 15:44:12.957641 PCI: 00:17.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
1161 15:44:12.967076 PCI: 00:17.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
1162 15:44:12.970597 PCI: 00:19.0 child on link 0 I2C: 03:1a
1163 15:44:12.980314 PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1164 15:44:12.980437 I2C: 03:1a
1165 15:44:12.983863 I2C: 03:38
1166 15:44:12.983965 I2C: 03:39
1167 15:44:12.986948 I2C: 03:3a
1168 15:44:12.987044 I2C: 03:3b
1169 15:44:12.993458 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1170 15:44:13.000564 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1171 15:44:13.010358 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1172 15:44:13.020220 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1173 15:44:13.020331 PCI: 01:00.0
1174 15:44:13.030416 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1175 15:44:13.033591 PCI: 00:1e.0
1176 15:44:13.043485 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1177 15:44:13.053490 PCI: 00:1e.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1178 15:44:13.056874 PCI: 00:1e.2 child on link 0 SPI: 00
1179 15:44:13.067014 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1180 15:44:13.070058 SPI: 00
1181 15:44:13.073649 PCI: 00:1e.3 child on link 0 SPI: 01
1182 15:44:13.083394 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1183 15:44:13.083598 SPI: 01
1184 15:44:13.090042 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1185 15:44:13.096940 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1186 15:44:13.106624 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1187 15:44:13.107216 PNP: 0c09.0
1188 15:44:13.116763 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1189 15:44:13.119743 PCI: 00:1f.3
1190 15:44:13.129982 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1191 15:44:13.139933 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1192 15:44:13.140476 PCI: 00:1f.4
1193 15:44:13.149784 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1194 15:44:13.159692 PCI: 00:1f.4 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
1195 15:44:13.160235 PCI: 00:1f.5
1196 15:44:13.169809 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1197 15:44:13.176055 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1198 15:44:13.182686 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
1199 15:44:13.189228 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
1200 15:44:13.192709 PCI: 00:02.0 20 * [0x0 - 0x3f] io
1201 15:44:13.195836 PCI: 00:17.0 20 * [0x40 - 0x5f] io
1202 15:44:13.199413 PCI: 00:17.0 18 * [0x60 - 0x67] io
1203 15:44:13.202468 PCI: 00:17.0 1c * [0x68 - 0x6b] io
1204 15:44:13.209036 DOMAIN: 0000 io: base: 6c size: 6c align: 6 gran: 0 limit: ffff done
1205 15:44:13.215677 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
1206 15:44:13.225693 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1207 15:44:13.232244 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1208 15:44:13.238991 PCI: 00:1d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
1209 15:44:13.245893 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1210 15:44:13.251992 PCI: 00:1d.0 mem: base: 4000 size: 100000 align: 20 gran: 20 limit: ffffffff done
1211 15:44:13.255555 PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
1212 15:44:13.261933 PCI: 00:02.0 10 * [0x10000000 - 0x10ffffff] mem
1213 15:44:13.265644 PCI: 00:1d.0 20 * [0x11000000 - 0x110fffff] mem
1214 15:44:13.272154 PCI: 00:1f.3 20 * [0x11100000 - 0x111fffff] mem
1215 15:44:13.275375 PCI: 00:14.0 10 * [0x11200000 - 0x1120ffff] mem
1216 15:44:13.282172 PCI: 00:14.3 10 * [0x11210000 - 0x11213fff] mem
1217 15:44:13.285231 PCI: 00:1f.3 10 * [0x11214000 - 0x11217fff] mem
1218 15:44:13.291888 PCI: 00:14.2 10 * [0x11218000 - 0x11219fff] mem
1219 15:44:13.294927 PCI: 00:17.0 10 * [0x1121a000 - 0x1121bfff] mem
1220 15:44:13.301660 PCI: 00:08.0 10 * [0x1121c000 - 0x1121cfff] mem
1221 15:44:13.305257 PCI: 00:12.0 10 * [0x1121d000 - 0x1121dfff] mem
1222 15:44:13.311630 PCI: 00:14.2 18 * [0x1121e000 - 0x1121efff] mem
1223 15:44:13.315322 PCI: 00:15.0 10 * [0x1121f000 - 0x1121ffff] mem
1224 15:44:13.318507 PCI: 00:15.1 10 * [0x11220000 - 0x11220fff] mem
1225 15:44:13.325125 PCI: 00:16.0 10 * [0x11221000 - 0x11221fff] mem
1226 15:44:13.328118 PCI: 00:19.0 10 * [0x11222000 - 0x11222fff] mem
1227 15:44:13.334775 PCI: 00:1e.0 18 * [0x11223000 - 0x11223fff] mem
1228 15:44:13.338610 PCI: 00:1e.2 10 * [0x11224000 - 0x11224fff] mem
1229 15:44:13.344655 PCI: 00:1e.3 10 * [0x11225000 - 0x11225fff] mem
1230 15:44:13.348337 PCI: 00:1f.5 10 * [0x11226000 - 0x11226fff] mem
1231 15:44:13.354882 PCI: 00:17.0 24 * [0x11227000 - 0x112277ff] mem
1232 15:44:13.358064 PCI: 00:17.0 14 * [0x11228000 - 0x112280ff] mem
1233 15:44:13.365016 PCI: 00:1f.4 10 * [0x11229000 - 0x112290ff] mem
1234 15:44:13.371480 DOMAIN: 0000 mem: base: 11229100 size: 11229100 align: 28 gran: 0 limit: ffffffff done
1235 15:44:13.374588 avoid_fixed_resources: DOMAIN: 0000
1236 15:44:13.381321 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
1237 15:44:13.387893 avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
1238 15:44:13.394537 constrain_resources: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)
1239 15:44:13.404501 constrain_resources: PCI: 00:00.0 09 base 00000000 limit 0009ffff mem (fixed)
1240 15:44:13.411190 constrain_resources: PCI: 00:00.0 0a base 000c0000 limit 99ffffff mem (fixed)
1241 15:44:13.417616 constrain_resources: PCI: 00:00.0 0b base 9a000000 limit 9affffff mem (fixed)
1242 15:44:13.427678 constrain_resources: PCI: 00:00.0 0c base 9b000000 limit 9f7fffff mem (fixed)
1243 15:44:13.434373 constrain_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1244 15:44:13.441211 constrain_resources: PCI: 00:1f.0 20 base 00001800 limit 000018ff io (fixed)
1245 15:44:13.447437 constrain_resources: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
1246 15:44:13.457432 avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001900 limit 0000ef9f
1247 15:44:13.463791 avoid_fixed_resources:@DOMAIN: 0000 10000100 base c0000000 limit dfffffff
1248 15:44:13.464245 Setting resources...
1249 15:44:13.470879 DOMAIN: 0000 io: base:1900 size:6c align:6 gran:0 limit:ef9f
1250 15:44:13.477342 PCI: 00:02.0 20 * [0x1c00 - 0x1c3f] io
1251 15:44:13.480505 PCI: 00:17.0 20 * [0x1c40 - 0x1c5f] io
1252 15:44:13.484460 PCI: 00:17.0 18 * [0x1c60 - 0x1c67] io
1253 15:44:13.487710 PCI: 00:17.0 1c * [0x1c68 - 0x1c6b] io
1254 15:44:13.494345 DOMAIN: 0000 io: next_base: 1c6c size: 6c align: 6 gran: 0 done
1255 15:44:13.500893 PCI: 00:1d.0 io: base:ef9f size:0 align:12 gran:12 limit:ef9f
1256 15:44:13.507313 PCI: 00:1d.0 io: next_base: ef9f size: 0 align: 12 gran: 12 done
1257 15:44:13.513797 DOMAIN: 0000 mem: base:c0000000 size:11229100 align:28 gran:0 limit:dfffffff
1258 15:44:13.520277 PCI: 00:02.0 18 * [0xc0000000 - 0xcfffffff] prefmem
1259 15:44:13.523800 PCI: 00:02.0 10 * [0xd0000000 - 0xd0ffffff] mem
1260 15:44:13.530450 PCI: 00:1d.0 20 * [0xd1000000 - 0xd10fffff] mem
1261 15:44:13.533595 PCI: 00:1f.3 20 * [0xd1100000 - 0xd11fffff] mem
1262 15:44:13.540238 PCI: 00:14.0 10 * [0xd1200000 - 0xd120ffff] mem
1263 15:44:13.543507 PCI: 00:14.3 10 * [0xd1210000 - 0xd1213fff] mem
1264 15:44:13.547205 PCI: 00:1f.3 10 * [0xd1214000 - 0xd1217fff] mem
1265 15:44:13.553484 PCI: 00:14.2 10 * [0xd1218000 - 0xd1219fff] mem
1266 15:44:13.557004 PCI: 00:17.0 10 * [0xd121a000 - 0xd121bfff] mem
1267 15:44:13.563939 PCI: 00:08.0 10 * [0xd121c000 - 0xd121cfff] mem
1268 15:44:13.566947 PCI: 00:12.0 10 * [0xd121d000 - 0xd121dfff] mem
1269 15:44:13.573270 PCI: 00:14.2 18 * [0xd121e000 - 0xd121efff] mem
1270 15:44:13.576821 PCI: 00:15.0 10 * [0xd121f000 - 0xd121ffff] mem
1271 15:44:13.583587 PCI: 00:15.1 10 * [0xd1220000 - 0xd1220fff] mem
1272 15:44:13.586652 PCI: 00:16.0 10 * [0xd1221000 - 0xd1221fff] mem
1273 15:44:13.593450 PCI: 00:19.0 10 * [0xd1222000 - 0xd1222fff] mem
1274 15:44:13.596836 PCI: 00:1e.0 18 * [0xd1223000 - 0xd1223fff] mem
1275 15:44:13.603467 PCI: 00:1e.2 10 * [0xd1224000 - 0xd1224fff] mem
1276 15:44:13.606499 PCI: 00:1e.3 10 * [0xd1225000 - 0xd1225fff] mem
1277 15:44:13.613044 PCI: 00:1f.5 10 * [0xd1226000 - 0xd1226fff] mem
1278 15:44:13.616611 PCI: 00:17.0 24 * [0xd1227000 - 0xd12277ff] mem
1279 15:44:13.623254 PCI: 00:17.0 14 * [0xd1228000 - 0xd12280ff] mem
1280 15:44:13.626442 PCI: 00:1f.4 10 * [0xd1229000 - 0xd12290ff] mem
1281 15:44:13.632904 DOMAIN: 0000 mem: next_base: d1229100 size: 11229100 align: 28 gran: 0 done
1282 15:44:13.639850 PCI: 00:1d.0 prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
1283 15:44:13.649795 PCI: 00:1d.0 prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
1284 15:44:13.656295 PCI: 00:1d.0 mem: base:d1000000 size:100000 align:20 gran:20 limit:d10fffff
1285 15:44:13.659447 PCI: 01:00.0 10 * [0xd1000000 - 0xd1003fff] mem
1286 15:44:13.669640 PCI: 00:1d.0 mem: next_base: d1004000 size: 100000 align: 20 gran: 20 done
1287 15:44:13.672684 Root Device assign_resources, bus 0 link: 0
1288 15:44:13.676290 DOMAIN: 0000 assign_resources, bus 0 link: 0
1289 15:44:13.686569 PCI: 00:02.0 10 <- [0x00d0000000 - 0x00d0ffffff] size 0x01000000 gran 0x18 mem64
1290 15:44:13.693159 PCI: 00:02.0 18 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64
1291 15:44:13.702787 PCI: 00:02.0 20 <- [0x0000001c00 - 0x0000001c3f] size 0x00000040 gran 0x06 io
1292 15:44:13.709545 PCI: 00:08.0 10 <- [0x00d121c000 - 0x00d121cfff] size 0x00001000 gran 0x0c mem64
1293 15:44:13.719601 PCI: 00:12.0 10 <- [0x00d121d000 - 0x00d121dfff] size 0x00001000 gran 0x0c mem64
1294 15:44:13.726136 PCI: 00:14.0 10 <- [0x00d1200000 - 0x00d120ffff] size 0x00010000 gran 0x10 mem64
1295 15:44:13.732721 PCI: 00:14.0 assign_resources, bus 0 link: 0
1296 15:44:13.736180 PCI: 00:14.0 assign_resources, bus 0 link: 0
1297 15:44:13.745652 PCI: 00:14.2 10 <- [0x00d1218000 - 0x00d1219fff] size 0x00002000 gran 0x0d mem64
1298 15:44:13.752577 PCI: 00:14.2 18 <- [0x00d121e000 - 0x00d121efff] size 0x00001000 gran 0x0c mem64
1299 15:44:13.759234 PCI: 00:14.3 10 <- [0x00d1210000 - 0x00d1213fff] size 0x00004000 gran 0x0e mem64
1300 15:44:13.769169 PCI: 00:15.0 10 <- [0x00d121f000 - 0x00d121ffff] size 0x00001000 gran 0x0c mem64
1301 15:44:13.772766 PCI: 00:15.0 assign_resources, bus 1 link: 0
1302 15:44:13.779189 PCI: 00:15.0 assign_resources, bus 1 link: 0
1303 15:44:13.786279 PCI: 00:15.1 10 <- [0x00d1220000 - 0x00d1220fff] size 0x00001000 gran 0x0c mem64
1304 15:44:13.792401 PCI: 00:15.1 assign_resources, bus 2 link: 0
1305 15:44:13.796069 PCI: 00:15.1 assign_resources, bus 2 link: 0
1306 15:44:13.802439 PCI: 00:16.0 10 <- [0x00d1221000 - 0x00d1221fff] size 0x00001000 gran 0x0c mem64
1307 15:44:13.812425 PCI: 00:17.0 10 <- [0x00d121a000 - 0x00d121bfff] size 0x00002000 gran 0x0d mem
1308 15:44:13.819501 PCI: 00:17.0 14 <- [0x00d1228000 - 0x00d12280ff] size 0x00000100 gran 0x08 mem
1309 15:44:13.829032 PCI: 00:17.0 18 <- [0x0000001c60 - 0x0000001c67] size 0x00000008 gran 0x03 io
1310 15:44:13.836210 PCI: 00:17.0 1c <- [0x0000001c68 - 0x0000001c6b] size 0x00000004 gran 0x02 io
1311 15:44:13.842357 PCI: 00:17.0 20 <- [0x0000001c40 - 0x0000001c5f] size 0x00000020 gran 0x05 io
1312 15:44:13.852407 PCI: 00:17.0 24 <- [0x00d1227000 - 0x00d12277ff] size 0x00000800 gran 0x0b mem
1313 15:44:13.858685 PCI: 00:19.0 10 <- [0x00d1222000 - 0x00d1222fff] size 0x00001000 gran 0x0c mem64
1314 15:44:13.862375 PCI: 00:19.0 assign_resources, bus 3 link: 0
1315 15:44:13.868933 PCI: 00:19.0 assign_resources, bus 3 link: 0
1316 15:44:13.875192 PCI: 00:1d.0 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus 01 io
1317 15:44:13.885544 PCI: 00:1d.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1318 15:44:13.895285 PCI: 00:1d.0 20 <- [0x00d1000000 - 0x00d10fffff] size 0x00100000 gran 0x14 bus 01 mem
1319 15:44:13.898422 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1320 15:44:13.908467 PCI: 01:00.0 10 <- [0x00d1000000 - 0x00d1003fff] size 0x00004000 gran 0x0e mem64
1321 15:44:13.911814 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1322 15:44:13.921345 PCI: 00:1e.0 18 <- [0x00d1223000 - 0x00d1223fff] size 0x00001000 gran 0x0c mem64
1323 15:44:13.928170 PCI: 00:1e.2 10 <- [0x00d1224000 - 0x00d1224fff] size 0x00001000 gran 0x0c mem64
1324 15:44:13.931238 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1325 15:44:13.938238 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1326 15:44:13.944425 PCI: 00:1e.3 10 <- [0x00d1225000 - 0x00d1225fff] size 0x00001000 gran 0x0c mem64
1327 15:44:13.951158 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1328 15:44:13.954702 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1329 15:44:13.961111 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1330 15:44:13.964713 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1331 15:44:13.970999 LPC: Trying to open IO window from 800 size 1ff
1332 15:44:13.977837 PCI: 00:1f.3 10 <- [0x00d1214000 - 0x00d1217fff] size 0x00004000 gran 0x0e mem64
1333 15:44:13.987563 PCI: 00:1f.3 20 <- [0x00d1100000 - 0x00d11fffff] size 0x00100000 gran 0x14 mem64
1334 15:44:13.994350 PCI: 00:1f.4 10 <- [0x00d1229000 - 0x00d12290ff] size 0x00000100 gran 0x08 mem64
1335 15:44:14.004086 PCI: 00:1f.5 10 <- [0x00d1226000 - 0x00d1226fff] size 0x00001000 gran 0x0c mem
1336 15:44:14.007270 DOMAIN: 0000 assign_resources, bus 0 link: 0
1337 15:44:14.010869 Root Device assign_resources, bus 0 link: 0
1338 15:44:14.013967 Done setting resources.
1339 15:44:14.020614 Show resources in subtree (Root Device)...After assigning values.
1340 15:44:14.023712 Root Device child on link 0 CPU_CLUSTER: 0
1341 15:44:14.030353 CPU_CLUSTER: 0 child on link 0 APIC: 00
1342 15:44:14.030781 APIC: 00
1343 15:44:14.031118 APIC: 02
1344 15:44:14.033769 APIC: 01
1345 15:44:14.034195 APIC: 03
1346 15:44:14.037300 APIC: 05
1347 15:44:14.037747 APIC: 04
1348 15:44:14.038086 APIC: 06
1349 15:44:14.040382 APIC: 07
1350 15:44:14.043831 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1351 15:44:14.053653 DOMAIN: 0000 resource base 1900 size 6c align 6 gran 0 limit ef9f flags 40040100 index 10000000
1352 15:44:14.063542 DOMAIN: 0000 resource base c0000000 size 11229100 align 28 gran 0 limit dfffffff flags 40040200 index 10000100
1353 15:44:14.066776 PCI: 00:00.0
1354 15:44:14.076969 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1355 15:44:14.086834 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1356 15:44:14.093675 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1357 15:44:14.103221 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1358 15:44:14.113085 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1359 15:44:14.122819 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1360 15:44:14.132667 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1361 15:44:14.142907 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1362 15:44:14.149644 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1363 15:44:14.159108 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1364 15:44:14.168928 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1365 15:44:14.179204 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1366 15:44:14.188978 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1367 15:44:14.198851 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1368 15:44:14.208868 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1369 15:44:14.215334 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1370 15:44:14.218253 PCI: 00:02.0
1371 15:44:14.228465 PCI: 00:02.0 resource base d0000000 size 1000000 align 24 gran 24 limit d0ffffff flags 60000201 index 10
1372 15:44:14.238199 PCI: 00:02.0 resource base c0000000 size 10000000 align 28 gran 28 limit cfffffff flags 60001201 index 18
1373 15:44:14.248160 PCI: 00:02.0 resource base 1c00 size 40 align 6 gran 6 limit 1c3f flags 60000100 index 20
1374 15:44:14.251656 PCI: 00:04.0
1375 15:44:14.252127 PCI: 00:08.0
1376 15:44:14.261416 PCI: 00:08.0 resource base d121c000 size 1000 align 12 gran 12 limit d121cfff flags 60000201 index 10
1377 15:44:14.264619 PCI: 00:12.0
1378 15:44:14.274400 PCI: 00:12.0 resource base d121d000 size 1000 align 12 gran 12 limit d121dfff flags 60000201 index 10
1379 15:44:14.278019 PCI: 00:14.0 child on link 0 USB0 port 0
1380 15:44:14.287980 PCI: 00:14.0 resource base d1200000 size 10000 align 16 gran 16 limit d120ffff flags 60000201 index 10
1381 15:44:14.294407 USB0 port 0 child on link 0 USB2 port 0
1382 15:44:14.294934 USB2 port 0
1383 15:44:14.297534 USB2 port 1
1384 15:44:14.298042 USB2 port 2
1385 15:44:14.301244 USB2 port 3
1386 15:44:14.301730 USB2 port 5
1387 15:44:14.304262 USB2 port 6
1388 15:44:14.304848 USB2 port 9
1389 15:44:14.307612 USB3 port 0
1390 15:44:14.308125 USB3 port 1
1391 15:44:14.310732 USB3 port 2
1392 15:44:14.311197 USB3 port 3
1393 15:44:14.314294 USB3 port 4
1394 15:44:14.317814 PCI: 00:14.2
1395 15:44:14.327396 PCI: 00:14.2 resource base d1218000 size 2000 align 13 gran 13 limit d1219fff flags 60000201 index 10
1396 15:44:14.337583 PCI: 00:14.2 resource base d121e000 size 1000 align 12 gran 12 limit d121efff flags 60000201 index 18
1397 15:44:14.338139 PCI: 00:14.3
1398 15:44:14.347014 PCI: 00:14.3 resource base d1210000 size 4000 align 14 gran 14 limit d1213fff flags 60000201 index 10
1399 15:44:14.353648 PCI: 00:15.0 child on link 0 I2C: 01:15
1400 15:44:14.363797 PCI: 00:15.0 resource base d121f000 size 1000 align 12 gran 12 limit d121ffff flags 60000201 index 10
1401 15:44:14.364306 I2C: 01:15
1402 15:44:14.370162 PCI: 00:15.1 child on link 0 I2C: 02:5d
1403 15:44:14.380795 PCI: 00:15.1 resource base d1220000 size 1000 align 12 gran 12 limit d1220fff flags 60000201 index 10
1404 15:44:14.381433 I2C: 02:5d
1405 15:44:14.383644 GENERIC: 0.0
1406 15:44:14.384111 PCI: 00:16.0
1407 15:44:14.393634 PCI: 00:16.0 resource base d1221000 size 1000 align 12 gran 12 limit d1221fff flags 60000201 index 10
1408 15:44:14.396654 PCI: 00:17.0
1409 15:44:14.406809 PCI: 00:17.0 resource base d121a000 size 2000 align 13 gran 13 limit d121bfff flags 60000200 index 10
1410 15:44:14.416560 PCI: 00:17.0 resource base d1228000 size 100 align 12 gran 8 limit d12280ff flags 60000200 index 14
1411 15:44:14.426667 PCI: 00:17.0 resource base 1c60 size 8 align 3 gran 3 limit 1c67 flags 60000100 index 18
1412 15:44:14.433509 PCI: 00:17.0 resource base 1c68 size 4 align 2 gran 2 limit 1c6b flags 60000100 index 1c
1413 15:44:14.443156 PCI: 00:17.0 resource base 1c40 size 20 align 5 gran 5 limit 1c5f flags 60000100 index 20
1414 15:44:14.452806 PCI: 00:17.0 resource base d1227000 size 800 align 12 gran 11 limit d12277ff flags 60000200 index 24
1415 15:44:14.460072 PCI: 00:19.0 child on link 0 I2C: 03:1a
1416 15:44:14.469603 PCI: 00:19.0 resource base d1222000 size 1000 align 12 gran 12 limit d1222fff flags 60000201 index 10
1417 15:44:14.470060 I2C: 03:1a
1418 15:44:14.472832 I2C: 03:38
1419 15:44:14.473294 I2C: 03:39
1420 15:44:14.475910 I2C: 03:3a
1421 15:44:14.476345 I2C: 03:3b
1422 15:44:14.479621 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1423 15:44:14.489104 PCI: 00:1d.0 resource base ef9f size 0 align 12 gran 12 limit ef9f flags 60080102 index 1c
1424 15:44:14.499298 PCI: 00:1d.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
1425 15:44:14.509308 PCI: 00:1d.0 resource base d1000000 size 100000 align 20 gran 20 limit d10fffff flags 60080202 index 20
1426 15:44:14.512347 PCI: 01:00.0
1427 15:44:14.522869 PCI: 01:00.0 resource base d1000000 size 4000 align 14 gran 14 limit d1003fff flags 60000201 index 10
1428 15:44:14.525722 PCI: 00:1e.0
1429 15:44:14.535309 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1430 15:44:14.545369 PCI: 00:1e.0 resource base d1223000 size 1000 align 12 gran 12 limit d1223fff flags 60000201 index 18
1431 15:44:14.548920 PCI: 00:1e.2 child on link 0 SPI: 00
1432 15:44:14.558716 PCI: 00:1e.2 resource base d1224000 size 1000 align 12 gran 12 limit d1224fff flags 60000201 index 10
1433 15:44:14.561809 SPI: 00
1434 15:44:14.565756 PCI: 00:1e.3 child on link 0 SPI: 01
1435 15:44:14.575520 PCI: 00:1e.3 resource base d1225000 size 1000 align 12 gran 12 limit d1225fff flags 60000201 index 10
1436 15:44:14.576055 SPI: 01
1437 15:44:14.581648 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1438 15:44:14.588447 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1439 15:44:14.598106 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1440 15:44:14.601654 PNP: 0c09.0
1441 15:44:14.608515 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1442 15:44:14.611613 PCI: 00:1f.3
1443 15:44:14.621656 PCI: 00:1f.3 resource base d1214000 size 4000 align 14 gran 14 limit d1217fff flags 60000201 index 10
1444 15:44:14.631152 PCI: 00:1f.3 resource base d1100000 size 100000 align 20 gran 20 limit d11fffff flags 60000201 index 20
1445 15:44:14.634371 PCI: 00:1f.4
1446 15:44:14.641178 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1447 15:44:14.651404 PCI: 00:1f.4 resource base d1229000 size 100 align 12 gran 8 limit d12290ff flags 60000201 index 10
1448 15:44:14.654244 PCI: 00:1f.5
1449 15:44:14.664450 PCI: 00:1f.5 resource base d1226000 size 1000 align 12 gran 12 limit d1226fff flags 60000200 index 10
1450 15:44:14.667657 Done allocating resources.
1451 15:44:14.674251 BS: BS_DEV_RESOURCES times (ms): entry 0 run 30 exit 0
1452 15:44:14.674690 Enabling resources...
1453 15:44:14.681180 PCI: 00:00.0 subsystem <- 8086/9b61
1454 15:44:14.681668 PCI: 00:00.0 cmd <- 06
1455 15:44:14.684666 PCI: 00:02.0 subsystem <- 8086/9b41
1456 15:44:14.688006 PCI: 00:02.0 cmd <- 03
1457 15:44:14.691594 PCI: 00:08.0 cmd <- 06
1458 15:44:14.694599 PCI: 00:12.0 subsystem <- 8086/02f9
1459 15:44:14.697725 PCI: 00:12.0 cmd <- 02
1460 15:44:14.701334 PCI: 00:14.0 subsystem <- 8086/02ed
1461 15:44:14.704316 PCI: 00:14.0 cmd <- 02
1462 15:44:14.707868 PCI: 00:14.2 cmd <- 02
1463 15:44:14.711019 PCI: 00:14.3 subsystem <- 8086/02f0
1464 15:44:14.711458 PCI: 00:14.3 cmd <- 02
1465 15:44:14.717733 PCI: 00:15.0 subsystem <- 8086/02e8
1466 15:44:14.718173 PCI: 00:15.0 cmd <- 02
1467 15:44:14.721447 PCI: 00:15.1 subsystem <- 8086/02e9
1468 15:44:14.724612 PCI: 00:15.1 cmd <- 02
1469 15:44:14.727680 PCI: 00:16.0 subsystem <- 8086/02e0
1470 15:44:14.730896 PCI: 00:16.0 cmd <- 02
1471 15:44:14.734551 PCI: 00:17.0 subsystem <- 8086/02d3
1472 15:44:14.737816 PCI: 00:17.0 cmd <- 03
1473 15:44:14.741382 PCI: 00:19.0 subsystem <- 8086/02c5
1474 15:44:14.744180 PCI: 00:19.0 cmd <- 02
1475 15:44:14.747696 PCI: 00:1d.0 bridge ctrl <- 0013
1476 15:44:14.750768 PCI: 00:1d.0 subsystem <- 8086/02b0
1477 15:44:14.754504 PCI: 00:1d.0 cmd <- 06
1478 15:44:14.757541 PCI: 00:1e.0 subsystem <- 8086/02a8
1479 15:44:14.761227 PCI: 00:1e.0 cmd <- 06
1480 15:44:14.764334 PCI: 00:1e.2 subsystem <- 8086/02aa
1481 15:44:14.767416 PCI: 00:1e.2 cmd <- 06
1482 15:44:14.770685 PCI: 00:1e.3 subsystem <- 8086/02ab
1483 15:44:14.771380 PCI: 00:1e.3 cmd <- 02
1484 15:44:14.777482 PCI: 00:1f.0 subsystem <- 8086/0284
1485 15:44:14.777938 PCI: 00:1f.0 cmd <- 407
1486 15:44:14.784371 PCI: 00:1f.3 subsystem <- 8086/02c8
1487 15:44:14.784808 PCI: 00:1f.3 cmd <- 02
1488 15:44:14.787410 PCI: 00:1f.4 subsystem <- 8086/02a3
1489 15:44:14.790892 PCI: 00:1f.4 cmd <- 03
1490 15:44:14.794028 PCI: 00:1f.5 subsystem <- 8086/02a4
1491 15:44:14.797248 PCI: 00:1f.5 cmd <- 406
1492 15:44:14.806252 PCI: 01:00.0 cmd <- 02
1493 15:44:14.811501 done.
1494 15:44:14.824738 ME: Version: 14.0.39.1367
1495 15:44:14.831398 BS: BS_DEV_ENABLE times (ms): entry 0 run 17 exit 13
1496 15:44:14.835256 Initializing devices...
1497 15:44:14.835841 Root Device init ...
1498 15:44:14.841559 Chrome EC: Set SMI mask to 0x0000000000000000
1499 15:44:14.844615 Chrome EC: clear events_b mask to 0x0000000000000000
1500 15:44:14.851209 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1501 15:44:14.858239 Chrome EC: Set S3 LAZY WAKE mask to 0x0000000014001006
1502 15:44:14.864871 Chrome EC: Set S0iX LAZY WAKE mask to 0x0000000014081006
1503 15:44:14.867754 Chrome EC: Set WAKE mask to 0x0000000000000000
1504 15:44:14.870946 Root Device init finished in 35242 usecs
1505 15:44:14.874754 CPU_CLUSTER: 0 init ...
1506 15:44:14.881536 CPU_CLUSTER: 0 init finished in 2438 usecs
1507 15:44:14.885836 PCI: 00:00.0 init ...
1508 15:44:14.889290 CPU TDP: 15 Watts
1509 15:44:14.892410 CPU PL2 = 64 Watts
1510 15:44:14.895471 PCI: 00:00.0 init finished in 7071 usecs
1511 15:44:14.899146 PCI: 00:02.0 init ...
1512 15:44:14.902308 PCI: 00:02.0 init finished in 2244 usecs
1513 15:44:14.905184 PCI: 00:08.0 init ...
1514 15:44:14.908827 PCI: 00:08.0 init finished in 2253 usecs
1515 15:44:14.912217 PCI: 00:12.0 init ...
1516 15:44:14.915408 PCI: 00:12.0 init finished in 2242 usecs
1517 15:44:14.919036 PCI: 00:14.0 init ...
1518 15:44:14.921884 PCI: 00:14.0 init finished in 2252 usecs
1519 15:44:14.925315 PCI: 00:14.2 init ...
1520 15:44:14.928848 PCI: 00:14.2 init finished in 2252 usecs
1521 15:44:14.931881 PCI: 00:14.3 init ...
1522 15:44:14.935674 PCI: 00:14.3 init finished in 2260 usecs
1523 15:44:14.938650 PCI: 00:15.0 init ...
1524 15:44:14.941959 DW I2C bus 0 at 0xd121f000 (400 KHz)
1525 15:44:14.945484 PCI: 00:15.0 init finished in 5975 usecs
1526 15:44:14.948464 PCI: 00:15.1 init ...
1527 15:44:14.952092 DW I2C bus 1 at 0xd1220000 (400 KHz)
1528 15:44:14.958368 PCI: 00:15.1 init finished in 5976 usecs
1529 15:44:14.958825 PCI: 00:16.0 init ...
1530 15:44:14.964908 PCI: 00:16.0 init finished in 2252 usecs
1531 15:44:14.968381 PCI: 00:19.0 init ...
1532 15:44:14.971386 DW I2C bus 4 at 0xd1222000 (400 KHz)
1533 15:44:14.975422 PCI: 00:19.0 init finished in 5979 usecs
1534 15:44:14.978292 PCI: 00:1d.0 init ...
1535 15:44:14.981452 Initializing PCH PCIe bridge.
1536 15:44:14.984697 PCI: 00:1d.0 init finished in 5284 usecs
1537 15:44:14.988373 PCI: 00:1f.0 init ...
1538 15:44:14.992207 IOAPIC: Initializing IOAPIC at 0xfec00000
1539 15:44:14.998263 IOAPIC: Bootstrap Processor Local APIC = 0x00
1540 15:44:14.998829 IOAPIC: ID = 0x02
1541 15:44:15.001391 IOAPIC: Dumping registers
1542 15:44:15.004545 reg 0x0000: 0x02000000
1543 15:44:15.007618 reg 0x0001: 0x00770020
1544 15:44:15.008095 reg 0x0002: 0x00000000
1545 15:44:15.014330 PCI: 00:1f.0 init finished in 23548 usecs
1546 15:44:15.017778 PCI: 00:1f.4 init ...
1547 15:44:15.020861 PCI: 00:1f.4 init finished in 2263 usecs
1548 15:44:15.031909 PCI: 01:00.0 init ...
1549 15:44:15.035274 PCI: 01:00.0 init finished in 2243 usecs
1550 15:44:15.039099 PNP: 0c09.0 init ...
1551 15:44:15.042385 Google Chrome EC uptime: 11.068 seconds
1552 15:44:15.049342 Google Chrome AP resets since EC boot: 0
1553 15:44:15.052286 Google Chrome most recent AP reset causes:
1554 15:44:15.058671 Google Chrome EC reset flags at last EC boot: reset-pin
1555 15:44:15.062335 PNP: 0c09.0 init finished in 20572 usecs
1556 15:44:15.065522 Devices initialized
1557 15:44:15.068939 Show all devs... After init.
1558 15:44:15.069448 Root Device: enabled 1
1559 15:44:15.072024 CPU_CLUSTER: 0: enabled 1
1560 15:44:15.075587 DOMAIN: 0000: enabled 1
1561 15:44:15.076021 APIC: 00: enabled 1
1562 15:44:15.078629 PCI: 00:00.0: enabled 1
1563 15:44:15.081899 PCI: 00:02.0: enabled 1
1564 15:44:15.085146 PCI: 00:04.0: enabled 0
1565 15:44:15.085580 PCI: 00:05.0: enabled 0
1566 15:44:15.088872 PCI: 00:12.0: enabled 1
1567 15:44:15.092192 PCI: 00:12.5: enabled 0
1568 15:44:15.095025 PCI: 00:12.6: enabled 0
1569 15:44:15.095470 PCI: 00:14.0: enabled 1
1570 15:44:15.098483 PCI: 00:14.1: enabled 0
1571 15:44:15.101817 PCI: 00:14.3: enabled 1
1572 15:44:15.105356 PCI: 00:14.5: enabled 0
1573 15:44:15.105789 PCI: 00:15.0: enabled 1
1574 15:44:15.108303 PCI: 00:15.1: enabled 1
1575 15:44:15.111562 PCI: 00:15.2: enabled 0
1576 15:44:15.111992 PCI: 00:15.3: enabled 0
1577 15:44:15.115166 PCI: 00:16.0: enabled 1
1578 15:44:15.118245 PCI: 00:16.1: enabled 0
1579 15:44:15.121535 PCI: 00:16.2: enabled 0
1580 15:44:15.121980 PCI: 00:16.3: enabled 0
1581 15:44:15.125035 PCI: 00:16.4: enabled 0
1582 15:44:15.128152 PCI: 00:16.5: enabled 0
1583 15:44:15.131742 PCI: 00:17.0: enabled 1
1584 15:44:15.132171 PCI: 00:19.0: enabled 1
1585 15:44:15.134809 PCI: 00:19.1: enabled 0
1586 15:44:15.138305 PCI: 00:19.2: enabled 0
1587 15:44:15.141432 PCI: 00:1a.0: enabled 0
1588 15:44:15.141873 PCI: 00:1c.0: enabled 0
1589 15:44:15.144840 PCI: 00:1c.1: enabled 0
1590 15:44:15.148319 PCI: 00:1c.2: enabled 0
1591 15:44:15.148767 PCI: 00:1c.3: enabled 0
1592 15:44:15.151374 PCI: 00:1c.4: enabled 0
1593 15:44:15.154693 PCI: 00:1c.5: enabled 0
1594 15:44:15.158165 PCI: 00:1c.6: enabled 0
1595 15:44:15.158602 PCI: 00:1c.7: enabled 0
1596 15:44:15.161590 PCI: 00:1d.0: enabled 1
1597 15:44:15.164601 PCI: 00:1d.1: enabled 0
1598 15:44:15.167956 PCI: 00:1d.2: enabled 0
1599 15:44:15.168395 PCI: 00:1d.3: enabled 0
1600 15:44:15.171218 PCI: 00:1d.4: enabled 0
1601 15:44:15.174348 PCI: 00:1d.5: enabled 0
1602 15:44:15.177768 PCI: 00:1e.0: enabled 1
1603 15:44:15.178201 PCI: 00:1e.1: enabled 0
1604 15:44:15.180972 PCI: 00:1e.2: enabled 1
1605 15:44:15.185042 PCI: 00:1e.3: enabled 1
1606 15:44:15.188159 PCI: 00:1f.0: enabled 1
1607 15:44:15.188687 PCI: 00:1f.1: enabled 0
1608 15:44:15.191232 PCI: 00:1f.2: enabled 0
1609 15:44:15.194727 PCI: 00:1f.3: enabled 1
1610 15:44:15.195211 PCI: 00:1f.4: enabled 1
1611 15:44:15.197704 PCI: 00:1f.5: enabled 1
1612 15:44:15.200831 PCI: 00:1f.6: enabled 0
1613 15:44:15.204828 USB0 port 0: enabled 1
1614 15:44:15.205393 I2C: 01:15: enabled 1
1615 15:44:15.207890 I2C: 02:5d: enabled 1
1616 15:44:15.210680 GENERIC: 0.0: enabled 1
1617 15:44:15.211146 I2C: 03:1a: enabled 1
1618 15:44:15.214203 I2C: 03:38: enabled 1
1619 15:44:15.217677 I2C: 03:39: enabled 1
1620 15:44:15.218137 I2C: 03:3a: enabled 1
1621 15:44:15.220755 I2C: 03:3b: enabled 1
1622 15:44:15.223912 PCI: 00:00.0: enabled 1
1623 15:44:15.224353 SPI: 00: enabled 1
1624 15:44:15.227541 SPI: 01: enabled 1
1625 15:44:15.230610 PNP: 0c09.0: enabled 1
1626 15:44:15.231068 USB2 port 0: enabled 1
1627 15:44:15.233778 USB2 port 1: enabled 1
1628 15:44:15.237223 USB2 port 2: enabled 0
1629 15:44:15.240840 USB2 port 3: enabled 0
1630 15:44:15.241333 USB2 port 5: enabled 0
1631 15:44:15.243798 USB2 port 6: enabled 1
1632 15:44:15.247337 USB2 port 9: enabled 1
1633 15:44:15.247774 USB3 port 0: enabled 1
1634 15:44:15.250394 USB3 port 1: enabled 1
1635 15:44:15.254233 USB3 port 2: enabled 1
1636 15:44:15.257150 USB3 port 3: enabled 1
1637 15:44:15.257613 USB3 port 4: enabled 0
1638 15:44:15.260276 APIC: 02: enabled 1
1639 15:44:15.260791 APIC: 01: enabled 1
1640 15:44:15.263644 APIC: 03: enabled 1
1641 15:44:15.267287 APIC: 05: enabled 1
1642 15:44:15.267746 APIC: 04: enabled 1
1643 15:44:15.270153 APIC: 06: enabled 1
1644 15:44:15.273875 APIC: 07: enabled 1
1645 15:44:15.274312 PCI: 00:08.0: enabled 1
1646 15:44:15.276893 PCI: 00:14.2: enabled 1
1647 15:44:15.280207 PCI: 01:00.0: enabled 1
1648 15:44:15.283779 Disabling ACPI via APMC:
1649 15:44:15.287396 done.
1650 15:44:15.290478 FMAP: area RW_ELOG found @ af0000 (16384 bytes)
1651 15:44:15.293748 ELOG: NV offset 0xaf0000 size 0x4000
1652 15:44:15.300629 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1653 15:44:15.307339 ELOG: Event(17) added with size 13 at 2022-09-17 15:44:05 UTC
1654 15:44:15.314233 ELOG: Event(92) added with size 9 at 2022-09-17 15:44:05 UTC
1655 15:44:15.320773 ELOG: Event(93) added with size 9 at 2022-09-17 15:44:05 UTC
1656 15:44:15.327513 ELOG: Event(9A) added with size 9 at 2022-09-17 15:44:05 UTC
1657 15:44:15.334221 ELOG: Event(9E) added with size 10 at 2022-09-17 15:44:05 UTC
1658 15:44:15.340881 ELOG: Event(9F) added with size 14 at 2022-09-17 15:44:05 UTC
1659 15:44:15.343947 BS: BS_DEV_INIT times (ms): entry 0 run 28 exit 6
1660 15:44:15.351114 ELOG: Event(A1) added with size 10 at 2022-09-17 15:44:05 UTC
1661 15:44:15.360987 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1662 15:44:15.367599 ELOG: Event(A0) added with size 9 at 2022-09-17 15:44:05 UTC
1663 15:44:15.370513 elog_add_boot_reason: Logged dev mode boot
1664 15:44:15.373980 Finalize devices...
1665 15:44:15.374419 PCI: 00:17.0 final
1666 15:44:15.377473 Devices finalized
1667 15:44:15.380582 FMAP: area RW_NVRAM found @ afa000 (24576 bytes)
1668 15:44:15.387230 BS: BS_POST_DEVICE times (ms): entry 1 run 0 exit 0
1669 15:44:15.390359 ME: HFSTS1 : 0x90000245
1670 15:44:15.393865 ME: HFSTS2 : 0x3B850126
1671 15:44:15.400227 ME: HFSTS3 : 0x00000020
1672 15:44:15.403742 ME: HFSTS4 : 0x00004800
1673 15:44:15.406945 ME: HFSTS5 : 0x00000000
1674 15:44:15.410617 ME: HFSTS6 : 0x40400006
1675 15:44:15.413716 ME: Manufacturing Mode : NO
1676 15:44:15.416722 ME: FW Partition Table : OK
1677 15:44:15.420313 ME: Bringup Loader Failure : NO
1678 15:44:15.423478 ME: Firmware Init Complete : YES
1679 15:44:15.427050 ME: Boot Options Present : NO
1680 15:44:15.430108 ME: Update In Progress : NO
1681 15:44:15.433556 ME: D0i3 Support : YES
1682 15:44:15.436816 ME: Low Power State Enabled : NO
1683 15:44:15.440278 ME: CPU Replaced : NO
1684 15:44:15.443394 ME: CPU Replacement Valid : YES
1685 15:44:15.446511 ME: Current Working State : 5
1686 15:44:15.450274 ME: Current Operation State : 1
1687 15:44:15.453039 ME: Current Operation Mode : 0
1688 15:44:15.456583 ME: Error Code : 0
1689 15:44:15.459863 ME: CPU Debug Disabled : YES
1690 15:44:15.463241 ME: TXT Support : NO
1691 15:44:15.469674 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
1692 15:44:15.476227 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1693 15:44:15.476671 CBFS @ c08000 size 3f8000
1694 15:44:15.483171 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1695 15:44:15.486212 CBFS: Locating 'fallback/dsdt.aml'
1696 15:44:15.489491 CBFS: Found @ offset 10bb80 size 3fa5
1697 15:44:15.496410 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1698 15:44:15.499637 CBFS @ c08000 size 3f8000
1699 15:44:15.506916 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1700 15:44:15.507506 CBFS: Locating 'fallback/slic'
1701 15:44:15.511725 CBFS: 'fallback/slic' not found.
1702 15:44:15.518358 ACPI: Writing ACPI tables at 99b3e000.
1703 15:44:15.518829 ACPI: * FACS
1704 15:44:15.521547 ACPI: * DSDT
1705 15:44:15.525006 Ramoops buffer: 0x100000@0x99a3d000.
1706 15:44:15.528088 FMAP: area RO_VPD found @ c00000 (16384 bytes)
1707 15:44:15.534828 FMAP: area RW_VPD found @ af8000 (8192 bytes)
1708 15:44:15.537857 Google Chrome EC: version:
1709 15:44:15.541456 ro: helios_v2.0.2659-56403530b
1710 15:44:15.544641 rw: helios_v2.0.2849-c41de27e7d
1711 15:44:15.545243 running image: 1
1712 15:44:15.548750 ACPI: * FADT
1713 15:44:15.549240 SCI is IRQ9
1714 15:44:15.555463 ACPI: added table 1/32, length now 40
1715 15:44:15.555898 ACPI: * SSDT
1716 15:44:15.559114 Found 1 CPU(s) with 8 core(s) each.
1717 15:44:15.562338 Error: Could not locate 'wifi_sar' in VPD.
1718 15:44:15.568682 Checking CBFS for default SAR values
1719 15:44:15.572173 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1720 15:44:15.575687 CBFS @ c08000 size 3f8000
1721 15:44:15.581730 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1722 15:44:15.585426 CBFS: Locating 'wifi_sar_defaults.hex'
1723 15:44:15.588488 CBFS: Found @ offset 5fac0 size 77
1724 15:44:15.592353 \_SB.PCI0.WFA3: Intel WiFi PCI: 00:14.3
1725 15:44:15.598527 \_SB.PCI0.I2C0.D015: ELAN Touchpad at I2C: 01:15
1726 15:44:15.601616 \_SB.PCI0.I2C1.H05D: Goodix Touchscreen at I2C: 02:5d
1727 15:44:15.608739 \_SB.PCI0.I2C4.RT58: Realtek RT5682 at I2C: 03:1a
1728 15:44:15.611811 failed to find key in VPD: dsm_calib_r0_0
1729 15:44:15.621604 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_0 and dsm_calib_temp_0
1730 15:44:15.624699 \_SB.PCI0.I2C4.RTWL: Realtek RT1011 Codec address 038h
1731 15:44:15.631241 failed to find key in VPD: dsm_calib_r0_1
1732 15:44:15.638267 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_1 and dsm_calib_temp_0
1733 15:44:15.644721 \_SB.PCI0.I2C4.RTWR: Realtek RT1011 Codec address 039h
1734 15:44:15.647821 failed to find key in VPD: dsm_calib_r0_2
1735 15:44:15.658255 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_2 and dsm_calib_temp_0
1736 15:44:15.661191 \_SB.PCI0.I2C4.RTTL: Realtek RT1011 Codec address 03ah
1737 15:44:15.667620 failed to find key in VPD: dsm_calib_r0_3
1738 15:44:15.674230 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_3 and dsm_calib_temp_0
1739 15:44:15.680794 \_SB.PCI0.I2C4.RTTR: Realtek RT1011 Codec address 03bh
1740 15:44:15.684291 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1741 15:44:15.691007 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 01
1742 15:44:15.694599 EC returned error result code 1
1743 15:44:15.698171 EC returned error result code 1
1744 15:44:15.701221 EC returned error result code 1
1745 15:44:15.704926 PS2K: Bad resp from EC. Vivaldi disabled!
1746 15:44:15.711059 \_SB.PCI0.XHCI.RHUB.HS01: Left Type-C Port at USB2 port 0
1747 15:44:15.718035 \_SB.PCI0.XHCI.RHUB.HS02: Right Type-C Port 1 at USB2 port 1
1748 15:44:15.721153 \_SB.PCI0.XHCI.RHUB.HS07: Camera at USB2 port 6
1749 15:44:15.727849 \_SB.PCI0.XHCI.RHUB.HS10: Bluetooth at USB2 port 9
1750 15:44:15.731042 \_SB.PCI0.XHCI.RHUB.SS01: Left Type-C Port at USB3 port 0
1751 15:44:15.737689 \_SB.PCI0.XHCI.RHUB.SS02: Right Type-C Port 1 at USB3 port 1
1752 15:44:15.744362 \_SB.PCI0.XHCI.RHUB.SS03: Left Type-A Port at USB3 port 2
1753 15:44:15.751222 \_SB.PCI0.XHCI.RHUB.SS04: Right Type-A Port 1 at USB3 port 3
1754 15:44:15.754401 ACPI: added table 2/32, length now 44
1755 15:44:15.754837 ACPI: * MCFG
1756 15:44:15.761150 ACPI: added table 3/32, length now 48
1757 15:44:15.761716 ACPI: * TPM2
1758 15:44:15.764062 TPM2 log created at 99a2d000
1759 15:44:15.767616 ACPI: added table 4/32, length now 52
1760 15:44:15.770916 ACPI: * MADT
1761 15:44:15.771396 SCI is IRQ9
1762 15:44:15.774009 ACPI: added table 5/32, length now 56
1763 15:44:15.777614 current = 99b43ac0
1764 15:44:15.778042 ACPI: * DMAR
1765 15:44:15.780744 ACPI: added table 6/32, length now 60
1766 15:44:15.784320 ACPI: * IGD OpRegion
1767 15:44:15.787375 GMA: Found VBT in CBFS
1768 15:44:15.790937 GMA: Found valid VBT in CBFS
1769 15:44:15.794148 ACPI: added table 7/32, length now 64
1770 15:44:15.794686 ACPI: * HPET
1771 15:44:15.797283 ACPI: added table 8/32, length now 68
1772 15:44:15.800857 ACPI: done.
1773 15:44:15.803881 ACPI tables: 31744 bytes.
1774 15:44:15.807452 smbios_write_tables: 99a2c000
1775 15:44:15.810753 EC returned error result code 3
1776 15:44:15.814364 Couldn't obtain OEM name from CBI
1777 15:44:15.817291 Create SMBIOS type 17
1778 15:44:15.820456 PCI: 00:00.0 (Intel Cannonlake)
1779 15:44:15.820888 PCI: 00:14.3 (Intel WiFi)
1780 15:44:15.823666 SMBIOS tables: 939 bytes.
1781 15:44:15.826748 Writing table forward entry at 0x00000500
1782 15:44:15.833773 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4628
1783 15:44:15.836809 Writing coreboot table at 0x99b62000
1784 15:44:15.843712 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1785 15:44:15.846601 1. 0000000000001000-000000000009ffff: RAM
1786 15:44:15.853330 2. 00000000000a0000-00000000000fffff: RESERVED
1787 15:44:15.856737 3. 0000000000100000-0000000099a2bfff: RAM
1788 15:44:15.863475 4. 0000000099a2c000-0000000099baffff: CONFIGURATION TABLES
1789 15:44:15.866848 5. 0000000099bb0000-0000000099c0afff: RAMSTAGE
1790 15:44:15.873321 6. 0000000099c0b000-0000000099ffffff: CONFIGURATION TABLES
1791 15:44:15.880072 7. 000000009a000000-000000009f7fffff: RESERVED
1792 15:44:15.883071 8. 00000000e0000000-00000000efffffff: RESERVED
1793 15:44:15.889641 9. 00000000fc000000-00000000fc000fff: RESERVED
1794 15:44:15.893170 10. 00000000fe000000-00000000fe00ffff: RESERVED
1795 15:44:15.896473 11. 00000000fed10000-00000000fed17fff: RESERVED
1796 15:44:15.902708 12. 00000000fed80000-00000000fed83fff: RESERVED
1797 15:44:15.905956 13. 00000000fed90000-00000000fed91fff: RESERVED
1798 15:44:15.912698 14. 00000000feda0000-00000000feda1fff: RESERVED
1799 15:44:15.916146 15. 0000000100000000-000000045e7fffff: RAM
1800 15:44:15.919385 Graphics framebuffer located at 0xc0000000
1801 15:44:15.922560 Passing 5 GPIOs to payload:
1802 15:44:15.929439 NAME | PORT | POLARITY | VALUE
1803 15:44:15.932934 write protect | undefined | high | low
1804 15:44:15.939535 lid | undefined | high | high
1805 15:44:15.946019 power | undefined | high | low
1806 15:44:15.949236 oprom | undefined | high | low
1807 15:44:15.955943 EC in RW | 0x000000cb | high | low
1808 15:44:15.956380 Board ID: 4
1809 15:44:15.962217 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1810 15:44:15.962728 CBFS @ c08000 size 3f8000
1811 15:44:15.969292 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1812 15:44:15.975516 Wrote coreboot table at: 99b62000, 0x5bc bytes, checksum 6264
1813 15:44:15.979021 coreboot table: 1492 bytes.
1814 15:44:15.982158 IMD ROOT 0. 99fff000 00001000
1815 15:44:15.985640 IMD SMALL 1. 99ffe000 00001000
1816 15:44:15.988862 FSP MEMORY 2. 99c4e000 003b0000
1817 15:44:15.992243 CONSOLE 3. 99c2e000 00020000
1818 15:44:15.995695 FMAP 4. 99c2d000 0000054e
1819 15:44:15.998928 TIME STAMP 5. 99c2c000 00000910
1820 15:44:16.002044 VBOOT WORK 6. 99c18000 00014000
1821 15:44:16.005244 MRC DATA 7. 99c16000 00001958
1822 15:44:16.008825 ROMSTG STCK 8. 99c15000 00001000
1823 15:44:16.012152 AFTER CAR 9. 99c0b000 0000a000
1824 15:44:16.015195 RAMSTAGE 10. 99baf000 0005c000
1825 15:44:16.018638 REFCODE 11. 99b7a000 00035000
1826 15:44:16.021853 SMM BACKUP 12. 99b6a000 00010000
1827 15:44:16.025041 COREBOOT 13. 99b62000 00008000
1828 15:44:16.028339 ACPI 14. 99b3e000 00024000
1829 15:44:16.031777 ACPI GNVS 15. 99b3d000 00001000
1830 15:44:16.035263 RAMOOPS 16. 99a3d000 00100000
1831 15:44:16.038451 TPM2 TCGLOG17. 99a2d000 00010000
1832 15:44:16.041966 SMBIOS 18. 99a2c000 00000800
1833 15:44:16.045045 IMD small region:
1834 15:44:16.048557 IMD ROOT 0. 99ffec00 00000400
1835 15:44:16.051744 FSP RUNTIME 1. 99ffebe0 00000004
1836 15:44:16.055224 EC HOSTEVENT 2. 99ffebc0 00000008
1837 15:44:16.058392 POWER STATE 3. 99ffeb80 00000040
1838 15:44:16.061879 ROMSTAGE 4. 99ffeb60 00000004
1839 15:44:16.064990 MEM INFO 5. 99ffe9a0 000001b9
1840 15:44:16.068202 VPD 6. 99ffe920 0000006c
1841 15:44:16.071671 MTRR: Physical address space:
1842 15:44:16.078407 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1843 15:44:16.084888 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1844 15:44:16.091450 0x00000000000c0000 - 0x000000009b000000 size 0x9af40000 type 6
1845 15:44:16.094555 0x000000009b000000 - 0x00000000c0000000 size 0x25000000 type 0
1846 15:44:16.101517 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 1
1847 15:44:16.107836 0x00000000d0000000 - 0x0000000100000000 size 0x30000000 type 0
1848 15:44:16.114714 0x0000000100000000 - 0x000000045e800000 size 0x35e800000 type 6
1849 15:44:16.118220 MTRR: Fixed MSR 0x250 0x0606060606060606
1850 15:44:16.124819 MTRR: Fixed MSR 0x258 0x0606060606060606
1851 15:44:16.127982 MTRR: Fixed MSR 0x259 0x0000000000000000
1852 15:44:16.131120 MTRR: Fixed MSR 0x268 0x0606060606060606
1853 15:44:16.134700 MTRR: Fixed MSR 0x269 0x0606060606060606
1854 15:44:16.140866 MTRR: Fixed MSR 0x26a 0x0606060606060606
1855 15:44:16.144587 MTRR: Fixed MSR 0x26b 0x0606060606060606
1856 15:44:16.147638 MTRR: Fixed MSR 0x26c 0x0606060606060606
1857 15:44:16.151096 MTRR: Fixed MSR 0x26d 0x0606060606060606
1858 15:44:16.157835 MTRR: Fixed MSR 0x26e 0x0606060606060606
1859 15:44:16.160810 MTRR: Fixed MSR 0x26f 0x0606060606060606
1860 15:44:16.163858 call enable_fixed_mtrr()
1861 15:44:16.167588 CPU physical address size: 39 bits
1862 15:44:16.170740 MTRR: default type WB/UC MTRR counts: 6/8.
1863 15:44:16.174293 MTRR: WB selected as default type.
1864 15:44:16.180662 MTRR: 0 base 0x000000009b000000 mask 0x0000007fff000000 type 0
1865 15:44:16.187530 MTRR: 1 base 0x000000009c000000 mask 0x0000007ffc000000 type 0
1866 15:44:16.194212 MTRR: 2 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
1867 15:44:16.200651 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 1
1868 15:44:16.207198 MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 0
1869 15:44:16.213526 MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
1870 15:44:16.217253 MTRR: Fixed MSR 0x250 0x0606060606060606
1871 15:44:16.220350 MTRR: Fixed MSR 0x258 0x0606060606060606
1872 15:44:16.227213 MTRR: Fixed MSR 0x259 0x0000000000000000
1873 15:44:16.230308 MTRR: Fixed MSR 0x268 0x0606060606060606
1874 15:44:16.233488 MTRR: Fixed MSR 0x269 0x0606060606060606
1875 15:44:16.236922 MTRR: Fixed MSR 0x26a 0x0606060606060606
1876 15:44:16.239962 MTRR: Fixed MSR 0x26b 0x0606060606060606
1877 15:44:16.246921 MTRR: Fixed MSR 0x26c 0x0606060606060606
1878 15:44:16.249981 MTRR: Fixed MSR 0x26d 0x0606060606060606
1879 15:44:16.253467 MTRR: Fixed MSR 0x26e 0x0606060606060606
1880 15:44:16.256552 MTRR: Fixed MSR 0x26f 0x0606060606060606
1881 15:44:16.257049
1882 15:44:16.260214 MTRR check
1883 15:44:16.263625 Fixed MTRRs : Enabled
1884 15:44:16.264164 Variable MTRRs: Enabled
1885 15:44:16.264518
1886 15:44:16.266389 call enable_fixed_mtrr()
1887 15:44:16.272954 BS: BS_WRITE_TABLES times (ms): entry 0 run 9 exit 2
1888 15:44:16.276433 CPU physical address size: 39 bits
1889 15:44:16.282866 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1890 15:44:16.286348 MTRR: Fixed MSR 0x250 0x0606060606060606
1891 15:44:16.289720 MTRR: Fixed MSR 0x258 0x0606060606060606
1892 15:44:16.292790 MTRR: Fixed MSR 0x259 0x0000000000000000
1893 15:44:16.299549 MTRR: Fixed MSR 0x268 0x0606060606060606
1894 15:44:16.303049 MTRR: Fixed MSR 0x269 0x0606060606060606
1895 15:44:16.305966 MTRR: Fixed MSR 0x26a 0x0606060606060606
1896 15:44:16.309201 MTRR: Fixed MSR 0x26b 0x0606060606060606
1897 15:44:16.313094 MTRR: Fixed MSR 0x26c 0x0606060606060606
1898 15:44:16.319224 MTRR: Fixed MSR 0x26d 0x0606060606060606
1899 15:44:16.322580 MTRR: Fixed MSR 0x26e 0x0606060606060606
1900 15:44:16.326152 MTRR: Fixed MSR 0x26f 0x0606060606060606
1901 15:44:16.332870 MTRR: Fixed MSR 0x250 0x0606060606060606
1902 15:44:16.333381 call enable_fixed_mtrr()
1903 15:44:16.339302 MTRR: Fixed MSR 0x258 0x0606060606060606
1904 15:44:16.342604 MTRR: Fixed MSR 0x259 0x0000000000000000
1905 15:44:16.346056 MTRR: Fixed MSR 0x268 0x0606060606060606
1906 15:44:16.348972 MTRR: Fixed MSR 0x269 0x0606060606060606
1907 15:44:16.352585 MTRR: Fixed MSR 0x26a 0x0606060606060606
1908 15:44:16.359349 MTRR: Fixed MSR 0x26b 0x0606060606060606
1909 15:44:16.362394 MTRR: Fixed MSR 0x26c 0x0606060606060606
1910 15:44:16.365758 MTRR: Fixed MSR 0x26d 0x0606060606060606
1911 15:44:16.368959 MTRR: Fixed MSR 0x26e 0x0606060606060606
1912 15:44:16.375688 MTRR: Fixed MSR 0x26f 0x0606060606060606
1913 15:44:16.379110 CPU physical address size: 39 bits
1914 15:44:16.381882 call enable_fixed_mtrr()
1915 15:44:16.385473 MTRR: Fixed MSR 0x250 0x0606060606060606
1916 15:44:16.388694 MTRR: Fixed MSR 0x250 0x0606060606060606
1917 15:44:16.392257 MTRR: Fixed MSR 0x258 0x0606060606060606
1918 15:44:16.398879 MTRR: Fixed MSR 0x259 0x0000000000000000
1919 15:44:16.402022 MTRR: Fixed MSR 0x268 0x0606060606060606
1920 15:44:16.405383 MTRR: Fixed MSR 0x269 0x0606060606060606
1921 15:44:16.408404 MTRR: Fixed MSR 0x26a 0x0606060606060606
1922 15:44:16.415280 MTRR: Fixed MSR 0x26b 0x0606060606060606
1923 15:44:16.418196 MTRR: Fixed MSR 0x26c 0x0606060606060606
1924 15:44:16.421911 MTRR: Fixed MSR 0x26d 0x0606060606060606
1925 15:44:16.425048 MTRR: Fixed MSR 0x26e 0x0606060606060606
1926 15:44:16.431751 MTRR: Fixed MSR 0x26f 0x0606060606060606
1927 15:44:16.435144 MTRR: Fixed MSR 0x258 0x0606060606060606
1928 15:44:16.438147 call enable_fixed_mtrr()
1929 15:44:16.441680 CPU physical address size: 39 bits
1930 15:44:16.445139 MTRR: Fixed MSR 0x250 0x0606060606060606
1931 15:44:16.448403 MTRR: Fixed MSR 0x258 0x0606060606060606
1932 15:44:16.451266 MTRR: Fixed MSR 0x259 0x0000000000000000
1933 15:44:16.458023 MTRR: Fixed MSR 0x268 0x0606060606060606
1934 15:44:16.461635 MTRR: Fixed MSR 0x269 0x0606060606060606
1935 15:44:16.464537 MTRR: Fixed MSR 0x26a 0x0606060606060606
1936 15:44:16.468105 MTRR: Fixed MSR 0x26b 0x0606060606060606
1937 15:44:16.474467 MTRR: Fixed MSR 0x26c 0x0606060606060606
1938 15:44:16.477821 MTRR: Fixed MSR 0x26d 0x0606060606060606
1939 15:44:16.481216 MTRR: Fixed MSR 0x26e 0x0606060606060606
1940 15:44:16.484547 MTRR: Fixed MSR 0x26f 0x0606060606060606
1941 15:44:16.491445 MTRR: Fixed MSR 0x250 0x0606060606060606
1942 15:44:16.491881 call enable_fixed_mtrr()
1943 15:44:16.498146 MTRR: Fixed MSR 0x258 0x0606060606060606
1944 15:44:16.501358 MTRR: Fixed MSR 0x259 0x0000000000000000
1945 15:44:16.504496 MTRR: Fixed MSR 0x268 0x0606060606060606
1946 15:44:16.507884 MTRR: Fixed MSR 0x269 0x0606060606060606
1947 15:44:16.511561 MTRR: Fixed MSR 0x26a 0x0606060606060606
1948 15:44:16.517878 MTRR: Fixed MSR 0x26b 0x0606060606060606
1949 15:44:16.521268 MTRR: Fixed MSR 0x26c 0x0606060606060606
1950 15:44:16.524484 MTRR: Fixed MSR 0x26d 0x0606060606060606
1951 15:44:16.527947 MTRR: Fixed MSR 0x26e 0x0606060606060606
1952 15:44:16.534174 MTRR: Fixed MSR 0x26f 0x0606060606060606
1953 15:44:16.537392 CPU physical address size: 39 bits
1954 15:44:16.541238 call enable_fixed_mtrr()
1955 15:44:16.544383 CBFS @ c08000 size 3f8000
1956 15:44:16.547465 CPU physical address size: 39 bits
1957 15:44:16.550984 CPU physical address size: 39 bits
1958 15:44:16.554482 MTRR: Fixed MSR 0x259 0x0000000000000000
1959 15:44:16.557529 MTRR: Fixed MSR 0x268 0x0606060606060606
1960 15:44:16.560479 MTRR: Fixed MSR 0x269 0x0606060606060606
1961 15:44:16.567430 MTRR: Fixed MSR 0x26a 0x0606060606060606
1962 15:44:16.570396 MTRR: Fixed MSR 0x26b 0x0606060606060606
1963 15:44:16.573864 MTRR: Fixed MSR 0x26c 0x0606060606060606
1964 15:44:16.576756 MTRR: Fixed MSR 0x26d 0x0606060606060606
1965 15:44:16.583684 MTRR: Fixed MSR 0x26e 0x0606060606060606
1966 15:44:16.587290 MTRR: Fixed MSR 0x26f 0x0606060606060606
1967 15:44:16.593522 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1968 15:44:16.597035 CBFS: Locating 'fallback/payload'
1969 15:44:16.597499 call enable_fixed_mtrr()
1970 15:44:16.603335 CBFS: Found @ offset 1c96c0 size 3f798
1971 15:44:16.606721 CPU physical address size: 39 bits
1972 15:44:16.610157 Checking segment from ROM address 0xffdd16f8
1973 15:44:16.613755 Checking segment from ROM address 0xffdd1714
1974 15:44:16.619863 Loading segment from ROM address 0xffdd16f8
1975 15:44:16.620301 code (compression=0)
1976 15:44:16.629936 New segment dstaddr 0x30000000 memsize 0x657430 srcaddr 0xffdd1730 filesize 0x3f760
1977 15:44:16.639837 Loading Segment: addr: 0x30000000 memsz: 0x0000000000657430 filesz: 0x000000000003f760
1978 15:44:16.640229 it's not compressed!
1979 15:44:16.732922 [ 0x30000000, 3003f760, 0x30657430) <- ffdd1730
1980 15:44:16.739613 Clearing Segment: addr: 0x000000003003f760 memsz: 0x0000000000617cd0
1981 15:44:16.742740 Loading segment from ROM address 0xffdd1714
1982 15:44:16.745897 Entry Point 0x30000000
1983 15:44:16.749168 Loaded segments
1984 15:44:16.755235 Finalizing chipset.
1985 15:44:16.758203 Finalizing SMM.
1986 15:44:16.761263 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 88 exit 5
1987 15:44:16.764916 mp_park_aps done after 0 msecs.
1988 15:44:16.771399 Jumping to boot code at 30000000(99b62000)
1989 15:44:16.778051 CPU0: stack: 99bf9000 - 99bfa000, lowest used address 99bf99d8, stack used: 1576 bytes
1990 15:44:16.778493
1991 15:44:16.781121 Starting depthcharge on Helios...
1992 15:44:16.782182 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
1993 15:44:16.782710 start: 2.2.4 bootloader-commands (timeout 00:04:41) [common]
1994 15:44:16.783142 Setting prompt string to ['hatch:']
1995 15:44:16.783550 bootloader-commands: Wait for prompt ['hatch:'] (timeout 00:04:41)
1996 15:44:16.791076 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
1997 15:44:16.797943 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
1998 15:44:16.804423 board_setup: Info: eMMC controller not present; skipping
1999 15:44:16.807653 New NVMe Controller 0x30053ac0 @ 00:1d:00
2000 15:44:16.814139 board_setup: Info: SDHCI controller not present; skipping
2001 15:44:16.820861 vboot_create_vbsd: creating legacy VbSharedDataHeader structure
2002 15:44:16.821491 Wipe memory regions:
2003 15:44:16.823971 [0x00000000001000, 0x000000000a0000)
2004 15:44:16.830704 [0x00000000100000, 0x00000030000000)
2005 15:44:16.897487 [0x00000030657430, 0x00000099a2c000)
2006 15:44:17.047103 [0x00000100000000, 0x0000045e800000)
2007 15:44:18.502668 R8152: Initializing
2008 15:44:18.506283 Version 9 (ocp_data = 6010)
2009 15:44:18.510477 R8152: Done initializing
2010 15:44:18.513455 Adding net device
2011 15:44:18.888315 [firmware-hatch-12672.B-collabora] Jul 21 2021 08:27:58
2012 15:44:18.888463
2013 15:44:18.888759 Setting prompt string to ['hatch:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n']
2015 15:44:18.989553 hatch: tftpboot 192.168.201.1 7300442/tftp-deploy-ux950rm4/kernel/bzImage 7300442/tftp-deploy-ux950rm4/kernel/cmdline 7300442/tftp-deploy-ux950rm4/ramdisk/ramdisk.cpio.gz
2016 15:44:18.989700 Setting prompt string to 'Starting kernel'
2017 15:44:18.989785 Setting prompt string to ['Starting kernel']
2018 15:44:18.989858 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n']
2019 15:44:18.989936 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n'] (timeout 00:04:38)
2020 15:44:18.993912 tftpboot 192.168.201.1 7300442/tftp-deploy-ux950rm4/kernel/bzImy-ux950rm4/kernel/cmdline 7300442/tftp-deploy-ux950rm4/ramdisk/ramdisk.cpio.gz
2021 15:44:18.994020 Waiting for link
2022 15:44:19.195301 done.
2023 15:44:19.195786 MAC: f4:f5:e8:50:e3:ec
2024 15:44:19.198481 Sending DHCP discover... done.
2025 15:44:19.201973 Waiting for reply... done.
2026 15:44:19.205085 Sending DHCP request... done.
2027 15:44:19.208417 Waiting for reply... done.
2028 15:44:19.211340 My ip is 192.168.201.14
2029 15:44:19.215008 The DHCP server ip is 192.168.201.1
2030 15:44:19.217839 TFTP server IP predefined by user: 192.168.201.1
2031 15:44:19.224351 Bootfile predefined by user: 7300442/tftp-deploy-ux950rm4/kernel/bzImage
2032 15:44:19.227964 Sending tftp read request... done.
2033 15:44:19.234362 Waiting for the transfer...
2034 15:44:19.475441 00000000 ################################################################
2035 15:44:19.711096 00080000 ################################################################
2036 15:44:19.947101 00100000 ################################################################
2037 15:44:20.191799 00180000 ################################################################
2038 15:44:20.436327 00200000 ################################################################
2039 15:44:20.687452 00280000 ################################################################
2040 15:44:20.942200 00300000 ################################################################
2041 15:44:21.199521 00380000 ################################################################
2042 15:44:21.442004 00400000 ################################################################
2043 15:44:21.684251 00480000 ################################################################
2044 15:44:21.912028 00500000 ################################################################
2045 15:44:22.141431 00580000 ################################################################
2046 15:44:22.371268 00600000 ################################################################ done.
2047 15:44:22.374645 The bootfile was 6815632 bytes long.
2048 15:44:22.377777 Sending tftp read request... done.
2049 15:44:22.380784 Waiting for the transfer...
2050 15:44:22.613302 00000000 ################################################################
2051 15:44:22.838984 00080000 ################################################################
2052 15:44:23.077957 00100000 ################################################################
2053 15:44:23.310484 00180000 ################################################################
2054 15:44:23.541023 00200000 ################################################################
2055 15:44:23.775485 00280000 ################################################################
2056 15:44:24.004993 00300000 ################################################################
2057 15:44:24.232588 00380000 ################################################################
2058 15:44:24.464525 00400000 ################################################################
2059 15:44:24.699957 00480000 ################################################################
2060 15:44:24.811481 00500000 ############################# done.
2061 15:44:24.814736 Sending tftp read request... done.
2062 15:44:24.817916 Waiting for the transfer...
2063 15:44:24.818010 00000000 # done.
2064 15:44:24.827706 Command line loaded dynamically from TFTP file: 7300442/tftp-deploy-ux950rm4/kernel/cmdline
2065 15:44:24.850724 The command line is: earlyprintk=uart8250,mmio32,0xfedc6000,115200n8 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/7300442/extract-nfsrootfs-bp4laq2o,tcp,hard ip=dhcp tftpserverip=192.168.201.1
2066 15:44:24.854300 ec_init(0): CrosEC protocol v3 supported (256, 256)
2067 15:44:24.863661 Shutting down all USB controllers.
2068 15:44:24.863752 Removing current net device
2069 15:44:24.867441 Finalizing coreboot
2070 15:44:24.873876 Exiting depthcharge with code 4 at timestamp: 15370443
2071 15:44:24.873965
2072 15:44:24.874050 Starting kernel ...
2073 15:44:24.874126
2074 15:44:24.874194
2075 15:44:24.874505 end: 2.2.4 bootloader-commands (duration 00:00:08) [common]
2076 15:44:24.874633 start: 2.2.5 auto-login-action (timeout 00:04:32) [common]
2077 15:44:24.874723 Setting prompt string to ['Linux version [0-9]']
2078 15:44:24.874803 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n']
2079 15:44:24.874900 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n'] (timeout 00:05:00)
2081 15:48:56.874894 end: 2.2.5 auto-login-action (duration 00:04:32) [common]
2083 15:48:56.875137 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 272 seconds'
2085 15:48:56.875318 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2088 15:48:56.875650 end: 2 depthcharge-action (duration 00:05:00) [common]
2090 15:48:56.875910 Cleaning after the job
2091 15:48:56.876005 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/7300442/tftp-deploy-ux950rm4/ramdisk
2092 15:48:56.876558 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/7300442/tftp-deploy-ux950rm4/kernel
2093 15:48:56.877155 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/7300442/tftp-deploy-ux950rm4/nfsrootfs
2094 15:48:56.932924 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/7300442/tftp-deploy-ux950rm4/modules
2095 15:48:56.933332 start: 4.1 power-off (timeout 00:00:30) [common]
2096 15:48:56.933561 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-4' '--port=1' '--command=off'
2097 15:48:56.955247 >> Command sent successfully.
2098 15:48:56.957340 Returned 0 in 0 seconds
2099 15:48:57.058102 end: 4.1 power-off (duration 00:00:00) [common]
2101 15:48:57.058473 start: 4.2 read-feedback (timeout 00:10:00) [common]
2102 15:48:57.058765 Listened to connection for namespace 'common' for up to 1s
2103 15:48:57.498564 Listened to connection for namespace 'common' for up to 1s
2104 15:48:57.502150 Listened to connection for namespace 'common' for up to 1s
2105 15:48:57.505408 Listened to connection for namespace 'common' for up to 1s
2106 15:48:57.508336 Listened to connection for namespace 'common' for up to 1s
2107 15:48:57.512038 Listened to connection for namespace 'common' for up to 1s
2108 15:48:57.514980 Listened to connection for namespace 'common' for up to 1s
2109 15:48:57.518315 Listened to connection for namespace 'common' for up to 1s
2110 15:48:57.521920 Listened to connection for namespace 'common' for up to 1s
2111 15:48:57.525024 Listened to connection for namespace 'common' for up to 1s
2112 15:48:57.528093 Listened to connection for namespace 'common' for up to 1s
2113 15:48:57.531466 Listened to connection for namespace 'common' for up to 1s
2114 15:48:57.534907 Listened to connection for namespace 'common' for up to 1s
2115 15:48:57.538415 Listened to connection for namespace 'common' for up to 1s
2116 15:48:57.541719 Listened to connection for namespace 'common' for up to 1s
2117 15:48:57.544932 Listened to connection for namespace 'common' for up to 1s
2118 15:48:57.548470 Listened to connection for namespace 'common' for up to 1s
2119 15:48:57.554364 Listened to connection for namespace 'common' for up to 1s
2120 15:48:57.557880 Listened to connection for namespace 'common' for up to 1s
2121 15:48:58.061188 Finalising connection for namespace 'common'
2122 15:48:58.061401 Disconnecting from shell: Finalise
2123 15:48:58.061521
2124 15:48:58.162302 end: 4.2 read-feedback (duration 00:00:01) [common]
2125 15:48:58.162452 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/7300442
2126 15:48:58.325797 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/7300442
2127 15:48:58.326006 JobError: Your job cannot terminate cleanly.