Boot log: asus-cx9400-volteer
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: FAIL
- Kernel Errors: 0
1 14:47:45.194033 lava-dispatcher, installed at version: 2022.06
2 14:47:45.194212 start: 0 validate
3 14:47:45.194339 Start time: 2022-09-30 14:47:45.194333+00:00 (UTC)
4 14:47:45.194471 Using caching service: 'http://localhost/cache/?uri=%s'
5 14:47:45.194596 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20220919.0%2Fx86%2Frootfs.cpio.gz exists
6 14:47:45.197403 Using caching service: 'http://localhost/cache/?uri=%s'
7 14:47:45.197520 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv4.4.302-cip70-98-gb2bfffe124dae%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 14:47:45.488384 Using caching service: 'http://localhost/cache/?uri=%s'
9 14:47:45.488534 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv4.4.302-cip70-98-gb2bfffe124dae%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 14:47:45.491566 validate duration: 0.30
12 14:47:45.491808 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 14:47:45.491977 start: 1.1 download-retry (timeout 00:10:00) [common]
14 14:47:45.492065 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 14:47:45.492161 Not decompressing ramdisk as can be used compressed.
16 14:47:45.492244 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20220919.0/x86/rootfs.cpio.gz
17 14:47:45.492310 saving as /var/lib/lava/dispatcher/tmp/7462822/tftp-deploy-64hlhhce/ramdisk/rootfs.cpio.gz
18 14:47:45.492370 total size: 8415689 (8MB)
19 14:47:45.494536 progress 0% (0MB)
20 14:47:45.497944 progress 5% (0MB)
21 14:47:45.501591 progress 10% (0MB)
22 14:47:45.505629 progress 15% (1MB)
23 14:47:45.509161 progress 20% (1MB)
24 14:47:45.513721 progress 25% (2MB)
25 14:47:45.517375 progress 30% (2MB)
26 14:47:45.520799 progress 35% (2MB)
27 14:47:45.524550 progress 40% (3MB)
28 14:47:45.528924 progress 45% (3MB)
29 14:47:45.533100 progress 50% (4MB)
30 14:47:45.536615 progress 55% (4MB)
31 14:47:45.540278 progress 60% (4MB)
32 14:47:45.543636 progress 65% (5MB)
33 14:47:45.548046 progress 70% (5MB)
34 14:47:45.551998 progress 75% (6MB)
35 14:47:45.555560 progress 80% (6MB)
36 14:47:45.559761 progress 85% (6MB)
37 14:47:45.563051 progress 90% (7MB)
38 14:47:45.567188 progress 95% (7MB)
39 14:47:45.571012 progress 100% (8MB)
40 14:47:45.571291 8MB downloaded in 0.08s (101.70MB/s)
41 14:47:45.571444 end: 1.1.1 http-download (duration 00:00:00) [common]
43 14:47:45.571692 end: 1.1 download-retry (duration 00:00:00) [common]
44 14:47:45.571781 start: 1.2 download-retry (timeout 00:10:00) [common]
45 14:47:45.571935 start: 1.2.1 http-download (timeout 00:10:00) [common]
46 14:47:45.572044 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v4.4.302-cip70-98-gb2bfffe124dae/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 14:47:45.572112 saving as /var/lib/lava/dispatcher/tmp/7462822/tftp-deploy-64hlhhce/kernel/bzImage
48 14:47:45.572174 total size: 7126928 (6MB)
49 14:47:45.572235 No compression specified
50 14:47:45.574244 progress 0% (0MB)
51 14:47:45.577469 progress 5% (0MB)
52 14:47:45.580703 progress 10% (0MB)
53 14:47:45.584067 progress 15% (1MB)
54 14:47:45.587606 progress 20% (1MB)
55 14:47:45.590536 progress 25% (1MB)
56 14:47:45.594149 progress 30% (2MB)
57 14:47:45.597443 progress 35% (2MB)
58 14:47:45.600377 progress 40% (2MB)
59 14:47:45.603741 progress 45% (3MB)
60 14:47:45.606861 progress 50% (3MB)
61 14:47:45.610174 progress 55% (3MB)
62 14:47:45.613802 progress 60% (4MB)
63 14:47:45.617419 progress 65% (4MB)
64 14:47:45.620720 progress 70% (4MB)
65 14:47:45.623373 progress 75% (5MB)
66 14:47:45.626211 progress 80% (5MB)
67 14:47:45.629498 progress 85% (5MB)
68 14:47:45.633405 progress 90% (6MB)
69 14:47:45.636254 progress 95% (6MB)
70 14:47:45.639702 progress 100% (6MB)
71 14:47:45.639964 6MB downloaded in 0.07s (100.27MB/s)
72 14:47:45.640118 end: 1.2.1 http-download (duration 00:00:00) [common]
74 14:47:45.640356 end: 1.2 download-retry (duration 00:00:00) [common]
75 14:47:45.640445 start: 1.3 download-retry (timeout 00:10:00) [common]
76 14:47:45.640538 start: 1.3.1 http-download (timeout 00:10:00) [common]
77 14:47:45.640644 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v4.4.302-cip70-98-gb2bfffe124dae/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 14:47:45.640712 saving as /var/lib/lava/dispatcher/tmp/7462822/tftp-deploy-64hlhhce/modules/modules.tar
79 14:47:45.640772 total size: 52080 (0MB)
80 14:47:45.640832 Using unxz to decompress xz
81 14:47:45.644789 progress 62% (0MB)
82 14:47:45.645152 progress 100% (0MB)
83 14:47:45.648453 0MB downloaded in 0.01s (6.47MB/s)
84 14:47:45.648683 end: 1.3.1 http-download (duration 00:00:00) [common]
86 14:47:45.648943 end: 1.3 download-retry (duration 00:00:00) [common]
87 14:47:45.649040 start: 1.4 prepare-tftp-overlay (timeout 00:10:00) [common]
88 14:47:45.649132 start: 1.4.1 extract-nfsrootfs (timeout 00:10:00) [common]
89 14:47:45.649219 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
90 14:47:45.649307 start: 1.4.2 lava-overlay (timeout 00:10:00) [common]
91 14:47:45.649469 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1
92 14:47:45.649602 makedir: /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin
93 14:47:45.649702 makedir: /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/tests
94 14:47:45.649782 makedir: /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/results
95 14:47:45.649920 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-add-keys
96 14:47:45.650045 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-add-sources
97 14:47:45.650158 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-background-process-start
98 14:47:45.650267 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-background-process-stop
99 14:47:45.650376 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-common-functions
100 14:47:45.650484 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-echo-ipv4
101 14:47:45.650597 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-install-packages
102 14:47:45.650706 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-installed-packages
103 14:47:45.650813 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-os-build
104 14:47:45.650922 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-probe-channel
105 14:47:45.651029 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-probe-ip
106 14:47:45.651136 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-target-ip
107 14:47:45.651243 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-target-mac
108 14:47:45.651348 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-target-storage
109 14:47:45.651460 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-test-case
110 14:47:45.651568 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-test-event
111 14:47:45.651674 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-test-feedback
112 14:47:45.651781 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-test-raise
113 14:47:45.651902 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-test-reference
114 14:47:45.652010 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-test-runner
115 14:47:45.652116 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-test-set
116 14:47:45.652222 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-test-shell
117 14:47:45.652331 Updating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-install-packages (oe)
118 14:47:45.652442 Updating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/bin/lava-installed-packages (oe)
119 14:47:45.652541 Creating /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/environment
120 14:47:45.652629 LAVA metadata
121 14:47:45.652701 - LAVA_JOB_ID=7462822
122 14:47:45.652765 - LAVA_DISPATCHER_IP=192.168.201.1
123 14:47:45.652868 start: 1.4.2.1 lava-vland-overlay (timeout 00:10:00) [common]
124 14:47:45.652933 skipped lava-vland-overlay
125 14:47:45.653008 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
126 14:47:45.653092 start: 1.4.2.2 lava-multinode-overlay (timeout 00:10:00) [common]
127 14:47:45.653154 skipped lava-multinode-overlay
128 14:47:45.653227 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
129 14:47:45.653308 start: 1.4.2.3 test-definition (timeout 00:10:00) [common]
130 14:47:45.653381 Loading test definitions
131 14:47:45.653477 start: 1.4.2.3.1 inline-repo-action (timeout 00:10:00) [common]
132 14:47:45.653553 Using /lava-7462822 at stage 0
133 14:47:45.653810 uuid=7462822_1.4.2.3.1 testdef=None
134 14:47:45.653900 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
135 14:47:45.653989 start: 1.4.2.3.2 test-overlay (timeout 00:10:00) [common]
136 14:47:45.654482 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
138 14:47:45.654712 start: 1.4.2.3.3 test-install-overlay (timeout 00:10:00) [common]
139 14:47:45.655285 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
141 14:47:45.655527 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:10:00) [common]
142 14:47:45.656113 runner path: /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/0/tests/0_dmesg test_uuid 7462822_1.4.2.3.1
143 14:47:45.656263 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
145 14:47:45.656509 start: 1.4.2.3.5 inline-repo-action (timeout 00:10:00) [common]
146 14:47:45.656583 Using /lava-7462822 at stage 1
147 14:47:45.656822 uuid=7462822_1.4.2.3.5 testdef=None
148 14:47:45.656911 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
149 14:47:45.656999 start: 1.4.2.3.6 test-overlay (timeout 00:10:00) [common]
150 14:47:45.657439 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
152 14:47:45.657662 start: 1.4.2.3.7 test-install-overlay (timeout 00:10:00) [common]
153 14:47:45.658230 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
155 14:47:45.658470 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:10:00) [common]
156 14:47:45.659014 runner path: /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/1/tests/1_bootrr test_uuid 7462822_1.4.2.3.5
157 14:47:45.659155 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
159 14:47:45.659366 Creating lava-test-runner.conf files
160 14:47:45.659431 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/0 for stage 0
161 14:47:45.659511 - 0_dmesg
162 14:47:45.659584 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/7462822/lava-overlay-n4gwe8q1/lava-7462822/1 for stage 1
163 14:47:45.659666 - 1_bootrr
164 14:47:45.659756 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
165 14:47:45.659867 start: 1.4.2.4 compress-overlay (timeout 00:10:00) [common]
166 14:47:45.665879 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
167 14:47:45.665990 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:10:00) [common]
168 14:47:45.666079 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
169 14:47:45.666165 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
170 14:47:45.666251 start: 1.4.3 extract-overlay-ramdisk (timeout 00:10:00) [common]
171 14:47:45.848083 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
172 14:47:45.848418 start: 1.4.4 extract-modules (timeout 00:10:00) [common]
173 14:47:45.848525 extracting modules file /var/lib/lava/dispatcher/tmp/7462822/tftp-deploy-64hlhhce/modules/modules.tar to /var/lib/lava/dispatcher/tmp/7462822/extract-overlay-ramdisk-42hsjz4x/ramdisk
174 14:47:45.852585 end: 1.4.4 extract-modules (duration 00:00:00) [common]
175 14:47:45.852695 start: 1.4.5 apply-overlay-tftp (timeout 00:10:00) [common]
176 14:47:45.852780 [common] Applying overlay /var/lib/lava/dispatcher/tmp/7462822/compress-overlay-dm18hho1/overlay-1.4.2.4.tar.gz to ramdisk
177 14:47:45.852853 [common] Applying overlay /var/lib/lava/dispatcher/tmp/7462822/compress-overlay-dm18hho1/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/7462822/extract-overlay-ramdisk-42hsjz4x/ramdisk
178 14:47:45.856636 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
179 14:47:45.856745 start: 1.4.6 configure-preseed-file (timeout 00:10:00) [common]
180 14:47:45.856837 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
181 14:47:45.856928 start: 1.4.7 compress-ramdisk (timeout 00:10:00) [common]
182 14:47:45.857006 Building ramdisk /var/lib/lava/dispatcher/tmp/7462822/extract-overlay-ramdisk-42hsjz4x/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/7462822/extract-overlay-ramdisk-42hsjz4x/ramdisk
183 14:47:45.919016 >> 48008 blocks
184 14:47:46.663055 rename /var/lib/lava/dispatcher/tmp/7462822/extract-overlay-ramdisk-42hsjz4x/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/7462822/tftp-deploy-64hlhhce/ramdisk/ramdisk.cpio.gz
185 14:47:46.663448 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
186 14:47:46.663614 start: 1.4.8 prepare-kernel (timeout 00:09:59) [common]
187 14:47:46.663719 start: 1.4.8.1 prepare-fit (timeout 00:09:59) [common]
188 14:47:46.663812 No mkimage arch provided, not using FIT.
189 14:47:46.663943 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
190 14:47:46.664030 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
191 14:47:46.664129 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
192 14:47:46.664223 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:59) [common]
193 14:47:46.664301 No LXC device requested
194 14:47:46.664382 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
195 14:47:46.664470 start: 1.6 deploy-device-env (timeout 00:09:59) [common]
196 14:47:46.664551 end: 1.6 deploy-device-env (duration 00:00:00) [common]
197 14:47:46.664620 Checking files for TFTP limit of 4294967296 bytes.
198 14:47:46.665006 end: 1 tftp-deploy (duration 00:00:01) [common]
199 14:47:46.665110 start: 2 depthcharge-action (timeout 00:05:00) [common]
200 14:47:46.665207 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
201 14:47:46.665331 substitutions:
202 14:47:46.665398 - {DTB}: None
203 14:47:46.665464 - {INITRD}: 7462822/tftp-deploy-64hlhhce/ramdisk/ramdisk.cpio.gz
204 14:47:46.665524 - {KERNEL}: 7462822/tftp-deploy-64hlhhce/kernel/bzImage
205 14:47:46.665583 - {LAVA_MAC}: None
206 14:47:46.665640 - {PRESEED_CONFIG}: None
207 14:47:46.665700 - {PRESEED_LOCAL}: None
208 14:47:46.665756 - {RAMDISK}: 7462822/tftp-deploy-64hlhhce/ramdisk/ramdisk.cpio.gz
209 14:47:46.665812 - {ROOT_PART}: None
210 14:47:46.665867 - {ROOT}: None
211 14:47:46.665922 - {SERVER_IP}: 192.168.201.1
212 14:47:46.665976 - {TEE}: None
213 14:47:46.666031 Parsed boot commands:
214 14:47:46.666104 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
215 14:47:46.666263 Parsed boot commands: tftpboot 192.168.201.1 7462822/tftp-deploy-64hlhhce/kernel/bzImage 7462822/tftp-deploy-64hlhhce/kernel/cmdline 7462822/tftp-deploy-64hlhhce/ramdisk/ramdisk.cpio.gz
216 14:47:46.666356 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
217 14:47:46.666445 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
218 14:47:46.666544 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
219 14:47:46.666631 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
220 14:47:46.666702 Not connected, no need to disconnect.
221 14:47:46.666780 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
222 14:47:46.666861 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
223 14:47:46.666928 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost asus-cx9400-volteer-cbg-10'
224 14:47:46.669511 Setting prompt string to ['lava-test: # ']
225 14:47:46.669795 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
226 14:47:46.669898 end: 2.2.1 reset-connection (duration 00:00:00) [common]
227 14:47:46.670014 start: 2.2.2 reset-device (timeout 00:05:00) [common]
228 14:47:46.670108 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
229 14:47:46.670283 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-10' '--port=1' '--command=reboot'
230 14:47:46.688865 >> Command sent successfully.
231 14:47:46.690694 Returned 0 in 0 seconds
232 14:47:46.791437 end: 2.2.2.1 pdu-reboot (duration 00:00:00) [common]
234 14:47:46.792035 end: 2.2.2 reset-device (duration 00:00:00) [common]
235 14:47:46.792135 start: 2.2.3 depthcharge-start (timeout 00:05:00) [common]
236 14:47:46.792220 Setting prompt string to 'Starting depthcharge on Voema...'
237 14:47:46.792285 Changing prompt to 'Starting depthcharge on Voema...'
238 14:47:46.792353 depthcharge-start: Wait for prompt Starting depthcharge on Voema... (timeout 00:05:00)
239 14:47:46.792613 [Enter `^Ec?' for help]
240 14:47:53.827239
241 14:47:53.827854
242 14:47:53.837561 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 bootblock starting (log level: 8)...
243 14:47:53.844072 CPU: 11th Gen Intel(R) Core(TM) i7-1160G7 @ 1.20GHz
244 14:47:53.847440 CPU: ID 806c1, Tigerlake B0, ucode: 00000086
245 14:47:53.850916 CPU: AES supported, TXT NOT supported, VT supported
246 14:47:53.857566 MCH: device id 9a12 (rev 01) is Tigerlake-Y-4-2
247 14:47:53.860648 PCH: device id a087 (rev 20) is Tigerlake-Y Premium SKU
248 14:47:53.868505 IGD: device id 9a40 (rev 01) is Tigerlake Y GT2
249 14:47:53.871456 VBOOT: Loading verstage.
250 14:47:53.874393 FMAP: Found \"FLASH\" version 1.1 at 0x1804000.
251 14:47:53.881610 FMAP: base = 0x0 size = 0x2000000 #areas = 32
252 14:47:53.884794 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
253 14:47:53.894900 CBFS: mcache @0xfef45600 built for 70 files, used 0xfdc of 0x1800 bytes
254 14:47:53.901752 CBFS: Found 'fallback/verstage' @0x165e40 size 0x147ec in mcache @0xfef45984
255 14:47:53.902324
256 14:47:53.902677
257 14:47:53.911740 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 verstage starting (log level: 8)...
258 14:47:53.928469 Probing TPM: . done!
259 14:47:53.931559 TPM ready after 0 ms
260 14:47:53.935014 Connected to device vid:did:rid of 1ae0:0028:00
261 14:47:53.946118 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.5.30/cr50_v1.9311_mp.7-535187521e
262 14:47:53.952358 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
263 14:47:53.955959 Initialized TPM device CR50 revision 0
264 14:47:54.012524 tlcl_send_startup: Startup return code is 0
265 14:47:54.013042 TPM: setup succeeded
266 14:47:54.028459 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
267 14:47:54.042269 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
268 14:47:54.054559 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
269 14:47:54.064518 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
270 14:47:54.068195 Chrome EC: UHEPI supported
271 14:47:54.071500 Phase 1
272 14:47:54.075172 FMAP: area GBB found @ 1805000 (458752 bytes)
273 14:47:54.084905 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
274 14:47:54.091535 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
275 14:47:54.098006 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
276 14:47:54.104430 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
277 14:47:54.108137 Recovery requested (1009000e)
278 14:47:54.111359 TPM: Extending digest for VBOOT: boot mode into PCR 0
279 14:47:54.123429 tlcl_extend: response is 0
280 14:47:54.129953 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
281 14:47:54.140253 tlcl_extend: response is 0
282 14:47:54.146438 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
283 14:47:54.152944 CBFS: Found 'fallback/romstage' @0x80 size 0x1bf24 in mcache @0xfef45638
284 14:47:54.160043 BS: verstage times (exec / console): total (unknown) / 142 ms
285 14:47:54.160205
286 14:47:54.160279
287 14:47:54.173040 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 romstage starting (log level: 8)...
288 14:47:54.179113 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
289 14:47:54.182669 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
290 14:47:54.185922 gpe0_sts[0]: 00200000 gpe0_en[0]: 00000000
291 14:47:54.192730 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
292 14:47:54.195722 gpe0_sts[2]: 00001000 gpe0_en[2]: 00000000
293 14:47:54.199111 gpe0_sts[3]: 00000000 gpe0_en[3]: 00092000
294 14:47:54.202341 TCO_STS: 0000 0000
295 14:47:54.205757 GEN_PMCON: d0015038 00002200
296 14:47:54.209182 GBLRST_CAUSE: 00000000 00000000
297 14:47:54.213013 HPR_CAUSE0: 00000000
298 14:47:54.213153 prev_sleep_state 5
299 14:47:54.215846 Boot Count incremented to 8198
300 14:47:54.222640 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
301 14:47:54.229346 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
302 14:47:54.239095 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
303 14:47:54.245944 CBFS: Found 'fspm.bin' @0x78fc0 size 0xa5000 in mcache @0xfef4585c
304 14:47:54.248933 Chrome EC: UHEPI supported
305 14:47:54.255345 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
306 14:47:54.266319 Probing TPM: done!
307 14:47:54.273063 Connected to device vid:did:rid of 1ae0:0028:00
308 14:47:54.283371 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.5.30/cr50_v1.9311_mp.7-535187521e
309 14:47:54.286581 Initialized TPM device CR50 revision 0
310 14:47:54.301285 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
311 14:47:54.307873 MRC: Hash idx 0x100b comparison successful.
312 14:47:54.311520 MRC cache found, size faa8
313 14:47:54.311650 bootmode is set to: 2
314 14:47:54.314870 SPD index = 2
315 14:47:54.321496 CBFS: Found 'spd.bin' @0x72940 size 0x600 in mcache @0xfef4579c
316 14:47:54.324959 SPD: module type is LPDDR4X
317 14:47:54.327609 SPD: module part number is MT53D1G64D4NW-046
318 14:47:54.334114 SPD: banks 8, ranks 1, rows 17, columns 10, density 16384 Mb
319 14:47:54.337903 SPD: device width 16 bits, bus width 16 bits
320 14:47:54.344013 SPD: module size is 2048 MB (per channel)
321 14:47:54.774817 CBMEM:
322 14:47:54.778234 IMD: root @ 0x76fff000 254 entries.
323 14:47:54.781186 IMD: root @ 0x76ffec00 62 entries.
324 14:47:54.784537 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
325 14:47:54.791200 FMAP: area RW_VPD found @ f35000 (8192 bytes)
326 14:47:54.794575 External stage cache:
327 14:47:54.797847 IMD: root @ 0x7b3ff000 254 entries.
328 14:47:54.801286 IMD: root @ 0x7b3fec00 62 entries.
329 14:47:54.815975 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
330 14:47:54.822970 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
331 14:47:54.829474 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
332 14:47:54.843262 MRC: 'RECOVERY_MRC_CACHE' does not need update.
333 14:47:54.849369 cse_lite: Skip switching to RW in the recovery path
334 14:47:54.849829 8 DIMMs found
335 14:47:54.850335 SMM Memory Map
336 14:47:54.856121 SMRAM : 0x7b000000 0x800000
337 14:47:54.859500 Subregion 0: 0x7b000000 0x200000
338 14:47:54.862793 Subregion 1: 0x7b200000 0x200000
339 14:47:54.866393 Subregion 2: 0x7b400000 0x400000
340 14:47:54.866824 top_of_ram = 0x77000000
341 14:47:54.872882 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
342 14:47:54.879562 MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
343 14:47:54.882765 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
344 14:47:54.889220 MTRR Range: Start=ff000000 End=0 (Size 1000000)
345 14:47:54.895741 CBFS: Found 'fallback/postcar' @0x160900 size 0x54f8 in mcache @0xfef4594c
346 14:47:54.902283 Decompressing stage fallback/postcar @ 0x76c0afc0 (38208 bytes)
347 14:47:54.913108 Loading module at 0x76c0b000 with entry 0x76c0b000. filesize: 0x5150 memsize: 0x9500
348 14:47:54.919349 Processing 211 relocs. Offset value of 0x74c0b000
349 14:47:54.925805 BS: romstage times (exec / console): total (unknown) / 276 ms
350 14:47:54.931474
351 14:47:54.931969
352 14:47:54.942454 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 postcar starting (log level: 8)...
353 14:47:54.945511 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
354 14:47:54.952093 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
355 14:47:54.961833 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
356 14:47:54.968644 CBFS: Found 'fallback/ramstage' @0x524c0 size 0x1fbe3 in mcache @0x76c4c0ec
357 14:47:54.975232 Decompressing stage fallback/ramstage @ 0x76b97fc0 (463536 bytes)
358 14:47:55.018520 Loading module at 0x76b98000 with entry 0x76b98000. filesize: 0x4d5d8 memsize: 0x71270
359 14:47:55.024979 Processing 5008 relocs. Offset value of 0x75d98000
360 14:47:55.029161 BS: postcar times (exec / console): total (unknown) / 59 ms
361 14:47:55.029593
362 14:47:55.031638
363 14:47:55.041621 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 ramstage starting (log level: 8)...
364 14:47:55.042060 Normal boot
365 14:47:55.044839 FW_CONFIG value is 0x804c02
366 14:47:55.048141 PCI: 00:07.0 disabled by fw_config
367 14:47:55.051199 PCI: 00:07.1 disabled by fw_config
368 14:47:55.058190 PCI: 00:0d.2 disabled by fw_config
369 14:47:55.061823 PCI: 00:1c.7 disabled by fw_config
370 14:47:55.064573 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
371 14:47:55.071251 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
372 14:47:55.077998 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
373 14:47:55.081057 GENERIC: 0.0 disabled by fw_config
374 14:47:55.084637 GENERIC: 1.0 disabled by fw_config
375 14:47:55.087744 fw_config match found: DB_USB=USB3_ACTIVE
376 14:47:55.091390 fw_config match found: DB_USB=USB3_ACTIVE
377 14:47:55.094606 fw_config match found: DB_USB=USB3_ACTIVE
378 14:47:55.101257 fw_config match found: DB_USB=USB3_ACTIVE
379 14:47:55.104472 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
380 14:47:55.114142 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
381 14:47:55.121265 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
382 14:47:55.127816 CBFS: Found 'cpu_microcode_blob.bin' @0x1c040 size 0x36400 in mcache @0x76c4c09c
383 14:47:55.134191 microcode: sig=0x806c1 pf=0x80 revision=0x86
384 14:47:55.137325 microcode: Update skipped, already up-to-date
385 14:47:55.144082 CBFS: Found 'fsps.bin' @0x11efc0 size 0x418f9 in mcache @0x76c4c30c
386 14:47:55.172395 Detected 4 core, 8 thread CPU.
387 14:47:55.175817 Setting up SMI for CPU
388 14:47:55.178825 IED base = 0x7b400000
389 14:47:55.179385 IED size = 0x00400000
390 14:47:55.182257 Will perform SMM setup.
391 14:47:55.188784 CPU: 11th Gen Intel(R) Core(TM) i7-1160G7 @ 1.20GHz.
392 14:47:55.195358 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
393 14:47:55.201939 Processing 16 relocs. Offset value of 0x00030000
394 14:47:55.205430 Attempting to start 7 APs
395 14:47:55.208725 Waiting for 10ms after sending INIT.
396 14:47:55.223912 Waiting for 1st SIPI to complete...AP: slot 1 apic_id 1.
397 14:47:55.227200 AP: slot 3 apic_id 5.
398 14:47:55.230625 AP: slot 2 apic_id 3.
399 14:47:55.231056 AP: slot 6 apic_id 2.
400 14:47:55.234355 AP: slot 7 apic_id 4.
401 14:47:55.237504 AP: slot 5 apic_id 6.
402 14:47:55.237934 AP: slot 4 apic_id 7.
403 14:47:55.238274 done.
404 14:47:55.244064 Waiting for 2nd SIPI to complete...done.
405 14:47:55.250812 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
406 14:47:55.257202 Processing 13 relocs. Offset value of 0x00038000
407 14:47:55.260248 Unable to locate Global NVS
408 14:47:55.267100 SMM Module: stub loaded at 0x00038000. Will call 0x76bb6318(0x00000000)
409 14:47:55.270379 Installing permanent SMM handler to 0x7b000000
410 14:47:55.280358 Loading module at 0x7b010000 with entry 0x7b010c16. filesize: 0xa7c8 memsize: 0xf908
411 14:47:55.283759 Processing 794 relocs. Offset value of 0x7b010000
412 14:47:55.293485 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8
413 14:47:55.296930 Processing 13 relocs. Offset value of 0x7b008000
414 14:47:55.303732 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
415 14:47:55.310261 SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
416 14:47:55.313203 SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
417 14:47:55.320205 SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
418 14:47:55.326676 SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
419 14:47:55.333143 SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
420 14:47:55.340104 SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
421 14:47:55.343410 Unable to locate Global NVS
422 14:47:55.349966 SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c16(0x00000000)
423 14:47:55.353402 Clearing SMI status registers
424 14:47:55.353840 SMI_STS: PM1
425 14:47:55.356447 PM1_STS: PWRBTN
426 14:47:55.363150 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
427 14:47:55.366235 In relocation handler: CPU 0
428 14:47:55.369911 New SMBASE=0x7b000000 IEDBASE=0x7b400000
429 14:47:55.376432 Writing SMRR. base = 0x7b000006, mask=0xff800c00
430 14:47:55.379278 Relocation complete.
431 14:47:55.386164 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
432 14:47:55.389494 In relocation handler: CPU 1
433 14:47:55.392990 New SMBASE=0x7afffc00 IEDBASE=0x7b400000
434 14:47:55.393424 Relocation complete.
435 14:47:55.402995 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
436 14:47:55.403423 In relocation handler: CPU 4
437 14:47:55.409632 New SMBASE=0x7afff000 IEDBASE=0x7b400000
438 14:47:55.410064 Relocation complete.
439 14:47:55.419309 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
440 14:47:55.419772 In relocation handler: CPU 5
441 14:47:55.425962 New SMBASE=0x7affec00 IEDBASE=0x7b400000
442 14:47:55.429276 Writing SMRR. base = 0x7b000006, mask=0xff800c00
443 14:47:55.432770 Relocation complete.
444 14:47:55.439391 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
445 14:47:55.442728 In relocation handler: CPU 7
446 14:47:55.445823 New SMBASE=0x7affe400 IEDBASE=0x7b400000
447 14:47:55.452422 Writing SMRR. base = 0x7b000006, mask=0xff800c00
448 14:47:55.452857 Relocation complete.
449 14:47:55.459394 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
450 14:47:55.462514 In relocation handler: CPU 3
451 14:47:55.469082 New SMBASE=0x7afff400 IEDBASE=0x7b400000
452 14:47:55.469523 Relocation complete.
453 14:47:55.475700 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
454 14:47:55.479346 In relocation handler: CPU 2
455 14:47:55.485719 New SMBASE=0x7afff800 IEDBASE=0x7b400000
456 14:47:55.486158 Relocation complete.
457 14:47:55.492461 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
458 14:47:55.495875 In relocation handler: CPU 6
459 14:47:55.502516 New SMBASE=0x7affe800 IEDBASE=0x7b400000
460 14:47:55.505378 Writing SMRR. base = 0x7b000006, mask=0xff800c00
461 14:47:55.508894 Relocation complete.
462 14:47:55.509337 Initializing CPU #0
463 14:47:55.512211 CPU: vendor Intel device 806c1
464 14:47:55.515602 CPU: family 06, model 8c, stepping 01
465 14:47:55.518588 Clearing out pending MCEs
466 14:47:55.521845 Setting up local APIC...
467 14:47:55.525484 apic_id: 0x00 done.
468 14:47:55.528746 Turbo is available but hidden
469 14:47:55.531942 Turbo is available and visible
470 14:47:55.535262 microcode: Update skipped, already up-to-date
471 14:47:55.538637 CPU #0 initialized
472 14:47:55.539076 Initializing CPU #5
473 14:47:55.542168 Initializing CPU #1
474 14:47:55.545322 CPU: vendor Intel device 806c1
475 14:47:55.548723 CPU: family 06, model 8c, stepping 01
476 14:47:55.551872 Initializing CPU #4
477 14:47:55.552316 Initializing CPU #2
478 14:47:55.555317 Initializing CPU #6
479 14:47:55.558652 CPU: vendor Intel device 806c1
480 14:47:55.561760 CPU: family 06, model 8c, stepping 01
481 14:47:55.564968 CPU: vendor Intel device 806c1
482 14:47:55.568407 CPU: family 06, model 8c, stepping 01
483 14:47:55.571506 Clearing out pending MCEs
484 14:47:55.574996 Clearing out pending MCEs
485 14:47:55.575429 Setting up local APIC...
486 14:47:55.578294 CPU: vendor Intel device 806c1
487 14:47:55.584929 CPU: family 06, model 8c, stepping 01
488 14:47:55.585396 apic_id: 0x03 done.
489 14:47:55.588284 Initializing CPU #3
490 14:47:55.588718 Initializing CPU #7
491 14:47:55.591631 CPU: vendor Intel device 806c1
492 14:47:55.595914 CPU: family 06, model 8c, stepping 01
493 14:47:55.599232 CPU: vendor Intel device 806c1
494 14:47:55.602464 CPU: family 06, model 8c, stepping 01
495 14:47:55.605992 Clearing out pending MCEs
496 14:47:55.609370 Clearing out pending MCEs
497 14:47:55.612862 Setting up local APIC...
498 14:47:55.613278 Clearing out pending MCEs
499 14:47:55.615909 Setting up local APIC...
500 14:47:55.619065 Clearing out pending MCEs
501 14:47:55.622539 CPU: vendor Intel device 806c1
502 14:47:55.625808 CPU: family 06, model 8c, stepping 01
503 14:47:55.629011 Setting up local APIC...
504 14:47:55.632560 Setting up local APIC...
505 14:47:55.633029 Clearing out pending MCEs
506 14:47:55.635896 apic_id: 0x06 done.
507 14:47:55.639389 Setting up local APIC...
508 14:47:55.642789 Setting up local APIC...
509 14:47:55.643210 apic_id: 0x01 done.
510 14:47:55.649132 microcode: Update skipped, already up-to-date
511 14:47:55.649564 apic_id: 0x02 done.
512 14:47:55.652587 apic_id: 0x07 done.
513 14:47:55.655998 microcode: Update skipped, already up-to-date
514 14:47:55.662172 microcode: Update skipped, already up-to-date
515 14:47:55.662656 apic_id: 0x05 done.
516 14:47:55.665592 apic_id: 0x04 done.
517 14:47:55.668930 microcode: Update skipped, already up-to-date
518 14:47:55.675486 microcode: Update skipped, already up-to-date
519 14:47:55.675963 CPU #3 initialized
520 14:47:55.678825 CPU #7 initialized
521 14:47:55.682469 microcode: Update skipped, already up-to-date
522 14:47:55.685292 CPU #2 initialized
523 14:47:55.685745 CPU #6 initialized
524 14:47:55.688661 CPU #5 initialized
525 14:47:55.692276 CPU #4 initialized
526 14:47:55.695195 microcode: Update skipped, already up-to-date
527 14:47:55.698742 CPU #1 initialized
528 14:47:55.702137 bsp_do_flight_plan done after 454 msecs.
529 14:47:55.705322 CPU: frequency set to 4400 MHz
530 14:47:55.705843 Enabling SMIs.
531 14:47:55.711705 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 347 / 317 ms
532 14:47:55.728490 SATAXPCIE1 indicates PCIe NVMe is present
533 14:47:55.731673 Probing TPM: done!
534 14:47:55.735488 Connected to device vid:did:rid of 1ae0:0028:00
535 14:47:55.745712 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.5.30/cr50_v1.9311_mp.7-535187521e
536 14:47:55.748954 Initialized TPM device CR50 revision 0
537 14:47:55.752559 Enabling S0i3.4
538 14:47:55.759261 CBFS: Found 'vbt.bin' @0x78a40 size 0x4f0 in mcache @0x76c4c1fc
539 14:47:55.762057 Found a VBT of 8704 bytes after decompression
540 14:47:55.768909 cse_lite: CSE RO boot. HybridStorageMode disabled
541 14:47:55.775317 WEAK: src/soc/intel/tigerlake/fsp_params.c/mainboard_silicon_init_params called
542 14:47:55.850507 FSPS returned 0
543 14:47:55.853886 Executing Phase 1 of FspMultiPhaseSiInit
544 14:47:55.863625 FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
545 14:47:55.866936 port C0 DISC req: usage 1 usb3 1 usb2 5
546 14:47:55.870243 Raw Buffer output 0 00000511
547 14:47:55.873544 Raw Buffer output 1 00000000
548 14:47:55.877354 pmc_send_ipc_cmd succeeded
549 14:47:55.884161 port C1 DISC req: usage 1 usb3 2 usb2 3
550 14:47:55.884641 Raw Buffer output 0 00000321
551 14:47:55.886989 Raw Buffer output 1 00000000
552 14:47:55.891197 pmc_send_ipc_cmd succeeded
553 14:47:55.896639 Detected 4 core, 8 thread CPU.
554 14:47:55.899763 Detected 4 core, 8 thread CPU.
555 14:47:56.099780 Display FSP Version Info HOB
556 14:47:56.103052 Reference Code - CPU = a.0.4c.31
557 14:47:56.106144 uCode Version = 0.0.0.86
558 14:47:56.109560 TXT ACM version = ff.ff.ff.ffff
559 14:47:56.113016 Reference Code - ME = a.0.4c.31
560 14:47:56.116234 MEBx version = 0.0.0.0
561 14:47:56.119321 ME Firmware Version = Consumer SKU
562 14:47:56.122911 Reference Code - PCH = a.0.4c.31
563 14:47:56.126345 PCH-CRID Status = Disabled
564 14:47:56.129436 PCH-CRID Original Value = ff.ff.ff.ffff
565 14:47:56.132767 PCH-CRID New Value = ff.ff.ff.ffff
566 14:47:56.136416 OPROM - RST - RAID = ff.ff.ff.ffff
567 14:47:56.139556 PCH Hsio Version = 4.0.0.0
568 14:47:56.142635 Reference Code - SA - System Agent = a.0.4c.31
569 14:47:56.146448 Reference Code - MRC = 2.0.0.1
570 14:47:56.149320 SA - PCIe Version = a.0.4c.31
571 14:47:56.152668 SA-CRID Status = Disabled
572 14:47:56.155953 SA-CRID Original Value = 0.0.0.1
573 14:47:56.159198 SA-CRID New Value = 0.0.0.1
574 14:47:56.162640 OPROM - VBIOS = ff.ff.ff.ffff
575 14:47:56.166012 IO Manageability Engine FW Version = 11.1.4.0
576 14:47:56.169457 PHY Build Version = 0.0.0.e0
577 14:47:56.172941 Thunderbolt(TM) FW Version = 0.0.0.0
578 14:47:56.180507 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
579 14:47:56.180994 ITSS IRQ Polarities Before:
580 14:47:56.183807 IPC0: 0xffffffff
581 14:47:56.184299 IPC1: 0xffffffff
582 14:47:56.187199 IPC2: 0xffffffff
583 14:47:56.187634 IPC3: 0xffffffff
584 14:47:56.190832 ITSS IRQ Polarities After:
585 14:47:56.193760 IPC0: 0xffffffff
586 14:47:56.194238 IPC1: 0xffffffff
587 14:47:56.197026 IPC2: 0xffffffff
588 14:47:56.197526 IPC3: 0xffffffff
589 14:47:56.203988 Found PCIe Root Port #9 at PCI: 00:1d.0.
590 14:47:56.213879 pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
591 14:47:56.227374 pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing.
592 14:47:56.240350 pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
593 14:47:56.243686 BS: BS_DEV_INIT_CHIPS run times (exec / console): 290 / 236 ms
594 14:47:56.246775 Enumerating buses...
595 14:47:56.250411 Show all devs... Before device enumeration.
596 14:47:56.253703 Root Device: enabled 1
597 14:47:56.256994 DOMAIN: 0000: enabled 1
598 14:47:56.260130 CPU_CLUSTER: 0: enabled 1
599 14:47:56.260563 PCI: 00:00.0: enabled 1
600 14:47:56.263417 PCI: 00:02.0: enabled 1
601 14:47:56.267056 PCI: 00:04.0: enabled 1
602 14:47:56.270013 PCI: 00:05.0: enabled 1
603 14:47:56.270445 PCI: 00:06.0: enabled 0
604 14:47:56.273362 PCI: 00:07.0: enabled 0
605 14:47:56.277020 PCI: 00:07.1: enabled 0
606 14:47:56.280106 PCI: 00:07.2: enabled 0
607 14:47:56.280540 PCI: 00:07.3: enabled 0
608 14:47:56.283475 PCI: 00:08.0: enabled 1
609 14:47:56.286869 PCI: 00:09.0: enabled 0
610 14:47:56.289785 PCI: 00:0a.0: enabled 0
611 14:47:56.290220 PCI: 00:0d.0: enabled 1
612 14:47:56.293449 PCI: 00:0d.1: enabled 0
613 14:47:56.296785 PCI: 00:0d.2: enabled 0
614 14:47:56.300048 PCI: 00:0d.3: enabled 0
615 14:47:56.300479 PCI: 00:0e.0: enabled 0
616 14:47:56.303574 PCI: 00:10.2: enabled 1
617 14:47:56.306787 PCI: 00:10.6: enabled 0
618 14:47:56.307218 PCI: 00:10.7: enabled 0
619 14:47:56.310072 PCI: 00:12.0: enabled 0
620 14:47:56.313216 PCI: 00:12.6: enabled 0
621 14:47:56.316304 PCI: 00:13.0: enabled 0
622 14:47:56.316736 PCI: 00:14.0: enabled 1
623 14:47:56.319602 PCI: 00:14.1: enabled 0
624 14:47:56.322858 PCI: 00:14.2: enabled 1
625 14:47:56.326303 PCI: 00:14.3: enabled 1
626 14:47:56.326730 PCI: 00:15.0: enabled 1
627 14:47:56.329855 PCI: 00:15.1: enabled 1
628 14:47:56.333285 PCI: 00:15.2: enabled 1
629 14:47:56.336477 PCI: 00:15.3: enabled 1
630 14:47:56.336913 PCI: 00:16.0: enabled 1
631 14:47:56.339937 PCI: 00:16.1: enabled 0
632 14:47:56.343269 PCI: 00:16.2: enabled 0
633 14:47:56.343703 PCI: 00:16.3: enabled 0
634 14:47:56.346375 PCI: 00:16.4: enabled 0
635 14:47:56.349820 PCI: 00:16.5: enabled 0
636 14:47:56.353082 PCI: 00:17.0: enabled 1
637 14:47:56.353550 PCI: 00:19.0: enabled 0
638 14:47:56.356053 PCI: 00:19.1: enabled 1
639 14:47:56.359756 PCI: 00:19.2: enabled 0
640 14:47:56.363022 PCI: 00:1c.0: enabled 1
641 14:47:56.363459 PCI: 00:1c.1: enabled 0
642 14:47:56.366553 PCI: 00:1c.2: enabled 0
643 14:47:56.369433 PCI: 00:1c.3: enabled 0
644 14:47:56.373129 PCI: 00:1c.4: enabled 0
645 14:47:56.373562 PCI: 00:1c.5: enabled 0
646 14:47:56.376446 PCI: 00:1c.6: enabled 1
647 14:47:56.379580 PCI: 00:1c.7: enabled 0
648 14:47:56.382911 PCI: 00:1d.0: enabled 1
649 14:47:56.383342 PCI: 00:1d.1: enabled 0
650 14:47:56.386286 PCI: 00:1d.2: enabled 1
651 14:47:56.389542 PCI: 00:1d.3: enabled 0
652 14:47:56.390033 PCI: 00:1e.0: enabled 1
653 14:47:56.392653 PCI: 00:1e.1: enabled 0
654 14:47:56.396105 PCI: 00:1e.2: enabled 1
655 14:47:56.399702 PCI: 00:1e.3: enabled 1
656 14:47:56.400169 PCI: 00:1f.0: enabled 1
657 14:47:56.402811 PCI: 00:1f.1: enabled 0
658 14:47:56.406045 PCI: 00:1f.2: enabled 1
659 14:47:56.409357 PCI: 00:1f.3: enabled 1
660 14:47:56.409829 PCI: 00:1f.4: enabled 0
661 14:47:56.412741 PCI: 00:1f.5: enabled 1
662 14:47:56.416251 PCI: 00:1f.6: enabled 0
663 14:47:56.419486 PCI: 00:1f.7: enabled 0
664 14:47:56.419961 APIC: 00: enabled 1
665 14:47:56.422977 GENERIC: 0.0: enabled 1
666 14:47:56.425985 GENERIC: 0.0: enabled 1
667 14:47:56.426467 GENERIC: 1.0: enabled 1
668 14:47:56.429618 GENERIC: 0.0: enabled 1
669 14:47:56.432719 GENERIC: 1.0: enabled 1
670 14:47:56.436040 USB0 port 0: enabled 1
671 14:47:56.436490 GENERIC: 0.0: enabled 1
672 14:47:56.439319 USB0 port 0: enabled 1
673 14:47:56.442665 GENERIC: 0.0: enabled 1
674 14:47:56.443097 I2C: 00:1a: enabled 1
675 14:47:56.446114 I2C: 00:31: enabled 1
676 14:47:56.449391 I2C: 00:32: enabled 1
677 14:47:56.449821 I2C: 00:10: enabled 1
678 14:47:56.452515 I2C: 00:15: enabled 1
679 14:47:56.455696 GENERIC: 0.0: enabled 0
680 14:47:56.459129 GENERIC: 1.0: enabled 0
681 14:47:56.459570 GENERIC: 0.0: enabled 1
682 14:47:56.463087 SPI: 00: enabled 1
683 14:47:56.466319 SPI: 00: enabled 1
684 14:47:56.466862 PNP: 0c09.0: enabled 1
685 14:47:56.468791 GENERIC: 0.0: enabled 1
686 14:47:56.472319 USB3 port 0: enabled 1
687 14:47:56.472808 USB3 port 1: enabled 1
688 14:47:56.475782 USB3 port 2: enabled 0
689 14:47:56.478738 USB3 port 3: enabled 0
690 14:47:56.482335 USB2 port 0: enabled 0
691 14:47:56.482769 USB2 port 1: enabled 1
692 14:47:56.485714 USB2 port 2: enabled 1
693 14:47:56.488478 USB2 port 3: enabled 0
694 14:47:56.488912 USB2 port 4: enabled 1
695 14:47:56.491829 USB2 port 5: enabled 0
696 14:47:56.495061 USB2 port 6: enabled 0
697 14:47:56.498722 USB2 port 7: enabled 0
698 14:47:56.499159 USB2 port 8: enabled 0
699 14:47:56.501951 USB2 port 9: enabled 0
700 14:47:56.505558 USB3 port 0: enabled 0
701 14:47:56.505791 USB3 port 1: enabled 1
702 14:47:56.508475 USB3 port 2: enabled 0
703 14:47:56.511757 USB3 port 3: enabled 0
704 14:47:56.515157 GENERIC: 0.0: enabled 1
705 14:47:56.515314 GENERIC: 1.0: enabled 1
706 14:47:56.518521 APIC: 01: enabled 1
707 14:47:56.518683 APIC: 03: enabled 1
708 14:47:56.521493 APIC: 05: enabled 1
709 14:47:56.524864 APIC: 07: enabled 1
710 14:47:56.525061 APIC: 06: enabled 1
711 14:47:56.528192 APIC: 02: enabled 1
712 14:47:56.531727 APIC: 04: enabled 1
713 14:47:56.531917 Compare with tree...
714 14:47:56.534979 Root Device: enabled 1
715 14:47:56.538109 DOMAIN: 0000: enabled 1
716 14:47:56.541903 PCI: 00:00.0: enabled 1
717 14:47:56.542063 PCI: 00:02.0: enabled 1
718 14:47:56.544854 PCI: 00:04.0: enabled 1
719 14:47:56.547966 GENERIC: 0.0: enabled 1
720 14:47:56.551147 PCI: 00:05.0: enabled 1
721 14:47:56.554521 PCI: 00:06.0: enabled 0
722 14:47:56.554615 PCI: 00:07.0: enabled 0
723 14:47:56.557998 GENERIC: 0.0: enabled 1
724 14:47:56.560996 PCI: 00:07.1: enabled 0
725 14:47:56.565315 GENERIC: 1.0: enabled 1
726 14:47:56.567829 PCI: 00:07.2: enabled 0
727 14:47:56.567931 GENERIC: 0.0: enabled 1
728 14:47:56.571209 PCI: 00:07.3: enabled 0
729 14:47:56.574211 GENERIC: 1.0: enabled 1
730 14:47:56.577824 PCI: 00:08.0: enabled 1
731 14:47:56.580901 PCI: 00:09.0: enabled 0
732 14:47:56.580994 PCI: 00:0a.0: enabled 0
733 14:47:56.584172 PCI: 00:0d.0: enabled 1
734 14:47:56.587648 USB0 port 0: enabled 1
735 14:47:56.591191 USB3 port 0: enabled 1
736 14:47:56.594715 USB3 port 1: enabled 1
737 14:47:56.597736 USB3 port 2: enabled 0
738 14:47:56.597910 USB3 port 3: enabled 0
739 14:47:56.601196 PCI: 00:0d.1: enabled 0
740 14:47:56.604291 PCI: 00:0d.2: enabled 0
741 14:47:56.607565 GENERIC: 0.0: enabled 1
742 14:47:56.610709 PCI: 00:0d.3: enabled 0
743 14:47:56.610881 PCI: 00:0e.0: enabled 0
744 14:47:56.614222 PCI: 00:10.2: enabled 1
745 14:47:56.617687 PCI: 00:10.6: enabled 0
746 14:47:56.620508 PCI: 00:10.7: enabled 0
747 14:47:56.624061 PCI: 00:12.0: enabled 0
748 14:47:56.624250 PCI: 00:12.6: enabled 0
749 14:47:56.627390 PCI: 00:13.0: enabled 0
750 14:47:56.630652 PCI: 00:14.0: enabled 1
751 14:47:56.633729 USB0 port 0: enabled 1
752 14:47:56.637265 USB2 port 0: enabled 0
753 14:47:56.637488 USB2 port 1: enabled 1
754 14:47:56.640632 USB2 port 2: enabled 1
755 14:47:56.644231 USB2 port 3: enabled 0
756 14:47:56.647136 USB2 port 4: enabled 1
757 14:47:56.650605 USB2 port 5: enabled 0
758 14:47:56.654010 USB2 port 6: enabled 0
759 14:47:56.654154 USB2 port 7: enabled 0
760 14:47:56.657110 USB2 port 8: enabled 0
761 14:47:56.660470 USB2 port 9: enabled 0
762 14:47:56.663827 USB3 port 0: enabled 0
763 14:47:56.667351 USB3 port 1: enabled 1
764 14:47:56.667568 USB3 port 2: enabled 0
765 14:47:56.670570 USB3 port 3: enabled 0
766 14:47:56.673962 PCI: 00:14.1: enabled 0
767 14:47:56.677208 PCI: 00:14.2: enabled 1
768 14:47:56.680085 PCI: 00:14.3: enabled 1
769 14:47:56.683388 GENERIC: 0.0: enabled 1
770 14:47:56.683602 PCI: 00:15.0: enabled 1
771 14:47:56.686826 I2C: 00:1a: enabled 1
772 14:47:56.690566 I2C: 00:31: enabled 1
773 14:47:56.693666 I2C: 00:32: enabled 1
774 14:47:56.693801 PCI: 00:15.1: enabled 1
775 14:47:56.696814 I2C: 00:10: enabled 1
776 14:47:56.699825 PCI: 00:15.2: enabled 1
777 14:47:56.703319 PCI: 00:15.3: enabled 1
778 14:47:56.706840 PCI: 00:16.0: enabled 1
779 14:47:56.706980 PCI: 00:16.1: enabled 0
780 14:47:56.709743 PCI: 00:16.2: enabled 0
781 14:47:56.713475 PCI: 00:16.3: enabled 0
782 14:47:56.716445 PCI: 00:16.4: enabled 0
783 14:47:56.719810 PCI: 00:16.5: enabled 0
784 14:47:56.719970 PCI: 00:17.0: enabled 1
785 14:47:56.723490 PCI: 00:19.0: enabled 0
786 14:47:56.726633 PCI: 00:19.1: enabled 1
787 14:47:56.729789 I2C: 00:15: enabled 1
788 14:47:56.733264 PCI: 00:19.2: enabled 0
789 14:47:56.733399 PCI: 00:1d.0: enabled 1
790 14:47:56.735859 GENERIC: 0.0: enabled 1
791 14:47:56.739515 PCI: 00:1e.0: enabled 1
792 14:47:56.743121 PCI: 00:1e.1: enabled 0
793 14:47:56.746371 PCI: 00:1e.2: enabled 1
794 14:47:56.746535 SPI: 00: enabled 1
795 14:47:56.749790 PCI: 00:1e.3: enabled 1
796 14:47:56.753158 SPI: 00: enabled 1
797 14:47:56.756056 PCI: 00:1f.0: enabled 1
798 14:47:56.756191 PNP: 0c09.0: enabled 1
799 14:47:56.759765 PCI: 00:1f.1: enabled 0
800 14:47:56.762634 PCI: 00:1f.2: enabled 1
801 14:47:56.765958 GENERIC: 0.0: enabled 1
802 14:47:56.769407 GENERIC: 0.0: enabled 1
803 14:47:56.772641 GENERIC: 1.0: enabled 1
804 14:47:56.772774 PCI: 00:1f.3: enabled 1
805 14:47:56.776179 PCI: 00:1f.4: enabled 0
806 14:47:56.827498 PCI: 00:1f.5: enabled 1
807 14:47:56.827710 PCI: 00:1f.6: enabled 0
808 14:47:56.828038 PCI: 00:1f.7: enabled 0
809 14:47:56.828154 CPU_CLUSTER: 0: enabled 1
810 14:47:56.828253 APIC: 00: enabled 1
811 14:47:56.828557 APIC: 01: enabled 1
812 14:47:56.828659 APIC: 03: enabled 1
813 14:47:56.828763 APIC: 05: enabled 1
814 14:47:56.828864 APIC: 07: enabled 1
815 14:47:56.829001 APIC: 06: enabled 1
816 14:47:56.829351 APIC: 02: enabled 1
817 14:47:56.829457 APIC: 04: enabled 1
818 14:47:56.829550 Root Device scanning...
819 14:47:56.829639 scan_static_bus for Root Device
820 14:47:56.829734 DOMAIN: 0000 enabled
821 14:47:56.829823 CPU_CLUSTER: 0 enabled
822 14:47:56.829910 DOMAIN: 0000 scanning...
823 14:47:56.829995 PCI: pci_scan_bus for bus 00
824 14:47:56.830286 PCI: 00:00.0 [8086/0000] ops
825 14:47:56.830379 PCI: 00:00.0 [8086/9a12] enabled
826 14:47:56.878020 PCI: 00:02.0 [8086/0000] bus ops
827 14:47:56.878156 PCI: 00:02.0 [8086/9a40] enabled
828 14:47:56.878419 PCI: 00:04.0 [8086/0000] bus ops
829 14:47:56.878488 PCI: 00:04.0 [8086/9a03] enabled
830 14:47:56.878794 PCI: 00:05.0 [8086/9a19] enabled
831 14:47:56.879069 PCI: 00:07.0 [0000/0000] hidden
832 14:47:56.879140 PCI: 00:08.0 [8086/9a11] enabled
833 14:47:56.879392 PCI: 00:0a.0 [8086/9a0d] disabled
834 14:47:56.879458 PCI: 00:0d.0 [8086/0000] bus ops
835 14:47:56.879706 PCI: 00:0d.0 [8086/9a13] enabled
836 14:47:56.879771 PCI: 00:14.0 [8086/0000] bus ops
837 14:47:56.879828 PCI: 00:14.0 [8086/a0ed] enabled
838 14:47:56.879928 PCI: 00:14.2 [8086/a0ef] enabled
839 14:47:56.880172 PCI: 00:14.3 [8086/0000] bus ops
840 14:47:56.880235 PCI: 00:14.3 [8086/a0f0] enabled
841 14:47:56.927945 PCI: 00:15.0 [8086/0000] bus ops
842 14:47:56.928059 PCI: 00:15.0 [8086/a0e8] enabled
843 14:47:56.928339 PCI: 00:15.1 [8086/0000] bus ops
844 14:47:56.928427 PCI: 00:15.1 [8086/a0e9] enabled
845 14:47:56.928702 PCI: 00:15.2 [8086/0000] bus ops
846 14:47:56.928976 PCI: 00:15.2 [8086/a0ea] enabled
847 14:47:56.929062 PCI: 00:15.3 [8086/0000] bus ops
848 14:47:56.929343 PCI: 00:15.3 [8086/a0eb] enabled
849 14:47:56.929428 PCI: 00:16.0 [8086/0000] ops
850 14:47:56.929699 PCI: 00:16.0 [8086/a0e0] enabled
851 14:47:56.929780 PCI: Static device PCI: 00:17.0 not found, disabling it.
852 14:47:56.930043 PCI: 00:19.0 [8086/0000] bus ops
853 14:47:56.930341 PCI: 00:19.0 [8086/a0c5] disabled
854 14:47:56.930406 PCI: 00:19.1 [8086/0000] bus ops
855 14:47:56.954291 PCI: 00:19.1 [8086/a0c6] enabled
856 14:47:56.954376 PCI: 00:1d.0 [8086/0000] bus ops
857 14:47:56.954655 PCI: 00:1d.0 [8086/a0b0] enabled
858 14:47:56.954740 PCI: 00:1e.0 [8086/0000] ops
859 14:47:56.954990 PCI: 00:1e.0 [8086/a0a8] enabled
860 14:47:56.955055 PCI: 00:1e.2 [8086/0000] bus ops
861 14:47:56.955114 PCI: 00:1e.2 [8086/a0aa] enabled
862 14:47:56.955174 PCI: 00:1e.3 [8086/0000] bus ops
863 14:47:56.957849 PCI: 00:1e.3 [8086/a0ab] enabled
864 14:47:56.961593 PCI: 00:1f.0 [8086/0000] bus ops
865 14:47:56.964848 PCI: 00:1f.0 [8086/a087] enabled
866 14:47:56.964931 RTC Init
867 14:47:56.968103 Set power on after power failure.
868 14:47:56.971513 Disabling Deep S3
869 14:47:56.974466 Disabling Deep S3
870 14:47:56.974547 Disabling Deep S4
871 14:47:56.978061 Disabling Deep S4
872 14:47:56.978155 Disabling Deep S5
873 14:47:56.981452 Disabling Deep S5
874 14:47:56.984332 PCI: 00:1f.2 [0000/0000] hidden
875 14:47:56.987584 PCI: 00:1f.3 [8086/0000] bus ops
876 14:47:56.991264 PCI: 00:1f.3 [8086/a0c8] enabled
877 14:47:56.994539 PCI: 00:1f.5 [8086/0000] bus ops
878 14:47:56.997735 PCI: 00:1f.5 [8086/a0a4] enabled
879 14:47:57.000952 PCI: Leftover static devices:
880 14:47:57.001035 PCI: 00:10.2
881 14:47:57.003758 PCI: 00:10.6
882 14:47:57.003914 PCI: 00:10.7
883 14:47:57.004000 PCI: 00:06.0
884 14:47:57.007463 PCI: 00:07.1
885 14:47:57.007547 PCI: 00:07.2
886 14:47:57.010461 PCI: 00:07.3
887 14:47:57.010545 PCI: 00:09.0
888 14:47:57.010609 PCI: 00:0d.1
889 14:47:57.013997 PCI: 00:0d.2
890 14:47:57.014079 PCI: 00:0d.3
891 14:47:57.017255 PCI: 00:0e.0
892 14:47:57.017359 PCI: 00:12.0
893 14:47:57.020459 PCI: 00:12.6
894 14:47:57.020572 PCI: 00:13.0
895 14:47:57.020653 PCI: 00:14.1
896 14:47:57.023767 PCI: 00:16.1
897 14:47:57.023902 PCI: 00:16.2
898 14:47:57.026991 PCI: 00:16.3
899 14:47:57.027074 PCI: 00:16.4
900 14:47:57.027139 PCI: 00:16.5
901 14:47:57.030659 PCI: 00:17.0
902 14:47:57.030743 PCI: 00:19.2
903 14:47:57.033821 PCI: 00:1e.1
904 14:47:57.033906 PCI: 00:1f.1
905 14:47:57.037056 PCI: 00:1f.4
906 14:47:57.037139 PCI: 00:1f.6
907 14:47:57.037204 PCI: 00:1f.7
908 14:47:57.040484 PCI: Check your devicetree.cb.
909 14:47:57.043567 PCI: 00:02.0 scanning...
910 14:47:57.046728 scan_generic_bus for PCI: 00:02.0
911 14:47:57.050662 scan_generic_bus for PCI: 00:02.0 done
912 14:47:57.056716 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
913 14:47:57.060415 PCI: 00:04.0 scanning...
914 14:47:57.063619 scan_generic_bus for PCI: 00:04.0
915 14:47:57.063706 GENERIC: 0.0 enabled
916 14:47:57.070274 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
917 14:47:57.076646 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
918 14:47:57.076730 PCI: 00:0d.0 scanning...
919 14:47:57.079996 scan_static_bus for PCI: 00:0d.0
920 14:47:57.083659 USB0 port 0 enabled
921 14:47:57.086687 USB0 port 0 scanning...
922 14:47:57.089877 scan_static_bus for USB0 port 0
923 14:47:57.089961 USB3 port 0 enabled
924 14:47:57.093681 USB3 port 1 enabled
925 14:47:57.096779 USB3 port 2 disabled
926 14:47:57.096908 USB3 port 3 disabled
927 14:47:57.099705 USB3 port 0 scanning...
928 14:47:57.103359 scan_static_bus for USB3 port 0
929 14:47:57.106507 scan_static_bus for USB3 port 0 done
930 14:47:57.113050 scan_bus: bus USB3 port 0 finished in 6 msecs
931 14:47:57.113192 USB3 port 1 scanning...
932 14:47:57.116365 scan_static_bus for USB3 port 1
933 14:47:57.122847 scan_static_bus for USB3 port 1 done
934 14:47:57.126442 scan_bus: bus USB3 port 1 finished in 6 msecs
935 14:47:57.129884 scan_static_bus for USB0 port 0 done
936 14:47:57.132831 scan_bus: bus USB0 port 0 finished in 43 msecs
937 14:47:57.139706 scan_static_bus for PCI: 00:0d.0 done
938 14:47:57.142867 scan_bus: bus PCI: 00:0d.0 finished in 60 msecs
939 14:47:57.146269 PCI: 00:14.0 scanning...
940 14:47:57.149287 scan_static_bus for PCI: 00:14.0
941 14:47:57.152770 USB0 port 0 enabled
942 14:47:57.152915 USB0 port 0 scanning...
943 14:47:57.156370 scan_static_bus for USB0 port 0
944 14:47:57.158994 USB2 port 0 disabled
945 14:47:57.162865 USB2 port 1 enabled
946 14:47:57.162950 USB2 port 2 enabled
947 14:47:57.165942 USB2 port 3 disabled
948 14:47:57.169352 USB2 port 4 enabled
949 14:47:57.169435 USB2 port 5 disabled
950 14:47:57.172511 USB2 port 6 disabled
951 14:47:57.172597 USB2 port 7 disabled
952 14:47:57.175890 USB2 port 8 disabled
953 14:47:57.179318 USB2 port 9 disabled
954 14:47:57.179401 USB3 port 0 disabled
955 14:47:57.182601 USB3 port 1 enabled
956 14:47:57.185722 USB3 port 2 disabled
957 14:47:57.185806 USB3 port 3 disabled
958 14:47:57.189525 USB2 port 1 scanning...
959 14:47:57.192316 scan_static_bus for USB2 port 1
960 14:47:57.195461 scan_static_bus for USB2 port 1 done
961 14:47:57.202134 scan_bus: bus USB2 port 1 finished in 6 msecs
962 14:47:57.202215 USB2 port 2 scanning...
963 14:47:57.205467 scan_static_bus for USB2 port 2
964 14:47:57.212436 scan_static_bus for USB2 port 2 done
965 14:47:57.215606 scan_bus: bus USB2 port 2 finished in 6 msecs
966 14:47:57.218789 USB2 port 4 scanning...
967 14:47:57.222211 scan_static_bus for USB2 port 4
968 14:47:57.225584 scan_static_bus for USB2 port 4 done
969 14:47:57.229159 scan_bus: bus USB2 port 4 finished in 6 msecs
970 14:47:57.231803 USB3 port 1 scanning...
971 14:47:57.235382 scan_static_bus for USB3 port 1
972 14:47:57.238632 scan_static_bus for USB3 port 1 done
973 14:47:57.245099 scan_bus: bus USB3 port 1 finished in 6 msecs
974 14:47:57.248610 scan_static_bus for USB0 port 0 done
975 14:47:57.251861 scan_bus: bus USB0 port 0 finished in 93 msecs
976 14:47:57.255274 scan_static_bus for PCI: 00:14.0 done
977 14:47:57.261522 scan_bus: bus PCI: 00:14.0 finished in 109 msecs
978 14:47:57.261604 PCI: 00:14.3 scanning...
979 14:47:57.265172 scan_static_bus for PCI: 00:14.3
980 14:47:57.268376 GENERIC: 0.0 enabled
981 14:47:57.271943 scan_static_bus for PCI: 00:14.3 done
982 14:47:57.278264 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
983 14:47:57.278360 PCI: 00:15.0 scanning...
984 14:47:57.285396 scan_static_bus for PCI: 00:15.0
985 14:47:57.285507 I2C: 00:1a enabled
986 14:47:57.288335 I2C: 00:31 enabled
987 14:47:57.288439 I2C: 00:32 enabled
988 14:47:57.291775 scan_static_bus for PCI: 00:15.0 done
989 14:47:57.298339 scan_bus: bus PCI: 00:15.0 finished in 12 msecs
990 14:47:57.301547 PCI: 00:15.1 scanning...
991 14:47:57.305226 scan_static_bus for PCI: 00:15.1
992 14:47:57.305409 I2C: 00:10 enabled
993 14:47:57.308813 scan_static_bus for PCI: 00:15.1 done
994 14:47:57.315016 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
995 14:47:57.318278 PCI: 00:15.2 scanning...
996 14:47:57.321697 scan_static_bus for PCI: 00:15.2
997 14:47:57.324562 scan_static_bus for PCI: 00:15.2 done
998 14:47:57.328306 scan_bus: bus PCI: 00:15.2 finished in 7 msecs
999 14:47:57.331653 PCI: 00:15.3 scanning...
1000 14:47:57.334638 scan_static_bus for PCI: 00:15.3
1001 14:47:57.338236 scan_static_bus for PCI: 00:15.3 done
1002 14:47:57.344524 scan_bus: bus PCI: 00:15.3 finished in 7 msecs
1003 14:47:57.344603 PCI: 00:19.1 scanning...
1004 14:47:57.347912 scan_static_bus for PCI: 00:19.1
1005 14:47:57.351281 I2C: 00:15 enabled
1006 14:47:57.354566 scan_static_bus for PCI: 00:19.1 done
1007 14:47:57.361441 scan_bus: bus PCI: 00:19.1 finished in 9 msecs
1008 14:47:57.361520 PCI: 00:1d.0 scanning...
1009 14:47:57.367788 do_pci_scan_bridge for PCI: 00:1d.0
1010 14:47:57.367903 PCI: pci_scan_bus for bus 01
1011 14:47:57.371162 PCI: 01:00.0 [15b7/5009] enabled
1012 14:47:57.374781 GENERIC: 0.0 enabled
1013 14:47:57.378018 Enabling Common Clock Configuration
1014 14:47:57.384425 L1 Sub-State supported from root port 29
1015 14:47:57.384518 L1 Sub-State Support = 0x5
1016 14:47:57.387569 CommonModeRestoreTime = 0x28
1017 14:47:57.394401 Power On Value = 0x16, Power On Scale = 0x0
1018 14:47:57.394480 ASPM: Enabled L1
1019 14:47:57.397327 PCIe: Max_Payload_Size adjusted to 128
1020 14:47:57.404323 scan_bus: bus PCI: 00:1d.0 finished in 35 msecs
1021 14:47:57.407715 PCI: 00:1e.2 scanning...
1022 14:47:57.410958 scan_generic_bus for PCI: 00:1e.2
1023 14:47:57.411041 SPI: 00 enabled
1024 14:47:57.417245 bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done
1025 14:47:57.424606 scan_bus: bus PCI: 00:1e.2 finished in 11 msecs
1026 14:47:57.424688 PCI: 00:1e.3 scanning...
1027 14:47:57.427555 scan_generic_bus for PCI: 00:1e.3
1028 14:47:57.431092 SPI: 00 enabled
1029 14:47:57.437606 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1030 14:47:57.440830 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1031 14:47:57.444597 PCI: 00:1f.0 scanning...
1032 14:47:57.447900 scan_static_bus for PCI: 00:1f.0
1033 14:47:57.447974 PNP: 0c09.0 enabled
1034 14:47:57.451161 PNP: 0c09.0 scanning...
1035 14:47:57.454346 scan_static_bus for PNP: 0c09.0
1036 14:47:57.457658 scan_static_bus for PNP: 0c09.0 done
1037 14:47:57.464005 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1038 14:47:57.467741 scan_static_bus for PCI: 00:1f.0 done
1039 14:47:57.471010 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1040 14:47:57.474341 PCI: 00:1f.2 scanning...
1041 14:47:57.477516 scan_static_bus for PCI: 00:1f.2
1042 14:47:57.480733 GENERIC: 0.0 enabled
1043 14:47:57.484219 GENERIC: 0.0 scanning...
1044 14:47:57.487419 scan_static_bus for GENERIC: 0.0
1045 14:47:57.487496 GENERIC: 0.0 enabled
1046 14:47:57.490557 GENERIC: 1.0 enabled
1047 14:47:57.493810 scan_static_bus for GENERIC: 0.0 done
1048 14:47:57.501090 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1049 14:47:57.504184 scan_static_bus for PCI: 00:1f.2 done
1050 14:47:57.507575 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1051 14:47:57.510754 PCI: 00:1f.3 scanning...
1052 14:47:57.514302 scan_static_bus for PCI: 00:1f.3
1053 14:47:57.517168 scan_static_bus for PCI: 00:1f.3 done
1054 14:47:57.523989 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1055 14:47:57.524068 PCI: 00:1f.5 scanning...
1056 14:47:57.527095 scan_generic_bus for PCI: 00:1f.5
1057 14:47:57.533926 scan_generic_bus for PCI: 00:1f.5 done
1058 14:47:57.537278 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1059 14:47:57.543540 scan_bus: bus DOMAIN: 0000 finished in 717 msecs
1060 14:47:57.546920 scan_static_bus for Root Device done
1061 14:47:57.550201 scan_bus: bus Root Device finished in 736 msecs
1062 14:47:57.550274 done
1063 14:47:57.557074 BS: BS_DEV_ENUMERATE run times (exec / console): 11 / 1295 ms
1064 14:47:57.560145 Chrome EC: UHEPI supported
1065 14:47:57.566752 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (196608 bytes)
1066 14:47:57.573167 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1067 14:47:57.576501 SPI flash protection: WPSW=0 SRP0=1
1068 14:47:57.579801 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1069 14:47:57.586905 BS: BS_DEV_ENUMERATE exit times (exec / console): 1 / 23 ms
1070 14:47:57.590130 found VGA at PCI: 00:02.0
1071 14:47:57.593385 Setting up VGA for PCI: 00:02.0
1072 14:47:57.596434 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1073 14:47:57.603586 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1074 14:47:57.606540 Allocating resources...
1075 14:47:57.606615 Reading resources...
1076 14:47:57.613242 Root Device read_resources bus 0 link: 0
1077 14:47:57.616121 DOMAIN: 0000 read_resources bus 0 link: 0
1078 14:47:57.619789 PCI: 00:04.0 read_resources bus 1 link: 0
1079 14:47:57.626680 PCI: 00:04.0 read_resources bus 1 link: 0 done
1080 14:47:57.630009 PCI: 00:0d.0 read_resources bus 0 link: 0
1081 14:47:57.636540 USB0 port 0 read_resources bus 0 link: 0
1082 14:47:57.639785 USB0 port 0 read_resources bus 0 link: 0 done
1083 14:47:57.646592 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1084 14:47:57.649797 PCI: 00:14.0 read_resources bus 0 link: 0
1085 14:47:57.652869 USB0 port 0 read_resources bus 0 link: 0
1086 14:47:57.661158 USB0 port 0 read_resources bus 0 link: 0 done
1087 14:47:57.663932 PCI: 00:14.0 read_resources bus 0 link: 0 done
1088 14:47:57.671221 PCI: 00:14.3 read_resources bus 0 link: 0
1089 14:47:57.674498 PCI: 00:14.3 read_resources bus 0 link: 0 done
1090 14:47:57.680712 PCI: 00:15.0 read_resources bus 0 link: 0
1091 14:47:57.684142 PCI: 00:15.0 read_resources bus 0 link: 0 done
1092 14:47:57.691217 PCI: 00:15.1 read_resources bus 0 link: 0
1093 14:47:57.693892 PCI: 00:15.1 read_resources bus 0 link: 0 done
1094 14:47:57.701363 PCI: 00:19.1 read_resources bus 0 link: 0
1095 14:47:57.705014 PCI: 00:19.1 read_resources bus 0 link: 0 done
1096 14:47:57.711348 PCI: 00:1d.0 read_resources bus 1 link: 0
1097 14:47:57.714327 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1098 14:47:57.721385 PCI: 00:1e.2 read_resources bus 2 link: 0
1099 14:47:57.724549 PCI: 00:1e.2 read_resources bus 2 link: 0 done
1100 14:47:57.731280 PCI: 00:1e.3 read_resources bus 3 link: 0
1101 14:47:57.734752 PCI: 00:1e.3 read_resources bus 3 link: 0 done
1102 14:47:57.741153 PCI: 00:1f.0 read_resources bus 0 link: 0
1103 14:47:57.744340 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1104 14:47:57.750572 PCI: 00:1f.2 read_resources bus 0 link: 0
1105 14:47:57.753892 GENERIC: 0.0 read_resources bus 0 link: 0
1106 14:47:57.760393 GENERIC: 0.0 read_resources bus 0 link: 0 done
1107 14:47:57.763829 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1108 14:47:57.770560 DOMAIN: 0000 read_resources bus 0 link: 0 done
1109 14:47:57.773428 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1110 14:47:57.780505 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1111 14:47:57.783571 Root Device read_resources bus 0 link: 0 done
1112 14:47:57.786942 Done reading resources.
1113 14:47:57.793378 Show resources in subtree (Root Device)...After reading.
1114 14:47:57.796968 Root Device child on link 0 DOMAIN: 0000
1115 14:47:57.800125 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1116 14:47:57.809790 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1117 14:47:57.819861 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1118 14:47:57.823266 PCI: 00:00.0
1119 14:47:57.829816 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1120 14:47:57.840075 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1121 14:47:57.849810 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1122 14:47:57.859793 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1123 14:47:57.869835 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1124 14:47:57.879517 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1125 14:47:57.886170 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1126 14:47:57.896243 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1127 14:47:57.906080 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1128 14:47:57.916057 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1129 14:47:57.926085 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1130 14:47:57.935893 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1131 14:47:57.942269 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1132 14:47:57.952220 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1133 14:47:57.962426 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1134 14:47:57.972341 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1135 14:47:57.982294 PCI: 00:00.0 resource base 100000000 size 380400000 align 0 gran 0 limit 0 flags e0004200 index 10
1136 14:47:57.992060 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1137 14:47:57.998895 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1138 14:47:58.008702 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1139 14:47:58.012214 PCI: 00:02.0
1140 14:47:58.022243 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1141 14:47:58.031792 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1142 14:47:58.041789 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1143 14:47:58.045436 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1144 14:47:58.055263 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1145 14:47:58.058739 GENERIC: 0.0
1146 14:47:58.058825 PCI: 00:05.0
1147 14:47:58.068416 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1148 14:47:58.075125 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1149 14:47:58.075211 GENERIC: 0.0
1150 14:47:58.078572 PCI: 00:08.0
1151 14:47:58.088226 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1152 14:47:58.088313 PCI: 00:0a.0
1153 14:47:58.091585 PCI: 00:0d.0 child on link 0 USB0 port 0
1154 14:47:58.101405 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1155 14:47:58.108258 USB0 port 0 child on link 0 USB3 port 0
1156 14:47:58.108342 USB3 port 0
1157 14:47:58.111273 USB3 port 1
1158 14:47:58.111357 USB3 port 2
1159 14:47:58.114517 USB3 port 3
1160 14:47:58.118064 PCI: 00:14.0 child on link 0 USB0 port 0
1161 14:47:58.128352 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1162 14:47:58.134527 USB0 port 0 child on link 0 USB2 port 0
1163 14:47:58.134612 USB2 port 0
1164 14:47:58.137880 USB2 port 1
1165 14:47:58.137966 USB2 port 2
1166 14:47:58.141208 USB2 port 3
1167 14:47:58.141291 USB2 port 4
1168 14:47:58.144493 USB2 port 5
1169 14:47:58.144578 USB2 port 6
1170 14:47:58.147535 USB2 port 7
1171 14:47:58.147618 USB2 port 8
1172 14:47:58.150897 USB2 port 9
1173 14:47:58.154376 USB3 port 0
1174 14:47:58.154464 USB3 port 1
1175 14:47:58.157684 USB3 port 2
1176 14:47:58.157768 USB3 port 3
1177 14:47:58.161032 PCI: 00:14.2
1178 14:47:58.170721 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1179 14:47:58.180769 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1180 14:47:58.184114 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1181 14:47:58.193906 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1182 14:47:58.197172 GENERIC: 0.0
1183 14:47:58.200590 PCI: 00:15.0 child on link 0 I2C: 00:1a
1184 14:47:58.210404 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1185 14:47:58.210489 I2C: 00:1a
1186 14:47:58.213862 I2C: 00:31
1187 14:47:58.213946 I2C: 00:32
1188 14:47:58.220571 PCI: 00:15.1 child on link 0 I2C: 00:10
1189 14:47:58.230648 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1190 14:47:58.230735 I2C: 00:10
1191 14:47:58.233758 PCI: 00:15.2
1192 14:47:58.243448 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1193 14:47:58.243533 PCI: 00:15.3
1194 14:47:58.253293 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1195 14:47:58.256751 PCI: 00:16.0
1196 14:47:58.266661 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1197 14:47:58.266749 PCI: 00:19.0
1198 14:47:58.269960 PCI: 00:19.1 child on link 0 I2C: 00:15
1199 14:47:58.279893 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1200 14:47:58.282764 I2C: 00:15
1201 14:47:58.286224 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1202 14:47:58.296485 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1203 14:47:58.306209 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1204 14:47:58.315838 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1205 14:47:58.315957 GENERIC: 0.0
1206 14:47:58.319577 PCI: 01:00.0
1207 14:47:58.329191 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1208 14:47:58.339263 PCI: 01:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 20
1209 14:47:58.339359 PCI: 00:1e.0
1210 14:47:58.352803 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1211 14:47:58.356023 PCI: 00:1e.2 child on link 0 SPI: 00
1212 14:47:58.365620 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1213 14:47:58.365716 SPI: 00
1214 14:47:58.368924 PCI: 00:1e.3 child on link 0 SPI: 00
1215 14:47:58.378979 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1216 14:47:58.382122 SPI: 00
1217 14:47:58.385529 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1218 14:47:58.395275 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1219 14:47:58.395370 PNP: 0c09.0
1220 14:47:58.405248 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1221 14:47:58.408488 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1222 14:47:58.418360 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1223 14:47:58.428288 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1224 14:47:58.431688 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1225 14:47:58.434823 GENERIC: 0.0
1226 14:47:58.434917 GENERIC: 1.0
1227 14:47:58.438113 PCI: 00:1f.3
1228 14:47:58.447955 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1229 14:47:58.457859 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1230 14:47:58.461240 PCI: 00:1f.5
1231 14:47:58.468101 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1232 14:47:58.474304 CPU_CLUSTER: 0 child on link 0 APIC: 00
1233 14:47:58.474391 APIC: 00
1234 14:47:58.474457 APIC: 01
1235 14:47:58.477674 APIC: 03
1236 14:47:58.477758 APIC: 05
1237 14:47:58.480978 APIC: 07
1238 14:47:58.481061 APIC: 06
1239 14:47:58.481126 APIC: 02
1240 14:47:58.484305 APIC: 04
1241 14:47:58.491141 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1242 14:47:58.497750 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
1243 14:47:58.504172 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1244 14:47:58.510757 PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1245 14:47:58.513934 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1246 14:47:58.517413 PCI: 01:00.0 20 * [0x4000 - 0x40ff] mem
1247 14:47:58.524115 PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1248 14:47:58.530485 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1249 14:47:58.540793 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1250 14:47:58.547468 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1251 14:47:58.554105 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1252 14:47:58.560213 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1253 14:47:58.566859 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1254 14:47:58.576903 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1255 14:47:58.579961 DOMAIN: 0000: Resource ranges:
1256 14:47:58.583277 * Base: 1000, Size: 800, Tag: 100
1257 14:47:58.586824 * Base: 1900, Size: e700, Tag: 100
1258 14:47:58.590298 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1259 14:47:58.596705 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1260 14:47:58.603412 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1261 14:47:58.613279 update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
1262 14:47:58.619946 update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed)
1263 14:47:58.626741 update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
1264 14:47:58.636195 update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
1265 14:47:58.643360 update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
1266 14:47:58.649608 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
1267 14:47:58.659488 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
1268 14:47:58.666501 update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
1269 14:47:58.672700 update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
1270 14:47:58.682615 update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
1271 14:47:58.689509 update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
1272 14:47:58.696138 update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
1273 14:47:58.706295 update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
1274 14:47:58.712514 update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
1275 14:47:58.719361 update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
1276 14:47:58.729375 update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed)
1277 14:47:58.735950 update_constraints: PCI: 00:00.0 10 base 100000000 limit 4803fffff mem (fixed)
1278 14:47:58.745648 update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
1279 14:47:58.752425 update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
1280 14:47:58.759035 update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed)
1281 14:47:58.765552 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1282 14:47:58.775539 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1283 14:47:58.778996 DOMAIN: 0000: Resource ranges:
1284 14:47:58.781837 * Base: 7fc00000, Size: 40400000, Tag: 200
1285 14:47:58.785347 * Base: d0000000, Size: 28000000, Tag: 200
1286 14:47:58.791808 * Base: fa000000, Size: 1000000, Tag: 200
1287 14:47:58.795150 * Base: fb001000, Size: 2fff000, Tag: 200
1288 14:47:58.798351 * Base: fe010000, Size: 2e000, Tag: 200
1289 14:47:58.804956 * Base: fe03f000, Size: d41000, Tag: 200
1290 14:47:58.807827 * Base: fed88000, Size: 8000, Tag: 200
1291 14:47:58.811367 * Base: fed93000, Size: d000, Tag: 200
1292 14:47:58.814581 * Base: feda2000, Size: 1e000, Tag: 200
1293 14:47:58.821646 * Base: fede0000, Size: 1220000, Tag: 200
1294 14:47:58.824484 * Base: 480400000, Size: 7b7fc00000, Tag: 100200
1295 14:47:58.831229 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
1296 14:47:58.837973 PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
1297 14:47:58.844503 PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
1298 14:47:58.851111 PCI: 00:1d.0 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
1299 14:47:58.857974 PCI: 00:1f.3 20 * [0x7fd00000 - 0x7fdfffff] limit: 7fdfffff mem
1300 14:47:58.864507 PCI: 00:04.0 10 * [0x7fe00000 - 0x7fe1ffff] limit: 7fe1ffff mem
1301 14:47:58.871121 PCI: 00:0d.0 10 * [0x7fe20000 - 0x7fe2ffff] limit: 7fe2ffff mem
1302 14:47:58.877523 PCI: 00:14.0 10 * [0x7fe30000 - 0x7fe3ffff] limit: 7fe3ffff mem
1303 14:47:58.883993 PCI: 00:14.2 10 * [0x7fe40000 - 0x7fe43fff] limit: 7fe43fff mem
1304 14:47:58.891205 PCI: 00:14.3 10 * [0x7fe44000 - 0x7fe47fff] limit: 7fe47fff mem
1305 14:47:58.897476 PCI: 00:1f.3 10 * [0x7fe48000 - 0x7fe4bfff] limit: 7fe4bfff mem
1306 14:47:58.903713 PCI: 00:08.0 10 * [0x7fe4c000 - 0x7fe4cfff] limit: 7fe4cfff mem
1307 14:47:58.910580 PCI: 00:14.2 18 * [0x7fe4d000 - 0x7fe4dfff] limit: 7fe4dfff mem
1308 14:47:58.917189 PCI: 00:15.0 10 * [0x7fe4e000 - 0x7fe4efff] limit: 7fe4efff mem
1309 14:47:58.923844 PCI: 00:15.1 10 * [0x7fe4f000 - 0x7fe4ffff] limit: 7fe4ffff mem
1310 14:47:58.930222 PCI: 00:15.2 10 * [0x7fe50000 - 0x7fe50fff] limit: 7fe50fff mem
1311 14:47:58.936889 PCI: 00:15.3 10 * [0x7fe51000 - 0x7fe51fff] limit: 7fe51fff mem
1312 14:47:58.943301 PCI: 00:16.0 10 * [0x7fe52000 - 0x7fe52fff] limit: 7fe52fff mem
1313 14:47:58.950239 PCI: 00:19.1 10 * [0x7fe53000 - 0x7fe53fff] limit: 7fe53fff mem
1314 14:47:58.956972 PCI: 00:1e.2 10 * [0x7fe54000 - 0x7fe54fff] limit: 7fe54fff mem
1315 14:47:58.963378 PCI: 00:1e.3 10 * [0x7fe55000 - 0x7fe55fff] limit: 7fe55fff mem
1316 14:47:58.969791 PCI: 00:1f.5 10 * [0x7fe56000 - 0x7fe56fff] limit: 7fe56fff mem
1317 14:47:58.979953 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1318 14:47:58.986242 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff
1319 14:47:58.989507 PCI: 00:1d.0: Resource ranges:
1320 14:47:58.992862 * Base: 7fc00000, Size: 100000, Tag: 200
1321 14:47:58.999902 PCI: 01:00.0 10 * [0x7fc00000 - 0x7fc03fff] limit: 7fc03fff mem
1322 14:47:59.006173 PCI: 01:00.0 20 * [0x7fc04000 - 0x7fc040ff] limit: 7fc040ff mem
1323 14:47:59.016048 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff done
1324 14:47:59.023039 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1325 14:47:59.026000 Root Device assign_resources, bus 0 link: 0
1326 14:47:59.032912 DOMAIN: 0000 assign_resources, bus 0 link: 0
1327 14:47:59.039240 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
1328 14:47:59.049359 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
1329 14:47:59.056012 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1330 14:47:59.066321 PCI: 00:04.0 10 <- [0x007fe00000 - 0x007fe1ffff] size 0x00020000 gran 0x11 mem64
1331 14:47:59.069368 PCI: 00:04.0 assign_resources, bus 1 link: 0
1332 14:47:59.072125 PCI: 00:04.0 assign_resources, bus 1 link: 0
1333 14:47:59.082357 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64
1334 14:47:59.088773 PCI: 00:08.0 10 <- [0x007fe4c000 - 0x007fe4cfff] size 0x00001000 gran 0x0c mem64
1335 14:47:59.098537 PCI: 00:0d.0 10 <- [0x007fe20000 - 0x007fe2ffff] size 0x00010000 gran 0x10 mem64
1336 14:47:59.101956 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1337 14:47:59.108403 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1338 14:47:59.114922 PCI: 00:14.0 10 <- [0x007fe30000 - 0x007fe3ffff] size 0x00010000 gran 0x10 mem64
1339 14:47:59.121723 PCI: 00:14.0 assign_resources, bus 0 link: 0
1340 14:47:59.125550 PCI: 00:14.0 assign_resources, bus 0 link: 0
1341 14:47:59.131632 PCI: 00:14.2 10 <- [0x007fe40000 - 0x007fe43fff] size 0x00004000 gran 0x0e mem64
1342 14:47:59.141297 PCI: 00:14.2 18 <- [0x007fe4d000 - 0x007fe4dfff] size 0x00001000 gran 0x0c mem64
1343 14:47:59.148468 PCI: 00:14.3 10 <- [0x007fe44000 - 0x007fe47fff] size 0x00004000 gran 0x0e mem64
1344 14:47:59.155223 PCI: 00:14.3 assign_resources, bus 0 link: 0
1345 14:47:59.158361 PCI: 00:14.3 assign_resources, bus 0 link: 0
1346 14:47:59.168095 PCI: 00:15.0 10 <- [0x007fe4e000 - 0x007fe4efff] size 0x00001000 gran 0x0c mem64
1347 14:47:59.171009 PCI: 00:15.0 assign_resources, bus 0 link: 0
1348 14:47:59.174355 PCI: 00:15.0 assign_resources, bus 0 link: 0
1349 14:47:59.184741 PCI: 00:15.1 10 <- [0x007fe4f000 - 0x007fe4ffff] size 0x00001000 gran 0x0c mem64
1350 14:47:59.188047 PCI: 00:15.1 assign_resources, bus 0 link: 0
1351 14:47:59.194610 PCI: 00:15.1 assign_resources, bus 0 link: 0
1352 14:47:59.200674 PCI: 00:15.2 10 <- [0x007fe50000 - 0x007fe50fff] size 0x00001000 gran 0x0c mem64
1353 14:47:59.210914 PCI: 00:15.3 10 <- [0x007fe51000 - 0x007fe51fff] size 0x00001000 gran 0x0c mem64
1354 14:47:59.217725 PCI: 00:16.0 10 <- [0x007fe52000 - 0x007fe52fff] size 0x00001000 gran 0x0c mem64
1355 14:47:59.227466 PCI: 00:19.1 10 <- [0x007fe53000 - 0x007fe53fff] size 0x00001000 gran 0x0c mem64
1356 14:47:59.230550 PCI: 00:19.1 assign_resources, bus 0 link: 0
1357 14:47:59.237159 PCI: 00:19.1 assign_resources, bus 0 link: 0
1358 14:47:59.243883 PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1359 14:47:59.253884 PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1360 14:47:59.263632 PCI: 00:1d.0 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 bus 01 mem
1361 14:47:59.267893 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1362 14:47:59.277205 PCI: 01:00.0 10 <- [0x007fc00000 - 0x007fc03fff] size 0x00004000 gran 0x0e mem64
1363 14:47:59.283663 PCI: 01:00.0 20 <- [0x007fc04000 - 0x007fc040ff] size 0x00000100 gran 0x08 mem64
1364 14:47:59.286810 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1365 14:47:59.297203 PCI: 00:1e.2 10 <- [0x007fe54000 - 0x007fe54fff] size 0x00001000 gran 0x0c mem64
1366 14:47:59.300590 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1367 14:47:59.306956 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1368 14:47:59.313226 PCI: 00:1e.3 10 <- [0x007fe55000 - 0x007fe55fff] size 0x00001000 gran 0x0c mem64
1369 14:47:59.319874 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1370 14:47:59.323329 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1371 14:47:59.326245 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1372 14:47:59.333227 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1373 14:47:59.336422 LPC: Trying to open IO window from 800 size 1ff
1374 14:47:59.346655 PCI: 00:1f.3 10 <- [0x007fe48000 - 0x007fe4bfff] size 0x00004000 gran 0x0e mem64
1375 14:47:59.353451 PCI: 00:1f.3 20 <- [0x007fd00000 - 0x007fdfffff] size 0x00100000 gran 0x14 mem64
1376 14:47:59.362809 PCI: 00:1f.5 10 <- [0x007fe56000 - 0x007fe56fff] size 0x00001000 gran 0x0c mem
1377 14:47:59.366468 DOMAIN: 0000 assign_resources, bus 0 link: 0
1378 14:47:59.372777 Root Device assign_resources, bus 0 link: 0
1379 14:47:59.372927 Done setting resources.
1380 14:47:59.379753 Show resources in subtree (Root Device)...After assigning values.
1381 14:47:59.386178 Root Device child on link 0 DOMAIN: 0000
1382 14:47:59.389520 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1383 14:47:59.399029 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1384 14:47:59.409050 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1385 14:47:59.409360 PCI: 00:00.0
1386 14:47:59.418928 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1387 14:47:59.429435 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1388 14:47:59.439181 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1389 14:47:59.449044 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1390 14:47:59.458867 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1391 14:47:59.465337 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1392 14:47:59.475323 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1393 14:47:59.485217 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1394 14:47:59.495532 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1395 14:47:59.505377 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1396 14:47:59.515044 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1397 14:47:59.521894 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1398 14:47:59.531618 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1399 14:47:59.541904 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1400 14:47:59.551532 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1401 14:47:59.561667 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1402 14:47:59.571859 PCI: 00:00.0 resource base 100000000 size 380400000 align 0 gran 0 limit 0 flags e0004200 index 10
1403 14:47:59.578249 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1404 14:47:59.587976 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1405 14:47:59.598314 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1406 14:47:59.601346 PCI: 00:02.0
1407 14:47:59.611165 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10
1408 14:47:59.621419 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18
1409 14:47:59.631258 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1410 14:47:59.634589 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1411 14:47:59.644377 PCI: 00:04.0 resource base 7fe00000 size 20000 align 17 gran 17 limit 7fe1ffff flags 60000201 index 10
1412 14:47:59.647705 GENERIC: 0.0
1413 14:47:59.648162 PCI: 00:05.0
1414 14:47:59.660464 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10
1415 14:47:59.663831 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1416 14:47:59.667307 GENERIC: 0.0
1417 14:47:59.667744 PCI: 00:08.0
1418 14:47:59.677194 PCI: 00:08.0 resource base 7fe4c000 size 1000 align 12 gran 12 limit 7fe4cfff flags 60000201 index 10
1419 14:47:59.680499 PCI: 00:0a.0
1420 14:47:59.684134 PCI: 00:0d.0 child on link 0 USB0 port 0
1421 14:47:59.693463 PCI: 00:0d.0 resource base 7fe20000 size 10000 align 16 gran 16 limit 7fe2ffff flags 60000201 index 10
1422 14:47:59.700327 USB0 port 0 child on link 0 USB3 port 0
1423 14:47:59.700639 USB3 port 0
1424 14:47:59.703750 USB3 port 1
1425 14:47:59.704005 USB3 port 2
1426 14:47:59.707389 USB3 port 3
1427 14:47:59.710146 PCI: 00:14.0 child on link 0 USB0 port 0
1428 14:47:59.720184 PCI: 00:14.0 resource base 7fe30000 size 10000 align 16 gran 16 limit 7fe3ffff flags 60000201 index 10
1429 14:47:59.723592 USB0 port 0 child on link 0 USB2 port 0
1430 14:47:59.726915 USB2 port 0
1431 14:47:59.730063 USB2 port 1
1432 14:47:59.730166 USB2 port 2
1433 14:47:59.733433 USB2 port 3
1434 14:47:59.733536 USB2 port 4
1435 14:47:59.736960 USB2 port 5
1436 14:47:59.737064 USB2 port 6
1437 14:47:59.739856 USB2 port 7
1438 14:47:59.739960 USB2 port 8
1439 14:47:59.743381 USB2 port 9
1440 14:47:59.743484 USB3 port 0
1441 14:47:59.746497 USB3 port 1
1442 14:47:59.746602 USB3 port 2
1443 14:47:59.750248 USB3 port 3
1444 14:47:59.750352 PCI: 00:14.2
1445 14:47:59.762830 PCI: 00:14.2 resource base 7fe40000 size 4000 align 14 gran 14 limit 7fe43fff flags 60000201 index 10
1446 14:47:59.773324 PCI: 00:14.2 resource base 7fe4d000 size 1000 align 12 gran 12 limit 7fe4dfff flags 60000201 index 18
1447 14:47:59.776666 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1448 14:47:59.786654 PCI: 00:14.3 resource base 7fe44000 size 4000 align 14 gran 14 limit 7fe47fff flags 60000201 index 10
1449 14:47:59.789671 GENERIC: 0.0
1450 14:47:59.793065 PCI: 00:15.0 child on link 0 I2C: 00:1a
1451 14:47:59.802910 PCI: 00:15.0 resource base 7fe4e000 size 1000 align 12 gran 12 limit 7fe4efff flags 60000201 index 10
1452 14:47:59.806355 I2C: 00:1a
1453 14:47:59.806459 I2C: 00:31
1454 14:47:59.809652 I2C: 00:32
1455 14:47:59.812841 PCI: 00:15.1 child on link 0 I2C: 00:10
1456 14:47:59.822667 PCI: 00:15.1 resource base 7fe4f000 size 1000 align 12 gran 12 limit 7fe4ffff flags 60000201 index 10
1457 14:47:59.822817 I2C: 00:10
1458 14:47:59.826193 PCI: 00:15.2
1459 14:47:59.835960 PCI: 00:15.2 resource base 7fe50000 size 1000 align 12 gran 12 limit 7fe50fff flags 60000201 index 10
1460 14:47:59.839513 PCI: 00:15.3
1461 14:47:59.849509 PCI: 00:15.3 resource base 7fe51000 size 1000 align 12 gran 12 limit 7fe51fff flags 60000201 index 10
1462 14:47:59.849600 PCI: 00:16.0
1463 14:47:59.858931 PCI: 00:16.0 resource base 7fe52000 size 1000 align 12 gran 12 limit 7fe52fff flags 60000201 index 10
1464 14:47:59.862250 PCI: 00:19.0
1465 14:47:59.865779 PCI: 00:19.1 child on link 0 I2C: 00:15
1466 14:47:59.875585 PCI: 00:19.1 resource base 7fe53000 size 1000 align 12 gran 12 limit 7fe53fff flags 60000201 index 10
1467 14:47:59.878522 I2C: 00:15
1468 14:47:59.882107 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1469 14:47:59.892001 PCI: 00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1470 14:47:59.901887 PCI: 00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1471 14:47:59.915249 PCI: 00:1d.0 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60080202 index 20
1472 14:47:59.915559 GENERIC: 0.0
1473 14:47:59.918794 PCI: 01:00.0
1474 14:47:59.928755 PCI: 01:00.0 resource base 7fc00000 size 4000 align 14 gran 14 limit 7fc03fff flags 60000201 index 10
1475 14:47:59.938753 PCI: 01:00.0 resource base 7fc04000 size 100 align 12 gran 8 limit 7fc040ff flags 60000201 index 20
1476 14:47:59.939185 PCI: 00:1e.0
1477 14:47:59.951929 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1478 14:47:59.954852 PCI: 00:1e.2 child on link 0 SPI: 00
1479 14:47:59.965486 PCI: 00:1e.2 resource base 7fe54000 size 1000 align 12 gran 12 limit 7fe54fff flags 60000201 index 10
1480 14:47:59.968334 SPI: 00
1481 14:47:59.971426 PCI: 00:1e.3 child on link 0 SPI: 00
1482 14:47:59.981681 PCI: 00:1e.3 resource base 7fe55000 size 1000 align 12 gran 12 limit 7fe55fff flags 60000201 index 10
1483 14:47:59.982127 SPI: 00
1484 14:47:59.988210 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1485 14:47:59.994362 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1486 14:47:59.997958 PNP: 0c09.0
1487 14:48:00.004695 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1488 14:48:00.011167 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1489 14:48:00.021062 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1490 14:48:00.027640 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1491 14:48:00.034197 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1492 14:48:00.034640 GENERIC: 0.0
1493 14:48:00.037645 GENERIC: 1.0
1494 14:48:00.038048 PCI: 00:1f.3
1495 14:48:00.050583 PCI: 00:1f.3 resource base 7fe48000 size 4000 align 14 gran 14 limit 7fe4bfff flags 60000201 index 10
1496 14:48:00.060312 PCI: 00:1f.3 resource base 7fd00000 size 100000 align 20 gran 20 limit 7fdfffff flags 60000201 index 20
1497 14:48:00.060752 PCI: 00:1f.5
1498 14:48:00.070345 PCI: 00:1f.5 resource base 7fe56000 size 1000 align 12 gran 12 limit 7fe56fff flags 60000200 index 10
1499 14:48:00.077335 CPU_CLUSTER: 0 child on link 0 APIC: 00
1500 14:48:00.077763 APIC: 00
1501 14:48:00.078100 APIC: 01
1502 14:48:00.080864 APIC: 03
1503 14:48:00.081292 APIC: 05
1504 14:48:00.083388 APIC: 07
1505 14:48:00.083813 APIC: 06
1506 14:48:00.084204 APIC: 02
1507 14:48:00.086922 APIC: 04
1508 14:48:00.090462 Done allocating resources.
1509 14:48:00.093323 BS: BS_DEV_RESOURCES run times (exec / console): 26 / 2475 ms
1510 14:48:00.100234 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
1511 14:48:00.103631 Configure GPIOs for I2S audio on UP4.
1512 14:48:00.111105 BS: BS_DEV_ENABLE entry times (exec / console): 2 / 9 ms
1513 14:48:00.114345 Enabling resources...
1514 14:48:00.117364 PCI: 00:00.0 subsystem <- 8086/9a12
1515 14:48:00.120792 PCI: 00:00.0 cmd <- 06
1516 14:48:00.123980 PCI: 00:02.0 subsystem <- 8086/9a40
1517 14:48:00.127607 PCI: 00:02.0 cmd <- 03
1518 14:48:00.130341 PCI: 00:04.0 subsystem <- 8086/9a03
1519 14:48:00.133634 PCI: 00:04.0 cmd <- 02
1520 14:48:00.136958 PCI: 00:05.0 subsystem <- 8086/9a19
1521 14:48:00.137034 PCI: 00:05.0 cmd <- 02
1522 14:48:00.143678 PCI: 00:08.0 subsystem <- 8086/9a11
1523 14:48:00.143769 PCI: 00:08.0 cmd <- 06
1524 14:48:00.147091 PCI: 00:0d.0 subsystem <- 8086/9a13
1525 14:48:00.150436 PCI: 00:0d.0 cmd <- 02
1526 14:48:00.153772 PCI: 00:14.0 subsystem <- 8086/a0ed
1527 14:48:00.156863 PCI: 00:14.0 cmd <- 02
1528 14:48:00.160494 PCI: 00:14.2 subsystem <- 8086/a0ef
1529 14:48:00.163732 PCI: 00:14.2 cmd <- 02
1530 14:48:00.167045 PCI: 00:14.3 subsystem <- 8086/a0f0
1531 14:48:00.170325 PCI: 00:14.3 cmd <- 02
1532 14:48:00.173660 PCI: 00:15.0 subsystem <- 8086/a0e8
1533 14:48:00.176706 PCI: 00:15.0 cmd <- 02
1534 14:48:00.180169 PCI: 00:15.1 subsystem <- 8086/a0e9
1535 14:48:00.183770 PCI: 00:15.1 cmd <- 02
1536 14:48:00.186709 PCI: 00:15.2 subsystem <- 8086/a0ea
1537 14:48:00.186794 PCI: 00:15.2 cmd <- 02
1538 14:48:00.193691 PCI: 00:15.3 subsystem <- 8086/a0eb
1539 14:48:00.193783 PCI: 00:15.3 cmd <- 02
1540 14:48:00.196718 PCI: 00:16.0 subsystem <- 8086/a0e0
1541 14:48:00.199962 PCI: 00:16.0 cmd <- 02
1542 14:48:00.203506 PCI: 00:19.1 subsystem <- 8086/a0c6
1543 14:48:00.206666 PCI: 00:19.1 cmd <- 02
1544 14:48:00.209985 PCI: 00:1d.0 bridge ctrl <- 0013
1545 14:48:00.213088 PCI: 00:1d.0 subsystem <- 8086/a0b0
1546 14:48:00.216661 PCI: 00:1d.0 cmd <- 06
1547 14:48:00.219790 PCI: 00:1e.0 subsystem <- 8086/a0a8
1548 14:48:00.223335 PCI: 00:1e.0 cmd <- 06
1549 14:48:00.226491 PCI: 00:1e.2 subsystem <- 8086/a0aa
1550 14:48:00.229902 PCI: 00:1e.2 cmd <- 06
1551 14:48:00.232998 PCI: 00:1e.3 subsystem <- 8086/a0ab
1552 14:48:00.236109 PCI: 00:1e.3 cmd <- 02
1553 14:48:00.239468 PCI: 00:1f.0 subsystem <- 8086/a087
1554 14:48:00.239570 PCI: 00:1f.0 cmd <- 407
1555 14:48:00.246483 PCI: 00:1f.3 subsystem <- 8086/a0c8
1556 14:48:00.246598 PCI: 00:1f.3 cmd <- 02
1557 14:48:00.249907 PCI: 00:1f.5 subsystem <- 8086/a0a4
1558 14:48:00.253060 PCI: 00:1f.5 cmd <- 406
1559 14:48:00.258007 PCI: 01:00.0 cmd <- 02
1560 14:48:00.262407 done.
1561 14:48:00.265962 BS: BS_DEV_ENABLE run times (exec / console): 10 / 140 ms
1562 14:48:00.269223 Initializing devices...
1563 14:48:00.272570 Root Device init
1564 14:48:00.276060 Chrome EC: Set SMI mask to 0x0000000000000000
1565 14:48:00.282680 Chrome EC: clear events_b mask to 0x0000000000000000
1566 14:48:00.289412 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1567 14:48:00.295789 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001800101e
1568 14:48:00.302393 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001800101e
1569 14:48:00.305527 Chrome EC: Set WAKE mask to 0x0000000000000000
1570 14:48:00.312896 fw_config match found: DB_USB=USB3_ACTIVE
1571 14:48:00.316167 Configure Right Type-C port orientation for retimer
1572 14:48:00.319567 Root Device init finished in 45 msecs
1573 14:48:00.323590 PCI: 00:00.0 init
1574 14:48:00.327004 CPU TDP = 9 Watts
1575 14:48:00.327455 CPU PL1 = 9 Watts
1576 14:48:00.330435 CPU PL2 = 40 Watts
1577 14:48:00.333515 CPU PL4 = 83 Watts
1578 14:48:00.336976 PCI: 00:00.0 init finished in 8 msecs
1579 14:48:00.337413 PCI: 00:02.0 init
1580 14:48:00.340353 GMA: Found VBT in CBFS
1581 14:48:00.343726 GMA: Found valid VBT in CBFS
1582 14:48:00.349879 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1583 14:48:00.356756 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
1584 14:48:00.360163 PCI: 00:02.0 init finished in 18 msecs
1585 14:48:00.363638 PCI: 00:05.0 init
1586 14:48:00.366903 PCI: 00:05.0 init finished in 0 msecs
1587 14:48:00.369916 PCI: 00:08.0 init
1588 14:48:00.372885 PCI: 00:08.0 init finished in 0 msecs
1589 14:48:00.376409 PCI: 00:14.0 init
1590 14:48:00.379929 PCI: 00:14.0 init finished in 0 msecs
1591 14:48:00.383231 PCI: 00:14.2 init
1592 14:48:00.386139 PCI: 00:14.2 init finished in 0 msecs
1593 14:48:00.389523 PCI: 00:15.0 init
1594 14:48:00.392750 I2C bus 0 version 0x3230302a
1595 14:48:00.396551 DW I2C bus 0 at 0x7fe4e000 (400 KHz)
1596 14:48:00.399306 PCI: 00:15.0 init finished in 6 msecs
1597 14:48:00.399738 PCI: 00:15.1 init
1598 14:48:00.402698 I2C bus 1 version 0x3230302a
1599 14:48:00.406101 DW I2C bus 1 at 0x7fe4f000 (400 KHz)
1600 14:48:00.412825 PCI: 00:15.1 init finished in 6 msecs
1601 14:48:00.413268 PCI: 00:15.2 init
1602 14:48:00.416341 I2C bus 2 version 0x3230302a
1603 14:48:00.419551 DW I2C bus 2 at 0x7fe50000 (400 KHz)
1604 14:48:00.422499 PCI: 00:15.2 init finished in 6 msecs
1605 14:48:00.425956 PCI: 00:15.3 init
1606 14:48:00.429509 I2C bus 3 version 0x3230302a
1607 14:48:00.432382 DW I2C bus 3 at 0x7fe51000 (400 KHz)
1608 14:48:00.436138 PCI: 00:15.3 init finished in 6 msecs
1609 14:48:00.439370 PCI: 00:16.0 init
1610 14:48:00.442591 PCI: 00:16.0 init finished in 0 msecs
1611 14:48:00.445857 PCI: 00:19.1 init
1612 14:48:00.448833 I2C bus 5 version 0x3230302a
1613 14:48:00.452295 DW I2C bus 5 at 0x7fe53000 (400 KHz)
1614 14:48:00.455596 PCI: 00:19.1 init finished in 6 msecs
1615 14:48:00.458670 PCI: 00:1d.0 init
1616 14:48:00.462157 Initializing PCH PCIe bridge.
1617 14:48:00.465677 PCI: 00:1d.0 init finished in 3 msecs
1618 14:48:00.468728 PCI: 00:1f.0 init
1619 14:48:00.472344 IOAPIC: Initializing IOAPIC at 0xfec00000
1620 14:48:00.475211 IOAPIC: Bootstrap Processor Local APIC = 0x00
1621 14:48:00.478584 IOAPIC: ID = 0x02
1622 14:48:00.481826 IOAPIC: Dumping registers
1623 14:48:00.482259 reg 0x0000: 0x02000000
1624 14:48:00.485211 reg 0x0001: 0x00770020
1625 14:48:00.488618 reg 0x0002: 0x00000000
1626 14:48:00.491765 PCI: 00:1f.0 init finished in 21 msecs
1627 14:48:00.495748 PCI: 00:1f.2 init
1628 14:48:00.498309 Disabling ACPI via APMC.
1629 14:48:00.502035 APMC done.
1630 14:48:00.505365 PCI: 00:1f.2 init finished in 6 msecs
1631 14:48:00.517275 PCI: 01:00.0 init
1632 14:48:00.520205 PCI: 01:00.0 init finished in 0 msecs
1633 14:48:00.523405 PNP: 0c09.0 init
1634 14:48:00.530853 Google Chrome EC uptime: 8.264 seconds
1635 14:48:00.534259 Google Chrome AP resets since EC boot: 1
1636 14:48:00.537569 Google Chrome most recent AP reset causes:
1637 14:48:00.540871 0.452: 32775 shutdown: entering G3
1638 14:48:00.547295 Google Chrome EC reset flags at last EC boot: reset-pin | sysjump
1639 14:48:00.550420 PNP: 0c09.0 init finished in 24 msecs
1640 14:48:00.557096 Devices initialized
1641 14:48:00.560663 Show all devs... After init.
1642 14:48:00.564259 Root Device: enabled 1
1643 14:48:00.564708 DOMAIN: 0000: enabled 1
1644 14:48:00.567458 CPU_CLUSTER: 0: enabled 1
1645 14:48:00.570853 PCI: 00:00.0: enabled 1
1646 14:48:00.574120 PCI: 00:02.0: enabled 1
1647 14:48:00.574582 PCI: 00:04.0: enabled 1
1648 14:48:00.577266 PCI: 00:05.0: enabled 1
1649 14:48:00.580529 PCI: 00:06.0: enabled 0
1650 14:48:00.584001 PCI: 00:07.0: enabled 0
1651 14:48:00.584438 PCI: 00:07.1: enabled 0
1652 14:48:00.586903 PCI: 00:07.2: enabled 0
1653 14:48:00.590562 PCI: 00:07.3: enabled 0
1654 14:48:00.593768 PCI: 00:08.0: enabled 1
1655 14:48:00.594288 PCI: 00:09.0: enabled 0
1656 14:48:00.597205 PCI: 00:0a.0: enabled 0
1657 14:48:00.600661 PCI: 00:0d.0: enabled 1
1658 14:48:00.603698 PCI: 00:0d.1: enabled 0
1659 14:48:00.604173 PCI: 00:0d.2: enabled 0
1660 14:48:00.606768 PCI: 00:0d.3: enabled 0
1661 14:48:00.610054 PCI: 00:0e.0: enabled 0
1662 14:48:00.610601 PCI: 00:10.2: enabled 1
1663 14:48:00.613718 PCI: 00:10.6: enabled 0
1664 14:48:00.616757 PCI: 00:10.7: enabled 0
1665 14:48:00.620263 PCI: 00:12.0: enabled 0
1666 14:48:00.620700 PCI: 00:12.6: enabled 0
1667 14:48:00.623538 PCI: 00:13.0: enabled 0
1668 14:48:00.626647 PCI: 00:14.0: enabled 1
1669 14:48:00.630226 PCI: 00:14.1: enabled 0
1670 14:48:00.630651 PCI: 00:14.2: enabled 1
1671 14:48:00.633311 PCI: 00:14.3: enabled 1
1672 14:48:00.636758 PCI: 00:15.0: enabled 1
1673 14:48:00.640167 PCI: 00:15.1: enabled 1
1674 14:48:00.640648 PCI: 00:15.2: enabled 1
1675 14:48:00.643711 PCI: 00:15.3: enabled 1
1676 14:48:00.646595 PCI: 00:16.0: enabled 1
1677 14:48:00.649899 PCI: 00:16.1: enabled 0
1678 14:48:00.650366 PCI: 00:16.2: enabled 0
1679 14:48:00.653167 PCI: 00:16.3: enabled 0
1680 14:48:00.656466 PCI: 00:16.4: enabled 0
1681 14:48:00.659823 PCI: 00:16.5: enabled 0
1682 14:48:00.659942 PCI: 00:17.0: enabled 0
1683 14:48:00.663240 PCI: 00:19.0: enabled 0
1684 14:48:00.665954 PCI: 00:19.1: enabled 1
1685 14:48:00.666039 PCI: 00:19.2: enabled 0
1686 14:48:00.669570 PCI: 00:1c.0: enabled 1
1687 14:48:00.673016 PCI: 00:1c.1: enabled 0
1688 14:48:00.676278 PCI: 00:1c.2: enabled 0
1689 14:48:00.676374 PCI: 00:1c.3: enabled 0
1690 14:48:00.679286 PCI: 00:1c.4: enabled 0
1691 14:48:00.683038 PCI: 00:1c.5: enabled 0
1692 14:48:00.685992 PCI: 00:1c.6: enabled 1
1693 14:48:00.686097 PCI: 00:1c.7: enabled 0
1694 14:48:00.689256 PCI: 00:1d.0: enabled 1
1695 14:48:00.692696 PCI: 00:1d.1: enabled 0
1696 14:48:00.695959 PCI: 00:1d.2: enabled 1
1697 14:48:00.696083 PCI: 00:1d.3: enabled 0
1698 14:48:00.699392 PCI: 00:1e.0: enabled 1
1699 14:48:00.702622 PCI: 00:1e.1: enabled 0
1700 14:48:00.706134 PCI: 00:1e.2: enabled 1
1701 14:48:00.706289 PCI: 00:1e.3: enabled 1
1702 14:48:00.709446 PCI: 00:1f.0: enabled 1
1703 14:48:00.712376 PCI: 00:1f.1: enabled 0
1704 14:48:00.715745 PCI: 00:1f.2: enabled 1
1705 14:48:00.715995 PCI: 00:1f.3: enabled 1
1706 14:48:00.719105 PCI: 00:1f.4: enabled 0
1707 14:48:00.722738 PCI: 00:1f.5: enabled 1
1708 14:48:00.723027 PCI: 00:1f.6: enabled 0
1709 14:48:00.726303 PCI: 00:1f.7: enabled 0
1710 14:48:00.729609 APIC: 00: enabled 1
1711 14:48:00.732417 GENERIC: 0.0: enabled 1
1712 14:48:00.732866 GENERIC: 0.0: enabled 1
1713 14:48:00.736163 GENERIC: 1.0: enabled 1
1714 14:48:00.739353 GENERIC: 0.0: enabled 1
1715 14:48:00.742553 GENERIC: 1.0: enabled 1
1716 14:48:00.743034 USB0 port 0: enabled 1
1717 14:48:00.745920 GENERIC: 0.0: enabled 1
1718 14:48:00.749348 USB0 port 0: enabled 1
1719 14:48:00.749826 GENERIC: 0.0: enabled 1
1720 14:48:00.752836 I2C: 00:1a: enabled 1
1721 14:48:00.755863 I2C: 00:31: enabled 1
1722 14:48:00.756361 I2C: 00:32: enabled 1
1723 14:48:00.759269 I2C: 00:10: enabled 1
1724 14:48:00.762446 I2C: 00:15: enabled 1
1725 14:48:00.765978 GENERIC: 0.0: enabled 0
1726 14:48:00.766492 GENERIC: 1.0: enabled 0
1727 14:48:00.768927 GENERIC: 0.0: enabled 1
1728 14:48:00.772320 SPI: 00: enabled 1
1729 14:48:00.772755 SPI: 00: enabled 1
1730 14:48:00.775671 PNP: 0c09.0: enabled 1
1731 14:48:00.778840 GENERIC: 0.0: enabled 1
1732 14:48:00.779270 USB3 port 0: enabled 1
1733 14:48:00.782344 USB3 port 1: enabled 1
1734 14:48:00.785336 USB3 port 2: enabled 0
1735 14:48:00.785640 USB3 port 3: enabled 0
1736 14:48:00.788600 USB2 port 0: enabled 0
1737 14:48:00.792202 USB2 port 1: enabled 1
1738 14:48:00.795000 USB2 port 2: enabled 1
1739 14:48:00.795191 USB2 port 3: enabled 0
1740 14:48:00.798593 USB2 port 4: enabled 1
1741 14:48:00.801855 USB2 port 5: enabled 0
1742 14:48:00.802008 USB2 port 6: enabled 0
1743 14:48:00.804916 USB2 port 7: enabled 0
1744 14:48:00.808613 USB2 port 8: enabled 0
1745 14:48:00.811846 USB2 port 9: enabled 0
1746 14:48:00.812001 USB3 port 0: enabled 0
1747 14:48:00.815094 USB3 port 1: enabled 1
1748 14:48:00.818079 USB3 port 2: enabled 0
1749 14:48:00.818299 USB3 port 3: enabled 0
1750 14:48:00.821880 GENERIC: 0.0: enabled 1
1751 14:48:00.825043 GENERIC: 1.0: enabled 1
1752 14:48:00.828342 APIC: 01: enabled 1
1753 14:48:00.828530 APIC: 03: enabled 1
1754 14:48:00.831672 APIC: 05: enabled 1
1755 14:48:00.831827 APIC: 07: enabled 1
1756 14:48:00.834889 APIC: 06: enabled 1
1757 14:48:00.838234 APIC: 02: enabled 1
1758 14:48:00.838407 APIC: 04: enabled 1
1759 14:48:00.841807 PCI: 01:00.0: enabled 1
1760 14:48:00.848177 BS: BS_DEV_INIT run times (exec / console): 34 / 540 ms
1761 14:48:00.851254 FMAP: area RW_ELOG found @ f30000 (4096 bytes)
1762 14:48:00.854674 ELOG: NV offset 0xf30000 size 0x1000
1763 14:48:00.862494 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1764 14:48:00.868853 ELOG: Event(17) added with size 13 at 2022-09-30 14:47:02 UTC
1765 14:48:00.875441 ELOG: Event(92) added with size 9 at 2022-09-30 14:47:02 UTC
1766 14:48:00.881894 ELOG: Event(93) added with size 9 at 2022-09-30 14:47:02 UTC
1767 14:48:00.888736 ELOG: Event(9E) added with size 10 at 2022-09-30 14:47:02 UTC
1768 14:48:00.895140 ELOG: Event(9F) added with size 14 at 2022-09-30 14:47:02 UTC
1769 14:48:00.901886 BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms
1770 14:48:00.908489 ELOG: Event(A1) added with size 10 at 2022-09-30 14:47:02 UTC
1771 14:48:00.914862 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1772 14:48:00.921388 ELOG: Event(A0) added with size 9 at 2022-09-30 14:47:02 UTC
1773 14:48:00.924750 elog_add_boot_reason: Logged dev mode boot
1774 14:48:00.931421 BS: BS_POST_DEVICE entry times (exec / console): 0 / 24 ms
1775 14:48:00.931506 Finalize devices...
1776 14:48:00.934959 Devices finalized
1777 14:48:00.941304 BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
1778 14:48:00.944634 FMAP: area RW_NVRAM found @ f37000 (24576 bytes)
1779 14:48:00.951222 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
1780 14:48:00.954519 ME: HFSTS1 : 0x80030055
1781 14:48:00.961282 ME: HFSTS2 : 0x30280116
1782 14:48:00.964599 ME: HFSTS3 : 0x00000050
1783 14:48:00.967924 ME: HFSTS4 : 0x00004000
1784 14:48:00.974313 ME: HFSTS5 : 0x00000000
1785 14:48:00.977504 ME: HFSTS6 : 0x40400006
1786 14:48:00.981130 ME: Manufacturing Mode : YES
1787 14:48:00.984108 ME: SPI Protection Mode Enabled : NO
1788 14:48:00.990888 ME: FW Partition Table : OK
1789 14:48:00.994331 ME: Bringup Loader Failure : NO
1790 14:48:00.997523 ME: Firmware Init Complete : NO
1791 14:48:01.000887 ME: Boot Options Present : NO
1792 14:48:01.004262 ME: Update In Progress : NO
1793 14:48:01.007779 ME: D0i3 Support : YES
1794 14:48:01.011519 ME: Low Power State Enabled : NO
1795 14:48:01.014318 ME: CPU Replaced : YES
1796 14:48:01.020799 ME: CPU Replacement Valid : YES
1797 14:48:01.024133 ME: Current Working State : 5
1798 14:48:01.027699 ME: Current Operation State : 1
1799 14:48:01.030917 ME: Current Operation Mode : 3
1800 14:48:01.033870 ME: Error Code : 0
1801 14:48:01.037858 ME: Enhanced Debug Mode : NO
1802 14:48:01.040983 ME: CPU Debug Disabled : YES
1803 14:48:01.044535 ME: TXT Support : NO
1804 14:48:01.050573 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 94 ms
1805 14:48:01.057637 CBFS: Found 'fallback/dsdt.aml' @0x72f80 size 0x5a67 in mcache @0x76c4c1c4
1806 14:48:01.060945 CBFS: 'fallback/slic' not found.
1807 14:48:01.067339 ACPI: Writing ACPI tables at 76b01000.
1808 14:48:01.067430 ACPI: * FACS
1809 14:48:01.070925 ACPI: * DSDT
1810 14:48:01.074309 Ramoops buffer: 0x100000@0x76a00000.
1811 14:48:01.077359 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
1812 14:48:01.083811 FMAP: area RW_VPD found @ f35000 (8192 bytes)
1813 14:48:01.087243 Google Chrome EC: version:
1814 14:48:01.090570 ro: voema_v2.0.10114-a447f03e46
1815 14:48:01.093833 rw: voema_v2.0.10114-a447f03e46
1816 14:48:01.097207 running image: 2
1817 14:48:01.103145 PCI space above 4GB MMIO is at 0x480400000, len = 0x7b7fc00000
1818 14:48:01.106673 ACPI: * FADT
1819 14:48:01.106836 SCI is IRQ9
1820 14:48:01.110282 ACPI: added table 1/32, length now 40
1821 14:48:01.113969 ACPI: * SSDT
1822 14:48:01.116666 Found 1 CPU(s) with 8 core(s) each.
1823 14:48:01.120103 \_SB.PCI0.PMC: Intel Tigerlake at PCI: 00:1f.2
1824 14:48:01.123244 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
1825 14:48:01.130192 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
1826 14:48:01.133364 \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
1827 14:48:01.140123 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
1828 14:48:01.143517 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
1829 14:48:01.150154 \_SB.PCI0.I2C1.H010: ELAN Touchscreen at I2C: 00:10
1830 14:48:01.153416 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
1831 14:48:01.163293 \_SB.PCI0.RP09: Enable RTD3 for PCI: 00:1d.0 (Intel PCIe Runtime D3)
1832 14:48:01.166837 \_SB.PCI0.RP09: Added StorageD3Enable property
1833 14:48:01.169915 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1834 14:48:01.176983 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
1835 14:48:01.183807 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
1836 14:48:01.186637 PS2K: Passing 80 keymaps to kernel
1837 14:48:01.193299 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
1838 14:48:01.199584 \_SB.PCI0.TXHC.RHUB.SS02: USB3 Type-C Port C1 (DB) at USB3 port 1
1839 14:48:01.206452 \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-A Port A1 (DB) at USB2 port 1
1840 14:48:01.213141 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
1841 14:48:01.219808 \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-C Port C0 (MLB) at USB2 port 4
1842 14:48:01.226421 \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Port A1 (DB) at USB3 port 1
1843 14:48:01.232759 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
1844 14:48:01.239442 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
1845 14:48:01.243060 ACPI: added table 2/32, length now 44
1846 14:48:01.243481 ACPI: * MCFG
1847 14:48:01.249641 ACPI: added table 3/32, length now 48
1848 14:48:01.250061 ACPI: * TPM2
1849 14:48:01.252396 TPM2 log created at 0x769f0000
1850 14:48:01.256535 ACPI: added table 4/32, length now 52
1851 14:48:01.259315 ACPI: * MADT
1852 14:48:01.259748 SCI is IRQ9
1853 14:48:01.262578 ACPI: added table 5/32, length now 56
1854 14:48:01.265949 current = 76b09850
1855 14:48:01.266473 ACPI: * DMAR
1856 14:48:01.269516 ACPI: added table 6/32, length now 60
1857 14:48:01.275921 ACPI: added table 7/32, length now 64
1858 14:48:01.276345 ACPI: * HPET
1859 14:48:01.279571 ACPI: added table 8/32, length now 68
1860 14:48:01.282554 ACPI: done.
1861 14:48:01.282992 ACPI tables: 35216 bytes.
1862 14:48:01.286212 smbios_write_tables: 769ef000
1863 14:48:01.289481 EC returned error result code 3
1864 14:48:01.292698 Couldn't obtain OEM name from CBI
1865 14:48:01.297694 Create SMBIOS type 16
1866 14:48:01.301049 Create SMBIOS type 17
1867 14:48:01.303983 GENERIC: 0.0 (WIFI Device)
1868 14:48:01.307204 SMBIOS tables: 1734 bytes.
1869 14:48:01.310889 Writing table forward entry at 0x00000500
1870 14:48:01.317567 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 392c
1871 14:48:01.321024 Writing coreboot table at 0x76b25000
1872 14:48:01.327500 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1873 14:48:01.330384 1. 0000000000001000-000000000009ffff: RAM
1874 14:48:01.333785 2. 00000000000a0000-00000000000fffff: RESERVED
1875 14:48:01.340570 3. 0000000000100000-00000000769eefff: RAM
1876 14:48:01.344597 4. 00000000769ef000-0000000076b97fff: CONFIGURATION TABLES
1877 14:48:01.350392 5. 0000000076b98000-0000000076c09fff: RAMSTAGE
1878 14:48:01.357102 6. 0000000076c0a000-0000000076ffffff: CONFIGURATION TABLES
1879 14:48:01.360618 7. 0000000077000000-000000007fbfffff: RESERVED
1880 14:48:01.367191 8. 00000000c0000000-00000000cfffffff: RESERVED
1881 14:48:01.370250 9. 00000000f8000000-00000000f9ffffff: RESERVED
1882 14:48:01.373772 10. 00000000fb000000-00000000fb000fff: RESERVED
1883 14:48:01.380610 11. 00000000fe000000-00000000fe00ffff: RESERVED
1884 14:48:01.383782 12. 00000000fed80000-00000000fed87fff: RESERVED
1885 14:48:01.390352 13. 00000000fed90000-00000000fed92fff: RESERVED
1886 14:48:01.393999 14. 00000000feda0000-00000000feda1fff: RESERVED
1887 14:48:01.400159 15. 00000000fedc0000-00000000feddffff: RESERVED
1888 14:48:01.403214 16. 0000000100000000-00000004803fffff: RAM
1889 14:48:01.406318 Passing 4 GPIOs to payload:
1890 14:48:01.410018 NAME | PORT | POLARITY | VALUE
1891 14:48:01.416555 lid | undefined | high | high
1892 14:48:01.422950 power | undefined | high | low
1893 14:48:01.426188 oprom | undefined | high | low
1894 14:48:01.432939 EC in RW | 0x000000e5 | high | high
1895 14:48:01.439629 Wrote coreboot table at: 0x76b25000, 0x610 bytes, checksum f865
1896 14:48:01.443013 coreboot table: 1576 bytes.
1897 14:48:01.446527 IMD ROOT 0. 0x76fff000 0x00001000
1898 14:48:01.449713 IMD SMALL 1. 0x76ffe000 0x00001000
1899 14:48:01.453204 FSP MEMORY 2. 0x76c4e000 0x003b0000
1900 14:48:01.456618 VPD 3. 0x76c4d000 0x00000367
1901 14:48:01.459617 RO MCACHE 4. 0x76c4c000 0x00000fdc
1902 14:48:01.462864 CONSOLE 5. 0x76c2c000 0x00020000
1903 14:48:01.466392 FMAP 6. 0x76c2b000 0x00000578
1904 14:48:01.472901 TIME STAMP 7. 0x76c2a000 0x00000910
1905 14:48:01.476112 VBOOT WORK 8. 0x76c16000 0x00014000
1906 14:48:01.478842 ROMSTG STCK 9. 0x76c15000 0x00001000
1907 14:48:01.482474 AFTER CAR 10. 0x76c0a000 0x0000b000
1908 14:48:01.485461 RAMSTAGE 11. 0x76b97000 0x00073000
1909 14:48:01.489172 REFCODE 12. 0x76b42000 0x00055000
1910 14:48:01.492143 SMM BACKUP 13. 0x76b32000 0x00010000
1911 14:48:01.498862 4f444749 14. 0x76b30000 0x00002000
1912 14:48:01.502285 EXT VBT15. 0x76b2d000 0x0000219f
1913 14:48:01.506282 COREBOOT 16. 0x76b25000 0x00008000
1914 14:48:01.508814 ACPI 17. 0x76b01000 0x00024000
1915 14:48:01.512206 ACPI GNVS 18. 0x76b00000 0x00001000
1916 14:48:01.515673 RAMOOPS 19. 0x76a00000 0x00100000
1917 14:48:01.519465 TPM2 TCGLOG20. 0x769f0000 0x00010000
1918 14:48:01.522031 SMBIOS 21. 0x769ef000 0x00000800
1919 14:48:01.525523 IMD small region:
1920 14:48:01.528837 IMD ROOT 0. 0x76ffec00 0x00000400
1921 14:48:01.532169 FSP RUNTIME 1. 0x76ffebe0 0x00000004
1922 14:48:01.535304 POWER STATE 2. 0x76ffeb80 0x00000044
1923 14:48:01.542040 ROMSTAGE 3. 0x76ffeb60 0x00000004
1924 14:48:01.545415 MEM INFO 4. 0x76ffe980 0x000001e0
1925 14:48:01.552260 BS: BS_WRITE_TABLES run times (exec / console): 9 / 484 ms
1926 14:48:01.552772 MTRR: Physical address space:
1927 14:48:01.559060 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1928 14:48:01.565768 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1929 14:48:01.572178 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
1930 14:48:01.578544 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
1931 14:48:01.585467 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
1932 14:48:01.591979 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
1933 14:48:01.598356 0x0000000100000000 - 0x0000000480400000 size 0x380400000 type 6
1934 14:48:01.601548 MTRR: Fixed MSR 0x250 0x0606060606060606
1935 14:48:01.604938 MTRR: Fixed MSR 0x258 0x0606060606060606
1936 14:48:01.608382 MTRR: Fixed MSR 0x259 0x0000000000000000
1937 14:48:01.614774 MTRR: Fixed MSR 0x268 0x0606060606060606
1938 14:48:01.618135 MTRR: Fixed MSR 0x269 0x0606060606060606
1939 14:48:01.621857 MTRR: Fixed MSR 0x26a 0x0606060606060606
1940 14:48:01.624911 MTRR: Fixed MSR 0x26b 0x0606060606060606
1941 14:48:01.631695 MTRR: Fixed MSR 0x26c 0x0606060606060606
1942 14:48:01.634941 MTRR: Fixed MSR 0x26d 0x0606060606060606
1943 14:48:01.638167 MTRR: Fixed MSR 0x26e 0x0606060606060606
1944 14:48:01.641303 MTRR: Fixed MSR 0x26f 0x0606060606060606
1945 14:48:01.646315 call enable_fixed_mtrr()
1946 14:48:01.649640 CPU physical address size: 39 bits
1947 14:48:01.655970 MTRR: default type WB/UC MTRR counts: 6/7.
1948 14:48:01.659471 MTRR: WB selected as default type.
1949 14:48:01.666183 MTRR: 0 base 0x0000000077000000 mask 0x0000007fff000000 type 0
1950 14:48:01.669474 MTRR: 1 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
1951 14:48:01.676146 MTRR: 2 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
1952 14:48:01.682861 MTRR: 3 base 0x0000000090000000 mask 0x0000007ff0000000 type 0
1953 14:48:01.689433 MTRR: 4 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
1954 14:48:01.696284 MTRR: 5 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0
1955 14:48:01.699878
1956 14:48:01.700354 MTRR check
1957 14:48:01.703121 Fixed MTRRs : Enabled
1958 14:48:01.703596 Variable MTRRs: Enabled
1959 14:48:01.704009
1960 14:48:01.709987 MTRR: Fixed MSR 0x250 0x0606060606060606
1961 14:48:01.712825 MTRR: Fixed MSR 0x258 0x0606060606060606
1962 14:48:01.716188 MTRR: Fixed MSR 0x259 0x0000000000000000
1963 14:48:01.719818 MTRR: Fixed MSR 0x268 0x0606060606060606
1964 14:48:01.726315 MTRR: Fixed MSR 0x269 0x0606060606060606
1965 14:48:01.729619 MTRR: Fixed MSR 0x26a 0x0606060606060606
1966 14:48:01.733099 MTRR: Fixed MSR 0x26b 0x0606060606060606
1967 14:48:01.736539 MTRR: Fixed MSR 0x26c 0x0606060606060606
1968 14:48:01.742892 MTRR: Fixed MSR 0x26d 0x0606060606060606
1969 14:48:01.746053 MTRR: Fixed MSR 0x26e 0x0606060606060606
1970 14:48:01.749362 MTRR: Fixed MSR 0x26f 0x0606060606060606
1971 14:48:01.756565 BS: BS_WRITE_TABLES exit times (exec / console): 4 / 150 ms
1972 14:48:01.760084 call enable_fixed_mtrr()
1973 14:48:01.763501 Checking cr50 for pending updates
1974 14:48:01.767283 MTRR: Fixed MSR 0x250 0x0606060606060606
1975 14:48:01.770400 MTRR: Fixed MSR 0x250 0x0606060606060606
1976 14:48:01.777300 MTRR: Fixed MSR 0x258 0x0606060606060606
1977 14:48:01.780647 MTRR: Fixed MSR 0x259 0x0000000000000000
1978 14:48:01.784139 MTRR: Fixed MSR 0x268 0x0606060606060606
1979 14:48:01.786987 MTRR: Fixed MSR 0x269 0x0606060606060606
1980 14:48:01.790693 MTRR: Fixed MSR 0x26a 0x0606060606060606
1981 14:48:01.797117 MTRR: Fixed MSR 0x26b 0x0606060606060606
1982 14:48:01.800536 MTRR: Fixed MSR 0x26c 0x0606060606060606
1983 14:48:01.803823 MTRR: Fixed MSR 0x26d 0x0606060606060606
1984 14:48:01.806986 MTRR: Fixed MSR 0x26e 0x0606060606060606
1985 14:48:01.813472 MTRR: Fixed MSR 0x26f 0x0606060606060606
1986 14:48:01.816921 MTRR: Fixed MSR 0x258 0x0606060606060606
1987 14:48:01.824062 MTRR: Fixed MSR 0x259 0x0000000000000000
1988 14:48:01.827030 MTRR: Fixed MSR 0x268 0x0606060606060606
1989 14:48:01.830246 MTRR: Fixed MSR 0x269 0x0606060606060606
1990 14:48:01.833175 MTRR: Fixed MSR 0x26a 0x0606060606060606
1991 14:48:01.839898 MTRR: Fixed MSR 0x26b 0x0606060606060606
1992 14:48:01.843122 MTRR: Fixed MSR 0x26c 0x0606060606060606
1993 14:48:01.847159 MTRR: Fixed MSR 0x26d 0x0606060606060606
1994 14:48:01.850452 MTRR: Fixed MSR 0x26e 0x0606060606060606
1995 14:48:01.856495 MTRR: Fixed MSR 0x26f 0x0606060606060606
1996 14:48:01.860045 call enable_fixed_mtrr()
1997 14:48:01.863193 call enable_fixed_mtrr()
1998 14:48:01.866542 CPU physical address size: 39 bits
1999 14:48:01.870013 Reading cr50 TPM mode
2000 14:48:01.873780 MTRR: Fixed MSR 0x250 0x0606060606060606
2001 14:48:01.877243 MTRR: Fixed MSR 0x250 0x0606060606060606
2002 14:48:01.883718 MTRR: Fixed MSR 0x258 0x0606060606060606
2003 14:48:01.886823 MTRR: Fixed MSR 0x259 0x0000000000000000
2004 14:48:01.890314 MTRR: Fixed MSR 0x268 0x0606060606060606
2005 14:48:01.893927 MTRR: Fixed MSR 0x269 0x0606060606060606
2006 14:48:01.897076 MTRR: Fixed MSR 0x26a 0x0606060606060606
2007 14:48:01.903630 MTRR: Fixed MSR 0x26b 0x0606060606060606
2008 14:48:01.907230 MTRR: Fixed MSR 0x26c 0x0606060606060606
2009 14:48:01.910361 MTRR: Fixed MSR 0x26d 0x0606060606060606
2010 14:48:01.913705 MTRR: Fixed MSR 0x26e 0x0606060606060606
2011 14:48:01.920119 MTRR: Fixed MSR 0x26f 0x0606060606060606
2012 14:48:01.923485 MTRR: Fixed MSR 0x258 0x0606060606060606
2013 14:48:01.930250 MTRR: Fixed MSR 0x259 0x0000000000000000
2014 14:48:01.934099 MTRR: Fixed MSR 0x268 0x0606060606060606
2015 14:48:01.936908 MTRR: Fixed MSR 0x269 0x0606060606060606
2016 14:48:01.939960 MTRR: Fixed MSR 0x26a 0x0606060606060606
2017 14:48:01.946786 MTRR: Fixed MSR 0x26b 0x0606060606060606
2018 14:48:01.950257 MTRR: Fixed MSR 0x26c 0x0606060606060606
2019 14:48:01.953792 MTRR: Fixed MSR 0x26d 0x0606060606060606
2020 14:48:01.957033 MTRR: Fixed MSR 0x26e 0x0606060606060606
2021 14:48:01.963325 MTRR: Fixed MSR 0x26f 0x0606060606060606
2022 14:48:01.966874 call enable_fixed_mtrr()
2023 14:48:01.970274 call enable_fixed_mtrr()
2024 14:48:01.973552 MTRR: Fixed MSR 0x250 0x0606060606060606
2025 14:48:01.976752 MTRR: Fixed MSR 0x250 0x0606060606060606
2026 14:48:01.979742 MTRR: Fixed MSR 0x258 0x0606060606060606
2027 14:48:01.986566 MTRR: Fixed MSR 0x259 0x0000000000000000
2028 14:48:01.989834 MTRR: Fixed MSR 0x268 0x0606060606060606
2029 14:48:01.993214 MTRR: Fixed MSR 0x269 0x0606060606060606
2030 14:48:01.996447 MTRR: Fixed MSR 0x26a 0x0606060606060606
2031 14:48:02.003594 MTRR: Fixed MSR 0x26b 0x0606060606060606
2032 14:48:02.006773 MTRR: Fixed MSR 0x26c 0x0606060606060606
2033 14:48:02.009834 MTRR: Fixed MSR 0x26d 0x0606060606060606
2034 14:48:02.013257 MTRR: Fixed MSR 0x26e 0x0606060606060606
2035 14:48:02.019574 MTRR: Fixed MSR 0x26f 0x0606060606060606
2036 14:48:02.022880 MTRR: Fixed MSR 0x258 0x0606060606060606
2037 14:48:02.026243 call enable_fixed_mtrr()
2038 14:48:02.029558 MTRR: Fixed MSR 0x259 0x0000000000000000
2039 14:48:02.035970 MTRR: Fixed MSR 0x268 0x0606060606060606
2040 14:48:02.039831 MTRR: Fixed MSR 0x269 0x0606060606060606
2041 14:48:02.042569 MTRR: Fixed MSR 0x26a 0x0606060606060606
2042 14:48:02.045843 MTRR: Fixed MSR 0x26b 0x0606060606060606
2043 14:48:02.052733 MTRR: Fixed MSR 0x26c 0x0606060606060606
2044 14:48:02.056329 MTRR: Fixed MSR 0x26d 0x0606060606060606
2045 14:48:02.059463 MTRR: Fixed MSR 0x26e 0x0606060606060606
2046 14:48:02.062674 MTRR: Fixed MSR 0x26f 0x0606060606060606
2047 14:48:02.066900 CPU physical address size: 39 bits
2048 14:48:02.074375 call enable_fixed_mtrr()
2049 14:48:02.076803 CPU physical address size: 39 bits
2050 14:48:02.080328 CPU physical address size: 39 bits
2051 14:48:02.087071 CPU physical address size: 39 bits
2052 14:48:02.090630 CPU physical address size: 39 bits
2053 14:48:02.093759 CPU physical address size: 39 bits
2054 14:48:02.100192 BS: BS_PAYLOAD_LOAD entry times (exec / console): 109 / 8 ms
2055 14:48:02.107076 CBFS: Found 'fallback/payload' @0x38db00 size 0x4be9c in mcache @0x76c4cf60
2056 14:48:02.113415 Checking segment from ROM address 0xffc02b38
2057 14:48:02.116503 Checking segment from ROM address 0xffc02b54
2058 14:48:02.119816 Loading segment from ROM address 0xffc02b38
2059 14:48:02.123115 code (compression=0)
2060 14:48:02.133370 New segment dstaddr 0x30000000 memsize 0x2662db0 srcaddr 0xffc02b70 filesize 0x4be64
2061 14:48:02.139869 Loading Segment: addr: 0x30000000 memsz: 0x0000000002662db0 filesz: 0x000000000004be64
2062 14:48:02.143486 it's not compressed!
2063 14:48:02.283744 [ 0x30000000, 3004be64, 0x32662db0) <- ffc02b70
2064 14:48:02.289747 Clearing Segment: addr: 0x000000003004be64 memsz: 0x0000000002616f4c
2065 14:48:02.296788 Loading segment from ROM address 0xffc02b54
2066 14:48:02.300343 Entry Point 0x30000000
2067 14:48:02.300801 Loaded segments
2068 14:48:02.306761 BS: BS_PAYLOAD_LOAD run times (exec / console): 137 / 63 ms
2069 14:48:02.351716 Finalizing chipset.
2070 14:48:02.354924 Finalizing SMM.
2071 14:48:02.355385 APMC done.
2072 14:48:02.361350 BS: BS_PAYLOAD_LOAD exit times (exec / console): 44 / 5 ms
2073 14:48:02.364569 mp_park_aps done after 0 msecs.
2074 14:48:02.367943 Jumping to boot code at 0x30000000(0x76b25000)
2075 14:48:02.377953 CPU0: stack: 0x76bee000 - 0x76bef000, lowest used address 0x76beea78, stack used: 1416 bytes
2076 14:48:02.381384
2077 14:48:02.382752 end: 2.2.3 depthcharge-start (duration 00:00:16) [common]
2078 14:48:02.383341 start: 2.2.4 bootloader-commands (timeout 00:04:44) [common]
2079 14:48:02.383790 Setting prompt string to ['volteer:']
2080 14:48:02.384265 bootloader-commands: Wait for prompt ['volteer:'] (timeout 00:04:44)
2081 14:48:02.385051 Starting depthcharge on Voema...
2082 14:48:02.391208 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2083 14:48:02.397740 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2084 14:48:02.404385 Looking for NVMe Controller 0x3005f220 @ 00:1d:00
2085 14:48:02.407953 Failed to find eMMC card reader
2086 14:48:02.410951 Wipe memory regions:
2087 14:48:02.414270 [0x00000000001000, 0x000000000a0000)
2088 14:48:02.417552 [0x00000000100000, 0x00000030000000)
2089 14:48:02.456828 [0x00000032662db0, 0x000000769ef000)
2090 14:48:02.509709 [0x00000100000000, 0x00000480400000)
2091 14:48:03.143404 ec_init: CrosEC protocol v3 supported (256, 256)
2092 14:48:03.575031 R8152: Initializing
2093 14:48:03.578184 Version 6 (ocp_data = 5c30)
2094 14:48:03.581580 R8152: Done initializing
2095 14:48:03.585368 Adding net device
2096 14:48:03.890692 [firmware-volteer-13672.B-collabora] Oct 22 2021 06:32:35
2097 14:48:03.891241
2098 14:48:03.894762 Setting prompt string to ['volteer:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2100 14:48:03.996546 volteer: tftpboot 192.168.201.1 7462822/tftp-deploy-64hlhhce/kernel/bzImage 7462822/tftp-deploy-64hlhhce/kernel/cmdline 7462822/tftp-deploy-64hlhhce/ramdisk/ramdisk.cpio.gz
2101 14:48:03.997193 Setting prompt string to 'Starting kernel'
2102 14:48:03.997588 Setting prompt string to ['Starting kernel']
2103 14:48:03.997959 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2104 14:48:03.998362 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:43)
2105 14:48:04.001836 tftpboot 192.168.201.1 7462822/tftp-deploy-64hlhhce/kernel/bzImoy-64hlhhce/kernel/cmdline 7462822/tftp-deploy-64hlhhce/ramdisk/ramdisk.cpio.gz
2106 14:48:04.002287 Waiting for link
2107 14:48:04.205629 done.
2108 14:48:04.206233 MAC: 00:24:32:30:7a:04
2109 14:48:04.208972 Sending DHCP discover... done.
2110 14:48:04.212524 Waiting for reply... done.
2111 14:48:04.215233 Sending DHCP request... done.
2112 14:48:04.218801 Waiting for reply... done.
2113 14:48:04.222193 My ip is 192.168.201.21
2114 14:48:04.225124 The DHCP server ip is 192.168.201.1
2115 14:48:04.228541 TFTP server IP predefined by user: 192.168.201.1
2116 14:48:04.235000 Bootfile predefined by user: 7462822/tftp-deploy-64hlhhce/kernel/bzImage
2117 14:48:04.238654 Sending tftp read request... done.
2118 14:48:04.246534 Waiting for the transfer...
2119 14:48:04.885793 00000000 ################################################################
2120 14:48:05.431930 00080000 ################################################################
2121 14:48:06.058524 00100000 ################################################################
2122 14:48:06.699046 00180000 ################################################################
2123 14:48:07.269821 00200000 ################################################################
2124 14:48:07.786246 00280000 ################################################################
2125 14:48:08.301665 00300000 ################################################################
2126 14:48:08.828305 00380000 ################################################################
2127 14:48:09.342848 00400000 ################################################################
2128 14:48:09.858985 00480000 ################################################################
2129 14:48:10.371854 00500000 ################################################################
2130 14:48:10.892838 00580000 ################################################################
2131 14:48:11.411761 00600000 ################################################################
2132 14:48:11.720005 00680000 ###################################### done.
2133 14:48:11.722777 The bootfile was 7126928 bytes long.
2134 14:48:11.726015 Sending tftp read request... done.
2135 14:48:11.729306 Waiting for the transfer...
2136 14:48:12.295293 00000000 ################################################################
2137 14:48:12.828878 00080000 ################################################################
2138 14:48:13.349277 00100000 ################################################################
2139 14:48:13.874105 00180000 ################################################################
2140 14:48:14.405371 00200000 ################################################################
2141 14:48:14.928014 00280000 ################################################################
2142 14:48:15.461277 00300000 ################################################################
2143 14:48:15.977373 00380000 ################################################################
2144 14:48:16.541134 00400000 ################################################################
2145 14:48:17.099019 00480000 ################################################################
2146 14:48:17.614228 00500000 ################################################################
2147 14:48:18.138145 00580000 ################################################################
2148 14:48:18.658961 00600000 ################################################################
2149 14:48:19.190075 00680000 ################################################################
2150 14:48:19.902388 00700000 ################################################################
2151 14:48:20.619756 00780000 ################################################################
2152 14:48:20.834829 00800000 #################### done.
2153 14:48:20.837842 Sending tftp read request... done.
2154 14:48:20.841765 Waiting for the transfer...
2155 14:48:20.842336 00000000 # done.
2156 14:48:20.851000 Command line loaded dynamically from TFTP file: 7462822/tftp-deploy-64hlhhce/kernel/cmdline
2157 14:48:20.864473 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2158 14:48:20.871911 Shutting down all USB controllers.
2159 14:48:20.872430 Removing current net device
2160 14:48:20.875518 Finalizing coreboot
2161 14:48:20.882008 Exiting depthcharge with code 4 at timestamp: 27081118
2162 14:48:20.882451
2163 14:48:20.882795 Starting kernel ...
2164 14:48:20.883116
2165 14:48:20.883432
2166 14:48:20.884617 end: 2.2.4 bootloader-commands (duration 00:00:19) [common]
2167 14:48:20.885114 start: 2.2.5 auto-login-action (timeout 00:04:26) [common]
2168 14:48:20.885496 Setting prompt string to ['Linux version [0-9]']
2169 14:48:20.885856 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2170 14:48:20.886210 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2172 14:52:46.885954 end: 2.2.5 auto-login-action (duration 00:04:26) [common]
2174 14:52:46.887111 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 266 seconds'
2176 14:52:46.887966 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2179 14:52:46.889396 end: 2 depthcharge-action (duration 00:05:00) [common]
2181 14:52:46.890261 Cleaning after the job
2182 14:52:46.890344 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/7462822/tftp-deploy-64hlhhce/ramdisk
2183 14:52:46.890973 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/7462822/tftp-deploy-64hlhhce/kernel
2184 14:52:46.891473 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/7462822/tftp-deploy-64hlhhce/modules
2185 14:52:46.891670 start: 5.1 power-off (timeout 00:00:30) [common]
2186 14:52:46.891824 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-10' '--port=1' '--command=off'
2187 14:52:46.911128 >> Command sent successfully.
2188 14:52:46.913014 Returned 0 in 0 seconds
2189 14:52:47.014134 end: 5.1 power-off (duration 00:00:00) [common]
2191 14:52:47.015547 start: 5.2 read-feedback (timeout 00:10:00) [common]
2192 14:52:47.016675 Listened to connection for namespace 'common' for up to 1s
2193 14:52:48.019930 Finalising connection for namespace 'common'
2194 14:52:48.020118 Disconnecting from shell: Finalise
2195 14:52:48.120811 end: 5.2 read-feedback (duration 00:00:01) [common]
2196 14:52:48.120930 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/7462822
2197 14:52:48.125756 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/7462822
2198 14:52:48.125873 JobError: Your job cannot terminate cleanly.