Boot log: asus-cx9400-volteer
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: FAIL
- Kernel Errors: 0
1 14:47:33.850180 lava-dispatcher, installed at version: 2022.06
2 14:47:33.850386 start: 0 validate
3 14:47:33.850538 Start time: 2022-09-30 14:47:33.850529+00:00 (UTC)
4 14:47:33.850688 Using caching service: 'http://localhost/cache/?uri=%s'
5 14:47:33.850813 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20220923.1%2Famd64%2Finitrd.cpio.gz exists
6 14:47:34.141581 Using caching service: 'http://localhost/cache/?uri=%s'
7 14:47:34.141796 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv4.4.302-cip70-98-gb2bfffe124dae%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 14:47:34.433842 Using caching service: 'http://localhost/cache/?uri=%s'
9 14:47:34.434015 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20220923.1%2Famd64%2Ffull.rootfs.tar.xz exists
10 14:47:34.725950 Using caching service: 'http://localhost/cache/?uri=%s'
11 14:47:34.726122 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv4.4.302-cip70-98-gb2bfffe124dae%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 14:47:34.729661 validate duration: 0.88
14 14:47:34.729992 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 14:47:34.730119 start: 1.1 download-retry (timeout 00:10:00) [common]
16 14:47:34.730227 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 14:47:34.730338 Not decompressing ramdisk as can be used compressed.
18 14:47:34.730421 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20220923.1/amd64/initrd.cpio.gz
19 14:47:34.730512 saving as /var/lib/lava/dispatcher/tmp/7462823/tftp-deploy-3ksw9d6m/ramdisk/initrd.cpio.gz
20 14:47:34.730571 total size: 5431599 (5MB)
21 14:47:34.733677 progress 0% (0MB)
22 14:47:34.735589 progress 5% (0MB)
23 14:47:34.737884 progress 10% (0MB)
24 14:47:34.740178 progress 15% (0MB)
25 14:47:34.742697 progress 20% (1MB)
26 14:47:34.745150 progress 25% (1MB)
27 14:47:34.747081 progress 30% (1MB)
28 14:47:34.749624 progress 35% (1MB)
29 14:47:34.751837 progress 40% (2MB)
30 14:47:34.753999 progress 45% (2MB)
31 14:47:34.756661 progress 50% (2MB)
32 14:47:34.758779 progress 55% (2MB)
33 14:47:34.761123 progress 60% (3MB)
34 14:47:34.763240 progress 65% (3MB)
35 14:47:34.765890 progress 70% (3MB)
36 14:47:34.767979 progress 75% (3MB)
37 14:47:34.770252 progress 80% (4MB)
38 14:47:34.772431 progress 85% (4MB)
39 14:47:34.775272 progress 90% (4MB)
40 14:47:34.777194 progress 95% (4MB)
41 14:47:34.779306 progress 100% (5MB)
42 14:47:34.779562 5MB downloaded in 0.05s (105.74MB/s)
43 14:47:34.779711 end: 1.1.1 http-download (duration 00:00:00) [common]
45 14:47:34.779959 end: 1.1 download-retry (duration 00:00:00) [common]
46 14:47:34.780047 start: 1.2 download-retry (timeout 00:10:00) [common]
47 14:47:34.780134 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 14:47:34.780240 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v4.4.302-cip70-98-gb2bfffe124dae/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
49 14:47:34.780307 saving as /var/lib/lava/dispatcher/tmp/7462823/tftp-deploy-3ksw9d6m/kernel/bzImage
50 14:47:34.780368 total size: 7126928 (6MB)
51 14:47:34.780427 No compression specified
52 14:47:34.782148 progress 0% (0MB)
53 14:47:34.785196 progress 5% (0MB)
54 14:47:34.788117 progress 10% (0MB)
55 14:47:34.791418 progress 15% (1MB)
56 14:47:34.794277 progress 20% (1MB)
57 14:47:34.797484 progress 25% (1MB)
58 14:47:34.800351 progress 30% (2MB)
59 14:47:34.803858 progress 35% (2MB)
60 14:47:34.806534 progress 40% (2MB)
61 14:47:34.809404 progress 45% (3MB)
62 14:47:34.812795 progress 50% (3MB)
63 14:47:34.815881 progress 55% (3MB)
64 14:47:34.818605 progress 60% (4MB)
65 14:47:34.822044 progress 65% (4MB)
66 14:47:34.825356 progress 70% (4MB)
67 14:47:34.828032 progress 75% (5MB)
68 14:47:34.830683 progress 80% (5MB)
69 14:47:34.833759 progress 85% (5MB)
70 14:47:34.836945 progress 90% (6MB)
71 14:47:34.840067 progress 95% (6MB)
72 14:47:34.843206 progress 100% (6MB)
73 14:47:34.843438 6MB downloaded in 0.06s (107.77MB/s)
74 14:47:34.843591 end: 1.2.1 http-download (duration 00:00:00) [common]
76 14:47:34.843829 end: 1.2 download-retry (duration 00:00:00) [common]
77 14:47:34.843918 start: 1.3 download-retry (timeout 00:10:00) [common]
78 14:47:34.844005 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 14:47:34.844108 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20220923.1/amd64/full.rootfs.tar.xz
80 14:47:34.844174 saving as /var/lib/lava/dispatcher/tmp/7462823/tftp-deploy-3ksw9d6m/nfsrootfs/full.rootfs.tar
81 14:47:34.844236 total size: 133274540 (127MB)
82 14:47:34.844297 Using unxz to decompress xz
83 14:47:34.848902 progress 0% (0MB)
84 14:47:35.195725 progress 5% (6MB)
85 14:47:35.567386 progress 10% (12MB)
86 14:47:35.862028 progress 15% (19MB)
87 14:47:36.068347 progress 20% (25MB)
88 14:47:36.334732 progress 25% (31MB)
89 14:47:36.699597 progress 30% (38MB)
90 14:47:37.073766 progress 35% (44MB)
91 14:47:37.488875 progress 40% (50MB)
92 14:47:37.892547 progress 45% (57MB)
93 14:47:38.274351 progress 50% (63MB)
94 14:47:38.672487 progress 55% (69MB)
95 14:47:39.058909 progress 60% (76MB)
96 14:47:39.436348 progress 65% (82MB)
97 14:47:39.816802 progress 70% (89MB)
98 14:47:40.189221 progress 75% (95MB)
99 14:47:40.646526 progress 80% (101MB)
100 14:47:41.127830 progress 85% (108MB)
101 14:47:41.412105 progress 90% (114MB)
102 14:47:41.771948 progress 95% (120MB)
103 14:47:42.180526 progress 100% (127MB)
104 14:47:42.185734 127MB downloaded in 7.34s (17.31MB/s)
105 14:47:42.186195 end: 1.3.1 http-download (duration 00:00:07) [common]
107 14:47:42.186639 end: 1.3 download-retry (duration 00:00:07) [common]
108 14:47:42.186793 start: 1.4 download-retry (timeout 00:09:53) [common]
109 14:47:42.186942 start: 1.4.1 http-download (timeout 00:09:53) [common]
110 14:47:42.187117 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v4.4.302-cip70-98-gb2bfffe124dae/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
111 14:47:42.187238 saving as /var/lib/lava/dispatcher/tmp/7462823/tftp-deploy-3ksw9d6m/modules/modules.tar
112 14:47:42.187354 total size: 52080 (0MB)
113 14:47:42.187462 Using unxz to decompress xz
114 14:47:42.193109 progress 62% (0MB)
115 14:47:42.193757 progress 100% (0MB)
116 14:47:42.197042 0MB downloaded in 0.01s (5.13MB/s)
117 14:47:42.197368 end: 1.4.1 http-download (duration 00:00:00) [common]
119 14:47:42.197816 end: 1.4 download-retry (duration 00:00:00) [common]
120 14:47:42.197972 start: 1.5 prepare-tftp-overlay (timeout 00:09:53) [common]
121 14:47:42.198127 start: 1.5.1 extract-nfsrootfs (timeout 00:09:53) [common]
122 14:47:43.550198 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/7462823/extract-nfsrootfs-mzugkky2
123 14:47:43.550408 end: 1.5.1 extract-nfsrootfs (duration 00:00:01) [common]
124 14:47:43.550521 start: 1.5.2 lava-overlay (timeout 00:09:51) [common]
125 14:47:43.550660 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc
126 14:47:43.550765 makedir: /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin
127 14:47:43.550851 makedir: /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/tests
128 14:47:43.550936 makedir: /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/results
129 14:47:43.551050 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-add-keys
130 14:47:43.551185 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-add-sources
131 14:47:43.551306 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-background-process-start
132 14:47:43.551422 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-background-process-stop
133 14:47:43.551536 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-common-functions
134 14:47:43.551664 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-echo-ipv4
135 14:47:43.551785 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-install-packages
136 14:47:43.551899 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-installed-packages
137 14:47:43.552010 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-os-build
138 14:47:43.552123 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-probe-channel
139 14:47:43.552233 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-probe-ip
140 14:47:43.552343 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-target-ip
141 14:47:43.552453 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-target-mac
142 14:47:43.552567 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-target-storage
143 14:47:43.552683 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-test-case
144 14:47:43.552798 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-test-event
145 14:47:43.552910 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-test-feedback
146 14:47:43.553049 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-test-raise
147 14:47:43.553189 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-test-reference
148 14:47:43.553306 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-test-runner
149 14:47:43.553419 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-test-set
150 14:47:43.553531 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-test-shell
151 14:47:43.553644 Updating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-install-packages (oe)
152 14:47:43.553770 Updating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/bin/lava-installed-packages (oe)
153 14:47:43.553872 Creating /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/environment
154 14:47:43.553962 LAVA metadata
155 14:47:43.554031 - LAVA_JOB_ID=7462823
156 14:47:43.554097 - LAVA_DISPATCHER_IP=192.168.201.1
157 14:47:43.554203 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:51) [common]
158 14:47:43.554271 skipped lava-vland-overlay
159 14:47:43.554348 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
160 14:47:43.554434 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:51) [common]
161 14:47:43.554500 skipped lava-multinode-overlay
162 14:47:43.554611 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
163 14:47:43.554713 start: 1.5.2.3 test-definition (timeout 00:09:51) [common]
164 14:47:43.554789 Loading test definitions
165 14:47:43.554884 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:51) [common]
166 14:47:43.554961 Using /lava-7462823 at stage 0
167 14:47:43.555222 uuid=7462823_1.5.2.3.1 testdef=None
168 14:47:43.555316 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
169 14:47:43.555406 start: 1.5.2.3.2 test-overlay (timeout 00:09:51) [common]
170 14:47:43.555892 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
172 14:47:43.556130 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:51) [common]
173 14:47:43.556705 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
175 14:47:43.556947 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:51) [common]
176 14:47:43.557491 runner path: /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/0/tests/0_dmesg test_uuid 7462823_1.5.2.3.1
177 14:47:43.557640 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
179 14:47:43.557887 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:51) [common]
180 14:47:43.557963 Using /lava-7462823 at stage 1
181 14:47:43.558212 uuid=7462823_1.5.2.3.5 testdef=None
182 14:47:43.558306 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
183 14:47:43.558397 start: 1.5.2.3.6 test-overlay (timeout 00:09:51) [common]
184 14:47:43.558841 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
186 14:47:43.559073 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:51) [common]
187 14:47:43.559665 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
189 14:47:43.559909 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:51) [common]
190 14:47:43.560466 runner path: /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/1/tests/1_bootrr test_uuid 7462823_1.5.2.3.5
191 14:47:43.560611 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
193 14:47:43.560827 Creating lava-test-runner.conf files
194 14:47:43.560893 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/0 for stage 0
195 14:47:43.560978 - 0_dmesg
196 14:47:43.561054 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/7462823/lava-overlay-d4t636zc/lava-7462823/1 for stage 1
197 14:47:43.561137 - 1_bootrr
198 14:47:43.561256 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
199 14:47:43.561368 start: 1.5.2.4 compress-overlay (timeout 00:09:51) [common]
200 14:47:43.567001 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
201 14:47:43.567136 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:51) [common]
202 14:47:43.567233 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
203 14:47:43.567324 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
204 14:47:43.567415 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:51) [common]
205 14:47:43.677041 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
206 14:47:43.677389 start: 1.5.4 extract-modules (timeout 00:09:51) [common]
207 14:47:43.677509 extracting modules file /var/lib/lava/dispatcher/tmp/7462823/tftp-deploy-3ksw9d6m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/7462823/extract-nfsrootfs-mzugkky2
208 14:47:43.681595 extracting modules file /var/lib/lava/dispatcher/tmp/7462823/tftp-deploy-3ksw9d6m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/7462823/extract-overlay-ramdisk-4gwfeqjk/ramdisk
209 14:47:43.685412 end: 1.5.4 extract-modules (duration 00:00:00) [common]
210 14:47:43.685533 start: 1.5.5 apply-overlay-tftp (timeout 00:09:51) [common]
211 14:47:43.685623 [common] Applying overlay to NFS
212 14:47:43.685698 [common] Applying overlay /var/lib/lava/dispatcher/tmp/7462823/compress-overlay-2ch1fjvt/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/7462823/extract-nfsrootfs-mzugkky2
213 14:47:43.689593 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
214 14:47:43.689712 start: 1.5.6 configure-preseed-file (timeout 00:09:51) [common]
215 14:47:43.689821 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
216 14:47:43.689918 start: 1.5.7 compress-ramdisk (timeout 00:09:51) [common]
217 14:47:43.690000 Building ramdisk /var/lib/lava/dispatcher/tmp/7462823/extract-overlay-ramdisk-4gwfeqjk/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/7462823/extract-overlay-ramdisk-4gwfeqjk/ramdisk
218 14:47:43.726319 >> 24546 blocks
219 14:47:44.210284 rename /var/lib/lava/dispatcher/tmp/7462823/extract-overlay-ramdisk-4gwfeqjk/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/7462823/tftp-deploy-3ksw9d6m/ramdisk/ramdisk.cpio.gz
220 14:47:44.210771 end: 1.5.7 compress-ramdisk (duration 00:00:01) [common]
221 14:47:44.210946 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
222 14:47:44.211094 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
223 14:47:44.211237 No mkimage arch provided, not using FIT.
224 14:47:44.211369 end: 1.5.8.1 prepare-fit (duration 00:00:00) [common]
225 14:47:44.211498 end: 1.5.8 prepare-kernel (duration 00:00:00) [common]
226 14:47:44.211647 end: 1.5 prepare-tftp-overlay (duration 00:00:02) [common]
227 14:47:44.211814 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:51) [common]
228 14:47:44.211937 No LXC device requested
229 14:47:44.212067 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
230 14:47:44.212202 start: 1.7 deploy-device-env (timeout 00:09:51) [common]
231 14:47:44.212331 end: 1.7 deploy-device-env (duration 00:00:00) [common]
232 14:47:44.212470 Checking files for TFTP limit of 4294967296 bytes.
233 14:47:44.213049 end: 1 tftp-deploy (duration 00:00:09) [common]
234 14:47:44.213195 start: 2 depthcharge-action (timeout 00:05:00) [common]
235 14:47:44.213334 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
236 14:47:44.213514 substitutions:
237 14:47:44.213616 - {DTB}: None
238 14:47:44.213715 - {INITRD}: 7462823/tftp-deploy-3ksw9d6m/ramdisk/ramdisk.cpio.gz
239 14:47:44.213852 - {KERNEL}: 7462823/tftp-deploy-3ksw9d6m/kernel/bzImage
240 14:47:44.213949 - {LAVA_MAC}: None
241 14:47:44.214050 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/7462823/extract-nfsrootfs-mzugkky2
242 14:47:44.214147 - {NFS_SERVER_IP}: 192.168.201.1
243 14:47:44.214241 - {PRESEED_CONFIG}: None
244 14:47:44.214336 - {PRESEED_LOCAL}: None
245 14:47:44.214428 - {RAMDISK}: 7462823/tftp-deploy-3ksw9d6m/ramdisk/ramdisk.cpio.gz
246 14:47:44.214521 - {ROOT_PART}: None
247 14:47:44.214615 - {ROOT}: None
248 14:47:44.214708 - {SERVER_IP}: 192.168.201.1
249 14:47:44.214801 - {TEE}: None
250 14:47:44.214894 Parsed boot commands:
251 14:47:44.215016 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
252 14:47:44.215242 Parsed boot commands: tftpboot 192.168.201.1 7462823/tftp-deploy-3ksw9d6m/kernel/bzImage 7462823/tftp-deploy-3ksw9d6m/kernel/cmdline 7462823/tftp-deploy-3ksw9d6m/ramdisk/ramdisk.cpio.gz
253 14:47:44.215383 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
254 14:47:44.215538 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
255 14:47:44.215724 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
256 14:47:44.215857 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
257 14:47:44.215969 Not connected, no need to disconnect.
258 14:47:44.216091 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
259 14:47:44.216222 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
260 14:47:44.216328 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost asus-cx9400-volteer-cbg-0'
261 14:47:44.219673 Setting prompt string to ['lava-test: # ']
262 14:47:44.220055 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
263 14:47:44.220205 end: 2.2.1 reset-connection (duration 00:00:00) [common]
264 14:47:44.220346 start: 2.2.2 reset-device (timeout 00:05:00) [common]
265 14:47:44.220476 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
266 14:47:44.220759 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-0' '--port=1' '--command=reboot'
267 14:47:44.240957 >> Command sent successfully.
268 14:47:44.242983 Returned 0 in 0 seconds
269 14:47:44.343764 end: 2.2.2.1 pdu-reboot (duration 00:00:00) [common]
271 14:47:44.344090 end: 2.2.2 reset-device (duration 00:00:00) [common]
272 14:47:44.344189 start: 2.2.3 depthcharge-start (timeout 00:05:00) [common]
273 14:47:44.344275 Setting prompt string to 'Starting depthcharge on Voema...'
274 14:47:44.344339 Changing prompt to 'Starting depthcharge on Voema...'
275 14:47:44.344407 depthcharge-start: Wait for prompt Starting depthcharge on Voema... (timeout 00:05:00)
276 14:47:44.344675 [Enter `^Ec?' for help]
277 14:47:52.032731
278 14:47:52.032895
279 14:47:52.042473 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 bootblock starting (log level: 8)...
280 14:47:52.049249 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz
281 14:47:52.052531 CPU: ID 806c1, Tigerlake B0, ucode: 00000086
282 14:47:52.055601 CPU: AES supported, TXT NOT supported, VT supported
283 14:47:52.062168 MCH: device id 9a12 (rev 01) is Tigerlake-Y-4-2
284 14:47:52.068863 PCH: device id a087 (rev 20) is Tigerlake-Y Premium SKU
285 14:47:52.072204 IGD: device id 9a40 (rev 01) is Tigerlake Y GT2
286 14:47:52.075608 VBOOT: Loading verstage.
287 14:47:52.082146 FMAP: Found \"FLASH\" version 1.1 at 0x1804000.
288 14:47:52.085390 FMAP: base = 0x0 size = 0x2000000 #areas = 32
289 14:47:52.092017 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
290 14:47:52.098598 CBFS: mcache @0xfef45600 built for 70 files, used 0xfdc of 0x1800 bytes
291 14:47:52.105392 CBFS: Found 'fallback/verstage' @0x165e40 size 0x147ec in mcache @0xfef45984
292 14:47:52.108723
293 14:47:52.108808
294 14:47:52.118445 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 verstage starting (log level: 8)...
295 14:47:52.133033 Probing TPM: . done!
296 14:47:52.136881 TPM ready after 0 ms
297 14:47:52.140091 Connected to device vid:did:rid of 1ae0:0028:00
298 14:47:52.151177 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6
299 14:47:52.158019 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
300 14:47:52.161298 Initialized TPM device CR50 revision 0
301 14:47:52.208142 tlcl_send_startup: Startup return code is 0
302 14:47:52.208247 TPM: setup succeeded
303 14:47:52.222366 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
304 14:47:52.236310 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
305 14:47:52.249126 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
306 14:47:52.259187 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
307 14:47:52.262612 Chrome EC: UHEPI supported
308 14:47:52.266643 Phase 1
309 14:47:52.269239 FMAP: area GBB found @ 1805000 (458752 bytes)
310 14:47:52.278957 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
311 14:47:52.285603 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
312 14:47:52.292856 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
313 14:47:52.298807 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
314 14:47:52.302333 Recovery requested (1009000e)
315 14:47:52.305647 TPM: Extending digest for VBOOT: boot mode into PCR 0
316 14:47:52.317216 tlcl_extend: response is 0
317 14:47:52.324102 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
318 14:47:52.333918 tlcl_extend: response is 0
319 14:47:52.340346 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
320 14:47:52.347116 CBFS: Found 'fallback/romstage' @0x80 size 0x1bf24 in mcache @0xfef45638
321 14:47:52.353775 BS: verstage times (exec / console): total (unknown) / 142 ms
322 14:47:52.353863
323 14:47:52.353931
324 14:47:52.366835 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 romstage starting (log level: 8)...
325 14:47:52.373337 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
326 14:47:52.376605 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
327 14:47:52.380056 gpe0_sts[0]: 00200000 gpe0_en[0]: 00000000
328 14:47:52.386628 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
329 14:47:52.389996 gpe0_sts[2]: 00001000 gpe0_en[2]: 00000000
330 14:47:52.393339 gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000
331 14:47:52.396473 TCO_STS: 0000 0000
332 14:47:52.399786 GEN_PMCON: d0015038 00002200
333 14:47:52.403209 GBLRST_CAUSE: 00000000 00000000
334 14:47:52.406856 HPR_CAUSE0: 00000000
335 14:47:52.406942 prev_sleep_state 5
336 14:47:52.409992 Boot Count incremented to 10854
337 14:47:52.416608 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
338 14:47:52.422994 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
339 14:47:52.432905 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
340 14:47:52.439502 CBFS: Found 'fspm.bin' @0x78fc0 size 0xa5000 in mcache @0xfef4585c
341 14:47:52.442966 Chrome EC: UHEPI supported
342 14:47:52.449439 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
343 14:47:52.460594 Probing TPM: done!
344 14:47:52.467967 Connected to device vid:did:rid of 1ae0:0028:00
345 14:47:52.478213 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6
346 14:47:52.485590 Initialized TPM device CR50 revision 0
347 14:47:52.496078 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
348 14:47:52.502777 MRC: Hash idx 0x100b comparison successful.
349 14:47:52.506077 MRC cache found, size faa8
350 14:47:52.506176 bootmode is set to: 2
351 14:47:52.509358 SPD index = 0
352 14:47:52.516019 CBFS: Found 'spd.bin' @0x72940 size 0x600 in mcache @0xfef4579c
353 14:47:52.519107 SPD: module type is LPDDR4X
354 14:47:52.522599 SPD: module part number is MT53E512M64D4NW-046
355 14:47:52.528910 SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb
356 14:47:52.535580 SPD: device width 16 bits, bus width 16 bits
357 14:47:52.538894 SPD: module size is 1024 MB (per channel)
358 14:47:52.969146 CBMEM:
359 14:47:52.972276 IMD: root @ 0x76fff000 254 entries.
360 14:47:52.975917 IMD: root @ 0x76ffec00 62 entries.
361 14:47:52.979200 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
362 14:47:52.985724 FMAP: area RW_VPD found @ f35000 (8192 bytes)
363 14:47:52.989008 External stage cache:
364 14:47:52.992474 IMD: root @ 0x7b3ff000 254 entries.
365 14:47:52.995730 IMD: root @ 0x7b3fec00 62 entries.
366 14:47:53.011088 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
367 14:47:53.017962 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
368 14:47:53.024123 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
369 14:47:53.038099 MRC: 'RECOVERY_MRC_CACHE' does not need update.
370 14:47:53.044622 cse_lite: Skip switching to RW in the recovery path
371 14:47:53.044711 8 DIMMs found
372 14:47:53.047815 SMM Memory Map
373 14:47:53.051234 SMRAM : 0x7b000000 0x800000
374 14:47:53.054916 Subregion 0: 0x7b000000 0x200000
375 14:47:53.055000 Subregion 1: 0x7b200000 0x200000
376 14:47:53.059240 Subregion 2: 0x7b400000 0x400000
377 14:47:53.062528 top_of_ram = 0x77000000
378 14:47:53.069184 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
379 14:47:53.072374 MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
380 14:47:53.079426 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
381 14:47:53.082809 MTRR Range: Start=ff000000 End=0 (Size 1000000)
382 14:47:53.092009 CBFS: Found 'fallback/postcar' @0x160900 size 0x54f8 in mcache @0xfef4594c
383 14:47:53.098705 Decompressing stage fallback/postcar @ 0x76c0afc0 (38208 bytes)
384 14:47:53.108473 Loading module at 0x76c0b000 with entry 0x76c0b000. filesize: 0x5150 memsize: 0x9500
385 14:47:53.112004 Processing 211 relocs. Offset value of 0x74c0b000
386 14:47:53.121269 BS: romstage times (exec / console): total (unknown) / 277 ms
387 14:47:53.127012
388 14:47:53.127109
389 14:47:53.137138 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 postcar starting (log level: 8)...
390 14:47:53.140238 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
391 14:47:53.150232 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
392 14:47:53.156936 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
393 14:47:53.163369 CBFS: Found 'fallback/ramstage' @0x524c0 size 0x1fbe3 in mcache @0x76c4c0ec
394 14:47:53.169968 Decompressing stage fallback/ramstage @ 0x76b97fc0 (463536 bytes)
395 14:47:53.217182 Loading module at 0x76b98000 with entry 0x76b98000. filesize: 0x4d5d8 memsize: 0x71270
396 14:47:53.223520 Processing 5008 relocs. Offset value of 0x75d98000
397 14:47:53.226767 BS: postcar times (exec / console): total (unknown) / 59 ms
398 14:47:53.230081
399 14:47:53.230166
400 14:47:53.240328 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 ramstage starting (log level: 8)...
401 14:47:53.240414 Normal boot
402 14:47:53.243489 FW_CONFIG value is 0x804c02
403 14:47:53.246787 PCI: 00:07.0 disabled by fw_config
404 14:47:53.250100 PCI: 00:07.1 disabled by fw_config
405 14:47:53.256657 PCI: 00:0d.2 disabled by fw_config
406 14:47:53.260333 PCI: 00:1c.7 disabled by fw_config
407 14:47:53.263482 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
408 14:47:53.269980 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
409 14:47:53.277121 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
410 14:47:53.280076 GENERIC: 0.0 disabled by fw_config
411 14:47:53.283201 GENERIC: 1.0 disabled by fw_config
412 14:47:53.287089 fw_config match found: DB_USB=USB3_ACTIVE
413 14:47:53.289946 fw_config match found: DB_USB=USB3_ACTIVE
414 14:47:53.293213 fw_config match found: DB_USB=USB3_ACTIVE
415 14:47:53.299770 fw_config match found: DB_USB=USB3_ACTIVE
416 14:47:53.303699 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
417 14:47:53.313006 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
418 14:47:53.319540 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
419 14:47:53.326491 CBFS: Found 'cpu_microcode_blob.bin' @0x1c040 size 0x36400 in mcache @0x76c4c09c
420 14:47:53.332947 microcode: sig=0x806c1 pf=0x80 revision=0x86
421 14:47:53.336329 microcode: Update skipped, already up-to-date
422 14:47:53.342785 CBFS: Found 'fsps.bin' @0x11efc0 size 0x418f9 in mcache @0x76c4c30c
423 14:47:53.370958 Detected 4 core, 8 thread CPU.
424 14:47:53.374533 Setting up SMI for CPU
425 14:47:53.377500 IED base = 0x7b400000
426 14:47:53.377585 IED size = 0x00400000
427 14:47:53.380857 Will perform SMM setup.
428 14:47:53.387685 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz.
429 14:47:53.394071 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
430 14:47:53.400520 Processing 16 relocs. Offset value of 0x00030000
431 14:47:53.403874 Attempting to start 7 APs
432 14:47:53.407035 Waiting for 10ms after sending INIT.
433 14:47:53.423085 Waiting for 1st SIPI to complete...AP: slot 1 apic_id 1.
434 14:47:53.423171 done.
435 14:47:53.426093 AP: slot 7 apic_id 3.
436 14:47:53.429497 AP: slot 3 apic_id 2.
437 14:47:53.429583 AP: slot 2 apic_id 6.
438 14:47:53.432733 AP: slot 6 apic_id 7.
439 14:47:53.436095 AP: slot 4 apic_id 5.
440 14:47:53.436179 AP: slot 5 apic_id 4.
441 14:47:53.442645 Waiting for 2nd SIPI to complete...done.
442 14:47:53.449651 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
443 14:47:53.456241 Processing 13 relocs. Offset value of 0x00038000
444 14:47:53.459290 Unable to locate Global NVS
445 14:47:53.465590 SMM Module: stub loaded at 0x00038000. Will call 0x76bb6318(0x00000000)
446 14:47:53.469271 Installing permanent SMM handler to 0x7b000000
447 14:47:53.479310 Loading module at 0x7b010000 with entry 0x7b010c16. filesize: 0xa7c8 memsize: 0xf908
448 14:47:53.482531 Processing 794 relocs. Offset value of 0x7b010000
449 14:47:53.492410 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8
450 14:47:53.495791 Processing 13 relocs. Offset value of 0x7b008000
451 14:47:53.502536 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
452 14:47:53.508689 SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
453 14:47:53.512442 SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
454 14:47:53.519098 SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
455 14:47:53.525689 SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
456 14:47:53.532005 SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
457 14:47:53.538644 SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
458 14:47:53.541880 Unable to locate Global NVS
459 14:47:53.548608 SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c16(0x00000000)
460 14:47:53.551808 Clearing SMI status registers
461 14:47:53.555098 SMI_STS: PM1
462 14:47:53.555181 PM1_STS: PWRBTN
463 14:47:53.562064 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
464 14:47:53.565299 In relocation handler: CPU 0
465 14:47:53.568391 New SMBASE=0x7b000000 IEDBASE=0x7b400000
466 14:47:53.574804 Writing SMRR. base = 0x7b000006, mask=0xff800c00
467 14:47:53.578074 Relocation complete.
468 14:47:53.584862 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
469 14:47:53.588282 In relocation handler: CPU 1
470 14:47:53.591453 New SMBASE=0x7afffc00 IEDBASE=0x7b400000
471 14:47:53.594872 Relocation complete.
472 14:47:53.601646 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
473 14:47:53.604990 In relocation handler: CPU 2
474 14:47:53.607787 New SMBASE=0x7afff800 IEDBASE=0x7b400000
475 14:47:53.611665 Writing SMRR. base = 0x7b000006, mask=0xff800c00
476 14:47:53.614496 Relocation complete.
477 14:47:53.621162 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
478 14:47:53.624420 In relocation handler: CPU 6
479 14:47:53.627689 New SMBASE=0x7affe800 IEDBASE=0x7b400000
480 14:47:53.631130 Relocation complete.
481 14:47:53.638032 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
482 14:47:53.640840 In relocation handler: CPU 3
483 14:47:53.644496 New SMBASE=0x7afff400 IEDBASE=0x7b400000
484 14:47:53.650956 Writing SMRR. base = 0x7b000006, mask=0xff800c00
485 14:47:53.651044 Relocation complete.
486 14:47:53.661393 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
487 14:47:53.664528 In relocation handler: CPU 7
488 14:47:53.667796 New SMBASE=0x7affe400 IEDBASE=0x7b400000
489 14:47:53.667883 Relocation complete.
490 14:47:53.677475 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
491 14:47:53.677562 In relocation handler: CPU 4
492 14:47:53.684196 New SMBASE=0x7afff000 IEDBASE=0x7b400000
493 14:47:53.684283 Relocation complete.
494 14:47:53.694166 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
495 14:47:53.694252 In relocation handler: CPU 5
496 14:47:53.700609 New SMBASE=0x7affec00 IEDBASE=0x7b400000
497 14:47:53.704352 Writing SMRR. base = 0x7b000006, mask=0xff800c00
498 14:47:53.707106 Relocation complete.
499 14:47:53.710273 Initializing CPU #0
500 14:47:53.713627 CPU: vendor Intel device 806c1
501 14:47:53.717094 CPU: family 06, model 8c, stepping 01
502 14:47:53.717180 Clearing out pending MCEs
503 14:47:53.721037 Setting up local APIC...
504 14:47:53.724779 apic_id: 0x00 done.
505 14:47:53.727932 Turbo is available but hidden
506 14:47:53.731282 Turbo is available and visible
507 14:47:53.734421 microcode: Update skipped, already up-to-date
508 14:47:53.737629 CPU #0 initialized
509 14:47:53.737716 Initializing CPU #2
510 14:47:53.741320 Initializing CPU #6
511 14:47:53.744798 CPU: vendor Intel device 806c1
512 14:47:53.747490 CPU: family 06, model 8c, stepping 01
513 14:47:53.751272 CPU: vendor Intel device 806c1
514 14:47:53.754433 CPU: family 06, model 8c, stepping 01
515 14:47:53.757779 Clearing out pending MCEs
516 14:47:53.757864 Initializing CPU #1
517 14:47:53.761078 Initializing CPU #3
518 14:47:53.764364 Initializing CPU #7
519 14:47:53.767650 CPU: vendor Intel device 806c1
520 14:47:53.770841 CPU: family 06, model 8c, stepping 01
521 14:47:53.770927 Initializing CPU #5
522 14:47:53.774200 Initializing CPU #4
523 14:47:53.777388 CPU: vendor Intel device 806c1
524 14:47:53.780743 CPU: family 06, model 8c, stepping 01
525 14:47:53.784339 CPU: vendor Intel device 806c1
526 14:47:53.786993 CPU: family 06, model 8c, stepping 01
527 14:47:53.790698 Clearing out pending MCEs
528 14:47:53.793701 Clearing out pending MCEs
529 14:47:53.797164 Setting up local APIC...
530 14:47:53.800458 CPU: vendor Intel device 806c1
531 14:47:53.803551 CPU: family 06, model 8c, stepping 01
532 14:47:53.803638 Setting up local APIC...
533 14:47:53.807166 apic_id: 0x04 done.
534 14:47:53.810074 Setting up local APIC...
535 14:47:53.813365 Clearing out pending MCEs
536 14:47:53.817350 CPU: vendor Intel device 806c1
537 14:47:53.820064 CPU: family 06, model 8c, stepping 01
538 14:47:53.823487 Setting up local APIC...
539 14:47:53.823572 apic_id: 0x06 done.
540 14:47:53.827028 Clearing out pending MCEs
541 14:47:53.829738 microcode: Update skipped, already up-to-date
542 14:47:53.836648 microcode: Update skipped, already up-to-date
543 14:47:53.836733 apic_id: 0x05 done.
544 14:47:53.839954 CPU #5 initialized
545 14:47:53.846468 microcode: Update skipped, already up-to-date
546 14:47:53.846553 Clearing out pending MCEs
547 14:47:53.849806 apic_id: 0x02 done.
548 14:47:53.853078 Setting up local APIC...
549 14:47:53.856357 microcode: Update skipped, already up-to-date
550 14:47:53.859668 apic_id: 0x03 done.
551 14:47:53.859752 CPU #4 initialized
552 14:47:53.862935 CPU #2 initialized
553 14:47:53.866093 Setting up local APIC...
554 14:47:53.869850 Clearing out pending MCEs
555 14:47:53.869935 CPU #3 initialized
556 14:47:53.872951 microcode: Update skipped, already up-to-date
557 14:47:53.876265 Setting up local APIC...
558 14:47:53.879538 CPU #7 initialized
559 14:47:53.882635 apic_id: 0x01 done.
560 14:47:53.882719 apic_id: 0x07 done.
561 14:47:53.889022 microcode: Update skipped, already up-to-date
562 14:47:53.892635 microcode: Update skipped, already up-to-date
563 14:47:53.895920 CPU #1 initialized
564 14:47:53.896005 CPU #6 initialized
565 14:47:53.899034 bsp_do_flight_plan done after 454 msecs.
566 14:47:53.902562 CPU: frequency set to 4000 MHz
567 14:47:53.905702 Enabling SMIs.
568 14:47:53.912086 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 347 / 317 ms
569 14:47:53.927571 SATAXPCIE1 indicates PCIe NVMe is present
570 14:47:53.931448 Probing TPM: done!
571 14:47:53.934584 Connected to device vid:did:rid of 1ae0:0028:00
572 14:47:53.944757 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6
573 14:47:53.948103 Initialized TPM device CR50 revision 0
574 14:47:53.951387 Enabling S0i3.4
575 14:47:53.958351 CBFS: Found 'vbt.bin' @0x78a40 size 0x4f0 in mcache @0x76c4c1fc
576 14:47:53.961079 Found a VBT of 8704 bytes after decompression
577 14:47:53.968042 cse_lite: CSE RO boot. HybridStorageMode disabled
578 14:47:53.974773 WEAK: src/soc/intel/tigerlake/fsp_params.c/mainboard_silicon_init_params called
579 14:47:54.050417 FSPS returned 0
580 14:47:54.053514 Executing Phase 1 of FspMultiPhaseSiInit
581 14:47:54.063303 FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
582 14:47:54.066611 port C0 DISC req: usage 1 usb3 1 usb2 5
583 14:47:54.069712 Raw Buffer output 0 00000511
584 14:47:54.073019 Raw Buffer output 1 00000000
585 14:47:54.076870 pmc_send_ipc_cmd succeeded
586 14:47:54.083282 port C1 DISC req: usage 1 usb3 2 usb2 3
587 14:47:54.083360 Raw Buffer output 0 00000321
588 14:47:54.086994 Raw Buffer output 1 00000000
589 14:47:54.090795 pmc_send_ipc_cmd succeeded
590 14:47:54.096218 Detected 4 core, 8 thread CPU.
591 14:47:54.099180 Detected 4 core, 8 thread CPU.
592 14:47:54.333377 Display FSP Version Info HOB
593 14:47:54.337118 Reference Code - CPU = a.0.4c.31
594 14:47:54.339921 uCode Version = 0.0.0.86
595 14:47:54.343454 TXT ACM version = ff.ff.ff.ffff
596 14:47:54.346891 Reference Code - ME = a.0.4c.31
597 14:47:54.350104 MEBx version = 0.0.0.0
598 14:47:54.353373 ME Firmware Version = Consumer SKU
599 14:47:54.356826 Reference Code - PCH = a.0.4c.31
600 14:47:54.360035 PCH-CRID Status = Disabled
601 14:47:54.363173 PCH-CRID Original Value = ff.ff.ff.ffff
602 14:47:54.366444 PCH-CRID New Value = ff.ff.ff.ffff
603 14:47:54.370038 OPROM - RST - RAID = ff.ff.ff.ffff
604 14:47:54.373341 PCH Hsio Version = 4.0.0.0
605 14:47:54.376559 Reference Code - SA - System Agent = a.0.4c.31
606 14:47:54.379790 Reference Code - MRC = 2.0.0.1
607 14:47:54.382979 SA - PCIe Version = a.0.4c.31
608 14:47:54.386289 SA-CRID Status = Disabled
609 14:47:54.389463 SA-CRID Original Value = 0.0.0.1
610 14:47:54.393143 SA-CRID New Value = 0.0.0.1
611 14:47:54.396334 OPROM - VBIOS = ff.ff.ff.ffff
612 14:47:54.399601 IO Manageability Engine FW Version = 11.1.4.0
613 14:47:54.402897 PHY Build Version = 0.0.0.e0
614 14:47:54.406624 Thunderbolt(TM) FW Version = 0.0.0.0
615 14:47:54.412990 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
616 14:47:54.416291 ITSS IRQ Polarities Before:
617 14:47:54.416376 IPC0: 0xffffffff
618 14:47:54.419294 IPC1: 0xffffffff
619 14:47:54.419379 IPC2: 0xffffffff
620 14:47:54.422752 IPC3: 0xffffffff
621 14:47:54.426110 ITSS IRQ Polarities After:
622 14:47:54.426217 IPC0: 0xffffffff
623 14:47:54.429300 IPC1: 0xffffffff
624 14:47:54.429384 IPC2: 0xffffffff
625 14:47:54.432900 IPC3: 0xffffffff
626 14:47:54.436214 Found PCIe Root Port #9 at PCI: 00:1d.0.
627 14:47:54.448957 pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
628 14:47:54.458877 pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing.
629 14:47:54.472456 pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
630 14:47:54.479152 BS: BS_DEV_INIT_CHIPS run times (exec / console): 325 / 236 ms
631 14:47:54.482202 Enumerating buses...
632 14:47:54.485405 Show all devs... Before device enumeration.
633 14:47:54.489284 Root Device: enabled 1
634 14:47:54.489368 DOMAIN: 0000: enabled 1
635 14:47:54.492411 CPU_CLUSTER: 0: enabled 1
636 14:47:54.495490 PCI: 00:00.0: enabled 1
637 14:47:54.498649 PCI: 00:02.0: enabled 1
638 14:47:54.502009 PCI: 00:04.0: enabled 1
639 14:47:54.502092 PCI: 00:05.0: enabled 1
640 14:47:54.505508 PCI: 00:06.0: enabled 0
641 14:47:54.508700 PCI: 00:07.0: enabled 0
642 14:47:54.508784 PCI: 00:07.1: enabled 0
643 14:47:54.512310 PCI: 00:07.2: enabled 0
644 14:47:54.515341 PCI: 00:07.3: enabled 0
645 14:47:54.518652 PCI: 00:08.0: enabled 1
646 14:47:54.518734 PCI: 00:09.0: enabled 0
647 14:47:54.522427 PCI: 00:0a.0: enabled 0
648 14:47:54.525475 PCI: 00:0d.0: enabled 1
649 14:47:54.528835 PCI: 00:0d.1: enabled 0
650 14:47:54.528918 PCI: 00:0d.2: enabled 0
651 14:47:54.532069 PCI: 00:0d.3: enabled 0
652 14:47:54.535273 PCI: 00:0e.0: enabled 0
653 14:47:54.538523 PCI: 00:10.2: enabled 1
654 14:47:54.538619 PCI: 00:10.6: enabled 0
655 14:47:54.541881 PCI: 00:10.7: enabled 0
656 14:47:54.545274 PCI: 00:12.0: enabled 0
657 14:47:54.548529 PCI: 00:12.6: enabled 0
658 14:47:54.548618 PCI: 00:13.0: enabled 0
659 14:47:54.551579 PCI: 00:14.0: enabled 1
660 14:47:54.554795 PCI: 00:14.1: enabled 0
661 14:47:54.558123 PCI: 00:14.2: enabled 1
662 14:47:54.558240 PCI: 00:14.3: enabled 1
663 14:47:54.561321 PCI: 00:15.0: enabled 1
664 14:47:54.564647 PCI: 00:15.1: enabled 1
665 14:47:54.564770 PCI: 00:15.2: enabled 1
666 14:47:54.567981 PCI: 00:15.3: enabled 1
667 14:47:54.571633 PCI: 00:16.0: enabled 1
668 14:47:54.574530 PCI: 00:16.1: enabled 0
669 14:47:54.574646 PCI: 00:16.2: enabled 0
670 14:47:54.578300 PCI: 00:16.3: enabled 0
671 14:47:54.581190 PCI: 00:16.4: enabled 0
672 14:47:54.584525 PCI: 00:16.5: enabled 0
673 14:47:54.584645 PCI: 00:17.0: enabled 1
674 14:47:54.587985 PCI: 00:19.0: enabled 0
675 14:47:54.591285 PCI: 00:19.1: enabled 1
676 14:47:54.594528 PCI: 00:19.2: enabled 0
677 14:47:54.594645 PCI: 00:1c.0: enabled 1
678 14:47:54.597677 PCI: 00:1c.1: enabled 0
679 14:47:54.601593 PCI: 00:1c.2: enabled 0
680 14:47:54.604710 PCI: 00:1c.3: enabled 0
681 14:47:54.604836 PCI: 00:1c.4: enabled 0
682 14:47:54.608182 PCI: 00:1c.5: enabled 0
683 14:47:54.611373 PCI: 00:1c.6: enabled 1
684 14:47:54.611495 PCI: 00:1c.7: enabled 0
685 14:47:54.614672 PCI: 00:1d.0: enabled 1
686 14:47:54.617685 PCI: 00:1d.1: enabled 0
687 14:47:54.621117 PCI: 00:1d.2: enabled 1
688 14:47:54.621201 PCI: 00:1d.3: enabled 0
689 14:47:54.624586 PCI: 00:1e.0: enabled 1
690 14:47:54.627661 PCI: 00:1e.1: enabled 0
691 14:47:54.631085 PCI: 00:1e.2: enabled 1
692 14:47:54.631172 PCI: 00:1e.3: enabled 1
693 14:47:54.634111 PCI: 00:1f.0: enabled 1
694 14:47:54.637459 PCI: 00:1f.1: enabled 0
695 14:47:54.641093 PCI: 00:1f.2: enabled 1
696 14:47:54.641179 PCI: 00:1f.3: enabled 1
697 14:47:54.644362 PCI: 00:1f.4: enabled 0
698 14:47:54.647679 PCI: 00:1f.5: enabled 1
699 14:47:54.651145 PCI: 00:1f.6: enabled 0
700 14:47:54.651299 PCI: 00:1f.7: enabled 0
701 14:47:54.654269 APIC: 00: enabled 1
702 14:47:54.657665 GENERIC: 0.0: enabled 1
703 14:47:54.657781 GENERIC: 0.0: enabled 1
704 14:47:54.660872 GENERIC: 1.0: enabled 1
705 14:47:54.664053 GENERIC: 0.0: enabled 1
706 14:47:54.667301 GENERIC: 1.0: enabled 1
707 14:47:54.667385 USB0 port 0: enabled 1
708 14:47:54.670568 GENERIC: 0.0: enabled 1
709 14:47:54.673857 USB0 port 0: enabled 1
710 14:47:54.677561 GENERIC: 0.0: enabled 1
711 14:47:54.677646 I2C: 00:1a: enabled 1
712 14:47:54.680554 I2C: 00:31: enabled 1
713 14:47:54.683732 I2C: 00:32: enabled 1
714 14:47:54.683818 I2C: 00:10: enabled 1
715 14:47:54.687565 I2C: 00:15: enabled 1
716 14:47:54.690506 GENERIC: 0.0: enabled 0
717 14:47:54.690592 GENERIC: 1.0: enabled 0
718 14:47:54.694023 GENERIC: 0.0: enabled 1
719 14:47:54.697039 SPI: 00: enabled 1
720 14:47:54.697124 SPI: 00: enabled 1
721 14:47:54.700389 PNP: 0c09.0: enabled 1
722 14:47:54.703592 GENERIC: 0.0: enabled 1
723 14:47:54.703678 USB3 port 0: enabled 1
724 14:47:54.707315 USB3 port 1: enabled 1
725 14:47:54.710413 USB3 port 2: enabled 0
726 14:47:54.713743 USB3 port 3: enabled 0
727 14:47:54.713842 USB2 port 0: enabled 0
728 14:47:54.716917 USB2 port 1: enabled 1
729 14:47:54.720561 USB2 port 2: enabled 1
730 14:47:54.720648 USB2 port 3: enabled 0
731 14:47:54.723836 USB2 port 4: enabled 1
732 14:47:54.727189 USB2 port 5: enabled 0
733 14:47:54.730390 USB2 port 6: enabled 0
734 14:47:54.730480 USB2 port 7: enabled 0
735 14:47:54.733453 USB2 port 8: enabled 0
736 14:47:54.736768 USB2 port 9: enabled 0
737 14:47:54.736855 USB3 port 0: enabled 0
738 14:47:54.740053 USB3 port 1: enabled 1
739 14:47:54.743445 USB3 port 2: enabled 0
740 14:47:54.746527 USB3 port 3: enabled 0
741 14:47:54.746613 GENERIC: 0.0: enabled 1
742 14:47:54.749961 GENERIC: 1.0: enabled 1
743 14:47:54.753280 APIC: 01: enabled 1
744 14:47:54.753371 APIC: 06: enabled 1
745 14:47:54.756719 APIC: 02: enabled 1
746 14:47:54.756804 APIC: 05: enabled 1
747 14:47:54.760286 APIC: 04: enabled 1
748 14:47:54.763400 APIC: 07: enabled 1
749 14:47:54.763485 APIC: 03: enabled 1
750 14:47:54.766288 Compare with tree...
751 14:47:54.769567 Root Device: enabled 1
752 14:47:54.773165 DOMAIN: 0000: enabled 1
753 14:47:54.773255 PCI: 00:00.0: enabled 1
754 14:47:54.776487 PCI: 00:02.0: enabled 1
755 14:47:54.779638 PCI: 00:04.0: enabled 1
756 14:47:54.782962 GENERIC: 0.0: enabled 1
757 14:47:54.786283 PCI: 00:05.0: enabled 1
758 14:47:54.786369 PCI: 00:06.0: enabled 0
759 14:47:54.789459 PCI: 00:07.0: enabled 0
760 14:47:54.793153 GENERIC: 0.0: enabled 1
761 14:47:54.796405 PCI: 00:07.1: enabled 0
762 14:47:54.799528 GENERIC: 1.0: enabled 1
763 14:47:54.799615 PCI: 00:07.2: enabled 0
764 14:47:54.802793 GENERIC: 0.0: enabled 1
765 14:47:54.806176 PCI: 00:07.3: enabled 0
766 14:47:54.809472 GENERIC: 1.0: enabled 1
767 14:47:54.812422 PCI: 00:08.0: enabled 1
768 14:47:54.812508 PCI: 00:09.0: enabled 0
769 14:47:54.815706 PCI: 00:0a.0: enabled 0
770 14:47:54.819296 PCI: 00:0d.0: enabled 1
771 14:47:54.822393 USB0 port 0: enabled 1
772 14:47:54.825715 USB3 port 0: enabled 1
773 14:47:54.825813 USB3 port 1: enabled 1
774 14:47:54.829193 USB3 port 2: enabled 0
775 14:47:54.832406 USB3 port 3: enabled 0
776 14:47:54.835580 PCI: 00:0d.1: enabled 0
777 14:47:54.838881 PCI: 00:0d.2: enabled 0
778 14:47:54.842701 GENERIC: 0.0: enabled 1
779 14:47:54.842787 PCI: 00:0d.3: enabled 0
780 14:47:54.845943 PCI: 00:0e.0: enabled 0
781 14:47:54.849243 PCI: 00:10.2: enabled 1
782 14:47:54.852552 PCI: 00:10.6: enabled 0
783 14:47:54.855695 PCI: 00:10.7: enabled 0
784 14:47:54.855776 PCI: 00:12.0: enabled 0
785 14:47:54.859120 PCI: 00:12.6: enabled 0
786 14:47:54.862212 PCI: 00:13.0: enabled 0
787 14:47:54.865492 PCI: 00:14.0: enabled 1
788 14:47:54.868883 USB0 port 0: enabled 1
789 14:47:54.868961 USB2 port 0: enabled 0
790 14:47:54.872016 USB2 port 1: enabled 1
791 14:47:54.875822 USB2 port 2: enabled 1
792 14:47:54.878629 USB2 port 3: enabled 0
793 14:47:54.882417 USB2 port 4: enabled 1
794 14:47:54.885664 USB2 port 5: enabled 0
795 14:47:54.885749 USB2 port 6: enabled 0
796 14:47:54.888491 USB2 port 7: enabled 0
797 14:47:54.892228 USB2 port 8: enabled 0
798 14:47:54.895476 USB2 port 9: enabled 0
799 14:47:54.898474 USB3 port 0: enabled 0
800 14:47:54.901808 USB3 port 1: enabled 1
801 14:47:54.901907 USB3 port 2: enabled 0
802 14:47:54.905511 USB3 port 3: enabled 0
803 14:47:54.908804 PCI: 00:14.1: enabled 0
804 14:47:54.911632 PCI: 00:14.2: enabled 1
805 14:47:54.915455 PCI: 00:14.3: enabled 1
806 14:47:54.915535 GENERIC: 0.0: enabled 1
807 14:47:54.918605 PCI: 00:15.0: enabled 1
808 14:47:54.921723 I2C: 00:1a: enabled 1
809 14:47:54.924728 I2C: 00:31: enabled 1
810 14:47:54.924821 I2C: 00:32: enabled 1
811 14:47:54.928132 PCI: 00:15.1: enabled 1
812 14:47:54.931534 I2C: 00:10: enabled 1
813 14:47:54.934596 PCI: 00:15.2: enabled 1
814 14:47:54.938225 PCI: 00:15.3: enabled 1
815 14:47:54.938315 PCI: 00:16.0: enabled 1
816 14:47:54.941525 PCI: 00:16.1: enabled 0
817 14:47:54.944762 PCI: 00:16.2: enabled 0
818 14:47:54.948050 PCI: 00:16.3: enabled 0
819 14:47:54.951309 PCI: 00:16.4: enabled 0
820 14:47:54.951388 PCI: 00:16.5: enabled 0
821 14:47:54.954545 PCI: 00:17.0: enabled 1
822 14:47:54.958014 PCI: 00:19.0: enabled 0
823 14:47:54.961839 PCI: 00:19.1: enabled 1
824 14:47:54.961924 I2C: 00:15: enabled 1
825 14:47:54.965055 PCI: 00:19.2: enabled 0
826 14:47:54.968419 PCI: 00:1d.0: enabled 1
827 14:47:54.971690 GENERIC: 0.0: enabled 1
828 14:47:54.975164 PCI: 00:1e.0: enabled 1
829 14:47:54.975253 PCI: 00:1e.1: enabled 0
830 14:47:55.024965 PCI: 00:1e.2: enabled 1
831 14:47:55.025111 SPI: 00: enabled 1
832 14:47:55.025459 PCI: 00:1e.3: enabled 1
833 14:47:55.025532 SPI: 00: enabled 1
834 14:47:55.025595 PCI: 00:1f.0: enabled 1
835 14:47:55.026002 PNP: 0c09.0: enabled 1
836 14:47:55.026088 PCI: 00:1f.1: enabled 0
837 14:47:55.026520 PCI: 00:1f.2: enabled 1
838 14:47:55.026605 GENERIC: 0.0: enabled 1
839 14:47:55.027017 GENERIC: 0.0: enabled 1
840 14:47:55.027106 GENERIC: 1.0: enabled 1
841 14:47:55.027175 PCI: 00:1f.3: enabled 1
842 14:47:55.027863 PCI: 00:1f.4: enabled 0
843 14:47:55.027952 PCI: 00:1f.5: enabled 1
844 14:47:55.028209 PCI: 00:1f.6: enabled 0
845 14:47:55.028279 PCI: 00:1f.7: enabled 0
846 14:47:55.028341 CPU_CLUSTER: 0: enabled 1
847 14:47:55.028406 APIC: 00: enabled 1
848 14:47:55.028466 APIC: 01: enabled 1
849 14:47:55.077108 APIC: 06: enabled 1
850 14:47:55.077243 APIC: 02: enabled 1
851 14:47:55.077315 APIC: 05: enabled 1
852 14:47:55.077607 APIC: 04: enabled 1
853 14:47:55.077678 APIC: 07: enabled 1
854 14:47:55.077748 APIC: 03: enabled 1
855 14:47:55.078276 Root Device scanning...
856 14:47:55.078360 scan_static_bus for Root Device
857 14:47:55.078628 DOMAIN: 0000 enabled
858 14:47:55.078721 CPU_CLUSTER: 0 enabled
859 14:47:55.078793 DOMAIN: 0000 scanning...
860 14:47:55.078860 PCI: pci_scan_bus for bus 00
861 14:47:55.078922 PCI: 00:00.0 [8086/0000] ops
862 14:47:55.078987 PCI: 00:00.0 [8086/9a12] enabled
863 14:47:55.079051 PCI: 00:02.0 [8086/0000] bus ops
864 14:47:55.079110 PCI: 00:02.0 [8086/9a40] enabled
865 14:47:55.079356 PCI: 00:04.0 [8086/0000] bus ops
866 14:47:55.079420 PCI: 00:04.0 [8086/9a03] enabled
867 14:47:55.127158 PCI: 00:05.0 [8086/9a19] enabled
868 14:47:55.127319 PCI: 00:07.0 [0000/0000] hidden
869 14:47:55.127594 PCI: 00:08.0 [8086/9a11] enabled
870 14:47:55.127665 PCI: 00:0a.0 [8086/9a0d] disabled
871 14:47:55.127922 PCI: 00:0d.0 [8086/0000] bus ops
872 14:47:55.127995 PCI: 00:0d.0 [8086/9a13] enabled
873 14:47:55.128061 PCI: 00:14.0 [8086/0000] bus ops
874 14:47:55.128123 PCI: 00:14.0 [8086/a0ed] enabled
875 14:47:55.128182 PCI: 00:14.2 [8086/a0ef] enabled
876 14:47:55.128240 PCI: 00:14.3 [8086/0000] bus ops
877 14:47:55.128488 PCI: 00:14.3 [8086/a0f0] enabled
878 14:47:55.128555 PCI: 00:15.0 [8086/0000] bus ops
879 14:47:55.128800 PCI: 00:15.0 [8086/a0e8] enabled
880 14:47:55.129061 PCI: 00:15.1 [8086/0000] bus ops
881 14:47:55.129132 PCI: 00:15.1 [8086/a0e9] enabled
882 14:47:55.177274 PCI: 00:15.2 [8086/0000] bus ops
883 14:47:55.177417 PCI: 00:15.2 [8086/a0ea] enabled
884 14:47:55.178017 PCI: 00:15.3 [8086/0000] bus ops
885 14:47:55.178092 PCI: 00:15.3 [8086/a0eb] enabled
886 14:47:55.178344 PCI: 00:16.0 [8086/0000] ops
887 14:47:55.178414 PCI: 00:16.0 [8086/a0e0] enabled
888 14:47:55.178479 PCI: Static device PCI: 00:17.0 not found, disabling it.
889 14:47:55.178949 PCI: 00:19.0 [8086/0000] bus ops
890 14:47:55.179018 PCI: 00:19.0 [8086/a0c5] disabled
891 14:47:55.179266 PCI: 00:19.1 [8086/0000] bus ops
892 14:47:55.179334 PCI: 00:19.1 [8086/a0c6] enabled
893 14:47:55.179579 PCI: 00:1d.0 [8086/0000] bus ops
894 14:47:55.179649 PCI: 00:1d.0 [8086/a0b0] enabled
895 14:47:55.180512 PCI: 00:1e.0 [8086/0000] ops
896 14:47:55.180578 PCI: 00:1e.0 [8086/a0a8] enabled
897 14:47:55.187360 PCI: 00:1e.2 [8086/0000] bus ops
898 14:47:55.187451 PCI: 00:1e.2 [8086/a0aa] enabled
899 14:47:55.190662 PCI: 00:1e.3 [8086/0000] bus ops
900 14:47:55.190734 PCI: 00:1e.3 [8086/a0ab] enabled
901 14:47:55.193961 PCI: 00:1f.0 [8086/0000] bus ops
902 14:47:55.196761 PCI: 00:1f.0 [8086/a087] enabled
903 14:47:55.200450 RTC Init
904 14:47:55.203580 Set power on after power failure.
905 14:47:55.203653 Disabling Deep S3
906 14:47:55.206906 Disabling Deep S3
907 14:47:55.209943 Disabling Deep S4
908 14:47:55.210018 Disabling Deep S4
909 14:47:55.213712 Disabling Deep S5
910 14:47:55.213788 Disabling Deep S5
911 14:47:55.216590 PCI: 00:1f.2 [0000/0000] hidden
912 14:47:55.220148 PCI: 00:1f.3 [8086/0000] bus ops
913 14:47:55.223564 PCI: 00:1f.3 [8086/a0c8] enabled
914 14:47:55.226625 PCI: 00:1f.5 [8086/0000] bus ops
915 14:47:55.229700 PCI: 00:1f.5 [8086/a0a4] enabled
916 14:47:55.233188 PCI: Leftover static devices:
917 14:47:55.236369 PCI: 00:10.2
918 14:47:55.236444 PCI: 00:10.6
919 14:47:55.236519 PCI: 00:10.7
920 14:47:55.239642 PCI: 00:06.0
921 14:47:55.239734 PCI: 00:07.1
922 14:47:55.242916 PCI: 00:07.2
923 14:47:55.242993 PCI: 00:07.3
924 14:47:55.246744 PCI: 00:09.0
925 14:47:55.246819 PCI: 00:0d.1
926 14:47:55.246882 PCI: 00:0d.2
927 14:47:55.249866 PCI: 00:0d.3
928 14:47:55.249961 PCI: 00:0e.0
929 14:47:55.252722 PCI: 00:12.0
930 14:47:55.252795 PCI: 00:12.6
931 14:47:55.252858 PCI: 00:13.0
932 14:47:55.255972 PCI: 00:14.1
933 14:47:55.256044 PCI: 00:16.1
934 14:47:55.259903 PCI: 00:16.2
935 14:47:55.259979 PCI: 00:16.3
936 14:47:55.262612 PCI: 00:16.4
937 14:47:55.262702 PCI: 00:16.5
938 14:47:55.262768 PCI: 00:17.0
939 14:47:55.265947 PCI: 00:19.2
940 14:47:55.266057 PCI: 00:1e.1
941 14:47:55.269314 PCI: 00:1f.1
942 14:47:55.269450 PCI: 00:1f.4
943 14:47:55.269529 PCI: 00:1f.6
944 14:47:55.272537 PCI: 00:1f.7
945 14:47:55.275963 PCI: Check your devicetree.cb.
946 14:47:55.279585 PCI: 00:02.0 scanning...
947 14:47:55.282405 scan_generic_bus for PCI: 00:02.0
948 14:47:55.285985 scan_generic_bus for PCI: 00:02.0 done
949 14:47:55.289171 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
950 14:47:55.292233 PCI: 00:04.0 scanning...
951 14:47:55.295633 scan_generic_bus for PCI: 00:04.0
952 14:47:55.298891 GENERIC: 0.0 enabled
953 14:47:55.306021 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
954 14:47:55.309200 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
955 14:47:55.312288 PCI: 00:0d.0 scanning...
956 14:47:55.315558 scan_static_bus for PCI: 00:0d.0
957 14:47:55.318807 USB0 port 0 enabled
958 14:47:55.318904 USB0 port 0 scanning...
959 14:47:55.322059 scan_static_bus for USB0 port 0
960 14:47:55.325680 USB3 port 0 enabled
961 14:47:55.328592 USB3 port 1 enabled
962 14:47:55.328677 USB3 port 2 disabled
963 14:47:55.332075 USB3 port 3 disabled
964 14:47:55.335425 USB3 port 0 scanning...
965 14:47:55.338757 scan_static_bus for USB3 port 0
966 14:47:55.342226 scan_static_bus for USB3 port 0 done
967 14:47:55.345456 scan_bus: bus USB3 port 0 finished in 6 msecs
968 14:47:55.348551 USB3 port 1 scanning...
969 14:47:55.351979 scan_static_bus for USB3 port 1
970 14:47:55.355360 scan_static_bus for USB3 port 1 done
971 14:47:55.361971 scan_bus: bus USB3 port 1 finished in 6 msecs
972 14:47:55.365267 scan_static_bus for USB0 port 0 done
973 14:47:55.368453 scan_bus: bus USB0 port 0 finished in 43 msecs
974 14:47:55.371788 scan_static_bus for PCI: 00:0d.0 done
975 14:47:55.378670 scan_bus: bus PCI: 00:0d.0 finished in 60 msecs
976 14:47:55.378757 PCI: 00:14.0 scanning...
977 14:47:55.381635 scan_static_bus for PCI: 00:14.0
978 14:47:55.384866 USB0 port 0 enabled
979 14:47:55.388047 USB0 port 0 scanning...
980 14:47:55.391930 scan_static_bus for USB0 port 0
981 14:47:55.395082 USB2 port 0 disabled
982 14:47:55.395169 USB2 port 1 enabled
983 14:47:55.397993 USB2 port 2 enabled
984 14:47:55.398071 USB2 port 3 disabled
985 14:47:55.401234 USB2 port 4 enabled
986 14:47:55.404870 USB2 port 5 disabled
987 14:47:55.404954 USB2 port 6 disabled
988 14:47:55.407854 USB2 port 7 disabled
989 14:47:55.411587 USB2 port 8 disabled
990 14:47:55.411674 USB2 port 9 disabled
991 14:47:55.414853 USB3 port 0 disabled
992 14:47:55.417880 USB3 port 1 enabled
993 14:47:55.417960 USB3 port 2 disabled
994 14:47:55.420973 USB3 port 3 disabled
995 14:47:55.424394 USB2 port 1 scanning...
996 14:47:55.428104 scan_static_bus for USB2 port 1
997 14:47:55.431046 scan_static_bus for USB2 port 1 done
998 14:47:55.434309 scan_bus: bus USB2 port 1 finished in 6 msecs
999 14:47:55.437641 USB2 port 2 scanning...
1000 14:47:55.440969 scan_static_bus for USB2 port 2
1001 14:47:55.444201 scan_static_bus for USB2 port 2 done
1002 14:47:55.450828 scan_bus: bus USB2 port 2 finished in 6 msecs
1003 14:47:55.450914 USB2 port 4 scanning...
1004 14:47:55.454186 scan_static_bus for USB2 port 4
1005 14:47:55.457856 scan_static_bus for USB2 port 4 done
1006 14:47:55.464431 scan_bus: bus USB2 port 4 finished in 6 msecs
1007 14:47:55.467840 USB3 port 1 scanning...
1008 14:47:55.470954 scan_static_bus for USB3 port 1
1009 14:47:55.474226 scan_static_bus for USB3 port 1 done
1010 14:47:55.477666 scan_bus: bus USB3 port 1 finished in 6 msecs
1011 14:47:55.480935 scan_static_bus for USB0 port 0 done
1012 14:47:55.487066 scan_bus: bus USB0 port 0 finished in 93 msecs
1013 14:47:55.490596 scan_static_bus for PCI: 00:14.0 done
1014 14:47:55.493635 scan_bus: bus PCI: 00:14.0 finished in 110 msecs
1015 14:47:55.497490 PCI: 00:14.3 scanning...
1016 14:47:55.500452 scan_static_bus for PCI: 00:14.3
1017 14:47:55.503701 GENERIC: 0.0 enabled
1018 14:47:55.506879 scan_static_bus for PCI: 00:14.3 done
1019 14:47:55.510189 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
1020 14:47:55.513847 PCI: 00:15.0 scanning...
1021 14:47:55.517316 scan_static_bus for PCI: 00:15.0
1022 14:47:55.520269 I2C: 00:1a enabled
1023 14:47:55.520354 I2C: 00:31 enabled
1024 14:47:55.523211 I2C: 00:32 enabled
1025 14:47:55.526567 scan_static_bus for PCI: 00:15.0 done
1026 14:47:55.533425 scan_bus: bus PCI: 00:15.0 finished in 13 msecs
1027 14:47:55.533509 PCI: 00:15.1 scanning...
1028 14:47:55.536652 scan_static_bus for PCI: 00:15.1
1029 14:47:55.540860 I2C: 00:10 enabled
1030 14:47:55.544339 scan_static_bus for PCI: 00:15.1 done
1031 14:47:55.547397 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
1032 14:47:55.551061 PCI: 00:15.2 scanning...
1033 14:47:55.554534 scan_static_bus for PCI: 00:15.2
1034 14:47:55.557712 scan_static_bus for PCI: 00:15.2 done
1035 14:47:55.564238 scan_bus: bus PCI: 00:15.2 finished in 7 msecs
1036 14:47:55.567083 PCI: 00:15.3 scanning...
1037 14:47:55.570970 scan_static_bus for PCI: 00:15.3
1038 14:47:55.574140 scan_static_bus for PCI: 00:15.3 done
1039 14:47:55.577498 scan_bus: bus PCI: 00:15.3 finished in 7 msecs
1040 14:47:55.580730 PCI: 00:19.1 scanning...
1041 14:47:55.583952 scan_static_bus for PCI: 00:19.1
1042 14:47:55.587289 I2C: 00:15 enabled
1043 14:47:55.590624 scan_static_bus for PCI: 00:19.1 done
1044 14:47:55.593732 scan_bus: bus PCI: 00:19.1 finished in 9 msecs
1045 14:47:55.597108 PCI: 00:1d.0 scanning...
1046 14:47:55.600445 do_pci_scan_bridge for PCI: 00:1d.0
1047 14:47:55.603666 PCI: pci_scan_bus for bus 01
1048 14:47:55.606912 PCI: 01:00.0 [1c5c/174a] enabled
1049 14:47:55.610580 GENERIC: 0.0 enabled
1050 14:47:55.613634 Enabling Common Clock Configuration
1051 14:47:55.616520 L1 Sub-State supported from root port 29
1052 14:47:55.620197 L1 Sub-State Support = 0xf
1053 14:47:55.623423 CommonModeRestoreTime = 0x28
1054 14:47:55.626810 Power On Value = 0x16, Power On Scale = 0x0
1055 14:47:55.629896 ASPM: Enabled L1
1056 14:47:55.633081 PCIe: Max_Payload_Size adjusted to 128
1057 14:47:55.636347 scan_bus: bus PCI: 00:1d.0 finished in 35 msecs
1058 14:47:55.639682 PCI: 00:1e.2 scanning...
1059 14:47:55.643118 scan_generic_bus for PCI: 00:1e.2
1060 14:47:55.646417 SPI: 00 enabled
1061 14:47:55.653124 bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done
1062 14:47:55.656430 scan_bus: bus PCI: 00:1e.2 finished in 11 msecs
1063 14:47:55.659990 PCI: 00:1e.3 scanning...
1064 14:47:55.663011 scan_generic_bus for PCI: 00:1e.3
1065 14:47:55.663100 SPI: 00 enabled
1066 14:47:55.669408 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1067 14:47:55.676477 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1068 14:47:55.679324 PCI: 00:1f.0 scanning...
1069 14:47:55.682707 scan_static_bus for PCI: 00:1f.0
1070 14:47:55.682788 PNP: 0c09.0 enabled
1071 14:47:55.685901 PNP: 0c09.0 scanning...
1072 14:47:55.689120 scan_static_bus for PNP: 0c09.0
1073 14:47:55.692419 scan_static_bus for PNP: 0c09.0 done
1074 14:47:55.698981 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1075 14:47:55.702356 scan_static_bus for PCI: 00:1f.0 done
1076 14:47:55.705767 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1077 14:47:55.708933 PCI: 00:1f.2 scanning...
1078 14:47:55.712571 scan_static_bus for PCI: 00:1f.2
1079 14:47:55.715756 GENERIC: 0.0 enabled
1080 14:47:55.715833 GENERIC: 0.0 scanning...
1081 14:47:55.719113 scan_static_bus for GENERIC: 0.0
1082 14:47:55.722284 GENERIC: 0.0 enabled
1083 14:47:55.726003 GENERIC: 1.0 enabled
1084 14:47:55.729303 scan_static_bus for GENERIC: 0.0 done
1085 14:47:55.732532 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1086 14:47:55.739021 scan_static_bus for PCI: 00:1f.2 done
1087 14:47:55.741989 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1088 14:47:55.745537 PCI: 00:1f.3 scanning...
1089 14:47:55.749073 scan_static_bus for PCI: 00:1f.3
1090 14:47:55.752092 scan_static_bus for PCI: 00:1f.3 done
1091 14:47:55.755520 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1092 14:47:55.758557 PCI: 00:1f.5 scanning...
1093 14:47:55.761812 scan_generic_bus for PCI: 00:1f.5
1094 14:47:55.765197 scan_generic_bus for PCI: 00:1f.5 done
1095 14:47:55.771958 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1096 14:47:55.775408 scan_bus: bus DOMAIN: 0000 finished in 718 msecs
1097 14:47:55.782033 scan_static_bus for Root Device done
1098 14:47:55.785347 scan_bus: bus Root Device finished in 737 msecs
1099 14:47:55.785436 done
1100 14:47:55.791941 BS: BS_DEV_ENUMERATE run times (exec / console): 11 / 1296 ms
1101 14:47:55.795032 Chrome EC: UHEPI supported
1102 14:47:55.801350 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (196608 bytes)
1103 14:47:55.807990 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1104 14:47:55.811176 SPI flash protection: WPSW=0 SRP0=0
1105 14:47:55.814468 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1106 14:47:55.821399 BS: BS_DEV_ENUMERATE exit times (exec / console): 1 / 23 ms
1107 14:47:55.824422 found VGA at PCI: 00:02.0
1108 14:47:55.827620 Setting up VGA for PCI: 00:02.0
1109 14:47:55.831070 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1110 14:47:55.837787 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1111 14:47:55.841172 Allocating resources...
1112 14:47:55.841253 Reading resources...
1113 14:47:55.847492 Root Device read_resources bus 0 link: 0
1114 14:47:55.850907 DOMAIN: 0000 read_resources bus 0 link: 0
1115 14:47:55.854099 PCI: 00:04.0 read_resources bus 1 link: 0
1116 14:47:55.861546 PCI: 00:04.0 read_resources bus 1 link: 0 done
1117 14:47:55.864543 PCI: 00:0d.0 read_resources bus 0 link: 0
1118 14:47:55.871331 USB0 port 0 read_resources bus 0 link: 0
1119 14:47:55.875076 USB0 port 0 read_resources bus 0 link: 0 done
1120 14:47:55.881007 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1121 14:47:55.884324 PCI: 00:14.0 read_resources bus 0 link: 0
1122 14:47:55.891086 USB0 port 0 read_resources bus 0 link: 0
1123 14:47:55.894276 USB0 port 0 read_resources bus 0 link: 0 done
1124 14:47:55.900672 PCI: 00:14.0 read_resources bus 0 link: 0 done
1125 14:47:55.903916 PCI: 00:14.3 read_resources bus 0 link: 0
1126 14:47:55.910604 PCI: 00:14.3 read_resources bus 0 link: 0 done
1127 14:47:55.913905 PCI: 00:15.0 read_resources bus 0 link: 0
1128 14:47:55.920300 PCI: 00:15.0 read_resources bus 0 link: 0 done
1129 14:47:55.923870 PCI: 00:15.1 read_resources bus 0 link: 0
1130 14:47:55.930311 PCI: 00:15.1 read_resources bus 0 link: 0 done
1131 14:47:55.933504 PCI: 00:19.1 read_resources bus 0 link: 0
1132 14:47:55.941143 PCI: 00:19.1 read_resources bus 0 link: 0 done
1133 14:47:55.944064 PCI: 00:1d.0 read_resources bus 1 link: 0
1134 14:47:55.950660 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1135 14:47:55.953832 PCI: 00:1e.2 read_resources bus 2 link: 0
1136 14:47:55.960658 PCI: 00:1e.2 read_resources bus 2 link: 0 done
1137 14:47:55.964423 PCI: 00:1e.3 read_resources bus 3 link: 0
1138 14:47:55.970520 PCI: 00:1e.3 read_resources bus 3 link: 0 done
1139 14:47:55.974142 PCI: 00:1f.0 read_resources bus 0 link: 0
1140 14:47:55.980869 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1141 14:47:55.983685 PCI: 00:1f.2 read_resources bus 0 link: 0
1142 14:47:55.986987 GENERIC: 0.0 read_resources bus 0 link: 0
1143 14:47:55.994954 GENERIC: 0.0 read_resources bus 0 link: 0 done
1144 14:47:55.997905 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1145 14:47:56.004846 DOMAIN: 0000 read_resources bus 0 link: 0 done
1146 14:47:56.008179 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1147 14:47:56.014744 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1148 14:47:56.017906 Root Device read_resources bus 0 link: 0 done
1149 14:47:56.021566 Done reading resources.
1150 14:47:56.028085 Show resources in subtree (Root Device)...After reading.
1151 14:47:56.031188 Root Device child on link 0 DOMAIN: 0000
1152 14:47:56.034508 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1153 14:47:56.044756 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1154 14:47:56.054650 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1155 14:47:56.057774 PCI: 00:00.0
1156 14:47:56.068087 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1157 14:47:56.074309 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1158 14:47:56.084381 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1159 14:47:56.094200 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1160 14:47:56.104504 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1161 14:47:56.114359 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1162 14:47:56.124078 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1163 14:47:56.131045 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1164 14:47:56.140630 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1165 14:47:56.150865 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1166 14:47:56.161073 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1167 14:47:56.170696 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1168 14:47:56.180624 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1169 14:47:56.187483 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1170 14:47:56.197217 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1171 14:47:56.207313 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1172 14:47:56.216754 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1173 14:47:56.226813 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1174 14:47:56.237022 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1175 14:47:56.246859 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1176 14:47:56.246947 PCI: 00:02.0
1177 14:47:56.256630 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1178 14:47:56.266499 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1179 14:47:56.276724 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1180 14:47:56.279960 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1181 14:47:56.289721 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1182 14:47:56.293208 GENERIC: 0.0
1183 14:47:56.293294 PCI: 00:05.0
1184 14:47:56.302996 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1185 14:47:56.309351 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1186 14:47:56.309437 GENERIC: 0.0
1187 14:47:56.313018 PCI: 00:08.0
1188 14:47:56.322810 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1189 14:47:56.322897 PCI: 00:0a.0
1190 14:47:56.329341 PCI: 00:0d.0 child on link 0 USB0 port 0
1191 14:47:56.339336 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1192 14:47:56.342623 USB0 port 0 child on link 0 USB3 port 0
1193 14:47:56.345748 USB3 port 0
1194 14:47:56.345834 USB3 port 1
1195 14:47:56.348931 USB3 port 2
1196 14:47:56.349016 USB3 port 3
1197 14:47:56.352695 PCI: 00:14.0 child on link 0 USB0 port 0
1198 14:47:56.365642 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1199 14:47:56.368883 USB0 port 0 child on link 0 USB2 port 0
1200 14:47:56.368970 USB2 port 0
1201 14:47:56.372405 USB2 port 1
1202 14:47:56.372491 USB2 port 2
1203 14:47:56.375635 USB2 port 3
1204 14:47:56.378982 USB2 port 4
1205 14:47:56.379067 USB2 port 5
1206 14:47:56.382026 USB2 port 6
1207 14:47:56.382111 USB2 port 7
1208 14:47:56.385518 USB2 port 8
1209 14:47:56.385603 USB2 port 9
1210 14:47:56.389069 USB3 port 0
1211 14:47:56.389154 USB3 port 1
1212 14:47:56.391753 USB3 port 2
1213 14:47:56.391838 USB3 port 3
1214 14:47:56.395110 PCI: 00:14.2
1215 14:47:56.405283 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1216 14:47:56.415076 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1217 14:47:56.418253 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1218 14:47:56.428417 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1219 14:47:56.431777 GENERIC: 0.0
1220 14:47:56.435028 PCI: 00:15.0 child on link 0 I2C: 00:1a
1221 14:47:56.444571 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1222 14:47:56.448278 I2C: 00:1a
1223 14:47:56.448365 I2C: 00:31
1224 14:47:56.451294 I2C: 00:32
1225 14:47:56.454840 PCI: 00:15.1 child on link 0 I2C: 00:10
1226 14:47:56.464541 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1227 14:47:56.464688 I2C: 00:10
1228 14:47:56.467756 PCI: 00:15.2
1229 14:47:56.477895 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1230 14:47:56.478019 PCI: 00:15.3
1231 14:47:56.488112 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1232 14:47:56.490819 PCI: 00:16.0
1233 14:47:56.500736 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1234 14:47:56.500826 PCI: 00:19.0
1235 14:47:56.507406 PCI: 00:19.1 child on link 0 I2C: 00:15
1236 14:47:56.517249 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1237 14:47:56.517339 I2C: 00:15
1238 14:47:56.523844 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1239 14:47:56.530539 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1240 14:47:56.540442 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1241 14:47:56.550383 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1242 14:47:56.553721 GENERIC: 0.0
1243 14:47:56.553816 PCI: 01:00.0
1244 14:47:56.563742 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1245 14:47:56.573650 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18
1246 14:47:56.583201 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c
1247 14:47:56.583289 PCI: 00:1e.0
1248 14:47:56.596549 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1249 14:47:56.599799 PCI: 00:1e.2 child on link 0 SPI: 00
1250 14:47:56.609742 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1251 14:47:56.609830 SPI: 00
1252 14:47:56.613034 PCI: 00:1e.3 child on link 0 SPI: 00
1253 14:47:56.622647 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1254 14:47:56.625982 SPI: 00
1255 14:47:56.629296 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1256 14:47:56.639290 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1257 14:47:56.639378 PNP: 0c09.0
1258 14:47:56.649196 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1259 14:47:56.652427 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1260 14:47:56.662414 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1261 14:47:56.672314 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1262 14:47:56.675639 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1263 14:47:56.678664 GENERIC: 0.0
1264 14:47:56.682050 GENERIC: 1.0
1265 14:47:56.682167 PCI: 00:1f.3
1266 14:47:56.691946 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1267 14:47:56.702335 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1268 14:47:56.705122 PCI: 00:1f.5
1269 14:47:56.711813 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1270 14:47:56.718339 CPU_CLUSTER: 0 child on link 0 APIC: 00
1271 14:47:56.718423 APIC: 00
1272 14:47:56.718489 APIC: 01
1273 14:47:56.721564 APIC: 06
1274 14:47:56.721648 APIC: 02
1275 14:47:56.724923 APIC: 05
1276 14:47:56.725008 APIC: 04
1277 14:47:56.725093 APIC: 07
1278 14:47:56.728173 APIC: 03
1279 14:47:56.735074 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1280 14:47:56.741578 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
1281 14:47:56.748119 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1282 14:47:56.754640 PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1283 14:47:56.758220 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1284 14:47:56.761246 PCI: 01:00.0 18 * [0x4000 - 0x4fff] mem
1285 14:47:56.764614 PCI: 01:00.0 1c * [0x5000 - 0x5fff] mem
1286 14:47:56.774590 PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1287 14:47:56.781066 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1288 14:47:56.787741 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1289 14:47:56.794554 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1290 14:47:56.800940 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1291 14:47:56.807770 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1292 14:47:56.817416 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1293 14:47:56.824185 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1294 14:47:56.827687 DOMAIN: 0000: Resource ranges:
1295 14:47:56.830952 * Base: 1000, Size: 800, Tag: 100
1296 14:47:56.833654 * Base: 1900, Size: e700, Tag: 100
1297 14:47:56.840848 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1298 14:47:56.847305 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1299 14:47:56.853532 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1300 14:47:56.860771 update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
1301 14:47:56.870046 update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed)
1302 14:47:56.877205 update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
1303 14:47:56.883587 update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
1304 14:47:56.893647 update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
1305 14:47:56.899788 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
1306 14:47:56.906358 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
1307 14:47:56.916630 update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
1308 14:47:56.923178 update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
1309 14:47:56.929877 update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
1310 14:47:56.939790 update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
1311 14:47:56.946146 update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
1312 14:47:56.953000 update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
1313 14:47:56.962591 update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
1314 14:47:56.969117 update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
1315 14:47:56.975866 update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed)
1316 14:47:56.985498 update_constraints: PCI: 00:00.0 10 base 100000000 limit 2803fffff mem (fixed)
1317 14:47:56.993082 update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
1318 14:47:56.999033 update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
1319 14:47:57.008955 update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed)
1320 14:47:57.015712 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1321 14:47:57.022193 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1322 14:47:57.025582 DOMAIN: 0000: Resource ranges:
1323 14:47:57.031719 * Base: 7fc00000, Size: 40400000, Tag: 200
1324 14:47:57.035151 * Base: d0000000, Size: 28000000, Tag: 200
1325 14:47:57.038831 * Base: fa000000, Size: 1000000, Tag: 200
1326 14:47:57.045165 * Base: fb001000, Size: 2fff000, Tag: 200
1327 14:47:57.048407 * Base: fe010000, Size: 2e000, Tag: 200
1328 14:47:57.051593 * Base: fe03f000, Size: d41000, Tag: 200
1329 14:47:57.054942 * Base: fed88000, Size: 8000, Tag: 200
1330 14:47:57.058323 * Base: fed93000, Size: d000, Tag: 200
1331 14:47:57.064881 * Base: feda2000, Size: 1e000, Tag: 200
1332 14:47:57.068051 * Base: fede0000, Size: 1220000, Tag: 200
1333 14:47:57.074881 * Base: 280400000, Size: 7d7fc00000, Tag: 100200
1334 14:47:57.081318 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
1335 14:47:57.088506 PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
1336 14:47:57.094693 PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
1337 14:47:57.101349 PCI: 00:1d.0 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
1338 14:47:57.108218 PCI: 00:1f.3 20 * [0x7fd00000 - 0x7fdfffff] limit: 7fdfffff mem
1339 14:47:57.114807 PCI: 00:04.0 10 * [0x7fe00000 - 0x7fe1ffff] limit: 7fe1ffff mem
1340 14:47:57.120909 PCI: 00:0d.0 10 * [0x7fe20000 - 0x7fe2ffff] limit: 7fe2ffff mem
1341 14:47:57.128011 PCI: 00:14.0 10 * [0x7fe30000 - 0x7fe3ffff] limit: 7fe3ffff mem
1342 14:47:57.134718 PCI: 00:14.2 10 * [0x7fe40000 - 0x7fe43fff] limit: 7fe43fff mem
1343 14:47:57.140732 PCI: 00:14.3 10 * [0x7fe44000 - 0x7fe47fff] limit: 7fe47fff mem
1344 14:47:57.147822 PCI: 00:1f.3 10 * [0x7fe48000 - 0x7fe4bfff] limit: 7fe4bfff mem
1345 14:47:57.154147 PCI: 00:08.0 10 * [0x7fe4c000 - 0x7fe4cfff] limit: 7fe4cfff mem
1346 14:47:57.160730 PCI: 00:14.2 18 * [0x7fe4d000 - 0x7fe4dfff] limit: 7fe4dfff mem
1347 14:47:57.167488 PCI: 00:15.0 10 * [0x7fe4e000 - 0x7fe4efff] limit: 7fe4efff mem
1348 14:47:57.173991 PCI: 00:15.1 10 * [0x7fe4f000 - 0x7fe4ffff] limit: 7fe4ffff mem
1349 14:47:57.180586 PCI: 00:15.2 10 * [0x7fe50000 - 0x7fe50fff] limit: 7fe50fff mem
1350 14:47:57.187210 PCI: 00:15.3 10 * [0x7fe51000 - 0x7fe51fff] limit: 7fe51fff mem
1351 14:47:57.193856 PCI: 00:16.0 10 * [0x7fe52000 - 0x7fe52fff] limit: 7fe52fff mem
1352 14:47:57.200439 PCI: 00:19.1 10 * [0x7fe53000 - 0x7fe53fff] limit: 7fe53fff mem
1353 14:47:57.207067 PCI: 00:1e.2 10 * [0x7fe54000 - 0x7fe54fff] limit: 7fe54fff mem
1354 14:47:57.213820 PCI: 00:1e.3 10 * [0x7fe55000 - 0x7fe55fff] limit: 7fe55fff mem
1355 14:47:57.220003 PCI: 00:1f.5 10 * [0x7fe56000 - 0x7fe56fff] limit: 7fe56fff mem
1356 14:47:57.226667 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1357 14:47:57.236760 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff
1358 14:47:57.236891 PCI: 00:1d.0: Resource ranges:
1359 14:47:57.243291 * Base: 7fc00000, Size: 100000, Tag: 200
1360 14:47:57.249652 PCI: 01:00.0 10 * [0x7fc00000 - 0x7fc03fff] limit: 7fc03fff mem
1361 14:47:57.256245 PCI: 01:00.0 18 * [0x7fc04000 - 0x7fc04fff] limit: 7fc04fff mem
1362 14:47:57.263309 PCI: 01:00.0 1c * [0x7fc05000 - 0x7fc05fff] limit: 7fc05fff mem
1363 14:47:57.269286 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff done
1364 14:47:57.279344 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1365 14:47:57.282714 Root Device assign_resources, bus 0 link: 0
1366 14:47:57.286012 DOMAIN: 0000 assign_resources, bus 0 link: 0
1367 14:47:57.295954 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
1368 14:47:57.302617 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
1369 14:47:57.312406 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1370 14:47:57.319094 PCI: 00:04.0 10 <- [0x007fe00000 - 0x007fe1ffff] size 0x00020000 gran 0x11 mem64
1371 14:47:57.325852 PCI: 00:04.0 assign_resources, bus 1 link: 0
1372 14:47:57.329215 PCI: 00:04.0 assign_resources, bus 1 link: 0
1373 14:47:57.339202 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64
1374 14:47:57.345668 PCI: 00:08.0 10 <- [0x007fe4c000 - 0x007fe4cfff] size 0x00001000 gran 0x0c mem64
1375 14:47:57.355152 PCI: 00:0d.0 10 <- [0x007fe20000 - 0x007fe2ffff] size 0x00010000 gran 0x10 mem64
1376 14:47:57.358889 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1377 14:47:57.361973 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1378 14:47:57.371853 PCI: 00:14.0 10 <- [0x007fe30000 - 0x007fe3ffff] size 0x00010000 gran 0x10 mem64
1379 14:47:57.375020 PCI: 00:14.0 assign_resources, bus 0 link: 0
1380 14:47:57.381829 PCI: 00:14.0 assign_resources, bus 0 link: 0
1381 14:47:57.388797 PCI: 00:14.2 10 <- [0x007fe40000 - 0x007fe43fff] size 0x00004000 gran 0x0e mem64
1382 14:47:57.398237 PCI: 00:14.2 18 <- [0x007fe4d000 - 0x007fe4dfff] size 0x00001000 gran 0x0c mem64
1383 14:47:57.405114 PCI: 00:14.3 10 <- [0x007fe44000 - 0x007fe47fff] size 0x00004000 gran 0x0e mem64
1384 14:47:57.407725 PCI: 00:14.3 assign_resources, bus 0 link: 0
1385 14:47:57.414461 PCI: 00:14.3 assign_resources, bus 0 link: 0
1386 14:47:57.421189 PCI: 00:15.0 10 <- [0x007fe4e000 - 0x007fe4efff] size 0x00001000 gran 0x0c mem64
1387 14:47:57.427621 PCI: 00:15.0 assign_resources, bus 0 link: 0
1388 14:47:57.431107 PCI: 00:15.0 assign_resources, bus 0 link: 0
1389 14:47:57.440773 PCI: 00:15.1 10 <- [0x007fe4f000 - 0x007fe4ffff] size 0x00001000 gran 0x0c mem64
1390 14:47:57.444191 PCI: 00:15.1 assign_resources, bus 0 link: 0
1391 14:47:57.450875 PCI: 00:15.1 assign_resources, bus 0 link: 0
1392 14:47:57.457047 PCI: 00:15.2 10 <- [0x007fe50000 - 0x007fe50fff] size 0x00001000 gran 0x0c mem64
1393 14:47:57.467271 PCI: 00:15.3 10 <- [0x007fe51000 - 0x007fe51fff] size 0x00001000 gran 0x0c mem64
1394 14:47:57.473572 PCI: 00:16.0 10 <- [0x007fe52000 - 0x007fe52fff] size 0x00001000 gran 0x0c mem64
1395 14:47:57.483624 PCI: 00:19.1 10 <- [0x007fe53000 - 0x007fe53fff] size 0x00001000 gran 0x0c mem64
1396 14:47:57.486770 PCI: 00:19.1 assign_resources, bus 0 link: 0
1397 14:47:57.490569 PCI: 00:19.1 assign_resources, bus 0 link: 0
1398 14:47:57.499958 PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1399 14:47:57.510355 PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1400 14:47:57.520198 PCI: 00:1d.0 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 bus 01 mem
1401 14:47:57.523675 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1402 14:47:57.529605 PCI: 01:00.0 10 <- [0x007fc00000 - 0x007fc03fff] size 0x00004000 gran 0x0e mem64
1403 14:47:57.540034 PCI: 01:00.0 18 <- [0x007fc04000 - 0x007fc04fff] size 0x00001000 gran 0x0c mem
1404 14:47:57.546161 PCI: 01:00.0 1c <- [0x007fc05000 - 0x007fc05fff] size 0x00001000 gran 0x0c mem
1405 14:47:57.553160 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1406 14:47:57.560006 PCI: 00:1e.2 10 <- [0x007fe54000 - 0x007fe54fff] size 0x00001000 gran 0x0c mem64
1407 14:47:57.566317 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1408 14:47:57.569556 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1409 14:47:57.576094 PCI: 00:1e.3 10 <- [0x007fe55000 - 0x007fe55fff] size 0x00001000 gran 0x0c mem64
1410 14:47:57.582605 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1411 14:47:57.585982 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1412 14:47:57.592685 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1413 14:47:57.595944 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1414 14:47:57.602658 LPC: Trying to open IO window from 800 size 1ff
1415 14:47:57.609275 PCI: 00:1f.3 10 <- [0x007fe48000 - 0x007fe4bfff] size 0x00004000 gran 0x0e mem64
1416 14:47:57.619116 PCI: 00:1f.3 20 <- [0x007fd00000 - 0x007fdfffff] size 0x00100000 gran 0x14 mem64
1417 14:47:57.625993 PCI: 00:1f.5 10 <- [0x007fe56000 - 0x007fe56fff] size 0x00001000 gran 0x0c mem
1418 14:47:57.632463 DOMAIN: 0000 assign_resources, bus 0 link: 0
1419 14:47:57.635754 Root Device assign_resources, bus 0 link: 0
1420 14:47:57.638983 Done setting resources.
1421 14:47:57.645653 Show resources in subtree (Root Device)...After assigning values.
1422 14:47:57.648980 Root Device child on link 0 DOMAIN: 0000
1423 14:47:57.652142 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1424 14:47:57.661883 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1425 14:47:57.672081 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1426 14:47:57.675507 PCI: 00:00.0
1427 14:47:57.681872 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1428 14:47:57.691523 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1429 14:47:57.701663 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1430 14:47:57.711226 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1431 14:47:57.721071 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1432 14:47:57.731068 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1433 14:47:57.741483 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1434 14:47:57.747930 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1435 14:47:57.758023 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1436 14:47:57.768026 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1437 14:47:57.777667 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1438 14:47:57.787711 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1439 14:47:57.794510 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1440 14:47:57.803884 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1441 14:47:57.813934 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1442 14:47:57.823749 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1443 14:47:57.833962 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1444 14:47:57.843558 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1445 14:47:57.853504 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1446 14:47:57.863619 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1447 14:47:57.863707 PCI: 00:02.0
1448 14:47:57.873239 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10
1449 14:47:57.886445 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18
1450 14:47:57.893173 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1451 14:47:57.899747 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1452 14:47:57.909863 PCI: 00:04.0 resource base 7fe00000 size 20000 align 17 gran 17 limit 7fe1ffff flags 60000201 index 10
1453 14:47:57.909949 GENERIC: 0.0
1454 14:47:57.913255 PCI: 00:05.0
1455 14:47:57.923035 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10
1456 14:47:57.926401 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1457 14:47:57.929134 GENERIC: 0.0
1458 14:47:57.929215 PCI: 00:08.0
1459 14:47:57.942796 PCI: 00:08.0 resource base 7fe4c000 size 1000 align 12 gran 12 limit 7fe4cfff flags 60000201 index 10
1460 14:47:57.942881 PCI: 00:0a.0
1461 14:47:57.946296 PCI: 00:0d.0 child on link 0 USB0 port 0
1462 14:47:57.959035 PCI: 00:0d.0 resource base 7fe20000 size 10000 align 16 gran 16 limit 7fe2ffff flags 60000201 index 10
1463 14:47:57.962407 USB0 port 0 child on link 0 USB3 port 0
1464 14:47:57.962491 USB3 port 0
1465 14:47:57.965670 USB3 port 1
1466 14:47:57.969431 USB3 port 2
1467 14:47:57.969507 USB3 port 3
1468 14:47:57.972729 PCI: 00:14.0 child on link 0 USB0 port 0
1469 14:47:57.985928 PCI: 00:14.0 resource base 7fe30000 size 10000 align 16 gran 16 limit 7fe3ffff flags 60000201 index 10
1470 14:47:57.989328 USB0 port 0 child on link 0 USB2 port 0
1471 14:47:57.989429 USB2 port 0
1472 14:47:57.991931 USB2 port 1
1473 14:47:57.995423 USB2 port 2
1474 14:47:57.995503 USB2 port 3
1475 14:47:57.998750 USB2 port 4
1476 14:47:57.998829 USB2 port 5
1477 14:47:58.002082 USB2 port 6
1478 14:47:58.002165 USB2 port 7
1479 14:47:58.005363 USB2 port 8
1480 14:47:58.005447 USB2 port 9
1481 14:47:58.008809 USB3 port 0
1482 14:47:58.008887 USB3 port 1
1483 14:47:58.012168 USB3 port 2
1484 14:47:58.012244 USB3 port 3
1485 14:47:58.015395 PCI: 00:14.2
1486 14:47:58.025087 PCI: 00:14.2 resource base 7fe40000 size 4000 align 14 gran 14 limit 7fe43fff flags 60000201 index 10
1487 14:47:58.035149 PCI: 00:14.2 resource base 7fe4d000 size 1000 align 12 gran 12 limit 7fe4dfff flags 60000201 index 18
1488 14:47:58.041772 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1489 14:47:58.051803 PCI: 00:14.3 resource base 7fe44000 size 4000 align 14 gran 14 limit 7fe47fff flags 60000201 index 10
1490 14:47:58.051889 GENERIC: 0.0
1491 14:47:58.055067 PCI: 00:15.0 child on link 0 I2C: 00:1a
1492 14:47:58.068405 PCI: 00:15.0 resource base 7fe4e000 size 1000 align 12 gran 12 limit 7fe4efff flags 60000201 index 10
1493 14:47:58.068491 I2C: 00:1a
1494 14:47:58.071627 I2C: 00:31
1495 14:47:58.071714 I2C: 00:32
1496 14:47:58.074914 PCI: 00:15.1 child on link 0 I2C: 00:10
1497 14:47:58.084738 PCI: 00:15.1 resource base 7fe4f000 size 1000 align 12 gran 12 limit 7fe4ffff flags 60000201 index 10
1498 14:47:58.087913 I2C: 00:10
1499 14:47:58.087998 PCI: 00:15.2
1500 14:47:58.101349 PCI: 00:15.2 resource base 7fe50000 size 1000 align 12 gran 12 limit 7fe50fff flags 60000201 index 10
1501 14:47:58.101434 PCI: 00:15.3
1502 14:47:58.111045 PCI: 00:15.3 resource base 7fe51000 size 1000 align 12 gran 12 limit 7fe51fff flags 60000201 index 10
1503 14:47:58.114419 PCI: 00:16.0
1504 14:47:58.124360 PCI: 00:16.0 resource base 7fe52000 size 1000 align 12 gran 12 limit 7fe52fff flags 60000201 index 10
1505 14:47:58.124454 PCI: 00:19.0
1506 14:47:58.131095 PCI: 00:19.1 child on link 0 I2C: 00:15
1507 14:47:58.140724 PCI: 00:19.1 resource base 7fe53000 size 1000 align 12 gran 12 limit 7fe53fff flags 60000201 index 10
1508 14:47:58.140815 I2C: 00:15
1509 14:47:58.147939 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1510 14:47:58.154237 PCI: 00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1511 14:47:58.167368 PCI: 00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1512 14:47:58.177494 PCI: 00:1d.0 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60080202 index 20
1513 14:47:58.180738 GENERIC: 0.0
1514 14:47:58.180822 PCI: 01:00.0
1515 14:47:58.190373 PCI: 01:00.0 resource base 7fc00000 size 4000 align 14 gran 14 limit 7fc03fff flags 60000201 index 10
1516 14:47:58.203735 PCI: 01:00.0 resource base 7fc04000 size 1000 align 12 gran 12 limit 7fc04fff flags 60000200 index 18
1517 14:47:58.213583 PCI: 01:00.0 resource base 7fc05000 size 1000 align 12 gran 12 limit 7fc05fff flags 60000200 index 1c
1518 14:47:58.213686 PCI: 00:1e.0
1519 14:47:58.226966 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1520 14:47:58.230323 PCI: 00:1e.2 child on link 0 SPI: 00
1521 14:47:58.239873 PCI: 00:1e.2 resource base 7fe54000 size 1000 align 12 gran 12 limit 7fe54fff flags 60000201 index 10
1522 14:47:58.239961 SPI: 00
1523 14:47:58.243125 PCI: 00:1e.3 child on link 0 SPI: 00
1524 14:47:58.257035 PCI: 00:1e.3 resource base 7fe55000 size 1000 align 12 gran 12 limit 7fe55fff flags 60000201 index 10
1525 14:47:58.257123 SPI: 00
1526 14:47:58.259749 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1527 14:47:58.269653 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1528 14:47:58.269777 PNP: 0c09.0
1529 14:47:58.279695 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1530 14:47:58.282943 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1531 14:47:58.293085 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1532 14:47:58.302893 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1533 14:47:58.306149 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1534 14:47:58.309636 GENERIC: 0.0
1535 14:47:58.312716 GENERIC: 1.0
1536 14:47:58.312800 PCI: 00:1f.3
1537 14:47:58.322807 PCI: 00:1f.3 resource base 7fe48000 size 4000 align 14 gran 14 limit 7fe4bfff flags 60000201 index 10
1538 14:47:58.332508 PCI: 00:1f.3 resource base 7fd00000 size 100000 align 20 gran 20 limit 7fdfffff flags 60000201 index 20
1539 14:47:58.335871 PCI: 00:1f.5
1540 14:47:58.346059 PCI: 00:1f.5 resource base 7fe56000 size 1000 align 12 gran 12 limit 7fe56fff flags 60000200 index 10
1541 14:47:58.349235 CPU_CLUSTER: 0 child on link 0 APIC: 00
1542 14:47:58.352641 APIC: 00
1543 14:47:58.352721 APIC: 01
1544 14:47:58.352788 APIC: 06
1545 14:47:58.355810 APIC: 02
1546 14:47:58.355886 APIC: 05
1547 14:47:58.359132 APIC: 04
1548 14:47:58.359209 APIC: 07
1549 14:47:58.359274 APIC: 03
1550 14:47:58.362524 Done allocating resources.
1551 14:47:58.369232 BS: BS_DEV_RESOURCES run times (exec / console): 28 / 2514 ms
1552 14:47:58.375865 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
1553 14:47:58.379171 Configure GPIOs for I2S audio on UP4.
1554 14:47:58.385540 BS: BS_DEV_ENABLE entry times (exec / console): 2 / 9 ms
1555 14:47:58.388691 Enabling resources...
1556 14:47:58.392189 PCI: 00:00.0 subsystem <- 8086/9a12
1557 14:47:58.395353 PCI: 00:00.0 cmd <- 06
1558 14:47:58.398683 PCI: 00:02.0 subsystem <- 8086/9a40
1559 14:47:58.402059 PCI: 00:02.0 cmd <- 03
1560 14:47:58.405372 PCI: 00:04.0 subsystem <- 8086/9a03
1561 14:47:58.408576 PCI: 00:04.0 cmd <- 02
1562 14:47:58.411745 PCI: 00:05.0 subsystem <- 8086/9a19
1563 14:47:58.411823 PCI: 00:05.0 cmd <- 02
1564 14:47:58.418581 PCI: 00:08.0 subsystem <- 8086/9a11
1565 14:47:58.418661 PCI: 00:08.0 cmd <- 06
1566 14:47:58.421852 PCI: 00:0d.0 subsystem <- 8086/9a13
1567 14:47:58.425238 PCI: 00:0d.0 cmd <- 02
1568 14:47:58.428637 PCI: 00:14.0 subsystem <- 8086/a0ed
1569 14:47:58.431862 PCI: 00:14.0 cmd <- 02
1570 14:47:58.435327 PCI: 00:14.2 subsystem <- 8086/a0ef
1571 14:47:58.438754 PCI: 00:14.2 cmd <- 02
1572 14:47:58.441524 PCI: 00:14.3 subsystem <- 8086/a0f0
1573 14:47:58.445280 PCI: 00:14.3 cmd <- 02
1574 14:47:58.448471 PCI: 00:15.0 subsystem <- 8086/a0e8
1575 14:47:58.451769 PCI: 00:15.0 cmd <- 02
1576 14:47:58.455024 PCI: 00:15.1 subsystem <- 8086/a0e9
1577 14:47:58.458312 PCI: 00:15.1 cmd <- 02
1578 14:47:58.461590 PCI: 00:15.2 subsystem <- 8086/a0ea
1579 14:47:58.461683 PCI: 00:15.2 cmd <- 02
1580 14:47:58.468298 PCI: 00:15.3 subsystem <- 8086/a0eb
1581 14:47:58.468382 PCI: 00:15.3 cmd <- 02
1582 14:47:58.471761 PCI: 00:16.0 subsystem <- 8086/a0e0
1583 14:47:58.475138 PCI: 00:16.0 cmd <- 02
1584 14:47:58.478474 PCI: 00:19.1 subsystem <- 8086/a0c6
1585 14:47:58.481462 PCI: 00:19.1 cmd <- 02
1586 14:47:58.485046 PCI: 00:1d.0 bridge ctrl <- 0013
1587 14:47:58.488260 PCI: 00:1d.0 subsystem <- 8086/a0b0
1588 14:47:58.491459 PCI: 00:1d.0 cmd <- 06
1589 14:47:58.494810 PCI: 00:1e.0 subsystem <- 8086/a0a8
1590 14:47:58.498070 PCI: 00:1e.0 cmd <- 06
1591 14:47:58.501356 PCI: 00:1e.2 subsystem <- 8086/a0aa
1592 14:47:58.504859 PCI: 00:1e.2 cmd <- 06
1593 14:47:58.508094 PCI: 00:1e.3 subsystem <- 8086/a0ab
1594 14:47:58.510946 PCI: 00:1e.3 cmd <- 02
1595 14:47:58.514204 PCI: 00:1f.0 subsystem <- 8086/a087
1596 14:47:58.517499 PCI: 00:1f.0 cmd <- 407
1597 14:47:58.521036 PCI: 00:1f.3 subsystem <- 8086/a0c8
1598 14:47:58.521122 PCI: 00:1f.3 cmd <- 02
1599 14:47:58.527516 PCI: 00:1f.5 subsystem <- 8086/a0a4
1600 14:47:58.527602 PCI: 00:1f.5 cmd <- 406
1601 14:47:58.532930 PCI: 01:00.0 cmd <- 02
1602 14:47:58.537586 done.
1603 14:47:58.540844 BS: BS_DEV_ENABLE run times (exec / console): 10 / 140 ms
1604 14:47:58.544267 Initializing devices...
1605 14:47:58.547663 Root Device init
1606 14:47:58.550801 Chrome EC: Set SMI mask to 0x0000000000000000
1607 14:47:58.557315 Chrome EC: clear events_b mask to 0x0000000000000000
1608 14:47:58.563918 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1609 14:47:58.567324 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001800101e
1610 14:47:58.574360 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001800101e
1611 14:47:58.581028 Chrome EC: Set WAKE mask to 0x0000000000000000
1612 14:47:58.584386 fw_config match found: DB_USB=USB3_ACTIVE
1613 14:47:58.590881 Configure Right Type-C port orientation for retimer
1614 14:47:58.594111 Root Device init finished in 44 msecs
1615 14:47:58.597180 PCI: 00:00.0 init
1616 14:47:58.601028 CPU TDP = 9 Watts
1617 14:47:58.601113 CPU PL1 = 9 Watts
1618 14:47:58.604318 CPU PL2 = 40 Watts
1619 14:47:58.607119 CPU PL4 = 83 Watts
1620 14:47:58.610439 PCI: 00:00.0 init finished in 8 msecs
1621 14:47:58.610523 PCI: 00:02.0 init
1622 14:47:58.613826 GMA: Found VBT in CBFS
1623 14:47:58.617109 GMA: Found valid VBT in CBFS
1624 14:47:58.623853 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1625 14:47:58.630389 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
1626 14:47:58.633789 PCI: 00:02.0 init finished in 18 msecs
1627 14:47:58.637131 PCI: 00:05.0 init
1628 14:47:58.640415 PCI: 00:05.0 init finished in 0 msecs
1629 14:47:58.643819 PCI: 00:08.0 init
1630 14:47:58.647004 PCI: 00:08.0 init finished in 0 msecs
1631 14:47:58.650459 PCI: 00:14.0 init
1632 14:47:58.653646 PCI: 00:14.0 init finished in 0 msecs
1633 14:47:58.657135 PCI: 00:14.2 init
1634 14:47:58.660293 PCI: 00:14.2 init finished in 0 msecs
1635 14:47:58.663247 PCI: 00:15.0 init
1636 14:47:58.666608 I2C bus 0 version 0x3230302a
1637 14:47:58.669871 DW I2C bus 0 at 0x7fe4e000 (400 KHz)
1638 14:47:58.673068 PCI: 00:15.0 init finished in 6 msecs
1639 14:47:58.676521 PCI: 00:15.1 init
1640 14:47:58.676607 I2C bus 1 version 0x3230302a
1641 14:47:58.683257 DW I2C bus 1 at 0x7fe4f000 (400 KHz)
1642 14:47:58.686460 PCI: 00:15.1 init finished in 6 msecs
1643 14:47:58.686548 PCI: 00:15.2 init
1644 14:47:58.689665 I2C bus 2 version 0x3230302a
1645 14:47:58.693044 DW I2C bus 2 at 0x7fe50000 (400 KHz)
1646 14:47:58.699885 PCI: 00:15.2 init finished in 6 msecs
1647 14:47:58.699978 PCI: 00:15.3 init
1648 14:47:58.703328 I2C bus 3 version 0x3230302a
1649 14:47:58.706652 DW I2C bus 3 at 0x7fe51000 (400 KHz)
1650 14:47:58.709413 PCI: 00:15.3 init finished in 6 msecs
1651 14:47:58.712814 PCI: 00:16.0 init
1652 14:47:58.716046 PCI: 00:16.0 init finished in 0 msecs
1653 14:47:58.719264 PCI: 00:19.1 init
1654 14:47:58.723119 I2C bus 5 version 0x3230302a
1655 14:47:58.726032 DW I2C bus 5 at 0x7fe53000 (400 KHz)
1656 14:47:58.729415 PCI: 00:19.1 init finished in 6 msecs
1657 14:47:58.732848 PCI: 00:1d.0 init
1658 14:47:58.736130 Initializing PCH PCIe bridge.
1659 14:47:58.739560 PCI: 00:1d.0 init finished in 3 msecs
1660 14:47:58.742692 PCI: 00:1f.0 init
1661 14:47:58.746027 IOAPIC: Initializing IOAPIC at 0xfec00000
1662 14:47:58.749366 IOAPIC: Bootstrap Processor Local APIC = 0x00
1663 14:47:58.752403 IOAPIC: ID = 0x02
1664 14:47:58.755661 IOAPIC: Dumping registers
1665 14:47:58.759261 reg 0x0000: 0x02000000
1666 14:47:58.759345 reg 0x0001: 0x00770020
1667 14:47:58.762431 reg 0x0002: 0x00000000
1668 14:47:58.765836 PCI: 00:1f.0 init finished in 21 msecs
1669 14:47:58.769114 PCI: 00:1f.2 init
1670 14:47:58.772435 Disabling ACPI via APMC.
1671 14:47:58.775768 APMC done.
1672 14:47:58.779052 PCI: 00:1f.2 init finished in 5 msecs
1673 14:47:58.790075 PCI: 01:00.0 init
1674 14:47:58.793400 PCI: 01:00.0 init finished in 0 msecs
1675 14:47:58.796578 PNP: 0c09.0 init
1676 14:47:58.799876 Google Chrome EC uptime: 8.430 seconds
1677 14:47:58.806422 Google Chrome AP resets since EC boot: 1
1678 14:47:58.809769 Google Chrome most recent AP reset causes:
1679 14:47:58.813333 0.379: 32775 shutdown: entering G3
1680 14:47:58.819812 Google Chrome EC reset flags at last EC boot: reset-pin | sysjump
1681 14:47:58.823108 PNP: 0c09.0 init finished in 23 msecs
1682 14:47:58.829224 Devices initialized
1683 14:47:58.832118 Show all devs... After init.
1684 14:47:58.835517 Root Device: enabled 1
1685 14:47:58.835601 DOMAIN: 0000: enabled 1
1686 14:47:58.838801 CPU_CLUSTER: 0: enabled 1
1687 14:47:58.842217 PCI: 00:00.0: enabled 1
1688 14:47:58.845433 PCI: 00:02.0: enabled 1
1689 14:47:58.845515 PCI: 00:04.0: enabled 1
1690 14:47:58.848755 PCI: 00:05.0: enabled 1
1691 14:47:58.852195 PCI: 00:06.0: enabled 0
1692 14:47:58.855363 PCI: 00:07.0: enabled 0
1693 14:47:58.855448 PCI: 00:07.1: enabled 0
1694 14:47:58.858708 PCI: 00:07.2: enabled 0
1695 14:47:58.861745 PCI: 00:07.3: enabled 0
1696 14:47:58.865666 PCI: 00:08.0: enabled 1
1697 14:47:58.865785 PCI: 00:09.0: enabled 0
1698 14:47:58.868442 PCI: 00:0a.0: enabled 0
1699 14:47:58.872253 PCI: 00:0d.0: enabled 1
1700 14:47:58.875521 PCI: 00:0d.1: enabled 0
1701 14:47:58.875602 PCI: 00:0d.2: enabled 0
1702 14:47:58.879113 PCI: 00:0d.3: enabled 0
1703 14:47:58.882154 PCI: 00:0e.0: enabled 0
1704 14:47:58.885108 PCI: 00:10.2: enabled 1
1705 14:47:58.885190 PCI: 00:10.6: enabled 0
1706 14:47:58.889070 PCI: 00:10.7: enabled 0
1707 14:47:58.892158 PCI: 00:12.0: enabled 0
1708 14:47:58.892241 PCI: 00:12.6: enabled 0
1709 14:47:58.895027 PCI: 00:13.0: enabled 0
1710 14:47:58.898278 PCI: 00:14.0: enabled 1
1711 14:47:58.901639 PCI: 00:14.1: enabled 0
1712 14:47:58.901744 PCI: 00:14.2: enabled 1
1713 14:47:58.904796 PCI: 00:14.3: enabled 1
1714 14:47:58.908593 PCI: 00:15.0: enabled 1
1715 14:47:58.911946 PCI: 00:15.1: enabled 1
1716 14:47:58.912031 PCI: 00:15.2: enabled 1
1717 14:47:58.914725 PCI: 00:15.3: enabled 1
1718 14:47:58.917986 PCI: 00:16.0: enabled 1
1719 14:47:58.921976 PCI: 00:16.1: enabled 0
1720 14:47:58.922054 PCI: 00:16.2: enabled 0
1721 14:47:58.925176 PCI: 00:16.3: enabled 0
1722 14:47:58.927896 PCI: 00:16.4: enabled 0
1723 14:47:58.931215 PCI: 00:16.5: enabled 0
1724 14:47:58.931299 PCI: 00:17.0: enabled 0
1725 14:47:58.934779 PCI: 00:19.0: enabled 0
1726 14:47:58.937916 PCI: 00:19.1: enabled 1
1727 14:47:58.941113 PCI: 00:19.2: enabled 0
1728 14:47:58.941189 PCI: 00:1c.0: enabled 1
1729 14:47:58.944823 PCI: 00:1c.1: enabled 0
1730 14:47:58.948118 PCI: 00:1c.2: enabled 0
1731 14:47:58.948206 PCI: 00:1c.3: enabled 0
1732 14:47:58.951523 PCI: 00:1c.4: enabled 0
1733 14:47:58.954762 PCI: 00:1c.5: enabled 0
1734 14:47:58.958010 PCI: 00:1c.6: enabled 1
1735 14:47:58.958093 PCI: 00:1c.7: enabled 0
1736 14:47:58.961383 PCI: 00:1d.0: enabled 1
1737 14:47:58.964589 PCI: 00:1d.1: enabled 0
1738 14:47:58.967858 PCI: 00:1d.2: enabled 1
1739 14:47:58.967941 PCI: 00:1d.3: enabled 0
1740 14:47:58.971158 PCI: 00:1e.0: enabled 1
1741 14:47:58.974554 PCI: 00:1e.1: enabled 0
1742 14:47:58.977951 PCI: 00:1e.2: enabled 1
1743 14:47:58.978034 PCI: 00:1e.3: enabled 1
1744 14:47:58.981199 PCI: 00:1f.0: enabled 1
1745 14:47:58.984350 PCI: 00:1f.1: enabled 0
1746 14:47:58.987825 PCI: 00:1f.2: enabled 1
1747 14:47:58.987908 PCI: 00:1f.3: enabled 1
1748 14:47:58.991195 PCI: 00:1f.4: enabled 0
1749 14:47:58.994059 PCI: 00:1f.5: enabled 1
1750 14:47:58.997659 PCI: 00:1f.6: enabled 0
1751 14:47:58.997774 PCI: 00:1f.7: enabled 0
1752 14:47:59.000858 APIC: 00: enabled 1
1753 14:47:59.004206 GENERIC: 0.0: enabled 1
1754 14:47:59.004289 GENERIC: 0.0: enabled 1
1755 14:47:59.007450 GENERIC: 1.0: enabled 1
1756 14:47:59.010816 GENERIC: 0.0: enabled 1
1757 14:47:59.014214 GENERIC: 1.0: enabled 1
1758 14:47:59.014296 USB0 port 0: enabled 1
1759 14:47:59.017099 GENERIC: 0.0: enabled 1
1760 14:47:59.020772 USB0 port 0: enabled 1
1761 14:47:59.024030 GENERIC: 0.0: enabled 1
1762 14:47:59.024112 I2C: 00:1a: enabled 1
1763 14:47:59.027340 I2C: 00:31: enabled 1
1764 14:47:59.030720 I2C: 00:32: enabled 1
1765 14:47:59.030805 I2C: 00:10: enabled 1
1766 14:47:59.033581 I2C: 00:15: enabled 1
1767 14:47:59.036739 GENERIC: 0.0: enabled 0
1768 14:47:59.036821 GENERIC: 1.0: enabled 0
1769 14:47:59.040583 GENERIC: 0.0: enabled 1
1770 14:47:59.043812 SPI: 00: enabled 1
1771 14:47:59.043895 SPI: 00: enabled 1
1772 14:47:59.046787 PNP: 0c09.0: enabled 1
1773 14:47:59.050031 GENERIC: 0.0: enabled 1
1774 14:47:59.050114 USB3 port 0: enabled 1
1775 14:47:59.053400 USB3 port 1: enabled 1
1776 14:47:59.056798 USB3 port 2: enabled 0
1777 14:47:59.060057 USB3 port 3: enabled 0
1778 14:47:59.060142 USB2 port 0: enabled 0
1779 14:47:59.063440 USB2 port 1: enabled 1
1780 14:47:59.066707 USB2 port 2: enabled 1
1781 14:47:59.066792 USB2 port 3: enabled 0
1782 14:47:59.069892 USB2 port 4: enabled 1
1783 14:47:59.073155 USB2 port 5: enabled 0
1784 14:47:59.076376 USB2 port 6: enabled 0
1785 14:47:59.076460 USB2 port 7: enabled 0
1786 14:47:59.079713 USB2 port 8: enabled 0
1787 14:47:59.083141 USB2 port 9: enabled 0
1788 14:47:59.083225 USB3 port 0: enabled 0
1789 14:47:59.086561 USB3 port 1: enabled 1
1790 14:47:59.089802 USB3 port 2: enabled 0
1791 14:47:59.092974 USB3 port 3: enabled 0
1792 14:47:59.093059 GENERIC: 0.0: enabled 1
1793 14:47:59.096463 GENERIC: 1.0: enabled 1
1794 14:47:59.099691 APIC: 01: enabled 1
1795 14:47:59.099775 APIC: 06: enabled 1
1796 14:47:59.103457 APIC: 02: enabled 1
1797 14:47:59.103547 APIC: 05: enabled 1
1798 14:47:59.106290 APIC: 04: enabled 1
1799 14:47:59.109570 APIC: 07: enabled 1
1800 14:47:59.109654 APIC: 03: enabled 1
1801 14:47:59.112930 PCI: 01:00.0: enabled 1
1802 14:47:59.120034 BS: BS_DEV_INIT run times (exec / console): 31 / 540 ms
1803 14:47:59.122838 FMAP: area RW_ELOG found @ f30000 (4096 bytes)
1804 14:47:59.126087 ELOG: NV offset 0xf30000 size 0x1000
1805 14:47:59.134013 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1806 14:47:59.140734 ELOG: Event(17) added with size 13 at 2022-09-30 14:37:34 UTC
1807 14:47:59.147364 ELOG: Event(92) added with size 9 at 2022-09-30 14:37:34 UTC
1808 14:47:59.154002 ELOG: Event(93) added with size 9 at 2022-09-30 14:37:34 UTC
1809 14:47:59.160570 ELOG: Event(9E) added with size 10 at 2022-09-30 14:37:34 UTC
1810 14:47:59.167382 ELOG: Event(9F) added with size 14 at 2022-09-30 14:37:34 UTC
1811 14:47:59.173880 BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms
1812 14:47:59.177350 ELOG: Event(A1) added with size 10 at 2022-09-30 14:37:34 UTC
1813 14:47:59.184032 elog_add_boot_reason: Logged recovery mode boot, reason: 0x1b
1814 14:47:59.190579 BS: BS_POST_DEVICE entry times (exec / console): 0 / 12 ms
1815 14:47:59.193895 Finalize devices...
1816 14:47:59.193982 Devices finalized
1817 14:47:59.200555 BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
1818 14:47:59.206850 FMAP: area RW_NVRAM found @ f37000 (24576 bytes)
1819 14:47:59.210046 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
1820 14:47:59.216663 ME: HFSTS1 : 0x80030055
1821 14:47:59.219950 ME: HFSTS2 : 0x30280116
1822 14:47:59.223323 ME: HFSTS3 : 0x00000050
1823 14:47:59.229922 ME: HFSTS4 : 0x00004000
1824 14:47:59.233186 ME: HFSTS5 : 0x00000000
1825 14:47:59.240041 ME: HFSTS6 : 0x00400006
1826 14:47:59.243255 ME: Manufacturing Mode : YES
1827 14:47:59.246803 ME: SPI Protection Mode Enabled : NO
1828 14:47:59.249803 ME: FW Partition Table : OK
1829 14:47:59.253420 ME: Bringup Loader Failure : NO
1830 14:47:59.256166 ME: Firmware Init Complete : NO
1831 14:47:59.259701 ME: Boot Options Present : NO
1832 14:47:59.263052 ME: Update In Progress : NO
1833 14:47:59.269618 ME: D0i3 Support : YES
1834 14:47:59.272655 ME: Low Power State Enabled : NO
1835 14:47:59.275993 ME: CPU Replaced : YES
1836 14:47:59.279870 ME: CPU Replacement Valid : YES
1837 14:47:59.282654 ME: Current Working State : 5
1838 14:47:59.285995 ME: Current Operation State : 1
1839 14:47:59.289665 ME: Current Operation Mode : 3
1840 14:47:59.293029 ME: Error Code : 0
1841 14:47:59.296010 ME: Enhanced Debug Mode : NO
1842 14:47:59.302942 ME: CPU Debug Disabled : YES
1843 14:47:59.305872 ME: TXT Support : NO
1844 14:47:59.312540 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 94 ms
1845 14:47:59.319035 CBFS: Found 'fallback/dsdt.aml' @0x72f80 size 0x5a67 in mcache @0x76c4c1c4
1846 14:47:59.322382 CBFS: 'fallback/slic' not found.
1847 14:47:59.325628 ACPI: Writing ACPI tables at 76b01000.
1848 14:47:59.329366 ACPI: * FACS
1849 14:47:59.329451 ACPI: * DSDT
1850 14:47:59.332709 Ramoops buffer: 0x100000@0x76a00000.
1851 14:47:59.338888 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
1852 14:47:59.342047 FMAP: area RW_VPD found @ f35000 (8192 bytes)
1853 14:47:59.345979 Google Chrome EC: version:
1854 14:47:59.349286 ro: voema_v2.0.7540-147f8d37d1
1855 14:47:59.352700 rw: voema_v2.0.7540-147f8d37d1
1856 14:47:59.356018 running image: 2
1857 14:47:59.362521 PCI space above 4GB MMIO is at 0x280400000, len = 0x7d7fc00000
1858 14:47:59.366042 ACPI: * FADT
1859 14:47:59.366125 SCI is IRQ9
1860 14:47:59.372526 ACPI: added table 1/32, length now 40
1861 14:47:59.372611 ACPI: * SSDT
1862 14:47:59.375712 Found 1 CPU(s) with 8 core(s) each.
1863 14:47:59.382334 \_SB.PCI0.PMC: Intel Tigerlake at PCI: 00:1f.2
1864 14:47:59.385863 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
1865 14:47:59.388687 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
1866 14:47:59.392049 \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
1867 14:47:59.398690 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
1868 14:47:59.405234 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
1869 14:47:59.408588 \_SB.PCI0.I2C1.H010: ELAN Touchscreen at I2C: 00:10
1870 14:47:59.415265 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
1871 14:47:59.421960 \_SB.PCI0.RP09: Enable RTD3 for PCI: 00:1d.0 (Intel PCIe Runtime D3)
1872 14:47:59.424917 \_SB.PCI0.RP09: Added StorageD3Enable property
1873 14:47:59.431999 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1874 14:47:59.435222 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
1875 14:47:59.442007 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
1876 14:47:59.445245 PS2K: Passing 80 keymaps to kernel
1877 14:47:59.451634 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
1878 14:47:59.458439 \_SB.PCI0.TXHC.RHUB.SS02: USB3 Type-C Port C1 (DB) at USB3 port 1
1879 14:47:59.465149 \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-A Port A1 (DB) at USB2 port 1
1880 14:47:59.471630 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
1881 14:47:59.478238 \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-C Port C0 (MLB) at USB2 port 4
1882 14:47:59.484809 \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Port A1 (DB) at USB3 port 1
1883 14:47:59.491328 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
1884 14:47:59.498304 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
1885 14:47:59.501403 ACPI: added table 2/32, length now 44
1886 14:47:59.504674 ACPI: * MCFG
1887 14:47:59.508029 ACPI: added table 3/32, length now 48
1888 14:47:59.508112 ACPI: * TPM2
1889 14:47:59.511113 TPM2 log created at 0x769f0000
1890 14:47:59.514529 ACPI: added table 4/32, length now 52
1891 14:47:59.517820 ACPI: * MADT
1892 14:47:59.517903 SCI is IRQ9
1893 14:47:59.521023 ACPI: added table 5/32, length now 56
1894 14:47:59.524368 current = 76b09850
1895 14:47:59.524445 ACPI: * DMAR
1896 14:47:59.531096 ACPI: added table 6/32, length now 60
1897 14:47:59.534613 ACPI: added table 7/32, length now 64
1898 14:47:59.534699 ACPI: * HPET
1899 14:47:59.537940 ACPI: added table 8/32, length now 68
1900 14:47:59.540851 ACPI: done.
1901 14:47:59.544188 ACPI tables: 35216 bytes.
1902 14:47:59.547636 smbios_write_tables: 769ef000
1903 14:47:59.550838 EC returned error result code 3
1904 14:47:59.554009 Couldn't obtain OEM name from CBI
1905 14:47:59.554089 Create SMBIOS type 16
1906 14:47:59.557487 Create SMBIOS type 17
1907 14:47:59.560857 GENERIC: 0.0 (WIFI Device)
1908 14:47:59.564038 SMBIOS tables: 1750 bytes.
1909 14:47:59.567672 Writing table forward entry at 0x00000500
1910 14:47:59.573893 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 392c
1911 14:47:59.577724 Writing coreboot table at 0x76b25000
1912 14:47:59.583896 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1913 14:47:59.587581 1. 0000000000001000-000000000009ffff: RAM
1914 14:47:59.594230 2. 00000000000a0000-00000000000fffff: RESERVED
1915 14:47:59.596981 3. 0000000000100000-00000000769eefff: RAM
1916 14:47:59.604057 4. 00000000769ef000-0000000076b97fff: CONFIGURATION TABLES
1917 14:47:59.607215 5. 0000000076b98000-0000000076c09fff: RAMSTAGE
1918 14:47:59.613644 6. 0000000076c0a000-0000000076ffffff: CONFIGURATION TABLES
1919 14:47:59.617238 7. 0000000077000000-000000007fbfffff: RESERVED
1920 14:47:59.623644 8. 00000000c0000000-00000000cfffffff: RESERVED
1921 14:47:59.626964 9. 00000000f8000000-00000000f9ffffff: RESERVED
1922 14:47:59.633670 10. 00000000fb000000-00000000fb000fff: RESERVED
1923 14:47:59.636927 11. 00000000fe000000-00000000fe00ffff: RESERVED
1924 14:47:59.643585 12. 00000000fed80000-00000000fed87fff: RESERVED
1925 14:47:59.647036 13. 00000000fed90000-00000000fed92fff: RESERVED
1926 14:47:59.653289 14. 00000000feda0000-00000000feda1fff: RESERVED
1927 14:47:59.656949 15. 00000000fedc0000-00000000feddffff: RESERVED
1928 14:47:59.659923 16. 0000000100000000-00000002803fffff: RAM
1929 14:47:59.663550 Passing 4 GPIOs to payload:
1930 14:47:59.670242 NAME | PORT | POLARITY | VALUE
1931 14:47:59.673785 lid | undefined | high | high
1932 14:47:59.679750 power | undefined | high | low
1933 14:47:59.686517 oprom | undefined | high | low
1934 14:47:59.689769 EC in RW | 0x000000e5 | high | high
1935 14:47:59.696735 Wrote coreboot table at: 0x76b25000, 0x610 bytes, checksum f6c6
1936 14:47:59.699950 coreboot table: 1576 bytes.
1937 14:47:59.703375 IMD ROOT 0. 0x76fff000 0x00001000
1938 14:47:59.706713 IMD SMALL 1. 0x76ffe000 0x00001000
1939 14:47:59.709564 FSP MEMORY 2. 0x76c4e000 0x003b0000
1940 14:47:59.712663 VPD 3. 0x76c4d000 0x00000367
1941 14:47:59.719251 RO MCACHE 4. 0x76c4c000 0x00000fdc
1942 14:47:59.722766 CONSOLE 5. 0x76c2c000 0x00020000
1943 14:47:59.726145 FMAP 6. 0x76c2b000 0x00000578
1944 14:47:59.729639 TIME STAMP 7. 0x76c2a000 0x00000910
1945 14:47:59.732522 VBOOT WORK 8. 0x76c16000 0x00014000
1946 14:47:59.735844 ROMSTG STCK 9. 0x76c15000 0x00001000
1947 14:47:59.739000 AFTER CAR 10. 0x76c0a000 0x0000b000
1948 14:47:59.742394 RAMSTAGE 11. 0x76b97000 0x00073000
1949 14:47:59.749285 REFCODE 12. 0x76b42000 0x00055000
1950 14:47:59.752568 SMM BACKUP 13. 0x76b32000 0x00010000
1951 14:47:59.755478 4f444749 14. 0x76b30000 0x00002000
1952 14:47:59.759294 EXT VBT15. 0x76b2d000 0x0000219f
1953 14:47:59.762349 COREBOOT 16. 0x76b25000 0x00008000
1954 14:47:59.765612 ACPI 17. 0x76b01000 0x00024000
1955 14:47:59.769059 ACPI GNVS 18. 0x76b00000 0x00001000
1956 14:47:59.772365 RAMOOPS 19. 0x76a00000 0x00100000
1957 14:47:59.778566 TPM2 TCGLOG20. 0x769f0000 0x00010000
1958 14:47:59.781952 SMBIOS 21. 0x769ef000 0x00000800
1959 14:47:59.782036 IMD small region:
1960 14:47:59.785187 IMD ROOT 0. 0x76ffec00 0x00000400
1961 14:47:59.792154 FSP RUNTIME 1. 0x76ffebe0 0x00000004
1962 14:47:59.795559 POWER STATE 2. 0x76ffeb80 0x00000044
1963 14:47:59.798705 ROMSTAGE 3. 0x76ffeb60 0x00000004
1964 14:47:59.802084 MEM INFO 4. 0x76ffe980 0x000001e0
1965 14:47:59.808300 BS: BS_WRITE_TABLES run times (exec / console): 7 / 484 ms
1966 14:47:59.811685 MTRR: Physical address space:
1967 14:47:59.818751 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1968 14:47:59.825424 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1969 14:47:59.831707 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
1970 14:47:59.835182 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
1971 14:47:59.841873 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
1972 14:47:59.848612 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
1973 14:47:59.854855 0x0000000100000000 - 0x0000000280400000 size 0x180400000 type 6
1974 14:47:59.858193 MTRR: Fixed MSR 0x250 0x0606060606060606
1975 14:47:59.864978 MTRR: Fixed MSR 0x258 0x0606060606060606
1976 14:47:59.868320 MTRR: Fixed MSR 0x259 0x0000000000000000
1977 14:47:59.871702 MTRR: Fixed MSR 0x268 0x0606060606060606
1978 14:47:59.874961 MTRR: Fixed MSR 0x269 0x0606060606060606
1979 14:47:59.878236 MTRR: Fixed MSR 0x26a 0x0606060606060606
1980 14:47:59.884622 MTRR: Fixed MSR 0x26b 0x0606060606060606
1981 14:47:59.888070 MTRR: Fixed MSR 0x26c 0x0606060606060606
1982 14:47:59.891346 MTRR: Fixed MSR 0x26d 0x0606060606060606
1983 14:47:59.894722 MTRR: Fixed MSR 0x26e 0x0606060606060606
1984 14:47:59.901284 MTRR: Fixed MSR 0x26f 0x0606060606060606
1985 14:47:59.904731 call enable_fixed_mtrr()
1986 14:47:59.908114 CPU physical address size: 39 bits
1987 14:47:59.911535 MTRR: default type WB/UC MTRR counts: 6/6.
1988 14:47:59.914882 MTRR: UC selected as default type.
1989 14:47:59.921290 MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
1990 14:47:59.927575 MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
1991 14:47:59.934315 MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
1992 14:47:59.941289 MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
1993 14:47:59.947877 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
1994 14:47:59.954307 MTRR: 5 base 0x0000000200000000 mask 0x0000007f00000000 type 6
1995 14:47:59.957760 MTRR: Fixed MSR 0x250 0x0606060606060606
1996 14:47:59.961049 MTRR: Fixed MSR 0x258 0x0606060606060606
1997 14:47:59.967541 MTRR: Fixed MSR 0x259 0x0000000000000000
1998 14:47:59.971245 MTRR: Fixed MSR 0x268 0x0606060606060606
1999 14:47:59.973999 MTRR: Fixed MSR 0x269 0x0606060606060606
2000 14:47:59.977415 MTRR: Fixed MSR 0x26a 0x0606060606060606
2001 14:47:59.984171 MTRR: Fixed MSR 0x26b 0x0606060606060606
2002 14:47:59.987532 MTRR: Fixed MSR 0x26c 0x0606060606060606
2003 14:47:59.990856 MTRR: Fixed MSR 0x26d 0x0606060606060606
2004 14:47:59.993828 MTRR: Fixed MSR 0x26e 0x0606060606060606
2005 14:48:00.000806 MTRR: Fixed MSR 0x26f 0x0606060606060606
2006 14:48:00.000890
2007 14:48:00.000957 MTRR check
2008 14:48:00.003746 call enable_fixed_mtrr()
2009 14:48:00.007296 Fixed MTRRs : Enabled
2010 14:48:00.010489 Variable MTRRs: Enabled
2011 14:48:00.010573
2012 14:48:00.013753 CPU physical address size: 39 bits
2013 14:48:00.020544 BS: BS_WRITE_TABLES exit times (exec / console): 50 / 151 ms
2014 14:48:00.023847 MTRR: Fixed MSR 0x250 0x0606060606060606
2015 14:48:00.026995 MTRR: Fixed MSR 0x250 0x0606060606060606
2016 14:48:00.033316 MTRR: Fixed MSR 0x258 0x0606060606060606
2017 14:48:00.036770 MTRR: Fixed MSR 0x259 0x0000000000000000
2018 14:48:00.040393 MTRR: Fixed MSR 0x268 0x0606060606060606
2019 14:48:00.043713 MTRR: Fixed MSR 0x269 0x0606060606060606
2020 14:48:00.050318 MTRR: Fixed MSR 0x26a 0x0606060606060606
2021 14:48:00.053189 MTRR: Fixed MSR 0x26b 0x0606060606060606
2022 14:48:00.056512 MTRR: Fixed MSR 0x26c 0x0606060606060606
2023 14:48:00.059858 MTRR: Fixed MSR 0x26d 0x0606060606060606
2024 14:48:00.066699 MTRR: Fixed MSR 0x26e 0x0606060606060606
2025 14:48:00.069989 MTRR: Fixed MSR 0x26f 0x0606060606060606
2026 14:48:00.073452 MTRR: Fixed MSR 0x258 0x0606060606060606
2027 14:48:00.076869 call enable_fixed_mtrr()
2028 14:48:00.080332 MTRR: Fixed MSR 0x259 0x0000000000000000
2029 14:48:00.086425 MTRR: Fixed MSR 0x268 0x0606060606060606
2030 14:48:00.089838 MTRR: Fixed MSR 0x269 0x0606060606060606
2031 14:48:00.093062 MTRR: Fixed MSR 0x26a 0x0606060606060606
2032 14:48:00.096391 MTRR: Fixed MSR 0x26b 0x0606060606060606
2033 14:48:00.102970 MTRR: Fixed MSR 0x26c 0x0606060606060606
2034 14:48:00.106332 MTRR: Fixed MSR 0x26d 0x0606060606060606
2035 14:48:00.109686 MTRR: Fixed MSR 0x26e 0x0606060606060606
2036 14:48:00.113009 MTRR: Fixed MSR 0x26f 0x0606060606060606
2037 14:48:00.119764 CPU physical address size: 39 bits
2038 14:48:00.123095 call enable_fixed_mtrr()
2039 14:48:00.126400 MTRR: Fixed MSR 0x250 0x0606060606060606
2040 14:48:00.129617 MTRR: Fixed MSR 0x250 0x0606060606060606
2041 14:48:00.133090 MTRR: Fixed MSR 0x258 0x0606060606060606
2042 14:48:00.139811 MTRR: Fixed MSR 0x259 0x0000000000000000
2043 14:48:00.142662 MTRR: Fixed MSR 0x268 0x0606060606060606
2044 14:48:00.146488 MTRR: Fixed MSR 0x269 0x0606060606060606
2045 14:48:00.149690 MTRR: Fixed MSR 0x26a 0x0606060606060606
2046 14:48:00.156037 MTRR: Fixed MSR 0x26b 0x0606060606060606
2047 14:48:00.159422 MTRR: Fixed MSR 0x26c 0x0606060606060606
2048 14:48:00.162450 MTRR: Fixed MSR 0x26d 0x0606060606060606
2049 14:48:00.165754 MTRR: Fixed MSR 0x26e 0x0606060606060606
2050 14:48:00.172452 MTRR: Fixed MSR 0x26f 0x0606060606060606
2051 14:48:00.175724 MTRR: Fixed MSR 0x258 0x0606060606060606
2052 14:48:00.179165 call enable_fixed_mtrr()
2053 14:48:00.182657 MTRR: Fixed MSR 0x259 0x0000000000000000
2054 14:48:00.185867 MTRR: Fixed MSR 0x268 0x0606060606060606
2055 14:48:00.192043 MTRR: Fixed MSR 0x269 0x0606060606060606
2056 14:48:00.195500 MTRR: Fixed MSR 0x26a 0x0606060606060606
2057 14:48:00.198753 MTRR: Fixed MSR 0x26b 0x0606060606060606
2058 14:48:00.202204 MTRR: Fixed MSR 0x26c 0x0606060606060606
2059 14:48:00.208194 MTRR: Fixed MSR 0x26d 0x0606060606060606
2060 14:48:00.211682 MTRR: Fixed MSR 0x26e 0x0606060606060606
2061 14:48:00.215236 MTRR: Fixed MSR 0x26f 0x0606060606060606
2062 14:48:00.218441 CPU physical address size: 39 bits
2063 14:48:00.225309 call enable_fixed_mtrr()
2064 14:48:00.228398 MTRR: Fixed MSR 0x250 0x0606060606060606
2065 14:48:00.231664 MTRR: Fixed MSR 0x250 0x0606060606060606
2066 14:48:00.235033 MTRR: Fixed MSR 0x258 0x0606060606060606
2067 14:48:00.241318 MTRR: Fixed MSR 0x259 0x0000000000000000
2068 14:48:00.244689 MTRR: Fixed MSR 0x268 0x0606060606060606
2069 14:48:00.247933 MTRR: Fixed MSR 0x269 0x0606060606060606
2070 14:48:00.251248 MTRR: Fixed MSR 0x26a 0x0606060606060606
2071 14:48:00.257644 MTRR: Fixed MSR 0x26b 0x0606060606060606
2072 14:48:00.261144 MTRR: Fixed MSR 0x26c 0x0606060606060606
2073 14:48:00.264494 MTRR: Fixed MSR 0x26d 0x0606060606060606
2074 14:48:00.267837 MTRR: Fixed MSR 0x26e 0x0606060606060606
2075 14:48:00.274135 MTRR: Fixed MSR 0x26f 0x0606060606060606
2076 14:48:00.277342 MTRR: Fixed MSR 0x258 0x0606060606060606
2077 14:48:00.281116 call enable_fixed_mtrr()
2078 14:48:00.284201 MTRR: Fixed MSR 0x259 0x0000000000000000
2079 14:48:00.287530 MTRR: Fixed MSR 0x268 0x0606060606060606
2080 14:48:00.293578 MTRR: Fixed MSR 0x269 0x0606060606060606
2081 14:48:00.297059 MTRR: Fixed MSR 0x26a 0x0606060606060606
2082 14:48:00.300438 MTRR: Fixed MSR 0x26b 0x0606060606060606
2083 14:48:00.303826 MTRR: Fixed MSR 0x26c 0x0606060606060606
2084 14:48:00.310040 MTRR: Fixed MSR 0x26d 0x0606060606060606
2085 14:48:00.313492 MTRR: Fixed MSR 0x26e 0x0606060606060606
2086 14:48:00.316828 MTRR: Fixed MSR 0x26f 0x0606060606060606
2087 14:48:00.320798 CPU physical address size: 39 bits
2088 14:48:00.326935 call enable_fixed_mtrr()
2089 14:48:00.330370 CPU physical address size: 39 bits
2090 14:48:00.333655 CPU physical address size: 39 bits
2091 14:48:00.336705 CPU physical address size: 39 bits
2092 14:48:00.340065 Checking cr50 for pending updates
2093 14:48:00.346474 Reading cr50 TPM mode
2094 14:48:00.356994 BS: BS_PAYLOAD_LOAD entry times (exec / console): 325 / 6 ms
2095 14:48:00.366697 CBFS: Found 'fallback/payload' @0x38db00 size 0x4be9c in mcache @0x76c4cf60
2096 14:48:00.369952 Checking segment from ROM address 0xffc02b38
2097 14:48:00.373448 Checking segment from ROM address 0xffc02b54
2098 14:48:00.380263 Loading segment from ROM address 0xffc02b38
2099 14:48:00.380379 code (compression=0)
2100 14:48:00.389700 New segment dstaddr 0x30000000 memsize 0x2662db0 srcaddr 0xffc02b70 filesize 0x4be64
2101 14:48:00.399732 Loading Segment: addr: 0x30000000 memsz: 0x0000000002662db0 filesz: 0x000000000004be64
2102 14:48:00.399915 it's not compressed!
2103 14:48:00.539263 [ 0x30000000, 3004be64, 0x32662db0) <- ffc02b70
2104 14:48:00.545599 Clearing Segment: addr: 0x000000003004be64 memsz: 0x0000000002616f4c
2105 14:48:00.552517 Loading segment from ROM address 0xffc02b54
2106 14:48:00.556150 Entry Point 0x30000000
2107 14:48:00.556235 Loaded segments
2108 14:48:00.562257 BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 63 ms
2109 14:48:00.605375 Finalizing chipset.
2110 14:48:00.608608 Finalizing SMM.
2111 14:48:00.608694 APMC done.
2112 14:48:00.615283 BS: BS_PAYLOAD_LOAD exit times (exec / console): 42 / 5 ms
2113 14:48:00.618720 mp_park_aps done after 0 msecs.
2114 14:48:00.622042 Jumping to boot code at 0x30000000(0x76b25000)
2115 14:48:00.632022 CPU0: stack: 0x76bee000 - 0x76bef000, lowest used address 0x76beea78, stack used: 1416 bytes
2116 14:48:00.632109
2117 14:48:00.635277 Starting depthcharge on Voema...
2118 14:48:00.635651 end: 2.2.3 depthcharge-start (duration 00:00:16) [common]
2119 14:48:00.635758 start: 2.2.4 bootloader-commands (timeout 00:04:44) [common]
2120 14:48:00.635845 Setting prompt string to ['volteer:']
2121 14:48:00.635925 bootloader-commands: Wait for prompt ['volteer:'] (timeout 00:04:44)
2122 14:48:00.644944 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2123 14:48:00.651802 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2124 14:48:00.657816 Looking for NVMe Controller 0x3005f220 @ 00:1d:00
2125 14:48:00.661175 Failed to find eMMC card reader
2126 14:48:00.664660 Wipe memory regions:
2127 14:48:00.668357 [0x00000000001000, 0x000000000a0000)
2128 14:48:00.671680 [0x00000000100000, 0x00000030000000)
2129 14:48:00.700668 [0x00000032662db0, 0x000000769ef000)
2130 14:48:00.739597 [0x00000100000000, 0x00000280400000)
2131 14:48:00.943770 ec_init: CrosEC protocol v3 supported (256, 256)
2132 14:48:00.950056 update_port_state: port C0 state: usb enable 1 mux conn 0
2133 14:48:00.956760 update_port_state: port C0 req: usage 0 usb3 1 usb2 9 ufp 1 ori_hsl 0 ori_sbu 0 dbg_acc 1
2134 14:48:00.965251 pmc_check_ipc_sts: STS_BUSY done after 1662 us
2135 14:48:00.967804 send_conn_disc_msg: pmc_send_cmd succeeded
2136 14:48:01.399611 R8152: Initializing
2137 14:48:01.402521 Version 6 (ocp_data = 5c30)
2138 14:48:01.405713 R8152: Done initializing
2139 14:48:01.409028 Adding net device
2140 14:48:01.714772 [firmware-volteer-13672.B-collabora] Oct 22 2021 06:32:35
2141 14:48:01.714906
2142 14:48:01.718276 Setting prompt string to ['volteer:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2144 14:48:01.819008 volteer: tftpboot 192.168.201.1 7462823/tftp-deploy-3ksw9d6m/kernel/bzImage 7462823/tftp-deploy-3ksw9d6m/kernel/cmdline 7462823/tftp-deploy-3ksw9d6m/ramdisk/ramdisk.cpio.gz
2145 14:48:01.819129 Setting prompt string to 'Starting kernel'
2146 14:48:01.819284 Setting prompt string to ['Starting kernel']
2147 14:48:01.819355 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2148 14:48:01.819430 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:42)
2149 14:48:01.824032 tftpboot 192.168.201.1 7462823/tftp-deploy-3ksw9d6m/kernel/bzImoy-3ksw9d6m/kernel/cmdline 7462823/tftp-deploy-3ksw9d6m/ramdisk/ramdisk.cpio.gz
2150 14:48:01.824123 Waiting for link
2151 14:48:02.026491 done.
2152 14:48:02.026622 MAC: 00:24:32:30:7b:ec
2153 14:48:02.029686 Sending DHCP discover... done.
2154 14:48:02.032983 Waiting for reply... done.
2155 14:48:02.036493 Sending DHCP request... done.
2156 14:48:02.039640 Waiting for reply... done.
2157 14:48:02.043137 My ip is 192.168.201.11
2158 14:48:02.046387 The DHCP server ip is 192.168.201.1
2159 14:48:02.053196 TFTP server IP predefined by user: 192.168.201.1
2160 14:48:02.059554 Bootfile predefined by user: 7462823/tftp-deploy-3ksw9d6m/kernel/bzImage
2161 14:48:02.062658 Sending tftp read request... done.
2162 14:48:02.065918 Waiting for the transfer...
2163 14:48:02.694576 00000000 ################################################################
2164 14:48:03.337062 00080000 ################################################################
2165 14:48:03.902685 00100000 ################################################################
2166 14:48:04.469580 00180000 ################################################################
2167 14:48:05.021025 00200000 ################################################################
2168 14:48:05.576410 00280000 ################################################################
2169 14:48:06.119472 00300000 ################################################################
2170 14:48:06.679656 00380000 ################################################################
2171 14:48:07.244004 00400000 ################################################################
2172 14:48:07.799986 00480000 ################################################################
2173 14:48:08.367257 00500000 ################################################################
2174 14:48:08.928493 00580000 ################################################################
2175 14:48:09.522744 00600000 ################################################################
2176 14:48:09.919418 00680000 ###################################### done.
2177 14:48:09.922657 The bootfile was 7126928 bytes long.
2178 14:48:09.925532 Sending tftp read request... done.
2179 14:48:09.928702 Waiting for the transfer...
2180 14:48:10.613987 00000000 ################################################################
2181 14:48:11.273108 00080000 ################################################################
2182 14:48:11.855752 00100000 ################################################################
2183 14:48:12.448690 00180000 ################################################################
2184 14:48:13.019480 00200000 ################################################################
2185 14:48:13.589620 00280000 ################################################################
2186 14:48:14.195852 00300000 ################################################################
2187 14:48:14.817366 00380000 ################################################################
2188 14:48:15.403840 00400000 ################################################################
2189 14:48:16.017059 00480000 ################################################################
2190 14:48:16.386929 00500000 ################################ done.
2191 14:48:16.390303 Sending tftp read request... done.
2192 14:48:16.393180 Waiting for the transfer...
2193 14:48:16.393609 00000000 # done.
2194 14:48:16.402951 Command line loaded dynamically from TFTP file: 7462823/tftp-deploy-3ksw9d6m/kernel/cmdline
2195 14:48:16.422459 The command line is: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/7462823/extract-nfsrootfs-mzugkky2,tcp,hard ip=dhcp tftpserverip=192.168.201.1
2196 14:48:16.430535 Shutting down all USB controllers.
2197 14:48:16.431108 Removing current net device
2198 14:48:16.433797 Finalizing coreboot
2199 14:48:16.439780 Exiting depthcharge with code 4 at timestamp: 24444603
2200 14:48:16.440325
2201 14:48:16.440771 Starting kernel ...
2202 14:48:16.441133
2203 14:48:16.441480
2204 14:48:16.442731 end: 2.2.4 bootloader-commands (duration 00:00:16) [common]
2205 14:48:16.443271 start: 2.2.5 auto-login-action (timeout 00:04:28) [common]
2206 14:48:16.443717 Setting prompt string to ['Linux version [0-9]']
2207 14:48:16.444166 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2208 14:48:16.444565 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2210 14:52:44.444301 end: 2.2.5 auto-login-action (duration 00:04:28) [common]
2212 14:52:44.445414 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 268 seconds'
2214 14:52:44.446316 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2217 14:52:44.447884 end: 2 depthcharge-action (duration 00:05:00) [common]
2219 14:52:44.448981 Cleaning after the job
2220 14:52:44.449166 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/7462823/tftp-deploy-3ksw9d6m/ramdisk
2221 14:52:44.449638 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/7462823/tftp-deploy-3ksw9d6m/kernel
2222 14:52:44.450206 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/7462823/tftp-deploy-3ksw9d6m/nfsrootfs
2223 14:52:44.481145 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/7462823/tftp-deploy-3ksw9d6m/modules
2224 14:52:44.481453 start: 5.1 power-off (timeout 00:00:30) [common]
2225 14:52:44.481617 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-0' '--port=1' '--command=off'
2226 14:52:44.500674 >> Command sent successfully.
2227 14:52:44.502616 Returned 0 in 0 seconds
2228 14:52:44.603794 end: 5.1 power-off (duration 00:00:00) [common]
2230 14:52:44.605361 start: 5.2 read-feedback (timeout 00:10:00) [common]
2231 14:52:44.606762 Listened to connection for namespace 'common' for up to 1s
2232 14:52:45.611276 Finalising connection for namespace 'common'
2233 14:52:45.612101 Disconnecting from shell: Finalise
2234 14:52:45.713692 end: 5.2 read-feedback (duration 00:00:01) [common]
2235 14:52:45.714370 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/7462823
2236 14:52:45.806882 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/7462823
2237 14:52:45.807077 JobError: Your job cannot terminate cleanly.