Boot log: asus-cx9400-volteer
- Errors: 2
- Boot result: FAIL
- Kernel Errors: 0
- Warnings: 0
- Kernel Warnings: 0
1 12:44:09.480077 lava-dispatcher, installed at version: 2023.01
2 12:44:09.480272 start: 0 validate
3 12:44:09.480401 Start time: 2023-03-22 12:44:09.480394+00:00 (UTC)
4 12:44:09.480532 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:44:09.480655 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230317.0%2Famd64%2Finitrd.cpio.gz exists
6 12:44:09.785422 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:44:09.785597 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv5.10.175-cip29-rt12%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 12:44:22.580570 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:44:22.581263 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230317.0%2Famd64%2Ffull.rootfs.tar.xz exists
10 12:44:22.862674 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:44:22.863387 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv5.10.175-cip29-rt12%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:44:23.867317 validate duration: 14.39
14 12:44:23.867625 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:44:23.867784 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:44:23.867883 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:44:23.868026 Not decompressing ramdisk as can be used compressed.
18 12:44:23.868116 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230317.0/amd64/initrd.cpio.gz
19 12:44:23.868185 saving as /var/lib/lava/dispatcher/tmp/9729709/tftp-deploy-thsn03kf/ramdisk/initrd.cpio.gz
20 12:44:23.868249 total size: 5432123 (5MB)
21 12:44:24.152175 progress 0% (0MB)
22 12:44:24.154743 progress 5% (0MB)
23 12:44:24.156979 progress 10% (0MB)
24 12:44:24.159295 progress 15% (0MB)
25 12:44:24.161732 progress 20% (1MB)
26 12:44:24.164031 progress 25% (1MB)
27 12:44:24.166266 progress 30% (1MB)
28 12:44:24.168789 progress 35% (1MB)
29 12:44:24.171005 progress 40% (2MB)
30 12:44:24.173145 progress 45% (2MB)
31 12:44:24.175330 progress 50% (2MB)
32 12:44:24.177794 progress 55% (2MB)
33 12:44:24.179991 progress 60% (3MB)
34 12:44:24.182224 progress 65% (3MB)
35 12:44:24.184614 progress 70% (3MB)
36 12:44:24.186820 progress 75% (3MB)
37 12:44:24.189019 progress 80% (4MB)
38 12:44:24.191217 progress 85% (4MB)
39 12:44:24.193701 progress 90% (4MB)
40 12:44:24.195895 progress 95% (4MB)
41 12:44:24.198193 progress 100% (5MB)
42 12:44:24.198525 5MB downloaded in 0.33s (15.69MB/s)
43 12:44:24.198751 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:44:24.199188 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:44:24.199356 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:44:24.199558 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:44:24.199743 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v5.10.175-cip29-rt12/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
49 12:44:24.199909 saving as /var/lib/lava/dispatcher/tmp/9729709/tftp-deploy-thsn03kf/kernel/bzImage
50 12:44:24.200013 total size: 11646080 (11MB)
51 12:44:24.200115 No compression specified
52 12:44:24.201266 progress 0% (0MB)
53 12:44:24.205902 progress 5% (0MB)
54 12:44:24.210888 progress 10% (1MB)
55 12:44:24.215777 progress 15% (1MB)
56 12:44:24.220662 progress 20% (2MB)
57 12:44:24.225432 progress 25% (2MB)
58 12:44:24.230717 progress 30% (3MB)
59 12:44:24.235890 progress 35% (3MB)
60 12:44:24.241095 progress 40% (4MB)
61 12:44:24.246041 progress 45% (5MB)
62 12:44:24.251266 progress 50% (5MB)
63 12:44:24.256387 progress 55% (6MB)
64 12:44:24.261379 progress 60% (6MB)
65 12:44:24.266353 progress 65% (7MB)
66 12:44:24.270940 progress 70% (7MB)
67 12:44:24.275790 progress 75% (8MB)
68 12:44:24.280887 progress 80% (8MB)
69 12:44:24.285816 progress 85% (9MB)
70 12:44:24.290488 progress 90% (10MB)
71 12:44:24.295409 progress 95% (10MB)
72 12:44:24.300523 progress 100% (11MB)
73 12:44:24.300888 11MB downloaded in 0.10s (110.11MB/s)
74 12:44:24.301134 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:44:24.301555 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:44:24.301695 start: 1.3 download-retry (timeout 00:10:00) [common]
78 12:44:24.301847 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 12:44:24.302001 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230317.0/amd64/full.rootfs.tar.xz
80 12:44:24.302129 saving as /var/lib/lava/dispatcher/tmp/9729709/tftp-deploy-thsn03kf/nfsrootfs/full.rootfs.tar
81 12:44:24.302229 total size: 133351768 (127MB)
82 12:44:24.302328 Using unxz to decompress xz
83 12:44:24.306314 progress 0% (0MB)
84 12:44:24.676869 progress 5% (6MB)
85 12:44:25.059992 progress 10% (12MB)
86 12:44:25.362767 progress 15% (19MB)
87 12:44:25.588966 progress 20% (25MB)
88 12:44:25.858494 progress 25% (31MB)
89 12:44:26.214705 progress 30% (38MB)
90 12:44:26.576490 progress 35% (44MB)
91 12:44:26.986122 progress 40% (50MB)
92 12:44:27.380894 progress 45% (57MB)
93 12:44:27.749159 progress 50% (63MB)
94 12:44:28.137675 progress 55% (69MB)
95 12:44:28.515790 progress 60% (76MB)
96 12:44:28.903348 progress 65% (82MB)
97 12:44:29.287294 progress 70% (89MB)
98 12:44:29.663436 progress 75% (95MB)
99 12:44:30.113289 progress 80% (101MB)
100 12:44:30.576743 progress 85% (108MB)
101 12:44:30.858366 progress 90% (114MB)
102 12:44:31.230281 progress 95% (120MB)
103 12:44:31.655154 progress 100% (127MB)
104 12:44:31.661170 127MB downloaded in 7.36s (17.28MB/s)
105 12:44:31.661474 end: 1.3.1 http-download (duration 00:00:07) [common]
107 12:44:31.661754 end: 1.3 download-retry (duration 00:00:07) [common]
108 12:44:31.661853 start: 1.4 download-retry (timeout 00:09:52) [common]
109 12:44:31.661967 start: 1.4.1 http-download (timeout 00:09:52) [common]
110 12:44:31.662102 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v5.10.175-cip29-rt12/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
111 12:44:31.662179 saving as /var/lib/lava/dispatcher/tmp/9729709/tftp-deploy-thsn03kf/modules/modules.tar
112 12:44:31.662247 total size: 497788 (0MB)
113 12:44:31.662313 Using unxz to decompress xz
114 12:44:31.665514 progress 6% (0MB)
115 12:44:31.665903 progress 13% (0MB)
116 12:44:31.666162 progress 19% (0MB)
117 12:44:31.667429 progress 26% (0MB)
118 12:44:31.669456 progress 32% (0MB)
119 12:44:31.671583 progress 39% (0MB)
120 12:44:31.673539 progress 46% (0MB)
121 12:44:31.675453 progress 52% (0MB)
122 12:44:31.677756 progress 59% (0MB)
123 12:44:31.679714 progress 65% (0MB)
124 12:44:31.681749 progress 72% (0MB)
125 12:44:31.683672 progress 78% (0MB)
126 12:44:31.685600 progress 85% (0MB)
127 12:44:31.687638 progress 92% (0MB)
128 12:44:31.689560 progress 98% (0MB)
129 12:44:31.696866 0MB downloaded in 0.03s (13.72MB/s)
130 12:44:31.697167 end: 1.4.1 http-download (duration 00:00:00) [common]
132 12:44:31.697443 end: 1.4 download-retry (duration 00:00:00) [common]
133 12:44:31.697544 start: 1.5 prepare-tftp-overlay (timeout 00:09:52) [common]
134 12:44:31.697644 start: 1.5.1 extract-nfsrootfs (timeout 00:09:52) [common]
135 12:44:33.014483 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/9729709/extract-nfsrootfs-uejj9dly
136 12:44:33.014708 end: 1.5.1 extract-nfsrootfs (duration 00:00:01) [common]
137 12:44:33.014835 start: 1.5.2 lava-overlay (timeout 00:09:51) [common]
138 12:44:33.015018 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv
139 12:44:33.015124 makedir: /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin
140 12:44:33.015209 makedir: /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/tests
141 12:44:33.015290 makedir: /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/results
142 12:44:33.015387 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-add-keys
143 12:44:33.015519 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-add-sources
144 12:44:33.015633 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-background-process-start
145 12:44:33.015744 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-background-process-stop
146 12:44:33.015854 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-common-functions
147 12:44:33.015962 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-echo-ipv4
148 12:44:33.016070 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-install-packages
149 12:44:33.016178 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-installed-packages
150 12:44:33.016284 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-os-build
151 12:44:33.016390 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-probe-channel
152 12:44:33.016496 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-probe-ip
153 12:44:33.016601 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-target-ip
154 12:44:33.016706 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-target-mac
155 12:44:33.016830 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-target-storage
156 12:44:33.016940 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-test-case
157 12:44:33.017047 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-test-event
158 12:44:33.017151 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-test-feedback
159 12:44:33.017257 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-test-raise
160 12:44:33.017362 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-test-reference
161 12:44:33.017467 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-test-runner
162 12:44:33.017573 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-test-set
163 12:44:33.017678 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-test-shell
164 12:44:33.017786 Updating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-install-packages (oe)
165 12:44:33.017896 Updating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/bin/lava-installed-packages (oe)
166 12:44:33.017989 Creating /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/environment
167 12:44:33.018104 LAVA metadata
168 12:44:33.018184 - LAVA_JOB_ID=9729709
169 12:44:33.018247 - LAVA_DISPATCHER_IP=192.168.201.1
170 12:44:33.018349 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:51) [common]
171 12:44:33.018415 skipped lava-vland-overlay
172 12:44:33.018490 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
173 12:44:33.018573 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:51) [common]
174 12:44:33.018635 skipped lava-multinode-overlay
175 12:44:33.018708 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
176 12:44:33.018791 start: 1.5.2.3 test-definition (timeout 00:09:51) [common]
177 12:44:33.018910 Loading test definitions
178 12:44:33.019001 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:51) [common]
179 12:44:33.019073 Using /lava-9729709 at stage 0
180 12:44:33.019321 uuid=9729709_1.5.2.3.1 testdef=None
181 12:44:33.019410 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
182 12:44:33.019497 start: 1.5.2.3.2 test-overlay (timeout 00:09:51) [common]
183 12:44:33.019962 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
185 12:44:33.020191 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:51) [common]
186 12:44:33.020754 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
188 12:44:33.021050 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:51) [common]
189 12:44:33.021580 runner path: /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/0/tests/0_dmesg test_uuid 9729709_1.5.2.3.1
190 12:44:33.021729 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
192 12:44:33.021959 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:51) [common]
193 12:44:33.022032 Using /lava-9729709 at stage 1
194 12:44:33.022321 uuid=9729709_1.5.2.3.5 testdef=None
195 12:44:33.022409 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
196 12:44:33.022495 start: 1.5.2.3.6 test-overlay (timeout 00:09:51) [common]
197 12:44:33.022958 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
199 12:44:33.023180 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:51) [common]
200 12:44:33.023744 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
202 12:44:33.023977 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:51) [common]
203 12:44:33.024537 runner path: /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/1/tests/1_bootrr test_uuid 9729709_1.5.2.3.5
204 12:44:33.024677 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
206 12:44:33.024911 Creating lava-test-runner.conf files
207 12:44:33.024991 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/0 for stage 0
208 12:44:33.025090 - 0_dmesg
209 12:44:33.025165 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/9729709/lava-overlay-nx62mgvv/lava-9729709/1 for stage 1
210 12:44:33.025247 - 1_bootrr
211 12:44:33.025338 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
212 12:44:33.025424 start: 1.5.2.4 compress-overlay (timeout 00:09:51) [common]
213 12:44:33.031002 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
214 12:44:33.031126 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:51) [common]
215 12:44:33.031218 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
216 12:44:33.031307 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
217 12:44:33.031395 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:51) [common]
218 12:44:33.134674 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
219 12:44:33.135039 start: 1.5.4 extract-modules (timeout 00:09:51) [common]
220 12:44:33.135320 extracting modules file /var/lib/lava/dispatcher/tmp/9729709/tftp-deploy-thsn03kf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/9729709/extract-nfsrootfs-uejj9dly
221 12:44:33.148165 extracting modules file /var/lib/lava/dispatcher/tmp/9729709/tftp-deploy-thsn03kf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/9729709/extract-overlay-ramdisk-3ifvl_qt/ramdisk
222 12:44:33.160696 end: 1.5.4 extract-modules (duration 00:00:00) [common]
223 12:44:33.160853 start: 1.5.5 apply-overlay-tftp (timeout 00:09:51) [common]
224 12:44:33.160949 [common] Applying overlay to NFS
225 12:44:33.161023 [common] Applying overlay /var/lib/lava/dispatcher/tmp/9729709/compress-overlay-u6qhy1hv/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/9729709/extract-nfsrootfs-uejj9dly
226 12:44:33.165033 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
227 12:44:33.165143 start: 1.5.6 configure-preseed-file (timeout 00:09:51) [common]
228 12:44:33.165239 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
229 12:44:33.165333 start: 1.5.7 compress-ramdisk (timeout 00:09:51) [common]
230 12:44:33.165414 Building ramdisk /var/lib/lava/dispatcher/tmp/9729709/extract-overlay-ramdisk-3ifvl_qt/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/9729709/extract-overlay-ramdisk-3ifvl_qt/ramdisk
231 12:44:33.206744 >> 30091 blocks
232 12:44:33.754946 rename /var/lib/lava/dispatcher/tmp/9729709/extract-overlay-ramdisk-3ifvl_qt/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/9729709/tftp-deploy-thsn03kf/ramdisk/ramdisk.cpio.gz
233 12:44:33.755358 end: 1.5.7 compress-ramdisk (duration 00:00:01) [common]
234 12:44:33.755491 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
235 12:44:33.755592 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
236 12:44:33.755688 No mkimage arch provided, not using FIT.
237 12:44:33.755778 end: 1.5.8.1 prepare-fit (duration 00:00:00) [common]
238 12:44:33.755865 end: 1.5.8 prepare-kernel (duration 00:00:00) [common]
239 12:44:33.755968 end: 1.5 prepare-tftp-overlay (duration 00:00:02) [common]
240 12:44:33.756059 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:50) [common]
241 12:44:33.756138 No LXC device requested
242 12:44:33.756224 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
243 12:44:33.756318 start: 1.7 deploy-device-env (timeout 00:09:50) [common]
244 12:44:33.756399 end: 1.7 deploy-device-env (duration 00:00:00) [common]
245 12:44:33.756471 Checking files for TFTP limit of 4294967296 bytes.
246 12:44:33.756855 end: 1 tftp-deploy (duration 00:00:10) [common]
247 12:44:33.756962 start: 2 depthcharge-action (timeout 00:05:00) [common]
248 12:44:33.757057 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
249 12:44:33.757184 substitutions:
250 12:44:33.757254 - {DTB}: None
251 12:44:33.757320 - {INITRD}: 9729709/tftp-deploy-thsn03kf/ramdisk/ramdisk.cpio.gz
252 12:44:33.757381 - {KERNEL}: 9729709/tftp-deploy-thsn03kf/kernel/bzImage
253 12:44:33.757442 - {LAVA_MAC}: None
254 12:44:33.757501 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/9729709/extract-nfsrootfs-uejj9dly
255 12:44:33.757558 - {NFS_SERVER_IP}: 192.168.201.1
256 12:44:33.757615 - {PRESEED_CONFIG}: None
257 12:44:33.757674 - {PRESEED_LOCAL}: None
258 12:44:33.757730 - {RAMDISK}: 9729709/tftp-deploy-thsn03kf/ramdisk/ramdisk.cpio.gz
259 12:44:33.757787 - {ROOT_PART}: None
260 12:44:33.757842 - {ROOT}: None
261 12:44:33.757898 - {SERVER_IP}: 192.168.201.1
262 12:44:33.757954 - {TEE}: None
263 12:44:33.758009 Parsed boot commands:
264 12:44:33.758069 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
265 12:44:33.758251 Parsed boot commands: tftpboot 192.168.201.1 9729709/tftp-deploy-thsn03kf/kernel/bzImage 9729709/tftp-deploy-thsn03kf/kernel/cmdline 9729709/tftp-deploy-thsn03kf/ramdisk/ramdisk.cpio.gz
266 12:44:33.758345 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
267 12:44:33.758433 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
268 12:44:33.758528 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
269 12:44:33.758614 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
270 12:44:33.758683 Not connected, no need to disconnect.
271 12:44:33.758760 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
272 12:44:33.758843 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
273 12:44:33.758908 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost asus-cx9400-volteer-cbg-14'
274 12:44:33.761864 Setting prompt string to ['lava-test: # ']
275 12:44:33.762201 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
276 12:44:33.762341 end: 2.2.1 reset-connection (duration 00:00:00) [common]
277 12:44:33.762476 start: 2.2.2 reset-device (timeout 00:05:00) [common]
278 12:44:33.762605 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
279 12:44:33.762846 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-14' '--port=1' '--command=reboot'
280 12:44:38.894677 >> Command sent successfully.
281 12:44:38.896901 Returned 0 in 5 seconds
282 12:44:38.997698 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
284 12:44:38.998013 end: 2.2.2 reset-device (duration 00:00:05) [common]
285 12:44:38.998163 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
286 12:44:38.998255 Setting prompt string to 'Starting depthcharge on Voema...'
287 12:44:38.998325 Changing prompt to 'Starting depthcharge on Voema...'
288 12:44:38.998397 depthcharge-start: Wait for prompt Starting depthcharge on Voema... (timeout 00:05:00)
289 12:44:38.998664 [Enter `^Ec?' for help]
290 12:44:40.568907 ��˻1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 bootblock starting (log level: 8)...
291 12:44:40.576550 CPU: 11th Gen Intel(R) Core(TM) i7-1160G7 @ 1.20GHz
292 12:44:40.579926 CPU: ID 806c1, Tigerlake B0, ucode: 00000086
293 12:44:40.583817 CPU: AES supported, TXT NOT supported, VT supported
294 12:44:40.591729 MCH: device id 9a12 (rev 01) is Tigerlake-Y-4-2
295 12:44:40.596257 PCH: device id a087 (rev 20) is Tigerlake-Y Premium SKU
296 12:44:40.599393 IGD: device id 9a40 (rev 01) is Tigerlake Y GT2
297 12:44:40.603250 VBOOT: Loading verstage.
298 12:44:40.610741 FMAP: Found "FLASH" version 1.1 at 0x1804000.
299 12:44:40.614374 FMAP: base = 0x0 size = 0x2000000 #areas = 32
300 12:44:40.617444 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
301 12:44:40.625901 CBFS: mcache @0xfef45600 built for 70 files, used 0xfdc of 0x1800 bytes
302 12:44:40.632813 CBFS: Found 'fallback/verstage' @0x165e40 size 0x147ec in mcache @0xfef45984
303 12:44:40.637282
304 12:44:40.637367
305 12:44:40.648444 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 verstage starting (log level: 8)...
306 12:44:40.661697 Probing TPM: . done!
307 12:44:40.666006 TPM ready after 0 ms
308 12:44:40.670277 Connected to device vid:did:rid of 1ae0:0028:00
309 12:44:40.681058 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
310 12:44:40.684940 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
311 12:44:40.770564 Initialized TPM device CR50 revision 0
312 12:44:40.780027 tlcl_send_startup: Startup return code is 0
313 12:44:40.780127 TPM: setup succeeded
314 12:44:40.805239 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
315 12:44:40.814381 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
316 12:44:40.826947 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
317 12:44:40.836761 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
318 12:44:40.840680 Chrome EC: UHEPI supported
319 12:44:40.843913 Phase 1
320 12:44:40.847421 FMAP: area GBB found @ 1805000 (458752 bytes)
321 12:44:40.857227 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
322 12:44:40.863700 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
323 12:44:40.870521 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
324 12:44:40.876966 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
325 12:44:40.880092 Recovery requested (1009000e)
326 12:44:40.883571 TPM: Extending digest for VBOOT: boot mode into PCR 0
327 12:44:40.895092 tlcl_extend: response is 0
328 12:44:40.902202 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
329 12:44:40.911938 tlcl_extend: response is 0
330 12:44:40.918053 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
331 12:44:40.925033 CBFS: Found 'fallback/romstage' @0x80 size 0x1bf24 in mcache @0xfef45638
332 12:44:40.931467 BS: verstage times (exec / console): total (unknown) / 142 ms
333 12:44:40.931558
334 12:44:40.931627
335 12:44:40.944944 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 romstage starting (log level: 8)...
336 12:44:40.951667 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
337 12:44:40.954878 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
338 12:44:40.958008 gpe0_sts[0]: 00200000 gpe0_en[0]: 00000000
339 12:44:40.965187 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
340 12:44:40.968417 gpe0_sts[2]: 00001000 gpe0_en[2]: 00000000
341 12:44:40.971156 gpe0_sts[3]: 00000000 gpe0_en[3]: 00010000
342 12:44:40.974812 TCO_STS: 0000 0000
343 12:44:40.977997 GEN_PMCON: d0015038 00002200
344 12:44:40.981542 GBLRST_CAUSE: 00000000 00000000
345 12:44:40.984520 HPR_CAUSE0: 00000000
346 12:44:40.984608 prev_sleep_state 5
347 12:44:40.987632 Boot Count incremented to 5715
348 12:44:40.994558 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
349 12:44:41.001149 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
350 12:44:41.010953 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
351 12:44:41.017972 CBFS: Found 'fspm.bin' @0x78fc0 size 0xa5000 in mcache @0xfef4585c
352 12:44:41.021063 Chrome EC: UHEPI supported
353 12:44:41.027310 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
354 12:44:41.038861 Probing TPM: done!
355 12:44:41.044983 Connected to device vid:did:rid of 1ae0:0028:00
356 12:44:41.055155 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
357 12:44:41.059187 Initialized TPM device CR50 revision 0
358 12:44:41.073646 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
359 12:44:41.081118 MRC: Hash idx 0x100b comparison successful.
360 12:44:41.081212 MRC cache found, size faa8
361 12:44:41.084020 bootmode is set to: 2
362 12:44:41.087315 SPD index = 2
363 12:44:41.094025 CBFS: Found 'spd.bin' @0x72940 size 0x600 in mcache @0xfef4579c
364 12:44:41.097305 SPD: module type is LPDDR4X
365 12:44:41.100621 SPD: module part number is MT53D1G64D4NW-046
366 12:44:41.107413 SPD: banks 8, ranks 1, rows 17, columns 10, density 16384 Mb
367 12:44:41.110974 SPD: device width 16 bits, bus width 16 bits
368 12:44:41.113771 SPD: module size is 2048 MB (per channel)
369 12:44:41.545567 CBMEM:
370 12:44:41.548972 IMD: root @ 0x76fff000 254 entries.
371 12:44:41.552423 IMD: root @ 0x76ffec00 62 entries.
372 12:44:41.555407 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
373 12:44:41.562008 FMAP: area RW_VPD found @ f35000 (8192 bytes)
374 12:44:41.565977 External stage cache:
375 12:44:41.569025 IMD: root @ 0x7b3ff000 254 entries.
376 12:44:41.572276 IMD: root @ 0x7b3fec00 62 entries.
377 12:44:41.587242 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
378 12:44:41.593664 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
379 12:44:41.600213 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
380 12:44:41.613770 MRC: 'RECOVERY_MRC_CACHE' does not need update.
381 12:44:41.620872 cse_lite: Skip switching to RW in the recovery path
382 12:44:41.620962 8 DIMMs found
383 12:44:41.621032 SMM Memory Map
384 12:44:41.627065 SMRAM : 0x7b000000 0x800000
385 12:44:41.630374 Subregion 0: 0x7b000000 0x200000
386 12:44:41.633675 Subregion 1: 0x7b200000 0x200000
387 12:44:41.636918 Subregion 2: 0x7b400000 0x400000
388 12:44:41.637005 top_of_ram = 0x77000000
389 12:44:41.643882 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
390 12:44:41.651409 MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
391 12:44:41.655233 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
392 12:44:41.658235 MTRR Range: Start=ff000000 End=0 (Size 1000000)
393 12:44:41.668286 CBFS: Found 'fallback/postcar' @0x160900 size 0x54f8 in mcache @0xfef4594c
394 12:44:41.674904 Decompressing stage fallback/postcar @ 0x76c0afc0 (38208 bytes)
395 12:44:41.684516 Loading module at 0x76c0b000 with entry 0x76c0b000. filesize: 0x5150 memsize: 0x9500
396 12:44:41.687618 Processing 211 relocs. Offset value of 0x74c0b000
397 12:44:41.696751 BS: romstage times (exec / console): total (unknown) / 276 ms
398 12:44:41.702700
399 12:44:41.702800
400 12:44:41.712553 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 postcar starting (log level: 8)...
401 12:44:41.715741 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
402 12:44:41.725879 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
403 12:44:41.732266 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
404 12:44:41.739249 CBFS: Found 'fallback/ramstage' @0x524c0 size 0x1fbe3 in mcache @0x76c4c0ec
405 12:44:41.745792 Decompressing stage fallback/ramstage @ 0x76b97fc0 (463536 bytes)
406 12:44:41.789278 Loading module at 0x76b98000 with entry 0x76b98000. filesize: 0x4d5d8 memsize: 0x71270
407 12:44:41.795738 Processing 5008 relocs. Offset value of 0x75d98000
408 12:44:41.799317 BS: postcar times (exec / console): total (unknown) / 59 ms
409 12:44:41.802451
410 12:44:41.802536
411 12:44:41.812174 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 ramstage starting (log level: 8)...
412 12:44:41.812261 Normal boot
413 12:44:41.815536 FW_CONFIG value is 0x804c02
414 12:44:41.819322 PCI: 00:07.0 disabled by fw_config
415 12:44:41.822427 PCI: 00:07.1 disabled by fw_config
416 12:44:41.825452 PCI: 00:0d.2 disabled by fw_config
417 12:44:41.832642 PCI: 00:1c.7 disabled by fw_config
418 12:44:41.835716 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
419 12:44:41.842176 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
420 12:44:41.845385 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
421 12:44:41.852197 GENERIC: 0.0 disabled by fw_config
422 12:44:41.855998 GENERIC: 1.0 disabled by fw_config
423 12:44:41.859231 fw_config match found: DB_USB=USB3_ACTIVE
424 12:44:41.862508 fw_config match found: DB_USB=USB3_ACTIVE
425 12:44:41.865997 fw_config match found: DB_USB=USB3_ACTIVE
426 12:44:41.869422 fw_config match found: DB_USB=USB3_ACTIVE
427 12:44:41.876079 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
428 12:44:41.883070 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
429 12:44:41.889135 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
430 12:44:41.899594 CBFS: Found 'cpu_microcode_blob.bin' @0x1c040 size 0x36400 in mcache @0x76c4c09c
431 12:44:41.902790 microcode: sig=0x806c1 pf=0x80 revision=0x86
432 12:44:41.909418 microcode: Update skipped, already up-to-date
433 12:44:41.915694 CBFS: Found 'fsps.bin' @0x11efc0 size 0x418f9 in mcache @0x76c4c30c
434 12:44:41.943204 Detected 4 core, 8 thread CPU.
435 12:44:41.946341 Setting up SMI for CPU
436 12:44:41.949705 IED base = 0x7b400000
437 12:44:41.949793 IED size = 0x00400000
438 12:44:41.952816 Will perform SMM setup.
439 12:44:41.959593 CPU: 11th Gen Intel(R) Core(TM) i7-1160G7 @ 1.20GHz.
440 12:44:41.965970 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
441 12:44:41.972892 Processing 16 relocs. Offset value of 0x00030000
442 12:44:41.976189 Attempting to start 7 APs
443 12:44:41.979048 Waiting for 10ms after sending INIT.
444 12:44:41.994967 Waiting for 1st SIPI to complete...done.
445 12:44:41.995111 AP: slot 1 apic_id 1.
446 12:44:41.998022 AP: slot 7 apic_id 3.
447 12:44:42.001240 AP: slot 5 apic_id 5.
448 12:44:42.001328 AP: slot 2 apic_id 4.
449 12:44:42.005143 AP: slot 3 apic_id 7.
450 12:44:42.008269 AP: slot 6 apic_id 6.
451 12:44:42.008387 AP: slot 4 apic_id 2.
452 12:44:42.014474 Waiting for 2nd SIPI to complete...done.
453 12:44:42.021545 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
454 12:44:42.028101 Processing 13 relocs. Offset value of 0x00038000
455 12:44:42.028192 Unable to locate Global NVS
456 12:44:42.038230 SMM Module: stub loaded at 0x00038000. Will call 0x76bb6318(0x00000000)
457 12:44:42.041526 Installing permanent SMM handler to 0x7b000000
458 12:44:42.050973 Loading module at 0x7b010000 with entry 0x7b010c16. filesize: 0xa7c8 memsize: 0xf908
459 12:44:42.054267 Processing 794 relocs. Offset value of 0x7b010000
460 12:44:42.064815 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8
461 12:44:42.068064 Processing 13 relocs. Offset value of 0x7b008000
462 12:44:42.074429 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
463 12:44:42.081262 SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
464 12:44:42.084279 SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
465 12:44:42.091068 SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
466 12:44:42.097959 SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
467 12:44:42.104598 SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
468 12:44:42.111173 SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
469 12:44:42.111263 Unable to locate Global NVS
470 12:44:42.120608 SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c16(0x00000000)
471 12:44:42.124044 Clearing SMI status registers
472 12:44:42.124132 SMI_STS: PM1
473 12:44:42.127305 PM1_STS: PWRBTN
474 12:44:42.133748 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
475 12:44:42.137630 In relocation handler: CPU 0
476 12:44:42.140739 New SMBASE=0x7b000000 IEDBASE=0x7b400000
477 12:44:42.147024 Writing SMRR. base = 0x7b000006, mask=0xff800c00
478 12:44:42.147142 Relocation complete.
479 12:44:42.157478 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
480 12:44:42.157569 In relocation handler: CPU 1
481 12:44:42.164180 New SMBASE=0x7afffc00 IEDBASE=0x7b400000
482 12:44:42.164267 Relocation complete.
483 12:44:42.173495 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
484 12:44:42.173602 In relocation handler: CPU 6
485 12:44:42.180614 New SMBASE=0x7affe800 IEDBASE=0x7b400000
486 12:44:42.183770 Writing SMRR. base = 0x7b000006, mask=0xff800c00
487 12:44:42.186855 Relocation complete.
488 12:44:42.193487 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
489 12:44:42.197118 In relocation handler: CPU 3
490 12:44:42.200062 New SMBASE=0x7afff400 IEDBASE=0x7b400000
491 12:44:42.203805 Relocation complete.
492 12:44:42.210345 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
493 12:44:42.213458 In relocation handler: CPU 5
494 12:44:42.216807 New SMBASE=0x7affec00 IEDBASE=0x7b400000
495 12:44:42.219967 Relocation complete.
496 12:44:42.226966 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
497 12:44:42.230022 In relocation handler: CPU 2
498 12:44:42.233026 New SMBASE=0x7afff800 IEDBASE=0x7b400000
499 12:44:42.239682 Writing SMRR. base = 0x7b000006, mask=0xff800c00
500 12:44:42.239780 Relocation complete.
501 12:44:42.246462 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
502 12:44:42.249674 In relocation handler: CPU 7
503 12:44:42.256000 New SMBASE=0x7affe400 IEDBASE=0x7b400000
504 12:44:42.256096 Relocation complete.
505 12:44:42.263175 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
506 12:44:42.266331 In relocation handler: CPU 4
507 12:44:42.272518 New SMBASE=0x7afff000 IEDBASE=0x7b400000
508 12:44:42.276349 Writing SMRR. base = 0x7b000006, mask=0xff800c00
509 12:44:42.279526 Relocation complete.
510 12:44:42.279631 Initializing CPU #0
511 12:44:42.282843 CPU: vendor Intel device 806c1
512 12:44:42.286044 CPU: family 06, model 8c, stepping 01
513 12:44:42.289313 Clearing out pending MCEs
514 12:44:42.292355 Setting up local APIC...
515 12:44:42.296040 apic_id: 0x00 done.
516 12:44:42.298974 Turbo is available but hidden
517 12:44:42.302724 Turbo is available and visible
518 12:44:42.305897 microcode: Update skipped, already up-to-date
519 12:44:42.308930 CPU #0 initialized
520 12:44:42.309018 Initializing CPU #4
521 12:44:42.313135 Initializing CPU #7
522 12:44:42.316602 CPU: vendor Intel device 806c1
523 12:44:42.320535 CPU: family 06, model 8c, stepping 01
524 12:44:42.323728 CPU: vendor Intel device 806c1
525 12:44:42.326917 CPU: family 06, model 8c, stepping 01
526 12:44:42.330184 Clearing out pending MCEs
527 12:44:42.330272 Clearing out pending MCEs
528 12:44:42.333377 Setting up local APIC...
529 12:44:42.337108 Initializing CPU #1
530 12:44:42.337197 Initializing CPU #3
531 12:44:42.340130 Initializing CPU #6
532 12:44:42.343225 CPU: vendor Intel device 806c1
533 12:44:42.346938 CPU: family 06, model 8c, stepping 01
534 12:44:42.350109 CPU: vendor Intel device 806c1
535 12:44:42.353357 CPU: family 06, model 8c, stepping 01
536 12:44:42.356924 Clearing out pending MCEs
537 12:44:42.360178 CPU: vendor Intel device 806c1
538 12:44:42.363446 CPU: family 06, model 8c, stepping 01
539 12:44:42.366699 apic_id: 0x02 done.
540 12:44:42.366785 Setting up local APIC...
541 12:44:42.369917 Initializing CPU #2
542 12:44:42.373584 Initializing CPU #5
543 12:44:42.376656 CPU: vendor Intel device 806c1
544 12:44:42.379819 CPU: family 06, model 8c, stepping 01
545 12:44:42.383130 Setting up local APIC...
546 12:44:42.383238 apic_id: 0x03 done.
547 12:44:42.390325 microcode: Update skipped, already up-to-date
548 12:44:42.393430 microcode: Update skipped, already up-to-date
549 12:44:42.396767 CPU #4 initialized
550 12:44:42.396887 CPU #7 initialized
551 12:44:42.399696 apic_id: 0x07 done.
552 12:44:42.402915 Clearing out pending MCEs
553 12:44:42.406420 microcode: Update skipped, already up-to-date
554 12:44:42.409959 Setting up local APIC...
555 12:44:42.410046 Clearing out pending MCEs
556 12:44:42.413267 CPU #3 initialized
557 12:44:42.416549 apic_id: 0x06 done.
558 12:44:42.419975 Clearing out pending MCEs
559 12:44:42.420089 CPU: vendor Intel device 806c1
560 12:44:42.426162 CPU: family 06, model 8c, stepping 01
561 12:44:42.426251 Setting up local APIC...
562 12:44:42.429880 Setting up local APIC...
563 12:44:42.432959 apic_id: 0x04 done.
564 12:44:42.436140 Clearing out pending MCEs
565 12:44:42.439333 microcode: Update skipped, already up-to-date
566 12:44:42.443086 Setting up local APIC...
567 12:44:42.443177 apic_id: 0x01 done.
568 12:44:42.449809 microcode: Update skipped, already up-to-date
569 12:44:42.452889 microcode: Update skipped, already up-to-date
570 12:44:42.456143 CPU #6 initialized
571 12:44:42.456231 CPU #1 initialized
572 12:44:42.459437 CPU #2 initialized
573 12:44:42.462592 apic_id: 0x05 done.
574 12:44:42.466625 microcode: Update skipped, already up-to-date
575 12:44:42.469722 CPU #5 initialized
576 12:44:42.472939 bsp_do_flight_plan done after 454 msecs.
577 12:44:42.475958 CPU: frequency set to 4400 MHz
578 12:44:42.476047 Enabling SMIs.
579 12:44:42.482855 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 347 / 317 ms
580 12:44:42.499159 SATAXPCIE1 indicates PCIe NVMe is present
581 12:44:42.502888 Probing TPM: done!
582 12:44:42.506018 Connected to device vid:did:rid of 1ae0:0028:00
583 12:44:42.517265 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
584 12:44:42.520202 Initialized TPM device CR50 revision 0
585 12:44:42.523297 Enabling S0i3.4
586 12:44:42.529908 CBFS: Found 'vbt.bin' @0x78a40 size 0x4f0 in mcache @0x76c4c1fc
587 12:44:42.533473 Found a VBT of 8704 bytes after decompression
588 12:44:42.540005 cse_lite: CSE RO boot. HybridStorageMode disabled
589 12:44:42.546507 WEAK: src/soc/intel/tigerlake/fsp_params.c/mainboard_silicon_init_params called
590 12:44:42.621154 FSPS returned 0
591 12:44:42.624719 Executing Phase 1 of FspMultiPhaseSiInit
592 12:44:42.635146 FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
593 12:44:42.637694 port C0 DISC req: usage 1 usb3 1 usb2 5
594 12:44:42.641277 Raw Buffer output 0 00000511
595 12:44:42.644353 Raw Buffer output 1 00000000
596 12:44:42.648620 pmc_send_ipc_cmd succeeded
597 12:44:42.655120 port C1 DISC req: usage 1 usb3 2 usb2 3
598 12:44:42.655254 Raw Buffer output 0 00000321
599 12:44:42.658379 Raw Buffer output 1 00000000
600 12:44:42.662390 pmc_send_ipc_cmd succeeded
601 12:44:42.668168 Detected 4 core, 8 thread CPU.
602 12:44:42.671156 Detected 4 core, 8 thread CPU.
603 12:44:42.871040 Display FSP Version Info HOB
604 12:44:42.874204 Reference Code - CPU = a.0.4c.31
605 12:44:42.877833 uCode Version = 0.0.0.86
606 12:44:42.880586 TXT ACM version = ff.ff.ff.ffff
607 12:44:42.884024 Reference Code - ME = a.0.4c.31
608 12:44:42.887237 MEBx version = 0.0.0.0
609 12:44:42.891005 ME Firmware Version = Consumer SKU
610 12:44:42.894634 Reference Code - PCH = a.0.4c.31
611 12:44:42.897821 PCH-CRID Status = Disabled
612 12:44:42.901168 PCH-CRID Original Value = ff.ff.ff.ffff
613 12:44:42.904956 PCH-CRID New Value = ff.ff.ff.ffff
614 12:44:42.908228 OPROM - RST - RAID = ff.ff.ff.ffff
615 12:44:42.911366 PCH Hsio Version = 4.0.0.0
616 12:44:42.914650 Reference Code - SA - System Agent = a.0.4c.31
617 12:44:42.917897 Reference Code - MRC = 2.0.0.1
618 12:44:42.921094 SA - PCIe Version = a.0.4c.31
619 12:44:42.924269 SA-CRID Status = Disabled
620 12:44:42.927532 SA-CRID Original Value = 0.0.0.1
621 12:44:42.931469 SA-CRID New Value = 0.0.0.1
622 12:44:42.934732 OPROM - VBIOS = ff.ff.ff.ffff
623 12:44:42.938028 IO Manageability Engine FW Version = 11.1.4.0
624 12:44:42.941156 PHY Build Version = 0.0.0.e0
625 12:44:42.944437 Thunderbolt(TM) FW Version = 0.0.0.0
626 12:44:42.951309 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
627 12:44:42.954272 ITSS IRQ Polarities Before:
628 12:44:42.954359 IPC0: 0xffffffff
629 12:44:42.957747 IPC1: 0xffffffff
630 12:44:42.957833 IPC2: 0xffffffff
631 12:44:42.960740 IPC3: 0xffffffff
632 12:44:42.964198 ITSS IRQ Polarities After:
633 12:44:42.964287 IPC0: 0xffffffff
634 12:44:42.967297 IPC1: 0xffffffff
635 12:44:42.967384 IPC2: 0xffffffff
636 12:44:42.970918 IPC3: 0xffffffff
637 12:44:42.973954 Found PCIe Root Port #9 at PCI: 00:1d.0.
638 12:44:42.987515 pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
639 12:44:42.997206 pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing.
640 12:44:43.010503 pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
641 12:44:43.017645 BS: BS_DEV_INIT_CHIPS run times (exec / console): 290 / 236 ms
642 12:44:43.017741 Enumerating buses...
643 12:44:43.023949 Show all devs... Before device enumeration.
644 12:44:43.024039 Root Device: enabled 1
645 12:44:43.027179 DOMAIN: 0000: enabled 1
646 12:44:43.030503 CPU_CLUSTER: 0: enabled 1
647 12:44:43.033770 PCI: 00:00.0: enabled 1
648 12:44:43.033858 PCI: 00:02.0: enabled 1
649 12:44:43.036939 PCI: 00:04.0: enabled 1
650 12:44:43.040131 PCI: 00:05.0: enabled 1
651 12:44:43.043457 PCI: 00:06.0: enabled 0
652 12:44:43.043547 PCI: 00:07.0: enabled 0
653 12:44:43.047342 PCI: 00:07.1: enabled 0
654 12:44:43.050544 PCI: 00:07.2: enabled 0
655 12:44:43.053420 PCI: 00:07.3: enabled 0
656 12:44:43.053507 PCI: 00:08.0: enabled 1
657 12:44:43.056661 PCI: 00:09.0: enabled 0
658 12:44:43.059927 PCI: 00:0a.0: enabled 0
659 12:44:43.063631 PCI: 00:0d.0: enabled 1
660 12:44:43.063722 PCI: 00:0d.1: enabled 0
661 12:44:43.067014 PCI: 00:0d.2: enabled 0
662 12:44:43.070233 PCI: 00:0d.3: enabled 0
663 12:44:43.073199 PCI: 00:0e.0: enabled 0
664 12:44:43.073285 PCI: 00:10.2: enabled 1
665 12:44:43.076690 PCI: 00:10.6: enabled 0
666 12:44:43.080230 PCI: 00:10.7: enabled 0
667 12:44:43.080314 PCI: 00:12.0: enabled 0
668 12:44:43.083364 PCI: 00:12.6: enabled 0
669 12:44:43.086999 PCI: 00:13.0: enabled 0
670 12:44:43.090245 PCI: 00:14.0: enabled 1
671 12:44:43.090330 PCI: 00:14.1: enabled 0
672 12:44:43.093468 PCI: 00:14.2: enabled 1
673 12:44:43.096534 PCI: 00:14.3: enabled 1
674 12:44:43.100263 PCI: 00:15.0: enabled 1
675 12:44:43.100349 PCI: 00:15.1: enabled 1
676 12:44:43.103331 PCI: 00:15.2: enabled 1
677 12:44:43.106739 PCI: 00:15.3: enabled 1
678 12:44:43.109778 PCI: 00:16.0: enabled 1
679 12:44:43.109863 PCI: 00:16.1: enabled 0
680 12:44:43.113537 PCI: 00:16.2: enabled 0
681 12:44:43.117191 PCI: 00:16.3: enabled 0
682 12:44:43.117277 PCI: 00:16.4: enabled 0
683 12:44:43.120270 PCI: 00:16.5: enabled 0
684 12:44:43.123468 PCI: 00:17.0: enabled 1
685 12:44:43.126787 PCI: 00:19.0: enabled 0
686 12:44:43.126878 PCI: 00:19.1: enabled 1
687 12:44:43.130024 PCI: 00:19.2: enabled 0
688 12:44:43.133201 PCI: 00:1c.0: enabled 1
689 12:44:43.136657 PCI: 00:1c.1: enabled 0
690 12:44:43.136744 PCI: 00:1c.2: enabled 0
691 12:44:43.139805 PCI: 00:1c.3: enabled 0
692 12:44:43.143137 PCI: 00:1c.4: enabled 0
693 12:44:43.146713 PCI: 00:1c.5: enabled 0
694 12:44:43.146800 PCI: 00:1c.6: enabled 1
695 12:44:43.150061 PCI: 00:1c.7: enabled 0
696 12:44:43.153231 PCI: 00:1d.0: enabled 1
697 12:44:43.156309 PCI: 00:1d.1: enabled 0
698 12:44:43.156395 PCI: 00:1d.2: enabled 1
699 12:44:43.159468 PCI: 00:1d.3: enabled 0
700 12:44:43.163330 PCI: 00:1e.0: enabled 1
701 12:44:43.163416 PCI: 00:1e.1: enabled 0
702 12:44:43.166601 PCI: 00:1e.2: enabled 1
703 12:44:43.169642 PCI: 00:1e.3: enabled 1
704 12:44:43.173342 PCI: 00:1f.0: enabled 1
705 12:44:43.173428 PCI: 00:1f.1: enabled 0
706 12:44:43.176755 PCI: 00:1f.2: enabled 1
707 12:44:43.179645 PCI: 00:1f.3: enabled 1
708 12:44:43.183052 PCI: 00:1f.4: enabled 0
709 12:44:43.183138 PCI: 00:1f.5: enabled 1
710 12:44:43.186611 PCI: 00:1f.6: enabled 0
711 12:44:43.189482 PCI: 00:1f.7: enabled 0
712 12:44:43.189572 APIC: 00: enabled 1
713 12:44:43.193160 GENERIC: 0.0: enabled 1
714 12:44:43.196468 GENERIC: 0.0: enabled 1
715 12:44:43.199504 GENERIC: 1.0: enabled 1
716 12:44:43.199592 GENERIC: 0.0: enabled 1
717 12:44:43.202957 GENERIC: 1.0: enabled 1
718 12:44:43.206058 USB0 port 0: enabled 1
719 12:44:43.209320 GENERIC: 0.0: enabled 1
720 12:44:43.209406 USB0 port 0: enabled 1
721 12:44:43.212724 GENERIC: 0.0: enabled 1
722 12:44:43.215929 I2C: 00:1a: enabled 1
723 12:44:43.216041 I2C: 00:31: enabled 1
724 12:44:43.219213 I2C: 00:32: enabled 1
725 12:44:43.223053 I2C: 00:10: enabled 1
726 12:44:43.223161 I2C: 00:15: enabled 1
727 12:44:43.226048 GENERIC: 0.0: enabled 0
728 12:44:43.229248 GENERIC: 1.0: enabled 0
729 12:44:43.232542 GENERIC: 0.0: enabled 1
730 12:44:43.232648 SPI: 00: enabled 1
731 12:44:43.235749 SPI: 00: enabled 1
732 12:44:43.235854 PNP: 0c09.0: enabled 1
733 12:44:43.239099 GENERIC: 0.0: enabled 1
734 12:44:43.242959 USB3 port 0: enabled 1
735 12:44:43.246222 USB3 port 1: enabled 1
736 12:44:43.246332 USB3 port 2: enabled 0
737 12:44:43.249501 USB3 port 3: enabled 0
738 12:44:43.252764 USB2 port 0: enabled 0
739 12:44:43.252870 USB2 port 1: enabled 1
740 12:44:43.255821 USB2 port 2: enabled 1
741 12:44:43.259092 USB2 port 3: enabled 0
742 12:44:43.262932 USB2 port 4: enabled 1
743 12:44:43.263045 USB2 port 5: enabled 0
744 12:44:43.266225 USB2 port 6: enabled 0
745 12:44:43.269513 USB2 port 7: enabled 0
746 12:44:43.269624 USB2 port 8: enabled 0
747 12:44:43.272819 USB2 port 9: enabled 0
748 12:44:43.275985 USB3 port 0: enabled 0
749 12:44:43.279208 USB3 port 1: enabled 1
750 12:44:43.279321 USB3 port 2: enabled 0
751 12:44:43.282702 USB3 port 3: enabled 0
752 12:44:43.285749 GENERIC: 0.0: enabled 1
753 12:44:43.285864 GENERIC: 1.0: enabled 1
754 12:44:43.289172 APIC: 01: enabled 1
755 12:44:43.292803 APIC: 04: enabled 1
756 12:44:43.292918 APIC: 07: enabled 1
757 12:44:43.295737 APIC: 02: enabled 1
758 12:44:43.295849 APIC: 05: enabled 1
759 12:44:43.299162 APIC: 06: enabled 1
760 12:44:43.302696 APIC: 03: enabled 1
761 12:44:43.302807 Compare with tree...
762 12:44:43.305759 Root Device: enabled 1
763 12:44:43.308809 DOMAIN: 0000: enabled 1
764 12:44:43.312842 PCI: 00:00.0: enabled 1
765 12:44:43.312955 PCI: 00:02.0: enabled 1
766 12:44:43.315774 PCI: 00:04.0: enabled 1
767 12:44:43.318969 GENERIC: 0.0: enabled 1
768 12:44:43.322445 PCI: 00:05.0: enabled 1
769 12:44:43.325660 PCI: 00:06.0: enabled 0
770 12:44:43.325770 PCI: 00:07.0: enabled 0
771 12:44:43.329317 GENERIC: 0.0: enabled 1
772 12:44:43.332294 PCI: 00:07.1: enabled 0
773 12:44:43.336052 GENERIC: 1.0: enabled 1
774 12:44:43.339331 PCI: 00:07.2: enabled 0
775 12:44:43.339445 GENERIC: 0.0: enabled 1
776 12:44:43.342507 PCI: 00:07.3: enabled 0
777 12:44:43.345599 GENERIC: 1.0: enabled 1
778 12:44:43.349066 PCI: 00:08.0: enabled 1
779 12:44:43.352105 PCI: 00:09.0: enabled 0
780 12:44:43.352217 PCI: 00:0a.0: enabled 0
781 12:44:43.355340 PCI: 00:0d.0: enabled 1
782 12:44:43.358745 USB0 port 0: enabled 1
783 12:44:43.362004 USB3 port 0: enabled 1
784 12:44:43.365835 USB3 port 1: enabled 1
785 12:44:43.368999 USB3 port 2: enabled 0
786 12:44:43.369106 USB3 port 3: enabled 0
787 12:44:43.372222 PCI: 00:0d.1: enabled 0
788 12:44:43.375455 PCI: 00:0d.2: enabled 0
789 12:44:43.378855 GENERIC: 0.0: enabled 1
790 12:44:43.381806 PCI: 00:0d.3: enabled 0
791 12:44:43.381921 PCI: 00:0e.0: enabled 0
792 12:44:43.385648 PCI: 00:10.2: enabled 1
793 12:44:43.389113 PCI: 00:10.6: enabled 0
794 12:44:43.392220 PCI: 00:10.7: enabled 0
795 12:44:43.395284 PCI: 00:12.0: enabled 0
796 12:44:43.395402 PCI: 00:12.6: enabled 0
797 12:44:43.398914 PCI: 00:13.0: enabled 0
798 12:44:43.402013 PCI: 00:14.0: enabled 1
799 12:44:43.405086 USB0 port 0: enabled 1
800 12:44:43.408696 USB2 port 0: enabled 0
801 12:44:43.408807 USB2 port 1: enabled 1
802 12:44:43.412184 USB2 port 2: enabled 1
803 12:44:43.415303 USB2 port 3: enabled 0
804 12:44:43.418394 USB2 port 4: enabled 1
805 12:44:43.422258 USB2 port 5: enabled 0
806 12:44:43.422370 USB2 port 6: enabled 0
807 12:44:43.425321 USB2 port 7: enabled 0
808 12:44:43.428603 USB2 port 8: enabled 0
809 12:44:43.431760 USB2 port 9: enabled 0
810 12:44:43.435287 USB3 port 0: enabled 0
811 12:44:43.438500 USB3 port 1: enabled 1
812 12:44:43.438616 USB3 port 2: enabled 0
813 12:44:43.441925 USB3 port 3: enabled 0
814 12:44:43.444889 PCI: 00:14.1: enabled 0
815 12:44:43.448787 PCI: 00:14.2: enabled 1
816 12:44:43.452033 PCI: 00:14.3: enabled 1
817 12:44:43.452155 GENERIC: 0.0: enabled 1
818 12:44:43.455333 PCI: 00:15.0: enabled 1
819 12:44:43.458523 I2C: 00:1a: enabled 1
820 12:44:43.461777 I2C: 00:31: enabled 1
821 12:44:43.464996 I2C: 00:32: enabled 1
822 12:44:43.465111 PCI: 00:15.1: enabled 1
823 12:44:43.468263 I2C: 00:10: enabled 1
824 12:44:43.472104 PCI: 00:15.2: enabled 1
825 12:44:43.475059 PCI: 00:15.3: enabled 1
826 12:44:43.475145 PCI: 00:16.0: enabled 1
827 12:44:43.478506 PCI: 00:16.1: enabled 0
828 12:44:43.481580 PCI: 00:16.2: enabled 0
829 12:44:43.484853 PCI: 00:16.3: enabled 0
830 12:44:43.488175 PCI: 00:16.4: enabled 0
831 12:44:43.488267 PCI: 00:16.5: enabled 0
832 12:44:43.491856 PCI: 00:17.0: enabled 1
833 12:44:43.495182 PCI: 00:19.0: enabled 0
834 12:44:43.498222 PCI: 00:19.1: enabled 1
835 12:44:43.501398 I2C: 00:15: enabled 1
836 12:44:43.501506 PCI: 00:19.2: enabled 0
837 12:44:43.504878 PCI: 00:1d.0: enabled 1
838 12:44:43.508493 GENERIC: 0.0: enabled 1
839 12:44:43.558471 PCI: 00:1e.0: enabled 1
840 12:44:43.558616 PCI: 00:1e.1: enabled 0
841 12:44:43.559155 PCI: 00:1e.2: enabled 1
842 12:44:43.559348 SPI: 00: enabled 1
843 12:44:43.559467 PCI: 00:1e.3: enabled 1
844 12:44:43.559727 SPI: 00: enabled 1
845 12:44:43.559799 PCI: 00:1f.0: enabled 1
846 12:44:43.559865 PNP: 0c09.0: enabled 1
847 12:44:43.559928 PCI: 00:1f.1: enabled 0
848 12:44:43.559990 PCI: 00:1f.2: enabled 1
849 12:44:43.560049 GENERIC: 0.0: enabled 1
850 12:44:43.560109 GENERIC: 0.0: enabled 1
851 12:44:43.560403 GENERIC: 1.0: enabled 1
852 12:44:43.560474 PCI: 00:1f.3: enabled 1
853 12:44:43.560754 PCI: 00:1f.4: enabled 0
854 12:44:43.560822 PCI: 00:1f.5: enabled 1
855 12:44:43.560883 PCI: 00:1f.6: enabled 0
856 12:44:43.560941 PCI: 00:1f.7: enabled 0
857 12:44:43.560999 CPU_CLUSTER: 0: enabled 1
858 12:44:43.568871 APIC: 00: enabled 1
859 12:44:43.569040 APIC: 01: enabled 1
860 12:44:43.569165 APIC: 04: enabled 1
861 12:44:43.572230 APIC: 07: enabled 1
862 12:44:43.572339 APIC: 02: enabled 1
863 12:44:43.572436 APIC: 05: enabled 1
864 12:44:43.575097 APIC: 06: enabled 1
865 12:44:43.575290 APIC: 03: enabled 1
866 12:44:43.578868 Root Device scanning...
867 12:44:43.582287 scan_static_bus for Root Device
868 12:44:43.586091 DOMAIN: 0000 enabled
869 12:44:43.589254 CPU_CLUSTER: 0 enabled
870 12:44:43.589366 DOMAIN: 0000 scanning...
871 12:44:43.592374 PCI: pci_scan_bus for bus 00
872 12:44:43.595345 PCI: 00:00.0 [8086/0000] ops
873 12:44:43.599163 PCI: 00:00.0 [8086/9a12] enabled
874 12:44:43.602531 PCI: 00:02.0 [8086/0000] bus ops
875 12:44:43.605592 PCI: 00:02.0 [8086/9a40] enabled
876 12:44:43.608905 PCI: 00:04.0 [8086/0000] bus ops
877 12:44:43.612055 PCI: 00:04.0 [8086/9a03] enabled
878 12:44:43.615843 PCI: 00:05.0 [8086/9a19] enabled
879 12:44:43.618842 PCI: 00:07.0 [0000/0000] hidden
880 12:44:43.622314 PCI: 00:08.0 [8086/9a11] enabled
881 12:44:43.625357 PCI: 00:0a.0 [8086/9a0d] disabled
882 12:44:43.629013 PCI: 00:0d.0 [8086/0000] bus ops
883 12:44:43.632011 PCI: 00:0d.0 [8086/9a13] enabled
884 12:44:43.635535 PCI: 00:14.0 [8086/0000] bus ops
885 12:44:43.638635 PCI: 00:14.0 [8086/a0ed] enabled
886 12:44:43.641862 PCI: 00:14.2 [8086/a0ef] enabled
887 12:44:43.644952 PCI: 00:14.3 [8086/0000] bus ops
888 12:44:43.648781 PCI: 00:14.3 [8086/a0f0] enabled
889 12:44:43.651680 PCI: 00:15.0 [8086/0000] bus ops
890 12:44:43.655307 PCI: 00:15.0 [8086/a0e8] enabled
891 12:44:43.658472 PCI: 00:15.1 [8086/0000] bus ops
892 12:44:43.661646 PCI: 00:15.1 [8086/a0e9] enabled
893 12:44:43.664934 PCI: 00:15.2 [8086/0000] bus ops
894 12:44:43.668215 PCI: 00:15.2 [8086/a0ea] enabled
895 12:44:43.671613 PCI: 00:15.3 [8086/0000] bus ops
896 12:44:43.675194 PCI: 00:15.3 [8086/a0eb] enabled
897 12:44:43.678490 PCI: 00:16.0 [8086/0000] ops
898 12:44:43.681466 PCI: 00:16.0 [8086/a0e0] enabled
899 12:44:43.688727 PCI: Static device PCI: 00:17.0 not found, disabling it.
900 12:44:43.692003 PCI: 00:19.0 [8086/0000] bus ops
901 12:44:43.695203 PCI: 00:19.0 [8086/a0c5] disabled
902 12:44:43.698339 PCI: 00:19.1 [8086/0000] bus ops
903 12:44:43.701479 PCI: 00:19.1 [8086/a0c6] enabled
904 12:44:43.704688 PCI: 00:1d.0 [8086/0000] bus ops
905 12:44:43.708502 PCI: 00:1d.0 [8086/a0b0] enabled
906 12:44:43.711605 PCI: 00:1e.0 [8086/0000] ops
907 12:44:43.714705 PCI: 00:1e.0 [8086/a0a8] enabled
908 12:44:43.717888 PCI: 00:1e.2 [8086/0000] bus ops
909 12:44:43.721175 PCI: 00:1e.2 [8086/a0aa] enabled
910 12:44:43.724717 PCI: 00:1e.3 [8086/0000] bus ops
911 12:44:43.727917 PCI: 00:1e.3 [8086/a0ab] enabled
912 12:44:43.731438 PCI: 00:1f.0 [8086/0000] bus ops
913 12:44:43.734592 PCI: 00:1f.0 [8086/a087] enabled
914 12:44:43.734680 RTC Init
915 12:44:43.738034 Set power on after power failure.
916 12:44:43.740975 Disabling Deep S3
917 12:44:43.744804 Disabling Deep S3
918 12:44:43.744894 Disabling Deep S4
919 12:44:43.748022 Disabling Deep S4
920 12:44:43.748111 Disabling Deep S5
921 12:44:43.751176 Disabling Deep S5
922 12:44:43.754834 PCI: 00:1f.2 [0000/0000] hidden
923 12:44:43.757955 PCI: 00:1f.3 [8086/0000] bus ops
924 12:44:43.761016 PCI: 00:1f.3 [8086/a0c8] enabled
925 12:44:43.764613 PCI: 00:1f.5 [8086/0000] bus ops
926 12:44:43.767722 PCI: 00:1f.5 [8086/a0a4] enabled
927 12:44:43.770994 PCI: Leftover static devices:
928 12:44:43.771081 PCI: 00:10.2
929 12:44:43.774298 PCI: 00:10.6
930 12:44:43.774384 PCI: 00:10.7
931 12:44:43.774452 PCI: 00:06.0
932 12:44:43.778306 PCI: 00:07.1
933 12:44:43.778392 PCI: 00:07.2
934 12:44:43.781247 PCI: 00:07.3
935 12:44:43.781334 PCI: 00:09.0
936 12:44:43.784386 PCI: 00:0d.1
937 12:44:43.784472 PCI: 00:0d.2
938 12:44:43.784539 PCI: 00:0d.3
939 12:44:43.787418 PCI: 00:0e.0
940 12:44:43.787510 PCI: 00:12.0
941 12:44:43.791280 PCI: 00:12.6
942 12:44:43.791368 PCI: 00:13.0
943 12:44:43.791435 PCI: 00:14.1
944 12:44:43.794476 PCI: 00:16.1
945 12:44:43.794561 PCI: 00:16.2
946 12:44:43.797679 PCI: 00:16.3
947 12:44:43.797763 PCI: 00:16.4
948 12:44:43.800840 PCI: 00:16.5
949 12:44:43.800925 PCI: 00:17.0
950 12:44:43.800992 PCI: 00:19.2
951 12:44:43.803955 PCI: 00:1e.1
952 12:44:43.804039 PCI: 00:1f.1
953 12:44:43.807754 PCI: 00:1f.4
954 12:44:43.807840 PCI: 00:1f.6
955 12:44:43.807908 PCI: 00:1f.7
956 12:44:43.811047 PCI: Check your devicetree.cb.
957 12:44:43.814368 PCI: 00:02.0 scanning...
958 12:44:43.817546 scan_generic_bus for PCI: 00:02.0
959 12:44:43.820566 scan_generic_bus for PCI: 00:02.0 done
960 12:44:43.827166 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
961 12:44:43.830490 PCI: 00:04.0 scanning...
962 12:44:43.833613 scan_generic_bus for PCI: 00:04.0
963 12:44:43.833701 GENERIC: 0.0 enabled
964 12:44:43.840986 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
965 12:44:43.846999 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
966 12:44:43.847090 PCI: 00:0d.0 scanning...
967 12:44:43.850461 scan_static_bus for PCI: 00:0d.0
968 12:44:43.853350 USB0 port 0 enabled
969 12:44:43.856721 USB0 port 0 scanning...
970 12:44:43.860248 scan_static_bus for USB0 port 0
971 12:44:43.863805 USB3 port 0 enabled
972 12:44:43.863892 USB3 port 1 enabled
973 12:44:43.866856 USB3 port 2 disabled
974 12:44:43.866943 USB3 port 3 disabled
975 12:44:43.869917 USB3 port 0 scanning...
976 12:44:43.873491 scan_static_bus for USB3 port 0
977 12:44:43.876630 scan_static_bus for USB3 port 0 done
978 12:44:43.883390 scan_bus: bus USB3 port 0 finished in 6 msecs
979 12:44:43.883477 USB3 port 1 scanning...
980 12:44:43.886707 scan_static_bus for USB3 port 1
981 12:44:43.893639 scan_static_bus for USB3 port 1 done
982 12:44:43.896759 scan_bus: bus USB3 port 1 finished in 6 msecs
983 12:44:43.900344 scan_static_bus for USB0 port 0 done
984 12:44:43.903306 scan_bus: bus USB0 port 0 finished in 43 msecs
985 12:44:43.910266 scan_static_bus for PCI: 00:0d.0 done
986 12:44:43.913535 scan_bus: bus PCI: 00:0d.0 finished in 60 msecs
987 12:44:43.916858 PCI: 00:14.0 scanning...
988 12:44:43.919989 scan_static_bus for PCI: 00:14.0
989 12:44:43.923182 USB0 port 0 enabled
990 12:44:43.923269 USB0 port 0 scanning...
991 12:44:43.926905 scan_static_bus for USB0 port 0
992 12:44:43.930236 USB2 port 0 disabled
993 12:44:43.933413 USB2 port 1 enabled
994 12:44:43.933501 USB2 port 2 enabled
995 12:44:43.936714 USB2 port 3 disabled
996 12:44:43.936802 USB2 port 4 enabled
997 12:44:43.939740 USB2 port 5 disabled
998 12:44:43.943602 USB2 port 6 disabled
999 12:44:43.943688 USB2 port 7 disabled
1000 12:44:43.946239 USB2 port 8 disabled
1001 12:44:43.949970 USB2 port 9 disabled
1002 12:44:43.950059 USB3 port 0 disabled
1003 12:44:43.953148 USB3 port 1 enabled
1004 12:44:43.956302 USB3 port 2 disabled
1005 12:44:43.956388 USB3 port 3 disabled
1006 12:44:43.959936 USB2 port 1 scanning...
1007 12:44:43.962894 scan_static_bus for USB2 port 1
1008 12:44:43.966417 scan_static_bus for USB2 port 1 done
1009 12:44:43.973214 scan_bus: bus USB2 port 1 finished in 6 msecs
1010 12:44:43.973309 USB2 port 2 scanning...
1011 12:44:43.976412 scan_static_bus for USB2 port 2
1012 12:44:43.979347 scan_static_bus for USB2 port 2 done
1013 12:44:43.986690 scan_bus: bus USB2 port 2 finished in 6 msecs
1014 12:44:43.989695 USB2 port 4 scanning...
1015 12:44:43.992739 scan_static_bus for USB2 port 4
1016 12:44:43.995958 scan_static_bus for USB2 port 4 done
1017 12:44:43.999143 scan_bus: bus USB2 port 4 finished in 6 msecs
1018 12:44:44.003089 USB3 port 1 scanning...
1019 12:44:44.006305 scan_static_bus for USB3 port 1
1020 12:44:44.009576 scan_static_bus for USB3 port 1 done
1021 12:44:44.012722 scan_bus: bus USB3 port 1 finished in 6 msecs
1022 12:44:44.019076 scan_static_bus for USB0 port 0 done
1023 12:44:44.022384 scan_bus: bus USB0 port 0 finished in 93 msecs
1024 12:44:44.026249 scan_static_bus for PCI: 00:14.0 done
1025 12:44:44.032623 scan_bus: bus PCI: 00:14.0 finished in 109 msecs
1026 12:44:44.032712 PCI: 00:14.3 scanning...
1027 12:44:44.035847 scan_static_bus for PCI: 00:14.3
1028 12:44:44.039184 GENERIC: 0.0 enabled
1029 12:44:44.042763 scan_static_bus for PCI: 00:14.3 done
1030 12:44:44.049189 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
1031 12:44:44.049277 PCI: 00:15.0 scanning...
1032 12:44:44.052284 scan_static_bus for PCI: 00:15.0
1033 12:44:44.055996 I2C: 00:1a enabled
1034 12:44:44.058953 I2C: 00:31 enabled
1035 12:44:44.059042 I2C: 00:32 enabled
1036 12:44:44.062536 scan_static_bus for PCI: 00:15.0 done
1037 12:44:44.068835 scan_bus: bus PCI: 00:15.0 finished in 12 msecs
1038 12:44:44.072557 PCI: 00:15.1 scanning...
1039 12:44:44.075625 scan_static_bus for PCI: 00:15.1
1040 12:44:44.075725 I2C: 00:10 enabled
1041 12:44:44.078727 scan_static_bus for PCI: 00:15.1 done
1042 12:44:44.085609 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
1043 12:44:44.088804 PCI: 00:15.2 scanning...
1044 12:44:44.092594 scan_static_bus for PCI: 00:15.2
1045 12:44:44.095570 scan_static_bus for PCI: 00:15.2 done
1046 12:44:44.098642 scan_bus: bus PCI: 00:15.2 finished in 7 msecs
1047 12:44:44.102258 PCI: 00:15.3 scanning...
1048 12:44:44.105570 scan_static_bus for PCI: 00:15.3
1049 12:44:44.108845 scan_static_bus for PCI: 00:15.3 done
1050 12:44:44.115300 scan_bus: bus PCI: 00:15.3 finished in 7 msecs
1051 12:44:44.115387 PCI: 00:19.1 scanning...
1052 12:44:44.118432 scan_static_bus for PCI: 00:19.1
1053 12:44:44.121694 I2C: 00:15 enabled
1054 12:44:44.125007 scan_static_bus for PCI: 00:19.1 done
1055 12:44:44.131922 scan_bus: bus PCI: 00:19.1 finished in 9 msecs
1056 12:44:44.132016 PCI: 00:1d.0 scanning...
1057 12:44:44.135814 do_pci_scan_bridge for PCI: 00:1d.0
1058 12:44:44.139006 PCI: pci_scan_bus for bus 01
1059 12:44:44.142308 PCI: 01:00.0 [15b7/5009] enabled
1060 12:44:44.145667 GENERIC: 0.0 enabled
1061 12:44:44.149331 Enabling Common Clock Configuration
1062 12:44:44.152796 L1 Sub-State supported from root port 29
1063 12:44:44.155768 L1 Sub-State Support = 0x5
1064 12:44:44.159015 CommonModeRestoreTime = 0x28
1065 12:44:44.162201 Power On Value = 0x16, Power On Scale = 0x0
1066 12:44:44.165720 ASPM: Enabled L1
1067 12:44:44.168780 PCIe: Max_Payload_Size adjusted to 128
1068 12:44:44.175447 scan_bus: bus PCI: 00:1d.0 finished in 35 msecs
1069 12:44:44.175547 PCI: 00:1e.2 scanning...
1070 12:44:44.179063 scan_generic_bus for PCI: 00:1e.2
1071 12:44:44.182262 SPI: 00 enabled
1072 12:44:44.189070 bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done
1073 12:44:44.192079 scan_bus: bus PCI: 00:1e.2 finished in 11 msecs
1074 12:44:44.195291 PCI: 00:1e.3 scanning...
1075 12:44:44.198514 scan_generic_bus for PCI: 00:1e.3
1076 12:44:44.202071 SPI: 00 enabled
1077 12:44:44.205498 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1078 12:44:44.211977 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1079 12:44:44.215357 PCI: 00:1f.0 scanning...
1080 12:44:44.218441 scan_static_bus for PCI: 00:1f.0
1081 12:44:44.218531 PNP: 0c09.0 enabled
1082 12:44:44.221521 PNP: 0c09.0 scanning...
1083 12:44:44.225356 scan_static_bus for PNP: 0c09.0
1084 12:44:44.228523 scan_static_bus for PNP: 0c09.0 done
1085 12:44:44.234811 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1086 12:44:44.238788 scan_static_bus for PCI: 00:1f.0 done
1087 12:44:44.241960 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1088 12:44:44.245265 PCI: 00:1f.2 scanning...
1089 12:44:44.248525 scan_static_bus for PCI: 00:1f.2
1090 12:44:44.251651 GENERIC: 0.0 enabled
1091 12:44:44.251755 GENERIC: 0.0 scanning...
1092 12:44:44.255392 scan_static_bus for GENERIC: 0.0
1093 12:44:44.258348 GENERIC: 0.0 enabled
1094 12:44:44.261637 GENERIC: 1.0 enabled
1095 12:44:44.264958 scan_static_bus for GENERIC: 0.0 done
1096 12:44:44.268753 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1097 12:44:44.274825 scan_static_bus for PCI: 00:1f.2 done
1098 12:44:44.278493 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1099 12:44:44.281436 PCI: 00:1f.3 scanning...
1100 12:44:44.284870 scan_static_bus for PCI: 00:1f.3
1101 12:44:44.287923 scan_static_bus for PCI: 00:1f.3 done
1102 12:44:44.291445 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1103 12:44:44.294806 PCI: 00:1f.5 scanning...
1104 12:44:44.298327 scan_generic_bus for PCI: 00:1f.5
1105 12:44:44.301561 scan_generic_bus for PCI: 00:1f.5 done
1106 12:44:44.308156 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1107 12:44:44.311282 scan_bus: bus DOMAIN: 0000 finished in 716 msecs
1108 12:44:44.314939 scan_static_bus for Root Device done
1109 12:44:44.321098 scan_bus: bus Root Device finished in 735 msecs
1110 12:44:44.321188 done
1111 12:44:44.328051 BS: BS_DEV_ENUMERATE run times (exec / console): 10 / 1295 ms
1112 12:44:44.331332 Chrome EC: UHEPI supported
1113 12:44:44.337770 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (196608 bytes)
1114 12:44:44.344528 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1115 12:44:44.347868 SPI flash protection: WPSW=0 SRP0=1
1116 12:44:44.354358 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1117 12:44:44.357979 BS: BS_DEV_ENUMERATE exit times (exec / console): 2 / 23 ms
1118 12:44:44.361040 found VGA at PCI: 00:02.0
1119 12:44:44.364804 Setting up VGA for PCI: 00:02.0
1120 12:44:44.371207 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1121 12:44:44.374643 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1122 12:44:44.377710 Allocating resources...
1123 12:44:44.380792 Reading resources...
1124 12:44:44.384637 Root Device read_resources bus 0 link: 0
1125 12:44:44.387704 DOMAIN: 0000 read_resources bus 0 link: 0
1126 12:44:44.393968 PCI: 00:04.0 read_resources bus 1 link: 0
1127 12:44:44.397289 PCI: 00:04.0 read_resources bus 1 link: 0 done
1128 12:44:44.403834 PCI: 00:0d.0 read_resources bus 0 link: 0
1129 12:44:44.407256 USB0 port 0 read_resources bus 0 link: 0
1130 12:44:44.413957 USB0 port 0 read_resources bus 0 link: 0 done
1131 12:44:44.416980 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1132 12:44:44.423923 PCI: 00:14.0 read_resources bus 0 link: 0
1133 12:44:44.426961 USB0 port 0 read_resources bus 0 link: 0
1134 12:44:44.433454 USB0 port 0 read_resources bus 0 link: 0 done
1135 12:44:44.436923 PCI: 00:14.0 read_resources bus 0 link: 0 done
1136 12:44:44.443920 PCI: 00:14.3 read_resources bus 0 link: 0
1137 12:44:44.446998 PCI: 00:14.3 read_resources bus 0 link: 0 done
1138 12:44:44.450203 PCI: 00:15.0 read_resources bus 0 link: 0
1139 12:44:44.457628 PCI: 00:15.0 read_resources bus 0 link: 0 done
1140 12:44:44.460975 PCI: 00:15.1 read_resources bus 0 link: 0
1141 12:44:44.467449 PCI: 00:15.1 read_resources bus 0 link: 0 done
1142 12:44:44.470679 PCI: 00:19.1 read_resources bus 0 link: 0
1143 12:44:44.477779 PCI: 00:19.1 read_resources bus 0 link: 0 done
1144 12:44:44.481057 PCI: 00:1d.0 read_resources bus 1 link: 0
1145 12:44:44.487901 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1146 12:44:44.490927 PCI: 00:1e.2 read_resources bus 2 link: 0
1147 12:44:44.498082 PCI: 00:1e.2 read_resources bus 2 link: 0 done
1148 12:44:44.501493 PCI: 00:1e.3 read_resources bus 3 link: 0
1149 12:44:44.507769 PCI: 00:1e.3 read_resources bus 3 link: 0 done
1150 12:44:44.511618 PCI: 00:1f.0 read_resources bus 0 link: 0
1151 12:44:44.518182 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1152 12:44:44.521168 PCI: 00:1f.2 read_resources bus 0 link: 0
1153 12:44:44.524281 GENERIC: 0.0 read_resources bus 0 link: 0
1154 12:44:44.531211 GENERIC: 0.0 read_resources bus 0 link: 0 done
1155 12:44:44.534934 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1156 12:44:44.541956 DOMAIN: 0000 read_resources bus 0 link: 0 done
1157 12:44:44.545226 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1158 12:44:44.551439 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1159 12:44:44.554619 Root Device read_resources bus 0 link: 0 done
1160 12:44:44.557846 Done reading resources.
1161 12:44:44.564517 Show resources in subtree (Root Device)...After reading.
1162 12:44:44.568425 Root Device child on link 0 DOMAIN: 0000
1163 12:44:44.571383 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1164 12:44:44.581276 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1165 12:44:44.591528 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1166 12:44:44.594778 PCI: 00:00.0
1167 12:44:44.604296 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1168 12:44:44.611050 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1169 12:44:44.620885 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1170 12:44:44.630686 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1171 12:44:44.640666 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1172 12:44:44.651155 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1173 12:44:44.660693 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1174 12:44:44.668095 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1175 12:44:44.677563 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1176 12:44:44.687430 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1177 12:44:44.697061 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1178 12:44:44.707064 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1179 12:44:44.716999 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1180 12:44:44.723763 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1181 12:44:44.733879 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1182 12:44:44.743442 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1183 12:44:44.753464 PCI: 00:00.0 resource base 100000000 size 380400000 align 0 gran 0 limit 0 flags e0004200 index 10
1184 12:44:44.763948 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1185 12:44:44.773524 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1186 12:44:44.783661 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1187 12:44:44.783760 PCI: 00:02.0
1188 12:44:44.793559 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1189 12:44:44.803152 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1190 12:44:44.813188 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1191 12:44:44.817028 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1192 12:44:44.826322 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1193 12:44:44.830018 GENERIC: 0.0
1194 12:44:44.830133 PCI: 00:05.0
1195 12:44:44.840208 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1196 12:44:44.846010 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1197 12:44:44.846125 GENERIC: 0.0
1198 12:44:44.849896 PCI: 00:08.0
1199 12:44:44.859248 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1200 12:44:44.859349 PCI: 00:0a.0
1201 12:44:44.866200 PCI: 00:0d.0 child on link 0 USB0 port 0
1202 12:44:44.876253 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1203 12:44:44.879498 USB0 port 0 child on link 0 USB3 port 0
1204 12:44:44.879616 USB3 port 0
1205 12:44:44.882740 USB3 port 1
1206 12:44:44.885873 USB3 port 2
1207 12:44:44.885958 USB3 port 3
1208 12:44:44.889284 PCI: 00:14.0 child on link 0 USB0 port 0
1209 12:44:44.899583 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1210 12:44:44.906010 USB0 port 0 child on link 0 USB2 port 0
1211 12:44:44.906123 USB2 port 0
1212 12:44:44.909192 USB2 port 1
1213 12:44:44.909279 USB2 port 2
1214 12:44:44.912304 USB2 port 3
1215 12:44:44.912392 USB2 port 4
1216 12:44:44.915478 USB2 port 5
1217 12:44:44.915566 USB2 port 6
1218 12:44:44.919439 USB2 port 7
1219 12:44:44.922351 USB2 port 8
1220 12:44:44.922438 USB2 port 9
1221 12:44:44.926038 USB3 port 0
1222 12:44:44.926166 USB3 port 1
1223 12:44:44.929193 USB3 port 2
1224 12:44:44.929281 USB3 port 3
1225 12:44:44.932411 PCI: 00:14.2
1226 12:44:44.942173 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1227 12:44:44.952494 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1228 12:44:44.955637 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1229 12:44:44.965402 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1230 12:44:44.969091 GENERIC: 0.0
1231 12:44:44.972388 PCI: 00:15.0 child on link 0 I2C: 00:1a
1232 12:44:44.981785 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1233 12:44:44.981881 I2C: 00:1a
1234 12:44:44.985692 I2C: 00:31
1235 12:44:44.985780 I2C: 00:32
1236 12:44:44.992014 PCI: 00:15.1 child on link 0 I2C: 00:10
1237 12:44:45.002324 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1238 12:44:45.002413 I2C: 00:10
1239 12:44:45.005697 PCI: 00:15.2
1240 12:44:45.015363 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1241 12:44:45.015450 PCI: 00:15.3
1242 12:44:45.024884 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1243 12:44:45.028271 PCI: 00:16.0
1244 12:44:45.038662 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1245 12:44:45.038781 PCI: 00:19.0
1246 12:44:45.041827 PCI: 00:19.1 child on link 0 I2C: 00:15
1247 12:44:45.051768 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1248 12:44:45.054778 I2C: 00:15
1249 12:44:45.058379 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1250 12:44:45.068415 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1251 12:44:45.078343 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1252 12:44:45.087940 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1253 12:44:45.088037 GENERIC: 0.0
1254 12:44:45.091228 PCI: 01:00.0
1255 12:44:45.101492 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1256 12:44:45.111219 PCI: 01:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 20
1257 12:44:45.111401 PCI: 00:1e.0
1258 12:44:45.124706 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1259 12:44:45.127896 PCI: 00:1e.2 child on link 0 SPI: 00
1260 12:44:45.137881 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1261 12:44:45.138024 SPI: 00
1262 12:44:45.141512 PCI: 00:1e.3 child on link 0 SPI: 00
1263 12:44:45.150858 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1264 12:44:45.154547 SPI: 00
1265 12:44:45.157747 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1266 12:44:45.167752 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1267 12:44:45.167874 PNP: 0c09.0
1268 12:44:45.177767 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1269 12:44:45.180703 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1270 12:44:45.190818 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1271 12:44:45.200903 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1272 12:44:45.204150 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1273 12:44:45.207577 GENERIC: 0.0
1274 12:44:45.207670 GENERIC: 1.0
1275 12:44:45.210614 PCI: 00:1f.3
1276 12:44:45.220391 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1277 12:44:45.230752 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1278 12:44:45.230876 PCI: 00:1f.5
1279 12:44:45.240625 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1280 12:44:45.243775 CPU_CLUSTER: 0 child on link 0 APIC: 00
1281 12:44:45.247420 APIC: 00
1282 12:44:45.247587 APIC: 01
1283 12:44:45.250493 APIC: 04
1284 12:44:45.250581 APIC: 07
1285 12:44:45.250650 APIC: 02
1286 12:44:45.253495 APIC: 05
1287 12:44:45.253583 APIC: 06
1288 12:44:45.253652 APIC: 03
1289 12:44:45.263555 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1290 12:44:45.267371 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
1291 12:44:45.274034 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1292 12:44:45.280464 PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1293 12:44:45.283638 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1294 12:44:45.290559 PCI: 01:00.0 20 * [0x4000 - 0x40ff] mem
1295 12:44:45.297073 PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1296 12:44:45.303597 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1297 12:44:45.310616 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1298 12:44:45.320275 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1299 12:44:45.323499 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1300 12:44:45.333832 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1301 12:44:45.340179 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1302 12:44:45.346973 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1303 12:44:45.350103 DOMAIN: 0000: Resource ranges:
1304 12:44:45.353669 * Base: 1000, Size: 800, Tag: 100
1305 12:44:45.356726 * Base: 1900, Size: e700, Tag: 100
1306 12:44:45.363231 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1307 12:44:45.370340 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1308 12:44:45.376493 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1309 12:44:45.383160 update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
1310 12:44:45.393394 update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed)
1311 12:44:45.399643 update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
1312 12:44:45.406240 update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
1313 12:44:45.416901 update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
1314 12:44:45.423238 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
1315 12:44:45.429609 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
1316 12:44:45.439911 update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
1317 12:44:45.446509 update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
1318 12:44:45.452694 update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
1319 12:44:45.462948 update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
1320 12:44:45.469133 update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
1321 12:44:45.475810 update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
1322 12:44:45.486017 update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
1323 12:44:45.492297 update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
1324 12:44:45.499369 update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed)
1325 12:44:45.509510 update_constraints: PCI: 00:00.0 10 base 100000000 limit 4803fffff mem (fixed)
1326 12:44:45.515584 update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
1327 12:44:45.522218 update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
1328 12:44:45.532524 update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed)
1329 12:44:45.538919 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1330 12:44:45.545724 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1331 12:44:45.549239 DOMAIN: 0000: Resource ranges:
1332 12:44:45.555597 * Base: 7fc00000, Size: 40400000, Tag: 200
1333 12:44:45.558660 * Base: d0000000, Size: 28000000, Tag: 200
1334 12:44:45.562385 * Base: fa000000, Size: 1000000, Tag: 200
1335 12:44:45.565375 * Base: fb001000, Size: 2fff000, Tag: 200
1336 12:44:45.571896 * Base: fe010000, Size: 2e000, Tag: 200
1337 12:44:45.575039 * Base: fe03f000, Size: d41000, Tag: 200
1338 12:44:45.578693 * Base: fed88000, Size: 8000, Tag: 200
1339 12:44:45.582005 * Base: fed93000, Size: d000, Tag: 200
1340 12:44:45.588683 * Base: feda2000, Size: 1e000, Tag: 200
1341 12:44:45.591746 * Base: fede0000, Size: 1220000, Tag: 200
1342 12:44:45.595147 * Base: 480400000, Size: 7b7fc00000, Tag: 100200
1343 12:44:45.605449 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
1344 12:44:45.611644 PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
1345 12:44:45.618591 PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
1346 12:44:45.624945 PCI: 00:1d.0 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
1347 12:44:45.632081 PCI: 00:1f.3 20 * [0x7fd00000 - 0x7fdfffff] limit: 7fdfffff mem
1348 12:44:45.638219 PCI: 00:04.0 10 * [0x7fe00000 - 0x7fe1ffff] limit: 7fe1ffff mem
1349 12:44:45.645274 PCI: 00:0d.0 10 * [0x7fe20000 - 0x7fe2ffff] limit: 7fe2ffff mem
1350 12:44:45.651821 PCI: 00:14.0 10 * [0x7fe30000 - 0x7fe3ffff] limit: 7fe3ffff mem
1351 12:44:45.658207 PCI: 00:14.2 10 * [0x7fe40000 - 0x7fe43fff] limit: 7fe43fff mem
1352 12:44:45.664546 PCI: 00:14.3 10 * [0x7fe44000 - 0x7fe47fff] limit: 7fe47fff mem
1353 12:44:45.671207 PCI: 00:1f.3 10 * [0x7fe48000 - 0x7fe4bfff] limit: 7fe4bfff mem
1354 12:44:45.677888 PCI: 00:08.0 10 * [0x7fe4c000 - 0x7fe4cfff] limit: 7fe4cfff mem
1355 12:44:45.684596 PCI: 00:14.2 18 * [0x7fe4d000 - 0x7fe4dfff] limit: 7fe4dfff mem
1356 12:44:45.691364 PCI: 00:15.0 10 * [0x7fe4e000 - 0x7fe4efff] limit: 7fe4efff mem
1357 12:44:45.697977 PCI: 00:15.1 10 * [0x7fe4f000 - 0x7fe4ffff] limit: 7fe4ffff mem
1358 12:44:45.704371 PCI: 00:15.2 10 * [0x7fe50000 - 0x7fe50fff] limit: 7fe50fff mem
1359 12:44:45.711478 PCI: 00:15.3 10 * [0x7fe51000 - 0x7fe51fff] limit: 7fe51fff mem
1360 12:44:45.717721 PCI: 00:16.0 10 * [0x7fe52000 - 0x7fe52fff] limit: 7fe52fff mem
1361 12:44:45.724793 PCI: 00:19.1 10 * [0x7fe53000 - 0x7fe53fff] limit: 7fe53fff mem
1362 12:44:45.731192 PCI: 00:1e.2 10 * [0x7fe54000 - 0x7fe54fff] limit: 7fe54fff mem
1363 12:44:45.734561 PCI: 00:1e.3 10 * [0x7fe55000 - 0x7fe55fff] limit: 7fe55fff mem
1364 12:44:45.741043 PCI: 00:1f.5 10 * [0x7fe56000 - 0x7fe56fff] limit: 7fe56fff mem
1365 12:44:45.751119 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1366 12:44:45.757513 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff
1367 12:44:45.760827 PCI: 00:1d.0: Resource ranges:
1368 12:44:45.764174 * Base: 7fc00000, Size: 100000, Tag: 200
1369 12:44:45.771140 PCI: 01:00.0 10 * [0x7fc00000 - 0x7fc03fff] limit: 7fc03fff mem
1370 12:44:45.777780 PCI: 01:00.0 20 * [0x7fc04000 - 0x7fc040ff] limit: 7fc040ff mem
1371 12:44:45.787545 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff done
1372 12:44:45.794249 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1373 12:44:45.797161 Root Device assign_resources, bus 0 link: 0
1374 12:44:45.803811 DOMAIN: 0000 assign_resources, bus 0 link: 0
1375 12:44:45.810774 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
1376 12:44:45.820510 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
1377 12:44:45.827563 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1378 12:44:45.837073 PCI: 00:04.0 10 <- [0x007fe00000 - 0x007fe1ffff] size 0x00020000 gran 0x11 mem64
1379 12:44:45.840868 PCI: 00:04.0 assign_resources, bus 1 link: 0
1380 12:44:45.843925 PCI: 00:04.0 assign_resources, bus 1 link: 0
1381 12:44:45.854078 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64
1382 12:44:45.860376 PCI: 00:08.0 10 <- [0x007fe4c000 - 0x007fe4cfff] size 0x00001000 gran 0x0c mem64
1383 12:44:45.870748 PCI: 00:0d.0 10 <- [0x007fe20000 - 0x007fe2ffff] size 0x00010000 gran 0x10 mem64
1384 12:44:45.873946 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1385 12:44:45.880414 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1386 12:44:45.887169 PCI: 00:14.0 10 <- [0x007fe30000 - 0x007fe3ffff] size 0x00010000 gran 0x10 mem64
1387 12:44:45.893842 PCI: 00:14.0 assign_resources, bus 0 link: 0
1388 12:44:45.896965 PCI: 00:14.0 assign_resources, bus 0 link: 0
1389 12:44:45.903755 PCI: 00:14.2 10 <- [0x007fe40000 - 0x007fe43fff] size 0x00004000 gran 0x0e mem64
1390 12:44:45.913488 PCI: 00:14.2 18 <- [0x007fe4d000 - 0x007fe4dfff] size 0x00001000 gran 0x0c mem64
1391 12:44:45.920057 PCI: 00:14.3 10 <- [0x007fe44000 - 0x007fe47fff] size 0x00004000 gran 0x0e mem64
1392 12:44:45.926400 PCI: 00:14.3 assign_resources, bus 0 link: 0
1393 12:44:45.929775 PCI: 00:14.3 assign_resources, bus 0 link: 0
1394 12:44:45.939877 PCI: 00:15.0 10 <- [0x007fe4e000 - 0x007fe4efff] size 0x00001000 gran 0x0c mem64
1395 12:44:45.943092 PCI: 00:15.0 assign_resources, bus 0 link: 0
1396 12:44:45.946590 PCI: 00:15.0 assign_resources, bus 0 link: 0
1397 12:44:45.956431 PCI: 00:15.1 10 <- [0x007fe4f000 - 0x007fe4ffff] size 0x00001000 gran 0x0c mem64
1398 12:44:45.959370 PCI: 00:15.1 assign_resources, bus 0 link: 0
1399 12:44:45.966345 PCI: 00:15.1 assign_resources, bus 0 link: 0
1400 12:44:45.972867 PCI: 00:15.2 10 <- [0x007fe50000 - 0x007fe50fff] size 0x00001000 gran 0x0c mem64
1401 12:44:45.983051 PCI: 00:15.3 10 <- [0x007fe51000 - 0x007fe51fff] size 0x00001000 gran 0x0c mem64
1402 12:44:45.989271 PCI: 00:16.0 10 <- [0x007fe52000 - 0x007fe52fff] size 0x00001000 gran 0x0c mem64
1403 12:44:45.999246 PCI: 00:19.1 10 <- [0x007fe53000 - 0x007fe53fff] size 0x00001000 gran 0x0c mem64
1404 12:44:46.002940 PCI: 00:19.1 assign_resources, bus 0 link: 0
1405 12:44:46.005774 PCI: 00:19.1 assign_resources, bus 0 link: 0
1406 12:44:46.016099 PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1407 12:44:46.025763 PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1408 12:44:46.035512 PCI: 00:1d.0 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 bus 01 mem
1409 12:44:46.039212 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1410 12:44:46.045593 PCI: 01:00.0 10 <- [0x007fc00000 - 0x007fc03fff] size 0x00004000 gran 0x0e mem64
1411 12:44:46.055496 PCI: 01:00.0 20 <- [0x007fc04000 - 0x007fc040ff] size 0x00000100 gran 0x08 mem64
1412 12:44:46.058940 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1413 12:44:46.068946 PCI: 00:1e.2 10 <- [0x007fe54000 - 0x007fe54fff] size 0x00001000 gran 0x0c mem64
1414 12:44:46.072173 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1415 12:44:46.078551 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1416 12:44:46.085635 PCI: 00:1e.3 10 <- [0x007fe55000 - 0x007fe55fff] size 0x00001000 gran 0x0c mem64
1417 12:44:46.088783 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1418 12:44:46.095615 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1419 12:44:46.098650 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1420 12:44:46.105187 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1421 12:44:46.108799 LPC: Trying to open IO window from 800 size 1ff
1422 12:44:46.118584 PCI: 00:1f.3 10 <- [0x007fe48000 - 0x007fe4bfff] size 0x00004000 gran 0x0e mem64
1423 12:44:46.125029 PCI: 00:1f.3 20 <- [0x007fd00000 - 0x007fdfffff] size 0x00100000 gran 0x14 mem64
1424 12:44:46.135088 PCI: 00:1f.5 10 <- [0x007fe56000 - 0x007fe56fff] size 0x00001000 gran 0x0c mem
1425 12:44:46.138202 DOMAIN: 0000 assign_resources, bus 0 link: 0
1426 12:44:46.142014 Root Device assign_resources, bus 0 link: 0
1427 12:44:46.145185 Done setting resources.
1428 12:44:46.151536 Show resources in subtree (Root Device)...After assigning values.
1429 12:44:46.154745 Root Device child on link 0 DOMAIN: 0000
1430 12:44:46.161514 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1431 12:44:46.171734 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1432 12:44:46.181342 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1433 12:44:46.181428 PCI: 00:00.0
1434 12:44:46.191543 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1435 12:44:46.201466 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1436 12:44:46.211322 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1437 12:44:46.218199 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1438 12:44:46.227923 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1439 12:44:46.237755 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1440 12:44:46.247971 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1441 12:44:46.257994 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1442 12:44:46.268119 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1443 12:44:46.274371 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1444 12:44:46.284078 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1445 12:44:46.294200 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1446 12:44:46.304265 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1447 12:44:46.313855 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1448 12:44:46.320393 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1449 12:44:46.330490 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1450 12:44:46.340348 PCI: 00:00.0 resource base 100000000 size 380400000 align 0 gran 0 limit 0 flags e0004200 index 10
1451 12:44:46.350593 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1452 12:44:46.360759 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1453 12:44:46.370250 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1454 12:44:46.370410 PCI: 00:02.0
1455 12:44:46.383675 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10
1456 12:44:46.393859 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18
1457 12:44:46.403472 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1458 12:44:46.406736 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1459 12:44:46.417004 PCI: 00:04.0 resource base 7fe00000 size 20000 align 17 gran 17 limit 7fe1ffff flags 60000201 index 10
1460 12:44:46.420170 GENERIC: 0.0
1461 12:44:46.420262 PCI: 00:05.0
1462 12:44:46.429783 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10
1463 12:44:46.436493 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1464 12:44:46.436592 GENERIC: 0.0
1465 12:44:46.440419 PCI: 00:08.0
1466 12:44:46.450220 PCI: 00:08.0 resource base 7fe4c000 size 1000 align 12 gran 12 limit 7fe4cfff flags 60000201 index 10
1467 12:44:46.450318 PCI: 00:0a.0
1468 12:44:46.456071 PCI: 00:0d.0 child on link 0 USB0 port 0
1469 12:44:46.466821 PCI: 00:0d.0 resource base 7fe20000 size 10000 align 16 gran 16 limit 7fe2ffff flags 60000201 index 10
1470 12:44:46.469574 USB0 port 0 child on link 0 USB3 port 0
1471 12:44:46.472610 USB3 port 0
1472 12:44:46.472689 USB3 port 1
1473 12:44:46.476440 USB3 port 2
1474 12:44:46.476515 USB3 port 3
1475 12:44:46.482906 PCI: 00:14.0 child on link 0 USB0 port 0
1476 12:44:46.492843 PCI: 00:14.0 resource base 7fe30000 size 10000 align 16 gran 16 limit 7fe3ffff flags 60000201 index 10
1477 12:44:46.496038 USB0 port 0 child on link 0 USB2 port 0
1478 12:44:46.499190 USB2 port 0
1479 12:44:46.499289 USB2 port 1
1480 12:44:46.503284 USB2 port 2
1481 12:44:46.503373 USB2 port 3
1482 12:44:46.506289 USB2 port 4
1483 12:44:46.506376 USB2 port 5
1484 12:44:46.509552 USB2 port 6
1485 12:44:46.509638 USB2 port 7
1486 12:44:46.512684 USB2 port 8
1487 12:44:46.512785 USB2 port 9
1488 12:44:46.516313 USB3 port 0
1489 12:44:46.519006 USB3 port 1
1490 12:44:46.519154 USB3 port 2
1491 12:44:46.522468 USB3 port 3
1492 12:44:46.522585 PCI: 00:14.2
1493 12:44:46.532750 PCI: 00:14.2 resource base 7fe40000 size 4000 align 14 gran 14 limit 7fe43fff flags 60000201 index 10
1494 12:44:46.542479 PCI: 00:14.2 resource base 7fe4d000 size 1000 align 12 gran 12 limit 7fe4dfff flags 60000201 index 18
1495 12:44:46.549182 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1496 12:44:46.558983 PCI: 00:14.3 resource base 7fe44000 size 4000 align 14 gran 14 limit 7fe47fff flags 60000201 index 10
1497 12:44:46.559087 GENERIC: 0.0
1498 12:44:46.566162 PCI: 00:15.0 child on link 0 I2C: 00:1a
1499 12:44:46.575351 PCI: 00:15.0 resource base 7fe4e000 size 1000 align 12 gran 12 limit 7fe4efff flags 60000201 index 10
1500 12:44:46.575467 I2C: 00:1a
1501 12:44:46.578723 I2C: 00:31
1502 12:44:46.578811 I2C: 00:32
1503 12:44:46.582350 PCI: 00:15.1 child on link 0 I2C: 00:10
1504 12:44:46.595546 PCI: 00:15.1 resource base 7fe4f000 size 1000 align 12 gran 12 limit 7fe4ffff flags 60000201 index 10
1505 12:44:46.595658 I2C: 00:10
1506 12:44:46.598710 PCI: 00:15.2
1507 12:44:46.608484 PCI: 00:15.2 resource base 7fe50000 size 1000 align 12 gran 12 limit 7fe50fff flags 60000201 index 10
1508 12:44:46.608580 PCI: 00:15.3
1509 12:44:46.618795 PCI: 00:15.3 resource base 7fe51000 size 1000 align 12 gran 12 limit 7fe51fff flags 60000201 index 10
1510 12:44:46.621957 PCI: 00:16.0
1511 12:44:46.632166 PCI: 00:16.0 resource base 7fe52000 size 1000 align 12 gran 12 limit 7fe52fff flags 60000201 index 10
1512 12:44:46.632274 PCI: 00:19.0
1513 12:44:46.638375 PCI: 00:19.1 child on link 0 I2C: 00:15
1514 12:44:46.649007 PCI: 00:19.1 resource base 7fe53000 size 1000 align 12 gran 12 limit 7fe53fff flags 60000201 index 10
1515 12:44:46.649112 I2C: 00:15
1516 12:44:46.655472 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1517 12:44:46.662078 PCI: 00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1518 12:44:46.675455 PCI: 00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1519 12:44:46.685550 PCI: 00:1d.0 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60080202 index 20
1520 12:44:46.688118 GENERIC: 0.0
1521 12:44:46.688216 PCI: 01:00.0
1522 12:44:46.698296 PCI: 01:00.0 resource base 7fc00000 size 4000 align 14 gran 14 limit 7fc03fff flags 60000201 index 10
1523 12:44:46.708209 PCI: 01:00.0 resource base 7fc04000 size 100 align 12 gran 8 limit 7fc040ff flags 60000201 index 20
1524 12:44:46.711497 PCI: 00:1e.0
1525 12:44:46.721701 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1526 12:44:46.724973 PCI: 00:1e.2 child on link 0 SPI: 00
1527 12:44:46.738286 PCI: 00:1e.2 resource base 7fe54000 size 1000 align 12 gran 12 limit 7fe54fff flags 60000201 index 10
1528 12:44:46.738389 SPI: 00
1529 12:44:46.741826 PCI: 00:1e.3 child on link 0 SPI: 00
1530 12:44:46.751397 PCI: 00:1e.3 resource base 7fe55000 size 1000 align 12 gran 12 limit 7fe55fff flags 60000201 index 10
1531 12:44:46.754961 SPI: 00
1532 12:44:46.758022 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1533 12:44:46.768185 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1534 12:44:46.768280 PNP: 0c09.0
1535 12:44:46.777954 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1536 12:44:46.781248 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1537 12:44:46.791260 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1538 12:44:46.801076 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1539 12:44:46.804212 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1540 12:44:46.808075 GENERIC: 0.0
1541 12:44:46.808167 GENERIC: 1.0
1542 12:44:46.810998 PCI: 00:1f.3
1543 12:44:46.820618 PCI: 00:1f.3 resource base 7fe48000 size 4000 align 14 gran 14 limit 7fe4bfff flags 60000201 index 10
1544 12:44:46.830891 PCI: 00:1f.3 resource base 7fd00000 size 100000 align 20 gran 20 limit 7fdfffff flags 60000201 index 20
1545 12:44:46.834005 PCI: 00:1f.5
1546 12:44:46.844527 PCI: 00:1f.5 resource base 7fe56000 size 1000 align 12 gran 12 limit 7fe56fff flags 60000200 index 10
1547 12:44:46.847472 CPU_CLUSTER: 0 child on link 0 APIC: 00
1548 12:44:46.847592 APIC: 00
1549 12:44:46.851017 APIC: 01
1550 12:44:46.851102 APIC: 04
1551 12:44:46.851198 APIC: 07
1552 12:44:46.854154 APIC: 02
1553 12:44:46.854244 APIC: 05
1554 12:44:46.857255 APIC: 06
1555 12:44:46.857338 APIC: 03
1556 12:44:46.860628 Done allocating resources.
1557 12:44:46.867210 BS: BS_DEV_RESOURCES run times (exec / console): 26 / 2475 ms
1558 12:44:46.870884 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
1559 12:44:46.877282 Configure GPIOs for I2S audio on UP4.
1560 12:44:46.883954 BS: BS_DEV_ENABLE entry times (exec / console): 2 / 9 ms
1561 12:44:46.884059 Enabling resources...
1562 12:44:46.890736 PCI: 00:00.0 subsystem <- 8086/9a12
1563 12:44:46.890828 PCI: 00:00.0 cmd <- 06
1564 12:44:46.894039 PCI: 00:02.0 subsystem <- 8086/9a40
1565 12:44:46.897155 PCI: 00:02.0 cmd <- 03
1566 12:44:46.901035 PCI: 00:04.0 subsystem <- 8086/9a03
1567 12:44:46.904227 PCI: 00:04.0 cmd <- 02
1568 12:44:46.907468 PCI: 00:05.0 subsystem <- 8086/9a19
1569 12:44:46.910577 PCI: 00:05.0 cmd <- 02
1570 12:44:46.913760 PCI: 00:08.0 subsystem <- 8086/9a11
1571 12:44:46.917332 PCI: 00:08.0 cmd <- 06
1572 12:44:46.920450 PCI: 00:0d.0 subsystem <- 8086/9a13
1573 12:44:46.923544 PCI: 00:0d.0 cmd <- 02
1574 12:44:46.926912 PCI: 00:14.0 subsystem <- 8086/a0ed
1575 12:44:46.930088 PCI: 00:14.0 cmd <- 02
1576 12:44:46.933424 PCI: 00:14.2 subsystem <- 8086/a0ef
1577 12:44:46.933529 PCI: 00:14.2 cmd <- 02
1578 12:44:46.940297 PCI: 00:14.3 subsystem <- 8086/a0f0
1579 12:44:46.940409 PCI: 00:14.3 cmd <- 02
1580 12:44:46.943445 PCI: 00:15.0 subsystem <- 8086/a0e8
1581 12:44:46.947098 PCI: 00:15.0 cmd <- 02
1582 12:44:46.950216 PCI: 00:15.1 subsystem <- 8086/a0e9
1583 12:44:46.953799 PCI: 00:15.1 cmd <- 02
1584 12:44:46.956826 PCI: 00:15.2 subsystem <- 8086/a0ea
1585 12:44:46.959815 PCI: 00:15.2 cmd <- 02
1586 12:44:46.963597 PCI: 00:15.3 subsystem <- 8086/a0eb
1587 12:44:46.966632 PCI: 00:15.3 cmd <- 02
1588 12:44:46.969720 PCI: 00:16.0 subsystem <- 8086/a0e0
1589 12:44:46.973273 PCI: 00:16.0 cmd <- 02
1590 12:44:46.976913 PCI: 00:19.1 subsystem <- 8086/a0c6
1591 12:44:46.979819 PCI: 00:19.1 cmd <- 02
1592 12:44:46.983032 PCI: 00:1d.0 bridge ctrl <- 0013
1593 12:44:46.986420 PCI: 00:1d.0 subsystem <- 8086/a0b0
1594 12:44:46.986533 PCI: 00:1d.0 cmd <- 06
1595 12:44:46.993121 PCI: 00:1e.0 subsystem <- 8086/a0a8
1596 12:44:46.993242 PCI: 00:1e.0 cmd <- 06
1597 12:44:46.996411 PCI: 00:1e.2 subsystem <- 8086/a0aa
1598 12:44:46.999602 PCI: 00:1e.2 cmd <- 06
1599 12:44:47.002910 PCI: 00:1e.3 subsystem <- 8086/a0ab
1600 12:44:47.006167 PCI: 00:1e.3 cmd <- 02
1601 12:44:47.009975 PCI: 00:1f.0 subsystem <- 8086/a087
1602 12:44:47.013195 PCI: 00:1f.0 cmd <- 407
1603 12:44:47.016303 PCI: 00:1f.3 subsystem <- 8086/a0c8
1604 12:44:47.020138 PCI: 00:1f.3 cmd <- 02
1605 12:44:47.023304 PCI: 00:1f.5 subsystem <- 8086/a0a4
1606 12:44:47.026339 PCI: 00:1f.5 cmd <- 406
1607 12:44:47.029531 PCI: 01:00.0 cmd <- 02
1608 12:44:47.033934 done.
1609 12:44:47.037039 BS: BS_DEV_ENABLE run times (exec / console): 10 / 140 ms
1610 12:44:47.040318 Initializing devices...
1611 12:44:47.044337 Root Device init
1612 12:44:47.047421 Chrome EC: Set SMI mask to 0x0000000000000000
1613 12:44:47.054014 Chrome EC: clear events_b mask to 0x0000000000000000
1614 12:44:47.060117 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1615 12:44:47.063720 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001800101e
1616 12:44:47.070729 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001800101e
1617 12:44:47.076955 Chrome EC: Set WAKE mask to 0x0000000000000000
1618 12:44:47.080656 fw_config match found: DB_USB=USB3_ACTIVE
1619 12:44:47.087403 Configure Right Type-C port orientation for retimer
1620 12:44:47.090365 Root Device init finished in 43 msecs
1621 12:44:47.093959 PCI: 00:00.0 init
1622 12:44:47.097036 CPU TDP = 9 Watts
1623 12:44:47.097124 CPU PL1 = 9 Watts
1624 12:44:47.100669 CPU PL2 = 40 Watts
1625 12:44:47.100755 CPU PL4 = 83 Watts
1626 12:44:47.107093 PCI: 00:00.0 init finished in 8 msecs
1627 12:44:47.107189 PCI: 00:02.0 init
1628 12:44:47.110158 GMA: Found VBT in CBFS
1629 12:44:47.113992 GMA: Found valid VBT in CBFS
1630 12:44:47.120356 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1631 12:44:47.126814 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
1632 12:44:47.130399 PCI: 00:02.0 init finished in 18 msecs
1633 12:44:47.133608 PCI: 00:05.0 init
1634 12:44:47.136883 PCI: 00:05.0 init finished in 0 msecs
1635 12:44:47.139888 PCI: 00:08.0 init
1636 12:44:47.143731 PCI: 00:08.0 init finished in 0 msecs
1637 12:44:47.147100 PCI: 00:14.0 init
1638 12:44:47.150184 PCI: 00:14.0 init finished in 0 msecs
1639 12:44:47.150299 PCI: 00:14.2 init
1640 12:44:47.156522 PCI: 00:14.2 init finished in 0 msecs
1641 12:44:47.156610 PCI: 00:15.0 init
1642 12:44:47.160234 I2C bus 0 version 0x3230302a
1643 12:44:47.163138 DW I2C bus 0 at 0x7fe4e000 (400 KHz)
1644 12:44:47.170015 PCI: 00:15.0 init finished in 6 msecs
1645 12:44:47.170145 PCI: 00:15.1 init
1646 12:44:47.173027 I2C bus 1 version 0x3230302a
1647 12:44:47.176544 DW I2C bus 1 at 0x7fe4f000 (400 KHz)
1648 12:44:47.179402 PCI: 00:15.1 init finished in 6 msecs
1649 12:44:47.183191 PCI: 00:15.2 init
1650 12:44:47.186313 I2C bus 2 version 0x3230302a
1651 12:44:47.190009 DW I2C bus 2 at 0x7fe50000 (400 KHz)
1652 12:44:47.192901 PCI: 00:15.2 init finished in 6 msecs
1653 12:44:47.196416 PCI: 00:15.3 init
1654 12:44:47.199433 I2C bus 3 version 0x3230302a
1655 12:44:47.203031 DW I2C bus 3 at 0x7fe51000 (400 KHz)
1656 12:44:47.206483 PCI: 00:15.3 init finished in 6 msecs
1657 12:44:47.209668 PCI: 00:16.0 init
1658 12:44:47.212831 PCI: 00:16.0 init finished in 0 msecs
1659 12:44:47.216150 PCI: 00:19.1 init
1660 12:44:47.216240 I2C bus 5 version 0x3230302a
1661 12:44:47.223207 DW I2C bus 5 at 0x7fe53000 (400 KHz)
1662 12:44:47.226420 PCI: 00:19.1 init finished in 6 msecs
1663 12:44:47.226523 PCI: 00:1d.0 init
1664 12:44:47.229566 Initializing PCH PCIe bridge.
1665 12:44:47.232706 PCI: 00:1d.0 init finished in 3 msecs
1666 12:44:47.236997 PCI: 00:1f.0 init
1667 12:44:47.240269 IOAPIC: Initializing IOAPIC at 0xfec00000
1668 12:44:47.246872 IOAPIC: Bootstrap Processor Local APIC = 0x00
1669 12:44:47.246970 IOAPIC: ID = 0x02
1670 12:44:47.250738 IOAPIC: Dumping registers
1671 12:44:47.253950 reg 0x0000: 0x02000000
1672 12:44:47.257157 reg 0x0001: 0x00770020
1673 12:44:47.257250 reg 0x0002: 0x00000000
1674 12:44:47.263542 PCI: 00:1f.0 init finished in 21 msecs
1675 12:44:47.263666 PCI: 00:1f.2 init
1676 12:44:47.266646 Disabling ACPI via APMC.
1677 12:44:47.271406 APMC done.
1678 12:44:47.275021 PCI: 00:1f.2 init finished in 6 msecs
1679 12:44:47.286508 PCI: 01:00.0 init
1680 12:44:47.289908 PCI: 01:00.0 init finished in 0 msecs
1681 12:44:47.293151 PNP: 0c09.0 init
1682 12:44:47.299702 Google Chrome EC uptime: 8.340 seconds
1683 12:44:47.303291 Google Chrome AP resets since EC boot: 1
1684 12:44:47.306802 Google Chrome most recent AP reset causes:
1685 12:44:47.309762 0.453: 32775 shutdown: entering G3
1686 12:44:47.316389 Google Chrome EC reset flags at last EC boot: reset-pin | sysjump
1687 12:44:47.319639 PNP: 0c09.0 init finished in 24 msecs
1688 12:44:47.326711 Devices initialized
1689 12:44:47.329882 Show all devs... After init.
1690 12:44:47.333127 Root Device: enabled 1
1691 12:44:47.333292 DOMAIN: 0000: enabled 1
1692 12:44:47.336486 CPU_CLUSTER: 0: enabled 1
1693 12:44:47.339641 PCI: 00:00.0: enabled 1
1694 12:44:47.343278 PCI: 00:02.0: enabled 1
1695 12:44:47.343407 PCI: 00:04.0: enabled 1
1696 12:44:47.346590 PCI: 00:05.0: enabled 1
1697 12:44:47.349829 PCI: 00:06.0: enabled 0
1698 12:44:47.353010 PCI: 00:07.0: enabled 0
1699 12:44:47.353126 PCI: 00:07.1: enabled 0
1700 12:44:47.356482 PCI: 00:07.2: enabled 0
1701 12:44:47.359634 PCI: 00:07.3: enabled 0
1702 12:44:47.363170 PCI: 00:08.0: enabled 1
1703 12:44:47.363285 PCI: 00:09.0: enabled 0
1704 12:44:47.366283 PCI: 00:0a.0: enabled 0
1705 12:44:47.369519 PCI: 00:0d.0: enabled 1
1706 12:44:47.372945 PCI: 00:0d.1: enabled 0
1707 12:44:47.373059 PCI: 00:0d.2: enabled 0
1708 12:44:47.375872 PCI: 00:0d.3: enabled 0
1709 12:44:47.379604 PCI: 00:0e.0: enabled 0
1710 12:44:47.382549 PCI: 00:10.2: enabled 1
1711 12:44:47.382664 PCI: 00:10.6: enabled 0
1712 12:44:47.386142 PCI: 00:10.7: enabled 0
1713 12:44:47.389683 PCI: 00:12.0: enabled 0
1714 12:44:47.389798 PCI: 00:12.6: enabled 0
1715 12:44:47.392831 PCI: 00:13.0: enabled 0
1716 12:44:47.395939 PCI: 00:14.0: enabled 1
1717 12:44:47.399375 PCI: 00:14.1: enabled 0
1718 12:44:47.399489 PCI: 00:14.2: enabled 1
1719 12:44:47.402629 PCI: 00:14.3: enabled 1
1720 12:44:47.406219 PCI: 00:15.0: enabled 1
1721 12:44:47.409214 PCI: 00:15.1: enabled 1
1722 12:44:47.409329 PCI: 00:15.2: enabled 1
1723 12:44:47.412873 PCI: 00:15.3: enabled 1
1724 12:44:47.416032 PCI: 00:16.0: enabled 1
1725 12:44:47.419416 PCI: 00:16.1: enabled 0
1726 12:44:47.419530 PCI: 00:16.2: enabled 0
1727 12:44:47.422576 PCI: 00:16.3: enabled 0
1728 12:44:47.426191 PCI: 00:16.4: enabled 0
1729 12:44:47.426300 PCI: 00:16.5: enabled 0
1730 12:44:47.429439 PCI: 00:17.0: enabled 0
1731 12:44:47.432659 PCI: 00:19.0: enabled 0
1732 12:44:47.435833 PCI: 00:19.1: enabled 1
1733 12:44:47.435919 PCI: 00:19.2: enabled 0
1734 12:44:47.439054 PCI: 00:1c.0: enabled 1
1735 12:44:47.442301 PCI: 00:1c.1: enabled 0
1736 12:44:47.445616 PCI: 00:1c.2: enabled 0
1737 12:44:47.445696 PCI: 00:1c.3: enabled 0
1738 12:44:47.449238 PCI: 00:1c.4: enabled 0
1739 12:44:47.452354 PCI: 00:1c.5: enabled 0
1740 12:44:47.455419 PCI: 00:1c.6: enabled 1
1741 12:44:47.455499 PCI: 00:1c.7: enabled 0
1742 12:44:47.458718 PCI: 00:1d.0: enabled 1
1743 12:44:47.462605 PCI: 00:1d.1: enabled 0
1744 12:44:47.465837 PCI: 00:1d.2: enabled 1
1745 12:44:47.465913 PCI: 00:1d.3: enabled 0
1746 12:44:47.468759 PCI: 00:1e.0: enabled 1
1747 12:44:47.472353 PCI: 00:1e.1: enabled 0
1748 12:44:47.475665 PCI: 00:1e.2: enabled 1
1749 12:44:47.475742 PCI: 00:1e.3: enabled 1
1750 12:44:47.478950 PCI: 00:1f.0: enabled 1
1751 12:44:47.482232 PCI: 00:1f.1: enabled 0
1752 12:44:47.482312 PCI: 00:1f.2: enabled 1
1753 12:44:47.485407 PCI: 00:1f.3: enabled 1
1754 12:44:47.488593 PCI: 00:1f.4: enabled 0
1755 12:44:47.492192 PCI: 00:1f.5: enabled 1
1756 12:44:47.492276 PCI: 00:1f.6: enabled 0
1757 12:44:47.495239 PCI: 00:1f.7: enabled 0
1758 12:44:47.498707 APIC: 00: enabled 1
1759 12:44:47.498793 GENERIC: 0.0: enabled 1
1760 12:44:47.502264 GENERIC: 0.0: enabled 1
1761 12:44:47.505497 GENERIC: 1.0: enabled 1
1762 12:44:47.508965 GENERIC: 0.0: enabled 1
1763 12:44:47.509076 GENERIC: 1.0: enabled 1
1764 12:44:47.511697 USB0 port 0: enabled 1
1765 12:44:47.515322 GENERIC: 0.0: enabled 1
1766 12:44:47.518862 USB0 port 0: enabled 1
1767 12:44:47.518948 GENERIC: 0.0: enabled 1
1768 12:44:47.521977 I2C: 00:1a: enabled 1
1769 12:44:47.525388 I2C: 00:31: enabled 1
1770 12:44:47.525468 I2C: 00:32: enabled 1
1771 12:44:47.528276 I2C: 00:10: enabled 1
1772 12:44:47.531862 I2C: 00:15: enabled 1
1773 12:44:47.531957 GENERIC: 0.0: enabled 0
1774 12:44:47.535046 GENERIC: 1.0: enabled 0
1775 12:44:47.538297 GENERIC: 0.0: enabled 1
1776 12:44:47.538373 SPI: 00: enabled 1
1777 12:44:47.541698 SPI: 00: enabled 1
1778 12:44:47.545440 PNP: 0c09.0: enabled 1
1779 12:44:47.548680 GENERIC: 0.0: enabled 1
1780 12:44:47.548764 USB3 port 0: enabled 1
1781 12:44:47.551858 USB3 port 1: enabled 1
1782 12:44:47.555035 USB3 port 2: enabled 0
1783 12:44:47.555117 USB3 port 3: enabled 0
1784 12:44:47.558163 USB2 port 0: enabled 0
1785 12:44:47.562099 USB2 port 1: enabled 1
1786 12:44:47.562188 USB2 port 2: enabled 1
1787 12:44:47.565420 USB2 port 3: enabled 0
1788 12:44:47.568586 USB2 port 4: enabled 1
1789 12:44:47.571844 USB2 port 5: enabled 0
1790 12:44:47.571955 USB2 port 6: enabled 0
1791 12:44:47.575242 USB2 port 7: enabled 0
1792 12:44:47.578309 USB2 port 8: enabled 0
1793 12:44:47.578406 USB2 port 9: enabled 0
1794 12:44:47.581533 USB3 port 0: enabled 0
1795 12:44:47.584710 USB3 port 1: enabled 1
1796 12:44:47.588035 USB3 port 2: enabled 0
1797 12:44:47.588123 USB3 port 3: enabled 0
1798 12:44:47.591451 GENERIC: 0.0: enabled 1
1799 12:44:47.595128 GENERIC: 1.0: enabled 1
1800 12:44:47.595207 APIC: 01: enabled 1
1801 12:44:47.598092 APIC: 04: enabled 1
1802 12:44:47.601688 APIC: 07: enabled 1
1803 12:44:47.601764 APIC: 02: enabled 1
1804 12:44:47.604931 APIC: 05: enabled 1
1805 12:44:47.605023 APIC: 06: enabled 1
1806 12:44:47.608582 APIC: 03: enabled 1
1807 12:44:47.611640 PCI: 01:00.0: enabled 1
1808 12:44:47.614592 BS: BS_DEV_INIT run times (exec / console): 32 / 540 ms
1809 12:44:47.621479 FMAP: area RW_ELOG found @ f30000 (4096 bytes)
1810 12:44:47.624621 ELOG: NV offset 0xf30000 size 0x1000
1811 12:44:47.631819 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1812 12:44:47.638344 ELOG: Event(17) added with size 13 at 2023-03-22 12:44:47 UTC
1813 12:44:47.644733 ELOG: Event(92) added with size 9 at 2023-03-22 12:44:47 UTC
1814 12:44:47.651141 ELOG: Event(93) added with size 9 at 2023-03-22 12:44:47 UTC
1815 12:44:47.658124 ELOG: Event(9E) added with size 10 at 2023-03-22 12:44:47 UTC
1816 12:44:47.664396 ELOG: Event(9F) added with size 14 at 2023-03-22 12:44:47 UTC
1817 12:44:47.671803 BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms
1818 12:44:47.677967 ELOG: Event(A1) added with size 10 at 2023-03-22 12:44:47 UTC
1819 12:44:47.684529 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1820 12:44:47.690981 ELOG: Event(A0) added with size 9 at 2023-03-22 12:44:47 UTC
1821 12:44:47.694329 elog_add_boot_reason: Logged dev mode boot
1822 12:44:47.700781 BS: BS_POST_DEVICE entry times (exec / console): 0 / 24 ms
1823 12:44:47.700872 Finalize devices...
1824 12:44:47.704509 Devices finalized
1825 12:44:47.711162 BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
1826 12:44:47.714650 FMAP: area RW_NVRAM found @ f37000 (24576 bytes)
1827 12:44:47.720744 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
1828 12:44:47.724481 ME: HFSTS1 : 0x80030055
1829 12:44:47.730798 ME: HFSTS2 : 0x30280116
1830 12:44:47.734307 ME: HFSTS3 : 0x00000050
1831 12:44:47.737701 ME: HFSTS4 : 0x00004000
1832 12:44:47.744016 ME: HFSTS5 : 0x00000000
1833 12:44:47.747591 ME: HFSTS6 : 0x40400006
1834 12:44:47.750655 ME: Manufacturing Mode : YES
1835 12:44:47.754050 ME: SPI Protection Mode Enabled : NO
1836 12:44:47.760653 ME: FW Partition Table : OK
1837 12:44:47.763841 ME: Bringup Loader Failure : NO
1838 12:44:47.767083 ME: Firmware Init Complete : NO
1839 12:44:47.770717 ME: Boot Options Present : NO
1840 12:44:47.773912 ME: Update In Progress : NO
1841 12:44:47.777137 ME: D0i3 Support : YES
1842 12:44:47.780575 ME: Low Power State Enabled : NO
1843 12:44:47.783778 ME: CPU Replaced : YES
1844 12:44:47.790822 ME: CPU Replacement Valid : YES
1845 12:44:47.794088 ME: Current Working State : 5
1846 12:44:47.797275 ME: Current Operation State : 1
1847 12:44:47.800640 ME: Current Operation Mode : 3
1848 12:44:47.803982 ME: Error Code : 0
1849 12:44:47.807120 ME: Enhanced Debug Mode : NO
1850 12:44:47.810902 ME: CPU Debug Disabled : YES
1851 12:44:47.813893 ME: TXT Support : NO
1852 12:44:47.820643 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 94 ms
1853 12:44:47.826775 CBFS: Found 'fallback/dsdt.aml' @0x72f80 size 0x5a67 in mcache @0x76c4c1c4
1854 12:44:47.830482 CBFS: 'fallback/slic' not found.
1855 12:44:47.837399 ACPI: Writing ACPI tables at 76b01000.
1856 12:44:47.837492 ACPI: * FACS
1857 12:44:47.840304 ACPI: * DSDT
1858 12:44:47.843331 Ramoops buffer: 0x100000@0x76a00000.
1859 12:44:47.846880 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
1860 12:44:47.853422 FMAP: area RW_VPD found @ f35000 (8192 bytes)
1861 12:44:47.857187 Google Chrome EC: version:
1862 12:44:47.860105 ro: voema_v2.0.10114-a447f03e46
1863 12:44:47.863269 rw: voema_v2.0.10132-7b2059e3bc
1864 12:44:47.863349 running image: 2
1865 12:44:47.869675 PCI space above 4GB MMIO is at 0x480400000, len = 0x7b7fc00000
1866 12:44:47.874904 ACPI: * FADT
1867 12:44:47.874989 SCI is IRQ9
1868 12:44:47.882007 ACPI: added table 1/32, length now 40
1869 12:44:47.882109 ACPI: * SSDT
1870 12:44:47.885052 Found 1 CPU(s) with 8 core(s) each.
1871 12:44:47.891597 \_SB.PCI0.PMC: Intel Tigerlake at PCI: 00:1f.2
1872 12:44:47.894746 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
1873 12:44:47.897932 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
1874 12:44:47.901134 \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
1875 12:44:47.907779 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
1876 12:44:47.914974 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
1877 12:44:47.918093 \_SB.PCI0.I2C1.H010: ELAN Touchscreen at I2C: 00:10
1878 12:44:47.924598 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
1879 12:44:47.931490 \_SB.PCI0.RP09: Enable RTD3 for PCI: 00:1d.0 (Intel PCIe Runtime D3)
1880 12:44:47.934559 \_SB.PCI0.RP09: Added StorageD3Enable property
1881 12:44:47.941456 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1882 12:44:47.944627 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
1883 12:44:47.951382 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
1884 12:44:47.954932 PS2K: Passing 80 keymaps to kernel
1885 12:44:47.961629 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
1886 12:44:47.967989 \_SB.PCI0.TXHC.RHUB.SS02: USB3 Type-C Port C1 (DB) at USB3 port 1
1887 12:44:47.974548 \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-A Port A1 (DB) at USB2 port 1
1888 12:44:47.981381 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
1889 12:44:47.988144 \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-C Port C0 (MLB) at USB2 port 4
1890 12:44:47.994492 \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Port A1 (DB) at USB3 port 1
1891 12:44:48.001058 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
1892 12:44:48.007610 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
1893 12:44:48.010900 ACPI: added table 2/32, length now 44
1894 12:44:48.014248 ACPI: * MCFG
1895 12:44:48.017582 ACPI: added table 3/32, length now 48
1896 12:44:48.017660 ACPI: * TPM2
1897 12:44:48.020781 TPM2 log created at 0x769f0000
1898 12:44:48.024640 ACPI: added table 4/32, length now 52
1899 12:44:48.027894 ACPI: * MADT
1900 12:44:48.027971 SCI is IRQ9
1901 12:44:48.031033 ACPI: added table 5/32, length now 56
1902 12:44:48.034431 current = 76b09850
1903 12:44:48.034516 ACPI: * DMAR
1904 12:44:48.040584 ACPI: added table 6/32, length now 60
1905 12:44:48.044252 ACPI: added table 7/32, length now 64
1906 12:44:48.044336 ACPI: * HPET
1907 12:44:48.047256 ACPI: added table 8/32, length now 68
1908 12:44:48.050486 ACPI: done.
1909 12:44:48.053638 ACPI tables: 35216 bytes.
1910 12:44:48.053721 smbios_write_tables: 769ef000
1911 12:44:48.057543 EC returned error result code 3
1912 12:44:48.060603 Couldn't obtain OEM name from CBI
1913 12:44:48.065346 Create SMBIOS type 16
1914 12:44:48.068309 Create SMBIOS type 17
1915 12:44:48.071845 GENERIC: 0.0 (WIFI Device)
1916 12:44:48.071925 SMBIOS tables: 1734 bytes.
1917 12:44:48.078691 Writing table forward entry at 0x00000500
1918 12:44:48.085224 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 392c
1919 12:44:48.088527 Writing coreboot table at 0x76b25000
1920 12:44:48.095277 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1921 12:44:48.098396 1. 0000000000001000-000000000009ffff: RAM
1922 12:44:48.101667 2. 00000000000a0000-00000000000fffff: RESERVED
1923 12:44:48.108125 3. 0000000000100000-00000000769eefff: RAM
1924 12:44:48.111457 4. 00000000769ef000-0000000076b97fff: CONFIGURATION TABLES
1925 12:44:48.118515 5. 0000000076b98000-0000000076c09fff: RAMSTAGE
1926 12:44:48.124998 6. 0000000076c0a000-0000000076ffffff: CONFIGURATION TABLES
1927 12:44:48.128116 7. 0000000077000000-000000007fbfffff: RESERVED
1928 12:44:48.134858 8. 00000000c0000000-00000000cfffffff: RESERVED
1929 12:44:48.138224 9. 00000000f8000000-00000000f9ffffff: RESERVED
1930 12:44:48.141341 10. 00000000fb000000-00000000fb000fff: RESERVED
1931 12:44:48.147803 11. 00000000fe000000-00000000fe00ffff: RESERVED
1932 12:44:48.151305 12. 00000000fed80000-00000000fed87fff: RESERVED
1933 12:44:48.158204 13. 00000000fed90000-00000000fed92fff: RESERVED
1934 12:44:48.161392 14. 00000000feda0000-00000000feda1fff: RESERVED
1935 12:44:48.167699 15. 00000000fedc0000-00000000feddffff: RESERVED
1936 12:44:48.171395 16. 0000000100000000-00000004803fffff: RAM
1937 12:44:48.174569 Passing 4 GPIOs to payload:
1938 12:44:48.177808 NAME | PORT | POLARITY | VALUE
1939 12:44:48.184548 lid | undefined | high | high
1940 12:44:48.191608 power | undefined | high | low
1941 12:44:48.194800 oprom | undefined | high | low
1942 12:44:48.201138 EC in RW | 0x000000e5 | high | high
1943 12:44:48.207558 Wrote coreboot table at: 0x76b25000, 0x610 bytes, checksum 7e26
1944 12:44:48.207645 coreboot table: 1576 bytes.
1945 12:44:48.214100 IMD ROOT 0. 0x76fff000 0x00001000
1946 12:44:48.217589 IMD SMALL 1. 0x76ffe000 0x00001000
1947 12:44:48.220775 FSP MEMORY 2. 0x76c4e000 0x003b0000
1948 12:44:48.224033 VPD 3. 0x76c4d000 0x00000367
1949 12:44:48.227904 RO MCACHE 4. 0x76c4c000 0x00000fdc
1950 12:44:48.231049 CONSOLE 5. 0x76c2c000 0x00020000
1951 12:44:48.234166 FMAP 6. 0x76c2b000 0x00000578
1952 12:44:48.237444 TIME STAMP 7. 0x76c2a000 0x00000910
1953 12:44:48.243986 VBOOT WORK 8. 0x76c16000 0x00014000
1954 12:44:48.247289 ROMSTG STCK 9. 0x76c15000 0x00001000
1955 12:44:48.251139 AFTER CAR 10. 0x76c0a000 0x0000b000
1956 12:44:48.253826 RAMSTAGE 11. 0x76b97000 0x00073000
1957 12:44:48.257744 REFCODE 12. 0x76b42000 0x00055000
1958 12:44:48.260682 SMM BACKUP 13. 0x76b32000 0x00010000
1959 12:44:48.263869 4f444749 14. 0x76b30000 0x00002000
1960 12:44:48.267499 EXT VBT15. 0x76b2d000 0x0000219f
1961 12:44:48.273974 COREBOOT 16. 0x76b25000 0x00008000
1962 12:44:48.276959 ACPI 17. 0x76b01000 0x00024000
1963 12:44:48.280672 ACPI GNVS 18. 0x76b00000 0x00001000
1964 12:44:48.283794 RAMOOPS 19. 0x76a00000 0x00100000
1965 12:44:48.287676 TPM2 TCGLOG20. 0x769f0000 0x00010000
1966 12:44:48.290729 SMBIOS 21. 0x769ef000 0x00000800
1967 12:44:48.293884 IMD small region:
1968 12:44:48.296928 IMD ROOT 0. 0x76ffec00 0x00000400
1969 12:44:48.300170 FSP RUNTIME 1. 0x76ffebe0 0x00000004
1970 12:44:48.304129 POWER STATE 2. 0x76ffeb80 0x00000044
1971 12:44:48.307141 ROMSTAGE 3. 0x76ffeb60 0x00000004
1972 12:44:48.313691 MEM INFO 4. 0x76ffe980 0x000001e0
1973 12:44:48.316961 BS: BS_WRITE_TABLES run times (exec / console): 7 / 484 ms
1974 12:44:48.320308 MTRR: Physical address space:
1975 12:44:48.326775 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1976 12:44:48.333377 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1977 12:44:48.340271 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
1978 12:44:48.346794 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
1979 12:44:48.353563 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
1980 12:44:48.359878 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
1981 12:44:48.366760 0x0000000100000000 - 0x0000000480400000 size 0x380400000 type 6
1982 12:44:48.369707 MTRR: Fixed MSR 0x250 0x0606060606060606
1983 12:44:48.373345 MTRR: Fixed MSR 0x258 0x0606060606060606
1984 12:44:48.376502 MTRR: Fixed MSR 0x259 0x0000000000000000
1985 12:44:48.380234 MTRR: Fixed MSR 0x268 0x0606060606060606
1986 12:44:48.386547 MTRR: Fixed MSR 0x269 0x0606060606060606
1987 12:44:48.390044 MTRR: Fixed MSR 0x26a 0x0606060606060606
1988 12:44:48.393642 MTRR: Fixed MSR 0x26b 0x0606060606060606
1989 12:44:48.396675 MTRR: Fixed MSR 0x26c 0x0606060606060606
1990 12:44:48.403661 MTRR: Fixed MSR 0x26d 0x0606060606060606
1991 12:44:48.406594 MTRR: Fixed MSR 0x26e 0x0606060606060606
1992 12:44:48.409829 MTRR: Fixed MSR 0x26f 0x0606060606060606
1993 12:44:48.414192 call enable_fixed_mtrr()
1994 12:44:48.417378 CPU physical address size: 39 bits
1995 12:44:48.423966 MTRR: default type WB/UC MTRR counts: 6/7.
1996 12:44:48.427151 MTRR: WB selected as default type.
1997 12:44:48.433784 MTRR: 0 base 0x0000000077000000 mask 0x0000007fff000000 type 0
1998 12:44:48.437045 MTRR: 1 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
1999 12:44:48.443514 MTRR: 2 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
2000 12:44:48.450185 MTRR: 3 base 0x0000000090000000 mask 0x0000007ff0000000 type 0
2001 12:44:48.457388 MTRR: 4 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
2002 12:44:48.463279 MTRR: 5 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0
2003 12:44:48.467238
2004 12:44:48.467324 MTRR check
2005 12:44:48.470368 Fixed MTRRs : Enabled
2006 12:44:48.470493 Variable MTRRs: Enabled
2007 12:44:48.470562
2008 12:44:48.477063 MTRR: Fixed MSR 0x250 0x0606060606060606
2009 12:44:48.480594 MTRR: Fixed MSR 0x258 0x0606060606060606
2010 12:44:48.483813 MTRR: Fixed MSR 0x259 0x0000000000000000
2011 12:44:48.486804 MTRR: Fixed MSR 0x268 0x0606060606060606
2012 12:44:48.493919 MTRR: Fixed MSR 0x269 0x0606060606060606
2013 12:44:48.496844 MTRR: Fixed MSR 0x26a 0x0606060606060606
2014 12:44:48.500472 MTRR: Fixed MSR 0x26b 0x0606060606060606
2015 12:44:48.503581 MTRR: Fixed MSR 0x26c 0x0606060606060606
2016 12:44:48.510327 MTRR: Fixed MSR 0x26d 0x0606060606060606
2017 12:44:48.513284 MTRR: Fixed MSR 0x26e 0x0606060606060606
2018 12:44:48.516493 MTRR: Fixed MSR 0x26f 0x0606060606060606
2019 12:44:48.524065 BS: BS_WRITE_TABLES exit times (exec / console): 4 / 150 ms
2020 12:44:48.527502 call enable_fixed_mtrr()
2021 12:44:48.531227 Checking cr50 for pending updates
2022 12:44:48.534381 CPU physical address size: 39 bits
2023 12:44:48.537738 MTRR: Fixed MSR 0x250 0x0606060606060606
2024 12:44:48.541147 MTRR: Fixed MSR 0x250 0x0606060606060606
2025 12:44:48.548026 MTRR: Fixed MSR 0x258 0x0606060606060606
2026 12:44:48.551315 MTRR: Fixed MSR 0x259 0x0000000000000000
2027 12:44:48.554111 MTRR: Fixed MSR 0x268 0x0606060606060606
2028 12:44:48.557973 MTRR: Fixed MSR 0x269 0x0606060606060606
2029 12:44:48.564545 MTRR: Fixed MSR 0x26a 0x0606060606060606
2030 12:44:48.567820 MTRR: Fixed MSR 0x26b 0x0606060606060606
2031 12:44:48.571134 MTRR: Fixed MSR 0x26c 0x0606060606060606
2032 12:44:48.574498 MTRR: Fixed MSR 0x26d 0x0606060606060606
2033 12:44:48.577600 MTRR: Fixed MSR 0x26e 0x0606060606060606
2034 12:44:48.583950 MTRR: Fixed MSR 0x26f 0x0606060606060606
2035 12:44:48.587510 MTRR: Fixed MSR 0x258 0x0606060606060606
2036 12:44:48.594368 MTRR: Fixed MSR 0x259 0x0000000000000000
2037 12:44:48.597553 MTRR: Fixed MSR 0x268 0x0606060606060606
2038 12:44:48.600932 MTRR: Fixed MSR 0x269 0x0606060606060606
2039 12:44:48.603939 MTRR: Fixed MSR 0x26a 0x0606060606060606
2040 12:44:48.610571 MTRR: Fixed MSR 0x26b 0x0606060606060606
2041 12:44:48.614169 MTRR: Fixed MSR 0x26c 0x0606060606060606
2042 12:44:48.617511 MTRR: Fixed MSR 0x26d 0x0606060606060606
2043 12:44:48.620795 MTRR: Fixed MSR 0x26e 0x0606060606060606
2044 12:44:48.627574 MTRR: Fixed MSR 0x26f 0x0606060606060606
2045 12:44:48.630655 call enable_fixed_mtrr()
2046 12:44:48.633621 call enable_fixed_mtrr()
2047 12:44:48.637578 MTRR: Fixed MSR 0x250 0x0606060606060606
2048 12:44:48.640802 MTRR: Fixed MSR 0x250 0x0606060606060606
2049 12:44:48.644156 MTRR: Fixed MSR 0x258 0x0606060606060606
2050 12:44:48.650408 MTRR: Fixed MSR 0x259 0x0000000000000000
2051 12:44:48.653602 MTRR: Fixed MSR 0x268 0x0606060606060606
2052 12:44:48.657541 MTRR: Fixed MSR 0x269 0x0606060606060606
2053 12:44:48.660893 MTRR: Fixed MSR 0x26a 0x0606060606060606
2054 12:44:48.667624 MTRR: Fixed MSR 0x26b 0x0606060606060606
2055 12:44:48.670143 MTRR: Fixed MSR 0x26c 0x0606060606060606
2056 12:44:48.674058 MTRR: Fixed MSR 0x26d 0x0606060606060606
2057 12:44:48.676848 MTRR: Fixed MSR 0x26e 0x0606060606060606
2058 12:44:48.680795 MTRR: Fixed MSR 0x26f 0x0606060606060606
2059 12:44:48.687119 MTRR: Fixed MSR 0x258 0x0606060606060606
2060 12:44:48.690382 MTRR: Fixed MSR 0x259 0x0000000000000000
2061 12:44:48.697166 MTRR: Fixed MSR 0x268 0x0606060606060606
2062 12:44:48.700257 MTRR: Fixed MSR 0x269 0x0606060606060606
2063 12:44:48.703333 MTRR: Fixed MSR 0x26a 0x0606060606060606
2064 12:44:48.706659 MTRR: Fixed MSR 0x26b 0x0606060606060606
2065 12:44:48.713554 MTRR: Fixed MSR 0x26c 0x0606060606060606
2066 12:44:48.717088 MTRR: Fixed MSR 0x26d 0x0606060606060606
2067 12:44:48.720125 MTRR: Fixed MSR 0x26e 0x0606060606060606
2068 12:44:48.723902 MTRR: Fixed MSR 0x26f 0x0606060606060606
2069 12:44:48.728100 call enable_fixed_mtrr()
2070 12:44:48.731886 call enable_fixed_mtrr()
2071 12:44:48.735008 MTRR: Fixed MSR 0x250 0x0606060606060606
2072 12:44:48.738040 MTRR: Fixed MSR 0x250 0x0606060606060606
2073 12:44:48.745077 MTRR: Fixed MSR 0x258 0x0606060606060606
2074 12:44:48.748308 MTRR: Fixed MSR 0x259 0x0000000000000000
2075 12:44:48.751402 MTRR: Fixed MSR 0x268 0x0606060606060606
2076 12:44:48.754562 MTRR: Fixed MSR 0x269 0x0606060606060606
2077 12:44:48.761079 MTRR: Fixed MSR 0x26a 0x0606060606060606
2078 12:44:48.764914 MTRR: Fixed MSR 0x26b 0x0606060606060606
2079 12:44:48.768147 MTRR: Fixed MSR 0x26c 0x0606060606060606
2080 12:44:48.771410 MTRR: Fixed MSR 0x26d 0x0606060606060606
2081 12:44:48.778092 MTRR: Fixed MSR 0x26e 0x0606060606060606
2082 12:44:48.781323 MTRR: Fixed MSR 0x26f 0x0606060606060606
2083 12:44:48.787865 MTRR: Fixed MSR 0x258 0x0606060606060606
2084 12:44:48.787997 call enable_fixed_mtrr()
2085 12:44:48.794775 MTRR: Fixed MSR 0x259 0x0000000000000000
2086 12:44:48.797975 MTRR: Fixed MSR 0x268 0x0606060606060606
2087 12:44:48.801081 MTRR: Fixed MSR 0x269 0x0606060606060606
2088 12:44:48.804159 MTRR: Fixed MSR 0x26a 0x0606060606060606
2089 12:44:48.810772 MTRR: Fixed MSR 0x26b 0x0606060606060606
2090 12:44:48.814638 MTRR: Fixed MSR 0x26c 0x0606060606060606
2091 12:44:48.817909 MTRR: Fixed MSR 0x26d 0x0606060606060606
2092 12:44:48.820849 MTRR: Fixed MSR 0x26e 0x0606060606060606
2093 12:44:48.827548 MTRR: Fixed MSR 0x26f 0x0606060606060606
2094 12:44:48.830666 CPU physical address size: 39 bits
2095 12:44:48.835091 call enable_fixed_mtrr()
2096 12:44:48.838730 Reading cr50 TPM mode
2097 12:44:48.841934 CPU physical address size: 39 bits
2098 12:44:48.845727 CPU physical address size: 39 bits
2099 12:44:48.852218 CPU physical address size: 39 bits
2100 12:44:48.855477 BS: BS_PAYLOAD_LOAD entry times (exec / console): 312 / 6 ms
2101 12:44:48.858706 CPU physical address size: 39 bits
2102 12:44:48.863955 CPU physical address size: 39 bits
2103 12:44:48.873939 CBFS: Found 'fallback/payload' @0x38db00 size 0x4be9c in mcache @0x76c4cf60
2104 12:44:48.877205 Checking segment from ROM address 0xffc02b38
2105 12:44:48.880438 Checking segment from ROM address 0xffc02b54
2106 12:44:48.886922 Loading segment from ROM address 0xffc02b38
2107 12:44:48.890169 code (compression=0)
2108 12:44:48.896774 New segment dstaddr 0x30000000 memsize 0x2662db0 srcaddr 0xffc02b70 filesize 0x4be64
2109 12:44:48.906553 Loading Segment: addr: 0x30000000 memsz: 0x0000000002662db0 filesz: 0x000000000004be64
2110 12:44:48.906641 it's not compressed!
2111 12:44:49.047954 [ 0x30000000, 3004be64, 0x32662db0) <- ffc02b70
2112 12:44:49.054805 Clearing Segment: addr: 0x000000003004be64 memsz: 0x0000000002616f4c
2113 12:44:49.061745 Loading segment from ROM address 0xffc02b54
2114 12:44:49.064895 Entry Point 0x30000000
2115 12:44:49.064982 Loaded segments
2116 12:44:49.071376 BS: BS_PAYLOAD_LOAD run times (exec / console): 145 / 63 ms
2117 12:44:49.116552 Finalizing chipset.
2118 12:44:49.120333 Finalizing SMM.
2119 12:44:49.120424 APMC done.
2120 12:44:49.126691 BS: BS_PAYLOAD_LOAD exit times (exec / console): 44 / 5 ms
2121 12:44:49.129961 mp_park_aps done after 0 msecs.
2122 12:44:49.132961 Jumping to boot code at 0x30000000(0x76b25000)
2123 12:44:49.143036 CPU0: stack: 0x76bee000 - 0x76bef000, lowest used address 0x76beea78, stack used: 1416 bytes
2124 12:44:49.143128
2125 12:44:49.143200
2126 12:44:49.146666
2127 12:44:49.146756 Starting depthcharge on Voema...
2128 12:44:49.147213 end: 2.2.3 depthcharge-start (duration 00:00:10) [common]
2129 12:44:49.147344 start: 2.2.4 bootloader-commands (timeout 00:04:45) [common]
2130 12:44:49.147431 Setting prompt string to ['volteer:']
2131 12:44:49.147512 bootloader-commands: Wait for prompt ['volteer:'] (timeout 00:04:45)
2132 12:44:49.149570
2133 12:44:49.156358 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2134 12:44:49.156460
2135 12:44:49.162860 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2136 12:44:49.162962
2137 12:44:49.169538 Looking for NVMe Controller 0x3005f220 @ 00:1d:00
2138 12:44:49.169625
2139 12:44:49.172765 Failed to find eMMC card reader
2140 12:44:49.172852
2141 12:44:49.175940 Wipe memory regions:
2142 12:44:49.176025
2143 12:44:49.179217 [0x00000000001000, 0x000000000a0000)
2144 12:44:49.179302
2145 12:44:49.182643 [0x00000000100000, 0x00000030000000)
2146 12:44:49.217221
2147 12:44:49.220339 [0x00000032662db0, 0x000000769ef000)
2148 12:44:49.267987
2149 12:44:49.271122 [0x00000100000000, 0x00000480400000)
2150 12:44:49.879089
2151 12:44:49.882202 ec_init: CrosEC protocol v3 supported (256, 256)
2152 12:44:50.312851
2153 12:44:50.312998 R8152: Initializing
2154 12:44:50.313069
2155 12:44:50.316614 Version 6 (ocp_data = 5c30)
2156 12:44:50.316703
2157 12:44:50.319770 R8152: Done initializing
2158 12:44:50.319858
2159 12:44:50.322985 Adding net device
2160 12:44:50.625455
2161 12:44:50.628653 [firmware-volteer-13672.B-collabora] Oct 22 2021 06:32:35
2162 12:44:50.628747
2163 12:44:50.628817
2164 12:44:50.628881
2165 12:44:50.631948 Setting prompt string to ['volteer:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2167 12:44:50.732677 volteer: tftpboot 192.168.201.1 9729709/tftp-deploy-thsn03kf/kernel/bzImage 9729709/tftp-deploy-thsn03kf/kernel/cmdline 9729709/tftp-deploy-thsn03kf/ramdisk/ramdisk.cpio.gz
2168 12:44:50.732846 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2169 12:44:50.732960 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:43)
2170 12:44:50.737604 tftpboot 192.168.201.1 9729709/tftp-deploy-thsn03kf/kernel/bzImoy-thsn03kf/kernel/cmdline 9729709/tftp-deploy-thsn03kf/ramdisk/ramdisk.cpio.gz
2171 12:44:50.737693
2172 12:44:50.737762 Waiting for link
2173 12:44:50.940732
2174 12:44:50.940870 done.
2175 12:44:50.940974
2176 12:44:50.941058 MAC: 00:24:32:30:7e:22
2177 12:44:50.941125
2178 12:44:50.943879 Sending DHCP discover... done.
2179 12:44:50.943969
2180 12:44:50.947072 Waiting for reply... done.
2181 12:44:50.947161
2182 12:44:50.950392 Sending DHCP request... done.
2183 12:44:50.950481
2184 12:44:50.953592 Waiting for reply... done.
2185 12:44:50.953680
2186 12:44:50.957224 My ip is 192.168.201.21
2187 12:44:50.957313
2188 12:44:50.960234 The DHCP server ip is 192.168.201.1
2189 12:44:50.960328
2190 12:44:50.963626 TFTP server IP predefined by user: 192.168.201.1
2191 12:44:50.963711
2192 12:44:50.969938 Bootfile predefined by user: 9729709/tftp-deploy-thsn03kf/kernel/bzImage
2193 12:44:50.970029
2194 12:44:50.973751 Sending tftp read request... done.
2195 12:44:50.973840
2196 12:44:50.980386 Waiting for the transfer...
2197 12:44:50.980486
2198 12:44:51.491250 00000000 ################################################################
2199 12:44:51.491401
2200 12:44:52.003463 00080000 ################################################################
2201 12:44:52.003615
2202 12:44:52.518550 00100000 ################################################################
2203 12:44:52.518692
2204 12:44:53.035192 00180000 ################################################################
2205 12:44:53.035336
2206 12:44:53.552652 00200000 ################################################################
2207 12:44:53.552792
2208 12:44:54.074939 00280000 ################################################################
2209 12:44:54.075084
2210 12:44:54.593690 00300000 ################################################################
2211 12:44:54.593836
2212 12:44:55.111471 00380000 ################################################################
2213 12:44:55.111613
2214 12:44:55.625667 00400000 ################################################################
2215 12:44:55.625812
2216 12:44:56.143488 00480000 ################################################################
2217 12:44:56.143686
2218 12:44:56.709942 00500000 ################################################################
2219 12:44:56.710089
2220 12:44:57.302660 00580000 ################################################################
2221 12:44:57.302801
2222 12:44:57.845093 00600000 ################################################################
2223 12:44:57.845244
2224 12:44:58.376480 00680000 ################################################################
2225 12:44:58.376628
2226 12:44:58.901100 00700000 ################################################################
2227 12:44:58.901252
2228 12:44:59.439955 00780000 ################################################################
2229 12:44:59.440098
2230 12:44:59.950189 00800000 ################################################################
2231 12:44:59.950345
2232 12:45:00.473861 00880000 ################################################################
2233 12:45:00.473997
2234 12:45:00.991717 00900000 ################################################################
2235 12:45:00.991859
2236 12:45:01.523845 00980000 ################################################################
2237 12:45:01.523990
2238 12:45:02.069730 00a00000 ################################################################
2239 12:45:02.069878
2240 12:45:02.603611 00a80000 ################################################################
2241 12:45:02.603768
2242 12:45:02.723804 00b00000 ############## done.
2243 12:45:02.723950
2244 12:45:02.727373 The bootfile was 11646080 bytes long.
2245 12:45:02.727463
2246 12:45:02.730386 Sending tftp read request... done.
2247 12:45:02.730469
2248 12:45:02.733591 Waiting for the transfer...
2249 12:45:02.733690
2250 12:45:03.281189 00000000 ################################################################
2251 12:45:03.281334
2252 12:45:03.820112 00080000 ################################################################
2253 12:45:03.820260
2254 12:45:04.344429 00100000 ################################################################
2255 12:45:04.344573
2256 12:45:04.876855 00180000 ################################################################
2257 12:45:04.877002
2258 12:45:05.396474 00200000 ################################################################
2259 12:45:05.396618
2260 12:45:05.930914 00280000 ################################################################
2261 12:45:05.931064
2262 12:45:06.452736 00300000 ################################################################
2263 12:45:06.452876
2264 12:45:06.985316 00380000 ################################################################
2265 12:45:06.985462
2266 12:45:07.538908 00400000 ################################################################
2267 12:45:07.539095
2268 12:45:08.085115 00480000 ################################################################
2269 12:45:08.085260
2270 12:45:08.628027 00500000 ################################################################
2271 12:45:08.628167
2272 12:45:09.034105 00580000 ################################################# done.
2273 12:45:09.034252
2274 12:45:09.037508 Sending tftp read request... done.
2275 12:45:09.037599
2276 12:45:09.040508 Waiting for the transfer...
2277 12:45:09.040599
2278 12:45:09.040670 00000000 # done.
2279 12:45:09.040740
2280 12:45:09.050531 Command line loaded dynamically from TFTP file: 9729709/tftp-deploy-thsn03kf/kernel/cmdline
2281 12:45:09.050626
2282 12:45:09.073843 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/9729709/extract-nfsrootfs-uejj9dly,tcp,hard ip=dhcp tftpserverip=192.168.201.1
2283 12:45:09.077155
2284 12:45:09.081248 Shutting down all USB controllers.
2285 12:45:09.081341
2286 12:45:09.081412 Removing current net device
2287 12:45:09.081479
2288 12:45:09.084221 Finalizing coreboot
2289 12:45:09.084311
2290 12:45:09.090448 Exiting depthcharge with code 4 at timestamp: 28556819
2291 12:45:09.090540
2292 12:45:09.090612
2293 12:45:09.090678 Starting kernel ...
2294 12:45:09.090743
2295 12:45:09.090806
2296 12:45:09.091190 end: 2.2.4 bootloader-commands (duration 00:00:20) [common]
2297 12:45:09.091296 start: 2.2.5 auto-login-action (timeout 00:04:25) [common]
2298 12:45:09.091376 Setting prompt string to ['Linux version [0-9]']
2299 12:45:09.091449 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2300 12:45:09.091523 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2302 12:49:34.092129 end: 2.2.5 auto-login-action (duration 00:04:25) [common]
2304 12:49:34.093298 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 265 seconds'
2306 12:49:34.094202 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2309 12:49:34.095910 end: 2 depthcharge-action (duration 00:05:00) [common]
2311 12:49:34.097238 Cleaning after the job
2312 12:49:34.097755 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9729709/tftp-deploy-thsn03kf/ramdisk
2313 12:49:34.100172 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9729709/tftp-deploy-thsn03kf/kernel
2314 12:49:34.103756 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9729709/tftp-deploy-thsn03kf/nfsrootfs
2315 12:49:34.163683 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9729709/tftp-deploy-thsn03kf/modules
2316 12:49:34.164168 start: 5.1 power-off (timeout 00:00:30) [common]
2317 12:49:34.164335 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-14' '--port=1' '--command=off'
2318 12:49:34.246379 >> Command sent successfully.
2319 12:49:34.255168 Returned 0 in 0 seconds
2320 12:49:34.356995 end: 5.1 power-off (duration 00:00:00) [common]
2322 12:49:34.358771 start: 5.2 read-feedback (timeout 00:10:00) [common]
2323 12:49:34.360007 Listened to connection for namespace 'common' for up to 1s
2324 12:49:35.363268 Finalising connection for namespace 'common'
2325 12:49:35.363909 Disconnecting from shell: Finalise
2326 12:49:35.364322
2327 12:49:35.465383 end: 5.2 read-feedback (duration 00:00:01) [common]
2328 12:49:35.465560 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/9729709
2329 12:49:35.560505 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/9729709
2330 12:49:35.560702 JobError: Your job cannot terminate cleanly.