Boot log: asus-cx9400-volteer
- Errors: 2
- Boot result: FAIL
- Kernel Errors: 0
- Warnings: 0
- Kernel Warnings: 0
1 12:51:09.830124 lava-dispatcher, installed at version: 2023.01
2 12:51:09.830328 start: 0 validate
3 12:51:09.830451 Start time: 2023-03-22 12:51:09.830446+00:00 (UTC)
4 12:51:09.830586 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:51:09.830716 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230310.0%2Fx86%2Frootfs.cpio.gz exists
6 12:51:10.118915 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:51:10.119089 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-5.10.y-cip-rt%2Fv5.10.175-cip29-rt12%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Bpreempt_rt%2Fgcc-10%2Fkernel%2FbzImage exists
8 12:51:10.406106 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:51:10.406295 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-5.10.y-cip-rt%2Fv5.10.175-cip29-rt12%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Bpreempt_rt%2Fgcc-10%2Fmodules.tar.xz exists
10 12:51:14.189137 validate duration: 4.36
12 12:51:14.189433 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 12:51:14.189593 start: 1.1 download-retry (timeout 00:10:00) [common]
14 12:51:14.189689 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 12:51:14.189787 Not decompressing ramdisk as can be used compressed.
16 12:51:14.189871 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230310.0/x86/rootfs.cpio.gz
17 12:51:14.189937 saving as /var/lib/lava/dispatcher/tmp/9729813/tftp-deploy-89qikdnh/ramdisk/rootfs.cpio.gz
18 12:51:14.190029 total size: 8429740 (8MB)
19 12:51:15.224267 progress 0% (0MB)
20 12:51:15.226622 progress 5% (0MB)
21 12:51:15.228849 progress 10% (0MB)
22 12:51:15.231057 progress 15% (1MB)
23 12:51:15.233150 progress 20% (1MB)
24 12:51:15.235301 progress 25% (2MB)
25 12:51:15.237400 progress 30% (2MB)
26 12:51:15.239520 progress 35% (2MB)
27 12:51:15.241443 progress 40% (3MB)
28 12:51:15.243568 progress 45% (3MB)
29 12:51:15.245634 progress 50% (4MB)
30 12:51:15.247742 progress 55% (4MB)
31 12:51:15.249841 progress 60% (4MB)
32 12:51:15.251928 progress 65% (5MB)
33 12:51:15.253988 progress 70% (5MB)
34 12:51:15.255991 progress 75% (6MB)
35 12:51:15.258055 progress 80% (6MB)
36 12:51:15.260159 progress 85% (6MB)
37 12:51:15.262215 progress 90% (7MB)
38 12:51:15.264303 progress 95% (7MB)
39 12:51:15.266388 progress 100% (8MB)
40 12:51:15.266554 8MB downloaded in 1.08s (7.47MB/s)
41 12:51:15.266723 end: 1.1.1 http-download (duration 00:00:01) [common]
43 12:51:15.266978 end: 1.1 download-retry (duration 00:00:01) [common]
44 12:51:15.267065 start: 1.2 download-retry (timeout 00:09:59) [common]
45 12:51:15.267149 start: 1.2.1 http-download (timeout 00:09:59) [common]
46 12:51:15.267257 downloading http://storage.kernelci.org/cip/linux-5.10.y-cip-rt/v5.10.175-cip29-rt12/x86_64/x86_64_defconfig+x86-chromebook+preempt_rt/gcc-10/kernel/bzImage
47 12:51:15.267322 saving as /var/lib/lava/dispatcher/tmp/9729813/tftp-deploy-89qikdnh/kernel/bzImage
48 12:51:15.267381 total size: 11878592 (11MB)
49 12:51:15.267438 No compression specified
50 12:51:15.268382 progress 0% (0MB)
51 12:51:15.271317 progress 5% (0MB)
52 12:51:15.274145 progress 10% (1MB)
53 12:51:15.277037 progress 15% (1MB)
54 12:51:15.279927 progress 20% (2MB)
55 12:51:15.282782 progress 25% (2MB)
56 12:51:15.285589 progress 30% (3MB)
57 12:51:15.288451 progress 35% (3MB)
58 12:51:15.291446 progress 40% (4MB)
59 12:51:15.294255 progress 45% (5MB)
60 12:51:15.297103 progress 50% (5MB)
61 12:51:15.299962 progress 55% (6MB)
62 12:51:15.302833 progress 60% (6MB)
63 12:51:15.305654 progress 65% (7MB)
64 12:51:15.308574 progress 70% (7MB)
65 12:51:15.311383 progress 75% (8MB)
66 12:51:15.314347 progress 80% (9MB)
67 12:51:15.317162 progress 85% (9MB)
68 12:51:15.320017 progress 90% (10MB)
69 12:51:15.322828 progress 95% (10MB)
70 12:51:15.325605 progress 100% (11MB)
71 12:51:15.325767 11MB downloaded in 0.06s (194.04MB/s)
72 12:51:15.325913 end: 1.2.1 http-download (duration 00:00:00) [common]
74 12:51:15.326146 end: 1.2 download-retry (duration 00:00:00) [common]
75 12:51:15.326232 start: 1.3 download-retry (timeout 00:09:59) [common]
76 12:51:15.326322 start: 1.3.1 http-download (timeout 00:09:59) [common]
77 12:51:15.326432 downloading http://storage.kernelci.org/cip/linux-5.10.y-cip-rt/v5.10.175-cip29-rt12/x86_64/x86_64_defconfig+x86-chromebook+preempt_rt/gcc-10/modules.tar.xz
78 12:51:15.326499 saving as /var/lib/lava/dispatcher/tmp/9729813/tftp-deploy-89qikdnh/modules/modules.tar
79 12:51:15.326566 total size: 1255052 (1MB)
80 12:51:15.326627 Using unxz to decompress xz
81 12:51:15.329612 progress 2% (0MB)
82 12:51:15.330143 progress 7% (0MB)
83 12:51:15.333530 progress 13% (0MB)
84 12:51:15.337391 progress 18% (0MB)
85 12:51:15.341194 progress 23% (0MB)
86 12:51:15.345027 progress 28% (0MB)
87 12:51:15.348824 progress 33% (0MB)
88 12:51:15.352585 progress 39% (0MB)
89 12:51:15.356683 progress 44% (0MB)
90 12:51:15.360386 progress 49% (0MB)
91 12:51:15.364184 progress 54% (0MB)
92 12:51:15.367937 progress 60% (0MB)
93 12:51:15.371656 progress 65% (0MB)
94 12:51:15.375533 progress 70% (0MB)
95 12:51:15.379341 progress 75% (0MB)
96 12:51:15.382960 progress 80% (0MB)
97 12:51:15.386963 progress 86% (1MB)
98 12:51:15.390756 progress 91% (1MB)
99 12:51:15.394674 progress 96% (1MB)
100 12:51:15.404266 1MB downloaded in 0.08s (15.41MB/s)
101 12:51:15.404548 end: 1.3.1 http-download (duration 00:00:00) [common]
103 12:51:15.404818 end: 1.3 download-retry (duration 00:00:00) [common]
104 12:51:15.404966 start: 1.4 prepare-tftp-overlay (timeout 00:09:59) [common]
105 12:51:15.405091 start: 1.4.1 extract-nfsrootfs (timeout 00:09:59) [common]
106 12:51:15.405190 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
107 12:51:15.405275 start: 1.4.2 lava-overlay (timeout 00:09:59) [common]
108 12:51:15.405455 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn
109 12:51:15.405564 makedir: /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin
110 12:51:15.405654 makedir: /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/tests
111 12:51:15.405735 makedir: /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/results
112 12:51:15.405842 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-add-keys
113 12:51:15.405982 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-add-sources
114 12:51:15.406097 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-background-process-start
115 12:51:15.406212 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-background-process-stop
116 12:51:15.406325 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-common-functions
117 12:51:15.406438 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-echo-ipv4
118 12:51:15.406588 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-install-packages
119 12:51:15.406700 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-installed-packages
120 12:51:15.406809 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-os-build
121 12:51:15.406921 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-probe-channel
122 12:51:15.407029 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-probe-ip
123 12:51:15.407137 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-target-ip
124 12:51:15.407244 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-target-mac
125 12:51:15.407350 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-target-storage
126 12:51:15.407466 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-test-case
127 12:51:15.407579 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-test-event
128 12:51:15.407686 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-test-feedback
129 12:51:15.407793 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-test-raise
130 12:51:15.407906 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-test-reference
131 12:51:15.408030 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-test-runner
132 12:51:15.408139 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-test-set
133 12:51:15.408245 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-test-shell
134 12:51:15.408361 Updating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-install-packages (oe)
135 12:51:15.408474 Updating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/bin/lava-installed-packages (oe)
136 12:51:15.408574 Creating /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/environment
137 12:51:15.408662 LAVA metadata
138 12:51:15.408734 - LAVA_JOB_ID=9729813
139 12:51:15.408798 - LAVA_DISPATCHER_IP=192.168.201.1
140 12:51:15.408903 start: 1.4.2.1 lava-vland-overlay (timeout 00:09:59) [common]
141 12:51:15.408968 skipped lava-vland-overlay
142 12:51:15.409043 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
143 12:51:15.409131 start: 1.4.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
144 12:51:15.409197 skipped lava-multinode-overlay
145 12:51:15.409272 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
146 12:51:15.409359 start: 1.4.2.3 test-definition (timeout 00:09:59) [common]
147 12:51:15.409432 Loading test definitions
148 12:51:15.409528 start: 1.4.2.3.1 inline-repo-action (timeout 00:09:59) [common]
149 12:51:15.409607 Using /lava-9729813 at stage 0
150 12:51:15.409874 uuid=9729813_1.4.2.3.1 testdef=None
151 12:51:15.410027 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
152 12:51:15.410151 start: 1.4.2.3.2 test-overlay (timeout 00:09:59) [common]
153 12:51:15.410698 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
155 12:51:15.410933 start: 1.4.2.3.3 test-install-overlay (timeout 00:09:59) [common]
156 12:51:15.411501 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
158 12:51:15.411739 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
159 12:51:15.412282 runner path: /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/0/tests/0_dmesg test_uuid 9729813_1.4.2.3.1
160 12:51:15.412428 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
162 12:51:15.412659 start: 1.4.2.3.5 inline-repo-action (timeout 00:09:59) [common]
163 12:51:15.412735 Using /lava-9729813 at stage 1
164 12:51:15.412982 uuid=9729813_1.4.2.3.5 testdef=None
165 12:51:15.413072 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
166 12:51:15.413159 start: 1.4.2.3.6 test-overlay (timeout 00:09:59) [common]
167 12:51:15.413661 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
169 12:51:15.413889 start: 1.4.2.3.7 test-install-overlay (timeout 00:09:59) [common]
170 12:51:15.414454 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
172 12:51:15.414728 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
173 12:51:15.415271 runner path: /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/1/tests/1_bootrr test_uuid 9729813_1.4.2.3.5
174 12:51:15.415411 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
176 12:51:15.415619 Creating lava-test-runner.conf files
177 12:51:15.415686 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/0 for stage 0
178 12:51:15.415767 - 0_dmesg
179 12:51:15.415839 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/9729813/lava-overlay-ioexn2cn/lava-9729813/1 for stage 1
180 12:51:15.415919 - 1_bootrr
181 12:51:15.416023 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
182 12:51:15.416123 start: 1.4.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:51:15.422455 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
184 12:51:15.422604 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:51:15.422694 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:51:15.422783 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
187 12:51:15.422872 start: 1.4.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:51:15.605004 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 12:51:15.605386 start: 1.4.4 extract-modules (timeout 00:09:59) [common]
190 12:51:15.605501 extracting modules file /var/lib/lava/dispatcher/tmp/9729813/tftp-deploy-89qikdnh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/9729813/extract-overlay-ramdisk-tl7o1cki/ramdisk
191 12:51:15.632354 end: 1.4.4 extract-modules (duration 00:00:00) [common]
192 12:51:15.632511 start: 1.4.5 apply-overlay-tftp (timeout 00:09:59) [common]
193 12:51:15.632603 [common] Applying overlay /var/lib/lava/dispatcher/tmp/9729813/compress-overlay-lsy57dlh/overlay-1.4.2.4.tar.gz to ramdisk
194 12:51:15.632679 [common] Applying overlay /var/lib/lava/dispatcher/tmp/9729813/compress-overlay-lsy57dlh/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/9729813/extract-overlay-ramdisk-tl7o1cki/ramdisk
195 12:51:15.636750 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:51:15.636860 start: 1.4.6 configure-preseed-file (timeout 00:09:59) [common]
197 12:51:15.636952 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
198 12:51:15.637040 start: 1.4.7 compress-ramdisk (timeout 00:09:59) [common]
199 12:51:15.637117 Building ramdisk /var/lib/lava/dispatcher/tmp/9729813/extract-overlay-ramdisk-tl7o1cki/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/9729813/extract-overlay-ramdisk-tl7o1cki/ramdisk
200 12:51:15.718039 >> 62739 blocks
201 12:51:16.678351 rename /var/lib/lava/dispatcher/tmp/9729813/extract-overlay-ramdisk-tl7o1cki/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/9729813/tftp-deploy-89qikdnh/ramdisk/ramdisk.cpio.gz
202 12:51:16.678789 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
203 12:51:16.678915 start: 1.4.8 prepare-kernel (timeout 00:09:58) [common]
204 12:51:16.679018 start: 1.4.8.1 prepare-fit (timeout 00:09:58) [common]
205 12:51:16.679118 No mkimage arch provided, not using FIT.
206 12:51:16.679210 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
207 12:51:16.679299 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
208 12:51:16.679402 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
209 12:51:16.679495 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:58) [common]
210 12:51:16.679577 No LXC device requested
211 12:51:16.679666 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
212 12:51:16.679758 start: 1.6 deploy-device-env (timeout 00:09:58) [common]
213 12:51:16.679840 end: 1.6 deploy-device-env (duration 00:00:00) [common]
214 12:51:16.679910 Checking files for TFTP limit of 4294967296 bytes.
215 12:51:16.680288 end: 1 tftp-deploy (duration 00:00:02) [common]
216 12:51:16.680394 start: 2 depthcharge-action (timeout 00:05:00) [common]
217 12:51:16.680493 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
218 12:51:16.680622 substitutions:
219 12:51:16.680691 - {DTB}: None
220 12:51:16.680756 - {INITRD}: 9729813/tftp-deploy-89qikdnh/ramdisk/ramdisk.cpio.gz
221 12:51:16.680821 - {KERNEL}: 9729813/tftp-deploy-89qikdnh/kernel/bzImage
222 12:51:16.680882 - {LAVA_MAC}: None
223 12:51:16.680940 - {PRESEED_CONFIG}: None
224 12:51:16.680997 - {PRESEED_LOCAL}: None
225 12:51:16.681056 - {RAMDISK}: 9729813/tftp-deploy-89qikdnh/ramdisk/ramdisk.cpio.gz
226 12:51:16.681112 - {ROOT_PART}: None
227 12:51:16.681167 - {ROOT}: None
228 12:51:16.681223 - {SERVER_IP}: 192.168.201.1
229 12:51:16.681281 - {TEE}: None
230 12:51:16.681338 Parsed boot commands:
231 12:51:16.681391 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
232 12:51:16.681544 Parsed boot commands: tftpboot 192.168.201.1 9729813/tftp-deploy-89qikdnh/kernel/bzImage 9729813/tftp-deploy-89qikdnh/kernel/cmdline 9729813/tftp-deploy-89qikdnh/ramdisk/ramdisk.cpio.gz
233 12:51:16.681637 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
234 12:51:16.681729 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
235 12:51:16.681825 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
236 12:51:16.681910 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
237 12:51:16.681980 Not connected, no need to disconnect.
238 12:51:16.682065 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
239 12:51:16.682148 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
240 12:51:16.682219 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost asus-cx9400-volteer-cbg-2'
241 12:51:16.684996 Setting prompt string to ['lava-test: # ']
242 12:51:16.685278 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
243 12:51:16.685383 end: 2.2.1 reset-connection (duration 00:00:00) [common]
244 12:51:16.685486 start: 2.2.2 reset-device (timeout 00:05:00) [common]
245 12:51:16.685581 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
246 12:51:16.685876 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-2' '--port=1' '--command=reboot'
247 12:51:21.829087 >> Command sent successfully.
248 12:51:21.837840 Returned 0 in 5 seconds
249 12:51:21.938992 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
251 12:51:21.940360 end: 2.2.2 reset-device (duration 00:00:05) [common]
252 12:51:21.940851 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
253 12:51:21.941284 Setting prompt string to 'Starting depthcharge on Voema...'
254 12:51:21.941624 Changing prompt to 'Starting depthcharge on Voema...'
255 12:51:21.941972 depthcharge-start: Wait for prompt Starting depthcharge on Voema... (timeout 00:05:00)
256 12:51:21.943187 [Enter `^Ec?' for help]
257 12:51:23.537516
258 12:51:23.538132
259 12:51:23.547204 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 bootblock starting (log level: 8)...
260 12:51:23.554101 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz
261 12:51:23.557280 CPU: ID 806c1, Tigerlake B0, ucode: 00000086
262 12:51:23.560881 CPU: AES supported, TXT NOT supported, VT supported
263 12:51:23.567043 MCH: device id 9a12 (rev 01) is Tigerlake-Y-4-2
264 12:51:23.573790 PCH: device id a087 (rev 20) is Tigerlake-Y Premium SKU
265 12:51:23.577503 IGD: device id 9a40 (rev 01) is Tigerlake Y GT2
266 12:51:23.580355 VBOOT: Loading verstage.
267 12:51:23.587322 FMAP: Found "FLASH" version 1.1 at 0x1804000.
268 12:51:23.590451 FMAP: base = 0x0 size = 0x2000000 #areas = 32
269 12:51:23.596926 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
270 12:51:23.603643 CBFS: mcache @0xfef45600 built for 70 files, used 0xfdc of 0x1800 bytes
271 12:51:23.609939 CBFS: Found 'fallback/verstage' @0x165e40 size 0x147ec in mcache @0xfef45984
272 12:51:23.613770
273 12:51:23.614206
274 12:51:23.623399 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 verstage starting (log level: 8)...
275 12:51:23.638168 Probing TPM: . done!
276 12:51:23.642029 TPM ready after 0 ms
277 12:51:23.645145 Connected to device vid:did:rid of 1ae0:0028:00
278 12:51:23.656294 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6
279 12:51:23.663055 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
280 12:51:23.665975 Initialized TPM device CR50 revision 0
281 12:51:23.718078 tlcl_send_startup: Startup return code is 0
282 12:51:23.718625 TPM: setup succeeded
283 12:51:23.733592 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
284 12:51:23.747307 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
285 12:51:23.760448 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
286 12:51:23.770212 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
287 12:51:23.773945 Chrome EC: UHEPI supported
288 12:51:23.776959 Phase 1
289 12:51:23.780540 FMAP: area GBB found @ 1805000 (458752 bytes)
290 12:51:23.790211 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
291 12:51:23.797048 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
292 12:51:23.803799 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
293 12:51:23.810059 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
294 12:51:23.813775 Recovery requested (1009000e)
295 12:51:23.816840 TPM: Extending digest for VBOOT: boot mode into PCR 0
296 12:51:23.828594 tlcl_extend: response is 0
297 12:51:23.835116 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
298 12:51:23.845114 tlcl_extend: response is 0
299 12:51:23.852184 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
300 12:51:23.858300 CBFS: Found 'fallback/romstage' @0x80 size 0x1bf24 in mcache @0xfef45638
301 12:51:23.865413 BS: verstage times (exec / console): total (unknown) / 142 ms
302 12:51:23.866017
303 12:51:23.866432
304 12:51:23.878664 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 romstage starting (log level: 8)...
305 12:51:23.884671 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
306 12:51:23.888197 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
307 12:51:23.891322 gpe0_sts[0]: 00200000 gpe0_en[0]: 00000000
308 12:51:23.897943 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
309 12:51:23.901105 gpe0_sts[2]: 00001000 gpe0_en[2]: 00000000
310 12:51:23.904869 gpe0_sts[3]: 00000000 gpe0_en[3]: 00010000
311 12:51:23.907910 TCO_STS: 0000 0000
312 12:51:23.911455 GEN_PMCON: d0015038 00002200
313 12:51:23.914452 GBLRST_CAUSE: 00000000 00000000
314 12:51:23.917597 HPR_CAUSE0: 00000000
315 12:51:23.918032 prev_sleep_state 5
316 12:51:23.921409 Boot Count incremented to 18611
317 12:51:23.927556 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
318 12:51:23.934726 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
319 12:51:23.943944 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
320 12:51:23.950894 CBFS: Found 'fspm.bin' @0x78fc0 size 0xa5000 in mcache @0xfef4585c
321 12:51:23.953990 Chrome EC: UHEPI supported
322 12:51:23.960320 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
323 12:51:23.972356 Probing TPM: done!
324 12:51:23.978827 Connected to device vid:did:rid of 1ae0:0028:00
325 12:51:23.989828 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6
326 12:51:23.997140 Initialized TPM device CR50 revision 0
327 12:51:24.006977 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
328 12:51:24.013680 MRC: Hash idx 0x100b comparison successful.
329 12:51:24.017307 MRC cache found, size faa8
330 12:51:24.017750 bootmode is set to: 2
331 12:51:24.020343 SPD index = 0
332 12:51:24.027124 CBFS: Found 'spd.bin' @0x72940 size 0x600 in mcache @0xfef4579c
333 12:51:24.030196 SPD: module type is LPDDR4X
334 12:51:24.033233 SPD: module part number is MT53E512M64D4NW-046
335 12:51:24.040106 SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb
336 12:51:24.043671 SPD: device width 16 bits, bus width 16 bits
337 12:51:24.049926 SPD: module size is 1024 MB (per channel)
338 12:51:24.482262 CBMEM:
339 12:51:24.485861 IMD: root @ 0x76fff000 254 entries.
340 12:51:24.488879 IMD: root @ 0x76ffec00 62 entries.
341 12:51:24.492027 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
342 12:51:24.498838 FMAP: area RW_VPD found @ f35000 (8192 bytes)
343 12:51:24.501934 External stage cache:
344 12:51:24.505131 IMD: root @ 0x7b3ff000 254 entries.
345 12:51:24.508751 IMD: root @ 0x7b3fec00 62 entries.
346 12:51:24.524028 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
347 12:51:24.530547 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
348 12:51:24.537281 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
349 12:51:24.551128 MRC: 'RECOVERY_MRC_CACHE' does not need update.
350 12:51:24.558096 cse_lite: Skip switching to RW in the recovery path
351 12:51:24.558609 8 DIMMs found
352 12:51:24.561280 SMM Memory Map
353 12:51:24.564989 SMRAM : 0x7b000000 0x800000
354 12:51:24.568357 Subregion 0: 0x7b000000 0x200000
355 12:51:24.571866 Subregion 1: 0x7b200000 0x200000
356 12:51:24.572390 Subregion 2: 0x7b400000 0x400000
357 12:51:24.575726 top_of_ram = 0x77000000
358 12:51:24.581697 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
359 12:51:24.584871 MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
360 12:51:24.591885 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
361 12:51:24.594862 MTRR Range: Start=ff000000 End=0 (Size 1000000)
362 12:51:24.604881 CBFS: Found 'fallback/postcar' @0x160900 size 0x54f8 in mcache @0xfef4594c
363 12:51:24.611690 Decompressing stage fallback/postcar @ 0x76c0afc0 (38208 bytes)
364 12:51:24.621673 Loading module at 0x76c0b000 with entry 0x76c0b000. filesize: 0x5150 memsize: 0x9500
365 12:51:24.624559 Processing 211 relocs. Offset value of 0x74c0b000
366 12:51:24.634283 BS: romstage times (exec / console): total (unknown) / 277 ms
367 12:51:24.640306
368 12:51:24.640746
369 12:51:24.650090 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 postcar starting (log level: 8)...
370 12:51:24.653796 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
371 12:51:24.663644 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
372 12:51:24.669774 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
373 12:51:24.676612 CBFS: Found 'fallback/ramstage' @0x524c0 size 0x1fbe3 in mcache @0x76c4c0ec
374 12:51:24.683583 Decompressing stage fallback/ramstage @ 0x76b97fc0 (463536 bytes)
375 12:51:24.730469 Loading module at 0x76b98000 with entry 0x76b98000. filesize: 0x4d5d8 memsize: 0x71270
376 12:51:24.737047 Processing 5008 relocs. Offset value of 0x75d98000
377 12:51:24.740389 BS: postcar times (exec / console): total (unknown) / 59 ms
378 12:51:24.743445
379 12:51:24.743932
380 12:51:24.753581 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 ramstage starting (log level: 8)...
381 12:51:24.754051 Normal boot
382 12:51:24.756704 FW_CONFIG value is 0x804c02
383 12:51:24.760136 PCI: 00:07.0 disabled by fw_config
384 12:51:24.763929 PCI: 00:07.1 disabled by fw_config
385 12:51:24.767140 PCI: 00:0d.2 disabled by fw_config
386 12:51:24.770279 PCI: 00:1c.7 disabled by fw_config
387 12:51:24.777033 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
388 12:51:24.783920 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
389 12:51:24.787030 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
390 12:51:24.790282 GENERIC: 0.0 disabled by fw_config
391 12:51:24.797251 GENERIC: 1.0 disabled by fw_config
392 12:51:24.800334 fw_config match found: DB_USB=USB3_ACTIVE
393 12:51:24.803356 fw_config match found: DB_USB=USB3_ACTIVE
394 12:51:24.807199 fw_config match found: DB_USB=USB3_ACTIVE
395 12:51:24.813464 fw_config match found: DB_USB=USB3_ACTIVE
396 12:51:24.817049 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
397 12:51:24.823558 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
398 12:51:24.833399 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
399 12:51:24.840047 CBFS: Found 'cpu_microcode_blob.bin' @0x1c040 size 0x36400 in mcache @0x76c4c09c
400 12:51:24.843141 microcode: sig=0x806c1 pf=0x80 revision=0x86
401 12:51:24.849639 microcode: Update skipped, already up-to-date
402 12:51:24.856650 CBFS: Found 'fsps.bin' @0x11efc0 size 0x418f9 in mcache @0x76c4c30c
403 12:51:24.884336 Detected 4 core, 8 thread CPU.
404 12:51:24.887343 Setting up SMI for CPU
405 12:51:24.890579 IED base = 0x7b400000
406 12:51:24.891034 IED size = 0x00400000
407 12:51:24.893642 Will perform SMM setup.
408 12:51:24.900540 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz.
409 12:51:24.907166 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
410 12:51:24.913050 Processing 16 relocs. Offset value of 0x00030000
411 12:51:24.916810 Attempting to start 7 APs
412 12:51:24.919750 Waiting for 10ms after sending INIT.
413 12:51:24.935751 Waiting for 1st SIPI to complete...AP: slot 1 apic_id 1.
414 12:51:24.938792 AP: slot 5 apic_id 4.
415 12:51:24.938885 done.
416 12:51:24.942405 AP: slot 4 apic_id 5.
417 12:51:24.942511 AP: slot 6 apic_id 2.
418 12:51:24.946054 AP: slot 2 apic_id 3.
419 12:51:24.949307 AP: slot 3 apic_id 6.
420 12:51:24.949396 AP: slot 7 apic_id 7.
421 12:51:24.955782 Waiting for 2nd SIPI to complete...done.
422 12:51:24.962197 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
423 12:51:24.968823 Processing 13 relocs. Offset value of 0x00038000
424 12:51:24.971845 Unable to locate Global NVS
425 12:51:24.978678 SMM Module: stub loaded at 0x00038000. Will call 0x76bb6318(0x00000000)
426 12:51:24.981806 Installing permanent SMM handler to 0x7b000000
427 12:51:24.992257 Loading module at 0x7b010000 with entry 0x7b010c16. filesize: 0xa7c8 memsize: 0xf908
428 12:51:24.995380 Processing 794 relocs. Offset value of 0x7b010000
429 12:51:25.005444 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8
430 12:51:25.008515 Processing 13 relocs. Offset value of 0x7b008000
431 12:51:25.015244 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
432 12:51:25.021893 SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
433 12:51:25.024887 SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
434 12:51:25.031642 SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
435 12:51:25.038295 SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
436 12:51:25.045043 SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
437 12:51:25.051688 SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
438 12:51:25.051777 Unable to locate Global NVS
439 12:51:25.061504 SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c16(0x00000000)
440 12:51:25.065122 Clearing SMI status registers
441 12:51:25.065211 SMI_STS: PM1
442 12:51:25.068312 PM1_STS: PWRBTN
443 12:51:25.074415 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
444 12:51:25.077976 In relocation handler: CPU 0
445 12:51:25.081601 New SMBASE=0x7b000000 IEDBASE=0x7b400000
446 12:51:25.087850 Writing SMRR. base = 0x7b000006, mask=0xff800c00
447 12:51:25.091339 Relocation complete.
448 12:51:25.097657 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
449 12:51:25.100890 In relocation handler: CPU 1
450 12:51:25.104669 New SMBASE=0x7afffc00 IEDBASE=0x7b400000
451 12:51:25.107728 Relocation complete.
452 12:51:25.114456 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
453 12:51:25.117525 In relocation handler: CPU 2
454 12:51:25.120680 New SMBASE=0x7afff800 IEDBASE=0x7b400000
455 12:51:25.120768 Relocation complete.
456 12:51:25.131203 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
457 12:51:25.134359 In relocation handler: CPU 6
458 12:51:25.137399 New SMBASE=0x7affe800 IEDBASE=0x7b400000
459 12:51:25.141032 Writing SMRR. base = 0x7b000006, mask=0xff800c00
460 12:51:25.144184 Relocation complete.
461 12:51:25.150824 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
462 12:51:25.154341 In relocation handler: CPU 7
463 12:51:25.157403 New SMBASE=0x7affe400 IEDBASE=0x7b400000
464 12:51:25.161039 Relocation complete.
465 12:51:25.167562 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
466 12:51:25.170683 In relocation handler: CPU 3
467 12:51:25.173837 New SMBASE=0x7afff400 IEDBASE=0x7b400000
468 12:51:25.180521 Writing SMRR. base = 0x7b000006, mask=0xff800c00
469 12:51:25.180613 Relocation complete.
470 12:51:25.190415 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
471 12:51:25.190509 In relocation handler: CPU 5
472 12:51:25.197172 New SMBASE=0x7affec00 IEDBASE=0x7b400000
473 12:51:25.200149 Writing SMRR. base = 0x7b000006, mask=0xff800c00
474 12:51:25.203973 Relocation complete.
475 12:51:25.210342 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
476 12:51:25.213475 In relocation handler: CPU 4
477 12:51:25.217215 New SMBASE=0x7afff000 IEDBASE=0x7b400000
478 12:51:25.220167 Relocation complete.
479 12:51:25.220243 Initializing CPU #0
480 12:51:25.223811 CPU: vendor Intel device 806c1
481 12:51:25.230086 CPU: family 06, model 8c, stepping 01
482 12:51:25.230170 Clearing out pending MCEs
483 12:51:25.233116 Setting up local APIC...
484 12:51:25.236683 apic_id: 0x00 done.
485 12:51:25.241033 Turbo is available but hidden
486 12:51:25.241128 Turbo is available and visible
487 12:51:25.247831 microcode: Update skipped, already up-to-date
488 12:51:25.247916 CPU #0 initialized
489 12:51:25.250992 Initializing CPU #1
490 12:51:25.254150 Initializing CPU #6
491 12:51:25.254228 Initializing CPU #2
492 12:51:25.257595 CPU: vendor Intel device 806c1
493 12:51:25.260748 CPU: family 06, model 8c, stepping 01
494 12:51:25.264529 CPU: vendor Intel device 806c1
495 12:51:25.271081 CPU: family 06, model 8c, stepping 01
496 12:51:25.271195 Clearing out pending MCEs
497 12:51:25.273935 Clearing out pending MCEs
498 12:51:25.277543 Initializing CPU #7
499 12:51:25.277649 Initializing CPU #3
500 12:51:25.280601 CPU: vendor Intel device 806c1
501 12:51:25.284383 CPU: family 06, model 8c, stepping 01
502 12:51:25.287468 CPU: vendor Intel device 806c1
503 12:51:25.294316 CPU: family 06, model 8c, stepping 01
504 12:51:25.294408 Clearing out pending MCEs
505 12:51:25.297311 Clearing out pending MCEs
506 12:51:25.300480 Setting up local APIC...
507 12:51:25.300571 Initializing CPU #4
508 12:51:25.304182 Initializing CPU #5
509 12:51:25.307340 CPU: vendor Intel device 806c1
510 12:51:25.310419 CPU: family 06, model 8c, stepping 01
511 12:51:25.314162 CPU: vendor Intel device 806c1
512 12:51:25.317311 CPU: family 06, model 8c, stepping 01
513 12:51:25.320457 Clearing out pending MCEs
514 12:51:25.324145 Clearing out pending MCEs
515 12:51:25.327271 Setting up local APIC...
516 12:51:25.327359 Setting up local APIC...
517 12:51:25.330397 apic_id: 0x07 done.
518 12:51:25.333497 Setting up local APIC...
519 12:51:25.336967 apic_id: 0x05 done.
520 12:51:25.337065 Setting up local APIC...
521 12:51:25.343727 microcode: Update skipped, already up-to-date
522 12:51:25.343827 apic_id: 0x06 done.
523 12:51:25.346970 CPU #7 initialized
524 12:51:25.350436 microcode: Update skipped, already up-to-date
525 12:51:25.353558 CPU: vendor Intel device 806c1
526 12:51:25.356648 CPU: family 06, model 8c, stepping 01
527 12:51:25.360356 apic_id: 0x04 done.
528 12:51:25.363648 microcode: Update skipped, already up-to-date
529 12:51:25.369954 microcode: Update skipped, already up-to-date
530 12:51:25.370052 CPU #4 initialized
531 12:51:25.373618 CPU #5 initialized
532 12:51:25.376830 CPU #3 initialized
533 12:51:25.376916 Setting up local APIC...
534 12:51:25.380271 Clearing out pending MCEs
535 12:51:25.383282 apic_id: 0x03 done.
536 12:51:25.383368 apic_id: 0x02 done.
537 12:51:25.390114 microcode: Update skipped, already up-to-date
538 12:51:25.393258 microcode: Update skipped, already up-to-date
539 12:51:25.396408 CPU #2 initialized
540 12:51:25.396494 CPU #6 initialized
541 12:51:25.400205 Setting up local APIC...
542 12:51:25.403129 apic_id: 0x01 done.
543 12:51:25.406265 microcode: Update skipped, already up-to-date
544 12:51:25.409956 CPU #1 initialized
545 12:51:25.413153 bsp_do_flight_plan done after 455 msecs.
546 12:51:25.416233 CPU: frequency set to 4000 MHz
547 12:51:25.419900 Enabling SMIs.
548 12:51:25.426216 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 347 / 317 ms
549 12:51:25.440470 SATAXPCIE1 indicates PCIe NVMe is present
550 12:51:25.444205 Probing TPM: done!
551 12:51:25.447830 Connected to device vid:did:rid of 1ae0:0028:00
552 12:51:25.458335 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6
553 12:51:25.461343 Initialized TPM device CR50 revision 0
554 12:51:25.464470 Enabling S0i3.4
555 12:51:25.471094 CBFS: Found 'vbt.bin' @0x78a40 size 0x4f0 in mcache @0x76c4c1fc
556 12:51:25.474736 Found a VBT of 8704 bytes after decompression
557 12:51:25.480851 cse_lite: CSE RO boot. HybridStorageMode disabled
558 12:51:25.487711 WEAK: src/soc/intel/tigerlake/fsp_params.c/mainboard_silicon_init_params called
559 12:51:25.562917 FSPS returned 0
560 12:51:25.565929 Executing Phase 1 of FspMultiPhaseSiInit
561 12:51:25.576345 FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
562 12:51:25.579318 port C0 DISC req: usage 1 usb3 1 usb2 5
563 12:51:25.582398 Raw Buffer output 0 00000511
564 12:51:25.586227 Raw Buffer output 1 00000000
565 12:51:25.589890 pmc_send_ipc_cmd succeeded
566 12:51:25.596029 port C1 DISC req: usage 1 usb3 2 usb2 3
567 12:51:25.596123 Raw Buffer output 0 00000321
568 12:51:25.599644 Raw Buffer output 1 00000000
569 12:51:25.604072 pmc_send_ipc_cmd succeeded
570 12:51:25.609132 Detected 4 core, 8 thread CPU.
571 12:51:25.612093 Detected 4 core, 8 thread CPU.
572 12:51:25.846482 Display FSP Version Info HOB
573 12:51:25.849943 Reference Code - CPU = a.0.4c.31
574 12:51:25.853109 uCode Version = 0.0.0.86
575 12:51:25.856269 TXT ACM version = ff.ff.ff.ffff
576 12:51:25.859914 Reference Code - ME = a.0.4c.31
577 12:51:25.862972 MEBx version = 0.0.0.0
578 12:51:25.866111 ME Firmware Version = Consumer SKU
579 12:51:25.869987 Reference Code - PCH = a.0.4c.31
580 12:51:25.873015 PCH-CRID Status = Disabled
581 12:51:25.876685 PCH-CRID Original Value = ff.ff.ff.ffff
582 12:51:25.879617 PCH-CRID New Value = ff.ff.ff.ffff
583 12:51:25.883248 OPROM - RST - RAID = ff.ff.ff.ffff
584 12:51:25.886301 PCH Hsio Version = 4.0.0.0
585 12:51:25.889970 Reference Code - SA - System Agent = a.0.4c.31
586 12:51:25.893020 Reference Code - MRC = 2.0.0.1
587 12:51:25.896159 SA - PCIe Version = a.0.4c.31
588 12:51:25.899777 SA-CRID Status = Disabled
589 12:51:25.902885 SA-CRID Original Value = 0.0.0.1
590 12:51:25.906615 SA-CRID New Value = 0.0.0.1
591 12:51:25.909639 OPROM - VBIOS = ff.ff.ff.ffff
592 12:51:25.912678 IO Manageability Engine FW Version = 11.1.4.0
593 12:51:25.916466 PHY Build Version = 0.0.0.e0
594 12:51:25.919496 Thunderbolt(TM) FW Version = 0.0.0.0
595 12:51:25.926259 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
596 12:51:25.930220 ITSS IRQ Polarities Before:
597 12:51:25.930691 IPC0: 0xffffffff
598 12:51:25.932752 IPC1: 0xffffffff
599 12:51:25.933174 IPC2: 0xffffffff
600 12:51:25.936529 IPC3: 0xffffffff
601 12:51:25.939812 ITSS IRQ Polarities After:
602 12:51:25.940251 IPC0: 0xffffffff
603 12:51:25.942989 IPC1: 0xffffffff
604 12:51:25.943427 IPC2: 0xffffffff
605 12:51:25.946033 IPC3: 0xffffffff
606 12:51:25.949749 Found PCIe Root Port #9 at PCI: 00:1d.0.
607 12:51:25.962584 pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
608 12:51:25.972698 pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing.
609 12:51:25.985945 pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
610 12:51:25.992583 BS: BS_DEV_INIT_CHIPS run times (exec / console): 325 / 236 ms
611 12:51:25.995504 Enumerating buses...
612 12:51:25.999246 Show all devs... Before device enumeration.
613 12:51:26.002354 Root Device: enabled 1
614 12:51:26.002861 DOMAIN: 0000: enabled 1
615 12:51:26.005547 CPU_CLUSTER: 0: enabled 1
616 12:51:26.008763 PCI: 00:00.0: enabled 1
617 12:51:26.011885 PCI: 00:02.0: enabled 1
618 12:51:26.011970 PCI: 00:04.0: enabled 1
619 12:51:26.015474 PCI: 00:05.0: enabled 1
620 12:51:26.018586 PCI: 00:06.0: enabled 0
621 12:51:26.021632 PCI: 00:07.0: enabled 0
622 12:51:26.021717 PCI: 00:07.1: enabled 0
623 12:51:26.025508 PCI: 00:07.2: enabled 0
624 12:51:26.028493 PCI: 00:07.3: enabled 0
625 12:51:26.031607 PCI: 00:08.0: enabled 1
626 12:51:26.031693 PCI: 00:09.0: enabled 0
627 12:51:26.035376 PCI: 00:0a.0: enabled 0
628 12:51:26.038409 PCI: 00:0d.0: enabled 1
629 12:51:26.041603 PCI: 00:0d.1: enabled 0
630 12:51:26.041689 PCI: 00:0d.2: enabled 0
631 12:51:26.044782 PCI: 00:0d.3: enabled 0
632 12:51:26.048548 PCI: 00:0e.0: enabled 0
633 12:51:26.051627 PCI: 00:10.2: enabled 1
634 12:51:26.051712 PCI: 00:10.6: enabled 0
635 12:51:26.055256 PCI: 00:10.7: enabled 0
636 12:51:26.058303 PCI: 00:12.0: enabled 0
637 12:51:26.058388 PCI: 00:12.6: enabled 0
638 12:51:26.061819 PCI: 00:13.0: enabled 0
639 12:51:26.064951 PCI: 00:14.0: enabled 1
640 12:51:26.068030 PCI: 00:14.1: enabled 0
641 12:51:26.068115 PCI: 00:14.2: enabled 1
642 12:51:26.071713 PCI: 00:14.3: enabled 1
643 12:51:26.074658 PCI: 00:15.0: enabled 1
644 12:51:26.077781 PCI: 00:15.1: enabled 1
645 12:51:26.077866 PCI: 00:15.2: enabled 1
646 12:51:26.081488 PCI: 00:15.3: enabled 1
647 12:51:26.084613 PCI: 00:16.0: enabled 1
648 12:51:26.087764 PCI: 00:16.1: enabled 0
649 12:51:26.087849 PCI: 00:16.2: enabled 0
650 12:51:26.091329 PCI: 00:16.3: enabled 0
651 12:51:26.094438 PCI: 00:16.4: enabled 0
652 12:51:26.098040 PCI: 00:16.5: enabled 0
653 12:51:26.098131 PCI: 00:17.0: enabled 1
654 12:51:26.101015 PCI: 00:19.0: enabled 0
655 12:51:26.104269 PCI: 00:19.1: enabled 1
656 12:51:26.107504 PCI: 00:19.2: enabled 0
657 12:51:26.107589 PCI: 00:1c.0: enabled 1
658 12:51:26.111285 PCI: 00:1c.1: enabled 0
659 12:51:26.114343 PCI: 00:1c.2: enabled 0
660 12:51:26.114429 PCI: 00:1c.3: enabled 0
661 12:51:26.117525 PCI: 00:1c.4: enabled 0
662 12:51:26.121182 PCI: 00:1c.5: enabled 0
663 12:51:26.124354 PCI: 00:1c.6: enabled 1
664 12:51:26.124440 PCI: 00:1c.7: enabled 0
665 12:51:26.127513 PCI: 00:1d.0: enabled 1
666 12:51:26.131226 PCI: 00:1d.1: enabled 0
667 12:51:26.134271 PCI: 00:1d.2: enabled 1
668 12:51:26.134356 PCI: 00:1d.3: enabled 0
669 12:51:26.137405 PCI: 00:1e.0: enabled 1
670 12:51:26.141177 PCI: 00:1e.1: enabled 0
671 12:51:26.144357 PCI: 00:1e.2: enabled 1
672 12:51:26.144442 PCI: 00:1e.3: enabled 1
673 12:51:26.147505 PCI: 00:1f.0: enabled 1
674 12:51:26.150636 PCI: 00:1f.1: enabled 0
675 12:51:26.154355 PCI: 00:1f.2: enabled 1
676 12:51:26.154441 PCI: 00:1f.3: enabled 1
677 12:51:26.157509 PCI: 00:1f.4: enabled 0
678 12:51:26.160602 PCI: 00:1f.5: enabled 1
679 12:51:26.164255 PCI: 00:1f.6: enabled 0
680 12:51:26.164343 PCI: 00:1f.7: enabled 0
681 12:51:26.167327 APIC: 00: enabled 1
682 12:51:26.170347 GENERIC: 0.0: enabled 1
683 12:51:26.170432 GENERIC: 0.0: enabled 1
684 12:51:26.174105 GENERIC: 1.0: enabled 1
685 12:51:26.177254 GENERIC: 0.0: enabled 1
686 12:51:26.180817 GENERIC: 1.0: enabled 1
687 12:51:26.180901 USB0 port 0: enabled 1
688 12:51:26.183770 GENERIC: 0.0: enabled 1
689 12:51:26.186934 USB0 port 0: enabled 1
690 12:51:26.187020 GENERIC: 0.0: enabled 1
691 12:51:26.190627 I2C: 00:1a: enabled 1
692 12:51:26.193639 I2C: 00:31: enabled 1
693 12:51:26.196733 I2C: 00:32: enabled 1
694 12:51:26.196819 I2C: 00:10: enabled 1
695 12:51:26.200572 I2C: 00:15: enabled 1
696 12:51:26.203600 GENERIC: 0.0: enabled 0
697 12:51:26.203680 GENERIC: 1.0: enabled 0
698 12:51:26.206740 GENERIC: 0.0: enabled 1
699 12:51:26.210495 SPI: 00: enabled 1
700 12:51:26.210620 SPI: 00: enabled 1
701 12:51:26.213572 PNP: 0c09.0: enabled 1
702 12:51:26.216688 GENERIC: 0.0: enabled 1
703 12:51:26.216773 USB3 port 0: enabled 1
704 12:51:26.220432 USB3 port 1: enabled 1
705 12:51:26.223544 USB3 port 2: enabled 0
706 12:51:26.227095 USB3 port 3: enabled 0
707 12:51:26.227180 USB2 port 0: enabled 0
708 12:51:26.230205 USB2 port 1: enabled 1
709 12:51:26.233284 USB2 port 2: enabled 1
710 12:51:26.233391 USB2 port 3: enabled 0
711 12:51:26.236378 USB2 port 4: enabled 1
712 12:51:26.240180 USB2 port 5: enabled 0
713 12:51:26.243134 USB2 port 6: enabled 0
714 12:51:26.243215 USB2 port 7: enabled 0
715 12:51:26.246248 USB2 port 8: enabled 0
716 12:51:26.250152 USB2 port 9: enabled 0
717 12:51:26.250242 USB3 port 0: enabled 0
718 12:51:26.253384 USB3 port 1: enabled 1
719 12:51:26.256290 USB3 port 2: enabled 0
720 12:51:26.260029 USB3 port 3: enabled 0
721 12:51:26.260112 GENERIC: 0.0: enabled 1
722 12:51:26.263289 GENERIC: 1.0: enabled 1
723 12:51:26.266292 APIC: 01: enabled 1
724 12:51:26.266377 APIC: 03: enabled 1
725 12:51:26.269479 APIC: 06: enabled 1
726 12:51:26.269560 APIC: 05: enabled 1
727 12:51:26.273023 APIC: 04: enabled 1
728 12:51:26.276234 APIC: 02: enabled 1
729 12:51:26.276330 APIC: 07: enabled 1
730 12:51:26.279507 Compare with tree...
731 12:51:26.283227 Root Device: enabled 1
732 12:51:26.283307 DOMAIN: 0000: enabled 1
733 12:51:26.286187 PCI: 00:00.0: enabled 1
734 12:51:26.289412 PCI: 00:02.0: enabled 1
735 12:51:26.293096 PCI: 00:04.0: enabled 1
736 12:51:26.296112 GENERIC: 0.0: enabled 1
737 12:51:26.296193 PCI: 00:05.0: enabled 1
738 12:51:26.299775 PCI: 00:06.0: enabled 0
739 12:51:26.302839 PCI: 00:07.0: enabled 0
740 12:51:26.305965 GENERIC: 0.0: enabled 1
741 12:51:26.309590 PCI: 00:07.1: enabled 0
742 12:51:26.312881 GENERIC: 1.0: enabled 1
743 12:51:26.312958 PCI: 00:07.2: enabled 0
744 12:51:26.316046 GENERIC: 0.0: enabled 1
745 12:51:26.319029 PCI: 00:07.3: enabled 0
746 12:51:26.322734 GENERIC: 1.0: enabled 1
747 12:51:26.325817 PCI: 00:08.0: enabled 1
748 12:51:26.325895 PCI: 00:09.0: enabled 0
749 12:51:26.329329 PCI: 00:0a.0: enabled 0
750 12:51:26.332437 PCI: 00:0d.0: enabled 1
751 12:51:26.335770 USB0 port 0: enabled 1
752 12:51:26.339755 USB3 port 0: enabled 1
753 12:51:26.340197 USB3 port 1: enabled 1
754 12:51:26.342813 USB3 port 2: enabled 0
755 12:51:26.345803 USB3 port 3: enabled 0
756 12:51:26.348962 PCI: 00:0d.1: enabled 0
757 12:51:26.352649 PCI: 00:0d.2: enabled 0
758 12:51:26.355689 GENERIC: 0.0: enabled 1
759 12:51:26.356213 PCI: 00:0d.3: enabled 0
760 12:51:26.359544 PCI: 00:0e.0: enabled 0
761 12:51:26.362694 PCI: 00:10.2: enabled 1
762 12:51:26.365732 PCI: 00:10.6: enabled 0
763 12:51:26.368864 PCI: 00:10.7: enabled 0
764 12:51:26.369391 PCI: 00:12.0: enabled 0
765 12:51:26.372494 PCI: 00:12.6: enabled 0
766 12:51:26.375890 PCI: 00:13.0: enabled 0
767 12:51:26.378942 PCI: 00:14.0: enabled 1
768 12:51:26.382118 USB0 port 0: enabled 1
769 12:51:26.382629 USB2 port 0: enabled 0
770 12:51:26.385177 USB2 port 1: enabled 1
771 12:51:26.388852 USB2 port 2: enabled 1
772 12:51:26.391897 USB2 port 3: enabled 0
773 12:51:26.395549 USB2 port 4: enabled 1
774 12:51:26.398643 USB2 port 5: enabled 0
775 12:51:26.399076 USB2 port 6: enabled 0
776 12:51:26.402396 USB2 port 7: enabled 0
777 12:51:26.405249 USB2 port 8: enabled 0
778 12:51:26.409022 USB2 port 9: enabled 0
779 12:51:26.412103 USB3 port 0: enabled 0
780 12:51:26.412658 USB3 port 1: enabled 1
781 12:51:26.415041 USB3 port 2: enabled 0
782 12:51:26.418687 USB3 port 3: enabled 0
783 12:51:26.421795 PCI: 00:14.1: enabled 0
784 12:51:26.425591 PCI: 00:14.2: enabled 1
785 12:51:26.428724 PCI: 00:14.3: enabled 1
786 12:51:26.429170 GENERIC: 0.0: enabled 1
787 12:51:26.431722 PCI: 00:15.0: enabled 1
788 12:51:26.435328 I2C: 00:1a: enabled 1
789 12:51:26.438611 I2C: 00:31: enabled 1
790 12:51:26.439054 I2C: 00:32: enabled 1
791 12:51:26.441551 PCI: 00:15.1: enabled 1
792 12:51:26.444923 I2C: 00:10: enabled 1
793 12:51:26.448450 PCI: 00:15.2: enabled 1
794 12:51:26.451426 PCI: 00:15.3: enabled 1
795 12:51:26.451894 PCI: 00:16.0: enabled 1
796 12:51:26.455263 PCI: 00:16.1: enabled 0
797 12:51:26.458289 PCI: 00:16.2: enabled 0
798 12:51:26.461551 PCI: 00:16.3: enabled 0
799 12:51:26.465075 PCI: 00:16.4: enabled 0
800 12:51:26.465522 PCI: 00:16.5: enabled 0
801 12:51:26.468319 PCI: 00:17.0: enabled 1
802 12:51:26.471365 PCI: 00:19.0: enabled 0
803 12:51:26.474546 PCI: 00:19.1: enabled 1
804 12:51:26.478297 I2C: 00:15: enabled 1
805 12:51:26.478802 PCI: 00:19.2: enabled 0
806 12:51:26.481343 PCI: 00:1d.0: enabled 1
807 12:51:26.484798 GENERIC: 0.0: enabled 1
808 12:51:26.534822 PCI: 00:1e.0: enabled 1
809 12:51:26.535322 PCI: 00:1e.1: enabled 0
810 12:51:26.535717 PCI: 00:1e.2: enabled 1
811 12:51:26.536172 SPI: 00: enabled 1
812 12:51:26.536720 PCI: 00:1e.3: enabled 1
813 12:51:26.537225 SPI: 00: enabled 1
814 12:51:26.537563 PCI: 00:1f.0: enabled 1
815 12:51:26.537879 PNP: 0c09.0: enabled 1
816 12:51:26.538570 PCI: 00:1f.1: enabled 0
817 12:51:26.538947 PCI: 00:1f.2: enabled 1
818 12:51:26.539478 GENERIC: 0.0: enabled 1
819 12:51:26.539925 GENERIC: 0.0: enabled 1
820 12:51:26.540318 GENERIC: 1.0: enabled 1
821 12:51:26.540632 PCI: 00:1f.3: enabled 1
822 12:51:26.540937 PCI: 00:1f.4: enabled 0
823 12:51:26.541230 PCI: 00:1f.5: enabled 1
824 12:51:26.541523 PCI: 00:1f.6: enabled 0
825 12:51:26.541812 PCI: 00:1f.7: enabled 0
826 12:51:26.542098 CPU_CLUSTER: 0: enabled 1
827 12:51:26.586832 APIC: 00: enabled 1
828 12:51:26.587317 APIC: 01: enabled 1
829 12:51:26.587667 APIC: 03: enabled 1
830 12:51:26.587993 APIC: 06: enabled 1
831 12:51:26.588306 APIC: 05: enabled 1
832 12:51:26.588611 APIC: 04: enabled 1
833 12:51:26.588909 APIC: 02: enabled 1
834 12:51:26.589209 APIC: 07: enabled 1
835 12:51:26.589501 Root Device scanning...
836 12:51:26.590126 scan_static_bus for Root Device
837 12:51:26.590447 DOMAIN: 0000 enabled
838 12:51:26.590799 CPU_CLUSTER: 0 enabled
839 12:51:26.591097 DOMAIN: 0000 scanning...
840 12:51:26.591388 PCI: pci_scan_bus for bus 00
841 12:51:26.591680 PCI: 00:00.0 [8086/0000] ops
842 12:51:26.591971 PCI: 00:00.0 [8086/9a12] enabled
843 12:51:26.592260 PCI: 00:02.0 [8086/0000] bus ops
844 12:51:26.592546 PCI: 00:02.0 [8086/9a40] enabled
845 12:51:26.592831 PCI: 00:04.0 [8086/0000] bus ops
846 12:51:26.637109 PCI: 00:04.0 [8086/9a03] enabled
847 12:51:26.637578 PCI: 00:05.0 [8086/9a19] enabled
848 12:51:26.637928 PCI: 00:07.0 [0000/0000] hidden
849 12:51:26.638256 PCI: 00:08.0 [8086/9a11] enabled
850 12:51:26.639167 PCI: 00:0a.0 [8086/9a0d] disabled
851 12:51:26.639584 PCI: 00:0d.0 [8086/0000] bus ops
852 12:51:26.639919 PCI: 00:0d.0 [8086/9a13] enabled
853 12:51:26.640234 PCI: 00:14.0 [8086/0000] bus ops
854 12:51:26.640560 PCI: 00:14.0 [8086/a0ed] enabled
855 12:51:26.640862 PCI: 00:14.2 [8086/a0ef] enabled
856 12:51:26.641157 PCI: 00:14.3 [8086/0000] bus ops
857 12:51:26.641449 PCI: 00:14.3 [8086/a0f0] enabled
858 12:51:26.641830 PCI: 00:15.0 [8086/0000] bus ops
859 12:51:26.642232 PCI: 00:15.0 [8086/a0e8] enabled
860 12:51:26.642579 PCI: 00:15.1 [8086/0000] bus ops
861 12:51:26.673468 PCI: 00:15.1 [8086/a0e9] enabled
862 12:51:26.673947 PCI: 00:15.2 [8086/0000] bus ops
863 12:51:26.674300 PCI: 00:15.2 [8086/a0ea] enabled
864 12:51:26.674673 PCI: 00:15.3 [8086/0000] bus ops
865 12:51:26.675340 PCI: 00:15.3 [8086/a0eb] enabled
866 12:51:26.675694 PCI: 00:16.0 [8086/0000] ops
867 12:51:26.676009 PCI: 00:16.0 [8086/a0e0] enabled
868 12:51:26.676311 PCI: Static device PCI: 00:17.0 not found, disabling it.
869 12:51:26.676619 PCI: 00:19.0 [8086/0000] bus ops
870 12:51:26.677230 PCI: 00:19.0 [8086/a0c5] disabled
871 12:51:26.677557 PCI: 00:19.1 [8086/0000] bus ops
872 12:51:26.680920 PCI: 00:19.1 [8086/a0c6] enabled
873 12:51:26.681359 PCI: 00:1d.0 [8086/0000] bus ops
874 12:51:26.684067 PCI: 00:1d.0 [8086/a0b0] enabled
875 12:51:26.687157 PCI: 00:1e.0 [8086/0000] ops
876 12:51:26.690881 PCI: 00:1e.0 [8086/a0a8] enabled
877 12:51:26.693760 PCI: 00:1e.2 [8086/0000] bus ops
878 12:51:26.696953 PCI: 00:1e.2 [8086/a0aa] enabled
879 12:51:26.700890 PCI: 00:1e.3 [8086/0000] bus ops
880 12:51:26.703934 PCI: 00:1e.3 [8086/a0ab] enabled
881 12:51:26.707124 PCI: 00:1f.0 [8086/0000] bus ops
882 12:51:26.710625 PCI: 00:1f.0 [8086/a087] enabled
883 12:51:26.713674 RTC Init
884 12:51:26.716703 Set power on after power failure.
885 12:51:26.717133 Disabling Deep S3
886 12:51:26.720247 Disabling Deep S3
887 12:51:26.723248 Disabling Deep S4
888 12:51:26.723715 Disabling Deep S4
889 12:51:26.726830 Disabling Deep S5
890 12:51:26.727424 Disabling Deep S5
891 12:51:26.729990 PCI: 00:1f.2 [0000/0000] hidden
892 12:51:26.733108 PCI: 00:1f.3 [8086/0000] bus ops
893 12:51:26.736992 PCI: 00:1f.3 [8086/a0c8] enabled
894 12:51:26.739936 PCI: 00:1f.5 [8086/0000] bus ops
895 12:51:26.743590 PCI: 00:1f.5 [8086/a0a4] enabled
896 12:51:26.746664 PCI: Leftover static devices:
897 12:51:26.750279 PCI: 00:10.2
898 12:51:26.750845 PCI: 00:10.6
899 12:51:26.751295 PCI: 00:10.7
900 12:51:26.753197 PCI: 00:06.0
901 12:51:26.753724 PCI: 00:07.1
902 12:51:26.756346 PCI: 00:07.2
903 12:51:26.756812 PCI: 00:07.3
904 12:51:26.757194 PCI: 00:09.0
905 12:51:26.759649 PCI: 00:0d.1
906 12:51:26.760105 PCI: 00:0d.2
907 12:51:26.763162 PCI: 00:0d.3
908 12:51:26.763713 PCI: 00:0e.0
909 12:51:26.766104 PCI: 00:12.0
910 12:51:26.766560 PCI: 00:12.6
911 12:51:26.766911 PCI: 00:13.0
912 12:51:26.769406 PCI: 00:14.1
913 12:51:26.769832 PCI: 00:16.1
914 12:51:26.773210 PCI: 00:16.2
915 12:51:26.773640 PCI: 00:16.3
916 12:51:26.773976 PCI: 00:16.4
917 12:51:26.776365 PCI: 00:16.5
918 12:51:26.776792 PCI: 00:17.0
919 12:51:26.779368 PCI: 00:19.2
920 12:51:26.779795 PCI: 00:1e.1
921 12:51:26.783095 PCI: 00:1f.1
922 12:51:26.783525 PCI: 00:1f.4
923 12:51:26.783866 PCI: 00:1f.6
924 12:51:26.786238 PCI: 00:1f.7
925 12:51:26.789224 PCI: Check your devicetree.cb.
926 12:51:26.793062 PCI: 00:02.0 scanning...
927 12:51:26.796166 scan_generic_bus for PCI: 00:02.0
928 12:51:26.799167 scan_generic_bus for PCI: 00:02.0 done
929 12:51:26.802986 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
930 12:51:26.806159 PCI: 00:04.0 scanning...
931 12:51:26.809060 scan_generic_bus for PCI: 00:04.0
932 12:51:26.812695 GENERIC: 0.0 enabled
933 12:51:26.819510 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
934 12:51:26.822583 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
935 12:51:26.825708 PCI: 00:0d.0 scanning...
936 12:51:26.829358 scan_static_bus for PCI: 00:0d.0
937 12:51:26.829847 USB0 port 0 enabled
938 12:51:26.832592 USB0 port 0 scanning...
939 12:51:26.835564 scan_static_bus for USB0 port 0
940 12:51:26.839399 USB3 port 0 enabled
941 12:51:26.842461 USB3 port 1 enabled
942 12:51:26.843068 USB3 port 2 disabled
943 12:51:26.845980 USB3 port 3 disabled
944 12:51:26.849093 USB3 port 0 scanning...
945 12:51:26.852669 scan_static_bus for USB3 port 0
946 12:51:26.855732 scan_static_bus for USB3 port 0 done
947 12:51:26.859251 scan_bus: bus USB3 port 0 finished in 6 msecs
948 12:51:26.862394 USB3 port 1 scanning...
949 12:51:26.865526 scan_static_bus for USB3 port 1
950 12:51:26.869079 scan_static_bus for USB3 port 1 done
951 12:51:26.872100 scan_bus: bus USB3 port 1 finished in 6 msecs
952 12:51:26.878512 scan_static_bus for USB0 port 0 done
953 12:51:26.882558 scan_bus: bus USB0 port 0 finished in 43 msecs
954 12:51:26.885478 scan_static_bus for PCI: 00:0d.0 done
955 12:51:26.891706 scan_bus: bus PCI: 00:0d.0 finished in 60 msecs
956 12:51:26.892197 PCI: 00:14.0 scanning...
957 12:51:26.895477 scan_static_bus for PCI: 00:14.0
958 12:51:26.898655 USB0 port 0 enabled
959 12:51:26.901603 USB0 port 0 scanning...
960 12:51:26.905247 scan_static_bus for USB0 port 0
961 12:51:26.905710 USB2 port 0 disabled
962 12:51:26.908404 USB2 port 1 enabled
963 12:51:26.911619 USB2 port 2 enabled
964 12:51:26.911999 USB2 port 3 disabled
965 12:51:26.915168 USB2 port 4 enabled
966 12:51:26.918240 USB2 port 5 disabled
967 12:51:26.918679 USB2 port 6 disabled
968 12:51:26.921877 USB2 port 7 disabled
969 12:51:26.924938 USB2 port 8 disabled
970 12:51:26.925337 USB2 port 9 disabled
971 12:51:26.927975 USB3 port 0 disabled
972 12:51:26.931792 USB3 port 1 enabled
973 12:51:26.932176 USB3 port 2 disabled
974 12:51:26.934744 USB3 port 3 disabled
975 12:51:26.938248 USB2 port 1 scanning...
976 12:51:26.941237 scan_static_bus for USB2 port 1
977 12:51:26.944316 scan_static_bus for USB2 port 1 done
978 12:51:26.947459 scan_bus: bus USB2 port 1 finished in 6 msecs
979 12:51:26.950875 USB2 port 2 scanning...
980 12:51:26.953984 scan_static_bus for USB2 port 2
981 12:51:26.957792 scan_static_bus for USB2 port 2 done
982 12:51:26.960883 scan_bus: bus USB2 port 2 finished in 6 msecs
983 12:51:26.964000 USB2 port 4 scanning...
984 12:51:26.967790 scan_static_bus for USB2 port 4
985 12:51:26.970920 scan_static_bus for USB2 port 4 done
986 12:51:26.977555 scan_bus: bus USB2 port 4 finished in 6 msecs
987 12:51:26.977640 USB3 port 1 scanning...
988 12:51:26.980651 scan_static_bus for USB3 port 1
989 12:51:26.987592 scan_static_bus for USB3 port 1 done
990 12:51:26.990598 scan_bus: bus USB3 port 1 finished in 6 msecs
991 12:51:26.994401 scan_static_bus for USB0 port 0 done
992 12:51:27.000668 scan_bus: bus USB0 port 0 finished in 93 msecs
993 12:51:27.004433 scan_static_bus for PCI: 00:14.0 done
994 12:51:27.007473 scan_bus: bus PCI: 00:14.0 finished in 110 msecs
995 12:51:27.010477 PCI: 00:14.3 scanning...
996 12:51:27.014409 scan_static_bus for PCI: 00:14.3
997 12:51:27.017462 GENERIC: 0.0 enabled
998 12:51:27.020563 scan_static_bus for PCI: 00:14.3 done
999 12:51:27.024255 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
1000 12:51:27.027318 PCI: 00:15.0 scanning...
1001 12:51:27.030341 scan_static_bus for PCI: 00:15.0
1002 12:51:27.033940 I2C: 00:1a enabled
1003 12:51:27.034025 I2C: 00:31 enabled
1004 12:51:27.037050 I2C: 00:32 enabled
1005 12:51:27.040632 scan_static_bus for PCI: 00:15.0 done
1006 12:51:27.043814 scan_bus: bus PCI: 00:15.0 finished in 12 msecs
1007 12:51:27.047858 PCI: 00:15.1 scanning...
1008 12:51:27.050203 scan_static_bus for PCI: 00:15.1
1009 12:51:27.053682 I2C: 00:10 enabled
1010 12:51:27.056856 scan_static_bus for PCI: 00:15.1 done
1011 12:51:27.060085 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
1012 12:51:27.063728 PCI: 00:15.2 scanning...
1013 12:51:27.066795 scan_static_bus for PCI: 00:15.2
1014 12:51:27.069967 scan_static_bus for PCI: 00:15.2 done
1015 12:51:27.077351 scan_bus: bus PCI: 00:15.2 finished in 7 msecs
1016 12:51:27.080224 PCI: 00:15.3 scanning...
1017 12:51:27.083467 scan_static_bus for PCI: 00:15.3
1018 12:51:27.087032 scan_static_bus for PCI: 00:15.3 done
1019 12:51:27.090082 scan_bus: bus PCI: 00:15.3 finished in 7 msecs
1020 12:51:27.093360 PCI: 00:19.1 scanning...
1021 12:51:27.097078 scan_static_bus for PCI: 00:19.1
1022 12:51:27.100230 I2C: 00:15 enabled
1023 12:51:27.103264 scan_static_bus for PCI: 00:19.1 done
1024 12:51:27.107110 scan_bus: bus PCI: 00:19.1 finished in 9 msecs
1025 12:51:27.110145 PCI: 00:1d.0 scanning...
1026 12:51:27.113317 do_pci_scan_bridge for PCI: 00:1d.0
1027 12:51:27.116964 PCI: pci_scan_bus for bus 01
1028 12:51:27.119985 PCI: 01:00.0 [1c5c/174a] enabled
1029 12:51:27.123772 GENERIC: 0.0 enabled
1030 12:51:27.126724 Enabling Common Clock Configuration
1031 12:51:27.129815 L1 Sub-State supported from root port 29
1032 12:51:27.133602 L1 Sub-State Support = 0xf
1033 12:51:27.136616 CommonModeRestoreTime = 0x28
1034 12:51:27.140308 Power On Value = 0x16, Power On Scale = 0x0
1035 12:51:27.143331 ASPM: Enabled L1
1036 12:51:27.146455 PCIe: Max_Payload_Size adjusted to 128
1037 12:51:27.150228 scan_bus: bus PCI: 00:1d.0 finished in 35 msecs
1038 12:51:27.153480 PCI: 00:1e.2 scanning...
1039 12:51:27.156675 scan_generic_bus for PCI: 00:1e.2
1040 12:51:27.160402 SPI: 00 enabled
1041 12:51:27.166479 bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done
1042 12:51:27.170249 scan_bus: bus PCI: 00:1e.2 finished in 11 msecs
1043 12:51:27.173608 PCI: 00:1e.3 scanning...
1044 12:51:27.176585 scan_generic_bus for PCI: 00:1e.3
1045 12:51:27.176982 SPI: 00 enabled
1046 12:51:27.183354 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1047 12:51:27.189950 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1048 12:51:27.190385 PCI: 00:1f.0 scanning...
1049 12:51:27.193051 scan_static_bus for PCI: 00:1f.0
1050 12:51:27.196821 PNP: 0c09.0 enabled
1051 12:51:27.200030 PNP: 0c09.0 scanning...
1052 12:51:27.203047 scan_static_bus for PNP: 0c09.0
1053 12:51:27.206173 scan_static_bus for PNP: 0c09.0 done
1054 12:51:27.209946 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1055 12:51:27.216624 scan_static_bus for PCI: 00:1f.0 done
1056 12:51:27.219561 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1057 12:51:27.222746 PCI: 00:1f.2 scanning...
1058 12:51:27.226383 scan_static_bus for PCI: 00:1f.2
1059 12:51:27.229466 GENERIC: 0.0 enabled
1060 12:51:27.229901 GENERIC: 0.0 scanning...
1061 12:51:27.233105 scan_static_bus for GENERIC: 0.0
1062 12:51:27.236243 GENERIC: 0.0 enabled
1063 12:51:27.239283 GENERIC: 1.0 enabled
1064 12:51:27.242971 scan_static_bus for GENERIC: 0.0 done
1065 12:51:27.245971 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1066 12:51:27.249475 scan_static_bus for PCI: 00:1f.2 done
1067 12:51:27.256505 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1068 12:51:27.259400 PCI: 00:1f.3 scanning...
1069 12:51:27.262444 scan_static_bus for PCI: 00:1f.3
1070 12:51:27.265924 scan_static_bus for PCI: 00:1f.3 done
1071 12:51:27.268959 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1072 12:51:27.272605 PCI: 00:1f.5 scanning...
1073 12:51:27.275701 scan_generic_bus for PCI: 00:1f.5
1074 12:51:27.278783 scan_generic_bus for PCI: 00:1f.5 done
1075 12:51:27.285602 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1076 12:51:27.289090 scan_bus: bus DOMAIN: 0000 finished in 717 msecs
1077 12:51:27.292252 scan_static_bus for Root Device done
1078 12:51:27.298882 scan_bus: bus Root Device finished in 737 msecs
1079 12:51:27.299419 done
1080 12:51:27.305766 BS: BS_DEV_ENUMERATE run times (exec / console): 11 / 1296 ms
1081 12:51:27.308919 Chrome EC: UHEPI supported
1082 12:51:27.315360 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (196608 bytes)
1083 12:51:27.322001 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1084 12:51:27.325605 SPI flash protection: WPSW=0 SRP0=0
1085 12:51:27.328557 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1086 12:51:27.335386 BS: BS_DEV_ENUMERATE exit times (exec / console): 1 / 23 ms
1087 12:51:27.338255 found VGA at PCI: 00:02.0
1088 12:51:27.342092 Setting up VGA for PCI: 00:02.0
1089 12:51:27.344989 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1090 12:51:27.351744 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1091 12:51:27.355324 Allocating resources...
1092 12:51:27.355766 Reading resources...
1093 12:51:27.361625 Root Device read_resources bus 0 link: 0
1094 12:51:27.364725 DOMAIN: 0000 read_resources bus 0 link: 0
1095 12:51:27.368477 PCI: 00:04.0 read_resources bus 1 link: 0
1096 12:51:27.375145 PCI: 00:04.0 read_resources bus 1 link: 0 done
1097 12:51:27.378297 PCI: 00:0d.0 read_resources bus 0 link: 0
1098 12:51:27.384938 USB0 port 0 read_resources bus 0 link: 0
1099 12:51:27.387936 USB0 port 0 read_resources bus 0 link: 0 done
1100 12:51:27.394933 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1101 12:51:27.397999 PCI: 00:14.0 read_resources bus 0 link: 0
1102 12:51:27.404763 USB0 port 0 read_resources bus 0 link: 0
1103 12:51:27.407630 USB0 port 0 read_resources bus 0 link: 0 done
1104 12:51:27.414641 PCI: 00:14.0 read_resources bus 0 link: 0 done
1105 12:51:27.417709 PCI: 00:14.3 read_resources bus 0 link: 0
1106 12:51:27.424555 PCI: 00:14.3 read_resources bus 0 link: 0 done
1107 12:51:27.427601 PCI: 00:15.0 read_resources bus 0 link: 0
1108 12:51:27.434143 PCI: 00:15.0 read_resources bus 0 link: 0 done
1109 12:51:27.437390 PCI: 00:15.1 read_resources bus 0 link: 0
1110 12:51:27.444078 PCI: 00:15.1 read_resources bus 0 link: 0 done
1111 12:51:27.450853 PCI: 00:19.1 read_resources bus 0 link: 0
1112 12:51:27.453954 PCI: 00:19.1 read_resources bus 0 link: 0 done
1113 12:51:27.457409 PCI: 00:1d.0 read_resources bus 1 link: 0
1114 12:51:27.464782 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1115 12:51:27.467864 PCI: 00:1e.2 read_resources bus 2 link: 0
1116 12:51:27.474672 PCI: 00:1e.2 read_resources bus 2 link: 0 done
1117 12:51:27.477779 PCI: 00:1e.3 read_resources bus 3 link: 0
1118 12:51:27.484660 PCI: 00:1e.3 read_resources bus 3 link: 0 done
1119 12:51:27.487479 PCI: 00:1f.0 read_resources bus 0 link: 0
1120 12:51:27.494134 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1121 12:51:27.498051 PCI: 00:1f.2 read_resources bus 0 link: 0
1122 12:51:27.501016 GENERIC: 0.0 read_resources bus 0 link: 0
1123 12:51:27.508366 GENERIC: 0.0 read_resources bus 0 link: 0 done
1124 12:51:27.511494 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1125 12:51:27.519014 DOMAIN: 0000 read_resources bus 0 link: 0 done
1126 12:51:27.522101 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1127 12:51:27.528428 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1128 12:51:27.532017 Root Device read_resources bus 0 link: 0 done
1129 12:51:27.534992 Done reading resources.
1130 12:51:27.541600 Show resources in subtree (Root Device)...After reading.
1131 12:51:27.545052 Root Device child on link 0 DOMAIN: 0000
1132 12:51:27.548683 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1133 12:51:27.558277 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1134 12:51:27.568082 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1135 12:51:27.571865 PCI: 00:00.0
1136 12:51:27.581788 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1137 12:51:27.588236 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1138 12:51:27.598446 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1139 12:51:27.608134 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1140 12:51:27.617950 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1141 12:51:27.628017 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1142 12:51:27.637839 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1143 12:51:27.644136 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1144 12:51:27.653973 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1145 12:51:27.663902 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1146 12:51:27.674259 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1147 12:51:27.684251 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1148 12:51:27.694170 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1149 12:51:27.700715 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1150 12:51:27.710383 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1151 12:51:27.720669 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1152 12:51:27.730011 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1153 12:51:27.740052 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1154 12:51:27.750389 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1155 12:51:27.760287 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1156 12:51:27.760374 PCI: 00:02.0
1157 12:51:27.770091 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1158 12:51:27.779983 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1159 12:51:27.790062 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1160 12:51:27.793129 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1161 12:51:27.802942 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1162 12:51:27.806648 GENERIC: 0.0
1163 12:51:27.806734 PCI: 00:05.0
1164 12:51:27.816610 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1165 12:51:27.822727 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1166 12:51:27.822813 GENERIC: 0.0
1167 12:51:27.826427 PCI: 00:08.0
1168 12:51:27.835930 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1169 12:51:27.836016 PCI: 00:0a.0
1170 12:51:27.842838 PCI: 00:0d.0 child on link 0 USB0 port 0
1171 12:51:27.852686 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1172 12:51:27.855698 USB0 port 0 child on link 0 USB3 port 0
1173 12:51:27.859263 USB3 port 0
1174 12:51:27.859348 USB3 port 1
1175 12:51:27.862373 USB3 port 2
1176 12:51:27.862458 USB3 port 3
1177 12:51:27.865557 PCI: 00:14.0 child on link 0 USB0 port 0
1178 12:51:27.878772 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1179 12:51:27.882450 USB0 port 0 child on link 0 USB2 port 0
1180 12:51:27.882575 USB2 port 0
1181 12:51:27.885641 USB2 port 1
1182 12:51:27.885726 USB2 port 2
1183 12:51:27.888777 USB2 port 3
1184 12:51:27.892338 USB2 port 4
1185 12:51:27.892423 USB2 port 5
1186 12:51:27.895489 USB2 port 6
1187 12:51:27.895574 USB2 port 7
1188 12:51:27.898469 USB2 port 8
1189 12:51:27.898594 USB2 port 9
1190 12:51:27.902238 USB3 port 0
1191 12:51:27.902323 USB3 port 1
1192 12:51:27.905460 USB3 port 2
1193 12:51:27.905546 USB3 port 3
1194 12:51:27.908562 PCI: 00:14.2
1195 12:51:27.918798 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1196 12:51:27.928545 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1197 12:51:27.931616 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1198 12:51:27.941818 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1199 12:51:27.945523 GENERIC: 0.0
1200 12:51:27.948544 PCI: 00:15.0 child on link 0 I2C: 00:1a
1201 12:51:27.958304 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1202 12:51:27.961934 I2C: 00:1a
1203 12:51:27.962019 I2C: 00:31
1204 12:51:27.965048 I2C: 00:32
1205 12:51:27.968109 PCI: 00:15.1 child on link 0 I2C: 00:10
1206 12:51:27.977922 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1207 12:51:27.978011 I2C: 00:10
1208 12:51:27.981340 PCI: 00:15.2
1209 12:51:27.991322 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1210 12:51:27.991407 PCI: 00:15.3
1211 12:51:28.001541 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1212 12:51:28.004758 PCI: 00:16.0
1213 12:51:28.014499 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1214 12:51:28.014620 PCI: 00:19.0
1215 12:51:28.021208 PCI: 00:19.1 child on link 0 I2C: 00:15
1216 12:51:28.031048 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1217 12:51:28.031130 I2C: 00:15
1218 12:51:28.034020 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1219 12:51:28.044065 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1220 12:51:28.054102 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1221 12:51:28.063875 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1222 12:51:28.063961 GENERIC: 0.0
1223 12:51:28.067538 PCI: 01:00.0
1224 12:51:28.077448 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1225 12:51:28.087156 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18
1226 12:51:28.097267 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c
1227 12:51:28.097353 PCI: 00:1e.0
1228 12:51:28.106916 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1229 12:51:28.113251 PCI: 00:1e.2 child on link 0 SPI: 00
1230 12:51:28.123582 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1231 12:51:28.123664 SPI: 00
1232 12:51:28.126529 PCI: 00:1e.3 child on link 0 SPI: 00
1233 12:51:28.136322 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1234 12:51:28.139947 SPI: 00
1235 12:51:28.143131 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1236 12:51:28.152979 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1237 12:51:28.153071 PNP: 0c09.0
1238 12:51:28.162968 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1239 12:51:28.166152 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1240 12:51:28.175975 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1241 12:51:28.186464 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1242 12:51:28.189549 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1243 12:51:28.192537 GENERIC: 0.0
1244 12:51:28.192612 GENERIC: 1.0
1245 12:51:28.196234 PCI: 00:1f.3
1246 12:51:28.206199 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1247 12:51:28.216025 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1248 12:51:28.216107 PCI: 00:1f.5
1249 12:51:28.225912 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1250 12:51:28.229364 CPU_CLUSTER: 0 child on link 0 APIC: 00
1251 12:51:28.232465 APIC: 00
1252 12:51:28.232540 APIC: 01
1253 12:51:28.235591 APIC: 03
1254 12:51:28.235663 APIC: 06
1255 12:51:28.235727 APIC: 05
1256 12:51:28.239340 APIC: 04
1257 12:51:28.239410 APIC: 02
1258 12:51:28.242206 APIC: 07
1259 12:51:28.249092 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1260 12:51:28.255441 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
1261 12:51:28.259107 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1262 12:51:28.265166 PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1263 12:51:28.272135 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1264 12:51:28.275353 PCI: 01:00.0 18 * [0x4000 - 0x4fff] mem
1265 12:51:28.279004 PCI: 01:00.0 1c * [0x5000 - 0x5fff] mem
1266 12:51:28.285181 PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1267 12:51:28.295332 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1268 12:51:28.302208 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1269 12:51:28.308546 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1270 12:51:28.315120 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1271 12:51:28.321952 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1272 12:51:28.331774 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1273 12:51:28.338617 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1274 12:51:28.341772 DOMAIN: 0000: Resource ranges:
1275 12:51:28.345376 * Base: 1000, Size: 800, Tag: 100
1276 12:51:28.348500 * Base: 1900, Size: e700, Tag: 100
1277 12:51:28.355174 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1278 12:51:28.361981 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1279 12:51:28.368199 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1280 12:51:28.374979 update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
1281 12:51:28.381634 update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed)
1282 12:51:28.391259 update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
1283 12:51:28.398028 update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
1284 12:51:28.404576 update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
1285 12:51:28.414893 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
1286 12:51:28.421190 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
1287 12:51:28.427808 update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
1288 12:51:28.437491 update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
1289 12:51:28.444304 update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
1290 12:51:28.450643 update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
1291 12:51:28.460964 update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
1292 12:51:28.467157 update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
1293 12:51:28.474037 update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
1294 12:51:28.483686 update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
1295 12:51:28.490467 update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed)
1296 12:51:28.497227 update_constraints: PCI: 00:00.0 10 base 100000000 limit 2803fffff mem (fixed)
1297 12:51:28.506849 update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
1298 12:51:28.513575 update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
1299 12:51:28.520527 update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed)
1300 12:51:28.530158 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1301 12:51:28.537102 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1302 12:51:28.540131 DOMAIN: 0000: Resource ranges:
1303 12:51:28.543143 * Base: 7fc00000, Size: 40400000, Tag: 200
1304 12:51:28.550006 * Base: d0000000, Size: 28000000, Tag: 200
1305 12:51:28.553220 * Base: fa000000, Size: 1000000, Tag: 200
1306 12:51:28.556354 * Base: fb001000, Size: 2fff000, Tag: 200
1307 12:51:28.559993 * Base: fe010000, Size: 2e000, Tag: 200
1308 12:51:28.566544 * Base: fe03f000, Size: d41000, Tag: 200
1309 12:51:28.569633 * Base: fed88000, Size: 8000, Tag: 200
1310 12:51:28.572852 * Base: fed93000, Size: d000, Tag: 200
1311 12:51:28.576613 * Base: feda2000, Size: 1e000, Tag: 200
1312 12:51:28.583182 * Base: fede0000, Size: 1220000, Tag: 200
1313 12:51:28.586229 * Base: 280400000, Size: 7d7fc00000, Tag: 100200
1314 12:51:28.593008 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
1315 12:51:28.599950 PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
1316 12:51:28.606141 PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
1317 12:51:28.612733 PCI: 00:1d.0 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
1318 12:51:28.619795 PCI: 00:1f.3 20 * [0x7fd00000 - 0x7fdfffff] limit: 7fdfffff mem
1319 12:51:28.625977 PCI: 00:04.0 10 * [0x7fe00000 - 0x7fe1ffff] limit: 7fe1ffff mem
1320 12:51:28.632781 PCI: 00:0d.0 10 * [0x7fe20000 - 0x7fe2ffff] limit: 7fe2ffff mem
1321 12:51:28.639335 PCI: 00:14.0 10 * [0x7fe30000 - 0x7fe3ffff] limit: 7fe3ffff mem
1322 12:51:28.646200 PCI: 00:14.2 10 * [0x7fe40000 - 0x7fe43fff] limit: 7fe43fff mem
1323 12:51:28.652605 PCI: 00:14.3 10 * [0x7fe44000 - 0x7fe47fff] limit: 7fe47fff mem
1324 12:51:28.658952 PCI: 00:1f.3 10 * [0x7fe48000 - 0x7fe4bfff] limit: 7fe4bfff mem
1325 12:51:28.665649 PCI: 00:08.0 10 * [0x7fe4c000 - 0x7fe4cfff] limit: 7fe4cfff mem
1326 12:51:28.672360 PCI: 00:14.2 18 * [0x7fe4d000 - 0x7fe4dfff] limit: 7fe4dfff mem
1327 12:51:28.679365 PCI: 00:15.0 10 * [0x7fe4e000 - 0x7fe4efff] limit: 7fe4efff mem
1328 12:51:28.685463 PCI: 00:15.1 10 * [0x7fe4f000 - 0x7fe4ffff] limit: 7fe4ffff mem
1329 12:51:28.692047 PCI: 00:15.2 10 * [0x7fe50000 - 0x7fe50fff] limit: 7fe50fff mem
1330 12:51:28.698619 PCI: 00:15.3 10 * [0x7fe51000 - 0x7fe51fff] limit: 7fe51fff mem
1331 12:51:28.705462 PCI: 00:16.0 10 * [0x7fe52000 - 0x7fe52fff] limit: 7fe52fff mem
1332 12:51:28.712253 PCI: 00:19.1 10 * [0x7fe53000 - 0x7fe53fff] limit: 7fe53fff mem
1333 12:51:28.718807 PCI: 00:1e.2 10 * [0x7fe54000 - 0x7fe54fff] limit: 7fe54fff mem
1334 12:51:28.725024 PCI: 00:1e.3 10 * [0x7fe55000 - 0x7fe55fff] limit: 7fe55fff mem
1335 12:51:28.731801 PCI: 00:1f.5 10 * [0x7fe56000 - 0x7fe56fff] limit: 7fe56fff mem
1336 12:51:28.741557 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1337 12:51:28.748467 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff
1338 12:51:28.751508 PCI: 00:1d.0: Resource ranges:
1339 12:51:28.755187 * Base: 7fc00000, Size: 100000, Tag: 200
1340 12:51:28.761496 PCI: 01:00.0 10 * [0x7fc00000 - 0x7fc03fff] limit: 7fc03fff mem
1341 12:51:28.768301 PCI: 01:00.0 18 * [0x7fc04000 - 0x7fc04fff] limit: 7fc04fff mem
1342 12:51:28.775081 PCI: 01:00.0 1c * [0x7fc05000 - 0x7fc05fff] limit: 7fc05fff mem
1343 12:51:28.784570 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff done
1344 12:51:28.791370 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1345 12:51:28.794372 Root Device assign_resources, bus 0 link: 0
1346 12:51:28.801242 DOMAIN: 0000 assign_resources, bus 0 link: 0
1347 12:51:28.808010 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
1348 12:51:28.817813 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
1349 12:51:28.824290 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1350 12:51:28.834450 PCI: 00:04.0 10 <- [0x007fe00000 - 0x007fe1ffff] size 0x00020000 gran 0x11 mem64
1351 12:51:28.837562 PCI: 00:04.0 assign_resources, bus 1 link: 0
1352 12:51:28.844303 PCI: 00:04.0 assign_resources, bus 1 link: 0
1353 12:51:28.850911 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64
1354 12:51:28.860722 PCI: 00:08.0 10 <- [0x007fe4c000 - 0x007fe4cfff] size 0x00001000 gran 0x0c mem64
1355 12:51:28.867501 PCI: 00:0d.0 10 <- [0x007fe20000 - 0x007fe2ffff] size 0x00010000 gran 0x10 mem64
1356 12:51:28.870371 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1357 12:51:28.877104 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1358 12:51:28.884063 PCI: 00:14.0 10 <- [0x007fe30000 - 0x007fe3ffff] size 0x00010000 gran 0x10 mem64
1359 12:51:28.890740 PCI: 00:14.0 assign_resources, bus 0 link: 0
1360 12:51:28.893827 PCI: 00:14.0 assign_resources, bus 0 link: 0
1361 12:51:28.903658 PCI: 00:14.2 10 <- [0x007fe40000 - 0x007fe43fff] size 0x00004000 gran 0x0e mem64
1362 12:51:28.910257 PCI: 00:14.2 18 <- [0x007fe4d000 - 0x007fe4dfff] size 0x00001000 gran 0x0c mem64
1363 12:51:28.920005 PCI: 00:14.3 10 <- [0x007fe44000 - 0x007fe47fff] size 0x00004000 gran 0x0e mem64
1364 12:51:28.923178 PCI: 00:14.3 assign_resources, bus 0 link: 0
1365 12:51:28.926641 PCI: 00:14.3 assign_resources, bus 0 link: 0
1366 12:51:28.936682 PCI: 00:15.0 10 <- [0x007fe4e000 - 0x007fe4efff] size 0x00001000 gran 0x0c mem64
1367 12:51:28.939804 PCI: 00:15.0 assign_resources, bus 0 link: 0
1368 12:51:28.946755 PCI: 00:15.0 assign_resources, bus 0 link: 0
1369 12:51:28.952942 PCI: 00:15.1 10 <- [0x007fe4f000 - 0x007fe4ffff] size 0x00001000 gran 0x0c mem64
1370 12:51:28.956714 PCI: 00:15.1 assign_resources, bus 0 link: 0
1371 12:51:28.963339 PCI: 00:15.1 assign_resources, bus 0 link: 0
1372 12:51:28.969952 PCI: 00:15.2 10 <- [0x007fe50000 - 0x007fe50fff] size 0x00001000 gran 0x0c mem64
1373 12:51:28.979938 PCI: 00:15.3 10 <- [0x007fe51000 - 0x007fe51fff] size 0x00001000 gran 0x0c mem64
1374 12:51:28.986880 PCI: 00:16.0 10 <- [0x007fe52000 - 0x007fe52fff] size 0x00001000 gran 0x0c mem64
1375 12:51:28.996216 PCI: 00:19.1 10 <- [0x007fe53000 - 0x007fe53fff] size 0x00001000 gran 0x0c mem64
1376 12:51:28.999927 PCI: 00:19.1 assign_resources, bus 0 link: 0
1377 12:51:29.006415 PCI: 00:19.1 assign_resources, bus 0 link: 0
1378 12:51:29.012624 PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1379 12:51:29.022949 PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1380 12:51:29.032805 PCI: 00:1d.0 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 bus 01 mem
1381 12:51:29.035767 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1382 12:51:29.045463 PCI: 01:00.0 10 <- [0x007fc00000 - 0x007fc03fff] size 0x00004000 gran 0x0e mem64
1383 12:51:29.052405 PCI: 01:00.0 18 <- [0x007fc04000 - 0x007fc04fff] size 0x00001000 gran 0x0c mem
1384 12:51:29.062241 PCI: 01:00.0 1c <- [0x007fc05000 - 0x007fc05fff] size 0x00001000 gran 0x0c mem
1385 12:51:29.065301 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1386 12:51:29.075436 PCI: 00:1e.2 10 <- [0x007fe54000 - 0x007fe54fff] size 0x00001000 gran 0x0c mem64
1387 12:51:29.078691 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1388 12:51:29.082033 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1389 12:51:29.092054 PCI: 00:1e.3 10 <- [0x007fe55000 - 0x007fe55fff] size 0x00001000 gran 0x0c mem64
1390 12:51:29.095278 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1391 12:51:29.101520 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1392 12:51:29.105093 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1393 12:51:29.111574 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1394 12:51:29.114597 LPC: Trying to open IO window from 800 size 1ff
1395 12:51:29.124581 PCI: 00:1f.3 10 <- [0x007fe48000 - 0x007fe4bfff] size 0x00004000 gran 0x0e mem64
1396 12:51:29.131176 PCI: 00:1f.3 20 <- [0x007fd00000 - 0x007fdfffff] size 0x00100000 gran 0x14 mem64
1397 12:51:29.138048 PCI: 00:1f.5 10 <- [0x007fe56000 - 0x007fe56fff] size 0x00001000 gran 0x0c mem
1398 12:51:29.144533 DOMAIN: 0000 assign_resources, bus 0 link: 0
1399 12:51:29.148113 Root Device assign_resources, bus 0 link: 0
1400 12:51:29.151133 Done setting resources.
1401 12:51:29.157976 Show resources in subtree (Root Device)...After assigning values.
1402 12:51:29.161195 Root Device child on link 0 DOMAIN: 0000
1403 12:51:29.168055 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1404 12:51:29.174118 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1405 12:51:29.183989 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1406 12:51:29.187164 PCI: 00:00.0
1407 12:51:29.197668 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1408 12:51:29.207056 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1409 12:51:29.216686 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1410 12:51:29.223532 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1411 12:51:29.233391 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1412 12:51:29.243066 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1413 12:51:29.252910 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1414 12:51:29.262944 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1415 12:51:29.273320 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1416 12:51:29.279510 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1417 12:51:29.289376 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1418 12:51:29.299623 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1419 12:51:29.309317 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1420 12:51:29.318966 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1421 12:51:29.328929 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1422 12:51:29.335782 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1423 12:51:29.345964 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1424 12:51:29.355390 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1425 12:51:29.365144 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1426 12:51:29.375132 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1427 12:51:29.379041 PCI: 00:02.0
1428 12:51:29.388833 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10
1429 12:51:29.398278 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18
1430 12:51:29.408121 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1431 12:51:29.411920 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1432 12:51:29.421762 PCI: 00:04.0 resource base 7fe00000 size 20000 align 17 gran 17 limit 7fe1ffff flags 60000201 index 10
1433 12:51:29.424907 GENERIC: 0.0
1434 12:51:29.425461 PCI: 00:05.0
1435 12:51:29.438588 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10
1436 12:51:29.441605 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1437 12:51:29.442179 GENERIC: 0.0
1438 12:51:29.444641 PCI: 00:08.0
1439 12:51:29.454901 PCI: 00:08.0 resource base 7fe4c000 size 1000 align 12 gran 12 limit 7fe4cfff flags 60000201 index 10
1440 12:51:29.457847 PCI: 00:0a.0
1441 12:51:29.461481 PCI: 00:0d.0 child on link 0 USB0 port 0
1442 12:51:29.471428 PCI: 00:0d.0 resource base 7fe20000 size 10000 align 16 gran 16 limit 7fe2ffff flags 60000201 index 10
1443 12:51:29.474376 USB0 port 0 child on link 0 USB3 port 0
1444 12:51:29.478034 USB3 port 0
1445 12:51:29.481174 USB3 port 1
1446 12:51:29.481657 USB3 port 2
1447 12:51:29.484424 USB3 port 3
1448 12:51:29.487725 PCI: 00:14.0 child on link 0 USB0 port 0
1449 12:51:29.498026 PCI: 00:14.0 resource base 7fe30000 size 10000 align 16 gran 16 limit 7fe3ffff flags 60000201 index 10
1450 12:51:29.501237 USB0 port 0 child on link 0 USB2 port 0
1451 12:51:29.504136 USB2 port 0
1452 12:51:29.504620 USB2 port 1
1453 12:51:29.507832 USB2 port 2
1454 12:51:29.511273 USB2 port 3
1455 12:51:29.511870 USB2 port 4
1456 12:51:29.514173 USB2 port 5
1457 12:51:29.514858 USB2 port 6
1458 12:51:29.517451 USB2 port 7
1459 12:51:29.518034 USB2 port 8
1460 12:51:29.521063 USB2 port 9
1461 12:51:29.521569 USB3 port 0
1462 12:51:29.524144 USB3 port 1
1463 12:51:29.524627 USB3 port 2
1464 12:51:29.527113 USB3 port 3
1465 12:51:29.527598 PCI: 00:14.2
1466 12:51:29.540462 PCI: 00:14.2 resource base 7fe40000 size 4000 align 14 gran 14 limit 7fe43fff flags 60000201 index 10
1467 12:51:29.550402 PCI: 00:14.2 resource base 7fe4d000 size 1000 align 12 gran 12 limit 7fe4dfff flags 60000201 index 18
1468 12:51:29.554040 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1469 12:51:29.563662 PCI: 00:14.3 resource base 7fe44000 size 4000 align 14 gran 14 limit 7fe47fff flags 60000201 index 10
1470 12:51:29.567146 GENERIC: 0.0
1471 12:51:29.570313 PCI: 00:15.0 child on link 0 I2C: 00:1a
1472 12:51:29.580390 PCI: 00:15.0 resource base 7fe4e000 size 1000 align 12 gran 12 limit 7fe4efff flags 60000201 index 10
1473 12:51:29.583506 I2C: 00:1a
1474 12:51:29.584080 I2C: 00:31
1475 12:51:29.586633 I2C: 00:32
1476 12:51:29.590220 PCI: 00:15.1 child on link 0 I2C: 00:10
1477 12:51:29.600095 PCI: 00:15.1 resource base 7fe4f000 size 1000 align 12 gran 12 limit 7fe4ffff flags 60000201 index 10
1478 12:51:29.600621 I2C: 00:10
1479 12:51:29.603798 PCI: 00:15.2
1480 12:51:29.613630 PCI: 00:15.2 resource base 7fe50000 size 1000 align 12 gran 12 limit 7fe50fff flags 60000201 index 10
1481 12:51:29.616796 PCI: 00:15.3
1482 12:51:29.626724 PCI: 00:15.3 resource base 7fe51000 size 1000 align 12 gran 12 limit 7fe51fff flags 60000201 index 10
1483 12:51:29.627170 PCI: 00:16.0
1484 12:51:29.636685 PCI: 00:16.0 resource base 7fe52000 size 1000 align 12 gran 12 limit 7fe52fff flags 60000201 index 10
1485 12:51:29.639836 PCI: 00:19.0
1486 12:51:29.642827 PCI: 00:19.1 child on link 0 I2C: 00:15
1487 12:51:29.653190 PCI: 00:19.1 resource base 7fe53000 size 1000 align 12 gran 12 limit 7fe53fff flags 60000201 index 10
1488 12:51:29.656200 I2C: 00:15
1489 12:51:29.659243 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1490 12:51:29.669421 PCI: 00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1491 12:51:29.679122 PCI: 00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1492 12:51:29.692731 PCI: 00:1d.0 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60080202 index 20
1493 12:51:29.693180 GENERIC: 0.0
1494 12:51:29.695820 PCI: 01:00.0
1495 12:51:29.705789 PCI: 01:00.0 resource base 7fc00000 size 4000 align 14 gran 14 limit 7fc03fff flags 60000201 index 10
1496 12:51:29.716068 PCI: 01:00.0 resource base 7fc04000 size 1000 align 12 gran 12 limit 7fc04fff flags 60000200 index 18
1497 12:51:29.725445 PCI: 01:00.0 resource base 7fc05000 size 1000 align 12 gran 12 limit 7fc05fff flags 60000200 index 1c
1498 12:51:29.729332 PCI: 00:1e.0
1499 12:51:29.739216 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1500 12:51:29.742324 PCI: 00:1e.2 child on link 0 SPI: 00
1501 12:51:29.752097 PCI: 00:1e.2 resource base 7fe54000 size 1000 align 12 gran 12 limit 7fe54fff flags 60000201 index 10
1502 12:51:29.755585 SPI: 00
1503 12:51:29.758875 PCI: 00:1e.3 child on link 0 SPI: 00
1504 12:51:29.768419 PCI: 00:1e.3 resource base 7fe55000 size 1000 align 12 gran 12 limit 7fe55fff flags 60000201 index 10
1505 12:51:29.768875 SPI: 00
1506 12:51:29.775566 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1507 12:51:29.781876 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1508 12:51:29.785635 PNP: 0c09.0
1509 12:51:29.791878 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1510 12:51:29.798607 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1511 12:51:29.808396 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1512 12:51:29.814924 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1513 12:51:29.821807 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1514 12:51:29.822289 GENERIC: 0.0
1515 12:51:29.824967 GENERIC: 1.0
1516 12:51:29.827949 PCI: 00:1f.3
1517 12:51:29.838082 PCI: 00:1f.3 resource base 7fe48000 size 4000 align 14 gran 14 limit 7fe4bfff flags 60000201 index 10
1518 12:51:29.847976 PCI: 00:1f.3 resource base 7fd00000 size 100000 align 20 gran 20 limit 7fdfffff flags 60000201 index 20
1519 12:51:29.848429 PCI: 00:1f.5
1520 12:51:29.857838 PCI: 00:1f.5 resource base 7fe56000 size 1000 align 12 gran 12 limit 7fe56fff flags 60000200 index 10
1521 12:51:29.864843 CPU_CLUSTER: 0 child on link 0 APIC: 00
1522 12:51:29.865284 APIC: 00
1523 12:51:29.865632 APIC: 01
1524 12:51:29.867811 APIC: 03
1525 12:51:29.868279 APIC: 06
1526 12:51:29.871441 APIC: 05
1527 12:51:29.871876 APIC: 04
1528 12:51:29.872301 APIC: 02
1529 12:51:29.874577 APIC: 07
1530 12:51:29.878268 Done allocating resources.
1531 12:51:29.881290 BS: BS_DEV_RESOURCES run times (exec / console): 28 / 2514 ms
1532 12:51:29.888618 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
1533 12:51:29.891807 Configure GPIOs for I2S audio on UP4.
1534 12:51:29.898947 BS: BS_DEV_ENABLE entry times (exec / console): 2 / 9 ms
1535 12:51:29.902720 Enabling resources...
1536 12:51:29.906033 PCI: 00:00.0 subsystem <- 8086/9a12
1537 12:51:29.908942 PCI: 00:00.0 cmd <- 06
1538 12:51:29.911972 PCI: 00:02.0 subsystem <- 8086/9a40
1539 12:51:29.915839 PCI: 00:02.0 cmd <- 03
1540 12:51:29.918883 PCI: 00:04.0 subsystem <- 8086/9a03
1541 12:51:29.921950 PCI: 00:04.0 cmd <- 02
1542 12:51:29.925153 PCI: 00:05.0 subsystem <- 8086/9a19
1543 12:51:29.925625 PCI: 00:05.0 cmd <- 02
1544 12:51:29.932021 PCI: 00:08.0 subsystem <- 8086/9a11
1545 12:51:29.932458 PCI: 00:08.0 cmd <- 06
1546 12:51:29.935850 PCI: 00:0d.0 subsystem <- 8086/9a13
1547 12:51:29.939002 PCI: 00:0d.0 cmd <- 02
1548 12:51:29.942101 PCI: 00:14.0 subsystem <- 8086/a0ed
1549 12:51:29.945268 PCI: 00:14.0 cmd <- 02
1550 12:51:29.949056 PCI: 00:14.2 subsystem <- 8086/a0ef
1551 12:51:29.952098 PCI: 00:14.2 cmd <- 02
1552 12:51:29.955135 PCI: 00:14.3 subsystem <- 8086/a0f0
1553 12:51:29.958909 PCI: 00:14.3 cmd <- 02
1554 12:51:29.961805 PCI: 00:15.0 subsystem <- 8086/a0e8
1555 12:51:29.965526 PCI: 00:15.0 cmd <- 02
1556 12:51:29.968612 PCI: 00:15.1 subsystem <- 8086/a0e9
1557 12:51:29.971758 PCI: 00:15.1 cmd <- 02
1558 12:51:29.974790 PCI: 00:15.2 subsystem <- 8086/a0ea
1559 12:51:29.978443 PCI: 00:15.2 cmd <- 02
1560 12:51:29.981500 PCI: 00:15.3 subsystem <- 8086/a0eb
1561 12:51:29.981938 PCI: 00:15.3 cmd <- 02
1562 12:51:29.987723 PCI: 00:16.0 subsystem <- 8086/a0e0
1563 12:51:29.988159 PCI: 00:16.0 cmd <- 02
1564 12:51:29.991212 PCI: 00:19.1 subsystem <- 8086/a0c6
1565 12:51:29.994316 PCI: 00:19.1 cmd <- 02
1566 12:51:29.998175 PCI: 00:1d.0 bridge ctrl <- 0013
1567 12:51:30.001228 PCI: 00:1d.0 subsystem <- 8086/a0b0
1568 12:51:30.004815 PCI: 00:1d.0 cmd <- 06
1569 12:51:30.007982 PCI: 00:1e.0 subsystem <- 8086/a0a8
1570 12:51:30.011160 PCI: 00:1e.0 cmd <- 06
1571 12:51:30.014067 PCI: 00:1e.2 subsystem <- 8086/a0aa
1572 12:51:30.017760 PCI: 00:1e.2 cmd <- 06
1573 12:51:30.021005 PCI: 00:1e.3 subsystem <- 8086/a0ab
1574 12:51:30.024046 PCI: 00:1e.3 cmd <- 02
1575 12:51:30.027692 PCI: 00:1f.0 subsystem <- 8086/a087
1576 12:51:30.030939 PCI: 00:1f.0 cmd <- 407
1577 12:51:30.033951 PCI: 00:1f.3 subsystem <- 8086/a0c8
1578 12:51:30.037064 PCI: 00:1f.3 cmd <- 02
1579 12:51:30.040200 PCI: 00:1f.5 subsystem <- 8086/a0a4
1580 12:51:30.044029 PCI: 00:1f.5 cmd <- 406
1581 12:51:30.047268 PCI: 01:00.0 cmd <- 02
1582 12:51:30.051019 done.
1583 12:51:30.054572 BS: BS_DEV_ENABLE run times (exec / console): 10 / 140 ms
1584 12:51:30.057657 Initializing devices...
1585 12:51:30.060905 Root Device init
1586 12:51:30.063972 Chrome EC: Set SMI mask to 0x0000000000000000
1587 12:51:30.070580 Chrome EC: clear events_b mask to 0x0000000000000000
1588 12:51:30.077331 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1589 12:51:30.080469 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001800101e
1590 12:51:30.087808 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001800101e
1591 12:51:30.094000 Chrome EC: Set WAKE mask to 0x0000000000000000
1592 12:51:30.097427 fw_config match found: DB_USB=USB3_ACTIVE
1593 12:51:30.104317 Configure Right Type-C port orientation for retimer
1594 12:51:30.107344 Root Device init finished in 43 msecs
1595 12:51:30.111072 PCI: 00:00.0 init
1596 12:51:30.114216 CPU TDP = 9 Watts
1597 12:51:30.114730 CPU PL1 = 9 Watts
1598 12:51:30.117359 CPU PL2 = 40 Watts
1599 12:51:30.120346 CPU PL4 = 83 Watts
1600 12:51:30.124113 PCI: 00:00.0 init finished in 8 msecs
1601 12:51:30.124601 PCI: 00:02.0 init
1602 12:51:30.127409 GMA: Found VBT in CBFS
1603 12:51:30.130238 GMA: Found valid VBT in CBFS
1604 12:51:30.137120 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1605 12:51:30.144033 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
1606 12:51:30.147142 PCI: 00:02.0 init finished in 18 msecs
1607 12:51:30.150260 PCI: 00:05.0 init
1608 12:51:30.153544 PCI: 00:05.0 init finished in 0 msecs
1609 12:51:30.157215 PCI: 00:08.0 init
1610 12:51:30.160255 PCI: 00:08.0 init finished in 0 msecs
1611 12:51:30.163355 PCI: 00:14.0 init
1612 12:51:30.167207 PCI: 00:14.0 init finished in 0 msecs
1613 12:51:30.170225 PCI: 00:14.2 init
1614 12:51:30.173311 PCI: 00:14.2 init finished in 0 msecs
1615 12:51:30.173855 PCI: 00:15.0 init
1616 12:51:30.176912 I2C bus 0 version 0x3230302a
1617 12:51:30.180053 DW I2C bus 0 at 0x7fe4e000 (400 KHz)
1618 12:51:30.186858 PCI: 00:15.0 init finished in 6 msecs
1619 12:51:30.187306 PCI: 00:15.1 init
1620 12:51:30.189923 I2C bus 1 version 0x3230302a
1621 12:51:30.193632 DW I2C bus 1 at 0x7fe4f000 (400 KHz)
1622 12:51:30.196621 PCI: 00:15.1 init finished in 6 msecs
1623 12:51:30.200080 PCI: 00:15.2 init
1624 12:51:30.203186 I2C bus 2 version 0x3230302a
1625 12:51:30.206385 DW I2C bus 2 at 0x7fe50000 (400 KHz)
1626 12:51:30.209546 PCI: 00:15.2 init finished in 6 msecs
1627 12:51:30.213243 PCI: 00:15.3 init
1628 12:51:30.216424 I2C bus 3 version 0x3230302a
1629 12:51:30.219529 DW I2C bus 3 at 0x7fe51000 (400 KHz)
1630 12:51:30.222669 PCI: 00:15.3 init finished in 6 msecs
1631 12:51:30.226161 PCI: 00:16.0 init
1632 12:51:30.229286 PCI: 00:16.0 init finished in 0 msecs
1633 12:51:30.232424 PCI: 00:19.1 init
1634 12:51:30.236414 I2C bus 5 version 0x3230302a
1635 12:51:30.239358 DW I2C bus 5 at 0x7fe53000 (400 KHz)
1636 12:51:30.242424 PCI: 00:19.1 init finished in 6 msecs
1637 12:51:30.242500 PCI: 00:1d.0 init
1638 12:51:30.245639 Initializing PCH PCIe bridge.
1639 12:51:30.252529 PCI: 00:1d.0 init finished in 3 msecs
1640 12:51:30.255843 PCI: 00:1f.0 init
1641 12:51:30.258875 IOAPIC: Initializing IOAPIC at 0xfec00000
1642 12:51:30.262433 IOAPIC: Bootstrap Processor Local APIC = 0x00
1643 12:51:30.265437 IOAPIC: ID = 0x02
1644 12:51:30.269191 IOAPIC: Dumping registers
1645 12:51:30.269267 reg 0x0000: 0x02000000
1646 12:51:30.272333 reg 0x0001: 0x00770020
1647 12:51:30.275504 reg 0x0002: 0x00000000
1648 12:51:30.279119 PCI: 00:1f.0 init finished in 21 msecs
1649 12:51:30.282003 PCI: 00:1f.2 init
1650 12:51:30.285645 Disabling ACPI via APMC.
1651 12:51:30.285732 APMC done.
1652 12:51:30.288800 PCI: 00:1f.2 init finished in 5 msecs
1653 12:51:30.302351 PCI: 01:00.0 init
1654 12:51:30.305326 PCI: 01:00.0 init finished in 0 msecs
1655 12:51:30.309281 PNP: 0c09.0 init
1656 12:51:30.312249 Google Chrome EC uptime: 8.359 seconds
1657 12:51:30.319152 Google Chrome AP resets since EC boot: 1
1658 12:51:30.322347 Google Chrome most recent AP reset causes:
1659 12:51:30.325371 0.346: 32775 shutdown: entering G3
1660 12:51:30.332170 Google Chrome EC reset flags at last EC boot: reset-pin | sysjump
1661 12:51:30.335271 PNP: 0c09.0 init finished in 22 msecs
1662 12:51:30.341367 Devices initialized
1663 12:51:30.344495 Show all devs... After init.
1664 12:51:30.347596 Root Device: enabled 1
1665 12:51:30.347689 DOMAIN: 0000: enabled 1
1666 12:51:30.351512 CPU_CLUSTER: 0: enabled 1
1667 12:51:30.354669 PCI: 00:00.0: enabled 1
1668 12:51:30.357751 PCI: 00:02.0: enabled 1
1669 12:51:30.357830 PCI: 00:04.0: enabled 1
1670 12:51:30.360889 PCI: 00:05.0: enabled 1
1671 12:51:30.364535 PCI: 00:06.0: enabled 0
1672 12:51:30.367605 PCI: 00:07.0: enabled 0
1673 12:51:30.367698 PCI: 00:07.1: enabled 0
1674 12:51:30.371208 PCI: 00:07.2: enabled 0
1675 12:51:30.374282 PCI: 00:07.3: enabled 0
1676 12:51:30.377450 PCI: 00:08.0: enabled 1
1677 12:51:30.377557 PCI: 00:09.0: enabled 0
1678 12:51:30.381138 PCI: 00:0a.0: enabled 0
1679 12:51:30.384230 PCI: 00:0d.0: enabled 1
1680 12:51:30.387813 PCI: 00:0d.1: enabled 0
1681 12:51:30.387904 PCI: 00:0d.2: enabled 0
1682 12:51:30.390996 PCI: 00:0d.3: enabled 0
1683 12:51:30.393932 PCI: 00:0e.0: enabled 0
1684 12:51:30.394014 PCI: 00:10.2: enabled 1
1685 12:51:30.397670 PCI: 00:10.6: enabled 0
1686 12:51:30.400854 PCI: 00:10.7: enabled 0
1687 12:51:30.404412 PCI: 00:12.0: enabled 0
1688 12:51:30.404507 PCI: 00:12.6: enabled 0
1689 12:51:30.407315 PCI: 00:13.0: enabled 0
1690 12:51:30.410969 PCI: 00:14.0: enabled 1
1691 12:51:30.414193 PCI: 00:14.1: enabled 0
1692 12:51:30.414271 PCI: 00:14.2: enabled 1
1693 12:51:30.417389 PCI: 00:14.3: enabled 1
1694 12:51:30.420966 PCI: 00:15.0: enabled 1
1695 12:51:30.424031 PCI: 00:15.1: enabled 1
1696 12:51:30.424117 PCI: 00:15.2: enabled 1
1697 12:51:30.427232 PCI: 00:15.3: enabled 1
1698 12:51:30.430904 PCI: 00:16.0: enabled 1
1699 12:51:30.434417 PCI: 00:16.1: enabled 0
1700 12:51:30.434502 PCI: 00:16.2: enabled 0
1701 12:51:30.437589 PCI: 00:16.3: enabled 0
1702 12:51:30.440755 PCI: 00:16.4: enabled 0
1703 12:51:30.440842 PCI: 00:16.5: enabled 0
1704 12:51:30.443851 PCI: 00:17.0: enabled 0
1705 12:51:30.447641 PCI: 00:19.0: enabled 0
1706 12:51:30.450700 PCI: 00:19.1: enabled 1
1707 12:51:30.450780 PCI: 00:19.2: enabled 0
1708 12:51:30.453889 PCI: 00:1c.0: enabled 1
1709 12:51:30.457659 PCI: 00:1c.1: enabled 0
1710 12:51:30.460818 PCI: 00:1c.2: enabled 0
1711 12:51:30.460898 PCI: 00:1c.3: enabled 0
1712 12:51:30.463937 PCI: 00:1c.4: enabled 0
1713 12:51:30.467037 PCI: 00:1c.5: enabled 0
1714 12:51:30.470607 PCI: 00:1c.6: enabled 1
1715 12:51:30.470687 PCI: 00:1c.7: enabled 0
1716 12:51:30.474235 PCI: 00:1d.0: enabled 1
1717 12:51:30.477191 PCI: 00:1d.1: enabled 0
1718 12:51:30.480254 PCI: 00:1d.2: enabled 1
1719 12:51:30.480353 PCI: 00:1d.3: enabled 0
1720 12:51:30.483860 PCI: 00:1e.0: enabled 1
1721 12:51:30.486975 PCI: 00:1e.1: enabled 0
1722 12:51:30.487055 PCI: 00:1e.2: enabled 1
1723 12:51:30.490603 PCI: 00:1e.3: enabled 1
1724 12:51:30.493602 PCI: 00:1f.0: enabled 1
1725 12:51:30.497293 PCI: 00:1f.1: enabled 0
1726 12:51:30.497380 PCI: 00:1f.2: enabled 1
1727 12:51:30.500270 PCI: 00:1f.3: enabled 1
1728 12:51:30.504023 PCI: 00:1f.4: enabled 0
1729 12:51:30.506995 PCI: 00:1f.5: enabled 1
1730 12:51:30.507080 PCI: 00:1f.6: enabled 0
1731 12:51:30.510124 PCI: 00:1f.7: enabled 0
1732 12:51:30.513749 APIC: 00: enabled 1
1733 12:51:30.513835 GENERIC: 0.0: enabled 1
1734 12:51:30.516774 GENERIC: 0.0: enabled 1
1735 12:51:30.520729 GENERIC: 1.0: enabled 1
1736 12:51:30.523792 GENERIC: 0.0: enabled 1
1737 12:51:30.523894 GENERIC: 1.0: enabled 1
1738 12:51:30.526843 USB0 port 0: enabled 1
1739 12:51:30.529986 GENERIC: 0.0: enabled 1
1740 12:51:30.533712 USB0 port 0: enabled 1
1741 12:51:30.533797 GENERIC: 0.0: enabled 1
1742 12:51:30.536632 I2C: 00:1a: enabled 1
1743 12:51:30.540349 I2C: 00:31: enabled 1
1744 12:51:30.540435 I2C: 00:32: enabled 1
1745 12:51:30.543372 I2C: 00:10: enabled 1
1746 12:51:30.547237 I2C: 00:15: enabled 1
1747 12:51:30.547322 GENERIC: 0.0: enabled 0
1748 12:51:30.550088 GENERIC: 1.0: enabled 0
1749 12:51:30.553353 GENERIC: 0.0: enabled 1
1750 12:51:30.553437 SPI: 00: enabled 1
1751 12:51:30.556514 SPI: 00: enabled 1
1752 12:51:30.560282 PNP: 0c09.0: enabled 1
1753 12:51:30.560367 GENERIC: 0.0: enabled 1
1754 12:51:30.563490 USB3 port 0: enabled 1
1755 12:51:30.566637 USB3 port 1: enabled 1
1756 12:51:30.569725 USB3 port 2: enabled 0
1757 12:51:30.569810 USB3 port 3: enabled 0
1758 12:51:30.572960 USB2 port 0: enabled 0
1759 12:51:30.576544 USB2 port 1: enabled 1
1760 12:51:30.576630 USB2 port 2: enabled 1
1761 12:51:30.579723 USB2 port 3: enabled 0
1762 12:51:30.583453 USB2 port 4: enabled 1
1763 12:51:30.586351 USB2 port 5: enabled 0
1764 12:51:30.586455 USB2 port 6: enabled 0
1765 12:51:30.590066 USB2 port 7: enabled 0
1766 12:51:30.593155 USB2 port 8: enabled 0
1767 12:51:30.593240 USB2 port 9: enabled 0
1768 12:51:30.596176 USB3 port 0: enabled 0
1769 12:51:30.599791 USB3 port 1: enabled 1
1770 12:51:30.602927 USB3 port 2: enabled 0
1771 12:51:30.603012 USB3 port 3: enabled 0
1772 12:51:30.606416 GENERIC: 0.0: enabled 1
1773 12:51:30.609404 GENERIC: 1.0: enabled 1
1774 12:51:30.609489 APIC: 01: enabled 1
1775 12:51:30.612536 APIC: 03: enabled 1
1776 12:51:30.616296 APIC: 06: enabled 1
1777 12:51:30.616400 APIC: 05: enabled 1
1778 12:51:30.619300 APIC: 04: enabled 1
1779 12:51:30.619385 APIC: 02: enabled 1
1780 12:51:30.622879 APIC: 07: enabled 1
1781 12:51:30.626077 PCI: 01:00.0: enabled 1
1782 12:51:30.632996 BS: BS_DEV_INIT run times (exec / console): 30 / 540 ms
1783 12:51:30.636157 FMAP: area RW_ELOG found @ f30000 (4096 bytes)
1784 12:51:30.639311 ELOG: NV offset 0xf30000 size 0x1000
1785 12:51:30.646152 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1786 12:51:30.653201 ELOG: Event(17) added with size 13 at 2023-03-22 12:51:30 UTC
1787 12:51:30.659572 ELOG: Event(92) added with size 9 at 2023-03-22 12:51:30 UTC
1788 12:51:30.666393 ELOG: Event(93) added with size 9 at 2023-03-22 12:51:30 UTC
1789 12:51:30.672675 ELOG: Event(9E) added with size 10 at 2023-03-22 12:51:30 UTC
1790 12:51:30.679551 ELOG: Event(9F) added with size 14 at 2023-03-22 12:51:30 UTC
1791 12:51:30.685839 BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms
1792 12:51:30.692454 ELOG: Event(A1) added with size 10 at 2023-03-22 12:51:30 UTC
1793 12:51:30.698715 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1794 12:51:30.705504 ELOG: Event(A0) added with size 9 at 2023-03-22 12:51:30 UTC
1795 12:51:30.709109 elog_add_boot_reason: Logged dev mode boot
1796 12:51:30.715170 BS: BS_POST_DEVICE entry times (exec / console): 0 / 24 ms
1797 12:51:30.718882 Finalize devices...
1798 12:51:30.718968 Devices finalized
1799 12:51:30.725704 BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
1800 12:51:30.728872 FMAP: area RW_NVRAM found @ f37000 (24576 bytes)
1801 12:51:30.735031 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
1802 12:51:30.741977 ME: HFSTS1 : 0x80030055
1803 12:51:30.745144 ME: HFSTS2 : 0x30280116
1804 12:51:30.748675 ME: HFSTS3 : 0x00000050
1805 12:51:30.755001 ME: HFSTS4 : 0x00004000
1806 12:51:30.758633 ME: HFSTS5 : 0x00000000
1807 12:51:30.761647 ME: HFSTS6 : 0x00400006
1808 12:51:30.768047 ME: Manufacturing Mode : YES
1809 12:51:30.771762 ME: SPI Protection Mode Enabled : NO
1810 12:51:30.774907 ME: FW Partition Table : OK
1811 12:51:30.778065 ME: Bringup Loader Failure : NO
1812 12:51:30.781267 ME: Firmware Init Complete : NO
1813 12:51:30.784521 ME: Boot Options Present : NO
1814 12:51:30.788236 ME: Update In Progress : NO
1815 12:51:30.791182 ME: D0i3 Support : YES
1816 12:51:30.794623 ME: Low Power State Enabled : NO
1817 12:51:30.801417 ME: CPU Replaced : YES
1818 12:51:30.804535 ME: CPU Replacement Valid : YES
1819 12:51:30.807585 ME: Current Working State : 5
1820 12:51:30.810840 ME: Current Operation State : 1
1821 12:51:30.814393 ME: Current Operation Mode : 3
1822 12:51:30.817527 ME: Error Code : 0
1823 12:51:30.821253 ME: Enhanced Debug Mode : NO
1824 12:51:30.824261 ME: CPU Debug Disabled : YES
1825 12:51:30.830982 ME: TXT Support : NO
1826 12:51:30.834106 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 94 ms
1827 12:51:30.844009 CBFS: Found 'fallback/dsdt.aml' @0x72f80 size 0x5a67 in mcache @0x76c4c1c4
1828 12:51:30.847194 CBFS: 'fallback/slic' not found.
1829 12:51:30.850726 ACPI: Writing ACPI tables at 76b01000.
1830 12:51:30.850811 ACPI: * FACS
1831 12:51:30.853806 ACPI: * DSDT
1832 12:51:30.857507 Ramoops buffer: 0x100000@0x76a00000.
1833 12:51:30.863711 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
1834 12:51:30.867452 FMAP: area RW_VPD found @ f35000 (8192 bytes)
1835 12:51:30.870615 Google Chrome EC: version:
1836 12:51:30.873723 ro: voema_v2.0.7540-147f8d37d1
1837 12:51:30.876942 rw: voema_v2.0.7540-147f8d37d1
1838 12:51:30.880553 running image: 2
1839 12:51:30.883763 PCI space above 4GB MMIO is at 0x280400000, len = 0x7d7fc00000
1840 12:51:30.889383 ACPI: * FADT
1841 12:51:30.889503 SCI is IRQ9
1842 12:51:30.895661 ACPI: added table 1/32, length now 40
1843 12:51:30.895788 ACPI: * SSDT
1844 12:51:30.899337 Found 1 CPU(s) with 8 core(s) each.
1845 12:51:30.906092 \_SB.PCI0.PMC: Intel Tigerlake at PCI: 00:1f.2
1846 12:51:30.909345 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
1847 12:51:30.912357 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
1848 12:51:30.915964 \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
1849 12:51:30.922126 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
1850 12:51:30.929070 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
1851 12:51:30.932550 \_SB.PCI0.I2C1.H010: ELAN Touchscreen at I2C: 00:10
1852 12:51:30.939020 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
1853 12:51:30.945621 \_SB.PCI0.RP09: Enable RTD3 for PCI: 00:1d.0 (Intel PCIe Runtime D3)
1854 12:51:30.949376 \_SB.PCI0.RP09: Added StorageD3Enable property
1855 12:51:30.955457 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1856 12:51:30.959062 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
1857 12:51:30.965878 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
1858 12:51:30.968856 PS2K: Passing 80 keymaps to kernel
1859 12:51:30.975862 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
1860 12:51:30.982203 \_SB.PCI0.TXHC.RHUB.SS02: USB3 Type-C Port C1 (DB) at USB3 port 1
1861 12:51:30.989096 \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-A Port A1 (DB) at USB2 port 1
1862 12:51:30.995887 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
1863 12:51:31.002127 \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-C Port C0 (MLB) at USB2 port 4
1864 12:51:31.008775 \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Port A1 (DB) at USB3 port 1
1865 12:51:31.015488 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
1866 12:51:31.022268 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
1867 12:51:31.025438 ACPI: added table 2/32, length now 44
1868 12:51:31.028971 ACPI: * MCFG
1869 12:51:31.031966 ACPI: added table 3/32, length now 48
1870 12:51:31.032455 ACPI: * TPM2
1871 12:51:31.034857 TPM2 log created at 0x769f0000
1872 12:51:31.038344 ACPI: added table 4/32, length now 52
1873 12:51:31.041622 ACPI: * MADT
1874 12:51:31.042075 SCI is IRQ9
1875 12:51:31.045322 ACPI: added table 5/32, length now 56
1876 12:51:31.048543 current = 76b09850
1877 12:51:31.048987 ACPI: * DMAR
1878 12:51:31.054909 ACPI: added table 6/32, length now 60
1879 12:51:31.058619 ACPI: added table 7/32, length now 64
1880 12:51:31.059116 ACPI: * HPET
1881 12:51:31.061533 ACPI: added table 8/32, length now 68
1882 12:51:31.064700 ACPI: done.
1883 12:51:31.068521 ACPI tables: 35216 bytes.
1884 12:51:31.071493 smbios_write_tables: 769ef000
1885 12:51:31.074464 EC returned error result code 3
1886 12:51:31.078217 Couldn't obtain OEM name from CBI
1887 12:51:31.078789 Create SMBIOS type 16
1888 12:51:31.081333 Create SMBIOS type 17
1889 12:51:31.084526 GENERIC: 0.0 (WIFI Device)
1890 12:51:31.087693 SMBIOS tables: 1750 bytes.
1891 12:51:31.091290 Writing table forward entry at 0x00000500
1892 12:51:31.097331 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 392c
1893 12:51:31.100574 Writing coreboot table at 0x76b25000
1894 12:51:31.107374 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1895 12:51:31.110947 1. 0000000000001000-000000000009ffff: RAM
1896 12:51:31.117289 2. 00000000000a0000-00000000000fffff: RESERVED
1897 12:51:31.120567 3. 0000000000100000-00000000769eefff: RAM
1898 12:51:31.127349 4. 00000000769ef000-0000000076b97fff: CONFIGURATION TABLES
1899 12:51:31.130459 5. 0000000076b98000-0000000076c09fff: RAMSTAGE
1900 12:51:31.136980 6. 0000000076c0a000-0000000076ffffff: CONFIGURATION TABLES
1901 12:51:31.140608 7. 0000000077000000-000000007fbfffff: RESERVED
1902 12:51:31.146942 8. 00000000c0000000-00000000cfffffff: RESERVED
1903 12:51:31.150535 9. 00000000f8000000-00000000f9ffffff: RESERVED
1904 12:51:31.156813 10. 00000000fb000000-00000000fb000fff: RESERVED
1905 12:51:31.160483 11. 00000000fe000000-00000000fe00ffff: RESERVED
1906 12:51:31.166834 12. 00000000fed80000-00000000fed87fff: RESERVED
1907 12:51:31.169927 13. 00000000fed90000-00000000fed92fff: RESERVED
1908 12:51:31.176640 14. 00000000feda0000-00000000feda1fff: RESERVED
1909 12:51:31.180308 15. 00000000fedc0000-00000000feddffff: RESERVED
1910 12:51:31.183523 16. 0000000100000000-00000002803fffff: RAM
1911 12:51:31.186715 Passing 4 GPIOs to payload:
1912 12:51:31.193577 NAME | PORT | POLARITY | VALUE
1913 12:51:31.196781 lid | undefined | high | high
1914 12:51:31.202976 power | undefined | high | low
1915 12:51:31.209889 oprom | undefined | high | low
1916 12:51:31.213389 EC in RW | 0x000000e5 | high | high
1917 12:51:31.219747 Wrote coreboot table at: 0x76b25000, 0x610 bytes, checksum 5bd9
1918 12:51:31.223505 coreboot table: 1576 bytes.
1919 12:51:31.226569 IMD ROOT 0. 0x76fff000 0x00001000
1920 12:51:31.229923 IMD SMALL 1. 0x76ffe000 0x00001000
1921 12:51:31.232863 FSP MEMORY 2. 0x76c4e000 0x003b0000
1922 12:51:31.239658 VPD 3. 0x76c4d000 0x00000367
1923 12:51:31.243176 RO MCACHE 4. 0x76c4c000 0x00000fdc
1924 12:51:31.246117 CONSOLE 5. 0x76c2c000 0x00020000
1925 12:51:31.249947 FMAP 6. 0x76c2b000 0x00000578
1926 12:51:31.253191 TIME STAMP 7. 0x76c2a000 0x00000910
1927 12:51:31.256147 VBOOT WORK 8. 0x76c16000 0x00014000
1928 12:51:31.259833 ROMSTG STCK 9. 0x76c15000 0x00001000
1929 12:51:31.262939 AFTER CAR 10. 0x76c0a000 0x0000b000
1930 12:51:31.269711 RAMSTAGE 11. 0x76b97000 0x00073000
1931 12:51:31.273006 REFCODE 12. 0x76b42000 0x00055000
1932 12:51:31.276085 SMM BACKUP 13. 0x76b32000 0x00010000
1933 12:51:31.279246 4f444749 14. 0x76b30000 0x00002000
1934 12:51:31.282909 EXT VBT15. 0x76b2d000 0x0000219f
1935 12:51:31.285991 COREBOOT 16. 0x76b25000 0x00008000
1936 12:51:31.289250 ACPI 17. 0x76b01000 0x00024000
1937 12:51:31.292227 ACPI GNVS 18. 0x76b00000 0x00001000
1938 12:51:31.296003 RAMOOPS 19. 0x76a00000 0x00100000
1939 12:51:31.302334 TPM2 TCGLOG20. 0x769f0000 0x00010000
1940 12:51:31.305537 SMBIOS 21. 0x769ef000 0x00000800
1941 12:51:31.305983 IMD small region:
1942 12:51:31.309160 IMD ROOT 0. 0x76ffec00 0x00000400
1943 12:51:31.315859 FSP RUNTIME 1. 0x76ffebe0 0x00000004
1944 12:51:31.318871 POWER STATE 2. 0x76ffeb80 0x00000044
1945 12:51:31.322510 ROMSTAGE 3. 0x76ffeb60 0x00000004
1946 12:51:31.325666 MEM INFO 4. 0x76ffe980 0x000001e0
1947 12:51:31.332161 BS: BS_WRITE_TABLES run times (exec / console): 6 / 484 ms
1948 12:51:31.335058 MTRR: Physical address space:
1949 12:51:31.341809 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1950 12:51:31.348645 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1951 12:51:31.355458 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
1952 12:51:31.361640 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
1953 12:51:31.365251 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
1954 12:51:31.371627 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
1955 12:51:31.378201 0x0000000100000000 - 0x0000000280400000 size 0x180400000 type 6
1956 12:51:31.381898 MTRR: Fixed MSR 0x250 0x0606060606060606
1957 12:51:31.388015 MTRR: Fixed MSR 0x258 0x0606060606060606
1958 12:51:31.391697 MTRR: Fixed MSR 0x259 0x0000000000000000
1959 12:51:31.394795 MTRR: Fixed MSR 0x268 0x0606060606060606
1960 12:51:31.398633 MTRR: Fixed MSR 0x269 0x0606060606060606
1961 12:51:31.404804 MTRR: Fixed MSR 0x26a 0x0606060606060606
1962 12:51:31.408522 MTRR: Fixed MSR 0x26b 0x0606060606060606
1963 12:51:31.411666 MTRR: Fixed MSR 0x26c 0x0606060606060606
1964 12:51:31.414732 MTRR: Fixed MSR 0x26d 0x0606060606060606
1965 12:51:31.421576 MTRR: Fixed MSR 0x26e 0x0606060606060606
1966 12:51:31.424760 MTRR: Fixed MSR 0x26f 0x0606060606060606
1967 12:51:31.427734 call enable_fixed_mtrr()
1968 12:51:31.431507 CPU physical address size: 39 bits
1969 12:51:31.434620 MTRR: default type WB/UC MTRR counts: 6/6.
1970 12:51:31.437672 MTRR: UC selected as default type.
1971 12:51:31.444652 MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
1972 12:51:31.451311 MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
1973 12:51:31.458115 MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
1974 12:51:31.464228 MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
1975 12:51:31.471021 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
1976 12:51:31.477697 MTRR: 5 base 0x0000000200000000 mask 0x0000007f00000000 type 6
1977 12:51:31.480809 MTRR: Fixed MSR 0x250 0x0606060606060606
1978 12:51:31.487254 MTRR: Fixed MSR 0x258 0x0606060606060606
1979 12:51:31.490847 MTRR: Fixed MSR 0x259 0x0000000000000000
1980 12:51:31.493805 MTRR: Fixed MSR 0x268 0x0606060606060606
1981 12:51:31.497446 MTRR: Fixed MSR 0x269 0x0606060606060606
1982 12:51:31.503905 MTRR: Fixed MSR 0x26a 0x0606060606060606
1983 12:51:31.507487 MTRR: Fixed MSR 0x26b 0x0606060606060606
1984 12:51:31.510555 MTRR: Fixed MSR 0x26c 0x0606060606060606
1985 12:51:31.513625 MTRR: Fixed MSR 0x26d 0x0606060606060606
1986 12:51:31.520377 MTRR: Fixed MSR 0x26e 0x0606060606060606
1987 12:51:31.523419 MTRR: Fixed MSR 0x26f 0x0606060606060606
1988 12:51:31.527152 MTRR: Fixed MSR 0x250 0x0606060606060606
1989 12:51:31.530072 call enable_fixed_mtrr()
1990 12:51:31.533488 MTRR: Fixed MSR 0x258 0x0606060606060606
1991 12:51:31.540146 MTRR: Fixed MSR 0x259 0x0000000000000000
1992 12:51:31.543268 MTRR: Fixed MSR 0x268 0x0606060606060606
1993 12:51:31.546410 MTRR: Fixed MSR 0x269 0x0606060606060606
1994 12:51:31.550266 MTRR: Fixed MSR 0x26a 0x0606060606060606
1995 12:51:31.556263 MTRR: Fixed MSR 0x26b 0x0606060606060606
1996 12:51:31.559695 MTRR: Fixed MSR 0x26c 0x0606060606060606
1997 12:51:31.562890 MTRR: Fixed MSR 0x26d 0x0606060606060606
1998 12:51:31.566643 MTRR: Fixed MSR 0x26e 0x0606060606060606
1999 12:51:31.572666 MTRR: Fixed MSR 0x26f 0x0606060606060606
2000 12:51:31.575955 CPU physical address size: 39 bits
2001 12:51:31.579671 call enable_fixed_mtrr()
2002 12:51:31.582499 MTRR: Fixed MSR 0x250 0x0606060606060606
2003 12:51:31.589487 MTRR: Fixed MSR 0x250 0x0606060606060606
2004 12:51:31.592467 MTRR: Fixed MSR 0x258 0x0606060606060606
2005 12:51:31.596231 MTRR: Fixed MSR 0x259 0x0000000000000000
2006 12:51:31.599232 MTRR: Fixed MSR 0x268 0x0606060606060606
2007 12:51:31.602768 MTRR: Fixed MSR 0x269 0x0606060606060606
2008 12:51:31.608988 MTRR: Fixed MSR 0x26a 0x0606060606060606
2009 12:51:31.612782 MTRR: Fixed MSR 0x26b 0x0606060606060606
2010 12:51:31.615871 MTRR: Fixed MSR 0x26c 0x0606060606060606
2011 12:51:31.619638 MTRR: Fixed MSR 0x26d 0x0606060606060606
2012 12:51:31.625801 MTRR: Fixed MSR 0x26e 0x0606060606060606
2013 12:51:31.629014 MTRR: Fixed MSR 0x26f 0x0606060606060606
2014 12:51:31.632218 MTRR: Fixed MSR 0x258 0x0606060606060606
2015 12:51:31.635633 call enable_fixed_mtrr()
2016 12:51:31.639129 MTRR: Fixed MSR 0x259 0x0000000000000000
2017 12:51:31.645387 MTRR: Fixed MSR 0x268 0x0606060606060606
2018 12:51:31.649150 MTRR: Fixed MSR 0x269 0x0606060606060606
2019 12:51:31.652228 MTRR: Fixed MSR 0x26a 0x0606060606060606
2020 12:51:31.655297 MTRR: Fixed MSR 0x26b 0x0606060606060606
2021 12:51:31.661838 MTRR: Fixed MSR 0x26c 0x0606060606060606
2022 12:51:31.665418 MTRR: Fixed MSR 0x26d 0x0606060606060606
2023 12:51:31.668547 MTRR: Fixed MSR 0x26e 0x0606060606060606
2024 12:51:31.672143 MTRR: Fixed MSR 0x26f 0x0606060606060606
2025 12:51:31.676389 CPU physical address size: 39 bits
2026 12:51:31.682695 call enable_fixed_mtrr()
2027 12:51:31.686392 MTRR: Fixed MSR 0x250 0x0606060606060606
2028 12:51:31.686478
2029 12:51:31.686584 MTRR check
2030 12:51:31.689297 MTRR: Fixed MSR 0x258 0x0606060606060606
2031 12:51:31.696156 MTRR: Fixed MSR 0x259 0x0000000000000000
2032 12:51:31.699267 MTRR: Fixed MSR 0x268 0x0606060606060606
2033 12:51:31.703053 MTRR: Fixed MSR 0x269 0x0606060606060606
2034 12:51:31.706125 MTRR: Fixed MSR 0x26a 0x0606060606060606
2035 12:51:31.712812 MTRR: Fixed MSR 0x26b 0x0606060606060606
2036 12:51:31.715890 MTRR: Fixed MSR 0x26c 0x0606060606060606
2037 12:51:31.719750 MTRR: Fixed MSR 0x26d 0x0606060606060606
2038 12:51:31.723118 MTRR: Fixed MSR 0x26e 0x0606060606060606
2039 12:51:31.729296 MTRR: Fixed MSR 0x26f 0x0606060606060606
2040 12:51:31.732374 Fixed MTRRs : call enable_fixed_mtrr()
2041 12:51:31.732515 Enabled
2042 12:51:31.736162 Variable MTRRs: Enabled
2043 12:51:31.736401
2044 12:51:31.739191 CPU physical address size: 39 bits
2045 12:51:31.745705 MTRR: Fixed MSR 0x250 0x0606060606060606
2046 12:51:31.748963 MTRR: Fixed MSR 0x250 0x0606060606060606
2047 12:51:31.752617 MTRR: Fixed MSR 0x258 0x0606060606060606
2048 12:51:31.755749 MTRR: Fixed MSR 0x259 0x0000000000000000
2049 12:51:31.762495 MTRR: Fixed MSR 0x268 0x0606060606060606
2050 12:51:31.765643 MTRR: Fixed MSR 0x269 0x0606060606060606
2051 12:51:31.769210 MTRR: Fixed MSR 0x26a 0x0606060606060606
2052 12:51:31.772248 MTRR: Fixed MSR 0x26b 0x0606060606060606
2053 12:51:31.778906 MTRR: Fixed MSR 0x26c 0x0606060606060606
2054 12:51:31.782120 MTRR: Fixed MSR 0x26d 0x0606060606060606
2055 12:51:31.785315 MTRR: Fixed MSR 0x26e 0x0606060606060606
2056 12:51:31.788612 MTRR: Fixed MSR 0x26f 0x0606060606060606
2057 12:51:31.795692 MTRR: Fixed MSR 0x258 0x0606060606060606
2058 12:51:31.796183 call enable_fixed_mtrr()
2059 12:51:31.802570 MTRR: Fixed MSR 0x259 0x0000000000000000
2060 12:51:31.805757 MTRR: Fixed MSR 0x268 0x0606060606060606
2061 12:51:31.808803 MTRR: Fixed MSR 0x269 0x0606060606060606
2062 12:51:31.812542 MTRR: Fixed MSR 0x26a 0x0606060606060606
2063 12:51:31.819214 MTRR: Fixed MSR 0x26b 0x0606060606060606
2064 12:51:31.822335 MTRR: Fixed MSR 0x26c 0x0606060606060606
2065 12:51:31.825455 MTRR: Fixed MSR 0x26d 0x0606060606060606
2066 12:51:31.829307 MTRR: Fixed MSR 0x26e 0x0606060606060606
2067 12:51:31.835544 MTRR: Fixed MSR 0x26f 0x0606060606060606
2068 12:51:31.838634 CPU physical address size: 39 bits
2069 12:51:31.842340 call enable_fixed_mtrr()
2070 12:51:31.845350 CPU physical address size: 39 bits
2071 12:51:31.852054 BS: BS_WRITE_TABLES exit times (exec / console): 254 / 151 ms
2072 12:51:31.855233 CPU physical address size: 39 bits
2073 12:51:31.858984 Checking cr50 for pending updates
2074 12:51:31.862730 CPU physical address size: 39 bits
2075 12:51:31.866330 Reading cr50 TPM mode
2076 12:51:31.876465 BS: BS_PAYLOAD_LOAD entry times (exec / console): 13 / 6 ms
2077 12:51:31.886450 CBFS: Found 'fallback/payload' @0x38db00 size 0x4be9c in mcache @0x76c4cf60
2078 12:51:31.889546 Checking segment from ROM address 0xffc02b38
2079 12:51:31.893275 Checking segment from ROM address 0xffc02b54
2080 12:51:31.899854 Loading segment from ROM address 0xffc02b38
2081 12:51:31.900301 code (compression=0)
2082 12:51:31.909795 New segment dstaddr 0x30000000 memsize 0x2662db0 srcaddr 0xffc02b70 filesize 0x4be64
2083 12:51:31.919523 Loading Segment: addr: 0x30000000 memsz: 0x0000000002662db0 filesz: 0x000000000004be64
2084 12:51:31.919991 it's not compressed!
2085 12:51:32.059051 [ 0x30000000, 3004be64, 0x32662db0) <- ffc02b70
2086 12:51:32.065787 Clearing Segment: addr: 0x000000003004be64 memsz: 0x0000000002616f4c
2087 12:51:32.072348 Loading segment from ROM address 0xffc02b54
2088 12:51:32.072897 Entry Point 0x30000000
2089 12:51:32.075851 Loaded segments
2090 12:51:32.082017 BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 63 ms
2091 12:51:32.125447 Finalizing chipset.
2092 12:51:32.128298 Finalizing SMM.
2093 12:51:32.128840 APMC done.
2094 12:51:32.135009 BS: BS_PAYLOAD_LOAD exit times (exec / console): 42 / 5 ms
2095 12:51:32.138258 mp_park_aps done after 0 msecs.
2096 12:51:32.142058 Jumping to boot code at 0x30000000(0x76b25000)
2097 12:51:32.151488 CPU0: stack: 0x76bee000 - 0x76bef000, lowest used address 0x76beea78, stack used: 1416 bytes
2098 12:51:32.152051
2099 12:51:32.152467
2100 12:51:32.154652
2101 12:51:32.155137 Starting depthcharge on Voema...
2102 12:51:32.156249 end: 2.2.3 depthcharge-start (duration 00:00:10) [common]
2103 12:51:32.156857 start: 2.2.4 bootloader-commands (timeout 00:04:45) [common]
2104 12:51:32.157315 Setting prompt string to ['volteer:']
2105 12:51:32.157740 bootloader-commands: Wait for prompt ['volteer:'] (timeout 00:04:45)
2106 12:51:32.158637
2107 12:51:32.165093 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2108 12:51:32.165578
2109 12:51:32.171472 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2110 12:51:32.171980
2111 12:51:32.178425 Looking for NVMe Controller 0x3005f220 @ 00:1d:00
2112 12:51:32.179107
2113 12:51:32.181384 Failed to find eMMC card reader
2114 12:51:32.181866
2115 12:51:32.182245 Wipe memory regions:
2116 12:51:32.184977
2117 12:51:32.187724 [0x00000000001000, 0x000000000a0000)
2118 12:51:32.188208
2119 12:51:32.191464 [0x00000000100000, 0x00000030000000)
2120 12:51:32.216832
2121 12:51:32.219675 [0x00000032662db0, 0x000000769ef000)
2122 12:51:32.255713
2123 12:51:32.258800 [0x00000100000000, 0x00000280400000)
2124 12:51:32.461762
2125 12:51:32.464872 ec_init: CrosEC protocol v3 supported (256, 256)
2126 12:51:32.465458
2127 12:51:32.471453 update_port_state: port C0 state: usb enable 1 mux conn 0
2128 12:51:32.471990
2129 12:51:32.481410 update_port_state: port C0 req: usage 0 usb3 1 usb2 9 ufp 1 ori_hsl 0 ori_sbu 0 dbg_acc 1
2130 12:51:32.481968
2131 12:51:32.488379 pmc_check_ipc_sts: STS_BUSY done after 1612 us
2132 12:51:32.488936
2133 12:51:32.491151 send_conn_disc_msg: pmc_send_cmd succeeded
2134 12:51:32.922932
2135 12:51:32.923529 R8152: Initializing
2136 12:51:32.923960
2137 12:51:32.925992 Version 6 (ocp_data = 5c30)
2138 12:51:32.926499
2139 12:51:32.929285 R8152: Done initializing
2140 12:51:32.929878
2141 12:51:32.932181 Adding net device
2142 12:51:33.235796
2143 12:51:33.238677 [firmware-volteer-13672.B-collabora] Oct 22 2021 06:32:35
2144 12:51:33.239334
2145 12:51:33.239776
2146 12:51:33.240145
2147 12:51:33.242358 Setting prompt string to ['volteer:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2149 12:51:33.344196 volteer: tftpboot 192.168.201.1 9729813/tftp-deploy-89qikdnh/kernel/bzImage 9729813/tftp-deploy-89qikdnh/kernel/cmdline 9729813/tftp-deploy-89qikdnh/ramdisk/ramdisk.cpio.gz
2150 12:51:33.344932 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2151 12:51:33.345398 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:43)
2152 12:51:33.350043 tftpboot 192.168.201.1 9729813/tftp-deploy-89qikdnh/kernel/bzImaoy-89qikdnh/kernel/cmdline 9729813/tftp-deploy-89qikdnh/ramdisk/ramdisk.cpio.gz
2153 12:51:33.350677
2154 12:51:33.351241 Waiting for link
2155 12:51:33.554405
2156 12:51:33.555019 done.
2157 12:51:33.555554
2158 12:51:33.556093 MAC: 00:24:32:30:79:06
2159 12:51:33.556601
2160 12:51:33.558089 Sending DHCP discover... done.
2161 12:51:33.558636
2162 12:51:33.561034 Waiting for reply... done.
2163 12:51:33.561514
2164 12:51:33.564022 Sending DHCP request... done.
2165 12:51:33.564506
2166 12:51:33.567630 Waiting for reply... done.
2167 12:51:33.568111
2168 12:51:33.570866 My ip is 192.168.201.23
2169 12:51:33.571349
2170 12:51:33.573865 The DHCP server ip is 192.168.201.1
2171 12:51:33.574349
2172 12:51:33.580762 TFTP server IP predefined by user: 192.168.201.1
2173 12:51:33.581249
2174 12:51:33.586970 Bootfile predefined by user: 9729813/tftp-deploy-89qikdnh/kernel/bzImage
2175 12:51:33.587477
2176 12:51:33.590636 Sending tftp read request... done.
2177 12:51:33.591138
2178 12:51:33.593598 Waiting for the transfer...
2179 12:51:33.594080
2180 12:51:34.245237 00000000 ################################################################
2181 12:51:34.245772
2182 12:51:34.822794 00080000 ################################################################
2183 12:51:34.822940
2184 12:51:35.426444 00100000 ################################################################
2185 12:51:35.426630
2186 12:51:35.993379 00180000 ################################################################
2187 12:51:35.993529
2188 12:51:36.581882 00200000 ################################################################
2189 12:51:36.582028
2190 12:51:37.146449 00280000 ################################################################
2191 12:51:37.146636
2192 12:51:37.681112 00300000 ################################################################
2193 12:51:37.681252
2194 12:51:38.210317 00380000 ################################################################
2195 12:51:38.210478
2196 12:51:38.758396 00400000 ################################################################
2197 12:51:38.758569
2198 12:51:39.283621 00480000 ################################################################
2199 12:51:39.283772
2200 12:51:39.798341 00500000 ################################################################
2201 12:51:39.798486
2202 12:51:40.338007 00580000 ################################################################
2203 12:51:40.338197
2204 12:51:40.997426 00600000 ################################################################
2205 12:51:40.997564
2206 12:51:41.606418 00680000 ################################################################
2207 12:51:41.606605
2208 12:51:42.137698 00700000 ################################################################
2209 12:51:42.137845
2210 12:51:42.722532 00780000 ################################################################
2211 12:51:42.722693
2212 12:51:43.285107 00800000 ################################################################
2213 12:51:43.285244
2214 12:51:43.860286 00880000 ################################################################
2215 12:51:43.860435
2216 12:51:44.441909 00900000 ################################################################
2217 12:51:44.442044
2218 12:51:45.013982 00980000 ################################################################
2219 12:51:45.014119
2220 12:51:45.597225 00a00000 ################################################################
2221 12:51:45.597365
2222 12:51:46.165835 00a80000 ################################################################
2223 12:51:46.165971
2224 12:51:46.532729 00b00000 ########################################### done.
2225 12:51:46.532871
2226 12:51:46.536299 The bootfile was 11878592 bytes long.
2227 12:51:46.536396
2228 12:51:46.539603 Sending tftp read request... done.
2229 12:51:46.539776
2230 12:51:46.542423 Waiting for the transfer...
2231 12:51:46.542579
2232 12:51:47.143988 00000000 ################################################################
2233 12:51:47.144519
2234 12:51:47.807105 00080000 ################################################################
2235 12:51:47.807620
2236 12:51:48.470069 00100000 ################################################################
2237 12:51:48.470687
2238 12:51:49.131429 00180000 ################################################################
2239 12:51:49.132015
2240 12:51:49.808682 00200000 ################################################################
2241 12:51:49.809287
2242 12:51:50.488599 00280000 ################################################################
2243 12:51:50.489128
2244 12:51:51.162195 00300000 ################################################################
2245 12:51:51.162821
2246 12:51:51.776033 00380000 ################################################################
2247 12:51:51.776789
2248 12:51:52.352622 00400000 ################################################################
2249 12:51:52.352774
2250 12:51:52.945230 00480000 ################################################################
2251 12:51:52.945383
2252 12:51:53.567107 00500000 ################################################################
2253 12:51:53.567260
2254 12:51:54.111811 00580000 ################################################################
2255 12:51:54.111965
2256 12:51:54.682400 00600000 ################################################################
2257 12:51:54.682973
2258 12:51:55.360919 00680000 ################################################################
2259 12:51:55.361496
2260 12:51:55.998321 00700000 ################################################################
2261 12:51:55.998471
2262 12:51:56.650508 00780000 ################################################################
2263 12:51:56.651138
2264 12:51:57.327156 00800000 ################################################################
2265 12:51:57.327776
2266 12:51:58.000318 00880000 ################################################################
2267 12:51:58.000867
2268 12:51:58.679834 00900000 ################################################################
2269 12:51:58.680409
2270 12:51:59.231561 00980000 ######################################################### done.
2271 12:51:59.231842
2272 12:51:59.235321 Sending tftp read request... done.
2273 12:51:59.235761
2274 12:51:59.238140 Waiting for the transfer...
2275 12:51:59.238623
2276 12:51:59.238978 00000000 # done.
2277 12:51:59.239315
2278 12:51:59.247984 Command line loaded dynamically from TFTP file: 9729813/tftp-deploy-89qikdnh/kernel/cmdline
2279 12:51:59.248532
2280 12:51:59.261573 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2281 12:51:59.266577
2282 12:51:59.269723 Shutting down all USB controllers.
2283 12:51:59.270203
2284 12:51:59.270618 Removing current net device
2285 12:51:59.270985
2286 12:51:59.272543 Finalizing coreboot
2287 12:51:59.273030
2288 12:51:59.279131 Exiting depthcharge with code 4 at timestamp: 35783964
2289 12:51:59.279738
2290 12:51:59.280318
2291 12:51:59.280895 Starting kernel ...
2292 12:51:59.281360
2293 12:51:59.281774
2294 12:51:59.283684 end: 2.2.4 bootloader-commands (duration 00:00:27) [common]
2295 12:51:59.284415 start: 2.2.5 auto-login-action (timeout 00:04:17) [common]
2296 12:51:59.284867 Setting prompt string to ['Linux version [0-9]']
2297 12:51:59.285268 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2298 12:51:59.285669 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2300 12:56:16.284859 end: 2.2.5 auto-login-action (duration 00:04:17) [common]
2302 12:56:16.285190 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 257 seconds'
2304 12:56:16.285440 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2307 12:56:16.285860 end: 2 depthcharge-action (duration 00:05:00) [common]
2309 12:56:16.286218 Cleaning after the job
2310 12:56:16.286346 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9729813/tftp-deploy-89qikdnh/ramdisk
2311 12:56:16.287443 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9729813/tftp-deploy-89qikdnh/kernel
2312 12:56:16.288642 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9729813/tftp-deploy-89qikdnh/modules
2313 12:56:16.289572 start: 5.1 power-off (timeout 00:00:30) [common]
2314 12:56:16.289819 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-2' '--port=1' '--command=off'
2315 12:56:16.364885 >> Command sent successfully.
2316 12:56:16.367119 Returned 0 in 0 seconds
2317 12:56:16.467965 end: 5.1 power-off (duration 00:00:00) [common]
2319 12:56:16.468427 start: 5.2 read-feedback (timeout 00:10:00) [common]
2320 12:56:16.468745 Listened to connection for namespace 'common' for up to 1s
2321 12:56:17.470590 Finalising connection for namespace 'common'
2322 12:56:17.470817 Disconnecting from shell: Finalise
2323 12:56:17.470939
2324 12:56:17.571689 end: 5.2 read-feedback (duration 00:00:01) [common]
2325 12:56:17.571863 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/9729813
2326 12:56:17.578964 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/9729813
2327 12:56:17.579107 JobError: Your job cannot terminate cleanly.