Boot log: mt8192-asurada-spherion-r0
- Warnings: 3
- Kernel Warnings: 102
- Errors: 2
- Kernel Errors: 7
- Boot result: FAIL
1 19:14:30.716270 lava-dispatcher, installed at version: 2024.03
2 19:14:30.716531 start: 0 validate
3 19:14:30.716666 Start time: 2024-05-18 19:14:30.716658+00:00 (UTC)
4 19:14:30.716791 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:14:30.716924 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 19:14:30.975909 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:14:30.976087 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.9-8654-g0cc6f45cecb46%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:14:52.479187 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:14:52.479345 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.9-8654-g0cc6f45cecb46%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:14:52.736125 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:14:52.736346 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.9-8654-g0cc6f45cecb46%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 19:14:56.992035 validate duration: 26.28
14 19:14:56.992305 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 19:14:56.992454 start: 1.1 download-retry (timeout 00:10:00) [common]
16 19:14:56.992549 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 19:14:56.992679 Not decompressing ramdisk as can be used compressed.
18 19:14:56.992768 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 19:14:56.992835 saving as /var/lib/lava/dispatcher/tmp/13888633/tftp-deploy-lq2x80os/ramdisk/rootfs.cpio.gz
20 19:14:56.992898 total size: 8181887 (7 MB)
21 19:14:57.249390 progress 0 % (0 MB)
22 19:14:57.252097 progress 5 % (0 MB)
23 19:14:57.254465 progress 10 % (0 MB)
24 19:14:57.257040 progress 15 % (1 MB)
25 19:14:57.259518 progress 20 % (1 MB)
26 19:14:57.262051 progress 25 % (1 MB)
27 19:14:57.264517 progress 30 % (2 MB)
28 19:14:57.267137 progress 35 % (2 MB)
29 19:14:57.269587 progress 40 % (3 MB)
30 19:14:57.272211 progress 45 % (3 MB)
31 19:14:57.274591 progress 50 % (3 MB)
32 19:14:57.277174 progress 55 % (4 MB)
33 19:14:57.279312 progress 60 % (4 MB)
34 19:14:57.281633 progress 65 % (5 MB)
35 19:14:57.283765 progress 70 % (5 MB)
36 19:14:57.286048 progress 75 % (5 MB)
37 19:14:57.288226 progress 80 % (6 MB)
38 19:14:57.290569 progress 85 % (6 MB)
39 19:14:57.292761 progress 90 % (7 MB)
40 19:14:57.295144 progress 95 % (7 MB)
41 19:14:57.297417 progress 100 % (7 MB)
42 19:14:57.297660 7 MB downloaded in 0.30 s (25.60 MB/s)
43 19:14:57.297837 end: 1.1.1 http-download (duration 00:00:00) [common]
45 19:14:57.298241 end: 1.1 download-retry (duration 00:00:00) [common]
46 19:14:57.298390 start: 1.2 download-retry (timeout 00:10:00) [common]
47 19:14:57.298539 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 19:14:57.298776 downloading http://storage.kernelci.org/mainline/master/v6.9-8654-g0cc6f45cecb46/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 19:14:57.298900 saving as /var/lib/lava/dispatcher/tmp/13888633/tftp-deploy-lq2x80os/kernel/Image
50 19:14:57.299021 total size: 61022720 (58 MB)
51 19:14:57.299144 No compression specified
52 19:14:57.300425 progress 0 % (0 MB)
53 19:14:57.318332 progress 5 % (2 MB)
54 19:14:57.334820 progress 10 % (5 MB)
55 19:14:57.351248 progress 15 % (8 MB)
56 19:14:57.367459 progress 20 % (11 MB)
57 19:14:57.383482 progress 25 % (14 MB)
58 19:14:57.400697 progress 30 % (17 MB)
59 19:14:57.417547 progress 35 % (20 MB)
60 19:14:57.434496 progress 40 % (23 MB)
61 19:14:57.451752 progress 45 % (26 MB)
62 19:14:57.468397 progress 50 % (29 MB)
63 19:14:57.484806 progress 55 % (32 MB)
64 19:14:57.501094 progress 60 % (34 MB)
65 19:14:57.518089 progress 65 % (37 MB)
66 19:14:57.535063 progress 70 % (40 MB)
67 19:14:57.551589 progress 75 % (43 MB)
68 19:14:57.568443 progress 80 % (46 MB)
69 19:14:57.585472 progress 85 % (49 MB)
70 19:14:57.603895 progress 90 % (52 MB)
71 19:14:57.621794 progress 95 % (55 MB)
72 19:14:57.639291 progress 100 % (58 MB)
73 19:14:57.639557 58 MB downloaded in 0.34 s (170.90 MB/s)
74 19:14:57.639736 end: 1.2.1 http-download (duration 00:00:00) [common]
76 19:14:57.640120 end: 1.2 download-retry (duration 00:00:00) [common]
77 19:14:57.640241 start: 1.3 download-retry (timeout 00:09:59) [common]
78 19:14:57.640373 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 19:14:57.640529 downloading http://storage.kernelci.org/mainline/master/v6.9-8654-g0cc6f45cecb46/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 19:14:57.640628 saving as /var/lib/lava/dispatcher/tmp/13888633/tftp-deploy-lq2x80os/dtb/mt8192-asurada-spherion-r0.dtb
81 19:14:57.640722 total size: 65308 (0 MB)
82 19:14:57.640829 No compression specified
83 19:14:57.642561 progress 50 % (0 MB)
84 19:14:57.684441 progress 100 % (0 MB)
85 19:14:57.684777 0 MB downloaded in 0.04 s (1.41 MB/s)
86 19:14:57.684996 end: 1.3.1 http-download (duration 00:00:00) [common]
88 19:14:57.685396 end: 1.3 download-retry (duration 00:00:00) [common]
89 19:14:57.685518 start: 1.4 download-retry (timeout 00:09:59) [common]
90 19:14:57.685649 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 19:14:57.685847 downloading http://storage.kernelci.org/mainline/master/v6.9-8654-g0cc6f45cecb46/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 19:14:57.685949 saving as /var/lib/lava/dispatcher/tmp/13888633/tftp-deploy-lq2x80os/modules/modules.tar
93 19:14:57.686043 total size: 10215828 (9 MB)
94 19:14:57.686152 Using unxz to decompress xz
95 19:14:57.690995 progress 0 % (0 MB)
96 19:14:57.719496 progress 5 % (0 MB)
97 19:14:57.753699 progress 10 % (1 MB)
98 19:14:57.789938 progress 15 % (1 MB)
99 19:14:57.829639 progress 20 % (1 MB)
100 19:14:57.859743 progress 25 % (2 MB)
101 19:14:57.893922 progress 30 % (2 MB)
102 19:14:57.928724 progress 35 % (3 MB)
103 19:14:57.961517 progress 40 % (3 MB)
104 19:14:57.997340 progress 45 % (4 MB)
105 19:14:58.030108 progress 50 % (4 MB)
106 19:14:58.067725 progress 55 % (5 MB)
107 19:14:58.102876 progress 60 % (5 MB)
108 19:14:58.135352 progress 65 % (6 MB)
109 19:14:58.171472 progress 70 % (6 MB)
110 19:14:58.210502 progress 75 % (7 MB)
111 19:14:58.248282 progress 80 % (7 MB)
112 19:14:58.279037 progress 85 % (8 MB)
113 19:14:58.312470 progress 90 % (8 MB)
114 19:14:58.345935 progress 95 % (9 MB)
115 19:14:58.376791 progress 100 % (9 MB)
116 19:14:58.383066 9 MB downloaded in 0.70 s (13.98 MB/s)
117 19:14:58.383447 end: 1.4.1 http-download (duration 00:00:01) [common]
119 19:14:58.383908 end: 1.4 download-retry (duration 00:00:01) [common]
120 19:14:58.384112 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 19:14:58.384270 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 19:14:58.384438 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 19:14:58.384579 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 19:14:58.384964 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1
125 19:14:58.385182 makedir: /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin
126 19:14:58.385384 makedir: /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/tests
127 19:14:58.385547 makedir: /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/results
128 19:14:58.385720 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-add-keys
129 19:14:58.385939 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-add-sources
130 19:14:58.386142 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-background-process-start
131 19:14:58.386357 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-background-process-stop
132 19:14:58.386595 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-common-functions
133 19:14:58.386822 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-echo-ipv4
134 19:14:58.387050 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-install-packages
135 19:14:58.387236 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-installed-packages
136 19:14:58.387432 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-os-build
137 19:14:58.387645 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-probe-channel
138 19:14:58.387848 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-probe-ip
139 19:14:58.388067 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-target-ip
140 19:14:58.388251 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-target-mac
141 19:14:58.388487 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-target-storage
142 19:14:58.388694 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-test-case
143 19:14:58.388881 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-test-event
144 19:14:58.389096 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-test-feedback
145 19:14:58.389323 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-test-raise
146 19:14:58.389553 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-test-reference
147 19:14:58.389742 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-test-runner
148 19:14:58.389927 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-test-set
149 19:14:58.390125 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-test-shell
150 19:14:58.390320 Updating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-install-packages (oe)
151 19:14:58.390548 Updating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/bin/lava-installed-packages (oe)
152 19:14:58.390744 Creating /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/environment
153 19:14:58.390908 LAVA metadata
154 19:14:58.391026 - LAVA_JOB_ID=13888633
155 19:14:58.391143 - LAVA_DISPATCHER_IP=192.168.201.1
156 19:14:58.391314 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 19:14:58.391426 skipped lava-vland-overlay
158 19:14:58.391578 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 19:14:58.391741 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 19:14:58.391903 skipped lava-multinode-overlay
161 19:14:58.392056 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 19:14:58.392196 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 19:14:58.392317 Loading test definitions
164 19:14:58.392467 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 19:14:58.392590 Using /lava-13888633 at stage 0
166 19:14:58.393154 uuid=13888633_1.5.2.3.1 testdef=None
167 19:14:58.393326 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 19:14:58.393457 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 19:14:58.394279 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 19:14:58.394662 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 19:14:58.395764 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 19:14:58.396157 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 19:14:58.397127 runner path: /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/0/tests/0_dmesg test_uuid 13888633_1.5.2.3.1
176 19:14:58.397352 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 19:14:58.397772 Creating lava-test-runner.conf files
179 19:14:58.397904 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13888633/lava-overlay-30tglox1/lava-13888633/0 for stage 0
180 19:14:58.398061 - 0_dmesg
181 19:14:58.398206 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 19:14:58.398342 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 19:14:58.410113 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 19:14:58.410343 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 19:14:58.410498 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 19:14:58.410665 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 19:14:58.410815 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 19:14:58.681747 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 19:14:58.682298 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 19:14:58.682485 extracting modules file /var/lib/lava/dispatcher/tmp/13888633/tftp-deploy-lq2x80os/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13888633/extract-overlay-ramdisk-apcu354v/ramdisk
191 19:14:58.995294 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 19:14:58.995471 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 19:14:58.995581 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13888633/compress-overlay-oo33_vrq/overlay-1.5.2.4.tar.gz to ramdisk
194 19:14:58.995682 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13888633/compress-overlay-oo33_vrq/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13888633/extract-overlay-ramdisk-apcu354v/ramdisk
195 19:14:59.003847 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 19:14:59.003998 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 19:14:59.004129 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 19:14:59.004254 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 19:14:59.004384 Building ramdisk /var/lib/lava/dispatcher/tmp/13888633/extract-overlay-ramdisk-apcu354v/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13888633/extract-overlay-ramdisk-apcu354v/ramdisk
200 19:14:59.425551 >> 166416 blocks
201 19:15:02.294131 rename /var/lib/lava/dispatcher/tmp/13888633/extract-overlay-ramdisk-apcu354v/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13888633/tftp-deploy-lq2x80os/ramdisk/ramdisk.cpio.gz
202 19:15:02.294776 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 19:15:02.295013 start: 1.5.8 prepare-kernel (timeout 00:09:55) [common]
204 19:15:02.295166 start: 1.5.8.1 prepare-fit (timeout 00:09:55) [common]
205 19:15:02.295354 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/13888633/tftp-deploy-lq2x80os/kernel/Image']
206 19:15:20.586851 Returned 0 in 18 seconds
207 19:15:20.687622 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13888633/tftp-deploy-lq2x80os/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13888633/tftp-deploy-lq2x80os/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13888633/tftp-deploy-lq2x80os/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13888633/tftp-deploy-lq2x80os/kernel/image.itb
208 19:15:21.134996 output: FIT description: Kernel Image image with one or more FDT blobs
209 19:15:21.135457 output: Created: Sat May 18 20:15:21 2024
210 19:15:21.135602 output: Image 0 (kernel-1)
211 19:15:21.135697 output: Description:
212 19:15:21.135790 output: Created: Sat May 18 20:15:21 2024
213 19:15:21.135884 output: Type: Kernel Image
214 19:15:21.136040 output: Compression: lzma compressed
215 19:15:21.136136 output: Data Size: 13879864 Bytes = 13554.55 KiB = 13.24 MiB
216 19:15:21.136235 output: Architecture: AArch64
217 19:15:21.136333 output: OS: Linux
218 19:15:21.136437 output: Load Address: 0x00000000
219 19:15:21.136533 output: Entry Point: 0x00000000
220 19:15:21.136625 output: Hash algo: crc32
221 19:15:21.136718 output: Hash value: 78077d7c
222 19:15:21.136812 output: Image 1 (fdt-1)
223 19:15:21.136903 output: Description: mt8192-asurada-spherion-r0
224 19:15:21.136998 output: Created: Sat May 18 20:15:21 2024
225 19:15:21.137092 output: Type: Flat Device Tree
226 19:15:21.137182 output: Compression: uncompressed
227 19:15:21.137275 output: Data Size: 65308 Bytes = 63.78 KiB = 0.06 MiB
228 19:15:21.137365 output: Architecture: AArch64
229 19:15:21.137456 output: Hash algo: crc32
230 19:15:21.137546 output: Hash value: 5ff524f6
231 19:15:21.137635 output: Image 2 (ramdisk-1)
232 19:15:21.137729 output: Description: unavailable
233 19:15:21.137818 output: Created: Sat May 18 20:15:21 2024
234 19:15:21.137909 output: Type: RAMDisk Image
235 19:15:21.137998 output: Compression: Unknown Compression
236 19:15:21.138084 output: Data Size: 23944650 Bytes = 23383.45 KiB = 22.84 MiB
237 19:15:21.138172 output: Architecture: AArch64
238 19:15:21.138258 output: OS: Linux
239 19:15:21.138348 output: Load Address: unavailable
240 19:15:21.138438 output: Entry Point: unavailable
241 19:15:21.138526 output: Hash algo: crc32
242 19:15:21.138610 output: Hash value: 1d42e45c
243 19:15:21.138700 output: Default Configuration: 'conf-1'
244 19:15:21.138787 output: Configuration 0 (conf-1)
245 19:15:21.138877 output: Description: mt8192-asurada-spherion-r0
246 19:15:21.138967 output: Kernel: kernel-1
247 19:15:21.139055 output: Init Ramdisk: ramdisk-1
248 19:15:21.139146 output: FDT: fdt-1
249 19:15:21.139234 output: Loadables: kernel-1
250 19:15:21.139323 output:
251 19:15:21.139599 end: 1.5.8.1 prepare-fit (duration 00:00:19) [common]
252 19:15:21.139747 end: 1.5.8 prepare-kernel (duration 00:00:19) [common]
253 19:15:21.139902 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 19:15:21.140043 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 19:15:21.140163 No LXC device requested
256 19:15:21.140286 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 19:15:21.140456 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 19:15:21.140609 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 19:15:21.140743 Checking files for TFTP limit of 4294967296 bytes.
260 19:15:21.141514 end: 1 tftp-deploy (duration 00:00:24) [common]
261 19:15:21.141662 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 19:15:21.141802 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 19:15:21.142005 substitutions:
264 19:15:21.142107 - {DTB}: 13888633/tftp-deploy-lq2x80os/dtb/mt8192-asurada-spherion-r0.dtb
265 19:15:21.142232 - {INITRD}: 13888633/tftp-deploy-lq2x80os/ramdisk/ramdisk.cpio.gz
266 19:15:21.142352 - {KERNEL}: 13888633/tftp-deploy-lq2x80os/kernel/Image
267 19:15:21.142470 - {LAVA_MAC}: None
268 19:15:21.142563 - {PRESEED_CONFIG}: None
269 19:15:21.142650 - {PRESEED_LOCAL}: None
270 19:15:21.142743 - {RAMDISK}: 13888633/tftp-deploy-lq2x80os/ramdisk/ramdisk.cpio.gz
271 19:15:21.142832 - {ROOT_PART}: None
272 19:15:21.142920 - {ROOT}: None
273 19:15:21.143012 - {SERVER_IP}: 192.168.201.1
274 19:15:21.143103 - {TEE}: None
275 19:15:21.143191 Parsed boot commands:
276 19:15:21.143277 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 19:15:21.143527 Parsed boot commands: tftpboot 192.168.201.1 13888633/tftp-deploy-lq2x80os/kernel/image.itb 13888633/tftp-deploy-lq2x80os/kernel/cmdline
278 19:15:21.143653 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 19:15:21.143781 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 19:15:21.143910 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 19:15:21.144035 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 19:15:21.144151 Not connected, no need to disconnect.
283 19:15:21.144265 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 19:15:21.144394 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 19:15:21.144504 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 19:15:21.149139 Setting prompt string to ['lava-test: # ']
287 19:15:21.149642 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 19:15:21.149802 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 19:15:21.149950 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 19:15:21.150122 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 19:15:21.150468 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
292 19:15:26.287231 >> Command sent successfully.
293 19:15:26.289943 Returned 0 in 5 seconds
294 19:15:26.390425 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 19:15:26.391091 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 19:15:26.391233 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 19:15:26.391361 Setting prompt string to 'Starting depthcharge on Spherion...'
299 19:15:26.391463 Changing prompt to 'Starting depthcharge on Spherion...'
300 19:15:26.391572 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 19:15:26.392152 [Enter `^Ec?' for help]
302 19:15:26.563405
303 19:15:26.563599
304 19:15:26.563706 F0: 102B 0000
305 19:15:26.563805
306 19:15:26.563898 F3: 1001 0000 [0200]
307 19:15:26.566720
308 19:15:26.566878 F3: 1001 0000
309 19:15:26.566984
310 19:15:26.567077 F7: 102D 0000
311 19:15:26.567169
312 19:15:26.569924 F1: 0000 0000
313 19:15:26.570079
314 19:15:26.570183 V0: 0000 0000 [0001]
315 19:15:26.570277
316 19:15:26.573535 00: 0007 8000
317 19:15:26.573694
318 19:15:26.573795 01: 0000 0000
319 19:15:26.573889
320 19:15:26.576937 BP: 0C00 0209 [0000]
321 19:15:26.577100
322 19:15:26.577204 G0: 1182 0000
323 19:15:26.577297
324 19:15:26.580267 EC: 0000 0021 [4000]
325 19:15:26.580450
326 19:15:26.580557 S7: 0000 0000 [0000]
327 19:15:26.580651
328 19:15:26.584047 CC: 0000 0000 [0001]
329 19:15:26.584205
330 19:15:26.584306 T0: 0000 0040 [010F]
331 19:15:26.584401
332 19:15:26.584466 Jump to BL
333 19:15:26.584527
334 19:15:26.610670
335 19:15:26.610837
336 19:15:26.618177 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 19:15:26.621511 ARM64: Exception handlers installed.
338 19:15:26.625091 ARM64: Testing exception
339 19:15:26.628404 ARM64: Done test exception
340 19:15:26.635412 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 19:15:26.645597 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 19:15:26.652230 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 19:15:26.662400 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 19:15:26.669401 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 19:15:26.675923 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 19:15:26.687676 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 19:15:26.694143 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 19:15:26.713637 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 19:15:26.716384 WDT: Last reset was cold boot
350 19:15:26.719918 SPI1(PAD0) initialized at 2873684 Hz
351 19:15:26.723223 SPI5(PAD0) initialized at 992727 Hz
352 19:15:26.726593 VBOOT: Loading verstage.
353 19:15:26.733483 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 19:15:26.737022 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 19:15:26.740463 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 19:15:26.743171 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 19:15:26.750735 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 19:15:26.757551 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 19:15:26.768899 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
360 19:15:26.769110
361 19:15:26.769224
362 19:15:26.779253 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 19:15:26.782396 ARM64: Exception handlers installed.
364 19:15:26.785370 ARM64: Testing exception
365 19:15:26.785517 ARM64: Done test exception
366 19:15:26.792085 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 19:15:26.795532 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 19:15:26.809311 Probing TPM: . done!
369 19:15:26.809491 TPM ready after 0 ms
370 19:15:26.816879 Connected to device vid:did:rid of 1ae0:0028:00
371 19:15:26.823863 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 19:15:26.884128 Initialized TPM device CR50 revision 0
373 19:15:26.894670 tlcl_send_startup: Startup return code is 0
374 19:15:26.894853 TPM: setup succeeded
375 19:15:26.906227 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 19:15:26.914702 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 19:15:26.928869 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 19:15:26.936305 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 19:15:26.940032 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 19:15:26.943648 in-header: 03 07 00 00 08 00 00 00
381 19:15:26.947348 in-data: aa e4 47 04 13 02 00 00
382 19:15:26.947497 Chrome EC: UHEPI supported
383 19:15:26.955013 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 19:15:26.959204 in-header: 03 95 00 00 08 00 00 00
385 19:15:26.962529 in-data: 18 20 20 08 00 00 00 00
386 19:15:26.962694 Phase 1
387 19:15:26.965964 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 19:15:26.973501 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 19:15:26.977682 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 19:15:26.981220 Recovery requested (1009000e)
391 19:15:26.990346 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 19:15:26.995587 tlcl_extend: response is 0
393 19:15:27.005474 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 19:15:27.010862 tlcl_extend: response is 0
395 19:15:27.017381 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 19:15:27.037241 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
397 19:15:27.043905 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 19:15:27.044073
399 19:15:27.044183
400 19:15:27.054291 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 19:15:27.057549 ARM64: Exception handlers installed.
402 19:15:27.060594 ARM64: Testing exception
403 19:15:27.060739 ARM64: Done test exception
404 19:15:27.082870 pmic_efuse_setting: Set efuses in 11 msecs
405 19:15:27.086421 pmwrap_interface_init: Select PMIF_VLD_RDY
406 19:15:27.093337 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 19:15:27.096116 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 19:15:27.104193 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 19:15:27.107476 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 19:15:27.110685 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 19:15:27.118314 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 19:15:27.122192 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 19:15:27.125944 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 19:15:27.129387 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 19:15:27.136872 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 19:15:27.141092 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 19:15:27.144261 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 19:15:27.147194 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 19:15:27.155612 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 19:15:27.162386 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 19:15:27.166479 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 19:15:27.173799 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 19:15:27.177677 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 19:15:27.185253 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 19:15:27.188849 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 19:15:27.196474 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 19:15:27.199952 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 19:15:27.206875 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 19:15:27.210838 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 19:15:27.218199 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 19:15:27.222393 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 19:15:27.225906 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 19:15:27.232788 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 19:15:27.236509 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 19:15:27.240083 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 19:15:27.247526 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 19:15:27.251506 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 19:15:27.259062 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 19:15:27.262255 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 19:15:27.265795 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 19:15:27.273449 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 19:15:27.277650 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 19:15:27.281166 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 19:15:27.285275 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 19:15:27.292601 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 19:15:27.296288 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 19:15:27.299353 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 19:15:27.303092 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 19:15:27.306904 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 19:15:27.314489 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 19:15:27.317901 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 19:15:27.321953 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 19:15:27.325236 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 19:15:27.329466 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 19:15:27.333081 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 19:15:27.336560 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 19:15:27.348116 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 19:15:27.355345 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 19:15:27.358828 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 19:15:27.366355 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 19:15:27.377170 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 19:15:27.381300 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 19:15:27.384885 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 19:15:27.388260 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 19:15:27.396101 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde71, sec=0x38
466 19:15:27.403412 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 19:15:27.406599 [RTC]rtc_osc_init,62: osc32con val = 0xde71
468 19:15:27.410022 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 19:15:27.420870 [RTC]rtc_get_frequency_meter,154: input=15, output=759
470 19:15:27.430247 [RTC]rtc_get_frequency_meter,154: input=23, output=942
471 19:15:27.439775 [RTC]rtc_get_frequency_meter,154: input=19, output=850
472 19:15:27.449504 [RTC]rtc_get_frequency_meter,154: input=17, output=805
473 19:15:27.459248 [RTC]rtc_get_frequency_meter,154: input=16, output=781
474 19:15:27.468332 [RTC]rtc_get_frequency_meter,154: input=16, output=780
475 19:15:27.478075 [RTC]rtc_get_frequency_meter,154: input=17, output=805
476 19:15:27.481212 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
477 19:15:27.488420 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
478 19:15:27.492257 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 19:15:27.495749 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 19:15:27.499878 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 19:15:27.503956 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 19:15:27.507322 ADC[4]: Raw value=906573 ID=7
483 19:15:27.511150 ADC[3]: Raw value=213441 ID=1
484 19:15:27.511324 RAM Code: 0x71
485 19:15:27.514592 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 19:15:27.518839 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 19:15:27.529594 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 19:15:27.537012 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 19:15:27.540518 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 19:15:27.544193 in-header: 03 07 00 00 08 00 00 00
491 19:15:27.547829 in-data: aa e4 47 04 13 02 00 00
492 19:15:27.547991 Chrome EC: UHEPI supported
493 19:15:27.555152 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 19:15:27.559337 in-header: 03 95 00 00 08 00 00 00
495 19:15:27.562976 in-data: 18 20 20 08 00 00 00 00
496 19:15:27.566477 MRC: failed to locate region type 0.
497 19:15:27.573453 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 19:15:27.573638 DRAM-K: Running full calibration
499 19:15:27.581061 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 19:15:27.585159 header.status = 0x0
501 19:15:27.585364 header.version = 0x6 (expected: 0x6)
502 19:15:27.588421 header.size = 0xd00 (expected: 0xd00)
503 19:15:27.592311 header.flags = 0x0
504 19:15:27.598782 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 19:15:27.616121 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
506 19:15:27.623021 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 19:15:27.627002 dram_init: ddr_geometry: 2
508 19:15:27.627142 [EMI] MDL number = 2
509 19:15:27.631163 [EMI] Get MDL freq = 0
510 19:15:27.631286 dram_init: ddr_type: 0
511 19:15:27.634690 is_discrete_lpddr4: 1
512 19:15:27.634799 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 19:15:27.638879
514 19:15:27.639002
515 19:15:27.639074 [Bian_co] ETT version 0.0.0.1
516 19:15:27.642326 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 19:15:27.646964
518 19:15:27.647101 dramc_set_vcore_voltage set vcore to 650000
519 19:15:27.650083 Read voltage for 800, 4
520 19:15:27.650193 Vio18 = 0
521 19:15:27.654518 Vcore = 650000
522 19:15:27.654656 Vdram = 0
523 19:15:27.654762 Vddq = 0
524 19:15:27.654831 Vmddr = 0
525 19:15:27.658101 dram_init: config_dvfs: 1
526 19:15:27.661703 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 19:15:27.669383 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 19:15:27.672850 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
529 19:15:27.677007 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
530 19:15:27.680513 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
531 19:15:27.684015 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
532 19:15:27.687469 MEM_TYPE=3, freq_sel=18
533 19:15:27.687593 sv_algorithm_assistance_LP4_1600
534 19:15:27.694369 ============ PULL DRAM RESETB DOWN ============
535 19:15:27.697033 ========== PULL DRAM RESETB DOWN end =========
536 19:15:27.700547 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 19:15:27.703845 ===================================
538 19:15:27.708015 LPDDR4 DRAM CONFIGURATION
539 19:15:27.711535 ===================================
540 19:15:27.711670 EX_ROW_EN[0] = 0x0
541 19:15:27.714986 EX_ROW_EN[1] = 0x0
542 19:15:27.715099 LP4Y_EN = 0x0
543 19:15:27.718957 WORK_FSP = 0x0
544 19:15:27.719084 WL = 0x2
545 19:15:27.722587 RL = 0x2
546 19:15:27.722692 BL = 0x2
547 19:15:27.726189 RPST = 0x0
548 19:15:27.726324 RD_PRE = 0x0
549 19:15:27.729556 WR_PRE = 0x1
550 19:15:27.729656 WR_PST = 0x0
551 19:15:27.732681 DBI_WR = 0x0
552 19:15:27.732804 DBI_RD = 0x0
553 19:15:27.736221 OTF = 0x1
554 19:15:27.739559 ===================================
555 19:15:27.742835 ===================================
556 19:15:27.742945 ANA top config
557 19:15:27.745968 ===================================
558 19:15:27.749725 DLL_ASYNC_EN = 0
559 19:15:27.752890 ALL_SLAVE_EN = 1
560 19:15:27.753046 NEW_RANK_MODE = 1
561 19:15:27.756285 DLL_IDLE_MODE = 1
562 19:15:27.759482 LP45_APHY_COMB_EN = 1
563 19:15:27.762851 TX_ODT_DIS = 1
564 19:15:27.762986 NEW_8X_MODE = 1
565 19:15:27.766892 ===================================
566 19:15:27.770208 ===================================
567 19:15:27.773508 data_rate = 1600
568 19:15:27.777259 CKR = 1
569 19:15:27.780298 DQ_P2S_RATIO = 8
570 19:15:27.783748 ===================================
571 19:15:27.787233 CA_P2S_RATIO = 8
572 19:15:27.787376 DQ_CA_OPEN = 0
573 19:15:27.790707 DQ_SEMI_OPEN = 0
574 19:15:27.793380 CA_SEMI_OPEN = 0
575 19:15:27.796943 CA_FULL_RATE = 0
576 19:15:27.800372 DQ_CKDIV4_EN = 1
577 19:15:27.803858 CA_CKDIV4_EN = 1
578 19:15:27.804009 CA_PREDIV_EN = 0
579 19:15:27.807322 PH8_DLY = 0
580 19:15:27.810883 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 19:15:27.813487 DQ_AAMCK_DIV = 4
582 19:15:27.817003 CA_AAMCK_DIV = 4
583 19:15:27.817181 CA_ADMCK_DIV = 4
584 19:15:27.820627 DQ_TRACK_CA_EN = 0
585 19:15:27.824114 CA_PICK = 800
586 19:15:27.826965 CA_MCKIO = 800
587 19:15:27.831254 MCKIO_SEMI = 0
588 19:15:27.834764 PLL_FREQ = 3068
589 19:15:27.834911 DQ_UI_PI_RATIO = 32
590 19:15:27.838232 CA_UI_PI_RATIO = 0
591 19:15:27.842166 ===================================
592 19:15:27.845405 ===================================
593 19:15:27.849369 memory_type:LPDDR4
594 19:15:27.849491 GP_NUM : 10
595 19:15:27.852961 SRAM_EN : 1
596 19:15:27.853077 MD32_EN : 0
597 19:15:27.856464 ===================================
598 19:15:27.859954 [ANA_INIT] >>>>>>>>>>>>>>
599 19:15:27.863769 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 19:15:27.867338 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 19:15:27.867466 ===================================
602 19:15:27.870581 data_rate = 1600,PCW = 0X7600
603 19:15:27.873920 ===================================
604 19:15:27.877089 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 19:15:27.884090 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 19:15:27.890741 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 19:15:27.893928 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 19:15:27.897099 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 19:15:27.900990 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 19:15:27.903872 [ANA_INIT] flow start
611 19:15:27.903983 [ANA_INIT] PLL >>>>>>>>
612 19:15:27.907317 [ANA_INIT] PLL <<<<<<<<
613 19:15:27.910892 [ANA_INIT] MIDPI >>>>>>>>
614 19:15:27.911017 [ANA_INIT] MIDPI <<<<<<<<
615 19:15:27.914338 [ANA_INIT] DLL >>>>>>>>
616 19:15:27.917773 [ANA_INIT] flow end
617 19:15:27.921224 ============ LP4 DIFF to SE enter ============
618 19:15:27.924590 ============ LP4 DIFF to SE exit ============
619 19:15:27.927380 [ANA_INIT] <<<<<<<<<<<<<
620 19:15:27.930907 [Flow] Enable top DCM control >>>>>
621 19:15:27.934411 [Flow] Enable top DCM control <<<<<
622 19:15:27.937916 Enable DLL master slave shuffle
623 19:15:27.940683 ==============================================================
624 19:15:27.944220 Gating Mode config
625 19:15:27.951064 ==============================================================
626 19:15:27.951208 Config description:
627 19:15:27.960696 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 19:15:27.967626 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 19:15:27.971060 SELPH_MODE 0: By rank 1: By Phase
630 19:15:27.977391 ==============================================================
631 19:15:27.980639 GAT_TRACK_EN = 1
632 19:15:27.984332 RX_GATING_MODE = 2
633 19:15:27.987759 RX_GATING_TRACK_MODE = 2
634 19:15:27.990949 SELPH_MODE = 1
635 19:15:27.994091 PICG_EARLY_EN = 1
636 19:15:27.994199 VALID_LAT_VALUE = 1
637 19:15:28.001066 ==============================================================
638 19:15:28.004043 Enter into Gating configuration >>>>
639 19:15:28.007400 Exit from Gating configuration <<<<
640 19:15:28.010854 Enter into DVFS_PRE_config >>>>>
641 19:15:28.020934 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 19:15:28.024193 Exit from DVFS_PRE_config <<<<<
643 19:15:28.027455 Enter into PICG configuration >>>>
644 19:15:28.030970 Exit from PICG configuration <<<<
645 19:15:28.034120 [RX_INPUT] configuration >>>>>
646 19:15:28.037686 [RX_INPUT] configuration <<<<<
647 19:15:28.041269 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 19:15:28.047450 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 19:15:28.054338 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 19:15:28.061279 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 19:15:28.067629 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 19:15:28.071078 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 19:15:28.077634 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 19:15:28.081015 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 19:15:28.084533 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 19:15:28.087935 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 19:15:28.091509 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 19:15:28.098106 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 19:15:28.101566 ===================================
660 19:15:28.104947 LPDDR4 DRAM CONFIGURATION
661 19:15:28.108177 ===================================
662 19:15:28.108320 EX_ROW_EN[0] = 0x0
663 19:15:28.111654 EX_ROW_EN[1] = 0x0
664 19:15:28.111778 LP4Y_EN = 0x0
665 19:15:28.114415 WORK_FSP = 0x0
666 19:15:28.114531 WL = 0x2
667 19:15:28.117773 RL = 0x2
668 19:15:28.117862 BL = 0x2
669 19:15:28.121218 RPST = 0x0
670 19:15:28.121315 RD_PRE = 0x0
671 19:15:28.124726 WR_PRE = 0x1
672 19:15:28.124828 WR_PST = 0x0
673 19:15:28.128204 DBI_WR = 0x0
674 19:15:28.128316 DBI_RD = 0x0
675 19:15:28.131629 OTF = 0x1
676 19:15:28.134648 ===================================
677 19:15:28.138186 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 19:15:28.141434 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 19:15:28.148224 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 19:15:28.151547 ===================================
681 19:15:28.151661 LPDDR4 DRAM CONFIGURATION
682 19:15:28.154979 ===================================
683 19:15:28.158193 EX_ROW_EN[0] = 0x10
684 19:15:28.158301 EX_ROW_EN[1] = 0x0
685 19:15:28.161468 LP4Y_EN = 0x0
686 19:15:28.165085 WORK_FSP = 0x0
687 19:15:28.165232 WL = 0x2
688 19:15:28.171419 RL = 0x2
689 19:15:28.171586 BL = 0x2
690 19:15:28.171861 RPST = 0x0
691 19:15:28.171960 RD_PRE = 0x0
692 19:15:28.175081 WR_PRE = 0x1
693 19:15:28.175216 WR_PST = 0x0
694 19:15:28.177874 DBI_WR = 0x0
695 19:15:28.177984 DBI_RD = 0x0
696 19:15:28.181355 OTF = 0x1
697 19:15:28.184966 ===================================
698 19:15:28.191344 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 19:15:28.194873 nWR fixed to 40
700 19:15:28.195008 [ModeRegInit_LP4] CH0 RK0
701 19:15:28.198213 [ModeRegInit_LP4] CH0 RK1
702 19:15:28.201557 [ModeRegInit_LP4] CH1 RK0
703 19:15:28.201656 [ModeRegInit_LP4] CH1 RK1
704 19:15:28.204704 match AC timing 13
705 19:15:28.207815 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 19:15:28.211705 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 19:15:28.218246 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 19:15:28.221623 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 19:15:28.228354 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 19:15:28.228485 [EMI DOE] emi_dcm 0
711 19:15:28.231294 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 19:15:28.234939 ==
713 19:15:28.238425 Dram Type= 6, Freq= 0, CH_0, rank 0
714 19:15:28.242040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 19:15:28.242159 ==
716 19:15:28.244785 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 19:15:28.251093 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 19:15:28.261263 [CA 0] Center 36 (6~67) winsize 62
719 19:15:28.264375 [CA 1] Center 36 (6~67) winsize 62
720 19:15:28.267685 [CA 2] Center 34 (4~65) winsize 62
721 19:15:28.271527 [CA 3] Center 33 (3~64) winsize 62
722 19:15:28.274625 [CA 4] Center 33 (3~64) winsize 62
723 19:15:28.277769 [CA 5] Center 32 (3~62) winsize 60
724 19:15:28.277878
725 19:15:28.281613 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 19:15:28.281719
727 19:15:28.284476 [CATrainingPosCal] consider 1 rank data
728 19:15:28.288048 u2DelayCellTimex100 = 270/100 ps
729 19:15:28.291198 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
730 19:15:28.294650 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
731 19:15:28.301089 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
732 19:15:28.304480 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
733 19:15:28.307920 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
734 19:15:28.311235 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
735 19:15:28.311371
736 19:15:28.314600 CA PerBit enable=1, Macro0, CA PI delay=32
737 19:15:28.314730
738 19:15:28.318326 [CBTSetCACLKResult] CA Dly = 32
739 19:15:28.318450 CS Dly: 4 (0~35)
740 19:15:28.318547 ==
741 19:15:28.321278 Dram Type= 6, Freq= 0, CH_0, rank 1
742 19:15:28.328330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 19:15:28.328475 ==
744 19:15:28.331278 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 19:15:28.337878 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 19:15:28.347561 [CA 0] Center 36 (6~67) winsize 62
747 19:15:28.351143 [CA 1] Center 36 (6~67) winsize 62
748 19:15:28.353725 [CA 2] Center 34 (4~64) winsize 61
749 19:15:28.357339 [CA 3] Center 33 (3~64) winsize 62
750 19:15:28.360724 [CA 4] Center 32 (2~63) winsize 62
751 19:15:28.364126 [CA 5] Center 32 (2~63) winsize 62
752 19:15:28.364258
753 19:15:28.367589 [CmdBusTrainingLP45] Vref(ca) range 1: 32
754 19:15:28.367705
755 19:15:28.371070 [CATrainingPosCal] consider 2 rank data
756 19:15:28.374394 u2DelayCellTimex100 = 270/100 ps
757 19:15:28.377913 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
758 19:15:28.380576 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
759 19:15:28.387530 CA2 delay=34 (4~64),Diff = 2 PI (14 cell)
760 19:15:28.391117 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
761 19:15:28.394448 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
762 19:15:28.397720 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
763 19:15:28.397855
764 19:15:28.401059 CA PerBit enable=1, Macro0, CA PI delay=32
765 19:15:28.401184
766 19:15:28.404145 [CBTSetCACLKResult] CA Dly = 32
767 19:15:28.404231 CS Dly: 4 (0~36)
768 19:15:28.404346
769 19:15:28.407781 ----->DramcWriteLeveling(PI) begin...
770 19:15:28.407900 ==
771 19:15:28.411625 Dram Type= 6, Freq= 0, CH_0, rank 0
772 19:15:28.415078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 19:15:28.419347 ==
774 19:15:28.419478 Write leveling (Byte 0): 33 => 33
775 19:15:28.422894 Write leveling (Byte 1): 31 => 31
776 19:15:28.426297 DramcWriteLeveling(PI) end<-----
777 19:15:28.426439
778 19:15:28.426514 ==
779 19:15:28.429562 Dram Type= 6, Freq= 0, CH_0, rank 0
780 19:15:28.432883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 19:15:28.432986 ==
782 19:15:28.436191 [Gating] SW mode calibration
783 19:15:28.443938 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 19:15:28.450603 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 19:15:28.454092 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 19:15:28.456966 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 19:15:28.460410 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
788 19:15:28.466809 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 19:15:28.470144 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 19:15:28.473559 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 19:15:28.480619 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 19:15:28.483357 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 19:15:28.487356 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 19:15:28.493533 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 19:15:28.496910 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 19:15:28.500327 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 19:15:28.507393 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 19:15:28.510192 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 19:15:28.513549 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 19:15:28.520187 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 19:15:28.524200 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 19:15:28.526949 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 19:15:28.533844 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 19:15:28.537119 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 19:15:28.540324 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 19:15:28.547133 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 19:15:28.550367 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 19:15:28.553485 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 19:15:28.557223 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 19:15:28.564066 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 19:15:28.566929 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
812 19:15:28.570337 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
813 19:15:28.577177 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 19:15:28.580612 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 19:15:28.584205 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 19:15:28.590322 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 19:15:28.593675 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 19:15:28.597079 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 19:15:28.604120 0 10 8 | B1->B0 | 3131 2828 | 1 0 | (1 1) (1 1)
820 19:15:28.606943 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
821 19:15:28.610563 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 19:15:28.617451 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 19:15:28.620897 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 19:15:28.623686 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 19:15:28.630958 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 19:15:28.633773 0 11 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
827 19:15:28.637270 0 11 8 | B1->B0 | 2d2d 3c3b | 0 1 | (0 0) (0 0)
828 19:15:28.640738 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
829 19:15:28.647145 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 19:15:28.650885 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 19:15:28.654293 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 19:15:28.660686 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 19:15:28.664254 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 19:15:28.667306 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 19:15:28.673965 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 19:15:28.677767 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 19:15:28.680607 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 19:15:28.687753 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 19:15:28.691345 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 19:15:28.694361 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 19:15:28.698001 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 19:15:28.704571 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 19:15:28.707355 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 19:15:28.711008 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 19:15:28.717474 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 19:15:28.721019 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 19:15:28.724470 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 19:15:28.730794 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 19:15:28.734390 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 19:15:28.737951 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 19:15:28.744162 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
852 19:15:28.744322 Total UI for P1: 0, mck2ui 16
853 19:15:28.751092 best dqsien dly found for B0: ( 0, 14, 6)
854 19:15:28.754562 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
855 19:15:28.758100 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 19:15:28.760872 Total UI for P1: 0, mck2ui 16
857 19:15:28.765075 best dqsien dly found for B1: ( 0, 14, 10)
858 19:15:28.768503 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 19:15:28.772036 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 19:15:28.772180
861 19:15:28.775472 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 19:15:28.778954 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 19:15:28.782114 [Gating] SW calibration Done
864 19:15:28.782252 ==
865 19:15:28.785375 Dram Type= 6, Freq= 0, CH_0, rank 0
866 19:15:28.788323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 19:15:28.792071 ==
868 19:15:28.792206 RX Vref Scan: 0
869 19:15:28.792308
870 19:15:28.795104 RX Vref 0 -> 0, step: 1
871 19:15:28.795219
872 19:15:28.798479 RX Delay -130 -> 252, step: 16
873 19:15:28.801500 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
874 19:15:28.805378 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 19:15:28.808661 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 19:15:28.811612 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 19:15:28.818436 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 19:15:28.821821 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 19:15:28.825241 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
880 19:15:28.828793 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 19:15:28.831862 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
882 19:15:28.838680 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
883 19:15:28.841474 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 19:15:28.844988 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
885 19:15:28.848647 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
886 19:15:28.852083 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
887 19:15:28.858463 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 19:15:28.861843 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 19:15:28.861989 ==
890 19:15:28.865354 Dram Type= 6, Freq= 0, CH_0, rank 0
891 19:15:28.868955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 19:15:28.869106 ==
893 19:15:28.869213 DQS Delay:
894 19:15:28.871622 DQS0 = 0, DQS1 = 0
895 19:15:28.871737 DQM Delay:
896 19:15:28.875109 DQM0 = 90, DQM1 = 84
897 19:15:28.875247 DQ Delay:
898 19:15:28.878515 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
899 19:15:28.882058 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
900 19:15:28.884987 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
901 19:15:28.888467 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
902 19:15:28.888610
903 19:15:28.888714
904 19:15:28.888780 ==
905 19:15:28.891904 Dram Type= 6, Freq= 0, CH_0, rank 0
906 19:15:28.895282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 19:15:28.898857 ==
908 19:15:28.899001
909 19:15:28.899105
910 19:15:28.899177 TX Vref Scan disable
911 19:15:28.902407 == TX Byte 0 ==
912 19:15:28.905184 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
913 19:15:28.908511 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
914 19:15:28.911795 == TX Byte 1 ==
915 19:15:28.915794 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 19:15:28.918610 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 19:15:28.918754 ==
918 19:15:28.922381 Dram Type= 6, Freq= 0, CH_0, rank 0
919 19:15:28.928923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 19:15:28.929058 ==
921 19:15:28.940939 TX Vref=22, minBit 8, minWin=27, winSum=444
922 19:15:28.944370 TX Vref=24, minBit 8, minWin=27, winSum=449
923 19:15:28.947551 TX Vref=26, minBit 0, minWin=28, winSum=455
924 19:15:28.950678 TX Vref=28, minBit 0, minWin=28, winSum=455
925 19:15:28.954390 TX Vref=30, minBit 5, minWin=28, winSum=458
926 19:15:28.960829 TX Vref=32, minBit 10, minWin=27, winSum=454
927 19:15:28.964288 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 30
928 19:15:28.964430
929 19:15:28.967686 Final TX Range 1 Vref 30
930 19:15:28.967819
931 19:15:28.967920 ==
932 19:15:28.971214 Dram Type= 6, Freq= 0, CH_0, rank 0
933 19:15:28.974140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 19:15:28.974242 ==
935 19:15:28.977618
936 19:15:28.977716
937 19:15:28.977785 TX Vref Scan disable
938 19:15:28.981042 == TX Byte 0 ==
939 19:15:28.984318 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
940 19:15:28.987983 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
941 19:15:28.991465 == TX Byte 1 ==
942 19:15:28.994338 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
943 19:15:28.997714 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
944 19:15:28.997825
945 19:15:29.001104 [DATLAT]
946 19:15:29.001210 Freq=800, CH0 RK0
947 19:15:29.001281
948 19:15:29.004697 DATLAT Default: 0xa
949 19:15:29.004796 0, 0xFFFF, sum = 0
950 19:15:29.008163 1, 0xFFFF, sum = 0
951 19:15:29.008258 2, 0xFFFF, sum = 0
952 19:15:29.010843 3, 0xFFFF, sum = 0
953 19:15:29.010965 4, 0xFFFF, sum = 0
954 19:15:29.014373 5, 0xFFFF, sum = 0
955 19:15:29.014471 6, 0xFFFF, sum = 0
956 19:15:29.017883 7, 0xFFFF, sum = 0
957 19:15:29.017986 8, 0xFFFF, sum = 0
958 19:15:29.021173 9, 0x0, sum = 1
959 19:15:29.021273 10, 0x0, sum = 2
960 19:15:29.024442 11, 0x0, sum = 3
961 19:15:29.024538 12, 0x0, sum = 4
962 19:15:29.027873 best_step = 10
963 19:15:29.027970
964 19:15:29.028039 ==
965 19:15:29.031046 Dram Type= 6, Freq= 0, CH_0, rank 0
966 19:15:29.034532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 19:15:29.034634 ==
968 19:15:29.038071 RX Vref Scan: 1
969 19:15:29.038172
970 19:15:29.038243 Set Vref Range= 32 -> 127
971 19:15:29.038306
972 19:15:29.041666 RX Vref 32 -> 127, step: 1
973 19:15:29.041765
974 19:15:29.044724 RX Delay -79 -> 252, step: 8
975 19:15:29.044819
976 19:15:29.047732 Set Vref, RX VrefLevel [Byte0]: 32
977 19:15:29.051554 [Byte1]: 32
978 19:15:29.051662
979 19:15:29.054833 Set Vref, RX VrefLevel [Byte0]: 33
980 19:15:29.057982 [Byte1]: 33
981 19:15:29.058098
982 19:15:29.061928 Set Vref, RX VrefLevel [Byte0]: 34
983 19:15:29.065099 [Byte1]: 34
984 19:15:29.069056
985 19:15:29.069197 Set Vref, RX VrefLevel [Byte0]: 35
986 19:15:29.071921 [Byte1]: 35
987 19:15:29.076931
988 19:15:29.077051 Set Vref, RX VrefLevel [Byte0]: 36
989 19:15:29.080224 [Byte1]: 36
990 19:15:29.084425
991 19:15:29.084550 Set Vref, RX VrefLevel [Byte0]: 37
992 19:15:29.087852 [Byte1]: 37
993 19:15:29.091750
994 19:15:29.091880 Set Vref, RX VrefLevel [Byte0]: 38
995 19:15:29.095320 [Byte1]: 38
996 19:15:29.098702
997 19:15:29.098803 Set Vref, RX VrefLevel [Byte0]: 39
998 19:15:29.102242 [Byte1]: 39
999 19:15:29.106559
1000 19:15:29.106669 Set Vref, RX VrefLevel [Byte0]: 40
1001 19:15:29.109945 [Byte1]: 40
1002 19:15:29.114409
1003 19:15:29.114519 Set Vref, RX VrefLevel [Byte0]: 41
1004 19:15:29.117131 [Byte1]: 41
1005 19:15:29.121355
1006 19:15:29.121461 Set Vref, RX VrefLevel [Byte0]: 42
1007 19:15:29.124982 [Byte1]: 42
1008 19:15:29.129046
1009 19:15:29.129154 Set Vref, RX VrefLevel [Byte0]: 43
1010 19:15:29.132505 [Byte1]: 43
1011 19:15:29.136535
1012 19:15:29.136642 Set Vref, RX VrefLevel [Byte0]: 44
1013 19:15:29.140124 [Byte1]: 44
1014 19:15:29.144282
1015 19:15:29.144441 Set Vref, RX VrefLevel [Byte0]: 45
1016 19:15:29.147635 [Byte1]: 45
1017 19:15:29.151595
1018 19:15:29.151736 Set Vref, RX VrefLevel [Byte0]: 46
1019 19:15:29.155238 [Byte1]: 46
1020 19:15:29.159447
1021 19:15:29.159570 Set Vref, RX VrefLevel [Byte0]: 47
1022 19:15:29.162393 [Byte1]: 47
1023 19:15:29.166783
1024 19:15:29.166905 Set Vref, RX VrefLevel [Byte0]: 48
1025 19:15:29.169810 [Byte1]: 48
1026 19:15:29.174380
1027 19:15:29.174553 Set Vref, RX VrefLevel [Byte0]: 49
1028 19:15:29.177674 [Byte1]: 49
1029 19:15:29.181884
1030 19:15:29.182011 Set Vref, RX VrefLevel [Byte0]: 50
1031 19:15:29.184927 [Byte1]: 50
1032 19:15:29.189606
1033 19:15:29.189745 Set Vref, RX VrefLevel [Byte0]: 51
1034 19:15:29.193079 [Byte1]: 51
1035 19:15:29.197321
1036 19:15:29.197450 Set Vref, RX VrefLevel [Byte0]: 52
1037 19:15:29.200768 [Byte1]: 52
1038 19:15:29.204222
1039 19:15:29.204348 Set Vref, RX VrefLevel [Byte0]: 53
1040 19:15:29.207757 [Byte1]: 53
1041 19:15:29.211935
1042 19:15:29.212063 Set Vref, RX VrefLevel [Byte0]: 54
1043 19:15:29.215373 [Byte1]: 54
1044 19:15:29.220226
1045 19:15:29.220372 Set Vref, RX VrefLevel [Byte0]: 55
1046 19:15:29.223163 [Byte1]: 55
1047 19:15:29.227280
1048 19:15:29.227407 Set Vref, RX VrefLevel [Byte0]: 56
1049 19:15:29.230737 [Byte1]: 56
1050 19:15:29.234886
1051 19:15:29.235015 Set Vref, RX VrefLevel [Byte0]: 57
1052 19:15:29.237862 [Byte1]: 57
1053 19:15:29.242255
1054 19:15:29.242379 Set Vref, RX VrefLevel [Byte0]: 58
1055 19:15:29.245776 [Byte1]: 58
1056 19:15:29.249931
1057 19:15:29.250055 Set Vref, RX VrefLevel [Byte0]: 59
1058 19:15:29.253537 [Byte1]: 59
1059 19:15:29.257638
1060 19:15:29.257758 Set Vref, RX VrefLevel [Byte0]: 60
1061 19:15:29.260682 [Byte1]: 60
1062 19:15:29.264745
1063 19:15:29.264865 Set Vref, RX VrefLevel [Byte0]: 61
1064 19:15:29.268381 [Byte1]: 61
1065 19:15:29.272660
1066 19:15:29.272761 Set Vref, RX VrefLevel [Byte0]: 62
1067 19:15:29.275616 [Byte1]: 62
1068 19:15:29.280097
1069 19:15:29.280212 Set Vref, RX VrefLevel [Byte0]: 63
1070 19:15:29.283152 [Byte1]: 63
1071 19:15:29.287749
1072 19:15:29.287853 Set Vref, RX VrefLevel [Byte0]: 64
1073 19:15:29.291231 [Byte1]: 64
1074 19:15:29.295086
1075 19:15:29.295175 Set Vref, RX VrefLevel [Byte0]: 65
1076 19:15:29.298280 [Byte1]: 65
1077 19:15:29.302898
1078 19:15:29.303004 Set Vref, RX VrefLevel [Byte0]: 66
1079 19:15:29.306013 [Byte1]: 66
1080 19:15:29.309973
1081 19:15:29.310111 Set Vref, RX VrefLevel [Byte0]: 67
1082 19:15:29.313244 [Byte1]: 67
1083 19:15:29.318154
1084 19:15:29.318288 Set Vref, RX VrefLevel [Byte0]: 68
1085 19:15:29.320973 [Byte1]: 68
1086 19:15:29.325666
1087 19:15:29.325775 Set Vref, RX VrefLevel [Byte0]: 69
1088 19:15:29.328650 [Byte1]: 69
1089 19:15:29.332966
1090 19:15:29.333058 Set Vref, RX VrefLevel [Byte0]: 70
1091 19:15:29.336443 [Byte1]: 70
1092 19:15:29.340831
1093 19:15:29.340922 Set Vref, RX VrefLevel [Byte0]: 71
1094 19:15:29.343677 [Byte1]: 71
1095 19:15:29.348096
1096 19:15:29.348192 Set Vref, RX VrefLevel [Byte0]: 72
1097 19:15:29.351588 [Byte1]: 72
1098 19:15:29.355892
1099 19:15:29.355987 Set Vref, RX VrefLevel [Byte0]: 73
1100 19:15:29.358802 [Byte1]: 73
1101 19:15:29.362997
1102 19:15:29.363094 Set Vref, RX VrefLevel [Byte0]: 74
1103 19:15:29.366377 [Byte1]: 74
1104 19:15:29.370879
1105 19:15:29.370972 Set Vref, RX VrefLevel [Byte0]: 75
1106 19:15:29.374349 [Byte1]: 75
1107 19:15:29.378514
1108 19:15:29.378619 Set Vref, RX VrefLevel [Byte0]: 76
1109 19:15:29.381743 [Byte1]: 76
1110 19:15:29.385725
1111 19:15:29.385817 Set Vref, RX VrefLevel [Byte0]: 77
1112 19:15:29.389204 [Byte1]: 77
1113 19:15:29.393391
1114 19:15:29.393487 Final RX Vref Byte 0 = 58 to rank0
1115 19:15:29.396608 Final RX Vref Byte 1 = 57 to rank0
1116 19:15:29.399963 Final RX Vref Byte 0 = 58 to rank1
1117 19:15:29.403271 Final RX Vref Byte 1 = 57 to rank1==
1118 19:15:29.406744 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 19:15:29.410147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 19:15:29.413760 ==
1121 19:15:29.413854 DQS Delay:
1122 19:15:29.413919 DQS0 = 0, DQS1 = 0
1123 19:15:29.417061 DQM Delay:
1124 19:15:29.417138 DQM0 = 92, DQM1 = 84
1125 19:15:29.419839 DQ Delay:
1126 19:15:29.423553 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1127 19:15:29.423644 DQ4 =96, DQ5 =80, DQ6 =96, DQ7 =100
1128 19:15:29.426750 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1129 19:15:29.430212 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1130 19:15:29.433420
1131 19:15:29.433516
1132 19:15:29.440019 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f45, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
1133 19:15:29.443423 CH0 RK0: MR19=606, MR18=4F45
1134 19:15:29.449850 CH0_RK0: MR19=0x606, MR18=0x4F45, DQSOSC=390, MR23=63, INC=97, DEC=64
1135 19:15:29.449959
1136 19:15:29.453353 ----->DramcWriteLeveling(PI) begin...
1137 19:15:29.453476 ==
1138 19:15:29.456931 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 19:15:29.460465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 19:15:29.460556 ==
1141 19:15:29.463233 Write leveling (Byte 0): 32 => 32
1142 19:15:29.466876 Write leveling (Byte 1): 31 => 31
1143 19:15:29.470452 DramcWriteLeveling(PI) end<-----
1144 19:15:29.470547
1145 19:15:29.470611 ==
1146 19:15:29.473282 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 19:15:29.476961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 19:15:29.477113 ==
1149 19:15:29.480565 [Gating] SW mode calibration
1150 19:15:29.527344 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 19:15:29.528143 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 19:15:29.528451 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 19:15:29.528555 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1154 19:15:29.528647 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1155 19:15:29.528717 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 19:15:29.528792 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 19:15:29.528868 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 19:15:29.528953 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 19:15:29.529053 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 19:15:29.551232 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 19:15:29.551901 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 19:15:29.552052 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 19:15:29.552146 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 19:15:29.552404 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 19:15:29.555854 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 19:15:29.559223 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 19:15:29.562111 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 19:15:29.566058 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 19:15:29.572070 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 19:15:29.575506 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1171 19:15:29.579132 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 19:15:29.585512 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 19:15:29.589189 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 19:15:29.591947 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 19:15:29.598967 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 19:15:29.602380 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 19:15:29.605358 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 19:15:29.612300 0 9 8 | B1->B0 | 3131 2e2e | 0 0 | (0 0) (0 0)
1179 19:15:29.615667 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 19:15:29.619055 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 19:15:29.625482 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 19:15:29.628765 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 19:15:29.632597 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 19:15:29.638913 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 19:15:29.642435 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1186 19:15:29.646026 0 10 8 | B1->B0 | 2727 2424 | 0 0 | (0 0) (1 0)
1187 19:15:29.648767 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 19:15:29.656307 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 19:15:29.660328 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 19:15:29.664273 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 19:15:29.667618 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 19:15:29.671688 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 19:15:29.678116 0 11 4 | B1->B0 | 2828 2626 | 0 1 | (0 0) (0 0)
1194 19:15:29.681183 0 11 8 | B1->B0 | 3c3b 3737 | 1 1 | (0 0) (0 0)
1195 19:15:29.684760 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 19:15:29.691881 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 19:15:29.695436 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 19:15:29.698374 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 19:15:29.701691 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 19:15:29.708674 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 19:15:29.711329 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 19:15:29.714975 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 19:15:29.722040 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1204 19:15:29.724865 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 19:15:29.728194 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 19:15:29.735247 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 19:15:29.738793 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 19:15:29.742141 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 19:15:29.748609 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 19:15:29.751844 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 19:15:29.754981 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 19:15:29.761914 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 19:15:29.765517 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 19:15:29.768382 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 19:15:29.775390 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 19:15:29.778847 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 19:15:29.782273 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 19:15:29.785034 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1219 19:15:29.791932 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1220 19:15:29.795407 Total UI for P1: 0, mck2ui 16
1221 19:15:29.798754 best dqsien dly found for B1: ( 0, 14, 8)
1222 19:15:29.801853 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 19:15:29.805006 Total UI for P1: 0, mck2ui 16
1224 19:15:29.808764 best dqsien dly found for B0: ( 0, 14, 10)
1225 19:15:29.811650 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1226 19:15:29.815224 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1227 19:15:29.815369
1228 19:15:29.818700 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1229 19:15:29.821830 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1230 19:15:29.825319 [Gating] SW calibration Done
1231 19:15:29.825443 ==
1232 19:15:29.828636 Dram Type= 6, Freq= 0, CH_0, rank 1
1233 19:15:29.831953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1234 19:15:29.835496 ==
1235 19:15:29.835593 RX Vref Scan: 0
1236 19:15:29.835660
1237 19:15:29.838358 RX Vref 0 -> 0, step: 1
1238 19:15:29.838461
1239 19:15:29.841931 RX Delay -130 -> 252, step: 16
1240 19:15:29.845495 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1241 19:15:29.848246 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1242 19:15:29.851744 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1243 19:15:29.855122 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1244 19:15:29.861793 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1245 19:15:29.865131 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1246 19:15:29.868327 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1247 19:15:29.871625 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1248 19:15:29.874984 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1249 19:15:29.881771 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1250 19:15:29.885316 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1251 19:15:29.888621 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1252 19:15:29.891484 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1253 19:15:29.898496 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1254 19:15:29.901382 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1255 19:15:29.904931 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1256 19:15:29.905103 ==
1257 19:15:29.908576 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 19:15:29.911317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1259 19:15:29.911467 ==
1260 19:15:29.914724 DQS Delay:
1261 19:15:29.914925 DQS0 = 0, DQS1 = 0
1262 19:15:29.915027 DQM Delay:
1263 19:15:29.918065 DQM0 = 92, DQM1 = 84
1264 19:15:29.918283 DQ Delay:
1265 19:15:29.921505 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1266 19:15:29.924881 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1267 19:15:29.928319 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1268 19:15:29.931383 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
1269 19:15:29.931514
1270 19:15:29.931614
1271 19:15:29.931706 ==
1272 19:15:29.935054 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 19:15:29.941540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 19:15:29.941686 ==
1275 19:15:29.941758
1276 19:15:29.941820
1277 19:15:29.941878 TX Vref Scan disable
1278 19:15:29.945728 == TX Byte 0 ==
1279 19:15:29.948362 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1280 19:15:29.951977 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1281 19:15:29.955673 == TX Byte 1 ==
1282 19:15:29.958505 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1283 19:15:29.961922 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1284 19:15:29.965383 ==
1285 19:15:29.968914 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 19:15:29.972259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 19:15:29.972408 ==
1288 19:15:29.984595 TX Vref=22, minBit 8, minWin=27, winSum=450
1289 19:15:29.987678 TX Vref=24, minBit 8, minWin=28, winSum=456
1290 19:15:29.991328 TX Vref=26, minBit 7, minWin=28, winSum=456
1291 19:15:29.994550 TX Vref=28, minBit 1, minWin=28, winSum=458
1292 19:15:29.998071 TX Vref=30, minBit 7, minWin=28, winSum=460
1293 19:15:30.001118 TX Vref=32, minBit 2, minWin=28, winSum=456
1294 19:15:30.007682 [TxChooseVref] Worse bit 7, Min win 28, Win sum 460, Final Vref 30
1295 19:15:30.007875
1296 19:15:30.011401 Final TX Range 1 Vref 30
1297 19:15:30.011579
1298 19:15:30.011677 ==
1299 19:15:30.014399 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 19:15:30.017407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 19:15:30.017521 ==
1302 19:15:30.017589
1303 19:15:30.020898
1304 19:15:30.020992 TX Vref Scan disable
1305 19:15:30.024420 == TX Byte 0 ==
1306 19:15:30.027330 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1307 19:15:30.031109 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1308 19:15:30.034086 == TX Byte 1 ==
1309 19:15:30.037702 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1310 19:15:30.041059 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1311 19:15:30.043939
1312 19:15:30.044056 [DATLAT]
1313 19:15:30.044124 Freq=800, CH0 RK1
1314 19:15:30.044187
1315 19:15:30.047415 DATLAT Default: 0xa
1316 19:15:30.047520 0, 0xFFFF, sum = 0
1317 19:15:30.050680 1, 0xFFFF, sum = 0
1318 19:15:30.050776 2, 0xFFFF, sum = 0
1319 19:15:30.054435 3, 0xFFFF, sum = 0
1320 19:15:30.054533 4, 0xFFFF, sum = 0
1321 19:15:30.057646 5, 0xFFFF, sum = 0
1322 19:15:30.060831 6, 0xFFFF, sum = 0
1323 19:15:30.060959 7, 0xFFFF, sum = 0
1324 19:15:30.064219 8, 0xFFFF, sum = 0
1325 19:15:30.064316 9, 0x0, sum = 1
1326 19:15:30.064418 10, 0x0, sum = 2
1327 19:15:30.067826 11, 0x0, sum = 3
1328 19:15:30.067957 12, 0x0, sum = 4
1329 19:15:30.070780 best_step = 10
1330 19:15:30.070898
1331 19:15:30.071001 ==
1332 19:15:30.074397 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 19:15:30.077943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 19:15:30.078092 ==
1335 19:15:30.080947 RX Vref Scan: 0
1336 19:15:30.081076
1337 19:15:30.081194 RX Vref 0 -> 0, step: 1
1338 19:15:30.081302
1339 19:15:30.084592 RX Delay -79 -> 252, step: 8
1340 19:15:30.090757 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1341 19:15:30.094153 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1342 19:15:30.097616 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1343 19:15:30.101452 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1344 19:15:30.104106 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1345 19:15:30.111406 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1346 19:15:30.114315 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1347 19:15:30.118039 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1348 19:15:30.120831 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1349 19:15:30.124255 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1350 19:15:30.131105 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1351 19:15:30.134602 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1352 19:15:30.137471 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1353 19:15:30.141178 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1354 19:15:30.144514 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1355 19:15:30.150933 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1356 19:15:30.151069 ==
1357 19:15:30.154556 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 19:15:30.158148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 19:15:30.158240 ==
1360 19:15:30.158305 DQS Delay:
1361 19:15:30.161010 DQS0 = 0, DQS1 = 0
1362 19:15:30.161094 DQM Delay:
1363 19:15:30.164288 DQM0 = 93, DQM1 = 82
1364 19:15:30.164396 DQ Delay:
1365 19:15:30.168185 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1366 19:15:30.171325 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1367 19:15:30.174599 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1368 19:15:30.177690 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1369 19:15:30.177796
1370 19:15:30.177865
1371 19:15:30.184287 [DQSOSCAuto] RK1, (LSB)MR18= 0x4616, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1372 19:15:30.187733 CH0 RK1: MR19=606, MR18=4616
1373 19:15:30.194478 CH0_RK1: MR19=0x606, MR18=0x4616, DQSOSC=392, MR23=63, INC=96, DEC=64
1374 19:15:30.198008 [RxdqsGatingPostProcess] freq 800
1375 19:15:30.204363 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1376 19:15:30.204498 Pre-setting of DQS Precalculation
1377 19:15:30.211364 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1378 19:15:30.211481 ==
1379 19:15:30.214749 Dram Type= 6, Freq= 0, CH_1, rank 0
1380 19:15:30.218252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 19:15:30.218424 ==
1382 19:15:30.224519 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1383 19:15:30.231687 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1384 19:15:30.239130 [CA 0] Center 36 (6~67) winsize 62
1385 19:15:30.242903 [CA 1] Center 36 (6~67) winsize 62
1386 19:15:30.245925 [CA 2] Center 35 (4~66) winsize 63
1387 19:15:30.249539 [CA 3] Center 34 (4~65) winsize 62
1388 19:15:30.252552 [CA 4] Center 34 (4~65) winsize 62
1389 19:15:30.256197 [CA 5] Center 34 (4~65) winsize 62
1390 19:15:30.256333
1391 19:15:30.259131 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1392 19:15:30.259238
1393 19:15:30.262948 [CATrainingPosCal] consider 1 rank data
1394 19:15:30.265788 u2DelayCellTimex100 = 270/100 ps
1395 19:15:30.269441 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 19:15:30.273024 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1397 19:15:30.276314 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1398 19:15:30.282959 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1399 19:15:30.286577 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1400 19:15:30.289509 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 19:15:30.289599
1402 19:15:30.293209 CA PerBit enable=1, Macro0, CA PI delay=34
1403 19:15:30.293298
1404 19:15:30.295939 [CBTSetCACLKResult] CA Dly = 34
1405 19:15:30.296023 CS Dly: 5 (0~36)
1406 19:15:30.296089 ==
1407 19:15:30.299646 Dram Type= 6, Freq= 0, CH_1, rank 1
1408 19:15:30.306120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1409 19:15:30.306230 ==
1410 19:15:30.309333 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1411 19:15:30.316128 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1412 19:15:30.325890 [CA 0] Center 37 (6~68) winsize 63
1413 19:15:30.329812 [CA 1] Center 36 (6~67) winsize 62
1414 19:15:30.333455 [CA 2] Center 35 (5~66) winsize 62
1415 19:15:30.337338 [CA 3] Center 35 (5~65) winsize 61
1416 19:15:30.340798 [CA 4] Center 35 (5~66) winsize 62
1417 19:15:30.340901 [CA 5] Center 34 (4~65) winsize 62
1418 19:15:30.344347
1419 19:15:30.348494 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1420 19:15:30.348593
1421 19:15:30.352109 [CATrainingPosCal] consider 2 rank data
1422 19:15:30.352199 u2DelayCellTimex100 = 270/100 ps
1423 19:15:30.355548 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 19:15:30.358952 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1425 19:15:30.365477 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1426 19:15:30.368829 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1427 19:15:30.372410 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1428 19:15:30.375401 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 19:15:30.375494
1430 19:15:30.378917 CA PerBit enable=1, Macro0, CA PI delay=34
1431 19:15:30.379004
1432 19:15:30.382185 [CBTSetCACLKResult] CA Dly = 34
1433 19:15:30.382272 CS Dly: 6 (0~38)
1434 19:15:30.382339
1435 19:15:30.385873 ----->DramcWriteLeveling(PI) begin...
1436 19:15:30.388830 ==
1437 19:15:30.388920 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 19:15:30.395435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 19:15:30.395533 ==
1440 19:15:30.398996 Write leveling (Byte 0): 25 => 25
1441 19:15:30.402643 Write leveling (Byte 1): 25 => 25
1442 19:15:30.402734 DramcWriteLeveling(PI) end<-----
1443 19:15:30.405457
1444 19:15:30.405542 ==
1445 19:15:30.409061 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 19:15:30.412075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 19:15:30.412219 ==
1448 19:15:30.415772 [Gating] SW mode calibration
1449 19:15:30.422165 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1450 19:15:30.425418 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1451 19:15:30.432519 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1452 19:15:30.435990 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1453 19:15:30.438801 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 19:15:30.445907 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 19:15:30.449085 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 19:15:30.452330 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 19:15:30.458818 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 19:15:30.462131 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 19:15:30.465993 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 19:15:30.472608 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 19:15:30.475618 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 19:15:30.479189 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 19:15:30.485641 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 19:15:30.489148 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 19:15:30.491914 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 19:15:30.495644 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 19:15:30.502459 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1468 19:15:30.505325 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1469 19:15:30.508916 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1470 19:15:30.515457 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 19:15:30.519338 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 19:15:30.522218 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 19:15:30.529497 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 19:15:30.532452 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 19:15:30.535856 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 19:15:30.542672 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 19:15:30.546210 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1478 19:15:30.549076 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 19:15:30.555650 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 19:15:30.559363 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 19:15:30.562595 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 19:15:30.566092 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 19:15:30.572491 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 19:15:30.575859 0 10 4 | B1->B0 | 3030 2d2d | 1 1 | (1 0) (1 0)
1485 19:15:30.579106 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1486 19:15:30.586249 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 19:15:30.589565 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 19:15:30.592378 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 19:15:30.599694 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 19:15:30.602657 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 19:15:30.606352 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 19:15:30.612960 0 11 4 | B1->B0 | 2727 3636 | 0 0 | (0 0) (0 0)
1493 19:15:30.615761 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
1494 19:15:30.619351 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 19:15:30.626010 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 19:15:30.629614 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 19:15:30.632714 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 19:15:30.636391 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 19:15:30.643045 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 19:15:30.645886 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1501 19:15:30.649467 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 19:15:30.656075 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 19:15:30.659463 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 19:15:30.662972 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 19:15:30.669969 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 19:15:30.672612 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 19:15:30.676203 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 19:15:30.683367 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 19:15:30.686013 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 19:15:30.689579 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 19:15:30.696255 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 19:15:30.699516 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 19:15:30.702793 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 19:15:30.709416 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 19:15:30.713002 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 19:15:30.716658 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1517 19:15:30.719508 Total UI for P1: 0, mck2ui 16
1518 19:15:30.723380 best dqsien dly found for B1: ( 0, 14, 2)
1519 19:15:30.726151 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 19:15:30.729959 Total UI for P1: 0, mck2ui 16
1521 19:15:30.732906 best dqsien dly found for B0: ( 0, 14, 4)
1522 19:15:30.736494 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1523 19:15:30.739499 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1524 19:15:30.743156
1525 19:15:30.746133 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1526 19:15:30.749687 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1527 19:15:30.753262 [Gating] SW calibration Done
1528 19:15:30.753352 ==
1529 19:15:30.756207 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 19:15:30.759902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 19:15:30.759980 ==
1532 19:15:30.760041 RX Vref Scan: 0
1533 19:15:30.760100
1534 19:15:30.763230 RX Vref 0 -> 0, step: 1
1535 19:15:30.763304
1536 19:15:30.766421 RX Delay -130 -> 252, step: 16
1537 19:15:30.769774 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1538 19:15:30.773189 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1539 19:15:30.780052 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1540 19:15:30.783259 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1541 19:15:30.786662 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1542 19:15:30.789620 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1543 19:15:30.793264 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1544 19:15:30.796761 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1545 19:15:30.803463 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1546 19:15:30.806376 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1547 19:15:30.809690 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1548 19:15:30.813356 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1549 19:15:30.819692 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1550 19:15:30.823380 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1551 19:15:30.826642 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1552 19:15:30.830297 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1553 19:15:30.830417 ==
1554 19:15:30.833162 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 19:15:30.836748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 19:15:30.839711 ==
1557 19:15:30.839853 DQS Delay:
1558 19:15:30.839951 DQS0 = 0, DQS1 = 0
1559 19:15:30.843387 DQM Delay:
1560 19:15:30.843490 DQM0 = 93, DQM1 = 87
1561 19:15:30.843608 DQ Delay:
1562 19:15:30.846384 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1563 19:15:30.850129 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1564 19:15:30.853132 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1565 19:15:30.856607 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1566 19:15:30.856712
1567 19:15:30.860147
1568 19:15:30.860231 ==
1569 19:15:30.863133 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 19:15:30.866929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 19:15:30.867018 ==
1572 19:15:30.867083
1573 19:15:30.867143
1574 19:15:30.869743 TX Vref Scan disable
1575 19:15:30.869827 == TX Byte 0 ==
1576 19:15:30.876575 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1577 19:15:30.879863 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1578 19:15:30.879980 == TX Byte 1 ==
1579 19:15:30.886150 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1580 19:15:30.889874 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1581 19:15:30.889971 ==
1582 19:15:30.893370 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 19:15:30.896725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 19:15:30.896902 ==
1585 19:15:30.909792 TX Vref=22, minBit 0, minWin=26, winSum=430
1586 19:15:30.913504 TX Vref=24, minBit 0, minWin=27, winSum=437
1587 19:15:30.916379 TX Vref=26, minBit 1, minWin=27, winSum=441
1588 19:15:30.920010 TX Vref=28, minBit 1, minWin=27, winSum=446
1589 19:15:30.923030 TX Vref=30, minBit 3, minWin=26, winSum=443
1590 19:15:30.926420 TX Vref=32, minBit 0, minWin=26, winSum=437
1591 19:15:30.933027 [TxChooseVref] Worse bit 1, Min win 27, Win sum 446, Final Vref 28
1592 19:15:30.933140
1593 19:15:30.936690 Final TX Range 1 Vref 28
1594 19:15:30.936781
1595 19:15:30.936847 ==
1596 19:15:30.939986 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 19:15:30.943146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 19:15:30.943268 ==
1599 19:15:30.943349
1600 19:15:30.946585
1601 19:15:30.946676 TX Vref Scan disable
1602 19:15:30.949728 == TX Byte 0 ==
1603 19:15:30.953455 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1604 19:15:30.956105 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1605 19:15:30.959721 == TX Byte 1 ==
1606 19:15:30.962954 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1607 19:15:30.966755 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1608 19:15:30.969627
1609 19:15:30.969741 [DATLAT]
1610 19:15:30.969810 Freq=800, CH1 RK0
1611 19:15:30.969874
1612 19:15:30.973172 DATLAT Default: 0xa
1613 19:15:30.973261 0, 0xFFFF, sum = 0
1614 19:15:30.976203 1, 0xFFFF, sum = 0
1615 19:15:30.976319 2, 0xFFFF, sum = 0
1616 19:15:30.979778 3, 0xFFFF, sum = 0
1617 19:15:30.979871 4, 0xFFFF, sum = 0
1618 19:15:30.983259 5, 0xFFFF, sum = 0
1619 19:15:30.983351 6, 0xFFFF, sum = 0
1620 19:15:30.986533 7, 0xFFFF, sum = 0
1621 19:15:30.989882 8, 0xFFFF, sum = 0
1622 19:15:30.989978 9, 0x0, sum = 1
1623 19:15:30.990046 10, 0x0, sum = 2
1624 19:15:30.993264 11, 0x0, sum = 3
1625 19:15:30.993354 12, 0x0, sum = 4
1626 19:15:30.996539 best_step = 10
1627 19:15:30.996626
1628 19:15:30.996693 ==
1629 19:15:31.000070 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 19:15:31.003562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 19:15:31.003654 ==
1632 19:15:31.006196 RX Vref Scan: 1
1633 19:15:31.006282
1634 19:15:31.006349 Set Vref Range= 32 -> 127
1635 19:15:31.006412
1636 19:15:31.010024 RX Vref 32 -> 127, step: 1
1637 19:15:31.010111
1638 19:15:31.013160 RX Delay -79 -> 252, step: 8
1639 19:15:31.013262
1640 19:15:31.016786 Set Vref, RX VrefLevel [Byte0]: 32
1641 19:15:31.019767 [Byte1]: 32
1642 19:15:31.019856
1643 19:15:31.023447 Set Vref, RX VrefLevel [Byte0]: 33
1644 19:15:31.026385 [Byte1]: 33
1645 19:15:31.029954
1646 19:15:31.030042 Set Vref, RX VrefLevel [Byte0]: 34
1647 19:15:31.033611 [Byte1]: 34
1648 19:15:31.037350
1649 19:15:31.037440 Set Vref, RX VrefLevel [Byte0]: 35
1650 19:15:31.040967 [Byte1]: 35
1651 19:15:31.045024
1652 19:15:31.045116 Set Vref, RX VrefLevel [Byte0]: 36
1653 19:15:31.048323 [Byte1]: 36
1654 19:15:31.052756
1655 19:15:31.052853 Set Vref, RX VrefLevel [Byte0]: 37
1656 19:15:31.055615 [Byte1]: 37
1657 19:15:31.059889
1658 19:15:31.059980 Set Vref, RX VrefLevel [Byte0]: 38
1659 19:15:31.063283 [Byte1]: 38
1660 19:15:31.067170
1661 19:15:31.067264 Set Vref, RX VrefLevel [Byte0]: 39
1662 19:15:31.070669 [Byte1]: 39
1663 19:15:31.075262
1664 19:15:31.075355 Set Vref, RX VrefLevel [Byte0]: 40
1665 19:15:31.078854 [Byte1]: 40
1666 19:15:31.082414
1667 19:15:31.082498 Set Vref, RX VrefLevel [Byte0]: 41
1668 19:15:31.085941 [Byte1]: 41
1669 19:15:31.090258
1670 19:15:31.090349 Set Vref, RX VrefLevel [Byte0]: 42
1671 19:15:31.093740 [Byte1]: 42
1672 19:15:31.098018
1673 19:15:31.098110 Set Vref, RX VrefLevel [Byte0]: 43
1674 19:15:31.100867 [Byte1]: 43
1675 19:15:31.105051
1676 19:15:31.105141 Set Vref, RX VrefLevel [Byte0]: 44
1677 19:15:31.108499 [Byte1]: 44
1678 19:15:31.112764
1679 19:15:31.112852 Set Vref, RX VrefLevel [Byte0]: 45
1680 19:15:31.116529 [Byte1]: 45
1681 19:15:31.120615
1682 19:15:31.120713 Set Vref, RX VrefLevel [Byte0]: 46
1683 19:15:31.123951 [Byte1]: 46
1684 19:15:31.127639
1685 19:15:31.127723 Set Vref, RX VrefLevel [Byte0]: 47
1686 19:15:31.131361 [Byte1]: 47
1687 19:15:31.135924
1688 19:15:31.136010 Set Vref, RX VrefLevel [Byte0]: 48
1689 19:15:31.138799 [Byte1]: 48
1690 19:15:31.143177
1691 19:15:31.143268 Set Vref, RX VrefLevel [Byte0]: 49
1692 19:15:31.146010 [Byte1]: 49
1693 19:15:31.150475
1694 19:15:31.150584 Set Vref, RX VrefLevel [Byte0]: 50
1695 19:15:31.153770 [Byte1]: 50
1696 19:15:31.158567
1697 19:15:31.158673 Set Vref, RX VrefLevel [Byte0]: 51
1698 19:15:31.161372 [Byte1]: 51
1699 19:15:31.165822
1700 19:15:31.165928 Set Vref, RX VrefLevel [Byte0]: 52
1701 19:15:31.169431 [Byte1]: 52
1702 19:15:31.172936
1703 19:15:31.173030 Set Vref, RX VrefLevel [Byte0]: 53
1704 19:15:31.176632 [Byte1]: 53
1705 19:15:31.181063
1706 19:15:31.181153 Set Vref, RX VrefLevel [Byte0]: 54
1707 19:15:31.183792 [Byte1]: 54
1708 19:15:31.188027
1709 19:15:31.188122 Set Vref, RX VrefLevel [Byte0]: 55
1710 19:15:31.191488 [Byte1]: 55
1711 19:15:31.196189
1712 19:15:31.196292 Set Vref, RX VrefLevel [Byte0]: 56
1713 19:15:31.202112 [Byte1]: 56
1714 19:15:31.202237
1715 19:15:31.205621 Set Vref, RX VrefLevel [Byte0]: 57
1716 19:15:31.209309 [Byte1]: 57
1717 19:15:31.209419
1718 19:15:31.212175 Set Vref, RX VrefLevel [Byte0]: 58
1719 19:15:31.215778 [Byte1]: 58
1720 19:15:31.215868
1721 19:15:31.218649 Set Vref, RX VrefLevel [Byte0]: 59
1722 19:15:31.222027 [Byte1]: 59
1723 19:15:31.225699
1724 19:15:31.225819 Set Vref, RX VrefLevel [Byte0]: 60
1725 19:15:31.229290 [Byte1]: 60
1726 19:15:31.233451
1727 19:15:31.233544 Set Vref, RX VrefLevel [Byte0]: 61
1728 19:15:31.237216 [Byte1]: 61
1729 19:15:31.240837
1730 19:15:31.240921 Set Vref, RX VrefLevel [Byte0]: 62
1731 19:15:31.244475 [Byte1]: 62
1732 19:15:31.248814
1733 19:15:31.248898 Set Vref, RX VrefLevel [Byte0]: 63
1734 19:15:31.252308 [Byte1]: 63
1735 19:15:31.256260
1736 19:15:31.256385 Set Vref, RX VrefLevel [Byte0]: 64
1737 19:15:31.259319 [Byte1]: 64
1738 19:15:31.263791
1739 19:15:31.263935 Set Vref, RX VrefLevel [Byte0]: 65
1740 19:15:31.267340 [Byte1]: 65
1741 19:15:31.271138
1742 19:15:31.271278 Set Vref, RX VrefLevel [Byte0]: 66
1743 19:15:31.274306 [Byte1]: 66
1744 19:15:31.278587
1745 19:15:31.278699 Set Vref, RX VrefLevel [Byte0]: 67
1746 19:15:31.282398 [Byte1]: 67
1747 19:15:31.286094
1748 19:15:31.286185 Set Vref, RX VrefLevel [Byte0]: 68
1749 19:15:31.290024 [Byte1]: 68
1750 19:15:31.293671
1751 19:15:31.293790 Set Vref, RX VrefLevel [Byte0]: 69
1752 19:15:31.297358 [Byte1]: 69
1753 19:15:31.301581
1754 19:15:31.301683 Set Vref, RX VrefLevel [Byte0]: 70
1755 19:15:31.304497 [Byte1]: 70
1756 19:15:31.308758
1757 19:15:31.308866 Set Vref, RX VrefLevel [Byte0]: 71
1758 19:15:31.312216 [Byte1]: 71
1759 19:15:31.316453
1760 19:15:31.316579 Set Vref, RX VrefLevel [Byte0]: 72
1761 19:15:31.319846 [Byte1]: 72
1762 19:15:31.323942
1763 19:15:31.324082 Final RX Vref Byte 0 = 59 to rank0
1764 19:15:31.327344 Final RX Vref Byte 1 = 56 to rank0
1765 19:15:31.330759 Final RX Vref Byte 0 = 59 to rank1
1766 19:15:31.334259 Final RX Vref Byte 1 = 56 to rank1==
1767 19:15:31.337625 Dram Type= 6, Freq= 0, CH_1, rank 0
1768 19:15:31.343750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1769 19:15:31.343899 ==
1770 19:15:31.344004 DQS Delay:
1771 19:15:31.344096 DQS0 = 0, DQS1 = 0
1772 19:15:31.347486 DQM Delay:
1773 19:15:31.347591 DQM0 = 95, DQM1 = 90
1774 19:15:31.350561 DQ Delay:
1775 19:15:31.354181 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1776 19:15:31.357171 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
1777 19:15:31.360993 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1778 19:15:31.363876 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1779 19:15:31.363984
1780 19:15:31.364076
1781 19:15:31.370656 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b47, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
1782 19:15:31.374077 CH1 RK0: MR19=606, MR18=2B47
1783 19:15:31.380377 CH1_RK0: MR19=0x606, MR18=0x2B47, DQSOSC=392, MR23=63, INC=96, DEC=64
1784 19:15:31.380498
1785 19:15:31.384171 ----->DramcWriteLeveling(PI) begin...
1786 19:15:31.384292 ==
1787 19:15:31.387207 Dram Type= 6, Freq= 0, CH_1, rank 1
1788 19:15:31.390942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1789 19:15:31.391049 ==
1790 19:15:31.394003 Write leveling (Byte 0): 26 => 26
1791 19:15:31.397135 Write leveling (Byte 1): 26 => 26
1792 19:15:31.400138 DramcWriteLeveling(PI) end<-----
1793 19:15:31.400272
1794 19:15:31.400398 ==
1795 19:15:31.403910 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 19:15:31.406846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1797 19:15:31.406972 ==
1798 19:15:31.410648 [Gating] SW mode calibration
1799 19:15:31.417199 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1800 19:15:31.423517 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1801 19:15:31.426949 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1802 19:15:31.434075 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1803 19:15:31.437336 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1804 19:15:31.440179 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 19:15:31.443548 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 19:15:31.450187 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 19:15:31.453508 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 19:15:31.457071 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 19:15:31.464003 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 19:15:31.466926 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 19:15:31.470637 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 19:15:31.477342 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 19:15:31.480737 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 19:15:31.483597 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 19:15:31.490183 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 19:15:31.493528 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 19:15:31.497203 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1818 19:15:31.503748 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1819 19:15:31.507342 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 19:15:31.510829 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 19:15:31.517332 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 19:15:31.520140 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 19:15:31.524043 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 19:15:31.530644 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 19:15:31.533634 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 19:15:31.537509 0 9 4 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
1827 19:15:31.540289 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1828 19:15:31.546816 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 19:15:31.550153 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 19:15:31.553739 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 19:15:31.560324 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 19:15:31.563726 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 19:15:31.567179 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 19:15:31.573941 0 10 4 | B1->B0 | 2626 3030 | 0 0 | (1 0) (0 1)
1835 19:15:31.577200 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 19:15:31.580070 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 19:15:31.587248 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 19:15:31.590170 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 19:15:31.593723 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 19:15:31.600346 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 19:15:31.603634 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 19:15:31.607047 0 11 4 | B1->B0 | 3c3c 3030 | 0 1 | (1 1) (0 0)
1843 19:15:31.613364 0 11 8 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
1844 19:15:31.617012 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 19:15:31.620737 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 19:15:31.626890 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 19:15:31.630582 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 19:15:31.634133 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 19:15:31.637155 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1850 19:15:31.643913 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1851 19:15:31.647596 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 19:15:31.651035 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 19:15:31.657146 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 19:15:31.660544 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 19:15:31.663883 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 19:15:31.670668 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 19:15:31.673971 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 19:15:31.677486 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 19:15:31.684464 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 19:15:31.687598 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 19:15:31.691178 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 19:15:31.697691 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 19:15:31.700656 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 19:15:31.704094 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 19:15:31.707740 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 19:15:31.713856 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1867 19:15:31.717417 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 19:15:31.720667 Total UI for P1: 0, mck2ui 16
1869 19:15:31.724260 best dqsien dly found for B0: ( 0, 14, 4)
1870 19:15:31.727235 Total UI for P1: 0, mck2ui 16
1871 19:15:31.730918 best dqsien dly found for B1: ( 0, 14, 4)
1872 19:15:31.733872 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1873 19:15:31.737667 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1874 19:15:31.737751
1875 19:15:31.741159 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1876 19:15:31.744182 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1877 19:15:31.747892 [Gating] SW calibration Done
1878 19:15:31.747978 ==
1879 19:15:31.750700 Dram Type= 6, Freq= 0, CH_1, rank 1
1880 19:15:31.754516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1881 19:15:31.757456 ==
1882 19:15:31.757569 RX Vref Scan: 0
1883 19:15:31.757671
1884 19:15:31.761022 RX Vref 0 -> 0, step: 1
1885 19:15:31.761107
1886 19:15:31.764617 RX Delay -130 -> 252, step: 16
1887 19:15:31.767644 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1888 19:15:31.771099 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1889 19:15:31.774358 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1890 19:15:31.777698 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1891 19:15:31.784107 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1892 19:15:31.787959 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1893 19:15:31.790891 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1894 19:15:31.794451 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1895 19:15:31.797302 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1896 19:15:31.800601 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1897 19:15:31.807385 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1898 19:15:31.811198 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1899 19:15:31.814027 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1900 19:15:31.817696 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1901 19:15:31.824102 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1902 19:15:31.827798 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1903 19:15:31.827928 ==
1904 19:15:31.831116 Dram Type= 6, Freq= 0, CH_1, rank 1
1905 19:15:31.833940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1906 19:15:31.834039 ==
1907 19:15:31.834116 DQS Delay:
1908 19:15:31.837555 DQS0 = 0, DQS1 = 0
1909 19:15:31.837668 DQM Delay:
1910 19:15:31.840650 DQM0 = 92, DQM1 = 90
1911 19:15:31.840768 DQ Delay:
1912 19:15:31.844291 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
1913 19:15:31.847261 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1914 19:15:31.850905 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1915 19:15:31.854160 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1916 19:15:31.854274
1917 19:15:31.854367
1918 19:15:31.854455 ==
1919 19:15:31.857216 Dram Type= 6, Freq= 0, CH_1, rank 1
1920 19:15:31.863832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1921 19:15:31.863947 ==
1922 19:15:31.864041
1923 19:15:31.864123
1924 19:15:31.864222 TX Vref Scan disable
1925 19:15:31.867512 == TX Byte 0 ==
1926 19:15:31.870464 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1927 19:15:31.874171 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1928 19:15:31.877100 == TX Byte 1 ==
1929 19:15:31.880695 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1930 19:15:31.884129 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1931 19:15:31.887779 ==
1932 19:15:31.890714 Dram Type= 6, Freq= 0, CH_1, rank 1
1933 19:15:31.894443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1934 19:15:31.894545 ==
1935 19:15:31.906017 TX Vref=22, minBit 1, minWin=26, winSum=436
1936 19:15:31.909581 TX Vref=24, minBit 0, minWin=27, winSum=438
1937 19:15:31.912786 TX Vref=26, minBit 2, minWin=27, winSum=445
1938 19:15:31.916541 TX Vref=28, minBit 2, minWin=27, winSum=448
1939 19:15:31.920110 TX Vref=30, minBit 0, minWin=27, winSum=444
1940 19:15:31.923013 TX Vref=32, minBit 2, minWin=27, winSum=448
1941 19:15:31.929382 [TxChooseVref] Worse bit 2, Min win 27, Win sum 448, Final Vref 28
1942 19:15:31.929502
1943 19:15:31.933031 Final TX Range 1 Vref 28
1944 19:15:31.933145
1945 19:15:31.933234 ==
1946 19:15:31.935961 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 19:15:31.939417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 19:15:31.939530 ==
1949 19:15:31.939626
1950 19:15:31.942864
1951 19:15:31.942975 TX Vref Scan disable
1952 19:15:31.946500 == TX Byte 0 ==
1953 19:15:31.949430 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1954 19:15:31.953058 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1955 19:15:31.956635 == TX Byte 1 ==
1956 19:15:31.959563 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1957 19:15:31.963366 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1958 19:15:31.966245
1959 19:15:31.966352 [DATLAT]
1960 19:15:31.966448 Freq=800, CH1 RK1
1961 19:15:31.966537
1962 19:15:31.969614 DATLAT Default: 0xa
1963 19:15:31.969693 0, 0xFFFF, sum = 0
1964 19:15:31.973193 1, 0xFFFF, sum = 0
1965 19:15:31.973315 2, 0xFFFF, sum = 0
1966 19:15:31.976137 3, 0xFFFF, sum = 0
1967 19:15:31.976242 4, 0xFFFF, sum = 0
1968 19:15:31.979889 5, 0xFFFF, sum = 0
1969 19:15:31.980001 6, 0xFFFF, sum = 0
1970 19:15:31.982733 7, 0xFFFF, sum = 0
1971 19:15:31.982824 8, 0xFFFF, sum = 0
1972 19:15:31.986287 9, 0x0, sum = 1
1973 19:15:31.986408 10, 0x0, sum = 2
1974 19:15:31.989576 11, 0x0, sum = 3
1975 19:15:31.989690 12, 0x0, sum = 4
1976 19:15:31.993320 best_step = 10
1977 19:15:31.993433
1978 19:15:31.993530 ==
1979 19:15:31.996105 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 19:15:31.999672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 19:15:31.999793 ==
1982 19:15:32.003234 RX Vref Scan: 0
1983 19:15:32.003323
1984 19:15:32.003417 RX Vref 0 -> 0, step: 1
1985 19:15:32.003512
1986 19:15:32.006325 RX Delay -63 -> 252, step: 8
1987 19:15:32.013018 iDelay=209, Bit 0, Center 100 (1 ~ 200) 200
1988 19:15:32.016173 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1989 19:15:32.019788 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1990 19:15:32.022634 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1991 19:15:32.026064 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1992 19:15:32.029369 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1993 19:15:32.036466 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1994 19:15:32.039494 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1995 19:15:32.043096 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1996 19:15:32.046053 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1997 19:15:32.049621 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
1998 19:15:32.056105 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
1999 19:15:32.059766 iDelay=209, Bit 12, Center 96 (-15 ~ 208) 224
2000 19:15:32.062620 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2001 19:15:32.066566 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2002 19:15:32.069648 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2003 19:15:32.072669 ==
2004 19:15:32.076475 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 19:15:32.079293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 19:15:32.079418 ==
2007 19:15:32.079514 DQS Delay:
2008 19:15:32.082862 DQS0 = 0, DQS1 = 0
2009 19:15:32.082982 DQM Delay:
2010 19:15:32.085957 DQM0 = 97, DQM1 = 90
2011 19:15:32.086061 DQ Delay:
2012 19:15:32.089582 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =92
2013 19:15:32.092605 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2014 19:15:32.096145 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2015 19:15:32.099654 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
2016 19:15:32.099750
2017 19:15:32.099815
2018 19:15:32.106029 [DQSOSCAuto] RK1, (LSB)MR18= 0x450f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2019 19:15:32.109111 CH1 RK1: MR19=606, MR18=450F
2020 19:15:32.115830 CH1_RK1: MR19=0x606, MR18=0x450F, DQSOSC=392, MR23=63, INC=96, DEC=64
2021 19:15:32.119511 [RxdqsGatingPostProcess] freq 800
2022 19:15:32.122527 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2023 19:15:32.126278 Pre-setting of DQS Precalculation
2024 19:15:32.132804 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2025 19:15:32.139039 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2026 19:15:32.145864 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2027 19:15:32.145984
2028 19:15:32.146053
2029 19:15:32.149602 [Calibration Summary] 1600 Mbps
2030 19:15:32.152874 CH 0, Rank 0
2031 19:15:32.152978 SW Impedance : PASS
2032 19:15:32.155877 DUTY Scan : NO K
2033 19:15:32.155970 ZQ Calibration : PASS
2034 19:15:32.159291 Jitter Meter : NO K
2035 19:15:32.162790 CBT Training : PASS
2036 19:15:32.162886 Write leveling : PASS
2037 19:15:32.166176 RX DQS gating : PASS
2038 19:15:32.169667 RX DQ/DQS(RDDQC) : PASS
2039 19:15:32.169765 TX DQ/DQS : PASS
2040 19:15:32.173236 RX DATLAT : PASS
2041 19:15:32.176208 RX DQ/DQS(Engine): PASS
2042 19:15:32.176329 TX OE : NO K
2043 19:15:32.179875 All Pass.
2044 19:15:32.179970
2045 19:15:32.180058 CH 0, Rank 1
2046 19:15:32.182905 SW Impedance : PASS
2047 19:15:32.182989 DUTY Scan : NO K
2048 19:15:32.186569 ZQ Calibration : PASS
2049 19:15:32.186660 Jitter Meter : NO K
2050 19:15:32.189420 CBT Training : PASS
2051 19:15:32.193083 Write leveling : PASS
2052 19:15:32.193194 RX DQS gating : PASS
2053 19:15:32.196670 RX DQ/DQS(RDDQC) : PASS
2054 19:15:32.199396 TX DQ/DQS : PASS
2055 19:15:32.199530 RX DATLAT : PASS
2056 19:15:32.202956 RX DQ/DQS(Engine): PASS
2057 19:15:32.206436 TX OE : NO K
2058 19:15:32.206559 All Pass.
2059 19:15:32.206664
2060 19:15:32.206765 CH 1, Rank 0
2061 19:15:32.209860 SW Impedance : PASS
2062 19:15:32.213305 DUTY Scan : NO K
2063 19:15:32.213406 ZQ Calibration : PASS
2064 19:15:32.216159 Jitter Meter : NO K
2065 19:15:32.219834 CBT Training : PASS
2066 19:15:32.219934 Write leveling : PASS
2067 19:15:32.222790 RX DQS gating : PASS
2068 19:15:32.222873 RX DQ/DQS(RDDQC) : PASS
2069 19:15:32.226497 TX DQ/DQS : PASS
2070 19:15:32.230045 RX DATLAT : PASS
2071 19:15:32.230140 RX DQ/DQS(Engine): PASS
2072 19:15:32.233097 TX OE : NO K
2073 19:15:32.233187 All Pass.
2074 19:15:32.233275
2075 19:15:32.236665 CH 1, Rank 1
2076 19:15:32.236753 SW Impedance : PASS
2077 19:15:32.239776 DUTY Scan : NO K
2078 19:15:32.242898 ZQ Calibration : PASS
2079 19:15:32.242992 Jitter Meter : NO K
2080 19:15:32.246449 CBT Training : PASS
2081 19:15:32.250005 Write leveling : PASS
2082 19:15:32.250101 RX DQS gating : PASS
2083 19:15:32.253027 RX DQ/DQS(RDDQC) : PASS
2084 19:15:32.256461 TX DQ/DQS : PASS
2085 19:15:32.256559 RX DATLAT : PASS
2086 19:15:32.259988 RX DQ/DQS(Engine): PASS
2087 19:15:32.260093 TX OE : NO K
2088 19:15:32.263388 All Pass.
2089 19:15:32.263500
2090 19:15:32.263596 DramC Write-DBI off
2091 19:15:32.266884 PER_BANK_REFRESH: Hybrid Mode
2092 19:15:32.270322 TX_TRACKING: ON
2093 19:15:32.272955 [GetDramInforAfterCalByMRR] Vendor 6.
2094 19:15:32.276947 [GetDramInforAfterCalByMRR] Revision 606.
2095 19:15:32.279735 [GetDramInforAfterCalByMRR] Revision 2 0.
2096 19:15:32.279853 MR0 0x3b3b
2097 19:15:32.279953 MR8 0x5151
2098 19:15:32.286928 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2099 19:15:32.287059
2100 19:15:32.287131 MR0 0x3b3b
2101 19:15:32.287201 MR8 0x5151
2102 19:15:32.289907 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2103 19:15:32.290022
2104 19:15:32.299939 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2105 19:15:32.302848 [FAST_K] Save calibration result to emmc
2106 19:15:32.306554 [FAST_K] Save calibration result to emmc
2107 19:15:32.309479 dram_init: config_dvfs: 1
2108 19:15:32.313182 dramc_set_vcore_voltage set vcore to 662500
2109 19:15:32.316635 Read voltage for 1200, 2
2110 19:15:32.316734 Vio18 = 0
2111 19:15:32.319555 Vcore = 662500
2112 19:15:32.319637 Vdram = 0
2113 19:15:32.319703 Vddq = 0
2114 19:15:32.319764 Vmddr = 0
2115 19:15:32.326409 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2116 19:15:32.330163 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2117 19:15:32.333219 MEM_TYPE=3, freq_sel=15
2118 19:15:32.336254 sv_algorithm_assistance_LP4_1600
2119 19:15:32.340092 ============ PULL DRAM RESETB DOWN ============
2120 19:15:32.346486 ========== PULL DRAM RESETB DOWN end =========
2121 19:15:32.350063 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2122 19:15:32.352928 ===================================
2123 19:15:32.356629 LPDDR4 DRAM CONFIGURATION
2124 19:15:32.359524 ===================================
2125 19:15:32.359616 EX_ROW_EN[0] = 0x0
2126 19:15:32.363226 EX_ROW_EN[1] = 0x0
2127 19:15:32.363313 LP4Y_EN = 0x0
2128 19:15:32.366866 WORK_FSP = 0x0
2129 19:15:32.366954 WL = 0x4
2130 19:15:32.369778 RL = 0x4
2131 19:15:32.369865 BL = 0x2
2132 19:15:32.373278 RPST = 0x0
2133 19:15:32.373365 RD_PRE = 0x0
2134 19:15:32.376620 WR_PRE = 0x1
2135 19:15:32.376708 WR_PST = 0x0
2136 19:15:32.379519 DBI_WR = 0x0
2137 19:15:32.379603 DBI_RD = 0x0
2138 19:15:32.382945 OTF = 0x1
2139 19:15:32.386260 ===================================
2140 19:15:32.389569 ===================================
2141 19:15:32.389665 ANA top config
2142 19:15:32.393110 ===================================
2143 19:15:32.396386 DLL_ASYNC_EN = 0
2144 19:15:32.400046 ALL_SLAVE_EN = 0
2145 19:15:32.403465 NEW_RANK_MODE = 1
2146 19:15:32.403559 DLL_IDLE_MODE = 1
2147 19:15:32.406866 LP45_APHY_COMB_EN = 1
2148 19:15:32.410554 TX_ODT_DIS = 1
2149 19:15:32.413316 NEW_8X_MODE = 1
2150 19:15:32.416746 ===================================
2151 19:15:32.420291 ===================================
2152 19:15:32.423313 data_rate = 2400
2153 19:15:32.423432 CKR = 1
2154 19:15:32.426989 DQ_P2S_RATIO = 8
2155 19:15:32.430455 ===================================
2156 19:15:32.433244 CA_P2S_RATIO = 8
2157 19:15:32.436607 DQ_CA_OPEN = 0
2158 19:15:32.440151 DQ_SEMI_OPEN = 0
2159 19:15:32.443160 CA_SEMI_OPEN = 0
2160 19:15:32.443261 CA_FULL_RATE = 0
2161 19:15:32.446817 DQ_CKDIV4_EN = 0
2162 19:15:32.449766 CA_CKDIV4_EN = 0
2163 19:15:32.453499 CA_PREDIV_EN = 0
2164 19:15:32.456599 PH8_DLY = 17
2165 19:15:32.456693 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2166 19:15:32.460193 DQ_AAMCK_DIV = 4
2167 19:15:32.463835 CA_AAMCK_DIV = 4
2168 19:15:32.466969 CA_ADMCK_DIV = 4
2169 19:15:32.470304 DQ_TRACK_CA_EN = 0
2170 19:15:32.473249 CA_PICK = 1200
2171 19:15:32.476930 CA_MCKIO = 1200
2172 19:15:32.477019 MCKIO_SEMI = 0
2173 19:15:32.480444 PLL_FREQ = 2366
2174 19:15:32.483295 DQ_UI_PI_RATIO = 32
2175 19:15:32.486986 CA_UI_PI_RATIO = 0
2176 19:15:32.489900 ===================================
2177 19:15:32.493443 ===================================
2178 19:15:32.497048 memory_type:LPDDR4
2179 19:15:32.497165 GP_NUM : 10
2180 19:15:32.500013 SRAM_EN : 1
2181 19:15:32.503863 MD32_EN : 0
2182 19:15:32.504031 ===================================
2183 19:15:32.506664 [ANA_INIT] >>>>>>>>>>>>>>
2184 19:15:32.510030 <<<<<< [CONFIGURE PHASE]: ANA_TX
2185 19:15:32.513756 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2186 19:15:32.517146 ===================================
2187 19:15:32.520401 data_rate = 2400,PCW = 0X5b00
2188 19:15:32.523269 ===================================
2189 19:15:32.526671 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2190 19:15:32.533799 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2191 19:15:32.536693 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2192 19:15:32.543896 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2193 19:15:32.547239 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2194 19:15:32.549974 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2195 19:15:32.550060 [ANA_INIT] flow start
2196 19:15:32.553730 [ANA_INIT] PLL >>>>>>>>
2197 19:15:32.556788 [ANA_INIT] PLL <<<<<<<<
2198 19:15:32.556877 [ANA_INIT] MIDPI >>>>>>>>
2199 19:15:32.560257 [ANA_INIT] MIDPI <<<<<<<<
2200 19:15:32.563260 [ANA_INIT] DLL >>>>>>>>
2201 19:15:32.563345 [ANA_INIT] DLL <<<<<<<<
2202 19:15:32.567076 [ANA_INIT] flow end
2203 19:15:32.569925 ============ LP4 DIFF to SE enter ============
2204 19:15:32.573549 ============ LP4 DIFF to SE exit ============
2205 19:15:32.577132 [ANA_INIT] <<<<<<<<<<<<<
2206 19:15:32.579989 [Flow] Enable top DCM control >>>>>
2207 19:15:32.583546 [Flow] Enable top DCM control <<<<<
2208 19:15:32.587119 Enable DLL master slave shuffle
2209 19:15:32.593494 ==============================================================
2210 19:15:32.593607 Gating Mode config
2211 19:15:32.600023 ==============================================================
2212 19:15:32.600147 Config description:
2213 19:15:32.610186 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2214 19:15:32.617398 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2215 19:15:32.623709 SELPH_MODE 0: By rank 1: By Phase
2216 19:15:32.627351 ==============================================================
2217 19:15:32.630625 GAT_TRACK_EN = 1
2218 19:15:32.633953 RX_GATING_MODE = 2
2219 19:15:32.637234 RX_GATING_TRACK_MODE = 2
2220 19:15:32.640890 SELPH_MODE = 1
2221 19:15:32.643555 PICG_EARLY_EN = 1
2222 19:15:32.647324 VALID_LAT_VALUE = 1
2223 19:15:32.650880 ==============================================================
2224 19:15:32.653602 Enter into Gating configuration >>>>
2225 19:15:32.656976 Exit from Gating configuration <<<<
2226 19:15:32.660591 Enter into DVFS_PRE_config >>>>>
2227 19:15:32.674287 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2228 19:15:32.677347 Exit from DVFS_PRE_config <<<<<
2229 19:15:32.677442 Enter into PICG configuration >>>>
2230 19:15:32.680941 Exit from PICG configuration <<<<
2231 19:15:32.683772 [RX_INPUT] configuration >>>>>
2232 19:15:32.687242 [RX_INPUT] configuration <<<<<
2233 19:15:32.693962 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2234 19:15:32.697482 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2235 19:15:32.703996 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2236 19:15:32.710446 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2237 19:15:32.717741 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2238 19:15:32.724239 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2239 19:15:32.727132 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2240 19:15:32.730971 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2241 19:15:32.733848 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2242 19:15:32.741080 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2243 19:15:32.743783 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2244 19:15:32.747086 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2245 19:15:32.750427 ===================================
2246 19:15:32.753770 LPDDR4 DRAM CONFIGURATION
2247 19:15:32.757643 ===================================
2248 19:15:32.757756 EX_ROW_EN[0] = 0x0
2249 19:15:32.760676 EX_ROW_EN[1] = 0x0
2250 19:15:32.764091 LP4Y_EN = 0x0
2251 19:15:32.764200 WORK_FSP = 0x0
2252 19:15:32.767512 WL = 0x4
2253 19:15:32.767616 RL = 0x4
2254 19:15:32.770602 BL = 0x2
2255 19:15:32.770706 RPST = 0x0
2256 19:15:32.774014 RD_PRE = 0x0
2257 19:15:32.774131 WR_PRE = 0x1
2258 19:15:32.777748 WR_PST = 0x0
2259 19:15:32.777833 DBI_WR = 0x0
2260 19:15:32.780647 DBI_RD = 0x0
2261 19:15:32.780729 OTF = 0x1
2262 19:15:32.784389 ===================================
2263 19:15:32.787285 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2264 19:15:32.794065 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2265 19:15:32.797794 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2266 19:15:32.800604 ===================================
2267 19:15:32.804398 LPDDR4 DRAM CONFIGURATION
2268 19:15:32.807204 ===================================
2269 19:15:32.807306 EX_ROW_EN[0] = 0x10
2270 19:15:32.811078 EX_ROW_EN[1] = 0x0
2271 19:15:32.811185 LP4Y_EN = 0x0
2272 19:15:32.814421 WORK_FSP = 0x0
2273 19:15:32.814522 WL = 0x4
2274 19:15:32.817216 RL = 0x4
2275 19:15:32.817298 BL = 0x2
2276 19:15:32.820583 RPST = 0x0
2277 19:15:32.820659 RD_PRE = 0x0
2278 19:15:32.824418 WR_PRE = 0x1
2279 19:15:32.824524 WR_PST = 0x0
2280 19:15:32.827284 DBI_WR = 0x0
2281 19:15:32.831075 DBI_RD = 0x0
2282 19:15:32.831181 OTF = 0x1
2283 19:15:32.833942 ===================================
2284 19:15:32.840609 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2285 19:15:32.840693 ==
2286 19:15:32.844244 Dram Type= 6, Freq= 0, CH_0, rank 0
2287 19:15:32.847331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2288 19:15:32.847409 ==
2289 19:15:32.851097 [Duty_Offset_Calibration]
2290 19:15:32.851173 B0:2 B1:1 CA:1
2291 19:15:32.851236
2292 19:15:32.854057 [DutyScan_Calibration_Flow] k_type=0
2293 19:15:32.865134
2294 19:15:32.865223 ==CLK 0==
2295 19:15:32.868689 Final CLK duty delay cell = 0
2296 19:15:32.871941 [0] MAX Duty = 5187%(X100), DQS PI = 24
2297 19:15:32.874624 [0] MIN Duty = 4844%(X100), DQS PI = 48
2298 19:15:32.874699 [0] AVG Duty = 5015%(X100)
2299 19:15:32.878495
2300 19:15:32.881416 CH0 CLK Duty spec in!! Max-Min= 343%
2301 19:15:32.884592 [DutyScan_Calibration_Flow] ====Done====
2302 19:15:32.884686
2303 19:15:32.887899 [DutyScan_Calibration_Flow] k_type=1
2304 19:15:32.903816
2305 19:15:32.903921 ==DQS 0 ==
2306 19:15:32.907353 Final DQS duty delay cell = -4
2307 19:15:32.910119 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2308 19:15:32.913812 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2309 19:15:32.916793 [-4] AVG Duty = 4937%(X100)
2310 19:15:32.916880
2311 19:15:32.916945 ==DQS 1 ==
2312 19:15:32.920410 Final DQS duty delay cell = 0
2313 19:15:32.923508 [0] MAX Duty = 5156%(X100), DQS PI = 62
2314 19:15:32.927259 [0] MIN Duty = 5000%(X100), DQS PI = 34
2315 19:15:32.930550 [0] AVG Duty = 5078%(X100)
2316 19:15:32.930636
2317 19:15:32.933547 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2318 19:15:32.933631
2319 19:15:32.937050 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2320 19:15:32.940100 [DutyScan_Calibration_Flow] ====Done====
2321 19:15:32.940202
2322 19:15:32.943887 [DutyScan_Calibration_Flow] k_type=3
2323 19:15:32.960164
2324 19:15:32.960295 ==DQM 0 ==
2325 19:15:32.963845 Final DQM duty delay cell = 0
2326 19:15:32.966732 [0] MAX Duty = 5156%(X100), DQS PI = 30
2327 19:15:32.970411 [0] MIN Duty = 4906%(X100), DQS PI = 50
2328 19:15:32.970518 [0] AVG Duty = 5031%(X100)
2329 19:15:32.973419
2330 19:15:32.973500 ==DQM 1 ==
2331 19:15:32.976991 Final DQM duty delay cell = 0
2332 19:15:32.980267 [0] MAX Duty = 5093%(X100), DQS PI = 0
2333 19:15:32.983912 [0] MIN Duty = 5031%(X100), DQS PI = 14
2334 19:15:32.984018 [0] AVG Duty = 5062%(X100)
2335 19:15:32.987350
2336 19:15:32.990409 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2337 19:15:32.990492
2338 19:15:32.994140 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2339 19:15:32.997058 [DutyScan_Calibration_Flow] ====Done====
2340 19:15:32.997141
2341 19:15:33.000429 [DutyScan_Calibration_Flow] k_type=2
2342 19:15:33.016896
2343 19:15:33.017030 ==DQ 0 ==
2344 19:15:33.020505 Final DQ duty delay cell = 0
2345 19:15:33.023438 [0] MAX Duty = 5031%(X100), DQS PI = 24
2346 19:15:33.026814 [0] MIN Duty = 4844%(X100), DQS PI = 62
2347 19:15:33.026902 [0] AVG Duty = 4937%(X100)
2348 19:15:33.026977
2349 19:15:33.030413 ==DQ 1 ==
2350 19:15:33.033352 Final DQ duty delay cell = 0
2351 19:15:33.036885 [0] MAX Duty = 5093%(X100), DQS PI = 24
2352 19:15:33.040509 [0] MIN Duty = 4907%(X100), DQS PI = 36
2353 19:15:33.040603 [0] AVG Duty = 5000%(X100)
2354 19:15:33.040668
2355 19:15:33.043981 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2356 19:15:33.044071
2357 19:15:33.047746 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2358 19:15:33.050536 [DutyScan_Calibration_Flow] ====Done====
2359 19:15:33.054139 ==
2360 19:15:33.057072 Dram Type= 6, Freq= 0, CH_1, rank 0
2361 19:15:33.060929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2362 19:15:33.061012 ==
2363 19:15:33.063875 [Duty_Offset_Calibration]
2364 19:15:33.063981 B0:1 B1:0 CA:0
2365 19:15:33.064077
2366 19:15:33.067535 [DutyScan_Calibration_Flow] k_type=0
2367 19:15:33.076186
2368 19:15:33.076293 ==CLK 0==
2369 19:15:33.079133 Final CLK duty delay cell = -4
2370 19:15:33.082712 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2371 19:15:33.086270 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2372 19:15:33.089780 [-4] AVG Duty = 4969%(X100)
2373 19:15:33.089859
2374 19:15:33.092518 CH1 CLK Duty spec in!! Max-Min= 124%
2375 19:15:33.096011 [DutyScan_Calibration_Flow] ====Done====
2376 19:15:33.096116
2377 19:15:33.099773 [DutyScan_Calibration_Flow] k_type=1
2378 19:15:33.115563
2379 19:15:33.115680 ==DQS 0 ==
2380 19:15:33.119503 Final DQS duty delay cell = 0
2381 19:15:33.122484 [0] MAX Duty = 5062%(X100), DQS PI = 24
2382 19:15:33.126123 [0] MIN Duty = 4844%(X100), DQS PI = 0
2383 19:15:33.126236 [0] AVG Duty = 4953%(X100)
2384 19:15:33.128897
2385 19:15:33.129000 ==DQS 1 ==
2386 19:15:33.132193 Final DQS duty delay cell = 0
2387 19:15:33.135972 [0] MAX Duty = 5218%(X100), DQS PI = 20
2388 19:15:33.139111 [0] MIN Duty = 4969%(X100), DQS PI = 10
2389 19:15:33.139219 [0] AVG Duty = 5093%(X100)
2390 19:15:33.142824
2391 19:15:33.146046 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2392 19:15:33.146151
2393 19:15:33.149347 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2394 19:15:33.152680 [DutyScan_Calibration_Flow] ====Done====
2395 19:15:33.152765
2396 19:15:33.155700 [DutyScan_Calibration_Flow] k_type=3
2397 19:15:33.172975
2398 19:15:33.173082 ==DQM 0 ==
2399 19:15:33.175803 Final DQM duty delay cell = 0
2400 19:15:33.178817 [0] MAX Duty = 5156%(X100), DQS PI = 6
2401 19:15:33.182559 [0] MIN Duty = 5031%(X100), DQS PI = 0
2402 19:15:33.182668 [0] AVG Duty = 5093%(X100)
2403 19:15:33.185548
2404 19:15:33.185653 ==DQM 1 ==
2405 19:15:33.189247 Final DQM duty delay cell = 0
2406 19:15:33.192690 [0] MAX Duty = 5031%(X100), DQS PI = 16
2407 19:15:33.196076 [0] MIN Duty = 4907%(X100), DQS PI = 36
2408 19:15:33.196156 [0] AVG Duty = 4969%(X100)
2409 19:15:33.198768
2410 19:15:33.202221 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2411 19:15:33.202324
2412 19:15:33.205769 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2413 19:15:33.209298 [DutyScan_Calibration_Flow] ====Done====
2414 19:15:33.209401
2415 19:15:33.212226 [DutyScan_Calibration_Flow] k_type=2
2416 19:15:33.228294
2417 19:15:33.228418 ==DQ 0 ==
2418 19:15:33.231254 Final DQ duty delay cell = -4
2419 19:15:33.234959 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2420 19:15:33.238657 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2421 19:15:33.238741 [-4] AVG Duty = 4984%(X100)
2422 19:15:33.241631
2423 19:15:33.241713 ==DQ 1 ==
2424 19:15:33.245170 Final DQ duty delay cell = 0
2425 19:15:33.248543 [0] MAX Duty = 5125%(X100), DQS PI = 20
2426 19:15:33.251655 [0] MIN Duty = 4969%(X100), DQS PI = 10
2427 19:15:33.251763 [0] AVG Duty = 5047%(X100)
2428 19:15:33.251857
2429 19:15:33.255021 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2430 19:15:33.258533
2431 19:15:33.261742 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2432 19:15:33.265360 [DutyScan_Calibration_Flow] ====Done====
2433 19:15:33.268003 nWR fixed to 30
2434 19:15:33.268113 [ModeRegInit_LP4] CH0 RK0
2435 19:15:33.271447 [ModeRegInit_LP4] CH0 RK1
2436 19:15:33.274782 [ModeRegInit_LP4] CH1 RK0
2437 19:15:33.274887 [ModeRegInit_LP4] CH1 RK1
2438 19:15:33.278604 match AC timing 7
2439 19:15:33.281513 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2440 19:15:33.285026 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2441 19:15:33.291954 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2442 19:15:33.294971 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2443 19:15:33.301937 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2444 19:15:33.302052 ==
2445 19:15:33.304850 Dram Type= 6, Freq= 0, CH_0, rank 0
2446 19:15:33.308803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2447 19:15:33.308912 ==
2448 19:15:33.315335 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2449 19:15:33.318421 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2450 19:15:33.328553 [CA 0] Center 39 (8~70) winsize 63
2451 19:15:33.331530 [CA 1] Center 39 (8~70) winsize 63
2452 19:15:33.335278 [CA 2] Center 35 (5~66) winsize 62
2453 19:15:33.338295 [CA 3] Center 34 (4~65) winsize 62
2454 19:15:33.341961 [CA 4] Center 33 (3~64) winsize 62
2455 19:15:33.344907 [CA 5] Center 32 (3~62) winsize 60
2456 19:15:33.344986
2457 19:15:33.348608 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2458 19:15:33.348710
2459 19:15:33.351502 [CATrainingPosCal] consider 1 rank data
2460 19:15:33.355168 u2DelayCellTimex100 = 270/100 ps
2461 19:15:33.358004 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2462 19:15:33.361435 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2463 19:15:33.368462 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2464 19:15:33.371870 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2465 19:15:33.374647 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2466 19:15:33.378299 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2467 19:15:33.378403
2468 19:15:33.382048 CA PerBit enable=1, Macro0, CA PI delay=32
2469 19:15:33.382152
2470 19:15:33.385057 [CBTSetCACLKResult] CA Dly = 32
2471 19:15:33.385160 CS Dly: 6 (0~37)
2472 19:15:33.387901 ==
2473 19:15:33.387984 Dram Type= 6, Freq= 0, CH_0, rank 1
2474 19:15:33.395013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2475 19:15:33.395127 ==
2476 19:15:33.398225 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2477 19:15:33.404948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2478 19:15:33.414372 [CA 0] Center 38 (8~69) winsize 62
2479 19:15:33.417268 [CA 1] Center 38 (8~69) winsize 62
2480 19:15:33.420824 [CA 2] Center 35 (5~66) winsize 62
2481 19:15:33.424155 [CA 3] Center 34 (4~65) winsize 62
2482 19:15:33.427128 [CA 4] Center 33 (3~64) winsize 62
2483 19:15:33.431094 [CA 5] Center 32 (3~62) winsize 60
2484 19:15:33.431202
2485 19:15:33.433835 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2486 19:15:33.433942
2487 19:15:33.437440 [CATrainingPosCal] consider 2 rank data
2488 19:15:33.441209 u2DelayCellTimex100 = 270/100 ps
2489 19:15:33.444130 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2490 19:15:33.447576 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2491 19:15:33.454309 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2492 19:15:33.457247 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2493 19:15:33.460867 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2494 19:15:33.464369 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2495 19:15:33.464467
2496 19:15:33.467414 CA PerBit enable=1, Macro0, CA PI delay=32
2497 19:15:33.467496
2498 19:15:33.471065 [CBTSetCACLKResult] CA Dly = 32
2499 19:15:33.471147 CS Dly: 6 (0~38)
2500 19:15:33.471212
2501 19:15:33.474650 ----->DramcWriteLeveling(PI) begin...
2502 19:15:33.474734 ==
2503 19:15:33.477559 Dram Type= 6, Freq= 0, CH_0, rank 0
2504 19:15:33.484306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2505 19:15:33.484461 ==
2506 19:15:33.487498 Write leveling (Byte 0): 34 => 34
2507 19:15:33.490963 Write leveling (Byte 1): 30 => 30
2508 19:15:33.491072 DramcWriteLeveling(PI) end<-----
2509 19:15:33.494741
2510 19:15:33.494840 ==
2511 19:15:33.497577 Dram Type= 6, Freq= 0, CH_0, rank 0
2512 19:15:33.501144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 19:15:33.501227 ==
2514 19:15:33.504211 [Gating] SW mode calibration
2515 19:15:33.510810 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2516 19:15:33.514463 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2517 19:15:33.521092 0 15 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
2518 19:15:33.524721 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2519 19:15:33.527532 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 19:15:33.534364 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 19:15:33.537636 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 19:15:33.541388 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 19:15:33.548035 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2524 19:15:33.550923 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (0 0) (0 0)
2525 19:15:33.554680 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 19:15:33.560908 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 19:15:33.564689 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 19:15:33.568246 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 19:15:33.571264 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 19:15:33.577635 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 19:15:33.581199 1 0 24 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
2532 19:15:33.584616 1 0 28 | B1->B0 | 2424 4443 | 0 1 | (0 0) (0 0)
2533 19:15:33.591516 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2534 19:15:33.594331 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 19:15:33.598116 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 19:15:33.604529 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 19:15:33.608096 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 19:15:33.610987 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 19:15:33.617564 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 19:15:33.621160 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2541 19:15:33.624624 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2542 19:15:33.631247 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 19:15:33.635005 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 19:15:33.637835 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 19:15:33.645054 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 19:15:33.647865 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 19:15:33.651630 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 19:15:33.657881 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 19:15:33.661421 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 19:15:33.664881 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 19:15:33.668287 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 19:15:33.674732 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 19:15:33.678495 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 19:15:33.681534 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 19:15:33.687976 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 19:15:33.691541 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2557 19:15:33.694625 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2558 19:15:33.701548 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 19:15:33.701681 Total UI for P1: 0, mck2ui 16
2560 19:15:33.708250 best dqsien dly found for B0: ( 1, 3, 30)
2561 19:15:33.708402 Total UI for P1: 0, mck2ui 16
2562 19:15:33.714919 best dqsien dly found for B1: ( 1, 4, 0)
2563 19:15:33.718537 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2564 19:15:33.721460 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2565 19:15:33.721574
2566 19:15:33.725178 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2567 19:15:33.728105 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2568 19:15:33.731612 [Gating] SW calibration Done
2569 19:15:33.731726 ==
2570 19:15:33.735184 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 19:15:33.737888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 19:15:33.738003 ==
2573 19:15:33.741681 RX Vref Scan: 0
2574 19:15:33.741791
2575 19:15:33.741915 RX Vref 0 -> 0, step: 1
2576 19:15:33.742006
2577 19:15:33.744791 RX Delay -40 -> 252, step: 8
2578 19:15:33.748194 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
2579 19:15:33.751763 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2580 19:15:33.758190 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2581 19:15:33.761674 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2582 19:15:33.765150 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2583 19:15:33.768020 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2584 19:15:33.771708 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2585 19:15:33.778248 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2586 19:15:33.781208 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2587 19:15:33.784945 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2588 19:15:33.788841 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2589 19:15:33.791521 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2590 19:15:33.798362 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2591 19:15:33.802039 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2592 19:15:33.805283 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2593 19:15:33.808332 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2594 19:15:33.808493 ==
2595 19:15:33.811668 Dram Type= 6, Freq= 0, CH_0, rank 0
2596 19:15:33.814730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2597 19:15:33.818337 ==
2598 19:15:33.818466 DQS Delay:
2599 19:15:33.818561 DQS0 = 0, DQS1 = 0
2600 19:15:33.821563 DQM Delay:
2601 19:15:33.821669 DQM0 = 121, DQM1 = 113
2602 19:15:33.824991 DQ Delay:
2603 19:15:33.828289 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2604 19:15:33.831453 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2605 19:15:33.835238 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2606 19:15:33.838081 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2607 19:15:33.838182
2608 19:15:33.838248
2609 19:15:33.838308 ==
2610 19:15:33.841578 Dram Type= 6, Freq= 0, CH_0, rank 0
2611 19:15:33.845070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2612 19:15:33.845168 ==
2613 19:15:33.848364
2614 19:15:33.848468
2615 19:15:33.848534 TX Vref Scan disable
2616 19:15:33.851803 == TX Byte 0 ==
2617 19:15:33.855227 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2618 19:15:33.858183 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2619 19:15:33.861834 == TX Byte 1 ==
2620 19:15:33.865312 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2621 19:15:33.868047 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2622 19:15:33.868134 ==
2623 19:15:33.871608 Dram Type= 6, Freq= 0, CH_0, rank 0
2624 19:15:33.878179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2625 19:15:33.878295 ==
2626 19:15:33.889024 TX Vref=22, minBit 4, minWin=24, winSum=406
2627 19:15:33.892716 TX Vref=24, minBit 0, minWin=25, winSum=411
2628 19:15:33.895509 TX Vref=26, minBit 4, minWin=25, winSum=416
2629 19:15:33.899058 TX Vref=28, minBit 12, minWin=25, winSum=418
2630 19:15:33.902626 TX Vref=30, minBit 12, minWin=25, winSum=421
2631 19:15:33.909105 TX Vref=32, minBit 0, minWin=26, winSum=420
2632 19:15:33.912079 [TxChooseVref] Worse bit 0, Min win 26, Win sum 420, Final Vref 32
2633 19:15:33.912165
2634 19:15:33.915676 Final TX Range 1 Vref 32
2635 19:15:33.915757
2636 19:15:33.915821 ==
2637 19:15:33.918735 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 19:15:33.922473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 19:15:33.922566 ==
2640 19:15:33.922637
2641 19:15:33.925921
2642 19:15:33.926052 TX Vref Scan disable
2643 19:15:33.929452 == TX Byte 0 ==
2644 19:15:33.932183 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2645 19:15:33.935650 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2646 19:15:33.938841 == TX Byte 1 ==
2647 19:15:33.942628 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2648 19:15:33.945672 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2649 19:15:33.945756
2650 19:15:33.949391 [DATLAT]
2651 19:15:33.949473 Freq=1200, CH0 RK0
2652 19:15:33.949539
2653 19:15:33.952275 DATLAT Default: 0xd
2654 19:15:33.952368 0, 0xFFFF, sum = 0
2655 19:15:33.955533 1, 0xFFFF, sum = 0
2656 19:15:33.955616 2, 0xFFFF, sum = 0
2657 19:15:33.959183 3, 0xFFFF, sum = 0
2658 19:15:33.959267 4, 0xFFFF, sum = 0
2659 19:15:33.962978 5, 0xFFFF, sum = 0
2660 19:15:33.963061 6, 0xFFFF, sum = 0
2661 19:15:33.966238 7, 0xFFFF, sum = 0
2662 19:15:33.966325 8, 0xFFFF, sum = 0
2663 19:15:33.969369 9, 0xFFFF, sum = 0
2664 19:15:33.972813 10, 0xFFFF, sum = 0
2665 19:15:33.972905 11, 0xFFFF, sum = 0
2666 19:15:33.975577 12, 0x0, sum = 1
2667 19:15:33.975687 13, 0x0, sum = 2
2668 19:15:33.975782 14, 0x0, sum = 3
2669 19:15:33.979004 15, 0x0, sum = 4
2670 19:15:33.979087 best_step = 13
2671 19:15:33.979151
2672 19:15:33.979210 ==
2673 19:15:33.982742 Dram Type= 6, Freq= 0, CH_0, rank 0
2674 19:15:33.989258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2675 19:15:33.989345 ==
2676 19:15:33.989411 RX Vref Scan: 1
2677 19:15:33.989472
2678 19:15:33.992271 Set Vref Range= 32 -> 127
2679 19:15:33.992412
2680 19:15:33.995847 RX Vref 32 -> 127, step: 1
2681 19:15:33.995929
2682 19:15:33.999387 RX Delay -13 -> 252, step: 4
2683 19:15:33.999475
2684 19:15:34.002952 Set Vref, RX VrefLevel [Byte0]: 32
2685 19:15:34.005676 [Byte1]: 32
2686 19:15:34.005759
2687 19:15:34.009381 Set Vref, RX VrefLevel [Byte0]: 33
2688 19:15:34.012351 [Byte1]: 33
2689 19:15:34.012465
2690 19:15:34.015890 Set Vref, RX VrefLevel [Byte0]: 34
2691 19:15:34.019489 [Byte1]: 34
2692 19:15:34.023174
2693 19:15:34.023250 Set Vref, RX VrefLevel [Byte0]: 35
2694 19:15:34.026810 [Byte1]: 35
2695 19:15:34.031100
2696 19:15:34.031185 Set Vref, RX VrefLevel [Byte0]: 36
2697 19:15:34.034697 [Byte1]: 36
2698 19:15:34.039156
2699 19:15:34.039238 Set Vref, RX VrefLevel [Byte0]: 37
2700 19:15:34.042058 [Byte1]: 37
2701 19:15:34.047092
2702 19:15:34.047173 Set Vref, RX VrefLevel [Byte0]: 38
2703 19:15:34.050561 [Byte1]: 38
2704 19:15:34.054952
2705 19:15:34.055037 Set Vref, RX VrefLevel [Byte0]: 39
2706 19:15:34.058286 [Byte1]: 39
2707 19:15:34.062463
2708 19:15:34.062545 Set Vref, RX VrefLevel [Byte0]: 40
2709 19:15:34.065764 [Byte1]: 40
2710 19:15:34.070374
2711 19:15:34.070458 Set Vref, RX VrefLevel [Byte0]: 41
2712 19:15:34.073556 [Byte1]: 41
2713 19:15:34.078553
2714 19:15:34.078634 Set Vref, RX VrefLevel [Byte0]: 42
2715 19:15:34.081601 [Byte1]: 42
2716 19:15:34.086454
2717 19:15:34.086565 Set Vref, RX VrefLevel [Byte0]: 43
2718 19:15:34.089471 [Byte1]: 43
2719 19:15:34.094009
2720 19:15:34.094140 Set Vref, RX VrefLevel [Byte0]: 44
2721 19:15:34.097442 [Byte1]: 44
2722 19:15:34.102024
2723 19:15:34.102225 Set Vref, RX VrefLevel [Byte0]: 45
2724 19:15:34.105391 [Byte1]: 45
2725 19:15:34.109754
2726 19:15:34.109871 Set Vref, RX VrefLevel [Byte0]: 46
2727 19:15:34.113144 [Byte1]: 46
2728 19:15:34.117546
2729 19:15:34.117637 Set Vref, RX VrefLevel [Byte0]: 47
2730 19:15:34.121028 [Byte1]: 47
2731 19:15:34.125381
2732 19:15:34.125490 Set Vref, RX VrefLevel [Byte0]: 48
2733 19:15:34.129044 [Byte1]: 48
2734 19:15:34.133447
2735 19:15:34.133523 Set Vref, RX VrefLevel [Byte0]: 49
2736 19:15:34.136950 [Byte1]: 49
2737 19:15:34.141425
2738 19:15:34.141501 Set Vref, RX VrefLevel [Byte0]: 50
2739 19:15:34.144961 [Byte1]: 50
2740 19:15:34.149469
2741 19:15:34.149549 Set Vref, RX VrefLevel [Byte0]: 51
2742 19:15:34.152453 [Byte1]: 51
2743 19:15:34.157378
2744 19:15:34.157479 Set Vref, RX VrefLevel [Byte0]: 52
2745 19:15:34.160311 [Byte1]: 52
2746 19:15:34.165309
2747 19:15:34.165392 Set Vref, RX VrefLevel [Byte0]: 53
2748 19:15:34.168255 [Byte1]: 53
2749 19:15:34.173237
2750 19:15:34.173311 Set Vref, RX VrefLevel [Byte0]: 54
2751 19:15:34.176750 [Byte1]: 54
2752 19:15:34.181048
2753 19:15:34.181145 Set Vref, RX VrefLevel [Byte0]: 55
2754 19:15:34.183803 [Byte1]: 55
2755 19:15:34.188695
2756 19:15:34.188801 Set Vref, RX VrefLevel [Byte0]: 56
2757 19:15:34.192299 [Byte1]: 56
2758 19:15:34.196758
2759 19:15:34.196844 Set Vref, RX VrefLevel [Byte0]: 57
2760 19:15:34.200078 [Byte1]: 57
2761 19:15:34.204262
2762 19:15:34.204368 Set Vref, RX VrefLevel [Byte0]: 58
2763 19:15:34.207624 [Byte1]: 58
2764 19:15:34.212405
2765 19:15:34.212486 Set Vref, RX VrefLevel [Byte0]: 59
2766 19:15:34.215696 [Byte1]: 59
2767 19:15:34.220047
2768 19:15:34.220129 Set Vref, RX VrefLevel [Byte0]: 60
2769 19:15:34.223749 [Byte1]: 60
2770 19:15:34.228025
2771 19:15:34.228130 Set Vref, RX VrefLevel [Byte0]: 61
2772 19:15:34.231692 [Byte1]: 61
2773 19:15:34.236138
2774 19:15:34.236277 Set Vref, RX VrefLevel [Byte0]: 62
2775 19:15:34.239152 [Byte1]: 62
2776 19:15:34.243835
2777 19:15:34.243916 Set Vref, RX VrefLevel [Byte0]: 63
2778 19:15:34.247464 [Byte1]: 63
2779 19:15:34.251734
2780 19:15:34.251810 Set Vref, RX VrefLevel [Byte0]: 64
2781 19:15:34.254862 [Byte1]: 64
2782 19:15:34.259844
2783 19:15:34.259923 Set Vref, RX VrefLevel [Byte0]: 65
2784 19:15:34.263472 [Byte1]: 65
2785 19:15:34.267906
2786 19:15:34.267983 Set Vref, RX VrefLevel [Byte0]: 66
2787 19:15:34.270672 [Byte1]: 66
2788 19:15:34.275789
2789 19:15:34.275877 Set Vref, RX VrefLevel [Byte0]: 67
2790 19:15:34.278597 [Byte1]: 67
2791 19:15:34.283692
2792 19:15:34.283779 Set Vref, RX VrefLevel [Byte0]: 68
2793 19:15:34.286739 [Byte1]: 68
2794 19:15:34.291080
2795 19:15:34.291156 Set Vref, RX VrefLevel [Byte0]: 69
2796 19:15:34.294991 [Byte1]: 69
2797 19:15:34.299295
2798 19:15:34.299405 Final RX Vref Byte 0 = 56 to rank0
2799 19:15:34.302864 Final RX Vref Byte 1 = 47 to rank0
2800 19:15:34.305737 Final RX Vref Byte 0 = 56 to rank1
2801 19:15:34.309391 Final RX Vref Byte 1 = 47 to rank1==
2802 19:15:34.312299 Dram Type= 6, Freq= 0, CH_0, rank 0
2803 19:15:34.319048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2804 19:15:34.319237 ==
2805 19:15:34.319349 DQS Delay:
2806 19:15:34.319443 DQS0 = 0, DQS1 = 0
2807 19:15:34.322720 DQM Delay:
2808 19:15:34.322827 DQM0 = 120, DQM1 = 110
2809 19:15:34.325518 DQ Delay:
2810 19:15:34.329063 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2811 19:15:34.332408 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2812 19:15:34.336113 DQ8 =96, DQ9 =100, DQ10 =112, DQ11 =102
2813 19:15:34.339139 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2814 19:15:34.339250
2815 19:15:34.339341
2816 19:15:34.345904 [DQSOSCAuto] RK0, (LSB)MR18= 0x120b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2817 19:15:34.349231 CH0 RK0: MR19=404, MR18=120B
2818 19:15:34.355999 CH0_RK0: MR19=0x404, MR18=0x120B, DQSOSC=403, MR23=63, INC=40, DEC=26
2819 19:15:34.356104
2820 19:15:34.359085 ----->DramcWriteLeveling(PI) begin...
2821 19:15:34.359167 ==
2822 19:15:34.362655 Dram Type= 6, Freq= 0, CH_0, rank 1
2823 19:15:34.365728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2824 19:15:34.369379 ==
2825 19:15:34.369463 Write leveling (Byte 0): 34 => 34
2826 19:15:34.372862 Write leveling (Byte 1): 30 => 30
2827 19:15:34.376168 DramcWriteLeveling(PI) end<-----
2828 19:15:34.376293
2829 19:15:34.376399 ==
2830 19:15:34.379055 Dram Type= 6, Freq= 0, CH_0, rank 1
2831 19:15:34.385660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2832 19:15:34.385741 ==
2833 19:15:34.385805 [Gating] SW mode calibration
2834 19:15:34.395863 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2835 19:15:34.399446 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2836 19:15:34.402264 0 15 0 | B1->B0 | 3333 3131 | 1 1 | (1 1) (1 1)
2837 19:15:34.409162 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 19:15:34.412598 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 19:15:34.416187 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 19:15:34.422708 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 19:15:34.425612 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 19:15:34.429321 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
2843 19:15:34.436319 0 15 28 | B1->B0 | 3131 3030 | 1 1 | (1 1) (1 0)
2844 19:15:34.439204 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 19:15:34.442816 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 19:15:34.449517 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 19:15:34.452293 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 19:15:34.455933 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 19:15:34.462366 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 19:15:34.465855 1 0 24 | B1->B0 | 2424 2423 | 0 1 | (0 0) (0 0)
2851 19:15:34.469376 1 0 28 | B1->B0 | 3838 3433 | 0 1 | (0 0) (0 0)
2852 19:15:34.475565 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 19:15:34.479356 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 19:15:34.482589 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 19:15:34.489519 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 19:15:34.492724 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 19:15:34.495777 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 19:15:34.499142 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 19:15:34.506448 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2860 19:15:34.509058 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2861 19:15:34.512472 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 19:15:34.519508 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 19:15:34.522419 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 19:15:34.526473 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 19:15:34.532993 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 19:15:34.536538 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 19:15:34.539223 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 19:15:34.546459 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 19:15:34.549261 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 19:15:34.552895 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 19:15:34.559532 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 19:15:34.562406 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 19:15:34.566072 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 19:15:34.572890 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 19:15:34.575895 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2876 19:15:34.579500 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2877 19:15:34.583073 Total UI for P1: 0, mck2ui 16
2878 19:15:34.585994 best dqsien dly found for B1: ( 1, 3, 28)
2879 19:15:34.589537 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 19:15:34.593097 Total UI for P1: 0, mck2ui 16
2881 19:15:34.596461 best dqsien dly found for B0: ( 1, 3, 30)
2882 19:15:34.599753 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2883 19:15:34.603102 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2884 19:15:34.603184
2885 19:15:34.609743 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2886 19:15:34.613044 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2887 19:15:34.613135 [Gating] SW calibration Done
2888 19:15:34.616100 ==
2889 19:15:34.619802 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 19:15:34.622788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 19:15:34.622881 ==
2892 19:15:34.622961 RX Vref Scan: 0
2893 19:15:34.623041
2894 19:15:34.626521 RX Vref 0 -> 0, step: 1
2895 19:15:34.626606
2896 19:15:34.629959 RX Delay -40 -> 252, step: 8
2897 19:15:34.633141 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2898 19:15:34.636552 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2899 19:15:34.639754 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2900 19:15:34.646171 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2901 19:15:34.649861 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2902 19:15:34.652901 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2903 19:15:34.656593 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2904 19:15:34.660079 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2905 19:15:34.666457 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2906 19:15:34.670045 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2907 19:15:34.672915 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2908 19:15:34.676313 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2909 19:15:34.679694 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2910 19:15:34.686893 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2911 19:15:34.689725 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2912 19:15:34.692861 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2913 19:15:34.692943 ==
2914 19:15:34.696311 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 19:15:34.700152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 19:15:34.700257 ==
2917 19:15:34.702929 DQS Delay:
2918 19:15:34.703002 DQS0 = 0, DQS1 = 0
2919 19:15:34.706281 DQM Delay:
2920 19:15:34.706356 DQM0 = 121, DQM1 = 111
2921 19:15:34.706425 DQ Delay:
2922 19:15:34.709546 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2923 19:15:34.716703 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2924 19:15:34.719578 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =103
2925 19:15:34.723095 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2926 19:15:34.723184
2927 19:15:34.723250
2928 19:15:34.723309 ==
2929 19:15:34.726640 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 19:15:34.729843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 19:15:34.729952 ==
2932 19:15:34.730020
2933 19:15:34.730080
2934 19:15:34.733068 TX Vref Scan disable
2935 19:15:34.733178 == TX Byte 0 ==
2936 19:15:34.739761 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2937 19:15:34.743606 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2938 19:15:34.743692 == TX Byte 1 ==
2939 19:15:34.749984 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2940 19:15:34.753571 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2941 19:15:34.753654 ==
2942 19:15:34.756425 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 19:15:34.760086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 19:15:34.760171 ==
2945 19:15:34.773140 TX Vref=22, minBit 2, minWin=25, winSum=415
2946 19:15:34.776811 TX Vref=24, minBit 1, minWin=25, winSum=419
2947 19:15:34.779694 TX Vref=26, minBit 0, minWin=26, winSum=426
2948 19:15:34.783109 TX Vref=28, minBit 1, minWin=26, winSum=428
2949 19:15:34.786555 TX Vref=30, minBit 1, minWin=26, winSum=425
2950 19:15:34.789874 TX Vref=32, minBit 5, minWin=25, winSum=424
2951 19:15:34.796467 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
2952 19:15:34.796556
2953 19:15:34.800154 Final TX Range 1 Vref 28
2954 19:15:34.800259
2955 19:15:34.800371 ==
2956 19:15:34.803134 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 19:15:34.806828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 19:15:34.806902 ==
2959 19:15:34.806965
2960 19:15:34.807023
2961 19:15:34.810413 TX Vref Scan disable
2962 19:15:34.813127 == TX Byte 0 ==
2963 19:15:34.816486 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2964 19:15:34.819861 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2965 19:15:34.823365 == TX Byte 1 ==
2966 19:15:34.827022 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2967 19:15:34.830096 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2968 19:15:34.830182
2969 19:15:34.833605 [DATLAT]
2970 19:15:34.833688 Freq=1200, CH0 RK1
2971 19:15:34.833753
2972 19:15:34.836953 DATLAT Default: 0xd
2973 19:15:34.837034 0, 0xFFFF, sum = 0
2974 19:15:34.839940 1, 0xFFFF, sum = 0
2975 19:15:34.840024 2, 0xFFFF, sum = 0
2976 19:15:34.843493 3, 0xFFFF, sum = 0
2977 19:15:34.843576 4, 0xFFFF, sum = 0
2978 19:15:34.847104 5, 0xFFFF, sum = 0
2979 19:15:34.847188 6, 0xFFFF, sum = 0
2980 19:15:34.850080 7, 0xFFFF, sum = 0
2981 19:15:34.850163 8, 0xFFFF, sum = 0
2982 19:15:34.853539 9, 0xFFFF, sum = 0
2983 19:15:34.853622 10, 0xFFFF, sum = 0
2984 19:15:34.857098 11, 0xFFFF, sum = 0
2985 19:15:34.859826 12, 0x0, sum = 1
2986 19:15:34.859903 13, 0x0, sum = 2
2987 19:15:34.859975 14, 0x0, sum = 3
2988 19:15:34.863315 15, 0x0, sum = 4
2989 19:15:34.863392 best_step = 13
2990 19:15:34.863456
2991 19:15:34.863522 ==
2992 19:15:34.866895 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 19:15:34.873557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 19:15:34.873643 ==
2995 19:15:34.873708 RX Vref Scan: 0
2996 19:15:34.873768
2997 19:15:34.876872 RX Vref 0 -> 0, step: 1
2998 19:15:34.876953
2999 19:15:34.879827 RX Delay -13 -> 252, step: 4
3000 19:15:34.883306 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3001 19:15:34.887095 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3002 19:15:34.893581 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3003 19:15:34.896976 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3004 19:15:34.900479 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3005 19:15:34.903953 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3006 19:15:34.906854 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3007 19:15:34.910466 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3008 19:15:34.917025 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3009 19:15:34.920648 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3010 19:15:34.924054 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3011 19:15:34.926884 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3012 19:15:34.930369 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3013 19:15:34.936965 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3014 19:15:34.940336 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3015 19:15:34.944027 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3016 19:15:34.944110 ==
3017 19:15:34.946973 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 19:15:34.950530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 19:15:34.950607 ==
3020 19:15:34.954170 DQS Delay:
3021 19:15:34.954242 DQS0 = 0, DQS1 = 0
3022 19:15:34.957506 DQM Delay:
3023 19:15:34.957578 DQM0 = 120, DQM1 = 109
3024 19:15:34.960363 DQ Delay:
3025 19:15:34.964096 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3026 19:15:34.966868 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3027 19:15:34.970436 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3028 19:15:34.974170 DQ12 =114, DQ13 =116, DQ14 =120, DQ15 =118
3029 19:15:34.974249
3030 19:15:34.974311
3031 19:15:34.980264 [DQSOSCAuto] RK1, (LSB)MR18= 0xdee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3032 19:15:34.983883 CH0 RK1: MR19=403, MR18=DEE
3033 19:15:34.990494 CH0_RK1: MR19=0x403, MR18=0xDEE, DQSOSC=405, MR23=63, INC=39, DEC=26
3034 19:15:34.993810 [RxdqsGatingPostProcess] freq 1200
3035 19:15:34.997203 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3036 19:15:35.000503 best DQS0 dly(2T, 0.5T) = (0, 11)
3037 19:15:35.003628 best DQS1 dly(2T, 0.5T) = (0, 12)
3038 19:15:35.007419 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3039 19:15:35.010574 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3040 19:15:35.013626 best DQS0 dly(2T, 0.5T) = (0, 11)
3041 19:15:35.017521 best DQS1 dly(2T, 0.5T) = (0, 11)
3042 19:15:35.020193 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3043 19:15:35.023948 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3044 19:15:35.027553 Pre-setting of DQS Precalculation
3045 19:15:35.030197 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3046 19:15:35.030306 ==
3047 19:15:35.033486 Dram Type= 6, Freq= 0, CH_1, rank 0
3048 19:15:35.040731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 19:15:35.040827 ==
3050 19:15:35.043736 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3051 19:15:35.050807 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3052 19:15:35.059075 [CA 0] Center 37 (7~68) winsize 62
3053 19:15:35.062753 [CA 1] Center 37 (7~68) winsize 62
3054 19:15:35.066331 [CA 2] Center 35 (5~65) winsize 61
3055 19:15:35.069202 [CA 3] Center 34 (4~65) winsize 62
3056 19:15:35.072547 [CA 4] Center 34 (4~64) winsize 61
3057 19:15:35.076117 [CA 5] Center 33 (3~63) winsize 61
3058 19:15:35.076201
3059 19:15:35.079226 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3060 19:15:35.079308
3061 19:15:35.082839 [CATrainingPosCal] consider 1 rank data
3062 19:15:35.085846 u2DelayCellTimex100 = 270/100 ps
3063 19:15:35.089458 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3064 19:15:35.092463 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3065 19:15:35.099442 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3066 19:15:35.103054 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3067 19:15:35.105919 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3068 19:15:35.109434 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3069 19:15:35.109518
3070 19:15:35.112973 CA PerBit enable=1, Macro0, CA PI delay=33
3071 19:15:35.113055
3072 19:15:35.115918 [CBTSetCACLKResult] CA Dly = 33
3073 19:15:35.116000 CS Dly: 8 (0~39)
3074 19:15:35.116065 ==
3075 19:15:35.119177 Dram Type= 6, Freq= 0, CH_1, rank 1
3076 19:15:35.125692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 19:15:35.125780 ==
3078 19:15:35.129422 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3079 19:15:35.135994 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3080 19:15:35.145117 [CA 0] Center 37 (7~68) winsize 62
3081 19:15:35.148530 [CA 1] Center 38 (7~69) winsize 63
3082 19:15:35.151369 [CA 2] Center 35 (5~65) winsize 61
3083 19:15:35.154905 [CA 3] Center 34 (4~65) winsize 62
3084 19:15:35.158548 [CA 4] Center 34 (4~65) winsize 62
3085 19:15:35.161479 [CA 5] Center 33 (3~63) winsize 61
3086 19:15:35.161559
3087 19:15:35.165175 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3088 19:15:35.165258
3089 19:15:35.168055 [CATrainingPosCal] consider 2 rank data
3090 19:15:35.171784 u2DelayCellTimex100 = 270/100 ps
3091 19:15:35.174624 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3092 19:15:35.178167 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3093 19:15:35.184960 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3094 19:15:35.188570 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3095 19:15:35.191589 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3096 19:15:35.195276 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3097 19:15:35.195360
3098 19:15:35.198240 CA PerBit enable=1, Macro0, CA PI delay=33
3099 19:15:35.198323
3100 19:15:35.201846 [CBTSetCACLKResult] CA Dly = 33
3101 19:15:35.201932 CS Dly: 9 (0~41)
3102 19:15:35.201998
3103 19:15:35.205422 ----->DramcWriteLeveling(PI) begin...
3104 19:15:35.208474 ==
3105 19:15:35.208556 Dram Type= 6, Freq= 0, CH_1, rank 0
3106 19:15:35.215481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 19:15:35.215568 ==
3108 19:15:35.218398 Write leveling (Byte 0): 24 => 24
3109 19:15:35.222120 Write leveling (Byte 1): 27 => 27
3110 19:15:35.222205 DramcWriteLeveling(PI) end<-----
3111 19:15:35.225008
3112 19:15:35.225089 ==
3113 19:15:35.228680 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 19:15:35.231528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 19:15:35.231612 ==
3116 19:15:35.235007 [Gating] SW mode calibration
3117 19:15:35.241627 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3118 19:15:35.245091 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3119 19:15:35.252106 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3120 19:15:35.255438 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 19:15:35.258591 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 19:15:35.264863 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 19:15:35.268636 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 19:15:35.271471 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 19:15:35.278682 0 15 24 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 0)
3126 19:15:35.281522 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3127 19:15:35.285241 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 19:15:35.292089 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 19:15:35.294999 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 19:15:35.298530 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 19:15:35.305051 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 19:15:35.308540 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 19:15:35.312183 1 0 24 | B1->B0 | 2d2d 3e3e | 0 0 | (0 0) (0 0)
3134 19:15:35.318747 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 19:15:35.321431 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 19:15:35.325038 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 19:15:35.328483 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 19:15:35.335151 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 19:15:35.338109 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 19:15:35.341621 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 19:15:35.348634 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3142 19:15:35.351357 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3143 19:15:35.354985 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 19:15:35.361463 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 19:15:35.365040 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 19:15:35.368631 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 19:15:35.374865 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 19:15:35.378221 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 19:15:35.381808 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 19:15:35.388474 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 19:15:35.391588 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 19:15:35.395196 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 19:15:35.401795 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 19:15:35.405433 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 19:15:35.408519 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 19:15:35.411785 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 19:15:35.419046 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3158 19:15:35.422700 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3159 19:15:35.425494 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 19:15:35.429053 Total UI for P1: 0, mck2ui 16
3161 19:15:35.432490 best dqsien dly found for B0: ( 1, 3, 26)
3162 19:15:35.435542 Total UI for P1: 0, mck2ui 16
3163 19:15:35.439082 best dqsien dly found for B1: ( 1, 3, 26)
3164 19:15:35.441969 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3165 19:15:35.445410 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3166 19:15:35.445494
3167 19:15:35.451953 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3168 19:15:35.455337 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3169 19:15:35.455423 [Gating] SW calibration Done
3170 19:15:35.458927 ==
3171 19:15:35.461878 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 19:15:35.465601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 19:15:35.465685 ==
3174 19:15:35.465749 RX Vref Scan: 0
3175 19:15:35.465809
3176 19:15:35.469206 RX Vref 0 -> 0, step: 1
3177 19:15:35.469287
3178 19:15:35.472225 RX Delay -40 -> 252, step: 8
3179 19:15:35.475893 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3180 19:15:35.478923 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3181 19:15:35.481829 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3182 19:15:35.488561 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3183 19:15:35.492098 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3184 19:15:35.495735 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3185 19:15:35.498571 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3186 19:15:35.502124 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3187 19:15:35.508544 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3188 19:15:35.512061 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3189 19:15:35.515297 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3190 19:15:35.518994 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3191 19:15:35.522024 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3192 19:15:35.528664 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3193 19:15:35.531799 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3194 19:15:35.535240 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3195 19:15:35.535358 ==
3196 19:15:35.538701 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 19:15:35.542458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 19:15:35.542580 ==
3199 19:15:35.545322 DQS Delay:
3200 19:15:35.545408 DQS0 = 0, DQS1 = 0
3201 19:15:35.548912 DQM Delay:
3202 19:15:35.548997 DQM0 = 119, DQM1 = 117
3203 19:15:35.552478 DQ Delay:
3204 19:15:35.555398 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3205 19:15:35.559035 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3206 19:15:35.561902 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3207 19:15:35.565454 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =127
3208 19:15:35.565540
3209 19:15:35.565605
3210 19:15:35.565664 ==
3211 19:15:35.569216 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 19:15:35.572155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 19:15:35.572240 ==
3214 19:15:35.572305
3215 19:15:35.572413
3216 19:15:35.575742 TX Vref Scan disable
3217 19:15:35.578768 == TX Byte 0 ==
3218 19:15:35.582189 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3219 19:15:35.585864 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3220 19:15:35.588890 == TX Byte 1 ==
3221 19:15:35.592477 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3222 19:15:35.595222 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3223 19:15:35.595305 ==
3224 19:15:35.598946 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 19:15:35.601853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 19:15:35.605457 ==
3227 19:15:35.615603 TX Vref=22, minBit 1, minWin=25, winSum=410
3228 19:15:35.618532 TX Vref=24, minBit 9, minWin=25, winSum=413
3229 19:15:35.622044 TX Vref=26, minBit 9, minWin=25, winSum=423
3230 19:15:35.625657 TX Vref=28, minBit 2, minWin=26, winSum=429
3231 19:15:35.628623 TX Vref=30, minBit 9, minWin=25, winSum=429
3232 19:15:35.632122 TX Vref=32, minBit 9, minWin=25, winSum=427
3233 19:15:35.639268 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 28
3234 19:15:35.639363
3235 19:15:35.642050 Final TX Range 1 Vref 28
3236 19:15:35.642134
3237 19:15:35.642199 ==
3238 19:15:35.645373 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 19:15:35.648535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 19:15:35.648620 ==
3241 19:15:35.648688
3242 19:15:35.648749
3243 19:15:35.652495 TX Vref Scan disable
3244 19:15:35.655643 == TX Byte 0 ==
3245 19:15:35.658777 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3246 19:15:35.662021 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3247 19:15:35.665628 == TX Byte 1 ==
3248 19:15:35.669194 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3249 19:15:35.672529 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3250 19:15:35.672614
3251 19:15:35.675798 [DATLAT]
3252 19:15:35.675881 Freq=1200, CH1 RK0
3253 19:15:35.675946
3254 19:15:35.678946 DATLAT Default: 0xd
3255 19:15:35.679054 0, 0xFFFF, sum = 0
3256 19:15:35.682009 1, 0xFFFF, sum = 0
3257 19:15:35.682093 2, 0xFFFF, sum = 0
3258 19:15:35.685705 3, 0xFFFF, sum = 0
3259 19:15:35.685790 4, 0xFFFF, sum = 0
3260 19:15:35.689115 5, 0xFFFF, sum = 0
3261 19:15:35.689200 6, 0xFFFF, sum = 0
3262 19:15:35.692683 7, 0xFFFF, sum = 0
3263 19:15:35.692767 8, 0xFFFF, sum = 0
3264 19:15:35.695598 9, 0xFFFF, sum = 0
3265 19:15:35.695681 10, 0xFFFF, sum = 0
3266 19:15:35.699088 11, 0xFFFF, sum = 0
3267 19:15:35.699173 12, 0x0, sum = 1
3268 19:15:35.702647 13, 0x0, sum = 2
3269 19:15:35.702729 14, 0x0, sum = 3
3270 19:15:35.705443 15, 0x0, sum = 4
3271 19:15:35.705527 best_step = 13
3272 19:15:35.705598
3273 19:15:35.705661 ==
3274 19:15:35.709185 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 19:15:35.715331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 19:15:35.715420 ==
3277 19:15:35.715486 RX Vref Scan: 1
3278 19:15:35.715546
3279 19:15:35.719233 Set Vref Range= 32 -> 127
3280 19:15:35.719315
3281 19:15:35.722199 RX Vref 32 -> 127, step: 1
3282 19:15:35.722282
3283 19:15:35.725731 RX Delay -5 -> 252, step: 4
3284 19:15:35.725815
3285 19:15:35.728770 Set Vref, RX VrefLevel [Byte0]: 32
3286 19:15:35.728853 [Byte1]: 32
3287 19:15:35.733727
3288 19:15:35.733809 Set Vref, RX VrefLevel [Byte0]: 33
3289 19:15:35.736568 [Byte1]: 33
3290 19:15:35.741459
3291 19:15:35.741543 Set Vref, RX VrefLevel [Byte0]: 34
3292 19:15:35.744304 [Byte1]: 34
3293 19:15:35.749474
3294 19:15:35.749561 Set Vref, RX VrefLevel [Byte0]: 35
3295 19:15:35.752322 [Byte1]: 35
3296 19:15:35.757325
3297 19:15:35.757409 Set Vref, RX VrefLevel [Byte0]: 36
3298 19:15:35.760170 [Byte1]: 36
3299 19:15:35.765159
3300 19:15:35.765243 Set Vref, RX VrefLevel [Byte0]: 37
3301 19:15:35.767910 [Byte1]: 37
3302 19:15:35.773090
3303 19:15:35.773248 Set Vref, RX VrefLevel [Byte0]: 38
3304 19:15:35.776037 [Byte1]: 38
3305 19:15:35.780247
3306 19:15:35.780334 Set Vref, RX VrefLevel [Byte0]: 39
3307 19:15:35.783652 [Byte1]: 39
3308 19:15:35.788252
3309 19:15:35.788387 Set Vref, RX VrefLevel [Byte0]: 40
3310 19:15:35.791884 [Byte1]: 40
3311 19:15:35.796624
3312 19:15:35.796709 Set Vref, RX VrefLevel [Byte0]: 41
3313 19:15:35.799991 [Byte1]: 41
3314 19:15:35.804319
3315 19:15:35.804443 Set Vref, RX VrefLevel [Byte0]: 42
3316 19:15:35.807633 [Byte1]: 42
3317 19:15:35.812032
3318 19:15:35.812117 Set Vref, RX VrefLevel [Byte0]: 43
3319 19:15:35.815409 [Byte1]: 43
3320 19:15:35.819819
3321 19:15:35.819976 Set Vref, RX VrefLevel [Byte0]: 44
3322 19:15:35.823471 [Byte1]: 44
3323 19:15:35.827877
3324 19:15:35.827964 Set Vref, RX VrefLevel [Byte0]: 45
3325 19:15:35.830934 [Byte1]: 45
3326 19:15:35.835978
3327 19:15:35.836061 Set Vref, RX VrefLevel [Byte0]: 46
3328 19:15:35.839038 [Byte1]: 46
3329 19:15:35.843432
3330 19:15:35.843514 Set Vref, RX VrefLevel [Byte0]: 47
3331 19:15:35.846889 [Byte1]: 47
3332 19:15:35.851235
3333 19:15:35.851315 Set Vref, RX VrefLevel [Byte0]: 48
3334 19:15:35.854221 [Byte1]: 48
3335 19:15:35.859156
3336 19:15:35.859240 Set Vref, RX VrefLevel [Byte0]: 49
3337 19:15:35.862631 [Byte1]: 49
3338 19:15:35.866895
3339 19:15:35.866976 Set Vref, RX VrefLevel [Byte0]: 50
3340 19:15:35.870347 [Byte1]: 50
3341 19:15:35.875062
3342 19:15:35.875147 Set Vref, RX VrefLevel [Byte0]: 51
3343 19:15:35.878019 [Byte1]: 51
3344 19:15:35.882411
3345 19:15:35.882499 Set Vref, RX VrefLevel [Byte0]: 52
3346 19:15:35.886102 [Byte1]: 52
3347 19:15:35.890709
3348 19:15:35.890794 Set Vref, RX VrefLevel [Byte0]: 53
3349 19:15:35.893656 [Byte1]: 53
3350 19:15:35.898512
3351 19:15:35.898627 Set Vref, RX VrefLevel [Byte0]: 54
3352 19:15:35.901693 [Byte1]: 54
3353 19:15:35.906488
3354 19:15:35.906573 Set Vref, RX VrefLevel [Byte0]: 55
3355 19:15:35.909157 [Byte1]: 55
3356 19:15:35.914180
3357 19:15:35.914261 Set Vref, RX VrefLevel [Byte0]: 56
3358 19:15:35.917078 [Byte1]: 56
3359 19:15:35.921895
3360 19:15:35.921976 Set Vref, RX VrefLevel [Byte0]: 57
3361 19:15:35.925416 [Byte1]: 57
3362 19:15:35.929904
3363 19:15:35.929989 Set Vref, RX VrefLevel [Byte0]: 58
3364 19:15:35.933122 [Byte1]: 58
3365 19:15:35.937835
3366 19:15:35.937924 Set Vref, RX VrefLevel [Byte0]: 59
3367 19:15:35.940710 [Byte1]: 59
3368 19:15:35.945528
3369 19:15:35.945625 Set Vref, RX VrefLevel [Byte0]: 60
3370 19:15:35.948600 [Byte1]: 60
3371 19:15:35.953530
3372 19:15:35.953618 Set Vref, RX VrefLevel [Byte0]: 61
3373 19:15:35.956428 [Byte1]: 61
3374 19:15:35.960807
3375 19:15:35.960894 Set Vref, RX VrefLevel [Byte0]: 62
3376 19:15:35.964516 [Byte1]: 62
3377 19:15:35.968812
3378 19:15:35.968897 Set Vref, RX VrefLevel [Byte0]: 63
3379 19:15:35.972383 [Byte1]: 63
3380 19:15:35.976713
3381 19:15:35.976797 Set Vref, RX VrefLevel [Byte0]: 64
3382 19:15:35.980247 [Byte1]: 64
3383 19:15:35.985116
3384 19:15:35.985205 Set Vref, RX VrefLevel [Byte0]: 65
3385 19:15:35.988072 [Byte1]: 65
3386 19:15:35.992528
3387 19:15:35.992611 Set Vref, RX VrefLevel [Byte0]: 66
3388 19:15:35.996232 [Byte1]: 66
3389 19:15:36.000605
3390 19:15:36.000687 Set Vref, RX VrefLevel [Byte0]: 67
3391 19:15:36.003419 [Byte1]: 67
3392 19:15:36.008404
3393 19:15:36.008484 Set Vref, RX VrefLevel [Byte0]: 68
3394 19:15:36.011304 [Byte1]: 68
3395 19:15:36.016099
3396 19:15:36.016181 Final RX Vref Byte 0 = 53 to rank0
3397 19:15:36.019458 Final RX Vref Byte 1 = 47 to rank0
3398 19:15:36.023027 Final RX Vref Byte 0 = 53 to rank1
3399 19:15:36.025933 Final RX Vref Byte 1 = 47 to rank1==
3400 19:15:36.029434 Dram Type= 6, Freq= 0, CH_1, rank 0
3401 19:15:36.036053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3402 19:15:36.036143 ==
3403 19:15:36.036210 DQS Delay:
3404 19:15:36.036304 DQS0 = 0, DQS1 = 0
3405 19:15:36.039635 DQM Delay:
3406 19:15:36.039717 DQM0 = 120, DQM1 = 115
3407 19:15:36.042477 DQ Delay:
3408 19:15:36.045988 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3409 19:15:36.049402 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3410 19:15:36.052870 DQ8 =102, DQ9 =106, DQ10 =118, DQ11 =108
3411 19:15:36.056118 DQ12 =122, DQ13 =122, DQ14 =122, DQ15 =126
3412 19:15:36.056201
3413 19:15:36.056266
3414 19:15:36.063005 [DQSOSCAuto] RK0, (LSB)MR18= 0x12, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3415 19:15:36.066058 CH1 RK0: MR19=404, MR18=12
3416 19:15:36.072620 CH1_RK0: MR19=0x404, MR18=0x12, DQSOSC=403, MR23=63, INC=40, DEC=26
3417 19:15:36.072708
3418 19:15:36.076234 ----->DramcWriteLeveling(PI) begin...
3419 19:15:36.076319 ==
3420 19:15:36.079288 Dram Type= 6, Freq= 0, CH_1, rank 1
3421 19:15:36.082859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3422 19:15:36.082946 ==
3423 19:15:36.086205 Write leveling (Byte 0): 25 => 25
3424 19:15:36.089672 Write leveling (Byte 1): 28 => 28
3425 19:15:36.092538 DramcWriteLeveling(PI) end<-----
3426 19:15:36.092621
3427 19:15:36.092690 ==
3428 19:15:36.095901 Dram Type= 6, Freq= 0, CH_1, rank 1
3429 19:15:36.099656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 19:15:36.103108 ==
3431 19:15:36.103194 [Gating] SW mode calibration
3432 19:15:36.109582 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3433 19:15:36.116139 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3434 19:15:36.119748 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 19:15:36.126656 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 19:15:36.129535 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 19:15:36.133255 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 19:15:36.139815 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 19:15:36.143553 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3440 19:15:36.146366 0 15 24 | B1->B0 | 2929 3333 | 0 0 | (0 0) (0 0)
3441 19:15:36.149855 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
3442 19:15:36.156213 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 19:15:36.159906 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 19:15:36.163403 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 19:15:36.169649 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 19:15:36.172611 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 19:15:36.176285 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3448 19:15:36.183120 1 0 24 | B1->B0 | 4545 3232 | 0 0 | (0 0) (1 1)
3449 19:15:36.186368 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 19:15:36.189612 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 19:15:36.196163 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 19:15:36.199322 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 19:15:36.203098 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 19:15:36.209421 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 19:15:36.212509 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3456 19:15:36.215993 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3457 19:15:36.222399 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3458 19:15:36.226196 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 19:15:36.229049 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 19:15:36.235908 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 19:15:36.239489 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 19:15:36.242453 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 19:15:36.248933 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 19:15:36.252612 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 19:15:36.256052 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 19:15:36.262484 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 19:15:36.266203 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 19:15:36.269145 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 19:15:36.276065 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 19:15:36.278971 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 19:15:36.282588 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 19:15:36.289122 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3473 19:15:36.292682 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3474 19:15:36.295565 Total UI for P1: 0, mck2ui 16
3475 19:15:36.299314 best dqsien dly found for B1: ( 1, 3, 24)
3476 19:15:36.302249 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 19:15:36.305776 Total UI for P1: 0, mck2ui 16
3478 19:15:36.309457 best dqsien dly found for B0: ( 1, 3, 28)
3479 19:15:36.312184 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3480 19:15:36.315777 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3481 19:15:36.315868
3482 19:15:36.318760 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3483 19:15:36.322358 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3484 19:15:36.325911 [Gating] SW calibration Done
3485 19:15:36.326000 ==
3486 19:15:36.329450 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 19:15:36.335356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 19:15:36.335453 ==
3489 19:15:36.335520 RX Vref Scan: 0
3490 19:15:36.335581
3491 19:15:36.338980 RX Vref 0 -> 0, step: 1
3492 19:15:36.339066
3493 19:15:36.342190 RX Delay -40 -> 252, step: 8
3494 19:15:36.345664 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3495 19:15:36.349131 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3496 19:15:36.352396 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3497 19:15:36.358793 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3498 19:15:36.362204 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3499 19:15:36.365431 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3500 19:15:36.368858 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3501 19:15:36.372230 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3502 19:15:36.375729 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3503 19:15:36.382052 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3504 19:15:36.385781 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3505 19:15:36.388665 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3506 19:15:36.392187 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3507 19:15:36.398784 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3508 19:15:36.402484 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3509 19:15:36.405350 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3510 19:15:36.405444 ==
3511 19:15:36.408407 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 19:15:36.412019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 19:15:36.412106 ==
3514 19:15:36.414972 DQS Delay:
3515 19:15:36.415060 DQS0 = 0, DQS1 = 0
3516 19:15:36.418589 DQM Delay:
3517 19:15:36.418676 DQM0 = 120, DQM1 = 118
3518 19:15:36.418741 DQ Delay:
3519 19:15:36.422110 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3520 19:15:36.428597 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3521 19:15:36.431548 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3522 19:15:36.435234 DQ12 =127, DQ13 =123, DQ14 =123, DQ15 =127
3523 19:15:36.435323
3524 19:15:36.435388
3525 19:15:36.435449 ==
3526 19:15:36.438863 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 19:15:36.441751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 19:15:36.441838 ==
3529 19:15:36.441904
3530 19:15:36.441964
3531 19:15:36.445524 TX Vref Scan disable
3532 19:15:36.448240 == TX Byte 0 ==
3533 19:15:36.451970 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3534 19:15:36.454885 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3535 19:15:36.458435 == TX Byte 1 ==
3536 19:15:36.462080 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3537 19:15:36.465373 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3538 19:15:36.465463 ==
3539 19:15:36.468261 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 19:15:36.471576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 19:15:36.474906 ==
3542 19:15:36.484816 TX Vref=22, minBit 9, minWin=25, winSum=419
3543 19:15:36.488154 TX Vref=24, minBit 1, minWin=26, winSum=424
3544 19:15:36.491452 TX Vref=26, minBit 10, minWin=25, winSum=426
3545 19:15:36.494944 TX Vref=28, minBit 2, minWin=26, winSum=433
3546 19:15:36.498041 TX Vref=30, minBit 9, minWin=26, winSum=435
3547 19:15:36.504911 TX Vref=32, minBit 9, minWin=26, winSum=434
3548 19:15:36.508174 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3549 19:15:36.508267
3550 19:15:36.511567 Final TX Range 1 Vref 30
3551 19:15:36.511654
3552 19:15:36.511719 ==
3553 19:15:36.514926 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 19:15:36.517999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 19:15:36.521195 ==
3556 19:15:36.521303
3557 19:15:36.521370
3558 19:15:36.521430 TX Vref Scan disable
3559 19:15:36.524746 == TX Byte 0 ==
3560 19:15:36.528287 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3561 19:15:36.534955 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3562 19:15:36.535060 == TX Byte 1 ==
3563 19:15:36.537984 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3564 19:15:36.545063 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3565 19:15:36.545161
3566 19:15:36.545228 [DATLAT]
3567 19:15:36.545288 Freq=1200, CH1 RK1
3568 19:15:36.545348
3569 19:15:36.547990 DATLAT Default: 0xd
3570 19:15:36.548073 0, 0xFFFF, sum = 0
3571 19:15:36.551504 1, 0xFFFF, sum = 0
3572 19:15:36.554462 2, 0xFFFF, sum = 0
3573 19:15:36.554557 3, 0xFFFF, sum = 0
3574 19:15:36.558146 4, 0xFFFF, sum = 0
3575 19:15:36.558239 5, 0xFFFF, sum = 0
3576 19:15:36.561054 6, 0xFFFF, sum = 0
3577 19:15:36.561142 7, 0xFFFF, sum = 0
3578 19:15:36.564588 8, 0xFFFF, sum = 0
3579 19:15:36.564677 9, 0xFFFF, sum = 0
3580 19:15:36.568238 10, 0xFFFF, sum = 0
3581 19:15:36.568325 11, 0xFFFF, sum = 0
3582 19:15:36.570961 12, 0x0, sum = 1
3583 19:15:36.571046 13, 0x0, sum = 2
3584 19:15:36.574700 14, 0x0, sum = 3
3585 19:15:36.574799 15, 0x0, sum = 4
3586 19:15:36.574867 best_step = 13
3587 19:15:36.578244
3588 19:15:36.578329 ==
3589 19:15:36.581133 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 19:15:36.584624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 19:15:36.584733 ==
3592 19:15:36.584801 RX Vref Scan: 0
3593 19:15:36.584862
3594 19:15:36.588275 RX Vref 0 -> 0, step: 1
3595 19:15:36.588403
3596 19:15:36.591124 RX Delay -5 -> 252, step: 4
3597 19:15:36.594955 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3598 19:15:36.601575 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3599 19:15:36.604908 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3600 19:15:36.607665 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3601 19:15:36.611098 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3602 19:15:36.614293 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3603 19:15:36.621312 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3604 19:15:36.624250 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3605 19:15:36.627962 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3606 19:15:36.631003 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3607 19:15:36.634692 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3608 19:15:36.641069 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3609 19:15:36.644655 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3610 19:15:36.647650 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3611 19:15:36.651218 iDelay=195, Bit 14, Center 120 (63 ~ 178) 116
3612 19:15:36.654682 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3613 19:15:36.657634 ==
3614 19:15:36.661372 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 19:15:36.664232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 19:15:36.664319 ==
3617 19:15:36.664428 DQS Delay:
3618 19:15:36.667995 DQS0 = 0, DQS1 = 0
3619 19:15:36.668079 DQM Delay:
3620 19:15:36.670760 DQM0 = 120, DQM1 = 116
3621 19:15:36.670843 DQ Delay:
3622 19:15:36.674265 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3623 19:15:36.677914 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3624 19:15:36.681176 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3625 19:15:36.684710 DQ12 =126, DQ13 =124, DQ14 =120, DQ15 =124
3626 19:15:36.684803
3627 19:15:36.684879
3628 19:15:36.694168 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3629 19:15:36.694267 CH1 RK1: MR19=403, MR18=10ED
3630 19:15:36.701120 CH1_RK1: MR19=0x403, MR18=0x10ED, DQSOSC=403, MR23=63, INC=40, DEC=26
3631 19:15:36.704110 [RxdqsGatingPostProcess] freq 1200
3632 19:15:36.711149 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3633 19:15:36.714531 best DQS0 dly(2T, 0.5T) = (0, 11)
3634 19:15:36.717306 best DQS1 dly(2T, 0.5T) = (0, 11)
3635 19:15:36.721011 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3636 19:15:36.724619 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3637 19:15:36.727396 best DQS0 dly(2T, 0.5T) = (0, 11)
3638 19:15:36.730899 best DQS1 dly(2T, 0.5T) = (0, 11)
3639 19:15:36.734398 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3640 19:15:36.737263 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3641 19:15:36.737349 Pre-setting of DQS Precalculation
3642 19:15:36.744279 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3643 19:15:36.750690 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3644 19:15:36.757120 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3645 19:15:36.757228
3646 19:15:36.757299
3647 19:15:36.760486 [Calibration Summary] 2400 Mbps
3648 19:15:36.764318 CH 0, Rank 0
3649 19:15:36.764430 SW Impedance : PASS
3650 19:15:36.767686 DUTY Scan : NO K
3651 19:15:36.770662 ZQ Calibration : PASS
3652 19:15:36.770765 Jitter Meter : NO K
3653 19:15:36.773665 CBT Training : PASS
3654 19:15:36.777416 Write leveling : PASS
3655 19:15:36.777518 RX DQS gating : PASS
3656 19:15:36.780720 RX DQ/DQS(RDDQC) : PASS
3657 19:15:36.780844 TX DQ/DQS : PASS
3658 19:15:36.783512 RX DATLAT : PASS
3659 19:15:36.787249 RX DQ/DQS(Engine): PASS
3660 19:15:36.787334 TX OE : NO K
3661 19:15:36.790838 All Pass.
3662 19:15:36.790923
3663 19:15:36.790988 CH 0, Rank 1
3664 19:15:36.794456 SW Impedance : PASS
3665 19:15:36.794540 DUTY Scan : NO K
3666 19:15:36.797258 ZQ Calibration : PASS
3667 19:15:36.800945 Jitter Meter : NO K
3668 19:15:36.801050 CBT Training : PASS
3669 19:15:36.803672 Write leveling : PASS
3670 19:15:36.807424 RX DQS gating : PASS
3671 19:15:36.807515 RX DQ/DQS(RDDQC) : PASS
3672 19:15:36.810274 TX DQ/DQS : PASS
3673 19:15:36.813751 RX DATLAT : PASS
3674 19:15:36.813838 RX DQ/DQS(Engine): PASS
3675 19:15:36.817151 TX OE : NO K
3676 19:15:36.817238 All Pass.
3677 19:15:36.817305
3678 19:15:36.820565 CH 1, Rank 0
3679 19:15:36.820648 SW Impedance : PASS
3680 19:15:36.824176 DUTY Scan : NO K
3681 19:15:36.827049 ZQ Calibration : PASS
3682 19:15:36.827134 Jitter Meter : NO K
3683 19:15:36.830811 CBT Training : PASS
3684 19:15:36.833633 Write leveling : PASS
3685 19:15:36.833718 RX DQS gating : PASS
3686 19:15:36.837117 RX DQ/DQS(RDDQC) : PASS
3687 19:15:36.837229 TX DQ/DQS : PASS
3688 19:15:36.840613 RX DATLAT : PASS
3689 19:15:36.843444 RX DQ/DQS(Engine): PASS
3690 19:15:36.843529 TX OE : NO K
3691 19:15:36.847037 All Pass.
3692 19:15:36.847121
3693 19:15:36.847186 CH 1, Rank 1
3694 19:15:36.850519 SW Impedance : PASS
3695 19:15:36.850602 DUTY Scan : NO K
3696 19:15:36.853965 ZQ Calibration : PASS
3697 19:15:36.857364 Jitter Meter : NO K
3698 19:15:36.857450 CBT Training : PASS
3699 19:15:36.860194 Write leveling : PASS
3700 19:15:36.863988 RX DQS gating : PASS
3701 19:15:36.864077 RX DQ/DQS(RDDQC) : PASS
3702 19:15:36.866879 TX DQ/DQS : PASS
3703 19:15:36.870626 RX DATLAT : PASS
3704 19:15:36.870713 RX DQ/DQS(Engine): PASS
3705 19:15:36.873386 TX OE : NO K
3706 19:15:36.873470 All Pass.
3707 19:15:36.873536
3708 19:15:36.877035 DramC Write-DBI off
3709 19:15:36.880576 PER_BANK_REFRESH: Hybrid Mode
3710 19:15:36.880660 TX_TRACKING: ON
3711 19:15:36.890135 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3712 19:15:36.893310 [FAST_K] Save calibration result to emmc
3713 19:15:36.897084 dramc_set_vcore_voltage set vcore to 650000
3714 19:15:36.900041 Read voltage for 600, 5
3715 19:15:36.900126 Vio18 = 0
3716 19:15:36.900191 Vcore = 650000
3717 19:15:36.903617 Vdram = 0
3718 19:15:36.903701 Vddq = 0
3719 19:15:36.903766 Vmddr = 0
3720 19:15:36.910422 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3721 19:15:36.913397 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3722 19:15:36.916900 MEM_TYPE=3, freq_sel=19
3723 19:15:36.919942 sv_algorithm_assistance_LP4_1600
3724 19:15:36.923615 ============ PULL DRAM RESETB DOWN ============
3725 19:15:36.926936 ========== PULL DRAM RESETB DOWN end =========
3726 19:15:36.933701 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3727 19:15:36.936617 ===================================
3728 19:15:36.936703 LPDDR4 DRAM CONFIGURATION
3729 19:15:36.940165 ===================================
3730 19:15:36.943008 EX_ROW_EN[0] = 0x0
3731 19:15:36.946538 EX_ROW_EN[1] = 0x0
3732 19:15:36.946620 LP4Y_EN = 0x0
3733 19:15:36.949968 WORK_FSP = 0x0
3734 19:15:36.950051 WL = 0x2
3735 19:15:36.953439 RL = 0x2
3736 19:15:36.953521 BL = 0x2
3737 19:15:36.956447 RPST = 0x0
3738 19:15:36.956532 RD_PRE = 0x0
3739 19:15:36.959972 WR_PRE = 0x1
3740 19:15:36.960055 WR_PST = 0x0
3741 19:15:36.963396 DBI_WR = 0x0
3742 19:15:36.963478 DBI_RD = 0x0
3743 19:15:36.966515 OTF = 0x1
3744 19:15:36.970259 ===================================
3745 19:15:36.973068 ===================================
3746 19:15:36.973154 ANA top config
3747 19:15:36.976750 ===================================
3748 19:15:36.979731 DLL_ASYNC_EN = 0
3749 19:15:36.983291 ALL_SLAVE_EN = 1
3750 19:15:36.986822 NEW_RANK_MODE = 1
3751 19:15:36.986908 DLL_IDLE_MODE = 1
3752 19:15:36.989772 LP45_APHY_COMB_EN = 1
3753 19:15:36.993365 TX_ODT_DIS = 1
3754 19:15:36.996221 NEW_8X_MODE = 1
3755 19:15:36.999755 ===================================
3756 19:15:37.002705 ===================================
3757 19:15:37.006368 data_rate = 1200
3758 19:15:37.006452 CKR = 1
3759 19:15:37.009751 DQ_P2S_RATIO = 8
3760 19:15:37.012585 ===================================
3761 19:15:37.016480 CA_P2S_RATIO = 8
3762 19:15:37.019331 DQ_CA_OPEN = 0
3763 19:15:37.022791 DQ_SEMI_OPEN = 0
3764 19:15:37.026350 CA_SEMI_OPEN = 0
3765 19:15:37.026436 CA_FULL_RATE = 0
3766 19:15:37.029439 DQ_CKDIV4_EN = 1
3767 19:15:37.032638 CA_CKDIV4_EN = 1
3768 19:15:37.035834 CA_PREDIV_EN = 0
3769 19:15:37.039376 PH8_DLY = 0
3770 19:15:37.043098 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3771 19:15:37.043211 DQ_AAMCK_DIV = 4
3772 19:15:37.045972 CA_AAMCK_DIV = 4
3773 19:15:37.049545 CA_ADMCK_DIV = 4
3774 19:15:37.052301 DQ_TRACK_CA_EN = 0
3775 19:15:37.055897 CA_PICK = 600
3776 19:15:37.059558 CA_MCKIO = 600
3777 19:15:37.062613 MCKIO_SEMI = 0
3778 19:15:37.062697 PLL_FREQ = 2288
3779 19:15:37.065493 DQ_UI_PI_RATIO = 32
3780 19:15:37.069168 CA_UI_PI_RATIO = 0
3781 19:15:37.072489 ===================================
3782 19:15:37.075960 ===================================
3783 19:15:37.078915 memory_type:LPDDR4
3784 19:15:37.079003 GP_NUM : 10
3785 19:15:37.082528 SRAM_EN : 1
3786 19:15:37.085526 MD32_EN : 0
3787 19:15:37.088905 ===================================
3788 19:15:37.088991 [ANA_INIT] >>>>>>>>>>>>>>
3789 19:15:37.092578 <<<<<< [CONFIGURE PHASE]: ANA_TX
3790 19:15:37.095491 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3791 19:15:37.099106 ===================================
3792 19:15:37.102117 data_rate = 1200,PCW = 0X5800
3793 19:15:37.105612 ===================================
3794 19:15:37.108562 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3795 19:15:37.115234 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3796 19:15:37.121847 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3797 19:15:37.125468 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3798 19:15:37.128336 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3799 19:15:37.131788 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3800 19:15:37.135091 [ANA_INIT] flow start
3801 19:15:37.135174 [ANA_INIT] PLL >>>>>>>>
3802 19:15:37.138562 [ANA_INIT] PLL <<<<<<<<
3803 19:15:37.142088 [ANA_INIT] MIDPI >>>>>>>>
3804 19:15:37.142171 [ANA_INIT] MIDPI <<<<<<<<
3805 19:15:37.144835 [ANA_INIT] DLL >>>>>>>>
3806 19:15:37.148648 [ANA_INIT] flow end
3807 19:15:37.151961 ============ LP4 DIFF to SE enter ============
3808 19:15:37.154970 ============ LP4 DIFF to SE exit ============
3809 19:15:37.158600 [ANA_INIT] <<<<<<<<<<<<<
3810 19:15:37.161593 [Flow] Enable top DCM control >>>>>
3811 19:15:37.165098 [Flow] Enable top DCM control <<<<<
3812 19:15:37.167992 Enable DLL master slave shuffle
3813 19:15:37.171499 ==============================================================
3814 19:15:37.175068 Gating Mode config
3815 19:15:37.181376 ==============================================================
3816 19:15:37.181464 Config description:
3817 19:15:37.191331 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3818 19:15:37.197764 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3819 19:15:37.205011 SELPH_MODE 0: By rank 1: By Phase
3820 19:15:37.207927 ==============================================================
3821 19:15:37.211478 GAT_TRACK_EN = 1
3822 19:15:37.214368 RX_GATING_MODE = 2
3823 19:15:37.218050 RX_GATING_TRACK_MODE = 2
3824 19:15:37.221488 SELPH_MODE = 1
3825 19:15:37.224363 PICG_EARLY_EN = 1
3826 19:15:37.228140 VALID_LAT_VALUE = 1
3827 19:15:37.230891 ==============================================================
3828 19:15:37.234646 Enter into Gating configuration >>>>
3829 19:15:37.237543 Exit from Gating configuration <<<<
3830 19:15:37.241130 Enter into DVFS_PRE_config >>>>>
3831 19:15:37.254746 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3832 19:15:37.254873 Exit from DVFS_PRE_config <<<<<
3833 19:15:37.257739 Enter into PICG configuration >>>>
3834 19:15:37.261303 Exit from PICG configuration <<<<
3835 19:15:37.264778 [RX_INPUT] configuration >>>>>
3836 19:15:37.267624 [RX_INPUT] configuration <<<<<
3837 19:15:37.274712 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3838 19:15:37.278102 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3839 19:15:37.284496 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3840 19:15:37.291188 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3841 19:15:37.297388 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3842 19:15:37.304190 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3843 19:15:37.307623 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3844 19:15:37.311100 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3845 19:15:37.314389 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3846 19:15:37.320999 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3847 19:15:37.324555 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3848 19:15:37.327605 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3849 19:15:37.330418 ===================================
3850 19:15:37.334035 LPDDR4 DRAM CONFIGURATION
3851 19:15:37.337655 ===================================
3852 19:15:37.340503 EX_ROW_EN[0] = 0x0
3853 19:15:37.340612 EX_ROW_EN[1] = 0x0
3854 19:15:37.344097 LP4Y_EN = 0x0
3855 19:15:37.344179 WORK_FSP = 0x0
3856 19:15:37.347615 WL = 0x2
3857 19:15:37.347696 RL = 0x2
3858 19:15:37.350371 BL = 0x2
3859 19:15:37.350453 RPST = 0x0
3860 19:15:37.354411 RD_PRE = 0x0
3861 19:15:37.354512 WR_PRE = 0x1
3862 19:15:37.357397 WR_PST = 0x0
3863 19:15:37.357488 DBI_WR = 0x0
3864 19:15:37.360202 DBI_RD = 0x0
3865 19:15:37.360316 OTF = 0x1
3866 19:15:37.364024 ===================================
3867 19:15:37.370394 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3868 19:15:37.373471 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3869 19:15:37.377214 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3870 19:15:37.380234 ===================================
3871 19:15:37.384012 LPDDR4 DRAM CONFIGURATION
3872 19:15:37.386969 ===================================
3873 19:15:37.387093 EX_ROW_EN[0] = 0x10
3874 19:15:37.390659 EX_ROW_EN[1] = 0x0
3875 19:15:37.393563 LP4Y_EN = 0x0
3876 19:15:37.393684 WORK_FSP = 0x0
3877 19:15:37.397198 WL = 0x2
3878 19:15:37.397302 RL = 0x2
3879 19:15:37.400852 BL = 0x2
3880 19:15:37.400963 RPST = 0x0
3881 19:15:37.403728 RD_PRE = 0x0
3882 19:15:37.403838 WR_PRE = 0x1
3883 19:15:37.407117 WR_PST = 0x0
3884 19:15:37.407229 DBI_WR = 0x0
3885 19:15:37.410430 DBI_RD = 0x0
3886 19:15:37.410548 OTF = 0x1
3887 19:15:37.413776 ===================================
3888 19:15:37.420438 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3889 19:15:37.424890 nWR fixed to 30
3890 19:15:37.428317 [ModeRegInit_LP4] CH0 RK0
3891 19:15:37.428448 [ModeRegInit_LP4] CH0 RK1
3892 19:15:37.431304 [ModeRegInit_LP4] CH1 RK0
3893 19:15:37.434988 [ModeRegInit_LP4] CH1 RK1
3894 19:15:37.435103 match AC timing 17
3895 19:15:37.441239 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3896 19:15:37.445182 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3897 19:15:37.448184 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3898 19:15:37.454864 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3899 19:15:37.458296 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3900 19:15:37.458421 ==
3901 19:15:37.461737 Dram Type= 6, Freq= 0, CH_0, rank 0
3902 19:15:37.464503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3903 19:15:37.464627 ==
3904 19:15:37.471649 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3905 19:15:37.478140 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3906 19:15:37.481788 [CA 0] Center 36 (5~67) winsize 63
3907 19:15:37.484702 [CA 1] Center 36 (5~67) winsize 63
3908 19:15:37.488364 [CA 2] Center 33 (3~64) winsize 62
3909 19:15:37.491203 [CA 3] Center 33 (2~64) winsize 63
3910 19:15:37.494796 [CA 4] Center 33 (2~64) winsize 63
3911 19:15:37.498382 [CA 5] Center 32 (2~63) winsize 62
3912 19:15:37.498490
3913 19:15:37.501356 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3914 19:15:37.501439
3915 19:15:37.504373 [CATrainingPosCal] consider 1 rank data
3916 19:15:37.508016 u2DelayCellTimex100 = 270/100 ps
3917 19:15:37.511012 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3918 19:15:37.514511 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3919 19:15:37.517935 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3920 19:15:37.521467 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3921 19:15:37.524351 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3922 19:15:37.528089 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3923 19:15:37.528210
3924 19:15:37.534649 CA PerBit enable=1, Macro0, CA PI delay=32
3925 19:15:37.534775
3926 19:15:37.537546 [CBTSetCACLKResult] CA Dly = 32
3927 19:15:37.537655 CS Dly: 4 (0~35)
3928 19:15:37.537758 ==
3929 19:15:37.541241 Dram Type= 6, Freq= 0, CH_0, rank 1
3930 19:15:37.544753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3931 19:15:37.544870 ==
3932 19:15:37.551034 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3933 19:15:37.557657 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3934 19:15:37.560949 [CA 0] Center 35 (5~66) winsize 62
3935 19:15:37.564127 [CA 1] Center 35 (5~66) winsize 62
3936 19:15:37.567846 [CA 2] Center 34 (3~65) winsize 63
3937 19:15:37.570839 [CA 3] Center 33 (2~64) winsize 63
3938 19:15:37.573953 [CA 4] Center 32 (2~63) winsize 62
3939 19:15:37.577675 [CA 5] Center 32 (2~63) winsize 62
3940 19:15:37.577780
3941 19:15:37.580678 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3942 19:15:37.580787
3943 19:15:37.584012 [CATrainingPosCal] consider 2 rank data
3944 19:15:37.587887 u2DelayCellTimex100 = 270/100 ps
3945 19:15:37.591139 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3946 19:15:37.594445 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3947 19:15:37.597830 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3948 19:15:37.600913 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3949 19:15:37.604588 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3950 19:15:37.611238 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3951 19:15:37.611362
3952 19:15:37.614126 CA PerBit enable=1, Macro0, CA PI delay=32
3953 19:15:37.614242
3954 19:15:37.617886 [CBTSetCACLKResult] CA Dly = 32
3955 19:15:37.617999 CS Dly: 4 (0~36)
3956 19:15:37.618095
3957 19:15:37.620693 ----->DramcWriteLeveling(PI) begin...
3958 19:15:37.620803 ==
3959 19:15:37.624161 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 19:15:37.627441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 19:15:37.631085 ==
3962 19:15:37.634077 Write leveling (Byte 0): 35 => 35
3963 19:15:37.634198 Write leveling (Byte 1): 31 => 31
3964 19:15:37.637619 DramcWriteLeveling(PI) end<-----
3965 19:15:37.637723
3966 19:15:37.637827 ==
3967 19:15:37.641131 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 19:15:37.647659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 19:15:37.647777 ==
3970 19:15:37.650572 [Gating] SW mode calibration
3971 19:15:37.657096 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3972 19:15:37.660699 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3973 19:15:37.667237 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3974 19:15:37.670878 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 19:15:37.674337 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 19:15:37.677100 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
3977 19:15:37.684397 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
3978 19:15:37.687196 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 19:15:37.690623 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 19:15:37.697145 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 19:15:37.700422 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 19:15:37.704230 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 19:15:37.710577 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3984 19:15:37.714157 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
3985 19:15:37.717085 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
3986 19:15:37.723460 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 19:15:37.727075 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 19:15:37.730520 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 19:15:37.736906 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 19:15:37.740530 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 19:15:37.743418 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 19:15:37.750603 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3993 19:15:37.753450 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3994 19:15:37.757141 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 19:15:37.763734 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 19:15:37.766433 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 19:15:37.770187 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 19:15:37.776595 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 19:15:37.780278 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 19:15:37.783402 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 19:15:37.789858 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 19:15:37.793529 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 19:15:37.796491 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 19:15:37.803126 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 19:15:37.806594 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 19:15:37.809657 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 19:15:37.816748 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 19:15:37.819408 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4009 19:15:37.822993 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4010 19:15:37.826258 Total UI for P1: 0, mck2ui 16
4011 19:15:37.829703 best dqsien dly found for B0: ( 0, 13, 12)
4012 19:15:37.836571 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 19:15:37.836665 Total UI for P1: 0, mck2ui 16
4014 19:15:37.839524 best dqsien dly found for B1: ( 0, 13, 16)
4015 19:15:37.846317 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4016 19:15:37.849809 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4017 19:15:37.849915
4018 19:15:37.853348 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4019 19:15:37.856461 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4020 19:15:37.860075 [Gating] SW calibration Done
4021 19:15:37.860193 ==
4022 19:15:37.863004 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 19:15:37.866520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 19:15:37.866626 ==
4025 19:15:37.869369 RX Vref Scan: 0
4026 19:15:37.869463
4027 19:15:37.869555 RX Vref 0 -> 0, step: 1
4028 19:15:37.869644
4029 19:15:37.873152 RX Delay -230 -> 252, step: 16
4030 19:15:37.876709 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4031 19:15:37.883128 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4032 19:15:37.886837 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4033 19:15:37.889599 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4034 19:15:37.893029 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4035 19:15:37.896552 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4036 19:15:37.903232 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4037 19:15:37.906331 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4038 19:15:37.909675 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4039 19:15:37.913412 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4040 19:15:37.919854 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4041 19:15:37.923369 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4042 19:15:37.926185 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4043 19:15:37.929881 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4044 19:15:37.936412 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4045 19:15:37.939360 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4046 19:15:37.939472 ==
4047 19:15:37.942928 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 19:15:37.946337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 19:15:37.946454 ==
4050 19:15:37.949717 DQS Delay:
4051 19:15:37.949829 DQS0 = 0, DQS1 = 0
4052 19:15:37.949926 DQM Delay:
4053 19:15:37.953191 DQM0 = 51, DQM1 = 45
4054 19:15:37.953304 DQ Delay:
4055 19:15:37.956702 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4056 19:15:37.959515 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4057 19:15:37.962783 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4058 19:15:37.966519 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4059 19:15:37.966602
4060 19:15:37.966667
4061 19:15:37.966728 ==
4062 19:15:37.969433 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 19:15:37.972939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 19:15:37.976256 ==
4065 19:15:37.976381
4066 19:15:37.976481
4067 19:15:37.976572 TX Vref Scan disable
4068 19:15:37.979356 == TX Byte 0 ==
4069 19:15:37.982717 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4070 19:15:37.986362 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4071 19:15:37.989402 == TX Byte 1 ==
4072 19:15:37.992684 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4073 19:15:37.999828 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4074 19:15:37.999948 ==
4075 19:15:38.002898 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 19:15:38.006322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 19:15:38.006432 ==
4078 19:15:38.006530
4079 19:15:38.006619
4080 19:15:38.009382 TX Vref Scan disable
4081 19:15:38.012997 == TX Byte 0 ==
4082 19:15:38.015898 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4083 19:15:38.019422 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4084 19:15:38.022815 == TX Byte 1 ==
4085 19:15:38.026350 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4086 19:15:38.029244 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4087 19:15:38.029354
4088 19:15:38.029451 [DATLAT]
4089 19:15:38.033066 Freq=600, CH0 RK0
4090 19:15:38.033182
4091 19:15:38.033282 DATLAT Default: 0x9
4092 19:15:38.035872 0, 0xFFFF, sum = 0
4093 19:15:38.035983 1, 0xFFFF, sum = 0
4094 19:15:38.039446 2, 0xFFFF, sum = 0
4095 19:15:38.042668 3, 0xFFFF, sum = 0
4096 19:15:38.042779 4, 0xFFFF, sum = 0
4097 19:15:38.046318 5, 0xFFFF, sum = 0
4098 19:15:38.046427 6, 0xFFFF, sum = 0
4099 19:15:38.049246 7, 0xFFFF, sum = 0
4100 19:15:38.049352 8, 0x0, sum = 1
4101 19:15:38.049457 9, 0x0, sum = 2
4102 19:15:38.052785 10, 0x0, sum = 3
4103 19:15:38.052893 11, 0x0, sum = 4
4104 19:15:38.056220 best_step = 9
4105 19:15:38.056323
4106 19:15:38.056432 ==
4107 19:15:38.059527 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 19:15:38.062541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 19:15:38.062654 ==
4110 19:15:38.066041 RX Vref Scan: 1
4111 19:15:38.066146
4112 19:15:38.066249 RX Vref 0 -> 0, step: 1
4113 19:15:38.066349
4114 19:15:38.069116 RX Delay -163 -> 252, step: 8
4115 19:15:38.069221
4116 19:15:38.072827 Set Vref, RX VrefLevel [Byte0]: 56
4117 19:15:38.075652 [Byte1]: 47
4118 19:15:38.079932
4119 19:15:38.080039 Final RX Vref Byte 0 = 56 to rank0
4120 19:15:38.083170 Final RX Vref Byte 1 = 47 to rank0
4121 19:15:38.086406 Final RX Vref Byte 0 = 56 to rank1
4122 19:15:38.089541 Final RX Vref Byte 1 = 47 to rank1==
4123 19:15:38.093027 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 19:15:38.100051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 19:15:38.100167 ==
4126 19:15:38.100273 DQS Delay:
4127 19:15:38.102730 DQS0 = 0, DQS1 = 0
4128 19:15:38.102829 DQM Delay:
4129 19:15:38.102936 DQM0 = 52, DQM1 = 46
4130 19:15:38.106629 DQ Delay:
4131 19:15:38.109796 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =48
4132 19:15:38.112795 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4133 19:15:38.116285 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4134 19:15:38.119534 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4135 19:15:38.119649
4136 19:15:38.119746
4137 19:15:38.126681 [DQSOSCAuto] RK0, (LSB)MR18= 0x7063, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
4138 19:15:38.129575 CH0 RK0: MR19=808, MR18=7063
4139 19:15:38.136360 CH0_RK0: MR19=0x808, MR18=0x7063, DQSOSC=388, MR23=63, INC=174, DEC=116
4140 19:15:38.136448
4141 19:15:38.139377 ----->DramcWriteLeveling(PI) begin...
4142 19:15:38.139465 ==
4143 19:15:38.143072 Dram Type= 6, Freq= 0, CH_0, rank 1
4144 19:15:38.146029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 19:15:38.146140 ==
4146 19:15:38.149706 Write leveling (Byte 0): 32 => 32
4147 19:15:38.152665 Write leveling (Byte 1): 31 => 31
4148 19:15:38.156247 DramcWriteLeveling(PI) end<-----
4149 19:15:38.156331
4150 19:15:38.156407 ==
4151 19:15:38.159358 Dram Type= 6, Freq= 0, CH_0, rank 1
4152 19:15:38.162783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 19:15:38.162867 ==
4154 19:15:38.166377 [Gating] SW mode calibration
4155 19:15:38.172754 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4156 19:15:38.179389 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4157 19:15:38.182326 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4158 19:15:38.188977 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4159 19:15:38.192572 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 19:15:38.195463 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
4161 19:15:38.202454 0 9 16 | B1->B0 | 2a2a 2626 | 0 0 | (0 0) (0 0)
4162 19:15:38.205414 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 19:15:38.209004 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 19:15:38.215805 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 19:15:38.218996 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 19:15:38.222262 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 19:15:38.229148 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 19:15:38.232320 0 10 12 | B1->B0 | 2929 2626 | 0 0 | (0 0) (0 0)
4169 19:15:38.235363 0 10 16 | B1->B0 | 3c3c 4444 | 0 0 | (0 0) (0 0)
4170 19:15:38.242227 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 19:15:38.245636 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 19:15:38.249147 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 19:15:38.252516 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 19:15:38.259195 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 19:15:38.261884 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 19:15:38.265651 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 19:15:38.272085 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 19:15:38.275679 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 19:15:38.279124 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 19:15:38.285619 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 19:15:38.288538 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 19:15:38.292173 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 19:15:38.298652 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 19:15:38.302285 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 19:15:38.305048 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 19:15:38.312237 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 19:15:38.315578 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 19:15:38.318941 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 19:15:38.325164 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 19:15:38.328624 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 19:15:38.332052 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 19:15:38.338801 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 19:15:38.341695 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 19:15:38.345296 Total UI for P1: 0, mck2ui 16
4195 19:15:38.348773 best dqsien dly found for B0: ( 0, 13, 14)
4196 19:15:38.352146 Total UI for P1: 0, mck2ui 16
4197 19:15:38.355403 best dqsien dly found for B1: ( 0, 13, 14)
4198 19:15:38.358712 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4199 19:15:38.362039 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4200 19:15:38.362154
4201 19:15:38.365205 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4202 19:15:38.368277 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4203 19:15:38.371954 [Gating] SW calibration Done
4204 19:15:38.372069 ==
4205 19:15:38.375401 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 19:15:38.378394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 19:15:38.378509 ==
4208 19:15:38.381577 RX Vref Scan: 0
4209 19:15:38.381688
4210 19:15:38.385113 RX Vref 0 -> 0, step: 1
4211 19:15:38.385228
4212 19:15:38.388527 RX Delay -230 -> 252, step: 16
4213 19:15:38.392107 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4214 19:15:38.395081 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4215 19:15:38.398140 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4216 19:15:38.401960 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4217 19:15:38.408395 iDelay=218, Bit 4, Center 65 (-86 ~ 217) 304
4218 19:15:38.412005 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4219 19:15:38.414990 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4220 19:15:38.417904 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4221 19:15:38.424464 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4222 19:15:38.428024 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4223 19:15:38.431378 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4224 19:15:38.434891 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4225 19:15:38.438379 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4226 19:15:38.444482 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4227 19:15:38.448014 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4228 19:15:38.451525 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4229 19:15:38.451617 ==
4230 19:15:38.454597 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 19:15:38.461168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 19:15:38.461264 ==
4233 19:15:38.461332 DQS Delay:
4234 19:15:38.461394 DQS0 = 0, DQS1 = 0
4235 19:15:38.464791 DQM Delay:
4236 19:15:38.464876 DQM0 = 54, DQM1 = 43
4237 19:15:38.468241 DQ Delay:
4238 19:15:38.471007 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4239 19:15:38.474731 DQ4 =65, DQ5 =41, DQ6 =65, DQ7 =65
4240 19:15:38.474821 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4241 19:15:38.481260 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4242 19:15:38.481357
4243 19:15:38.481425
4244 19:15:38.481487 ==
4245 19:15:38.484692 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 19:15:38.488035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 19:15:38.488157 ==
4248 19:15:38.488255
4249 19:15:38.488353
4250 19:15:38.491477 TX Vref Scan disable
4251 19:15:38.491562 == TX Byte 0 ==
4252 19:15:38.497705 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4253 19:15:38.501059 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4254 19:15:38.501152 == TX Byte 1 ==
4255 19:15:38.507477 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4256 19:15:38.511191 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4257 19:15:38.511337 ==
4258 19:15:38.514501 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 19:15:38.517888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 19:15:38.518020 ==
4261 19:15:38.518116
4262 19:15:38.520832
4263 19:15:38.520922 TX Vref Scan disable
4264 19:15:38.524263 == TX Byte 0 ==
4265 19:15:38.527981 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4266 19:15:38.534659 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4267 19:15:38.534802 == TX Byte 1 ==
4268 19:15:38.537617 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4269 19:15:38.544295 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4270 19:15:38.544453
4271 19:15:38.544554 [DATLAT]
4272 19:15:38.544650 Freq=600, CH0 RK1
4273 19:15:38.544743
4274 19:15:38.547985 DATLAT Default: 0x9
4275 19:15:38.548098 0, 0xFFFF, sum = 0
4276 19:15:38.550709 1, 0xFFFF, sum = 0
4277 19:15:38.550821 2, 0xFFFF, sum = 0
4278 19:15:38.554101 3, 0xFFFF, sum = 0
4279 19:15:38.554215 4, 0xFFFF, sum = 0
4280 19:15:38.557436 5, 0xFFFF, sum = 0
4281 19:15:38.560977 6, 0xFFFF, sum = 0
4282 19:15:38.561096 7, 0xFFFF, sum = 0
4283 19:15:38.561192 8, 0x0, sum = 1
4284 19:15:38.564513 9, 0x0, sum = 2
4285 19:15:38.564628 10, 0x0, sum = 3
4286 19:15:38.567445 11, 0x0, sum = 4
4287 19:15:38.567539 best_step = 9
4288 19:15:38.567607
4289 19:15:38.567669 ==
4290 19:15:38.570945 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 19:15:38.577389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 19:15:38.577526 ==
4293 19:15:38.577632 RX Vref Scan: 0
4294 19:15:38.577725
4295 19:15:38.581108 RX Vref 0 -> 0, step: 1
4296 19:15:38.581224
4297 19:15:38.583849 RX Delay -163 -> 252, step: 8
4298 19:15:38.587573 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4299 19:15:38.591090 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4300 19:15:38.597725 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4301 19:15:38.600723 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4302 19:15:38.604263 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4303 19:15:38.607617 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4304 19:15:38.611023 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4305 19:15:38.617297 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4306 19:15:38.621184 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4307 19:15:38.624249 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4308 19:15:38.627446 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4309 19:15:38.633810 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4310 19:15:38.637688 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4311 19:15:38.640749 iDelay=197, Bit 13, Center 48 (-91 ~ 188) 280
4312 19:15:38.643949 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4313 19:15:38.647476 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4314 19:15:38.650395 ==
4315 19:15:38.650484 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 19:15:38.657014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 19:15:38.657111 ==
4318 19:15:38.657178 DQS Delay:
4319 19:15:38.660667 DQS0 = 0, DQS1 = 0
4320 19:15:38.660778 DQM Delay:
4321 19:15:38.663609 DQM0 = 53, DQM1 = 46
4322 19:15:38.663721 DQ Delay:
4323 19:15:38.667127 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4324 19:15:38.670631 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60
4325 19:15:38.674023 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4326 19:15:38.677313 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4327 19:15:38.677401
4328 19:15:38.677467
4329 19:15:38.683565 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e1f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
4330 19:15:38.687028 CH0 RK1: MR19=808, MR18=5E1F
4331 19:15:38.693564 CH0_RK1: MR19=0x808, MR18=0x5E1F, DQSOSC=392, MR23=63, INC=170, DEC=113
4332 19:15:38.697295 [RxdqsGatingPostProcess] freq 600
4333 19:15:38.703928 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4334 19:15:38.704032 Pre-setting of DQS Precalculation
4335 19:15:38.710587 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4336 19:15:38.710691 ==
4337 19:15:38.713453 Dram Type= 6, Freq= 0, CH_1, rank 0
4338 19:15:38.717257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 19:15:38.717344 ==
4340 19:15:38.723545 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4341 19:15:38.730437 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4342 19:15:38.733970 [CA 0] Center 36 (5~67) winsize 63
4343 19:15:38.736711 [CA 1] Center 36 (5~67) winsize 63
4344 19:15:38.739986 [CA 2] Center 34 (4~65) winsize 62
4345 19:15:38.743684 [CA 3] Center 34 (4~65) winsize 62
4346 19:15:38.747196 [CA 4] Center 34 (4~65) winsize 62
4347 19:15:38.750054 [CA 5] Center 34 (3~65) winsize 63
4348 19:15:38.750165
4349 19:15:38.753419 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4350 19:15:38.753531
4351 19:15:38.756769 [CATrainingPosCal] consider 1 rank data
4352 19:15:38.760096 u2DelayCellTimex100 = 270/100 ps
4353 19:15:38.763351 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4354 19:15:38.766741 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4355 19:15:38.770287 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4356 19:15:38.773183 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4357 19:15:38.776871 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4358 19:15:38.779765 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4359 19:15:38.779852
4360 19:15:38.786898 CA PerBit enable=1, Macro0, CA PI delay=34
4361 19:15:38.786995
4362 19:15:38.787068 [CBTSetCACLKResult] CA Dly = 34
4363 19:15:38.790094 CS Dly: 5 (0~36)
4364 19:15:38.790183 ==
4365 19:15:38.793061 Dram Type= 6, Freq= 0, CH_1, rank 1
4366 19:15:38.796445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 19:15:38.796536 ==
4368 19:15:38.803034 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4369 19:15:38.809628 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4370 19:15:38.813122 [CA 0] Center 36 (5~67) winsize 63
4371 19:15:38.816863 [CA 1] Center 36 (5~67) winsize 63
4372 19:15:38.819834 [CA 2] Center 35 (5~65) winsize 61
4373 19:15:38.823483 [CA 3] Center 34 (4~65) winsize 62
4374 19:15:38.826352 [CA 4] Center 34 (4~65) winsize 62
4375 19:15:38.829808 [CA 5] Center 34 (3~65) winsize 63
4376 19:15:38.829936
4377 19:15:38.833379 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4378 19:15:38.833495
4379 19:15:38.836307 [CATrainingPosCal] consider 2 rank data
4380 19:15:38.839861 u2DelayCellTimex100 = 270/100 ps
4381 19:15:38.843299 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4382 19:15:38.846714 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4383 19:15:38.850256 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4384 19:15:38.853050 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4385 19:15:38.856668 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4386 19:15:38.863256 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4387 19:15:38.863377
4388 19:15:38.866666 CA PerBit enable=1, Macro0, CA PI delay=34
4389 19:15:38.866756
4390 19:15:38.869453 [CBTSetCACLKResult] CA Dly = 34
4391 19:15:38.869538 CS Dly: 5 (0~37)
4392 19:15:38.869605
4393 19:15:38.872978 ----->DramcWriteLeveling(PI) begin...
4394 19:15:38.873065 ==
4395 19:15:38.876266 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 19:15:38.879600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 19:15:38.883209 ==
4398 19:15:38.883302 Write leveling (Byte 0): 29 => 29
4399 19:15:38.886241 Write leveling (Byte 1): 29 => 29
4400 19:15:38.889921 DramcWriteLeveling(PI) end<-----
4401 19:15:38.890014
4402 19:15:38.890082 ==
4403 19:15:38.893585 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 19:15:38.900005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 19:15:38.900134 ==
4406 19:15:38.900236 [Gating] SW mode calibration
4407 19:15:38.910010 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4408 19:15:38.912938 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4409 19:15:38.916503 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4410 19:15:38.922616 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4411 19:15:38.926075 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4412 19:15:38.929323 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (1 1) (1 1)
4413 19:15:38.936275 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 19:15:38.939541 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 19:15:38.942938 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 19:15:38.949584 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 19:15:38.952924 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 19:15:38.956032 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 19:15:38.962381 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 19:15:38.966118 0 10 12 | B1->B0 | 3434 3737 | 0 0 | (0 0) (0 0)
4421 19:15:38.969548 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 19:15:38.976200 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 19:15:38.979234 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 19:15:38.982802 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 19:15:38.989104 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 19:15:38.992377 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 19:15:38.995760 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4428 19:15:39.002264 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4429 19:15:39.005798 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 19:15:39.009552 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 19:15:39.016278 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 19:15:39.019181 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 19:15:39.022876 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 19:15:39.029351 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 19:15:39.032937 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 19:15:39.035730 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 19:15:39.039365 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 19:15:39.046112 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 19:15:39.049297 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 19:15:39.052285 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 19:15:39.059071 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 19:15:39.062219 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 19:15:39.066004 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4444 19:15:39.072458 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 19:15:39.075645 Total UI for P1: 0, mck2ui 16
4446 19:15:39.078719 best dqsien dly found for B0: ( 0, 13, 8)
4447 19:15:39.081944 Total UI for P1: 0, mck2ui 16
4448 19:15:39.085297 best dqsien dly found for B1: ( 0, 13, 10)
4449 19:15:39.088855 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4450 19:15:39.091656 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4451 19:15:39.091766
4452 19:15:39.095325 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4453 19:15:39.098966 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4454 19:15:39.102170 [Gating] SW calibration Done
4455 19:15:39.102285 ==
4456 19:15:39.105596 Dram Type= 6, Freq= 0, CH_1, rank 0
4457 19:15:39.108974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 19:15:39.109092 ==
4459 19:15:39.111970 RX Vref Scan: 0
4460 19:15:39.112086
4461 19:15:39.115524 RX Vref 0 -> 0, step: 1
4462 19:15:39.115633
4463 19:15:39.115733 RX Delay -230 -> 252, step: 16
4464 19:15:39.122161 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4465 19:15:39.125137 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4466 19:15:39.128990 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4467 19:15:39.131802 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4468 19:15:39.139031 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4469 19:15:39.141828 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4470 19:15:39.145527 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4471 19:15:39.148428 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4472 19:15:39.152217 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4473 19:15:39.158734 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4474 19:15:39.161548 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4475 19:15:39.164962 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4476 19:15:39.168510 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4477 19:15:39.175153 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4478 19:15:39.178384 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4479 19:15:39.181831 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4480 19:15:39.181955 ==
4481 19:15:39.185014 Dram Type= 6, Freq= 0, CH_1, rank 0
4482 19:15:39.188316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4483 19:15:39.188423 ==
4484 19:15:39.191747 DQS Delay:
4485 19:15:39.191830 DQS0 = 0, DQS1 = 0
4486 19:15:39.195191 DQM Delay:
4487 19:15:39.195270 DQM0 = 47, DQM1 = 49
4488 19:15:39.195334 DQ Delay:
4489 19:15:39.198380 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4490 19:15:39.202062 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4491 19:15:39.205044 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4492 19:15:39.208290 DQ12 =65, DQ13 =57, DQ14 =49, DQ15 =65
4493 19:15:39.208406
4494 19:15:39.208493
4495 19:15:39.211682 ==
4496 19:15:39.211795 Dram Type= 6, Freq= 0, CH_1, rank 0
4497 19:15:39.218580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4498 19:15:39.218709 ==
4499 19:15:39.218807
4500 19:15:39.218907
4501 19:15:39.221356 TX Vref Scan disable
4502 19:15:39.221470 == TX Byte 0 ==
4503 19:15:39.228012 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4504 19:15:39.231742 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4505 19:15:39.231853 == TX Byte 1 ==
4506 19:15:39.235390 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4507 19:15:39.241895 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4508 19:15:39.241990 ==
4509 19:15:39.244981 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 19:15:39.248533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 19:15:39.248648 ==
4512 19:15:39.248744
4513 19:15:39.248805
4514 19:15:39.251520 TX Vref Scan disable
4515 19:15:39.255127 == TX Byte 0 ==
4516 19:15:39.258086 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4517 19:15:39.261622 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4518 19:15:39.265183 == TX Byte 1 ==
4519 19:15:39.268152 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4520 19:15:39.271729 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4521 19:15:39.271817
4522 19:15:39.274626 [DATLAT]
4523 19:15:39.274725 Freq=600, CH1 RK0
4524 19:15:39.274818
4525 19:15:39.278308 DATLAT Default: 0x9
4526 19:15:39.278382 0, 0xFFFF, sum = 0
4527 19:15:39.281723 1, 0xFFFF, sum = 0
4528 19:15:39.281815 2, 0xFFFF, sum = 0
4529 19:15:39.285227 3, 0xFFFF, sum = 0
4530 19:15:39.285340 4, 0xFFFF, sum = 0
4531 19:15:39.288564 5, 0xFFFF, sum = 0
4532 19:15:39.288661 6, 0xFFFF, sum = 0
4533 19:15:39.291933 7, 0xFFFF, sum = 0
4534 19:15:39.292047 8, 0x0, sum = 1
4535 19:15:39.295216 9, 0x0, sum = 2
4536 19:15:39.295355 10, 0x0, sum = 3
4537 19:15:39.297966 11, 0x0, sum = 4
4538 19:15:39.298079 best_step = 9
4539 19:15:39.298179
4540 19:15:39.298289 ==
4541 19:15:39.301360 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 19:15:39.304903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 19:15:39.305025 ==
4544 19:15:39.307749 RX Vref Scan: 1
4545 19:15:39.307894
4546 19:15:39.311210 RX Vref 0 -> 0, step: 1
4547 19:15:39.311394
4548 19:15:39.311489 RX Delay -163 -> 252, step: 8
4549 19:15:39.314588
4550 19:15:39.314699 Set Vref, RX VrefLevel [Byte0]: 53
4551 19:15:39.317722 [Byte1]: 47
4552 19:15:39.323126
4553 19:15:39.323253 Final RX Vref Byte 0 = 53 to rank0
4554 19:15:39.326207 Final RX Vref Byte 1 = 47 to rank0
4555 19:15:39.329226 Final RX Vref Byte 0 = 53 to rank1
4556 19:15:39.332568 Final RX Vref Byte 1 = 47 to rank1==
4557 19:15:39.336317 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 19:15:39.342961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 19:15:39.343105 ==
4560 19:15:39.343210 DQS Delay:
4561 19:15:39.343303 DQS0 = 0, DQS1 = 0
4562 19:15:39.346308 DQM Delay:
4563 19:15:39.346417 DQM0 = 47, DQM1 = 46
4564 19:15:39.349270 DQ Delay:
4565 19:15:39.352942 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4566 19:15:39.356493 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4567 19:15:39.356607 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4568 19:15:39.363102 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4569 19:15:39.363214
4570 19:15:39.363314
4571 19:15:39.369565 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b71, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4572 19:15:39.372959 CH1 RK0: MR19=808, MR18=4B71
4573 19:15:39.379210 CH1_RK0: MR19=0x808, MR18=0x4B71, DQSOSC=388, MR23=63, INC=174, DEC=116
4574 19:15:39.379331
4575 19:15:39.382800 ----->DramcWriteLeveling(PI) begin...
4576 19:15:39.382914 ==
4577 19:15:39.386421 Dram Type= 6, Freq= 0, CH_1, rank 1
4578 19:15:39.389367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 19:15:39.389483 ==
4580 19:15:39.392869 Write leveling (Byte 0): 31 => 31
4581 19:15:39.395805 Write leveling (Byte 1): 31 => 31
4582 19:15:39.399241 DramcWriteLeveling(PI) end<-----
4583 19:15:39.399361
4584 19:15:39.399460 ==
4585 19:15:39.402660 Dram Type= 6, Freq= 0, CH_1, rank 1
4586 19:15:39.406065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 19:15:39.406182 ==
4588 19:15:39.408895 [Gating] SW mode calibration
4589 19:15:39.415420 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4590 19:15:39.422841 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4591 19:15:39.425593 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4592 19:15:39.432599 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4593 19:15:39.435352 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4594 19:15:39.438677 0 9 12 | B1->B0 | 2a2a 2e2e | 1 1 | (1 0) (1 0)
4595 19:15:39.442126 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4596 19:15:39.449222 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 19:15:39.452462 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 19:15:39.455906 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 19:15:39.461986 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 19:15:39.465523 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 19:15:39.469152 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 19:15:39.475657 0 10 12 | B1->B0 | 3a3a 3433 | 0 1 | (0 0) (0 0)
4603 19:15:39.478408 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 19:15:39.481910 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 19:15:39.488998 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 19:15:39.492507 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 19:15:39.495238 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 19:15:39.501814 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 19:15:39.505513 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 19:15:39.508936 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 19:15:39.515092 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4612 19:15:39.518406 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 19:15:39.522176 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 19:15:39.528564 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 19:15:39.532248 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 19:15:39.535227 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 19:15:39.541922 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 19:15:39.545300 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 19:15:39.548575 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 19:15:39.555400 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 19:15:39.558371 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 19:15:39.561892 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 19:15:39.568637 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 19:15:39.571749 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 19:15:39.575026 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4626 19:15:39.578720 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4627 19:15:39.581576 Total UI for P1: 0, mck2ui 16
4628 19:15:39.585157 best dqsien dly found for B1: ( 0, 13, 8)
4629 19:15:39.591573 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4630 19:15:39.595017 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 19:15:39.598396 Total UI for P1: 0, mck2ui 16
4632 19:15:39.601906 best dqsien dly found for B0: ( 0, 13, 14)
4633 19:15:39.605363 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4634 19:15:39.608419 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4635 19:15:39.608531
4636 19:15:39.611847 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4637 19:15:39.615382 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4638 19:15:39.618163 [Gating] SW calibration Done
4639 19:15:39.618275 ==
4640 19:15:39.621635 Dram Type= 6, Freq= 0, CH_1, rank 1
4641 19:15:39.628776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 19:15:39.628902 ==
4643 19:15:39.629002 RX Vref Scan: 0
4644 19:15:39.629096
4645 19:15:39.631569 RX Vref 0 -> 0, step: 1
4646 19:15:39.631679
4647 19:15:39.635158 RX Delay -230 -> 252, step: 16
4648 19:15:39.638029 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4649 19:15:39.641494 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4650 19:15:39.645142 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4651 19:15:39.651634 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4652 19:15:39.655072 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4653 19:15:39.658020 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4654 19:15:39.661247 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4655 19:15:39.664680 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4656 19:15:39.671277 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4657 19:15:39.674881 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4658 19:15:39.678374 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4659 19:15:39.681132 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4660 19:15:39.687830 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4661 19:15:39.691359 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4662 19:15:39.695056 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4663 19:15:39.697897 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4664 19:15:39.698008 ==
4665 19:15:39.701524 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 19:15:39.708230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 19:15:39.708358 ==
4668 19:15:39.708459 DQS Delay:
4669 19:15:39.711109 DQS0 = 0, DQS1 = 0
4670 19:15:39.711219 DQM Delay:
4671 19:15:39.714759 DQM0 = 51, DQM1 = 48
4672 19:15:39.714873 DQ Delay:
4673 19:15:39.718203 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4674 19:15:39.721124 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4675 19:15:39.724745 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =49
4676 19:15:39.728170 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4677 19:15:39.728285
4678 19:15:39.728388
4679 19:15:39.728484 ==
4680 19:15:39.731740 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 19:15:39.734448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 19:15:39.734565 ==
4683 19:15:39.734668
4684 19:15:39.734761
4685 19:15:39.738148 TX Vref Scan disable
4686 19:15:39.741567 == TX Byte 0 ==
4687 19:15:39.744374 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4688 19:15:39.747869 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4689 19:15:39.751548 == TX Byte 1 ==
4690 19:15:39.755065 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4691 19:15:39.757998 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4692 19:15:39.758109 ==
4693 19:15:39.761589 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 19:15:39.764498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 19:15:39.764611 ==
4696 19:15:39.768013
4697 19:15:39.768119
4698 19:15:39.768212 TX Vref Scan disable
4699 19:15:39.771911 == TX Byte 0 ==
4700 19:15:39.775328 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4701 19:15:39.781776 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4702 19:15:39.781894 == TX Byte 1 ==
4703 19:15:39.784840 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4704 19:15:39.791677 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4705 19:15:39.791793
4706 19:15:39.791889 [DATLAT]
4707 19:15:39.791980 Freq=600, CH1 RK1
4708 19:15:39.792071
4709 19:15:39.794500 DATLAT Default: 0x9
4710 19:15:39.794608 0, 0xFFFF, sum = 0
4711 19:15:39.798067 1, 0xFFFF, sum = 0
4712 19:15:39.798179 2, 0xFFFF, sum = 0
4713 19:15:39.801315 3, 0xFFFF, sum = 0
4714 19:15:39.804614 4, 0xFFFF, sum = 0
4715 19:15:39.804730 5, 0xFFFF, sum = 0
4716 19:15:39.808224 6, 0xFFFF, sum = 0
4717 19:15:39.808334 7, 0xFFFF, sum = 0
4718 19:15:39.811713 8, 0x0, sum = 1
4719 19:15:39.811823 9, 0x0, sum = 2
4720 19:15:39.811921 10, 0x0, sum = 3
4721 19:15:39.815094 11, 0x0, sum = 4
4722 19:15:39.815205 best_step = 9
4723 19:15:39.815297
4724 19:15:39.815386 ==
4725 19:15:39.818499 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 19:15:39.824618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 19:15:39.824736 ==
4728 19:15:39.824832 RX Vref Scan: 0
4729 19:15:39.824930
4730 19:15:39.828263 RX Vref 0 -> 0, step: 1
4731 19:15:39.828377
4732 19:15:39.831145 RX Delay -163 -> 252, step: 8
4733 19:15:39.834956 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4734 19:15:39.841249 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4735 19:15:39.844588 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4736 19:15:39.848204 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4737 19:15:39.851739 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4738 19:15:39.854840 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4739 19:15:39.861340 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4740 19:15:39.864967 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4741 19:15:39.867810 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4742 19:15:39.871504 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4743 19:15:39.874471 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4744 19:15:39.881258 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4745 19:15:39.884471 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4746 19:15:39.888095 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4747 19:15:39.891004 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4748 19:15:39.894551 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4749 19:15:39.898066 ==
4750 19:15:39.901492 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 19:15:39.904471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 19:15:39.904584 ==
4753 19:15:39.904682 DQS Delay:
4754 19:15:39.908083 DQS0 = 0, DQS1 = 0
4755 19:15:39.908195 DQM Delay:
4756 19:15:39.911010 DQM0 = 49, DQM1 = 44
4757 19:15:39.911121 DQ Delay:
4758 19:15:39.914354 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4759 19:15:39.917660 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4760 19:15:39.920824 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =36
4761 19:15:39.924202 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4762 19:15:39.924314
4763 19:15:39.924418
4764 19:15:39.930951 [DQSOSCAuto] RK1, (LSB)MR18= 0x691f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4765 19:15:39.934636 CH1 RK1: MR19=808, MR18=691F
4766 19:15:39.941034 CH1_RK1: MR19=0x808, MR18=0x691F, DQSOSC=390, MR23=63, INC=172, DEC=114
4767 19:15:39.944620 [RxdqsGatingPostProcess] freq 600
4768 19:15:39.951324 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4769 19:15:39.951451 Pre-setting of DQS Precalculation
4770 19:15:39.957548 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4771 19:15:39.964742 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4772 19:15:39.971218 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4773 19:15:39.971319
4774 19:15:39.971386
4775 19:15:39.974154 [Calibration Summary] 1200 Mbps
4776 19:15:39.977830 CH 0, Rank 0
4777 19:15:39.977905 SW Impedance : PASS
4778 19:15:39.980805 DUTY Scan : NO K
4779 19:15:39.984569 ZQ Calibration : PASS
4780 19:15:39.984684 Jitter Meter : NO K
4781 19:15:39.987445 CBT Training : PASS
4782 19:15:39.987553 Write leveling : PASS
4783 19:15:39.990932 RX DQS gating : PASS
4784 19:15:39.994382 RX DQ/DQS(RDDQC) : PASS
4785 19:15:39.994498 TX DQ/DQS : PASS
4786 19:15:39.997525 RX DATLAT : PASS
4787 19:15:40.001110 RX DQ/DQS(Engine): PASS
4788 19:15:40.001228 TX OE : NO K
4789 19:15:40.003920 All Pass.
4790 19:15:40.004032
4791 19:15:40.004130 CH 0, Rank 1
4792 19:15:40.007471 SW Impedance : PASS
4793 19:15:40.007585 DUTY Scan : NO K
4794 19:15:40.011109 ZQ Calibration : PASS
4795 19:15:40.014134 Jitter Meter : NO K
4796 19:15:40.014251 CBT Training : PASS
4797 19:15:40.017812 Write leveling : PASS
4798 19:15:40.020653 RX DQS gating : PASS
4799 19:15:40.020768 RX DQ/DQS(RDDQC) : PASS
4800 19:15:40.024248 TX DQ/DQS : PASS
4801 19:15:40.027789 RX DATLAT : PASS
4802 19:15:40.027901 RX DQ/DQS(Engine): PASS
4803 19:15:40.030500 TX OE : NO K
4804 19:15:40.030614 All Pass.
4805 19:15:40.030709
4806 19:15:40.033866 CH 1, Rank 0
4807 19:15:40.033982 SW Impedance : PASS
4808 19:15:40.037351 DUTY Scan : NO K
4809 19:15:40.037461 ZQ Calibration : PASS
4810 19:15:40.040865 Jitter Meter : NO K
4811 19:15:40.043679 CBT Training : PASS
4812 19:15:40.043794 Write leveling : PASS
4813 19:15:40.046951 RX DQS gating : PASS
4814 19:15:40.050199 RX DQ/DQS(RDDQC) : PASS
4815 19:15:40.050309 TX DQ/DQS : PASS
4816 19:15:40.053956 RX DATLAT : PASS
4817 19:15:40.057417 RX DQ/DQS(Engine): PASS
4818 19:15:40.057509 TX OE : NO K
4819 19:15:40.060831 All Pass.
4820 19:15:40.060914
4821 19:15:40.060980 CH 1, Rank 1
4822 19:15:40.063661 SW Impedance : PASS
4823 19:15:40.063737 DUTY Scan : NO K
4824 19:15:40.067440 ZQ Calibration : PASS
4825 19:15:40.070483 Jitter Meter : NO K
4826 19:15:40.070560 CBT Training : PASS
4827 19:15:40.074115 Write leveling : PASS
4828 19:15:40.076983 RX DQS gating : PASS
4829 19:15:40.077070 RX DQ/DQS(RDDQC) : PASS
4830 19:15:40.080506 TX DQ/DQS : PASS
4831 19:15:40.084159 RX DATLAT : PASS
4832 19:15:40.084267 RX DQ/DQS(Engine): PASS
4833 19:15:40.087108 TX OE : NO K
4834 19:15:40.087194 All Pass.
4835 19:15:40.087261
4836 19:15:40.090801 DramC Write-DBI off
4837 19:15:40.093784 PER_BANK_REFRESH: Hybrid Mode
4838 19:15:40.093862 TX_TRACKING: ON
4839 19:15:40.103509 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4840 19:15:40.106860 [FAST_K] Save calibration result to emmc
4841 19:15:40.109993 dramc_set_vcore_voltage set vcore to 662500
4842 19:15:40.113371 Read voltage for 933, 3
4843 19:15:40.113488 Vio18 = 0
4844 19:15:40.113582 Vcore = 662500
4845 19:15:40.116720 Vdram = 0
4846 19:15:40.116809 Vddq = 0
4847 19:15:40.116876 Vmddr = 0
4848 19:15:40.123127 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4849 19:15:40.126863 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4850 19:15:40.129657 MEM_TYPE=3, freq_sel=17
4851 19:15:40.133317 sv_algorithm_assistance_LP4_1600
4852 19:15:40.136201 ============ PULL DRAM RESETB DOWN ============
4853 19:15:40.139636 ========== PULL DRAM RESETB DOWN end =========
4854 19:15:40.146481 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4855 19:15:40.150055 ===================================
4856 19:15:40.150152 LPDDR4 DRAM CONFIGURATION
4857 19:15:40.152786 ===================================
4858 19:15:40.156283 EX_ROW_EN[0] = 0x0
4859 19:15:40.159815 EX_ROW_EN[1] = 0x0
4860 19:15:40.159951 LP4Y_EN = 0x0
4861 19:15:40.163179 WORK_FSP = 0x0
4862 19:15:40.163285 WL = 0x3
4863 19:15:40.166263 RL = 0x3
4864 19:15:40.166373 BL = 0x2
4865 19:15:40.169800 RPST = 0x0
4866 19:15:40.169885 RD_PRE = 0x0
4867 19:15:40.173344 WR_PRE = 0x1
4868 19:15:40.173425 WR_PST = 0x0
4869 19:15:40.176006 DBI_WR = 0x0
4870 19:15:40.176111 DBI_RD = 0x0
4871 19:15:40.179891 OTF = 0x1
4872 19:15:40.182821 ===================================
4873 19:15:40.186544 ===================================
4874 19:15:40.186626 ANA top config
4875 19:15:40.189452 ===================================
4876 19:15:40.193097 DLL_ASYNC_EN = 0
4877 19:15:40.196901 ALL_SLAVE_EN = 1
4878 19:15:40.196991 NEW_RANK_MODE = 1
4879 19:15:40.200003 DLL_IDLE_MODE = 1
4880 19:15:40.203508 LP45_APHY_COMB_EN = 1
4881 19:15:40.206446 TX_ODT_DIS = 1
4882 19:15:40.210005 NEW_8X_MODE = 1
4883 19:15:40.212973 ===================================
4884 19:15:40.216499 ===================================
4885 19:15:40.219786 data_rate = 1866
4886 19:15:40.219868 CKR = 1
4887 19:15:40.222958 DQ_P2S_RATIO = 8
4888 19:15:40.226170 ===================================
4889 19:15:40.229508 CA_P2S_RATIO = 8
4890 19:15:40.232596 DQ_CA_OPEN = 0
4891 19:15:40.236624 DQ_SEMI_OPEN = 0
4892 19:15:40.236704 CA_SEMI_OPEN = 0
4893 19:15:40.239319 CA_FULL_RATE = 0
4894 19:15:40.243008 DQ_CKDIV4_EN = 1
4895 19:15:40.245962 CA_CKDIV4_EN = 1
4896 19:15:40.249486 CA_PREDIV_EN = 0
4897 19:15:40.252908 PH8_DLY = 0
4898 19:15:40.252983 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4899 19:15:40.256432 DQ_AAMCK_DIV = 4
4900 19:15:40.259625 CA_AAMCK_DIV = 4
4901 19:15:40.263048 CA_ADMCK_DIV = 4
4902 19:15:40.265731 DQ_TRACK_CA_EN = 0
4903 19:15:40.269615 CA_PICK = 933
4904 19:15:40.272453 CA_MCKIO = 933
4905 19:15:40.272529 MCKIO_SEMI = 0
4906 19:15:40.275787 PLL_FREQ = 3732
4907 19:15:40.279257 DQ_UI_PI_RATIO = 32
4908 19:15:40.282730 CA_UI_PI_RATIO = 0
4909 19:15:40.286007 ===================================
4910 19:15:40.289381 ===================================
4911 19:15:40.292172 memory_type:LPDDR4
4912 19:15:40.292274 GP_NUM : 10
4913 19:15:40.295754 SRAM_EN : 1
4914 19:15:40.299589 MD32_EN : 0
4915 19:15:40.302627 ===================================
4916 19:15:40.302707 [ANA_INIT] >>>>>>>>>>>>>>
4917 19:15:40.306239 <<<<<< [CONFIGURE PHASE]: ANA_TX
4918 19:15:40.309117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4919 19:15:40.312695 ===================================
4920 19:15:40.315489 data_rate = 1866,PCW = 0X8f00
4921 19:15:40.319244 ===================================
4922 19:15:40.322210 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4923 19:15:40.329330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4924 19:15:40.332189 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4925 19:15:40.338642 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4926 19:15:40.341923 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4927 19:15:40.345224 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4928 19:15:40.345308 [ANA_INIT] flow start
4929 19:15:40.349114 [ANA_INIT] PLL >>>>>>>>
4930 19:15:40.352590 [ANA_INIT] PLL <<<<<<<<
4931 19:15:40.352677 [ANA_INIT] MIDPI >>>>>>>>
4932 19:15:40.355598 [ANA_INIT] MIDPI <<<<<<<<
4933 19:15:40.359255 [ANA_INIT] DLL >>>>>>>>
4934 19:15:40.359397 [ANA_INIT] flow end
4935 19:15:40.365186 ============ LP4 DIFF to SE enter ============
4936 19:15:40.368543 ============ LP4 DIFF to SE exit ============
4937 19:15:40.372157 [ANA_INIT] <<<<<<<<<<<<<
4938 19:15:40.375452 [Flow] Enable top DCM control >>>>>
4939 19:15:40.378988 [Flow] Enable top DCM control <<<<<
4940 19:15:40.382274 Enable DLL master slave shuffle
4941 19:15:40.385583 ==============================================================
4942 19:15:40.389105 Gating Mode config
4943 19:15:40.392507 ==============================================================
4944 19:15:40.395254 Config description:
4945 19:15:40.405618 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4946 19:15:40.412058 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4947 19:15:40.415641 SELPH_MODE 0: By rank 1: By Phase
4948 19:15:40.422157 ==============================================================
4949 19:15:40.425110 GAT_TRACK_EN = 1
4950 19:15:40.428612 RX_GATING_MODE = 2
4951 19:15:40.432105 RX_GATING_TRACK_MODE = 2
4952 19:15:40.434996 SELPH_MODE = 1
4953 19:15:40.438666 PICG_EARLY_EN = 1
4954 19:15:40.438746 VALID_LAT_VALUE = 1
4955 19:15:40.445361 ==============================================================
4956 19:15:40.448170 Enter into Gating configuration >>>>
4957 19:15:40.451870 Exit from Gating configuration <<<<
4958 19:15:40.455245 Enter into DVFS_PRE_config >>>>>
4959 19:15:40.464891 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4960 19:15:40.468452 Exit from DVFS_PRE_config <<<<<
4961 19:15:40.471391 Enter into PICG configuration >>>>
4962 19:15:40.474852 Exit from PICG configuration <<<<
4963 19:15:40.478336 [RX_INPUT] configuration >>>>>
4964 19:15:40.481908 [RX_INPUT] configuration <<<<<
4965 19:15:40.484731 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4966 19:15:40.491631 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4967 19:15:40.498382 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4968 19:15:40.505250 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4969 19:15:40.511382 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4970 19:15:40.518310 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4971 19:15:40.521062 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4972 19:15:40.524732 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4973 19:15:40.528336 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4974 19:15:40.534816 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4975 19:15:40.538392 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4976 19:15:40.541131 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4977 19:15:40.544691 ===================================
4978 19:15:40.547569 LPDDR4 DRAM CONFIGURATION
4979 19:15:40.551387 ===================================
4980 19:15:40.551493 EX_ROW_EN[0] = 0x0
4981 19:15:40.554488 EX_ROW_EN[1] = 0x0
4982 19:15:40.554592 LP4Y_EN = 0x0
4983 19:15:40.558069 WORK_FSP = 0x0
4984 19:15:40.558175 WL = 0x3
4985 19:15:40.561077 RL = 0x3
4986 19:15:40.561180 BL = 0x2
4987 19:15:40.564562 RPST = 0x0
4988 19:15:40.568132 RD_PRE = 0x0
4989 19:15:40.568238 WR_PRE = 0x1
4990 19:15:40.571439 WR_PST = 0x0
4991 19:15:40.571526 DBI_WR = 0x0
4992 19:15:40.574612 DBI_RD = 0x0
4993 19:15:40.574712 OTF = 0x1
4994 19:15:40.577791 ===================================
4995 19:15:40.581151 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4996 19:15:40.587727 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4997 19:15:40.591077 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4998 19:15:40.594525 ===================================
4999 19:15:40.597895 LPDDR4 DRAM CONFIGURATION
5000 19:15:40.601436 ===================================
5001 19:15:40.601524 EX_ROW_EN[0] = 0x10
5002 19:15:40.604233 EX_ROW_EN[1] = 0x0
5003 19:15:40.604320 LP4Y_EN = 0x0
5004 19:15:40.607582 WORK_FSP = 0x0
5005 19:15:40.607668 WL = 0x3
5006 19:15:40.610943 RL = 0x3
5007 19:15:40.611028 BL = 0x2
5008 19:15:40.614497 RPST = 0x0
5009 19:15:40.614589 RD_PRE = 0x0
5010 19:15:40.617527 WR_PRE = 0x1
5011 19:15:40.621022 WR_PST = 0x0
5012 19:15:40.621108 DBI_WR = 0x0
5013 19:15:40.624297 DBI_RD = 0x0
5014 19:15:40.624394 OTF = 0x1
5015 19:15:40.627560 ===================================
5016 19:15:40.634548 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5017 19:15:40.638273 nWR fixed to 30
5018 19:15:40.641141 [ModeRegInit_LP4] CH0 RK0
5019 19:15:40.641244 [ModeRegInit_LP4] CH0 RK1
5020 19:15:40.644692 [ModeRegInit_LP4] CH1 RK0
5021 19:15:40.647585 [ModeRegInit_LP4] CH1 RK1
5022 19:15:40.647660 match AC timing 9
5023 19:15:40.654114 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5024 19:15:40.657652 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5025 19:15:40.660655 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5026 19:15:40.667889 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5027 19:15:40.670957 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5028 19:15:40.671062 ==
5029 19:15:40.674570 Dram Type= 6, Freq= 0, CH_0, rank 0
5030 19:15:40.677485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5031 19:15:40.677590 ==
5032 19:15:40.684269 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5033 19:15:40.691016 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5034 19:15:40.694589 [CA 0] Center 37 (6~68) winsize 63
5035 19:15:40.697293 [CA 1] Center 37 (7~68) winsize 62
5036 19:15:40.700546 [CA 2] Center 34 (4~65) winsize 62
5037 19:15:40.703855 [CA 3] Center 33 (3~64) winsize 62
5038 19:15:40.707299 [CA 4] Center 33 (3~64) winsize 62
5039 19:15:40.710877 [CA 5] Center 32 (2~62) winsize 61
5040 19:15:40.710986
5041 19:15:40.713860 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5042 19:15:40.713970
5043 19:15:40.717288 [CATrainingPosCal] consider 1 rank data
5044 19:15:40.720535 u2DelayCellTimex100 = 270/100 ps
5045 19:15:40.723781 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5046 19:15:40.727079 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5047 19:15:40.730765 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5048 19:15:40.734274 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5049 19:15:40.737605 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5050 19:15:40.740893 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5051 19:15:40.743828
5052 19:15:40.747392 CA PerBit enable=1, Macro0, CA PI delay=32
5053 19:15:40.747498
5054 19:15:40.750964 [CBTSetCACLKResult] CA Dly = 32
5055 19:15:40.751071 CS Dly: 5 (0~36)
5056 19:15:40.751164 ==
5057 19:15:40.753859 Dram Type= 6, Freq= 0, CH_0, rank 1
5058 19:15:40.757446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5059 19:15:40.757551 ==
5060 19:15:40.763909 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5061 19:15:40.770526 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5062 19:15:40.774298 [CA 0] Center 37 (6~68) winsize 63
5063 19:15:40.777882 [CA 1] Center 37 (6~68) winsize 63
5064 19:15:40.780855 [CA 2] Center 34 (4~65) winsize 62
5065 19:15:40.783899 [CA 3] Center 33 (3~64) winsize 62
5066 19:15:40.787412 [CA 4] Center 33 (3~63) winsize 61
5067 19:15:40.790872 [CA 5] Center 32 (2~62) winsize 61
5068 19:15:40.790982
5069 19:15:40.794335 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5070 19:15:40.794437
5071 19:15:40.797075 [CATrainingPosCal] consider 2 rank data
5072 19:15:40.800803 u2DelayCellTimex100 = 270/100 ps
5073 19:15:40.803828 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5074 19:15:40.807282 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5075 19:15:40.810622 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5076 19:15:40.813925 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5077 19:15:40.817168 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5078 19:15:40.823799 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5079 19:15:40.823967
5080 19:15:40.827261 CA PerBit enable=1, Macro0, CA PI delay=32
5081 19:15:40.827396
5082 19:15:40.830687 [CBTSetCACLKResult] CA Dly = 32
5083 19:15:40.830809 CS Dly: 5 (0~37)
5084 19:15:40.830908
5085 19:15:40.834077 ----->DramcWriteLeveling(PI) begin...
5086 19:15:40.834199 ==
5087 19:15:40.837303 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 19:15:40.840869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 19:15:40.844429 ==
5090 19:15:40.844562 Write leveling (Byte 0): 33 => 33
5091 19:15:40.847161 Write leveling (Byte 1): 29 => 29
5092 19:15:40.850593 DramcWriteLeveling(PI) end<-----
5093 19:15:40.850721
5094 19:15:40.850819 ==
5095 19:15:40.854489 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 19:15:40.861026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 19:15:40.861160 ==
5098 19:15:40.861232 [Gating] SW mode calibration
5099 19:15:40.870651 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5100 19:15:40.874256 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5101 19:15:40.877160 0 14 0 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
5102 19:15:40.884492 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 19:15:40.887320 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 19:15:40.891017 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 19:15:40.897185 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 19:15:40.900814 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 19:15:40.904230 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5108 19:15:40.910918 0 14 28 | B1->B0 | 3434 2525 | 0 0 | (0 0) (0 0)
5109 19:15:40.913837 0 15 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
5110 19:15:40.917479 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 19:15:40.923900 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 19:15:40.927208 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 19:15:40.930461 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 19:15:40.937376 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 19:15:40.940821 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 19:15:40.944028 0 15 28 | B1->B0 | 2424 3b3b | 0 0 | (0 0) (0 0)
5117 19:15:40.950984 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5118 19:15:40.953938 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 19:15:40.957540 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 19:15:40.963729 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 19:15:40.967172 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 19:15:40.970322 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 19:15:40.974127 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5124 19:15:40.980988 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5125 19:15:40.983860 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5126 19:15:40.987554 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 19:15:40.993992 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 19:15:40.997005 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 19:15:41.000426 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 19:15:41.007350 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 19:15:41.010208 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 19:15:41.013629 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 19:15:41.020138 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 19:15:41.024240 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 19:15:41.027532 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 19:15:41.033884 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 19:15:41.037197 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 19:15:41.040085 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 19:15:41.047077 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5140 19:15:41.050473 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5141 19:15:41.053790 Total UI for P1: 0, mck2ui 16
5142 19:15:41.057019 best dqsien dly found for B0: ( 1, 2, 24)
5143 19:15:41.060402 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5144 19:15:41.066674 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 19:15:41.066792 Total UI for P1: 0, mck2ui 16
5146 19:15:41.073888 best dqsien dly found for B1: ( 1, 3, 0)
5147 19:15:41.076835 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5148 19:15:41.080206 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5149 19:15:41.080319
5150 19:15:41.083644 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5151 19:15:41.087014 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5152 19:15:41.090069 [Gating] SW calibration Done
5153 19:15:41.090177 ==
5154 19:15:41.093216 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 19:15:41.096867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 19:15:41.096980 ==
5157 19:15:41.099753 RX Vref Scan: 0
5158 19:15:41.099858
5159 19:15:41.099957 RX Vref 0 -> 0, step: 1
5160 19:15:41.100047
5161 19:15:41.103330 RX Delay -80 -> 252, step: 8
5162 19:15:41.106320 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5163 19:15:41.113342 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5164 19:15:41.116243 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5165 19:15:41.119570 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5166 19:15:41.123116 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5167 19:15:41.126756 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5168 19:15:41.130260 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5169 19:15:41.136502 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5170 19:15:41.140150 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5171 19:15:41.143119 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5172 19:15:41.146680 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5173 19:15:41.150064 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5174 19:15:41.153461 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5175 19:15:41.159678 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5176 19:15:41.162951 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5177 19:15:41.166767 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5178 19:15:41.166851 ==
5179 19:15:41.169951 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 19:15:41.173187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 19:15:41.173268 ==
5182 19:15:41.176424 DQS Delay:
5183 19:15:41.176509 DQS0 = 0, DQS1 = 0
5184 19:15:41.176576 DQM Delay:
5185 19:15:41.180125 DQM0 = 104, DQM1 = 95
5186 19:15:41.180207 DQ Delay:
5187 19:15:41.182968 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5188 19:15:41.186626 DQ4 =103, DQ5 =95, DQ6 =115, DQ7 =111
5189 19:15:41.189545 DQ8 =87, DQ9 =87, DQ10 =91, DQ11 =91
5190 19:15:41.193142 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5191 19:15:41.193255
5192 19:15:41.193352
5193 19:15:41.196854 ==
5194 19:15:41.200170 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 19:15:41.203486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 19:15:41.203570 ==
5197 19:15:41.203638
5198 19:15:41.203700
5199 19:15:41.206172 TX Vref Scan disable
5200 19:15:41.206280 == TX Byte 0 ==
5201 19:15:41.213159 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5202 19:15:41.216684 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5203 19:15:41.216806 == TX Byte 1 ==
5204 19:15:41.223338 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5205 19:15:41.226547 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5206 19:15:41.226666 ==
5207 19:15:41.229462 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 19:15:41.233082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 19:15:41.233180 ==
5210 19:15:41.233248
5211 19:15:41.233309
5212 19:15:41.236178 TX Vref Scan disable
5213 19:15:41.239718 == TX Byte 0 ==
5214 19:15:41.243336 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5215 19:15:41.246126 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5216 19:15:41.249844 == TX Byte 1 ==
5217 19:15:41.252854 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5218 19:15:41.256174 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5219 19:15:41.256286
5220 19:15:41.259934 [DATLAT]
5221 19:15:41.260018 Freq=933, CH0 RK0
5222 19:15:41.260084
5223 19:15:41.263279 DATLAT Default: 0xd
5224 19:15:41.263362 0, 0xFFFF, sum = 0
5225 19:15:41.266355 1, 0xFFFF, sum = 0
5226 19:15:41.266440 2, 0xFFFF, sum = 0
5227 19:15:41.270003 3, 0xFFFF, sum = 0
5228 19:15:41.270089 4, 0xFFFF, sum = 0
5229 19:15:41.272787 5, 0xFFFF, sum = 0
5230 19:15:41.272871 6, 0xFFFF, sum = 0
5231 19:15:41.276273 7, 0xFFFF, sum = 0
5232 19:15:41.276389 8, 0xFFFF, sum = 0
5233 19:15:41.279844 9, 0xFFFF, sum = 0
5234 19:15:41.279923 10, 0x0, sum = 1
5235 19:15:41.282540 11, 0x0, sum = 2
5236 19:15:41.282653 12, 0x0, sum = 3
5237 19:15:41.286033 13, 0x0, sum = 4
5238 19:15:41.286111 best_step = 11
5239 19:15:41.286174
5240 19:15:41.286233 ==
5241 19:15:41.289588 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 19:15:41.293153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 19:15:41.296174 ==
5244 19:15:41.296254 RX Vref Scan: 1
5245 19:15:41.296319
5246 19:15:41.299162 RX Vref 0 -> 0, step: 1
5247 19:15:41.299254
5248 19:15:41.302883 RX Delay -45 -> 252, step: 4
5249 19:15:41.302968
5250 19:15:41.305863 Set Vref, RX VrefLevel [Byte0]: 56
5251 19:15:41.309655 [Byte1]: 47
5252 19:15:41.309736
5253 19:15:41.312827 Final RX Vref Byte 0 = 56 to rank0
5254 19:15:41.316315 Final RX Vref Byte 1 = 47 to rank0
5255 19:15:41.319192 Final RX Vref Byte 0 = 56 to rank1
5256 19:15:41.322448 Final RX Vref Byte 1 = 47 to rank1==
5257 19:15:41.325749 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 19:15:41.329067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 19:15:41.329148 ==
5260 19:15:41.332874 DQS Delay:
5261 19:15:41.332958 DQS0 = 0, DQS1 = 0
5262 19:15:41.333057 DQM Delay:
5263 19:15:41.336089 DQM0 = 104, DQM1 = 94
5264 19:15:41.336172 DQ Delay:
5265 19:15:41.339423 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5266 19:15:41.342737 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5267 19:15:41.346002 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =90
5268 19:15:41.349505 DQ12 =100, DQ13 =98, DQ14 =106, DQ15 =102
5269 19:15:41.349591
5270 19:15:41.352545
5271 19:15:41.358916 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
5272 19:15:41.362591 CH0 RK0: MR19=505, MR18=2E26
5273 19:15:41.369239 CH0_RK0: MR19=0x505, MR18=0x2E26, DQSOSC=407, MR23=63, INC=65, DEC=43
5274 19:15:41.369323
5275 19:15:41.373023 ----->DramcWriteLeveling(PI) begin...
5276 19:15:41.373108 ==
5277 19:15:41.375850 Dram Type= 6, Freq= 0, CH_0, rank 1
5278 19:15:41.379472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 19:15:41.379565 ==
5280 19:15:41.382286 Write leveling (Byte 0): 33 => 33
5281 19:15:41.385956 Write leveling (Byte 1): 31 => 31
5282 19:15:41.389081 DramcWriteLeveling(PI) end<-----
5283 19:15:41.389181
5284 19:15:41.389271 ==
5285 19:15:41.392625 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 19:15:41.395983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 19:15:41.396072 ==
5288 19:15:41.398871 [Gating] SW mode calibration
5289 19:15:41.405531 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5290 19:15:41.412211 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5291 19:15:41.415840 0 14 0 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 1)
5292 19:15:41.418815 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 19:15:41.425477 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 19:15:41.429224 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 19:15:41.432094 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 19:15:41.438995 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 19:15:41.442442 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5298 19:15:41.445846 0 14 28 | B1->B0 | 2626 2929 | 0 0 | (0 0) (1 0)
5299 19:15:41.452662 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
5300 19:15:41.456053 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 19:15:41.459126 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 19:15:41.462168 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 19:15:41.469274 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 19:15:41.472256 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 19:15:41.475849 0 15 24 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
5306 19:15:41.482366 0 15 28 | B1->B0 | 3d3d 3737 | 0 0 | (0 0) (0 0)
5307 19:15:41.485230 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 19:15:41.489043 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 19:15:41.495518 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 19:15:41.499010 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 19:15:41.501757 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 19:15:41.508664 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 19:15:41.512257 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 19:15:41.515228 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5315 19:15:41.522065 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 19:15:41.525748 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 19:15:41.528641 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 19:15:41.535297 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 19:15:41.538986 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 19:15:41.541939 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 19:15:41.549084 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 19:15:41.551924 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 19:15:41.555624 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 19:15:41.562421 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 19:15:41.565097 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 19:15:41.568537 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 19:15:41.575321 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 19:15:41.578581 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 19:15:41.581766 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 19:15:41.588577 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5331 19:15:41.592051 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 19:15:41.594887 Total UI for P1: 0, mck2ui 16
5333 19:15:41.598375 best dqsien dly found for B0: ( 1, 2, 28)
5334 19:15:41.602098 Total UI for P1: 0, mck2ui 16
5335 19:15:41.605081 best dqsien dly found for B1: ( 1, 2, 30)
5336 19:15:41.608599 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5337 19:15:41.611915 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5338 19:15:41.612023
5339 19:15:41.615324 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5340 19:15:41.618763 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5341 19:15:41.621788 [Gating] SW calibration Done
5342 19:15:41.621897 ==
5343 19:15:41.625476 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 19:15:41.628575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 19:15:41.628654 ==
5346 19:15:41.632243 RX Vref Scan: 0
5347 19:15:41.632328
5348 19:15:41.632417 RX Vref 0 -> 0, step: 1
5349 19:15:41.635195
5350 19:15:41.635284 RX Delay -80 -> 252, step: 8
5351 19:15:41.641854 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5352 19:15:41.645505 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5353 19:15:41.648413 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5354 19:15:41.652012 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5355 19:15:41.654885 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5356 19:15:41.658667 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5357 19:15:41.665330 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5358 19:15:41.668288 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5359 19:15:41.671947 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5360 19:15:41.674858 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5361 19:15:41.678557 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5362 19:15:41.681474 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5363 19:15:41.688015 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5364 19:15:41.691778 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5365 19:15:41.695281 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5366 19:15:41.698000 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5367 19:15:41.698075 ==
5368 19:15:41.701404 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 19:15:41.708197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 19:15:41.708282 ==
5371 19:15:41.708394 DQS Delay:
5372 19:15:41.708479 DQS0 = 0, DQS1 = 0
5373 19:15:41.711347 DQM Delay:
5374 19:15:41.711428 DQM0 = 104, DQM1 = 93
5375 19:15:41.715126 DQ Delay:
5376 19:15:41.718308 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5377 19:15:41.721513 DQ4 =107, DQ5 =99, DQ6 =107, DQ7 =111
5378 19:15:41.724840 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5379 19:15:41.728040 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5380 19:15:41.728126
5381 19:15:41.728237
5382 19:15:41.728350 ==
5383 19:15:41.731474 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 19:15:41.734832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 19:15:41.734925 ==
5386 19:15:41.735015
5387 19:15:41.735102
5388 19:15:41.737885 TX Vref Scan disable
5389 19:15:41.741558 == TX Byte 0 ==
5390 19:15:41.744466 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5391 19:15:41.748150 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5392 19:15:41.751058 == TX Byte 1 ==
5393 19:15:41.754778 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5394 19:15:41.757750 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5395 19:15:41.757828 ==
5396 19:15:41.761383 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 19:15:41.764867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 19:15:41.767762 ==
5399 19:15:41.767885
5400 19:15:41.768000
5401 19:15:41.768102 TX Vref Scan disable
5402 19:15:41.771181 == TX Byte 0 ==
5403 19:15:41.774815 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5404 19:15:41.778320 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5405 19:15:41.782020 == TX Byte 1 ==
5406 19:15:41.784868 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5407 19:15:41.791567 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5408 19:15:41.791667
5409 19:15:41.791753 [DATLAT]
5410 19:15:41.791863 Freq=933, CH0 RK1
5411 19:15:41.791969
5412 19:15:41.794422 DATLAT Default: 0xb
5413 19:15:41.794531 0, 0xFFFF, sum = 0
5414 19:15:41.798062 1, 0xFFFF, sum = 0
5415 19:15:41.798147 2, 0xFFFF, sum = 0
5416 19:15:41.801620 3, 0xFFFF, sum = 0
5417 19:15:41.804777 4, 0xFFFF, sum = 0
5418 19:15:41.804894 5, 0xFFFF, sum = 0
5419 19:15:41.807935 6, 0xFFFF, sum = 0
5420 19:15:41.808043 7, 0xFFFF, sum = 0
5421 19:15:41.811460 8, 0xFFFF, sum = 0
5422 19:15:41.811550 9, 0xFFFF, sum = 0
5423 19:15:41.814301 10, 0x0, sum = 1
5424 19:15:41.814381 11, 0x0, sum = 2
5425 19:15:41.817914 12, 0x0, sum = 3
5426 19:15:41.818023 13, 0x0, sum = 4
5427 19:15:41.818117 best_step = 11
5428 19:15:41.818204
5429 19:15:41.821314 ==
5430 19:15:41.824861 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 19:15:41.827726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 19:15:41.827827 ==
5433 19:15:41.827925 RX Vref Scan: 0
5434 19:15:41.828013
5435 19:15:41.831070 RX Vref 0 -> 0, step: 1
5436 19:15:41.831181
5437 19:15:41.834299 RX Delay -53 -> 252, step: 4
5438 19:15:41.837675 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5439 19:15:41.844087 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5440 19:15:41.847444 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5441 19:15:41.851026 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5442 19:15:41.854547 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5443 19:15:41.857449 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5444 19:15:41.864171 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5445 19:15:41.867926 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5446 19:15:41.870719 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5447 19:15:41.874285 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5448 19:15:41.877868 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5449 19:15:41.884222 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5450 19:15:41.887280 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5451 19:15:41.890960 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5452 19:15:41.893897 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5453 19:15:41.897493 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5454 19:15:41.897578 ==
5455 19:15:41.900399 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 19:15:41.907529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 19:15:41.907613 ==
5458 19:15:41.907711 DQS Delay:
5459 19:15:41.910511 DQS0 = 0, DQS1 = 0
5460 19:15:41.910598 DQM Delay:
5461 19:15:41.914177 DQM0 = 104, DQM1 = 93
5462 19:15:41.914293 DQ Delay:
5463 19:15:41.917074 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5464 19:15:41.920780 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5465 19:15:41.923760 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =88
5466 19:15:41.927422 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =102
5467 19:15:41.927508
5468 19:15:41.927595
5469 19:15:41.933983 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5470 19:15:41.937027 CH0 RK1: MR19=505, MR18=2A02
5471 19:15:41.944313 CH0_RK1: MR19=0x505, MR18=0x2A02, DQSOSC=408, MR23=63, INC=65, DEC=43
5472 19:15:41.947034 [RxdqsGatingPostProcess] freq 933
5473 19:15:41.953844 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5474 19:15:41.957215 best DQS0 dly(2T, 0.5T) = (0, 10)
5475 19:15:41.960733 best DQS1 dly(2T, 0.5T) = (0, 11)
5476 19:15:41.963459 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5477 19:15:41.967022 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5478 19:15:41.967106 best DQS0 dly(2T, 0.5T) = (0, 10)
5479 19:15:41.970206 best DQS1 dly(2T, 0.5T) = (0, 10)
5480 19:15:41.973782 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5481 19:15:41.977340 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5482 19:15:41.980217 Pre-setting of DQS Precalculation
5483 19:15:41.987152 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5484 19:15:41.987240 ==
5485 19:15:41.990496 Dram Type= 6, Freq= 0, CH_1, rank 0
5486 19:15:41.993440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 19:15:41.993523 ==
5488 19:15:42.000053 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5489 19:15:42.003602 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5490 19:15:42.008067 [CA 0] Center 36 (6~67) winsize 62
5491 19:15:42.011026 [CA 1] Center 37 (6~68) winsize 63
5492 19:15:42.014636 [CA 2] Center 35 (5~65) winsize 61
5493 19:15:42.018171 [CA 3] Center 34 (4~65) winsize 62
5494 19:15:42.021016 [CA 4] Center 34 (4~65) winsize 62
5495 19:15:42.024786 [CA 5] Center 33 (3~64) winsize 62
5496 19:15:42.024868
5497 19:15:42.027753 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5498 19:15:42.027860
5499 19:15:42.031405 [CATrainingPosCal] consider 1 rank data
5500 19:15:42.034284 u2DelayCellTimex100 = 270/100 ps
5501 19:15:42.038008 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5502 19:15:42.044345 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5503 19:15:42.047864 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5504 19:15:42.050969 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5505 19:15:42.054568 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5506 19:15:42.057499 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5507 19:15:42.057611
5508 19:15:42.061200 CA PerBit enable=1, Macro0, CA PI delay=33
5509 19:15:42.061277
5510 19:15:42.064152 [CBTSetCACLKResult] CA Dly = 33
5511 19:15:42.064259 CS Dly: 6 (0~37)
5512 19:15:42.067762 ==
5513 19:15:42.071296 Dram Type= 6, Freq= 0, CH_1, rank 1
5514 19:15:42.074126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 19:15:42.074202 ==
5516 19:15:42.077571 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5517 19:15:42.084288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5518 19:15:42.088034 [CA 0] Center 36 (6~67) winsize 62
5519 19:15:42.091342 [CA 1] Center 37 (6~68) winsize 63
5520 19:15:42.094678 [CA 2] Center 35 (5~66) winsize 62
5521 19:15:42.098239 [CA 3] Center 34 (4~65) winsize 62
5522 19:15:42.100954 [CA 4] Center 34 (4~65) winsize 62
5523 19:15:42.104963 [CA 5] Center 33 (3~64) winsize 62
5524 19:15:42.105049
5525 19:15:42.107851 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5526 19:15:42.107956
5527 19:15:42.111529 [CATrainingPosCal] consider 2 rank data
5528 19:15:42.114495 u2DelayCellTimex100 = 270/100 ps
5529 19:15:42.118137 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5530 19:15:42.124878 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5531 19:15:42.127747 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5532 19:15:42.131393 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5533 19:15:42.134363 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5534 19:15:42.137863 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5535 19:15:42.137980
5536 19:15:42.141258 CA PerBit enable=1, Macro0, CA PI delay=33
5537 19:15:42.141339
5538 19:15:42.144227 [CBTSetCACLKResult] CA Dly = 33
5539 19:15:42.144327 CS Dly: 7 (0~39)
5540 19:15:42.148022
5541 19:15:42.150863 ----->DramcWriteLeveling(PI) begin...
5542 19:15:42.150986 ==
5543 19:15:42.154599 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 19:15:42.158153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 19:15:42.158270 ==
5546 19:15:42.161069 Write leveling (Byte 0): 25 => 25
5547 19:15:42.164640 Write leveling (Byte 1): 27 => 27
5548 19:15:42.167488 DramcWriteLeveling(PI) end<-----
5549 19:15:42.167596
5550 19:15:42.167687 ==
5551 19:15:42.171207 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 19:15:42.174292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 19:15:42.174392 ==
5554 19:15:42.177962 [Gating] SW mode calibration
5555 19:15:42.184464 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5556 19:15:42.191401 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5557 19:15:42.194303 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 19:15:42.197768 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 19:15:42.201118 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 19:15:42.207446 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 19:15:42.211377 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 19:15:42.214598 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 19:15:42.221291 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 0) (0 1)
5564 19:15:42.224788 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5565 19:15:42.227997 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 19:15:42.234608 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 19:15:42.238293 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 19:15:42.241373 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 19:15:42.248374 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 19:15:42.251321 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5571 19:15:42.254217 0 15 24 | B1->B0 | 2c2c 3434 | 0 0 | (0 0) (0 0)
5572 19:15:42.261474 0 15 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5573 19:15:42.264407 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 19:15:42.267949 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 19:15:42.274588 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 19:15:42.277608 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 19:15:42.281268 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 19:15:42.287928 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 19:15:42.290812 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5580 19:15:42.294502 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 19:15:42.301056 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 19:15:42.303896 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 19:15:42.307422 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 19:15:42.313890 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 19:15:42.317727 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 19:15:42.320631 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 19:15:42.327228 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 19:15:42.330784 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 19:15:42.334017 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 19:15:42.340444 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 19:15:42.344242 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 19:15:42.347209 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 19:15:42.353956 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 19:15:42.357188 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 19:15:42.360485 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5596 19:15:42.363688 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 19:15:42.367095 Total UI for P1: 0, mck2ui 16
5598 19:15:42.370332 best dqsien dly found for B0: ( 1, 2, 24)
5599 19:15:42.373655 Total UI for P1: 0, mck2ui 16
5600 19:15:42.377245 best dqsien dly found for B1: ( 1, 2, 24)
5601 19:15:42.380105 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5602 19:15:42.386822 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5603 19:15:42.386926
5604 19:15:42.390563 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5605 19:15:42.393573 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5606 19:15:42.397210 [Gating] SW calibration Done
5607 19:15:42.397283 ==
5608 19:15:42.400124 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 19:15:42.403702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 19:15:42.403783 ==
5611 19:15:42.403883 RX Vref Scan: 0
5612 19:15:42.407056
5613 19:15:42.407153 RX Vref 0 -> 0, step: 1
5614 19:15:42.407245
5615 19:15:42.409880 RX Delay -80 -> 252, step: 8
5616 19:15:42.413361 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5617 19:15:42.416948 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5618 19:15:42.423564 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5619 19:15:42.426559 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5620 19:15:42.430299 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5621 19:15:42.433362 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5622 19:15:42.436259 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5623 19:15:42.440040 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5624 19:15:42.446497 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5625 19:15:42.450271 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5626 19:15:42.453121 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5627 19:15:42.456498 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5628 19:15:42.460111 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5629 19:15:42.466674 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5630 19:15:42.469849 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5631 19:15:42.473090 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5632 19:15:42.473172 ==
5633 19:15:42.476127 Dram Type= 6, Freq= 0, CH_1, rank 0
5634 19:15:42.479872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5635 19:15:42.479975 ==
5636 19:15:42.483083 DQS Delay:
5637 19:15:42.483188 DQS0 = 0, DQS1 = 0
5638 19:15:42.486469 DQM Delay:
5639 19:15:42.486548 DQM0 = 102, DQM1 = 98
5640 19:15:42.486631 DQ Delay:
5641 19:15:42.489726 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5642 19:15:42.492896 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5643 19:15:42.495906 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5644 19:15:42.503134 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5645 19:15:42.503212
5646 19:15:42.503276
5647 19:15:42.503335 ==
5648 19:15:42.506163 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 19:15:42.509899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 19:15:42.509974 ==
5651 19:15:42.510037
5652 19:15:42.510096
5653 19:15:42.512845 TX Vref Scan disable
5654 19:15:42.512919 == TX Byte 0 ==
5655 19:15:42.519818 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5656 19:15:42.522609 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5657 19:15:42.522712 == TX Byte 1 ==
5658 19:15:42.529545 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5659 19:15:42.532632 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5660 19:15:42.532739 ==
5661 19:15:42.536473 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 19:15:42.539482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 19:15:42.539559 ==
5664 19:15:42.539630
5665 19:15:42.539691
5666 19:15:42.542989 TX Vref Scan disable
5667 19:15:42.546003 == TX Byte 0 ==
5668 19:15:42.548959 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5669 19:15:42.552749 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5670 19:15:42.555645 == TX Byte 1 ==
5671 19:15:42.558958 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5672 19:15:42.562775 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5673 19:15:42.562878
5674 19:15:42.565596 [DATLAT]
5675 19:15:42.565706 Freq=933, CH1 RK0
5676 19:15:42.565805
5677 19:15:42.569349 DATLAT Default: 0xd
5678 19:15:42.569455 0, 0xFFFF, sum = 0
5679 19:15:42.573035 1, 0xFFFF, sum = 0
5680 19:15:42.573128 2, 0xFFFF, sum = 0
5681 19:15:42.575908 3, 0xFFFF, sum = 0
5682 19:15:42.576016 4, 0xFFFF, sum = 0
5683 19:15:42.578840 5, 0xFFFF, sum = 0
5684 19:15:42.578939 6, 0xFFFF, sum = 0
5685 19:15:42.582448 7, 0xFFFF, sum = 0
5686 19:15:42.582559 8, 0xFFFF, sum = 0
5687 19:15:42.586031 9, 0xFFFF, sum = 0
5688 19:15:42.586152 10, 0x0, sum = 1
5689 19:15:42.588983 11, 0x0, sum = 2
5690 19:15:42.589092 12, 0x0, sum = 3
5691 19:15:42.592237 13, 0x0, sum = 4
5692 19:15:42.592353 best_step = 11
5693 19:15:42.592422
5694 19:15:42.592498 ==
5695 19:15:42.595678 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 19:15:42.602520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 19:15:42.602611 ==
5698 19:15:42.602677 RX Vref Scan: 1
5699 19:15:42.602747
5700 19:15:42.605854 RX Vref 0 -> 0, step: 1
5701 19:15:42.605956
5702 19:15:42.609155 RX Delay -45 -> 252, step: 4
5703 19:15:42.609263
5704 19:15:42.612318 Set Vref, RX VrefLevel [Byte0]: 53
5705 19:15:42.615588 [Byte1]: 47
5706 19:15:42.615695
5707 19:15:42.618747 Final RX Vref Byte 0 = 53 to rank0
5708 19:15:42.622259 Final RX Vref Byte 1 = 47 to rank0
5709 19:15:42.625965 Final RX Vref Byte 0 = 53 to rank1
5710 19:15:42.628727 Final RX Vref Byte 1 = 47 to rank1==
5711 19:15:42.632361 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 19:15:42.635918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 19:15:42.636036 ==
5714 19:15:42.638613 DQS Delay:
5715 19:15:42.638718 DQS0 = 0, DQS1 = 0
5716 19:15:42.638811 DQM Delay:
5717 19:15:42.642364 DQM0 = 102, DQM1 = 98
5718 19:15:42.642464 DQ Delay:
5719 19:15:42.645331 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5720 19:15:42.649088 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5721 19:15:42.652035 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =92
5722 19:15:42.655617 DQ12 =106, DQ13 =106, DQ14 =106, DQ15 =108
5723 19:15:42.658868
5724 19:15:42.658967
5725 19:15:42.665415 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a31, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5726 19:15:42.669189 CH1 RK0: MR19=505, MR18=1A31
5727 19:15:42.675618 CH1_RK0: MR19=0x505, MR18=0x1A31, DQSOSC=406, MR23=63, INC=65, DEC=43
5728 19:15:42.675695
5729 19:15:42.678561 ----->DramcWriteLeveling(PI) begin...
5730 19:15:42.678667 ==
5731 19:15:42.682249 Dram Type= 6, Freq= 0, CH_1, rank 1
5732 19:15:42.685231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 19:15:42.685329 ==
5734 19:15:42.688885 Write leveling (Byte 0): 27 => 27
5735 19:15:42.691994 Write leveling (Byte 1): 28 => 28
5736 19:15:42.695601 DramcWriteLeveling(PI) end<-----
5737 19:15:42.695715
5738 19:15:42.695808 ==
5739 19:15:42.698431 Dram Type= 6, Freq= 0, CH_1, rank 1
5740 19:15:42.702101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 19:15:42.702204 ==
5742 19:15:42.705722 [Gating] SW mode calibration
5743 19:15:42.711905 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5744 19:15:42.718262 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5745 19:15:42.721760 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 19:15:42.725311 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 19:15:42.732261 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 19:15:42.735340 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 19:15:42.738939 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 19:15:42.745372 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 19:15:42.748723 0 14 24 | B1->B0 | 2e2e 3030 | 0 0 | (0 0) (1 0)
5752 19:15:42.752240 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5753 19:15:42.758873 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 19:15:42.761780 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 19:15:42.765211 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 19:15:42.771890 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 19:15:42.775541 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 19:15:42.778393 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 19:15:42.785510 0 15 24 | B1->B0 | 3e3e 2a2a | 0 0 | (0 0) (0 0)
5760 19:15:42.788529 0 15 28 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
5761 19:15:42.792094 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 19:15:42.795697 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 19:15:42.802121 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 19:15:42.805094 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 19:15:42.808952 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 19:15:42.815286 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 19:15:42.818787 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 19:15:42.822144 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5769 19:15:42.828391 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 19:15:42.832164 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 19:15:42.835074 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 19:15:42.842057 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 19:15:42.844763 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 19:15:42.848640 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 19:15:42.855010 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 19:15:42.858188 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 19:15:42.861788 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 19:15:42.868554 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 19:15:42.872102 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 19:15:42.874995 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 19:15:42.881460 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 19:15:42.885312 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 19:15:42.888210 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5784 19:15:42.894672 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 19:15:42.894750 Total UI for P1: 0, mck2ui 16
5786 19:15:42.901458 best dqsien dly found for B0: ( 1, 2, 24)
5787 19:15:42.901535 Total UI for P1: 0, mck2ui 16
5788 19:15:42.907995 best dqsien dly found for B1: ( 1, 2, 24)
5789 19:15:42.911664 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5790 19:15:42.914688 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5791 19:15:42.914798
5792 19:15:42.918125 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5793 19:15:42.921111 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5794 19:15:42.924627 [Gating] SW calibration Done
5795 19:15:42.924702 ==
5796 19:15:42.928191 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 19:15:42.931622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 19:15:42.931695 ==
5799 19:15:42.934883 RX Vref Scan: 0
5800 19:15:42.934995
5801 19:15:42.935062 RX Vref 0 -> 0, step: 1
5802 19:15:42.935123
5803 19:15:42.937815 RX Delay -80 -> 252, step: 8
5804 19:15:42.941470 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5805 19:15:42.948075 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5806 19:15:42.951567 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5807 19:15:42.954439 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5808 19:15:42.958153 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5809 19:15:42.960967 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5810 19:15:42.964621 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5811 19:15:42.971174 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5812 19:15:42.974286 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5813 19:15:42.977599 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5814 19:15:42.980890 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5815 19:15:42.984109 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5816 19:15:42.988117 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5817 19:15:42.994422 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5818 19:15:42.997980 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5819 19:15:43.001008 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5820 19:15:43.001094 ==
5821 19:15:43.004604 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 19:15:43.007475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 19:15:43.007579 ==
5824 19:15:43.011068 DQS Delay:
5825 19:15:43.011172 DQS0 = 0, DQS1 = 0
5826 19:15:43.014129 DQM Delay:
5827 19:15:43.014216 DQM0 = 102, DQM1 = 97
5828 19:15:43.014298 DQ Delay:
5829 19:15:43.017922 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5830 19:15:43.021265 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5831 19:15:43.024271 DQ8 =83, DQ9 =91, DQ10 =99, DQ11 =91
5832 19:15:43.031149 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5833 19:15:43.031259
5834 19:15:43.031345
5835 19:15:43.031436 ==
5836 19:15:43.034067 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 19:15:43.037660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 19:15:43.037744 ==
5839 19:15:43.037810
5840 19:15:43.037869
5841 19:15:43.041245 TX Vref Scan disable
5842 19:15:43.041327 == TX Byte 0 ==
5843 19:15:43.047238 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5844 19:15:43.050878 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5845 19:15:43.050989 == TX Byte 1 ==
5846 19:15:43.057381 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5847 19:15:43.060978 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5848 19:15:43.061060 ==
5849 19:15:43.064096 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 19:15:43.067182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 19:15:43.067268 ==
5852 19:15:43.067332
5853 19:15:43.067392
5854 19:15:43.070923 TX Vref Scan disable
5855 19:15:43.073885 == TX Byte 0 ==
5856 19:15:43.077387 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5857 19:15:43.080859 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5858 19:15:43.084347 == TX Byte 1 ==
5859 19:15:43.087131 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5860 19:15:43.090727 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5861 19:15:43.090835
5862 19:15:43.094459 [DATLAT]
5863 19:15:43.094566 Freq=933, CH1 RK1
5864 19:15:43.094661
5865 19:15:43.097166 DATLAT Default: 0xb
5866 19:15:43.097268 0, 0xFFFF, sum = 0
5867 19:15:43.100446 1, 0xFFFF, sum = 0
5868 19:15:43.100549 2, 0xFFFF, sum = 0
5869 19:15:43.104166 3, 0xFFFF, sum = 0
5870 19:15:43.104273 4, 0xFFFF, sum = 0
5871 19:15:43.107371 5, 0xFFFF, sum = 0
5872 19:15:43.107476 6, 0xFFFF, sum = 0
5873 19:15:43.111135 7, 0xFFFF, sum = 0
5874 19:15:43.111243 8, 0xFFFF, sum = 0
5875 19:15:43.114364 9, 0xFFFF, sum = 0
5876 19:15:43.114472 10, 0x0, sum = 1
5877 19:15:43.117501 11, 0x0, sum = 2
5878 19:15:43.117605 12, 0x0, sum = 3
5879 19:15:43.120956 13, 0x0, sum = 4
5880 19:15:43.121042 best_step = 11
5881 19:15:43.121107
5882 19:15:43.121168 ==
5883 19:15:43.123676 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 19:15:43.130906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 19:15:43.131014 ==
5886 19:15:43.131107 RX Vref Scan: 0
5887 19:15:43.131206
5888 19:15:43.133865 RX Vref 0 -> 0, step: 1
5889 19:15:43.133986
5890 19:15:43.137614 RX Delay -53 -> 252, step: 4
5891 19:15:43.140482 iDelay=199, Bit 0, Center 108 (27 ~ 190) 164
5892 19:15:43.144249 iDelay=199, Bit 1, Center 98 (15 ~ 182) 168
5893 19:15:43.150760 iDelay=199, Bit 2, Center 94 (11 ~ 178) 168
5894 19:15:43.154086 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5895 19:15:43.156956 iDelay=199, Bit 4, Center 100 (19 ~ 182) 164
5896 19:15:43.160442 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5897 19:15:43.163848 iDelay=199, Bit 6, Center 114 (31 ~ 198) 168
5898 19:15:43.170351 iDelay=199, Bit 7, Center 104 (19 ~ 190) 172
5899 19:15:43.173993 iDelay=199, Bit 8, Center 86 (-1 ~ 174) 176
5900 19:15:43.177141 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5901 19:15:43.180681 iDelay=199, Bit 10, Center 100 (15 ~ 186) 172
5902 19:15:43.183621 iDelay=199, Bit 11, Center 94 (11 ~ 178) 168
5903 19:15:43.190116 iDelay=199, Bit 12, Center 108 (23 ~ 194) 172
5904 19:15:43.193492 iDelay=199, Bit 13, Center 104 (23 ~ 186) 164
5905 19:15:43.196857 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5906 19:15:43.200535 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5907 19:15:43.200652 ==
5908 19:15:43.203508 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 19:15:43.207240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 19:15:43.210088 ==
5911 19:15:43.210197 DQS Delay:
5912 19:15:43.210326 DQS0 = 0, DQS1 = 0
5913 19:15:43.213773 DQM Delay:
5914 19:15:43.213899 DQM0 = 104, DQM1 = 99
5915 19:15:43.217383 DQ Delay:
5916 19:15:43.220652 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =100
5917 19:15:43.223834 DQ4 =100, DQ5 =116, DQ6 =114, DQ7 =104
5918 19:15:43.226875 DQ8 =86, DQ9 =88, DQ10 =100, DQ11 =94
5919 19:15:43.230090 DQ12 =108, DQ13 =104, DQ14 =104, DQ15 =108
5920 19:15:43.230203
5921 19:15:43.230307
5922 19:15:43.236907 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5923 19:15:43.240227 CH1 RK1: MR19=505, MR18=2D01
5924 19:15:43.246776 CH1_RK1: MR19=0x505, MR18=0x2D01, DQSOSC=407, MR23=63, INC=65, DEC=43
5925 19:15:43.250222 [RxdqsGatingPostProcess] freq 933
5926 19:15:43.256726 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5927 19:15:43.256841 best DQS0 dly(2T, 0.5T) = (0, 10)
5928 19:15:43.260391 best DQS1 dly(2T, 0.5T) = (0, 10)
5929 19:15:43.263129 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5930 19:15:43.266782 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5931 19:15:43.270356 best DQS0 dly(2T, 0.5T) = (0, 10)
5932 19:15:43.273146 best DQS1 dly(2T, 0.5T) = (0, 10)
5933 19:15:43.276550 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5934 19:15:43.280267 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5935 19:15:43.283215 Pre-setting of DQS Precalculation
5936 19:15:43.290013 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5937 19:15:43.296474 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5938 19:15:43.303490 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5939 19:15:43.303609
5940 19:15:43.303708
5941 19:15:43.306248 [Calibration Summary] 1866 Mbps
5942 19:15:43.306355 CH 0, Rank 0
5943 19:15:43.309988 SW Impedance : PASS
5944 19:15:43.313060 DUTY Scan : NO K
5945 19:15:43.313165 ZQ Calibration : PASS
5946 19:15:43.316615 Jitter Meter : NO K
5947 19:15:43.316725 CBT Training : PASS
5948 19:15:43.320236 Write leveling : PASS
5949 19:15:43.323205 RX DQS gating : PASS
5950 19:15:43.323306 RX DQ/DQS(RDDQC) : PASS
5951 19:15:43.326813 TX DQ/DQS : PASS
5952 19:15:43.329758 RX DATLAT : PASS
5953 19:15:43.329870 RX DQ/DQS(Engine): PASS
5954 19:15:43.333291 TX OE : NO K
5955 19:15:43.333401 All Pass.
5956 19:15:43.333504
5957 19:15:43.336667 CH 0, Rank 1
5958 19:15:43.336769 SW Impedance : PASS
5959 19:15:43.339570 DUTY Scan : NO K
5960 19:15:43.343249 ZQ Calibration : PASS
5961 19:15:43.343356 Jitter Meter : NO K
5962 19:15:43.346026 CBT Training : PASS
5963 19:15:43.349651 Write leveling : PASS
5964 19:15:43.349755 RX DQS gating : PASS
5965 19:15:43.353209 RX DQ/DQS(RDDQC) : PASS
5966 19:15:43.355859 TX DQ/DQS : PASS
5967 19:15:43.355960 RX DATLAT : PASS
5968 19:15:43.359768 RX DQ/DQS(Engine): PASS
5969 19:15:43.362533 TX OE : NO K
5970 19:15:43.362639 All Pass.
5971 19:15:43.362740
5972 19:15:43.362839 CH 1, Rank 0
5973 19:15:43.365730 SW Impedance : PASS
5974 19:15:43.369574 DUTY Scan : NO K
5975 19:15:43.369679 ZQ Calibration : PASS
5976 19:15:43.372938 Jitter Meter : NO K
5977 19:15:43.373047 CBT Training : PASS
5978 19:15:43.375810 Write leveling : PASS
5979 19:15:43.379304 RX DQS gating : PASS
5980 19:15:43.379407 RX DQ/DQS(RDDQC) : PASS
5981 19:15:43.382830 TX DQ/DQS : PASS
5982 19:15:43.385602 RX DATLAT : PASS
5983 19:15:43.385706 RX DQ/DQS(Engine): PASS
5984 19:15:43.389204 TX OE : NO K
5985 19:15:43.389308 All Pass.
5986 19:15:43.389400
5987 19:15:43.392889 CH 1, Rank 1
5988 19:15:43.392972 SW Impedance : PASS
5989 19:15:43.395890 DUTY Scan : NO K
5990 19:15:43.399542 ZQ Calibration : PASS
5991 19:15:43.399625 Jitter Meter : NO K
5992 19:15:43.402678 CBT Training : PASS
5993 19:15:43.405489 Write leveling : PASS
5994 19:15:43.405572 RX DQS gating : PASS
5995 19:15:43.409151 RX DQ/DQS(RDDQC) : PASS
5996 19:15:43.412417 TX DQ/DQS : PASS
5997 19:15:43.412497 RX DATLAT : PASS
5998 19:15:43.415768 RX DQ/DQS(Engine): PASS
5999 19:15:43.418851 TX OE : NO K
6000 19:15:43.418935 All Pass.
6001 19:15:43.419000
6002 19:15:43.419061 DramC Write-DBI off
6003 19:15:43.422578 PER_BANK_REFRESH: Hybrid Mode
6004 19:15:43.425555 TX_TRACKING: ON
6005 19:15:43.432040 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6006 19:15:43.435871 [FAST_K] Save calibration result to emmc
6007 19:15:43.442335 dramc_set_vcore_voltage set vcore to 650000
6008 19:15:43.442429 Read voltage for 400, 6
6009 19:15:43.445529 Vio18 = 0
6010 19:15:43.445608 Vcore = 650000
6011 19:15:43.445679 Vdram = 0
6012 19:15:43.449135 Vddq = 0
6013 19:15:43.449216 Vmddr = 0
6014 19:15:43.452091 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6015 19:15:43.458676 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6016 19:15:43.462306 MEM_TYPE=3, freq_sel=20
6017 19:15:43.462393 sv_algorithm_assistance_LP4_800
6018 19:15:43.468590 ============ PULL DRAM RESETB DOWN ============
6019 19:15:43.472234 ========== PULL DRAM RESETB DOWN end =========
6020 19:15:43.475789 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6021 19:15:43.478639 ===================================
6022 19:15:43.481957 LPDDR4 DRAM CONFIGURATION
6023 19:15:43.486007 ===================================
6024 19:15:43.489107 EX_ROW_EN[0] = 0x0
6025 19:15:43.489211 EX_ROW_EN[1] = 0x0
6026 19:15:43.492114 LP4Y_EN = 0x0
6027 19:15:43.492192 WORK_FSP = 0x0
6028 19:15:43.495394 WL = 0x2
6029 19:15:43.495511 RL = 0x2
6030 19:15:43.498930 BL = 0x2
6031 19:15:43.499039 RPST = 0x0
6032 19:15:43.502204 RD_PRE = 0x0
6033 19:15:43.502311 WR_PRE = 0x1
6034 19:15:43.505635 WR_PST = 0x0
6035 19:15:43.505713 DBI_WR = 0x0
6036 19:15:43.508534 DBI_RD = 0x0
6037 19:15:43.508637 OTF = 0x1
6038 19:15:43.512136 ===================================
6039 19:15:43.515739 ===================================
6040 19:15:43.519274 ANA top config
6041 19:15:43.522011 ===================================
6042 19:15:43.525252 DLL_ASYNC_EN = 0
6043 19:15:43.525359 ALL_SLAVE_EN = 1
6044 19:15:43.528911 NEW_RANK_MODE = 1
6045 19:15:43.531827 DLL_IDLE_MODE = 1
6046 19:15:43.535551 LP45_APHY_COMB_EN = 1
6047 19:15:43.535627 TX_ODT_DIS = 1
6048 19:15:43.538572 NEW_8X_MODE = 1
6049 19:15:43.542257 ===================================
6050 19:15:43.545267 ===================================
6051 19:15:43.548870 data_rate = 800
6052 19:15:43.551757 CKR = 1
6053 19:15:43.555057 DQ_P2S_RATIO = 4
6054 19:15:43.558595 ===================================
6055 19:15:43.562315 CA_P2S_RATIO = 4
6056 19:15:43.562422 DQ_CA_OPEN = 0
6057 19:15:43.565319 DQ_SEMI_OPEN = 1
6058 19:15:43.568323 CA_SEMI_OPEN = 1
6059 19:15:43.571805 CA_FULL_RATE = 0
6060 19:15:43.575416 DQ_CKDIV4_EN = 0
6061 19:15:43.578309 CA_CKDIV4_EN = 1
6062 19:15:43.578389 CA_PREDIV_EN = 0
6063 19:15:43.581984 PH8_DLY = 0
6064 19:15:43.584855 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6065 19:15:43.588584 DQ_AAMCK_DIV = 0
6066 19:15:43.591535 CA_AAMCK_DIV = 0
6067 19:15:43.595204 CA_ADMCK_DIV = 4
6068 19:15:43.598020 DQ_TRACK_CA_EN = 0
6069 19:15:43.598098 CA_PICK = 800
6070 19:15:43.601563 CA_MCKIO = 400
6071 19:15:43.604855 MCKIO_SEMI = 400
6072 19:15:43.608136 PLL_FREQ = 3016
6073 19:15:43.611257 DQ_UI_PI_RATIO = 32
6074 19:15:43.614550 CA_UI_PI_RATIO = 32
6075 19:15:43.617939 ===================================
6076 19:15:43.621153 ===================================
6077 19:15:43.624977 memory_type:LPDDR4
6078 19:15:43.625064 GP_NUM : 10
6079 19:15:43.627751 SRAM_EN : 1
6080 19:15:43.627832 MD32_EN : 0
6081 19:15:43.631115 ===================================
6082 19:15:43.634501 [ANA_INIT] >>>>>>>>>>>>>>
6083 19:15:43.637801 <<<<<< [CONFIGURE PHASE]: ANA_TX
6084 19:15:43.641015 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6085 19:15:43.644685 ===================================
6086 19:15:43.647554 data_rate = 800,PCW = 0X7400
6087 19:15:43.651353 ===================================
6088 19:15:43.654346 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6089 19:15:43.657880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6090 19:15:43.671107 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6091 19:15:43.674808 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6092 19:15:43.677556 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6093 19:15:43.681061 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6094 19:15:43.684674 [ANA_INIT] flow start
6095 19:15:43.687661 [ANA_INIT] PLL >>>>>>>>
6096 19:15:43.687773 [ANA_INIT] PLL <<<<<<<<
6097 19:15:43.691365 [ANA_INIT] MIDPI >>>>>>>>
6098 19:15:43.694248 [ANA_INIT] MIDPI <<<<<<<<
6099 19:15:43.694325 [ANA_INIT] DLL >>>>>>>>
6100 19:15:43.697919 [ANA_INIT] flow end
6101 19:15:43.700863 ============ LP4 DIFF to SE enter ============
6102 19:15:43.704631 ============ LP4 DIFF to SE exit ============
6103 19:15:43.707557 [ANA_INIT] <<<<<<<<<<<<<
6104 19:15:43.711177 [Flow] Enable top DCM control >>>>>
6105 19:15:43.714619 [Flow] Enable top DCM control <<<<<
6106 19:15:43.717552 Enable DLL master slave shuffle
6107 19:15:43.724096 ==============================================================
6108 19:15:43.724209 Gating Mode config
6109 19:15:43.731259 ==============================================================
6110 19:15:43.733937 Config description:
6111 19:15:43.740925 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6112 19:15:43.747560 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6113 19:15:43.754223 SELPH_MODE 0: By rank 1: By Phase
6114 19:15:43.760882 ==============================================================
6115 19:15:43.760966 GAT_TRACK_EN = 0
6116 19:15:43.763870 RX_GATING_MODE = 2
6117 19:15:43.767485 RX_GATING_TRACK_MODE = 2
6118 19:15:43.771084 SELPH_MODE = 1
6119 19:15:43.773838 PICG_EARLY_EN = 1
6120 19:15:43.777135 VALID_LAT_VALUE = 1
6121 19:15:43.784281 ==============================================================
6122 19:15:43.787107 Enter into Gating configuration >>>>
6123 19:15:43.790797 Exit from Gating configuration <<<<
6124 19:15:43.793897 Enter into DVFS_PRE_config >>>>>
6125 19:15:43.804127 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6126 19:15:43.807095 Exit from DVFS_PRE_config <<<<<
6127 19:15:43.810876 Enter into PICG configuration >>>>
6128 19:15:43.813776 Exit from PICG configuration <<<<
6129 19:15:43.817401 [RX_INPUT] configuration >>>>>
6130 19:15:43.817491 [RX_INPUT] configuration <<<<<
6131 19:15:43.823935 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6132 19:15:43.830421 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6133 19:15:43.836934 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6134 19:15:43.840611 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6135 19:15:43.847358 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6136 19:15:43.853796 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6137 19:15:43.856804 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6138 19:15:43.860133 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6139 19:15:43.867058 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6140 19:15:43.870255 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6141 19:15:43.873567 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6142 19:15:43.880080 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6143 19:15:43.883607 ===================================
6144 19:15:43.883690 LPDDR4 DRAM CONFIGURATION
6145 19:15:43.887039 ===================================
6146 19:15:43.890258 EX_ROW_EN[0] = 0x0
6147 19:15:43.890341 EX_ROW_EN[1] = 0x0
6148 19:15:43.893496 LP4Y_EN = 0x0
6149 19:15:43.893588 WORK_FSP = 0x0
6150 19:15:43.896787 WL = 0x2
6151 19:15:43.900325 RL = 0x2
6152 19:15:43.900419 BL = 0x2
6153 19:15:43.903362 RPST = 0x0
6154 19:15:43.903448 RD_PRE = 0x0
6155 19:15:43.907036 WR_PRE = 0x1
6156 19:15:43.907113 WR_PST = 0x0
6157 19:15:43.909822 DBI_WR = 0x0
6158 19:15:43.909911 DBI_RD = 0x0
6159 19:15:43.913581 OTF = 0x1
6160 19:15:43.916564 ===================================
6161 19:15:43.920327 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6162 19:15:43.923423 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6163 19:15:43.926472 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6164 19:15:43.929986 ===================================
6165 19:15:43.933365 LPDDR4 DRAM CONFIGURATION
6166 19:15:43.936305 ===================================
6167 19:15:43.939847 EX_ROW_EN[0] = 0x10
6168 19:15:43.939923 EX_ROW_EN[1] = 0x0
6169 19:15:43.943421 LP4Y_EN = 0x0
6170 19:15:43.943492 WORK_FSP = 0x0
6171 19:15:43.946358 WL = 0x2
6172 19:15:43.946458 RL = 0x2
6173 19:15:43.949991 BL = 0x2
6174 19:15:43.950063 RPST = 0x0
6175 19:15:43.953095 RD_PRE = 0x0
6176 19:15:43.956626 WR_PRE = 0x1
6177 19:15:43.956697 WR_PST = 0x0
6178 19:15:43.959618 DBI_WR = 0x0
6179 19:15:43.959689 DBI_RD = 0x0
6180 19:15:43.963279 OTF = 0x1
6181 19:15:43.966841 ===================================
6182 19:15:43.969651 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6183 19:15:43.975253 nWR fixed to 30
6184 19:15:43.978586 [ModeRegInit_LP4] CH0 RK0
6185 19:15:43.978656 [ModeRegInit_LP4] CH0 RK1
6186 19:15:43.982034 [ModeRegInit_LP4] CH1 RK0
6187 19:15:43.985399 [ModeRegInit_LP4] CH1 RK1
6188 19:15:43.985490 match AC timing 19
6189 19:15:43.991877 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6190 19:15:43.995321 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6191 19:15:43.998138 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6192 19:15:44.005295 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6193 19:15:44.008525 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6194 19:15:44.008614 ==
6195 19:15:44.011882 Dram Type= 6, Freq= 0, CH_0, rank 0
6196 19:15:44.014754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6197 19:15:44.014840 ==
6198 19:15:44.021458 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6199 19:15:44.028007 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6200 19:15:44.031744 [CA 0] Center 36 (8~64) winsize 57
6201 19:15:44.034737 [CA 1] Center 36 (8~64) winsize 57
6202 19:15:44.038178 [CA 2] Center 36 (8~64) winsize 57
6203 19:15:44.041862 [CA 3] Center 36 (8~64) winsize 57
6204 19:15:44.041977 [CA 4] Center 36 (8~64) winsize 57
6205 19:15:44.044854 [CA 5] Center 36 (8~64) winsize 57
6206 19:15:44.044951
6207 19:15:44.051341 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6208 19:15:44.051437
6209 19:15:44.055091 [CATrainingPosCal] consider 1 rank data
6210 19:15:44.057994 u2DelayCellTimex100 = 270/100 ps
6211 19:15:44.061567 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 19:15:44.064584 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 19:15:44.068202 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 19:15:44.071124 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 19:15:44.074824 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 19:15:44.077815 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 19:15:44.077906
6218 19:15:44.081506 CA PerBit enable=1, Macro0, CA PI delay=36
6219 19:15:44.081586
6220 19:15:44.084415 [CBTSetCACLKResult] CA Dly = 36
6221 19:15:44.087990 CS Dly: 1 (0~32)
6222 19:15:44.088074 ==
6223 19:15:44.091724 Dram Type= 6, Freq= 0, CH_0, rank 1
6224 19:15:44.094519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6225 19:15:44.094596 ==
6226 19:15:44.101178 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6227 19:15:44.104237 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6228 19:15:44.107693 [CA 0] Center 36 (8~64) winsize 57
6229 19:15:44.111247 [CA 1] Center 36 (8~64) winsize 57
6230 19:15:44.114837 [CA 2] Center 36 (8~64) winsize 57
6231 19:15:44.117556 [CA 3] Center 36 (8~64) winsize 57
6232 19:15:44.120921 [CA 4] Center 36 (8~64) winsize 57
6233 19:15:44.124221 [CA 5] Center 36 (8~64) winsize 57
6234 19:15:44.124336
6235 19:15:44.127738 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6236 19:15:44.127850
6237 19:15:44.131105 [CATrainingPosCal] consider 2 rank data
6238 19:15:44.134590 u2DelayCellTimex100 = 270/100 ps
6239 19:15:44.137519 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 19:15:44.141123 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 19:15:44.147757 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 19:15:44.151213 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 19:15:44.154132 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 19:15:44.157778 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 19:15:44.157866
6246 19:15:44.161415 CA PerBit enable=1, Macro0, CA PI delay=36
6247 19:15:44.161499
6248 19:15:44.164211 [CBTSetCACLKResult] CA Dly = 36
6249 19:15:44.164296 CS Dly: 1 (0~32)
6250 19:15:44.164371
6251 19:15:44.168041 ----->DramcWriteLeveling(PI) begin...
6252 19:15:44.170920 ==
6253 19:15:44.171000 Dram Type= 6, Freq= 0, CH_0, rank 0
6254 19:15:44.177493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 19:15:44.177584 ==
6256 19:15:44.180630 Write leveling (Byte 0): 40 => 8
6257 19:15:44.184308 Write leveling (Byte 1): 40 => 8
6258 19:15:44.184433 DramcWriteLeveling(PI) end<-----
6259 19:15:44.187339
6260 19:15:44.187418 ==
6261 19:15:44.190977 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 19:15:44.193948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 19:15:44.194037 ==
6264 19:15:44.197666 [Gating] SW mode calibration
6265 19:15:44.204316 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6266 19:15:44.207318 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6267 19:15:44.214130 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6268 19:15:44.217304 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6269 19:15:44.220922 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6270 19:15:44.227392 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 19:15:44.230943 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 19:15:44.234190 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 19:15:44.240410 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 19:15:44.243730 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 19:15:44.247194 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 19:15:44.250819 Total UI for P1: 0, mck2ui 16
6277 19:15:44.253749 best dqsien dly found for B0: ( 0, 14, 24)
6278 19:15:44.257353 Total UI for P1: 0, mck2ui 16
6279 19:15:44.260902 best dqsien dly found for B1: ( 0, 14, 24)
6280 19:15:44.263884 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6281 19:15:44.267488 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6282 19:15:44.267575
6283 19:15:44.274223 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6284 19:15:44.277133 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6285 19:15:44.280620 [Gating] SW calibration Done
6286 19:15:44.280701 ==
6287 19:15:44.284476 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 19:15:44.287430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 19:15:44.287516 ==
6290 19:15:44.287586 RX Vref Scan: 0
6291 19:15:44.287651
6292 19:15:44.290265 RX Vref 0 -> 0, step: 1
6293 19:15:44.290352
6294 19:15:44.293948 RX Delay -410 -> 252, step: 16
6295 19:15:44.297570 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6296 19:15:44.304078 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6297 19:15:44.307064 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6298 19:15:44.310648 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6299 19:15:44.313547 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6300 19:15:44.320254 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6301 19:15:44.323520 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6302 19:15:44.327189 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6303 19:15:44.330091 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6304 19:15:44.336826 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6305 19:15:44.340436 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6306 19:15:44.343050 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6307 19:15:44.346739 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6308 19:15:44.353028 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6309 19:15:44.356399 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6310 19:15:44.359663 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6311 19:15:44.359756 ==
6312 19:15:44.363443 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 19:15:44.369724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 19:15:44.369840 ==
6315 19:15:44.369936 DQS Delay:
6316 19:15:44.373215 DQS0 = 27, DQS1 = 35
6317 19:15:44.373299 DQM Delay:
6318 19:15:44.373364 DQM0 = 9, DQM1 = 11
6319 19:15:44.376849 DQ Delay:
6320 19:15:44.376932 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6321 19:15:44.379766 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6322 19:15:44.383416 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6323 19:15:44.386370 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6324 19:15:44.386456
6325 19:15:44.386523
6326 19:15:44.390039 ==
6327 19:15:44.392971 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 19:15:44.396842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 19:15:44.396927 ==
6330 19:15:44.396999
6331 19:15:44.397060
6332 19:15:44.399829 TX Vref Scan disable
6333 19:15:44.399932 == TX Byte 0 ==
6334 19:15:44.402833 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6335 19:15:44.409388 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6336 19:15:44.409472 == TX Byte 1 ==
6337 19:15:44.412397 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 19:15:44.419057 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 19:15:44.419134 ==
6340 19:15:44.422656 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 19:15:44.426200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 19:15:44.426282 ==
6343 19:15:44.426355
6344 19:15:44.426431
6345 19:15:44.429622 TX Vref Scan disable
6346 19:15:44.429697 == TX Byte 0 ==
6347 19:15:44.432348 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 19:15:44.439443 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 19:15:44.439551 == TX Byte 1 ==
6350 19:15:44.442350 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 19:15:44.448893 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 19:15:44.449004
6353 19:15:44.449097 [DATLAT]
6354 19:15:44.449186 Freq=400, CH0 RK0
6355 19:15:44.452218
6356 19:15:44.452318 DATLAT Default: 0xf
6357 19:15:44.455961 0, 0xFFFF, sum = 0
6358 19:15:44.456059 1, 0xFFFF, sum = 0
6359 19:15:44.459079 2, 0xFFFF, sum = 0
6360 19:15:44.459154 3, 0xFFFF, sum = 0
6361 19:15:44.462593 4, 0xFFFF, sum = 0
6362 19:15:44.462698 5, 0xFFFF, sum = 0
6363 19:15:44.465447 6, 0xFFFF, sum = 0
6364 19:15:44.465524 7, 0xFFFF, sum = 0
6365 19:15:44.468970 8, 0xFFFF, sum = 0
6366 19:15:44.469076 9, 0xFFFF, sum = 0
6367 19:15:44.472331 10, 0xFFFF, sum = 0
6368 19:15:44.472420 11, 0xFFFF, sum = 0
6369 19:15:44.475787 12, 0xFFFF, sum = 0
6370 19:15:44.475870 13, 0x0, sum = 1
6371 19:15:44.478427 14, 0x0, sum = 2
6372 19:15:44.478511 15, 0x0, sum = 3
6373 19:15:44.481899 16, 0x0, sum = 4
6374 19:15:44.481982 best_step = 14
6375 19:15:44.482047
6376 19:15:44.482108 ==
6377 19:15:44.485301 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 19:15:44.492141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 19:15:44.492225 ==
6380 19:15:44.492291 RX Vref Scan: 1
6381 19:15:44.492361
6382 19:15:44.495791 RX Vref 0 -> 0, step: 1
6383 19:15:44.495873
6384 19:15:44.498533 RX Delay -311 -> 252, step: 8
6385 19:15:44.498616
6386 19:15:44.502272 Set Vref, RX VrefLevel [Byte0]: 56
6387 19:15:44.505823 [Byte1]: 47
6388 19:15:44.505901
6389 19:15:44.508814 Final RX Vref Byte 0 = 56 to rank0
6390 19:15:44.512315 Final RX Vref Byte 1 = 47 to rank0
6391 19:15:44.515244 Final RX Vref Byte 0 = 56 to rank1
6392 19:15:44.519065 Final RX Vref Byte 1 = 47 to rank1==
6393 19:15:44.521998 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 19:15:44.525504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 19:15:44.525598 ==
6396 19:15:44.529061 DQS Delay:
6397 19:15:44.529151 DQS0 = 28, DQS1 = 36
6398 19:15:44.531945 DQM Delay:
6399 19:15:44.532030 DQM0 = 10, DQM1 = 12
6400 19:15:44.535662 DQ Delay:
6401 19:15:44.535763 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6402 19:15:44.538399 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6403 19:15:44.541815 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6404 19:15:44.545766 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6405 19:15:44.545869
6406 19:15:44.545976
6407 19:15:44.555122 [DQSOSCAuto] RK0, (LSB)MR18= 0xcfbd, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6408 19:15:44.558647 CH0 RK0: MR19=C0C, MR18=CFBD
6409 19:15:44.562409 CH0_RK0: MR19=0xC0C, MR18=0xCFBD, DQSOSC=384, MR23=63, INC=400, DEC=267
6410 19:15:44.565435 ==
6411 19:15:44.569118 Dram Type= 6, Freq= 0, CH_0, rank 1
6412 19:15:44.571985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 19:15:44.572088 ==
6414 19:15:44.575016 [Gating] SW mode calibration
6415 19:15:44.581604 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6416 19:15:44.585022 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6417 19:15:44.591980 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6418 19:15:44.595474 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6419 19:15:44.598420 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6420 19:15:44.605464 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 19:15:44.608412 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6422 19:15:44.612103 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 19:15:44.618575 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 19:15:44.621525 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 19:15:44.625284 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 19:15:44.628270 Total UI for P1: 0, mck2ui 16
6427 19:15:44.631884 best dqsien dly found for B0: ( 0, 14, 24)
6428 19:15:44.634824 Total UI for P1: 0, mck2ui 16
6429 19:15:44.638373 best dqsien dly found for B1: ( 0, 14, 24)
6430 19:15:44.641391 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6431 19:15:44.645025 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6432 19:15:44.645109
6433 19:15:44.651375 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6434 19:15:44.654901 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6435 19:15:44.654986 [Gating] SW calibration Done
6436 19:15:44.658293 ==
6437 19:15:44.661816 Dram Type= 6, Freq= 0, CH_0, rank 1
6438 19:15:44.665179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 19:15:44.665289 ==
6440 19:15:44.665357 RX Vref Scan: 0
6441 19:15:44.665421
6442 19:15:44.668747 RX Vref 0 -> 0, step: 1
6443 19:15:44.668831
6444 19:15:44.671661 RX Delay -410 -> 252, step: 16
6445 19:15:44.675173 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6446 19:15:44.678222 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6447 19:15:44.684868 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6448 19:15:44.688503 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6449 19:15:44.691357 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6450 19:15:44.694871 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6451 19:15:44.701230 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6452 19:15:44.705103 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6453 19:15:44.708547 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6454 19:15:44.711421 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6455 19:15:44.717956 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6456 19:15:44.721674 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6457 19:15:44.724557 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6458 19:15:44.728213 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6459 19:15:44.734643 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6460 19:15:44.738057 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6461 19:15:44.738162 ==
6462 19:15:44.741736 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 19:15:44.744614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 19:15:44.744707 ==
6465 19:15:44.748328 DQS Delay:
6466 19:15:44.748432 DQS0 = 27, DQS1 = 35
6467 19:15:44.751214 DQM Delay:
6468 19:15:44.751310 DQM0 = 12, DQM1 = 11
6469 19:15:44.751376 DQ Delay:
6470 19:15:44.754913 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6471 19:15:44.757791 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6472 19:15:44.761335 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6473 19:15:44.764614 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6474 19:15:44.764691
6475 19:15:44.764759
6476 19:15:44.764819 ==
6477 19:15:44.768260 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 19:15:44.774534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 19:15:44.774639 ==
6480 19:15:44.774711
6481 19:15:44.774776
6482 19:15:44.774838 TX Vref Scan disable
6483 19:15:44.777927 == TX Byte 0 ==
6484 19:15:44.781395 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6485 19:15:44.784315 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6486 19:15:44.788114 == TX Byte 1 ==
6487 19:15:44.791041 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6488 19:15:44.794572 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6489 19:15:44.794659 ==
6490 19:15:44.797638 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 19:15:44.804200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 19:15:44.804283 ==
6493 19:15:44.804367
6494 19:15:44.804428
6495 19:15:44.804493 TX Vref Scan disable
6496 19:15:44.807710 == TX Byte 0 ==
6497 19:15:44.811100 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6498 19:15:44.814407 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6499 19:15:44.818024 == TX Byte 1 ==
6500 19:15:44.820798 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6501 19:15:44.824277 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6502 19:15:44.824392
6503 19:15:44.827838 [DATLAT]
6504 19:15:44.827946 Freq=400, CH0 RK1
6505 19:15:44.828040
6506 19:15:44.830787 DATLAT Default: 0xe
6507 19:15:44.830873 0, 0xFFFF, sum = 0
6508 19:15:44.834316 1, 0xFFFF, sum = 0
6509 19:15:44.834400 2, 0xFFFF, sum = 0
6510 19:15:44.837242 3, 0xFFFF, sum = 0
6511 19:15:44.837324 4, 0xFFFF, sum = 0
6512 19:15:44.840778 5, 0xFFFF, sum = 0
6513 19:15:44.840855 6, 0xFFFF, sum = 0
6514 19:15:44.844263 7, 0xFFFF, sum = 0
6515 19:15:44.844380 8, 0xFFFF, sum = 0
6516 19:15:44.847243 9, 0xFFFF, sum = 0
6517 19:15:44.847325 10, 0xFFFF, sum = 0
6518 19:15:44.851021 11, 0xFFFF, sum = 0
6519 19:15:44.854006 12, 0xFFFF, sum = 0
6520 19:15:44.854087 13, 0x0, sum = 1
6521 19:15:44.857756 14, 0x0, sum = 2
6522 19:15:44.857838 15, 0x0, sum = 3
6523 19:15:44.857907 16, 0x0, sum = 4
6524 19:15:44.860717 best_step = 14
6525 19:15:44.860799
6526 19:15:44.860865 ==
6527 19:15:44.864250 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 19:15:44.867824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 19:15:44.867913 ==
6530 19:15:44.870515 RX Vref Scan: 0
6531 19:15:44.870603
6532 19:15:44.870670 RX Vref 0 -> 0, step: 1
6533 19:15:44.870743
6534 19:15:44.874274 RX Delay -311 -> 252, step: 8
6535 19:15:44.882325 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6536 19:15:44.885896 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6537 19:15:44.888613 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6538 19:15:44.892574 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6539 19:15:44.899098 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6540 19:15:44.902142 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6541 19:15:44.905950 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6542 19:15:44.908866 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6543 19:15:44.915516 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6544 19:15:44.918954 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6545 19:15:44.922362 iDelay=217, Bit 10, Center -24 (-239 ~ 192) 432
6546 19:15:44.925801 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6547 19:15:44.931958 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6548 19:15:44.936056 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6549 19:15:44.938677 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6550 19:15:44.942155 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6551 19:15:44.945598 ==
6552 19:15:44.949129 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 19:15:44.952244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 19:15:44.952365 ==
6555 19:15:44.952454 DQS Delay:
6556 19:15:44.955671 DQS0 = 24, DQS1 = 36
6557 19:15:44.955758 DQM Delay:
6558 19:15:44.958594 DQM0 = 9, DQM1 = 12
6559 19:15:44.958681 DQ Delay:
6560 19:15:44.962096 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6561 19:15:44.965788 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6562 19:15:44.968777 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6563 19:15:44.972330 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6564 19:15:44.972447
6565 19:15:44.972547
6566 19:15:44.978629 [DQSOSCAuto] RK1, (LSB)MR18= 0xb657, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
6567 19:15:44.982368 CH0 RK1: MR19=C0C, MR18=B657
6568 19:15:44.989010 CH0_RK1: MR19=0xC0C, MR18=0xB657, DQSOSC=387, MR23=63, INC=394, DEC=262
6569 19:15:44.992513 [RxdqsGatingPostProcess] freq 400
6570 19:15:44.995334 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6571 19:15:44.998785 best DQS0 dly(2T, 0.5T) = (0, 10)
6572 19:15:45.002113 best DQS1 dly(2T, 0.5T) = (0, 10)
6573 19:15:45.005535 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6574 19:15:45.008479 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6575 19:15:45.012354 best DQS0 dly(2T, 0.5T) = (0, 10)
6576 19:15:45.015425 best DQS1 dly(2T, 0.5T) = (0, 10)
6577 19:15:45.018443 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6578 19:15:45.022273 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6579 19:15:45.025154 Pre-setting of DQS Precalculation
6580 19:15:45.028650 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6581 19:15:45.028742 ==
6582 19:15:45.032154 Dram Type= 6, Freq= 0, CH_1, rank 0
6583 19:15:45.038684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 19:15:45.038797 ==
6585 19:15:45.042296 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6586 19:15:45.048724 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6587 19:15:45.052198 [CA 0] Center 36 (8~64) winsize 57
6588 19:15:45.055166 [CA 1] Center 36 (8~64) winsize 57
6589 19:15:45.058703 [CA 2] Center 36 (8~64) winsize 57
6590 19:15:45.062043 [CA 3] Center 36 (8~64) winsize 57
6591 19:15:45.065347 [CA 4] Center 36 (8~64) winsize 57
6592 19:15:45.068579 [CA 5] Center 36 (8~64) winsize 57
6593 19:15:45.068684
6594 19:15:45.071453 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6595 19:15:45.071559
6596 19:15:45.075082 [CATrainingPosCal] consider 1 rank data
6597 19:15:45.078637 u2DelayCellTimex100 = 270/100 ps
6598 19:15:45.081656 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 19:15:45.085110 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 19:15:45.088086 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 19:15:45.091752 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 19:15:45.094775 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 19:15:45.101437 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 19:15:45.101541
6605 19:15:45.105236 CA PerBit enable=1, Macro0, CA PI delay=36
6606 19:15:45.105353
6607 19:15:45.107953 [CBTSetCACLKResult] CA Dly = 36
6608 19:15:45.108054 CS Dly: 1 (0~32)
6609 19:15:45.108145 ==
6610 19:15:45.111501 Dram Type= 6, Freq= 0, CH_1, rank 1
6611 19:15:45.114868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 19:15:45.118574 ==
6613 19:15:45.121441 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6614 19:15:45.128045 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6615 19:15:45.131575 [CA 0] Center 36 (8~64) winsize 57
6616 19:15:45.134508 [CA 1] Center 36 (8~64) winsize 57
6617 19:15:45.138013 [CA 2] Center 36 (8~64) winsize 57
6618 19:15:45.141506 [CA 3] Center 36 (8~64) winsize 57
6619 19:15:45.145032 [CA 4] Center 36 (8~64) winsize 57
6620 19:15:45.147806 [CA 5] Center 36 (8~64) winsize 57
6621 19:15:45.147919
6622 19:15:45.151440 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6623 19:15:45.151581
6624 19:15:45.154937 [CATrainingPosCal] consider 2 rank data
6625 19:15:45.157824 u2DelayCellTimex100 = 270/100 ps
6626 19:15:45.161537 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 19:15:45.164507 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 19:15:45.168160 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 19:15:45.171105 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 19:15:45.174417 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 19:15:45.177718 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 19:15:45.177813
6633 19:15:45.181184 CA PerBit enable=1, Macro0, CA PI delay=36
6634 19:15:45.184575
6635 19:15:45.184692 [CBTSetCACLKResult] CA Dly = 36
6636 19:15:45.188067 CS Dly: 1 (0~32)
6637 19:15:45.188181
6638 19:15:45.191348 ----->DramcWriteLeveling(PI) begin...
6639 19:15:45.191443 ==
6640 19:15:45.194744 Dram Type= 6, Freq= 0, CH_1, rank 0
6641 19:15:45.197682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 19:15:45.197793 ==
6643 19:15:45.201376 Write leveling (Byte 0): 40 => 8
6644 19:15:45.204529 Write leveling (Byte 1): 40 => 8
6645 19:15:45.208177 DramcWriteLeveling(PI) end<-----
6646 19:15:45.208289
6647 19:15:45.208399 ==
6648 19:15:45.211192 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 19:15:45.214197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 19:15:45.214304 ==
6651 19:15:45.217693 [Gating] SW mode calibration
6652 19:15:45.224080 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6653 19:15:45.231233 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6654 19:15:45.234200 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6655 19:15:45.240822 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6656 19:15:45.244354 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6657 19:15:45.247366 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 19:15:45.254327 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 19:15:45.257113 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 19:15:45.260777 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 19:15:45.267397 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 19:15:45.271133 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 19:15:45.274140 Total UI for P1: 0, mck2ui 16
6664 19:15:45.277835 best dqsien dly found for B0: ( 0, 14, 24)
6665 19:15:45.280833 Total UI for P1: 0, mck2ui 16
6666 19:15:45.284307 best dqsien dly found for B1: ( 0, 14, 24)
6667 19:15:45.287141 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6668 19:15:45.290591 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6669 19:15:45.290683
6670 19:15:45.293993 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6671 19:15:45.297537 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6672 19:15:45.300909 [Gating] SW calibration Done
6673 19:15:45.301016 ==
6674 19:15:45.303655 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 19:15:45.307092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 19:15:45.307221 ==
6677 19:15:45.310714 RX Vref Scan: 0
6678 19:15:45.310828
6679 19:15:45.314358 RX Vref 0 -> 0, step: 1
6680 19:15:45.314466
6681 19:15:45.314571 RX Delay -410 -> 252, step: 16
6682 19:15:45.321096 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6683 19:15:45.323984 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6684 19:15:45.327635 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6685 19:15:45.330428 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6686 19:15:45.337600 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6687 19:15:45.340563 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6688 19:15:45.344349 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6689 19:15:45.347314 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6690 19:15:45.353745 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6691 19:15:45.357323 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6692 19:15:45.360927 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6693 19:15:45.363761 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6694 19:15:45.370738 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6695 19:15:45.373802 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6696 19:15:45.377442 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6697 19:15:45.383987 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6698 19:15:45.384088 ==
6699 19:15:45.386930 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 19:15:45.390732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 19:15:45.390811 ==
6702 19:15:45.390875 DQS Delay:
6703 19:15:45.393662 DQS0 = 35, DQS1 = 35
6704 19:15:45.393774 DQM Delay:
6705 19:15:45.397156 DQM0 = 18, DQM1 = 13
6706 19:15:45.397235 DQ Delay:
6707 19:15:45.400583 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6708 19:15:45.403850 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6709 19:15:45.407457 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6710 19:15:45.410425 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6711 19:15:45.410502
6712 19:15:45.410590
6713 19:15:45.410654 ==
6714 19:15:45.413931 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 19:15:45.417315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 19:15:45.417416 ==
6717 19:15:45.417519
6718 19:15:45.417612
6719 19:15:45.420687 TX Vref Scan disable
6720 19:15:45.420792 == TX Byte 0 ==
6721 19:15:45.427426 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6722 19:15:45.430980 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6723 19:15:45.431080 == TX Byte 1 ==
6724 19:15:45.437604 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 19:15:45.440262 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 19:15:45.440398 ==
6727 19:15:45.443614 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 19:15:45.447181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 19:15:45.447296 ==
6730 19:15:45.447400
6731 19:15:45.447510
6732 19:15:45.450460 TX Vref Scan disable
6733 19:15:45.450560 == TX Byte 0 ==
6734 19:15:45.457628 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 19:15:45.460503 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 19:15:45.460643 == TX Byte 1 ==
6737 19:15:45.466959 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 19:15:45.470344 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 19:15:45.470441
6740 19:15:45.470538 [DATLAT]
6741 19:15:45.474078 Freq=400, CH1 RK0
6742 19:15:45.474175
6743 19:15:45.474270 DATLAT Default: 0xf
6744 19:15:45.477334 0, 0xFFFF, sum = 0
6745 19:15:45.477470 1, 0xFFFF, sum = 0
6746 19:15:45.480962 2, 0xFFFF, sum = 0
6747 19:15:45.481139 3, 0xFFFF, sum = 0
6748 19:15:45.483896 4, 0xFFFF, sum = 0
6749 19:15:45.484037 5, 0xFFFF, sum = 0
6750 19:15:45.487621 6, 0xFFFF, sum = 0
6751 19:15:45.487731 7, 0xFFFF, sum = 0
6752 19:15:45.490622 8, 0xFFFF, sum = 0
6753 19:15:45.490697 9, 0xFFFF, sum = 0
6754 19:15:45.494352 10, 0xFFFF, sum = 0
6755 19:15:45.497396 11, 0xFFFF, sum = 0
6756 19:15:45.497496 12, 0xFFFF, sum = 0
6757 19:15:45.500414 13, 0x0, sum = 1
6758 19:15:45.500520 14, 0x0, sum = 2
6759 19:15:45.500666 15, 0x0, sum = 3
6760 19:15:45.504110 16, 0x0, sum = 4
6761 19:15:45.504241 best_step = 14
6762 19:15:45.504345
6763 19:15:45.506990 ==
6764 19:15:45.507093 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 19:15:45.513759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 19:15:45.513865 ==
6767 19:15:45.513961 RX Vref Scan: 1
6768 19:15:45.514047
6769 19:15:45.517130 RX Vref 0 -> 0, step: 1
6770 19:15:45.517261
6771 19:15:45.520762 RX Delay -311 -> 252, step: 8
6772 19:15:45.520878
6773 19:15:45.523602 Set Vref, RX VrefLevel [Byte0]: 53
6774 19:15:45.527059 [Byte1]: 47
6775 19:15:45.530579
6776 19:15:45.530693 Final RX Vref Byte 0 = 53 to rank0
6777 19:15:45.534315 Final RX Vref Byte 1 = 47 to rank0
6778 19:15:45.537303 Final RX Vref Byte 0 = 53 to rank1
6779 19:15:45.540344 Final RX Vref Byte 1 = 47 to rank1==
6780 19:15:45.544047 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 19:15:45.550476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 19:15:45.550601 ==
6783 19:15:45.550717 DQS Delay:
6784 19:15:45.554209 DQS0 = 32, DQS1 = 36
6785 19:15:45.554316 DQM Delay:
6786 19:15:45.554425 DQM0 = 13, DQM1 = 15
6787 19:15:45.557181 DQ Delay:
6788 19:15:45.560147 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6789 19:15:45.560259 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6790 19:15:45.563700 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6791 19:15:45.567497 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =24
6792 19:15:45.567583
6793 19:15:45.570331
6794 19:15:45.577443 [DQSOSCAuto] RK0, (LSB)MR18= 0x94cd, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6795 19:15:45.580409 CH1 RK0: MR19=C0C, MR18=94CD
6796 19:15:45.587035 CH1_RK0: MR19=0xC0C, MR18=0x94CD, DQSOSC=384, MR23=63, INC=400, DEC=267
6797 19:15:45.587156 ==
6798 19:15:45.590762 Dram Type= 6, Freq= 0, CH_1, rank 1
6799 19:15:45.593656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 19:15:45.593766 ==
6801 19:15:45.597571 [Gating] SW mode calibration
6802 19:15:45.603677 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6803 19:15:45.610338 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6804 19:15:45.614055 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6805 19:15:45.617073 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6806 19:15:45.623224 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6807 19:15:45.626631 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6808 19:15:45.630248 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6809 19:15:45.636618 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 19:15:45.639911 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 19:15:45.643166 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 19:15:45.647179 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 19:15:45.650053 Total UI for P1: 0, mck2ui 16
6814 19:15:45.653523 best dqsien dly found for B0: ( 0, 14, 24)
6815 19:15:45.657115 Total UI for P1: 0, mck2ui 16
6816 19:15:45.659762 best dqsien dly found for B1: ( 0, 14, 24)
6817 19:15:45.663210 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6818 19:15:45.670250 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6819 19:15:45.670360
6820 19:15:45.673230 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6821 19:15:45.676856 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6822 19:15:45.679917 [Gating] SW calibration Done
6823 19:15:45.680024 ==
6824 19:15:45.683450 Dram Type= 6, Freq= 0, CH_1, rank 1
6825 19:15:45.686925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 19:15:45.687046 ==
6827 19:15:45.689844 RX Vref Scan: 0
6828 19:15:45.689917
6829 19:15:45.689979 RX Vref 0 -> 0, step: 1
6830 19:15:45.690045
6831 19:15:45.693351 RX Delay -410 -> 252, step: 16
6832 19:15:45.696227 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6833 19:15:45.703372 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6834 19:15:45.706207 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6835 19:15:45.709999 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6836 19:15:45.712969 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6837 19:15:45.719505 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6838 19:15:45.723263 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6839 19:15:45.726109 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6840 19:15:45.729741 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6841 19:15:45.736107 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6842 19:15:45.739891 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6843 19:15:45.743340 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6844 19:15:45.746327 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6845 19:15:45.752968 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6846 19:15:45.756272 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6847 19:15:45.759675 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6848 19:15:45.759749 ==
6849 19:15:45.763277 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 19:15:45.766879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 19:15:45.769803 ==
6852 19:15:45.769906 DQS Delay:
6853 19:15:45.770014 DQS0 = 35, DQS1 = 35
6854 19:15:45.773346 DQM Delay:
6855 19:15:45.773458 DQM0 = 18, DQM1 = 13
6856 19:15:45.776226 DQ Delay:
6857 19:15:45.780000 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6858 19:15:45.780120 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6859 19:15:45.783057 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6860 19:15:45.786804 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6861 19:15:45.786884
6862 19:15:45.786947
6863 19:15:45.789740 ==
6864 19:15:45.793332 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 19:15:45.796082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 19:15:45.796181 ==
6867 19:15:45.796272
6868 19:15:45.796369
6869 19:15:45.799553 TX Vref Scan disable
6870 19:15:45.799625 == TX Byte 0 ==
6871 19:15:45.803136 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6872 19:15:45.809725 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6873 19:15:45.809810 == TX Byte 1 ==
6874 19:15:45.812558 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6875 19:15:45.819303 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6876 19:15:45.819380 ==
6877 19:15:45.822819 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 19:15:45.826433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 19:15:45.826520 ==
6880 19:15:45.826588
6881 19:15:45.826650
6882 19:15:45.830162 TX Vref Scan disable
6883 19:15:45.830246 == TX Byte 0 ==
6884 19:15:45.833649 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6885 19:15:45.839485 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6886 19:15:45.839571 == TX Byte 1 ==
6887 19:15:45.842930 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6888 19:15:45.849406 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6889 19:15:45.849488
6890 19:15:45.849561 [DATLAT]
6891 19:15:45.849623 Freq=400, CH1 RK1
6892 19:15:45.849682
6893 19:15:45.853013 DATLAT Default: 0xe
6894 19:15:45.853082 0, 0xFFFF, sum = 0
6895 19:15:45.855931 1, 0xFFFF, sum = 0
6896 19:15:45.859431 2, 0xFFFF, sum = 0
6897 19:15:45.859503 3, 0xFFFF, sum = 0
6898 19:15:45.862848 4, 0xFFFF, sum = 0
6899 19:15:45.862929 5, 0xFFFF, sum = 0
6900 19:15:45.866109 6, 0xFFFF, sum = 0
6901 19:15:45.866183 7, 0xFFFF, sum = 0
6902 19:15:45.869278 8, 0xFFFF, sum = 0
6903 19:15:45.869355 9, 0xFFFF, sum = 0
6904 19:15:45.872650 10, 0xFFFF, sum = 0
6905 19:15:45.872760 11, 0xFFFF, sum = 0
6906 19:15:45.875944 12, 0xFFFF, sum = 0
6907 19:15:45.876034 13, 0x0, sum = 1
6908 19:15:45.879368 14, 0x0, sum = 2
6909 19:15:45.879453 15, 0x0, sum = 3
6910 19:15:45.882788 16, 0x0, sum = 4
6911 19:15:45.882872 best_step = 14
6912 19:15:45.882938
6913 19:15:45.882999 ==
6914 19:15:45.886128 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 19:15:45.889133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 19:15:45.892670 ==
6917 19:15:45.892754 RX Vref Scan: 0
6918 19:15:45.892820
6919 19:15:45.895554 RX Vref 0 -> 0, step: 1
6920 19:15:45.895637
6921 19:15:45.899046 RX Delay -311 -> 252, step: 8
6922 19:15:45.902794 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6923 19:15:45.909171 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6924 19:15:45.912653 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6925 19:15:45.916234 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6926 19:15:45.919153 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6927 19:15:45.925840 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6928 19:15:45.929367 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6929 19:15:45.932256 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6930 19:15:45.935867 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6931 19:15:45.942312 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6932 19:15:45.945941 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6933 19:15:45.949352 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6934 19:15:45.952348 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6935 19:15:45.959237 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6936 19:15:45.962125 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6937 19:15:45.965865 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6938 19:15:45.965949 ==
6939 19:15:45.968790 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 19:15:45.975890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 19:15:45.975989 ==
6942 19:15:45.976060 DQS Delay:
6943 19:15:45.979466 DQS0 = 32, DQS1 = 32
6944 19:15:45.979563 DQM Delay:
6945 19:15:45.979638 DQM0 = 13, DQM1 = 11
6946 19:15:45.982086 DQ Delay:
6947 19:15:45.985364 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6948 19:15:45.988692 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6949 19:15:45.988776 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6950 19:15:45.992002 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6951 19:15:45.992085
6952 19:15:45.995792
6953 19:15:46.001907 [DQSOSCAuto] RK1, (LSB)MR18= 0xc051, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 386 ps
6954 19:15:46.005341 CH1 RK1: MR19=C0C, MR18=C051
6955 19:15:46.012290 CH1_RK1: MR19=0xC0C, MR18=0xC051, DQSOSC=386, MR23=63, INC=396, DEC=264
6956 19:15:46.015794 [RxdqsGatingPostProcess] freq 400
6957 19:15:46.018538 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6958 19:15:46.022279 best DQS0 dly(2T, 0.5T) = (0, 10)
6959 19:15:46.025187 best DQS1 dly(2T, 0.5T) = (0, 10)
6960 19:15:46.028865 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6961 19:15:46.031856 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6962 19:15:46.035503 best DQS0 dly(2T, 0.5T) = (0, 10)
6963 19:15:46.039060 best DQS1 dly(2T, 0.5T) = (0, 10)
6964 19:15:46.042113 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6965 19:15:46.045031 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6966 19:15:46.048596 Pre-setting of DQS Precalculation
6967 19:15:46.052206 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6968 19:15:46.058542 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6969 19:15:46.068827 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6970 19:15:46.068939
6971 19:15:46.069032
6972 19:15:46.071908 [Calibration Summary] 800 Mbps
6973 19:15:46.072021 CH 0, Rank 0
6974 19:15:46.074892 SW Impedance : PASS
6975 19:15:46.074980 DUTY Scan : NO K
6976 19:15:46.078527 ZQ Calibration : PASS
6977 19:15:46.081579 Jitter Meter : NO K
6978 19:15:46.081653 CBT Training : PASS
6979 19:15:46.085310 Write leveling : PASS
6980 19:15:46.085395 RX DQS gating : PASS
6981 19:15:46.088243 RX DQ/DQS(RDDQC) : PASS
6982 19:15:46.091863 TX DQ/DQS : PASS
6983 19:15:46.091948 RX DATLAT : PASS
6984 19:15:46.095408 RX DQ/DQS(Engine): PASS
6985 19:15:46.098238 TX OE : NO K
6986 19:15:46.098315 All Pass.
6987 19:15:46.098379
6988 19:15:46.098445 CH 0, Rank 1
6989 19:15:46.101725 SW Impedance : PASS
6990 19:15:46.105138 DUTY Scan : NO K
6991 19:15:46.105240 ZQ Calibration : PASS
6992 19:15:46.108375 Jitter Meter : NO K
6993 19:15:46.111805 CBT Training : PASS
6994 19:15:46.111882 Write leveling : NO K
6995 19:15:46.115148 RX DQS gating : PASS
6996 19:15:46.118650 RX DQ/DQS(RDDQC) : PASS
6997 19:15:46.118728 TX DQ/DQS : PASS
6998 19:15:46.121447 RX DATLAT : PASS
6999 19:15:46.124855 RX DQ/DQS(Engine): PASS
7000 19:15:46.124930 TX OE : NO K
7001 19:15:46.125002 All Pass.
7002 19:15:46.128278
7003 19:15:46.128387 CH 1, Rank 0
7004 19:15:46.131656 SW Impedance : PASS
7005 19:15:46.131758 DUTY Scan : NO K
7006 19:15:46.135054 ZQ Calibration : PASS
7007 19:15:46.135155 Jitter Meter : NO K
7008 19:15:46.138343 CBT Training : PASS
7009 19:15:46.141854 Write leveling : PASS
7010 19:15:46.141961 RX DQS gating : PASS
7011 19:15:46.144751 RX DQ/DQS(RDDQC) : PASS
7012 19:15:46.148512 TX DQ/DQS : PASS
7013 19:15:46.148592 RX DATLAT : PASS
7014 19:15:46.151437 RX DQ/DQS(Engine): PASS
7015 19:15:46.154998 TX OE : NO K
7016 19:15:46.155101 All Pass.
7017 19:15:46.155190
7018 19:15:46.155281 CH 1, Rank 1
7019 19:15:46.157964 SW Impedance : PASS
7020 19:15:46.161480 DUTY Scan : NO K
7021 19:15:46.161592 ZQ Calibration : PASS
7022 19:15:46.165150 Jitter Meter : NO K
7023 19:15:46.168033 CBT Training : PASS
7024 19:15:46.168117 Write leveling : NO K
7025 19:15:46.171581 RX DQS gating : PASS
7026 19:15:46.174683 RX DQ/DQS(RDDQC) : PASS
7027 19:15:46.174767 TX DQ/DQS : PASS
7028 19:15:46.178264 RX DATLAT : PASS
7029 19:15:46.181132 RX DQ/DQS(Engine): PASS
7030 19:15:46.181215 TX OE : NO K
7031 19:15:46.181281 All Pass.
7032 19:15:46.184665
7033 19:15:46.184748 DramC Write-DBI off
7034 19:15:46.188264 PER_BANK_REFRESH: Hybrid Mode
7035 19:15:46.188382 TX_TRACKING: ON
7036 19:15:46.197827 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7037 19:15:46.201448 [FAST_K] Save calibration result to emmc
7038 19:15:46.204991 dramc_set_vcore_voltage set vcore to 725000
7039 19:15:46.207844 Read voltage for 1600, 0
7040 19:15:46.207927 Vio18 = 0
7041 19:15:46.211494 Vcore = 725000
7042 19:15:46.211576 Vdram = 0
7043 19:15:46.211643 Vddq = 0
7044 19:15:46.211704 Vmddr = 0
7045 19:15:46.217789 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7046 19:15:46.224816 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7047 19:15:46.224941 MEM_TYPE=3, freq_sel=13
7048 19:15:46.227577 sv_algorithm_assistance_LP4_3733
7049 19:15:46.231238 ============ PULL DRAM RESETB DOWN ============
7050 19:15:46.237599 ========== PULL DRAM RESETB DOWN end =========
7051 19:15:46.241284 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7052 19:15:46.244753 ===================================
7053 19:15:46.247494 LPDDR4 DRAM CONFIGURATION
7054 19:15:46.250801 ===================================
7055 19:15:46.250906 EX_ROW_EN[0] = 0x0
7056 19:15:46.254064 EX_ROW_EN[1] = 0x0
7057 19:15:46.254166 LP4Y_EN = 0x0
7058 19:15:46.257950 WORK_FSP = 0x1
7059 19:15:46.260809 WL = 0x5
7060 19:15:46.260884 RL = 0x5
7061 19:15:46.264396 BL = 0x2
7062 19:15:46.264477 RPST = 0x0
7063 19:15:46.267852 RD_PRE = 0x0
7064 19:15:46.267935 WR_PRE = 0x1
7065 19:15:46.270812 WR_PST = 0x1
7066 19:15:46.270892 DBI_WR = 0x0
7067 19:15:46.274506 DBI_RD = 0x0
7068 19:15:46.274602 OTF = 0x1
7069 19:15:46.277498 ===================================
7070 19:15:46.281150 ===================================
7071 19:15:46.284125 ANA top config
7072 19:15:46.287763 ===================================
7073 19:15:46.287859 DLL_ASYNC_EN = 0
7074 19:15:46.290623 ALL_SLAVE_EN = 0
7075 19:15:46.294268 NEW_RANK_MODE = 1
7076 19:15:46.297275 DLL_IDLE_MODE = 1
7077 19:15:46.297381 LP45_APHY_COMB_EN = 1
7078 19:15:46.300896 TX_ODT_DIS = 0
7079 19:15:46.303787 NEW_8X_MODE = 1
7080 19:15:46.307492 ===================================
7081 19:15:46.310505 ===================================
7082 19:15:46.313957 data_rate = 3200
7083 19:15:46.317726 CKR = 1
7084 19:15:46.320599 DQ_P2S_RATIO = 8
7085 19:15:46.324058 ===================================
7086 19:15:46.324180 CA_P2S_RATIO = 8
7087 19:15:46.327529 DQ_CA_OPEN = 0
7088 19:15:46.330260 DQ_SEMI_OPEN = 0
7089 19:15:46.333954 CA_SEMI_OPEN = 0
7090 19:15:46.336788 CA_FULL_RATE = 0
7091 19:15:46.340091 DQ_CKDIV4_EN = 0
7092 19:15:46.340217 CA_CKDIV4_EN = 0
7093 19:15:46.343794 CA_PREDIV_EN = 0
7094 19:15:46.347224 PH8_DLY = 12
7095 19:15:46.350333 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7096 19:15:46.354074 DQ_AAMCK_DIV = 4
7097 19:15:46.357047 CA_AAMCK_DIV = 4
7098 19:15:46.357125 CA_ADMCK_DIV = 4
7099 19:15:46.360546 DQ_TRACK_CA_EN = 0
7100 19:15:46.363853 CA_PICK = 1600
7101 19:15:46.367175 CA_MCKIO = 1600
7102 19:15:46.370412 MCKIO_SEMI = 0
7103 19:15:46.373647 PLL_FREQ = 3068
7104 19:15:46.377504 DQ_UI_PI_RATIO = 32
7105 19:15:46.377623 CA_UI_PI_RATIO = 0
7106 19:15:46.380887 ===================================
7107 19:15:46.383669 ===================================
7108 19:15:46.387306 memory_type:LPDDR4
7109 19:15:46.390931 GP_NUM : 10
7110 19:15:46.391040 SRAM_EN : 1
7111 19:15:46.393801 MD32_EN : 0
7112 19:15:46.397515 ===================================
7113 19:15:46.400470 [ANA_INIT] >>>>>>>>>>>>>>
7114 19:15:46.403467 <<<<<< [CONFIGURE PHASE]: ANA_TX
7115 19:15:46.407230 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7116 19:15:46.410941 ===================================
7117 19:15:46.411044 data_rate = 3200,PCW = 0X7600
7118 19:15:46.413974 ===================================
7119 19:15:46.416773 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7120 19:15:46.430513 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7121 19:15:46.430670 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7122 19:15:46.433775 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7123 19:15:46.437241 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7124 19:15:46.440034 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7125 19:15:46.443622 [ANA_INIT] flow start
7126 19:15:46.443715 [ANA_INIT] PLL >>>>>>>>
7127 19:15:46.447222 [ANA_INIT] PLL <<<<<<<<
7128 19:15:46.450104 [ANA_INIT] MIDPI >>>>>>>>
7129 19:15:46.453611 [ANA_INIT] MIDPI <<<<<<<<
7130 19:15:46.453697 [ANA_INIT] DLL >>>>>>>>
7131 19:15:46.457070 [ANA_INIT] DLL <<<<<<<<
7132 19:15:46.460023 [ANA_INIT] flow end
7133 19:15:46.463839 ============ LP4 DIFF to SE enter ============
7134 19:15:46.466877 ============ LP4 DIFF to SE exit ============
7135 19:15:46.469850 [ANA_INIT] <<<<<<<<<<<<<
7136 19:15:46.473493 [Flow] Enable top DCM control >>>>>
7137 19:15:46.477039 [Flow] Enable top DCM control <<<<<
7138 19:15:46.480590 Enable DLL master slave shuffle
7139 19:15:46.483333 ==============================================================
7140 19:15:46.486658 Gating Mode config
7141 19:15:46.490223 ==============================================================
7142 19:15:46.493305 Config description:
7143 19:15:46.503356 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7144 19:15:46.509792 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7145 19:15:46.513591 SELPH_MODE 0: By rank 1: By Phase
7146 19:15:46.520205 ==============================================================
7147 19:15:46.523138 GAT_TRACK_EN = 1
7148 19:15:46.526747 RX_GATING_MODE = 2
7149 19:15:46.529619 RX_GATING_TRACK_MODE = 2
7150 19:15:46.533235 SELPH_MODE = 1
7151 19:15:46.536782 PICG_EARLY_EN = 1
7152 19:15:46.536891 VALID_LAT_VALUE = 1
7153 19:15:46.543101 ==============================================================
7154 19:15:46.546453 Enter into Gating configuration >>>>
7155 19:15:46.549852 Exit from Gating configuration <<<<
7156 19:15:46.552763 Enter into DVFS_PRE_config >>>>>
7157 19:15:46.563430 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7158 19:15:46.566281 Exit from DVFS_PRE_config <<<<<
7159 19:15:46.569980 Enter into PICG configuration >>>>
7160 19:15:46.572977 Exit from PICG configuration <<<<
7161 19:15:46.575944 [RX_INPUT] configuration >>>>>
7162 19:15:46.579426 [RX_INPUT] configuration <<<<<
7163 19:15:46.586005 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7164 19:15:46.589734 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7165 19:15:46.596230 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7166 19:15:46.602782 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7167 19:15:46.609590 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7168 19:15:46.616351 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7169 19:15:46.619385 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7170 19:15:46.622894 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7171 19:15:46.626250 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7172 19:15:46.632802 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7173 19:15:46.636324 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7174 19:15:46.639165 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7175 19:15:46.642608 ===================================
7176 19:15:46.646195 LPDDR4 DRAM CONFIGURATION
7177 19:15:46.649180 ===================================
7178 19:15:46.649274 EX_ROW_EN[0] = 0x0
7179 19:15:46.652498 EX_ROW_EN[1] = 0x0
7180 19:15:46.655798 LP4Y_EN = 0x0
7181 19:15:46.655911 WORK_FSP = 0x1
7182 19:15:46.659519 WL = 0x5
7183 19:15:46.659627 RL = 0x5
7184 19:15:46.662426 BL = 0x2
7185 19:15:46.662532 RPST = 0x0
7186 19:15:46.666029 RD_PRE = 0x0
7187 19:15:46.666140 WR_PRE = 0x1
7188 19:15:46.668803 WR_PST = 0x1
7189 19:15:46.668911 DBI_WR = 0x0
7190 19:15:46.672360 DBI_RD = 0x0
7191 19:15:46.672470 OTF = 0x1
7192 19:15:46.675274 ===================================
7193 19:15:46.678906 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7194 19:15:46.685211 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7195 19:15:46.688828 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7196 19:15:46.691722 ===================================
7197 19:15:46.695510 LPDDR4 DRAM CONFIGURATION
7198 19:15:46.698374 ===================================
7199 19:15:46.698486 EX_ROW_EN[0] = 0x10
7200 19:15:46.702046 EX_ROW_EN[1] = 0x0
7201 19:15:46.704929 LP4Y_EN = 0x0
7202 19:15:46.705013 WORK_FSP = 0x1
7203 19:15:46.708497 WL = 0x5
7204 19:15:46.708577 RL = 0x5
7205 19:15:46.712098 BL = 0x2
7206 19:15:46.712207 RPST = 0x0
7207 19:15:46.715047 RD_PRE = 0x0
7208 19:15:46.715157 WR_PRE = 0x1
7209 19:15:46.718609 WR_PST = 0x1
7210 19:15:46.718714 DBI_WR = 0x0
7211 19:15:46.722251 DBI_RD = 0x0
7212 19:15:46.722359 OTF = 0x1
7213 19:15:46.725139 ===================================
7214 19:15:46.731716 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7215 19:15:46.731834 ==
7216 19:15:46.734873 Dram Type= 6, Freq= 0, CH_0, rank 0
7217 19:15:46.738557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7218 19:15:46.738666 ==
7219 19:15:46.741979 [Duty_Offset_Calibration]
7220 19:15:46.744995 B0:2 B1:1 CA:1
7221 19:15:46.745083
7222 19:15:46.748359 [DutyScan_Calibration_Flow] k_type=0
7223 19:15:46.756738
7224 19:15:46.756883 ==CLK 0==
7225 19:15:46.760045 Final CLK duty delay cell = 0
7226 19:15:46.764015 [0] MAX Duty = 5156%(X100), DQS PI = 22
7227 19:15:46.767253 [0] MIN Duty = 4876%(X100), DQS PI = 48
7228 19:15:46.767367 [0] AVG Duty = 5016%(X100)
7229 19:15:46.770363
7230 19:15:46.773650 CH0 CLK Duty spec in!! Max-Min= 280%
7231 19:15:46.776936 [DutyScan_Calibration_Flow] ====Done====
7232 19:15:46.777024
7233 19:15:46.780269 [DutyScan_Calibration_Flow] k_type=1
7234 19:15:46.796239
7235 19:15:46.796390 ==DQS 0 ==
7236 19:15:46.799827 Final DQS duty delay cell = -4
7237 19:15:46.802742 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7238 19:15:46.806422 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7239 19:15:46.809509 [-4] AVG Duty = 4891%(X100)
7240 19:15:46.809623
7241 19:15:46.809718 ==DQS 1 ==
7242 19:15:46.813168 Final DQS duty delay cell = 0
7243 19:15:46.815907 [0] MAX Duty = 5187%(X100), DQS PI = 4
7244 19:15:46.819675 [0] MIN Duty = 5031%(X100), DQS PI = 32
7245 19:15:46.822501 [0] AVG Duty = 5109%(X100)
7246 19:15:46.822620
7247 19:15:46.826156 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7248 19:15:46.826275
7249 19:15:46.829155 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7250 19:15:46.832805 [DutyScan_Calibration_Flow] ====Done====
7251 19:15:46.832912
7252 19:15:46.836455 [DutyScan_Calibration_Flow] k_type=3
7253 19:15:46.853079
7254 19:15:46.853196 ==DQM 0 ==
7255 19:15:46.855890 Final DQM duty delay cell = 0
7256 19:15:46.859378 [0] MAX Duty = 5218%(X100), DQS PI = 34
7257 19:15:46.862874 [0] MIN Duty = 4875%(X100), DQS PI = 60
7258 19:15:46.866185 [0] AVG Duty = 5046%(X100)
7259 19:15:46.866302
7260 19:15:46.866402 ==DQM 1 ==
7261 19:15:46.869357 Final DQM duty delay cell = -4
7262 19:15:46.872407 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7263 19:15:46.875628 [-4] MIN Duty = 4813%(X100), DQS PI = 14
7264 19:15:46.879428 [-4] AVG Duty = 4891%(X100)
7265 19:15:46.879541
7266 19:15:46.882524 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7267 19:15:46.882631
7268 19:15:46.885650 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7269 19:15:46.889460 [DutyScan_Calibration_Flow] ====Done====
7270 19:15:46.889568
7271 19:15:46.892395 [DutyScan_Calibration_Flow] k_type=2
7272 19:15:46.910557
7273 19:15:46.910676 ==DQ 0 ==
7274 19:15:46.913487 Final DQ duty delay cell = 0
7275 19:15:46.917123 [0] MAX Duty = 5062%(X100), DQS PI = 24
7276 19:15:46.920658 [0] MIN Duty = 4907%(X100), DQS PI = 0
7277 19:15:46.920769 [0] AVG Duty = 4984%(X100)
7278 19:15:46.920864
7279 19:15:46.923600 ==DQ 1 ==
7280 19:15:46.927287 Final DQ duty delay cell = 0
7281 19:15:46.930365 [0] MAX Duty = 5093%(X100), DQS PI = 6
7282 19:15:46.933966 [0] MIN Duty = 4907%(X100), DQS PI = 34
7283 19:15:46.934077 [0] AVG Duty = 5000%(X100)
7284 19:15:46.934175
7285 19:15:46.936897 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7286 19:15:46.937002
7287 19:15:46.940533 CH0 DQ 1 Duty spec in!! Max-Min= 186%
7288 19:15:46.947055 [DutyScan_Calibration_Flow] ====Done====
7289 19:15:46.947173 ==
7290 19:15:46.950522 Dram Type= 6, Freq= 0, CH_1, rank 0
7291 19:15:46.953403 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7292 19:15:46.953514 ==
7293 19:15:46.956965 [Duty_Offset_Calibration]
7294 19:15:46.957065 B0:1 B1:0 CA:0
7295 19:15:46.957162
7296 19:15:46.959934 [DutyScan_Calibration_Flow] k_type=0
7297 19:15:46.969477
7298 19:15:46.969582 ==CLK 0==
7299 19:15:46.973009 Final CLK duty delay cell = -4
7300 19:15:46.976593 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7301 19:15:46.979482 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7302 19:15:46.982863 [-4] AVG Duty = 4922%(X100)
7303 19:15:46.982973
7304 19:15:46.986321 CH1 CLK Duty spec in!! Max-Min= 156%
7305 19:15:46.989494 [DutyScan_Calibration_Flow] ====Done====
7306 19:15:46.989596
7307 19:15:46.993142 [DutyScan_Calibration_Flow] k_type=1
7308 19:15:47.009903
7309 19:15:47.010015 ==DQS 0 ==
7310 19:15:47.013221 Final DQS duty delay cell = 0
7311 19:15:47.016371 [0] MAX Duty = 5062%(X100), DQS PI = 16
7312 19:15:47.019500 [0] MIN Duty = 4844%(X100), DQS PI = 0
7313 19:15:47.019605 [0] AVG Duty = 4953%(X100)
7314 19:15:47.022659
7315 19:15:47.022763 ==DQS 1 ==
7316 19:15:47.026284 Final DQS duty delay cell = 0
7317 19:15:47.029460 [0] MAX Duty = 5249%(X100), DQS PI = 16
7318 19:15:47.032886 [0] MIN Duty = 4938%(X100), DQS PI = 8
7319 19:15:47.032992 [0] AVG Duty = 5093%(X100)
7320 19:15:47.036346
7321 19:15:47.039332 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7322 19:15:47.039418
7323 19:15:47.042974 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7324 19:15:47.046634 [DutyScan_Calibration_Flow] ====Done====
7325 19:15:47.046744
7326 19:15:47.049601 [DutyScan_Calibration_Flow] k_type=3
7327 19:15:47.066775
7328 19:15:47.066891 ==DQM 0 ==
7329 19:15:47.069680 Final DQM duty delay cell = 0
7330 19:15:47.073266 [0] MAX Duty = 5218%(X100), DQS PI = 20
7331 19:15:47.076884 [0] MIN Duty = 4969%(X100), DQS PI = 48
7332 19:15:47.079840 [0] AVG Duty = 5093%(X100)
7333 19:15:47.079921
7334 19:15:47.079986 ==DQM 1 ==
7335 19:15:47.083419 Final DQM duty delay cell = 0
7336 19:15:47.086287 [0] MAX Duty = 5093%(X100), DQS PI = 16
7337 19:15:47.089952 [0] MIN Duty = 4876%(X100), DQS PI = 52
7338 19:15:47.090034 [0] AVG Duty = 4984%(X100)
7339 19:15:47.093429
7340 19:15:47.096329 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7341 19:15:47.096419
7342 19:15:47.099785 CH1 DQM 1 Duty spec in!! Max-Min= 217%
7343 19:15:47.103210 [DutyScan_Calibration_Flow] ====Done====
7344 19:15:47.103320
7345 19:15:47.106653 [DutyScan_Calibration_Flow] k_type=2
7346 19:15:47.122742
7347 19:15:47.122865 ==DQ 0 ==
7348 19:15:47.125696 Final DQ duty delay cell = -4
7349 19:15:47.129236 [-4] MAX Duty = 5062%(X100), DQS PI = 10
7350 19:15:47.132625 [-4] MIN Duty = 4875%(X100), DQS PI = 40
7351 19:15:47.135964 [-4] AVG Duty = 4968%(X100)
7352 19:15:47.136092
7353 19:15:47.136169 ==DQ 1 ==
7354 19:15:47.139260 Final DQ duty delay cell = 0
7355 19:15:47.142450 [0] MAX Duty = 5156%(X100), DQS PI = 18
7356 19:15:47.146253 [0] MIN Duty = 4938%(X100), DQS PI = 8
7357 19:15:47.146401 [0] AVG Duty = 5047%(X100)
7358 19:15:47.149648
7359 19:15:47.152867 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7360 19:15:47.152968
7361 19:15:47.156193 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7362 19:15:47.159548 [DutyScan_Calibration_Flow] ====Done====
7363 19:15:47.162366 nWR fixed to 30
7364 19:15:47.162451 [ModeRegInit_LP4] CH0 RK0
7365 19:15:47.165946 [ModeRegInit_LP4] CH0 RK1
7366 19:15:47.169524 [ModeRegInit_LP4] CH1 RK0
7367 19:15:47.172545 [ModeRegInit_LP4] CH1 RK1
7368 19:15:47.172627 match AC timing 5
7369 19:15:47.178991 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7370 19:15:47.182551 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7371 19:15:47.185588 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7372 19:15:47.191975 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7373 19:15:47.195580 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7374 19:15:47.195663 [MiockJmeterHQA]
7375 19:15:47.195729
7376 19:15:47.199268 [DramcMiockJmeter] u1RxGatingPI = 0
7377 19:15:47.201991 0 : 4252, 4027
7378 19:15:47.202075 4 : 4258, 4030
7379 19:15:47.205399 8 : 4253, 4026
7380 19:15:47.205482 12 : 4253, 4027
7381 19:15:47.208869 16 : 4254, 4029
7382 19:15:47.208953 20 : 4253, 4027
7383 19:15:47.209019 24 : 4363, 4138
7384 19:15:47.211579 28 : 4363, 4138
7385 19:15:47.211662 32 : 4252, 4026
7386 19:15:47.215174 36 : 4252, 4027
7387 19:15:47.215257 40 : 4252, 4027
7388 19:15:47.218826 44 : 4363, 4137
7389 19:15:47.218910 48 : 4253, 4027
7390 19:15:47.221801 52 : 4363, 4138
7391 19:15:47.221885 56 : 4253, 4027
7392 19:15:47.221952 60 : 4252, 4027
7393 19:15:47.225393 64 : 4250, 4027
7394 19:15:47.225477 68 : 4253, 4029
7395 19:15:47.228265 72 : 4361, 4137
7396 19:15:47.228359 76 : 4250, 4027
7397 19:15:47.231981 80 : 4361, 4137
7398 19:15:47.232064 84 : 4250, 4025
7399 19:15:47.232131 88 : 4250, 126
7400 19:15:47.234931 92 : 4363, 0
7401 19:15:47.235014 96 : 4252, 0
7402 19:15:47.238608 100 : 4252, 0
7403 19:15:47.238691 104 : 4250, 0
7404 19:15:47.238757 108 : 4250, 0
7405 19:15:47.241597 112 : 4250, 0
7406 19:15:47.241680 116 : 4253, 0
7407 19:15:47.245133 120 : 4250, 0
7408 19:15:47.245217 124 : 4250, 0
7409 19:15:47.245284 128 : 4252, 0
7410 19:15:47.248547 132 : 4361, 0
7411 19:15:47.248629 136 : 4250, 0
7412 19:15:47.251454 140 : 4250, 0
7413 19:15:47.251537 144 : 4250, 0
7414 19:15:47.251603 148 : 4361, 0
7415 19:15:47.254886 152 : 4361, 0
7416 19:15:47.254969 156 : 4250, 0
7417 19:15:47.255035 160 : 4250, 0
7418 19:15:47.258237 164 : 4249, 0
7419 19:15:47.258321 168 : 4253, 0
7420 19:15:47.261591 172 : 4250, 0
7421 19:15:47.261674 176 : 4249, 0
7422 19:15:47.261740 180 : 4253, 0
7423 19:15:47.264927 184 : 4361, 0
7424 19:15:47.265011 188 : 4249, 0
7425 19:15:47.268473 192 : 4250, 0
7426 19:15:47.268567 196 : 4250, 0
7427 19:15:47.268634 200 : 4250, 0
7428 19:15:47.271781 204 : 4363, 1241
7429 19:15:47.271867 208 : 4249, 3933
7430 19:15:47.274677 212 : 4250, 4027
7431 19:15:47.274760 216 : 4250, 4027
7432 19:15:47.278505 220 : 4250, 4027
7433 19:15:47.278602 224 : 4250, 4027
7434 19:15:47.281909 228 : 4250, 4027
7435 19:15:47.281994 232 : 4250, 4027
7436 19:15:47.284784 236 : 4252, 4030
7437 19:15:47.284872 240 : 4250, 4027
7438 19:15:47.284938 244 : 4361, 4137
7439 19:15:47.288399 248 : 4361, 4137
7440 19:15:47.288486 252 : 4250, 4027
7441 19:15:47.291448 256 : 4363, 4140
7442 19:15:47.291569 260 : 4361, 4138
7443 19:15:47.295067 264 : 4250, 4026
7444 19:15:47.295185 268 : 4250, 4027
7445 19:15:47.298053 272 : 4252, 4029
7446 19:15:47.298155 276 : 4249, 4027
7447 19:15:47.301479 280 : 4250, 4026
7448 19:15:47.301563 284 : 4250, 4027
7449 19:15:47.304924 288 : 4252, 4029
7450 19:15:47.305018 292 : 4250, 4027
7451 19:15:47.305119 296 : 4361, 4137
7452 19:15:47.308499 300 : 4361, 4137
7453 19:15:47.308577 304 : 4250, 4027
7454 19:15:47.311873 308 : 4363, 4082
7455 19:15:47.311966 312 : 4361, 2100
7456 19:15:47.312040
7457 19:15:47.315300 MIOCK jitter meter ch=0
7458 19:15:47.315375
7459 19:15:47.318084 1T = (312-88) = 224 dly cells
7460 19:15:47.325402 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7461 19:15:47.325488 ==
7462 19:15:47.328306 Dram Type= 6, Freq= 0, CH_0, rank 0
7463 19:15:47.331897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7464 19:15:47.331977 ==
7465 19:15:47.338307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7466 19:15:47.341251 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7467 19:15:47.344973 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7468 19:15:47.351447 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7469 19:15:47.360201 [CA 0] Center 42 (12~73) winsize 62
7470 19:15:47.363732 [CA 1] Center 42 (12~73) winsize 62
7471 19:15:47.367203 [CA 2] Center 38 (8~68) winsize 61
7472 19:15:47.370072 [CA 3] Center 37 (8~67) winsize 60
7473 19:15:47.373577 [CA 4] Center 36 (6~66) winsize 61
7474 19:15:47.377244 [CA 5] Center 35 (6~64) winsize 59
7475 19:15:47.377320
7476 19:15:47.380049 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7477 19:15:47.380119
7478 19:15:47.384071 [CATrainingPosCal] consider 1 rank data
7479 19:15:47.387234 u2DelayCellTimex100 = 290/100 ps
7480 19:15:47.389968 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7481 19:15:47.397279 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7482 19:15:47.399997 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7483 19:15:47.403432 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7484 19:15:47.406994 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7485 19:15:47.409855 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7486 19:15:47.409932
7487 19:15:47.413502 CA PerBit enable=1, Macro0, CA PI delay=35
7488 19:15:47.413577
7489 19:15:47.417006 [CBTSetCACLKResult] CA Dly = 35
7490 19:15:47.419866 CS Dly: 9 (0~40)
7491 19:15:47.423303 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7492 19:15:47.426798 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7493 19:15:47.426884 ==
7494 19:15:47.429857 Dram Type= 6, Freq= 0, CH_0, rank 1
7495 19:15:47.433432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7496 19:15:47.436209 ==
7497 19:15:47.439835 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7498 19:15:47.442802 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7499 19:15:47.450182 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7500 19:15:47.456580 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7501 19:15:47.463740 [CA 0] Center 42 (12~73) winsize 62
7502 19:15:47.466518 [CA 1] Center 42 (12~73) winsize 62
7503 19:15:47.470206 [CA 2] Center 38 (8~68) winsize 61
7504 19:15:47.473765 [CA 3] Center 37 (8~67) winsize 60
7505 19:15:47.476569 [CA 4] Center 36 (6~66) winsize 61
7506 19:15:47.480077 [CA 5] Center 34 (5~64) winsize 60
7507 19:15:47.480163
7508 19:15:47.483734 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7509 19:15:47.483819
7510 19:15:47.486707 [CATrainingPosCal] consider 2 rank data
7511 19:15:47.490330 u2DelayCellTimex100 = 290/100 ps
7512 19:15:47.493982 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7513 19:15:47.500393 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7514 19:15:47.503328 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7515 19:15:47.506793 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7516 19:15:47.510073 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7517 19:15:47.513340 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7518 19:15:47.513423
7519 19:15:47.516675 CA PerBit enable=1, Macro0, CA PI delay=35
7520 19:15:47.516761
7521 19:15:47.520109 [CBTSetCACLKResult] CA Dly = 35
7522 19:15:47.523277 CS Dly: 10 (0~42)
7523 19:15:47.526948 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7524 19:15:47.530159 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7525 19:15:47.530260
7526 19:15:47.533422 ----->DramcWriteLeveling(PI) begin...
7527 19:15:47.533522 ==
7528 19:15:47.536510 Dram Type= 6, Freq= 0, CH_0, rank 0
7529 19:15:47.539860 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7530 19:15:47.543792 ==
7531 19:15:47.543896 Write leveling (Byte 0): 35 => 35
7532 19:15:47.546851 Write leveling (Byte 1): 26 => 26
7533 19:15:47.549825 DramcWriteLeveling(PI) end<-----
7534 19:15:47.549932
7535 19:15:47.550023 ==
7536 19:15:47.553325 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 19:15:47.559836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 19:15:47.559954 ==
7539 19:15:47.560049 [Gating] SW mode calibration
7540 19:15:47.569728 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7541 19:15:47.573336 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7542 19:15:47.580170 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7543 19:15:47.583045 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7544 19:15:47.586669 1 4 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
7545 19:15:47.590221 1 4 12 | B1->B0 | 2323 3938 | 0 1 | (0 0) (0 0)
7546 19:15:47.596787 1 4 16 | B1->B0 | 2323 3636 | 0 0 | (0 0) (1 1)
7547 19:15:47.599720 1 4 20 | B1->B0 | 3434 3737 | 0 0 | (0 0) (0 0)
7548 19:15:47.603251 1 4 24 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
7549 19:15:47.609862 1 4 28 | B1->B0 | 3434 3b3b | 1 1 | (1 1) (0 0)
7550 19:15:47.613553 1 5 0 | B1->B0 | 3434 3c3c | 1 0 | (1 1) (0 0)
7551 19:15:47.616347 1 5 4 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
7552 19:15:47.622933 1 5 8 | B1->B0 | 3434 3636 | 1 1 | (1 1) (0 1)
7553 19:15:47.626217 1 5 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (0 1)
7554 19:15:47.629631 1 5 16 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
7555 19:15:47.636059 1 5 20 | B1->B0 | 2828 2d2c | 0 1 | (1 0) (0 0)
7556 19:15:47.639599 1 5 24 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7557 19:15:47.642918 1 5 28 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
7558 19:15:47.649371 1 6 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7559 19:15:47.652959 1 6 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
7560 19:15:47.656014 1 6 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
7561 19:15:47.663239 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7562 19:15:47.665983 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7563 19:15:47.669683 1 6 20 | B1->B0 | 4545 4645 | 0 1 | (0 0) (0 0)
7564 19:15:47.676214 1 6 24 | B1->B0 | 4646 4646 | 0 1 | (0 0) (0 0)
7565 19:15:47.679712 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 19:15:47.683274 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 19:15:47.689856 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 19:15:47.693427 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7569 19:15:47.696229 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7570 19:15:47.702839 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7571 19:15:47.706424 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7572 19:15:47.709363 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 19:15:47.716065 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 19:15:47.719763 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 19:15:47.722574 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 19:15:47.729236 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 19:15:47.732797 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 19:15:47.736299 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 19:15:47.742541 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 19:15:47.746207 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 19:15:47.749031 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 19:15:47.752790 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 19:15:47.759034 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 19:15:47.762455 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7585 19:15:47.765941 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7586 19:15:47.772434 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7587 19:15:47.776058 Total UI for P1: 0, mck2ui 16
7588 19:15:47.778995 best dqsien dly found for B0: ( 1, 9, 10)
7589 19:15:47.782532 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7590 19:15:47.785635 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 19:15:47.788905 Total UI for P1: 0, mck2ui 16
7592 19:15:47.792403 best dqsien dly found for B1: ( 1, 9, 18)
7593 19:15:47.795995 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7594 19:15:47.798783 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7595 19:15:47.802368
7596 19:15:47.805344 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7597 19:15:47.808866 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7598 19:15:47.812504 [Gating] SW calibration Done
7599 19:15:47.812584 ==
7600 19:15:47.815492 Dram Type= 6, Freq= 0, CH_0, rank 0
7601 19:15:47.819164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7602 19:15:47.819249 ==
7603 19:15:47.819321 RX Vref Scan: 0
7604 19:15:47.822160
7605 19:15:47.822286 RX Vref 0 -> 0, step: 1
7606 19:15:47.822382
7607 19:15:47.825606 RX Delay 0 -> 252, step: 8
7608 19:15:47.829088 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7609 19:15:47.832204 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7610 19:15:47.838828 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7611 19:15:47.842282 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7612 19:15:47.845805 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7613 19:15:47.849046 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7614 19:15:47.852030 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7615 19:15:47.855639 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7616 19:15:47.862224 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7617 19:15:47.865757 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7618 19:15:47.868634 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7619 19:15:47.872301 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7620 19:15:47.878815 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7621 19:15:47.882279 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7622 19:15:47.885831 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7623 19:15:47.888578 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7624 19:15:47.888660 ==
7625 19:15:47.892022 Dram Type= 6, Freq= 0, CH_0, rank 0
7626 19:15:47.895371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7627 19:15:47.899120 ==
7628 19:15:47.899196 DQS Delay:
7629 19:15:47.899264 DQS0 = 0, DQS1 = 0
7630 19:15:47.901892 DQM Delay:
7631 19:15:47.901966 DQM0 = 137, DQM1 = 130
7632 19:15:47.905328 DQ Delay:
7633 19:15:47.908766 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7634 19:15:47.912369 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7635 19:15:47.915529 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7636 19:15:47.918805 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7637 19:15:47.918888
7638 19:15:47.918958
7639 19:15:47.919019 ==
7640 19:15:47.921992 Dram Type= 6, Freq= 0, CH_0, rank 0
7641 19:15:47.925411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7642 19:15:47.925493 ==
7643 19:15:47.925559
7644 19:15:47.929126
7645 19:15:47.929207 TX Vref Scan disable
7646 19:15:47.931889 == TX Byte 0 ==
7647 19:15:47.935402 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7648 19:15:47.939062 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7649 19:15:47.941910 == TX Byte 1 ==
7650 19:15:47.945582 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7651 19:15:47.948598 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7652 19:15:47.948706 ==
7653 19:15:47.952121 Dram Type= 6, Freq= 0, CH_0, rank 0
7654 19:15:47.958289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7655 19:15:47.958387 ==
7656 19:15:47.969838
7657 19:15:47.973528 TX Vref early break, caculate TX vref
7658 19:15:47.976610 TX Vref=16, minBit 4, minWin=23, winSum=382
7659 19:15:47.980328 TX Vref=18, minBit 1, minWin=23, winSum=387
7660 19:15:47.983264 TX Vref=20, minBit 0, minWin=24, winSum=398
7661 19:15:47.986832 TX Vref=22, minBit 1, minWin=24, winSum=408
7662 19:15:47.989769 TX Vref=24, minBit 4, minWin=25, winSum=419
7663 19:15:47.996316 TX Vref=26, minBit 6, minWin=25, winSum=426
7664 19:15:48.000167 TX Vref=28, minBit 2, minWin=25, winSum=423
7665 19:15:48.002979 TX Vref=30, minBit 6, minWin=24, winSum=415
7666 19:15:48.006740 TX Vref=32, minBit 1, minWin=24, winSum=402
7667 19:15:48.013219 [TxChooseVref] Worse bit 6, Min win 25, Win sum 426, Final Vref 26
7668 19:15:48.013301
7669 19:15:48.016769 Final TX Range 0 Vref 26
7670 19:15:48.016863
7671 19:15:48.016934 ==
7672 19:15:48.019286 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 19:15:48.023104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 19:15:48.023225 ==
7675 19:15:48.023292
7676 19:15:48.023383
7677 19:15:48.026191 TX Vref Scan disable
7678 19:15:48.032747 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7679 19:15:48.032848 == TX Byte 0 ==
7680 19:15:48.035753 u2DelayCellOfst[0]=10 cells (3 PI)
7681 19:15:48.039225 u2DelayCellOfst[1]=13 cells (4 PI)
7682 19:15:48.042846 u2DelayCellOfst[2]=10 cells (3 PI)
7683 19:15:48.045779 u2DelayCellOfst[3]=6 cells (2 PI)
7684 19:15:48.049003 u2DelayCellOfst[4]=6 cells (2 PI)
7685 19:15:48.052835 u2DelayCellOfst[5]=0 cells (0 PI)
7686 19:15:48.052919 u2DelayCellOfst[6]=16 cells (5 PI)
7687 19:15:48.055964 u2DelayCellOfst[7]=16 cells (5 PI)
7688 19:15:48.062192 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7689 19:15:48.065655 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7690 19:15:48.065762 == TX Byte 1 ==
7691 19:15:48.069065 u2DelayCellOfst[8]=3 cells (1 PI)
7692 19:15:48.072465 u2DelayCellOfst[9]=0 cells (0 PI)
7693 19:15:48.076115 u2DelayCellOfst[10]=10 cells (3 PI)
7694 19:15:48.079006 u2DelayCellOfst[11]=3 cells (1 PI)
7695 19:15:48.082644 u2DelayCellOfst[12]=10 cells (3 PI)
7696 19:15:48.085545 u2DelayCellOfst[13]=10 cells (3 PI)
7697 19:15:48.089276 u2DelayCellOfst[14]=13 cells (4 PI)
7698 19:15:48.091988 u2DelayCellOfst[15]=10 cells (3 PI)
7699 19:15:48.095576 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7700 19:15:48.102172 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7701 19:15:48.102277 DramC Write-DBI on
7702 19:15:48.102380 ==
7703 19:15:48.105912 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 19:15:48.108777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 19:15:48.112356 ==
7706 19:15:48.112455
7707 19:15:48.112556
7708 19:15:48.112644 TX Vref Scan disable
7709 19:15:48.115386 == TX Byte 0 ==
7710 19:15:48.119045 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7711 19:15:48.122619 == TX Byte 1 ==
7712 19:15:48.125705 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7713 19:15:48.125806 DramC Write-DBI off
7714 19:15:48.129243
7715 19:15:48.129356 [DATLAT]
7716 19:15:48.129446 Freq=1600, CH0 RK0
7717 19:15:48.129546
7718 19:15:48.131978 DATLAT Default: 0xf
7719 19:15:48.132083 0, 0xFFFF, sum = 0
7720 19:15:48.135536 1, 0xFFFF, sum = 0
7721 19:15:48.135676 2, 0xFFFF, sum = 0
7722 19:15:48.138928 3, 0xFFFF, sum = 0
7723 19:15:48.142519 4, 0xFFFF, sum = 0
7724 19:15:48.142627 5, 0xFFFF, sum = 0
7725 19:15:48.145426 6, 0xFFFF, sum = 0
7726 19:15:48.145510 7, 0xFFFF, sum = 0
7727 19:15:48.148791 8, 0xFFFF, sum = 0
7728 19:15:48.148876 9, 0xFFFF, sum = 0
7729 19:15:48.152263 10, 0xFFFF, sum = 0
7730 19:15:48.152387 11, 0xFFFF, sum = 0
7731 19:15:48.155619 12, 0xFFFF, sum = 0
7732 19:15:48.155716 13, 0xFFFF, sum = 0
7733 19:15:48.159029 14, 0x0, sum = 1
7734 19:15:48.159153 15, 0x0, sum = 2
7735 19:15:48.162261 16, 0x0, sum = 3
7736 19:15:48.162345 17, 0x0, sum = 4
7737 19:15:48.165354 best_step = 15
7738 19:15:48.165441
7739 19:15:48.165507 ==
7740 19:15:48.169008 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 19:15:48.171942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 19:15:48.172052 ==
7743 19:15:48.172151 RX Vref Scan: 1
7744 19:15:48.175704
7745 19:15:48.175787 Set Vref Range= 24 -> 127
7746 19:15:48.175854
7747 19:15:48.178792 RX Vref 24 -> 127, step: 1
7748 19:15:48.178875
7749 19:15:48.181880 RX Delay 27 -> 252, step: 4
7750 19:15:48.181964
7751 19:15:48.185609 Set Vref, RX VrefLevel [Byte0]: 24
7752 19:15:48.188546 [Byte1]: 24
7753 19:15:48.188632
7754 19:15:48.192119 Set Vref, RX VrefLevel [Byte0]: 25
7755 19:15:48.195391 [Byte1]: 25
7756 19:15:48.195476
7757 19:15:48.198955 Set Vref, RX VrefLevel [Byte0]: 26
7758 19:15:48.201821 [Byte1]: 26
7759 19:15:48.205467
7760 19:15:48.205552 Set Vref, RX VrefLevel [Byte0]: 27
7761 19:15:48.209078 [Byte1]: 27
7762 19:15:48.213407
7763 19:15:48.213491 Set Vref, RX VrefLevel [Byte0]: 28
7764 19:15:48.216349 [Byte1]: 28
7765 19:15:48.220920
7766 19:15:48.220998 Set Vref, RX VrefLevel [Byte0]: 29
7767 19:15:48.223813 [Byte1]: 29
7768 19:15:48.228150
7769 19:15:48.228240 Set Vref, RX VrefLevel [Byte0]: 30
7770 19:15:48.231862 [Byte1]: 30
7771 19:15:48.235585
7772 19:15:48.235696 Set Vref, RX VrefLevel [Byte0]: 31
7773 19:15:48.239070 [Byte1]: 31
7774 19:15:48.243446
7775 19:15:48.243532 Set Vref, RX VrefLevel [Byte0]: 32
7776 19:15:48.246432 [Byte1]: 32
7777 19:15:48.250609
7778 19:15:48.250718 Set Vref, RX VrefLevel [Byte0]: 33
7779 19:15:48.254361 [Byte1]: 33
7780 19:15:48.258800
7781 19:15:48.258879 Set Vref, RX VrefLevel [Byte0]: 34
7782 19:15:48.261628 [Byte1]: 34
7783 19:15:48.266106
7784 19:15:48.266187 Set Vref, RX VrefLevel [Byte0]: 35
7785 19:15:48.269084 [Byte1]: 35
7786 19:15:48.273326
7787 19:15:48.273403 Set Vref, RX VrefLevel [Byte0]: 36
7788 19:15:48.276772 [Byte1]: 36
7789 19:15:48.280772
7790 19:15:48.280856 Set Vref, RX VrefLevel [Byte0]: 37
7791 19:15:48.284054 [Byte1]: 37
7792 19:15:48.288264
7793 19:15:48.288380 Set Vref, RX VrefLevel [Byte0]: 38
7794 19:15:48.291969 [Byte1]: 38
7795 19:15:48.296079
7796 19:15:48.296165 Set Vref, RX VrefLevel [Byte0]: 39
7797 19:15:48.299408 [Byte1]: 39
7798 19:15:48.303797
7799 19:15:48.303881 Set Vref, RX VrefLevel [Byte0]: 40
7800 19:15:48.306713 [Byte1]: 40
7801 19:15:48.311316
7802 19:15:48.311394 Set Vref, RX VrefLevel [Byte0]: 41
7803 19:15:48.314277 [Byte1]: 41
7804 19:15:48.318704
7805 19:15:48.318786 Set Vref, RX VrefLevel [Byte0]: 42
7806 19:15:48.321933 [Byte1]: 42
7807 19:15:48.326252
7808 19:15:48.326337 Set Vref, RX VrefLevel [Byte0]: 43
7809 19:15:48.329221 [Byte1]: 43
7810 19:15:48.333574
7811 19:15:48.333684 Set Vref, RX VrefLevel [Byte0]: 44
7812 19:15:48.337187 [Byte1]: 44
7813 19:15:48.341496
7814 19:15:48.341576 Set Vref, RX VrefLevel [Byte0]: 45
7815 19:15:48.344525 [Byte1]: 45
7816 19:15:48.348660
7817 19:15:48.348773 Set Vref, RX VrefLevel [Byte0]: 46
7818 19:15:48.352408 [Byte1]: 46
7819 19:15:48.356719
7820 19:15:48.356822 Set Vref, RX VrefLevel [Byte0]: 47
7821 19:15:48.359599 [Byte1]: 47
7822 19:15:48.363861
7823 19:15:48.363965 Set Vref, RX VrefLevel [Byte0]: 48
7824 19:15:48.367445 [Byte1]: 48
7825 19:15:48.371243
7826 19:15:48.371320 Set Vref, RX VrefLevel [Byte0]: 49
7827 19:15:48.374773 [Byte1]: 49
7828 19:15:48.379250
7829 19:15:48.379363 Set Vref, RX VrefLevel [Byte0]: 50
7830 19:15:48.382153 [Byte1]: 50
7831 19:15:48.386442
7832 19:15:48.386518 Set Vref, RX VrefLevel [Byte0]: 51
7833 19:15:48.389855 [Byte1]: 51
7834 19:15:48.393709
7835 19:15:48.393791 Set Vref, RX VrefLevel [Byte0]: 52
7836 19:15:48.397515 [Byte1]: 52
7837 19:15:48.401758
7838 19:15:48.401840 Set Vref, RX VrefLevel [Byte0]: 53
7839 19:15:48.404749 [Byte1]: 53
7840 19:15:48.409110
7841 19:15:48.409194 Set Vref, RX VrefLevel [Byte0]: 54
7842 19:15:48.412706 [Byte1]: 54
7843 19:15:48.416793
7844 19:15:48.416879 Set Vref, RX VrefLevel [Byte0]: 55
7845 19:15:48.420242 [Byte1]: 55
7846 19:15:48.424148
7847 19:15:48.424236 Set Vref, RX VrefLevel [Byte0]: 56
7848 19:15:48.427504 [Byte1]: 56
7849 19:15:48.431459
7850 19:15:48.431537 Set Vref, RX VrefLevel [Byte0]: 57
7851 19:15:48.434886 [Byte1]: 57
7852 19:15:48.439403
7853 19:15:48.439483 Set Vref, RX VrefLevel [Byte0]: 58
7854 19:15:48.442811 [Byte1]: 58
7855 19:15:48.446367
7856 19:15:48.446478 Set Vref, RX VrefLevel [Byte0]: 59
7857 19:15:48.449897 [Byte1]: 59
7858 19:15:48.454043
7859 19:15:48.454129 Set Vref, RX VrefLevel [Byte0]: 60
7860 19:15:48.457665 [Byte1]: 60
7861 19:15:48.461908
7862 19:15:48.461989 Set Vref, RX VrefLevel [Byte0]: 61
7863 19:15:48.464793 [Byte1]: 61
7864 19:15:48.469142
7865 19:15:48.469230 Set Vref, RX VrefLevel [Byte0]: 62
7866 19:15:48.472769 [Byte1]: 62
7867 19:15:48.477073
7868 19:15:48.477183 Set Vref, RX VrefLevel [Byte0]: 63
7869 19:15:48.480094 [Byte1]: 63
7870 19:15:48.484521
7871 19:15:48.484622 Set Vref, RX VrefLevel [Byte0]: 64
7872 19:15:48.487443 [Byte1]: 64
7873 19:15:48.491834
7874 19:15:48.491936 Set Vref, RX VrefLevel [Byte0]: 65
7875 19:15:48.495420 [Byte1]: 65
7876 19:15:48.499623
7877 19:15:48.499729 Set Vref, RX VrefLevel [Byte0]: 66
7878 19:15:48.502999 [Byte1]: 66
7879 19:15:48.506776
7880 19:15:48.506875 Set Vref, RX VrefLevel [Byte0]: 67
7881 19:15:48.510080 [Byte1]: 67
7882 19:15:48.514391
7883 19:15:48.514498 Set Vref, RX VrefLevel [Byte0]: 68
7884 19:15:48.518117 [Byte1]: 68
7885 19:15:48.521842
7886 19:15:48.521918 Set Vref, RX VrefLevel [Byte0]: 69
7887 19:15:48.525522 [Byte1]: 69
7888 19:15:48.529776
7889 19:15:48.529855 Set Vref, RX VrefLevel [Byte0]: 70
7890 19:15:48.533217 [Byte1]: 70
7891 19:15:48.536785
7892 19:15:48.536872 Set Vref, RX VrefLevel [Byte0]: 71
7893 19:15:48.540472 [Byte1]: 71
7894 19:15:48.544533
7895 19:15:48.544613 Set Vref, RX VrefLevel [Byte0]: 72
7896 19:15:48.547892 [Byte1]: 72
7897 19:15:48.552353
7898 19:15:48.552440 Final RX Vref Byte 0 = 57 to rank0
7899 19:15:48.555489 Final RX Vref Byte 1 = 60 to rank0
7900 19:15:48.558874 Final RX Vref Byte 0 = 57 to rank1
7901 19:15:48.562011 Final RX Vref Byte 1 = 60 to rank1==
7902 19:15:48.565406 Dram Type= 6, Freq= 0, CH_0, rank 0
7903 19:15:48.572368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7904 19:15:48.572492 ==
7905 19:15:48.572583 DQS Delay:
7906 19:15:48.572660 DQS0 = 0, DQS1 = 0
7907 19:15:48.575249 DQM Delay:
7908 19:15:48.575331 DQM0 = 134, DQM1 = 127
7909 19:15:48.578806 DQ Delay:
7910 19:15:48.581885 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7911 19:15:48.585540 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7912 19:15:48.588578 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7913 19:15:48.592159 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7914 19:15:48.592259
7915 19:15:48.592375
7916 19:15:48.592459
7917 19:15:48.595092 [DramC_TX_OE_Calibration] TA2
7918 19:15:48.598820 Original DQ_B0 (3 6) =30, OEN = 27
7919 19:15:48.601563 Original DQ_B1 (3 6) =30, OEN = 27
7920 19:15:48.605309 24, 0x0, End_B0=24 End_B1=24
7921 19:15:48.605403 25, 0x0, End_B0=25 End_B1=25
7922 19:15:48.608318 26, 0x0, End_B0=26 End_B1=26
7923 19:15:48.611882 27, 0x0, End_B0=27 End_B1=27
7924 19:15:48.615228 28, 0x0, End_B0=28 End_B1=28
7925 19:15:48.618419 29, 0x0, End_B0=29 End_B1=29
7926 19:15:48.618503 30, 0x0, End_B0=30 End_B1=30
7927 19:15:48.621834 31, 0x5151, End_B0=30 End_B1=30
7928 19:15:48.624820 Byte0 end_step=30 best_step=27
7929 19:15:48.628349 Byte1 end_step=30 best_step=27
7930 19:15:48.631301 Byte0 TX OE(2T, 0.5T) = (3, 3)
7931 19:15:48.634973 Byte1 TX OE(2T, 0.5T) = (3, 3)
7932 19:15:48.635058
7933 19:15:48.635123
7934 19:15:48.641377 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7935 19:15:48.644997 CH0 RK0: MR19=303, MR18=2622
7936 19:15:48.651617 CH0_RK0: MR19=0x303, MR18=0x2622, DQSOSC=390, MR23=63, INC=24, DEC=16
7937 19:15:48.651706
7938 19:15:48.654549 ----->DramcWriteLeveling(PI) begin...
7939 19:15:48.654635 ==
7940 19:15:48.657995 Dram Type= 6, Freq= 0, CH_0, rank 1
7941 19:15:48.661568 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7942 19:15:48.661677 ==
7943 19:15:48.665122 Write leveling (Byte 0): 35 => 35
7944 19:15:48.667958 Write leveling (Byte 1): 27 => 27
7945 19:15:48.671468 DramcWriteLeveling(PI) end<-----
7946 19:15:48.671571
7947 19:15:48.671672 ==
7948 19:15:48.674808 Dram Type= 6, Freq= 0, CH_0, rank 1
7949 19:15:48.678056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7950 19:15:48.678164 ==
7951 19:15:48.681470 [Gating] SW mode calibration
7952 19:15:48.687872 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7953 19:15:48.694568 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7954 19:15:48.697786 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7955 19:15:48.704910 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7956 19:15:48.707894 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7957 19:15:48.711533 1 4 12 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7958 19:15:48.714401 1 4 16 | B1->B0 | 2e2e 3534 | 1 1 | (1 1) (1 1)
7959 19:15:48.721623 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7960 19:15:48.724407 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7961 19:15:48.727797 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7962 19:15:48.734875 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7963 19:15:48.737809 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 1)
7964 19:15:48.741470 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
7965 19:15:48.748312 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
7966 19:15:48.751451 1 5 16 | B1->B0 | 2d2d 2828 | 0 0 | (1 0) (0 1)
7967 19:15:48.755180 1 5 20 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (1 1)
7968 19:15:48.761014 1 5 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7969 19:15:48.764502 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7970 19:15:48.768108 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7971 19:15:48.774675 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7972 19:15:48.777607 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7973 19:15:48.781145 1 6 12 | B1->B0 | 2929 3838 | 0 1 | (1 1) (0 0)
7974 19:15:48.787873 1 6 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7975 19:15:48.791408 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7976 19:15:48.794289 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7977 19:15:48.800922 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7978 19:15:48.804319 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7979 19:15:48.807694 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7980 19:15:48.814631 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7981 19:15:48.817880 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7982 19:15:48.821042 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7983 19:15:48.824661 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7984 19:15:48.831258 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7985 19:15:48.834711 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 19:15:48.837919 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 19:15:48.844699 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 19:15:48.848250 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 19:15:48.850857 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 19:15:48.858066 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 19:15:48.860953 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 19:15:48.864580 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 19:15:48.870686 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 19:15:48.874550 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 19:15:48.877423 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 19:15:48.883977 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7997 19:15:48.887655 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7998 19:15:48.891090 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7999 19:15:48.897639 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8000 19:15:48.897756 Total UI for P1: 0, mck2ui 16
8001 19:15:48.904145 best dqsien dly found for B0: ( 1, 9, 12)
8002 19:15:48.904254 Total UI for P1: 0, mck2ui 16
8003 19:15:48.910720 best dqsien dly found for B1: ( 1, 9, 12)
8004 19:15:48.914323 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8005 19:15:48.917246 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8006 19:15:48.917334
8007 19:15:48.920853 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8008 19:15:48.924382 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8009 19:15:48.927298 [Gating] SW calibration Done
8010 19:15:48.927378 ==
8011 19:15:48.930740 Dram Type= 6, Freq= 0, CH_0, rank 1
8012 19:15:48.934093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8013 19:15:48.934195 ==
8014 19:15:48.937442 RX Vref Scan: 0
8015 19:15:48.937520
8016 19:15:48.937603 RX Vref 0 -> 0, step: 1
8017 19:15:48.937712
8018 19:15:48.940726 RX Delay 0 -> 252, step: 8
8019 19:15:48.943927 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8020 19:15:48.950689 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8021 19:15:48.953970 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8022 19:15:48.957288 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8023 19:15:48.960568 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8024 19:15:48.963894 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8025 19:15:48.970579 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8026 19:15:48.973451 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8027 19:15:48.976812 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8028 19:15:48.980571 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8029 19:15:48.983480 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8030 19:15:48.990315 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8031 19:15:48.993966 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8032 19:15:48.997429 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8033 19:15:49.000214 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8034 19:15:49.003743 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8035 19:15:49.007369 ==
8036 19:15:49.010332 Dram Type= 6, Freq= 0, CH_0, rank 1
8037 19:15:49.013978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8038 19:15:49.014093 ==
8039 19:15:49.014190 DQS Delay:
8040 19:15:49.016921 DQS0 = 0, DQS1 = 0
8041 19:15:49.017000 DQM Delay:
8042 19:15:49.020498 DQM0 = 137, DQM1 = 129
8043 19:15:49.020578 DQ Delay:
8044 19:15:49.024139 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8045 19:15:49.026898 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8046 19:15:49.030457 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =123
8047 19:15:49.033984 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8048 19:15:49.034070
8049 19:15:49.034136
8050 19:15:49.034198 ==
8051 19:15:49.036952 Dram Type= 6, Freq= 0, CH_0, rank 1
8052 19:15:49.043517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8053 19:15:49.043608 ==
8054 19:15:49.043674
8055 19:15:49.043735
8056 19:15:49.043793 TX Vref Scan disable
8057 19:15:49.047109 == TX Byte 0 ==
8058 19:15:49.050633 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8059 19:15:49.057177 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8060 19:15:49.057308 == TX Byte 1 ==
8061 19:15:49.060378 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8062 19:15:49.066905 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8063 19:15:49.067020 ==
8064 19:15:49.070482 Dram Type= 6, Freq= 0, CH_0, rank 1
8065 19:15:49.074033 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8066 19:15:49.074151 ==
8067 19:15:49.087140
8068 19:15:49.090699 TX Vref early break, caculate TX vref
8069 19:15:49.093566 TX Vref=16, minBit 0, minWin=23, winSum=386
8070 19:15:49.097288 TX Vref=18, minBit 1, minWin=23, winSum=394
8071 19:15:49.100153 TX Vref=20, minBit 3, minWin=23, winSum=405
8072 19:15:49.103803 TX Vref=22, minBit 1, minWin=24, winSum=410
8073 19:15:49.107264 TX Vref=24, minBit 1, minWin=24, winSum=419
8074 19:15:49.113769 TX Vref=26, minBit 1, minWin=25, winSum=428
8075 19:15:49.117495 TX Vref=28, minBit 1, minWin=25, winSum=427
8076 19:15:49.120458 TX Vref=30, minBit 0, minWin=25, winSum=416
8077 19:15:49.123431 TX Vref=32, minBit 0, minWin=25, winSum=409
8078 19:15:49.127085 TX Vref=34, minBit 1, minWin=24, winSum=403
8079 19:15:49.133672 [TxChooseVref] Worse bit 1, Min win 25, Win sum 428, Final Vref 26
8080 19:15:49.133761
8081 19:15:49.137197 Final TX Range 0 Vref 26
8082 19:15:49.137313
8083 19:15:49.137407 ==
8084 19:15:49.140091 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 19:15:49.143737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 19:15:49.143850 ==
8087 19:15:49.143956
8088 19:15:49.144053
8089 19:15:49.146584 TX Vref Scan disable
8090 19:15:49.153123 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8091 19:15:49.153216 == TX Byte 0 ==
8092 19:15:49.156753 u2DelayCellOfst[0]=10 cells (3 PI)
8093 19:15:49.160444 u2DelayCellOfst[1]=16 cells (5 PI)
8094 19:15:49.163276 u2DelayCellOfst[2]=10 cells (3 PI)
8095 19:15:49.166825 u2DelayCellOfst[3]=6 cells (2 PI)
8096 19:15:49.170200 u2DelayCellOfst[4]=6 cells (2 PI)
8097 19:15:49.173352 u2DelayCellOfst[5]=0 cells (0 PI)
8098 19:15:49.176527 u2DelayCellOfst[6]=16 cells (5 PI)
8099 19:15:49.180118 u2DelayCellOfst[7]=13 cells (4 PI)
8100 19:15:49.183241 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8101 19:15:49.186548 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8102 19:15:49.189800 == TX Byte 1 ==
8103 19:15:49.189914 u2DelayCellOfst[8]=3 cells (1 PI)
8104 19:15:49.193023 u2DelayCellOfst[9]=0 cells (0 PI)
8105 19:15:49.196271 u2DelayCellOfst[10]=10 cells (3 PI)
8106 19:15:49.200140 u2DelayCellOfst[11]=3 cells (1 PI)
8107 19:15:49.203335 u2DelayCellOfst[12]=10 cells (3 PI)
8108 19:15:49.206591 u2DelayCellOfst[13]=13 cells (4 PI)
8109 19:15:49.210142 u2DelayCellOfst[14]=13 cells (4 PI)
8110 19:15:49.212851 u2DelayCellOfst[15]=10 cells (3 PI)
8111 19:15:49.216172 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8112 19:15:49.222847 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8113 19:15:49.222955 DramC Write-DBI on
8114 19:15:49.223053 ==
8115 19:15:49.226609 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 19:15:49.233252 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 19:15:49.233364 ==
8118 19:15:49.233462
8119 19:15:49.233553
8120 19:15:49.233642 TX Vref Scan disable
8121 19:15:49.236929 == TX Byte 0 ==
8122 19:15:49.240250 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8123 19:15:49.243850 == TX Byte 1 ==
8124 19:15:49.246717 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8125 19:15:49.250267 DramC Write-DBI off
8126 19:15:49.250373
8127 19:15:49.250469 [DATLAT]
8128 19:15:49.250560 Freq=1600, CH0 RK1
8129 19:15:49.250624
8130 19:15:49.253254 DATLAT Default: 0xf
8131 19:15:49.253363 0, 0xFFFF, sum = 0
8132 19:15:49.256930 1, 0xFFFF, sum = 0
8133 19:15:49.257027 2, 0xFFFF, sum = 0
8134 19:15:49.259778 3, 0xFFFF, sum = 0
8135 19:15:49.263554 4, 0xFFFF, sum = 0
8136 19:15:49.263662 5, 0xFFFF, sum = 0
8137 19:15:49.266628 6, 0xFFFF, sum = 0
8138 19:15:49.266729 7, 0xFFFF, sum = 0
8139 19:15:49.270383 8, 0xFFFF, sum = 0
8140 19:15:49.270492 9, 0xFFFF, sum = 0
8141 19:15:49.273335 10, 0xFFFF, sum = 0
8142 19:15:49.273418 11, 0xFFFF, sum = 0
8143 19:15:49.277065 12, 0xFFFF, sum = 0
8144 19:15:49.277174 13, 0xFFFF, sum = 0
8145 19:15:49.280030 14, 0x0, sum = 1
8146 19:15:49.280137 15, 0x0, sum = 2
8147 19:15:49.283501 16, 0x0, sum = 3
8148 19:15:49.283608 17, 0x0, sum = 4
8149 19:15:49.286935 best_step = 15
8150 19:15:49.287037
8151 19:15:49.287146 ==
8152 19:15:49.290325 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 19:15:49.293654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 19:15:49.293771 ==
8155 19:15:49.293866 RX Vref Scan: 0
8156 19:15:49.293959
8157 19:15:49.296682 RX Vref 0 -> 0, step: 1
8158 19:15:49.296788
8159 19:15:49.299869 RX Delay 19 -> 252, step: 4
8160 19:15:49.303368 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8161 19:15:49.309838 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8162 19:15:49.312922 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8163 19:15:49.316194 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8164 19:15:49.319634 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8165 19:15:49.323295 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8166 19:15:49.330043 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8167 19:15:49.332960 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8168 19:15:49.336557 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8169 19:15:49.339555 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8170 19:15:49.343086 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8171 19:15:49.349315 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8172 19:15:49.352825 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8173 19:15:49.356368 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8174 19:15:49.359355 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8175 19:15:49.363033 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8176 19:15:49.366043 ==
8177 19:15:49.369781 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 19:15:49.372654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 19:15:49.372742 ==
8180 19:15:49.372814 DQS Delay:
8181 19:15:49.376323 DQS0 = 0, DQS1 = 0
8182 19:15:49.376435 DQM Delay:
8183 19:15:49.379347 DQM0 = 134, DQM1 = 127
8184 19:15:49.379452 DQ Delay:
8185 19:15:49.382292 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8186 19:15:49.386010 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8187 19:15:49.388886 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8188 19:15:49.392314 DQ12 =134, DQ13 =132, DQ14 =136, DQ15 =136
8189 19:15:49.392414
8190 19:15:49.392489
8191 19:15:49.392579
8192 19:15:49.395997 [DramC_TX_OE_Calibration] TA2
8193 19:15:49.398857 Original DQ_B0 (3 6) =30, OEN = 27
8194 19:15:49.402345 Original DQ_B1 (3 6) =30, OEN = 27
8195 19:15:49.405956 24, 0x0, End_B0=24 End_B1=24
8196 19:15:49.409295 25, 0x0, End_B0=25 End_B1=25
8197 19:15:49.409406 26, 0x0, End_B0=26 End_B1=26
8198 19:15:49.412585 27, 0x0, End_B0=27 End_B1=27
8199 19:15:49.415583 28, 0x0, End_B0=28 End_B1=28
8200 19:15:49.419109 29, 0x0, End_B0=29 End_B1=29
8201 19:15:49.422495 30, 0x0, End_B0=30 End_B1=30
8202 19:15:49.422602 31, 0x4545, End_B0=30 End_B1=30
8203 19:15:49.425840 Byte0 end_step=30 best_step=27
8204 19:15:49.429216 Byte1 end_step=30 best_step=27
8205 19:15:49.432627 Byte0 TX OE(2T, 0.5T) = (3, 3)
8206 19:15:49.436080 Byte1 TX OE(2T, 0.5T) = (3, 3)
8207 19:15:49.436183
8208 19:15:49.436277
8209 19:15:49.442629 [DQSOSCAuto] RK1, (LSB)MR18= 0x220b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8210 19:15:49.445727 CH0 RK1: MR19=303, MR18=220B
8211 19:15:49.452441 CH0_RK1: MR19=0x303, MR18=0x220B, DQSOSC=392, MR23=63, INC=24, DEC=16
8212 19:15:49.455640 [RxdqsGatingPostProcess] freq 1600
8213 19:15:49.462428 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8214 19:15:49.462542 best DQS0 dly(2T, 0.5T) = (1, 1)
8215 19:15:49.465913 best DQS1 dly(2T, 0.5T) = (1, 1)
8216 19:15:49.468777 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8217 19:15:49.472423 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8218 19:15:49.476107 best DQS0 dly(2T, 0.5T) = (1, 1)
8219 19:15:49.478947 best DQS1 dly(2T, 0.5T) = (1, 1)
8220 19:15:49.482614 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8221 19:15:49.485626 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8222 19:15:49.489261 Pre-setting of DQS Precalculation
8223 19:15:49.492242 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8224 19:15:49.492358 ==
8225 19:15:49.495712 Dram Type= 6, Freq= 0, CH_1, rank 0
8226 19:15:49.502505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 19:15:49.502614 ==
8228 19:15:49.505962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8229 19:15:49.512371 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8230 19:15:49.515750 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8231 19:15:49.522395 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8232 19:15:49.529820 [CA 0] Center 41 (12~71) winsize 60
8233 19:15:49.533301 [CA 1] Center 41 (12~71) winsize 60
8234 19:15:49.536794 [CA 2] Center 38 (9~68) winsize 60
8235 19:15:49.539526 [CA 3] Center 37 (9~66) winsize 58
8236 19:15:49.543088 [CA 4] Center 37 (8~67) winsize 60
8237 19:15:49.546470 [CA 5] Center 36 (7~66) winsize 60
8238 19:15:49.546579
8239 19:15:49.550021 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8240 19:15:49.550129
8241 19:15:49.553431 [CATrainingPosCal] consider 1 rank data
8242 19:15:49.556742 u2DelayCellTimex100 = 290/100 ps
8243 19:15:49.559567 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8244 19:15:49.566605 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8245 19:15:49.569959 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8246 19:15:49.573265 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8247 19:15:49.576526 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8248 19:15:49.579617 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8249 19:15:49.579720
8250 19:15:49.583172 CA PerBit enable=1, Macro0, CA PI delay=36
8251 19:15:49.583277
8252 19:15:49.586099 [CBTSetCACLKResult] CA Dly = 36
8253 19:15:49.589532 CS Dly: 11 (0~42)
8254 19:15:49.593185 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8255 19:15:49.596091 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8256 19:15:49.596195 ==
8257 19:15:49.599620 Dram Type= 6, Freq= 0, CH_1, rank 1
8258 19:15:49.602645 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8259 19:15:49.602752 ==
8260 19:15:49.609249 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8261 19:15:49.612794 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8262 19:15:49.619324 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8263 19:15:49.622926 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8264 19:15:49.633370 [CA 0] Center 42 (12~72) winsize 61
8265 19:15:49.636266 [CA 1] Center 42 (12~72) winsize 61
8266 19:15:49.639870 [CA 2] Center 38 (9~68) winsize 60
8267 19:15:49.642635 [CA 3] Center 38 (8~68) winsize 61
8268 19:15:49.646078 [CA 4] Center 38 (8~68) winsize 61
8269 19:15:49.649400 [CA 5] Center 37 (7~67) winsize 61
8270 19:15:49.649507
8271 19:15:49.652891 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8272 19:15:49.652999
8273 19:15:49.656432 [CATrainingPosCal] consider 2 rank data
8274 19:15:49.659306 u2DelayCellTimex100 = 290/100 ps
8275 19:15:49.662741 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8276 19:15:49.669152 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8277 19:15:49.672774 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8278 19:15:49.676379 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8279 19:15:49.679290 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8280 19:15:49.682966 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8281 19:15:49.683072
8282 19:15:49.686464 CA PerBit enable=1, Macro0, CA PI delay=36
8283 19:15:49.686566
8284 19:15:49.689389 [CBTSetCACLKResult] CA Dly = 36
8285 19:15:49.692842 CS Dly: 12 (0~45)
8286 19:15:49.696317 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8287 19:15:49.699636 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8288 19:15:49.699739
8289 19:15:49.702633 ----->DramcWriteLeveling(PI) begin...
8290 19:15:49.702738 ==
8291 19:15:49.705944 Dram Type= 6, Freq= 0, CH_1, rank 0
8292 19:15:49.709675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 19:15:49.712980 ==
8294 19:15:49.713072 Write leveling (Byte 0): 25 => 25
8295 19:15:49.715830 Write leveling (Byte 1): 28 => 28
8296 19:15:49.719266 DramcWriteLeveling(PI) end<-----
8297 19:15:49.719351
8298 19:15:49.719416 ==
8299 19:15:49.723040 Dram Type= 6, Freq= 0, CH_1, rank 0
8300 19:15:49.729623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 19:15:49.729707 ==
8302 19:15:49.732604 [Gating] SW mode calibration
8303 19:15:49.738985 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8304 19:15:49.742707 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8305 19:15:49.749309 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8306 19:15:49.752212 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8307 19:15:49.756332 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8308 19:15:49.759488 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
8309 19:15:49.765637 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8310 19:15:49.769131 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8311 19:15:49.772615 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8312 19:15:49.778972 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8313 19:15:49.782695 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8314 19:15:49.785537 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 19:15:49.791998 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
8316 19:15:49.795760 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (1 0) (1 0)
8317 19:15:49.798796 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 19:15:49.805933 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 19:15:49.808782 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 19:15:49.812095 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 19:15:49.819002 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 19:15:49.822176 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 19:15:49.825427 1 6 8 | B1->B0 | 2d2d 4242 | 0 0 | (0 0) (0 0)
8324 19:15:49.832326 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8325 19:15:49.835515 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8326 19:15:49.838369 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8327 19:15:49.845368 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8328 19:15:49.848919 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8329 19:15:49.851942 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8330 19:15:49.858500 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 19:15:49.862145 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8332 19:15:49.865630 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8333 19:15:49.871717 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8334 19:15:49.875115 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8335 19:15:49.878336 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8336 19:15:49.885248 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 19:15:49.889005 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 19:15:49.891851 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 19:15:49.898561 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 19:15:49.902305 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 19:15:49.905296 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 19:15:49.911992 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 19:15:49.915581 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 19:15:49.918402 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 19:15:49.921881 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 19:15:49.928506 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 19:15:49.932156 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8348 19:15:49.935143 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8349 19:15:49.941924 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 19:15:49.945298 Total UI for P1: 0, mck2ui 16
8351 19:15:49.948507 best dqsien dly found for B0: ( 1, 9, 12)
8352 19:15:49.948620 Total UI for P1: 0, mck2ui 16
8353 19:15:49.954988 best dqsien dly found for B1: ( 1, 9, 10)
8354 19:15:49.958867 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8355 19:15:49.962170 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8356 19:15:49.962283
8357 19:15:49.965000 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8358 19:15:49.968499 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8359 19:15:49.972062 [Gating] SW calibration Done
8360 19:15:49.972142 ==
8361 19:15:49.975423 Dram Type= 6, Freq= 0, CH_1, rank 0
8362 19:15:49.979056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8363 19:15:49.979137 ==
8364 19:15:49.981964 RX Vref Scan: 0
8365 19:15:49.982044
8366 19:15:49.982114 RX Vref 0 -> 0, step: 1
8367 19:15:49.982177
8368 19:15:49.985381 RX Delay 0 -> 252, step: 8
8369 19:15:49.988782 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8370 19:15:49.995524 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8371 19:15:49.998962 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8372 19:15:50.002053 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8373 19:15:50.005648 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8374 19:15:50.008515 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8375 19:15:50.015340 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8376 19:15:50.018343 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8377 19:15:50.021995 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8378 19:15:50.024971 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8379 19:15:50.028418 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8380 19:15:50.031841 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8381 19:15:50.038295 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8382 19:15:50.042024 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8383 19:15:50.044879 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8384 19:15:50.048531 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8385 19:15:50.048615 ==
8386 19:15:50.052189 Dram Type= 6, Freq= 0, CH_1, rank 0
8387 19:15:50.058114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8388 19:15:50.058199 ==
8389 19:15:50.058273 DQS Delay:
8390 19:15:50.061578 DQS0 = 0, DQS1 = 0
8391 19:15:50.061660 DQM Delay:
8392 19:15:50.065059 DQM0 = 137, DQM1 = 132
8393 19:15:50.065146 DQ Delay:
8394 19:15:50.068271 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8395 19:15:50.071384 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8396 19:15:50.075244 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8397 19:15:50.078666 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8398 19:15:50.078752
8399 19:15:50.078816
8400 19:15:50.078879 ==
8401 19:15:50.081340 Dram Type= 6, Freq= 0, CH_1, rank 0
8402 19:15:50.088475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 19:15:50.088571 ==
8404 19:15:50.088680
8405 19:15:50.088771
8406 19:15:50.088878 TX Vref Scan disable
8407 19:15:50.091654 == TX Byte 0 ==
8408 19:15:50.094973 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8409 19:15:50.098578 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8410 19:15:50.102126 == TX Byte 1 ==
8411 19:15:50.104810 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8412 19:15:50.111641 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8413 19:15:50.111732 ==
8414 19:15:50.115297 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 19:15:50.118266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 19:15:50.118351 ==
8417 19:15:50.130779
8418 19:15:50.133493 TX Vref early break, caculate TX vref
8419 19:15:50.137046 TX Vref=16, minBit 0, minWin=23, winSum=378
8420 19:15:50.139944 TX Vref=18, minBit 0, minWin=23, winSum=382
8421 19:15:50.143346 TX Vref=20, minBit 1, minWin=23, winSum=392
8422 19:15:50.146736 TX Vref=22, minBit 6, minWin=24, winSum=410
8423 19:15:50.150201 TX Vref=24, minBit 0, minWin=25, winSum=415
8424 19:15:50.156835 TX Vref=26, minBit 0, minWin=25, winSum=424
8425 19:15:50.160500 TX Vref=28, minBit 0, minWin=25, winSum=426
8426 19:15:50.163433 TX Vref=30, minBit 6, minWin=24, winSum=419
8427 19:15:50.167063 TX Vref=32, minBit 0, minWin=24, winSum=410
8428 19:15:50.169913 TX Vref=34, minBit 2, minWin=23, winSum=401
8429 19:15:50.176290 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 28
8430 19:15:50.176388
8431 19:15:50.179927 Final TX Range 0 Vref 28
8432 19:15:50.180008
8433 19:15:50.180076 ==
8434 19:15:50.183437 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 19:15:50.186220 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 19:15:50.186298 ==
8437 19:15:50.186365
8438 19:15:50.186424
8439 19:15:50.189868 TX Vref Scan disable
8440 19:15:50.196817 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8441 19:15:50.196900 == TX Byte 0 ==
8442 19:15:50.200121 u2DelayCellOfst[0]=16 cells (5 PI)
8443 19:15:50.203208 u2DelayCellOfst[1]=10 cells (3 PI)
8444 19:15:50.206317 u2DelayCellOfst[2]=0 cells (0 PI)
8445 19:15:50.209908 u2DelayCellOfst[3]=6 cells (2 PI)
8446 19:15:50.212932 u2DelayCellOfst[4]=6 cells (2 PI)
8447 19:15:50.216229 u2DelayCellOfst[5]=16 cells (5 PI)
8448 19:15:50.219554 u2DelayCellOfst[6]=16 cells (5 PI)
8449 19:15:50.223243 u2DelayCellOfst[7]=6 cells (2 PI)
8450 19:15:50.226537 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8451 19:15:50.229774 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8452 19:15:50.233136 == TX Byte 1 ==
8453 19:15:50.233217 u2DelayCellOfst[8]=0 cells (0 PI)
8454 19:15:50.236074 u2DelayCellOfst[9]=3 cells (1 PI)
8455 19:15:50.239658 u2DelayCellOfst[10]=13 cells (4 PI)
8456 19:15:50.242618 u2DelayCellOfst[11]=6 cells (2 PI)
8457 19:15:50.246246 u2DelayCellOfst[12]=16 cells (5 PI)
8458 19:15:50.249902 u2DelayCellOfst[13]=16 cells (5 PI)
8459 19:15:50.252761 u2DelayCellOfst[14]=20 cells (6 PI)
8460 19:15:50.256023 u2DelayCellOfst[15]=16 cells (5 PI)
8461 19:15:50.259510 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8462 19:15:50.266166 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8463 19:15:50.266273 DramC Write-DBI on
8464 19:15:50.266370 ==
8465 19:15:50.269047 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 19:15:50.275593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8467 19:15:50.275683 ==
8468 19:15:50.275752
8469 19:15:50.275813
8470 19:15:50.275875 TX Vref Scan disable
8471 19:15:50.279941 == TX Byte 0 ==
8472 19:15:50.282778 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8473 19:15:50.286392 == TX Byte 1 ==
8474 19:15:50.290060 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8475 19:15:50.290143 DramC Write-DBI off
8476 19:15:50.293168
8477 19:15:50.293254 [DATLAT]
8478 19:15:50.293324 Freq=1600, CH1 RK0
8479 19:15:50.293389
8480 19:15:50.296111 DATLAT Default: 0xf
8481 19:15:50.296184 0, 0xFFFF, sum = 0
8482 19:15:50.299795 1, 0xFFFF, sum = 0
8483 19:15:50.299874 2, 0xFFFF, sum = 0
8484 19:15:50.302716 3, 0xFFFF, sum = 0
8485 19:15:50.306387 4, 0xFFFF, sum = 0
8486 19:15:50.306468 5, 0xFFFF, sum = 0
8487 19:15:50.310021 6, 0xFFFF, sum = 0
8488 19:15:50.310102 7, 0xFFFF, sum = 0
8489 19:15:50.312884 8, 0xFFFF, sum = 0
8490 19:15:50.312965 9, 0xFFFF, sum = 0
8491 19:15:50.316465 10, 0xFFFF, sum = 0
8492 19:15:50.316560 11, 0xFFFF, sum = 0
8493 19:15:50.319918 12, 0xFFFF, sum = 0
8494 19:15:50.320001 13, 0xFFFF, sum = 0
8495 19:15:50.323254 14, 0x0, sum = 1
8496 19:15:50.323334 15, 0x0, sum = 2
8497 19:15:50.326614 16, 0x0, sum = 3
8498 19:15:50.326694 17, 0x0, sum = 4
8499 19:15:50.329893 best_step = 15
8500 19:15:50.329970
8501 19:15:50.330036 ==
8502 19:15:50.333254 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 19:15:50.336859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 19:15:50.336974 ==
8505 19:15:50.337080 RX Vref Scan: 1
8506 19:15:50.339295
8507 19:15:50.339376 Set Vref Range= 24 -> 127
8508 19:15:50.339439
8509 19:15:50.342954 RX Vref 24 -> 127, step: 1
8510 19:15:50.343066
8511 19:15:50.346453 RX Delay 27 -> 252, step: 4
8512 19:15:50.346535
8513 19:15:50.349899 Set Vref, RX VrefLevel [Byte0]: 24
8514 19:15:50.353070 [Byte1]: 24
8515 19:15:50.353200
8516 19:15:50.356111 Set Vref, RX VrefLevel [Byte0]: 25
8517 19:15:50.359256 [Byte1]: 25
8518 19:15:50.359365
8519 19:15:50.362978 Set Vref, RX VrefLevel [Byte0]: 26
8520 19:15:50.366331 [Byte1]: 26
8521 19:15:50.369998
8522 19:15:50.370108 Set Vref, RX VrefLevel [Byte0]: 27
8523 19:15:50.373189 [Byte1]: 27
8524 19:15:50.377132
8525 19:15:50.377250 Set Vref, RX VrefLevel [Byte0]: 28
8526 19:15:50.380713 [Byte1]: 28
8527 19:15:50.385249
8528 19:15:50.385372 Set Vref, RX VrefLevel [Byte0]: 29
8529 19:15:50.388046 [Byte1]: 29
8530 19:15:50.392145
8531 19:15:50.392252 Set Vref, RX VrefLevel [Byte0]: 30
8532 19:15:50.395796 [Byte1]: 30
8533 19:15:50.400281
8534 19:15:50.400384 Set Vref, RX VrefLevel [Byte0]: 31
8535 19:15:50.403322 [Byte1]: 31
8536 19:15:50.407602
8537 19:15:50.407695 Set Vref, RX VrefLevel [Byte0]: 32
8538 19:15:50.410591 [Byte1]: 32
8539 19:15:50.415023
8540 19:15:50.415103 Set Vref, RX VrefLevel [Byte0]: 33
8541 19:15:50.418825 [Byte1]: 33
8542 19:15:50.422423
8543 19:15:50.422505 Set Vref, RX VrefLevel [Byte0]: 34
8544 19:15:50.425980 [Byte1]: 34
8545 19:15:50.430426
8546 19:15:50.430535 Set Vref, RX VrefLevel [Byte0]: 35
8547 19:15:50.433330 [Byte1]: 35
8548 19:15:50.437757
8549 19:15:50.437857 Set Vref, RX VrefLevel [Byte0]: 36
8550 19:15:50.440826 [Byte1]: 36
8551 19:15:50.445266
8552 19:15:50.445389 Set Vref, RX VrefLevel [Byte0]: 37
8553 19:15:50.448715 [Byte1]: 37
8554 19:15:50.453018
8555 19:15:50.453106 Set Vref, RX VrefLevel [Byte0]: 38
8556 19:15:50.455832 [Byte1]: 38
8557 19:15:50.460573
8558 19:15:50.460680 Set Vref, RX VrefLevel [Byte0]: 39
8559 19:15:50.463342 [Byte1]: 39
8560 19:15:50.467921
8561 19:15:50.468032 Set Vref, RX VrefLevel [Byte0]: 40
8562 19:15:50.470808 [Byte1]: 40
8563 19:15:50.475096
8564 19:15:50.475203 Set Vref, RX VrefLevel [Byte0]: 41
8565 19:15:50.478982 [Byte1]: 41
8566 19:15:50.482821
8567 19:15:50.482921 Set Vref, RX VrefLevel [Byte0]: 42
8568 19:15:50.485925 [Byte1]: 42
8569 19:15:50.490436
8570 19:15:50.490550 Set Vref, RX VrefLevel [Byte0]: 43
8571 19:15:50.493554 [Byte1]: 43
8572 19:15:50.497779
8573 19:15:50.497863 Set Vref, RX VrefLevel [Byte0]: 44
8574 19:15:50.501106 [Byte1]: 44
8575 19:15:50.505450
8576 19:15:50.505565 Set Vref, RX VrefLevel [Byte0]: 45
8577 19:15:50.508866 [Byte1]: 45
8578 19:15:50.513139
8579 19:15:50.513226 Set Vref, RX VrefLevel [Byte0]: 46
8580 19:15:50.516173 [Byte1]: 46
8581 19:15:50.520470
8582 19:15:50.520553 Set Vref, RX VrefLevel [Byte0]: 47
8583 19:15:50.524148 [Byte1]: 47
8584 19:15:50.528345
8585 19:15:50.528436 Set Vref, RX VrefLevel [Byte0]: 48
8586 19:15:50.531159 [Byte1]: 48
8587 19:15:50.535593
8588 19:15:50.535675 Set Vref, RX VrefLevel [Byte0]: 49
8589 19:15:50.539190 [Byte1]: 49
8590 19:15:50.542997
8591 19:15:50.543107 Set Vref, RX VrefLevel [Byte0]: 50
8592 19:15:50.546588 [Byte1]: 50
8593 19:15:50.550971
8594 19:15:50.551084 Set Vref, RX VrefLevel [Byte0]: 51
8595 19:15:50.553943 [Byte1]: 51
8596 19:15:50.558302
8597 19:15:50.558394 Set Vref, RX VrefLevel [Byte0]: 52
8598 19:15:50.561263 [Byte1]: 52
8599 19:15:50.565440
8600 19:15:50.565562 Set Vref, RX VrefLevel [Byte0]: 53
8601 19:15:50.569040 [Byte1]: 53
8602 19:15:50.573223
8603 19:15:50.573330 Set Vref, RX VrefLevel [Byte0]: 54
8604 19:15:50.576620 [Byte1]: 54
8605 19:15:50.580977
8606 19:15:50.581057 Set Vref, RX VrefLevel [Byte0]: 55
8607 19:15:50.583869 [Byte1]: 55
8608 19:15:50.588174
8609 19:15:50.588289 Set Vref, RX VrefLevel [Byte0]: 56
8610 19:15:50.591604 [Byte1]: 56
8611 19:15:50.595810
8612 19:15:50.595919 Set Vref, RX VrefLevel [Byte0]: 57
8613 19:15:50.599344 [Byte1]: 57
8614 19:15:50.603603
8615 19:15:50.603681 Set Vref, RX VrefLevel [Byte0]: 58
8616 19:15:50.606541 [Byte1]: 58
8617 19:15:50.610779
8618 19:15:50.610866 Set Vref, RX VrefLevel [Byte0]: 59
8619 19:15:50.614059 [Byte1]: 59
8620 19:15:50.618773
8621 19:15:50.618866 Set Vref, RX VrefLevel [Byte0]: 60
8622 19:15:50.621826 [Byte1]: 60
8623 19:15:50.625966
8624 19:15:50.626076 Set Vref, RX VrefLevel [Byte0]: 61
8625 19:15:50.629301 [Byte1]: 61
8626 19:15:50.633380
8627 19:15:50.633505 Set Vref, RX VrefLevel [Byte0]: 62
8628 19:15:50.636884 [Byte1]: 62
8629 19:15:50.641228
8630 19:15:50.641350 Set Vref, RX VrefLevel [Byte0]: 63
8631 19:15:50.644497 [Byte1]: 63
8632 19:15:50.648810
8633 19:15:50.648907 Set Vref, RX VrefLevel [Byte0]: 64
8634 19:15:50.651605 [Byte1]: 64
8635 19:15:50.655842
8636 19:15:50.655920 Set Vref, RX VrefLevel [Byte0]: 65
8637 19:15:50.659526 [Byte1]: 65
8638 19:15:50.663785
8639 19:15:50.663895 Set Vref, RX VrefLevel [Byte0]: 66
8640 19:15:50.666788 [Byte1]: 66
8641 19:15:50.671080
8642 19:15:50.671179 Set Vref, RX VrefLevel [Byte0]: 67
8643 19:15:50.674506 [Byte1]: 67
8644 19:15:50.678903
8645 19:15:50.679017 Set Vref, RX VrefLevel [Byte0]: 68
8646 19:15:50.682470 [Byte1]: 68
8647 19:15:50.686011
8648 19:15:50.686117 Set Vref, RX VrefLevel [Byte0]: 69
8649 19:15:50.689688 [Byte1]: 69
8650 19:15:50.693457
8651 19:15:50.693543 Set Vref, RX VrefLevel [Byte0]: 70
8652 19:15:50.697064 [Byte1]: 70
8653 19:15:50.701366
8654 19:15:50.701445 Set Vref, RX VrefLevel [Byte0]: 71
8655 19:15:50.704898 [Byte1]: 71
8656 19:15:50.708561
8657 19:15:50.708655 Set Vref, RX VrefLevel [Byte0]: 72
8658 19:15:50.712304 [Byte1]: 72
8659 19:15:50.716046
8660 19:15:50.716159 Set Vref, RX VrefLevel [Byte0]: 73
8661 19:15:50.719746 [Byte1]: 73
8662 19:15:50.724157
8663 19:15:50.724271 Set Vref, RX VrefLevel [Byte0]: 74
8664 19:15:50.727077 [Byte1]: 74
8665 19:15:50.731512
8666 19:15:50.731627 Set Vref, RX VrefLevel [Byte0]: 75
8667 19:15:50.734553 [Byte1]: 75
8668 19:15:50.738943
8669 19:15:50.739050 Set Vref, RX VrefLevel [Byte0]: 76
8670 19:15:50.742552 [Byte1]: 76
8671 19:15:50.746568
8672 19:15:50.746681 Final RX Vref Byte 0 = 57 to rank0
8673 19:15:50.749545 Final RX Vref Byte 1 = 56 to rank0
8674 19:15:50.752919 Final RX Vref Byte 0 = 57 to rank1
8675 19:15:50.756371 Final RX Vref Byte 1 = 56 to rank1==
8676 19:15:50.759940 Dram Type= 6, Freq= 0, CH_1, rank 0
8677 19:15:50.766157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8678 19:15:50.766272 ==
8679 19:15:50.766366 DQS Delay:
8680 19:15:50.769851 DQS0 = 0, DQS1 = 0
8681 19:15:50.769927 DQM Delay:
8682 19:15:50.770000 DQM0 = 134, DQM1 = 131
8683 19:15:50.773004 DQ Delay:
8684 19:15:50.776484 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8685 19:15:50.779317 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8686 19:15:50.782795 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =122
8687 19:15:50.786351 DQ12 =140, DQ13 =138, DQ14 =140, DQ15 =140
8688 19:15:50.786522
8689 19:15:50.786650
8690 19:15:50.786779
8691 19:15:50.789460 [DramC_TX_OE_Calibration] TA2
8692 19:15:50.793131 Original DQ_B0 (3 6) =30, OEN = 27
8693 19:15:50.796186 Original DQ_B1 (3 6) =30, OEN = 27
8694 19:15:50.799172 24, 0x0, End_B0=24 End_B1=24
8695 19:15:50.799275 25, 0x0, End_B0=25 End_B1=25
8696 19:15:50.802878 26, 0x0, End_B0=26 End_B1=26
8697 19:15:50.805744 27, 0x0, End_B0=27 End_B1=27
8698 19:15:50.809260 28, 0x0, End_B0=28 End_B1=28
8699 19:15:50.812895 29, 0x0, End_B0=29 End_B1=29
8700 19:15:50.813020 30, 0x0, End_B0=30 End_B1=30
8701 19:15:50.815956 31, 0x4141, End_B0=30 End_B1=30
8702 19:15:50.819832 Byte0 end_step=30 best_step=27
8703 19:15:50.822827 Byte1 end_step=30 best_step=27
8704 19:15:50.825847 Byte0 TX OE(2T, 0.5T) = (3, 3)
8705 19:15:50.829493 Byte1 TX OE(2T, 0.5T) = (3, 3)
8706 19:15:50.829610
8707 19:15:50.829707
8708 19:15:50.836150 [DQSOSCAuto] RK0, (LSB)MR18= 0x1825, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
8709 19:15:50.839170 CH1 RK0: MR19=303, MR18=1825
8710 19:15:50.846110 CH1_RK0: MR19=0x303, MR18=0x1825, DQSOSC=391, MR23=63, INC=24, DEC=16
8711 19:15:50.846234
8712 19:15:50.849251 ----->DramcWriteLeveling(PI) begin...
8713 19:15:50.849361 ==
8714 19:15:50.852353 Dram Type= 6, Freq= 0, CH_1, rank 1
8715 19:15:50.855919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8716 19:15:50.856036 ==
8717 19:15:50.859352 Write leveling (Byte 0): 24 => 24
8718 19:15:50.862266 Write leveling (Byte 1): 28 => 28
8719 19:15:50.865579 DramcWriteLeveling(PI) end<-----
8720 19:15:50.865667
8721 19:15:50.865733 ==
8722 19:15:50.868806 Dram Type= 6, Freq= 0, CH_1, rank 1
8723 19:15:50.872641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8724 19:15:50.872721 ==
8725 19:15:50.876023 [Gating] SW mode calibration
8726 19:15:50.882164 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8727 19:15:50.889178 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8728 19:15:50.892289 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8729 19:15:50.898858 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8730 19:15:50.902293 1 4 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8731 19:15:50.905429 1 4 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
8732 19:15:50.908583 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8733 19:15:50.915862 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8734 19:15:50.918722 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8735 19:15:50.922288 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8736 19:15:50.928880 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8737 19:15:50.931881 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8738 19:15:50.935594 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (0 1) (1 1)
8739 19:15:50.942206 1 5 12 | B1->B0 | 2424 3131 | 0 1 | (0 0) (1 0)
8740 19:15:50.945181 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8741 19:15:50.948926 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8742 19:15:50.955591 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 19:15:50.958490 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 19:15:50.962104 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 19:15:50.968671 1 6 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8746 19:15:50.972441 1 6 8 | B1->B0 | 3131 2323 | 1 0 | (0 0) (0 0)
8747 19:15:50.975258 1 6 12 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8748 19:15:50.981839 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8749 19:15:50.985376 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8750 19:15:50.988870 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 19:15:50.995661 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 19:15:50.998496 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 19:15:51.002232 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8754 19:15:51.008465 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8755 19:15:51.011891 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8756 19:15:51.015297 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8757 19:15:51.021976 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 19:15:51.025209 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 19:15:51.028346 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 19:15:51.035223 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 19:15:51.038116 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 19:15:51.041576 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 19:15:51.045259 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 19:15:51.051976 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 19:15:51.055636 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 19:15:51.058557 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 19:15:51.065028 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 19:15:51.068691 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 19:15:51.071588 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8770 19:15:51.078162 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8771 19:15:51.081993 Total UI for P1: 0, mck2ui 16
8772 19:15:51.084877 best dqsien dly found for B1: ( 1, 9, 4)
8773 19:15:51.088112 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8774 19:15:51.091525 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 19:15:51.094949 Total UI for P1: 0, mck2ui 16
8776 19:15:51.098143 best dqsien dly found for B0: ( 1, 9, 10)
8777 19:15:51.101445 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8778 19:15:51.104827 best DQS1 dly(MCK, UI, PI) = (1, 9, 4)
8779 19:15:51.104941
8780 19:15:51.111803 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8781 19:15:51.114762 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 4)
8782 19:15:51.118273 [Gating] SW calibration Done
8783 19:15:51.118365 ==
8784 19:15:51.121206 Dram Type= 6, Freq= 0, CH_1, rank 1
8785 19:15:51.124927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8786 19:15:51.125034 ==
8787 19:15:51.125134 RX Vref Scan: 0
8788 19:15:51.125225
8789 19:15:51.127946 RX Vref 0 -> 0, step: 1
8790 19:15:51.128018
8791 19:15:51.131572 RX Delay 0 -> 252, step: 8
8792 19:15:51.134547 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8793 19:15:51.138293 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8794 19:15:51.141798 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8795 19:15:51.147879 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8796 19:15:51.151205 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8797 19:15:51.154920 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8798 19:15:51.157930 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8799 19:15:51.161581 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8800 19:15:51.168144 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8801 19:15:51.171545 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8802 19:15:51.174468 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8803 19:15:51.178317 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8804 19:15:51.181240 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8805 19:15:51.187960 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8806 19:15:51.190932 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8807 19:15:51.194675 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8808 19:15:51.194790 ==
8809 19:15:51.197516 Dram Type= 6, Freq= 0, CH_1, rank 1
8810 19:15:51.201138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8811 19:15:51.204824 ==
8812 19:15:51.204944 DQS Delay:
8813 19:15:51.205043 DQS0 = 0, DQS1 = 0
8814 19:15:51.207525 DQM Delay:
8815 19:15:51.207633 DQM0 = 136, DQM1 = 133
8816 19:15:51.210980 DQ Delay:
8817 19:15:51.214426 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8818 19:15:51.217767 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8819 19:15:51.220976 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8820 19:15:51.224433 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8821 19:15:51.224550
8822 19:15:51.224642
8823 19:15:51.224787 ==
8824 19:15:51.227908 Dram Type= 6, Freq= 0, CH_1, rank 1
8825 19:15:51.230889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 19:15:51.231017 ==
8827 19:15:51.234595
8828 19:15:51.234729
8829 19:15:51.234863 TX Vref Scan disable
8830 19:15:51.237726 == TX Byte 0 ==
8831 19:15:51.241484 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8832 19:15:51.244397 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8833 19:15:51.247409 == TX Byte 1 ==
8834 19:15:51.251135 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8835 19:15:51.254145 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8836 19:15:51.254280 ==
8837 19:15:51.257789 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 19:15:51.264532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 19:15:51.264649 ==
8840 19:15:51.276895
8841 19:15:51.280619 TX Vref early break, caculate TX vref
8842 19:15:51.283904 TX Vref=16, minBit 0, minWin=23, winSum=383
8843 19:15:51.287191 TX Vref=18, minBit 0, minWin=23, winSum=391
8844 19:15:51.290273 TX Vref=20, minBit 0, minWin=24, winSum=404
8845 19:15:51.293833 TX Vref=22, minBit 0, minWin=25, winSum=411
8846 19:15:51.296827 TX Vref=24, minBit 0, minWin=25, winSum=422
8847 19:15:51.303332 TX Vref=26, minBit 10, minWin=25, winSum=424
8848 19:15:51.306897 TX Vref=28, minBit 0, minWin=25, winSum=422
8849 19:15:51.309852 TX Vref=30, minBit 6, minWin=25, winSum=421
8850 19:15:51.313317 TX Vref=32, minBit 0, minWin=25, winSum=415
8851 19:15:51.316964 TX Vref=34, minBit 0, minWin=25, winSum=408
8852 19:15:51.319803 TX Vref=36, minBit 6, minWin=23, winSum=398
8853 19:15:51.326820 [TxChooseVref] Worse bit 10, Min win 25, Win sum 424, Final Vref 26
8854 19:15:51.326938
8855 19:15:51.330136 Final TX Range 0 Vref 26
8856 19:15:51.330255
8857 19:15:51.330361 ==
8858 19:15:51.333389 Dram Type= 6, Freq= 0, CH_1, rank 1
8859 19:15:51.336580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8860 19:15:51.336705 ==
8861 19:15:51.339926
8862 19:15:51.340038
8863 19:15:51.340146 TX Vref Scan disable
8864 19:15:51.346564 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8865 19:15:51.346680 == TX Byte 0 ==
8866 19:15:51.349530 u2DelayCellOfst[0]=16 cells (5 PI)
8867 19:15:51.353409 u2DelayCellOfst[1]=10 cells (3 PI)
8868 19:15:51.356227 u2DelayCellOfst[2]=0 cells (0 PI)
8869 19:15:51.360012 u2DelayCellOfst[3]=6 cells (2 PI)
8870 19:15:51.362932 u2DelayCellOfst[4]=10 cells (3 PI)
8871 19:15:51.366623 u2DelayCellOfst[5]=16 cells (5 PI)
8872 19:15:51.369553 u2DelayCellOfst[6]=16 cells (5 PI)
8873 19:15:51.372581 u2DelayCellOfst[7]=6 cells (2 PI)
8874 19:15:51.376190 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8875 19:15:51.379297 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8876 19:15:51.383006 == TX Byte 1 ==
8877 19:15:51.385836 u2DelayCellOfst[8]=0 cells (0 PI)
8878 19:15:51.389570 u2DelayCellOfst[9]=3 cells (1 PI)
8879 19:15:51.392545 u2DelayCellOfst[10]=10 cells (3 PI)
8880 19:15:51.396251 u2DelayCellOfst[11]=3 cells (1 PI)
8881 19:15:51.399142 u2DelayCellOfst[12]=13 cells (4 PI)
8882 19:15:51.402522 u2DelayCellOfst[13]=13 cells (4 PI)
8883 19:15:51.402630 u2DelayCellOfst[14]=16 cells (5 PI)
8884 19:15:51.406019 u2DelayCellOfst[15]=16 cells (5 PI)
8885 19:15:51.412806 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8886 19:15:51.416012 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8887 19:15:51.416124 DramC Write-DBI on
8888 19:15:51.419172 ==
8889 19:15:51.422471 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 19:15:51.426088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 19:15:51.426204 ==
8892 19:15:51.426304
8893 19:15:51.426393
8894 19:15:51.429065 TX Vref Scan disable
8895 19:15:51.429155 == TX Byte 0 ==
8896 19:15:51.435978 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8897 19:15:51.436082 == TX Byte 1 ==
8898 19:15:51.438949 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8899 19:15:51.442462 DramC Write-DBI off
8900 19:15:51.442591
8901 19:15:51.442696 [DATLAT]
8902 19:15:51.445821 Freq=1600, CH1 RK1
8903 19:15:51.445932
8904 19:15:51.446029 DATLAT Default: 0xf
8905 19:15:51.449201 0, 0xFFFF, sum = 0
8906 19:15:51.449307 1, 0xFFFF, sum = 0
8907 19:15:51.452226 2, 0xFFFF, sum = 0
8908 19:15:51.452348 3, 0xFFFF, sum = 0
8909 19:15:51.455809 4, 0xFFFF, sum = 0
8910 19:15:51.455892 5, 0xFFFF, sum = 0
8911 19:15:51.458728 6, 0xFFFF, sum = 0
8912 19:15:51.462327 7, 0xFFFF, sum = 0
8913 19:15:51.462410 8, 0xFFFF, sum = 0
8914 19:15:51.465327 9, 0xFFFF, sum = 0
8915 19:15:51.465406 10, 0xFFFF, sum = 0
8916 19:15:51.469011 11, 0xFFFF, sum = 0
8917 19:15:51.469124 12, 0xFFFF, sum = 0
8918 19:15:51.472092 13, 0xFFFF, sum = 0
8919 19:15:51.472192 14, 0x0, sum = 1
8920 19:15:51.475794 15, 0x0, sum = 2
8921 19:15:51.475907 16, 0x0, sum = 3
8922 19:15:51.478716 17, 0x0, sum = 4
8923 19:15:51.478832 best_step = 15
8924 19:15:51.478927
8925 19:15:51.479028 ==
8926 19:15:51.482415 Dram Type= 6, Freq= 0, CH_1, rank 1
8927 19:15:51.485513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8928 19:15:51.485617 ==
8929 19:15:51.489285 RX Vref Scan: 0
8930 19:15:51.489391
8931 19:15:51.492154 RX Vref 0 -> 0, step: 1
8932 19:15:51.492255
8933 19:15:51.492357 RX Delay 19 -> 252, step: 4
8934 19:15:51.499628 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8935 19:15:51.502476 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8936 19:15:51.506272 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8937 19:15:51.509219 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8938 19:15:51.512907 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8939 19:15:51.519326 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8940 19:15:51.522861 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8941 19:15:51.525906 iDelay=195, Bit 7, Center 132 (79 ~ 186) 108
8942 19:15:51.529630 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8943 19:15:51.532561 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8944 19:15:51.539635 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8945 19:15:51.542412 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8946 19:15:51.545754 iDelay=195, Bit 12, Center 142 (91 ~ 194) 104
8947 19:15:51.548911 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8948 19:15:51.552801 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8949 19:15:51.559356 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8950 19:15:51.559481 ==
8951 19:15:51.562744 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 19:15:51.565670 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 19:15:51.565779 ==
8954 19:15:51.565876 DQS Delay:
8955 19:15:51.568947 DQS0 = 0, DQS1 = 0
8956 19:15:51.569058 DQM Delay:
8957 19:15:51.572189 DQM0 = 133, DQM1 = 130
8958 19:15:51.572298 DQ Delay:
8959 19:15:51.575572 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
8960 19:15:51.579319 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =132
8961 19:15:51.582423 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8962 19:15:51.585750 DQ12 =142, DQ13 =138, DQ14 =136, DQ15 =138
8963 19:15:51.585856
8964 19:15:51.588730
8965 19:15:51.588846
8966 19:15:51.588943 [DramC_TX_OE_Calibration] TA2
8967 19:15:51.592493 Original DQ_B0 (3 6) =30, OEN = 27
8968 19:15:51.595423 Original DQ_B1 (3 6) =30, OEN = 27
8969 19:15:51.598998 24, 0x0, End_B0=24 End_B1=24
8970 19:15:51.602096 25, 0x0, End_B0=25 End_B1=25
8971 19:15:51.605801 26, 0x0, End_B0=26 End_B1=26
8972 19:15:51.605912 27, 0x0, End_B0=27 End_B1=27
8973 19:15:51.608762 28, 0x0, End_B0=28 End_B1=28
8974 19:15:51.612440 29, 0x0, End_B0=29 End_B1=29
8975 19:15:51.616147 30, 0x0, End_B0=30 End_B1=30
8976 19:15:51.619090 31, 0x4141, End_B0=30 End_B1=30
8977 19:15:51.619202 Byte0 end_step=30 best_step=27
8978 19:15:51.622542 Byte1 end_step=30 best_step=27
8979 19:15:51.625427 Byte0 TX OE(2T, 0.5T) = (3, 3)
8980 19:15:51.628995 Byte1 TX OE(2T, 0.5T) = (3, 3)
8981 19:15:51.629099
8982 19:15:51.629204
8983 19:15:51.636172 [DQSOSCAuto] RK1, (LSB)MR18= 0x2106, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
8984 19:15:51.638972 CH1 RK1: MR19=303, MR18=2106
8985 19:15:51.645577 CH1_RK1: MR19=0x303, MR18=0x2106, DQSOSC=393, MR23=63, INC=23, DEC=15
8986 19:15:51.648572 [RxdqsGatingPostProcess] freq 1600
8987 19:15:51.655946 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8988 19:15:51.656061 best DQS0 dly(2T, 0.5T) = (1, 1)
8989 19:15:51.659321 best DQS1 dly(2T, 0.5T) = (1, 1)
8990 19:15:51.662398 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8991 19:15:51.666060 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8992 19:15:51.668887 best DQS0 dly(2T, 0.5T) = (1, 1)
8993 19:15:51.672548 best DQS1 dly(2T, 0.5T) = (1, 1)
8994 19:15:51.675364 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8995 19:15:51.678977 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8996 19:15:51.682466 Pre-setting of DQS Precalculation
8997 19:15:51.685869 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8998 19:15:51.695499 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8999 19:15:51.701889 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9000 19:15:51.702001
9001 19:15:51.702104
9002 19:15:51.705237 [Calibration Summary] 3200 Mbps
9003 19:15:51.705349 CH 0, Rank 0
9004 19:15:51.708900 SW Impedance : PASS
9005 19:15:51.709003 DUTY Scan : NO K
9006 19:15:51.712177 ZQ Calibration : PASS
9007 19:15:51.715330 Jitter Meter : NO K
9008 19:15:51.715446 CBT Training : PASS
9009 19:15:51.719312 Write leveling : PASS
9010 19:15:51.722060 RX DQS gating : PASS
9011 19:15:51.722159 RX DQ/DQS(RDDQC) : PASS
9012 19:15:51.725796 TX DQ/DQS : PASS
9013 19:15:51.728577 RX DATLAT : PASS
9014 19:15:51.728699 RX DQ/DQS(Engine): PASS
9015 19:15:51.732216 TX OE : PASS
9016 19:15:51.732329 All Pass.
9017 19:15:51.732439
9018 19:15:51.735786 CH 0, Rank 1
9019 19:15:51.735896 SW Impedance : PASS
9020 19:15:51.738552 DUTY Scan : NO K
9021 19:15:51.738667 ZQ Calibration : PASS
9022 19:15:51.742298 Jitter Meter : NO K
9023 19:15:51.745277 CBT Training : PASS
9024 19:15:51.745397 Write leveling : PASS
9025 19:15:51.748863 RX DQS gating : PASS
9026 19:15:51.752573 RX DQ/DQS(RDDQC) : PASS
9027 19:15:51.752674 TX DQ/DQS : PASS
9028 19:15:51.755529 RX DATLAT : PASS
9029 19:15:51.759229 RX DQ/DQS(Engine): PASS
9030 19:15:51.759348 TX OE : PASS
9031 19:15:51.762038 All Pass.
9032 19:15:51.762149
9033 19:15:51.762240 CH 1, Rank 0
9034 19:15:51.765723 SW Impedance : PASS
9035 19:15:51.765826 DUTY Scan : NO K
9036 19:15:51.768490 ZQ Calibration : PASS
9037 19:15:51.772243 Jitter Meter : NO K
9038 19:15:51.772351 CBT Training : PASS
9039 19:15:51.775046 Write leveling : PASS
9040 19:15:51.778630 RX DQS gating : PASS
9041 19:15:51.778734 RX DQ/DQS(RDDQC) : PASS
9042 19:15:51.782209 TX DQ/DQS : PASS
9043 19:15:51.782288 RX DATLAT : PASS
9044 19:15:51.785022 RX DQ/DQS(Engine): PASS
9045 19:15:51.788766 TX OE : PASS
9046 19:15:51.788846 All Pass.
9047 19:15:51.788909
9048 19:15:51.788969 CH 1, Rank 1
9049 19:15:51.791710 SW Impedance : PASS
9050 19:15:51.795365 DUTY Scan : NO K
9051 19:15:51.795446 ZQ Calibration : PASS
9052 19:15:51.799097 Jitter Meter : NO K
9053 19:15:51.802003 CBT Training : PASS
9054 19:15:51.802131 Write leveling : PASS
9055 19:15:51.805793 RX DQS gating : PASS
9056 19:15:51.808628 RX DQ/DQS(RDDQC) : PASS
9057 19:15:51.808726 TX DQ/DQS : PASS
9058 19:15:51.812316 RX DATLAT : PASS
9059 19:15:51.815404 RX DQ/DQS(Engine): PASS
9060 19:15:51.815507 TX OE : PASS
9061 19:15:51.818294 All Pass.
9062 19:15:51.818369
9063 19:15:51.818431 DramC Write-DBI on
9064 19:15:51.821894 PER_BANK_REFRESH: Hybrid Mode
9065 19:15:51.821967 TX_TRACKING: ON
9066 19:15:51.831590 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9067 19:15:51.841573 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9068 19:15:51.848468 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9069 19:15:51.851639 [FAST_K] Save calibration result to emmc
9070 19:15:51.855023 sync common calibartion params.
9071 19:15:51.855164 sync cbt_mode0:1, 1:1
9072 19:15:51.858598 dram_init: ddr_geometry: 2
9073 19:15:51.861673 dram_init: ddr_geometry: 2
9074 19:15:51.861785 dram_init: ddr_geometry: 2
9075 19:15:51.865367 0:dram_rank_size:100000000
9076 19:15:51.868295 1:dram_rank_size:100000000
9077 19:15:51.875071 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9078 19:15:51.875188 DFS_SHUFFLE_HW_MODE: ON
9079 19:15:51.877960 dramc_set_vcore_voltage set vcore to 725000
9080 19:15:51.881565 Read voltage for 1600, 0
9081 19:15:51.881674 Vio18 = 0
9082 19:15:51.885334 Vcore = 725000
9083 19:15:51.885447 Vdram = 0
9084 19:15:51.885545 Vddq = 0
9085 19:15:51.888049 Vmddr = 0
9086 19:15:51.888158 switch to 3200 Mbps bootup
9087 19:15:51.891729 [DramcRunTimeConfig]
9088 19:15:51.891845 PHYPLL
9089 19:15:51.895244 DPM_CONTROL_AFTERK: ON
9090 19:15:51.895358 PER_BANK_REFRESH: ON
9091 19:15:51.898236 REFRESH_OVERHEAD_REDUCTION: ON
9092 19:15:51.901345 CMD_PICG_NEW_MODE: OFF
9093 19:15:51.901458 XRTWTW_NEW_MODE: ON
9094 19:15:51.905012 XRTRTR_NEW_MODE: ON
9095 19:15:51.905131 TX_TRACKING: ON
9096 19:15:51.908623 RDSEL_TRACKING: OFF
9097 19:15:51.911552 DQS Precalculation for DVFS: ON
9098 19:15:51.911662 RX_TRACKING: OFF
9099 19:15:51.915131 HW_GATING DBG: ON
9100 19:15:51.915245 ZQCS_ENABLE_LP4: ON
9101 19:15:51.917976 RX_PICG_NEW_MODE: ON
9102 19:15:51.918079 TX_PICG_NEW_MODE: ON
9103 19:15:51.921628 ENABLE_RX_DCM_DPHY: ON
9104 19:15:51.924608 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9105 19:15:51.928172 DUMMY_READ_FOR_TRACKING: OFF
9106 19:15:51.928275 !!! SPM_CONTROL_AFTERK: OFF
9107 19:15:51.931194 !!! SPM could not control APHY
9108 19:15:51.934835 IMPEDANCE_TRACKING: ON
9109 19:15:51.934946 TEMP_SENSOR: ON
9110 19:15:51.937826 HW_SAVE_FOR_SR: OFF
9111 19:15:51.941665 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9112 19:15:51.944504 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9113 19:15:51.944621 Read ODT Tracking: ON
9114 19:15:51.948357 Refresh Rate DeBounce: ON
9115 19:15:51.951273 DFS_NO_QUEUE_FLUSH: ON
9116 19:15:51.954757 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9117 19:15:51.954873 ENABLE_DFS_RUNTIME_MRW: OFF
9118 19:15:51.958359 DDR_RESERVE_NEW_MODE: ON
9119 19:15:51.961169 MR_CBT_SWITCH_FREQ: ON
9120 19:15:51.961282 =========================
9121 19:15:51.981838 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9122 19:15:51.985059 dram_init: ddr_geometry: 2
9123 19:15:52.002924 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9124 19:15:52.006468 dram_init: dram init end (result: 0)
9125 19:15:52.013186 DRAM-K: Full calibration passed in 24426 msecs
9126 19:15:52.016734 MRC: failed to locate region type 0.
9127 19:15:52.016823 DRAM rank0 size:0x100000000,
9128 19:15:52.019680 DRAM rank1 size=0x100000000
9129 19:15:52.030048 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9130 19:15:52.036744 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9131 19:15:52.043626 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9132 19:15:52.049437 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9133 19:15:52.053188 DRAM rank0 size:0x100000000,
9134 19:15:52.056070 DRAM rank1 size=0x100000000
9135 19:15:52.056178 CBMEM:
9136 19:15:52.059761 IMD: root @ 0xfffff000 254 entries.
9137 19:15:52.062844 IMD: root @ 0xffffec00 62 entries.
9138 19:15:52.066516 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9139 19:15:52.069462 WARNING: RO_VPD is uninitialized or empty.
9140 19:15:52.076129 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9141 19:15:52.083667 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9142 19:15:52.095792 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9143 19:15:52.107312 BS: romstage times (exec / console): total (unknown) / 23965 ms
9144 19:15:52.107438
9145 19:15:52.107552
9146 19:15:52.117463 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9147 19:15:52.121044 ARM64: Exception handlers installed.
9148 19:15:52.123773 ARM64: Testing exception
9149 19:15:52.126998 ARM64: Done test exception
9150 19:15:52.127116 Enumerating buses...
9151 19:15:52.130666 Show all devs... Before device enumeration.
9152 19:15:52.133664 Root Device: enabled 1
9153 19:15:52.137240 CPU_CLUSTER: 0: enabled 1
9154 19:15:52.137325 CPU: 00: enabled 1
9155 19:15:52.140181 Compare with tree...
9156 19:15:52.140293 Root Device: enabled 1
9157 19:15:52.143480 CPU_CLUSTER: 0: enabled 1
9158 19:15:52.146847 CPU: 00: enabled 1
9159 19:15:52.146972 Root Device scanning...
9160 19:15:52.150087 scan_static_bus for Root Device
9161 19:15:52.153325 CPU_CLUSTER: 0 enabled
9162 19:15:52.156704 scan_static_bus for Root Device done
9163 19:15:52.160217 scan_bus: bus Root Device finished in 8 msecs
9164 19:15:52.160349 done
9165 19:15:52.166435 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9166 19:15:52.170099 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9167 19:15:52.176701 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9168 19:15:52.179640 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9169 19:15:52.183337 Allocating resources...
9170 19:15:52.186225 Reading resources...
9171 19:15:52.190019 Root Device read_resources bus 0 link: 0
9172 19:15:52.193013 DRAM rank0 size:0x100000000,
9173 19:15:52.193129 DRAM rank1 size=0x100000000
9174 19:15:52.196898 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9175 19:15:52.199768 CPU: 00 missing read_resources
9176 19:15:52.206496 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9177 19:15:52.209813 Root Device read_resources bus 0 link: 0 done
9178 19:15:52.209934 Done reading resources.
9179 19:15:52.216293 Show resources in subtree (Root Device)...After reading.
9180 19:15:52.220020 Root Device child on link 0 CPU_CLUSTER: 0
9181 19:15:52.222963 CPU_CLUSTER: 0 child on link 0 CPU: 00
9182 19:15:52.232844 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9183 19:15:52.232934 CPU: 00
9184 19:15:52.236579 Root Device assign_resources, bus 0 link: 0
9185 19:15:52.239506 CPU_CLUSTER: 0 missing set_resources
9186 19:15:52.246178 Root Device assign_resources, bus 0 link: 0 done
9187 19:15:52.246295 Done setting resources.
9188 19:15:52.253287 Show resources in subtree (Root Device)...After assigning values.
9189 19:15:52.256361 Root Device child on link 0 CPU_CLUSTER: 0
9190 19:15:52.259785 CPU_CLUSTER: 0 child on link 0 CPU: 00
9191 19:15:52.269936 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9192 19:15:52.270058 CPU: 00
9193 19:15:52.273217 Done allocating resources.
9194 19:15:52.279278 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9195 19:15:52.279394 Enabling resources...
9196 19:15:52.279488 done.
9197 19:15:52.286153 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9198 19:15:52.286258 Initializing devices...
9199 19:15:52.289259 Root Device init
9200 19:15:52.289372 init hardware done!
9201 19:15:52.292720 0x00000018: ctrlr->caps
9202 19:15:52.296178 52.000 MHz: ctrlr->f_max
9203 19:15:52.296291 0.400 MHz: ctrlr->f_min
9204 19:15:52.299304 0x40ff8080: ctrlr->voltages
9205 19:15:52.303042 sclk: 390625
9206 19:15:52.303128 Bus Width = 1
9207 19:15:52.303192 sclk: 390625
9208 19:15:52.306618 Bus Width = 1
9209 19:15:52.306721 Early init status = 3
9210 19:15:52.312972 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9211 19:15:52.316433 in-header: 03 fc 00 00 01 00 00 00
9212 19:15:52.316523 in-data: 00
9213 19:15:52.322598 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9214 19:15:52.326310 in-header: 03 fd 00 00 00 00 00 00
9215 19:15:52.329246 in-data:
9216 19:15:52.333018 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9217 19:15:52.335949 in-header: 03 fc 00 00 01 00 00 00
9218 19:15:52.339865 in-data: 00
9219 19:15:52.342816 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9220 19:15:52.347286 in-header: 03 fd 00 00 00 00 00 00
9221 19:15:52.351000 in-data:
9222 19:15:52.353968 [SSUSB] Setting up USB HOST controller...
9223 19:15:52.357526 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9224 19:15:52.360373 [SSUSB] phy power-on done.
9225 19:15:52.364210 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9226 19:15:52.370759 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9227 19:15:52.373867 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9228 19:15:52.380544 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9229 19:15:52.387237 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9230 19:15:52.393726 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9231 19:15:52.400684 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9232 19:15:52.407193 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9233 19:15:52.410474 SPM: binary array size = 0x9dc
9234 19:15:52.413774 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9235 19:15:52.420723 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9236 19:15:52.427239 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9237 19:15:52.430401 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9238 19:15:52.433716 configure_display: Starting display init
9239 19:15:52.470419 anx7625_power_on_init: Init interface.
9240 19:15:52.474036 anx7625_disable_pd_protocol: Disabled PD feature.
9241 19:15:52.476904 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9242 19:15:52.505196 anx7625_start_dp_work: Secure OCM version=00
9243 19:15:52.508100 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9244 19:15:52.523300 sp_tx_get_edid_block: EDID Block = 1
9245 19:15:52.625999 Extracted contents:
9246 19:15:52.628946 header: 00 ff ff ff ff ff ff 00
9247 19:15:52.631838 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9248 19:15:52.635636 version: 01 04
9249 19:15:52.638492 basic params: 95 1f 11 78 0a
9250 19:15:52.642208 chroma info: 76 90 94 55 54 90 27 21 50 54
9251 19:15:52.645119 established: 00 00 00
9252 19:15:52.652305 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9253 19:15:52.655365 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9254 19:15:52.662045 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9255 19:15:52.668781 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9256 19:15:52.675458 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9257 19:15:52.678797 extensions: 00
9258 19:15:52.678887 checksum: fb
9259 19:15:52.678980
9260 19:15:52.681503 Manufacturer: IVO Model 57d Serial Number 0
9261 19:15:52.685155 Made week 0 of 2020
9262 19:15:52.688247 EDID version: 1.4
9263 19:15:52.688380 Digital display
9264 19:15:52.691725 6 bits per primary color channel
9265 19:15:52.691810 DisplayPort interface
9266 19:15:52.695078 Maximum image size: 31 cm x 17 cm
9267 19:15:52.698570 Gamma: 220%
9268 19:15:52.698675 Check DPMS levels
9269 19:15:52.701736 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9270 19:15:52.708510 First detailed timing is preferred timing
9271 19:15:52.708596 Established timings supported:
9272 19:15:52.711985 Standard timings supported:
9273 19:15:52.715038 Detailed timings
9274 19:15:52.718478 Hex of detail: 383680a07038204018303c0035ae10000019
9275 19:15:52.721297 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9276 19:15:52.728656 0780 0798 07c8 0820 hborder 0
9277 19:15:52.731359 0438 043b 0447 0458 vborder 0
9278 19:15:52.734977 -hsync -vsync
9279 19:15:52.735105 Did detailed timing
9280 19:15:52.741870 Hex of detail: 000000000000000000000000000000000000
9281 19:15:52.741960 Manufacturer-specified data, tag 0
9282 19:15:52.747871 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9283 19:15:52.751718 ASCII string: InfoVision
9284 19:15:52.754541 Hex of detail: 000000fe00523134304e574635205248200a
9285 19:15:52.758214 ASCII string: R140NWF5 RH
9286 19:15:52.758298 Checksum
9287 19:15:52.761244 Checksum: 0xfb (valid)
9288 19:15:52.764821 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9289 19:15:52.767878 DSI data_rate: 832800000 bps
9290 19:15:52.774706 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9291 19:15:52.777604 anx7625_parse_edid: pixelclock(138800).
9292 19:15:52.781407 hactive(1920), hsync(48), hfp(24), hbp(88)
9293 19:15:52.784253 vactive(1080), vsync(12), vfp(3), vbp(17)
9294 19:15:52.787903 anx7625_dsi_config: config dsi.
9295 19:15:52.794759 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9296 19:15:52.807923 anx7625_dsi_config: success to config DSI
9297 19:15:52.810845 anx7625_dp_start: MIPI phy setup OK.
9298 19:15:52.814055 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9299 19:15:52.818099 mtk_ddp_mode_set invalid vrefresh 60
9300 19:15:52.820845 main_disp_path_setup
9301 19:15:52.820950 ovl_layer_smi_id_en
9302 19:15:52.824215 ovl_layer_smi_id_en
9303 19:15:52.824320 ccorr_config
9304 19:15:52.824428 aal_config
9305 19:15:52.827418 gamma_config
9306 19:15:52.827521 postmask_config
9307 19:15:52.831232 dither_config
9308 19:15:52.834237 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9309 19:15:52.841241 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9310 19:15:52.844814 Root Device init finished in 551 msecs
9311 19:15:52.844898 CPU_CLUSTER: 0 init
9312 19:15:52.854936 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9313 19:15:52.857537 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9314 19:15:52.861357 APU_MBOX 0x190000b0 = 0x10001
9315 19:15:52.864202 APU_MBOX 0x190001b0 = 0x10001
9316 19:15:52.867760 APU_MBOX 0x190005b0 = 0x10001
9317 19:15:52.870644 APU_MBOX 0x190006b0 = 0x10001
9318 19:15:52.874333 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9319 19:15:52.886922 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9320 19:15:52.898955 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9321 19:15:52.905712 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9322 19:15:52.917020 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9323 19:15:52.926359 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9324 19:15:52.930098 CPU_CLUSTER: 0 init finished in 81 msecs
9325 19:15:52.933050 Devices initialized
9326 19:15:52.936766 Show all devs... After init.
9327 19:15:52.936885 Root Device: enabled 1
9328 19:15:52.939808 CPU_CLUSTER: 0: enabled 1
9329 19:15:52.943264 CPU: 00: enabled 1
9330 19:15:52.946138 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9331 19:15:52.949599 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9332 19:15:52.953139 ELOG: NV offset 0x57f000 size 0x1000
9333 19:15:52.960026 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9334 19:15:52.966545 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9335 19:15:52.969642 ELOG: Event(17) added with size 13 at 2024-05-18 19:11:13 UTC
9336 19:15:52.975832 out: cmd=0x121: 03 db 21 01 00 00 00 00
9337 19:15:52.979394 in-header: 03 00 00 00 2c 00 00 00
9338 19:15:52.989167 in-data: 5f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9339 19:15:52.995734 ELOG: Event(A1) added with size 10 at 2024-05-18 19:11:13 UTC
9340 19:15:53.002479 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9341 19:15:53.009297 ELOG: Event(A0) added with size 9 at 2024-05-18 19:11:13 UTC
9342 19:15:53.012378 elog_add_boot_reason: Logged dev mode boot
9343 19:15:53.019075 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9344 19:15:53.019204 Finalize devices...
9345 19:15:53.022021 Devices finalized
9346 19:15:53.025495 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9347 19:15:53.028883 Writing coreboot table at 0xffe64000
9348 19:15:53.032399 0. 000000000010a000-0000000000113fff: RAMSTAGE
9349 19:15:53.035985 1. 0000000040000000-00000000400fffff: RAM
9350 19:15:53.042526 2. 0000000040100000-000000004032afff: RAMSTAGE
9351 19:15:53.045473 3. 000000004032b000-00000000545fffff: RAM
9352 19:15:53.049108 4. 0000000054600000-000000005465ffff: BL31
9353 19:15:53.052503 5. 0000000054660000-00000000ffe63fff: RAM
9354 19:15:53.058976 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9355 19:15:53.062062 7. 0000000100000000-000000023fffffff: RAM
9356 19:15:53.065719 Passing 5 GPIOs to payload:
9357 19:15:53.068545 NAME | PORT | POLARITY | VALUE
9358 19:15:53.072096 EC in RW | 0x000000aa | low | undefined
9359 19:15:53.078499 EC interrupt | 0x00000005 | low | undefined
9360 19:15:53.082268 TPM interrupt | 0x000000ab | high | undefined
9361 19:15:53.088863 SD card detect | 0x00000011 | high | undefined
9362 19:15:53.091736 speaker enable | 0x00000093 | high | undefined
9363 19:15:53.095081 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9364 19:15:53.098930 in-header: 03 f9 00 00 02 00 00 00
9365 19:15:53.101925 in-data: 02 00
9366 19:15:53.102043 ADC[4]: Raw value=904357 ID=7
9367 19:15:53.105130 ADC[3]: Raw value=213441 ID=1
9368 19:15:53.108415 RAM Code: 0x71
9369 19:15:53.108531 ADC[6]: Raw value=75332 ID=0
9370 19:15:53.111704 ADC[5]: Raw value=212703 ID=1
9371 19:15:53.115287 SKU Code: 0x1
9372 19:15:53.118256 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2627
9373 19:15:53.122012 coreboot table: 964 bytes.
9374 19:15:53.125561 IMD ROOT 0. 0xfffff000 0x00001000
9375 19:15:53.128573 IMD SMALL 1. 0xffffe000 0x00001000
9376 19:15:53.132132 RO MCACHE 2. 0xffffc000 0x00001104
9377 19:15:53.135639 CONSOLE 3. 0xfff7c000 0x00080000
9378 19:15:53.138785 FMAP 4. 0xfff7b000 0x00000452
9379 19:15:53.142326 TIME STAMP 5. 0xfff7a000 0x00000910
9380 19:15:53.145296 VBOOT WORK 6. 0xfff66000 0x00014000
9381 19:15:53.148425 RAMOOPS 7. 0xffe66000 0x00100000
9382 19:15:53.152417 COREBOOT 8. 0xffe64000 0x00002000
9383 19:15:53.152511 IMD small region:
9384 19:15:53.158261 IMD ROOT 0. 0xffffec00 0x00000400
9385 19:15:53.161465 VPD 1. 0xffffeb80 0x0000006c
9386 19:15:53.164712 MMC STATUS 2. 0xffffeb60 0x00000004
9387 19:15:53.168290 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9388 19:15:53.171989 Probing TPM: done!
9389 19:15:53.174834 Connected to device vid:did:rid of 1ae0:0028:00
9390 19:15:53.185557 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9391 19:15:53.188500 Initialized TPM device CR50 revision 0
9392 19:15:53.192162 Checking cr50 for pending updates
9393 19:15:53.195823 Reading cr50 TPM mode
9394 19:15:53.204581 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9395 19:15:53.211290 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9396 19:15:53.251324 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9397 19:15:53.254586 Checking segment from ROM address 0x40100000
9398 19:15:53.258180 Checking segment from ROM address 0x4010001c
9399 19:15:53.265031 Loading segment from ROM address 0x40100000
9400 19:15:53.265261 code (compression=0)
9401 19:15:53.274482 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9402 19:15:53.281382 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9403 19:15:53.281596 it's not compressed!
9404 19:15:53.288261 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9405 19:15:53.291235 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9406 19:15:53.311762 Loading segment from ROM address 0x4010001c
9407 19:15:53.311859 Entry Point 0x80000000
9408 19:15:53.315133 Loaded segments
9409 19:15:53.318596 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9410 19:15:53.325243 Jumping to boot code at 0x80000000(0xffe64000)
9411 19:15:53.332021 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9412 19:15:53.338551 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9413 19:15:53.346373 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9414 19:15:53.349314 Checking segment from ROM address 0x40100000
9415 19:15:53.352931 Checking segment from ROM address 0x4010001c
9416 19:15:53.359510 Loading segment from ROM address 0x40100000
9417 19:15:53.359624 code (compression=1)
9418 19:15:53.366605 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9419 19:15:53.376483 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9420 19:15:53.376588 using LZMA
9421 19:15:53.384738 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9422 19:15:53.391257 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9423 19:15:53.394970 Loading segment from ROM address 0x4010001c
9424 19:15:53.395059 Entry Point 0x54601000
9425 19:15:53.398058 Loaded segments
9426 19:15:53.401177 NOTICE: MT8192 bl31_setup
9427 19:15:53.408373 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9428 19:15:53.411352 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9429 19:15:53.414953 WARNING: region 0:
9430 19:15:53.417957 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9431 19:15:53.418047 WARNING: region 1:
9432 19:15:53.425056 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9433 19:15:53.428768 WARNING: region 2:
9434 19:15:53.431506 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9435 19:15:53.435287 WARNING: region 3:
9436 19:15:53.438231 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9437 19:15:53.441877 WARNING: region 4:
9438 19:15:53.448423 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9439 19:15:53.448545 WARNING: region 5:
9440 19:15:53.451542 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9441 19:15:53.455285 WARNING: region 6:
9442 19:15:53.458112 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9443 19:15:53.458226 WARNING: region 7:
9444 19:15:53.464727 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9445 19:15:53.472084 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9446 19:15:53.474964 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9447 19:15:53.478656 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9448 19:15:53.485210 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9449 19:15:53.488002 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9450 19:15:53.491429 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9451 19:15:53.498184 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9452 19:15:53.501452 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9453 19:15:53.508416 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9454 19:15:53.511646 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9455 19:15:53.514871 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9456 19:15:53.521475 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9457 19:15:53.524811 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9458 19:15:53.528166 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9459 19:15:53.534678 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9460 19:15:53.538575 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9461 19:15:53.541490 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9462 19:15:53.548779 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9463 19:15:53.551824 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9464 19:15:53.558255 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9465 19:15:53.561966 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9466 19:15:53.564903 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9467 19:15:53.571560 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9468 19:15:53.575342 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9469 19:15:53.581992 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9470 19:15:53.584834 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9471 19:15:53.588481 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9472 19:15:53.595068 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9473 19:15:53.598547 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9474 19:15:53.602217 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9475 19:15:53.608607 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9476 19:15:53.612078 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9477 19:15:53.615068 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9478 19:15:53.622377 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9479 19:15:53.625276 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9480 19:15:53.628884 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9481 19:15:53.631749 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9482 19:15:53.638417 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9483 19:15:53.641864 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9484 19:15:53.645091 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9485 19:15:53.648710 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9486 19:15:53.655338 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9487 19:15:53.658557 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9488 19:15:53.662026 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9489 19:15:53.665470 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9490 19:15:53.672011 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9491 19:15:53.675563 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9492 19:15:53.678692 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9493 19:15:53.685314 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9494 19:15:53.688945 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9495 19:15:53.692481 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9496 19:15:53.698970 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9497 19:15:53.702000 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9498 19:15:53.708989 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9499 19:15:53.711983 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9500 19:15:53.715519 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9501 19:15:53.721993 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9502 19:15:53.725623 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9503 19:15:53.732434 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9504 19:15:53.736041 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9505 19:15:53.742115 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9506 19:15:53.745644 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9507 19:15:53.752331 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9508 19:15:53.756065 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9509 19:15:53.759022 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9510 19:15:53.766038 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9511 19:15:53.769570 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9512 19:15:53.775674 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9513 19:15:53.778803 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9514 19:15:53.785772 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9515 19:15:53.788771 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9516 19:15:53.792424 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9517 19:15:53.798967 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9518 19:15:53.802371 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9519 19:15:53.809054 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9520 19:15:53.812581 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9521 19:15:53.819170 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9522 19:15:53.822512 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9523 19:15:53.825883 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9524 19:15:53.832368 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9525 19:15:53.835988 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9526 19:15:53.842744 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9527 19:15:53.845648 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9528 19:15:53.852150 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9529 19:15:53.855898 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9530 19:15:53.858826 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9531 19:15:53.865389 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9532 19:15:53.869110 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9533 19:15:53.875624 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9534 19:15:53.879336 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9535 19:15:53.885815 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9536 19:15:53.889545 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9537 19:15:53.892428 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9538 19:15:53.898757 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9539 19:15:53.902395 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9540 19:15:53.908743 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9541 19:15:53.912114 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9542 19:15:53.915506 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9543 19:15:53.919017 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9544 19:15:53.925516 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9545 19:15:53.928707 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9546 19:15:53.932290 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9547 19:15:53.938877 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9548 19:15:53.942539 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9549 19:15:53.948714 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9550 19:15:53.952254 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9551 19:15:53.955916 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9552 19:15:53.962719 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9553 19:15:53.965627 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9554 19:15:53.972209 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9555 19:15:53.975829 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9556 19:15:53.978756 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9557 19:15:53.985318 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9558 19:15:53.989161 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9559 19:15:53.995570 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9560 19:15:53.999365 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9561 19:15:54.002216 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9562 19:15:54.008793 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9563 19:15:54.012395 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9564 19:15:54.015726 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9565 19:15:54.018708 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9566 19:15:54.022362 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9567 19:15:54.029074 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9568 19:15:54.032111 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9569 19:15:54.035565 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9570 19:15:54.042722 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9571 19:15:54.045438 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9572 19:15:54.052807 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9573 19:15:54.055998 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9574 19:15:54.059082 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9575 19:15:54.065761 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9576 19:15:54.069176 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9577 19:15:54.072739 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9578 19:15:54.079454 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9579 19:15:54.082417 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9580 19:15:54.089379 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9581 19:15:54.092996 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9582 19:15:54.095871 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9583 19:15:54.102678 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9584 19:15:54.106288 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9585 19:15:54.109280 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9586 19:15:54.115832 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9587 19:15:54.119544 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9588 19:15:54.126067 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9589 19:15:54.129079 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9590 19:15:54.132749 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9591 19:15:54.139455 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9592 19:15:54.143045 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9593 19:15:54.149503 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9594 19:15:54.153028 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9595 19:15:54.156456 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9596 19:15:54.163232 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9597 19:15:54.165997 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9598 19:15:54.169742 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9599 19:15:54.175946 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9600 19:15:54.179251 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9601 19:15:54.186114 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9602 19:15:54.189136 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9603 19:15:54.192645 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9604 19:15:54.199236 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9605 19:15:54.202955 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9606 19:15:54.209362 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9607 19:15:54.212336 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9608 19:15:54.215909 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9609 19:15:54.222352 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9610 19:15:54.226002 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9611 19:15:54.232768 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9612 19:15:54.235639 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9613 19:15:54.239316 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9614 19:15:54.246044 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9615 19:15:54.249088 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9616 19:15:54.255592 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9617 19:15:54.259036 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9618 19:15:54.262474 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9619 19:15:54.268744 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9620 19:15:54.272462 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9621 19:15:54.275331 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9622 19:15:54.281897 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9623 19:15:54.285591 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9624 19:15:54.292154 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9625 19:15:54.295575 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9626 19:15:54.299005 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9627 19:15:54.305375 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9628 19:15:54.308612 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9629 19:15:54.315039 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9630 19:15:54.318739 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9631 19:15:54.321939 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9632 19:15:54.328416 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9633 19:15:54.332016 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9634 19:15:54.338626 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9635 19:15:54.341833 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9636 19:15:54.348310 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9637 19:15:54.351969 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9638 19:15:54.355094 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9639 19:15:54.362070 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9640 19:15:54.364903 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9641 19:15:54.372103 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9642 19:15:54.374932 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9643 19:15:54.378605 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9644 19:15:54.385463 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9645 19:15:54.388606 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9646 19:15:54.395396 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9647 19:15:54.398372 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9648 19:15:54.401467 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9649 19:15:54.408131 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9650 19:15:54.411818 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9651 19:15:54.418349 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9652 19:15:54.421789 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9653 19:15:54.428187 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9654 19:15:54.431799 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9655 19:15:54.434840 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9656 19:15:54.441765 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9657 19:15:54.445158 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9658 19:15:54.451061 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9659 19:15:54.454959 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9660 19:15:54.458210 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9661 19:15:54.465050 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9662 19:15:54.468605 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9663 19:15:54.475333 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9664 19:15:54.478372 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9665 19:15:54.481844 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9666 19:15:54.487879 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9667 19:15:54.491590 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9668 19:15:54.498293 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9669 19:15:54.501418 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9670 19:15:54.508130 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9671 19:15:54.511605 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9672 19:15:54.514547 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9673 19:15:54.521073 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9674 19:15:54.524664 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9675 19:15:54.528212 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9676 19:15:54.531518 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9677 19:15:54.537706 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9678 19:15:54.541481 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9679 19:15:54.545092 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9680 19:15:54.551287 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9681 19:15:54.555027 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9682 19:15:54.557982 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9683 19:15:54.564392 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9684 19:15:54.567844 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9685 19:15:54.574447 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9686 19:15:54.577756 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9687 19:15:54.580953 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9688 19:15:54.588185 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9689 19:15:54.590938 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9690 19:15:54.594485 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9691 19:15:54.601077 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9692 19:15:54.604793 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9693 19:15:54.607825 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9694 19:15:54.614552 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9695 19:15:54.617415 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9696 19:15:54.624017 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9697 19:15:54.627814 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9698 19:15:54.631259 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9699 19:15:54.637697 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9700 19:15:54.640958 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9701 19:15:54.644385 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9702 19:15:54.650763 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9703 19:15:54.653796 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9704 19:15:54.657361 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9705 19:15:54.663830 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9706 19:15:54.667488 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9707 19:15:54.674039 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9708 19:15:54.677051 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9709 19:15:54.680861 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9710 19:15:54.687353 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9711 19:15:54.690884 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9712 19:15:54.693584 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9713 19:15:54.700762 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9714 19:15:54.703789 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9715 19:15:54.706833 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9716 19:15:54.710785 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9717 19:15:54.717248 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9718 19:15:54.720063 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9719 19:15:54.723577 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9720 19:15:54.727242 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9721 19:15:54.733703 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9722 19:15:54.736617 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9723 19:15:54.740337 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9724 19:15:54.743269 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9725 19:15:54.750299 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9726 19:15:54.753625 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9727 19:15:54.756447 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9728 19:15:54.763005 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9729 19:15:54.766541 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9730 19:15:54.772945 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9731 19:15:54.776511 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9732 19:15:54.783153 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9733 19:15:54.786632 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9734 19:15:54.789657 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9735 19:15:54.796174 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9736 19:15:54.799914 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9737 19:15:54.806503 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9738 19:15:54.809392 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9739 19:15:54.812896 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9740 19:15:54.819360 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9741 19:15:54.823237 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9742 19:15:54.829438 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9743 19:15:54.833003 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9744 19:15:54.835972 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9745 19:15:54.842846 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9746 19:15:54.846388 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9747 19:15:54.853020 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9748 19:15:54.856635 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9749 19:15:54.862941 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9750 19:15:54.866479 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9751 19:15:54.869357 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9752 19:15:54.875854 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9753 19:15:54.879243 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9754 19:15:54.882798 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9755 19:15:54.889421 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9756 19:15:54.893202 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9757 19:15:54.899870 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9758 19:15:54.902768 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9759 19:15:54.906553 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9760 19:15:54.913076 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9761 19:15:54.916029 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9762 19:15:54.922783 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9763 19:15:54.926455 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9764 19:15:54.932939 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9765 19:15:54.936502 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9766 19:15:54.939313 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9767 19:15:54.946295 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9768 19:15:54.949498 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9769 19:15:54.956098 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9770 19:15:54.959344 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9771 19:15:54.962704 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9772 19:15:54.968998 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9773 19:15:54.972238 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9774 19:15:54.979159 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9775 19:15:54.982795 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9776 19:15:54.986237 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9777 19:15:54.992512 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9778 19:15:54.996071 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9779 19:15:55.002479 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9780 19:15:55.006222 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9781 19:15:55.009964 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9782 19:15:55.015870 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9783 19:15:55.019537 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9784 19:15:55.026247 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9785 19:15:55.029362 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9786 19:15:55.033015 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9787 19:15:55.039358 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9788 19:15:55.043079 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9789 19:15:55.049750 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9790 19:15:55.052735 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9791 19:15:55.056385 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9792 19:15:55.062272 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9793 19:15:55.065802 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9794 19:15:55.072291 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9795 19:15:55.075844 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9796 19:15:55.082274 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9797 19:15:55.085615 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9798 19:15:55.089316 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9799 19:15:55.096120 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9800 19:15:55.098945 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9801 19:15:55.105742 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9802 19:15:55.109228 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9803 19:15:55.115509 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9804 19:15:55.119076 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9805 19:15:55.122311 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9806 19:15:55.128879 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9807 19:15:55.132411 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9808 19:15:55.139368 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9809 19:15:55.142296 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9810 19:15:55.149017 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9811 19:15:55.151937 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9812 19:15:55.155843 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9813 19:15:55.162347 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9814 19:15:55.165192 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9815 19:15:55.172004 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9816 19:15:55.175937 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9817 19:15:55.178756 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9818 19:15:55.185306 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9819 19:15:55.188850 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9820 19:15:55.195812 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9821 19:15:55.199006 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9822 19:15:55.205354 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9823 19:15:55.208825 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9824 19:15:55.215404 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9825 19:15:55.218828 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9826 19:15:55.222463 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9827 19:15:55.228547 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9828 19:15:55.231905 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9829 19:15:55.238315 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9830 19:15:55.241945 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9831 19:15:55.248785 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9832 19:15:55.252027 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9833 19:15:55.255378 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9834 19:15:55.261987 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9835 19:15:55.265701 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9836 19:15:55.272246 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9837 19:15:55.275319 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9838 19:15:55.282020 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9839 19:15:55.285574 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9840 19:15:55.288525 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9841 19:15:55.295198 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9842 19:15:55.298884 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9843 19:15:55.304928 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9844 19:15:55.308189 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9845 19:15:55.314737 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9846 19:15:55.318592 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9847 19:15:55.322118 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9848 19:15:55.328264 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9849 19:15:55.331802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9850 19:15:55.338508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9851 19:15:55.341544 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9852 19:15:55.348689 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9853 19:15:55.352225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9854 19:15:55.358268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9855 19:15:55.361979 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9856 19:15:55.364937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9857 19:15:55.371929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9858 19:15:55.375060 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9859 19:15:55.381600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9860 19:15:55.384901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9861 19:15:55.391535 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9862 19:15:55.395207 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9863 19:15:55.401742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9864 19:15:55.405493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9865 19:15:55.412068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9866 19:15:55.414897 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9867 19:15:55.421355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9868 19:15:55.424792 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9869 19:15:55.431542 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9870 19:15:55.434924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9871 19:15:55.441992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9872 19:15:55.444903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9873 19:15:55.451585 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9874 19:15:55.454560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9875 19:15:55.461306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9876 19:15:55.465184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9877 19:15:55.471854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9878 19:15:55.474769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9879 19:15:55.481610 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9880 19:15:55.481722 INFO: [APUAPC] vio 0
9881 19:15:55.488039 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9882 19:15:55.491260 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9883 19:15:55.494578 INFO: [APUAPC] D0_APC_0: 0x400510
9884 19:15:55.497734 INFO: [APUAPC] D0_APC_1: 0x0
9885 19:15:55.501417 INFO: [APUAPC] D0_APC_2: 0x1540
9886 19:15:55.504770 INFO: [APUAPC] D0_APC_3: 0x0
9887 19:15:55.507668 INFO: [APUAPC] D1_APC_0: 0xffffffff
9888 19:15:55.511592 INFO: [APUAPC] D1_APC_1: 0xffffffff
9889 19:15:55.514344 INFO: [APUAPC] D1_APC_2: 0x3fffff
9890 19:15:55.517825 INFO: [APUAPC] D1_APC_3: 0x0
9891 19:15:55.521089 INFO: [APUAPC] D2_APC_0: 0xffffffff
9892 19:15:55.524641 INFO: [APUAPC] D2_APC_1: 0xffffffff
9893 19:15:55.527502 INFO: [APUAPC] D2_APC_2: 0x3fffff
9894 19:15:55.531090 INFO: [APUAPC] D2_APC_3: 0x0
9895 19:15:55.534796 INFO: [APUAPC] D3_APC_0: 0xffffffff
9896 19:15:55.537467 INFO: [APUAPC] D3_APC_1: 0xffffffff
9897 19:15:55.540897 INFO: [APUAPC] D3_APC_2: 0x3fffff
9898 19:15:55.544150 INFO: [APUAPC] D3_APC_3: 0x0
9899 19:15:55.547511 INFO: [APUAPC] D4_APC_0: 0xffffffff
9900 19:15:55.551143 INFO: [APUAPC] D4_APC_1: 0xffffffff
9901 19:15:55.554025 INFO: [APUAPC] D4_APC_2: 0x3fffff
9902 19:15:55.554130 INFO: [APUAPC] D4_APC_3: 0x0
9903 19:15:55.560826 INFO: [APUAPC] D5_APC_0: 0xffffffff
9904 19:15:55.564374 INFO: [APUAPC] D5_APC_1: 0xffffffff
9905 19:15:55.567439 INFO: [APUAPC] D5_APC_2: 0x3fffff
9906 19:15:55.567517 INFO: [APUAPC] D5_APC_3: 0x0
9907 19:15:55.571100 INFO: [APUAPC] D6_APC_0: 0xffffffff
9908 19:15:55.574150 INFO: [APUAPC] D6_APC_1: 0xffffffff
9909 19:15:55.577741 INFO: [APUAPC] D6_APC_2: 0x3fffff
9910 19:15:55.580549 INFO: [APUAPC] D6_APC_3: 0x0
9911 19:15:55.584132 INFO: [APUAPC] D7_APC_0: 0xffffffff
9912 19:15:55.587812 INFO: [APUAPC] D7_APC_1: 0xffffffff
9913 19:15:55.590618 INFO: [APUAPC] D7_APC_2: 0x3fffff
9914 19:15:55.594089 INFO: [APUAPC] D7_APC_3: 0x0
9915 19:15:55.597587 INFO: [APUAPC] D8_APC_0: 0xffffffff
9916 19:15:55.600530 INFO: [APUAPC] D8_APC_1: 0xffffffff
9917 19:15:55.604259 INFO: [APUAPC] D8_APC_2: 0x3fffff
9918 19:15:55.607147 INFO: [APUAPC] D8_APC_3: 0x0
9919 19:15:55.610764 INFO: [APUAPC] D9_APC_0: 0xffffffff
9920 19:15:55.614208 INFO: [APUAPC] D9_APC_1: 0xffffffff
9921 19:15:55.617595 INFO: [APUAPC] D9_APC_2: 0x3fffff
9922 19:15:55.620765 INFO: [APUAPC] D9_APC_3: 0x0
9923 19:15:55.623920 INFO: [APUAPC] D10_APC_0: 0xffffffff
9924 19:15:55.627163 INFO: [APUAPC] D10_APC_1: 0xffffffff
9925 19:15:55.630981 INFO: [APUAPC] D10_APC_2: 0x3fffff
9926 19:15:55.634188 INFO: [APUAPC] D10_APC_3: 0x0
9927 19:15:55.637346 INFO: [APUAPC] D11_APC_0: 0xffffffff
9928 19:15:55.640850 INFO: [APUAPC] D11_APC_1: 0xffffffff
9929 19:15:55.643707 INFO: [APUAPC] D11_APC_2: 0x3fffff
9930 19:15:55.647077 INFO: [APUAPC] D11_APC_3: 0x0
9931 19:15:55.650579 INFO: [APUAPC] D12_APC_0: 0xffffffff
9932 19:15:55.653707 INFO: [APUAPC] D12_APC_1: 0xffffffff
9933 19:15:55.657132 INFO: [APUAPC] D12_APC_2: 0x3fffff
9934 19:15:55.660473 INFO: [APUAPC] D12_APC_3: 0x0
9935 19:15:55.663765 INFO: [APUAPC] D13_APC_0: 0xffffffff
9936 19:15:55.666968 INFO: [APUAPC] D13_APC_1: 0xffffffff
9937 19:15:55.670521 INFO: [APUAPC] D13_APC_2: 0x3fffff
9938 19:15:55.674159 INFO: [APUAPC] D13_APC_3: 0x0
9939 19:15:55.677085 INFO: [APUAPC] D14_APC_0: 0xffffffff
9940 19:15:55.680836 INFO: [APUAPC] D14_APC_1: 0xffffffff
9941 19:15:55.683631 INFO: [APUAPC] D14_APC_2: 0x3fffff
9942 19:15:55.687223 INFO: [APUAPC] D14_APC_3: 0x0
9943 19:15:55.690236 INFO: [APUAPC] D15_APC_0: 0xffffffff
9944 19:15:55.693906 INFO: [APUAPC] D15_APC_1: 0xffffffff
9945 19:15:55.697444 INFO: [APUAPC] D15_APC_2: 0x3fffff
9946 19:15:55.700337 INFO: [APUAPC] D15_APC_3: 0x0
9947 19:15:55.703644 INFO: [APUAPC] APC_CON: 0x4
9948 19:15:55.707260 INFO: [NOCDAPC] D0_APC_0: 0x0
9949 19:15:55.710223 INFO: [NOCDAPC] D0_APC_1: 0x0
9950 19:15:55.714038 INFO: [NOCDAPC] D1_APC_0: 0x0
9951 19:15:55.717109 INFO: [NOCDAPC] D1_APC_1: 0xfff
9952 19:15:55.717209 INFO: [NOCDAPC] D2_APC_0: 0x0
9953 19:15:55.720738 INFO: [NOCDAPC] D2_APC_1: 0xfff
9954 19:15:55.723650 INFO: [NOCDAPC] D3_APC_0: 0x0
9955 19:15:55.727269 INFO: [NOCDAPC] D3_APC_1: 0xfff
9956 19:15:55.730584 INFO: [NOCDAPC] D4_APC_0: 0x0
9957 19:15:55.733415 INFO: [NOCDAPC] D4_APC_1: 0xfff
9958 19:15:55.737064 INFO: [NOCDAPC] D5_APC_0: 0x0
9959 19:15:55.740609 INFO: [NOCDAPC] D5_APC_1: 0xfff
9960 19:15:55.743556 INFO: [NOCDAPC] D6_APC_0: 0x0
9961 19:15:55.747211 INFO: [NOCDAPC] D6_APC_1: 0xfff
9962 19:15:55.750183 INFO: [NOCDAPC] D7_APC_0: 0x0
9963 19:15:55.750294 INFO: [NOCDAPC] D7_APC_1: 0xfff
9964 19:15:55.753849 INFO: [NOCDAPC] D8_APC_0: 0x0
9965 19:15:55.757077 INFO: [NOCDAPC] D8_APC_1: 0xfff
9966 19:15:55.760391 INFO: [NOCDAPC] D9_APC_0: 0x0
9967 19:15:55.763428 INFO: [NOCDAPC] D9_APC_1: 0xfff
9968 19:15:55.767122 INFO: [NOCDAPC] D10_APC_0: 0x0
9969 19:15:55.770420 INFO: [NOCDAPC] D10_APC_1: 0xfff
9970 19:15:55.773306 INFO: [NOCDAPC] D11_APC_0: 0x0
9971 19:15:55.776966 INFO: [NOCDAPC] D11_APC_1: 0xfff
9972 19:15:55.780336 INFO: [NOCDAPC] D12_APC_0: 0x0
9973 19:15:55.783544 INFO: [NOCDAPC] D12_APC_1: 0xfff
9974 19:15:55.786853 INFO: [NOCDAPC] D13_APC_0: 0x0
9975 19:15:55.790163 INFO: [NOCDAPC] D13_APC_1: 0xfff
9976 19:15:55.790267 INFO: [NOCDAPC] D14_APC_0: 0x0
9977 19:15:55.793348 INFO: [NOCDAPC] D14_APC_1: 0xfff
9978 19:15:55.796810 INFO: [NOCDAPC] D15_APC_0: 0x0
9979 19:15:55.800615 INFO: [NOCDAPC] D15_APC_1: 0xfff
9980 19:15:55.803358 INFO: [NOCDAPC] APC_CON: 0x4
9981 19:15:55.806886 INFO: [APUAPC] set_apusys_apc done
9982 19:15:55.810427 INFO: [DEVAPC] devapc_init done
9983 19:15:55.813356 INFO: GICv3 without legacy support detected.
9984 19:15:55.819868 INFO: ARM GICv3 driver initialized in EL3
9985 19:15:55.823593 INFO: Maximum SPI INTID supported: 639
9986 19:15:55.826473 INFO: BL31: Initializing runtime services
9987 19:15:55.833734 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9988 19:15:55.833845 INFO: SPM: enable CPC mode
9989 19:15:55.840150 INFO: mcdi ready for mcusys-off-idle and system suspend
9990 19:15:55.843185 INFO: BL31: Preparing for EL3 exit to normal world
9991 19:15:55.850259 INFO: Entry point address = 0x80000000
9992 19:15:55.850413 INFO: SPSR = 0x8
9993 19:15:55.856088
9994 19:15:55.856231
9995 19:15:55.856331
9996 19:15:55.859770 Starting depthcharge on Spherion...
9997 19:15:55.859885
9998 19:15:55.859979 Wipe memory regions:
9999 19:15:55.860072
10000 19:15:55.860919 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10001 19:15:55.861022 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10002 19:15:55.861135 Setting prompt string to ['asurada:']
10003 19:15:55.861249 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10004 19:15:55.862613 [0x00000040000000, 0x00000054600000)
10005 19:15:55.985329
10006 19:15:55.985459 [0x00000054660000, 0x00000080000000)
10007 19:15:56.245539
10008 19:15:56.245704 [0x000000821a7280, 0x000000ffe64000)
10009 19:15:56.990364
10010 19:15:56.990496 [0x00000100000000, 0x00000240000000)
10011 19:15:58.881433
10012 19:15:58.884329 Initializing XHCI USB controller at 0x11200000.
10013 19:15:59.921979
10014 19:15:59.925529 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10015 19:15:59.925649
10016 19:15:59.925752
10017 19:15:59.926074 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10019 19:16:00.026465 asurada: tftpboot 192.168.201.1 13888633/tftp-deploy-lq2x80os/kernel/image.itb 13888633/tftp-deploy-lq2x80os/kernel/cmdline
10020 19:16:00.026621 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10021 19:16:00.026712 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10022 19:16:00.030513 tftpboot 192.168.201.1 13888633/tftp-deploy-lq2x80os/kernel/image.ittp-deploy-lq2x80os/kernel/cmdline
10023 19:16:00.030622
10024 19:16:00.030724 Waiting for link
10025 19:16:00.191590
10026 19:16:00.191726 R8152: Initializing
10027 19:16:00.191795
10028 19:16:00.194701 Version 9 (ocp_data = 6010)
10029 19:16:00.194815
10030 19:16:00.197716 R8152: Done initializing
10031 19:16:00.197800
10032 19:16:00.197881 Adding net device
10033 19:16:02.070512
10034 19:16:02.070676 done.
10035 19:16:02.070773
10036 19:16:02.070870 MAC: 00:e0:4c:78:7a:aa
10037 19:16:02.070962
10038 19:16:02.073715 Sending DHCP discover... done.
10039 19:16:02.073826
10040 19:16:02.077026 Waiting for reply... done.
10041 19:16:02.077130
10042 19:16:02.080270 Sending DHCP request... done.
10043 19:16:02.080353
10044 19:16:02.083417 Waiting for reply... done.
10045 19:16:02.083501
10046 19:16:02.083567 My ip is 192.168.201.12
10047 19:16:02.083643
10048 19:16:02.087023 The DHCP server ip is 192.168.201.1
10049 19:16:02.087138
10050 19:16:02.093508 TFTP server IP predefined by user: 192.168.201.1
10051 19:16:02.093595
10052 19:16:02.100034 Bootfile predefined by user: 13888633/tftp-deploy-lq2x80os/kernel/image.itb
10053 19:16:02.100144
10054 19:16:02.102994 Sending tftp read request... done.
10055 19:16:02.103101
10056 19:16:02.106483 Waiting for the transfer...
10057 19:16:02.106586
10058 19:16:02.354068 00000000 ################################################################
10059 19:16:02.354234
10060 19:16:02.600384 00080000 ################################################################
10061 19:16:02.600516
10062 19:16:02.847727 00100000 ################################################################
10063 19:16:02.847872
10064 19:16:03.095963 00180000 ################################################################
10065 19:16:03.096136
10066 19:16:03.343886 00200000 ################################################################
10067 19:16:03.344042
10068 19:16:03.592364 00280000 ################################################################
10069 19:16:03.592498
10070 19:16:03.842515 00300000 ################################################################
10071 19:16:03.842649
10072 19:16:04.091373 00380000 ################################################################
10073 19:16:04.091518
10074 19:16:04.342354 00400000 ################################################################
10075 19:16:04.342529
10076 19:16:04.602455 00480000 ################################################################
10077 19:16:04.602630
10078 19:16:04.858442 00500000 ################################################################
10079 19:16:04.858608
10080 19:16:05.112818 00580000 ################################################################
10081 19:16:05.112954
10082 19:16:05.368943 00600000 ################################################################
10083 19:16:05.369124
10084 19:16:05.623609 00680000 ################################################################
10085 19:16:05.623746
10086 19:16:05.874172 00700000 ################################################################
10087 19:16:05.874321
10088 19:16:06.126297 00780000 ################################################################
10089 19:16:06.126467
10090 19:16:06.377209 00800000 ################################################################
10091 19:16:06.377372
10092 19:16:06.628030 00880000 ################################################################
10093 19:16:06.628194
10094 19:16:06.878027 00900000 ################################################################
10095 19:16:06.878203
10096 19:16:07.131350 00980000 ################################################################
10097 19:16:07.131510
10098 19:16:07.380011 00a00000 ################################################################
10099 19:16:07.380181
10100 19:16:07.635057 00a80000 ################################################################
10101 19:16:07.635236
10102 19:16:07.890551 00b00000 ################################################################
10103 19:16:07.890718
10104 19:16:08.152555 00b80000 ################################################################
10105 19:16:08.152716
10106 19:16:08.408970 00c00000 ################################################################
10107 19:16:08.409138
10108 19:16:08.659313 00c80000 ################################################################
10109 19:16:08.659451
10110 19:16:08.908249 00d00000 ################################################################
10111 19:16:08.908393
10112 19:16:09.158467 00d80000 ################################################################
10113 19:16:09.158610
10114 19:16:09.411220 00e00000 ################################################################
10115 19:16:09.411391
10116 19:16:09.666106 00e80000 ################################################################
10117 19:16:09.666270
10118 19:16:09.925008 00f00000 ################################################################
10119 19:16:09.925176
10120 19:16:10.183935 00f80000 ################################################################
10121 19:16:10.184072
10122 19:16:10.440820 01000000 ################################################################
10123 19:16:10.440987
10124 19:16:10.698247 01080000 ################################################################
10125 19:16:10.698421
10126 19:16:10.953916 01100000 ################################################################
10127 19:16:10.954083
10128 19:16:11.213429 01180000 ################################################################
10129 19:16:11.213599
10130 19:16:11.471070 01200000 ################################################################
10131 19:16:11.471238
10132 19:16:11.726129 01280000 ################################################################
10133 19:16:11.726302
10134 19:16:11.976168 01300000 ################################################################
10135 19:16:11.976335
10136 19:16:12.229806 01380000 ################################################################
10137 19:16:12.229980
10138 19:16:12.481891 01400000 ################################################################
10139 19:16:12.482111
10140 19:16:12.734156 01480000 ################################################################
10141 19:16:12.734300
10142 19:16:12.989462 01500000 ################################################################
10143 19:16:12.989664
10144 19:16:13.247057 01580000 ################################################################
10145 19:16:13.247201
10146 19:16:13.506257 01600000 ################################################################
10147 19:16:13.506403
10148 19:16:13.767768 01680000 ################################################################
10149 19:16:13.767947
10150 19:16:14.022768 01700000 ################################################################
10151 19:16:14.022928
10152 19:16:14.282811 01780000 ################################################################
10153 19:16:14.282996
10154 19:16:14.620232 01800000 ################################################################
10155 19:16:14.620403
10156 19:16:14.952513 01880000 ################################################################
10157 19:16:14.952699
10158 19:16:15.280454 01900000 ################################################################
10159 19:16:15.280599
10160 19:16:15.600879 01980000 ################################################################
10161 19:16:15.601056
10162 19:16:15.864606 01a00000 ################################################################
10163 19:16:15.864789
10164 19:16:16.124621 01a80000 ################################################################
10165 19:16:16.124770
10166 19:16:16.384694 01b00000 ################################################################
10167 19:16:16.384882
10168 19:16:16.642678 01b80000 ################################################################
10169 19:16:16.642842
10170 19:16:16.901261 01c00000 ################################################################
10171 19:16:16.901444
10172 19:16:17.164527 01c80000 ################################################################
10173 19:16:17.164700
10174 19:16:17.418226 01d00000 ################################################################
10175 19:16:17.418408
10176 19:16:17.681782 01d80000 ################################################################
10177 19:16:17.681952
10178 19:16:17.941118 01e00000 ################################################################
10179 19:16:17.941323
10180 19:16:18.202790 01e80000 ################################################################
10181 19:16:18.202932
10182 19:16:18.463950 01f00000 ################################################################
10183 19:16:18.464112
10184 19:16:18.734740 01f80000 ################################################################
10185 19:16:18.734927
10186 19:16:18.998505 02000000 ################################################################
10187 19:16:18.998706
10188 19:16:19.279851 02080000 ################################################################
10189 19:16:19.280046
10190 19:16:19.536782 02100000 ################################################################
10191 19:16:19.536962
10192 19:16:19.786783 02180000 ################################################################
10193 19:16:19.786917
10194 19:16:20.043213 02200000 ################################################################
10195 19:16:20.043382
10196 19:16:20.299522 02280000 ################################################################
10197 19:16:20.299675
10198 19:16:20.567595 02300000 ################################################################
10199 19:16:20.567773
10200 19:16:20.832967 02380000 ################################################################
10201 19:16:20.833138
10202 19:16:20.903429 02400000 ################## done.
10203 19:16:20.903623
10204 19:16:20.906230 The bootfile was 37891854 bytes long.
10205 19:16:20.906378
10206 19:16:20.909797 Sending tftp read request... done.
10207 19:16:20.909932
10208 19:16:20.913279 Waiting for the transfer...
10209 19:16:20.913409
10210 19:16:20.913520 00000000 # done.
10211 19:16:20.913630
10212 19:16:20.923076 Command line loaded dynamically from TFTP file: 13888633/tftp-deploy-lq2x80os/kernel/cmdline
10213 19:16:20.923212
10214 19:16:20.936096 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10215 19:16:20.936240
10216 19:16:20.936336 Loading FIT.
10217 19:16:20.936415
10218 19:16:20.939919 Image ramdisk-1 has 23944650 bytes.
10219 19:16:20.940007
10220 19:16:20.943144 Image fdt-1 has 65308 bytes.
10221 19:16:20.943230
10222 19:16:20.946337 Image kernel-1 has 13879864 bytes.
10223 19:16:20.946423
10224 19:16:20.956514 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10225 19:16:20.956631
10226 19:16:20.973135 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10227 19:16:20.973292
10228 19:16:20.979935 Choosing best match conf-1 for compat google,spherion-rev2.
10229 19:16:20.980035
10230 19:16:20.983296 Connected to device vid:did:rid of 1ae0:0028:00
10231 19:16:20.993639
10232 19:16:20.997072 tpm_get_response: command 0x17b, return code 0x0
10233 19:16:20.997180
10234 19:16:21.000553 ec_init: CrosEC protocol v3 supported (256, 248)
10235 19:16:21.006108
10236 19:16:21.008852 tpm_cleanup: add release locality here.
10237 19:16:21.008984
10238 19:16:21.009094 Shutting down all USB controllers.
10239 19:16:21.009203
10240 19:16:21.012334 Removing current net device
10241 19:16:21.012464
10242 19:16:21.019500 Exiting depthcharge with code 4 at timestamp: 54404586
10243 19:16:21.019633
10244 19:16:21.022277 LZMA decompressing kernel-1 to 0x821a6718
10245 19:16:21.022400
10246 19:16:21.025760 LZMA decompressing kernel-1 to 0x40000000
10247 19:16:22.757618
10248 19:16:22.757758 jumping to kernel
10249 19:16:22.758242 end: 2.2.4 bootloader-commands (duration 00:00:27) [common]
10250 19:16:22.758345 start: 2.2.5 auto-login-action (timeout 00:03:58) [common]
10251 19:16:22.758425 Setting prompt string to ['Linux version [0-9]']
10252 19:16:22.758496 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10253 19:16:22.758567 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10254 19:16:22.796799
10255 19:16:22.800466 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10256 19:16:22.803361 start: 2.2.5.1 login-action (timeout 00:03:58) [common]
10257 19:16:22.803469 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10258 19:16:22.803545 Setting prompt string to []
10259 19:16:22.803626 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10260 19:16:22.803703 Using line separator: #'\n'#
10261 19:16:22.803765 No login prompt set.
10262 19:16:22.803830 Parsing kernel messages
10263 19:16:22.803888 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10264 19:16:22.803992 [login-action] Waiting for messages, (timeout 00:03:58)
10265 19:16:22.804060 Waiting using forced prompt support (timeout 00:01:59)
10266 19:16:22.823307 [ 0.000000] Linux version 6.9.0 (KernelCI@build-j200981-arm64-gcc-10-defconfig-arm64-chromebook-mkrnw) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat May 18 18:50:51 UTC 2024
10267 19:16:22.826970 [ 0.000000] KASLR enabled
10268 19:16:22.830070 [ 0.000000] random: crng init done
10269 19:16:22.832968 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10270 19:16:22.836574 [ 0.000000] efi: UEFI not found.
10271 19:16:22.846653 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10272 19:16:22.852716 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10273 19:16:22.862707 [ 0.000000] OF: reserved mem: 0x0000000050000000..0x00000000528fffff (41984 KiB) nomap non-reusable scp@50000000
10274 19:16:22.872620 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10275 19:16:22.882773 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10276 19:16:22.892628 [ 0.000000] OF: reserved mem: 0x00000000c0000000..0x00000000c3ffffff (65536 KiB) map non-reusable wifi@c0000000
10277 19:16:22.902680 [ 0.000000] OF: reserved mem: 0x00000000ffe66000..0x00000000fff65fff (1024 KiB) map non-reusable ramoops
10278 19:16:22.908989 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10279 19:16:22.912516 [ 0.000000] printk: legacy bootconsole [mtk8250] enabled
10280 19:16:22.922052 [ 0.000000] NUMA: No NUMA configuration found
10281 19:16:22.929237 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10282 19:16:22.935706 [ 0.000000] NUMA: NODE_DATA [mem 0x23efb59c0-0x23efb7fff]
10283 19:16:22.938770 [ 0.000000] Zone ranges:
10284 19:16:22.942227 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10285 19:16:22.945764 [ 0.000000] DMA32 empty
10286 19:16:22.952029 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10287 19:16:22.954939 [ 0.000000] Movable zone start for each node
10288 19:16:22.958542 [ 0.000000] Early memory node ranges
10289 19:16:22.965167 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10290 19:16:22.971851 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10291 19:16:22.978289 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10292 19:16:22.985073 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10293 19:16:22.991596 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10294 19:16:22.998071 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10295 19:16:23.022809 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10296 19:16:23.062361 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10297 19:16:23.068604 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000 on node -1
10298 19:16:23.075100 [ 0.000000] psci: probing for conduit method from DT.
10299 19:16:23.078605 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10300 19:16:23.085235 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10301 19:16:23.088771 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10302 19:16:23.091435 [ 0.000000] psci: SMC Calling Convention v1.2
10303 19:16:23.098595 [ 0.000000] percpu: Embedded 24 pages/cpu s59752 r8192 d30360 u98304
10304 19:16:23.105686 [ 0.000000] Detected VIPT I-cache on CPU0
10305 19:16:23.112317 [ 0.000000] CPU features: detected: GIC system register CPU interface
10306 19:16:23.115530 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10307 19:16:23.121996 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10308 19:16:23.128494 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10309 19:16:23.135530 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10310 19:16:23.141892 [ 0.000000] alternatives: applying boot alternatives
10311 19:16:23.158746 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10312 19:16:23.168359 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10313 19:16:23.179207 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10314 19:16:23.189642 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10315 19:16:23.192369 <6>[ 0.000000] Fallback order for Node 0: 0
10316 19:16:23.199118 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10317 19:16:23.202718 <6>[ 0.000000] Policy zone: Normal
10318 19:16:23.209131 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10319 19:16:23.212751 <6>[ 0.000000] software IO TLB: area num 8.
10320 19:16:23.270715 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10321 19:16:23.415655 <6>[ 0.000000] Memory: 7933264K/8385536K available (18880K kernel code, 5128K rwdata, 24520K rodata, 10880K init, 752K bss, 419504K reserved, 32768K cma-reserved)
10322 19:16:23.421869 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10323 19:16:23.428306 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10324 19:16:23.431802 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10325 19:16:23.438630 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=8.
10326 19:16:23.444806 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10327 19:16:23.448303 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10328 19:16:23.458377 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10329 19:16:23.465335 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10330 19:16:23.472332 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
10331 19:16:23.478257 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
10332 19:16:23.485035 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10333 19:16:23.492295 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10334 19:16:23.495024 <6>[ 0.000000] GICv3: 608 SPIs implemented
10335 19:16:23.502021 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10336 19:16:23.505462 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10337 19:16:23.508824 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10338 19:16:23.518505 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10339 19:16:23.528598 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10340 19:16:23.541998 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10341 19:16:23.548408 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10342 19:16:23.558314 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10343 19:16:23.571673 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10344 19:16:23.578073 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10345 19:16:23.585008 <6>[ 0.009642] Console: colour dummy device 80x25
10346 19:16:23.595478 <6>[ 0.014401] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10347 19:16:23.601886 <6>[ 0.024844] pid_max: default: 32768 minimum: 301
10348 19:16:23.605436 <6>[ 0.029768] LSM: initializing lsm=capability
10349 19:16:23.612157 <6>[ 0.034392] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10350 19:16:23.621597 <6>[ 0.042205] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10351 19:16:23.628649 <6>[ 0.052020] rcu: Hierarchical SRCU implementation.
10352 19:16:23.632081 <6>[ 0.057073] rcu: Max phase no-delay instances is 1000.
10353 19:16:23.640350 <6>[ 0.064925] EFI services will not be available.
10354 19:16:23.644136 <6>[ 0.069903] smp: Bringing up secondary CPUs ...
10355 19:16:23.653395 <6>[ 0.074986] Detected VIPT I-cache on CPU1
10356 19:16:23.659775 <6>[ 0.075050] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10357 19:16:23.666732 <6>[ 0.075085] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10358 19:16:23.669887 <6>[ 0.075463] Detected VIPT I-cache on CPU2
10359 19:16:23.677002 <6>[ 0.075497] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10360 19:16:23.683238 <6>[ 0.075513] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10361 19:16:23.689500 <6>[ 0.075814] Detected VIPT I-cache on CPU3
10362 19:16:23.696316 <6>[ 0.075849] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10363 19:16:23.703125 <6>[ 0.075864] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10364 19:16:23.705982 <6>[ 0.076206] CPU features: detected: Spectre-v4
10365 19:16:23.712653 <6>[ 0.076213] CPU features: detected: Spectre-BHB
10366 19:16:23.716110 <6>[ 0.076219] Detected PIPT I-cache on CPU4
10367 19:16:23.722560 <6>[ 0.076260] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10368 19:16:23.729548 <6>[ 0.076278] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10369 19:16:23.736249 <6>[ 0.076605] Detected PIPT I-cache on CPU5
10370 19:16:23.742592 <6>[ 0.076653] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10371 19:16:23.749230 <6>[ 0.076673] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10372 19:16:23.752989 <6>[ 0.077000] Detected PIPT I-cache on CPU6
10373 19:16:23.759235 <6>[ 0.077047] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10374 19:16:23.766208 <6>[ 0.077066] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10375 19:16:23.773112 <6>[ 0.077388] Detected PIPT I-cache on CPU7
10376 19:16:23.779551 <6>[ 0.077437] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10377 19:16:23.785941 <6>[ 0.077455] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10378 19:16:23.789418 <6>[ 0.077536] smp: Brought up 1 node, 8 CPUs
10379 19:16:23.793004 <6>[ 0.218867] SMP: Total of 8 processors activated.
10380 19:16:23.799260 <6>[ 0.223788] CPU: All CPU(s) started at EL2
10381 19:16:23.802638 <6>[ 0.228118] CPU features: detected: 32-bit EL0 Support
10382 19:16:23.812414 <6>[ 0.233471] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10383 19:16:23.819205 <6>[ 0.242274] CPU features: detected: Common not Private translations
10384 19:16:23.825406 <6>[ 0.248785] CPU features: detected: CRC32 instructions
10385 19:16:23.832044 <6>[ 0.254178] CPU features: detected: RCpc load-acquire (LDAPR)
10386 19:16:23.835252 <6>[ 0.260132] CPU features: detected: LSE atomic instructions
10387 19:16:23.841961 <6>[ 0.265913] CPU features: detected: Privileged Access Never
10388 19:16:23.848751 <6>[ 0.271693] CPU features: detected: RAS Extension Support
10389 19:16:23.855554 <6>[ 0.277302] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10390 19:16:23.861827 <6>[ 0.284504] alternatives: applying system-wide alternatives
10391 19:16:23.872271 <6>[ 0.293339] CPU features: detected: Hardware dirty bit management on CPU4-7
10392 19:16:23.875563 <6>[ 0.302634] devtmpfs: initialized
10393 19:16:23.893431 <6>[ 0.314150] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10394 19:16:23.903131 <6>[ 0.324115] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10395 19:16:23.909531 <6>[ 0.331969] 2G module region forced by RANDOMIZE_MODULE_REGION_FULL
10396 19:16:23.912845 <6>[ 0.338458] 0 pages in range for non-PLT usage
10397 19:16:23.919831 <6>[ 0.338460] 509184 pages in range for PLT usage
10398 19:16:23.922746 <6>[ 0.343334] pinctrl core: initialized pinctrl subsystem
10399 19:16:23.931266 <6>[ 0.355322] DMI not present or invalid.
10400 19:16:23.937530 <6>[ 0.361535] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10401 19:16:23.947253 <6>[ 0.368398] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10402 19:16:23.954258 <6>[ 0.375913] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10403 19:16:23.964147 <6>[ 0.384144] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10404 19:16:23.967663 <6>[ 0.392396] audit: initializing netlink subsys (disabled)
10405 19:16:23.977360 <5>[ 0.398096] audit: type=2000 audit(0.288:1): state=initialized audit_enabled=0 res=1
10406 19:16:23.983931 <6>[ 0.399086] thermal_sys: Registered thermal governor 'step_wise'
10407 19:16:23.990775 <6>[ 0.406060] thermal_sys: Registered thermal governor 'power_allocator'
10408 19:16:23.994243 <6>[ 0.412321] cpuidle: using governor menu
10409 19:16:24.000319 <6>[ 0.423302] NET: Registered PF_QIPCRTR protocol family
10410 19:16:24.006786 <6>[ 0.428822] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10411 19:16:24.013672 <6>[ 0.435921] ASID allocator initialised with 32768 entries
10412 19:16:24.016488 <6>[ 0.443018] Serial: AMBA PL011 UART driver
10413 19:16:24.041644 <6>[ 0.462799] platform 11230000.pcie: Fixed dependency cycle(s) with /soc/pcie@11230000/interrupt-controller
10414 19:16:24.058047 <6>[ 0.479432] platform 14010000.dsi: Fixed dependency cycle(s) with /soc/i2c@11cb0000/anx7625@58
10415 19:16:24.076807 <6>[ 0.498171] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10416 19:16:24.083790 <6>[ 0.505208] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10417 19:16:24.090277 <6>[ 0.511744] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10418 19:16:24.096707 <6>[ 0.518751] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10419 19:16:24.103244 <6>[ 0.525235] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10420 19:16:24.110129 <6>[ 0.532242] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10421 19:16:24.116494 <6>[ 0.538731] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10422 19:16:24.123524 <6>[ 0.545734] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10423 19:16:24.127026 <6>[ 0.552504] Demotion targets for Node 0: null
10424 19:16:24.133335 <6>[ 0.558012] ACPI: Interpreter disabled.
10425 19:16:24.140361 <6>[ 0.564698] iommu: Default domain type: Translated
10426 19:16:24.146790 <6>[ 0.569724] iommu: DMA domain TLB invalidation policy: strict mode
10427 19:16:24.150420 <5>[ 0.576499] SCSI subsystem initialized
10428 19:16:24.156550 <6>[ 0.580687] usbcore: registered new interface driver usbfs
10429 19:16:24.163638 <6>[ 0.586420] usbcore: registered new interface driver hub
10430 19:16:24.166881 <6>[ 0.591976] usbcore: registered new device driver usb
10431 19:16:24.173692 <6>[ 0.598300] pps_core: LinuxPPS API ver. 1 registered
10432 19:16:24.183854 <6>[ 0.603495] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10433 19:16:24.187262 <6>[ 0.612835] PTP clock support registered
10434 19:16:24.190541 <6>[ 0.617096] EDAC MC: Ver: 3.0.0
10435 19:16:24.196827 <6>[ 0.620864] scmi_core: SCMI protocol bus registered
10436 19:16:24.200335 <6>[ 0.627427] FPGA manager framework
10437 19:16:24.207340 <6>[ 0.631120] Advanced Linux Sound Architecture Driver Initialized.
10438 19:16:24.210495 <6>[ 0.638096] vgaarb: loaded
10439 19:16:24.217281 <6>[ 0.641374] clocksource: Switched to clocksource arch_sys_counter
10440 19:16:24.223544 <5>[ 0.647845] VFS: Disk quotas dquot_6.6.0
10441 19:16:24.230549 <6>[ 0.652030] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10442 19:16:24.233323 <6>[ 0.659269] pnp: PnP ACPI: disabled
10443 19:16:24.241752 <6>[ 0.666404] NET: Registered PF_INET protocol family
10444 19:16:24.252084 <6>[ 0.671993] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10445 19:16:24.263187 <6>[ 0.684238] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10446 19:16:24.272867 <6>[ 0.693044] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10447 19:16:24.279390 <6>[ 0.701004] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10448 19:16:24.286504 <6>[ 0.709686] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10449 19:16:24.298430 <6>[ 0.719389] TCP: Hash tables configured (established 65536 bind 65536)
10450 19:16:24.304607 <6>[ 0.726251] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10451 19:16:24.311491 <6>[ 0.733453] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10452 19:16:24.317882 <6>[ 0.741156] NET: Registered PF_UNIX/PF_LOCAL protocol family
10453 19:16:24.324490 <6>[ 0.747288] RPC: Registered named UNIX socket transport module.
10454 19:16:24.328193 <6>[ 0.753440] RPC: Registered udp transport module.
10455 19:16:24.334998 <6>[ 0.758375] RPC: Registered tcp transport module.
10456 19:16:24.338041 <6>[ 0.763306] RPC: Registered tcp-with-tls transport module.
10457 19:16:24.347855 <6>[ 0.769014] RPC: Registered tcp NFSv4.1 backchannel transport module.
10458 19:16:24.351341 <6>[ 0.775683] PCI: CLS 0 bytes, default 64
10459 19:16:24.354461 <6>[ 0.780051] Unpacking initramfs...
10460 19:16:24.362193 <6>[ 0.786230] kvm [1]: nv: 477 coarse grained trap handlers
10461 19:16:24.368552 <6>[ 0.792069] kvm [1]: IPA Size Limit: 40 bits
10462 19:16:24.371996 <6>[ 0.796599] kvm [1]: GICv3: no GICV resource entry
10463 19:16:24.378237 <6>[ 0.801618] kvm [1]: disabling GICv2 emulation
10464 19:16:24.381565 <6>[ 0.806307] kvm [1]: GIC system register CPU interface enabled
10465 19:16:24.388320 <6>[ 0.812385] kvm [1]: vgic interrupt IRQ18
10466 19:16:24.391558 <6>[ 0.816646] kvm [1]: VHE mode initialized successfully
10467 19:16:24.398942 <5>[ 0.823077] Initialise system trusted keyrings
10468 19:16:24.405156 <6>[ 0.827905] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10469 19:16:24.412249 <6>[ 0.834776] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10470 19:16:24.415105 <5>[ 0.841001] NFS: Registering the id_resolver key type
10471 19:16:24.421927 <5>[ 0.846296] Key type id_resolver registered
10472 19:16:24.425281 <5>[ 0.850710] Key type id_legacy registered
10473 19:16:24.431842 <6>[ 0.854961] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10474 19:16:24.438561 <6>[ 0.861881] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10475 19:16:24.445395 <6>[ 0.869565] 9p: Installing v9fs 9p2000 file system support
10476 19:16:24.491875 <5>[ 0.916561] Key type asymmetric registered
10477 19:16:24.495311 <5>[ 0.920891] Asymmetric key parser 'x509' registered
10478 19:16:24.505249 <6>[ 0.926034] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10479 19:16:24.508746 <6>[ 0.933649] io scheduler mq-deadline registered
10480 19:16:24.512179 <6>[ 0.938411] io scheduler kyber registered
10481 19:16:24.518417 <6>[ 0.942679] io scheduler bfq registered
10482 19:16:24.549577 <3>[ 0.974383] cannot find "mediatek,mt8192-fhctl"
10483 19:16:24.585196 <6>[ 1.006458] mtk-socinfo mtk-socinfo.0.auto: MediaTek Kompanio 820 (MT8192) SoC detected.
10484 19:16:24.600550 <6>[ 1.025042] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10485 19:16:24.609310 <6>[ 1.033537] printk: legacy console [ttyS0] disabled
10486 19:16:24.637757 <6>[ 1.058889] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 252, base_baud = 1625000) is a ST16650V2
10487 19:16:24.644376 <6>[ 1.068365] printk: legacy console [ttyS0] enabled
10488 19:16:24.647903 <6>[ 1.068365] printk: legacy console [ttyS0] enabled
10489 19:16:24.654009 <6>[ 1.078494] printk: legacy bootconsole [mtk8250] disabled
10490 19:16:24.660761 <6>[ 1.078494] printk: legacy bootconsole [mtk8250] disabled
10491 19:16:24.670182 <6>[ 1.094985] msm_serial: driver initialized
10492 19:16:24.673725 <6>[ 1.099735] SuperH (H)SCI(F) driver initialized
10493 19:16:24.680826 <6>[ 1.104747] STM32 USART driver initialized
10494 19:16:24.686847 <4>[ 1.111054] SPI driver tpm_tis_spi has no spi_device_id for atmel,attpm20p
10495 19:16:24.701521 <6>[ 1.126084] loop: module loaded
10496 19:16:24.707723 <4>[ 1.132581] mtk-pmic-keys: Failed to locate of_node [id: -1]
10497 19:16:24.714729 <6>[ 1.133560] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10498 19:16:24.718082 <6>[ 1.139662] megasas: 07.727.03.00-rc1
10499 19:16:24.725519 <6>[ 1.150223] vsram_others: Bringing 850000uV into 800000-800000uV
10500 19:16:24.740270 <6>[ 1.164796] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10501 19:16:24.756299 <6>[ 1.180936] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10502 19:16:25.028761 <4>[ 1.453426] ------------[ cut here ]------------
10503 19:16:25.029181 Setting prompt string to ['-+\\[ end trace \\w* \\]-+[^\\n]*\\r', '/ #', 'Login timed out', 'Login incorrect']
10504 19:16:25.038648 <4>[ 1.458302] WARNING: CPU: 3 PID: 69 at kernel/module/kmod.c:144 __request_module+0x188/0x1f4
10505 19:16:25.042118 <4>[ 1.467013] Modules linked in:
10506 19:16:25.049162 <4>[ 1.470321] CPU: 3 PID: 69 Comm: kworker/u32:3 Not tainted 6.9.0 #1
10507 19:16:25.052587 <4>[ 1.476838] Hardware name: Google Spherion (rev0 - 3) (DT)
10508 19:16:25.058747 <4>[ 1.482573] Workqueue: async async_run_entry_fn
10509 19:16:25.065560 <4>[ 1.487360] pstate: 00400009 (nzcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
10510 19:16:25.069027 <4>[ 1.494572] pc : __request_module+0x188/0x1f4
10511 19:16:25.075691 <4>[ 1.499181] lr : __request_module+0x180/0x1f4
10512 19:16:25.078965 <4>[ 1.503788] sp : ffff8000809f3400
10513 19:16:25.085735 <4>[ 1.507352] x29: ffff8000809f3400 x28: 0000000000281ae0 x27: ffffb8f27488e0d2
10514 19:16:25.092399 <4>[ 1.514741] x26: 0000000000000000 x25: ffff6538008e6780 x24: 00000000ffffffff
10515 19:16:25.099258 <4>[ 1.522129] x23: 000000000000200f x22: ffffb8f2720e5f9e x21: 0000000000000001
10516 19:16:25.105789 <4>[ 1.529516] x20: 0000000000000000 x19: ffffb8f273602e60 x18: 0000000000000014
10517 19:16:25.115553 <4>[ 1.536903] x17: 0000000059b69624 x16: 000000001c1bafcd x15: 0000000064eca8c6
10518 19:16:25.122569 <4>[ 1.544291] x14: 0000000000000001 x13: ffff8000809f3850 x12: 0000000000000000
10519 19:16:25.128799 <4>[ 1.551678] x11: 00000000e723dca8 x10: fffffffffdd0a9b6 x9 : 0000000000000004
10520 19:16:25.135785 <4>[ 1.559065] x8 : ffff6538008e6780 x7 : 3135616873286361 x6 : 0c0406065b07370f
10521 19:16:25.145472 <4>[ 1.566452] x5 : 0f37075b0606040c x4 : 0000000000000000 x3 : 0000000000000008
10522 19:16:25.152418 <4>[ 1.573838] x2 : ffffb8f2720e5f9e x1 : ffffb8f270ec5468 x0 : 0000000000000001
10523 19:16:25.155930 <4>[ 1.581225] Call trace:
10524 19:16:25.158629 <4>[ 1.583924] __request_module+0x188/0x1f4
10525 19:16:25.162140 <4>[ 1.588186] crypto_alg_mod_lookup+0x178/0x21c
10526 19:16:25.168896 <4>[ 1.592886] crypto_alloc_tfm_node+0x58/0x114
10527 19:16:25.172156 <4>[ 1.597494] crypto_alloc_shash+0x24/0x30
10528 19:16:25.175803 <4>[ 1.601757] drbg_init_hash_kernel+0x28/0xdc
10529 19:16:25.182181 <4>[ 1.606281] drbg_kcapi_seed+0x21c/0x420
10530 19:16:25.185668 <4>[ 1.610454] crypto_rng_reset+0x84/0xb4
10531 19:16:25.189239 <4>[ 1.614540] crypto_get_default_rng+0xa4/0xd8
10532 19:16:25.191957 <4>[ 1.619148] ecc_gen_privkey+0x58/0xd0
10533 19:16:25.198639 <4>[ 1.623149] ecdh_set_secret+0x90/0x198
10534 19:16:25.202390 <4>[ 1.627235] tpm_buf_append_salt+0x164/0x2dc
10535 19:16:25.205494 <4>[ 1.631760] tpm2_start_auth_session+0xc8/0x29c
10536 19:16:25.212140 <4>[ 1.636543] tpm2_get_random+0x44/0x204
10537 19:16:25.215420 <4>[ 1.640629] tpm_get_random+0x74/0x90
10538 19:16:25.218942 <4>[ 1.644541] tpm_hwrng_read+0x24/0x30
10539 19:16:25.222490 <4>[ 1.648454] add_early_randomness+0x68/0x118
10540 19:16:25.228823 <4>[ 1.652978] hwrng_register+0x16c/0x218
10541 19:16:25.232045 <4>[ 1.657065] tpm_chip_register+0xf0/0x2cc
10542 19:16:25.235740 <4>[ 1.661324] tpm_tis_core_init+0x494/0x7e0
10543 19:16:25.238993 <4>[ 1.665672] tpm_tis_spi_init+0x54/0x70
10544 19:16:25.245904 <4>[ 1.669760] cr50_spi_probe+0xf4/0x27c
10545 19:16:25.248763 <4>[ 1.673760] tpm_tis_spi_driver_probe+0x34/0x64
10546 19:16:25.252228 <4>[ 1.678542] spi_probe+0x84/0xe4
10547 19:16:25.255486 <4>[ 1.682025] really_probe+0xbc/0x2a0
10548 19:16:25.262450 <4>[ 1.685855] __driver_probe_device+0x78/0x12c
10549 19:16:25.265967 <4>[ 1.690464] driver_probe_device+0x40/0x160
10550 19:16:25.268616 <4>[ 1.694899] __device_attach_driver+0xb8/0x134
10551 19:16:25.275888 <4>[ 1.699594] bus_for_each_drv+0x84/0xe0
10552 19:16:25.278629 <4>[ 1.703681] __device_attach_async_helper+0xac/0xd0
10553 19:16:25.281937 <4>[ 1.708811] async_run_entry_fn+0x34/0xe0
10554 19:16:25.289053 <4>[ 1.713072] process_one_work+0x154/0x298
10555 19:16:25.291880 <4>[ 1.717337] worker_thread+0x304/0x408
10556 19:16:25.295351 <4>[ 1.721338] kthread+0x118/0x11c
10557 19:16:25.298856 <4>[ 1.724819] ret_from_fork+0x10/0x20
10558 19:16:25.305345 <4>[ 1.728648] ---[ end trace 0000000000000000 ]---
10559 19:16:25.305742 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10560 19:16:25.305860 login-action: kernel 'warning'
10561 19:16:25.305955 [login-action] Waiting for messages, (timeout 00:03:56)
10562 19:16:25.306036 Waiting using forced prompt support (timeout 00:01:58)
10563 19:16:25.383127 <6>[ 1.807283] Freeing initrd memory: 23380K
10564 19:16:25.401419 <6>[ 1.826199] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10565 19:16:25.412585 <6>[ 1.837232] tun: Universal TUN/TAP device driver, 1.6
10566 19:16:25.416036 <6>[ 1.843570] thunder_xcv, ver 1.0
10567 19:16:25.422318 <6>[ 1.847078] thunder_bgx, ver 1.0
10568 19:16:25.422456 <6>[ 1.850571] nicpf, ver 1.0
10569 19:16:25.433560 <6>[ 1.854760] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10570 19:16:25.440512 <6>[ 1.862237] hns3: Copyright (c) 2017 Huawei Corporation.
10571 19:16:25.446152 <6>[ 1.867845] hclge is initializing
10572 19:16:25.449575 <6>[ 1.871449] e1000: Intel(R) PRO/1000 Network Driver
10573 19:16:25.453108 <6>[ 1.876585] e1000: Copyright (c) 1999-2006 Intel Corporation.
10574 19:16:25.459798 <6>[ 1.882595] e1000e: Intel(R) PRO/1000 Network Driver
10575 19:16:25.483686 <6>[ 1.887811] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10576 19:16:25.483860 <6>[ 1.893997] igb: Intel(R) Gigabit Ethernet Network Driver
10577 19:16:25.483965 <6>[ 1.899648] igb: Copyright (c) 2007-2014 Intel Corporation.
10578 19:16:25.484289 <6>[ 1.905481] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10579 19:16:25.486805 <6>[ 1.911999] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10580 19:16:25.497383 <6>[ 1.918523] sky2: driver version 1.30
10581 19:16:25.506357 <6>[ 1.923828] usbcore: registered new device driver r8152-cfgselector
10582 19:16:25.506723 <6>[ 1.930364] usbcore: registered new interface driver r8152
10583 19:16:25.510696 <6>[ 1.936309] VFIO - User Level meta-driver version: 0.3
10584 19:16:25.529050 <6>[ 1.944985] usbcore: registered new interface driver usb-storage
10585 19:16:25.535104 <6>[ 1.951502] usbcore: registered new device driver onboard-usb-hub
10586 19:16:25.538990 <6>[ 1.961440] mt6397-rtc mt6359-rtc: registered as rtc0
10587 19:16:25.550813 <6>[ 1.966929] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-18T19:11:46 UTC (1716059506)
10588 19:16:25.550935 <6>[ 1.976708] i2c_dev: i2c /dev entries driver
10589 19:16:25.562280 <6>[ 1.982069] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10590 19:16:25.574303 <6>[ 1.982405] platform 14010000.dsi: Fixed dependency cycle(s) with /soc/i2c@11cb0000/anx7625@58
10591 19:16:25.584585 <6>[ 2.002016] i2c 3-0058: Fixed dependency cycle(s) with /soc/i2c@11cb0000/anx7625@58/aux-bus/panel
10592 19:16:25.638612 <6>[ 2.011156] i2c 3-0058: Fixed dependency cycle(s) with /soc/dsi@14010000
10593 19:16:25.639311 <6>[ 2.026905] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10594 19:16:25.639670 <4>[ 2.036145] cpu cpu0: supply cpu not found, using dummy regulator
10595 19:16:25.640242 <4>[ 2.042576] cpu cpu1: supply cpu not found, using dummy regulator
10596 19:16:25.640549 <4>[ 2.049001] cpu cpu2: supply cpu not found, using dummy regulator
10597 19:16:25.640883 <4>[ 2.055404] cpu cpu3: supply cpu not found, using dummy regulator
10598 19:16:25.641258 <4>[ 2.061806] cpu cpu4: supply cpu not found, using dummy regulator
10599 19:16:25.644268 <4>[ 2.068205] cpu cpu5: supply cpu not found, using dummy regulator
10600 19:16:25.653839 <4>[ 2.074609] cpu cpu6: supply cpu not found, using dummy regulator
10601 19:16:25.657335 <4>[ 2.081027] cpu cpu7: supply cpu not found, using dummy regulator
10602 19:16:25.677061 <6>[ 2.101572] cpu cpu0: EM: created perf domain
10603 19:16:25.680627 <6>[ 2.106423] cpu cpu4: EM: created perf domain
10604 19:16:25.687841 <6>[ 2.112441] sdhci: Secure Digital Host Controller Interface driver
10605 19:16:25.694758 <6>[ 2.118876] sdhci: Copyright(c) Pierre Ossman
10606 19:16:25.704536 <6>[ 2.123939] Synopsys Designware Multimedia Card Interface Driver
10607 19:16:25.708572 <6>[ 2.130674] sdhci-pltfm: SDHCI platform and OF driver helper
10608 19:16:25.712135 <6>[ 2.130774] mmc0: CQHCI version 5.10
10609 19:16:25.718516 <6>[ 2.140800] ledtrig-cpu: registered to indicate activity on CPUs
10610 19:16:25.742514 <6>[ 2.147607] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10611 19:16:25.742915 <6>[ 2.154753] usbcore: registered new interface driver usbhid
10612 19:16:25.743005 <6>[ 2.160576] usbhid: USB HID core driver
10613 19:16:25.743071 <6>[ 2.164937] spi_master spi0: will run message pump with realtime priority
10614 19:16:25.758865 <6>[ 2.172826] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10615 19:16:25.761931 <6>[ 2.182197] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10616 19:16:25.774858 <6>[ 2.196088] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10617 19:16:25.788243 <6>[ 2.199390] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10618 19:16:25.795175 <6>[ 2.207202] mt8192_mt6359 sound: audio-routing not found: using legacy probe
10619 19:16:25.801860 <6>[ 2.225820] NET: Registered PF_PACKET protocol family
10620 19:16:25.815220 <6>[ 2.226614] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10621 19:16:25.818733 <6>[ 2.231193] 9pnet: Installing 9P2000 support
10622 19:16:25.828643 <4>[ 2.234527] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10623 19:16:25.838720 <4>[ 2.234629] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10624 19:16:25.845741 <4>[ 2.234665] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10625 19:16:25.855392 <4>[ 2.234701] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10626 19:16:25.865614 <4>[ 2.234738] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10627 19:16:25.875770 <4>[ 2.234774] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10628 19:16:25.882465 <4>[ 2.234810] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10629 19:16:25.892127 <4>[ 2.234846] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10630 19:16:25.901886 <4>[ 2.234882] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10631 19:16:25.911972 <4>[ 2.234917] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10632 19:16:25.921947 <4>[ 2.234953] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10633 19:16:25.928870 <4>[ 2.234989] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10634 19:16:25.938849 <4>[ 2.235024] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10635 19:16:25.949311 <4>[ 2.235060] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10636 19:16:25.958838 <4>[ 2.235095] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10637 19:16:25.965465 <4>[ 2.235131] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10638 19:16:25.975823 <4>[ 2.235167] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10639 19:16:25.985506 <4>[ 2.235203] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10640 19:16:25.996066 <4>[ 2.235238] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10641 19:16:26.002823 <4>[ 2.235274] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10642 19:16:26.012221 <4>[ 2.235310] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10643 19:16:26.022122 <4>[ 2.235346] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10644 19:16:26.032800 <4>[ 2.235382] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10645 19:16:26.035939 <6>[ 2.235947] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16c14
10646 19:16:26.042254 <6>[ 2.245801] cros-ec-spi spi0.0: Chrome EC device registered
10647 19:16:26.045965 <5>[ 2.249077] Key type dns_resolver registered
10648 19:16:26.052095 <6>[ 2.249222] mmc0: Command Queue Engine enabled
10649 19:16:26.059016 <6>[ 2.249229] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10650 19:16:26.062493 <6>[ 2.249881] mmcblk0: mmc0:0001 DA4128 116 GiB
10651 19:16:26.068740 <6>[ 2.252935] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10652 19:16:26.075642 <6>[ 2.253868] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10653 19:16:26.079077 <6>[ 2.254634] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10654 19:16:26.085783 <6>[ 2.255220] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10655 19:16:26.097373 <6>[ 2.518512] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
10656 19:16:26.100732 <6>[ 2.527470] registered taskstats version 1
10657 19:16:26.107399 <5>[ 2.532068] Loading compiled-in X.509 certificates
10658 19:16:26.140521 <6>[ 2.564885] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10659 19:16:26.147419 <6>[ 2.571773] xhci-mtk 11200000.usb: xHCI Host Controller
10660 19:16:26.153996 <6>[ 2.577272] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10661 19:16:26.163549 <6>[ 2.585113] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000200010
10662 19:16:26.170104 <6>[ 2.594540] xhci-mtk 11200000.usb: irq 270, io mem 0x11200000
10663 19:16:26.177059 <6>[ 2.600614] xhci-mtk 11200000.usb: xHCI Host Controller
10664 19:16:26.183687 <6>[ 2.606090] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10665 19:16:26.189929 <6>[ 2.613738] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10666 19:16:26.196711 <6>[ 2.621429] hub 1-0:1.0: USB hub found
10667 19:16:26.200162 <6>[ 2.625438] hub 1-0:1.0: 1 port detected
10668 19:16:26.210325 <6>[ 2.629711] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10669 19:16:26.213057 <6>[ 2.638391] hub 2-0:1.0: USB hub found
10670 19:16:26.216993 <6>[ 2.642406] hub 2-0:1.0: 1 port detected
10671 19:16:26.227173 <6>[ 2.651800] mtk-msdc 11f70000.mmc: Got CD GPIO
10672 19:16:26.244594 <4>[ 2.665934] rt5682 1-001a: Using default DAI clk names: rt5682-dai-wclk, rt5682-dai-bclk
10673 19:16:26.620332 <6>[ 3.041822] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10674 19:16:26.775163 <6>[ 3.199557] hub 1-1:1.0: USB hub found
10675 19:16:26.777855 <6>[ 3.204132] hub 1-1:1.0: 4 ports detected
10676 19:16:26.806625 <6>[ 3.233713] hub 1-1:1.0: USB hub found
10677 19:16:26.811887 <6>[ 3.238085] hub 1-1:1.0: 4 ports detected
10678 19:16:26.897178 <6>[ 3.321727] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10679 19:16:26.925734 <6>[ 3.350764] hub 2-1:1.0: USB hub found
10680 19:16:26.928415 <6>[ 3.355172] hub 2-1:1.0: 3 ports detected
10681 19:16:26.959251 <6>[ 3.383498] hub 2-1:1.0: USB hub found
10682 19:16:26.962534 <6>[ 3.387893] hub 2-1:1.0: 3 ports detected
10683 19:16:27.132354 <6>[ 3.553792] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10684 19:16:27.264475 <6>[ 3.688919] hub 1-1.4:1.0: USB hub found
10685 19:16:27.267270 <6>[ 3.693608] hub 1-1.4:1.0: 2 ports detected
10686 19:16:27.319623 <6>[ 3.744455] hub 1-1.4:1.0: USB hub found
10687 19:16:27.323248 <6>[ 3.748999] hub 1-1.4:1.0: 2 ports detected
10688 19:16:27.352365 <6>[ 3.773629] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10689 19:16:27.456563 <6>[ 3.878364] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10690 19:16:27.492926 <4>[ 3.914180] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10691 19:16:27.502739 <4>[ 3.923306] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10692 19:16:27.546396 <6>[ 3.970951] r8152 2-1.3:1.0 eth0: v1.12.13
10693 19:16:27.619713 <6>[ 4.041620] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10694 19:16:27.812229 <6>[ 4.233771] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10695 19:16:29.288760 <6>[ 5.714115] r8152 2-1.3:1.0 eth0: carrier on
10696 19:16:32.128596 <5>[ 5.741462] Sending DHCP requests .., OK
10697 19:16:32.134890 <6>[ 8.558187] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10698 19:16:32.138372 <6>[ 8.566504] IP-Config: Complete:
10699 19:16:32.151547 <6>[ 8.569999] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10700 19:16:32.158194 <6>[ 8.580712] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10701 19:16:32.165396 <6>[ 8.589333] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10702 19:16:32.171901 <6>[ 8.589342] nameserver0=192.168.201.1
10703 19:16:32.174702 <6>[ 8.601639] clk: Disabling unused clocks
10704 19:16:32.181685 <6>[ 8.606816] PM: genpd: Disabling unused power domains
10705 19:16:32.185184 <6>[ 8.612171] ALSA device list:
10706 19:16:32.188074 <6>[ 8.615412] No soundcards found.
10707 19:16:32.198878 <6>[ 8.624334] Freeing unused kernel memory: 10880K
10708 19:16:32.202354 <6>[ 8.629349] Run /init as init process
10709 19:16:32.233009 Starting syslogd: OK
10710 19:16:32.236969 Starting klogd: OK
10711 19:16:32.247032 Running sysctl: OK
10712 19:16:32.257396 Populating /dev using udev: <30>[ 8.682319] udevd[172]: starting version 3.2.9
10713 19:16:32.265806 <27>[ 8.690769] udevd[172]: specified user 'tss' unknown
10714 19:16:32.272059 <27>[ 8.696184] udevd[172]: specified group 'tss' unknown
10715 19:16:32.275613 <30>[ 8.702548] udevd[173]: starting eudev-3.2.9
10716 19:16:32.382452 <6>[ 8.807768] pstore: Using crash dump compression: deflate
10717 19:16:32.398109 <6>[ 8.823457] pstore: Registered ramoops as persistent store backend
10718 19:16:32.405156 <6>[ 8.830543] ramoops: using 0x100000@0xffe66000, ecc: 0
10719 19:16:32.508810 <6>[ 8.930598] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10720 19:16:32.516009 <6>[ 8.941308] remoteproc remoteproc0: scp is available
10721 19:16:32.522301 <6>[ 8.946757] remoteproc remoteproc0: powering up scp
10722 19:16:32.529519 <6>[ 8.951946] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10723 19:16:32.536013 <6>[ 8.960962] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10724 19:16:32.560312 <6>[ 8.982150] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10725 19:16:32.569853 <6>[ 8.990731] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10726 19:16:32.580112 <6>[ 9.000308] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10727 19:16:32.586250 <6>[ 9.005769] mediatek-mipi-tx 11e50000.dsi-phy: can't get nvmem_cell_get, ignore it
10728 19:16:32.613326 <6>[ 9.038617] Bluetooth: Core ver 2.22
10729 19:16:32.616365 <6>[ 9.042707] NET: Registered PF_BLUETOOTH protocol family
10730 19:16:32.626830 <6>[ 9.042861] sbs-battery 8-000b: sbs-battery: battery gas gauge device registered
10731 19:16:32.632949 <6>[ 9.048834] Bluetooth: HCI device and connection manager initialized
10732 19:16:32.636616 <6>[ 9.062806] Bluetooth: HCI socket layer initialized
10733 19:16:32.643002 <6>[ 9.068224] Bluetooth: L2CAP socket layer initialized
10734 19:16:32.646550 <6>[ 9.068759] mc: Linux media interface: v0.10
10735 19:16:32.652975 <6>[ 9.073980] Bluetooth: SCO socket layer initialized
10736 19:16:32.670590 <6>[ 9.092266] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10737 19:16:32.677247 <6>[ 9.092358] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10738 19:16:32.683262 <6>[ 9.092418] remoteproc remoteproc0: remote processor scp is now up
10739 19:16:32.693561 <4>[ 9.115864] sbs-battery 8-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10740 19:16:32.700524 <4>[ 9.115864] Fallback method does not support PEC.
10741 19:16:32.712529 <4>[ 9.134350] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
10742 19:16:32.719377 <6>[ 9.136637] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10743 19:16:32.725930 <4>[ 9.142527] elants_i2c 0-0010: supply vccio not found, using dummy regulator
10744 19:16:32.732149 <6>[ 9.143155] usbcore: registered new interface driver btusb
10745 19:16:32.739142 <6>[ 9.143552] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/ovl@14005000
10746 19:16:32.748943 <6>[ 9.143619] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/ovl@14006000
10747 19:16:32.758764 <6>[ 9.143656] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/rdma@14007000
10748 19:16:32.765931 <6>[ 9.143695] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/color@14009000
10749 19:16:32.775684 <6>[ 9.143735] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/ccorr@1400a000
10750 19:16:32.785282 <6>[ 9.143777] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/aal@1400b000
10751 19:16:32.792285 <6>[ 9.143819] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/gamma@1400c000
10752 19:16:32.801908 <6>[ 9.144056] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/dsi@14010000
10753 19:16:32.808712 <6>[ 9.144088] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/ovl@14014000
10754 19:16:32.818581 <6>[ 9.144125] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/rdma@14015000
10755 19:16:32.824963 <6>[ 9.148779] pci_bus 0000:00: root bus resource [bus 00-ff]
10756 19:16:32.831620 <6>[ 9.148788] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10757 19:16:32.841949 <6>[ 9.148791] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10758 19:16:32.848594 <6>[ 9.148841] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400 PCIe Root Port
10759 19:16:32.855348 <6>[ 9.148871] pci 0000:00:00.0: BAR 0 [mem 0x00000000-0x00003fff 64bit pref]
10760 19:16:32.861677 <6>[ 9.148887] pci 0000:00:00.0: PCI bridge to [bus 00]
10761 19:16:32.868610 <6>[ 9.148893] pci 0000:00:00.0: bridge window [io 0x0000-0x0fff]
10762 19:16:32.874959 <6>[ 9.148897] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff]
10763 19:16:32.881305 <6>[ 9.148908] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff 64bit pref]
10764 19:16:32.888400 <6>[ 9.149019] pci 0000:00:00.0: supports D1 D2
10765 19:16:32.898210 <4>[ 9.157557] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10766 19:16:32.904568 <6>[ 9.162109] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10767 19:16:32.913099 <3>[ 9.170931] Bluetooth: hci0: Failed to load firmware file (-2)
10768 19:16:32.919712 <6>[ 9.180970] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10769 19:16:32.926184 <3>[ 9.188052] Bluetooth: hci0: Failed to set up firmware (-2)
10770 19:16:32.932330 <6>[ 9.197813] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000 PCIe Endpoint
10771 19:16:32.938971 <6>[ 9.198935] panfrost 13000000.gpu: clock rate = 357999878
10772 19:16:32.945930 <6>[ 9.201494] panfrost 13000000.gpu: mali-g57 id 0x9093 major 0x0 minor 0x0 status 0x0
10773 19:16:32.955555 <6>[ 9.201500] panfrost 13000000.gpu: features: 00000000,000019f7, issues: 00000003,80000400
10774 19:16:32.965403 <6>[ 9.201504] panfrost 13000000.gpu: Features: L2:0x07130206 Shader:0x00000000 Tiler:0x00000809 Mem:0x101 MMU:0x00002830 AS:0xff JS:0x7
10775 19:16:32.972358 <6>[ 9.201508] panfrost 13000000.gpu: shader_present=0x50045 l2_present=0x1
10776 19:16:32.981957 <6>[ 9.202373] [drm] Initialized panfrost 1.2.0 20180908 for 13000000.gpu on minor 0
10777 19:16:32.992136 <4>[ 9.205816] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10778 19:16:32.999395 <6>[ 9.214468] pci 0000:01:00.0: BAR 0 [mem 0x00000000-0x000fffff 64bit pref]
10779 19:16:33.009332 <6>[ 9.214753] elan_i2c 2-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10780 19:16:33.019546 <6>[ 9.215878] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-2/2-0015/input/input2
10781 19:16:33.028968 <6>[ 9.269801] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-0/0-0010/input/input3
10782 19:16:33.035642 <6>[ 9.272091] pci 0000:01:00.0: BAR 2 [mem 0x00000000-0x00003fff 64bit pref]
10783 19:16:33.042611 <4>[ 9.303211] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10784 19:16:33.052319 <6>[ 9.305252] pci 0000:01:00.0: BAR 4 [mem 0x00000000-0x00000fff 64bit pref]
10785 19:16:33.055423 <6>[ 9.306701] videodev: Linux video capture interface: v2.00
10786 19:16:33.065649 <6>[ 9.314139] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10787 19:16:33.068572 <6>[ 9.317857] pci 0000:01:00.0: supports D1 D2
10788 19:16:33.078616 <6>[ 9.328301] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10789 19:16:33.085604 <6>[ 9.335147] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10790 19:16:33.092160 <3>[ 9.342937] power_supply sbs-8-000b: driver failed to report `time_to_empty_now' property: -5
10791 19:16:33.102086 <6>[ 9.350297] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10792 19:16:33.105507 <4>[ 9.384582] rt5682 1-001a: ASoC: source widget I2S1 overwritten
10793 19:16:33.115333 <6>[ 9.385101] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]: assigned
10794 19:16:33.125337 <6>[ 9.391242] cros-ec-dev cros-ec-dev.12.auto: CrOS System Control Processor MCU detected
10795 19:16:33.131588 <6>[ 9.392439] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10796 19:16:33.141861 <3>[ 9.430901] power_supply sbs-8-000b: driver failed to report `time_to_empty_now' property: -5
10797 19:16:33.148378 <6>[ 9.439897] pci 0000:00:00.0: BAR 0 [mem 0x12200000-0x12203fff 64bit pref]: assigned
10798 19:16:33.154844 <6>[ 9.440773] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10799 19:16:33.161274 <6>[ 9.442207] usbcore: registered new interface driver uvcvideo
10800 19:16:33.171459 <6>[ 9.592373] pci 0000:01:00.0: BAR 0 [mem 0x12000000-0x120fffff 64bit pref]: assigned
10801 19:16:33.178201 <6>[ 9.600507] pci 0000:01:00.0: BAR 2 [mem 0x12100000-0x12103fff 64bit pref]: assigned
10802 19:16:33.184842 <6>[ 9.608526] pci 0000:01:00.0: BAR 4 [mem 0x12104000-0x12104fff 64bit pref]: assigned
10803 19:16:33.191432 <6>[ 9.616536] pci 0000:00:00.0: PCI bridge to [bus 01]
10804 19:16:33.198083 <6>[ 9.621758] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10805 19:16:33.204913 <6>[ 9.629885] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10806 19:16:33.211372 <6>[ 9.637058] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10807 19:16:33.218305 <6>[ 9.644032] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10808 19:16:33.245423 <6>[ 9.667608] input: mt8192_mt6359_rt1015p_rt5682 Headset Jack as /devices/platform/sound/sound/card0/input4
10809 19:16:33.255307 <5>[ 9.667971] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10810 19:16:33.261737 <3>[ 9.681738] SVSB_GPU_LOW: cannot get "gpu-thermal" thermal zone
10811 19:16:33.268877 <3>[ 9.691861] mtk-svs 1100bc00.svs: error -ENODEV: svs bank resource setup fail
10812 19:16:33.280883 <6>[ 9.702604] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10813 19:16:33.287436 <5>[ 9.703572] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10814 19:16:33.293741 <6>[ 9.711010] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10815 19:16:33.303839 <6>[ 9.711018] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10816 19:16:33.310366 <5>[ 9.717432] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10817 19:16:33.320298 <6>[ 9.725398] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10818 19:16:33.326851 <4>[ 9.733803] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10819 19:16:33.337323 <6>[ 9.741159] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10820 19:16:33.343646 <6>[ 9.741167] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10821 19:16:33.350244 <6>[ 9.749730] cfg80211: failed to load regulatory.db
10822 19:16:33.357187 <6>[ 9.758368] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10823 19:16:33.367072 <6>[ 9.758373] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10824 19:16:33.373517 <6>[ 9.758378] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10825 19:16:33.383426 <6>[ 9.758384] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10826 19:16:33.390081 <6>[ 9.758390] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10827 19:16:33.400420 <6>[ 9.821788] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10828 19:16:33.406654 <6>[ 9.830135] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10829 19:16:33.416263 <6>[ 9.838481] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10830 19:16:33.423560 <6>[ 9.846851] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10831 19:16:33.461335 <6>[ 9.883233] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10832 19:16:33.467452 <6>[ 9.890765] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10833 19:16:33.474421 <6>[ 9.899608] mt7921e 0000:01:00.0: ASIC revision: 79610010
10834 19:16:33.574503 <6>[ 9.996131] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10835 19:16:33.574662 <6>[ 9.996131]
10836 19:16:33.600735 <6>[ 10.022542] panel-simple-dp-aux aux-3-0058: Detected IVO R140NWF5 RH (0x057d)
10837 19:16:33.610024 <6>[ 10.035467] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10838 19:16:33.621508 <6>[ 10.046627] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10839 19:16:33.624113 done
10840 19:16:33.631978 <6>[ 10.057444] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10841 19:16:33.645013 Saving random seed: <6>[ 10.067329] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10842 19:16:33.645177 OK
10843 19:16:33.659806 <6>[ 10.077351] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10844 19:16:33.676922 Starting network<6>[ 10.085113] mediatek-drm mediatek-drm.11.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops [mediatek_drm])
10845 19:16:33.717748 : <6>[ 10.096127] mediatek-drm mediatek-drm.11.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops [mediatek_drm])
10846 19:16:33.718141 ip: RTNETLINK an<6>[ 10.106862] mediatek-drm mediatek-drm.11.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops [mediatek_drm])
10847 19:16:33.718239 swers: File exis<6>[ 10.118851] mediatek-drm mediatek-drm.11.auto: bound 14009000.color (ops mtk_disp_color_component_ops [mediatek_drm])
10848 19:16:33.718307 ts
10849 19:16:33.718368 FAIL
10850 19:16:33.719043 Starti<6>[ 10.131075] mediatek-drm mediatek-drm.11.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops [mediatek_drm])
10851 19:16:33.737277 ng dropbear sshd<6>[ 10.143321] mediatek-drm mediatek-drm.11.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops [mediatek_drm])
10852 19:16:33.737668 : <6>[ 10.155210] mediatek-drm mediatek-drm.11.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops [mediatek_drm])
10853 19:16:33.740804 <6>[ 10.167317] NET: Registered PF_INET6 protocol family
10854 19:16:33.751169 <6>[ 10.168203] mediatek-drm mediatek-drm.11.auto: bound 14010000.dsi (ops mtk_dsi_component_ops [mediatek_drm])
10855 19:16:33.754754 <6>[ 10.173185] Segment Routing with IPv6
10856 19:16:33.769114 <6>[ 10.182614] mediatek-drm mediatek-drm.11.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops [mediatek_drm])
10857 19:16:33.769265 <6>[ 10.186542] In-situ OAM (IOAM) with IPv6
10858 19:16:33.782574 <6>[ 10.197040] mediatek-drm mediatek-drm.11.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops [mediatek_drm])
10859 19:16:33.793325 OK<6>[ 10.211937] mediatek-drm mediatek-drm.11.auto: Not creating crtc 1 because component 10 is disabled or missing
10860 19:16:33.793454
10861 19:16:33.799816 <6>[ 10.223336] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.11.auto on minor 1
10862 19:16:33.806897 /bin/sh: can't access tty; job control turned off
10863 19:16:33.807410 Matched prompt #10: / #
10865 19:16:33.807666 Kernel warnings or errors detected.
10866 19:16:33.807737 Setting prompt string to ['/ #']
10867 19:16:33.807829 end: 2.2.5.1 login-action (duration 00:00:11) [common]
10869 19:16:33.808095 end: 2.2.5 auto-login-action (duration 00:00:11) [common]
10870 19:16:33.808225 start: 2.2.6 expect-shell-connection (timeout 00:03:47) [common]
10871 19:16:33.808332 Setting prompt string to ['/ #']
10872 19:16:33.808410 Forcing a shell prompt, looking for ['/ #']
10874 19:16:33.858641 / #
10875 19:16:33.858820 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10876 19:16:33.858923 Waiting using forced prompt support (timeout 00:02:30)
10877 19:16:33.859042 <6>[ 10.265518] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10878 19:16:33.864109
10879 19:16:33.864392 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10880 19:16:33.864502 start: 2.2.7 export-device-env (timeout 00:03:47) [common]
10881 19:16:33.864606 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10882 19:16:33.864695 end: 2.2 depthcharge-retry (duration 00:01:13) [common]
10883 19:16:33.864778 end: 2 depthcharge-action (duration 00:01:13) [common]
10884 19:16:33.864866 start: 3 lava-test-retry (timeout 00:01:00) [common]
10885 19:16:33.864954 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10886 19:16:33.865033 Using namespace: common
10888 19:16:33.965360 / # #
10889 19:16:33.965526 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10890 19:16:33.970528 #
10891 19:16:33.970796 Using /lava-13888633
10893 19:16:34.071088 / # export SHELL=/bin/sh
10894 19:16:34.076482 export SHELL=/bin/sh
10896 19:16:34.177012 / # . /lava-13888633/environment
10897 19:16:34.181810 . /lava-13888633/environment
10899 19:16:34.282386 / # /lava-13888633/bin/lava-test-runner /lava-13888633/0
10900 19:16:34.282541 Test shell timeout: 10s (minimum of the action and connection timeout)
10901 19:16:34.282979 <6>[ 10.607310] Console: switching to colour frame buffer device 240x67
10902 19:16:34.283055 <6>[ 10.631993] mediatek-drm mediatek-drm.11.auto: [drm] fb0: mediatekdrmfb frame buffer device
10903 19:16:34.283120 <6>[ 10.664090] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 1
10904 19:16:34.283182 <4>[ 10.670773] ttyS ttyS0: 1 input overrun(s)
10905 19:16:34.283242 /lava-13888633/bin/lava-test-run<6>[ 10.678247] mtk-vcodec-dec 16000000.video-codec: Adding to iommu group 1
10906 19:16:34.324539 <6>[ 10.708247] mtk-vdec-comp 16010000.video-codec: Adding to iommu group 1
10907 19:16:34.324699 <6>[ 10.715666] mtk-vdec-comp 16025000.video-codec: Adding to iommu group 1
10908 19:16:34.324783
10909 19:16:34.324846 /bin/sh: /lava-13888633/bin/lava-test-run: not found
10910 19:16:34.668194 / # <6>[ 11.094031] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10911 19:17:03.577619 <6>[ 40.009832] vpu: disabling
10912 19:17:03.581092 <6>[ 40.012898] vproc2: disabling
10913 19:17:03.584218 <6>[ 40.016250] vproc1: disabling
10914 19:17:03.587873 <6>[ 40.019547] vaud18: disabling
10915 19:17:03.591241 <6>[ 40.023224] va09: disabling
10916 19:17:03.594147 <6>[ 40.026384] vsram_md: disabling
10917 19:17:03.605537 <6>[ 40.034137] pp1000_dpbrdg: disabling
10918 19:17:03.608298 <6>[ 40.037986] pp1800_dpbrdg: disabling
10919 19:17:03.611818 <6>[ 40.041852] pp3300_dpbrdg: disabling
10921 19:17:33.865195 end: 3.1 lava-test-shell (duration 00:01:00) [common]
10923 19:17:33.865491 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
10925 19:17:33.865732 end: 3 lava-test-retry (duration 00:01:00) [common]
10927 19:17:33.866080 Cleaning after the job
10928 19:17:33.866206 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13888633/tftp-deploy-lq2x80os/ramdisk
10929 19:17:33.869175 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13888633/tftp-deploy-lq2x80os/kernel
10930 19:17:33.882431 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13888633/tftp-deploy-lq2x80os/dtb
10931 19:17:33.882632 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13888633/tftp-deploy-lq2x80os/modules
10932 19:17:33.890141 start: 4.1 power-off (timeout 00:00:30) [common]
10933 19:17:33.890345 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
10934 19:17:33.968488 >> Command sent successfully.
10935 19:17:33.971009 Returned 0 in 0 seconds
10936 19:17:34.071432 end: 4.1 power-off (duration 00:00:00) [common]
10938 19:17:34.071801 start: 4.2 read-feedback (timeout 00:10:00) [common]
10939 19:17:34.072075 Listened to connection for namespace 'common' for up to 1s
10940 19:17:35.072440 Finalising connection for namespace 'common'
10941 19:17:35.072610 Disconnecting from shell: Finalise
10942 19:17:35.172958 end: 4.2 read-feedback (duration 00:00:01) [common]
10943 19:17:35.173107 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13888633
10944 19:17:35.218965 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13888633
10945 19:17:35.219187 TestError: A test failed to run, look at the error message.