Boot log: mt8192-asurada-spherion-r0
- Warnings: 3
- Kernel Warnings: 99
- Errors: 2
- Kernel Errors: 6
- Boot result: FAIL
1 22:52:53.981372 lava-dispatcher, installed at version: 2024.03
2 22:52:53.981583 start: 0 validate
3 22:52:53.981727 Start time: 2024-05-18 22:52:53.981719+00:00 (UTC)
4 22:52:53.981852 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:52:53.981982 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 22:52:54.243255 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:52:54.243967 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.9-8995-g0450d2083be6b%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:52:54.507692 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:52:54.508523 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.9-8995-g0450d2083be6b%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:53:08.589241 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:53:08.590158 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.9-8995-g0450d2083be6b%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:53:09.109574 validate duration: 15.13
14 22:53:09.110924 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:53:09.111516 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:53:09.112038 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:53:09.112670 Not decompressing ramdisk as can be used compressed.
18 22:53:09.113144 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 22:53:09.113503 saving as /var/lib/lava/dispatcher/tmp/13891089/tftp-deploy-o5quonh9/ramdisk/rootfs.cpio.gz
20 22:53:09.113858 total size: 8181887 (7 MB)
21 22:53:11.514750 progress 0 % (0 MB)
22 22:53:11.527767 progress 5 % (0 MB)
23 22:53:11.540127 progress 10 % (0 MB)
24 22:53:11.547870 progress 15 % (1 MB)
25 22:53:11.553308 progress 20 % (1 MB)
26 22:53:11.557765 progress 25 % (1 MB)
27 22:53:11.561420 progress 30 % (2 MB)
28 22:53:11.565202 progress 35 % (2 MB)
29 22:53:11.568417 progress 40 % (3 MB)
30 22:53:11.571730 progress 45 % (3 MB)
31 22:53:11.574631 progress 50 % (3 MB)
32 22:53:11.577328 progress 55 % (4 MB)
33 22:53:11.579592 progress 60 % (4 MB)
34 22:53:11.582188 progress 65 % (5 MB)
35 22:53:11.584419 progress 70 % (5 MB)
36 22:53:11.586659 progress 75 % (5 MB)
37 22:53:11.588678 progress 80 % (6 MB)
38 22:53:11.590872 progress 85 % (6 MB)
39 22:53:11.592866 progress 90 % (7 MB)
40 22:53:11.595232 progress 95 % (7 MB)
41 22:53:11.597259 progress 100 % (7 MB)
42 22:53:11.597455 7 MB downloaded in 2.48 s (3.14 MB/s)
43 22:53:11.597608 end: 1.1.1 http-download (duration 00:00:02) [common]
45 22:53:11.597846 end: 1.1 download-retry (duration 00:00:02) [common]
46 22:53:11.597932 start: 1.2 download-retry (timeout 00:09:58) [common]
47 22:53:11.598015 start: 1.2.1 http-download (timeout 00:09:58) [common]
48 22:53:11.598148 downloading http://storage.kernelci.org/mainline/master/v6.9-8995-g0450d2083be6b/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:53:11.598257 saving as /var/lib/lava/dispatcher/tmp/13891089/tftp-deploy-o5quonh9/kernel/Image
50 22:53:11.598318 total size: 61108736 (58 MB)
51 22:53:11.598378 No compression specified
52 22:53:11.599606 progress 0 % (0 MB)
53 22:53:11.615553 progress 5 % (2 MB)
54 22:53:11.631184 progress 10 % (5 MB)
55 22:53:11.646925 progress 15 % (8 MB)
56 22:53:11.662712 progress 20 % (11 MB)
57 22:53:11.678350 progress 25 % (14 MB)
58 22:53:11.693882 progress 30 % (17 MB)
59 22:53:11.709642 progress 35 % (20 MB)
60 22:53:11.725309 progress 40 % (23 MB)
61 22:53:11.741140 progress 45 % (26 MB)
62 22:53:11.756631 progress 50 % (29 MB)
63 22:53:11.772250 progress 55 % (32 MB)
64 22:53:11.788058 progress 60 % (34 MB)
65 22:53:11.803871 progress 65 % (37 MB)
66 22:53:11.819603 progress 70 % (40 MB)
67 22:53:11.835397 progress 75 % (43 MB)
68 22:53:11.851002 progress 80 % (46 MB)
69 22:53:11.866683 progress 85 % (49 MB)
70 22:53:11.882322 progress 90 % (52 MB)
71 22:53:11.897814 progress 95 % (55 MB)
72 22:53:11.913322 progress 100 % (58 MB)
73 22:53:11.913600 58 MB downloaded in 0.32 s (184.85 MB/s)
74 22:53:11.913758 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:53:11.913994 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:53:11.914081 start: 1.3 download-retry (timeout 00:09:57) [common]
78 22:53:11.914198 start: 1.3.1 http-download (timeout 00:09:57) [common]
79 22:53:11.914348 downloading http://storage.kernelci.org/mainline/master/v6.9-8995-g0450d2083be6b/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:53:11.914417 saving as /var/lib/lava/dispatcher/tmp/13891089/tftp-deploy-o5quonh9/dtb/mt8192-asurada-spherion-r0.dtb
81 22:53:11.914477 total size: 65308 (0 MB)
82 22:53:11.914536 No compression specified
83 22:53:11.915602 progress 50 % (0 MB)
84 22:53:11.962318 progress 100 % (0 MB)
85 22:53:11.962645 0 MB downloaded in 0.05 s (1.29 MB/s)
86 22:53:11.962804 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:53:11.963032 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:53:11.963120 start: 1.4 download-retry (timeout 00:09:57) [common]
90 22:53:11.963203 start: 1.4.1 http-download (timeout 00:09:57) [common]
91 22:53:11.963335 downloading http://storage.kernelci.org/mainline/master/v6.9-8995-g0450d2083be6b/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:53:11.963404 saving as /var/lib/lava/dispatcher/tmp/13891089/tftp-deploy-o5quonh9/modules/modules.tar
93 22:53:11.963463 total size: 10164968 (9 MB)
94 22:53:11.963524 Using unxz to decompress xz
95 22:53:11.967804 progress 0 % (0 MB)
96 22:53:11.993873 progress 5 % (0 MB)
97 22:53:12.025310 progress 10 % (1 MB)
98 22:53:12.054537 progress 15 % (1 MB)
99 22:53:12.085137 progress 20 % (1 MB)
100 22:53:12.111711 progress 25 % (2 MB)
101 22:53:12.142291 progress 30 % (2 MB)
102 22:53:12.170858 progress 35 % (3 MB)
103 22:53:12.201214 progress 40 % (3 MB)
104 22:53:12.231012 progress 45 % (4 MB)
105 22:53:12.261797 progress 50 % (4 MB)
106 22:53:12.292014 progress 55 % (5 MB)
107 22:53:12.322338 progress 60 % (5 MB)
108 22:53:12.350653 progress 65 % (6 MB)
109 22:53:12.382055 progress 70 % (6 MB)
110 22:53:12.416602 progress 75 % (7 MB)
111 22:53:12.449353 progress 80 % (7 MB)
112 22:53:12.476249 progress 85 % (8 MB)
113 22:53:12.505335 progress 90 % (8 MB)
114 22:53:12.533071 progress 95 % (9 MB)
115 22:53:12.562134 progress 100 % (9 MB)
116 22:53:12.566954 9 MB downloaded in 0.60 s (16.06 MB/s)
117 22:53:12.567202 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:53:12.567461 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:53:12.567556 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 22:53:12.567649 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 22:53:12.567731 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:53:12.567818 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 22:53:12.568050 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b
125 22:53:12.568183 makedir: /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin
126 22:53:12.568287 makedir: /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/tests
127 22:53:12.568385 makedir: /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/results
128 22:53:12.568498 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-add-keys
129 22:53:12.568645 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-add-sources
130 22:53:12.568777 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-background-process-start
131 22:53:12.568909 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-background-process-stop
132 22:53:12.569035 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-common-functions
133 22:53:12.569160 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-echo-ipv4
134 22:53:12.569284 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-install-packages
135 22:53:12.569408 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-installed-packages
136 22:53:12.569531 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-os-build
137 22:53:12.569654 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-probe-channel
138 22:53:12.569778 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-probe-ip
139 22:53:12.569901 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-target-ip
140 22:53:12.570024 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-target-mac
141 22:53:12.570147 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-target-storage
142 22:53:12.570282 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-test-case
143 22:53:12.570408 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-test-event
144 22:53:12.570530 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-test-feedback
145 22:53:12.570651 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-test-raise
146 22:53:12.570773 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-test-reference
147 22:53:12.570897 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-test-runner
148 22:53:12.571019 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-test-set
149 22:53:12.571146 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-test-shell
150 22:53:12.571271 Updating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-install-packages (oe)
151 22:53:12.571422 Updating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/bin/lava-installed-packages (oe)
152 22:53:12.571544 Creating /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/environment
153 22:53:12.571652 LAVA metadata
154 22:53:12.571724 - LAVA_JOB_ID=13891089
155 22:53:12.571788 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:53:12.571907 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:57) [common]
157 22:53:12.571975 skipped lava-vland-overlay
158 22:53:12.572048 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:53:12.572131 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:57) [common]
160 22:53:12.572195 skipped lava-multinode-overlay
161 22:53:12.572266 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:53:12.572350 start: 1.5.2.3 test-definition (timeout 00:09:57) [common]
163 22:53:12.572422 Loading test definitions
164 22:53:12.572513 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:57) [common]
165 22:53:12.572587 Using /lava-13891089 at stage 0
166 22:53:12.572907 uuid=13891089_1.5.2.3.1 testdef=None
167 22:53:12.572994 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:53:12.573079 start: 1.5.2.3.2 test-overlay (timeout 00:09:57) [common]
169 22:53:12.573611 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:53:12.573839 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:57) [common]
172 22:53:12.574488 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:53:12.574713 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:57) [common]
175 22:53:12.575329 runner path: /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/0/tests/0_dmesg test_uuid 13891089_1.5.2.3.1
176 22:53:12.575487 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:53:12.575692 Creating lava-test-runner.conf files
179 22:53:12.575756 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13891089/lava-overlay-6w_hy30b/lava-13891089/0 for stage 0
180 22:53:12.575843 - 0_dmesg
181 22:53:12.575947 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:53:12.576038 start: 1.5.2.4 compress-overlay (timeout 00:09:57) [common]
183 22:53:12.583292 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:53:12.583412 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:57) [common]
185 22:53:12.583501 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:53:12.583586 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:53:12.583672 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
188 22:53:12.823377 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 22:53:12.823755 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
190 22:53:12.823874 extracting modules file /var/lib/lava/dispatcher/tmp/13891089/tftp-deploy-o5quonh9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13891089/extract-overlay-ramdisk-4dx3lodc/ramdisk
191 22:53:13.080682 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:53:13.080859 start: 1.5.5 apply-overlay-tftp (timeout 00:09:56) [common]
193 22:53:13.080951 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13891089/compress-overlay-i7dn802u/overlay-1.5.2.4.tar.gz to ramdisk
194 22:53:13.081018 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13891089/compress-overlay-i7dn802u/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13891089/extract-overlay-ramdisk-4dx3lodc/ramdisk
195 22:53:13.087585 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:53:13.087704 start: 1.5.6 configure-preseed-file (timeout 00:09:56) [common]
197 22:53:13.087791 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:53:13.087881 start: 1.5.7 compress-ramdisk (timeout 00:09:56) [common]
199 22:53:13.087958 Building ramdisk /var/lib/lava/dispatcher/tmp/13891089/extract-overlay-ramdisk-4dx3lodc/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13891089/extract-overlay-ramdisk-4dx3lodc/ramdisk
200 22:53:13.526901 >> 165359 blocks
201 22:53:16.105156 rename /var/lib/lava/dispatcher/tmp/13891089/extract-overlay-ramdisk-4dx3lodc/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13891089/tftp-deploy-o5quonh9/ramdisk/ramdisk.cpio.gz
202 22:53:16.105605 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 22:53:16.105724 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 22:53:16.105825 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 22:53:16.105933 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/13891089/tftp-deploy-o5quonh9/kernel/Image']
206 22:53:31.217854 Returned 0 in 15 seconds
207 22:53:31.318522 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13891089/tftp-deploy-o5quonh9/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13891089/tftp-deploy-o5quonh9/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13891089/tftp-deploy-o5quonh9/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13891089/tftp-deploy-o5quonh9/kernel/image.itb
208 22:53:31.761021 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:53:31.761388 output: Created: Sat May 18 23:53:31 2024
210 22:53:31.761456 output: Image 0 (kernel-1)
211 22:53:31.761580 output: Description:
212 22:53:31.761671 output: Created: Sat May 18 23:53:31 2024
213 22:53:31.761757 output: Type: Kernel Image
214 22:53:31.761845 output: Compression: lzma compressed
215 22:53:31.761930 output: Data Size: 13892383 Bytes = 13566.78 KiB = 13.25 MiB
216 22:53:31.762017 output: Architecture: AArch64
217 22:53:31.762103 output: OS: Linux
218 22:53:31.762211 output: Load Address: 0x00000000
219 22:53:31.762286 output: Entry Point: 0x00000000
220 22:53:31.762343 output: Hash algo: crc32
221 22:53:31.762398 output: Hash value: 1df669d5
222 22:53:31.762450 output: Image 1 (fdt-1)
223 22:53:31.762505 output: Description: mt8192-asurada-spherion-r0
224 22:53:31.762560 output: Created: Sat May 18 23:53:31 2024
225 22:53:31.762613 output: Type: Flat Device Tree
226 22:53:31.762667 output: Compression: uncompressed
227 22:53:31.762717 output: Data Size: 65308 Bytes = 63.78 KiB = 0.06 MiB
228 22:53:31.762769 output: Architecture: AArch64
229 22:53:31.762819 output: Hash algo: crc32
230 22:53:31.762869 output: Hash value: 5ff524f6
231 22:53:31.762920 output: Image 2 (ramdisk-1)
232 22:53:31.762971 output: Description: unavailable
233 22:53:31.763021 output: Created: Sat May 18 23:53:31 2024
234 22:53:31.763072 output: Type: RAMDisk Image
235 22:53:31.763123 output: Compression: Unknown Compression
236 22:53:31.763174 output: Data Size: 23854042 Bytes = 23294.96 KiB = 22.75 MiB
237 22:53:31.763225 output: Architecture: AArch64
238 22:53:31.763275 output: OS: Linux
239 22:53:31.763326 output: Load Address: unavailable
240 22:53:31.763376 output: Entry Point: unavailable
241 22:53:31.763426 output: Hash algo: crc32
242 22:53:31.763476 output: Hash value: 69a552e7
243 22:53:31.763527 output: Default Configuration: 'conf-1'
244 22:53:31.763578 output: Configuration 0 (conf-1)
245 22:53:31.763628 output: Description: mt8192-asurada-spherion-r0
246 22:53:31.763678 output: Kernel: kernel-1
247 22:53:31.763729 output: Init Ramdisk: ramdisk-1
248 22:53:31.763779 output: FDT: fdt-1
249 22:53:31.763829 output: Loadables: kernel-1
250 22:53:31.763879 output:
251 22:53:31.764083 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 22:53:31.764177 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 22:53:31.764279 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 22:53:31.764371 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 22:53:31.764444 No LXC device requested
256 22:53:31.764520 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:53:31.764602 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 22:53:31.764674 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:53:31.764738 Checking files for TFTP limit of 4294967296 bytes.
260 22:53:31.765251 end: 1 tftp-deploy (duration 00:00:23) [common]
261 22:53:31.765353 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:53:31.765447 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:53:31.765570 substitutions:
264 22:53:31.765634 - {DTB}: 13891089/tftp-deploy-o5quonh9/dtb/mt8192-asurada-spherion-r0.dtb
265 22:53:31.765695 - {INITRD}: 13891089/tftp-deploy-o5quonh9/ramdisk/ramdisk.cpio.gz
266 22:53:31.765753 - {KERNEL}: 13891089/tftp-deploy-o5quonh9/kernel/Image
267 22:53:31.765808 - {LAVA_MAC}: None
268 22:53:31.765863 - {PRESEED_CONFIG}: None
269 22:53:31.765916 - {PRESEED_LOCAL}: None
270 22:53:31.765969 - {RAMDISK}: 13891089/tftp-deploy-o5quonh9/ramdisk/ramdisk.cpio.gz
271 22:53:31.766022 - {ROOT_PART}: None
272 22:53:31.766074 - {ROOT}: None
273 22:53:31.766128 - {SERVER_IP}: 192.168.201.1
274 22:53:31.766203 - {TEE}: None
275 22:53:31.766269 Parsed boot commands:
276 22:53:31.766321 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:53:31.766491 Parsed boot commands: tftpboot 192.168.201.1 13891089/tftp-deploy-o5quonh9/kernel/image.itb 13891089/tftp-deploy-o5quonh9/kernel/cmdline
278 22:53:31.766577 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:53:31.766661 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:53:31.766753 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:53:31.766838 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:53:31.766909 Not connected, no need to disconnect.
283 22:53:31.766981 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:53:31.767063 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:53:31.767128 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 22:53:31.770751 Setting prompt string to ['lava-test: # ']
287 22:53:31.771105 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:53:31.771204 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:53:31.771304 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:53:31.771436 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:53:31.771660 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
292 22:53:45.414516 Returned 0 in 13 seconds
293 22:53:45.515284 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 22:53:45.515987 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 22:53:45.516130 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 22:53:45.516250 Setting prompt string to 'Starting depthcharge on Spherion...'
298 22:53:45.516352 Changing prompt to 'Starting depthcharge on Spherion...'
299 22:53:45.516458 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 22:53:45.517062 [Enter `^Ec?' for help]
301 22:53:45.517175
302 22:53:45.517273 F0: 102B 0000
303 22:53:45.517364
304 22:53:45.517455 F3: 1001 0000 [0200]
305 22:53:45.517583
306 22:53:45.517669 F3: 1001 0000
307 22:53:45.517759
308 22:53:45.517846 F7: 102D 0000
309 22:53:45.517933
310 22:53:45.518018 F1: 0000 0000
311 22:53:45.518104
312 22:53:45.518219 V0: 0000 0000 [0001]
313 22:53:45.518319
314 22:53:45.518405 00: 0007 8000
315 22:53:45.518496
316 22:53:45.518581 01: 0000 0000
317 22:53:45.518669
318 22:53:45.518771 BP: 0C00 0209 [0000]
319 22:53:45.518870
320 22:53:45.518953 G0: 1182 0000
321 22:53:45.519038
322 22:53:45.519122 EC: 0000 0021 [4000]
323 22:53:45.519207
324 22:53:45.519291 S7: 0000 0000 [0000]
325 22:53:45.519375
326 22:53:45.519460 CC: 0000 0000 [0001]
327 22:53:45.519544
328 22:53:45.519629 T0: 0000 0040 [010F]
329 22:53:45.519714
330 22:53:45.519798 Jump to BL
331 22:53:45.519883
332 22:53:45.519965
333 22:53:45.520048
334 22:53:45.520133 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
335 22:53:45.520222 ARM64: Exception handlers installed.
336 22:53:45.520310 ARM64: Testing exception
337 22:53:45.520397 ARM64: Done test exception
338 22:53:45.520484 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
339 22:53:45.520572 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
340 22:53:45.520659 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
341 22:53:45.520748 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
342 22:53:45.520834 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
343 22:53:45.520923 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
344 22:53:45.521039 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
345 22:53:45.521127 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
346 22:53:45.521213 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
347 22:53:45.521300 WDT: Last reset was cold boot
348 22:53:45.521386 SPI1(PAD0) initialized at 2873684 Hz
349 22:53:45.521472 SPI5(PAD0) initialized at 992727 Hz
350 22:53:45.521559 VBOOT: Loading verstage.
351 22:53:45.521646 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
352 22:53:45.521733 FMAP: Found "FLASH" version 1.1 at 0x20000.
353 22:53:45.521820 FMAP: base = 0x0 size = 0x800000 #areas = 25
354 22:53:45.521905 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
355 22:53:45.521991 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
356 22:53:45.522077 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
357 22:53:45.522168 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
358 22:53:45.522291
359 22:53:45.522376
360 22:53:45.522462 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
361 22:53:45.522548 ARM64: Exception handlers installed.
362 22:53:45.522635 ARM64: Testing exception
363 22:53:45.522720 ARM64: Done test exception
364 22:53:45.522805 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
365 22:53:45.522891 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
366 22:53:45.522976 Probing TPM: . done!
367 22:53:45.523062 TPM ready after 0 ms
368 22:53:45.523146 Connected to device vid:did:rid of 1ae0:0028:00
369 22:53:45.523262 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
370 22:53:45.523350 Initialized TPM device CR50 revision 0
371 22:53:45.523435 tlcl_send_startup: Startup return code is 0
372 22:53:45.523521 TPM: setup succeeded
373 22:53:45.523607 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
374 22:53:45.523693 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
375 22:53:45.523778 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
376 22:53:45.523863 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 22:53:45.523949 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
378 22:53:45.524035 in-header: 03 07 00 00 08 00 00 00
379 22:53:45.524120 in-data: aa e4 47 04 13 02 00 00
380 22:53:45.524207 Chrome EC: UHEPI supported
381 22:53:45.524293 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
382 22:53:45.524381 in-header: 03 a9 00 00 08 00 00 00
383 22:53:45.524467 in-data: 84 60 60 08 00 00 00 00
384 22:53:45.524551 Phase 1
385 22:53:45.524636 FMAP: area GBB found @ 3f5000 (12032 bytes)
386 22:53:45.524721 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
387 22:53:45.524808 VB2:vb2_check_recovery() Recovery was requested manually
388 22:53:45.524895 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
389 22:53:45.524980 Recovery requested (1009000e)
390 22:53:45.525065 TPM: Extending digest for VBOOT: boot mode into PCR 0
391 22:53:45.525151 tlcl_extend: response is 0
392 22:53:45.525266 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
393 22:53:45.525351 tlcl_extend: response is 0
394 22:53:45.525436 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
395 22:53:45.525522 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
396 22:53:45.525607 BS: bootblock times (exec / console): total (unknown) / 148 ms
397 22:53:45.525693
398 22:53:45.525776
399 22:53:45.525861 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
400 22:53:45.525948 ARM64: Exception handlers installed.
401 22:53:45.526033 ARM64: Testing exception
402 22:53:45.526118 ARM64: Done test exception
403 22:53:45.526242 pmic_efuse_setting: Set efuses in 11 msecs
404 22:53:45.526328 pmwrap_interface_init: Select PMIF_VLD_RDY
405 22:53:45.526413 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
406 22:53:45.526708 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
407 22:53:45.526842 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
408 22:53:45.526932 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
409 22:53:45.527020 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
410 22:53:45.527107 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
411 22:53:45.527223 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
412 22:53:45.527309 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
413 22:53:45.527395 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
414 22:53:45.527482 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
415 22:53:45.527569 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
416 22:53:45.527653 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
417 22:53:45.527763 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
418 22:53:45.527863 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
419 22:53:45.527949 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
420 22:53:45.528034 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
421 22:53:45.528120 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
422 22:53:45.528232 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
423 22:53:45.528317 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
424 22:53:45.528402 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
425 22:53:45.528488 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
426 22:53:45.528573 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
427 22:53:45.528658 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
428 22:53:45.528744 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
429 22:53:45.528838 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
430 22:53:45.528925 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
431 22:53:45.529011 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
432 22:53:45.529097 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
433 22:53:45.529181 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
434 22:53:45.529265 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
435 22:53:45.529351 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
436 22:53:45.529435 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
437 22:53:45.529520 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
438 22:53:45.529605 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
439 22:53:45.529690 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
440 22:53:45.529774 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
441 22:53:45.529860 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
442 22:53:45.529974 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
443 22:53:45.530059 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
444 22:53:45.530143 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
445 22:53:45.530269 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
446 22:53:45.530353 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
447 22:53:45.530438 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
448 22:53:45.530523 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
449 22:53:45.530607 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
450 22:53:45.530692 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
451 22:53:45.530777 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
452 22:53:45.530861 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
453 22:53:45.530947 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
454 22:53:45.531033 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
455 22:53:45.531119 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
456 22:53:45.531204 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
457 22:53:45.531290 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
458 22:53:45.531377 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
459 22:53:45.531462 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
460 22:53:45.531549 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
461 22:53:45.531636 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
462 22:53:45.531720 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
463 22:53:45.531804 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 22:53:45.531889 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x32
465 22:53:45.531974 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
466 22:53:45.532058 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
467 22:53:45.532143 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
468 22:53:45.532227 [RTC]rtc_get_frequency_meter,154: input=15, output=835
469 22:53:45.532327 [RTC]rtc_get_frequency_meter,154: input=7, output=708
470 22:53:45.532425 [RTC]rtc_get_frequency_meter,154: input=11, output=772
471 22:53:45.532512 [RTC]rtc_get_frequency_meter,154: input=13, output=803
472 22:53:45.532597 [RTC]rtc_get_frequency_meter,154: input=12, output=788
473 22:53:45.532682 [RTC]rtc_get_frequency_meter,154: input=12, output=787
474 22:53:45.532767 [RTC]rtc_get_frequency_meter,154: input=13, output=802
475 22:53:45.532851 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
476 22:53:45.533144 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
477 22:53:45.533246 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
478 22:53:45.533335 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
479 22:53:45.533423 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
480 22:53:45.533510 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
481 22:53:45.533595 ADC[4]: Raw value=904509 ID=7
482 22:53:45.533682 ADC[3]: Raw value=213282 ID=1
483 22:53:45.533769 RAM Code: 0x71
484 22:53:45.533855 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
485 22:53:45.533974 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
486 22:53:45.534061 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
487 22:53:45.534170 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
488 22:53:45.534272 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
489 22:53:45.534358 in-header: 03 07 00 00 08 00 00 00
490 22:53:45.534443 in-data: aa e4 47 04 13 02 00 00
491 22:53:45.534527 Chrome EC: UHEPI supported
492 22:53:45.534612 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
493 22:53:45.534714 in-header: 03 a9 00 00 08 00 00 00
494 22:53:45.534813 in-data: 84 60 60 08 00 00 00 00
495 22:53:45.534898 MRC: failed to locate region type 0.
496 22:53:45.534984 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
497 22:53:45.535072 DRAM-K: Running full calibration
498 22:53:45.535159 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
499 22:53:45.535244 header.status = 0x0
500 22:53:45.535328 header.version = 0x6 (expected: 0x6)
501 22:53:45.535413 header.size = 0xd00 (expected: 0xd00)
502 22:53:45.535498 header.flags = 0x0
503 22:53:45.535583 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
504 22:53:45.535668 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
505 22:53:45.535753 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
506 22:53:45.535837 dram_init: ddr_geometry: 2
507 22:53:45.535921 [EMI] MDL number = 2
508 22:53:45.536006 [EMI] Get MDL freq = 0
509 22:53:45.536091 dram_init: ddr_type: 0
510 22:53:45.536175 is_discrete_lpddr4: 1
511 22:53:45.536259 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
512 22:53:45.536344
513 22:53:45.536427
514 22:53:45.536511 [Bian_co] ETT version 0.0.0.1
515 22:53:45.536596 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
516 22:53:45.536682
517 22:53:45.536767 dramc_set_vcore_voltage set vcore to 650000
518 22:53:45.536852 Read voltage for 800, 4
519 22:53:45.536936 Vio18 = 0
520 22:53:45.537058 Vcore = 650000
521 22:53:45.537142 Vdram = 0
522 22:53:45.537226 Vddq = 0
523 22:53:45.537310 Vmddr = 0
524 22:53:45.537394 dram_init: config_dvfs: 1
525 22:53:45.537479 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
526 22:53:45.537565 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
527 22:53:45.537651 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
528 22:53:45.537735 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
529 22:53:45.537821 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
530 22:53:45.537907 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
531 22:53:45.537992 MEM_TYPE=3, freq_sel=18
532 22:53:45.538076 sv_algorithm_assistance_LP4_1600
533 22:53:45.538170 ============ PULL DRAM RESETB DOWN ============
534 22:53:45.538258 ========== PULL DRAM RESETB DOWN end =========
535 22:53:45.538344 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
536 22:53:45.538447 ===================================
537 22:53:45.538548 LPDDR4 DRAM CONFIGURATION
538 22:53:45.538633 ===================================
539 22:53:45.538718 EX_ROW_EN[0] = 0x0
540 22:53:45.538802 EX_ROW_EN[1] = 0x0
541 22:53:45.538888 LP4Y_EN = 0x0
542 22:53:45.538974 WORK_FSP = 0x0
543 22:53:45.539061 WL = 0x2
544 22:53:45.539146 RL = 0x2
545 22:53:45.539231 BL = 0x2
546 22:53:45.539314 RPST = 0x0
547 22:53:45.539400 RD_PRE = 0x0
548 22:53:45.539484 WR_PRE = 0x1
549 22:53:45.539570 WR_PST = 0x0
550 22:53:45.539656 DBI_WR = 0x0
551 22:53:45.539740 DBI_RD = 0x0
552 22:53:45.539823 OTF = 0x1
553 22:53:45.539909 ===================================
554 22:53:45.539993 ===================================
555 22:53:45.540078 ANA top config
556 22:53:45.540167 ===================================
557 22:53:45.540254 DLL_ASYNC_EN = 0
558 22:53:45.540339 ALL_SLAVE_EN = 1
559 22:53:45.540423 NEW_RANK_MODE = 1
560 22:53:45.540510 DLL_IDLE_MODE = 1
561 22:53:45.540595 LP45_APHY_COMB_EN = 1
562 22:53:45.540679 TX_ODT_DIS = 1
563 22:53:45.540764 NEW_8X_MODE = 1
564 22:53:45.540848 ===================================
565 22:53:45.540932 ===================================
566 22:53:45.541016 data_rate = 1600
567 22:53:45.541101 CKR = 1
568 22:53:45.541187 DQ_P2S_RATIO = 8
569 22:53:45.541271 ===================================
570 22:53:45.541355 CA_P2S_RATIO = 8
571 22:53:45.541440 DQ_CA_OPEN = 0
572 22:53:45.541524 DQ_SEMI_OPEN = 0
573 22:53:45.541608 CA_SEMI_OPEN = 0
574 22:53:45.541692 CA_FULL_RATE = 0
575 22:53:45.541775 DQ_CKDIV4_EN = 1
576 22:53:45.541859 CA_CKDIV4_EN = 1
577 22:53:45.541944 CA_PREDIV_EN = 0
578 22:53:45.542028 PH8_DLY = 0
579 22:53:45.542112 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
580 22:53:45.542233 DQ_AAMCK_DIV = 4
581 22:53:45.542317 CA_AAMCK_DIV = 4
582 22:53:45.542401 CA_ADMCK_DIV = 4
583 22:53:45.542485 DQ_TRACK_CA_EN = 0
584 22:53:45.542569 CA_PICK = 800
585 22:53:45.542654 CA_MCKIO = 800
586 22:53:45.542738 MCKIO_SEMI = 0
587 22:53:45.542822 PLL_FREQ = 3068
588 22:53:45.542908 DQ_UI_PI_RATIO = 32
589 22:53:45.542992 CA_UI_PI_RATIO = 0
590 22:53:45.543077 ===================================
591 22:53:45.543164 ===================================
592 22:53:45.543249 memory_type:LPDDR4
593 22:53:45.543334 GP_NUM : 10
594 22:53:45.543419 SRAM_EN : 1
595 22:53:45.543503 MD32_EN : 0
596 22:53:45.543835 ===================================
597 22:53:45.543947 [ANA_INIT] >>>>>>>>>>>>>>
598 22:53:45.544036 <<<<<< [CONFIGURE PHASE]: ANA_TX
599 22:53:45.544128 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
600 22:53:45.544215 ===================================
601 22:53:45.544303 data_rate = 1600,PCW = 0X7600
602 22:53:45.544390 ===================================
603 22:53:45.544475 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
604 22:53:45.544561 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 22:53:45.544648 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 22:53:45.544736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
607 22:53:45.544852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
608 22:53:45.544938 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
609 22:53:45.545024 [ANA_INIT] flow start
610 22:53:45.545109 [ANA_INIT] PLL >>>>>>>>
611 22:53:45.545193 [ANA_INIT] PLL <<<<<<<<
612 22:53:45.545276 [ANA_INIT] MIDPI >>>>>>>>
613 22:53:45.545409 [ANA_INIT] MIDPI <<<<<<<<
614 22:53:45.545572 [ANA_INIT] DLL >>>>>>>>
615 22:53:45.545688 [ANA_INIT] flow end
616 22:53:45.545772 ============ LP4 DIFF to SE enter ============
617 22:53:45.545856 ============ LP4 DIFF to SE exit ============
618 22:53:45.545941 [ANA_INIT] <<<<<<<<<<<<<
619 22:53:45.546025 [Flow] Enable top DCM control >>>>>
620 22:53:45.546111 [Flow] Enable top DCM control <<<<<
621 22:53:45.546238 Enable DLL master slave shuffle
622 22:53:45.546323 ==============================================================
623 22:53:45.546408 Gating Mode config
624 22:53:45.546492 ==============================================================
625 22:53:45.546577 Config description:
626 22:53:45.546662 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
627 22:53:45.546749 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
628 22:53:45.546836 SELPH_MODE 0: By rank 1: By Phase
629 22:53:45.546921 ==============================================================
630 22:53:45.547006 GAT_TRACK_EN = 1
631 22:53:45.547090 RX_GATING_MODE = 2
632 22:53:45.547175 RX_GATING_TRACK_MODE = 2
633 22:53:45.547259 SELPH_MODE = 1
634 22:53:45.547344 PICG_EARLY_EN = 1
635 22:53:45.547429 VALID_LAT_VALUE = 1
636 22:53:45.547514 ==============================================================
637 22:53:45.547600 Enter into Gating configuration >>>>
638 22:53:45.547684 Exit from Gating configuration <<<<
639 22:53:45.547769 Enter into DVFS_PRE_config >>>>>
640 22:53:45.547854 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
641 22:53:45.547943 Exit from DVFS_PRE_config <<<<<
642 22:53:45.548027 Enter into PICG configuration >>>>
643 22:53:45.548112 Exit from PICG configuration <<<<
644 22:53:45.548196 [RX_INPUT] configuration >>>>>
645 22:53:45.548280 [RX_INPUT] configuration <<<<<
646 22:53:45.548364 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
647 22:53:45.548452 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
648 22:53:45.548538 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
649 22:53:45.548622 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
650 22:53:45.548706 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
651 22:53:45.548792 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
652 22:53:45.548879 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
653 22:53:45.548964 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
654 22:53:45.549066 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
655 22:53:45.549163 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
656 22:53:45.549249 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
657 22:53:45.549333 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
658 22:53:45.549418 ===================================
659 22:53:45.549502 LPDDR4 DRAM CONFIGURATION
660 22:53:45.549587 ===================================
661 22:53:45.549673 EX_ROW_EN[0] = 0x0
662 22:53:45.549757 EX_ROW_EN[1] = 0x0
663 22:53:45.549840 LP4Y_EN = 0x0
664 22:53:45.549924 WORK_FSP = 0x0
665 22:53:45.550007 WL = 0x2
666 22:53:45.550089 RL = 0x2
667 22:53:45.550199 BL = 0x2
668 22:53:45.550298 RPST = 0x0
669 22:53:45.550381 RD_PRE = 0x0
670 22:53:45.550465 WR_PRE = 0x1
671 22:53:45.550549 WR_PST = 0x0
672 22:53:45.550633 DBI_WR = 0x0
673 22:53:45.550717 DBI_RD = 0x0
674 22:53:45.550801 OTF = 0x1
675 22:53:45.550886 ===================================
676 22:53:45.550971 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
677 22:53:45.551054 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
678 22:53:45.551140 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
679 22:53:45.551225 ===================================
680 22:53:45.551310 LPDDR4 DRAM CONFIGURATION
681 22:53:45.551396 ===================================
682 22:53:45.551481 EX_ROW_EN[0] = 0x10
683 22:53:45.551566 EX_ROW_EN[1] = 0x0
684 22:53:45.551651 LP4Y_EN = 0x0
685 22:53:45.551736 WORK_FSP = 0x0
686 22:53:45.551821 WL = 0x2
687 22:53:45.551906 RL = 0x2
688 22:53:45.551996 BL = 0x2
689 22:53:45.552082 RPST = 0x0
690 22:53:45.552167 RD_PRE = 0x0
691 22:53:45.552252 WR_PRE = 0x1
692 22:53:45.552335 WR_PST = 0x0
693 22:53:45.552421 DBI_WR = 0x0
694 22:53:45.552505 DBI_RD = 0x0
695 22:53:45.552589 OTF = 0x1
696 22:53:45.552673 ===================================
697 22:53:45.552759 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
698 22:53:45.552844 nWR fixed to 40
699 22:53:45.552930 [ModeRegInit_LP4] CH0 RK0
700 22:53:45.553014 [ModeRegInit_LP4] CH0 RK1
701 22:53:45.553100 [ModeRegInit_LP4] CH1 RK0
702 22:53:45.553185 [ModeRegInit_LP4] CH1 RK1
703 22:53:45.553271 match AC timing 13
704 22:53:45.553577 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
705 22:53:45.553678 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
706 22:53:45.553769 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
707 22:53:45.553858 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
708 22:53:45.553947 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
709 22:53:45.554035 [EMI DOE] emi_dcm 0
710 22:53:45.554122 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
711 22:53:45.554320 ==
712 22:53:45.554394 Dram Type= 6, Freq= 0, CH_0, rank 0
713 22:53:45.554456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
714 22:53:45.554514 ==
715 22:53:45.554570 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
716 22:53:45.554625 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
717 22:53:45.554680 [CA 0] Center 37 (6~68) winsize 63
718 22:53:45.554734 [CA 1] Center 37 (6~68) winsize 63
719 22:53:45.554786 [CA 2] Center 34 (4~65) winsize 62
720 22:53:45.554839 [CA 3] Center 34 (4~65) winsize 62
721 22:53:45.554891 [CA 4] Center 33 (3~64) winsize 62
722 22:53:45.554943 [CA 5] Center 33 (3~64) winsize 62
723 22:53:45.554999
724 22:53:45.555065 [CmdBusTrainingLP45] Vref(ca) range 1: 32
725 22:53:45.555118
726 22:53:45.555170 [CATrainingPosCal] consider 1 rank data
727 22:53:45.555223 u2DelayCellTimex100 = 270/100 ps
728 22:53:45.555274 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
729 22:53:45.555327 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
730 22:53:45.555378 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
731 22:53:45.555430 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
732 22:53:45.555481 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
733 22:53:45.555533 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
734 22:53:45.555584
735 22:53:45.555634 CA PerBit enable=1, Macro0, CA PI delay=33
736 22:53:45.555686
737 22:53:45.555737 [CBTSetCACLKResult] CA Dly = 33
738 22:53:45.555788 CS Dly: 6 (0~37)
739 22:53:45.555840 ==
740 22:53:45.555891 Dram Type= 6, Freq= 0, CH_0, rank 1
741 22:53:45.555943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
742 22:53:45.555995 ==
743 22:53:45.556047 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
744 22:53:45.556099 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
745 22:53:45.556151 [CA 0] Center 37 (6~68) winsize 63
746 22:53:45.556202 [CA 1] Center 37 (7~68) winsize 62
747 22:53:45.556254 [CA 2] Center 34 (4~65) winsize 62
748 22:53:45.556305 [CA 3] Center 34 (4~65) winsize 62
749 22:53:45.556356 [CA 4] Center 33 (3~64) winsize 62
750 22:53:45.556407 [CA 5] Center 33 (2~64) winsize 63
751 22:53:45.556458
752 22:53:45.556508 [CmdBusTrainingLP45] Vref(ca) range 1: 32
753 22:53:45.556560
754 22:53:45.556610 [CATrainingPosCal] consider 2 rank data
755 22:53:45.556661 u2DelayCellTimex100 = 270/100 ps
756 22:53:45.556713 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
757 22:53:45.556764 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
758 22:53:45.556815 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
759 22:53:45.556866 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
760 22:53:45.556929 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
761 22:53:45.557013 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
762 22:53:45.557064
763 22:53:45.557115 CA PerBit enable=1, Macro0, CA PI delay=33
764 22:53:45.557166
765 22:53:45.557217 [CBTSetCACLKResult] CA Dly = 33
766 22:53:45.557268 CS Dly: 6 (0~38)
767 22:53:45.557319
768 22:53:45.557370 ----->DramcWriteLeveling(PI) begin...
769 22:53:45.557425 ==
770 22:53:45.557476 Dram Type= 6, Freq= 0, CH_0, rank 0
771 22:53:45.557527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
772 22:53:45.557579 ==
773 22:53:45.557631 Write leveling (Byte 0): 31 => 31
774 22:53:45.557681 Write leveling (Byte 1): 30 => 30
775 22:53:45.557732 DramcWriteLeveling(PI) end<-----
776 22:53:45.557783
777 22:53:45.557835 ==
778 22:53:45.557886 Dram Type= 6, Freq= 0, CH_0, rank 0
779 22:53:45.557937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 22:53:45.557989 ==
781 22:53:45.558040 [Gating] SW mode calibration
782 22:53:45.558091 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
783 22:53:45.558144 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
784 22:53:45.558236 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
785 22:53:45.558289 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
786 22:53:45.558340 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
787 22:53:45.558392 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 22:53:45.558444 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 22:53:45.558495 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 22:53:45.558546 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:53:45.558598 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:53:45.558649 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:53:45.558701 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:53:45.558752 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:53:45.558804 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:53:45.558855 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:53:45.558906 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 22:53:45.558957 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:53:45.559009 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:53:45.559059 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:53:45.559111 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:53:45.559162 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
803 22:53:45.559213 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
804 22:53:45.559264 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 22:53:45.559316 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:53:45.559367 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:53:45.559418 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:53:45.559469 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:53:45.559520 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 22:53:45.559571 0 9 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
811 22:53:45.559623 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
812 22:53:45.559883 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 22:53:45.559943 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 22:53:45.559996 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 22:53:45.560047 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 22:53:45.560099 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 22:53:45.560151 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
818 22:53:45.560203 0 10 8 | B1->B0 | 3131 2b2b | 1 0 | (1 0) (0 0)
819 22:53:45.560254 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
820 22:53:45.560305 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 22:53:45.560356 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 22:53:45.560407 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 22:53:45.560459 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:53:45.560509 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 22:53:45.560560 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
826 22:53:45.560611 0 11 8 | B1->B0 | 2828 3a3a | 0 0 | (0 0) (0 0)
827 22:53:45.560662 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
828 22:53:45.560741 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 22:53:45.560823 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 22:53:45.560875 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 22:53:45.560927 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 22:53:45.560979 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 22:53:45.561032 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 22:53:45.561084 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
835 22:53:45.561137 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
836 22:53:45.561189 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 22:53:45.561242 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 22:53:45.561294 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:53:45.561346 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:53:45.561398 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:53:45.561451 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:53:45.561503 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:53:45.561566 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:53:45.561649 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:53:45.561734 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:53:45.561819 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 22:53:45.561910 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 22:53:45.562000 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 22:53:45.562097 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 22:53:45.562193 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
851 22:53:45.562254 Total UI for P1: 0, mck2ui 16
852 22:53:45.562340 best dqsien dly found for B0: ( 0, 14, 6)
853 22:53:45.562395 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
854 22:53:45.562480 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
855 22:53:45.562534 Total UI for P1: 0, mck2ui 16
856 22:53:45.562623 best dqsien dly found for B1: ( 0, 14, 10)
857 22:53:45.562720 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
858 22:53:45.562810 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
859 22:53:45.562870
860 22:53:45.562939 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
861 22:53:45.563010 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
862 22:53:45.563095 [Gating] SW calibration Done
863 22:53:45.563177 ==
864 22:53:45.563234 Dram Type= 6, Freq= 0, CH_0, rank 0
865 22:53:45.563288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 22:53:45.563341 ==
867 22:53:45.563395 RX Vref Scan: 0
868 22:53:45.563448
869 22:53:45.563500 RX Vref 0 -> 0, step: 1
870 22:53:45.563553
871 22:53:45.563618 RX Delay -130 -> 252, step: 16
872 22:53:45.563671 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 22:53:45.563724 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
874 22:53:45.563777 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 22:53:45.563830 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
876 22:53:45.563883 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
877 22:53:45.563935 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
878 22:53:45.563988 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
879 22:53:45.564040 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
880 22:53:45.564093 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
881 22:53:45.564146 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
882 22:53:45.564198 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
883 22:53:45.564250 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
884 22:53:45.564303 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
885 22:53:45.564356 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
886 22:53:45.564408 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
887 22:53:45.564460 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
888 22:53:45.564512 ==
889 22:53:45.564564 Dram Type= 6, Freq= 0, CH_0, rank 0
890 22:53:45.564617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 22:53:45.564670 ==
892 22:53:45.564723 DQS Delay:
893 22:53:45.564775 DQS0 = 0, DQS1 = 0
894 22:53:45.564828 DQM Delay:
895 22:53:45.564880 DQM0 = 86, DQM1 = 71
896 22:53:45.564932 DQ Delay:
897 22:53:45.564984 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
898 22:53:45.565037 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =101
899 22:53:45.565089 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
900 22:53:45.565142 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
901 22:53:45.565195
902 22:53:45.565247
903 22:53:45.565299 ==
904 22:53:45.565351 Dram Type= 6, Freq= 0, CH_0, rank 0
905 22:53:45.565404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 22:53:45.565457 ==
907 22:53:45.565509
908 22:53:45.565611
909 22:53:45.565692 TX Vref Scan disable
910 22:53:45.565765 == TX Byte 0 ==
911 22:53:45.565819 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
912 22:53:45.565872 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
913 22:53:45.565940 == TX Byte 1 ==
914 22:53:45.566006 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
915 22:53:45.566057 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
916 22:53:45.566109 ==
917 22:53:45.566182 Dram Type= 6, Freq= 0, CH_0, rank 0
918 22:53:45.566254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 22:53:45.566306 ==
920 22:53:45.566562 TX Vref=22, minBit 5, minWin=27, winSum=444
921 22:53:45.566621 TX Vref=24, minBit 5, minWin=27, winSum=443
922 22:53:45.566674 TX Vref=26, minBit 5, minWin=27, winSum=449
923 22:53:45.566727 TX Vref=28, minBit 5, minWin=27, winSum=449
924 22:53:45.566780 TX Vref=30, minBit 4, minWin=27, winSum=447
925 22:53:45.566843 TX Vref=32, minBit 8, minWin=27, winSum=445
926 22:53:45.566927 [TxChooseVref] Worse bit 5, Min win 27, Win sum 449, Final Vref 26
927 22:53:45.566980
928 22:53:45.567031 Final TX Range 1 Vref 26
929 22:53:45.567083
930 22:53:45.567134 ==
931 22:53:45.567186 Dram Type= 6, Freq= 0, CH_0, rank 0
932 22:53:45.567237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 22:53:45.567289 ==
934 22:53:45.567340
935 22:53:45.567390
936 22:53:45.567441 TX Vref Scan disable
937 22:53:45.567493 == TX Byte 0 ==
938 22:53:45.567544 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
939 22:53:45.567596 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
940 22:53:45.567648 == TX Byte 1 ==
941 22:53:45.567699 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
942 22:53:45.567751 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
943 22:53:45.567806
944 22:53:45.567857 [DATLAT]
945 22:53:45.567907 Freq=800, CH0 RK0
946 22:53:45.567959
947 22:53:45.568010 DATLAT Default: 0xa
948 22:53:45.568061 0, 0xFFFF, sum = 0
949 22:53:45.568114 1, 0xFFFF, sum = 0
950 22:53:45.568166 2, 0xFFFF, sum = 0
951 22:53:45.568218 3, 0xFFFF, sum = 0
952 22:53:45.568271 4, 0xFFFF, sum = 0
953 22:53:45.568323 5, 0xFFFF, sum = 0
954 22:53:45.568375 6, 0xFFFF, sum = 0
955 22:53:45.568428 7, 0xFFFF, sum = 0
956 22:53:45.568480 8, 0xFFFF, sum = 0
957 22:53:45.568531 9, 0x0, sum = 1
958 22:53:45.568584 10, 0x0, sum = 2
959 22:53:45.568636 11, 0x0, sum = 3
960 22:53:45.568688 12, 0x0, sum = 4
961 22:53:45.568739 best_step = 10
962 22:53:45.568790
963 22:53:45.568841 ==
964 22:53:45.568892 Dram Type= 6, Freq= 0, CH_0, rank 0
965 22:53:45.568946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 22:53:45.569005 ==
967 22:53:45.569095 RX Vref Scan: 1
968 22:53:45.569203
969 22:53:45.569263 Set Vref Range= 32 -> 127
970 22:53:45.569316
971 22:53:45.569384 RX Vref 32 -> 127, step: 1
972 22:53:45.569449
973 22:53:45.569500 RX Delay -111 -> 252, step: 8
974 22:53:45.569551
975 22:53:45.569602 Set Vref, RX VrefLevel [Byte0]: 32
976 22:53:45.569653 [Byte1]: 32
977 22:53:45.569704
978 22:53:45.569755 Set Vref, RX VrefLevel [Byte0]: 33
979 22:53:45.569806 [Byte1]: 33
980 22:53:45.569858
981 22:53:45.569909 Set Vref, RX VrefLevel [Byte0]: 34
982 22:53:45.569960 [Byte1]: 34
983 22:53:45.570011
984 22:53:45.570063 Set Vref, RX VrefLevel [Byte0]: 35
985 22:53:45.570113 [Byte1]: 35
986 22:53:45.570240
987 22:53:45.570328 Set Vref, RX VrefLevel [Byte0]: 36
988 22:53:45.570380 [Byte1]: 36
989 22:53:45.570431
990 22:53:45.570482 Set Vref, RX VrefLevel [Byte0]: 37
991 22:53:45.570533 [Byte1]: 37
992 22:53:45.570585
993 22:53:45.570636 Set Vref, RX VrefLevel [Byte0]: 38
994 22:53:45.570687 [Byte1]: 38
995 22:53:45.570739
996 22:53:45.570790 Set Vref, RX VrefLevel [Byte0]: 39
997 22:53:45.570840 [Byte1]: 39
998 22:53:45.570901
999 22:53:45.570959 Set Vref, RX VrefLevel [Byte0]: 40
1000 22:53:45.571034 [Byte1]: 40
1001 22:53:45.571135
1002 22:53:45.571234 Set Vref, RX VrefLevel [Byte0]: 41
1003 22:53:45.571334 [Byte1]: 41
1004 22:53:45.571390
1005 22:53:45.571442 Set Vref, RX VrefLevel [Byte0]: 42
1006 22:53:45.571494 [Byte1]: 42
1007 22:53:45.571545
1008 22:53:45.571597 Set Vref, RX VrefLevel [Byte0]: 43
1009 22:53:45.571648 [Byte1]: 43
1010 22:53:45.571699
1011 22:53:45.571750 Set Vref, RX VrefLevel [Byte0]: 44
1012 22:53:45.571801 [Byte1]: 44
1013 22:53:45.571852
1014 22:53:45.571930 Set Vref, RX VrefLevel [Byte0]: 45
1015 22:53:45.572002 [Byte1]: 45
1016 22:53:45.572089
1017 22:53:45.572144 Set Vref, RX VrefLevel [Byte0]: 46
1018 22:53:45.572198 [Byte1]: 46
1019 22:53:45.572250
1020 22:53:45.572302 Set Vref, RX VrefLevel [Byte0]: 47
1021 22:53:45.572354 [Byte1]: 47
1022 22:53:45.572405
1023 22:53:45.572456 Set Vref, RX VrefLevel [Byte0]: 48
1024 22:53:45.572508 [Byte1]: 48
1025 22:53:45.572566
1026 22:53:45.572621 Set Vref, RX VrefLevel [Byte0]: 49
1027 22:53:45.572675 [Byte1]: 49
1028 22:53:45.572726
1029 22:53:45.572795 Set Vref, RX VrefLevel [Byte0]: 50
1030 22:53:45.572860 [Byte1]: 50
1031 22:53:45.572911
1032 22:53:45.572963 Set Vref, RX VrefLevel [Byte0]: 51
1033 22:53:45.573025 [Byte1]: 51
1034 22:53:45.573100
1035 22:53:45.573153 Set Vref, RX VrefLevel [Byte0]: 52
1036 22:53:45.573206 [Byte1]: 52
1037 22:53:45.573258
1038 22:53:45.573324 Set Vref, RX VrefLevel [Byte0]: 53
1039 22:53:45.573375 [Byte1]: 53
1040 22:53:45.573425
1041 22:53:45.573476 Set Vref, RX VrefLevel [Byte0]: 54
1042 22:53:45.573551 [Byte1]: 54
1043 22:53:45.573644
1044 22:53:45.573738 Set Vref, RX VrefLevel [Byte0]: 55
1045 22:53:45.573822 [Byte1]: 55
1046 22:53:45.573906
1047 22:53:45.573997 Set Vref, RX VrefLevel [Byte0]: 56
1048 22:53:45.574087 [Byte1]: 56
1049 22:53:45.574191
1050 22:53:45.574262 Set Vref, RX VrefLevel [Byte0]: 57
1051 22:53:45.574316 [Byte1]: 57
1052 22:53:45.574368
1053 22:53:45.574420 Set Vref, RX VrefLevel [Byte0]: 58
1054 22:53:45.574472 [Byte1]: 58
1055 22:53:45.574523
1056 22:53:45.574575 Set Vref, RX VrefLevel [Byte0]: 59
1057 22:53:45.574626 [Byte1]: 59
1058 22:53:45.574678
1059 22:53:45.574729 Set Vref, RX VrefLevel [Byte0]: 60
1060 22:53:45.574780 [Byte1]: 60
1061 22:53:45.574831
1062 22:53:45.574882 Set Vref, RX VrefLevel [Byte0]: 61
1063 22:53:45.574933 [Byte1]: 61
1064 22:53:45.574984
1065 22:53:45.575035 Set Vref, RX VrefLevel [Byte0]: 62
1066 22:53:45.575086 [Byte1]: 62
1067 22:53:45.575137
1068 22:53:45.575188 Set Vref, RX VrefLevel [Byte0]: 63
1069 22:53:45.575239 [Byte1]: 63
1070 22:53:45.575307
1071 22:53:45.575371 Set Vref, RX VrefLevel [Byte0]: 64
1072 22:53:45.575422 [Byte1]: 64
1073 22:53:45.575472
1074 22:53:45.575523 Set Vref, RX VrefLevel [Byte0]: 65
1075 22:53:45.575574 [Byte1]: 65
1076 22:53:45.575626
1077 22:53:45.575676 Set Vref, RX VrefLevel [Byte0]: 66
1078 22:53:45.575728 [Byte1]: 66
1079 22:53:45.575779
1080 22:53:45.575830 Set Vref, RX VrefLevel [Byte0]: 67
1081 22:53:45.575881 [Byte1]: 67
1082 22:53:45.575932
1083 22:53:45.575982 Set Vref, RX VrefLevel [Byte0]: 68
1084 22:53:45.576033 [Byte1]: 68
1085 22:53:45.576084
1086 22:53:45.576136 Set Vref, RX VrefLevel [Byte0]: 69
1087 22:53:45.576410 [Byte1]: 69
1088 22:53:45.576500
1089 22:53:45.576598 Set Vref, RX VrefLevel [Byte0]: 70
1090 22:53:45.576681 [Byte1]: 70
1091 22:53:45.576779
1092 22:53:45.576842 Set Vref, RX VrefLevel [Byte0]: 71
1093 22:53:45.576956 [Byte1]: 71
1094 22:53:45.577059
1095 22:53:45.577114 Set Vref, RX VrefLevel [Byte0]: 72
1096 22:53:45.577168 [Byte1]: 72
1097 22:53:45.577241
1098 22:53:45.577298 Set Vref, RX VrefLevel [Byte0]: 73
1099 22:53:45.577351 [Byte1]: 73
1100 22:53:45.577405
1101 22:53:45.577458 Set Vref, RX VrefLevel [Byte0]: 74
1102 22:53:45.577511 [Byte1]: 74
1103 22:53:45.577562
1104 22:53:45.577615 Set Vref, RX VrefLevel [Byte0]: 75
1105 22:53:45.577667 [Byte1]: 75
1106 22:53:45.577719
1107 22:53:45.577771 Set Vref, RX VrefLevel [Byte0]: 76
1108 22:53:45.577823 [Byte1]: 76
1109 22:53:45.577876
1110 22:53:45.577928 Set Vref, RX VrefLevel [Byte0]: 77
1111 22:53:45.577983 [Byte1]: 77
1112 22:53:45.578035
1113 22:53:45.578087 Set Vref, RX VrefLevel [Byte0]: 78
1114 22:53:45.578139 [Byte1]: 78
1115 22:53:45.578205
1116 22:53:45.578258 Set Vref, RX VrefLevel [Byte0]: 79
1117 22:53:45.578311 [Byte1]: 79
1118 22:53:45.578363
1119 22:53:45.578415 Set Vref, RX VrefLevel [Byte0]: 80
1120 22:53:45.578467 [Byte1]: 80
1121 22:53:45.578519
1122 22:53:45.578571 Set Vref, RX VrefLevel [Byte0]: 81
1123 22:53:45.578623 [Byte1]: 81
1124 22:53:45.578675
1125 22:53:45.578727 Final RX Vref Byte 0 = 67 to rank0
1126 22:53:45.578780 Final RX Vref Byte 1 = 54 to rank0
1127 22:53:45.578833 Final RX Vref Byte 0 = 67 to rank1
1128 22:53:45.578886 Final RX Vref Byte 1 = 54 to rank1==
1129 22:53:45.578938 Dram Type= 6, Freq= 0, CH_0, rank 0
1130 22:53:45.578991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1131 22:53:45.579044 ==
1132 22:53:45.579098 DQS Delay:
1133 22:53:45.579164 DQS0 = 0, DQS1 = 0
1134 22:53:45.579219 DQM Delay:
1135 22:53:45.579272 DQM0 = 87, DQM1 = 75
1136 22:53:45.579324 DQ Delay:
1137 22:53:45.579377 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1138 22:53:45.579429 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1139 22:53:45.579482 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1140 22:53:45.579534 DQ12 =80, DQ13 =76, DQ14 =88, DQ15 =84
1141 22:53:45.579586
1142 22:53:45.579638
1143 22:53:45.579691 [DQSOSCAuto] RK0, (LSB)MR18= 0x4122, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1144 22:53:45.579744 CH0 RK0: MR19=606, MR18=4122
1145 22:53:45.579797 CH0_RK0: MR19=0x606, MR18=0x4122, DQSOSC=393, MR23=63, INC=95, DEC=63
1146 22:53:45.579850
1147 22:53:45.579903 ----->DramcWriteLeveling(PI) begin...
1148 22:53:45.579957 ==
1149 22:53:45.580010 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 22:53:45.580061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 22:53:45.580114 ==
1152 22:53:45.580166 Write leveling (Byte 0): 31 => 31
1153 22:53:45.580219 Write leveling (Byte 1): 30 => 30
1154 22:53:45.580271 DramcWriteLeveling(PI) end<-----
1155 22:53:45.580322
1156 22:53:45.580375 ==
1157 22:53:45.580441 Dram Type= 6, Freq= 0, CH_0, rank 1
1158 22:53:45.580493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1159 22:53:45.580544 ==
1160 22:53:45.580595 [Gating] SW mode calibration
1161 22:53:45.580647 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1162 22:53:45.580699 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1163 22:53:45.580750 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1164 22:53:45.580817 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1165 22:53:45.580874 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1166 22:53:45.580939 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 22:53:45.581010 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 22:53:45.581074 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:53:45.581126 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:53:45.581177 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:53:45.581228 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:53:45.581279 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 22:53:45.581330 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 22:53:45.581381 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 22:53:45.581432 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 22:53:45.581483 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 22:53:45.581533 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 22:53:45.581584 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 22:53:45.581635 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 22:53:45.581686 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 22:53:45.581737 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1182 22:53:45.581789 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 22:53:45.581839 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 22:53:45.581890 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 22:53:45.581941 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 22:53:45.581992 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 22:53:45.582043 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 22:53:45.582094 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 22:53:45.582144 0 9 8 | B1->B0 | 2424 2e2e | 0 1 | (0 0) (0 0)
1190 22:53:45.582235 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1191 22:53:45.582287 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 22:53:45.582337 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 22:53:45.582388 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 22:53:45.582439 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 22:53:45.582491 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 22:53:45.582541 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 22:53:45.582591 0 10 8 | B1->B0 | 3030 2a2a | 1 0 | (1 0) (0 0)
1198 22:53:45.582642 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1199 22:53:45.582693 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 22:53:45.582743 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 22:53:45.583018 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 22:53:45.583140 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 22:53:45.583194 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 22:53:45.583257 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 22:53:45.583312 0 11 8 | B1->B0 | 2c2c 3d3d | 0 0 | (1 1) (0 0)
1206 22:53:45.583365 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1207 22:53:45.583418 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 22:53:45.583484 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 22:53:45.583535 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 22:53:45.583587 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 22:53:45.583638 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 22:53:45.583689 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 22:53:45.583739 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1214 22:53:45.583790 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 22:53:45.583842 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 22:53:45.583893 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 22:53:45.583944 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 22:53:45.583995 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 22:53:45.584046 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 22:53:45.584096 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 22:53:45.584147 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 22:53:45.584198 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 22:53:45.584249 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 22:53:45.584300 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 22:53:45.584352 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 22:53:45.584403 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 22:53:45.584454 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 22:53:45.584505 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 22:53:45.584555 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 22:53:45.584607 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1231 22:53:45.584657 Total UI for P1: 0, mck2ui 16
1232 22:53:45.584709 best dqsien dly found for B0: ( 0, 14, 10)
1233 22:53:45.584760 Total UI for P1: 0, mck2ui 16
1234 22:53:45.584812 best dqsien dly found for B1: ( 0, 14, 10)
1235 22:53:45.584863 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1236 22:53:45.584915 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1237 22:53:45.584965
1238 22:53:45.585015 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1239 22:53:45.585066 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1240 22:53:45.585117 [Gating] SW calibration Done
1241 22:53:45.585168 ==
1242 22:53:45.585219 Dram Type= 6, Freq= 0, CH_0, rank 1
1243 22:53:45.585271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1244 22:53:45.585322 ==
1245 22:53:45.585373 RX Vref Scan: 0
1246 22:53:45.585424
1247 22:53:45.585475 RX Vref 0 -> 0, step: 1
1248 22:53:45.585525
1249 22:53:45.585575 RX Delay -130 -> 252, step: 16
1250 22:53:45.585626 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1251 22:53:45.585677 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1252 22:53:45.585729 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1253 22:53:45.585780 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1254 22:53:45.585831 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1255 22:53:45.585881 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1256 22:53:45.585932 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1257 22:53:45.585983 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1258 22:53:45.586034 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1259 22:53:45.586084 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1260 22:53:45.586134 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1261 22:53:45.586231 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1262 22:53:45.586283 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1263 22:53:45.586334 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1264 22:53:45.586385 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1265 22:53:45.586436 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1266 22:53:45.586487 ==
1267 22:53:45.586538 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 22:53:45.586601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 22:53:45.586654 ==
1270 22:53:45.586705 DQS Delay:
1271 22:53:45.586756 DQS0 = 0, DQS1 = 0
1272 22:53:45.586807 DQM Delay:
1273 22:53:45.586858 DQM0 = 84, DQM1 = 77
1274 22:53:45.586908 DQ Delay:
1275 22:53:45.586960 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1276 22:53:45.587011 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1277 22:53:45.587061 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1278 22:53:45.587113 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1279 22:53:45.587164
1280 22:53:45.587215
1281 22:53:45.587265 ==
1282 22:53:45.587316 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 22:53:45.587367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 22:53:45.587419 ==
1285 22:53:45.587469
1286 22:53:45.587519
1287 22:53:45.587570 TX Vref Scan disable
1288 22:53:45.587620 == TX Byte 0 ==
1289 22:53:45.587671 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1290 22:53:45.587722 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1291 22:53:45.587774 == TX Byte 1 ==
1292 22:53:45.587824 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1293 22:53:45.587875 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1294 22:53:45.587926 ==
1295 22:53:45.587976 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 22:53:45.588027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 22:53:45.588077 ==
1298 22:53:45.588127 TX Vref=22, minBit 2, minWin=27, winSum=444
1299 22:53:45.588178 TX Vref=24, minBit 9, minWin=27, winSum=446
1300 22:53:45.588229 TX Vref=26, minBit 9, minWin=27, winSum=447
1301 22:53:45.588279 TX Vref=28, minBit 8, minWin=27, winSum=446
1302 22:53:45.588330 TX Vref=30, minBit 8, minWin=27, winSum=445
1303 22:53:45.588381 TX Vref=32, minBit 9, minWin=27, winSum=446
1304 22:53:45.588431 [TxChooseVref] Worse bit 9, Min win 27, Win sum 447, Final Vref 26
1305 22:53:45.588482
1306 22:53:45.588532 Final TX Range 1 Vref 26
1307 22:53:45.588582
1308 22:53:45.588632 ==
1309 22:53:45.588682 Dram Type= 6, Freq= 0, CH_0, rank 1
1310 22:53:45.588732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1311 22:53:45.588783 ==
1312 22:53:45.588833
1313 22:53:45.588883
1314 22:53:45.588933 TX Vref Scan disable
1315 22:53:45.588983 == TX Byte 0 ==
1316 22:53:45.589033 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1317 22:53:45.589283 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1318 22:53:45.589340 == TX Byte 1 ==
1319 22:53:45.589391 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1320 22:53:45.589442 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1321 22:53:45.589493
1322 22:53:45.589543 [DATLAT]
1323 22:53:45.589593 Freq=800, CH0 RK1
1324 22:53:45.589644
1325 22:53:45.589694 DATLAT Default: 0xa
1326 22:53:45.589744 0, 0xFFFF, sum = 0
1327 22:53:45.589796 1, 0xFFFF, sum = 0
1328 22:53:45.589847 2, 0xFFFF, sum = 0
1329 22:53:45.589898 3, 0xFFFF, sum = 0
1330 22:53:45.589949 4, 0xFFFF, sum = 0
1331 22:53:45.590000 5, 0xFFFF, sum = 0
1332 22:53:45.590051 6, 0xFFFF, sum = 0
1333 22:53:45.590102 7, 0xFFFF, sum = 0
1334 22:53:45.590153 8, 0xFFFF, sum = 0
1335 22:53:45.590250 9, 0x0, sum = 1
1336 22:53:45.590303 10, 0x0, sum = 2
1337 22:53:45.590355 11, 0x0, sum = 3
1338 22:53:45.590406 12, 0x0, sum = 4
1339 22:53:45.590469 best_step = 10
1340 22:53:45.590519
1341 22:53:45.590568 ==
1342 22:53:45.590618 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 22:53:45.590675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 22:53:45.590747 ==
1345 22:53:45.590824 RX Vref Scan: 0
1346 22:53:45.590897
1347 22:53:45.590959 RX Vref 0 -> 0, step: 1
1348 22:53:45.591010
1349 22:53:45.591060 RX Delay -111 -> 252, step: 8
1350 22:53:45.591135 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1351 22:53:45.591188 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1352 22:53:45.591240 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1353 22:53:45.591291 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1354 22:53:45.591341 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1355 22:53:45.591391 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1356 22:53:45.591441 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1357 22:53:45.591492 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1358 22:53:45.591542 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1359 22:53:45.591592 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1360 22:53:45.591643 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1361 22:53:45.591693 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1362 22:53:45.591743 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1363 22:53:45.591793 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1364 22:53:45.591844 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1365 22:53:45.591894 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1366 22:53:45.591944 ==
1367 22:53:45.591994 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 22:53:45.592066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 22:53:45.592143 ==
1370 22:53:45.592221 DQS Delay:
1371 22:53:45.592302 DQS0 = 0, DQS1 = 0
1372 22:53:45.592384 DQM Delay:
1373 22:53:45.592460 DQM0 = 85, DQM1 = 76
1374 22:53:45.592542 DQ Delay:
1375 22:53:45.592626 DQ0 =84, DQ1 =92, DQ2 =76, DQ3 =80
1376 22:53:45.592712 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1377 22:53:45.592802 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1378 22:53:45.592901 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1379 22:53:45.593068
1380 22:53:45.593130
1381 22:53:45.593185 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b02, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
1382 22:53:45.593239 CH0 RK1: MR19=606, MR18=3B02
1383 22:53:45.593291 CH0_RK1: MR19=0x606, MR18=0x3B02, DQSOSC=394, MR23=63, INC=95, DEC=63
1384 22:53:45.593343 [RxdqsGatingPostProcess] freq 800
1385 22:53:45.593394 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1386 22:53:45.593458 Pre-setting of DQS Precalculation
1387 22:53:45.593508 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1388 22:53:45.593559 ==
1389 22:53:45.593610 Dram Type= 6, Freq= 0, CH_1, rank 0
1390 22:53:45.593661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1391 22:53:45.593711 ==
1392 22:53:45.593762 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1393 22:53:45.593813 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1394 22:53:45.593864 [CA 0] Center 36 (6~67) winsize 62
1395 22:53:45.593915 [CA 1] Center 36 (6~67) winsize 62
1396 22:53:45.593966 [CA 2] Center 34 (4~65) winsize 62
1397 22:53:45.594016 [CA 3] Center 33 (3~64) winsize 62
1398 22:53:45.594066 [CA 4] Center 34 (4~65) winsize 62
1399 22:53:45.594116 [CA 5] Center 34 (4~65) winsize 62
1400 22:53:45.594192
1401 22:53:45.594258 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1402 22:53:45.594309
1403 22:53:45.594359 [CATrainingPosCal] consider 1 rank data
1404 22:53:45.594409 u2DelayCellTimex100 = 270/100 ps
1405 22:53:45.594459 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1406 22:53:45.594510 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1407 22:53:45.594561 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1408 22:53:45.594611 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1409 22:53:45.594661 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1410 22:53:45.594712 CA5 delay=34 (4~65),Diff = 1 PI (7 cell)
1411 22:53:45.594762
1412 22:53:45.594811 CA PerBit enable=1, Macro0, CA PI delay=33
1413 22:53:45.594866
1414 22:53:45.594923 [CBTSetCACLKResult] CA Dly = 33
1415 22:53:45.594975 CS Dly: 5 (0~36)
1416 22:53:45.595025 ==
1417 22:53:45.595075 Dram Type= 6, Freq= 0, CH_1, rank 1
1418 22:53:45.595125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 22:53:45.595176 ==
1420 22:53:45.595227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1421 22:53:45.595278 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1422 22:53:45.595329 [CA 0] Center 36 (6~67) winsize 62
1423 22:53:45.595379 [CA 1] Center 36 (6~67) winsize 62
1424 22:53:45.595429 [CA 2] Center 34 (4~65) winsize 62
1425 22:53:45.595479 [CA 3] Center 34 (3~65) winsize 63
1426 22:53:45.595529 [CA 4] Center 34 (4~65) winsize 62
1427 22:53:45.595579 [CA 5] Center 33 (3~64) winsize 62
1428 22:53:45.595629
1429 22:53:45.595679 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1430 22:53:45.595729
1431 22:53:45.595780 [CATrainingPosCal] consider 2 rank data
1432 22:53:45.595830 u2DelayCellTimex100 = 270/100 ps
1433 22:53:45.595880 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1434 22:53:45.595931 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1435 22:53:45.595980 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1436 22:53:45.596030 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1437 22:53:45.596081 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1438 22:53:45.596131 CA5 delay=34 (4~64),Diff = 1 PI (7 cell)
1439 22:53:45.596180
1440 22:53:45.596230 CA PerBit enable=1, Macro0, CA PI delay=33
1441 22:53:45.596281
1442 22:53:45.596331 [CBTSetCACLKResult] CA Dly = 33
1443 22:53:45.596381 CS Dly: 6 (0~38)
1444 22:53:45.596431
1445 22:53:45.596482 ----->DramcWriteLeveling(PI) begin...
1446 22:53:45.596533 ==
1447 22:53:45.596584 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 22:53:45.596634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 22:53:45.596684 ==
1450 22:53:45.596745 Write leveling (Byte 0): 27 => 27
1451 22:53:45.597050 Write leveling (Byte 1): 28 => 28
1452 22:53:45.597130 DramcWriteLeveling(PI) end<-----
1453 22:53:45.597192
1454 22:53:45.597249 ==
1455 22:53:45.597304 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 22:53:45.597360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1457 22:53:45.597415 ==
1458 22:53:45.597468 [Gating] SW mode calibration
1459 22:53:45.597520 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1460 22:53:45.597573 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1461 22:53:45.597625 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1462 22:53:45.597677 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1463 22:53:45.597728 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 22:53:45.597779 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 22:53:45.597830 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 22:53:45.597882 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 22:53:45.597933 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:53:45.597984 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:53:45.598035 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 22:53:45.598086 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 22:53:45.598137 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 22:53:45.598231 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 22:53:45.598283 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 22:53:45.598334 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 22:53:45.598385 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 22:53:45.598436 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 22:53:45.598488 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1478 22:53:45.598539 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1479 22:53:45.598591 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1480 22:53:45.598641 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 22:53:45.598693 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 22:53:45.598744 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 22:53:45.598795 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 22:53:45.598846 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 22:53:45.598898 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 22:53:45.598948 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1487 22:53:45.598999 0 9 8 | B1->B0 | 2b2b 3232 | 1 1 | (1 1) (1 1)
1488 22:53:45.599051 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 22:53:45.599101 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 22:53:45.599153 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 22:53:45.599204 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 22:53:45.599255 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 22:53:45.599306 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1494 22:53:45.599357 0 10 4 | B1->B0 | 3232 3131 | 1 1 | (1 0) (1 0)
1495 22:53:45.599408 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1496 22:53:45.599459 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 22:53:45.599510 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 22:53:45.599561 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 22:53:45.599612 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 22:53:45.599663 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 22:53:45.599714 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 22:53:45.599765 0 11 4 | B1->B0 | 2727 2b2b | 0 0 | (1 1) (1 1)
1503 22:53:45.599816 0 11 8 | B1->B0 | 3737 4141 | 0 0 | (0 0) (1 1)
1504 22:53:45.599867 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 22:53:45.599918 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 22:53:45.599969 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 22:53:45.600020 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 22:53:45.600071 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 22:53:45.600122 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 22:53:45.600172 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 22:53:45.600222 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1512 22:53:45.600274 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 22:53:45.600325 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 22:53:45.600375 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 22:53:45.600426 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 22:53:45.600477 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 22:53:45.600528 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 22:53:45.600580 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 22:53:45.600630 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 22:53:45.600681 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 22:53:45.600731 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 22:53:45.600782 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 22:53:45.600833 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 22:53:45.600885 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 22:53:45.600936 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 22:53:45.600987 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1527 22:53:45.601037 Total UI for P1: 0, mck2ui 16
1528 22:53:45.601089 best dqsien dly found for B0: ( 0, 14, 2)
1529 22:53:45.601140 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1530 22:53:45.601191 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 22:53:45.601242 Total UI for P1: 0, mck2ui 16
1532 22:53:45.601293 best dqsien dly found for B1: ( 0, 14, 6)
1533 22:53:45.601345 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1534 22:53:45.601396 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1535 22:53:45.601447
1536 22:53:45.601498 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1537 22:53:45.601747 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1538 22:53:45.601805 [Gating] SW calibration Done
1539 22:53:45.601857 ==
1540 22:53:45.601908 Dram Type= 6, Freq= 0, CH_1, rank 0
1541 22:53:45.601960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1542 22:53:45.602012 ==
1543 22:53:45.602063 RX Vref Scan: 0
1544 22:53:45.602114
1545 22:53:45.602193 RX Vref 0 -> 0, step: 1
1546 22:53:45.602260
1547 22:53:45.602312 RX Delay -130 -> 252, step: 16
1548 22:53:45.602362 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1549 22:53:45.602414 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1550 22:53:45.602465 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1551 22:53:45.602516 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1552 22:53:45.602566 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1553 22:53:45.602617 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1554 22:53:45.602668 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1555 22:53:45.602719 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1556 22:53:45.602770 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1557 22:53:45.602820 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1558 22:53:45.602871 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1559 22:53:45.602921 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1560 22:53:45.602972 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1561 22:53:45.603023 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1562 22:53:45.603074 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1563 22:53:45.603124 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1564 22:53:45.603175 ==
1565 22:53:45.603225 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 22:53:45.603276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 22:53:45.603327 ==
1568 22:53:45.603377 DQS Delay:
1569 22:53:45.603428 DQS0 = 0, DQS1 = 0
1570 22:53:45.603478 DQM Delay:
1571 22:53:45.603529 DQM0 = 87, DQM1 = 74
1572 22:53:45.603581 DQ Delay:
1573 22:53:45.603645 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1574 22:53:45.603697 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1575 22:53:45.603748 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1576 22:53:45.603799 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =85
1577 22:53:45.603850
1578 22:53:45.603900
1579 22:53:45.603951 ==
1580 22:53:45.604002 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 22:53:45.604053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1582 22:53:45.604104 ==
1583 22:53:45.604154
1584 22:53:45.604204
1585 22:53:45.604255 TX Vref Scan disable
1586 22:53:45.604306 == TX Byte 0 ==
1587 22:53:45.604356 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1588 22:53:45.604407 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1589 22:53:45.604458 == TX Byte 1 ==
1590 22:53:45.604509 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1591 22:53:45.604560 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1592 22:53:45.604611 ==
1593 22:53:45.604662 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 22:53:45.604712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 22:53:45.604763 ==
1596 22:53:45.604814 TX Vref=22, minBit 0, minWin=27, winSum=441
1597 22:53:45.604865 TX Vref=24, minBit 9, minWin=27, winSum=447
1598 22:53:45.604916 TX Vref=26, minBit 0, minWin=28, winSum=451
1599 22:53:45.604968 TX Vref=28, minBit 15, minWin=27, winSum=449
1600 22:53:45.605018 TX Vref=30, minBit 8, minWin=27, winSum=450
1601 22:53:45.605069 TX Vref=32, minBit 8, minWin=27, winSum=446
1602 22:53:45.605121 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 26
1603 22:53:45.605173
1604 22:53:45.605224 Final TX Range 1 Vref 26
1605 22:53:45.605275
1606 22:53:45.605325 ==
1607 22:53:45.605375 Dram Type= 6, Freq= 0, CH_1, rank 0
1608 22:53:45.605426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1609 22:53:45.605477 ==
1610 22:53:45.605527
1611 22:53:45.605578
1612 22:53:45.605628 TX Vref Scan disable
1613 22:53:45.605678 == TX Byte 0 ==
1614 22:53:45.605728 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1615 22:53:45.605779 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1616 22:53:45.605830 == TX Byte 1 ==
1617 22:53:45.605881 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1618 22:53:45.605931 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1619 22:53:45.605982
1620 22:53:45.606032 [DATLAT]
1621 22:53:45.606083 Freq=800, CH1 RK0
1622 22:53:45.606143
1623 22:53:45.606256 DATLAT Default: 0xa
1624 22:53:45.606336 0, 0xFFFF, sum = 0
1625 22:53:45.606419 1, 0xFFFF, sum = 0
1626 22:53:45.606501 2, 0xFFFF, sum = 0
1627 22:53:45.606583 3, 0xFFFF, sum = 0
1628 22:53:45.606665 4, 0xFFFF, sum = 0
1629 22:53:45.606747 5, 0xFFFF, sum = 0
1630 22:53:45.606829 6, 0xFFFF, sum = 0
1631 22:53:45.606910 7, 0xFFFF, sum = 0
1632 22:53:45.606992 8, 0xFFFF, sum = 0
1633 22:53:45.607074 9, 0x0, sum = 1
1634 22:53:45.607155 10, 0x0, sum = 2
1635 22:53:45.607237 11, 0x0, sum = 3
1636 22:53:45.607319 12, 0x0, sum = 4
1637 22:53:45.607401 best_step = 10
1638 22:53:45.607480
1639 22:53:45.607559 ==
1640 22:53:45.607639 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 22:53:45.607720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 22:53:45.607800 ==
1643 22:53:45.607880 RX Vref Scan: 1
1644 22:53:45.607959
1645 22:53:45.608039 Set Vref Range= 32 -> 127
1646 22:53:45.608119
1647 22:53:45.608199 RX Vref 32 -> 127, step: 1
1648 22:53:45.608278
1649 22:53:45.608358 RX Delay -111 -> 252, step: 8
1650 22:53:45.608437
1651 22:53:45.608517 Set Vref, RX VrefLevel [Byte0]: 32
1652 22:53:45.608597 [Byte1]: 32
1653 22:53:45.608676
1654 22:53:45.608756 Set Vref, RX VrefLevel [Byte0]: 33
1655 22:53:45.608837 [Byte1]: 33
1656 22:53:45.608916
1657 22:53:45.609034 Set Vref, RX VrefLevel [Byte0]: 34
1658 22:53:45.609113 [Byte1]: 34
1659 22:53:45.609193
1660 22:53:45.609272 Set Vref, RX VrefLevel [Byte0]: 35
1661 22:53:45.609352 [Byte1]: 35
1662 22:53:45.609432
1663 22:53:45.609512 Set Vref, RX VrefLevel [Byte0]: 36
1664 22:53:45.609592 [Byte1]: 36
1665 22:53:45.609671
1666 22:53:45.609751 Set Vref, RX VrefLevel [Byte0]: 37
1667 22:53:45.609831 [Byte1]: 37
1668 22:53:45.609910
1669 22:53:45.609990 Set Vref, RX VrefLevel [Byte0]: 38
1670 22:53:45.610070 [Byte1]: 38
1671 22:53:45.610149
1672 22:53:45.610245 Set Vref, RX VrefLevel [Byte0]: 39
1673 22:53:45.610296 [Byte1]: 39
1674 22:53:45.610348
1675 22:53:45.610398 Set Vref, RX VrefLevel [Byte0]: 40
1676 22:53:45.610450 [Byte1]: 40
1677 22:53:45.610500
1678 22:53:45.610551 Set Vref, RX VrefLevel [Byte0]: 41
1679 22:53:45.610602 [Byte1]: 41
1680 22:53:45.610653
1681 22:53:45.610704 Set Vref, RX VrefLevel [Byte0]: 42
1682 22:53:45.610755 [Byte1]: 42
1683 22:53:45.610805
1684 22:53:45.610855 Set Vref, RX VrefLevel [Byte0]: 43
1685 22:53:45.610906 [Byte1]: 43
1686 22:53:45.610985
1687 22:53:45.611078 Set Vref, RX VrefLevel [Byte0]: 44
1688 22:53:45.611134 [Byte1]: 44
1689 22:53:45.611188
1690 22:53:45.611240 Set Vref, RX VrefLevel [Byte0]: 45
1691 22:53:45.611291 [Byte1]: 45
1692 22:53:45.611343
1693 22:53:45.611599 Set Vref, RX VrefLevel [Byte0]: 46
1694 22:53:45.611658 [Byte1]: 46
1695 22:53:45.611729
1696 22:53:45.611811 Set Vref, RX VrefLevel [Byte0]: 47
1697 22:53:45.611878 [Byte1]: 47
1698 22:53:45.611929
1699 22:53:45.611980 Set Vref, RX VrefLevel [Byte0]: 48
1700 22:53:45.612031 [Byte1]: 48
1701 22:53:45.612082
1702 22:53:45.612133 Set Vref, RX VrefLevel [Byte0]: 49
1703 22:53:45.612184 [Byte1]: 49
1704 22:53:45.612236
1705 22:53:45.612286 Set Vref, RX VrefLevel [Byte0]: 50
1706 22:53:45.612336 [Byte1]: 50
1707 22:53:45.612388
1708 22:53:45.612438 Set Vref, RX VrefLevel [Byte0]: 51
1709 22:53:45.612489 [Byte1]: 51
1710 22:53:45.612539
1711 22:53:45.612590 Set Vref, RX VrefLevel [Byte0]: 52
1712 22:53:45.612641 [Byte1]: 52
1713 22:53:45.612691
1714 22:53:45.612741 Set Vref, RX VrefLevel [Byte0]: 53
1715 22:53:45.612792 [Byte1]: 53
1716 22:53:45.612843
1717 22:53:45.612893 Set Vref, RX VrefLevel [Byte0]: 54
1718 22:53:45.612976 [Byte1]: 54
1719 22:53:45.613026
1720 22:53:45.613076 Set Vref, RX VrefLevel [Byte0]: 55
1721 22:53:45.613127 [Byte1]: 55
1722 22:53:45.613178
1723 22:53:45.613227 Set Vref, RX VrefLevel [Byte0]: 56
1724 22:53:45.613278 [Byte1]: 56
1725 22:53:45.613328
1726 22:53:45.613379 Set Vref, RX VrefLevel [Byte0]: 57
1727 22:53:45.613430 [Byte1]: 57
1728 22:53:45.613480
1729 22:53:45.613531 Set Vref, RX VrefLevel [Byte0]: 58
1730 22:53:45.613581 [Byte1]: 58
1731 22:53:45.613632
1732 22:53:45.613683 Set Vref, RX VrefLevel [Byte0]: 59
1733 22:53:45.613733 [Byte1]: 59
1734 22:53:45.613783
1735 22:53:45.613833 Set Vref, RX VrefLevel [Byte0]: 60
1736 22:53:45.613884 [Byte1]: 60
1737 22:53:45.613934
1738 22:53:45.613985 Set Vref, RX VrefLevel [Byte0]: 61
1739 22:53:45.614035 [Byte1]: 61
1740 22:53:45.614086
1741 22:53:45.614136 Set Vref, RX VrefLevel [Byte0]: 62
1742 22:53:45.614223 [Byte1]: 62
1743 22:53:45.614288
1744 22:53:45.614338 Set Vref, RX VrefLevel [Byte0]: 63
1745 22:53:45.614389 [Byte1]: 63
1746 22:53:45.614439
1747 22:53:45.614490 Set Vref, RX VrefLevel [Byte0]: 64
1748 22:53:45.614540 [Byte1]: 64
1749 22:53:45.614591
1750 22:53:45.614641 Set Vref, RX VrefLevel [Byte0]: 65
1751 22:53:45.614693 [Byte1]: 65
1752 22:53:45.614743
1753 22:53:45.614794 Set Vref, RX VrefLevel [Byte0]: 66
1754 22:53:45.614844 [Byte1]: 66
1755 22:53:45.614895
1756 22:53:45.614946 Set Vref, RX VrefLevel [Byte0]: 67
1757 22:53:45.614996 [Byte1]: 67
1758 22:53:45.615047
1759 22:53:45.615097 Set Vref, RX VrefLevel [Byte0]: 68
1760 22:53:45.615147 [Byte1]: 68
1761 22:53:45.615198
1762 22:53:45.615249 Set Vref, RX VrefLevel [Byte0]: 69
1763 22:53:45.615299 [Byte1]: 69
1764 22:53:45.615350
1765 22:53:45.615400 Set Vref, RX VrefLevel [Byte0]: 70
1766 22:53:45.615451 [Byte1]: 70
1767 22:53:45.615501
1768 22:53:45.615551 Set Vref, RX VrefLevel [Byte0]: 71
1769 22:53:45.615602 [Byte1]: 71
1770 22:53:45.615653
1771 22:53:45.615704 Set Vref, RX VrefLevel [Byte0]: 72
1772 22:53:45.615755 [Byte1]: 72
1773 22:53:45.615806
1774 22:53:45.615857 Set Vref, RX VrefLevel [Byte0]: 73
1775 22:53:45.615907 [Byte1]: 73
1776 22:53:45.615958
1777 22:53:45.616008 Set Vref, RX VrefLevel [Byte0]: 74
1778 22:53:45.616059 [Byte1]: 74
1779 22:53:45.616110
1780 22:53:45.616160 Set Vref, RX VrefLevel [Byte0]: 75
1781 22:53:45.616210 [Byte1]: 75
1782 22:53:45.616261
1783 22:53:45.616312 Set Vref, RX VrefLevel [Byte0]: 76
1784 22:53:45.616362 [Byte1]: 76
1785 22:53:45.616414
1786 22:53:45.616464 Set Vref, RX VrefLevel [Byte0]: 77
1787 22:53:45.616515 [Byte1]: 77
1788 22:53:45.616565
1789 22:53:45.616616 Set Vref, RX VrefLevel [Byte0]: 78
1790 22:53:45.616666 [Byte1]: 78
1791 22:53:45.616717
1792 22:53:45.616767 Final RX Vref Byte 0 = 57 to rank0
1793 22:53:45.616818 Final RX Vref Byte 1 = 65 to rank0
1794 22:53:45.616869 Final RX Vref Byte 0 = 57 to rank1
1795 22:53:45.616953 Final RX Vref Byte 1 = 65 to rank1==
1796 22:53:45.617021 Dram Type= 6, Freq= 0, CH_1, rank 0
1797 22:53:45.617072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1798 22:53:45.617125 ==
1799 22:53:45.617176 DQS Delay:
1800 22:53:45.617226 DQS0 = 0, DQS1 = 0
1801 22:53:45.617277 DQM Delay:
1802 22:53:45.617328 DQM0 = 84, DQM1 = 76
1803 22:53:45.617378 DQ Delay:
1804 22:53:45.617429 DQ0 =92, DQ1 =76, DQ2 =76, DQ3 =80
1805 22:53:45.617480 DQ4 =76, DQ5 =96, DQ6 =96, DQ7 =80
1806 22:53:45.617530 DQ8 =64, DQ9 =68, DQ10 =80, DQ11 =68
1807 22:53:45.617581 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1808 22:53:45.617632
1809 22:53:45.617683
1810 22:53:45.617733 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
1811 22:53:45.617786 CH1 RK0: MR19=606, MR18=2D19
1812 22:53:45.617836 CH1_RK0: MR19=0x606, MR18=0x2D19, DQSOSC=398, MR23=63, INC=93, DEC=62
1813 22:53:45.617888
1814 22:53:45.617939 ----->DramcWriteLeveling(PI) begin...
1815 22:53:45.617992 ==
1816 22:53:45.618043 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 22:53:45.618093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1818 22:53:45.618145 ==
1819 22:53:45.618268 Write leveling (Byte 0): 28 => 28
1820 22:53:45.618322 Write leveling (Byte 1): 30 => 30
1821 22:53:45.618373 DramcWriteLeveling(PI) end<-----
1822 22:53:45.618424
1823 22:53:45.618475 ==
1824 22:53:45.618526 Dram Type= 6, Freq= 0, CH_1, rank 1
1825 22:53:45.618576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1826 22:53:45.618628 ==
1827 22:53:45.618679 [Gating] SW mode calibration
1828 22:53:45.618735 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1829 22:53:45.618830 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1830 22:53:45.618890 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1831 22:53:45.618942 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1832 22:53:45.618993 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1833 22:53:45.619045 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 22:53:45.619096 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 22:53:45.619147 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:53:45.619198 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:53:45.619249 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:53:45.619506 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:53:45.619564 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 22:53:45.619617 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 22:53:45.619669 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 22:53:45.619720 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 22:53:45.619771 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 22:53:45.619822 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 22:53:45.619874 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 22:53:45.619925 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 22:53:45.619977 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1848 22:53:45.620027 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1849 22:53:45.620078 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 22:53:45.620130 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 22:53:45.620182 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 22:53:45.620232 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 22:53:45.620283 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 22:53:45.620334 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 22:53:45.620385 0 9 4 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
1856 22:53:45.620436 0 9 8 | B1->B0 | 3030 3232 | 0 1 | (0 0) (1 1)
1857 22:53:45.620487 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1858 22:53:45.620538 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1859 22:53:45.620589 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1860 22:53:45.620640 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1861 22:53:45.620691 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1862 22:53:45.620742 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1863 22:53:45.620793 0 10 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1864 22:53:45.620844 0 10 8 | B1->B0 | 2929 2929 | 0 0 | (1 1) (1 1)
1865 22:53:45.620894 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 22:53:45.620946 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 22:53:45.620997 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 22:53:45.621048 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 22:53:45.621098 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 22:53:45.621149 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 22:53:45.621200 0 11 4 | B1->B0 | 2b2b 2626 | 0 0 | (0 0) (0 0)
1872 22:53:45.621251 0 11 8 | B1->B0 | 4242 3f3f | 0 0 | (0 0) (0 0)
1873 22:53:45.621302 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1874 22:53:45.621353 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 22:53:45.621404 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 22:53:45.621455 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1877 22:53:45.621505 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 22:53:45.621557 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 22:53:45.621608 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1880 22:53:45.621659 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1881 22:53:45.621710 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 22:53:45.621764 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 22:53:45.621856 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 22:53:45.621912 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 22:53:45.621964 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 22:53:45.622015 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 22:53:45.622067 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 22:53:45.622118 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 22:53:45.622195 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 22:53:45.622261 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 22:53:45.622312 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 22:53:45.622364 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 22:53:45.622415 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 22:53:45.622466 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 22:53:45.622517 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 22:53:45.622568 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1897 22:53:45.622619 Total UI for P1: 0, mck2ui 16
1898 22:53:45.622671 best dqsien dly found for B0: ( 0, 14, 6)
1899 22:53:45.622723 Total UI for P1: 0, mck2ui 16
1900 22:53:45.622804 best dqsien dly found for B1: ( 0, 14, 6)
1901 22:53:45.622855 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1902 22:53:45.622907 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1903 22:53:45.623010
1904 22:53:45.623110 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1905 22:53:45.623199 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1906 22:53:45.623254 [Gating] SW calibration Done
1907 22:53:45.623306 ==
1908 22:53:45.623357 Dram Type= 6, Freq= 0, CH_1, rank 1
1909 22:53:45.623409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1910 22:53:45.623461 ==
1911 22:53:45.623512 RX Vref Scan: 0
1912 22:53:45.623563
1913 22:53:45.623613 RX Vref 0 -> 0, step: 1
1914 22:53:45.623665
1915 22:53:45.623716 RX Delay -130 -> 252, step: 16
1916 22:53:45.623767 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1917 22:53:45.623818 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1918 22:53:45.623869 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1919 22:53:45.623920 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1920 22:53:45.796238 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1921 22:53:45.796378 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1922 22:53:45.796442 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1923 22:53:45.796501 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1924 22:53:45.796557 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1925 22:53:45.796612 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1926 22:53:45.796665 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1927 22:53:45.796719 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1928 22:53:45.796772 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1929 22:53:45.797034 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1930 22:53:45.797096 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1931 22:53:45.797152 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1932 22:53:45.797205 ==
1933 22:53:45.797258 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 22:53:45.797311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 22:53:45.797363 ==
1936 22:53:45.797415 DQS Delay:
1937 22:53:45.797467 DQS0 = 0, DQS1 = 0
1938 22:53:45.797518 DQM Delay:
1939 22:53:45.797569 DQM0 = 86, DQM1 = 74
1940 22:53:45.797620 DQ Delay:
1941 22:53:45.797703 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1942 22:53:45.797754 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =77
1943 22:53:45.797806 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =61
1944 22:53:45.797857 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =77
1945 22:53:45.797908
1946 22:53:45.797959
1947 22:53:45.798010 ==
1948 22:53:45.798060 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 22:53:45.798111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 22:53:45.798193 ==
1951 22:53:45.798262
1952 22:53:45.798313
1953 22:53:45.798363 TX Vref Scan disable
1954 22:53:45.798415 == TX Byte 0 ==
1955 22:53:45.798466 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1956 22:53:45.798518 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1957 22:53:45.798568 == TX Byte 1 ==
1958 22:53:45.798619 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1959 22:53:45.798671 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1960 22:53:45.798722 ==
1961 22:53:45.798772 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 22:53:45.798823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 22:53:45.798874 ==
1964 22:53:45.798925 TX Vref=22, minBit 7, minWin=27, winSum=443
1965 22:53:45.798978 TX Vref=24, minBit 8, minWin=27, winSum=447
1966 22:53:45.799028 TX Vref=26, minBit 15, minWin=27, winSum=452
1967 22:53:45.799080 TX Vref=28, minBit 1, minWin=27, winSum=449
1968 22:53:45.799131 TX Vref=30, minBit 0, minWin=28, winSum=453
1969 22:53:45.799182 TX Vref=32, minBit 15, minWin=27, winSum=447
1970 22:53:45.799233 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 30
1971 22:53:45.799285
1972 22:53:45.799335 Final TX Range 1 Vref 30
1973 22:53:45.799386
1974 22:53:45.799437 ==
1975 22:53:45.799487 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 22:53:45.799539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 22:53:45.799590 ==
1978 22:53:45.799641
1979 22:53:45.799691
1980 22:53:45.799741 TX Vref Scan disable
1981 22:53:45.799792 == TX Byte 0 ==
1982 22:53:45.799843 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1983 22:53:45.799894 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1984 22:53:45.799945 == TX Byte 1 ==
1985 22:53:45.799996 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1986 22:53:45.800047 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1987 22:53:45.800099
1988 22:53:45.800149 [DATLAT]
1989 22:53:45.800199 Freq=800, CH1 RK1
1990 22:53:45.800250
1991 22:53:45.800300 DATLAT Default: 0xa
1992 22:53:45.800351 0, 0xFFFF, sum = 0
1993 22:53:45.800403 1, 0xFFFF, sum = 0
1994 22:53:45.800455 2, 0xFFFF, sum = 0
1995 22:53:45.800507 3, 0xFFFF, sum = 0
1996 22:53:45.800559 4, 0xFFFF, sum = 0
1997 22:53:45.800610 5, 0xFFFF, sum = 0
1998 22:53:45.800662 6, 0xFFFF, sum = 0
1999 22:53:45.800713 7, 0xFFFF, sum = 0
2000 22:53:45.800764 8, 0xFFFF, sum = 0
2001 22:53:45.800816 9, 0x0, sum = 1
2002 22:53:45.800868 10, 0x0, sum = 2
2003 22:53:45.800920 11, 0x0, sum = 3
2004 22:53:45.800971 12, 0x0, sum = 4
2005 22:53:45.801023 best_step = 10
2006 22:53:45.801073
2007 22:53:45.801124 ==
2008 22:53:45.801174 Dram Type= 6, Freq= 0, CH_1, rank 1
2009 22:53:45.801225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2010 22:53:45.801275 ==
2011 22:53:45.801326 RX Vref Scan: 0
2012 22:53:45.801418
2013 22:53:45.801500 RX Vref 0 -> 0, step: 1
2014 22:53:45.801581
2015 22:53:45.801631 RX Delay -111 -> 252, step: 8
2016 22:53:45.801682 iDelay=217, Bit 0, Center 88 (-31 ~ 208) 240
2017 22:53:45.801733 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
2018 22:53:45.801784 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2019 22:53:45.801836 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
2020 22:53:45.801887 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
2021 22:53:45.801937 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2022 22:53:45.801988 iDelay=217, Bit 6, Center 96 (-23 ~ 216) 240
2023 22:53:45.802039 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
2024 22:53:45.802091 iDelay=217, Bit 8, Center 64 (-55 ~ 184) 240
2025 22:53:45.802142 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2026 22:53:45.802235 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2027 22:53:45.802288 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2028 22:53:45.802340 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2029 22:53:45.802391 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2030 22:53:45.802442 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2031 22:53:45.802493 iDelay=217, Bit 15, Center 84 (-39 ~ 208) 248
2032 22:53:45.802545 ==
2033 22:53:45.802597 Dram Type= 6, Freq= 0, CH_1, rank 1
2034 22:53:45.802648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2035 22:53:45.802700 ==
2036 22:53:45.802751 DQS Delay:
2037 22:53:45.802802 DQS0 = 0, DQS1 = 0
2038 22:53:45.802853 DQM Delay:
2039 22:53:45.802904 DQM0 = 84, DQM1 = 77
2040 22:53:45.802955 DQ Delay:
2041 22:53:45.803006 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =84
2042 22:53:45.803057 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
2043 22:53:45.803108 DQ8 =64, DQ9 =68, DQ10 =80, DQ11 =68
2044 22:53:45.803159 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
2045 22:53:45.803210
2046 22:53:45.803261
2047 22:53:45.803312 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 403 ps
2048 22:53:45.803365 CH1 RK1: MR19=606, MR18=1B14
2049 22:53:45.803416 CH1_RK1: MR19=0x606, MR18=0x1B14, DQSOSC=403, MR23=63, INC=90, DEC=60
2050 22:53:45.803468 [RxdqsGatingPostProcess] freq 800
2051 22:53:45.803519 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2052 22:53:45.803588 Pre-setting of DQS Precalculation
2053 22:53:45.803653 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2054 22:53:45.803705 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2055 22:53:45.803757 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2056 22:53:45.803808
2057 22:53:45.803859
2058 22:53:45.803936 [Calibration Summary] 1600 Mbps
2059 22:53:45.804001 CH 0, Rank 0
2060 22:53:45.804052 SW Impedance : PASS
2061 22:53:45.804103 DUTY Scan : NO K
2062 22:53:45.804154 ZQ Calibration : PASS
2063 22:53:45.804205 Jitter Meter : NO K
2064 22:53:45.804256 CBT Training : PASS
2065 22:53:45.804307 Write leveling : PASS
2066 22:53:45.804358 RX DQS gating : PASS
2067 22:53:45.804409 RX DQ/DQS(RDDQC) : PASS
2068 22:53:45.804482 TX DQ/DQS : PASS
2069 22:53:45.804567 RX DATLAT : PASS
2070 22:53:45.804620 RX DQ/DQS(Engine): PASS
2071 22:53:45.804893 TX OE : NO K
2072 22:53:45.804994 All Pass.
2073 22:53:45.805047
2074 22:53:45.805099 CH 0, Rank 1
2075 22:53:45.805165 SW Impedance : PASS
2076 22:53:45.805232 DUTY Scan : NO K
2077 22:53:45.805283 ZQ Calibration : PASS
2078 22:53:45.805334 Jitter Meter : NO K
2079 22:53:45.805385 CBT Training : PASS
2080 22:53:45.805437 Write leveling : PASS
2081 22:53:45.805488 RX DQS gating : PASS
2082 22:53:45.805539 RX DQ/DQS(RDDQC) : PASS
2083 22:53:45.805590 TX DQ/DQS : PASS
2084 22:53:45.805642 RX DATLAT : PASS
2085 22:53:45.805693 RX DQ/DQS(Engine): PASS
2086 22:53:45.805745 TX OE : NO K
2087 22:53:45.805797 All Pass.
2088 22:53:45.805848
2089 22:53:45.805899 CH 1, Rank 0
2090 22:53:45.805950 SW Impedance : PASS
2091 22:53:45.806001 DUTY Scan : NO K
2092 22:53:45.806053 ZQ Calibration : PASS
2093 22:53:45.806104 Jitter Meter : NO K
2094 22:53:45.806155 CBT Training : PASS
2095 22:53:45.806297 Write leveling : PASS
2096 22:53:45.806380 RX DQS gating : PASS
2097 22:53:45.806462 RX DQ/DQS(RDDQC) : PASS
2098 22:53:45.806542 TX DQ/DQS : PASS
2099 22:53:45.806624 RX DATLAT : PASS
2100 22:53:45.806705 RX DQ/DQS(Engine): PASS
2101 22:53:45.806785 TX OE : NO K
2102 22:53:45.806867 All Pass.
2103 22:53:45.806947
2104 22:53:45.807027 CH 1, Rank 1
2105 22:53:45.807108 SW Impedance : PASS
2106 22:53:45.807189 DUTY Scan : NO K
2107 22:53:45.807270 ZQ Calibration : PASS
2108 22:53:45.807351 Jitter Meter : NO K
2109 22:53:45.807431 CBT Training : PASS
2110 22:53:45.807542 Write leveling : PASS
2111 22:53:45.807623 RX DQS gating : PASS
2112 22:53:45.807703 RX DQ/DQS(RDDQC) : PASS
2113 22:53:45.807784 TX DQ/DQS : PASS
2114 22:53:45.807865 RX DATLAT : PASS
2115 22:53:45.807945 RX DQ/DQS(Engine): PASS
2116 22:53:45.808026 TX OE : NO K
2117 22:53:45.808106 All Pass.
2118 22:53:45.808186
2119 22:53:45.808266 DramC Write-DBI off
2120 22:53:45.808347 PER_BANK_REFRESH: Hybrid Mode
2121 22:53:45.808428 TX_TRACKING: ON
2122 22:53:45.808509 [GetDramInforAfterCalByMRR] Vendor 6.
2123 22:53:45.808590 [GetDramInforAfterCalByMRR] Revision 606.
2124 22:53:45.808671 [GetDramInforAfterCalByMRR] Revision 2 0.
2125 22:53:45.808751 MR0 0x3b3b
2126 22:53:45.808832 MR8 0x5151
2127 22:53:45.808912 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2128 22:53:45.808992
2129 22:53:45.809072 MR0 0x3b3b
2130 22:53:45.809152 MR8 0x5151
2131 22:53:45.809233 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2132 22:53:45.809313
2133 22:53:45.809395 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2134 22:53:45.809478 [FAST_K] Save calibration result to emmc
2135 22:53:45.809559 [FAST_K] Save calibration result to emmc
2136 22:53:45.809639 dram_init: config_dvfs: 1
2137 22:53:45.809751 dramc_set_vcore_voltage set vcore to 662500
2138 22:53:45.809832 Read voltage for 1200, 2
2139 22:53:45.809912 Vio18 = 0
2140 22:53:45.809991 Vcore = 662500
2141 22:53:45.810071 Vdram = 0
2142 22:53:45.810151 Vddq = 0
2143 22:53:45.810249 Vmddr = 0
2144 22:53:45.810302 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2145 22:53:45.810355 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2146 22:53:45.810407 MEM_TYPE=3, freq_sel=15
2147 22:53:45.810459 sv_algorithm_assistance_LP4_1600
2148 22:53:45.810510 ============ PULL DRAM RESETB DOWN ============
2149 22:53:45.810563 ========== PULL DRAM RESETB DOWN end =========
2150 22:53:45.810615 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2151 22:53:45.810667 ===================================
2152 22:53:45.810720 LPDDR4 DRAM CONFIGURATION
2153 22:53:45.810772 ===================================
2154 22:53:45.810823 EX_ROW_EN[0] = 0x0
2155 22:53:45.810875 EX_ROW_EN[1] = 0x0
2156 22:53:45.810926 LP4Y_EN = 0x0
2157 22:53:45.810977 WORK_FSP = 0x0
2158 22:53:45.811028 WL = 0x4
2159 22:53:45.811079 RL = 0x4
2160 22:53:45.811130 BL = 0x2
2161 22:53:45.811182 RPST = 0x0
2162 22:53:45.811233 RD_PRE = 0x0
2163 22:53:45.811283 WR_PRE = 0x1
2164 22:53:45.811334 WR_PST = 0x0
2165 22:53:45.811385 DBI_WR = 0x0
2166 22:53:45.811436 DBI_RD = 0x0
2167 22:53:45.811487 OTF = 0x1
2168 22:53:45.811539 ===================================
2169 22:53:45.811591 ===================================
2170 22:53:45.811642 ANA top config
2171 22:53:45.811693 ===================================
2172 22:53:45.811745 DLL_ASYNC_EN = 0
2173 22:53:45.811796 ALL_SLAVE_EN = 0
2174 22:53:45.811847 NEW_RANK_MODE = 1
2175 22:53:45.811900 DLL_IDLE_MODE = 1
2176 22:53:45.811951 LP45_APHY_COMB_EN = 1
2177 22:53:45.812002 TX_ODT_DIS = 1
2178 22:53:45.812055 NEW_8X_MODE = 1
2179 22:53:45.812123 ===================================
2180 22:53:45.812188 ===================================
2181 22:53:45.812240 data_rate = 2400
2182 22:53:45.812291 CKR = 1
2183 22:53:45.812342 DQ_P2S_RATIO = 8
2184 22:53:45.812393 ===================================
2185 22:53:45.812444 CA_P2S_RATIO = 8
2186 22:53:45.812495 DQ_CA_OPEN = 0
2187 22:53:45.812546 DQ_SEMI_OPEN = 0
2188 22:53:45.812597 CA_SEMI_OPEN = 0
2189 22:53:45.812648 CA_FULL_RATE = 0
2190 22:53:45.812699 DQ_CKDIV4_EN = 0
2191 22:53:45.812750 CA_CKDIV4_EN = 0
2192 22:53:45.812801 CA_PREDIV_EN = 0
2193 22:53:45.812852 PH8_DLY = 17
2194 22:53:45.812903 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2195 22:53:45.812954 DQ_AAMCK_DIV = 4
2196 22:53:45.813005 CA_AAMCK_DIV = 4
2197 22:53:45.813072 CA_ADMCK_DIV = 4
2198 22:53:45.813137 DQ_TRACK_CA_EN = 0
2199 22:53:45.813188 CA_PICK = 1200
2200 22:53:45.813256 CA_MCKIO = 1200
2201 22:53:45.813323 MCKIO_SEMI = 0
2202 22:53:45.813375 PLL_FREQ = 2366
2203 22:53:45.813425 DQ_UI_PI_RATIO = 32
2204 22:53:45.813476 CA_UI_PI_RATIO = 0
2205 22:53:45.813528 ===================================
2206 22:53:45.813579 ===================================
2207 22:53:45.813630 memory_type:LPDDR4
2208 22:53:45.813681 GP_NUM : 10
2209 22:53:45.813732 SRAM_EN : 1
2210 22:53:45.813784 MD32_EN : 0
2211 22:53:45.813834 ===================================
2212 22:53:45.813886 [ANA_INIT] >>>>>>>>>>>>>>
2213 22:53:45.813938 <<<<<< [CONFIGURE PHASE]: ANA_TX
2214 22:53:45.813989 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2215 22:53:45.814041 ===================================
2216 22:53:45.814093 data_rate = 2400,PCW = 0X5b00
2217 22:53:45.814166 ===================================
2218 22:53:45.814240 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2219 22:53:45.814518 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2220 22:53:45.814614 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2221 22:53:45.814682 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2222 22:53:45.814735 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2223 22:53:45.814787 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2224 22:53:45.814838 [ANA_INIT] flow start
2225 22:53:45.814890 [ANA_INIT] PLL >>>>>>>>
2226 22:53:45.814942 [ANA_INIT] PLL <<<<<<<<
2227 22:53:45.814993 [ANA_INIT] MIDPI >>>>>>>>
2228 22:53:45.815044 [ANA_INIT] MIDPI <<<<<<<<
2229 22:53:45.815095 [ANA_INIT] DLL >>>>>>>>
2230 22:53:45.815146 [ANA_INIT] DLL <<<<<<<<
2231 22:53:45.815197 [ANA_INIT] flow end
2232 22:53:45.815264 ============ LP4 DIFF to SE enter ============
2233 22:53:45.815318 ============ LP4 DIFF to SE exit ============
2234 22:53:45.815371 [ANA_INIT] <<<<<<<<<<<<<
2235 22:53:45.815437 [Flow] Enable top DCM control >>>>>
2236 22:53:45.815489 [Flow] Enable top DCM control <<<<<
2237 22:53:45.815540 Enable DLL master slave shuffle
2238 22:53:45.815591 ==============================================================
2239 22:53:45.815644 Gating Mode config
2240 22:53:45.815694 ==============================================================
2241 22:53:45.815746 Config description:
2242 22:53:45.815798 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2243 22:53:45.815851 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2244 22:53:45.815903 SELPH_MODE 0: By rank 1: By Phase
2245 22:53:45.815955 ==============================================================
2246 22:53:45.816007 GAT_TRACK_EN = 1
2247 22:53:45.816058 RX_GATING_MODE = 2
2248 22:53:45.816109 RX_GATING_TRACK_MODE = 2
2249 22:53:45.816161 SELPH_MODE = 1
2250 22:53:45.816213 PICG_EARLY_EN = 1
2251 22:53:45.816263 VALID_LAT_VALUE = 1
2252 22:53:45.816315 ==============================================================
2253 22:53:45.816367 Enter into Gating configuration >>>>
2254 22:53:45.816418 Exit from Gating configuration <<<<
2255 22:53:45.816469 Enter into DVFS_PRE_config >>>>>
2256 22:53:45.816521 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2257 22:53:45.816574 Exit from DVFS_PRE_config <<<<<
2258 22:53:45.816625 Enter into PICG configuration >>>>
2259 22:53:45.816676 Exit from PICG configuration <<<<
2260 22:53:45.816727 [RX_INPUT] configuration >>>>>
2261 22:53:45.816778 [RX_INPUT] configuration <<<<<
2262 22:53:45.816846 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2263 22:53:45.816911 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2264 22:53:45.816963 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2265 22:53:45.817015 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2266 22:53:45.817066 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2267 22:53:45.817118 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2268 22:53:45.817170 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2269 22:53:45.817221 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2270 22:53:45.817272 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2271 22:53:45.817324 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2272 22:53:45.817406 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2273 22:53:45.817487 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2274 22:53:45.817538 ===================================
2275 22:53:45.817589 LPDDR4 DRAM CONFIGURATION
2276 22:53:45.817641 ===================================
2277 22:53:45.817693 EX_ROW_EN[0] = 0x0
2278 22:53:45.817743 EX_ROW_EN[1] = 0x0
2279 22:53:45.817794 LP4Y_EN = 0x0
2280 22:53:45.817845 WORK_FSP = 0x0
2281 22:53:45.817896 WL = 0x4
2282 22:53:45.817947 RL = 0x4
2283 22:53:45.817998 BL = 0x2
2284 22:53:45.818049 RPST = 0x0
2285 22:53:45.818100 RD_PRE = 0x0
2286 22:53:45.818151 WR_PRE = 0x1
2287 22:53:45.818247 WR_PST = 0x0
2288 22:53:45.818298 DBI_WR = 0x0
2289 22:53:45.818349 DBI_RD = 0x0
2290 22:53:45.818401 OTF = 0x1
2291 22:53:45.818452 ===================================
2292 22:53:45.818504 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2293 22:53:45.818556 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2294 22:53:45.818607 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2295 22:53:45.818659 ===================================
2296 22:53:45.818710 LPDDR4 DRAM CONFIGURATION
2297 22:53:45.818761 ===================================
2298 22:53:45.818812 EX_ROW_EN[0] = 0x10
2299 22:53:45.818863 EX_ROW_EN[1] = 0x0
2300 22:53:45.818913 LP4Y_EN = 0x0
2301 22:53:45.818964 WORK_FSP = 0x0
2302 22:53:45.819014 WL = 0x4
2303 22:53:45.819065 RL = 0x4
2304 22:53:45.819115 BL = 0x2
2305 22:53:45.819166 RPST = 0x0
2306 22:53:45.819216 RD_PRE = 0x0
2307 22:53:45.819283 WR_PRE = 0x1
2308 22:53:45.819364 WR_PST = 0x0
2309 22:53:45.819446 DBI_WR = 0x0
2310 22:53:45.819511 DBI_RD = 0x0
2311 22:53:45.819561 OTF = 0x1
2312 22:53:45.819612 ===================================
2313 22:53:45.819663 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2314 22:53:45.819715 ==
2315 22:53:45.819766 Dram Type= 6, Freq= 0, CH_0, rank 0
2316 22:53:45.819817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2317 22:53:45.819868 ==
2318 22:53:45.819918 [Duty_Offset_Calibration]
2319 22:53:45.819969 B0:1 B1:-1 CA:0
2320 22:53:45.820019
2321 22:53:45.820069 [DutyScan_Calibration_Flow] k_type=0
2322 22:53:45.820119
2323 22:53:45.820169 ==CLK 0==
2324 22:53:45.820220 Final CLK duty delay cell = 0
2325 22:53:45.820271 [0] MAX Duty = 5094%(X100), DQS PI = 16
2326 22:53:45.820322 [0] MIN Duty = 4875%(X100), DQS PI = 8
2327 22:53:45.820373 [0] AVG Duty = 4984%(X100)
2328 22:53:45.820423
2329 22:53:45.820474 CH0 CLK Duty spec in!! Max-Min= 219%
2330 22:53:45.820525 [DutyScan_Calibration_Flow] ====Done====
2331 22:53:45.820575
2332 22:53:45.820626 [DutyScan_Calibration_Flow] k_type=1
2333 22:53:45.820677
2334 22:53:45.820727 ==DQS 0 ==
2335 22:53:45.820981 Final DQS duty delay cell = -4
2336 22:53:45.821041 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2337 22:53:45.821095 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2338 22:53:45.821146 [-4] AVG Duty = 4968%(X100)
2339 22:53:45.821197
2340 22:53:45.821248 ==DQS 1 ==
2341 22:53:45.821300 Final DQS duty delay cell = -4
2342 22:53:45.821352 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2343 22:53:45.821402 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2344 22:53:45.821453 [-4] AVG Duty = 4938%(X100)
2345 22:53:45.821504
2346 22:53:45.821555 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2347 22:53:45.821606
2348 22:53:45.821656 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2349 22:53:45.821707 [DutyScan_Calibration_Flow] ====Done====
2350 22:53:45.821758
2351 22:53:45.821809 [DutyScan_Calibration_Flow] k_type=3
2352 22:53:45.821860
2353 22:53:45.821910 ==DQM 0 ==
2354 22:53:45.821961 Final DQM duty delay cell = 0
2355 22:53:45.822013 [0] MAX Duty = 5062%(X100), DQS PI = 24
2356 22:53:45.822063 [0] MIN Duty = 4875%(X100), DQS PI = 8
2357 22:53:45.822131 [0] AVG Duty = 4968%(X100)
2358 22:53:45.822191
2359 22:53:45.822258 ==DQM 1 ==
2360 22:53:45.822309 Final DQM duty delay cell = 4
2361 22:53:45.822360 [4] MAX Duty = 5187%(X100), DQS PI = 54
2362 22:53:45.822412 [4] MIN Duty = 4969%(X100), DQS PI = 26
2363 22:53:45.822463 [4] AVG Duty = 5078%(X100)
2364 22:53:45.822514
2365 22:53:45.822565 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2366 22:53:45.822615
2367 22:53:45.822666 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2368 22:53:45.822717 [DutyScan_Calibration_Flow] ====Done====
2369 22:53:45.822767
2370 22:53:45.822818 [DutyScan_Calibration_Flow] k_type=2
2371 22:53:45.822869
2372 22:53:45.822920 ==DQ 0 ==
2373 22:53:45.822971 Final DQ duty delay cell = -4
2374 22:53:45.823021 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2375 22:53:45.823072 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2376 22:53:45.823124 [-4] AVG Duty = 4969%(X100)
2377 22:53:45.823174
2378 22:53:45.823226 ==DQ 1 ==
2379 22:53:45.823283 Final DQ duty delay cell = -4
2380 22:53:45.823348 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2381 22:53:45.823401 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2382 22:53:45.823453 [-4] AVG Duty = 4922%(X100)
2383 22:53:45.823504
2384 22:53:45.823555 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2385 22:53:45.823606
2386 22:53:45.823657 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2387 22:53:45.823708 [DutyScan_Calibration_Flow] ====Done====
2388 22:53:45.823759 ==
2389 22:53:45.823810 Dram Type= 6, Freq= 0, CH_1, rank 0
2390 22:53:45.823862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2391 22:53:45.823914 ==
2392 22:53:45.823965 [Duty_Offset_Calibration]
2393 22:53:45.824016 B0:-1 B1:1 CA:1
2394 22:53:45.824067
2395 22:53:45.824118 [DutyScan_Calibration_Flow] k_type=0
2396 22:53:45.824168
2397 22:53:45.824219 ==CLK 0==
2398 22:53:45.824270 Final CLK duty delay cell = 0
2399 22:53:45.824321 [0] MAX Duty = 5156%(X100), DQS PI = 38
2400 22:53:45.824372 [0] MIN Duty = 4969%(X100), DQS PI = 0
2401 22:53:45.824423 [0] AVG Duty = 5062%(X100)
2402 22:53:45.824474
2403 22:53:45.824524 CH1 CLK Duty spec in!! Max-Min= 187%
2404 22:53:45.824576 [DutyScan_Calibration_Flow] ====Done====
2405 22:53:45.824626
2406 22:53:45.824676 [DutyScan_Calibration_Flow] k_type=1
2407 22:53:45.824727
2408 22:53:45.824777 ==DQS 0 ==
2409 22:53:45.824828 Final DQS duty delay cell = 0
2410 22:53:45.824879 [0] MAX Duty = 5124%(X100), DQS PI = 48
2411 22:53:45.824930 [0] MIN Duty = 4875%(X100), DQS PI = 6
2412 22:53:45.824981 [0] AVG Duty = 4999%(X100)
2413 22:53:45.825032
2414 22:53:45.825082 ==DQS 1 ==
2415 22:53:45.825133 Final DQS duty delay cell = 0
2416 22:53:45.825185 [0] MAX Duty = 5062%(X100), DQS PI = 12
2417 22:53:45.825235 [0] MIN Duty = 4969%(X100), DQS PI = 56
2418 22:53:45.825286 [0] AVG Duty = 5015%(X100)
2419 22:53:45.825337
2420 22:53:45.825387 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2421 22:53:45.825440
2422 22:53:45.825491 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2423 22:53:45.825541 [DutyScan_Calibration_Flow] ====Done====
2424 22:53:45.825592
2425 22:53:45.825642 [DutyScan_Calibration_Flow] k_type=3
2426 22:53:45.825693
2427 22:53:45.825743 ==DQM 0 ==
2428 22:53:45.825794 Final DQM duty delay cell = -4
2429 22:53:45.825846 [-4] MAX Duty = 5031%(X100), DQS PI = 18
2430 22:53:45.825897 [-4] MIN Duty = 4844%(X100), DQS PI = 6
2431 22:53:45.825947 [-4] AVG Duty = 4937%(X100)
2432 22:53:45.825998
2433 22:53:45.826049 ==DQM 1 ==
2434 22:53:45.826100 Final DQM duty delay cell = 0
2435 22:53:45.826151 [0] MAX Duty = 5156%(X100), DQS PI = 4
2436 22:53:45.826271 [0] MIN Duty = 4969%(X100), DQS PI = 30
2437 22:53:45.826351 [0] AVG Duty = 5062%(X100)
2438 22:53:45.826431
2439 22:53:45.826511 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2440 22:53:45.826590
2441 22:53:45.826670 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2442 22:53:45.826751 [DutyScan_Calibration_Flow] ====Done====
2443 22:53:45.826830
2444 22:53:45.826909 [DutyScan_Calibration_Flow] k_type=2
2445 22:53:45.826998
2446 22:53:45.827055 ==DQ 0 ==
2447 22:53:45.827107 Final DQ duty delay cell = 0
2448 22:53:45.827159 [0] MAX Duty = 5187%(X100), DQS PI = 30
2449 22:53:45.827210 [0] MIN Duty = 4907%(X100), DQS PI = 6
2450 22:53:45.827262 [0] AVG Duty = 5047%(X100)
2451 22:53:45.827312
2452 22:53:45.827364 ==DQ 1 ==
2453 22:53:45.827415 Final DQ duty delay cell = 0
2454 22:53:45.827467 [0] MAX Duty = 5124%(X100), DQS PI = 10
2455 22:53:45.827517 [0] MIN Duty = 4969%(X100), DQS PI = 0
2456 22:53:45.827568 [0] AVG Duty = 5046%(X100)
2457 22:53:45.827619
2458 22:53:45.827670 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2459 22:53:45.827721
2460 22:53:45.827771 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2461 22:53:45.827822 [DutyScan_Calibration_Flow] ====Done====
2462 22:53:45.827873 nWR fixed to 30
2463 22:53:45.827925 [ModeRegInit_LP4] CH0 RK0
2464 22:53:45.827977 [ModeRegInit_LP4] CH0 RK1
2465 22:53:45.828028 [ModeRegInit_LP4] CH1 RK0
2466 22:53:45.828079 [ModeRegInit_LP4] CH1 RK1
2467 22:53:45.828129 match AC timing 7
2468 22:53:45.828180 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2469 22:53:45.828232 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2470 22:53:45.828283 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2471 22:53:45.828334 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2472 22:53:45.828386 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2473 22:53:45.828436 ==
2474 22:53:45.828488 Dram Type= 6, Freq= 0, CH_0, rank 0
2475 22:53:45.828539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2476 22:53:45.828590 ==
2477 22:53:45.828641 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2478 22:53:45.828693 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2479 22:53:45.828745 [CA 0] Center 39 (9~70) winsize 62
2480 22:53:45.828796 [CA 1] Center 39 (9~69) winsize 61
2481 22:53:45.828846 [CA 2] Center 35 (5~66) winsize 62
2482 22:53:45.828898 [CA 3] Center 35 (5~66) winsize 62
2483 22:53:45.828948 [CA 4] Center 33 (4~63) winsize 60
2484 22:53:45.828999 [CA 5] Center 33 (3~63) winsize 61
2485 22:53:45.829050
2486 22:53:45.829100 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2487 22:53:45.829151
2488 22:53:45.829408 [CATrainingPosCal] consider 1 rank data
2489 22:53:45.829466 u2DelayCellTimex100 = 270/100 ps
2490 22:53:45.829518 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2491 22:53:45.829570 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2492 22:53:45.829621 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2493 22:53:45.829672 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2494 22:53:45.829723 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2495 22:53:45.829774 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2496 22:53:45.829826
2497 22:53:45.829876 CA PerBit enable=1, Macro0, CA PI delay=33
2498 22:53:45.829927
2499 22:53:45.829978 [CBTSetCACLKResult] CA Dly = 33
2500 22:53:45.830029 CS Dly: 8 (0~39)
2501 22:53:45.830080 ==
2502 22:53:45.830131 Dram Type= 6, Freq= 0, CH_0, rank 1
2503 22:53:45.830230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2504 22:53:45.830284 ==
2505 22:53:45.830335 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2506 22:53:45.830386 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2507 22:53:45.830437 [CA 0] Center 39 (9~70) winsize 62
2508 22:53:45.830488 [CA 1] Center 39 (9~70) winsize 62
2509 22:53:45.830539 [CA 2] Center 35 (5~66) winsize 62
2510 22:53:45.830590 [CA 3] Center 34 (4~65) winsize 62
2511 22:53:45.830641 [CA 4] Center 33 (3~64) winsize 62
2512 22:53:45.830692 [CA 5] Center 33 (3~63) winsize 61
2513 22:53:45.830742
2514 22:53:45.830793 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2515 22:53:45.830844
2516 22:53:45.830894 [CATrainingPosCal] consider 2 rank data
2517 22:53:45.830946 u2DelayCellTimex100 = 270/100 ps
2518 22:53:45.830997 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2519 22:53:45.831049 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2520 22:53:45.831100 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2521 22:53:45.831151 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2522 22:53:45.831202 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2523 22:53:45.831253 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2524 22:53:45.831303
2525 22:53:45.831355 CA PerBit enable=1, Macro0, CA PI delay=33
2526 22:53:45.831406
2527 22:53:45.831457 [CBTSetCACLKResult] CA Dly = 33
2528 22:53:45.831507 CS Dly: 9 (0~41)
2529 22:53:45.831558
2530 22:53:45.831609 ----->DramcWriteLeveling(PI) begin...
2531 22:53:45.831661 ==
2532 22:53:45.831712 Dram Type= 6, Freq= 0, CH_0, rank 0
2533 22:53:45.831763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 22:53:45.831814 ==
2535 22:53:45.831865 Write leveling (Byte 0): 32 => 32
2536 22:53:45.831917 Write leveling (Byte 1): 31 => 31
2537 22:53:45.831967 DramcWriteLeveling(PI) end<-----
2538 22:53:45.832018
2539 22:53:45.832068 ==
2540 22:53:45.832119 Dram Type= 6, Freq= 0, CH_0, rank 0
2541 22:53:45.832170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 22:53:45.832221 ==
2543 22:53:45.832273 [Gating] SW mode calibration
2544 22:53:45.832325 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2545 22:53:45.832377 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2546 22:53:45.832428 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
2547 22:53:45.832480 0 15 4 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2548 22:53:45.832531 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (1 1) (1 1)
2549 22:53:45.832582 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2550 22:53:45.832633 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2551 22:53:45.832683 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2552 22:53:45.832734 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2553 22:53:45.832785 0 15 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
2554 22:53:45.832836 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
2555 22:53:45.832888 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2556 22:53:45.832939 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2557 22:53:45.832991 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2558 22:53:45.833042 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2559 22:53:45.833093 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2560 22:53:45.833144 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2561 22:53:45.833195 1 0 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
2562 22:53:45.833246 1 1 0 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
2563 22:53:45.833297 1 1 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2564 22:53:45.833348 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2565 22:53:45.833399 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 22:53:45.833450 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2567 22:53:45.833500 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2568 22:53:45.833551 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2569 22:53:45.833633 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2570 22:53:45.833684 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2571 22:53:45.833735 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2572 22:53:45.833786 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 22:53:45.833837 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 22:53:45.833889 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 22:53:45.833939 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 22:53:45.833990 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 22:53:45.834042 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 22:53:45.834093 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 22:53:45.834143 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 22:53:45.834238 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 22:53:45.834291 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 22:53:45.834342 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 22:53:45.834393 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 22:53:45.834444 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 22:53:45.834495 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2586 22:53:45.834546 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2587 22:53:45.834597 Total UI for P1: 0, mck2ui 16
2588 22:53:45.834648 best dqsien dly found for B0: ( 1, 3, 28)
2589 22:53:45.834700 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2590 22:53:45.834966 Total UI for P1: 0, mck2ui 16
2591 22:53:45.835029 best dqsien dly found for B1: ( 1, 4, 0)
2592 22:53:45.835082 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2593 22:53:45.835133 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2594 22:53:45.835185
2595 22:53:45.835236 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2596 22:53:45.835306 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2597 22:53:45.835371 [Gating] SW calibration Done
2598 22:53:45.835422 ==
2599 22:53:45.835474 Dram Type= 6, Freq= 0, CH_0, rank 0
2600 22:53:45.835525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2601 22:53:45.835577 ==
2602 22:53:45.835628 RX Vref Scan: 0
2603 22:53:45.835679
2604 22:53:45.835729 RX Vref 0 -> 0, step: 1
2605 22:53:45.835780
2606 22:53:45.835832 RX Delay -40 -> 252, step: 8
2607 22:53:45.835883 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2608 22:53:45.835934 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2609 22:53:45.835984 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2610 22:53:45.836035 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2611 22:53:45.836086 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2612 22:53:45.836137 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2613 22:53:45.836187 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2614 22:53:45.836239 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2615 22:53:45.836289 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2616 22:53:45.836340 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2617 22:53:45.836390 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2618 22:53:45.836441 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2619 22:53:45.836492 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2620 22:53:45.836543 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2621 22:53:45.836594 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2622 22:53:45.836644 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2623 22:53:45.836695 ==
2624 22:53:45.836746 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 22:53:45.836797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 22:53:45.836848 ==
2627 22:53:45.836899 DQS Delay:
2628 22:53:45.836950 DQS0 = 0, DQS1 = 0
2629 22:53:45.837000 DQM Delay:
2630 22:53:45.837051 DQM0 = 119, DQM1 = 107
2631 22:53:45.837132 DQ Delay:
2632 22:53:45.837183 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2633 22:53:45.837234 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2634 22:53:45.837284 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2635 22:53:45.837335 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2636 22:53:45.837386
2637 22:53:45.837436
2638 22:53:45.837487 ==
2639 22:53:45.837537 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 22:53:45.837610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 22:53:45.837664 ==
2642 22:53:45.837715
2643 22:53:45.837766
2644 22:53:45.837816 TX Vref Scan disable
2645 22:53:45.837867 == TX Byte 0 ==
2646 22:53:45.837918 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2647 22:53:45.837969 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2648 22:53:45.838021 == TX Byte 1 ==
2649 22:53:45.838072 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2650 22:53:45.838123 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2651 22:53:45.838201 ==
2652 22:53:45.838266 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 22:53:45.838317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 22:53:45.838369 ==
2655 22:53:45.838420 TX Vref=22, minBit 7, minWin=25, winSum=418
2656 22:53:45.838471 TX Vref=24, minBit 1, minWin=25, winSum=420
2657 22:53:45.838521 TX Vref=26, minBit 1, minWin=25, winSum=423
2658 22:53:45.838572 TX Vref=28, minBit 1, minWin=26, winSum=428
2659 22:53:45.838623 TX Vref=30, minBit 9, minWin=26, winSum=430
2660 22:53:45.838674 TX Vref=32, minBit 10, minWin=25, winSum=429
2661 22:53:45.838726 [TxChooseVref] Worse bit 9, Min win 26, Win sum 430, Final Vref 30
2662 22:53:45.838777
2663 22:53:45.838828 Final TX Range 1 Vref 30
2664 22:53:45.838879
2665 22:53:45.838930 ==
2666 22:53:45.838980 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 22:53:45.839031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 22:53:45.839083 ==
2669 22:53:45.839132
2670 22:53:45.839183
2671 22:53:45.839233 TX Vref Scan disable
2672 22:53:45.839300 == TX Byte 0 ==
2673 22:53:45.839365 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2674 22:53:45.839416 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2675 22:53:45.839467 == TX Byte 1 ==
2676 22:53:45.839517 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2677 22:53:45.839568 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2678 22:53:45.839618
2679 22:53:45.839669 [DATLAT]
2680 22:53:45.839719 Freq=1200, CH0 RK0
2681 22:53:45.839771
2682 22:53:45.839820 DATLAT Default: 0xd
2683 22:53:45.839871 0, 0xFFFF, sum = 0
2684 22:53:45.839923 1, 0xFFFF, sum = 0
2685 22:53:45.839975 2, 0xFFFF, sum = 0
2686 22:53:45.840026 3, 0xFFFF, sum = 0
2687 22:53:45.840078 4, 0xFFFF, sum = 0
2688 22:53:45.840130 5, 0xFFFF, sum = 0
2689 22:53:45.840181 6, 0xFFFF, sum = 0
2690 22:53:45.840233 7, 0xFFFF, sum = 0
2691 22:53:45.840284 8, 0xFFFF, sum = 0
2692 22:53:45.840365 9, 0xFFFF, sum = 0
2693 22:53:45.840416 10, 0xFFFF, sum = 0
2694 22:53:45.840467 11, 0xFFFF, sum = 0
2695 22:53:45.840518 12, 0x0, sum = 1
2696 22:53:45.840571 13, 0x0, sum = 2
2697 22:53:45.840623 14, 0x0, sum = 3
2698 22:53:45.840674 15, 0x0, sum = 4
2699 22:53:45.840726 best_step = 13
2700 22:53:45.840777
2701 22:53:45.840827 ==
2702 22:53:45.840877 Dram Type= 6, Freq= 0, CH_0, rank 0
2703 22:53:45.840929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2704 22:53:45.840980 ==
2705 22:53:45.841030 RX Vref Scan: 1
2706 22:53:45.841081
2707 22:53:45.841131 Set Vref Range= 32 -> 127
2708 22:53:45.841182
2709 22:53:45.841233 RX Vref 32 -> 127, step: 1
2710 22:53:45.841300
2711 22:53:45.841365 RX Delay -21 -> 252, step: 4
2712 22:53:45.841416
2713 22:53:45.841467 Set Vref, RX VrefLevel [Byte0]: 32
2714 22:53:45.841518 [Byte1]: 32
2715 22:53:45.841568
2716 22:53:45.841618 Set Vref, RX VrefLevel [Byte0]: 33
2717 22:53:45.841669 [Byte1]: 33
2718 22:53:45.841720
2719 22:53:45.841770 Set Vref, RX VrefLevel [Byte0]: 34
2720 22:53:45.841820 [Byte1]: 34
2721 22:53:45.841870
2722 22:53:45.841921 Set Vref, RX VrefLevel [Byte0]: 35
2723 22:53:45.841972 [Byte1]: 35
2724 22:53:45.842022
2725 22:53:45.842072 Set Vref, RX VrefLevel [Byte0]: 36
2726 22:53:45.842123 [Byte1]: 36
2727 22:53:45.842196
2728 22:53:45.842261 Set Vref, RX VrefLevel [Byte0]: 37
2729 22:53:45.842312 [Byte1]: 37
2730 22:53:45.842362
2731 22:53:45.842413 Set Vref, RX VrefLevel [Byte0]: 38
2732 22:53:45.842463 [Byte1]: 38
2733 22:53:45.842513
2734 22:53:45.842564 Set Vref, RX VrefLevel [Byte0]: 39
2735 22:53:45.842615 [Byte1]: 39
2736 22:53:45.842665
2737 22:53:45.842716 Set Vref, RX VrefLevel [Byte0]: 40
2738 22:53:45.842766 [Byte1]: 40
2739 22:53:45.842816
2740 22:53:45.842866 Set Vref, RX VrefLevel [Byte0]: 41
2741 22:53:45.842918 [Byte1]: 41
2742 22:53:45.842968
2743 22:53:45.843019 Set Vref, RX VrefLevel [Byte0]: 42
2744 22:53:45.843070 [Byte1]: 42
2745 22:53:45.843120
2746 22:53:45.843422 Set Vref, RX VrefLevel [Byte0]: 43
2747 22:53:45.843568 [Byte1]: 43
2748 22:53:45.843727
2749 22:53:45.843851 Set Vref, RX VrefLevel [Byte0]: 44
2750 22:53:45.843964 [Byte1]: 44
2751 22:53:45.844058
2752 22:53:45.844141 Set Vref, RX VrefLevel [Byte0]: 45
2753 22:53:45.844217 [Byte1]: 45
2754 22:53:45.844271
2755 22:53:45.844323 Set Vref, RX VrefLevel [Byte0]: 46
2756 22:53:45.844375 [Byte1]: 46
2757 22:53:45.844427
2758 22:53:45.844478 Set Vref, RX VrefLevel [Byte0]: 47
2759 22:53:45.844530 [Byte1]: 47
2760 22:53:45.844581
2761 22:53:45.844632 Set Vref, RX VrefLevel [Byte0]: 48
2762 22:53:45.844683 [Byte1]: 48
2763 22:53:45.844734
2764 22:53:45.844784 Set Vref, RX VrefLevel [Byte0]: 49
2765 22:53:45.844835 [Byte1]: 49
2766 22:53:45.844886
2767 22:53:45.844936 Set Vref, RX VrefLevel [Byte0]: 50
2768 22:53:45.844986 [Byte1]: 50
2769 22:53:45.845036
2770 22:53:45.845086 Set Vref, RX VrefLevel [Byte0]: 51
2771 22:53:45.845137 [Byte1]: 51
2772 22:53:45.845187
2773 22:53:45.845241 Set Vref, RX VrefLevel [Byte0]: 52
2774 22:53:45.845299 [Byte1]: 52
2775 22:53:45.845350
2776 22:53:45.845401 Set Vref, RX VrefLevel [Byte0]: 53
2777 22:53:45.845452 [Byte1]: 53
2778 22:53:45.845502
2779 22:53:45.845552 Set Vref, RX VrefLevel [Byte0]: 54
2780 22:53:45.845603 [Byte1]: 54
2781 22:53:45.845653
2782 22:53:45.845704 Set Vref, RX VrefLevel [Byte0]: 55
2783 22:53:45.845762 [Byte1]: 55
2784 22:53:45.845842
2785 22:53:45.845907 Set Vref, RX VrefLevel [Byte0]: 56
2786 22:53:45.845958 [Byte1]: 56
2787 22:53:45.846011
2788 22:53:45.846092 Set Vref, RX VrefLevel [Byte0]: 57
2789 22:53:45.846197 [Byte1]: 57
2790 22:53:45.846265
2791 22:53:45.846315 Set Vref, RX VrefLevel [Byte0]: 58
2792 22:53:45.846366 [Byte1]: 58
2793 22:53:45.846416
2794 22:53:45.846466 Set Vref, RX VrefLevel [Byte0]: 59
2795 22:53:45.846517 [Byte1]: 59
2796 22:53:45.846568
2797 22:53:45.846618 Set Vref, RX VrefLevel [Byte0]: 60
2798 22:53:45.846669 [Byte1]: 60
2799 22:53:45.846719
2800 22:53:45.846769 Set Vref, RX VrefLevel [Byte0]: 61
2801 22:53:45.846819 [Byte1]: 61
2802 22:53:45.846869
2803 22:53:45.846920 Set Vref, RX VrefLevel [Byte0]: 62
2804 22:53:45.846970 [Byte1]: 62
2805 22:53:45.847035
2806 22:53:45.847119 Set Vref, RX VrefLevel [Byte0]: 63
2807 22:53:45.847170 [Byte1]: 63
2808 22:53:45.847220
2809 22:53:45.847292 Set Vref, RX VrefLevel [Byte0]: 64
2810 22:53:45.847411 [Byte1]: 64
2811 22:53:45.847483
2812 22:53:45.847536 Set Vref, RX VrefLevel [Byte0]: 65
2813 22:53:45.847587 [Byte1]: 65
2814 22:53:45.847637
2815 22:53:45.847688 Set Vref, RX VrefLevel [Byte0]: 66
2816 22:53:45.847738 [Byte1]: 66
2817 22:53:45.847788
2818 22:53:45.847839 Set Vref, RX VrefLevel [Byte0]: 67
2819 22:53:45.847889 [Byte1]: 67
2820 22:53:45.847939
2821 22:53:45.847990 Set Vref, RX VrefLevel [Byte0]: 68
2822 22:53:45.848040 [Byte1]: 68
2823 22:53:45.848091
2824 22:53:45.848140 Set Vref, RX VrefLevel [Byte0]: 69
2825 22:53:45.848191 [Byte1]: 69
2826 22:53:45.848242
2827 22:53:45.848292 Set Vref, RX VrefLevel [Byte0]: 70
2828 22:53:45.848342 [Byte1]: 70
2829 22:53:45.848392
2830 22:53:45.848442 Set Vref, RX VrefLevel [Byte0]: 71
2831 22:53:45.848493 [Byte1]: 71
2832 22:53:45.848543
2833 22:53:45.848594 Set Vref, RX VrefLevel [Byte0]: 72
2834 22:53:45.848644 [Byte1]: 72
2835 22:53:45.848709
2836 22:53:45.848761 Set Vref, RX VrefLevel [Byte0]: 73
2837 22:53:45.848811 [Byte1]: 73
2838 22:53:45.848861
2839 22:53:45.848911 Set Vref, RX VrefLevel [Byte0]: 74
2840 22:53:45.848961 [Byte1]: 74
2841 22:53:45.849011
2842 22:53:45.849061 Set Vref, RX VrefLevel [Byte0]: 75
2843 22:53:45.849111 [Byte1]: 75
2844 22:53:45.849161
2845 22:53:45.849211 Set Vref, RX VrefLevel [Byte0]: 76
2846 22:53:45.849278 [Byte1]: 76
2847 22:53:45.849353
2848 22:53:45.849417 Set Vref, RX VrefLevel [Byte0]: 77
2849 22:53:45.849468 [Byte1]: 77
2850 22:53:45.849518
2851 22:53:45.849568 Final RX Vref Byte 0 = 59 to rank0
2852 22:53:45.849619 Final RX Vref Byte 1 = 58 to rank0
2853 22:53:45.849669 Final RX Vref Byte 0 = 59 to rank1
2854 22:53:45.849719 Final RX Vref Byte 1 = 58 to rank1==
2855 22:53:45.849770 Dram Type= 6, Freq= 0, CH_0, rank 0
2856 22:53:45.849820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2857 22:53:45.849871 ==
2858 22:53:45.849922 DQS Delay:
2859 22:53:45.849972 DQS0 = 0, DQS1 = 0
2860 22:53:45.850022 DQM Delay:
2861 22:53:45.850072 DQM0 = 118, DQM1 = 108
2862 22:53:45.850122 DQ Delay:
2863 22:53:45.850203 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2864 22:53:45.850283 DQ4 =120, DQ5 =114, DQ6 =124, DQ7 =124
2865 22:53:45.850335 DQ8 =96, DQ9 =94, DQ10 =112, DQ11 =102
2866 22:53:45.850402 DQ12 =112, DQ13 =112, DQ14 =122, DQ15 =114
2867 22:53:45.850455
2868 22:53:45.850506
2869 22:53:45.850557 [DQSOSCAuto] RK0, (LSB)MR18= 0xefa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 404 ps
2870 22:53:45.850609 CH0 RK0: MR19=403, MR18=EFA
2871 22:53:45.850660 CH0_RK0: MR19=0x403, MR18=0xEFA, DQSOSC=404, MR23=63, INC=40, DEC=26
2872 22:53:45.850711
2873 22:53:45.850761 ----->DramcWriteLeveling(PI) begin...
2874 22:53:45.850813 ==
2875 22:53:45.850863 Dram Type= 6, Freq= 0, CH_0, rank 1
2876 22:53:45.850914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2877 22:53:45.850965 ==
2878 22:53:45.851015 Write leveling (Byte 0): 33 => 33
2879 22:53:45.851066 Write leveling (Byte 1): 29 => 29
2880 22:53:45.851116 DramcWriteLeveling(PI) end<-----
2881 22:53:45.851171
2882 22:53:45.851222 ==
2883 22:53:45.851289 Dram Type= 6, Freq= 0, CH_0, rank 1
2884 22:53:45.851382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2885 22:53:45.851433 ==
2886 22:53:45.851484 [Gating] SW mode calibration
2887 22:53:45.851534 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2888 22:53:45.851585 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2889 22:53:45.851636 0 15 0 | B1->B0 | 2525 3131 | 0 1 | (0 0) (1 1)
2890 22:53:45.851686 0 15 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2891 22:53:45.851737 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2892 22:53:45.851787 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 22:53:45.851837 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 22:53:45.852097 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 22:53:45.852178 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 22:53:45.852283 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2897 22:53:45.852387 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2898 22:53:45.852492 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2899 22:53:45.852587 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2900 22:53:45.852676 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 22:53:45.852742 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 22:53:45.852795 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 22:53:45.852846 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 22:53:45.852898 1 0 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2905 22:53:45.852949 1 1 0 | B1->B0 | 3434 4444 | 0 0 | (0 0) (0 0)
2906 22:53:45.853000 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 22:53:45.853051 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 22:53:45.853102 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 22:53:45.853152 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 22:53:45.853203 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 22:53:45.853257 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 22:53:45.853353 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2913 22:53:45.853403 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2914 22:53:45.853454 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 22:53:45.853510 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 22:53:45.853562 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 22:53:45.853613 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 22:53:45.853677 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 22:53:45.853739 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 22:53:45.853791 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 22:53:45.853842 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 22:53:45.853893 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 22:53:45.853943 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 22:53:45.853993 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 22:53:45.854044 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 22:53:45.854094 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 22:53:45.854144 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 22:53:45.854236 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2929 22:53:45.854287 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2930 22:53:45.854337 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 22:53:45.854388 Total UI for P1: 0, mck2ui 16
2932 22:53:45.854439 best dqsien dly found for B0: ( 1, 3, 30)
2933 22:53:45.854490 Total UI for P1: 0, mck2ui 16
2934 22:53:45.854541 best dqsien dly found for B1: ( 1, 4, 0)
2935 22:53:45.854591 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2936 22:53:45.854642 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2937 22:53:45.854692
2938 22:53:46.026257 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2939 22:53:46.026393 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2940 22:53:46.026458 [Gating] SW calibration Done
2941 22:53:46.026515 ==
2942 22:53:46.026572 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 22:53:46.026627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 22:53:46.026682 ==
2945 22:53:46.026735 RX Vref Scan: 0
2946 22:53:46.026789
2947 22:53:46.026841 RX Vref 0 -> 0, step: 1
2948 22:53:46.026892
2949 22:53:46.026944 RX Delay -40 -> 252, step: 8
2950 22:53:46.026995 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2951 22:53:46.027047 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2952 22:53:46.027099 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2953 22:53:46.027151 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2954 22:53:46.027202 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2955 22:53:46.027253 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2956 22:53:46.027304 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2957 22:53:46.027354 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2958 22:53:46.027404 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2959 22:53:46.027455 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2960 22:53:46.027511 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2961 22:53:46.027577 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2962 22:53:46.027629 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2963 22:53:46.027680 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2964 22:53:46.027731 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2965 22:53:46.027781 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2966 22:53:46.027832 ==
2967 22:53:46.027883 Dram Type= 6, Freq= 0, CH_0, rank 1
2968 22:53:46.027934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2969 22:53:46.027986 ==
2970 22:53:46.028037 DQS Delay:
2971 22:53:46.028087 DQS0 = 0, DQS1 = 0
2972 22:53:46.028137 DQM Delay:
2973 22:53:46.028205 DQM0 = 117, DQM1 = 108
2974 22:53:46.028257 DQ Delay:
2975 22:53:46.028308 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
2976 22:53:46.028359 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2977 22:53:46.028410 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2978 22:53:46.028461 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =119
2979 22:53:46.028512
2980 22:53:46.028569
2981 22:53:46.028650 ==
2982 22:53:46.028707 Dram Type= 6, Freq= 0, CH_0, rank 1
2983 22:53:46.028758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2984 22:53:46.028809 ==
2985 22:53:46.028897
2986 22:53:46.028948
2987 22:53:46.028998 TX Vref Scan disable
2988 22:53:46.029049 == TX Byte 0 ==
2989 22:53:46.029099 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2990 22:53:46.029151 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2991 22:53:46.029201 == TX Byte 1 ==
2992 22:53:46.029252 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2993 22:53:46.029302 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2994 22:53:46.029353 ==
2995 22:53:46.029403 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 22:53:46.029454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 22:53:46.029505 ==
2998 22:53:46.029555 TX Vref=22, minBit 10, minWin=25, winSum=415
2999 22:53:46.029606 TX Vref=24, minBit 0, minWin=26, winSum=425
3000 22:53:46.029657 TX Vref=26, minBit 1, minWin=26, winSum=429
3001 22:53:46.029921 TX Vref=28, minBit 1, minWin=26, winSum=428
3002 22:53:46.030014 TX Vref=30, minBit 1, minWin=26, winSum=429
3003 22:53:46.030120 TX Vref=32, minBit 13, minWin=25, winSum=430
3004 22:53:46.030266 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 26
3005 22:53:46.030371
3006 22:53:46.030467 Final TX Range 1 Vref 26
3007 22:53:46.030556
3008 22:53:46.030622 ==
3009 22:53:46.030674 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 22:53:46.030726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 22:53:46.030778 ==
3012 22:53:46.030830
3013 22:53:46.030880
3014 22:53:46.030930 TX Vref Scan disable
3015 22:53:46.030981 == TX Byte 0 ==
3016 22:53:46.031032 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3017 22:53:46.031083 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3018 22:53:46.031134 == TX Byte 1 ==
3019 22:53:46.031184 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3020 22:53:46.031234 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3021 22:53:46.031285
3022 22:53:46.031336 [DATLAT]
3023 22:53:46.031386 Freq=1200, CH0 RK1
3024 22:53:46.031452
3025 22:53:46.031503 DATLAT Default: 0xd
3026 22:53:46.031554 0, 0xFFFF, sum = 0
3027 22:53:46.031606 1, 0xFFFF, sum = 0
3028 22:53:46.031658 2, 0xFFFF, sum = 0
3029 22:53:46.031710 3, 0xFFFF, sum = 0
3030 22:53:46.031762 4, 0xFFFF, sum = 0
3031 22:53:46.031813 5, 0xFFFF, sum = 0
3032 22:53:46.031865 6, 0xFFFF, sum = 0
3033 22:53:46.031917 7, 0xFFFF, sum = 0
3034 22:53:46.031968 8, 0xFFFF, sum = 0
3035 22:53:46.032019 9, 0xFFFF, sum = 0
3036 22:53:46.032070 10, 0xFFFF, sum = 0
3037 22:53:46.032122 11, 0xFFFF, sum = 0
3038 22:53:46.032173 12, 0x0, sum = 1
3039 22:53:46.032225 13, 0x0, sum = 2
3040 22:53:46.032276 14, 0x0, sum = 3
3041 22:53:46.032328 15, 0x0, sum = 4
3042 22:53:46.032379 best_step = 13
3043 22:53:46.032430
3044 22:53:46.032480 ==
3045 22:53:46.032531 Dram Type= 6, Freq= 0, CH_0, rank 1
3046 22:53:46.032582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3047 22:53:46.032633 ==
3048 22:53:46.032683 RX Vref Scan: 0
3049 22:53:46.032733
3050 22:53:46.032783 RX Vref 0 -> 0, step: 1
3051 22:53:46.032834
3052 22:53:46.032884 RX Delay -21 -> 252, step: 4
3053 22:53:46.032935 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3054 22:53:46.032986 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3055 22:53:46.033038 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3056 22:53:46.033088 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3057 22:53:46.033139 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3058 22:53:46.033190 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3059 22:53:46.033241 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3060 22:53:46.033298 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3061 22:53:46.033365 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3062 22:53:46.033437 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3063 22:53:46.033488 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3064 22:53:46.033540 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3065 22:53:46.033610 iDelay=199, Bit 12, Center 116 (51 ~ 182) 132
3066 22:53:46.033679 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
3067 22:53:46.033730 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3068 22:53:46.033781 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3069 22:53:46.033832 ==
3070 22:53:46.033883 Dram Type= 6, Freq= 0, CH_0, rank 1
3071 22:53:46.033933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 22:53:46.033985 ==
3073 22:53:46.034035 DQS Delay:
3074 22:53:46.034086 DQS0 = 0, DQS1 = 0
3075 22:53:46.034137 DQM Delay:
3076 22:53:46.034213 DQM0 = 116, DQM1 = 108
3077 22:53:46.034277 DQ Delay:
3078 22:53:46.034328 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3079 22:53:46.034379 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3080 22:53:46.034429 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =102
3081 22:53:46.034480 DQ12 =116, DQ13 =114, DQ14 =120, DQ15 =116
3082 22:53:46.034545
3083 22:53:46.034598
3084 22:53:46.034649 [DQSOSCAuto] RK1, (LSB)MR18= 0x9e4, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
3085 22:53:46.034701 CH0 RK1: MR19=403, MR18=9E4
3086 22:53:46.034752 CH0_RK1: MR19=0x403, MR18=0x9E4, DQSOSC=406, MR23=63, INC=39, DEC=26
3087 22:53:46.034803 [RxdqsGatingPostProcess] freq 1200
3088 22:53:46.034854 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3089 22:53:46.034905 best DQS0 dly(2T, 0.5T) = (0, 11)
3090 22:53:46.034956 best DQS1 dly(2T, 0.5T) = (0, 12)
3091 22:53:46.035006 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3092 22:53:46.035058 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3093 22:53:46.035109 best DQS0 dly(2T, 0.5T) = (0, 11)
3094 22:53:46.035160 best DQS1 dly(2T, 0.5T) = (0, 12)
3095 22:53:46.035210 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3096 22:53:46.035261 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3097 22:53:46.035312 Pre-setting of DQS Precalculation
3098 22:53:46.035363 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3099 22:53:46.035414 ==
3100 22:53:46.035464 Dram Type= 6, Freq= 0, CH_1, rank 0
3101 22:53:46.035515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 22:53:46.035567 ==
3103 22:53:46.035618 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3104 22:53:46.035672 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3105 22:53:46.035724 [CA 0] Center 37 (7~68) winsize 62
3106 22:53:46.035775 [CA 1] Center 37 (7~68) winsize 62
3107 22:53:46.035826 [CA 2] Center 34 (4~64) winsize 61
3108 22:53:46.035876 [CA 3] Center 33 (3~64) winsize 62
3109 22:53:46.035927 [CA 4] Center 34 (5~64) winsize 60
3110 22:53:46.035978 [CA 5] Center 33 (3~64) winsize 62
3111 22:53:46.036029
3112 22:53:46.036079 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3113 22:53:46.036129
3114 22:53:46.036180 [CATrainingPosCal] consider 1 rank data
3115 22:53:46.036231 u2DelayCellTimex100 = 270/100 ps
3116 22:53:46.036282 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3117 22:53:46.036333 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3118 22:53:46.036384 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3119 22:53:46.036434 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3120 22:53:46.036485 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3121 22:53:46.036536 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3122 22:53:46.036586
3123 22:53:46.036636 CA PerBit enable=1, Macro0, CA PI delay=33
3124 22:53:46.036687
3125 22:53:46.036737 [CBTSetCACLKResult] CA Dly = 33
3126 22:53:46.036788 CS Dly: 5 (0~36)
3127 22:53:46.036839 ==
3128 22:53:46.036890 Dram Type= 6, Freq= 0, CH_1, rank 1
3129 22:53:46.036940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 22:53:46.036992 ==
3131 22:53:46.037042 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3132 22:53:46.037093 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3133 22:53:46.037145 [CA 0] Center 37 (7~68) winsize 62
3134 22:53:46.037195 [CA 1] Center 38 (8~68) winsize 61
3135 22:53:46.037453 [CA 2] Center 34 (4~65) winsize 62
3136 22:53:46.037536 [CA 3] Center 34 (4~64) winsize 61
3137 22:53:46.037597 [CA 4] Center 34 (3~65) winsize 63
3138 22:53:46.037649 [CA 5] Center 33 (3~64) winsize 62
3139 22:53:46.037700
3140 22:53:46.037751 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3141 22:53:46.037802
3142 22:53:46.037854 [CATrainingPosCal] consider 2 rank data
3143 22:53:46.037905 u2DelayCellTimex100 = 270/100 ps
3144 22:53:46.037956 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3145 22:53:46.038007 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3146 22:53:46.038089 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3147 22:53:46.038197 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3148 22:53:46.038267 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3149 22:53:46.038318 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3150 22:53:46.038369
3151 22:53:46.038421 CA PerBit enable=1, Macro0, CA PI delay=33
3152 22:53:46.038472
3153 22:53:46.038523 [CBTSetCACLKResult] CA Dly = 33
3154 22:53:46.038574 CS Dly: 7 (0~40)
3155 22:53:46.038625
3156 22:53:46.038675 ----->DramcWriteLeveling(PI) begin...
3157 22:53:46.038729 ==
3158 22:53:46.038779 Dram Type= 6, Freq= 0, CH_1, rank 0
3159 22:53:46.038831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3160 22:53:46.038882 ==
3161 22:53:46.038933 Write leveling (Byte 0): 24 => 24
3162 22:53:46.038985 Write leveling (Byte 1): 26 => 26
3163 22:53:46.039036 DramcWriteLeveling(PI) end<-----
3164 22:53:46.039087
3165 22:53:46.039137 ==
3166 22:53:46.039188 Dram Type= 6, Freq= 0, CH_1, rank 0
3167 22:53:46.039239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3168 22:53:46.039290 ==
3169 22:53:46.039341 [Gating] SW mode calibration
3170 22:53:46.039392 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3171 22:53:46.039444 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3172 22:53:46.039499 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3173 22:53:46.039564 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3174 22:53:46.039616 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3175 22:53:46.039668 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 22:53:46.039720 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 22:53:46.039771 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 22:53:46.039823 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
3179 22:53:46.039874 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3180 22:53:46.039925 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3181 22:53:46.039977 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 22:53:46.040028 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 22:53:46.040079 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 22:53:46.040130 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 22:53:46.040181 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 22:53:46.040232 1 0 24 | B1->B0 | 2525 3b3b | 0 0 | (0 0) (1 1)
3187 22:53:46.040283 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3188 22:53:46.040334 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 22:53:46.040385 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 22:53:46.040436 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 22:53:46.040488 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 22:53:46.040539 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 22:53:46.040590 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 22:53:46.040641 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3195 22:53:46.040693 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3196 22:53:46.040743 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 22:53:46.040794 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 22:53:46.040845 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 22:53:46.040896 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 22:53:46.040947 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 22:53:46.040999 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 22:53:46.041050 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 22:53:46.041101 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 22:53:46.041152 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 22:53:46.041204 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 22:53:46.041255 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 22:53:46.041306 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 22:53:46.041357 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 22:53:46.041408 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 22:53:46.041460 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3211 22:53:46.041511 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3212 22:53:46.041562 Total UI for P1: 0, mck2ui 16
3213 22:53:46.041613 best dqsien dly found for B0: ( 1, 3, 24)
3214 22:53:46.041664 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 22:53:46.041715 Total UI for P1: 0, mck2ui 16
3216 22:53:46.041767 best dqsien dly found for B1: ( 1, 3, 26)
3217 22:53:46.041818 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3218 22:53:46.041869 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3219 22:53:46.041919
3220 22:53:46.041970 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3221 22:53:46.042021 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3222 22:53:46.042072 [Gating] SW calibration Done
3223 22:53:46.042123 ==
3224 22:53:46.042182 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 22:53:46.042235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 22:53:46.042287 ==
3227 22:53:46.042338 RX Vref Scan: 0
3228 22:53:46.042388
3229 22:53:46.042451 RX Vref 0 -> 0, step: 1
3230 22:53:46.042503
3231 22:53:46.042554 RX Delay -40 -> 252, step: 8
3232 22:53:46.042606 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3233 22:53:46.042657 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3234 22:53:46.042709 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3235 22:53:46.042759 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3236 22:53:46.042811 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3237 22:53:46.042862 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3238 22:53:46.042913 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3239 22:53:46.043170 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3240 22:53:46.043234 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3241 22:53:46.043287 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3242 22:53:46.043339 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3243 22:53:46.043391 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3244 22:53:46.043443 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3245 22:53:46.043494 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3246 22:53:46.043546 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3247 22:53:46.043597 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3248 22:53:46.043648 ==
3249 22:53:46.043699 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 22:53:46.043751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 22:53:46.043802 ==
3252 22:53:46.043854 DQS Delay:
3253 22:53:46.043905 DQS0 = 0, DQS1 = 0
3254 22:53:46.043956 DQM Delay:
3255 22:53:46.044006 DQM0 = 118, DQM1 = 109
3256 22:53:46.044057 DQ Delay:
3257 22:53:46.044108 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =115
3258 22:53:46.044160 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3259 22:53:46.044211 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =95
3260 22:53:46.044262 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3261 22:53:46.044313
3262 22:53:46.044364
3263 22:53:46.044414 ==
3264 22:53:46.044465 Dram Type= 6, Freq= 0, CH_1, rank 0
3265 22:53:46.044516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3266 22:53:46.044567 ==
3267 22:53:46.044618
3268 22:53:46.044668
3269 22:53:46.044718 TX Vref Scan disable
3270 22:53:46.044770 == TX Byte 0 ==
3271 22:53:46.044837 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3272 22:53:46.044889 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3273 22:53:46.044940 == TX Byte 1 ==
3274 22:53:46.044990 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3275 22:53:46.045041 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3276 22:53:46.045092 ==
3277 22:53:46.045143 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 22:53:46.045194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 22:53:46.045245 ==
3280 22:53:46.045296 TX Vref=22, minBit 10, minWin=25, winSum=418
3281 22:53:46.045347 TX Vref=24, minBit 10, minWin=25, winSum=421
3282 22:53:46.045399 TX Vref=26, minBit 10, minWin=25, winSum=429
3283 22:53:46.045450 TX Vref=28, minBit 10, minWin=25, winSum=432
3284 22:53:46.045502 TX Vref=30, minBit 15, minWin=25, winSum=431
3285 22:53:46.045553 TX Vref=32, minBit 9, minWin=25, winSum=427
3286 22:53:46.045605 [TxChooseVref] Worse bit 10, Min win 25, Win sum 432, Final Vref 28
3287 22:53:46.045656
3288 22:53:46.045707 Final TX Range 1 Vref 28
3289 22:53:46.045758
3290 22:53:46.045808 ==
3291 22:53:46.045859 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 22:53:46.045910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 22:53:46.045961 ==
3294 22:53:46.046011
3295 22:53:46.046062
3296 22:53:46.046112 TX Vref Scan disable
3297 22:53:46.046171 == TX Byte 0 ==
3298 22:53:46.046263 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3299 22:53:46.046314 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3300 22:53:46.046364 == TX Byte 1 ==
3301 22:53:46.046415 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3302 22:53:46.046465 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3303 22:53:46.046515
3304 22:53:46.046572 [DATLAT]
3305 22:53:46.046622 Freq=1200, CH1 RK0
3306 22:53:46.046673
3307 22:53:46.046722 DATLAT Default: 0xd
3308 22:53:46.046773 0, 0xFFFF, sum = 0
3309 22:53:46.046824 1, 0xFFFF, sum = 0
3310 22:53:46.046876 2, 0xFFFF, sum = 0
3311 22:53:46.046927 3, 0xFFFF, sum = 0
3312 22:53:46.046978 4, 0xFFFF, sum = 0
3313 22:53:46.047030 5, 0xFFFF, sum = 0
3314 22:53:46.047081 6, 0xFFFF, sum = 0
3315 22:53:46.047131 7, 0xFFFF, sum = 0
3316 22:53:46.047182 8, 0xFFFF, sum = 0
3317 22:53:46.047234 9, 0xFFFF, sum = 0
3318 22:53:46.047285 10, 0xFFFF, sum = 0
3319 22:53:46.047336 11, 0xFFFF, sum = 0
3320 22:53:46.047387 12, 0x0, sum = 1
3321 22:53:46.047438 13, 0x0, sum = 2
3322 22:53:46.047489 14, 0x0, sum = 3
3323 22:53:46.047540 15, 0x0, sum = 4
3324 22:53:46.047591 best_step = 13
3325 22:53:46.047640
3326 22:53:46.047690 ==
3327 22:53:46.047763 Dram Type= 6, Freq= 0, CH_1, rank 0
3328 22:53:46.047837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3329 22:53:46.047919 ==
3330 22:53:46.048000 RX Vref Scan: 1
3331 22:53:46.048092
3332 22:53:46.048172 Set Vref Range= 32 -> 127
3333 22:53:46.048267
3334 22:53:46.048365 RX Vref 32 -> 127, step: 1
3335 22:53:46.048444
3336 22:53:46.048523 RX Delay -21 -> 252, step: 4
3337 22:53:46.048602
3338 22:53:46.048682 Set Vref, RX VrefLevel [Byte0]: 32
3339 22:53:46.048764 [Byte1]: 32
3340 22:53:46.048843
3341 22:53:46.048923 Set Vref, RX VrefLevel [Byte0]: 33
3342 22:53:46.048989 [Byte1]: 33
3343 22:53:46.049041
3344 22:53:46.049091 Set Vref, RX VrefLevel [Byte0]: 34
3345 22:53:46.049142 [Byte1]: 34
3346 22:53:46.049193
3347 22:53:46.049243 Set Vref, RX VrefLevel [Byte0]: 35
3348 22:53:46.049293 [Byte1]: 35
3349 22:53:46.049344
3350 22:53:46.049394 Set Vref, RX VrefLevel [Byte0]: 36
3351 22:53:46.049444 [Byte1]: 36
3352 22:53:46.049494
3353 22:53:46.049544 Set Vref, RX VrefLevel [Byte0]: 37
3354 22:53:46.049595 [Byte1]: 37
3355 22:53:46.049644
3356 22:53:46.049694 Set Vref, RX VrefLevel [Byte0]: 38
3357 22:53:46.049745 [Byte1]: 38
3358 22:53:46.049795
3359 22:53:46.049845 Set Vref, RX VrefLevel [Byte0]: 39
3360 22:53:46.049894 [Byte1]: 39
3361 22:53:46.049945
3362 22:53:46.049995 Set Vref, RX VrefLevel [Byte0]: 40
3363 22:53:46.050046 [Byte1]: 40
3364 22:53:46.050095
3365 22:53:46.050145 Set Vref, RX VrefLevel [Byte0]: 41
3366 22:53:46.050260 [Byte1]: 41
3367 22:53:46.050339
3368 22:53:46.050419 Set Vref, RX VrefLevel [Byte0]: 42
3369 22:53:46.050502 [Byte1]: 42
3370 22:53:46.050557
3371 22:53:46.050608 Set Vref, RX VrefLevel [Byte0]: 43
3372 22:53:46.050659 [Byte1]: 43
3373 22:53:46.050710
3374 22:53:46.050760 Set Vref, RX VrefLevel [Byte0]: 44
3375 22:53:46.050811 [Byte1]: 44
3376 22:53:46.050862
3377 22:53:46.050912 Set Vref, RX VrefLevel [Byte0]: 45
3378 22:53:46.050963 [Byte1]: 45
3379 22:53:46.051013
3380 22:53:46.051063 Set Vref, RX VrefLevel [Byte0]: 46
3381 22:53:46.051114 [Byte1]: 46
3382 22:53:46.051165
3383 22:53:46.051215 Set Vref, RX VrefLevel [Byte0]: 47
3384 22:53:46.051282 [Byte1]: 47
3385 22:53:46.051335
3386 22:53:46.051385 Set Vref, RX VrefLevel [Byte0]: 48
3387 22:53:46.051436 [Byte1]: 48
3388 22:53:46.051487
3389 22:53:46.051537 Set Vref, RX VrefLevel [Byte0]: 49
3390 22:53:46.051587 [Byte1]: 49
3391 22:53:46.051637
3392 22:53:46.051687 Set Vref, RX VrefLevel [Byte0]: 50
3393 22:53:46.051737 [Byte1]: 50
3394 22:53:46.051787
3395 22:53:46.051837 Set Vref, RX VrefLevel [Byte0]: 51
3396 22:53:46.051888 [Byte1]: 51
3397 22:53:46.051938
3398 22:53:46.051987 Set Vref, RX VrefLevel [Byte0]: 52
3399 22:53:46.052037 [Byte1]: 52
3400 22:53:46.052087
3401 22:53:46.052351 Set Vref, RX VrefLevel [Byte0]: 53
3402 22:53:46.052413 [Byte1]: 53
3403 22:53:46.052465
3404 22:53:46.052516 Set Vref, RX VrefLevel [Byte0]: 54
3405 22:53:46.052567 [Byte1]: 54
3406 22:53:46.052618
3407 22:53:46.052668 Set Vref, RX VrefLevel [Byte0]: 55
3408 22:53:46.052718 [Byte1]: 55
3409 22:53:46.052769
3410 22:53:46.052819 Set Vref, RX VrefLevel [Byte0]: 56
3411 22:53:46.052869 [Byte1]: 56
3412 22:53:46.052920
3413 22:53:46.052970 Set Vref, RX VrefLevel [Byte0]: 57
3414 22:53:46.053021 [Byte1]: 57
3415 22:53:46.053071
3416 22:53:46.053120 Set Vref, RX VrefLevel [Byte0]: 58
3417 22:53:46.053170 [Byte1]: 58
3418 22:53:46.053220
3419 22:53:46.053270 Set Vref, RX VrefLevel [Byte0]: 59
3420 22:53:46.053319 [Byte1]: 59
3421 22:53:46.053369
3422 22:53:46.053419 Set Vref, RX VrefLevel [Byte0]: 60
3423 22:53:46.053471 [Byte1]: 60
3424 22:53:46.053521
3425 22:53:46.053571 Set Vref, RX VrefLevel [Byte0]: 61
3426 22:53:46.053621 [Byte1]: 61
3427 22:53:46.053671
3428 22:53:46.053720 Set Vref, RX VrefLevel [Byte0]: 62
3429 22:53:46.053770 [Byte1]: 62
3430 22:53:46.053820
3431 22:53:46.053870 Set Vref, RX VrefLevel [Byte0]: 63
3432 22:53:46.053920 [Byte1]: 63
3433 22:53:46.053970
3434 22:53:46.054019 Set Vref, RX VrefLevel [Byte0]: 64
3435 22:53:46.054070 [Byte1]: 64
3436 22:53:46.054119
3437 22:53:46.054202 Set Vref, RX VrefLevel [Byte0]: 65
3438 22:53:46.054268 [Byte1]: 65
3439 22:53:46.054318
3440 22:53:46.054368 Set Vref, RX VrefLevel [Byte0]: 66
3441 22:53:46.054419 [Byte1]: 66
3442 22:53:46.054469
3443 22:53:46.054519 Set Vref, RX VrefLevel [Byte0]: 67
3444 22:53:46.054570 [Byte1]: 67
3445 22:53:46.054620
3446 22:53:46.054669 Final RX Vref Byte 0 = 51 to rank0
3447 22:53:46.054720 Final RX Vref Byte 1 = 58 to rank0
3448 22:53:46.054770 Final RX Vref Byte 0 = 51 to rank1
3449 22:53:46.054835 Final RX Vref Byte 1 = 58 to rank1==
3450 22:53:46.054888 Dram Type= 6, Freq= 0, CH_1, rank 0
3451 22:53:46.054938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3452 22:53:46.054989 ==
3453 22:53:46.055039 DQS Delay:
3454 22:53:46.055090 DQS0 = 0, DQS1 = 0
3455 22:53:46.055139 DQM Delay:
3456 22:53:46.055189 DQM0 = 116, DQM1 = 111
3457 22:53:46.055240 DQ Delay:
3458 22:53:46.055290 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =114
3459 22:53:46.055340 DQ4 =114, DQ5 =128, DQ6 =124, DQ7 =112
3460 22:53:46.055390 DQ8 =100, DQ9 =100, DQ10 =114, DQ11 =100
3461 22:53:46.055440 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =120
3462 22:53:46.055491
3463 22:53:46.055541
3464 22:53:46.055591 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3465 22:53:46.055644 CH1 RK0: MR19=403, MR18=4F8
3466 22:53:46.055695 CH1_RK0: MR19=0x403, MR18=0x4F8, DQSOSC=408, MR23=63, INC=39, DEC=26
3467 22:53:46.055746
3468 22:53:46.055797 ----->DramcWriteLeveling(PI) begin...
3469 22:53:46.055848 ==
3470 22:53:46.055898 Dram Type= 6, Freq= 0, CH_1, rank 1
3471 22:53:46.055949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3472 22:53:46.056000 ==
3473 22:53:46.056050 Write leveling (Byte 0): 26 => 26
3474 22:53:46.056101 Write leveling (Byte 1): 28 => 28
3475 22:53:46.056151 DramcWriteLeveling(PI) end<-----
3476 22:53:46.056201
3477 22:53:46.056251 ==
3478 22:53:46.056301 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 22:53:46.056351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 22:53:46.056402 ==
3481 22:53:46.056453 [Gating] SW mode calibration
3482 22:53:46.056503 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3483 22:53:46.056554 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3484 22:53:46.056605 0 15 0 | B1->B0 | 3333 3131 | 1 1 | (1 1) (1 1)
3485 22:53:46.056656 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 22:53:46.056707 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 22:53:46.056757 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 22:53:46.056807 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 22:53:46.056858 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3490 22:53:46.056908 0 15 24 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 1)
3491 22:53:46.056959 0 15 28 | B1->B0 | 2424 2626 | 0 0 | (1 0) (0 0)
3492 22:53:46.057009 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 22:53:46.057060 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 22:53:46.057110 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 22:53:46.057160 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 22:53:46.057211 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 22:53:46.057261 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 22:53:46.057312 1 0 24 | B1->B0 | 3535 2828 | 0 0 | (1 1) (0 0)
3499 22:53:46.057362 1 0 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
3500 22:53:46.057412 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 22:53:46.057463 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 22:53:46.057514 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 22:53:46.057564 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 22:53:46.057615 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 22:53:46.057665 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 22:53:46.057716 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3507 22:53:46.057766 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3508 22:53:46.057830 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 22:53:46.057883 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 22:53:46.057934 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 22:53:46.057984 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 22:53:46.058035 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 22:53:46.058086 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 22:53:46.058137 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 22:53:46.058198 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 22:53:46.058249 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 22:53:46.058301 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 22:53:46.058359 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 22:53:46.058617 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 22:53:46.058676 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 22:53:46.058728 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 22:53:46.058780 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3523 22:53:46.058830 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3524 22:53:46.058881 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 22:53:46.058933 Total UI for P1: 0, mck2ui 16
3526 22:53:46.058984 best dqsien dly found for B0: ( 1, 3, 28)
3527 22:53:46.059035 Total UI for P1: 0, mck2ui 16
3528 22:53:46.059086 best dqsien dly found for B1: ( 1, 3, 26)
3529 22:53:46.059137 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3530 22:53:46.059188 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3531 22:53:46.059238
3532 22:53:46.059288 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3533 22:53:46.059339 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3534 22:53:46.059389 [Gating] SW calibration Done
3535 22:53:46.059438 ==
3536 22:53:46.059490 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 22:53:46.059540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 22:53:46.059592 ==
3539 22:53:46.059642 RX Vref Scan: 0
3540 22:53:46.059692
3541 22:53:46.059742 RX Vref 0 -> 0, step: 1
3542 22:53:46.059792
3543 22:53:46.059842 RX Delay -40 -> 252, step: 8
3544 22:53:46.059892 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3545 22:53:46.059943 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3546 22:53:46.059993 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3547 22:53:46.060044 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3548 22:53:46.060094 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3549 22:53:46.060144 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3550 22:53:46.060195 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3551 22:53:46.060245 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3552 22:53:46.060296 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3553 22:53:46.060346 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3554 22:53:46.060396 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3555 22:53:46.060447 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3556 22:53:46.060497 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3557 22:53:46.060547 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3558 22:53:46.060597 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3559 22:53:46.060648 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3560 22:53:46.060698 ==
3561 22:53:46.060748 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 22:53:46.060798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 22:53:46.060848 ==
3564 22:53:46.060899 DQS Delay:
3565 22:53:46.060963 DQS0 = 0, DQS1 = 0
3566 22:53:46.061015 DQM Delay:
3567 22:53:46.061066 DQM0 = 116, DQM1 = 110
3568 22:53:46.061116 DQ Delay:
3569 22:53:46.061167 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3570 22:53:46.061217 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3571 22:53:46.061267 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3572 22:53:46.061318 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3573 22:53:46.061368
3574 22:53:46.061418
3575 22:53:46.061467 ==
3576 22:53:46.061519 Dram Type= 6, Freq= 0, CH_1, rank 1
3577 22:53:46.061569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3578 22:53:46.061620 ==
3579 22:53:46.061670
3580 22:53:46.061720
3581 22:53:46.061770 TX Vref Scan disable
3582 22:53:46.061820 == TX Byte 0 ==
3583 22:53:46.061871 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3584 22:53:46.061952 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3585 22:53:46.062003 == TX Byte 1 ==
3586 22:53:46.062053 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3587 22:53:46.062104 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3588 22:53:46.062154 ==
3589 22:53:46.062254 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 22:53:46.062347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 22:53:46.062427 ==
3592 22:53:46.062508 TX Vref=22, minBit 8, minWin=25, winSum=420
3593 22:53:46.062588 TX Vref=24, minBit 8, minWin=25, winSum=427
3594 22:53:46.062669 TX Vref=26, minBit 8, minWin=26, winSum=431
3595 22:53:46.062749 TX Vref=28, minBit 8, minWin=26, winSum=429
3596 22:53:46.062829 TX Vref=30, minBit 9, minWin=25, winSum=429
3597 22:53:46.062909 TX Vref=32, minBit 9, minWin=25, winSum=428
3598 22:53:46.062990 [TxChooseVref] Worse bit 8, Min win 26, Win sum 431, Final Vref 26
3599 22:53:46.063069
3600 22:53:46.063149 Final TX Range 1 Vref 26
3601 22:53:46.063228
3602 22:53:46.063307 ==
3603 22:53:46.063386 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 22:53:46.063466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 22:53:46.063546 ==
3606 22:53:46.063625
3607 22:53:46.063707
3608 22:53:46.063798 TX Vref Scan disable
3609 22:53:46.063878 == TX Byte 0 ==
3610 22:53:46.063957 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3611 22:53:46.064038 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3612 22:53:46.064117 == TX Byte 1 ==
3613 22:53:46.064210 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3614 22:53:46.064294 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3615 22:53:46.064374
3616 22:53:46.064453 [DATLAT]
3617 22:53:46.064532 Freq=1200, CH1 RK1
3618 22:53:46.064612
3619 22:53:46.064691 DATLAT Default: 0xd
3620 22:53:46.064771 0, 0xFFFF, sum = 0
3621 22:53:46.064852 1, 0xFFFF, sum = 0
3622 22:53:46.064934 2, 0xFFFF, sum = 0
3623 22:53:46.065015 3, 0xFFFF, sum = 0
3624 22:53:46.065096 4, 0xFFFF, sum = 0
3625 22:53:46.065177 5, 0xFFFF, sum = 0
3626 22:53:46.065259 6, 0xFFFF, sum = 0
3627 22:53:46.065340 7, 0xFFFF, sum = 0
3628 22:53:46.065421 8, 0xFFFF, sum = 0
3629 22:53:46.065502 9, 0xFFFF, sum = 0
3630 22:53:46.065583 10, 0xFFFF, sum = 0
3631 22:53:46.065665 11, 0xFFFF, sum = 0
3632 22:53:46.065750 12, 0x0, sum = 1
3633 22:53:46.065838 13, 0x0, sum = 2
3634 22:53:46.065920 14, 0x0, sum = 3
3635 22:53:46.066001 15, 0x0, sum = 4
3636 22:53:46.066082 best_step = 13
3637 22:53:46.066166
3638 22:53:46.066254 ==
3639 22:53:46.066305 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 22:53:46.066356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 22:53:46.066407 ==
3642 22:53:46.066458 RX Vref Scan: 0
3643 22:53:46.066508
3644 22:53:46.066559 RX Vref 0 -> 0, step: 1
3645 22:53:46.066609
3646 22:53:46.066659 RX Delay -21 -> 252, step: 4
3647 22:53:46.066710 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3648 22:53:46.066761 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3649 22:53:46.066812 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3650 22:53:46.066862 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3651 22:53:46.066913 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3652 22:53:46.066964 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3653 22:53:46.067014 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3654 22:53:46.067065 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3655 22:53:46.067115 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3656 22:53:46.067165 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3657 22:53:46.067440 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3658 22:53:46.067503 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3659 22:53:46.067561 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3660 22:53:46.067613 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3661 22:53:46.067664 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3662 22:53:46.067715 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3663 22:53:46.067783 ==
3664 22:53:46.067885 Dram Type= 6, Freq= 0, CH_1, rank 1
3665 22:53:46.067937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3666 22:53:46.067988 ==
3667 22:53:46.068039 DQS Delay:
3668 22:53:46.068090 DQS0 = 0, DQS1 = 0
3669 22:53:46.068141 DQM Delay:
3670 22:53:46.068190 DQM0 = 117, DQM1 = 111
3671 22:53:46.068241 DQ Delay:
3672 22:53:46.068292 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3673 22:53:46.068342 DQ4 =116, DQ5 =128, DQ6 =130, DQ7 =116
3674 22:53:46.068392 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =100
3675 22:53:46.068443 DQ12 =120, DQ13 =118, DQ14 =120, DQ15 =120
3676 22:53:46.068494
3677 22:53:46.068544
3678 22:53:46.068594 [DQSOSCAuto] RK1, (LSB)MR18= 0xf5ef, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 414 ps
3679 22:53:46.068645 CH1 RK1: MR19=303, MR18=F5EF
3680 22:53:46.068696 CH1_RK1: MR19=0x303, MR18=0xF5EF, DQSOSC=414, MR23=63, INC=38, DEC=25
3681 22:53:46.068747 [RxdqsGatingPostProcess] freq 1200
3682 22:53:46.068798 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3683 22:53:46.068849 best DQS0 dly(2T, 0.5T) = (0, 11)
3684 22:53:46.068900 best DQS1 dly(2T, 0.5T) = (0, 11)
3685 22:53:46.068950 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3686 22:53:46.069001 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3687 22:53:46.069051 best DQS0 dly(2T, 0.5T) = (0, 11)
3688 22:53:46.069102 best DQS1 dly(2T, 0.5T) = (0, 11)
3689 22:53:46.069152 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3690 22:53:46.069203 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3691 22:53:46.069252 Pre-setting of DQS Precalculation
3692 22:53:46.069303 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3693 22:53:46.069354 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3694 22:53:46.069405 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3695 22:53:46.069456
3696 22:53:46.069506
3697 22:53:46.069557 [Calibration Summary] 2400 Mbps
3698 22:53:46.069608 CH 0, Rank 0
3699 22:53:46.069659 SW Impedance : PASS
3700 22:53:46.069709 DUTY Scan : NO K
3701 22:53:46.069773 ZQ Calibration : PASS
3702 22:53:46.069825 Jitter Meter : NO K
3703 22:53:46.069876 CBT Training : PASS
3704 22:53:46.069925 Write leveling : PASS
3705 22:53:46.069976 RX DQS gating : PASS
3706 22:53:46.070026 RX DQ/DQS(RDDQC) : PASS
3707 22:53:46.070077 TX DQ/DQS : PASS
3708 22:53:46.070128 RX DATLAT : PASS
3709 22:53:46.070207 RX DQ/DQS(Engine): PASS
3710 22:53:46.070273 TX OE : NO K
3711 22:53:46.070323 All Pass.
3712 22:53:46.070374
3713 22:53:46.070424 CH 0, Rank 1
3714 22:53:46.070475 SW Impedance : PASS
3715 22:53:46.070526 DUTY Scan : NO K
3716 22:53:46.070576 ZQ Calibration : PASS
3717 22:53:46.070627 Jitter Meter : NO K
3718 22:53:46.070676 CBT Training : PASS
3719 22:53:46.070727 Write leveling : PASS
3720 22:53:46.070790 RX DQS gating : PASS
3721 22:53:46.070842 RX DQ/DQS(RDDQC) : PASS
3722 22:53:46.070895 TX DQ/DQS : PASS
3723 22:53:46.070947 RX DATLAT : PASS
3724 22:53:46.070998 RX DQ/DQS(Engine): PASS
3725 22:53:46.071049 TX OE : NO K
3726 22:53:46.071099 All Pass.
3727 22:53:46.071149
3728 22:53:46.071200 CH 1, Rank 0
3729 22:53:46.071250 SW Impedance : PASS
3730 22:53:46.071301 DUTY Scan : NO K
3731 22:53:46.071351 ZQ Calibration : PASS
3732 22:53:46.071401 Jitter Meter : NO K
3733 22:53:46.071451 CBT Training : PASS
3734 22:53:46.071502 Write leveling : PASS
3735 22:53:46.071552 RX DQS gating : PASS
3736 22:53:46.071602 RX DQ/DQS(RDDQC) : PASS
3737 22:53:46.071652 TX DQ/DQS : PASS
3738 22:53:46.071703 RX DATLAT : PASS
3739 22:53:46.071758 RX DQ/DQS(Engine): PASS
3740 22:53:46.071819 TX OE : NO K
3741 22:53:46.071871 All Pass.
3742 22:53:46.071922
3743 22:53:46.071972 CH 1, Rank 1
3744 22:53:46.072024 SW Impedance : PASS
3745 22:53:46.072109 DUTY Scan : NO K
3746 22:53:46.072210 ZQ Calibration : PASS
3747 22:53:46.072314 Jitter Meter : NO K
3748 22:53:46.072393 CBT Training : PASS
3749 22:53:46.072446 Write leveling : PASS
3750 22:53:46.072497 RX DQS gating : PASS
3751 22:53:46.072549 RX DQ/DQS(RDDQC) : PASS
3752 22:53:46.072600 TX DQ/DQS : PASS
3753 22:53:46.072650 RX DATLAT : PASS
3754 22:53:46.072700 RX DQ/DQS(Engine): PASS
3755 22:53:46.072750 TX OE : NO K
3756 22:53:46.072802 All Pass.
3757 22:53:46.072853
3758 22:53:46.072903 DramC Write-DBI off
3759 22:53:46.072953 PER_BANK_REFRESH: Hybrid Mode
3760 22:53:46.073004 TX_TRACKING: ON
3761 22:53:46.073055 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3762 22:53:46.073107 [FAST_K] Save calibration result to emmc
3763 22:53:46.073157 dramc_set_vcore_voltage set vcore to 650000
3764 22:53:46.073207 Read voltage for 600, 5
3765 22:53:46.073258 Vio18 = 0
3766 22:53:46.073308 Vcore = 650000
3767 22:53:46.073358 Vdram = 0
3768 22:53:46.073408 Vddq = 0
3769 22:53:46.073458 Vmddr = 0
3770 22:53:46.073508 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3771 22:53:46.073560 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3772 22:53:46.073610 MEM_TYPE=3, freq_sel=19
3773 22:53:46.073660 sv_algorithm_assistance_LP4_1600
3774 22:53:46.073711 ============ PULL DRAM RESETB DOWN ============
3775 22:53:46.073775 ========== PULL DRAM RESETB DOWN end =========
3776 22:53:46.073863 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3777 22:53:46.073957 ===================================
3778 22:53:46.074068 LPDDR4 DRAM CONFIGURATION
3779 22:53:46.074154 ===================================
3780 22:53:46.074237 EX_ROW_EN[0] = 0x0
3781 22:53:46.074289 EX_ROW_EN[1] = 0x0
3782 22:53:46.074341 LP4Y_EN = 0x0
3783 22:53:46.074392 WORK_FSP = 0x0
3784 22:53:46.074442 WL = 0x2
3785 22:53:46.074493 RL = 0x2
3786 22:53:46.074543 BL = 0x2
3787 22:53:46.074593 RPST = 0x0
3788 22:53:46.074643 RD_PRE = 0x0
3789 22:53:46.074693 WR_PRE = 0x1
3790 22:53:46.074744 WR_PST = 0x0
3791 22:53:46.074794 DBI_WR = 0x0
3792 22:53:46.074844 DBI_RD = 0x0
3793 22:53:46.074894 OTF = 0x1
3794 22:53:46.074945 ===================================
3795 22:53:46.074996 ===================================
3796 22:53:46.075046 ANA top config
3797 22:53:46.075097 ===================================
3798 22:53:46.075147 DLL_ASYNC_EN = 0
3799 22:53:46.075198 ALL_SLAVE_EN = 1
3800 22:53:46.075255 NEW_RANK_MODE = 1
3801 22:53:46.075520 DLL_IDLE_MODE = 1
3802 22:53:46.075578 LP45_APHY_COMB_EN = 1
3803 22:53:46.075629 TX_ODT_DIS = 1
3804 22:53:46.075684 NEW_8X_MODE = 1
3805 22:53:46.075741 ===================================
3806 22:53:46.075826 ===================================
3807 22:53:46.075908 data_rate = 1200
3808 22:53:46.075972 CKR = 1
3809 22:53:46.076023 DQ_P2S_RATIO = 8
3810 22:53:46.076073 ===================================
3811 22:53:46.076124 CA_P2S_RATIO = 8
3812 22:53:46.076173 DQ_CA_OPEN = 0
3813 22:53:46.076224 DQ_SEMI_OPEN = 0
3814 22:53:46.076275 CA_SEMI_OPEN = 0
3815 22:53:46.076325 CA_FULL_RATE = 0
3816 22:53:46.076375 DQ_CKDIV4_EN = 1
3817 22:53:46.076426 CA_CKDIV4_EN = 1
3818 22:53:46.076476 CA_PREDIV_EN = 0
3819 22:53:46.076526 PH8_DLY = 0
3820 22:53:46.078006 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3821 22:53:46.080939 DQ_AAMCK_DIV = 4
3822 22:53:46.081023 CA_AAMCK_DIV = 4
3823 22:53:46.084261 CA_ADMCK_DIV = 4
3824 22:53:46.087389 DQ_TRACK_CA_EN = 0
3825 22:53:46.090926 CA_PICK = 600
3826 22:53:46.094103 CA_MCKIO = 600
3827 22:53:46.097303 MCKIO_SEMI = 0
3828 22:53:46.100587 PLL_FREQ = 2288
3829 22:53:46.104024 DQ_UI_PI_RATIO = 32
3830 22:53:46.104123 CA_UI_PI_RATIO = 0
3831 22:53:46.107278 ===================================
3832 22:53:46.110595 ===================================
3833 22:53:46.113958 memory_type:LPDDR4
3834 22:53:46.117001 GP_NUM : 10
3835 22:53:46.117095 SRAM_EN : 1
3836 22:53:46.120087 MD32_EN : 0
3837 22:53:46.123636 ===================================
3838 22:53:46.126982 [ANA_INIT] >>>>>>>>>>>>>>
3839 22:53:46.130110 <<<<<< [CONFIGURE PHASE]: ANA_TX
3840 22:53:46.133148 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3841 22:53:46.136694 ===================================
3842 22:53:46.140152 data_rate = 1200,PCW = 0X5800
3843 22:53:46.143000 ===================================
3844 22:53:46.147026 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3845 22:53:46.150123 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3846 22:53:46.157133 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3847 22:53:46.159716 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3848 22:53:46.162794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3849 22:53:46.166305 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3850 22:53:46.169733 [ANA_INIT] flow start
3851 22:53:46.173077 [ANA_INIT] PLL >>>>>>>>
3852 22:53:46.173183 [ANA_INIT] PLL <<<<<<<<
3853 22:53:46.176082 [ANA_INIT] MIDPI >>>>>>>>
3854 22:53:46.179489 [ANA_INIT] MIDPI <<<<<<<<
3855 22:53:46.183275 [ANA_INIT] DLL >>>>>>>>
3856 22:53:46.183370 [ANA_INIT] flow end
3857 22:53:46.186782 ============ LP4 DIFF to SE enter ============
3858 22:53:46.192461 ============ LP4 DIFF to SE exit ============
3859 22:53:46.192575 [ANA_INIT] <<<<<<<<<<<<<
3860 22:53:46.195841 [Flow] Enable top DCM control >>>>>
3861 22:53:46.198968 [Flow] Enable top DCM control <<<<<
3862 22:53:46.202500 Enable DLL master slave shuffle
3863 22:53:46.209008 ==============================================================
3864 22:53:46.209126 Gating Mode config
3865 22:53:46.215528 ==============================================================
3866 22:53:46.218535 Config description:
3867 22:53:46.228714 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3868 22:53:46.235812 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3869 22:53:46.238148 SELPH_MODE 0: By rank 1: By Phase
3870 22:53:46.245158 ==============================================================
3871 22:53:46.248431 GAT_TRACK_EN = 1
3872 22:53:46.252000 RX_GATING_MODE = 2
3873 22:53:46.255518 RX_GATING_TRACK_MODE = 2
3874 22:53:46.255606 SELPH_MODE = 1
3875 22:53:46.258355 PICG_EARLY_EN = 1
3876 22:53:46.261688 VALID_LAT_VALUE = 1
3877 22:53:46.268190 ==============================================================
3878 22:53:46.271804 Enter into Gating configuration >>>>
3879 22:53:46.274833 Exit from Gating configuration <<<<
3880 22:53:46.278201 Enter into DVFS_PRE_config >>>>>
3881 22:53:46.288063 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3882 22:53:46.291548 Exit from DVFS_PRE_config <<<<<
3883 22:53:46.294629 Enter into PICG configuration >>>>
3884 22:53:46.298314 Exit from PICG configuration <<<<
3885 22:53:46.301115 [RX_INPUT] configuration >>>>>
3886 22:53:46.304653 [RX_INPUT] configuration <<<<<
3887 22:53:46.307691 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3888 22:53:46.314570 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3889 22:53:46.321410 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3890 22:53:46.327749 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3891 22:53:46.334396 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3892 22:53:46.337837 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3893 22:53:46.344330 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3894 22:53:46.347710 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3895 22:53:46.350612 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3896 22:53:46.354135 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3897 22:53:46.360519 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3898 22:53:46.364274 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3899 22:53:46.367117 ===================================
3900 22:53:46.370562 LPDDR4 DRAM CONFIGURATION
3901 22:53:46.374151 ===================================
3902 22:53:46.374302 EX_ROW_EN[0] = 0x0
3903 22:53:46.377215 EX_ROW_EN[1] = 0x0
3904 22:53:46.377297 LP4Y_EN = 0x0
3905 22:53:46.380843 WORK_FSP = 0x0
3906 22:53:46.383615 WL = 0x2
3907 22:53:46.383704 RL = 0x2
3908 22:53:46.386884 BL = 0x2
3909 22:53:46.386974 RPST = 0x0
3910 22:53:46.390144 RD_PRE = 0x0
3911 22:53:46.390274 WR_PRE = 0x1
3912 22:53:46.393704 WR_PST = 0x0
3913 22:53:46.393793 DBI_WR = 0x0
3914 22:53:46.396751 DBI_RD = 0x0
3915 22:53:46.396840 OTF = 0x1
3916 22:53:46.400650 ===================================
3917 22:53:46.403627 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3918 22:53:46.409848 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3919 22:53:46.413408 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3920 22:53:46.416491 ===================================
3921 22:53:46.419900 LPDDR4 DRAM CONFIGURATION
3922 22:53:46.423115 ===================================
3923 22:53:46.423211 EX_ROW_EN[0] = 0x10
3924 22:53:46.426422 EX_ROW_EN[1] = 0x0
3925 22:53:46.429588 LP4Y_EN = 0x0
3926 22:53:46.429683 WORK_FSP = 0x0
3927 22:53:46.432975 WL = 0x2
3928 22:53:46.433064 RL = 0x2
3929 22:53:46.436408 BL = 0x2
3930 22:53:46.436498 RPST = 0x0
3931 22:53:46.439613 RD_PRE = 0x0
3932 22:53:46.439715 WR_PRE = 0x1
3933 22:53:46.442853 WR_PST = 0x0
3934 22:53:46.442942 DBI_WR = 0x0
3935 22:53:46.446078 DBI_RD = 0x0
3936 22:53:46.446192 OTF = 0x1
3937 22:53:46.449513 ===================================
3938 22:53:46.455982 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3939 22:53:46.460418 nWR fixed to 30
3940 22:53:46.463789 [ModeRegInit_LP4] CH0 RK0
3941 22:53:46.463890 [ModeRegInit_LP4] CH0 RK1
3942 22:53:46.467048 [ModeRegInit_LP4] CH1 RK0
3943 22:53:46.470436 [ModeRegInit_LP4] CH1 RK1
3944 22:53:46.470522 match AC timing 17
3945 22:53:46.477269 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3946 22:53:46.480301 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3947 22:53:46.483704 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3948 22:53:46.490424 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3949 22:53:46.493541 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3950 22:53:46.493649 ==
3951 22:53:46.497094 Dram Type= 6, Freq= 0, CH_0, rank 0
3952 22:53:46.500469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3953 22:53:46.500591 ==
3954 22:53:46.506531 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3955 22:53:46.513334 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3956 22:53:46.516231 [CA 0] Center 36 (6~66) winsize 61
3957 22:53:46.519736 [CA 1] Center 36 (6~66) winsize 61
3958 22:53:46.522887 [CA 2] Center 34 (4~65) winsize 62
3959 22:53:46.526437 [CA 3] Center 34 (4~65) winsize 62
3960 22:53:46.529548 [CA 4] Center 33 (3~64) winsize 62
3961 22:53:46.532821 [CA 5] Center 33 (3~64) winsize 62
3962 22:53:46.532928
3963 22:53:46.535914 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3964 22:53:46.536008
3965 22:53:46.539429 [CATrainingPosCal] consider 1 rank data
3966 22:53:46.542782 u2DelayCellTimex100 = 270/100 ps
3967 22:53:46.545787 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3968 22:53:46.549712 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3969 22:53:46.556174 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3970 22:53:46.559106 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3971 22:53:46.562419 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3972 22:53:46.565566 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3973 22:53:46.565664
3974 22:53:46.569125 CA PerBit enable=1, Macro0, CA PI delay=33
3975 22:53:46.569214
3976 22:53:46.572362 [CBTSetCACLKResult] CA Dly = 33
3977 22:53:46.572454 CS Dly: 5 (0~36)
3978 22:53:46.576014 ==
3979 22:53:46.576179 Dram Type= 6, Freq= 0, CH_0, rank 1
3980 22:53:46.581916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 22:53:46.582036 ==
3982 22:53:46.585732 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3983 22:53:46.592320 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3984 22:53:46.595934 [CA 0] Center 36 (6~66) winsize 61
3985 22:53:46.599501 [CA 1] Center 36 (6~66) winsize 61
3986 22:53:46.602291 [CA 2] Center 34 (3~65) winsize 63
3987 22:53:46.605996 [CA 3] Center 34 (4~64) winsize 61
3988 22:53:46.608904 [CA 4] Center 33 (3~64) winsize 62
3989 22:53:46.612291 [CA 5] Center 33 (2~64) winsize 63
3990 22:53:46.612401
3991 22:53:46.615738 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3992 22:53:46.615834
3993 22:53:46.621776 [CATrainingPosCal] consider 2 rank data
3994 22:53:46.621889 u2DelayCellTimex100 = 270/100 ps
3995 22:53:46.628730 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3996 22:53:46.631699 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3997 22:53:46.635319 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3998 22:53:46.638803 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3999 22:53:46.641964 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4000 22:53:46.644964 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4001 22:53:46.645073
4002 22:53:46.648613 CA PerBit enable=1, Macro0, CA PI delay=33
4003 22:53:46.648709
4004 22:53:46.651722 [CBTSetCACLKResult] CA Dly = 33
4005 22:53:46.655308 CS Dly: 5 (0~36)
4006 22:53:46.655408
4007 22:53:46.658435 ----->DramcWriteLeveling(PI) begin...
4008 22:53:46.658523 ==
4009 22:53:46.661702 Dram Type= 6, Freq= 0, CH_0, rank 0
4010 22:53:46.665319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4011 22:53:46.665427 ==
4012 22:53:46.668061 Write leveling (Byte 0): 33 => 33
4013 22:53:46.671279 Write leveling (Byte 1): 32 => 32
4014 22:53:46.674544 DramcWriteLeveling(PI) end<-----
4015 22:53:46.674666
4016 22:53:46.674733 ==
4017 22:53:46.678206 Dram Type= 6, Freq= 0, CH_0, rank 0
4018 22:53:46.681338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 22:53:46.681440 ==
4020 22:53:46.684292 [Gating] SW mode calibration
4021 22:53:46.690789 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4022 22:53:46.697744 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4023 22:53:46.700844 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4024 22:53:46.707587 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4025 22:53:46.710927 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4026 22:53:46.714117 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4027 22:53:46.720711 0 9 16 | B1->B0 | 2f2f 2727 | 0 0 | (0 1) (0 0)
4028 22:53:46.724619 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 22:53:46.727366 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 22:53:46.734178 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 22:53:46.737238 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 22:53:46.740530 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 22:53:46.747123 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 22:53:46.750638 0 10 12 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
4035 22:53:46.753729 0 10 16 | B1->B0 | 3030 4343 | 1 0 | (0 0) (0 0)
4036 22:53:46.760166 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 22:53:46.763938 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 22:53:46.767031 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 22:53:46.773518 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 22:53:46.776620 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 22:53:46.779872 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 22:53:46.786381 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4043 22:53:46.790097 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 22:53:46.793180 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 22:53:46.800374 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 22:53:46.803413 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 22:53:46.806473 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 22:53:46.812842 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 22:53:46.816323 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 22:53:46.819583 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 22:53:46.825892 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 22:53:46.829237 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 22:53:46.832843 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 22:53:46.839625 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 22:53:46.842730 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 22:53:46.846239 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 22:53:46.852525 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4058 22:53:46.855916 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4059 22:53:46.859152 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4060 22:53:46.865773 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 22:53:46.865899 Total UI for P1: 0, mck2ui 16
4062 22:53:46.869057 best dqsien dly found for B0: ( 0, 13, 16)
4063 22:53:46.872787 Total UI for P1: 0, mck2ui 16
4064 22:53:46.875829 best dqsien dly found for B1: ( 0, 13, 18)
4065 22:53:46.882724 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4066 22:53:46.885475 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4067 22:53:46.885578
4068 22:53:46.888662 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4069 22:53:46.892099 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4070 22:53:46.895367 [Gating] SW calibration Done
4071 22:53:46.895464 ==
4072 22:53:46.898680 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 22:53:46.902186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 22:53:46.902302 ==
4075 22:53:46.905919 RX Vref Scan: 0
4076 22:53:46.906021
4077 22:53:46.906086 RX Vref 0 -> 0, step: 1
4078 22:53:46.906145
4079 22:53:46.908782 RX Delay -230 -> 252, step: 16
4080 22:53:46.915015 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4081 22:53:46.918514 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4082 22:53:46.921915 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4083 22:53:46.925107 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4084 22:53:46.928234 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4085 22:53:46.934760 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4086 22:53:46.938130 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4087 22:53:46.941613 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4088 22:53:46.945293 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4089 22:53:46.951392 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4090 22:53:46.954817 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4091 22:53:46.957633 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4092 22:53:46.962085 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4093 22:53:46.968222 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4094 22:53:46.971019 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4095 22:53:46.974559 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4096 22:53:46.974675 ==
4097 22:53:46.977643 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 22:53:46.981046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 22:53:46.984169 ==
4100 22:53:46.984264 DQS Delay:
4101 22:53:46.984329 DQS0 = 0, DQS1 = 0
4102 22:53:46.987665 DQM Delay:
4103 22:53:46.987761 DQM0 = 42, DQM1 = 30
4104 22:53:46.991047 DQ Delay:
4105 22:53:46.994589 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4106 22:53:46.994687 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4107 22:53:46.997294 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4108 22:53:47.003942 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4109 22:53:47.004058
4110 22:53:47.004124
4111 22:53:47.004182 ==
4112 22:53:47.007450 Dram Type= 6, Freq= 0, CH_0, rank 0
4113 22:53:47.010695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4114 22:53:47.010792 ==
4115 22:53:47.010857
4116 22:53:47.010916
4117 22:53:47.013752 TX Vref Scan disable
4118 22:53:47.013864 == TX Byte 0 ==
4119 22:53:47.020782 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4120 22:53:47.023973 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4121 22:53:47.024080 == TX Byte 1 ==
4122 22:53:47.030501 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4123 22:53:47.033652 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4124 22:53:47.033792 ==
4125 22:53:47.036817 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 22:53:47.040550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 22:53:47.040659 ==
4128 22:53:47.040726
4129 22:53:47.043687
4130 22:53:47.043778 TX Vref Scan disable
4131 22:53:47.047342 == TX Byte 0 ==
4132 22:53:47.050203 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4133 22:53:47.057189 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4134 22:53:47.057338 == TX Byte 1 ==
4135 22:53:47.060435 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4136 22:53:47.066747 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4137 22:53:47.066883
4138 22:53:47.066949 [DATLAT]
4139 22:53:47.067010 Freq=600, CH0 RK0
4140 22:53:47.067068
4141 22:53:47.070100 DATLAT Default: 0x9
4142 22:53:47.073161 0, 0xFFFF, sum = 0
4143 22:53:47.073255 1, 0xFFFF, sum = 0
4144 22:53:47.076493 2, 0xFFFF, sum = 0
4145 22:53:47.076636 3, 0xFFFF, sum = 0
4146 22:53:47.079853 4, 0xFFFF, sum = 0
4147 22:53:47.079948 5, 0xFFFF, sum = 0
4148 22:53:47.083262 6, 0xFFFF, sum = 0
4149 22:53:47.083367 7, 0xFFFF, sum = 0
4150 22:53:47.086187 8, 0x0, sum = 1
4151 22:53:47.086284 9, 0x0, sum = 2
4152 22:53:47.090140 10, 0x0, sum = 3
4153 22:53:47.090263 11, 0x0, sum = 4
4154 22:53:47.090329 best_step = 9
4155 22:53:47.090388
4156 22:53:47.093228 ==
4157 22:53:47.096288 Dram Type= 6, Freq= 0, CH_0, rank 0
4158 22:53:47.099753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 22:53:47.099852 ==
4160 22:53:47.099917 RX Vref Scan: 1
4161 22:53:47.099976
4162 22:53:47.103584 RX Vref 0 -> 0, step: 1
4163 22:53:47.103677
4164 22:53:47.106702 RX Delay -195 -> 252, step: 8
4165 22:53:47.106805
4166 22:53:47.109974 Set Vref, RX VrefLevel [Byte0]: 59
4167 22:53:47.112774 [Byte1]: 58
4168 22:53:47.112868
4169 22:53:47.116164 Final RX Vref Byte 0 = 59 to rank0
4170 22:53:47.119391 Final RX Vref Byte 1 = 58 to rank0
4171 22:53:47.123434 Final RX Vref Byte 0 = 59 to rank1
4172 22:53:47.126288 Final RX Vref Byte 1 = 58 to rank1==
4173 22:53:47.129399 Dram Type= 6, Freq= 0, CH_0, rank 0
4174 22:53:47.132851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 22:53:47.136143 ==
4176 22:53:47.136270 DQS Delay:
4177 22:53:47.136338 DQS0 = 0, DQS1 = 0
4178 22:53:47.139540 DQM Delay:
4179 22:53:47.139631 DQM0 = 44, DQM1 = 32
4180 22:53:47.142482 DQ Delay:
4181 22:53:47.146739 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4182 22:53:47.146841 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4183 22:53:47.149146 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =24
4184 22:53:47.156134 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4185 22:53:47.156269
4186 22:53:47.156335
4187 22:53:47.162395 [DQSOSCAuto] RK0, (LSB)MR18= 0x6138, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
4188 22:53:47.165831 CH0 RK0: MR19=808, MR18=6138
4189 22:53:47.172562 CH0_RK0: MR19=0x808, MR18=0x6138, DQSOSC=391, MR23=63, INC=171, DEC=114
4190 22:53:47.172699
4191 22:53:47.175444 ----->DramcWriteLeveling(PI) begin...
4192 22:53:47.175550 ==
4193 22:53:47.179090 Dram Type= 6, Freq= 0, CH_0, rank 1
4194 22:53:47.182094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4195 22:53:47.182249 ==
4196 22:53:47.185654 Write leveling (Byte 0): 32 => 32
4197 22:53:47.188997 Write leveling (Byte 1): 32 => 32
4198 22:53:47.192024 DramcWriteLeveling(PI) end<-----
4199 22:53:47.192174
4200 22:53:47.192281 ==
4201 22:53:47.195914 Dram Type= 6, Freq= 0, CH_0, rank 1
4202 22:53:47.198743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 22:53:47.198838 ==
4204 22:53:47.201931 [Gating] SW mode calibration
4205 22:53:47.208399 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4206 22:53:47.215468 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4207 22:53:47.219032 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4208 22:53:47.225353 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4209 22:53:47.228070 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4210 22:53:47.231844 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 0)
4211 22:53:47.238000 0 9 16 | B1->B0 | 2e2e 2727 | 0 0 | (1 1) (0 0)
4212 22:53:47.241153 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 22:53:47.245092 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 22:53:47.251829 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 22:53:47.254919 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 22:53:47.258048 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 22:53:47.264397 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 22:53:47.267923 0 10 12 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
4219 22:53:47.271061 0 10 16 | B1->B0 | 3a3a 3f3f | 0 0 | (0 0) (0 0)
4220 22:53:47.277758 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 22:53:47.281164 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 22:53:47.284196 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 22:53:47.290725 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 22:53:47.294275 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 22:53:47.298140 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 22:53:47.304445 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4227 22:53:47.307727 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 22:53:47.311186 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 22:53:47.318057 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 22:53:47.320533 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 22:53:47.324114 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 22:53:47.330751 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 22:53:47.334202 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 22:53:47.337512 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 22:53:47.343876 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 22:53:47.347367 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 22:53:47.350529 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 22:53:47.357497 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 22:53:47.360430 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 22:53:47.363757 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 22:53:47.370498 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 22:53:47.374290 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 22:53:47.377049 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 22:53:47.380853 Total UI for P1: 0, mck2ui 16
4245 22:53:47.383557 best dqsien dly found for B0: ( 0, 13, 14)
4246 22:53:47.386834 Total UI for P1: 0, mck2ui 16
4247 22:53:47.390050 best dqsien dly found for B1: ( 0, 13, 14)
4248 22:53:47.393357 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4249 22:53:47.396584 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4250 22:53:47.396694
4251 22:53:47.400519 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4252 22:53:47.406625 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4253 22:53:47.406777 [Gating] SW calibration Done
4254 22:53:47.409927 ==
4255 22:53:47.410052 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 22:53:47.416481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 22:53:47.416647 ==
4258 22:53:47.416744 RX Vref Scan: 0
4259 22:53:47.416838
4260 22:53:47.420184 RX Vref 0 -> 0, step: 1
4261 22:53:47.420323
4262 22:53:47.423713 RX Delay -230 -> 252, step: 16
4263 22:53:47.426552 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4264 22:53:47.429799 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4265 22:53:47.436799 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4266 22:53:47.439633 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4267 22:53:47.443084 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4268 22:53:47.446338 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4269 22:53:47.452822 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4270 22:53:47.456063 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4271 22:53:47.459261 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4272 22:53:47.462493 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4273 22:53:47.469724 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4274 22:53:47.472596 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4275 22:53:47.475827 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4276 22:53:47.479154 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4277 22:53:47.485777 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4278 22:53:47.489049 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4279 22:53:47.489166 ==
4280 22:53:47.492140 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 22:53:47.495286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 22:53:47.495384 ==
4283 22:53:47.498724 DQS Delay:
4284 22:53:47.498817 DQS0 = 0, DQS1 = 0
4285 22:53:47.498880 DQM Delay:
4286 22:53:47.502444 DQM0 = 43, DQM1 = 35
4287 22:53:47.502539 DQ Delay:
4288 22:53:47.505240 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4289 22:53:47.508521 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4290 22:53:47.512099 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4291 22:53:47.515359 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4292 22:53:47.515471
4293 22:53:47.515536
4294 22:53:47.515594 ==
4295 22:53:47.518773 Dram Type= 6, Freq= 0, CH_0, rank 1
4296 22:53:47.525103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4297 22:53:47.525242 ==
4298 22:53:47.525309
4299 22:53:47.525367
4300 22:53:47.525422 TX Vref Scan disable
4301 22:53:47.528734 == TX Byte 0 ==
4302 22:53:47.532349 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4303 22:53:47.538479 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4304 22:53:47.538616 == TX Byte 1 ==
4305 22:53:47.542051 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4306 22:53:47.548995 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4307 22:53:47.549143 ==
4308 22:53:47.551664 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 22:53:47.555187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 22:53:47.555308 ==
4311 22:53:47.555374
4312 22:53:47.555432
4313 22:53:47.558567 TX Vref Scan disable
4314 22:53:47.561705 == TX Byte 0 ==
4315 22:53:47.565393 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4316 22:53:47.568465 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4317 22:53:47.571812 == TX Byte 1 ==
4318 22:53:47.574985 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4319 22:53:47.578197 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4320 22:53:47.578328
4321 22:53:47.578395 [DATLAT]
4322 22:53:47.581456 Freq=600, CH0 RK1
4323 22:53:47.581546
4324 22:53:47.585016 DATLAT Default: 0x9
4325 22:53:47.585143 0, 0xFFFF, sum = 0
4326 22:53:47.588510 1, 0xFFFF, sum = 0
4327 22:53:47.588619 2, 0xFFFF, sum = 0
4328 22:53:47.591580 3, 0xFFFF, sum = 0
4329 22:53:47.591706 4, 0xFFFF, sum = 0
4330 22:53:47.594507 5, 0xFFFF, sum = 0
4331 22:53:47.594674 6, 0xFFFF, sum = 0
4332 22:53:47.598245 7, 0xFFFF, sum = 0
4333 22:53:47.598371 8, 0x0, sum = 1
4334 22:53:47.601318 9, 0x0, sum = 2
4335 22:53:47.601409 10, 0x0, sum = 3
4336 22:53:47.605663 11, 0x0, sum = 4
4337 22:53:47.605795 best_step = 9
4338 22:53:47.605888
4339 22:53:47.605982 ==
4340 22:53:47.607817 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 22:53:47.611307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 22:53:47.611406 ==
4343 22:53:47.614404 RX Vref Scan: 0
4344 22:53:47.614498
4345 22:53:47.617801 RX Vref 0 -> 0, step: 1
4346 22:53:47.617895
4347 22:53:47.617958 RX Delay -195 -> 252, step: 8
4348 22:53:47.625930 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4349 22:53:47.629069 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4350 22:53:47.632634 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4351 22:53:47.635904 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4352 22:53:47.642942 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4353 22:53:47.645925 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4354 22:53:47.649157 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4355 22:53:47.652148 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4356 22:53:47.659459 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4357 22:53:47.662436 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4358 22:53:47.665613 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4359 22:53:47.668891 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4360 22:53:47.675899 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4361 22:53:47.678575 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4362 22:53:47.682066 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4363 22:53:47.685420 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4364 22:53:47.685539 ==
4365 22:53:47.688860 Dram Type= 6, Freq= 0, CH_0, rank 1
4366 22:53:47.695674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 22:53:47.695810 ==
4368 22:53:47.695878 DQS Delay:
4369 22:53:47.698276 DQS0 = 0, DQS1 = 0
4370 22:53:47.698370 DQM Delay:
4371 22:53:47.698435 DQM0 = 41, DQM1 = 35
4372 22:53:47.701768 DQ Delay:
4373 22:53:47.704971 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4374 22:53:47.708285 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4375 22:53:47.711391 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4376 22:53:47.715598 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =40
4377 22:53:47.715723
4378 22:53:47.715787
4379 22:53:47.721883 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b0e, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps
4380 22:53:47.724817 CH0 RK1: MR19=808, MR18=5B0E
4381 22:53:47.731333 CH0_RK1: MR19=0x808, MR18=0x5B0E, DQSOSC=392, MR23=63, INC=170, DEC=113
4382 22:53:47.734854 [RxdqsGatingPostProcess] freq 600
4383 22:53:47.737891 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4384 22:53:47.741532 Pre-setting of DQS Precalculation
4385 22:53:47.747857 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4386 22:53:47.747999 ==
4387 22:53:47.751087 Dram Type= 6, Freq= 0, CH_1, rank 0
4388 22:53:47.754640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 22:53:47.754753 ==
4390 22:53:47.760794 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4391 22:53:47.767318 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4392 22:53:47.771096 [CA 0] Center 35 (5~66) winsize 62
4393 22:53:47.774071 [CA 1] Center 35 (5~66) winsize 62
4394 22:53:47.777644 [CA 2] Center 34 (4~65) winsize 62
4395 22:53:47.781037 [CA 3] Center 33 (3~64) winsize 62
4396 22:53:47.784161 [CA 4] Center 34 (4~64) winsize 61
4397 22:53:47.787350 [CA 5] Center 33 (3~64) winsize 62
4398 22:53:47.787441
4399 22:53:47.791110 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4400 22:53:47.791245
4401 22:53:47.794338 [CATrainingPosCal] consider 1 rank data
4402 22:53:47.797336 u2DelayCellTimex100 = 270/100 ps
4403 22:53:47.801164 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4404 22:53:47.804449 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4405 22:53:47.807356 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4406 22:53:47.810906 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4407 22:53:47.813819 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4408 22:53:47.817911 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4409 22:53:47.818033
4410 22:53:47.823651 CA PerBit enable=1, Macro0, CA PI delay=33
4411 22:53:47.823778
4412 22:53:47.827358 [CBTSetCACLKResult] CA Dly = 33
4413 22:53:47.827455 CS Dly: 3 (0~34)
4414 22:53:47.827519 ==
4415 22:53:47.830539 Dram Type= 6, Freq= 0, CH_1, rank 1
4416 22:53:47.834211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 22:53:47.834313 ==
4418 22:53:47.840284 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4419 22:53:47.847387 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4420 22:53:47.850399 [CA 0] Center 35 (5~66) winsize 62
4421 22:53:47.853559 [CA 1] Center 36 (6~66) winsize 61
4422 22:53:47.857103 [CA 2] Center 34 (4~65) winsize 62
4423 22:53:47.860374 [CA 3] Center 34 (3~65) winsize 63
4424 22:53:47.863151 [CA 4] Center 34 (3~65) winsize 63
4425 22:53:47.867312 [CA 5] Center 34 (3~65) winsize 63
4426 22:53:47.867439
4427 22:53:47.870039 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4428 22:53:47.870129
4429 22:53:47.873515 [CATrainingPosCal] consider 2 rank data
4430 22:53:47.876596 u2DelayCellTimex100 = 270/100 ps
4431 22:53:47.879729 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4432 22:53:47.883066 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4433 22:53:47.886864 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4434 22:53:47.892895 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4435 22:53:47.896373 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4436 22:53:47.899677 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4437 22:53:47.899790
4438 22:53:47.902973 CA PerBit enable=1, Macro0, CA PI delay=33
4439 22:53:47.903071
4440 22:53:47.906100 [CBTSetCACLKResult] CA Dly = 33
4441 22:53:47.906249 CS Dly: 3 (0~35)
4442 22:53:47.906345
4443 22:53:47.909509 ----->DramcWriteLeveling(PI) begin...
4444 22:53:47.909609 ==
4445 22:53:47.912831 Dram Type= 6, Freq= 0, CH_1, rank 0
4446 22:53:47.919540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4447 22:53:47.919678 ==
4448 22:53:47.922973 Write leveling (Byte 0): 29 => 29
4449 22:53:47.926502 Write leveling (Byte 1): 31 => 31
4450 22:53:47.929400 DramcWriteLeveling(PI) end<-----
4451 22:53:47.929498
4452 22:53:47.929562 ==
4453 22:53:47.932535 Dram Type= 6, Freq= 0, CH_1, rank 0
4454 22:53:47.935826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4455 22:53:47.935924 ==
4456 22:53:47.938994 [Gating] SW mode calibration
4457 22:53:47.946055 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4458 22:53:47.949037 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4459 22:53:47.956257 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4460 22:53:47.958929 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4461 22:53:47.962350 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4462 22:53:47.968714 0 9 12 | B1->B0 | 3333 2d2d | 1 1 | (0 0) (0 1)
4463 22:53:47.972303 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4464 22:53:47.978872 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 22:53:47.981928 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 22:53:47.985424 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 22:53:47.991797 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 22:53:47.995907 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 22:53:47.998401 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 22:53:48.004871 0 10 12 | B1->B0 | 3131 3938 | 0 1 | (0 0) (0 0)
4471 22:53:48.008102 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 22:53:48.011509 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 22:53:48.018672 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 22:53:48.021513 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 22:53:48.025095 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 22:53:48.031376 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 22:53:48.034746 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 22:53:48.037870 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 22:53:48.044623 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4480 22:53:48.047941 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 22:53:48.051144 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 22:53:48.057504 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 22:53:48.061412 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 22:53:48.064388 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 22:53:48.071462 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 22:53:48.073983 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 22:53:48.078580 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 22:53:48.083750 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 22:53:48.087270 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 22:53:48.091555 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 22:53:48.097179 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 22:53:48.100584 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 22:53:48.103845 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 22:53:48.110845 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 22:53:48.110984 Total UI for P1: 0, mck2ui 16
4496 22:53:48.117080 best dqsien dly found for B0: ( 0, 13, 10)
4497 22:53:48.117200 Total UI for P1: 0, mck2ui 16
4498 22:53:48.120486 best dqsien dly found for B1: ( 0, 13, 10)
4499 22:53:48.127269 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4500 22:53:48.130389 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4501 22:53:48.130498
4502 22:53:48.134008 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4503 22:53:48.137350 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4504 22:53:48.140404 [Gating] SW calibration Done
4505 22:53:48.140505 ==
4506 22:53:48.143826 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 22:53:48.147117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 22:53:48.147249 ==
4509 22:53:48.150356 RX Vref Scan: 0
4510 22:53:48.150447
4511 22:53:48.150513 RX Vref 0 -> 0, step: 1
4512 22:53:48.150575
4513 22:53:48.153393 RX Delay -230 -> 252, step: 16
4514 22:53:48.160231 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4515 22:53:48.163470 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4516 22:53:48.166368 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4517 22:53:48.169908 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4518 22:53:48.173021 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4519 22:53:48.179736 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4520 22:53:48.183470 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4521 22:53:48.186149 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4522 22:53:48.189555 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4523 22:53:48.196175 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4524 22:53:48.199856 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4525 22:53:48.202725 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4526 22:53:48.206055 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4527 22:53:48.212923 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4528 22:53:48.216089 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4529 22:53:48.219348 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4530 22:53:48.219448 ==
4531 22:53:48.222997 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 22:53:48.225745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 22:53:48.229020 ==
4534 22:53:48.229131 DQS Delay:
4535 22:53:48.229225 DQS0 = 0, DQS1 = 0
4536 22:53:48.232500 DQM Delay:
4537 22:53:48.232592 DQM0 = 46, DQM1 = 36
4538 22:53:48.235787 DQ Delay:
4539 22:53:48.238821 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4540 22:53:48.238912 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4541 22:53:48.242092 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4542 22:53:48.248894 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =49
4543 22:53:48.249016
4544 22:53:48.249081
4545 22:53:48.249139 ==
4546 22:53:48.252194 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 22:53:48.255281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 22:53:48.255390 ==
4549 22:53:48.255457
4550 22:53:48.255516
4551 22:53:48.259012 TX Vref Scan disable
4552 22:53:48.259128 == TX Byte 0 ==
4553 22:53:48.265553 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4554 22:53:48.268911 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4555 22:53:48.269006 == TX Byte 1 ==
4556 22:53:48.275587 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4557 22:53:48.278910 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4558 22:53:48.279030 ==
4559 22:53:48.281825 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 22:53:48.284940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 22:53:48.285045 ==
4562 22:53:48.288746
4563 22:53:48.288836
4564 22:53:48.288899 TX Vref Scan disable
4565 22:53:48.292311 == TX Byte 0 ==
4566 22:53:48.295057 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4567 22:53:48.301995 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4568 22:53:48.302153 == TX Byte 1 ==
4569 22:53:48.305273 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4570 22:53:48.311765 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4571 22:53:48.311884
4572 22:53:48.311949 [DATLAT]
4573 22:53:48.312008 Freq=600, CH1 RK0
4574 22:53:48.312065
4575 22:53:48.315002 DATLAT Default: 0x9
4576 22:53:48.315087 0, 0xFFFF, sum = 0
4577 22:53:48.318427 1, 0xFFFF, sum = 0
4578 22:53:48.322107 2, 0xFFFF, sum = 0
4579 22:53:48.322273 3, 0xFFFF, sum = 0
4580 22:53:48.325016 4, 0xFFFF, sum = 0
4581 22:53:48.325104 5, 0xFFFF, sum = 0
4582 22:53:48.328199 6, 0xFFFF, sum = 0
4583 22:53:48.328289 7, 0xFFFF, sum = 0
4584 22:53:48.331787 8, 0x0, sum = 1
4585 22:53:48.331888 9, 0x0, sum = 2
4586 22:53:48.331954 10, 0x0, sum = 3
4587 22:53:48.335329 11, 0x0, sum = 4
4588 22:53:48.335421 best_step = 9
4589 22:53:48.335486
4590 22:53:48.338323 ==
4591 22:53:48.338408 Dram Type= 6, Freq= 0, CH_1, rank 0
4592 22:53:48.345326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 22:53:48.345446 ==
4594 22:53:48.345513 RX Vref Scan: 1
4595 22:53:48.345573
4596 22:53:48.348209 RX Vref 0 -> 0, step: 1
4597 22:53:48.348294
4598 22:53:48.351311 RX Delay -195 -> 252, step: 8
4599 22:53:48.351403
4600 22:53:48.355057 Set Vref, RX VrefLevel [Byte0]: 51
4601 22:53:48.358050 [Byte1]: 58
4602 22:53:48.358140
4603 22:53:48.361259 Final RX Vref Byte 0 = 51 to rank0
4604 22:53:48.364425 Final RX Vref Byte 1 = 58 to rank0
4605 22:53:48.368021 Final RX Vref Byte 0 = 51 to rank1
4606 22:53:48.371508 Final RX Vref Byte 1 = 58 to rank1==
4607 22:53:48.374849 Dram Type= 6, Freq= 0, CH_1, rank 0
4608 22:53:48.378099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 22:53:48.381659 ==
4610 22:53:48.381773 DQS Delay:
4611 22:53:48.381840 DQS0 = 0, DQS1 = 0
4612 22:53:48.384824 DQM Delay:
4613 22:53:48.384909 DQM0 = 46, DQM1 = 37
4614 22:53:48.387633 DQ Delay:
4615 22:53:48.387716 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =40
4616 22:53:48.391179 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4617 22:53:48.394300 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4618 22:53:48.397887 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4619 22:53:48.400676
4620 22:53:48.400769
4621 22:53:48.407344 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f33, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4622 22:53:48.410790 CH1 RK0: MR19=808, MR18=4F33
4623 22:53:48.417133 CH1_RK0: MR19=0x808, MR18=0x4F33, DQSOSC=394, MR23=63, INC=168, DEC=112
4624 22:53:48.417259
4625 22:53:48.421294 ----->DramcWriteLeveling(PI) begin...
4626 22:53:48.421390 ==
4627 22:53:48.423740 Dram Type= 6, Freq= 0, CH_1, rank 1
4628 22:53:48.427205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4629 22:53:48.427297 ==
4630 22:53:48.430477 Write leveling (Byte 0): 31 => 31
4631 22:53:48.433673 Write leveling (Byte 1): 30 => 30
4632 22:53:48.437129 DramcWriteLeveling(PI) end<-----
4633 22:53:48.437232
4634 22:53:48.437298 ==
4635 22:53:48.440552 Dram Type= 6, Freq= 0, CH_1, rank 1
4636 22:53:48.443540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 22:53:48.443637 ==
4638 22:53:48.446882 [Gating] SW mode calibration
4639 22:53:48.453480 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4640 22:53:48.460057 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4641 22:53:48.463731 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4642 22:53:48.469991 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4643 22:53:48.473955 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4644 22:53:48.476520 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 0) (1 0)
4645 22:53:48.483152 0 9 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4646 22:53:48.486625 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 22:53:48.489941 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 22:53:48.496379 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 22:53:48.499642 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 22:53:48.503200 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 22:53:48.509450 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 22:53:48.512767 0 10 12 | B1->B0 | 3636 2a2a | 0 0 | (0 0) (0 0)
4653 22:53:48.515956 0 10 16 | B1->B0 | 4646 4242 | 0 1 | (0 0) (0 0)
4654 22:53:48.522889 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 22:53:48.525951 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 22:53:48.529384 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 22:53:48.535696 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 22:53:48.539248 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 22:53:48.542393 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 22:53:48.549132 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4661 22:53:48.552381 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4662 22:53:48.555823 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 22:53:48.562141 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 22:53:48.565441 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 22:53:48.568934 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 22:53:48.575429 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 22:53:48.579204 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 22:53:48.582493 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 22:53:48.588637 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 22:53:48.592426 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 22:53:48.595005 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 22:53:48.602257 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 22:53:48.605195 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 22:53:48.608707 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 22:53:48.615092 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4676 22:53:48.618473 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4677 22:53:48.621751 Total UI for P1: 0, mck2ui 16
4678 22:53:48.625121 best dqsien dly found for B1: ( 0, 13, 8)
4679 22:53:48.628438 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 22:53:48.632024 Total UI for P1: 0, mck2ui 16
4681 22:53:48.634846 best dqsien dly found for B0: ( 0, 13, 12)
4682 22:53:48.638099 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4683 22:53:48.641341 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4684 22:53:48.641441
4685 22:53:48.648092 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4686 22:53:48.651706 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4687 22:53:48.651825 [Gating] SW calibration Done
4688 22:53:48.655032 ==
4689 22:53:48.657917 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 22:53:48.661245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 22:53:48.661340 ==
4692 22:53:48.661406 RX Vref Scan: 0
4693 22:53:48.661464
4694 22:53:48.665156 RX Vref 0 -> 0, step: 1
4695 22:53:48.665244
4696 22:53:48.667819 RX Delay -230 -> 252, step: 16
4697 22:53:48.671366 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4698 22:53:48.674836 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4699 22:53:48.681369 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4700 22:53:48.684339 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4701 22:53:48.687784 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4702 22:53:48.691244 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4703 22:53:48.697650 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4704 22:53:48.701056 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4705 22:53:48.704177 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4706 22:53:48.708193 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4707 22:53:48.710620 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4708 22:53:48.717561 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4709 22:53:48.720612 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4710 22:53:48.724134 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4711 22:53:48.730357 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4712 22:53:48.733774 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4713 22:53:48.733877 ==
4714 22:53:48.736942 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 22:53:48.740814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 22:53:48.740919 ==
4717 22:53:48.744089 DQS Delay:
4718 22:53:48.744181 DQS0 = 0, DQS1 = 0
4719 22:53:48.744246 DQM Delay:
4720 22:53:48.747274 DQM0 = 43, DQM1 = 39
4721 22:53:48.747360 DQ Delay:
4722 22:53:48.750315 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4723 22:53:48.753384 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4724 22:53:48.757161 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4725 22:53:48.760318 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4726 22:53:48.760422
4727 22:53:48.760487
4728 22:53:48.760545 ==
4729 22:53:48.763687 Dram Type= 6, Freq= 0, CH_1, rank 1
4730 22:53:48.769868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4731 22:53:48.769983 ==
4732 22:53:48.770050
4733 22:53:48.770108
4734 22:53:48.770191 TX Vref Scan disable
4735 22:53:48.773611 == TX Byte 0 ==
4736 22:53:48.776830 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4737 22:53:48.783322 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4738 22:53:48.783455 == TX Byte 1 ==
4739 22:53:48.786828 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4740 22:53:48.793175 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4741 22:53:48.793292 ==
4742 22:53:48.796964 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 22:53:48.800050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 22:53:48.800148 ==
4745 22:53:48.800214
4746 22:53:48.800272
4747 22:53:48.803115 TX Vref Scan disable
4748 22:53:48.806423 == TX Byte 0 ==
4749 22:53:48.809798 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4750 22:53:48.812847 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4751 22:53:48.816321 == TX Byte 1 ==
4752 22:53:48.819619 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4753 22:53:48.822880 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4754 22:53:48.822980
4755 22:53:48.826137 [DATLAT]
4756 22:53:48.826267 Freq=600, CH1 RK1
4757 22:53:48.826334
4758 22:53:48.830075 DATLAT Default: 0x9
4759 22:53:48.830208 0, 0xFFFF, sum = 0
4760 22:53:48.833398 1, 0xFFFF, sum = 0
4761 22:53:48.833485 2, 0xFFFF, sum = 0
4762 22:53:48.835908 3, 0xFFFF, sum = 0
4763 22:53:48.835991 4, 0xFFFF, sum = 0
4764 22:53:48.839155 5, 0xFFFF, sum = 0
4765 22:53:48.839243 6, 0xFFFF, sum = 0
4766 22:53:48.842633 7, 0xFFFF, sum = 0
4767 22:53:48.842715 8, 0x0, sum = 1
4768 22:53:48.846553 9, 0x0, sum = 2
4769 22:53:48.846634 10, 0x0, sum = 3
4770 22:53:48.849426 11, 0x0, sum = 4
4771 22:53:48.849509 best_step = 9
4772 22:53:48.849572
4773 22:53:48.849630 ==
4774 22:53:48.853015 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 22:53:48.855943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 22:53:48.856024 ==
4777 22:53:48.859480 RX Vref Scan: 0
4778 22:53:48.859560
4779 22:53:48.862863 RX Vref 0 -> 0, step: 1
4780 22:53:48.862943
4781 22:53:48.866050 RX Delay -179 -> 252, step: 8
4782 22:53:48.869063 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4783 22:53:48.872330 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4784 22:53:48.878873 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4785 22:53:48.882218 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4786 22:53:48.885781 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4787 22:53:48.888815 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4788 22:53:48.895240 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4789 22:53:48.898413 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4790 22:53:48.902399 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4791 22:53:48.905426 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4792 22:53:48.908890 iDelay=213, Bit 10, Center 40 (-115 ~ 196) 312
4793 22:53:48.915155 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4794 22:53:48.918264 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4795 22:53:48.921481 iDelay=213, Bit 13, Center 48 (-107 ~ 204) 312
4796 22:53:48.928483 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4797 22:53:48.931561 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4798 22:53:48.931643 ==
4799 22:53:48.934638 Dram Type= 6, Freq= 0, CH_1, rank 1
4800 22:53:48.938378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4801 22:53:48.938460 ==
4802 22:53:48.938523 DQS Delay:
4803 22:53:48.941864 DQS0 = 0, DQS1 = 0
4804 22:53:48.941943 DQM Delay:
4805 22:53:48.944919 DQM0 = 45, DQM1 = 38
4806 22:53:48.944999 DQ Delay:
4807 22:53:48.948257 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4808 22:53:48.951587 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =40
4809 22:53:48.954930 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4810 22:53:48.958208 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =48
4811 22:53:48.958291
4812 22:53:48.958355
4813 22:53:48.968175 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4814 22:53:48.968265 CH1 RK1: MR19=808, MR18=2E23
4815 22:53:48.974420 CH1_RK1: MR19=0x808, MR18=0x2E23, DQSOSC=401, MR23=63, INC=163, DEC=108
4816 22:53:48.977639 [RxdqsGatingPostProcess] freq 600
4817 22:53:48.984306 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4818 22:53:48.987853 Pre-setting of DQS Precalculation
4819 22:53:48.990794 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4820 22:53:48.997385 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4821 22:53:49.007429 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4822 22:53:49.007560
4823 22:53:49.007657
4824 22:53:49.010548 [Calibration Summary] 1200 Mbps
4825 22:53:49.010649 CH 0, Rank 0
4826 22:53:49.013828 SW Impedance : PASS
4827 22:53:49.013927 DUTY Scan : NO K
4828 22:53:49.017514 ZQ Calibration : PASS
4829 22:53:49.020753 Jitter Meter : NO K
4830 22:53:49.020853 CBT Training : PASS
4831 22:53:49.024379 Write leveling : PASS
4832 22:53:49.027160 RX DQS gating : PASS
4833 22:53:49.027259 RX DQ/DQS(RDDQC) : PASS
4834 22:53:49.030507 TX DQ/DQS : PASS
4835 22:53:49.033732 RX DATLAT : PASS
4836 22:53:49.033830 RX DQ/DQS(Engine): PASS
4837 22:53:49.036869 TX OE : NO K
4838 22:53:49.036973 All Pass.
4839 22:53:49.037064
4840 22:53:49.040553 CH 0, Rank 1
4841 22:53:49.040655 SW Impedance : PASS
4842 22:53:49.043354 DUTY Scan : NO K
4843 22:53:49.046918 ZQ Calibration : PASS
4844 22:53:49.047018 Jitter Meter : NO K
4845 22:53:49.050738 CBT Training : PASS
4846 22:53:49.050823 Write leveling : PASS
4847 22:53:49.053307 RX DQS gating : PASS
4848 22:53:49.057249 RX DQ/DQS(RDDQC) : PASS
4849 22:53:49.057329 TX DQ/DQS : PASS
4850 22:53:49.060042 RX DATLAT : PASS
4851 22:53:49.063457 RX DQ/DQS(Engine): PASS
4852 22:53:49.063539 TX OE : NO K
4853 22:53:49.066690 All Pass.
4854 22:53:49.066874
4855 22:53:49.066941 CH 1, Rank 0
4856 22:53:49.070147 SW Impedance : PASS
4857 22:53:49.070254 DUTY Scan : NO K
4858 22:53:49.072900 ZQ Calibration : PASS
4859 22:53:49.076262 Jitter Meter : NO K
4860 22:53:49.076345 CBT Training : PASS
4861 22:53:49.080077 Write leveling : PASS
4862 22:53:49.082993 RX DQS gating : PASS
4863 22:53:49.083077 RX DQ/DQS(RDDQC) : PASS
4864 22:53:49.086496 TX DQ/DQS : PASS
4865 22:53:49.089625 RX DATLAT : PASS
4866 22:53:49.089709 RX DQ/DQS(Engine): PASS
4867 22:53:49.092991 TX OE : NO K
4868 22:53:49.093072 All Pass.
4869 22:53:49.093135
4870 22:53:49.096267 CH 1, Rank 1
4871 22:53:49.096350 SW Impedance : PASS
4872 22:53:49.099476 DUTY Scan : NO K
4873 22:53:49.102857 ZQ Calibration : PASS
4874 22:53:49.102964 Jitter Meter : NO K
4875 22:53:49.106008 CBT Training : PASS
4876 22:53:49.109627 Write leveling : PASS
4877 22:53:49.109709 RX DQS gating : PASS
4878 22:53:49.112876 RX DQ/DQS(RDDQC) : PASS
4879 22:53:49.115839 TX DQ/DQS : PASS
4880 22:53:49.115920 RX DATLAT : PASS
4881 22:53:49.119465 RX DQ/DQS(Engine): PASS
4882 22:53:49.122827 TX OE : NO K
4883 22:53:49.122907 All Pass.
4884 22:53:49.122971
4885 22:53:49.123046 DramC Write-DBI off
4886 22:53:49.126040 PER_BANK_REFRESH: Hybrid Mode
4887 22:53:49.129180 TX_TRACKING: ON
4888 22:53:49.135720 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4889 22:53:49.139701 [FAST_K] Save calibration result to emmc
4890 22:53:49.146041 dramc_set_vcore_voltage set vcore to 662500
4891 22:53:49.146145 Read voltage for 933, 3
4892 22:53:49.148943 Vio18 = 0
4893 22:53:49.149026 Vcore = 662500
4894 22:53:49.149089 Vdram = 0
4895 22:53:49.152030 Vddq = 0
4896 22:53:49.152112 Vmddr = 0
4897 22:53:49.155614 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4898 22:53:49.162092 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4899 22:53:49.165370 MEM_TYPE=3, freq_sel=17
4900 22:53:49.169218 sv_algorithm_assistance_LP4_1600
4901 22:53:49.172051 ============ PULL DRAM RESETB DOWN ============
4902 22:53:49.175295 ========== PULL DRAM RESETB DOWN end =========
4903 22:53:49.178810 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4904 22:53:49.181820 ===================================
4905 22:53:49.185847 LPDDR4 DRAM CONFIGURATION
4906 22:53:49.189154 ===================================
4907 22:53:49.192169 EX_ROW_EN[0] = 0x0
4908 22:53:49.192250 EX_ROW_EN[1] = 0x0
4909 22:53:49.195447 LP4Y_EN = 0x0
4910 22:53:49.195527 WORK_FSP = 0x0
4911 22:53:49.198220 WL = 0x3
4912 22:53:49.201457 RL = 0x3
4913 22:53:49.201537 BL = 0x2
4914 22:53:49.204713 RPST = 0x0
4915 22:53:49.204794 RD_PRE = 0x0
4916 22:53:49.208762 WR_PRE = 0x1
4917 22:53:49.208843 WR_PST = 0x0
4918 22:53:49.211824 DBI_WR = 0x0
4919 22:53:49.211905 DBI_RD = 0x0
4920 22:53:49.214552 OTF = 0x1
4921 22:53:49.218049 ===================================
4922 22:53:49.221446 ===================================
4923 22:53:49.221531 ANA top config
4924 22:53:49.224687 ===================================
4925 22:53:49.227977 DLL_ASYNC_EN = 0
4926 22:53:49.231412 ALL_SLAVE_EN = 1
4927 22:53:49.231494 NEW_RANK_MODE = 1
4928 22:53:49.234466 DLL_IDLE_MODE = 1
4929 22:53:49.237971 LP45_APHY_COMB_EN = 1
4930 22:53:49.241109 TX_ODT_DIS = 1
4931 22:53:49.244053 NEW_8X_MODE = 1
4932 22:53:49.247883 ===================================
4933 22:53:49.251157 ===================================
4934 22:53:49.254326 data_rate = 1866
4935 22:53:49.254408 CKR = 1
4936 22:53:49.257420 DQ_P2S_RATIO = 8
4937 22:53:49.260474 ===================================
4938 22:53:49.263615 CA_P2S_RATIO = 8
4939 22:53:49.267289 DQ_CA_OPEN = 0
4940 22:53:49.270626 DQ_SEMI_OPEN = 0
4941 22:53:49.273587 CA_SEMI_OPEN = 0
4942 22:53:49.273677 CA_FULL_RATE = 0
4943 22:53:49.277034 DQ_CKDIV4_EN = 1
4944 22:53:49.280202 CA_CKDIV4_EN = 1
4945 22:53:49.283742 CA_PREDIV_EN = 0
4946 22:53:49.287114 PH8_DLY = 0
4947 22:53:49.290316 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4948 22:53:49.290401 DQ_AAMCK_DIV = 4
4949 22:53:49.294409 CA_AAMCK_DIV = 4
4950 22:53:49.296499 CA_ADMCK_DIV = 4
4951 22:53:49.300125 DQ_TRACK_CA_EN = 0
4952 22:53:49.303334 CA_PICK = 933
4953 22:53:49.307603 CA_MCKIO = 933
4954 22:53:49.309914 MCKIO_SEMI = 0
4955 22:53:49.313008 PLL_FREQ = 3732
4956 22:53:49.313092 DQ_UI_PI_RATIO = 32
4957 22:53:49.316490 CA_UI_PI_RATIO = 0
4958 22:53:49.319341 ===================================
4959 22:53:49.322830 ===================================
4960 22:53:49.326478 memory_type:LPDDR4
4961 22:53:49.329435 GP_NUM : 10
4962 22:53:49.329517 SRAM_EN : 1
4963 22:53:49.332691 MD32_EN : 0
4964 22:53:49.336007 ===================================
4965 22:53:49.339276 [ANA_INIT] >>>>>>>>>>>>>>
4966 22:53:49.339363 <<<<<< [CONFIGURE PHASE]: ANA_TX
4967 22:53:49.345789 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4968 22:53:49.349311 ===================================
4969 22:53:49.349396 data_rate = 1866,PCW = 0X8f00
4970 22:53:49.352384 ===================================
4971 22:53:49.355676 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4972 22:53:49.362484 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4973 22:53:49.369395 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4974 22:53:49.372288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4975 22:53:49.375645 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4976 22:53:49.378572 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4977 22:53:49.382268 [ANA_INIT] flow start
4978 22:53:49.385295 [ANA_INIT] PLL >>>>>>>>
4979 22:53:49.385423 [ANA_INIT] PLL <<<<<<<<
4980 22:53:49.388834 [ANA_INIT] MIDPI >>>>>>>>
4981 22:53:49.391795 [ANA_INIT] MIDPI <<<<<<<<
4982 22:53:49.391876 [ANA_INIT] DLL >>>>>>>>
4983 22:53:49.395387 [ANA_INIT] flow end
4984 22:53:49.398797 ============ LP4 DIFF to SE enter ============
4985 22:53:49.401778 ============ LP4 DIFF to SE exit ============
4986 22:53:49.405043 [ANA_INIT] <<<<<<<<<<<<<
4987 22:53:49.408402 [Flow] Enable top DCM control >>>>>
4988 22:53:49.411508 [Flow] Enable top DCM control <<<<<
4989 22:53:49.414783 Enable DLL master slave shuffle
4990 22:53:49.421361 ==============================================================
4991 22:53:49.421450 Gating Mode config
4992 22:53:49.428169 ==============================================================
4993 22:53:49.431610 Config description:
4994 22:53:49.438106 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4995 22:53:49.444817 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4996 22:53:49.451361 SELPH_MODE 0: By rank 1: By Phase
4997 22:53:49.458506 ==============================================================
4998 22:53:49.460860 GAT_TRACK_EN = 1
4999 22:53:49.460948 RX_GATING_MODE = 2
5000 22:53:49.464856 RX_GATING_TRACK_MODE = 2
5001 22:53:49.467702 SELPH_MODE = 1
5002 22:53:49.470974 PICG_EARLY_EN = 1
5003 22:53:49.473943 VALID_LAT_VALUE = 1
5004 22:53:49.480858 ==============================================================
5005 22:53:49.484263 Enter into Gating configuration >>>>
5006 22:53:49.487319 Exit from Gating configuration <<<<
5007 22:53:49.490517 Enter into DVFS_PRE_config >>>>>
5008 22:53:49.500798 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5009 22:53:49.503633 Exit from DVFS_PRE_config <<<<<
5010 22:53:49.507268 Enter into PICG configuration >>>>
5011 22:53:49.510359 Exit from PICG configuration <<<<
5012 22:53:49.513803 [RX_INPUT] configuration >>>>>
5013 22:53:49.517002 [RX_INPUT] configuration <<<<<
5014 22:53:49.520489 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5015 22:53:49.526886 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5016 22:53:49.533666 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5017 22:53:49.540444 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5018 22:53:49.543630 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5019 22:53:49.549920 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5020 22:53:49.556858 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5021 22:53:49.559896 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5022 22:53:49.562945 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5023 22:53:49.566451 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5024 22:53:49.573461 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5025 22:53:49.576420 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5026 22:53:49.580366 ===================================
5027 22:53:49.582909 LPDDR4 DRAM CONFIGURATION
5028 22:53:49.586212 ===================================
5029 22:53:49.586299 EX_ROW_EN[0] = 0x0
5030 22:53:49.589374 EX_ROW_EN[1] = 0x0
5031 22:53:49.589458 LP4Y_EN = 0x0
5032 22:53:49.593232 WORK_FSP = 0x0
5033 22:53:49.593315 WL = 0x3
5034 22:53:49.596082 RL = 0x3
5035 22:53:49.596162 BL = 0x2
5036 22:53:49.599529 RPST = 0x0
5037 22:53:49.599611 RD_PRE = 0x0
5038 22:53:49.602750 WR_PRE = 0x1
5039 22:53:49.605888 WR_PST = 0x0
5040 22:53:49.605970 DBI_WR = 0x0
5041 22:53:49.609438 DBI_RD = 0x0
5042 22:53:49.609521 OTF = 0x1
5043 22:53:49.612450 ===================================
5044 22:53:49.615836 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5045 22:53:49.619141 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5046 22:53:49.626082 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5047 22:53:49.629633 ===================================
5048 22:53:49.632289 LPDDR4 DRAM CONFIGURATION
5049 22:53:49.635725 ===================================
5050 22:53:49.635814 EX_ROW_EN[0] = 0x10
5051 22:53:49.638975 EX_ROW_EN[1] = 0x0
5052 22:53:49.639060 LP4Y_EN = 0x0
5053 22:53:49.642383 WORK_FSP = 0x0
5054 22:53:49.642468 WL = 0x3
5055 22:53:49.645618 RL = 0x3
5056 22:53:49.645773 BL = 0x2
5057 22:53:49.649279 RPST = 0x0
5058 22:53:49.649362 RD_PRE = 0x0
5059 22:53:49.652595 WR_PRE = 0x1
5060 22:53:49.656193 WR_PST = 0x0
5061 22:53:49.656283 DBI_WR = 0x0
5062 22:53:49.659007 DBI_RD = 0x0
5063 22:53:49.659090 OTF = 0x1
5064 22:53:49.662535 ===================================
5065 22:53:49.669071 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5066 22:53:49.672583 nWR fixed to 30
5067 22:53:49.675859 [ModeRegInit_LP4] CH0 RK0
5068 22:53:49.675942 [ModeRegInit_LP4] CH0 RK1
5069 22:53:49.679091 [ModeRegInit_LP4] CH1 RK0
5070 22:53:49.682291 [ModeRegInit_LP4] CH1 RK1
5071 22:53:49.682386 match AC timing 9
5072 22:53:49.688896 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5073 22:53:49.692050 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5074 22:53:49.695365 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5075 22:53:49.701948 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5076 22:53:49.705218 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5077 22:53:49.705308 ==
5078 22:53:49.708451 Dram Type= 6, Freq= 0, CH_0, rank 0
5079 22:53:49.712268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5080 22:53:49.712363 ==
5081 22:53:49.718412 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5082 22:53:49.724797 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5083 22:53:49.728267 [CA 0] Center 37 (7~68) winsize 62
5084 22:53:49.731689 [CA 1] Center 37 (7~68) winsize 62
5085 22:53:49.735270 [CA 2] Center 34 (4~65) winsize 62
5086 22:53:49.738920 [CA 3] Center 35 (5~65) winsize 61
5087 22:53:49.741824 [CA 4] Center 33 (3~64) winsize 62
5088 22:53:49.744629 [CA 5] Center 33 (3~63) winsize 61
5089 22:53:49.744719
5090 22:53:49.748191 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5091 22:53:49.748282
5092 22:53:49.751484 [CATrainingPosCal] consider 1 rank data
5093 22:53:49.754783 u2DelayCellTimex100 = 270/100 ps
5094 22:53:49.757812 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5095 22:53:49.761258 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5096 22:53:49.764455 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5097 22:53:49.771418 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5098 22:53:49.775161 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5099 22:53:49.777832 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5100 22:53:49.777942
5101 22:53:49.781179 CA PerBit enable=1, Macro0, CA PI delay=33
5102 22:53:49.781271
5103 22:53:49.784214 [CBTSetCACLKResult] CA Dly = 33
5104 22:53:49.784299 CS Dly: 7 (0~38)
5105 22:53:49.784365 ==
5106 22:53:49.787581 Dram Type= 6, Freq= 0, CH_0, rank 1
5107 22:53:49.794335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 22:53:49.794435 ==
5109 22:53:49.797524 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5110 22:53:49.804024 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5111 22:53:49.807910 [CA 0] Center 37 (7~68) winsize 62
5112 22:53:49.810949 [CA 1] Center 37 (7~68) winsize 62
5113 22:53:49.814463 [CA 2] Center 34 (4~65) winsize 62
5114 22:53:49.817756 [CA 3] Center 35 (5~65) winsize 61
5115 22:53:49.820512 [CA 4] Center 33 (3~64) winsize 62
5116 22:53:49.824040 [CA 5] Center 33 (3~63) winsize 61
5117 22:53:49.824135
5118 22:53:49.827615 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5119 22:53:49.827703
5120 22:53:49.830897 [CATrainingPosCal] consider 2 rank data
5121 22:53:49.834068 u2DelayCellTimex100 = 270/100 ps
5122 22:53:49.837666 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5123 22:53:49.843781 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5124 22:53:49.847216 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5125 22:53:49.850677 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5126 22:53:49.854085 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5127 22:53:49.857417 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5128 22:53:49.857500
5129 22:53:49.860347 CA PerBit enable=1, Macro0, CA PI delay=33
5130 22:53:49.860430
5131 22:53:49.863556 [CBTSetCACLKResult] CA Dly = 33
5132 22:53:49.866857 CS Dly: 7 (0~39)
5133 22:53:49.866943
5134 22:53:49.870150 ----->DramcWriteLeveling(PI) begin...
5135 22:53:49.870285 ==
5136 22:53:49.873460 Dram Type= 6, Freq= 0, CH_0, rank 0
5137 22:53:49.877133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5138 22:53:49.877234 ==
5139 22:53:49.880401 Write leveling (Byte 0): 33 => 33
5140 22:53:49.883425 Write leveling (Byte 1): 28 => 28
5141 22:53:49.886643 DramcWriteLeveling(PI) end<-----
5142 22:53:49.886748
5143 22:53:49.886814 ==
5144 22:53:49.889986 Dram Type= 6, Freq= 0, CH_0, rank 0
5145 22:53:49.893396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 22:53:49.893504 ==
5147 22:53:49.896797 [Gating] SW mode calibration
5148 22:53:49.903859 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5149 22:53:49.909748 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5150 22:53:49.912866 0 14 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5151 22:53:49.916437 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5152 22:53:49.922999 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 22:53:49.926029 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 22:53:49.929951 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 22:53:49.936491 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 22:53:49.939527 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 22:53:49.942828 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5158 22:53:49.949346 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 0) (1 0)
5159 22:53:49.952693 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 22:53:49.956373 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 22:53:49.962947 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 22:53:49.966325 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 22:53:49.969247 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 22:53:49.975924 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 22:53:49.979328 0 15 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5166 22:53:49.982630 1 0 0 | B1->B0 | 2f2f 4545 | 1 0 | (0 0) (0 0)
5167 22:53:49.988971 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 22:53:49.992126 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 22:53:49.995680 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 22:53:50.001948 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 22:53:50.005873 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 22:53:50.008833 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 22:53:50.015068 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5174 22:53:50.018627 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 22:53:50.021743 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 22:53:50.028336 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 22:53:50.031656 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 22:53:50.035228 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 22:53:50.041640 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 22:53:50.044859 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 22:53:50.048230 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 22:53:50.054765 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 22:53:50.058083 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 22:53:50.061285 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 22:53:50.068109 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 22:53:50.071457 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 22:53:50.074637 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 22:53:50.080992 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 22:53:50.084318 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5190 22:53:50.088017 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5191 22:53:50.090851 Total UI for P1: 0, mck2ui 16
5192 22:53:50.094188 best dqsien dly found for B0: ( 1, 2, 28)
5193 22:53:50.100908 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 22:53:50.104200 Total UI for P1: 0, mck2ui 16
5195 22:53:50.107322 best dqsien dly found for B1: ( 1, 3, 0)
5196 22:53:50.111057 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5197 22:53:50.114133 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5198 22:53:50.114265
5199 22:53:50.117915 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5200 22:53:50.120733 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5201 22:53:50.124175 [Gating] SW calibration Done
5202 22:53:50.124265 ==
5203 22:53:50.127342 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 22:53:50.130778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 22:53:50.130863 ==
5206 22:53:50.134094 RX Vref Scan: 0
5207 22:53:50.134239
5208 22:53:50.137574 RX Vref 0 -> 0, step: 1
5209 22:53:50.137656
5210 22:53:50.137720 RX Delay -80 -> 252, step: 8
5211 22:53:50.143597 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5212 22:53:50.147154 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5213 22:53:50.150346 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5214 22:53:50.153772 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5215 22:53:50.156953 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5216 22:53:50.160624 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5217 22:53:50.167060 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5218 22:53:50.170531 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5219 22:53:50.173428 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5220 22:53:50.176946 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5221 22:53:50.179770 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5222 22:53:50.186407 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5223 22:53:50.189624 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5224 22:53:50.193529 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5225 22:53:50.196478 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5226 22:53:50.199912 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5227 22:53:50.203083 ==
5228 22:53:50.203171 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 22:53:50.209478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 22:53:50.209578 ==
5231 22:53:50.209644 DQS Delay:
5232 22:53:50.213476 DQS0 = 0, DQS1 = 0
5233 22:53:50.213564 DQM Delay:
5234 22:53:50.216086 DQM0 = 96, DQM1 = 86
5235 22:53:50.216168 DQ Delay:
5236 22:53:50.219519 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5237 22:53:50.222587 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5238 22:53:50.226661 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =79
5239 22:53:50.229393 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =91
5240 22:53:50.229480
5241 22:53:50.229543
5242 22:53:50.229601 ==
5243 22:53:50.233271 Dram Type= 6, Freq= 0, CH_0, rank 0
5244 22:53:50.236312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5245 22:53:50.236423 ==
5246 22:53:50.236517
5247 22:53:50.239473
5248 22:53:50.239554 TX Vref Scan disable
5249 22:53:50.242643 == TX Byte 0 ==
5250 22:53:50.245695 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5251 22:53:50.249165 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5252 22:53:50.252533 == TX Byte 1 ==
5253 22:53:50.256034 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5254 22:53:50.259233 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5255 22:53:50.259322 ==
5256 22:53:50.262501 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 22:53:50.268668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 22:53:50.268763 ==
5259 22:53:50.268827
5260 22:53:50.268885
5261 22:53:50.268942 TX Vref Scan disable
5262 22:53:50.273360 == TX Byte 0 ==
5263 22:53:50.276240 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5264 22:53:50.283144 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5265 22:53:50.283263 == TX Byte 1 ==
5266 22:53:50.286099 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5267 22:53:50.293000 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5268 22:53:50.293100
5269 22:53:50.293166 [DATLAT]
5270 22:53:50.293225 Freq=933, CH0 RK0
5271 22:53:50.293283
5272 22:53:50.296181 DATLAT Default: 0xd
5273 22:53:50.299515 0, 0xFFFF, sum = 0
5274 22:53:50.299605 1, 0xFFFF, sum = 0
5275 22:53:50.303199 2, 0xFFFF, sum = 0
5276 22:53:50.303286 3, 0xFFFF, sum = 0
5277 22:53:50.306596 4, 0xFFFF, sum = 0
5278 22:53:50.306682 5, 0xFFFF, sum = 0
5279 22:53:50.309344 6, 0xFFFF, sum = 0
5280 22:53:50.309427 7, 0xFFFF, sum = 0
5281 22:53:50.312440 8, 0xFFFF, sum = 0
5282 22:53:50.312524 9, 0xFFFF, sum = 0
5283 22:53:50.315958 10, 0x0, sum = 1
5284 22:53:50.316044 11, 0x0, sum = 2
5285 22:53:50.318976 12, 0x0, sum = 3
5286 22:53:50.319060 13, 0x0, sum = 4
5287 22:53:50.322475 best_step = 11
5288 22:53:50.322559
5289 22:53:50.322624 ==
5290 22:53:50.325703 Dram Type= 6, Freq= 0, CH_0, rank 0
5291 22:53:50.329088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 22:53:50.329173 ==
5293 22:53:50.329237 RX Vref Scan: 1
5294 22:53:50.332244
5295 22:53:50.332326 RX Vref 0 -> 0, step: 1
5296 22:53:50.332389
5297 22:53:50.335670 RX Delay -69 -> 252, step: 4
5298 22:53:50.335754
5299 22:53:50.339232 Set Vref, RX VrefLevel [Byte0]: 59
5300 22:53:50.342030 [Byte1]: 58
5301 22:53:50.345839
5302 22:53:50.345950 Final RX Vref Byte 0 = 59 to rank0
5303 22:53:50.349142 Final RX Vref Byte 1 = 58 to rank0
5304 22:53:50.352110 Final RX Vref Byte 0 = 59 to rank1
5305 22:53:50.355959 Final RX Vref Byte 1 = 58 to rank1==
5306 22:53:50.359160 Dram Type= 6, Freq= 0, CH_0, rank 0
5307 22:53:50.365981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 22:53:50.366131 ==
5309 22:53:50.366271 DQS Delay:
5310 22:53:50.368892 DQS0 = 0, DQS1 = 0
5311 22:53:50.368997 DQM Delay:
5312 22:53:50.369090 DQM0 = 97, DQM1 = 87
5313 22:53:50.372319 DQ Delay:
5314 22:53:50.375107 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5315 22:53:50.378576 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =104
5316 22:53:50.381964 DQ8 =78, DQ9 =78, DQ10 =86, DQ11 =84
5317 22:53:50.384904 DQ12 =92, DQ13 =90, DQ14 =94, DQ15 =96
5318 22:53:50.385014
5319 22:53:50.385104
5320 22:53:50.392075 [DQSOSCAuto] RK0, (LSB)MR18= 0x260d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 409 ps
5321 22:53:50.395260 CH0 RK0: MR19=505, MR18=260D
5322 22:53:50.401464 CH0_RK0: MR19=0x505, MR18=0x260D, DQSOSC=409, MR23=63, INC=64, DEC=43
5323 22:53:50.401597
5324 22:53:50.404760 ----->DramcWriteLeveling(PI) begin...
5325 22:53:50.404870 ==
5326 22:53:50.408168 Dram Type= 6, Freq= 0, CH_0, rank 1
5327 22:53:50.411660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5328 22:53:50.414672 ==
5329 22:53:50.414786 Write leveling (Byte 0): 32 => 32
5330 22:53:50.418365 Write leveling (Byte 1): 32 => 32
5331 22:53:50.421215 DramcWriteLeveling(PI) end<-----
5332 22:53:50.421320
5333 22:53:50.421409 ==
5334 22:53:50.424509 Dram Type= 6, Freq= 0, CH_0, rank 1
5335 22:53:50.431751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 22:53:50.431885 ==
5337 22:53:50.432003 [Gating] SW mode calibration
5338 22:53:50.441401 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5339 22:53:50.444118 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5340 22:53:50.451050 0 14 0 | B1->B0 | 2c2c 3333 | 1 1 | (0 0) (1 1)
5341 22:53:50.454173 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5342 22:53:50.457405 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 22:53:50.464023 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 22:53:50.467670 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 22:53:50.470389 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 22:53:50.477481 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 22:53:50.480394 0 14 28 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 0)
5348 22:53:50.483931 0 15 0 | B1->B0 | 2d2d 2626 | 1 0 | (1 0) (0 0)
5349 22:53:50.490592 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 22:53:50.493580 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 22:53:50.497200 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 22:53:50.503674 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 22:53:50.507003 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 22:53:50.510147 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 22:53:50.517533 0 15 28 | B1->B0 | 2625 3737 | 1 0 | (0 0) (0 0)
5356 22:53:50.519922 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5357 22:53:50.523591 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 22:53:50.530100 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 22:53:50.533234 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 22:53:50.536548 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 22:53:50.543671 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 22:53:50.547157 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 22:53:50.549615 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 22:53:50.556360 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 22:53:50.559855 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 22:53:50.563705 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 22:53:50.569311 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 22:53:50.572619 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 22:53:50.575983 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 22:53:50.582628 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 22:53:50.585875 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 22:53:50.589336 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 22:53:50.595866 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 22:53:50.599254 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 22:53:50.602820 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 22:53:50.609068 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 22:53:50.612062 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 22:53:50.615781 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 22:53:50.622295 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5380 22:53:50.625430 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5381 22:53:50.628490 Total UI for P1: 0, mck2ui 16
5382 22:53:50.632162 best dqsien dly found for B0: ( 1, 2, 28)
5383 22:53:50.635384 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 22:53:50.638540 Total UI for P1: 0, mck2ui 16
5385 22:53:50.641553 best dqsien dly found for B1: ( 1, 3, 0)
5386 22:53:50.644962 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5387 22:53:50.648730 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5388 22:53:50.648845
5389 22:53:50.651884 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5390 22:53:50.658679 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5391 22:53:50.658782 [Gating] SW calibration Done
5392 22:53:50.661405 ==
5393 22:53:50.661490 Dram Type= 6, Freq= 0, CH_0, rank 1
5394 22:53:50.668069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5395 22:53:50.668167 ==
5396 22:53:50.668235 RX Vref Scan: 0
5397 22:53:50.668294
5398 22:53:50.671700 RX Vref 0 -> 0, step: 1
5399 22:53:50.671786
5400 22:53:50.675024 RX Delay -80 -> 252, step: 8
5401 22:53:50.678017 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5402 22:53:50.681989 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5403 22:53:50.684682 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5404 22:53:50.691098 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5405 22:53:50.694636 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5406 22:53:50.697587 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5407 22:53:50.701068 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5408 22:53:50.704677 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5409 22:53:50.707953 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5410 22:53:50.714086 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5411 22:53:50.717649 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5412 22:53:50.720882 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5413 22:53:50.724199 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5414 22:53:50.727486 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5415 22:53:50.733827 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5416 22:53:50.737374 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5417 22:53:50.737492 ==
5418 22:53:50.740714 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 22:53:50.743842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 22:53:50.743950 ==
5421 22:53:50.744043 DQS Delay:
5422 22:53:50.747158 DQS0 = 0, DQS1 = 0
5423 22:53:50.747261 DQM Delay:
5424 22:53:50.750487 DQM0 = 97, DQM1 = 90
5425 22:53:50.750595 DQ Delay:
5426 22:53:50.754102 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5427 22:53:50.757292 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5428 22:53:50.760707 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =83
5429 22:53:50.764048 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5430 22:53:50.764163
5431 22:53:50.764255
5432 22:53:50.764342 ==
5433 22:53:50.766958 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 22:53:50.773352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 22:53:50.773470 ==
5436 22:53:50.773564
5437 22:53:50.773651
5438 22:53:50.773737 TX Vref Scan disable
5439 22:53:50.777181 == TX Byte 0 ==
5440 22:53:50.780532 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5441 22:53:50.786933 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5442 22:53:50.787075 == TX Byte 1 ==
5443 22:53:50.789917 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5444 22:53:50.796571 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5445 22:53:50.796697 ==
5446 22:53:50.800087 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 22:53:50.803251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 22:53:50.803362 ==
5449 22:53:50.803453
5450 22:53:50.803538
5451 22:53:50.806240 TX Vref Scan disable
5452 22:53:50.806385 == TX Byte 0 ==
5453 22:53:50.813199 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5454 22:53:50.816415 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5455 22:53:50.820318 == TX Byte 1 ==
5456 22:53:50.823425 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5457 22:53:50.826605 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5458 22:53:50.826724
5459 22:53:50.826813 [DATLAT]
5460 22:53:50.829609 Freq=933, CH0 RK1
5461 22:53:50.829716
5462 22:53:50.832737 DATLAT Default: 0xb
5463 22:53:50.832846 0, 0xFFFF, sum = 0
5464 22:53:50.836270 1, 0xFFFF, sum = 0
5465 22:53:50.836380 2, 0xFFFF, sum = 0
5466 22:53:50.839674 3, 0xFFFF, sum = 0
5467 22:53:50.839784 4, 0xFFFF, sum = 0
5468 22:53:50.842526 5, 0xFFFF, sum = 0
5469 22:53:50.842632 6, 0xFFFF, sum = 0
5470 22:53:50.845988 7, 0xFFFF, sum = 0
5471 22:53:50.846094 8, 0xFFFF, sum = 0
5472 22:53:50.849486 9, 0xFFFF, sum = 0
5473 22:53:50.849592 10, 0x0, sum = 1
5474 22:53:50.852596 11, 0x0, sum = 2
5475 22:53:50.852700 12, 0x0, sum = 3
5476 22:53:50.855963 13, 0x0, sum = 4
5477 22:53:50.856069 best_step = 11
5478 22:53:50.856156
5479 22:53:50.856240 ==
5480 22:53:50.859160 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 22:53:50.862612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 22:53:50.865846 ==
5483 22:53:50.865952 RX Vref Scan: 0
5484 22:53:50.866056
5485 22:53:50.868994 RX Vref 0 -> 0, step: 1
5486 22:53:50.869099
5487 22:53:50.872280 RX Delay -61 -> 252, step: 4
5488 22:53:50.876215 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5489 22:53:50.878740 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5490 22:53:50.885877 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5491 22:53:50.889209 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5492 22:53:50.891809 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5493 22:53:50.895378 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5494 22:53:50.898507 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5495 22:53:50.901675 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5496 22:53:50.908431 iDelay=203, Bit 8, Center 82 (-9 ~ 174) 184
5497 22:53:50.912253 iDelay=203, Bit 9, Center 76 (-13 ~ 166) 180
5498 22:53:50.914872 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5499 22:53:50.918295 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5500 22:53:50.921652 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5501 22:53:50.928177 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5502 22:53:50.931880 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5503 22:53:50.934676 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5504 22:53:50.934788 ==
5505 22:53:50.937985 Dram Type= 6, Freq= 0, CH_0, rank 1
5506 22:53:50.941441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 22:53:50.944642 ==
5508 22:53:50.944749 DQS Delay:
5509 22:53:50.944840 DQS0 = 0, DQS1 = 0
5510 22:53:50.948359 DQM Delay:
5511 22:53:50.948465 DQM0 = 95, DQM1 = 87
5512 22:53:50.951670 DQ Delay:
5513 22:53:50.951773 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94
5514 22:53:50.954470 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5515 22:53:50.958099 DQ8 =82, DQ9 =76, DQ10 =92, DQ11 =80
5516 22:53:50.964867 DQ12 =92, DQ13 =92, DQ14 =94, DQ15 =92
5517 22:53:50.964983
5518 22:53:50.965074
5519 22:53:50.971356 [DQSOSCAuto] RK1, (LSB)MR18= 0x22f3, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 411 ps
5520 22:53:50.974358 CH0 RK1: MR19=504, MR18=22F3
5521 22:53:50.981301 CH0_RK1: MR19=0x504, MR18=0x22F3, DQSOSC=411, MR23=63, INC=64, DEC=42
5522 22:53:50.984102 [RxdqsGatingPostProcess] freq 933
5523 22:53:50.987369 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5524 22:53:50.990788 best DQS0 dly(2T, 0.5T) = (0, 10)
5525 22:53:50.994536 best DQS1 dly(2T, 0.5T) = (0, 11)
5526 22:53:50.997372 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5527 22:53:51.000804 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5528 22:53:51.004480 best DQS0 dly(2T, 0.5T) = (0, 10)
5529 22:53:51.007177 best DQS1 dly(2T, 0.5T) = (0, 11)
5530 22:53:51.010720 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5531 22:53:51.013747 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5532 22:53:51.017589 Pre-setting of DQS Precalculation
5533 22:53:51.021088 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5534 22:53:51.021197 ==
5535 22:53:51.023898 Dram Type= 6, Freq= 0, CH_1, rank 0
5536 22:53:51.030680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 22:53:51.030799 ==
5538 22:53:51.033937 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5539 22:53:51.040412 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5540 22:53:51.043986 [CA 0] Center 37 (7~67) winsize 61
5541 22:53:51.046912 [CA 1] Center 37 (6~68) winsize 63
5542 22:53:51.050752 [CA 2] Center 34 (4~65) winsize 62
5543 22:53:51.053389 [CA 3] Center 33 (3~64) winsize 62
5544 22:53:51.057057 [CA 4] Center 35 (5~65) winsize 61
5545 22:53:51.060139 [CA 5] Center 33 (3~64) winsize 62
5546 22:53:51.060246
5547 22:53:51.063645 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5548 22:53:51.063752
5549 22:53:51.067241 [CATrainingPosCal] consider 1 rank data
5550 22:53:51.069952 u2DelayCellTimex100 = 270/100 ps
5551 22:53:51.073572 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5552 22:53:51.080473 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5553 22:53:51.083392 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5554 22:53:51.086781 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5555 22:53:51.090032 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5556 22:53:51.093869 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5557 22:53:51.093975
5558 22:53:51.096836 CA PerBit enable=1, Macro0, CA PI delay=33
5559 22:53:51.096943
5560 22:53:51.100131 [CBTSetCACLKResult] CA Dly = 33
5561 22:53:51.103687 CS Dly: 6 (0~37)
5562 22:53:51.103790 ==
5563 22:53:51.106598 Dram Type= 6, Freq= 0, CH_1, rank 1
5564 22:53:51.110327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 22:53:51.110432 ==
5566 22:53:51.116783 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5567 22:53:51.119424 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5568 22:53:51.123626 [CA 0] Center 37 (7~67) winsize 61
5569 22:53:51.126865 [CA 1] Center 37 (7~68) winsize 62
5570 22:53:51.130342 [CA 2] Center 34 (4~65) winsize 62
5571 22:53:51.134292 [CA 3] Center 34 (4~65) winsize 62
5572 22:53:51.136629 [CA 4] Center 34 (4~65) winsize 62
5573 22:53:51.140198 [CA 5] Center 33 (3~64) winsize 62
5574 22:53:51.140298
5575 22:53:51.143166 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5576 22:53:51.143268
5577 22:53:51.149919 [CATrainingPosCal] consider 2 rank data
5578 22:53:51.150030 u2DelayCellTimex100 = 270/100 ps
5579 22:53:51.156470 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5580 22:53:51.159996 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5581 22:53:51.163027 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5582 22:53:51.166444 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5583 22:53:51.169694 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5584 22:53:51.173558 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5585 22:53:51.173662
5586 22:53:51.176577 CA PerBit enable=1, Macro0, CA PI delay=33
5587 22:53:51.176675
5588 22:53:51.179679 [CBTSetCACLKResult] CA Dly = 33
5589 22:53:51.183317 CS Dly: 7 (0~40)
5590 22:53:51.183422
5591 22:53:51.185952 ----->DramcWriteLeveling(PI) begin...
5592 22:53:51.186056 ==
5593 22:53:51.189633 Dram Type= 6, Freq= 0, CH_1, rank 0
5594 22:53:51.193450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5595 22:53:51.193558 ==
5596 22:53:51.196031 Write leveling (Byte 0): 26 => 26
5597 22:53:51.199404 Write leveling (Byte 1): 27 => 27
5598 22:53:51.203041 DramcWriteLeveling(PI) end<-----
5599 22:53:51.203145
5600 22:53:51.203233 ==
5601 22:53:51.205974 Dram Type= 6, Freq= 0, CH_1, rank 0
5602 22:53:51.209529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5603 22:53:51.209632 ==
5604 22:53:51.212556 [Gating] SW mode calibration
5605 22:53:51.219255 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5606 22:53:51.225703 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5607 22:53:51.229143 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 22:53:51.235662 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 22:53:51.239220 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 22:53:51.242085 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 22:53:51.249389 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 22:53:51.252358 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5613 22:53:51.255500 0 14 24 | B1->B0 | 3232 3333 | 1 1 | (1 1) (1 0)
5614 22:53:51.262033 0 14 28 | B1->B0 | 2d2d 2c2c | 0 0 | (1 1) (1 1)
5615 22:53:51.265715 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5616 22:53:51.268380 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 22:53:51.274986 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 22:53:51.278560 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 22:53:51.281575 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 22:53:51.288042 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 22:53:51.291829 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 22:53:51.294764 0 15 28 | B1->B0 | 3333 3535 | 1 0 | (0 0) (1 1)
5623 22:53:51.302191 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 22:53:51.305320 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 22:53:51.308442 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 22:53:51.314730 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 22:53:51.318048 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 22:53:51.321469 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 22:53:51.327682 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5630 22:53:51.331342 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5631 22:53:51.334368 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5632 22:53:51.340843 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 22:53:51.344771 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 22:53:51.347876 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 22:53:51.354002 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 22:53:51.357365 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 22:53:51.360574 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 22:53:51.367163 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 22:53:51.370836 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 22:53:51.374371 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 22:53:51.380434 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 22:53:51.383551 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 22:53:51.386966 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 22:53:51.393533 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 22:53:51.396643 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5646 22:53:51.400057 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 22:53:51.403474 Total UI for P1: 0, mck2ui 16
5648 22:53:51.407090 best dqsien dly found for B0: ( 1, 2, 24)
5649 22:53:51.409955 Total UI for P1: 0, mck2ui 16
5650 22:53:51.413114 best dqsien dly found for B1: ( 1, 2, 24)
5651 22:53:51.416715 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5652 22:53:51.419711 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5653 22:53:51.419824
5654 22:53:51.426548 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5655 22:53:51.430155 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5656 22:53:51.433391 [Gating] SW calibration Done
5657 22:53:51.433498 ==
5658 22:53:51.436336 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 22:53:51.440300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 22:53:51.440409 ==
5661 22:53:51.440504 RX Vref Scan: 0
5662 22:53:51.440595
5663 22:53:51.443093 RX Vref 0 -> 0, step: 1
5664 22:53:51.443198
5665 22:53:51.446524 RX Delay -80 -> 252, step: 8
5666 22:53:51.450003 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5667 22:53:51.452974 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5668 22:53:51.459484 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5669 22:53:51.462672 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5670 22:53:51.465758 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5671 22:53:51.469164 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5672 22:53:51.472445 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5673 22:53:51.475970 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5674 22:53:51.482413 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5675 22:53:51.485560 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5676 22:53:51.489121 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5677 22:53:51.492162 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5678 22:53:51.495391 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5679 22:53:51.502263 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5680 22:53:51.505385 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5681 22:53:51.509396 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5682 22:53:51.509510 ==
5683 22:53:51.511672 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 22:53:51.515211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 22:53:51.515321 ==
5686 22:53:51.518369 DQS Delay:
5687 22:53:51.518474 DQS0 = 0, DQS1 = 0
5688 22:53:51.521599 DQM Delay:
5689 22:53:51.521703 DQM0 = 102, DQM1 = 91
5690 22:53:51.525413 DQ Delay:
5691 22:53:51.525521 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =99
5692 22:53:51.528675 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5693 22:53:51.531907 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5694 22:53:51.538415 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =103
5695 22:53:51.538535
5696 22:53:51.538628
5697 22:53:51.538716 ==
5698 22:53:51.541767 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 22:53:51.545307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 22:53:51.545412 ==
5701 22:53:51.545490
5702 22:53:51.545552
5703 22:53:51.548123 TX Vref Scan disable
5704 22:53:51.548204 == TX Byte 0 ==
5705 22:53:51.554538 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5706 22:53:51.558101 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5707 22:53:51.558228 == TX Byte 1 ==
5708 22:53:51.564603 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5709 22:53:51.567879 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5710 22:53:51.567970 ==
5711 22:53:51.571315 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 22:53:51.574362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 22:53:51.574475 ==
5714 22:53:51.574567
5715 22:53:51.577938
5716 22:53:51.578021 TX Vref Scan disable
5717 22:53:51.581029 == TX Byte 0 ==
5718 22:53:51.584476 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5719 22:53:51.587856 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5720 22:53:51.591164 == TX Byte 1 ==
5721 22:53:51.594308 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5722 22:53:51.597735 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5723 22:53:51.601004
5724 22:53:51.601087 [DATLAT]
5725 22:53:51.601151 Freq=933, CH1 RK0
5726 22:53:51.601211
5727 22:53:51.604432 DATLAT Default: 0xd
5728 22:53:51.604518 0, 0xFFFF, sum = 0
5729 22:53:51.607786 1, 0xFFFF, sum = 0
5730 22:53:51.607901 2, 0xFFFF, sum = 0
5731 22:53:51.611122 3, 0xFFFF, sum = 0
5732 22:53:51.611225 4, 0xFFFF, sum = 0
5733 22:53:51.614233 5, 0xFFFF, sum = 0
5734 22:53:51.617462 6, 0xFFFF, sum = 0
5735 22:53:51.617544 7, 0xFFFF, sum = 0
5736 22:53:51.620888 8, 0xFFFF, sum = 0
5737 22:53:51.620973 9, 0xFFFF, sum = 0
5738 22:53:51.623974 10, 0x0, sum = 1
5739 22:53:51.624057 11, 0x0, sum = 2
5740 22:53:51.624122 12, 0x0, sum = 3
5741 22:53:51.627480 13, 0x0, sum = 4
5742 22:53:51.627564 best_step = 11
5743 22:53:51.627627
5744 22:53:51.630829 ==
5745 22:53:51.630914 Dram Type= 6, Freq= 0, CH_1, rank 0
5746 22:53:51.637455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 22:53:51.637542 ==
5748 22:53:51.637606 RX Vref Scan: 1
5749 22:53:51.637666
5750 22:53:51.640779 RX Vref 0 -> 0, step: 1
5751 22:53:51.640860
5752 22:53:51.644024 RX Delay -61 -> 252, step: 4
5753 22:53:51.644106
5754 22:53:51.647345 Set Vref, RX VrefLevel [Byte0]: 51
5755 22:53:51.650418 [Byte1]: 58
5756 22:53:51.650529
5757 22:53:51.654419 Final RX Vref Byte 0 = 51 to rank0
5758 22:53:51.657329 Final RX Vref Byte 1 = 58 to rank0
5759 22:53:51.660420 Final RX Vref Byte 0 = 51 to rank1
5760 22:53:51.664074 Final RX Vref Byte 1 = 58 to rank1==
5761 22:53:51.667152 Dram Type= 6, Freq= 0, CH_1, rank 0
5762 22:53:51.670328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 22:53:51.673502 ==
5764 22:53:51.673611 DQS Delay:
5765 22:53:51.673706 DQS0 = 0, DQS1 = 0
5766 22:53:51.676806 DQM Delay:
5767 22:53:51.676910 DQM0 = 100, DQM1 = 93
5768 22:53:51.680631 DQ Delay:
5769 22:53:51.683971 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =98
5770 22:53:51.687057 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =96
5771 22:53:51.690038 DQ8 =84, DQ9 =86, DQ10 =92, DQ11 =86
5772 22:53:51.693351 DQ12 =100, DQ13 =98, DQ14 =100, DQ15 =102
5773 22:53:51.693456
5774 22:53:51.693546
5775 22:53:51.700101 [DQSOSCAuto] RK0, (LSB)MR18= 0x1909, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5776 22:53:51.703297 CH1 RK0: MR19=505, MR18=1909
5777 22:53:51.710291 CH1_RK0: MR19=0x505, MR18=0x1909, DQSOSC=413, MR23=63, INC=63, DEC=42
5778 22:53:51.710407
5779 22:53:51.713080 ----->DramcWriteLeveling(PI) begin...
5780 22:53:51.713182 ==
5781 22:53:51.716287 Dram Type= 6, Freq= 0, CH_1, rank 1
5782 22:53:51.720366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 22:53:51.720470 ==
5784 22:53:51.722855 Write leveling (Byte 0): 24 => 24
5785 22:53:51.726495 Write leveling (Byte 1): 31 => 31
5786 22:53:51.729712 DramcWriteLeveling(PI) end<-----
5787 22:53:51.729818
5788 22:53:51.729908 ==
5789 22:53:51.732919 Dram Type= 6, Freq= 0, CH_1, rank 1
5790 22:53:51.736534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 22:53:51.739624 ==
5792 22:53:51.739728 [Gating] SW mode calibration
5793 22:53:51.749355 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5794 22:53:51.752845 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5795 22:53:51.755900 0 14 0 | B1->B0 | 3434 302f | 1 1 | (1 1) (1 1)
5796 22:53:51.763199 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 22:53:51.765967 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 22:53:51.769109 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 22:53:51.775545 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 22:53:51.778853 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 22:53:51.782441 0 14 24 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 1)
5802 22:53:51.789024 0 14 28 | B1->B0 | 2929 2f2f | 0 0 | (0 0) (1 1)
5803 22:53:51.792330 0 15 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
5804 22:53:51.795399 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 22:53:51.801874 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 22:53:51.805425 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 22:53:51.808438 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 22:53:51.815192 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 22:53:51.818528 0 15 24 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
5810 22:53:51.825526 0 15 28 | B1->B0 | 3b3b 3333 | 0 0 | (0 0) (0 0)
5811 22:53:51.828201 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5812 22:53:51.831683 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 22:53:51.834815 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 22:53:51.841934 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 22:53:51.845264 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 22:53:51.848003 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 22:53:51.854697 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 22:53:51.858240 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5819 22:53:51.861711 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 22:53:51.867973 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 22:53:51.871224 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 22:53:51.874325 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 22:53:51.881648 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 22:53:51.884728 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 22:53:51.887550 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 22:53:51.894639 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 22:53:51.897479 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 22:53:51.900839 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 22:53:51.907685 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 22:53:51.910777 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 22:53:51.914241 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 22:53:51.920965 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 22:53:51.923885 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 22:53:51.927175 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5835 22:53:51.933961 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 22:53:51.937040 Total UI for P1: 0, mck2ui 16
5837 22:53:51.940068 best dqsien dly found for B0: ( 1, 2, 28)
5838 22:53:51.943428 Total UI for P1: 0, mck2ui 16
5839 22:53:51.947461 best dqsien dly found for B1: ( 1, 2, 28)
5840 22:53:51.950170 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5841 22:53:51.953202 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5842 22:53:51.953305
5843 22:53:51.956626 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5844 22:53:51.959912 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5845 22:53:51.963059 [Gating] SW calibration Done
5846 22:53:51.963163 ==
5847 22:53:51.966563 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 22:53:51.970380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 22:53:51.970485 ==
5850 22:53:51.973407 RX Vref Scan: 0
5851 22:53:51.973511
5852 22:53:51.976854 RX Vref 0 -> 0, step: 1
5853 22:53:51.976956
5854 22:53:51.977044 RX Delay -80 -> 252, step: 8
5855 22:53:51.983419 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5856 22:53:51.986864 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5857 22:53:51.990395 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5858 22:53:51.993408 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5859 22:53:51.996671 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5860 22:53:52.000006 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5861 22:53:52.006450 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5862 22:53:52.009828 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5863 22:53:52.013123 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5864 22:53:52.016555 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5865 22:53:52.019861 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5866 22:53:52.026328 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5867 22:53:52.029380 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5868 22:53:52.032715 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5869 22:53:52.036223 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5870 22:53:52.039941 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5871 22:53:52.042588 ==
5872 22:53:52.042672 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 22:53:52.049988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 22:53:52.050091 ==
5875 22:53:52.050155 DQS Delay:
5876 22:53:52.052234 DQS0 = 0, DQS1 = 0
5877 22:53:52.052314 DQM Delay:
5878 22:53:52.056044 DQM0 = 99, DQM1 = 92
5879 22:53:52.056126 DQ Delay:
5880 22:53:52.058952 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5881 22:53:52.062099 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5882 22:53:52.065667 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =87
5883 22:53:52.069309 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =103
5884 22:53:52.069395
5885 22:53:52.069459
5886 22:53:52.069518 ==
5887 22:53:52.072259 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 22:53:52.075694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 22:53:52.075776 ==
5890 22:53:52.079049
5891 22:53:52.079130
5892 22:53:52.079193 TX Vref Scan disable
5893 22:53:52.082181 == TX Byte 0 ==
5894 22:53:52.085458 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5895 22:53:52.089458 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5896 22:53:52.091902 == TX Byte 1 ==
5897 22:53:52.095311 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5898 22:53:52.098626 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5899 22:53:52.101750 ==
5900 22:53:52.105041 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 22:53:52.108474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 22:53:52.108556 ==
5903 22:53:52.108621
5904 22:53:52.108680
5905 22:53:52.111583 TX Vref Scan disable
5906 22:53:52.111664 == TX Byte 0 ==
5907 22:53:52.118613 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5908 22:53:52.122056 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5909 22:53:52.122170 == TX Byte 1 ==
5910 22:53:52.128075 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5911 22:53:52.132039 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5912 22:53:52.132129
5913 22:53:52.132194 [DATLAT]
5914 22:53:52.135021 Freq=933, CH1 RK1
5915 22:53:52.135105
5916 22:53:52.135170 DATLAT Default: 0xb
5917 22:53:52.137984 0, 0xFFFF, sum = 0
5918 22:53:52.138068 1, 0xFFFF, sum = 0
5919 22:53:52.142301 2, 0xFFFF, sum = 0
5920 22:53:52.142386 3, 0xFFFF, sum = 0
5921 22:53:52.144500 4, 0xFFFF, sum = 0
5922 22:53:52.147844 5, 0xFFFF, sum = 0
5923 22:53:52.147928 6, 0xFFFF, sum = 0
5924 22:53:52.151380 7, 0xFFFF, sum = 0
5925 22:53:52.151464 8, 0xFFFF, sum = 0
5926 22:53:52.154509 9, 0xFFFF, sum = 0
5927 22:53:52.154592 10, 0x0, sum = 1
5928 22:53:52.157947 11, 0x0, sum = 2
5929 22:53:52.158102 12, 0x0, sum = 3
5930 22:53:52.158233 13, 0x0, sum = 4
5931 22:53:52.161585 best_step = 11
5932 22:53:52.161666
5933 22:53:52.161728 ==
5934 22:53:52.164724 Dram Type= 6, Freq= 0, CH_1, rank 1
5935 22:53:52.167825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5936 22:53:52.167912 ==
5937 22:53:52.171416 RX Vref Scan: 0
5938 22:53:52.171498
5939 22:53:52.174467 RX Vref 0 -> 0, step: 1
5940 22:53:52.174549
5941 22:53:52.174612 RX Delay -69 -> 252, step: 4
5942 22:53:52.182310 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5943 22:53:52.185623 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5944 22:53:52.188672 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5945 22:53:52.192457 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5946 22:53:52.195647 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
5947 22:53:52.202129 iDelay=207, Bit 5, Center 112 (23 ~ 202) 180
5948 22:53:52.205143 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5949 22:53:52.208529 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5950 22:53:52.211903 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
5951 22:53:52.215057 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5952 22:53:52.218489 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5953 22:53:52.225351 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5954 22:53:52.228211 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
5955 22:53:52.231650 iDelay=207, Bit 13, Center 100 (7 ~ 194) 188
5956 22:53:52.235005 iDelay=207, Bit 14, Center 100 (7 ~ 194) 188
5957 22:53:52.238208 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5958 22:53:52.241519 ==
5959 22:53:52.244624 Dram Type= 6, Freq= 0, CH_1, rank 1
5960 22:53:52.248235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5961 22:53:52.248356 ==
5962 22:53:52.248452 DQS Delay:
5963 22:53:52.251287 DQS0 = 0, DQS1 = 0
5964 22:53:52.251397 DQM Delay:
5965 22:53:52.254981 DQM0 = 101, DQM1 = 93
5966 22:53:52.255099 DQ Delay:
5967 22:53:52.257803 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =98
5968 22:53:52.261288 DQ4 =98, DQ5 =112, DQ6 =114, DQ7 =98
5969 22:53:52.264435 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =84
5970 22:53:52.267799 DQ12 =102, DQ13 =100, DQ14 =100, DQ15 =102
5971 22:53:52.267970
5972 22:53:52.268067
5973 22:53:52.277755 [DQSOSCAuto] RK1, (LSB)MR18= 0x4fc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 420 ps
5974 22:53:52.277980 CH1 RK1: MR19=504, MR18=4FC
5975 22:53:52.284204 CH1_RK1: MR19=0x504, MR18=0x4FC, DQSOSC=420, MR23=63, INC=61, DEC=40
5976 22:53:52.287789 [RxdqsGatingPostProcess] freq 933
5977 22:53:52.293929 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5978 22:53:52.297850 best DQS0 dly(2T, 0.5T) = (0, 10)
5979 22:53:52.300788 best DQS1 dly(2T, 0.5T) = (0, 10)
5980 22:53:52.304007 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5981 22:53:52.307088 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5982 22:53:52.310372 best DQS0 dly(2T, 0.5T) = (0, 10)
5983 22:53:52.313958 best DQS1 dly(2T, 0.5T) = (0, 10)
5984 22:53:52.317143 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5985 22:53:52.320187 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5986 22:53:52.320299 Pre-setting of DQS Precalculation
5987 22:53:52.326740 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5988 22:53:52.333292 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5989 22:53:52.339723 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5990 22:53:52.339894
5991 22:53:52.339995
5992 22:53:52.343203 [Calibration Summary] 1866 Mbps
5993 22:53:52.346458 CH 0, Rank 0
5994 22:53:52.346600 SW Impedance : PASS
5995 22:53:52.350228 DUTY Scan : NO K
5996 22:53:52.352947 ZQ Calibration : PASS
5997 22:53:52.353073 Jitter Meter : NO K
5998 22:53:52.356306 CBT Training : PASS
5999 22:53:52.359423 Write leveling : PASS
6000 22:53:52.359524 RX DQS gating : PASS
6001 22:53:52.362688 RX DQ/DQS(RDDQC) : PASS
6002 22:53:52.366316 TX DQ/DQS : PASS
6003 22:53:52.366432 RX DATLAT : PASS
6004 22:53:52.369113 RX DQ/DQS(Engine): PASS
6005 22:53:52.372964 TX OE : NO K
6006 22:53:52.373069 All Pass.
6007 22:53:52.373134
6008 22:53:52.373192 CH 0, Rank 1
6009 22:53:52.375669 SW Impedance : PASS
6010 22:53:52.379011 DUTY Scan : NO K
6011 22:53:52.379105 ZQ Calibration : PASS
6012 22:53:52.382716 Jitter Meter : NO K
6013 22:53:52.385951 CBT Training : PASS
6014 22:53:52.386098 Write leveling : PASS
6015 22:53:52.389023 RX DQS gating : PASS
6016 22:53:52.392142 RX DQ/DQS(RDDQC) : PASS
6017 22:53:52.392250 TX DQ/DQS : PASS
6018 22:53:52.395583 RX DATLAT : PASS
6019 22:53:52.399062 RX DQ/DQS(Engine): PASS
6020 22:53:52.399164 TX OE : NO K
6021 22:53:52.401923 All Pass.
6022 22:53:52.402035
6023 22:53:52.402128 CH 1, Rank 0
6024 22:53:52.405474 SW Impedance : PASS
6025 22:53:52.405560 DUTY Scan : NO K
6026 22:53:52.409086 ZQ Calibration : PASS
6027 22:53:52.412119 Jitter Meter : NO K
6028 22:53:52.412260 CBT Training : PASS
6029 22:53:52.415292 Write leveling : PASS
6030 22:53:52.418498 RX DQS gating : PASS
6031 22:53:52.418604 RX DQ/DQS(RDDQC) : PASS
6032 22:53:52.422253 TX DQ/DQS : PASS
6033 22:53:52.422359 RX DATLAT : PASS
6034 22:53:52.425229 RX DQ/DQS(Engine): PASS
6035 22:53:52.428721 TX OE : NO K
6036 22:53:52.428831 All Pass.
6037 22:53:52.428897
6038 22:53:52.428956 CH 1, Rank 1
6039 22:53:52.432505 SW Impedance : PASS
6040 22:53:52.435582 DUTY Scan : NO K
6041 22:53:52.435700 ZQ Calibration : PASS
6042 22:53:52.438296 Jitter Meter : NO K
6043 22:53:52.441820 CBT Training : PASS
6044 22:53:52.441938 Write leveling : PASS
6045 22:53:52.444968 RX DQS gating : PASS
6046 22:53:52.448525 RX DQ/DQS(RDDQC) : PASS
6047 22:53:52.448638 TX DQ/DQS : PASS
6048 22:53:52.451932 RX DATLAT : PASS
6049 22:53:52.454716 RX DQ/DQS(Engine): PASS
6050 22:53:52.454853 TX OE : NO K
6051 22:53:52.458441 All Pass.
6052 22:53:52.458528
6053 22:53:52.458592 DramC Write-DBI off
6054 22:53:52.461490 PER_BANK_REFRESH: Hybrid Mode
6055 22:53:52.461571 TX_TRACKING: ON
6056 22:53:52.471550 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6057 22:53:52.474669 [FAST_K] Save calibration result to emmc
6058 22:53:52.477915 dramc_set_vcore_voltage set vcore to 650000
6059 22:53:52.481806 Read voltage for 400, 6
6060 22:53:52.481901 Vio18 = 0
6061 22:53:52.484835 Vcore = 650000
6062 22:53:52.484928 Vdram = 0
6063 22:53:52.484998 Vddq = 0
6064 22:53:52.488149 Vmddr = 0
6065 22:53:52.491480 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6066 22:53:52.498112 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6067 22:53:52.498260 MEM_TYPE=3, freq_sel=20
6068 22:53:52.501287 sv_algorithm_assistance_LP4_800
6069 22:53:52.507901 ============ PULL DRAM RESETB DOWN ============
6070 22:53:52.511306 ========== PULL DRAM RESETB DOWN end =========
6071 22:53:52.514432 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6072 22:53:52.517653 ===================================
6073 22:53:52.521264 LPDDR4 DRAM CONFIGURATION
6074 22:53:52.524356 ===================================
6075 22:53:52.524448 EX_ROW_EN[0] = 0x0
6076 22:53:52.527625 EX_ROW_EN[1] = 0x0
6077 22:53:52.530845 LP4Y_EN = 0x0
6078 22:53:52.530934 WORK_FSP = 0x0
6079 22:53:52.534151 WL = 0x2
6080 22:53:52.534279 RL = 0x2
6081 22:53:52.537235 BL = 0x2
6082 22:53:52.537316 RPST = 0x0
6083 22:53:52.541030 RD_PRE = 0x0
6084 22:53:52.541115 WR_PRE = 0x1
6085 22:53:52.544038 WR_PST = 0x0
6086 22:53:52.544124 DBI_WR = 0x0
6087 22:53:52.547303 DBI_RD = 0x0
6088 22:53:52.547383 OTF = 0x1
6089 22:53:52.550620 ===================================
6090 22:53:52.553914 ===================================
6091 22:53:52.557796 ANA top config
6092 22:53:52.560676 ===================================
6093 22:53:52.563697 DLL_ASYNC_EN = 0
6094 22:53:52.563781 ALL_SLAVE_EN = 1
6095 22:53:52.567936 NEW_RANK_MODE = 1
6096 22:53:52.571015 DLL_IDLE_MODE = 1
6097 22:53:52.573705 LP45_APHY_COMB_EN = 1
6098 22:53:52.573845 TX_ODT_DIS = 1
6099 22:53:52.577443 NEW_8X_MODE = 1
6100 22:53:52.580305 ===================================
6101 22:53:52.583852 ===================================
6102 22:53:52.587031 data_rate = 800
6103 22:53:52.590377 CKR = 1
6104 22:53:52.593795 DQ_P2S_RATIO = 4
6105 22:53:52.596900 ===================================
6106 22:53:52.601083 CA_P2S_RATIO = 4
6107 22:53:52.601226 DQ_CA_OPEN = 0
6108 22:53:52.603745 DQ_SEMI_OPEN = 1
6109 22:53:52.606972 CA_SEMI_OPEN = 1
6110 22:53:52.610226 CA_FULL_RATE = 0
6111 22:53:52.614199 DQ_CKDIV4_EN = 0
6112 22:53:52.616606 CA_CKDIV4_EN = 1
6113 22:53:52.616779 CA_PREDIV_EN = 0
6114 22:53:52.619846 PH8_DLY = 0
6115 22:53:52.623167 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6116 22:53:52.626807 DQ_AAMCK_DIV = 0
6117 22:53:52.629935 CA_AAMCK_DIV = 0
6118 22:53:52.633368 CA_ADMCK_DIV = 4
6119 22:53:52.636066 DQ_TRACK_CA_EN = 0
6120 22:53:52.636152 CA_PICK = 800
6121 22:53:52.639538 CA_MCKIO = 400
6122 22:53:52.643033 MCKIO_SEMI = 400
6123 22:53:52.646409 PLL_FREQ = 3016
6124 22:53:52.649901 DQ_UI_PI_RATIO = 32
6125 22:53:52.653046 CA_UI_PI_RATIO = 32
6126 22:53:52.656478 ===================================
6127 22:53:52.659469 ===================================
6128 22:53:52.663186 memory_type:LPDDR4
6129 22:53:52.663270 GP_NUM : 10
6130 22:53:52.666044 SRAM_EN : 1
6131 22:53:52.666125 MD32_EN : 0
6132 22:53:52.669211 ===================================
6133 22:53:52.672615 [ANA_INIT] >>>>>>>>>>>>>>
6134 22:53:52.675907 <<<<<< [CONFIGURE PHASE]: ANA_TX
6135 22:53:52.679456 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6136 22:53:52.682596 ===================================
6137 22:53:52.685824 data_rate = 800,PCW = 0X7400
6138 22:53:52.689360 ===================================
6139 22:53:52.692566 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6140 22:53:52.699504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6141 22:53:52.709287 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6142 22:53:52.712422 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6143 22:53:52.715649 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6144 22:53:52.719047 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6145 22:53:52.722324 [ANA_INIT] flow start
6146 22:53:52.725524 [ANA_INIT] PLL >>>>>>>>
6147 22:53:52.725626 [ANA_INIT] PLL <<<<<<<<
6148 22:53:52.728729 [ANA_INIT] MIDPI >>>>>>>>
6149 22:53:52.732061 [ANA_INIT] MIDPI <<<<<<<<
6150 22:53:52.735470 [ANA_INIT] DLL >>>>>>>>
6151 22:53:52.735595 [ANA_INIT] flow end
6152 22:53:52.738980 ============ LP4 DIFF to SE enter ============
6153 22:53:52.745853 ============ LP4 DIFF to SE exit ============
6154 22:53:52.745966 [ANA_INIT] <<<<<<<<<<<<<
6155 22:53:52.748549 [Flow] Enable top DCM control >>>>>
6156 22:53:52.751978 [Flow] Enable top DCM control <<<<<
6157 22:53:52.755498 Enable DLL master slave shuffle
6158 22:53:52.762028 ==============================================================
6159 22:53:52.762158 Gating Mode config
6160 22:53:52.768297 ==============================================================
6161 22:53:52.771575 Config description:
6162 22:53:52.781635 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6163 22:53:52.788161 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6164 22:53:52.791569 SELPH_MODE 0: By rank 1: By Phase
6165 22:53:52.798354 ==============================================================
6166 22:53:52.801390 GAT_TRACK_EN = 0
6167 22:53:52.804634 RX_GATING_MODE = 2
6168 22:53:52.808164 RX_GATING_TRACK_MODE = 2
6169 22:53:52.808250 SELPH_MODE = 1
6170 22:53:52.811080 PICG_EARLY_EN = 1
6171 22:53:52.814628 VALID_LAT_VALUE = 1
6172 22:53:52.821095 ==============================================================
6173 22:53:52.824762 Enter into Gating configuration >>>>
6174 22:53:52.827876 Exit from Gating configuration <<<<
6175 22:53:52.830912 Enter into DVFS_PRE_config >>>>>
6176 22:53:52.841563 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6177 22:53:52.844878 Exit from DVFS_PRE_config <<<<<
6178 22:53:52.847391 Enter into PICG configuration >>>>
6179 22:53:52.850815 Exit from PICG configuration <<<<
6180 22:53:52.854084 [RX_INPUT] configuration >>>>>
6181 22:53:52.857563 [RX_INPUT] configuration <<<<<
6182 22:53:52.861113 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6183 22:53:52.867325 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6184 22:53:52.874113 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6185 22:53:52.880992 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6186 22:53:52.887330 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6187 22:53:52.894118 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6188 22:53:52.897168 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6189 22:53:52.900570 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6190 22:53:52.903725 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6191 22:53:52.910451 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6192 22:53:52.913752 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6193 22:53:52.916997 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6194 22:53:52.920021 ===================================
6195 22:53:52.923341 LPDDR4 DRAM CONFIGURATION
6196 22:53:52.926397 ===================================
6197 22:53:52.926480 EX_ROW_EN[0] = 0x0
6198 22:53:52.930308 EX_ROW_EN[1] = 0x0
6199 22:53:52.933719 LP4Y_EN = 0x0
6200 22:53:52.933802 WORK_FSP = 0x0
6201 22:53:52.936428 WL = 0x2
6202 22:53:52.936510 RL = 0x2
6203 22:53:52.939856 BL = 0x2
6204 22:53:52.939938 RPST = 0x0
6205 22:53:52.943109 RD_PRE = 0x0
6206 22:53:52.943246 WR_PRE = 0x1
6207 22:53:52.946470 WR_PST = 0x0
6208 22:53:52.946577 DBI_WR = 0x0
6209 22:53:52.949750 DBI_RD = 0x0
6210 22:53:52.949831 OTF = 0x1
6211 22:53:52.952853 ===================================
6212 22:53:52.956082 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6213 22:53:52.963073 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6214 22:53:52.966428 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6215 22:53:52.969950 ===================================
6216 22:53:52.972879 LPDDR4 DRAM CONFIGURATION
6217 22:53:52.975864 ===================================
6218 22:53:52.976006 EX_ROW_EN[0] = 0x10
6219 22:53:52.979598 EX_ROW_EN[1] = 0x0
6220 22:53:52.982785 LP4Y_EN = 0x0
6221 22:53:52.982867 WORK_FSP = 0x0
6222 22:53:52.985738 WL = 0x2
6223 22:53:52.985903 RL = 0x2
6224 22:53:52.989750 BL = 0x2
6225 22:53:52.989834 RPST = 0x0
6226 22:53:52.992514 RD_PRE = 0x0
6227 22:53:52.992595 WR_PRE = 0x1
6228 22:53:52.996081 WR_PST = 0x0
6229 22:53:52.996163 DBI_WR = 0x0
6230 22:53:52.999272 DBI_RD = 0x0
6231 22:53:52.999353 OTF = 0x1
6232 22:53:53.002599 ===================================
6233 22:53:53.009428 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6234 22:53:53.014004 nWR fixed to 30
6235 22:53:53.016743 [ModeRegInit_LP4] CH0 RK0
6236 22:53:53.016824 [ModeRegInit_LP4] CH0 RK1
6237 22:53:53.019709 [ModeRegInit_LP4] CH1 RK0
6238 22:53:53.023027 [ModeRegInit_LP4] CH1 RK1
6239 22:53:53.023107 match AC timing 19
6240 22:53:53.029687 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6241 22:53:53.033400 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6242 22:53:53.036221 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6243 22:53:53.043172 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6244 22:53:53.046427 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6245 22:53:53.046508 ==
6246 22:53:53.049310 Dram Type= 6, Freq= 0, CH_0, rank 0
6247 22:53:53.052862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6248 22:53:53.052944 ==
6249 22:53:53.059489 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6250 22:53:53.065820 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6251 22:53:53.069380 [CA 0] Center 36 (8~64) winsize 57
6252 22:53:53.073004 [CA 1] Center 36 (8~64) winsize 57
6253 22:53:53.076508 [CA 2] Center 36 (8~64) winsize 57
6254 22:53:53.079450 [CA 3] Center 36 (8~64) winsize 57
6255 22:53:53.082585 [CA 4] Center 36 (8~64) winsize 57
6256 22:53:53.086401 [CA 5] Center 36 (8~64) winsize 57
6257 22:53:53.086492
6258 22:53:53.089087 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6259 22:53:53.089168
6260 22:53:53.092909 [CATrainingPosCal] consider 1 rank data
6261 22:53:53.095745 u2DelayCellTimex100 = 270/100 ps
6262 22:53:53.099207 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 22:53:53.102773 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 22:53:53.105732 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 22:53:53.109002 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 22:53:53.112218 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 22:53:53.115305 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 22:53:53.115387
6269 22:53:53.122042 CA PerBit enable=1, Macro0, CA PI delay=36
6270 22:53:53.122122
6271 22:53:53.122193 [CBTSetCACLKResult] CA Dly = 36
6272 22:53:53.125294 CS Dly: 1 (0~32)
6273 22:53:53.125374 ==
6274 22:53:53.128516 Dram Type= 6, Freq= 0, CH_0, rank 1
6275 22:53:53.131697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 22:53:53.131782 ==
6277 22:53:53.138115 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6278 22:53:53.144838 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6279 22:53:53.148207 [CA 0] Center 36 (8~64) winsize 57
6280 22:53:53.151336 [CA 1] Center 36 (8~64) winsize 57
6281 22:53:53.155381 [CA 2] Center 36 (8~64) winsize 57
6282 22:53:53.158371 [CA 3] Center 36 (8~64) winsize 57
6283 22:53:53.161487 [CA 4] Center 36 (8~64) winsize 57
6284 22:53:53.161567 [CA 5] Center 36 (8~64) winsize 57
6285 22:53:53.164953
6286 22:53:53.167906 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6287 22:53:53.167986
6288 22:53:53.171942 [CATrainingPosCal] consider 2 rank data
6289 22:53:53.174654 u2DelayCellTimex100 = 270/100 ps
6290 22:53:53.178500 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 22:53:53.181245 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 22:53:53.184630 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 22:53:53.187638 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 22:53:53.191926 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 22:53:53.194436 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 22:53:53.194518
6297 22:53:53.197614 CA PerBit enable=1, Macro0, CA PI delay=36
6298 22:53:53.201188
6299 22:53:53.201267 [CBTSetCACLKResult] CA Dly = 36
6300 22:53:53.204446 CS Dly: 1 (0~32)
6301 22:53:53.204525
6302 22:53:53.207795 ----->DramcWriteLeveling(PI) begin...
6303 22:53:53.207876 ==
6304 22:53:53.210996 Dram Type= 6, Freq= 0, CH_0, rank 0
6305 22:53:53.214133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 22:53:53.214253 ==
6307 22:53:53.217832 Write leveling (Byte 0): 40 => 8
6308 22:53:53.221251 Write leveling (Byte 1): 32 => 0
6309 22:53:53.224528 DramcWriteLeveling(PI) end<-----
6310 22:53:53.224607
6311 22:53:53.224669 ==
6312 22:53:53.227921 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 22:53:53.230711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 22:53:53.230791 ==
6315 22:53:53.233887 [Gating] SW mode calibration
6316 22:53:53.240591 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6317 22:53:53.247500 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6318 22:53:53.250850 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6319 22:53:53.257064 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6320 22:53:53.260202 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6321 22:53:53.263982 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6322 22:53:53.270372 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6323 22:53:53.273532 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6324 22:53:53.276990 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6325 22:53:53.283612 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 22:53:53.287249 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6327 22:53:53.290052 Total UI for P1: 0, mck2ui 16
6328 22:53:53.293373 best dqsien dly found for B0: ( 0, 14, 24)
6329 22:53:53.296622 Total UI for P1: 0, mck2ui 16
6330 22:53:53.300205 best dqsien dly found for B1: ( 0, 14, 24)
6331 22:53:53.303343 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6332 22:53:53.306433 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6333 22:53:53.306512
6334 22:53:53.309940 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6335 22:53:53.312891 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6336 22:53:53.316156 [Gating] SW calibration Done
6337 22:53:53.316236 ==
6338 22:53:53.319430 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 22:53:53.326279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 22:53:53.326362 ==
6341 22:53:53.326425 RX Vref Scan: 0
6342 22:53:53.326483
6343 22:53:53.330013 RX Vref 0 -> 0, step: 1
6344 22:53:53.330093
6345 22:53:53.332552 RX Delay -410 -> 252, step: 16
6346 22:53:53.335931 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6347 22:53:53.339290 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6348 22:53:53.346020 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6349 22:53:53.349470 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6350 22:53:53.352450 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6351 22:53:53.355575 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6352 22:53:53.362862 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6353 22:53:53.366060 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6354 22:53:53.369395 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6355 22:53:53.372257 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6356 22:53:53.378682 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6357 22:53:53.381881 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6358 22:53:53.385487 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6359 22:53:53.391901 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6360 22:53:53.395598 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6361 22:53:53.398925 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6362 22:53:53.399005 ==
6363 22:53:53.401735 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 22:53:53.405533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 22:53:53.408997 ==
6366 22:53:53.409081 DQS Delay:
6367 22:53:53.409153 DQS0 = 43, DQS1 = 59
6368 22:53:53.412045 DQM Delay:
6369 22:53:53.412125 DQM0 = 10, DQM1 = 11
6370 22:53:53.415736 DQ Delay:
6371 22:53:53.415816 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6372 22:53:53.418922 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6373 22:53:53.422055 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6374 22:53:53.425197 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6375 22:53:53.425293
6376 22:53:53.425374
6377 22:53:53.425434 ==
6378 22:53:53.428617 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 22:53:53.434754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 22:53:53.434852 ==
6381 22:53:53.434916
6382 22:53:53.435025
6383 22:53:53.438308 TX Vref Scan disable
6384 22:53:53.438387 == TX Byte 0 ==
6385 22:53:53.441796 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6386 22:53:53.448306 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6387 22:53:53.448389 == TX Byte 1 ==
6388 22:53:53.451451 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6389 22:53:53.457913 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6390 22:53:53.457994 ==
6391 22:53:53.461141 Dram Type= 6, Freq= 0, CH_0, rank 0
6392 22:53:53.464972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6393 22:53:53.465057 ==
6394 22:53:53.465120
6395 22:53:53.465177
6396 22:53:53.467996 TX Vref Scan disable
6397 22:53:53.468090 == TX Byte 0 ==
6398 22:53:53.471136 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6399 22:53:53.478100 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6400 22:53:53.478250 == TX Byte 1 ==
6401 22:53:53.481398 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6402 22:53:53.487695 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6403 22:53:53.487807
6404 22:53:53.487911 [DATLAT]
6405 22:53:53.490850 Freq=400, CH0 RK0
6406 22:53:53.490934
6407 22:53:53.490997 DATLAT Default: 0xf
6408 22:53:53.494391 0, 0xFFFF, sum = 0
6409 22:53:53.494474 1, 0xFFFF, sum = 0
6410 22:53:53.497546 2, 0xFFFF, sum = 0
6411 22:53:53.497649 3, 0xFFFF, sum = 0
6412 22:53:53.500926 4, 0xFFFF, sum = 0
6413 22:53:53.501015 5, 0xFFFF, sum = 0
6414 22:53:53.504555 6, 0xFFFF, sum = 0
6415 22:53:53.504649 7, 0xFFFF, sum = 0
6416 22:53:53.507426 8, 0xFFFF, sum = 0
6417 22:53:53.507518 9, 0xFFFF, sum = 0
6418 22:53:53.510848 10, 0xFFFF, sum = 0
6419 22:53:53.510946 11, 0xFFFF, sum = 0
6420 22:53:53.513997 12, 0xFFFF, sum = 0
6421 22:53:53.514079 13, 0x0, sum = 1
6422 22:53:53.517486 14, 0x0, sum = 2
6423 22:53:53.517568 15, 0x0, sum = 3
6424 22:53:53.521145 16, 0x0, sum = 4
6425 22:53:53.521227 best_step = 14
6426 22:53:53.521291
6427 22:53:53.521350 ==
6428 22:53:53.524365 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 22:53:53.530911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 22:53:53.531065 ==
6431 22:53:53.531173 RX Vref Scan: 1
6432 22:53:53.531275
6433 22:53:53.533722 RX Vref 0 -> 0, step: 1
6434 22:53:53.533805
6435 22:53:53.536851 RX Delay -359 -> 252, step: 8
6436 22:53:53.536935
6437 22:53:53.540676 Set Vref, RX VrefLevel [Byte0]: 59
6438 22:53:53.543826 [Byte1]: 58
6439 22:53:53.547267
6440 22:53:53.547358 Final RX Vref Byte 0 = 59 to rank0
6441 22:53:53.550991 Final RX Vref Byte 1 = 58 to rank0
6442 22:53:53.553795 Final RX Vref Byte 0 = 59 to rank1
6443 22:53:53.557090 Final RX Vref Byte 1 = 58 to rank1==
6444 22:53:53.560403 Dram Type= 6, Freq= 0, CH_0, rank 0
6445 22:53:53.566772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 22:53:53.566857 ==
6447 22:53:53.566922 DQS Delay:
6448 22:53:53.570324 DQS0 = 48, DQS1 = 60
6449 22:53:53.570404 DQM Delay:
6450 22:53:53.570502 DQM0 = 11, DQM1 = 10
6451 22:53:53.573503 DQ Delay:
6452 22:53:53.577001 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6453 22:53:53.580162 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6454 22:53:53.580245 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6455 22:53:53.586947 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =16
6456 22:53:53.587061
6457 22:53:53.587174
6458 22:53:53.593413 [DQSOSCAuto] RK0, (LSB)MR18= 0xbc7f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6459 22:53:53.596852 CH0 RK0: MR19=C0C, MR18=BC7F
6460 22:53:53.603644 CH0_RK0: MR19=0xC0C, MR18=0xBC7F, DQSOSC=386, MR23=63, INC=396, DEC=264
6461 22:53:53.603743 ==
6462 22:53:53.606605 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 22:53:53.610298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 22:53:53.610386 ==
6465 22:53:53.612998 [Gating] SW mode calibration
6466 22:53:53.619638 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6467 22:53:53.626503 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6468 22:53:53.630104 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6469 22:53:53.632762 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6470 22:53:53.639996 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6471 22:53:53.643487 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6472 22:53:53.646487 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 22:53:53.652753 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6474 22:53:53.656293 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 22:53:53.659346 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 22:53:53.665999 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6477 22:53:53.669873 Total UI for P1: 0, mck2ui 16
6478 22:53:53.672572 best dqsien dly found for B0: ( 0, 14, 24)
6479 22:53:53.676306 Total UI for P1: 0, mck2ui 16
6480 22:53:53.678956 best dqsien dly found for B1: ( 0, 14, 24)
6481 22:53:53.682230 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6482 22:53:53.685548 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6483 22:53:53.685629
6484 22:53:53.688752 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6485 22:53:53.692086 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6486 22:53:53.695437 [Gating] SW calibration Done
6487 22:53:53.695520 ==
6488 22:53:53.699402 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 22:53:53.702562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 22:53:53.702644 ==
6491 22:53:53.705334 RX Vref Scan: 0
6492 22:53:53.705415
6493 22:53:53.708683 RX Vref 0 -> 0, step: 1
6494 22:53:53.708765
6495 22:53:53.708829 RX Delay -410 -> 252, step: 16
6496 22:53:53.715430 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6497 22:53:53.719160 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6498 22:53:53.722119 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6499 22:53:53.728633 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6500 22:53:53.731881 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6501 22:53:53.735246 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6502 22:53:53.738916 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6503 22:53:53.745311 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6504 22:53:53.748302 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6505 22:53:53.751662 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6506 22:53:53.754929 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6507 22:53:53.761428 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6508 22:53:53.764815 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6509 22:53:53.768116 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6510 22:53:53.772200 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6511 22:53:53.778050 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6512 22:53:53.778133 ==
6513 22:53:53.781107 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 22:53:53.784420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 22:53:53.784507 ==
6516 22:53:53.787719 DQS Delay:
6517 22:53:53.787801 DQS0 = 43, DQS1 = 59
6518 22:53:53.787865 DQM Delay:
6519 22:53:53.791142 DQM0 = 11, DQM1 = 15
6520 22:53:53.791223 DQ Delay:
6521 22:53:53.794721 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6522 22:53:53.797926 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6523 22:53:53.800852 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6524 22:53:53.804330 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6525 22:53:53.804412
6526 22:53:53.804476
6527 22:53:53.804536 ==
6528 22:53:53.808007 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 22:53:53.810861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 22:53:53.814157 ==
6531 22:53:53.814284
6532 22:53:53.814348
6533 22:53:53.814407 TX Vref Scan disable
6534 22:53:53.817547 == TX Byte 0 ==
6535 22:53:53.821339 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6536 22:53:53.824201 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6537 22:53:53.827469 == TX Byte 1 ==
6538 22:53:53.830822 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6539 22:53:53.834294 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6540 22:53:53.834408 ==
6541 22:53:53.837551 Dram Type= 6, Freq= 0, CH_0, rank 1
6542 22:53:53.844164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6543 22:53:53.844257 ==
6544 22:53:53.844323
6545 22:53:53.844382
6546 22:53:53.844439 TX Vref Scan disable
6547 22:53:53.847194 == TX Byte 0 ==
6548 22:53:53.850844 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6549 22:53:53.853864 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6550 22:53:53.857283 == TX Byte 1 ==
6551 22:53:53.860383 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6552 22:53:53.864104 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6553 22:53:53.864186
6554 22:53:53.867215 [DATLAT]
6555 22:53:53.867296 Freq=400, CH0 RK1
6556 22:53:53.867360
6557 22:53:53.870111 DATLAT Default: 0xe
6558 22:53:53.870215 0, 0xFFFF, sum = 0
6559 22:53:53.873464 1, 0xFFFF, sum = 0
6560 22:53:53.873546 2, 0xFFFF, sum = 0
6561 22:53:53.877148 3, 0xFFFF, sum = 0
6562 22:53:53.877231 4, 0xFFFF, sum = 0
6563 22:53:53.880456 5, 0xFFFF, sum = 0
6564 22:53:53.880539 6, 0xFFFF, sum = 0
6565 22:53:53.883447 7, 0xFFFF, sum = 0
6566 22:53:53.883530 8, 0xFFFF, sum = 0
6567 22:53:53.886448 9, 0xFFFF, sum = 0
6568 22:53:53.889760 10, 0xFFFF, sum = 0
6569 22:53:53.889852 11, 0xFFFF, sum = 0
6570 22:53:53.893468 12, 0xFFFF, sum = 0
6571 22:53:53.893552 13, 0x0, sum = 1
6572 22:53:53.896531 14, 0x0, sum = 2
6573 22:53:53.896614 15, 0x0, sum = 3
6574 22:53:53.896680 16, 0x0, sum = 4
6575 22:53:53.900119 best_step = 14
6576 22:53:53.900200
6577 22:53:53.900263 ==
6578 22:53:53.903400 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 22:53:53.906481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 22:53:53.906564 ==
6581 22:53:53.909791 RX Vref Scan: 0
6582 22:53:53.909902
6583 22:53:53.913062 RX Vref 0 -> 0, step: 1
6584 22:53:53.913144
6585 22:53:53.913232 RX Delay -359 -> 252, step: 8
6586 22:53:53.922008 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6587 22:53:53.925274 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6588 22:53:53.928332 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6589 22:53:53.931428 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6590 22:53:53.937958 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6591 22:53:53.941567 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6592 22:53:53.944532 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6593 22:53:53.951235 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6594 22:53:53.954497 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6595 22:53:53.958366 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6596 22:53:53.961368 iDelay=217, Bit 10, Center -44 (-295 ~ 208) 504
6597 22:53:53.968097 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6598 22:53:53.971015 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6599 22:53:53.974792 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6600 22:53:53.977917 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6601 22:53:54.001537 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6602 22:53:54.001684 ==
6603 22:53:54.001754 Dram Type= 6, Freq= 0, CH_0, rank 1
6604 22:53:54.001815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 22:53:54.001873 ==
6606 22:53:54.001930 DQS Delay:
6607 22:53:54.001985 DQS0 = 44, DQS1 = 60
6608 22:53:54.002039 DQM Delay:
6609 22:53:54.002093 DQM0 = 7, DQM1 = 14
6610 22:53:54.002146 DQ Delay:
6611 22:53:54.002245 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6612 22:53:54.004428 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6613 22:53:54.007842 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6614 22:53:54.010741 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6615 22:53:54.010853
6616 22:53:54.010920
6617 22:53:54.017432 [DQSOSCAuto] RK1, (LSB)MR18= 0xb641, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6618 22:53:54.021266 CH0 RK1: MR19=C0C, MR18=B641
6619 22:53:54.027569 CH0_RK1: MR19=0xC0C, MR18=0xB641, DQSOSC=387, MR23=63, INC=394, DEC=262
6620 22:53:54.031019 [RxdqsGatingPostProcess] freq 400
6621 22:53:54.036945 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6622 22:53:54.040092 best DQS0 dly(2T, 0.5T) = (0, 10)
6623 22:53:54.043975 best DQS1 dly(2T, 0.5T) = (0, 10)
6624 22:53:54.047305 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6625 22:53:54.050399 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6626 22:53:54.050482 best DQS0 dly(2T, 0.5T) = (0, 10)
6627 22:53:54.053326 best DQS1 dly(2T, 0.5T) = (0, 10)
6628 22:53:54.056786 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6629 22:53:54.060012 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6630 22:53:54.063328 Pre-setting of DQS Precalculation
6631 22:53:54.069686 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6632 22:53:54.069825 ==
6633 22:53:54.073562 Dram Type= 6, Freq= 0, CH_1, rank 0
6634 22:53:54.076679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 22:53:54.076760 ==
6636 22:53:54.083445 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6637 22:53:54.089982 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6638 22:53:54.092923 [CA 0] Center 36 (8~64) winsize 57
6639 22:53:54.096169 [CA 1] Center 36 (8~64) winsize 57
6640 22:53:54.099739 [CA 2] Center 36 (8~64) winsize 57
6641 22:53:54.099848 [CA 3] Center 36 (8~64) winsize 57
6642 22:53:54.103134 [CA 4] Center 36 (8~64) winsize 57
6643 22:53:54.106157 [CA 5] Center 36 (8~64) winsize 57
6644 22:53:54.106277
6645 22:53:54.109555 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6646 22:53:54.113139
6647 22:53:54.116060 [CATrainingPosCal] consider 1 rank data
6648 22:53:54.119493 u2DelayCellTimex100 = 270/100 ps
6649 22:53:54.122685 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 22:53:54.126347 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 22:53:54.129172 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 22:53:54.132594 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 22:53:54.135931 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 22:53:54.139349 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 22:53:54.139432
6656 22:53:54.142666 CA PerBit enable=1, Macro0, CA PI delay=36
6657 22:53:54.142752
6658 22:53:54.145670 [CBTSetCACLKResult] CA Dly = 36
6659 22:53:54.148913 CS Dly: 1 (0~32)
6660 22:53:54.149031 ==
6661 22:53:54.152609 Dram Type= 6, Freq= 0, CH_1, rank 1
6662 22:53:54.155850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 22:53:54.155954 ==
6664 22:53:54.162279 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6665 22:53:54.168990 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6666 22:53:54.169112 [CA 0] Center 36 (8~64) winsize 57
6667 22:53:54.171894 [CA 1] Center 36 (8~64) winsize 57
6668 22:53:54.175599 [CA 2] Center 36 (8~64) winsize 57
6669 22:53:54.179168 [CA 3] Center 36 (8~64) winsize 57
6670 22:53:54.181969 [CA 4] Center 36 (8~64) winsize 57
6671 22:53:54.185659 [CA 5] Center 36 (8~64) winsize 57
6672 22:53:54.185742
6673 22:53:54.188973 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6674 22:53:54.189058
6675 22:53:54.192191 [CATrainingPosCal] consider 2 rank data
6676 22:53:54.195440 u2DelayCellTimex100 = 270/100 ps
6677 22:53:54.198799 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 22:53:54.205018 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 22:53:54.208286 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 22:53:54.212031 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 22:53:54.215048 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 22:53:54.218131 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 22:53:54.218252
6684 22:53:54.221461 CA PerBit enable=1, Macro0, CA PI delay=36
6685 22:53:54.221543
6686 22:53:54.225143 [CBTSetCACLKResult] CA Dly = 36
6687 22:53:54.228006 CS Dly: 1 (0~32)
6688 22:53:54.228089
6689 22:53:54.231390 ----->DramcWriteLeveling(PI) begin...
6690 22:53:54.231473 ==
6691 22:53:54.234511 Dram Type= 6, Freq= 0, CH_1, rank 0
6692 22:53:54.237997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 22:53:54.238104 ==
6694 22:53:54.241227 Write leveling (Byte 0): 40 => 8
6695 22:53:54.244638 Write leveling (Byte 1): 40 => 8
6696 22:53:54.247831 DramcWriteLeveling(PI) end<-----
6697 22:53:54.247911
6698 22:53:54.247974 ==
6699 22:53:54.251808 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 22:53:54.255011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 22:53:54.255119 ==
6702 22:53:54.257999 [Gating] SW mode calibration
6703 22:53:54.264450 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6704 22:53:54.271281 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6705 22:53:54.274688 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6706 22:53:54.277877 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6707 22:53:54.284110 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6708 22:53:54.287960 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6709 22:53:54.290995 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6710 22:53:54.297812 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6711 22:53:54.300729 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6712 22:53:54.304350 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 22:53:54.310809 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6714 22:53:54.313926 Total UI for P1: 0, mck2ui 16
6715 22:53:54.317207 best dqsien dly found for B0: ( 0, 14, 24)
6716 22:53:54.317291 Total UI for P1: 0, mck2ui 16
6717 22:53:54.324514 best dqsien dly found for B1: ( 0, 14, 24)
6718 22:53:54.328012 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6719 22:53:54.330817 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6720 22:53:54.330897
6721 22:53:54.333776 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6722 22:53:54.337461 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6723 22:53:54.340926 [Gating] SW calibration Done
6724 22:53:54.341007 ==
6725 22:53:54.343659 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 22:53:54.347143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 22:53:54.347224 ==
6728 22:53:54.350668 RX Vref Scan: 0
6729 22:53:54.350748
6730 22:53:54.354140 RX Vref 0 -> 0, step: 1
6731 22:53:54.354259
6732 22:53:54.354322 RX Delay -410 -> 252, step: 16
6733 22:53:54.360503 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6734 22:53:54.364013 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6735 22:53:54.366790 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6736 22:53:54.373695 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6737 22:53:54.376612 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6738 22:53:54.380044 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6739 22:53:54.383166 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6740 22:53:54.390616 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6741 22:53:54.393098 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6742 22:53:54.397230 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6743 22:53:54.399904 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6744 22:53:54.406798 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6745 22:53:54.410020 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6746 22:53:54.412827 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6747 22:53:54.416640 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6748 22:53:54.422730 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6749 22:53:54.422815 ==
6750 22:53:54.426116 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 22:53:54.429661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 22:53:54.429744 ==
6753 22:53:54.429808 DQS Delay:
6754 22:53:54.433086 DQS0 = 43, DQS1 = 51
6755 22:53:54.433168 DQM Delay:
6756 22:53:54.436113 DQM0 = 12, DQM1 = 14
6757 22:53:54.436196 DQ Delay:
6758 22:53:54.439275 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6759 22:53:54.442917 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6760 22:53:54.446134 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6761 22:53:54.449131 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6762 22:53:54.449213
6763 22:53:54.449276
6764 22:53:54.449336 ==
6765 22:53:54.452450 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 22:53:54.456081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 22:53:54.456164 ==
6768 22:53:54.456229
6769 22:53:54.459275
6770 22:53:54.459356 TX Vref Scan disable
6771 22:53:54.462556 == TX Byte 0 ==
6772 22:53:54.465824 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 22:53:54.469119 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 22:53:54.472658 == TX Byte 1 ==
6775 22:53:54.475765 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 22:53:54.479126 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 22:53:54.479208 ==
6778 22:53:54.482359 Dram Type= 6, Freq= 0, CH_1, rank 0
6779 22:53:54.485921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6780 22:53:54.489187 ==
6781 22:53:54.489271
6782 22:53:54.489335
6783 22:53:54.489394 TX Vref Scan disable
6784 22:53:54.492241 == TX Byte 0 ==
6785 22:53:54.495823 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6786 22:53:54.499194 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6787 22:53:54.501845 == TX Byte 1 ==
6788 22:53:54.506119 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6789 22:53:54.509073 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6790 22:53:54.509154
6791 22:53:54.512257 [DATLAT]
6792 22:53:54.512338 Freq=400, CH1 RK0
6793 22:53:54.512402
6794 22:53:54.515410 DATLAT Default: 0xf
6795 22:53:54.515490 0, 0xFFFF, sum = 0
6796 22:53:54.518436 1, 0xFFFF, sum = 0
6797 22:53:54.518519 2, 0xFFFF, sum = 0
6798 22:53:54.521846 3, 0xFFFF, sum = 0
6799 22:53:54.521928 4, 0xFFFF, sum = 0
6800 22:53:54.524928 5, 0xFFFF, sum = 0
6801 22:53:54.525011 6, 0xFFFF, sum = 0
6802 22:53:54.528894 7, 0xFFFF, sum = 0
6803 22:53:54.528977 8, 0xFFFF, sum = 0
6804 22:53:54.531592 9, 0xFFFF, sum = 0
6805 22:53:54.531677 10, 0xFFFF, sum = 0
6806 22:53:54.535243 11, 0xFFFF, sum = 0
6807 22:53:54.538356 12, 0xFFFF, sum = 0
6808 22:53:54.538439 13, 0x0, sum = 1
6809 22:53:54.538504 14, 0x0, sum = 2
6810 22:53:54.541830 15, 0x0, sum = 3
6811 22:53:54.541913 16, 0x0, sum = 4
6812 22:53:54.544726 best_step = 14
6813 22:53:54.544832
6814 22:53:54.544910 ==
6815 22:53:54.547859 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 22:53:54.551556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 22:53:54.551639 ==
6818 22:53:54.554608 RX Vref Scan: 1
6819 22:53:54.554689
6820 22:53:54.554752 RX Vref 0 -> 0, step: 1
6821 22:53:54.557770
6822 22:53:54.557851 RX Delay -343 -> 252, step: 8
6823 22:53:54.557915
6824 22:53:54.561543 Set Vref, RX VrefLevel [Byte0]: 51
6825 22:53:54.564789 [Byte1]: 58
6826 22:53:54.569752
6827 22:53:54.569834 Final RX Vref Byte 0 = 51 to rank0
6828 22:53:54.572981 Final RX Vref Byte 1 = 58 to rank0
6829 22:53:54.576307 Final RX Vref Byte 0 = 51 to rank1
6830 22:53:54.580054 Final RX Vref Byte 1 = 58 to rank1==
6831 22:53:54.582867 Dram Type= 6, Freq= 0, CH_1, rank 0
6832 22:53:54.590147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 22:53:54.590283 ==
6834 22:53:54.590350 DQS Delay:
6835 22:53:54.592935 DQS0 = 44, DQS1 = 56
6836 22:53:54.593016 DQM Delay:
6837 22:53:54.593080 DQM0 = 9, DQM1 = 12
6838 22:53:54.595830 DQ Delay:
6839 22:53:54.599321 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6840 22:53:54.603042 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =0
6841 22:53:54.603124 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6842 22:53:54.606073 DQ12 =24, DQ13 =16, DQ14 =20, DQ15 =24
6843 22:53:54.609550
6844 22:53:54.609631
6845 22:53:54.616035 [DQSOSCAuto] RK0, (LSB)MR18= 0x9167, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6846 22:53:54.619434 CH1 RK0: MR19=C0C, MR18=9167
6847 22:53:54.625649 CH1_RK0: MR19=0xC0C, MR18=0x9167, DQSOSC=391, MR23=63, INC=386, DEC=257
6848 22:53:54.625734 ==
6849 22:53:54.629024 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 22:53:54.632424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 22:53:54.632506 ==
6852 22:53:54.635675 [Gating] SW mode calibration
6853 22:53:54.642666 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6854 22:53:54.648706 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6855 22:53:54.651919 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6856 22:53:54.655607 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6857 22:53:54.661656 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6858 22:53:54.665365 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6859 22:53:54.668296 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6860 22:53:54.674778 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6861 22:53:54.678113 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6862 22:53:54.681331 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 22:53:54.688126 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6864 22:53:54.691595 Total UI for P1: 0, mck2ui 16
6865 22:53:54.694589 best dqsien dly found for B0: ( 0, 14, 24)
6866 22:53:54.698084 Total UI for P1: 0, mck2ui 16
6867 22:53:54.701616 best dqsien dly found for B1: ( 0, 14, 24)
6868 22:53:54.704543 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6869 22:53:54.707858 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6870 22:53:54.707940
6871 22:53:54.711345 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6872 22:53:54.714640 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6873 22:53:54.717603 [Gating] SW calibration Done
6874 22:53:54.717684 ==
6875 22:53:54.720950 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 22:53:54.724331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 22:53:54.724414 ==
6878 22:53:54.727749 RX Vref Scan: 0
6879 22:53:54.727831
6880 22:53:54.730955 RX Vref 0 -> 0, step: 1
6881 22:53:54.731037
6882 22:53:54.733918 RX Delay -410 -> 252, step: 16
6883 22:53:54.737834 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6884 22:53:54.740679 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6885 22:53:54.744069 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6886 22:53:54.750883 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6887 22:53:54.754127 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6888 22:53:54.757403 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6889 22:53:54.760463 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6890 22:53:54.767557 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6891 22:53:54.770345 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6892 22:53:54.773805 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6893 22:53:54.777269 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6894 22:53:54.783712 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6895 22:53:54.786815 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6896 22:53:54.790363 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6897 22:53:54.797128 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6898 22:53:54.800409 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6899 22:53:54.800495 ==
6900 22:53:54.803585 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 22:53:54.807012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 22:53:54.807095 ==
6903 22:53:54.810431 DQS Delay:
6904 22:53:54.810538 DQS0 = 43, DQS1 = 59
6905 22:53:54.810604 DQM Delay:
6906 22:53:54.813528 DQM0 = 12, DQM1 = 22
6907 22:53:54.813609 DQ Delay:
6908 22:53:54.816476 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6909 22:53:54.820034 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6910 22:53:54.823238 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6911 22:53:54.826390 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6912 22:53:54.826473
6913 22:53:54.826536
6914 22:53:54.826596 ==
6915 22:53:54.830121 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 22:53:54.833074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 22:53:54.836662 ==
6918 22:53:54.836743
6919 22:53:54.836807
6920 22:53:54.836866 TX Vref Scan disable
6921 22:53:54.839897 == TX Byte 0 ==
6922 22:53:54.842891 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6923 22:53:54.846132 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6924 22:53:54.850502 == TX Byte 1 ==
6925 22:53:54.852883 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6926 22:53:54.856442 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6927 22:53:54.856523 ==
6928 22:53:54.859944 Dram Type= 6, Freq= 0, CH_1, rank 1
6929 22:53:54.866079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6930 22:53:54.866167 ==
6931 22:53:54.866233
6932 22:53:54.866292
6933 22:53:54.866348 TX Vref Scan disable
6934 22:53:54.869556 == TX Byte 0 ==
6935 22:53:54.872924 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6936 22:53:54.876491 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6937 22:53:54.879314 == TX Byte 1 ==
6938 22:53:54.882534 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6939 22:53:54.885825 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6940 22:53:54.885910
6941 22:53:54.889487 [DATLAT]
6942 22:53:54.889583 Freq=400, CH1 RK1
6943 22:53:54.889648
6944 22:53:54.892333 DATLAT Default: 0xe
6945 22:53:54.892415 0, 0xFFFF, sum = 0
6946 22:53:54.895969 1, 0xFFFF, sum = 0
6947 22:53:54.896052 2, 0xFFFF, sum = 0
6948 22:53:54.899689 3, 0xFFFF, sum = 0
6949 22:53:54.899771 4, 0xFFFF, sum = 0
6950 22:53:54.902824 5, 0xFFFF, sum = 0
6951 22:53:54.902907 6, 0xFFFF, sum = 0
6952 22:53:54.905673 7, 0xFFFF, sum = 0
6953 22:53:54.905756 8, 0xFFFF, sum = 0
6954 22:53:54.909001 9, 0xFFFF, sum = 0
6955 22:53:54.912696 10, 0xFFFF, sum = 0
6956 22:53:54.912779 11, 0xFFFF, sum = 0
6957 22:53:54.916022 12, 0xFFFF, sum = 0
6958 22:53:54.916105 13, 0x0, sum = 1
6959 22:53:54.919037 14, 0x0, sum = 2
6960 22:53:54.919118 15, 0x0, sum = 3
6961 22:53:54.919183 16, 0x0, sum = 4
6962 22:53:54.922344 best_step = 14
6963 22:53:54.922425
6964 22:53:54.922489 ==
6965 22:53:54.926108 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 22:53:54.928896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 22:53:54.928977 ==
6968 22:53:54.932339 RX Vref Scan: 0
6969 22:53:54.932420
6970 22:53:54.932484 RX Vref 0 -> 0, step: 1
6971 22:53:54.935706
6972 22:53:54.935787 RX Delay -359 -> 252, step: 8
6973 22:53:54.943817 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
6974 22:53:54.947196 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6975 22:53:54.950696 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
6976 22:53:54.957486 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6977 22:53:54.960611 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6978 22:53:54.963864 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
6979 22:53:54.967137 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6980 22:53:54.973769 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6981 22:53:54.977090 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6982 22:53:54.980362 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6983 22:53:54.983489 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
6984 22:53:54.990131 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
6985 22:53:54.993444 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6986 22:53:54.996834 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6987 22:53:55.003013 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6988 22:53:55.006303 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
6989 22:53:55.006389 ==
6990 22:53:55.009728 Dram Type= 6, Freq= 0, CH_1, rank 1
6991 22:53:55.013194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6992 22:53:55.013277 ==
6993 22:53:55.016326 DQS Delay:
6994 22:53:55.016407 DQS0 = 44, DQS1 = 56
6995 22:53:55.016472 DQM Delay:
6996 22:53:55.019598 DQM0 = 7, DQM1 = 11
6997 22:53:55.019679 DQ Delay:
6998 22:53:55.023094 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =4
6999 22:53:55.026079 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
7000 22:53:55.029747 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7001 22:53:55.033056 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7002 22:53:55.033140
7003 22:53:55.033204
7004 22:53:55.042642 [DQSOSCAuto] RK1, (LSB)MR18= 0x6252, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7005 22:53:55.042735 CH1 RK1: MR19=C0C, MR18=6252
7006 22:53:55.049738 CH1_RK1: MR19=0xC0C, MR18=0x6252, DQSOSC=397, MR23=63, INC=374, DEC=249
7007 22:53:55.052435 [RxdqsGatingPostProcess] freq 400
7008 22:53:55.059188 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7009 22:53:55.062635 best DQS0 dly(2T, 0.5T) = (0, 10)
7010 22:53:55.065774 best DQS1 dly(2T, 0.5T) = (0, 10)
7011 22:53:55.069541 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7012 22:53:55.072634 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7013 22:53:55.075864 best DQS0 dly(2T, 0.5T) = (0, 10)
7014 22:53:55.075945 best DQS1 dly(2T, 0.5T) = (0, 10)
7015 22:53:55.079069 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7016 22:53:55.082443 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7017 22:53:55.085700 Pre-setting of DQS Precalculation
7018 22:53:55.092628 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7019 22:53:55.098578 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7020 22:53:55.105626 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7021 22:53:55.105710
7022 22:53:55.105774
7023 22:53:55.108732 [Calibration Summary] 800 Mbps
7024 22:53:55.112093 CH 0, Rank 0
7025 22:53:55.112173 SW Impedance : PASS
7026 22:53:55.115110 DUTY Scan : NO K
7027 22:53:55.118675 ZQ Calibration : PASS
7028 22:53:55.118757 Jitter Meter : NO K
7029 22:53:55.121963 CBT Training : PASS
7030 22:53:55.125352 Write leveling : PASS
7031 22:53:55.125434 RX DQS gating : PASS
7032 22:53:55.128580 RX DQ/DQS(RDDQC) : PASS
7033 22:53:55.128661 TX DQ/DQS : PASS
7034 22:53:55.132065 RX DATLAT : PASS
7035 22:53:55.134723 RX DQ/DQS(Engine): PASS
7036 22:53:55.134804 TX OE : NO K
7037 22:53:55.138107 All Pass.
7038 22:53:55.138224
7039 22:53:55.138288 CH 0, Rank 1
7040 22:53:55.141770 SW Impedance : PASS
7041 22:53:55.141852 DUTY Scan : NO K
7042 22:53:55.144789 ZQ Calibration : PASS
7043 22:53:55.148208 Jitter Meter : NO K
7044 22:53:55.148290 CBT Training : PASS
7045 22:53:55.151274 Write leveling : NO K
7046 22:53:55.154767 RX DQS gating : PASS
7047 22:53:55.154849 RX DQ/DQS(RDDQC) : PASS
7048 22:53:55.158155 TX DQ/DQS : PASS
7049 22:53:55.161326 RX DATLAT : PASS
7050 22:53:55.161406 RX DQ/DQS(Engine): PASS
7051 22:53:55.164870 TX OE : NO K
7052 22:53:55.164951 All Pass.
7053 22:53:55.165015
7054 22:53:55.168028 CH 1, Rank 0
7055 22:53:55.168109 SW Impedance : PASS
7056 22:53:55.171664 DUTY Scan : NO K
7057 22:53:55.174606 ZQ Calibration : PASS
7058 22:53:55.174687 Jitter Meter : NO K
7059 22:53:55.177880 CBT Training : PASS
7060 22:53:55.181253 Write leveling : PASS
7061 22:53:55.181335 RX DQS gating : PASS
7062 22:53:55.184154 RX DQ/DQS(RDDQC) : PASS
7063 22:53:55.187509 TX DQ/DQS : PASS
7064 22:53:55.187591 RX DATLAT : PASS
7065 22:53:55.191053 RX DQ/DQS(Engine): PASS
7066 22:53:55.194789 TX OE : NO K
7067 22:53:55.194871 All Pass.
7068 22:53:55.194936
7069 22:53:55.194994 CH 1, Rank 1
7070 22:53:55.197383 SW Impedance : PASS
7071 22:53:55.200862 DUTY Scan : NO K
7072 22:53:55.200944 ZQ Calibration : PASS
7073 22:53:55.203971 Jitter Meter : NO K
7074 22:53:55.207323 CBT Training : PASS
7075 22:53:55.207404 Write leveling : NO K
7076 22:53:55.210652 RX DQS gating : PASS
7077 22:53:55.210734 RX DQ/DQS(RDDQC) : PASS
7078 22:53:55.213900 TX DQ/DQS : PASS
7079 22:53:55.217490 RX DATLAT : PASS
7080 22:53:55.217572 RX DQ/DQS(Engine): PASS
7081 22:53:55.220610 TX OE : NO K
7082 22:53:55.220692 All Pass.
7083 22:53:55.220756
7084 22:53:55.224177 DramC Write-DBI off
7085 22:53:55.227438 PER_BANK_REFRESH: Hybrid Mode
7086 22:53:55.227520 TX_TRACKING: ON
7087 22:53:55.237200 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7088 22:53:55.240524 [FAST_K] Save calibration result to emmc
7089 22:53:55.243854 dramc_set_vcore_voltage set vcore to 725000
7090 22:53:55.247553 Read voltage for 1600, 0
7091 22:53:55.247637 Vio18 = 0
7092 22:53:55.249969 Vcore = 725000
7093 22:53:55.250050 Vdram = 0
7094 22:53:55.250114 Vddq = 0
7095 22:53:55.250199 Vmddr = 0
7096 22:53:55.256671 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7097 22:53:55.263212 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7098 22:53:55.263301 MEM_TYPE=3, freq_sel=13
7099 22:53:55.266465 sv_algorithm_assistance_LP4_3733
7100 22:53:55.270040 ============ PULL DRAM RESETB DOWN ============
7101 22:53:55.276337 ========== PULL DRAM RESETB DOWN end =========
7102 22:53:55.279802 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7103 22:53:55.282928 ===================================
7104 22:53:55.286784 LPDDR4 DRAM CONFIGURATION
7105 22:53:55.289755 ===================================
7106 22:53:55.293182 EX_ROW_EN[0] = 0x0
7107 22:53:55.293272 EX_ROW_EN[1] = 0x0
7108 22:53:55.296039 LP4Y_EN = 0x0
7109 22:53:55.296121 WORK_FSP = 0x1
7110 22:53:55.299699 WL = 0x5
7111 22:53:55.299781 RL = 0x5
7112 22:53:55.302492 BL = 0x2
7113 22:53:55.302573 RPST = 0x0
7114 22:53:55.306103 RD_PRE = 0x0
7115 22:53:55.306225 WR_PRE = 0x1
7116 22:53:55.309389 WR_PST = 0x1
7117 22:53:55.309470 DBI_WR = 0x0
7118 22:53:55.312898 DBI_RD = 0x0
7119 22:53:55.312980 OTF = 0x1
7120 22:53:55.315819 ===================================
7121 22:53:55.319283 ===================================
7122 22:53:55.322302 ANA top config
7123 22:53:55.325452 ===================================
7124 22:53:55.329062 DLL_ASYNC_EN = 0
7125 22:53:55.329143 ALL_SLAVE_EN = 0
7126 22:53:55.332649 NEW_RANK_MODE = 1
7127 22:53:55.336134 DLL_IDLE_MODE = 1
7128 22:53:55.339131 LP45_APHY_COMB_EN = 1
7129 22:53:55.339213 TX_ODT_DIS = 0
7130 22:53:55.342367 NEW_8X_MODE = 1
7131 22:53:55.345746 ===================================
7132 22:53:55.348855 ===================================
7133 22:53:55.351904 data_rate = 3200
7134 22:53:55.355076 CKR = 1
7135 22:53:55.358272 DQ_P2S_RATIO = 8
7136 22:53:55.362048 ===================================
7137 22:53:55.364757 CA_P2S_RATIO = 8
7138 22:53:55.368160 DQ_CA_OPEN = 0
7139 22:53:55.368243 DQ_SEMI_OPEN = 0
7140 22:53:55.372112 CA_SEMI_OPEN = 0
7141 22:53:55.374775 CA_FULL_RATE = 0
7142 22:53:55.378504 DQ_CKDIV4_EN = 0
7143 22:53:55.381717 CA_CKDIV4_EN = 0
7144 22:53:55.384628 CA_PREDIV_EN = 0
7145 22:53:55.384713 PH8_DLY = 12
7146 22:53:55.387964 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7147 22:53:55.391723 DQ_AAMCK_DIV = 4
7148 22:53:55.394973 CA_AAMCK_DIV = 4
7149 22:53:55.398577 CA_ADMCK_DIV = 4
7150 22:53:55.401437 DQ_TRACK_CA_EN = 0
7151 22:53:55.404497 CA_PICK = 1600
7152 22:53:55.407589 CA_MCKIO = 1600
7153 22:53:55.407671 MCKIO_SEMI = 0
7154 22:53:55.411287 PLL_FREQ = 3068
7155 22:53:55.414449 DQ_UI_PI_RATIO = 32
7156 22:53:55.417368 CA_UI_PI_RATIO = 0
7157 22:53:55.420994 ===================================
7158 22:53:55.423948 ===================================
7159 22:53:55.427510 memory_type:LPDDR4
7160 22:53:55.427591 GP_NUM : 10
7161 22:53:55.430655 SRAM_EN : 1
7162 22:53:55.433599 MD32_EN : 0
7163 22:53:55.437521 ===================================
7164 22:53:55.437603 [ANA_INIT] >>>>>>>>>>>>>>
7165 22:53:55.440261 <<<<<< [CONFIGURE PHASE]: ANA_TX
7166 22:53:55.443786 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7167 22:53:55.447096 ===================================
7168 22:53:55.450740 data_rate = 3200,PCW = 0X7600
7169 22:53:55.454182 ===================================
7170 22:53:55.457007 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7171 22:53:55.464036 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7172 22:53:55.466686 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7173 22:53:55.474093 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7174 22:53:55.477102 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7175 22:53:55.480023 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7176 22:53:55.483774 [ANA_INIT] flow start
7177 22:53:55.483856 [ANA_INIT] PLL >>>>>>>>
7178 22:53:55.486404 [ANA_INIT] PLL <<<<<<<<
7179 22:53:55.489924 [ANA_INIT] MIDPI >>>>>>>>
7180 22:53:55.490006 [ANA_INIT] MIDPI <<<<<<<<
7181 22:53:55.493408 [ANA_INIT] DLL >>>>>>>>
7182 22:53:55.496436 [ANA_INIT] DLL <<<<<<<<
7183 22:53:55.496518 [ANA_INIT] flow end
7184 22:53:55.503022 ============ LP4 DIFF to SE enter ============
7185 22:53:55.506504 ============ LP4 DIFF to SE exit ============
7186 22:53:55.510414 [ANA_INIT] <<<<<<<<<<<<<
7187 22:53:55.512923 [Flow] Enable top DCM control >>>>>
7188 22:53:55.516177 [Flow] Enable top DCM control <<<<<
7189 22:53:55.516268 Enable DLL master slave shuffle
7190 22:53:55.523057 ==============================================================
7191 22:53:55.526384 Gating Mode config
7192 22:53:55.529518 ==============================================================
7193 22:53:55.532676 Config description:
7194 22:53:55.543077 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7195 22:53:55.549206 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7196 22:53:55.552953 SELPH_MODE 0: By rank 1: By Phase
7197 22:53:55.559426 ==============================================================
7198 22:53:55.562315 GAT_TRACK_EN = 1
7199 22:53:55.566158 RX_GATING_MODE = 2
7200 22:53:55.569450 RX_GATING_TRACK_MODE = 2
7201 22:53:55.572782 SELPH_MODE = 1
7202 22:53:55.575542 PICG_EARLY_EN = 1
7203 22:53:55.575625 VALID_LAT_VALUE = 1
7204 22:53:55.582086 ==============================================================
7205 22:53:55.585216 Enter into Gating configuration >>>>
7206 22:53:55.589137 Exit from Gating configuration <<<<
7207 22:53:55.592204 Enter into DVFS_PRE_config >>>>>
7208 22:53:55.601871 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7209 22:53:55.605543 Exit from DVFS_PRE_config <<<<<
7210 22:53:55.608589 Enter into PICG configuration >>>>
7211 22:53:55.612122 Exit from PICG configuration <<<<
7212 22:53:55.615370 [RX_INPUT] configuration >>>>>
7213 22:53:55.618760 [RX_INPUT] configuration <<<<<
7214 22:53:55.625116 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7215 22:53:55.628695 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7216 22:53:55.634769 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7217 22:53:55.641299 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7218 22:53:55.647966 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7219 22:53:55.654690 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7220 22:53:55.658093 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7221 22:53:55.661093 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7222 22:53:55.664779 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7223 22:53:55.670957 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7224 22:53:55.674949 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7225 22:53:55.677752 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7226 22:53:55.680967 ===================================
7227 22:53:55.684808 LPDDR4 DRAM CONFIGURATION
7228 22:53:55.687759 ===================================
7229 22:53:55.690910 EX_ROW_EN[0] = 0x0
7230 22:53:55.690992 EX_ROW_EN[1] = 0x0
7231 22:53:55.694408 LP4Y_EN = 0x0
7232 22:53:55.694492 WORK_FSP = 0x1
7233 22:53:55.697480 WL = 0x5
7234 22:53:55.697585 RL = 0x5
7235 22:53:55.700691 BL = 0x2
7236 22:53:55.700771 RPST = 0x0
7237 22:53:55.704128 RD_PRE = 0x0
7238 22:53:55.704209 WR_PRE = 0x1
7239 22:53:55.707450 WR_PST = 0x1
7240 22:53:55.707530 DBI_WR = 0x0
7241 22:53:55.710766 DBI_RD = 0x0
7242 22:53:55.710846 OTF = 0x1
7243 22:53:55.714143 ===================================
7244 22:53:55.720660 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7245 22:53:55.723969 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7246 22:53:55.727225 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7247 22:53:55.730388 ===================================
7248 22:53:55.734359 LPDDR4 DRAM CONFIGURATION
7249 22:53:55.737192 ===================================
7250 22:53:55.740782 EX_ROW_EN[0] = 0x10
7251 22:53:55.740862 EX_ROW_EN[1] = 0x0
7252 22:53:55.743909 LP4Y_EN = 0x0
7253 22:53:55.743989 WORK_FSP = 0x1
7254 22:53:55.746760 WL = 0x5
7255 22:53:55.746840 RL = 0x5
7256 22:53:55.750403 BL = 0x2
7257 22:53:55.750483 RPST = 0x0
7258 22:53:55.753650 RD_PRE = 0x0
7259 22:53:55.753730 WR_PRE = 0x1
7260 22:53:55.756660 WR_PST = 0x1
7261 22:53:55.756741 DBI_WR = 0x0
7262 22:53:55.759962 DBI_RD = 0x0
7263 22:53:55.763639 OTF = 0x1
7264 22:53:55.766789 ===================================
7265 22:53:55.769706 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7266 22:53:55.769788 ==
7267 22:53:55.773035 Dram Type= 6, Freq= 0, CH_0, rank 0
7268 22:53:55.779633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7269 22:53:55.779719 ==
7270 22:53:55.783562 [Duty_Offset_Calibration]
7271 22:53:55.783644 B0:1 B1:-1 CA:0
7272 22:53:55.783708
7273 22:53:55.786593 [DutyScan_Calibration_Flow] k_type=0
7274 22:53:55.796132
7275 22:53:55.796230 ==CLK 0==
7276 22:53:55.799286 Final CLK duty delay cell = 0
7277 22:53:55.802799 [0] MAX Duty = 5125%(X100), DQS PI = 20
7278 22:53:55.806380 [0] MIN Duty = 4907%(X100), DQS PI = 4
7279 22:53:55.806463 [0] AVG Duty = 5016%(X100)
7280 22:53:55.809326
7281 22:53:55.812659 CH0 CLK Duty spec in!! Max-Min= 218%
7282 22:53:55.815825 [DutyScan_Calibration_Flow] ====Done====
7283 22:53:55.815907
7284 22:53:55.819379 [DutyScan_Calibration_Flow] k_type=1
7285 22:53:55.835121
7286 22:53:55.835236 ==DQS 0 ==
7287 22:53:55.838861 Final DQS duty delay cell = -4
7288 22:53:55.841986 [-4] MAX Duty = 5000%(X100), DQS PI = 36
7289 22:53:55.845415 [-4] MIN Duty = 4844%(X100), DQS PI = 58
7290 22:53:55.848448 [-4] AVG Duty = 4922%(X100)
7291 22:53:55.848530
7292 22:53:55.848593 ==DQS 1 ==
7293 22:53:55.851903 Final DQS duty delay cell = 0
7294 22:53:55.855026 [0] MAX Duty = 5156%(X100), DQS PI = 2
7295 22:53:55.858220 [0] MIN Duty = 5000%(X100), DQS PI = 20
7296 22:53:55.861665 [0] AVG Duty = 5078%(X100)
7297 22:53:55.861745
7298 22:53:55.864541 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7299 22:53:55.864622
7300 22:53:55.868334 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7301 22:53:55.871327 [DutyScan_Calibration_Flow] ====Done====
7302 22:53:55.871407
7303 22:53:55.874530 [DutyScan_Calibration_Flow] k_type=3
7304 22:53:55.892596
7305 22:53:55.892744 ==DQM 0 ==
7306 22:53:55.896260 Final DQM duty delay cell = 0
7307 22:53:55.899382 [0] MAX Duty = 5093%(X100), DQS PI = 20
7308 22:53:55.902917 [0] MIN Duty = 4876%(X100), DQS PI = 10
7309 22:53:55.905813 [0] AVG Duty = 4984%(X100)
7310 22:53:55.905893
7311 22:53:55.905956 ==DQM 1 ==
7312 22:53:55.909488 Final DQM duty delay cell = 0
7313 22:53:55.912823 [0] MAX Duty = 5000%(X100), DQS PI = 6
7314 22:53:55.916481 [0] MIN Duty = 4813%(X100), DQS PI = 20
7315 22:53:55.919131 [0] AVG Duty = 4906%(X100)
7316 22:53:55.919212
7317 22:53:55.922451 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7318 22:53:55.922531
7319 22:53:55.925871 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7320 22:53:55.929155 [DutyScan_Calibration_Flow] ====Done====
7321 22:53:55.929236
7322 22:53:55.932062 [DutyScan_Calibration_Flow] k_type=2
7323 22:53:55.949062
7324 22:53:55.949174 ==DQ 0 ==
7325 22:53:55.952094 Final DQ duty delay cell = -4
7326 22:53:55.955657 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7327 22:53:55.959119 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7328 22:53:55.962328 [-4] AVG Duty = 4953%(X100)
7329 22:53:55.962407
7330 22:53:55.962470 ==DQ 1 ==
7331 22:53:55.965793 Final DQ duty delay cell = 0
7332 22:53:55.968920 [0] MAX Duty = 5125%(X100), DQS PI = 2
7333 22:53:55.972296 [0] MIN Duty = 5000%(X100), DQS PI = 36
7334 22:53:55.975591 [0] AVG Duty = 5062%(X100)
7335 22:53:55.975670
7336 22:53:55.978453 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7337 22:53:55.978533
7338 22:53:55.981804 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7339 22:53:55.985487 [DutyScan_Calibration_Flow] ====Done====
7340 22:53:55.985565 ==
7341 22:53:55.988686 Dram Type= 6, Freq= 0, CH_1, rank 0
7342 22:53:55.992158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7343 22:53:55.992239 ==
7344 22:53:55.994791 [Duty_Offset_Calibration]
7345 22:53:55.994873 B0:-1 B1:1 CA:2
7346 22:53:55.998218
7347 22:53:56.001287 [DutyScan_Calibration_Flow] k_type=0
7348 22:53:56.009824
7349 22:53:56.009903 ==CLK 0==
7350 22:53:56.013349 Final CLK duty delay cell = 0
7351 22:53:56.016230 [0] MAX Duty = 5187%(X100), DQS PI = 22
7352 22:53:56.019858 [0] MIN Duty = 4969%(X100), DQS PI = 0
7353 22:53:56.019939 [0] AVG Duty = 5078%(X100)
7354 22:53:56.022953
7355 22:53:56.026321 CH1 CLK Duty spec in!! Max-Min= 218%
7356 22:53:56.029953 [DutyScan_Calibration_Flow] ====Done====
7357 22:53:56.030034
7358 22:53:56.032933 [DutyScan_Calibration_Flow] k_type=1
7359 22:53:56.049317
7360 22:53:56.049399 ==DQS 0 ==
7361 22:53:56.052844 Final DQS duty delay cell = 0
7362 22:53:56.055618 [0] MAX Duty = 5156%(X100), DQS PI = 20
7363 22:53:56.059596 [0] MIN Duty = 4907%(X100), DQS PI = 10
7364 22:53:56.062732 [0] AVG Duty = 5031%(X100)
7365 22:53:56.062813
7366 22:53:56.062877 ==DQS 1 ==
7367 22:53:56.065964 Final DQS duty delay cell = 0
7368 22:53:56.069312 [0] MAX Duty = 5093%(X100), DQS PI = 26
7369 22:53:56.072257 [0] MIN Duty = 4969%(X100), DQS PI = 54
7370 22:53:56.075882 [0] AVG Duty = 5031%(X100)
7371 22:53:56.075963
7372 22:53:56.078772 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7373 22:53:56.078853
7374 22:53:56.082330 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7375 22:53:56.085476 [DutyScan_Calibration_Flow] ====Done====
7376 22:53:56.085556
7377 22:53:56.088942 [DutyScan_Calibration_Flow] k_type=3
7378 22:53:56.106216
7379 22:53:56.106308 ==DQM 0 ==
7380 22:53:56.109795 Final DQM duty delay cell = 0
7381 22:53:56.112964 [0] MAX Duty = 5218%(X100), DQS PI = 36
7382 22:53:56.116261 [0] MIN Duty = 5000%(X100), DQS PI = 10
7383 22:53:56.119100 [0] AVG Duty = 5109%(X100)
7384 22:53:56.119180
7385 22:53:56.119243 ==DQM 1 ==
7386 22:53:56.122887 Final DQM duty delay cell = 0
7387 22:53:56.126014 [0] MAX Duty = 5156%(X100), DQS PI = 6
7388 22:53:56.129256 [0] MIN Duty = 4938%(X100), DQS PI = 34
7389 22:53:56.132621 [0] AVG Duty = 5047%(X100)
7390 22:53:56.132701
7391 22:53:56.135776 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7392 22:53:56.135856
7393 22:53:56.139294 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7394 22:53:56.142748 [DutyScan_Calibration_Flow] ====Done====
7395 22:53:56.142828
7396 22:53:56.145838 [DutyScan_Calibration_Flow] k_type=2
7397 22:53:56.163111
7398 22:53:56.163191 ==DQ 0 ==
7399 22:53:56.166470 Final DQ duty delay cell = 0
7400 22:53:56.169944 [0] MAX Duty = 5156%(X100), DQS PI = 28
7401 22:53:56.172956 [0] MIN Duty = 4906%(X100), DQS PI = 8
7402 22:53:56.173037 [0] AVG Duty = 5031%(X100)
7403 22:53:56.176131
7404 22:53:56.176210 ==DQ 1 ==
7405 22:53:56.180146 Final DQ duty delay cell = 0
7406 22:53:56.182489 [0] MAX Duty = 5156%(X100), DQS PI = 8
7407 22:53:56.185883 [0] MIN Duty = 4969%(X100), DQS PI = 56
7408 22:53:56.185963 [0] AVG Duty = 5062%(X100)
7409 22:53:56.189444
7410 22:53:56.192704 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7411 22:53:56.192786
7412 22:53:56.196218 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7413 22:53:56.199435 [DutyScan_Calibration_Flow] ====Done====
7414 22:53:56.202788 nWR fixed to 30
7415 22:53:56.202869 [ModeRegInit_LP4] CH0 RK0
7416 22:53:56.205807 [ModeRegInit_LP4] CH0 RK1
7417 22:53:56.209505 [ModeRegInit_LP4] CH1 RK0
7418 22:53:56.212314 [ModeRegInit_LP4] CH1 RK1
7419 22:53:56.212395 match AC timing 5
7420 22:53:56.219120 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7421 22:53:56.222270 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7422 22:53:56.225646 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7423 22:53:56.232462 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7424 22:53:56.235541 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7425 22:53:56.235622 [MiockJmeterHQA]
7426 22:53:56.235686
7427 22:53:56.239217 [DramcMiockJmeter] u1RxGatingPI = 0
7428 22:53:56.241930 0 : 4363, 4138
7429 22:53:56.242012 4 : 4252, 4027
7430 22:53:56.245289 8 : 4363, 4138
7431 22:53:56.245365 12 : 4250, 4026
7432 22:53:56.248970 16 : 4360, 4137
7433 22:53:56.249055 20 : 4253, 4026
7434 22:53:56.249121 24 : 4363, 4140
7435 22:53:56.252090 28 : 4253, 4026
7436 22:53:56.252173 32 : 4363, 4138
7437 22:53:56.255471 36 : 4252, 4027
7438 22:53:56.255553 40 : 4250, 4027
7439 22:53:56.258660 44 : 4255, 4030
7440 22:53:56.258741 48 : 4250, 4026
7441 22:53:56.262014 52 : 4252, 4027
7442 22:53:56.262097 56 : 4249, 4027
7443 22:53:56.262190 60 : 4250, 4026
7444 22:53:56.265397 64 : 4250, 4027
7445 22:53:56.265478 68 : 4363, 4140
7446 22:53:56.268539 72 : 4250, 4027
7447 22:53:56.268621 76 : 4252, 4029
7448 22:53:56.272012 80 : 4250, 4026
7449 22:53:56.272095 84 : 4360, 4138
7450 22:53:56.274940 88 : 4250, 4027
7451 22:53:56.275022 92 : 4250, 283
7452 22:53:56.275087 96 : 4363, 0
7453 22:53:56.278149 100 : 4250, 0
7454 22:53:56.278237 104 : 4253, 0
7455 22:53:56.278303 108 : 4360, 0
7456 22:53:56.281909 112 : 4360, 0
7457 22:53:56.281991 116 : 4250, 0
7458 22:53:56.285094 120 : 4250, 0
7459 22:53:56.285175 124 : 4250, 0
7460 22:53:56.285239 128 : 4250, 0
7461 22:53:56.288386 132 : 4250, 0
7462 22:53:56.288468 136 : 4250, 0
7463 22:53:56.291562 140 : 4252, 0
7464 22:53:56.291644 144 : 4250, 0
7465 22:53:56.291709 148 : 4360, 0
7466 22:53:56.294569 152 : 4250, 0
7467 22:53:56.294651 156 : 4361, 0
7468 22:53:56.298330 160 : 4360, 0
7469 22:53:56.298413 164 : 4250, 0
7470 22:53:56.298477 168 : 4252, 0
7471 22:53:56.301314 172 : 4250, 0
7472 22:53:56.301395 176 : 4250, 0
7473 22:53:56.304839 180 : 4361, 0
7474 22:53:56.304920 184 : 4250, 0
7475 22:53:56.304985 188 : 4249, 0
7476 22:53:56.308007 192 : 4250, 0
7477 22:53:56.308089 196 : 4250, 0
7478 22:53:56.308154 200 : 4250, 0
7479 22:53:56.311118 204 : 4249, 0
7480 22:53:56.311200 208 : 4361, 0
7481 22:53:56.314197 212 : 4250, 0
7482 22:53:56.314292 216 : 4360, 0
7483 22:53:56.314357 220 : 4250, 0
7484 22:53:56.317989 224 : 4250, 104
7485 22:53:56.318071 228 : 4250, 3275
7486 22:53:56.321035 232 : 4360, 4138
7487 22:53:56.321117 236 : 4361, 4137
7488 22:53:56.324177 240 : 4360, 4138
7489 22:53:56.324258 244 : 4250, 4027
7490 22:53:56.328001 248 : 4250, 4027
7491 22:53:56.328083 252 : 4250, 4027
7492 22:53:56.330933 256 : 4250, 4027
7493 22:53:56.331015 260 : 4361, 4137
7494 22:53:56.334090 264 : 4250, 4027
7495 22:53:56.334210 268 : 4250, 4027
7496 22:53:56.337452 272 : 4250, 4027
7497 22:53:56.337534 276 : 4253, 4029
7498 22:53:56.337599 280 : 4363, 4138
7499 22:53:56.340691 284 : 4250, 4027
7500 22:53:56.340773 288 : 4363, 4137
7501 22:53:56.344750 292 : 4250, 4027
7502 22:53:56.344832 296 : 4250, 4027
7503 22:53:56.347544 300 : 4250, 4027
7504 22:53:56.347648 304 : 4250, 4027
7505 22:53:56.350824 308 : 4250, 4026
7506 22:53:56.350906 312 : 4361, 4137
7507 22:53:56.353959 316 : 4250, 4027
7508 22:53:56.354040 320 : 4249, 4027
7509 22:53:56.357617 324 : 4250, 4026
7510 22:53:56.357699 328 : 4250, 4027
7511 22:53:56.360474 332 : 4360, 4138
7512 22:53:56.360554 336 : 4360, 3983
7513 22:53:56.364101 340 : 4363, 2124
7514 22:53:56.364183
7515 22:53:56.364245 MIOCK jitter meter ch=0
7516 22:53:56.364305
7517 22:53:56.367122 1T = (340-92) = 248 dly cells
7518 22:53:56.373614 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7519 22:53:56.373695 ==
7520 22:53:56.376827 Dram Type= 6, Freq= 0, CH_0, rank 0
7521 22:53:56.380383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7522 22:53:56.380463 ==
7523 22:53:56.386798 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7524 22:53:56.390293 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7525 22:53:56.396891 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7526 22:53:56.399948 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7527 22:53:56.410031 [CA 0] Center 43 (13~74) winsize 62
7528 22:53:56.413381 [CA 1] Center 42 (12~73) winsize 62
7529 22:53:56.416464 [CA 2] Center 38 (9~68) winsize 60
7530 22:53:56.419682 [CA 3] Center 38 (9~68) winsize 60
7531 22:53:56.423674 [CA 4] Center 36 (7~66) winsize 60
7532 22:53:56.426288 [CA 5] Center 35 (6~65) winsize 60
7533 22:53:56.426368
7534 22:53:56.429965 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7535 22:53:56.430120
7536 22:53:56.436433 [CATrainingPosCal] consider 1 rank data
7537 22:53:56.436514 u2DelayCellTimex100 = 262/100 ps
7538 22:53:56.442888 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7539 22:53:56.446469 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7540 22:53:56.449341 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7541 22:53:56.452605 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7542 22:53:56.456649 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7543 22:53:56.459811 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7544 22:53:56.459892
7545 22:53:56.462649 CA PerBit enable=1, Macro0, CA PI delay=35
7546 22:53:56.462734
7547 22:53:56.466369 [CBTSetCACLKResult] CA Dly = 35
7548 22:53:56.469226 CS Dly: 12 (0~43)
7549 22:53:56.472864 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7550 22:53:56.475942 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7551 22:53:56.476029 ==
7552 22:53:56.478909 Dram Type= 6, Freq= 0, CH_0, rank 1
7553 22:53:56.485983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7554 22:53:56.486098 ==
7555 22:53:56.488750 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7556 22:53:56.495621 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7557 22:53:56.498734 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7558 22:53:56.505360 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7559 22:53:56.513298 [CA 0] Center 42 (12~73) winsize 62
7560 22:53:56.516496 [CA 1] Center 43 (13~73) winsize 61
7561 22:53:56.520240 [CA 2] Center 37 (8~67) winsize 60
7562 22:53:56.523117 [CA 3] Center 37 (7~67) winsize 61
7563 22:53:56.526942 [CA 4] Center 36 (6~66) winsize 61
7564 22:53:56.530008 [CA 5] Center 35 (5~65) winsize 61
7565 22:53:56.530089
7566 22:53:56.533702 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7567 22:53:56.533784
7568 22:53:56.537230 [CATrainingPosCal] consider 2 rank data
7569 22:53:56.540060 u2DelayCellTimex100 = 262/100 ps
7570 22:53:56.546549 CA0 delay=43 (13~73),Diff = 8 PI (29 cell)
7571 22:53:56.549773 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7572 22:53:56.553088 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7573 22:53:56.556671 CA3 delay=38 (9~67),Diff = 3 PI (11 cell)
7574 22:53:56.559983 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7575 22:53:56.563339 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7576 22:53:56.563535
7577 22:53:56.566296 CA PerBit enable=1, Macro0, CA PI delay=35
7578 22:53:56.566511
7579 22:53:56.569905 [CBTSetCACLKResult] CA Dly = 35
7580 22:53:56.572893 CS Dly: 12 (0~43)
7581 22:53:56.576753 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7582 22:53:56.580191 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7583 22:53:56.580482
7584 22:53:56.583182 ----->DramcWriteLeveling(PI) begin...
7585 22:53:56.583466 ==
7586 22:53:56.586178 Dram Type= 6, Freq= 0, CH_0, rank 0
7587 22:53:56.593064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7588 22:53:56.593367 ==
7589 22:53:56.596230 Write leveling (Byte 0): 37 => 37
7590 22:53:56.599480 Write leveling (Byte 1): 27 => 27
7591 22:53:56.599865 DramcWriteLeveling(PI) end<-----
7592 22:53:56.603213
7593 22:53:56.603482 ==
7594 22:53:56.605946 Dram Type= 6, Freq= 0, CH_0, rank 0
7595 22:53:56.609655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7596 22:53:56.609828 ==
7597 22:53:56.613136 [Gating] SW mode calibration
7598 22:53:56.619129 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7599 22:53:56.622832 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7600 22:53:56.629604 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 22:53:56.632288 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 22:53:56.635798 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 22:53:56.642360 1 4 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
7604 22:53:56.645439 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7605 22:53:56.648944 1 4 20 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7606 22:53:56.655277 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7607 22:53:56.658677 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7608 22:53:56.664990 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7609 22:53:56.668264 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7610 22:53:56.672013 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 22:53:56.678425 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
7612 22:53:56.682202 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7613 22:53:56.685046 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7614 22:53:56.691674 1 5 24 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
7615 22:53:56.694974 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 22:53:56.698018 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 22:53:56.704695 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 22:53:56.708151 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 22:53:56.711362 1 6 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7620 22:53:56.718174 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7621 22:53:56.721246 1 6 20 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7622 22:53:56.724596 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7623 22:53:56.730968 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 22:53:56.734525 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 22:53:56.737351 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 22:53:56.744551 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 22:53:56.747823 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7628 22:53:56.750805 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7629 22:53:56.757430 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7630 22:53:56.760945 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7631 22:53:56.763676 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 22:53:56.770416 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 22:53:56.773750 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 22:53:56.776889 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 22:53:56.783261 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 22:53:56.787095 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 22:53:56.789781 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 22:53:56.796730 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 22:53:56.799725 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 22:53:56.803326 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 22:53:56.809720 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 22:53:56.813267 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7643 22:53:56.816429 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7644 22:53:56.822742 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7645 22:53:56.822824 Total UI for P1: 0, mck2ui 16
7646 22:53:56.829415 best dqsien dly found for B0: ( 1, 9, 10)
7647 22:53:56.833003 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7648 22:53:56.836183 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 22:53:56.839647 Total UI for P1: 0, mck2ui 16
7650 22:53:56.842918 best dqsien dly found for B1: ( 1, 9, 20)
7651 22:53:56.846042 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7652 22:53:56.849471 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7653 22:53:56.849552
7654 22:53:56.856477 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7655 22:53:56.859473 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7656 22:53:56.862472 [Gating] SW calibration Done
7657 22:53:56.862553 ==
7658 22:53:56.865682 Dram Type= 6, Freq= 0, CH_0, rank 0
7659 22:53:56.869100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7660 22:53:56.869182 ==
7661 22:53:56.869246 RX Vref Scan: 0
7662 22:53:56.869307
7663 22:53:56.872991 RX Vref 0 -> 0, step: 1
7664 22:53:56.873072
7665 22:53:56.875695 RX Delay 0 -> 252, step: 8
7666 22:53:56.879246 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7667 22:53:56.882759 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7668 22:53:56.886007 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7669 22:53:56.892695 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7670 22:53:56.895533 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7671 22:53:56.899163 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7672 22:53:56.902025 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7673 22:53:56.909032 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7674 22:53:56.912527 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7675 22:53:56.915265 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7676 22:53:56.918603 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7677 22:53:56.922137 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7678 22:53:56.928575 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7679 22:53:56.931706 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7680 22:53:56.935197 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7681 22:53:56.938172 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7682 22:53:56.938267 ==
7683 22:53:56.941879 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 22:53:56.948112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 22:53:56.948199 ==
7686 22:53:56.948265 DQS Delay:
7687 22:53:56.951279 DQS0 = 0, DQS1 = 0
7688 22:53:56.951360 DQM Delay:
7689 22:53:56.954454 DQM0 = 135, DQM1 = 126
7690 22:53:56.954535 DQ Delay:
7691 22:53:56.957700 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7692 22:53:56.961461 DQ4 =135, DQ5 =123, DQ6 =143, DQ7 =147
7693 22:53:56.964456 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7694 22:53:56.967802 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7695 22:53:56.967883
7696 22:53:56.967947
7697 22:53:56.968006 ==
7698 22:53:56.971639 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 22:53:56.977948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 22:53:56.978032 ==
7701 22:53:56.978129
7702 22:53:56.978245
7703 22:53:56.978304 TX Vref Scan disable
7704 22:53:56.981232 == TX Byte 0 ==
7705 22:53:56.984939 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7706 22:53:56.991091 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7707 22:53:56.991171 == TX Byte 1 ==
7708 22:53:56.994485 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7709 22:53:57.001274 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7710 22:53:57.001356 ==
7711 22:53:57.004792 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 22:53:57.007895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 22:53:57.007977 ==
7714 22:53:57.021241
7715 22:53:57.024563 TX Vref early break, caculate TX vref
7716 22:53:57.027670 TX Vref=16, minBit 6, minWin=22, winSum=369
7717 22:53:57.030810 TX Vref=18, minBit 14, minWin=22, winSum=380
7718 22:53:57.034380 TX Vref=20, minBit 1, minWin=23, winSum=392
7719 22:53:57.037389 TX Vref=22, minBit 1, minWin=24, winSum=404
7720 22:53:57.040893 TX Vref=24, minBit 0, minWin=25, winSum=409
7721 22:53:57.048070 TX Vref=26, minBit 1, minWin=25, winSum=417
7722 22:53:57.050923 TX Vref=28, minBit 0, minWin=25, winSum=419
7723 22:53:57.053747 TX Vref=30, minBit 0, minWin=25, winSum=413
7724 22:53:57.057908 TX Vref=32, minBit 0, minWin=24, winSum=403
7725 22:53:57.060653 TX Vref=34, minBit 5, minWin=23, winSum=390
7726 22:53:57.066926 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
7727 22:53:57.067109
7728 22:53:57.070897 Final TX Range 0 Vref 28
7729 22:53:57.071080
7730 22:53:57.071192 ==
7731 22:53:57.073514 Dram Type= 6, Freq= 0, CH_0, rank 0
7732 22:53:57.076836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7733 22:53:57.077032 ==
7734 22:53:57.077133
7735 22:53:57.077228
7736 22:53:57.080263 TX Vref Scan disable
7737 22:53:57.086643 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7738 22:53:57.086784 == TX Byte 0 ==
7739 22:53:57.090113 u2DelayCellOfst[0]=14 cells (4 PI)
7740 22:53:57.093392 u2DelayCellOfst[1]=18 cells (5 PI)
7741 22:53:57.096567 u2DelayCellOfst[2]=14 cells (4 PI)
7742 22:53:57.100430 u2DelayCellOfst[3]=14 cells (4 PI)
7743 22:53:57.104006 u2DelayCellOfst[4]=11 cells (3 PI)
7744 22:53:57.107053 u2DelayCellOfst[5]=0 cells (0 PI)
7745 22:53:57.110305 u2DelayCellOfst[6]=22 cells (6 PI)
7746 22:53:57.113547 u2DelayCellOfst[7]=22 cells (6 PI)
7747 22:53:57.117019 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7748 22:53:57.120058 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7749 22:53:57.123272 == TX Byte 1 ==
7750 22:53:57.126547 u2DelayCellOfst[8]=0 cells (0 PI)
7751 22:53:57.129910 u2DelayCellOfst[9]=3 cells (1 PI)
7752 22:53:57.132825 u2DelayCellOfst[10]=7 cells (2 PI)
7753 22:53:57.136581 u2DelayCellOfst[11]=0 cells (0 PI)
7754 22:53:57.139768 u2DelayCellOfst[12]=11 cells (3 PI)
7755 22:53:57.143009 u2DelayCellOfst[13]=11 cells (3 PI)
7756 22:53:57.146585 u2DelayCellOfst[14]=14 cells (4 PI)
7757 22:53:57.146728 u2DelayCellOfst[15]=11 cells (3 PI)
7758 22:53:57.152769 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7759 22:53:57.156184 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7760 22:53:57.159309 DramC Write-DBI on
7761 22:53:57.159436 ==
7762 22:53:57.162981 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 22:53:57.166029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 22:53:57.166136 ==
7765 22:53:57.166228
7766 22:53:57.166299
7767 22:53:57.169866 TX Vref Scan disable
7768 22:53:57.169964 == TX Byte 0 ==
7769 22:53:57.175836 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7770 22:53:57.175923 == TX Byte 1 ==
7771 22:53:57.182644 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7772 22:53:57.182746 DramC Write-DBI off
7773 22:53:57.182811
7774 22:53:57.182869 [DATLAT]
7775 22:53:57.185723 Freq=1600, CH0 RK0
7776 22:53:57.185805
7777 22:53:57.189061 DATLAT Default: 0xf
7778 22:53:57.189143 0, 0xFFFF, sum = 0
7779 22:53:57.192777 1, 0xFFFF, sum = 0
7780 22:53:57.192859 2, 0xFFFF, sum = 0
7781 22:53:57.195618 3, 0xFFFF, sum = 0
7782 22:53:57.195705 4, 0xFFFF, sum = 0
7783 22:53:57.198653 5, 0xFFFF, sum = 0
7784 22:53:57.198737 6, 0xFFFF, sum = 0
7785 22:53:57.202408 7, 0xFFFF, sum = 0
7786 22:53:57.202497 8, 0xFFFF, sum = 0
7787 22:53:57.205495 9, 0xFFFF, sum = 0
7788 22:53:57.205578 10, 0xFFFF, sum = 0
7789 22:53:57.208341 11, 0xFFFF, sum = 0
7790 22:53:57.208423 12, 0xFFFF, sum = 0
7791 22:53:57.212278 13, 0xFFFF, sum = 0
7792 22:53:57.212361 14, 0x0, sum = 1
7793 22:53:57.215102 15, 0x0, sum = 2
7794 22:53:57.215185 16, 0x0, sum = 3
7795 22:53:57.218788 17, 0x0, sum = 4
7796 22:53:57.218871 best_step = 15
7797 22:53:57.218936
7798 22:53:57.218995 ==
7799 22:53:57.221855 Dram Type= 6, Freq= 0, CH_0, rank 0
7800 22:53:57.228235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7801 22:53:57.228335 ==
7802 22:53:57.228399 RX Vref Scan: 1
7803 22:53:57.228458
7804 22:53:57.231936 Set Vref Range= 24 -> 127
7805 22:53:57.232020
7806 22:53:57.234976 RX Vref 24 -> 127, step: 1
7807 22:53:57.235059
7808 22:53:57.238446 RX Delay 19 -> 252, step: 4
7809 22:53:57.238533
7810 22:53:57.241580 Set Vref, RX VrefLevel [Byte0]: 24
7811 22:53:57.244810 [Byte1]: 24
7812 22:53:57.244894
7813 22:53:57.248355 Set Vref, RX VrefLevel [Byte0]: 25
7814 22:53:57.251305 [Byte1]: 25
7815 22:53:57.251398
7816 22:53:57.255245 Set Vref, RX VrefLevel [Byte0]: 26
7817 22:53:57.258092 [Byte1]: 26
7818 22:53:57.258191
7819 22:53:57.261467 Set Vref, RX VrefLevel [Byte0]: 27
7820 22:53:57.264823 [Byte1]: 27
7821 22:53:57.269206
7822 22:53:57.269299 Set Vref, RX VrefLevel [Byte0]: 28
7823 22:53:57.272018 [Byte1]: 28
7824 22:53:57.276259
7825 22:53:57.276377 Set Vref, RX VrefLevel [Byte0]: 29
7826 22:53:57.279649 [Byte1]: 29
7827 22:53:57.283786
7828 22:53:57.283872 Set Vref, RX VrefLevel [Byte0]: 30
7829 22:53:57.287413 [Byte1]: 30
7830 22:53:57.291505
7831 22:53:57.291596 Set Vref, RX VrefLevel [Byte0]: 31
7832 22:53:57.294591 [Byte1]: 31
7833 22:53:57.299138
7834 22:53:57.299303 Set Vref, RX VrefLevel [Byte0]: 32
7835 22:53:57.302574 [Byte1]: 32
7836 22:53:57.306480
7837 22:53:57.306622 Set Vref, RX VrefLevel [Byte0]: 33
7838 22:53:57.310153 [Byte1]: 33
7839 22:53:57.314822
7840 22:53:57.314981 Set Vref, RX VrefLevel [Byte0]: 34
7841 22:53:57.317740 [Byte1]: 34
7842 22:53:57.321799
7843 22:53:57.321969 Set Vref, RX VrefLevel [Byte0]: 35
7844 22:53:57.325164 [Byte1]: 35
7845 22:53:57.329693
7846 22:53:57.329812 Set Vref, RX VrefLevel [Byte0]: 36
7847 22:53:57.333467 [Byte1]: 36
7848 22:53:57.336952
7849 22:53:57.337125 Set Vref, RX VrefLevel [Byte0]: 37
7850 22:53:57.339954 [Byte1]: 37
7851 22:53:57.344337
7852 22:53:57.344507 Set Vref, RX VrefLevel [Byte0]: 38
7853 22:53:57.347641 [Byte1]: 38
7854 22:53:57.352298
7855 22:53:57.352535 Set Vref, RX VrefLevel [Byte0]: 39
7856 22:53:57.355729 [Byte1]: 39
7857 22:53:57.359673
7858 22:53:57.359966 Set Vref, RX VrefLevel [Byte0]: 40
7859 22:53:57.363137 [Byte1]: 40
7860 22:53:57.367412
7861 22:53:57.367790 Set Vref, RX VrefLevel [Byte0]: 41
7862 22:53:57.370968 [Byte1]: 41
7863 22:53:57.375265
7864 22:53:57.375644 Set Vref, RX VrefLevel [Byte0]: 42
7865 22:53:57.378299 [Byte1]: 42
7866 22:53:57.382727
7867 22:53:57.383346 Set Vref, RX VrefLevel [Byte0]: 43
7868 22:53:57.386141 [Byte1]: 43
7869 22:53:57.390863
7870 22:53:57.391355 Set Vref, RX VrefLevel [Byte0]: 44
7871 22:53:57.393715 [Byte1]: 44
7872 22:53:57.397970
7873 22:53:57.398440 Set Vref, RX VrefLevel [Byte0]: 45
7874 22:53:57.400714 [Byte1]: 45
7875 22:53:57.405559
7876 22:53:57.406097 Set Vref, RX VrefLevel [Byte0]: 46
7877 22:53:57.408815 [Byte1]: 46
7878 22:53:57.413227
7879 22:53:57.413662 Set Vref, RX VrefLevel [Byte0]: 47
7880 22:53:57.416836 [Byte1]: 47
7881 22:53:57.420577
7882 22:53:57.421009 Set Vref, RX VrefLevel [Byte0]: 48
7883 22:53:57.423627 [Byte1]: 48
7884 22:53:57.427898
7885 22:53:57.428334 Set Vref, RX VrefLevel [Byte0]: 49
7886 22:53:57.431277 [Byte1]: 49
7887 22:53:57.435610
7888 22:53:57.436051 Set Vref, RX VrefLevel [Byte0]: 50
7889 22:53:57.439277 [Byte1]: 50
7890 22:53:57.443378
7891 22:53:57.443703 Set Vref, RX VrefLevel [Byte0]: 51
7892 22:53:57.446347 [Byte1]: 51
7893 22:53:57.450728
7894 22:53:57.450943 Set Vref, RX VrefLevel [Byte0]: 52
7895 22:53:57.453763 [Byte1]: 52
7896 22:53:57.458233
7897 22:53:57.458419 Set Vref, RX VrefLevel [Byte0]: 53
7898 22:53:57.461345 [Byte1]: 53
7899 22:53:57.465670
7900 22:53:57.465821 Set Vref, RX VrefLevel [Byte0]: 54
7901 22:53:57.469061 [Byte1]: 54
7902 22:53:57.473055
7903 22:53:57.473202 Set Vref, RX VrefLevel [Byte0]: 55
7904 22:53:57.476598 [Byte1]: 55
7905 22:53:57.480946
7906 22:53:57.481071 Set Vref, RX VrefLevel [Byte0]: 56
7907 22:53:57.483958 [Byte1]: 56
7908 22:53:57.488611
7909 22:53:57.488758 Set Vref, RX VrefLevel [Byte0]: 57
7910 22:53:57.491662 [Byte1]: 57
7911 22:53:57.495867
7912 22:53:57.496041 Set Vref, RX VrefLevel [Byte0]: 58
7913 22:53:57.498858 [Byte1]: 58
7914 22:53:57.503465
7915 22:53:57.503603 Set Vref, RX VrefLevel [Byte0]: 59
7916 22:53:57.506901 [Byte1]: 59
7917 22:53:57.511633
7918 22:53:57.512124 Set Vref, RX VrefLevel [Byte0]: 60
7919 22:53:57.514633 [Byte1]: 60
7920 22:53:57.519473
7921 22:53:57.519973 Set Vref, RX VrefLevel [Byte0]: 61
7922 22:53:57.522227 [Byte1]: 61
7923 22:53:57.526656
7924 22:53:57.527061 Set Vref, RX VrefLevel [Byte0]: 62
7925 22:53:57.529873 [Byte1]: 62
7926 22:53:57.534072
7927 22:53:57.534525 Set Vref, RX VrefLevel [Byte0]: 63
7928 22:53:57.537358 [Byte1]: 63
7929 22:53:57.541655
7930 22:53:57.542428 Set Vref, RX VrefLevel [Byte0]: 64
7931 22:53:57.545018 [Byte1]: 64
7932 22:53:57.549653
7933 22:53:57.550060 Set Vref, RX VrefLevel [Byte0]: 65
7934 22:53:57.552723 [Byte1]: 65
7935 22:53:57.556950
7936 22:53:57.557353 Set Vref, RX VrefLevel [Byte0]: 66
7937 22:53:57.559862 [Byte1]: 66
7938 22:53:57.564238
7939 22:53:57.567415 Set Vref, RX VrefLevel [Byte0]: 67
7940 22:53:57.570753 [Byte1]: 67
7941 22:53:57.571173
7942 22:53:57.574087 Set Vref, RX VrefLevel [Byte0]: 68
7943 22:53:57.577168 [Byte1]: 68
7944 22:53:57.577591
7945 22:53:57.581049 Set Vref, RX VrefLevel [Byte0]: 69
7946 22:53:57.584217 [Byte1]: 69
7947 22:53:57.586840
7948 22:53:57.587136 Set Vref, RX VrefLevel [Byte0]: 70
7949 22:53:57.589977 [Byte1]: 70
7950 22:53:57.594746
7951 22:53:57.594981 Set Vref, RX VrefLevel [Byte0]: 71
7952 22:53:57.597945 [Byte1]: 71
7953 22:53:57.601837
7954 22:53:57.601985 Set Vref, RX VrefLevel [Byte0]: 72
7955 22:53:57.605467 [Byte1]: 72
7956 22:53:57.609603
7957 22:53:57.609760 Set Vref, RX VrefLevel [Byte0]: 73
7958 22:53:57.612771 [Byte1]: 73
7959 22:53:57.617262
7960 22:53:57.617366 Set Vref, RX VrefLevel [Byte0]: 74
7961 22:53:57.620537 [Byte1]: 74
7962 22:53:57.624610
7963 22:53:57.624710 Set Vref, RX VrefLevel [Byte0]: 75
7964 22:53:57.627915 [Byte1]: 75
7965 22:53:57.632015
7966 22:53:57.632099 Set Vref, RX VrefLevel [Byte0]: 76
7967 22:53:57.635337 [Byte1]: 76
7968 22:53:57.639825
7969 22:53:57.639920 Set Vref, RX VrefLevel [Byte0]: 77
7970 22:53:57.643051 [Byte1]: 77
7971 22:53:57.647215
7972 22:53:57.647298 Set Vref, RX VrefLevel [Byte0]: 78
7973 22:53:57.650705 [Byte1]: 78
7974 22:53:57.654900
7975 22:53:57.654985 Final RX Vref Byte 0 = 63 to rank0
7976 22:53:57.658459 Final RX Vref Byte 1 = 56 to rank0
7977 22:53:57.661964 Final RX Vref Byte 0 = 63 to rank1
7978 22:53:57.664768 Final RX Vref Byte 1 = 56 to rank1==
7979 22:53:57.668348 Dram Type= 6, Freq= 0, CH_0, rank 0
7980 22:53:57.674559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7981 22:53:57.674647 ==
7982 22:53:57.674710 DQS Delay:
7983 22:53:57.677727 DQS0 = 0, DQS1 = 0
7984 22:53:57.677807 DQM Delay:
7985 22:53:57.677870 DQM0 = 133, DQM1 = 122
7986 22:53:57.681124 DQ Delay:
7987 22:53:57.684718 DQ0 =130, DQ1 =134, DQ2 =130, DQ3 =132
7988 22:53:57.687652 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
7989 22:53:57.691146 DQ8 =114, DQ9 =110, DQ10 =122, DQ11 =118
7990 22:53:57.694415 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =130
7991 22:53:57.694499
7992 22:53:57.694562
7993 22:53:57.694619
7994 22:53:57.697712 [DramC_TX_OE_Calibration] TA2
7995 22:53:57.700897 Original DQ_B0 (3 6) =30, OEN = 27
7996 22:53:57.704670 Original DQ_B1 (3 6) =30, OEN = 27
7997 22:53:57.707704 24, 0x0, End_B0=24 End_B1=24
7998 22:53:57.710568 25, 0x0, End_B0=25 End_B1=25
7999 22:53:57.710662 26, 0x0, End_B0=26 End_B1=26
8000 22:53:57.713877 27, 0x0, End_B0=27 End_B1=27
8001 22:53:57.717500 28, 0x0, End_B0=28 End_B1=28
8002 22:53:57.720690 29, 0x0, End_B0=29 End_B1=29
8003 22:53:57.720777 30, 0x0, End_B0=30 End_B1=30
8004 22:53:57.723973 31, 0x4141, End_B0=30 End_B1=30
8005 22:53:57.727509 Byte0 end_step=30 best_step=27
8006 22:53:57.730515 Byte1 end_step=30 best_step=27
8007 22:53:57.733828 Byte0 TX OE(2T, 0.5T) = (3, 3)
8008 22:53:57.737189 Byte1 TX OE(2T, 0.5T) = (3, 3)
8009 22:53:57.737268
8010 22:53:57.737331
8011 22:53:57.743975 [DQSOSCAuto] RK0, (LSB)MR18= 0x2112, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8012 22:53:57.747109 CH0 RK0: MR19=303, MR18=2112
8013 22:53:57.753754 CH0_RK0: MR19=0x303, MR18=0x2112, DQSOSC=393, MR23=63, INC=23, DEC=15
8014 22:53:57.753897
8015 22:53:57.757040 ----->DramcWriteLeveling(PI) begin...
8016 22:53:57.757200 ==
8017 22:53:57.760307 Dram Type= 6, Freq= 0, CH_0, rank 1
8018 22:53:57.763391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8019 22:53:57.766630 ==
8020 22:53:57.766720 Write leveling (Byte 0): 36 => 36
8021 22:53:57.770019 Write leveling (Byte 1): 27 => 27
8022 22:53:57.773634 DramcWriteLeveling(PI) end<-----
8023 22:53:57.773813
8024 22:53:57.773928 ==
8025 22:53:57.776820 Dram Type= 6, Freq= 0, CH_0, rank 1
8026 22:53:57.783264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8027 22:53:57.783435 ==
8028 22:53:57.783529 [Gating] SW mode calibration
8029 22:53:57.792961 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8030 22:53:57.796210 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8031 22:53:57.802842 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 22:53:57.806038 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8033 22:53:57.809958 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 22:53:57.816313 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8035 22:53:57.819202 1 4 16 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
8036 22:53:57.822912 1 4 20 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
8037 22:53:57.829795 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8038 22:53:57.832902 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8039 22:53:57.835877 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8040 22:53:57.842915 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8041 22:53:57.846201 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8042 22:53:57.849142 1 5 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
8043 22:53:57.855667 1 5 16 | B1->B0 | 3434 2424 | 0 0 | (0 1) (0 0)
8044 22:53:57.859426 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
8045 22:53:57.863040 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 22:53:57.869433 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 22:53:57.872193 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8048 22:53:57.875706 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 22:53:57.882284 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 22:53:57.885615 1 6 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8051 22:53:57.889079 1 6 16 | B1->B0 | 2626 4545 | 0 0 | (0 0) (0 0)
8052 22:53:57.895577 1 6 20 | B1->B0 | 4342 4646 | 1 0 | (0 0) (0 0)
8053 22:53:57.898847 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 22:53:57.901725 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 22:53:57.908295 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 22:53:57.912034 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 22:53:57.915000 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 22:53:57.921943 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8059 22:53:57.924944 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8060 22:53:57.928497 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8061 22:53:57.935013 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 22:53:57.938453 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 22:53:57.941901 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 22:53:57.948152 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 22:53:57.951696 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 22:53:57.954607 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 22:53:57.961509 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 22:53:57.964529 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 22:53:57.967860 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 22:53:57.974513 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 22:53:57.977887 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 22:53:57.981233 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 22:53:57.987424 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8074 22:53:57.990912 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8075 22:53:57.994424 Total UI for P1: 0, mck2ui 16
8076 22:53:57.997816 best dqsien dly found for B0: ( 1, 9, 8)
8077 22:53:58.000728 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8078 22:53:58.007844 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8079 22:53:58.010800 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 22:53:58.014391 Total UI for P1: 0, mck2ui 16
8081 22:53:58.017542 best dqsien dly found for B1: ( 1, 9, 16)
8082 22:53:58.020853 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8083 22:53:58.023815 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8084 22:53:58.024232
8085 22:53:58.028242 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8086 22:53:58.030554 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8087 22:53:58.033824 [Gating] SW calibration Done
8088 22:53:58.034448 ==
8089 22:53:58.037599 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 22:53:58.040575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 22:53:58.043533 ==
8092 22:53:58.043950 RX Vref Scan: 0
8093 22:53:58.044273
8094 22:53:58.046931 RX Vref 0 -> 0, step: 1
8095 22:53:58.047341
8096 22:53:58.047666 RX Delay 0 -> 252, step: 8
8097 22:53:58.053529 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8098 22:53:58.057399 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8099 22:53:58.060502 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8100 22:53:58.064044 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8101 22:53:58.067361 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8102 22:53:58.073677 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8103 22:53:58.077521 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8104 22:53:58.080142 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8105 22:53:58.084070 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8106 22:53:58.087059 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8107 22:53:58.093930 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8108 22:53:58.096659 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8109 22:53:58.100014 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8110 22:53:58.103027 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8111 22:53:58.109715 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8112 22:53:58.113257 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8113 22:53:58.113775 ==
8114 22:53:58.117033 Dram Type= 6, Freq= 0, CH_0, rank 1
8115 22:53:58.119871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8116 22:53:58.120440 ==
8117 22:53:58.123248 DQS Delay:
8118 22:53:58.123661 DQS0 = 0, DQS1 = 0
8119 22:53:58.124024 DQM Delay:
8120 22:53:58.126598 DQM0 = 132, DQM1 = 129
8121 22:53:58.127015 DQ Delay:
8122 22:53:58.129759 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8123 22:53:58.132879 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8124 22:53:58.139675 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8125 22:53:58.142920 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
8126 22:53:58.143436
8127 22:53:58.143762
8128 22:53:58.144065 ==
8129 22:53:58.146599 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 22:53:58.149509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 22:53:58.149942 ==
8132 22:53:58.150314
8133 22:53:58.150624
8134 22:53:58.152434 TX Vref Scan disable
8135 22:53:58.155952 == TX Byte 0 ==
8136 22:53:58.159656 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8137 22:53:58.162938 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8138 22:53:58.166015 == TX Byte 1 ==
8139 22:53:58.169097 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8140 22:53:58.172371 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8141 22:53:58.172790 ==
8142 22:53:58.175791 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 22:53:58.179038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 22:53:58.182761 ==
8145 22:53:58.193713
8146 22:53:58.196761 TX Vref early break, caculate TX vref
8147 22:53:58.200355 TX Vref=16, minBit 1, minWin=22, winSum=379
8148 22:53:58.203342 TX Vref=18, minBit 1, minWin=23, winSum=385
8149 22:53:58.206326 TX Vref=20, minBit 0, minWin=23, winSum=393
8150 22:53:58.209901 TX Vref=22, minBit 0, minWin=24, winSum=398
8151 22:53:58.213443 TX Vref=24, minBit 1, minWin=24, winSum=402
8152 22:53:58.219657 TX Vref=26, minBit 1, minWin=25, winSum=415
8153 22:53:58.223227 TX Vref=28, minBit 0, minWin=24, winSum=411
8154 22:53:58.226225 TX Vref=30, minBit 0, minWin=24, winSum=405
8155 22:53:58.229681 TX Vref=32, minBit 1, minWin=23, winSum=392
8156 22:53:58.236038 [TxChooseVref] Worse bit 1, Min win 25, Win sum 415, Final Vref 26
8157 22:53:58.236466
8158 22:53:58.239076 Final TX Range 0 Vref 26
8159 22:53:58.239488
8160 22:53:58.239815 ==
8161 22:53:58.242715 Dram Type= 6, Freq= 0, CH_0, rank 1
8162 22:53:58.246024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8163 22:53:58.246602 ==
8164 22:53:58.246935
8165 22:53:58.247241
8166 22:53:58.249343 TX Vref Scan disable
8167 22:53:58.255968 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8168 22:53:58.256387 == TX Byte 0 ==
8169 22:53:58.259650 u2DelayCellOfst[0]=14 cells (4 PI)
8170 22:53:58.262148 u2DelayCellOfst[1]=18 cells (5 PI)
8171 22:53:58.265896 u2DelayCellOfst[2]=14 cells (4 PI)
8172 22:53:58.268917 u2DelayCellOfst[3]=18 cells (5 PI)
8173 22:53:58.272261 u2DelayCellOfst[4]=11 cells (3 PI)
8174 22:53:58.275223 u2DelayCellOfst[5]=0 cells (0 PI)
8175 22:53:58.278583 u2DelayCellOfst[6]=18 cells (5 PI)
8176 22:53:58.282637 u2DelayCellOfst[7]=18 cells (5 PI)
8177 22:53:58.285348 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8178 22:53:58.288781 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8179 22:53:58.291891 == TX Byte 1 ==
8180 22:53:58.295426 u2DelayCellOfst[8]=0 cells (0 PI)
8181 22:53:58.295841 u2DelayCellOfst[9]=3 cells (1 PI)
8182 22:53:58.298461 u2DelayCellOfst[10]=7 cells (2 PI)
8183 22:53:58.301898 u2DelayCellOfst[11]=3 cells (1 PI)
8184 22:53:58.305483 u2DelayCellOfst[12]=11 cells (3 PI)
8185 22:53:58.308367 u2DelayCellOfst[13]=11 cells (3 PI)
8186 22:53:58.311847 u2DelayCellOfst[14]=18 cells (5 PI)
8187 22:53:58.315285 u2DelayCellOfst[15]=11 cells (3 PI)
8188 22:53:58.318368 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8189 22:53:58.325009 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8190 22:53:58.325423 DramC Write-DBI on
8191 22:53:58.325749 ==
8192 22:53:58.328346 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 22:53:58.335378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 22:53:58.335893 ==
8195 22:53:58.336226
8196 22:53:58.336530
8197 22:53:58.336820 TX Vref Scan disable
8198 22:53:58.339179 == TX Byte 0 ==
8199 22:53:58.342417 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8200 22:53:58.345716 == TX Byte 1 ==
8201 22:53:58.349444 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8202 22:53:58.351977 DramC Write-DBI off
8203 22:53:58.352416
8204 22:53:58.352819 [DATLAT]
8205 22:53:58.353134 Freq=1600, CH0 RK1
8206 22:53:58.353427
8207 22:53:58.355506 DATLAT Default: 0xf
8208 22:53:58.359049 0, 0xFFFF, sum = 0
8209 22:53:58.359470 1, 0xFFFF, sum = 0
8210 22:53:58.362129 2, 0xFFFF, sum = 0
8211 22:53:58.362580 3, 0xFFFF, sum = 0
8212 22:53:58.366028 4, 0xFFFF, sum = 0
8213 22:53:58.366609 5, 0xFFFF, sum = 0
8214 22:53:58.368819 6, 0xFFFF, sum = 0
8215 22:53:58.369237 7, 0xFFFF, sum = 0
8216 22:53:58.371843 8, 0xFFFF, sum = 0
8217 22:53:58.372262 9, 0xFFFF, sum = 0
8218 22:53:58.375191 10, 0xFFFF, sum = 0
8219 22:53:58.375616 11, 0xFFFF, sum = 0
8220 22:53:58.379001 12, 0xFFFF, sum = 0
8221 22:53:58.379522 13, 0xFFFF, sum = 0
8222 22:53:58.382390 14, 0x0, sum = 1
8223 22:53:58.382813 15, 0x0, sum = 2
8224 22:53:58.385172 16, 0x0, sum = 3
8225 22:53:58.385679 17, 0x0, sum = 4
8226 22:53:58.388494 best_step = 15
8227 22:53:58.389138
8228 22:53:58.389479 ==
8229 22:53:58.391836 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 22:53:58.394945 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 22:53:58.395468 ==
8232 22:53:58.398281 RX Vref Scan: 0
8233 22:53:58.399225
8234 22:53:58.399569 RX Vref 0 -> 0, step: 1
8235 22:53:58.399882
8236 22:53:58.401899 RX Delay 11 -> 252, step: 4
8237 22:53:58.408307 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8238 22:53:58.411509 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
8239 22:53:58.414547 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8240 22:53:58.417853 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8241 22:53:58.421700 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8242 22:53:58.428565 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8243 22:53:58.431452 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8244 22:53:58.434651 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8245 22:53:58.437949 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8246 22:53:58.441979 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8247 22:53:58.447945 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8248 22:53:58.451361 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8249 22:53:58.454867 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8250 22:53:58.458194 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8251 22:53:58.461613 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8252 22:53:58.467999 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8253 22:53:58.468537 ==
8254 22:53:58.471177 Dram Type= 6, Freq= 0, CH_0, rank 1
8255 22:53:58.474667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8256 22:53:58.475089 ==
8257 22:53:58.475416 DQS Delay:
8258 22:53:58.477874 DQS0 = 0, DQS1 = 0
8259 22:53:58.478455 DQM Delay:
8260 22:53:58.480870 DQM0 = 130, DQM1 = 125
8261 22:53:58.481283 DQ Delay:
8262 22:53:58.484399 DQ0 =128, DQ1 =132, DQ2 =126, DQ3 =128
8263 22:53:58.487378 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8264 22:53:58.490951 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8265 22:53:58.497026 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8266 22:53:58.497446
8267 22:53:58.497773
8268 22:53:58.498079
8269 22:53:58.501005 [DramC_TX_OE_Calibration] TA2
8270 22:53:58.504165 Original DQ_B0 (3 6) =30, OEN = 27
8271 22:53:58.504713 Original DQ_B1 (3 6) =30, OEN = 27
8272 22:53:58.507439 24, 0x0, End_B0=24 End_B1=24
8273 22:53:58.510732 25, 0x0, End_B0=25 End_B1=25
8274 22:53:58.513886 26, 0x0, End_B0=26 End_B1=26
8275 22:53:58.517004 27, 0x0, End_B0=27 End_B1=27
8276 22:53:58.517425 28, 0x0, End_B0=28 End_B1=28
8277 22:53:58.520660 29, 0x0, End_B0=29 End_B1=29
8278 22:53:58.523919 30, 0x0, End_B0=30 End_B1=30
8279 22:53:58.526942 31, 0x4545, End_B0=30 End_B1=30
8280 22:53:58.530610 Byte0 end_step=30 best_step=27
8281 22:53:58.531027 Byte1 end_step=30 best_step=27
8282 22:53:58.533568 Byte0 TX OE(2T, 0.5T) = (3, 3)
8283 22:53:58.537161 Byte1 TX OE(2T, 0.5T) = (3, 3)
8284 22:53:58.537572
8285 22:53:58.537893
8286 22:53:58.546997 [DQSOSCAuto] RK1, (LSB)MR18= 0x2003, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8287 22:53:58.549814 CH0 RK1: MR19=303, MR18=2003
8288 22:53:58.553484 CH0_RK1: MR19=0x303, MR18=0x2003, DQSOSC=393, MR23=63, INC=23, DEC=15
8289 22:53:58.556484 [RxdqsGatingPostProcess] freq 1600
8290 22:53:58.563085 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8291 22:53:58.566565 best DQS0 dly(2T, 0.5T) = (1, 1)
8292 22:53:58.569550 best DQS1 dly(2T, 0.5T) = (1, 1)
8293 22:53:58.573314 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8294 22:53:58.576198 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8295 22:53:58.579887 best DQS0 dly(2T, 0.5T) = (1, 1)
8296 22:53:58.583172 best DQS1 dly(2T, 0.5T) = (1, 1)
8297 22:53:58.585997 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8298 22:53:58.589565 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8299 22:53:58.589973 Pre-setting of DQS Precalculation
8300 22:53:58.596130 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8301 22:53:58.596645 ==
8302 22:53:58.599354 Dram Type= 6, Freq= 0, CH_1, rank 0
8303 22:53:58.602397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 22:53:58.602814 ==
8305 22:53:58.609627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8306 22:53:58.612837 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8307 22:53:58.619239 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8308 22:53:58.622693 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8309 22:53:58.632353 [CA 0] Center 41 (11~71) winsize 61
8310 22:53:58.635374 [CA 1] Center 42 (12~72) winsize 61
8311 22:53:58.638998 [CA 2] Center 37 (8~66) winsize 59
8312 22:53:58.642378 [CA 3] Center 35 (6~65) winsize 60
8313 22:53:58.645848 [CA 4] Center 37 (8~66) winsize 59
8314 22:53:58.648685 [CA 5] Center 36 (6~66) winsize 61
8315 22:53:58.649208
8316 22:53:58.652042 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8317 22:53:58.652570
8318 22:53:58.655307 [CATrainingPosCal] consider 1 rank data
8319 22:53:58.659035 u2DelayCellTimex100 = 262/100 ps
8320 22:53:58.665056 CA0 delay=41 (11~71),Diff = 6 PI (22 cell)
8321 22:53:58.668425 CA1 delay=42 (12~72),Diff = 7 PI (26 cell)
8322 22:53:58.671738 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8323 22:53:58.675130 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8324 22:53:58.678623 CA4 delay=37 (8~66),Diff = 2 PI (7 cell)
8325 22:53:58.681710 CA5 delay=36 (6~66),Diff = 1 PI (3 cell)
8326 22:53:58.682261
8327 22:53:58.685458 CA PerBit enable=1, Macro0, CA PI delay=35
8328 22:53:58.685998
8329 22:53:58.688560 [CBTSetCACLKResult] CA Dly = 35
8330 22:53:58.691771 CS Dly: 10 (0~41)
8331 22:53:58.695079 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8332 22:53:58.698251 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8333 22:53:58.698686 ==
8334 22:53:58.701712 Dram Type= 6, Freq= 0, CH_1, rank 1
8335 22:53:58.708335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 22:53:58.708878 ==
8337 22:53:58.711312 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8338 22:53:58.717853 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8339 22:53:58.721570 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8340 22:53:58.727753 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8341 22:53:58.735420 [CA 0] Center 42 (13~72) winsize 60
8342 22:53:58.738687 [CA 1] Center 43 (13~73) winsize 61
8343 22:53:58.741877 [CA 2] Center 37 (8~67) winsize 60
8344 22:53:58.745161 [CA 3] Center 37 (8~67) winsize 60
8345 22:53:58.748840 [CA 4] Center 38 (9~67) winsize 59
8346 22:53:58.752488 [CA 5] Center 37 (8~67) winsize 60
8347 22:53:58.752898
8348 22:53:58.755221 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8349 22:53:58.755632
8350 22:53:58.759008 [CATrainingPosCal] consider 2 rank data
8351 22:53:58.761916 u2DelayCellTimex100 = 262/100 ps
8352 22:53:58.765844 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8353 22:53:58.772324 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8354 22:53:58.774998 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8355 22:53:58.778805 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8356 22:53:58.781625 CA4 delay=37 (9~66),Diff = 1 PI (3 cell)
8357 22:53:58.785252 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8358 22:53:58.785774
8359 22:53:58.788936 CA PerBit enable=1, Macro0, CA PI delay=36
8360 22:53:58.789349
8361 22:53:58.791676 [CBTSetCACLKResult] CA Dly = 36
8362 22:53:58.794822 CS Dly: 11 (0~43)
8363 22:53:58.797886 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8364 22:53:58.801972 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8365 22:53:58.802431
8366 22:53:58.805067 ----->DramcWriteLeveling(PI) begin...
8367 22:53:58.805485 ==
8368 22:53:58.808099 Dram Type= 6, Freq= 0, CH_1, rank 0
8369 22:53:58.814379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 22:53:58.814881 ==
8371 22:53:58.817974 Write leveling (Byte 0): 24 => 24
8372 22:53:58.821033 Write leveling (Byte 1): 26 => 26
8373 22:53:58.824097 DramcWriteLeveling(PI) end<-----
8374 22:53:58.824507
8375 22:53:58.824832 ==
8376 22:53:58.827575 Dram Type= 6, Freq= 0, CH_1, rank 0
8377 22:53:58.830682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8378 22:53:58.831126 ==
8379 22:53:58.834216 [Gating] SW mode calibration
8380 22:53:58.840905 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8381 22:53:58.847451 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8382 22:53:58.850875 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 22:53:58.853723 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 22:53:58.857519 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8385 22:53:58.864327 1 4 12 | B1->B0 | 3030 3434 | 0 0 | (1 1) (0 0)
8386 22:53:58.867035 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 22:53:58.871269 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 22:53:58.877312 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 22:53:58.880352 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 22:53:58.887192 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 22:53:58.890293 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 22:53:58.893365 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8393 22:53:58.899952 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 0)
8394 22:53:58.903718 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 22:53:58.906715 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 22:53:58.909883 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 22:53:58.916641 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 22:53:58.920388 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 22:53:58.923659 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 22:53:58.930040 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8401 22:53:58.933329 1 6 12 | B1->B0 | 3737 4343 | 1 0 | (1 1) (0 0)
8402 22:53:58.936440 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 22:53:58.943288 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 22:53:58.947046 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 22:53:58.950097 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 22:53:58.956395 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 22:53:58.959818 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 22:53:58.962775 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8409 22:53:58.970079 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8410 22:53:58.972984 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8411 22:53:58.976105 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 22:53:58.982907 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 22:53:58.985894 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 22:53:58.989378 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 22:53:58.996142 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 22:53:58.999172 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 22:53:59.002564 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 22:53:59.009054 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 22:53:59.012469 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 22:53:59.015985 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 22:53:59.022187 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 22:53:59.025698 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 22:53:59.029081 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 22:53:59.036104 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 22:53:59.038728 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8426 22:53:59.042603 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 22:53:59.045277 Total UI for P1: 0, mck2ui 16
8428 22:53:59.049102 best dqsien dly found for B0: ( 1, 9, 12)
8429 22:53:59.052693 Total UI for P1: 0, mck2ui 16
8430 22:53:59.055649 best dqsien dly found for B1: ( 1, 9, 12)
8431 22:53:59.068996 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8432 22:53:59.069429 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8433 22:53:59.069756
8434 22:53:59.070118 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8435 22:53:59.071821 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8436 22:53:59.075092 [Gating] SW calibration Done
8437 22:53:59.075506 ==
8438 22:53:59.078356 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 22:53:59.082626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 22:53:59.083042 ==
8441 22:53:59.085588 RX Vref Scan: 0
8442 22:53:59.085998
8443 22:53:59.086457 RX Vref 0 -> 0, step: 1
8444 22:53:59.086994
8445 22:53:59.088466 RX Delay 0 -> 252, step: 8
8446 22:53:59.091635 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8447 22:53:59.094894 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8448 22:53:59.101878 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8449 22:53:59.105074 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8450 22:53:59.108094 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8451 22:53:59.111741 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8452 22:53:59.114884 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8453 22:53:59.121339 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8454 22:53:59.124762 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8455 22:53:59.128132 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8456 22:53:59.131670 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8457 22:53:59.138203 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8458 22:53:59.141561 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8459 22:53:59.145021 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8460 22:53:59.147500 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8461 22:53:59.150947 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8462 22:53:59.153892 ==
8463 22:53:59.157323 Dram Type= 6, Freq= 0, CH_1, rank 0
8464 22:53:59.160516 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8465 22:53:59.160933 ==
8466 22:53:59.161261 DQS Delay:
8467 22:53:59.164520 DQS0 = 0, DQS1 = 0
8468 22:53:59.164941 DQM Delay:
8469 22:53:59.167047 DQM0 = 136, DQM1 = 128
8470 22:53:59.167457 DQ Delay:
8471 22:53:59.170866 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =131
8472 22:53:59.173594 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8473 22:53:59.177432 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8474 22:53:59.180591 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8475 22:53:59.181040
8476 22:53:59.181374
8477 22:53:59.184009 ==
8478 22:53:59.187347 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 22:53:59.190697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 22:53:59.191111 ==
8481 22:53:59.191434
8482 22:53:59.191733
8483 22:53:59.193823 TX Vref Scan disable
8484 22:53:59.194259 == TX Byte 0 ==
8485 22:53:59.197023 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8486 22:53:59.203650 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8487 22:53:59.204062 == TX Byte 1 ==
8488 22:53:59.210074 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8489 22:53:59.213682 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8490 22:53:59.214092 ==
8491 22:53:59.216956 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 22:53:59.220344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 22:53:59.220858 ==
8494 22:53:59.233348
8495 22:53:59.236472 TX Vref early break, caculate TX vref
8496 22:53:59.240305 TX Vref=16, minBit 5, minWin=21, winSum=376
8497 22:53:59.243448 TX Vref=18, minBit 0, minWin=23, winSum=386
8498 22:53:59.246695 TX Vref=20, minBit 6, minWin=23, winSum=396
8499 22:53:59.249835 TX Vref=22, minBit 0, minWin=24, winSum=404
8500 22:53:59.253154 TX Vref=24, minBit 0, minWin=25, winSum=416
8501 22:53:59.260126 TX Vref=26, minBit 0, minWin=25, winSum=419
8502 22:53:59.263166 TX Vref=28, minBit 0, minWin=25, winSum=421
8503 22:53:59.266412 TX Vref=30, minBit 0, minWin=24, winSum=415
8504 22:53:59.269552 TX Vref=32, minBit 0, minWin=24, winSum=406
8505 22:53:59.272585 TX Vref=34, minBit 0, minWin=23, winSum=395
8506 22:53:59.279507 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 28
8507 22:53:59.280057
8508 22:53:59.282747 Final TX Range 0 Vref 28
8509 22:53:59.283259
8510 22:53:59.283581 ==
8511 22:53:59.285825 Dram Type= 6, Freq= 0, CH_1, rank 0
8512 22:53:59.289379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8513 22:53:59.289953 ==
8514 22:53:59.290333
8515 22:53:59.290644
8516 22:53:59.292769 TX Vref Scan disable
8517 22:53:59.298911 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8518 22:53:59.299325 == TX Byte 0 ==
8519 22:53:59.302457 u2DelayCellOfst[0]=18 cells (5 PI)
8520 22:53:59.305764 u2DelayCellOfst[1]=11 cells (3 PI)
8521 22:53:59.309401 u2DelayCellOfst[2]=0 cells (0 PI)
8522 22:53:59.312650 u2DelayCellOfst[3]=7 cells (2 PI)
8523 22:53:59.315326 u2DelayCellOfst[4]=7 cells (2 PI)
8524 22:53:59.318781 u2DelayCellOfst[5]=22 cells (6 PI)
8525 22:53:59.322377 u2DelayCellOfst[6]=22 cells (6 PI)
8526 22:53:59.325427 u2DelayCellOfst[7]=7 cells (2 PI)
8527 22:53:59.328588 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8528 22:53:59.332024 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8529 22:53:59.335359 == TX Byte 1 ==
8530 22:53:59.338159 u2DelayCellOfst[8]=0 cells (0 PI)
8531 22:53:59.341684 u2DelayCellOfst[9]=3 cells (1 PI)
8532 22:53:59.342036 u2DelayCellOfst[10]=14 cells (4 PI)
8533 22:53:59.344901 u2DelayCellOfst[11]=7 cells (2 PI)
8534 22:53:59.347894 u2DelayCellOfst[12]=14 cells (4 PI)
8535 22:53:59.351164 u2DelayCellOfst[13]=18 cells (5 PI)
8536 22:53:59.354539 u2DelayCellOfst[14]=18 cells (5 PI)
8537 22:53:59.358108 u2DelayCellOfst[15]=22 cells (6 PI)
8538 22:53:59.365062 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8539 22:53:59.367668 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8540 22:53:59.367798 DramC Write-DBI on
8541 22:53:59.367911 ==
8542 22:53:59.371190 Dram Type= 6, Freq= 0, CH_1, rank 0
8543 22:53:59.377893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8544 22:53:59.377993 ==
8545 22:53:59.378084
8546 22:53:59.378179
8547 22:53:59.381452 TX Vref Scan disable
8548 22:53:59.382015 == TX Byte 0 ==
8549 22:53:59.387676 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8550 22:53:59.388109 == TX Byte 1 ==
8551 22:53:59.391502 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8552 22:53:59.394316 DramC Write-DBI off
8553 22:53:59.394740
8554 22:53:59.395090 [DATLAT]
8555 22:53:59.397981 Freq=1600, CH1 RK0
8556 22:53:59.398454
8557 22:53:59.398861 DATLAT Default: 0xf
8558 22:53:59.400849 0, 0xFFFF, sum = 0
8559 22:53:59.401288 1, 0xFFFF, sum = 0
8560 22:53:59.404259 2, 0xFFFF, sum = 0
8561 22:53:59.404696 3, 0xFFFF, sum = 0
8562 22:53:59.407302 4, 0xFFFF, sum = 0
8563 22:53:59.407723 5, 0xFFFF, sum = 0
8564 22:53:59.410725 6, 0xFFFF, sum = 0
8565 22:53:59.414117 7, 0xFFFF, sum = 0
8566 22:53:59.414454 8, 0xFFFF, sum = 0
8567 22:53:59.417235 9, 0xFFFF, sum = 0
8568 22:53:59.417460 10, 0xFFFF, sum = 0
8569 22:53:59.420361 11, 0xFFFF, sum = 0
8570 22:53:59.420558 12, 0xFFFF, sum = 0
8571 22:53:59.423862 13, 0xFFFF, sum = 0
8572 22:53:59.424079 14, 0x0, sum = 1
8573 22:53:59.426971 15, 0x0, sum = 2
8574 22:53:59.427124 16, 0x0, sum = 3
8575 22:53:59.430103 17, 0x0, sum = 4
8576 22:53:59.430291 best_step = 15
8577 22:53:59.430412
8578 22:53:59.430538 ==
8579 22:53:59.433405 Dram Type= 6, Freq= 0, CH_1, rank 0
8580 22:53:59.437173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8581 22:53:59.440237 ==
8582 22:53:59.440413 RX Vref Scan: 1
8583 22:53:59.440558
8584 22:53:59.443517 Set Vref Range= 24 -> 127
8585 22:53:59.443646
8586 22:53:59.446963 RX Vref 24 -> 127, step: 1
8587 22:53:59.447092
8588 22:53:59.447193 RX Delay 11 -> 252, step: 4
8589 22:53:59.447287
8590 22:53:59.450128 Set Vref, RX VrefLevel [Byte0]: 24
8591 22:53:59.453044 [Byte1]: 24
8592 22:53:59.457121
8593 22:53:59.457289 Set Vref, RX VrefLevel [Byte0]: 25
8594 22:53:59.460130 [Byte1]: 25
8595 22:53:59.465098
8596 22:53:59.465227 Set Vref, RX VrefLevel [Byte0]: 26
8597 22:53:59.467739 [Byte1]: 26
8598 22:53:59.472317
8599 22:53:59.472501 Set Vref, RX VrefLevel [Byte0]: 27
8600 22:53:59.475545 [Byte1]: 27
8601 22:53:59.479821
8602 22:53:59.479982 Set Vref, RX VrefLevel [Byte0]: 28
8603 22:53:59.483080 [Byte1]: 28
8604 22:53:59.487463
8605 22:53:59.487594 Set Vref, RX VrefLevel [Byte0]: 29
8606 22:53:59.490924 [Byte1]: 29
8607 22:53:59.495925
8608 22:53:59.496059 Set Vref, RX VrefLevel [Byte0]: 30
8609 22:53:59.498098 [Byte1]: 30
8610 22:53:59.502547
8611 22:53:59.502667 Set Vref, RX VrefLevel [Byte0]: 31
8612 22:53:59.505964 [Byte1]: 31
8613 22:53:59.510528
8614 22:53:59.510643 Set Vref, RX VrefLevel [Byte0]: 32
8615 22:53:59.513842 [Byte1]: 32
8616 22:53:59.517821
8617 22:53:59.517928 Set Vref, RX VrefLevel [Byte0]: 33
8618 22:53:59.521174 [Byte1]: 33
8619 22:53:59.525540
8620 22:53:59.525661 Set Vref, RX VrefLevel [Byte0]: 34
8621 22:53:59.528950 [Byte1]: 34
8622 22:53:59.532958
8623 22:53:59.533082 Set Vref, RX VrefLevel [Byte0]: 35
8624 22:53:59.536311 [Byte1]: 35
8625 22:53:59.540973
8626 22:53:59.541086 Set Vref, RX VrefLevel [Byte0]: 36
8627 22:53:59.544356 [Byte1]: 36
8628 22:53:59.548709
8629 22:53:59.548811 Set Vref, RX VrefLevel [Byte0]: 37
8630 22:53:59.551541 [Byte1]: 37
8631 22:53:59.555855
8632 22:53:59.555936 Set Vref, RX VrefLevel [Byte0]: 38
8633 22:53:59.559597 [Byte1]: 38
8634 22:53:59.563378
8635 22:53:59.563458 Set Vref, RX VrefLevel [Byte0]: 39
8636 22:53:59.566678 [Byte1]: 39
8637 22:53:59.571052
8638 22:53:59.571132 Set Vref, RX VrefLevel [Byte0]: 40
8639 22:53:59.574674 [Byte1]: 40
8640 22:53:59.579083
8641 22:53:59.579163 Set Vref, RX VrefLevel [Byte0]: 41
8642 22:53:59.582217 [Byte1]: 41
8643 22:53:59.586398
8644 22:53:59.586477 Set Vref, RX VrefLevel [Byte0]: 42
8645 22:53:59.589701 [Byte1]: 42
8646 22:53:59.593957
8647 22:53:59.594042 Set Vref, RX VrefLevel [Byte0]: 43
8648 22:53:59.597150 [Byte1]: 43
8649 22:53:59.601767
8650 22:53:59.601898 Set Vref, RX VrefLevel [Byte0]: 44
8651 22:53:59.605309 [Byte1]: 44
8652 22:53:59.608918
8653 22:53:59.612708 Set Vref, RX VrefLevel [Byte0]: 45
8654 22:53:59.612826 [Byte1]: 45
8655 22:53:59.617007
8656 22:53:59.617112 Set Vref, RX VrefLevel [Byte0]: 46
8657 22:53:59.620530 [Byte1]: 46
8658 22:53:59.624966
8659 22:53:59.625065 Set Vref, RX VrefLevel [Byte0]: 47
8660 22:53:59.627567 [Byte1]: 47
8661 22:53:59.631899
8662 22:53:59.632028 Set Vref, RX VrefLevel [Byte0]: 48
8663 22:53:59.635232 [Byte1]: 48
8664 22:53:59.639820
8665 22:53:59.639901 Set Vref, RX VrefLevel [Byte0]: 49
8666 22:53:59.643116 [Byte1]: 49
8667 22:53:59.647329
8668 22:53:59.647410 Set Vref, RX VrefLevel [Byte0]: 50
8669 22:53:59.650419 [Byte1]: 50
8670 22:53:59.655066
8671 22:53:59.655146 Set Vref, RX VrefLevel [Byte0]: 51
8672 22:53:59.658282 [Byte1]: 51
8673 22:53:59.662952
8674 22:53:59.663033 Set Vref, RX VrefLevel [Byte0]: 52
8675 22:53:59.666133 [Byte1]: 52
8676 22:53:59.670577
8677 22:53:59.670986 Set Vref, RX VrefLevel [Byte0]: 53
8678 22:53:59.673915 [Byte1]: 53
8679 22:53:59.678267
8680 22:53:59.678751 Set Vref, RX VrefLevel [Byte0]: 54
8681 22:53:59.681382 [Byte1]: 54
8682 22:53:59.685870
8683 22:53:59.686376 Set Vref, RX VrefLevel [Byte0]: 55
8684 22:53:59.688962 [Byte1]: 55
8685 22:53:59.693269
8686 22:53:59.693725 Set Vref, RX VrefLevel [Byte0]: 56
8687 22:53:59.696599 [Byte1]: 56
8688 22:53:59.701053
8689 22:53:59.701476 Set Vref, RX VrefLevel [Byte0]: 57
8690 22:53:59.704052 [Byte1]: 57
8691 22:53:59.708765
8692 22:53:59.709216 Set Vref, RX VrefLevel [Byte0]: 58
8693 22:53:59.711914 [Byte1]: 58
8694 22:53:59.716454
8695 22:53:59.716900 Set Vref, RX VrefLevel [Byte0]: 59
8696 22:53:59.719373 [Byte1]: 59
8697 22:53:59.723754
8698 22:53:59.724286 Set Vref, RX VrefLevel [Byte0]: 60
8699 22:53:59.727155 [Byte1]: 60
8700 22:53:59.731529
8701 22:53:59.731958 Set Vref, RX VrefLevel [Byte0]: 61
8702 22:53:59.734917 [Byte1]: 61
8703 22:53:59.738955
8704 22:53:59.739249 Set Vref, RX VrefLevel [Byte0]: 62
8705 22:53:59.742252 [Byte1]: 62
8706 22:53:59.746466
8707 22:53:59.746645 Set Vref, RX VrefLevel [Byte0]: 63
8708 22:53:59.749756 [Byte1]: 63
8709 22:53:59.753907
8710 22:53:59.754147 Set Vref, RX VrefLevel [Byte0]: 64
8711 22:53:59.757119 [Byte1]: 64
8712 22:53:59.761557
8713 22:53:59.761671 Set Vref, RX VrefLevel [Byte0]: 65
8714 22:53:59.765268 [Byte1]: 65
8715 22:53:59.769435
8716 22:53:59.769540 Set Vref, RX VrefLevel [Byte0]: 66
8717 22:53:59.772291 [Byte1]: 66
8718 22:53:59.776813
8719 22:53:59.776900 Set Vref, RX VrefLevel [Byte0]: 67
8720 22:53:59.780171 [Byte1]: 67
8721 22:53:59.784167
8722 22:53:59.784305 Set Vref, RX VrefLevel [Byte0]: 68
8723 22:53:59.787860 [Byte1]: 68
8724 22:53:59.792257
8725 22:53:59.792340 Set Vref, RX VrefLevel [Byte0]: 69
8726 22:53:59.795869 [Byte1]: 69
8727 22:53:59.800120
8728 22:53:59.800424 Set Vref, RX VrefLevel [Byte0]: 70
8729 22:53:59.803059 [Byte1]: 70
8730 22:53:59.807153
8731 22:53:59.807385 Set Vref, RX VrefLevel [Byte0]: 71
8732 22:53:59.810992 [Byte1]: 71
8733 22:53:59.815213
8734 22:53:59.815400 Final RX Vref Byte 0 = 53 to rank0
8735 22:53:59.818127 Final RX Vref Byte 1 = 59 to rank0
8736 22:53:59.821586 Final RX Vref Byte 0 = 53 to rank1
8737 22:53:59.824563 Final RX Vref Byte 1 = 59 to rank1==
8738 22:53:59.828447 Dram Type= 6, Freq= 0, CH_1, rank 0
8739 22:53:59.834690 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8740 22:53:59.834880 ==
8741 22:53:59.835030 DQS Delay:
8742 22:53:59.838331 DQS0 = 0, DQS1 = 0
8743 22:53:59.838554 DQM Delay:
8744 22:53:59.838731 DQM0 = 133, DQM1 = 127
8745 22:53:59.841167 DQ Delay:
8746 22:53:59.844723 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8747 22:53:59.848067 DQ4 =132, DQ5 =146, DQ6 =142, DQ7 =128
8748 22:53:59.851284 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8749 22:53:59.854387 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8750 22:53:59.854742
8751 22:53:59.855048
8752 22:53:59.855310
8753 22:53:59.857882 [DramC_TX_OE_Calibration] TA2
8754 22:53:59.860924 Original DQ_B0 (3 6) =30, OEN = 27
8755 22:53:59.864429 Original DQ_B1 (3 6) =30, OEN = 27
8756 22:53:59.868071 24, 0x0, End_B0=24 End_B1=24
8757 22:53:59.870932 25, 0x0, End_B0=25 End_B1=25
8758 22:53:59.871415 26, 0x0, End_B0=26 End_B1=26
8759 22:53:59.874598 27, 0x0, End_B0=27 End_B1=27
8760 22:53:59.877512 28, 0x0, End_B0=28 End_B1=28
8761 22:53:59.880954 29, 0x0, End_B0=29 End_B1=29
8762 22:53:59.881374 30, 0x0, End_B0=30 End_B1=30
8763 22:53:59.884554 31, 0x4141, End_B0=30 End_B1=30
8764 22:53:59.887751 Byte0 end_step=30 best_step=27
8765 22:53:59.890940 Byte1 end_step=30 best_step=27
8766 22:53:59.894201 Byte0 TX OE(2T, 0.5T) = (3, 3)
8767 22:53:59.897766 Byte1 TX OE(2T, 0.5T) = (3, 3)
8768 22:53:59.898210
8769 22:53:59.898539
8770 22:53:59.904217 [DQSOSCAuto] RK0, (LSB)MR18= 0x180e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8771 22:53:59.907579 CH1 RK0: MR19=303, MR18=180E
8772 22:53:59.913800 CH1_RK0: MR19=0x303, MR18=0x180E, DQSOSC=397, MR23=63, INC=23, DEC=15
8773 22:53:59.914259
8774 22:53:59.917033 ----->DramcWriteLeveling(PI) begin...
8775 22:53:59.917408 ==
8776 22:53:59.921039 Dram Type= 6, Freq= 0, CH_1, rank 1
8777 22:53:59.923736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8778 22:53:59.924149 ==
8779 22:53:59.927184 Write leveling (Byte 0): 23 => 23
8780 22:53:59.930814 Write leveling (Byte 1): 27 => 27
8781 22:53:59.933955 DramcWriteLeveling(PI) end<-----
8782 22:53:59.934411
8783 22:53:59.934740 ==
8784 22:53:59.937160 Dram Type= 6, Freq= 0, CH_1, rank 1
8785 22:53:59.943773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8786 22:53:59.944227 ==
8787 22:53:59.944566 [Gating] SW mode calibration
8788 22:53:59.953268 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8789 22:53:59.957042 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8790 22:53:59.963005 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 22:53:59.966517 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 22:53:59.969685 1 4 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8793 22:53:59.975949 1 4 12 | B1->B0 | 3131 2323 | 1 0 | (0 0) (0 0)
8794 22:53:59.979665 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 22:53:59.982635 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 22:53:59.989137 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 22:53:59.992197 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 22:53:59.995661 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8799 22:54:00.002916 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 22:54:00.006238 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8801 22:54:00.009379 1 5 12 | B1->B0 | 2525 3333 | 0 1 | (0 1) (1 0)
8802 22:54:00.016402 1 5 16 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 0)
8803 22:54:00.019310 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 22:54:00.022592 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 22:54:00.029186 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 22:54:00.032667 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 22:54:00.035935 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 22:54:00.042444 1 6 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8809 22:54:00.045797 1 6 12 | B1->B0 | 4646 2323 | 0 0 | (0 0) (0 0)
8810 22:54:00.049017 1 6 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8811 22:54:00.056114 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 22:54:00.059216 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 22:54:00.062537 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 22:54:00.068774 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 22:54:00.071829 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 22:54:00.075242 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8817 22:54:00.082319 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8818 22:54:00.085529 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8819 22:54:00.088799 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 22:54:00.094917 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 22:54:00.098401 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 22:54:00.101519 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 22:54:00.108539 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 22:54:00.111725 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 22:54:00.114573 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 22:54:00.121911 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 22:54:00.124921 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 22:54:00.128349 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 22:54:00.135005 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 22:54:00.138015 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 22:54:00.141693 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 22:54:00.148040 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8833 22:54:00.151676 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8834 22:54:00.154599 Total UI for P1: 0, mck2ui 16
8835 22:54:00.157837 best dqsien dly found for B1: ( 1, 9, 8)
8836 22:54:00.161308 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8837 22:54:00.164925 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8838 22:54:00.167805 Total UI for P1: 0, mck2ui 16
8839 22:54:00.171147 best dqsien dly found for B0: ( 1, 9, 12)
8840 22:54:00.177755 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8841 22:54:00.180647 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8842 22:54:00.181053
8843 22:54:00.184292 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8844 22:54:00.187562 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8845 22:54:00.190862 [Gating] SW calibration Done
8846 22:54:00.191371 ==
8847 22:54:00.194304 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 22:54:00.197193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 22:54:00.197747 ==
8850 22:54:00.200275 RX Vref Scan: 0
8851 22:54:00.200696
8852 22:54:00.201102 RX Vref 0 -> 0, step: 1
8853 22:54:00.201412
8854 22:54:00.203768 RX Delay 0 -> 252, step: 8
8855 22:54:00.207230 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8856 22:54:00.213433 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8857 22:54:00.216888 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8858 22:54:00.220270 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8859 22:54:00.223152 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8860 22:54:00.227082 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8861 22:54:00.233017 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8862 22:54:00.236509 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8863 22:54:00.239605 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8864 22:54:00.242899 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8865 22:54:00.246568 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8866 22:54:00.253008 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8867 22:54:00.256428 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8868 22:54:00.259312 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8869 22:54:00.262898 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8870 22:54:00.269707 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8871 22:54:00.270123 ==
8872 22:54:00.272622 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 22:54:00.276167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 22:54:00.276583 ==
8875 22:54:00.276908 DQS Delay:
8876 22:54:00.279776 DQS0 = 0, DQS1 = 0
8877 22:54:00.280187 DQM Delay:
8878 22:54:00.282583 DQM0 = 137, DQM1 = 129
8879 22:54:00.283037 DQ Delay:
8880 22:54:00.285958 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8881 22:54:00.289340 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8882 22:54:00.292597 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8883 22:54:00.296118 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8884 22:54:00.296499
8885 22:54:00.299110
8886 22:54:00.299597 ==
8887 22:54:00.302392 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 22:54:00.305897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 22:54:00.306423 ==
8890 22:54:00.306788
8891 22:54:00.307095
8892 22:54:00.309235 TX Vref Scan disable
8893 22:54:00.309644 == TX Byte 0 ==
8894 22:54:00.315765 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8895 22:54:00.318909 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8896 22:54:00.319320 == TX Byte 1 ==
8897 22:54:00.326096 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8898 22:54:00.329135 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8899 22:54:00.329668 ==
8900 22:54:00.332476 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 22:54:00.335585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 22:54:00.336003 ==
8903 22:54:00.349420
8904 22:54:00.353314 TX Vref early break, caculate TX vref
8905 22:54:00.355906 TX Vref=16, minBit 0, minWin=22, winSum=384
8906 22:54:00.359288 TX Vref=18, minBit 0, minWin=23, winSum=392
8907 22:54:00.362487 TX Vref=20, minBit 0, minWin=24, winSum=399
8908 22:54:00.366286 TX Vref=22, minBit 5, minWin=23, winSum=403
8909 22:54:00.369084 TX Vref=24, minBit 5, minWin=24, winSum=413
8910 22:54:00.376214 TX Vref=26, minBit 0, minWin=25, winSum=419
8911 22:54:00.379152 TX Vref=28, minBit 0, minWin=24, winSum=418
8912 22:54:00.382687 TX Vref=30, minBit 0, minWin=24, winSum=414
8913 22:54:00.385869 TX Vref=32, minBit 0, minWin=23, winSum=404
8914 22:54:00.388649 TX Vref=34, minBit 0, minWin=22, winSum=396
8915 22:54:00.395249 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 26
8916 22:54:00.395768
8917 22:54:00.398541 Final TX Range 0 Vref 26
8918 22:54:00.399139
8919 22:54:00.399484 ==
8920 22:54:00.401724 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 22:54:00.405215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 22:54:00.405844 ==
8923 22:54:00.406220
8924 22:54:00.406583
8925 22:54:00.408397 TX Vref Scan disable
8926 22:54:00.414880 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8927 22:54:00.415373 == TX Byte 0 ==
8928 22:54:00.418846 u2DelayCellOfst[0]=18 cells (5 PI)
8929 22:54:00.421499 u2DelayCellOfst[1]=11 cells (3 PI)
8930 22:54:00.425697 u2DelayCellOfst[2]=0 cells (0 PI)
8931 22:54:00.428852 u2DelayCellOfst[3]=3 cells (1 PI)
8932 22:54:00.431755 u2DelayCellOfst[4]=7 cells (2 PI)
8933 22:54:00.435215 u2DelayCellOfst[5]=18 cells (5 PI)
8934 22:54:00.438768 u2DelayCellOfst[6]=18 cells (5 PI)
8935 22:54:00.441626 u2DelayCellOfst[7]=3 cells (1 PI)
8936 22:54:00.444999 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8937 22:54:00.448702 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8938 22:54:00.451971 == TX Byte 1 ==
8939 22:54:00.454530 u2DelayCellOfst[8]=0 cells (0 PI)
8940 22:54:00.458052 u2DelayCellOfst[9]=7 cells (2 PI)
8941 22:54:00.461767 u2DelayCellOfst[10]=11 cells (3 PI)
8942 22:54:00.462399 u2DelayCellOfst[11]=7 cells (2 PI)
8943 22:54:00.464519 u2DelayCellOfst[12]=14 cells (4 PI)
8944 22:54:00.468325 u2DelayCellOfst[13]=18 cells (5 PI)
8945 22:54:00.471395 u2DelayCellOfst[14]=18 cells (5 PI)
8946 22:54:00.474324 u2DelayCellOfst[15]=18 cells (5 PI)
8947 22:54:00.481376 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8948 22:54:00.484737 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8949 22:54:00.485190 DramC Write-DBI on
8950 22:54:00.485541 ==
8951 22:54:00.487688 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 22:54:00.494125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 22:54:00.494658 ==
8954 22:54:00.494982
8955 22:54:00.495277
8956 22:54:00.497788 TX Vref Scan disable
8957 22:54:00.498337 == TX Byte 0 ==
8958 22:54:00.503936 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8959 22:54:00.504344 == TX Byte 1 ==
8960 22:54:00.507571 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8961 22:54:00.510932 DramC Write-DBI off
8962 22:54:00.511334
8963 22:54:00.511652 [DATLAT]
8964 22:54:00.514513 Freq=1600, CH1 RK1
8965 22:54:00.514920
8966 22:54:00.515238 DATLAT Default: 0xf
8967 22:54:00.517347 0, 0xFFFF, sum = 0
8968 22:54:00.517792 1, 0xFFFF, sum = 0
8969 22:54:00.521244 2, 0xFFFF, sum = 0
8970 22:54:00.521750 3, 0xFFFF, sum = 0
8971 22:54:00.524245 4, 0xFFFF, sum = 0
8972 22:54:00.524691 5, 0xFFFF, sum = 0
8973 22:54:00.526837 6, 0xFFFF, sum = 0
8974 22:54:00.530250 7, 0xFFFF, sum = 0
8975 22:54:00.530704 8, 0xFFFF, sum = 0
8976 22:54:00.534033 9, 0xFFFF, sum = 0
8977 22:54:00.534631 10, 0xFFFF, sum = 0
8978 22:54:00.537038 11, 0xFFFF, sum = 0
8979 22:54:00.537446 12, 0xFFFF, sum = 0
8980 22:54:00.540102 13, 0xFFFF, sum = 0
8981 22:54:00.540514 14, 0x0, sum = 1
8982 22:54:00.543594 15, 0x0, sum = 2
8983 22:54:00.544102 16, 0x0, sum = 3
8984 22:54:00.547540 17, 0x0, sum = 4
8985 22:54:00.548099 best_step = 15
8986 22:54:00.548460
8987 22:54:00.548768 ==
8988 22:54:00.550254 Dram Type= 6, Freq= 0, CH_1, rank 1
8989 22:54:00.553831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8990 22:54:00.556494 ==
8991 22:54:00.557002 RX Vref Scan: 0
8992 22:54:00.557459
8993 22:54:00.559928 RX Vref 0 -> 0, step: 1
8994 22:54:00.560340
8995 22:54:00.560662 RX Delay 11 -> 252, step: 4
8996 22:54:00.568045 iDelay=199, Bit 0, Center 138 (87 ~ 190) 104
8997 22:54:00.570989 iDelay=199, Bit 1, Center 128 (75 ~ 182) 108
8998 22:54:00.574125 iDelay=199, Bit 2, Center 122 (67 ~ 178) 112
8999 22:54:00.577022 iDelay=199, Bit 3, Center 130 (79 ~ 182) 104
9000 22:54:00.584012 iDelay=199, Bit 4, Center 134 (79 ~ 190) 112
9001 22:54:00.586950 iDelay=199, Bit 5, Center 144 (91 ~ 198) 108
9002 22:54:00.590728 iDelay=199, Bit 6, Center 144 (91 ~ 198) 108
9003 22:54:00.593514 iDelay=199, Bit 7, Center 130 (79 ~ 182) 104
9004 22:54:00.596675 iDelay=199, Bit 8, Center 112 (55 ~ 170) 116
9005 22:54:00.603662 iDelay=199, Bit 9, Center 114 (59 ~ 170) 112
9006 22:54:00.607177 iDelay=199, Bit 10, Center 126 (71 ~ 182) 112
9007 22:54:00.610225 iDelay=199, Bit 11, Center 118 (67 ~ 170) 104
9008 22:54:00.613937 iDelay=199, Bit 12, Center 136 (83 ~ 190) 108
9009 22:54:00.617327 iDelay=199, Bit 13, Center 136 (83 ~ 190) 108
9010 22:54:00.623253 iDelay=199, Bit 14, Center 134 (79 ~ 190) 112
9011 22:54:00.626810 iDelay=199, Bit 15, Center 138 (83 ~ 194) 112
9012 22:54:00.627225 ==
9013 22:54:00.630320 Dram Type= 6, Freq= 0, CH_1, rank 1
9014 22:54:00.632919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9015 22:54:00.633353 ==
9016 22:54:00.636625 DQS Delay:
9017 22:54:00.637035 DQS0 = 0, DQS1 = 0
9018 22:54:00.639364 DQM Delay:
9019 22:54:00.639801 DQM0 = 133, DQM1 = 126
9020 22:54:00.640216 DQ Delay:
9021 22:54:00.646046 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9022 22:54:00.649745 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =130
9023 22:54:00.653127 DQ8 =112, DQ9 =114, DQ10 =126, DQ11 =118
9024 22:54:00.656444 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9025 22:54:00.656944
9026 22:54:00.657275
9027 22:54:00.657580
9028 22:54:00.659309 [DramC_TX_OE_Calibration] TA2
9029 22:54:00.662655 Original DQ_B0 (3 6) =30, OEN = 27
9030 22:54:00.666014 Original DQ_B1 (3 6) =30, OEN = 27
9031 22:54:00.666467 24, 0x0, End_B0=24 End_B1=24
9032 22:54:00.669179 25, 0x0, End_B0=25 End_B1=25
9033 22:54:00.672360 26, 0x0, End_B0=26 End_B1=26
9034 22:54:00.676308 27, 0x0, End_B0=27 End_B1=27
9035 22:54:00.679068 28, 0x0, End_B0=28 End_B1=28
9036 22:54:00.679494 29, 0x0, End_B0=29 End_B1=29
9037 22:54:00.682233 30, 0x0, End_B0=30 End_B1=30
9038 22:54:00.685750 31, 0x5151, End_B0=30 End_B1=30
9039 22:54:00.688841 Byte0 end_step=30 best_step=27
9040 22:54:00.692327 Byte1 end_step=30 best_step=27
9041 22:54:00.695854 Byte0 TX OE(2T, 0.5T) = (3, 3)
9042 22:54:00.696348 Byte1 TX OE(2T, 0.5T) = (3, 3)
9043 22:54:00.696698
9044 22:54:00.699072
9045 22:54:00.705343 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 403 ps
9046 22:54:00.708789 CH1 RK1: MR19=303, MR18=D0A
9047 22:54:00.715282 CH1_RK1: MR19=0x303, MR18=0xD0A, DQSOSC=403, MR23=63, INC=22, DEC=15
9048 22:54:00.718504 [RxdqsGatingPostProcess] freq 1600
9049 22:54:00.722086 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9050 22:54:00.725718 best DQS0 dly(2T, 0.5T) = (1, 1)
9051 22:54:00.728746 best DQS1 dly(2T, 0.5T) = (1, 1)
9052 22:54:00.732059 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9053 22:54:00.735334 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9054 22:54:00.738269 best DQS0 dly(2T, 0.5T) = (1, 1)
9055 22:54:00.741939 best DQS1 dly(2T, 0.5T) = (1, 1)
9056 22:54:00.745023 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9057 22:54:00.748569 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9058 22:54:00.751409 Pre-setting of DQS Precalculation
9059 22:54:00.755121 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9060 22:54:00.761810 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9061 22:54:00.767908 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9062 22:54:00.768324
9063 22:54:00.771292
9064 22:54:00.771729 [Calibration Summary] 3200 Mbps
9065 22:54:00.775295 CH 0, Rank 0
9066 22:54:00.775710 SW Impedance : PASS
9067 22:54:00.777997 DUTY Scan : NO K
9068 22:54:00.781461 ZQ Calibration : PASS
9069 22:54:00.781877 Jitter Meter : NO K
9070 22:54:00.785006 CBT Training : PASS
9071 22:54:00.788041 Write leveling : PASS
9072 22:54:00.788551 RX DQS gating : PASS
9073 22:54:00.791628 RX DQ/DQS(RDDQC) : PASS
9074 22:54:00.794266 TX DQ/DQS : PASS
9075 22:54:00.794686 RX DATLAT : PASS
9076 22:54:00.798000 RX DQ/DQS(Engine): PASS
9077 22:54:00.800994 TX OE : PASS
9078 22:54:00.801415 All Pass.
9079 22:54:00.801821
9080 22:54:00.802131 CH 0, Rank 1
9081 22:54:00.804393 SW Impedance : PASS
9082 22:54:00.807702 DUTY Scan : NO K
9083 22:54:00.808116 ZQ Calibration : PASS
9084 22:54:00.811016 Jitter Meter : NO K
9085 22:54:00.814034 CBT Training : PASS
9086 22:54:00.814492 Write leveling : PASS
9087 22:54:00.817636 RX DQS gating : PASS
9088 22:54:00.821533 RX DQ/DQS(RDDQC) : PASS
9089 22:54:00.822047 TX DQ/DQS : PASS
9090 22:54:00.824129 RX DATLAT : PASS
9091 22:54:00.827454 RX DQ/DQS(Engine): PASS
9092 22:54:00.827900 TX OE : PASS
9093 22:54:00.828235 All Pass.
9094 22:54:00.830483
9095 22:54:00.830893 CH 1, Rank 0
9096 22:54:00.833771 SW Impedance : PASS
9097 22:54:00.834220 DUTY Scan : NO K
9098 22:54:00.837536 ZQ Calibration : PASS
9099 22:54:00.840702 Jitter Meter : NO K
9100 22:54:00.841117 CBT Training : PASS
9101 22:54:00.843753 Write leveling : PASS
9102 22:54:00.844164 RX DQS gating : PASS
9103 22:54:00.847012 RX DQ/DQS(RDDQC) : PASS
9104 22:54:00.850669 TX DQ/DQS : PASS
9105 22:54:00.851091 RX DATLAT : PASS
9106 22:54:00.854118 RX DQ/DQS(Engine): PASS
9107 22:54:00.856913 TX OE : PASS
9108 22:54:00.857399 All Pass.
9109 22:54:00.857727
9110 22:54:00.858025 CH 1, Rank 1
9111 22:54:00.860291 SW Impedance : PASS
9112 22:54:00.863968 DUTY Scan : NO K
9113 22:54:00.864379 ZQ Calibration : PASS
9114 22:54:00.866939 Jitter Meter : NO K
9115 22:54:00.870299 CBT Training : PASS
9116 22:54:00.870703 Write leveling : PASS
9117 22:54:00.873859 RX DQS gating : PASS
9118 22:54:00.877430 RX DQ/DQS(RDDQC) : PASS
9119 22:54:00.877935 TX DQ/DQS : PASS
9120 22:54:00.880840 RX DATLAT : PASS
9121 22:54:00.884292 RX DQ/DQS(Engine): PASS
9122 22:54:00.884796 TX OE : PASS
9123 22:54:00.886721 All Pass.
9124 22:54:00.887125
9125 22:54:00.887442 DramC Write-DBI on
9126 22:54:00.890775 PER_BANK_REFRESH: Hybrid Mode
9127 22:54:00.891277 TX_TRACKING: ON
9128 22:54:00.899801 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9129 22:54:00.909890 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9130 22:54:00.916532 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9131 22:54:00.919862 [FAST_K] Save calibration result to emmc
9132 22:54:00.923244 sync common calibartion params.
9133 22:54:00.923760 sync cbt_mode0:1, 1:1
9134 22:54:00.926570 dram_init: ddr_geometry: 2
9135 22:54:00.929846 dram_init: ddr_geometry: 2
9136 22:54:00.930445 dram_init: ddr_geometry: 2
9137 22:54:00.933032 0:dram_rank_size:100000000
9138 22:54:00.936668 1:dram_rank_size:100000000
9139 22:54:00.943235 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9140 22:54:00.943752 DFS_SHUFFLE_HW_MODE: ON
9141 22:54:00.946243 dramc_set_vcore_voltage set vcore to 725000
9142 22:54:00.949423 Read voltage for 1600, 0
9143 22:54:00.949836 Vio18 = 0
9144 22:54:00.952590 Vcore = 725000
9145 22:54:00.953112 Vdram = 0
9146 22:54:00.953445 Vddq = 0
9147 22:54:00.956013 Vmddr = 0
9148 22:54:00.956425 switch to 3200 Mbps bootup
9149 22:54:00.959508 [DramcRunTimeConfig]
9150 22:54:00.959923 PHYPLL
9151 22:54:00.962822 DPM_CONTROL_AFTERK: ON
9152 22:54:00.963340 PER_BANK_REFRESH: ON
9153 22:54:00.965908 REFRESH_OVERHEAD_REDUCTION: ON
9154 22:54:00.969195 CMD_PICG_NEW_MODE: OFF
9155 22:54:00.969708 XRTWTW_NEW_MODE: ON
9156 22:54:00.972333 XRTRTR_NEW_MODE: ON
9157 22:54:00.972854 TX_TRACKING: ON
9158 22:54:00.975831 RDSEL_TRACKING: OFF
9159 22:54:00.978999 DQS Precalculation for DVFS: ON
9160 22:54:00.979411 RX_TRACKING: OFF
9161 22:54:00.982111 HW_GATING DBG: ON
9162 22:54:00.982569 ZQCS_ENABLE_LP4: ON
9163 22:54:00.985567 RX_PICG_NEW_MODE: ON
9164 22:54:00.988619 TX_PICG_NEW_MODE: ON
9165 22:54:00.989036 ENABLE_RX_DCM_DPHY: ON
9166 22:54:00.992451 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9167 22:54:00.995555 DUMMY_READ_FOR_TRACKING: OFF
9168 22:54:00.998507 !!! SPM_CONTROL_AFTERK: OFF
9169 22:54:00.998952 !!! SPM could not control APHY
9170 22:54:01.002407 IMPEDANCE_TRACKING: ON
9171 22:54:01.005555 TEMP_SENSOR: ON
9172 22:54:01.006025 HW_SAVE_FOR_SR: OFF
9173 22:54:01.008732 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9174 22:54:01.012074 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9175 22:54:01.015106 Read ODT Tracking: ON
9176 22:54:01.015521 Refresh Rate DeBounce: ON
9177 22:54:01.018413 DFS_NO_QUEUE_FLUSH: ON
9178 22:54:01.021755 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9179 22:54:01.025041 ENABLE_DFS_RUNTIME_MRW: OFF
9180 22:54:01.025459 DDR_RESERVE_NEW_MODE: ON
9181 22:54:01.028454 MR_CBT_SWITCH_FREQ: ON
9182 22:54:01.032025 =========================
9183 22:54:01.049893 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9184 22:54:01.053068 dram_init: ddr_geometry: 2
9185 22:54:01.071223 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9186 22:54:01.074709 dram_init: dram init end (result: 0)
9187 22:54:01.081267 DRAM-K: Full calibration passed in 24600 msecs
9188 22:54:01.084158 MRC: failed to locate region type 0.
9189 22:54:01.084577 DRAM rank0 size:0x100000000,
9190 22:54:01.087840 DRAM rank1 size=0x100000000
9191 22:54:01.097536 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9192 22:54:01.104354 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9193 22:54:01.111000 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9194 22:54:01.120885 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9195 22:54:01.121342 DRAM rank0 size:0x100000000,
9196 22:54:01.124146 DRAM rank1 size=0x100000000
9197 22:54:01.124615 CBMEM:
9198 22:54:01.127464 IMD: root @ 0xfffff000 254 entries.
9199 22:54:01.130878 IMD: root @ 0xffffec00 62 entries.
9200 22:54:01.134037 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9201 22:54:01.140621 WARNING: RO_VPD is uninitialized or empty.
9202 22:54:01.143369 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9203 22:54:01.151264 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9204 22:54:01.164064 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9205 22:54:01.175494 BS: romstage times (exec / console): total (unknown) / 24096 ms
9206 22:54:01.176018
9207 22:54:01.176349
9208 22:54:01.185762 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9209 22:54:01.188859 ARM64: Exception handlers installed.
9210 22:54:01.192208 ARM64: Testing exception
9211 22:54:01.195384 ARM64: Done test exception
9212 22:54:01.196063 Enumerating buses...
9213 22:54:01.199242 Show all devs... Before device enumeration.
9214 22:54:01.201907 Root Device: enabled 1
9215 22:54:01.204961 CPU_CLUSTER: 0: enabled 1
9216 22:54:01.205381 CPU: 00: enabled 1
9217 22:54:01.208847 Compare with tree...
9218 22:54:01.209342 Root Device: enabled 1
9219 22:54:01.211942 CPU_CLUSTER: 0: enabled 1
9220 22:54:01.214882 CPU: 00: enabled 1
9221 22:54:01.215292 Root Device scanning...
9222 22:54:01.218189 scan_static_bus for Root Device
9223 22:54:01.221469 CPU_CLUSTER: 0 enabled
9224 22:54:01.224768 scan_static_bus for Root Device done
9225 22:54:01.228105 scan_bus: bus Root Device finished in 8 msecs
9226 22:54:01.228512 done
9227 22:54:01.234710 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9228 22:54:01.238224 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9229 22:54:01.244933 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9230 22:54:01.250943 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9231 22:54:01.251433 Allocating resources...
9232 22:54:01.254463 Reading resources...
9233 22:54:01.257985 Root Device read_resources bus 0 link: 0
9234 22:54:01.261558 DRAM rank0 size:0x100000000,
9235 22:54:01.262065 DRAM rank1 size=0x100000000
9236 22:54:01.267619 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9237 22:54:01.268118 CPU: 00 missing read_resources
9238 22:54:01.273758 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9239 22:54:01.277102 Root Device read_resources bus 0 link: 0 done
9240 22:54:01.280621 Done reading resources.
9241 22:54:01.283962 Show resources in subtree (Root Device)...After reading.
9242 22:54:01.287189 Root Device child on link 0 CPU_CLUSTER: 0
9243 22:54:01.290398 CPU_CLUSTER: 0 child on link 0 CPU: 00
9244 22:54:01.300379 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9245 22:54:01.300874 CPU: 00
9246 22:54:01.306869 Root Device assign_resources, bus 0 link: 0
9247 22:54:01.310264 CPU_CLUSTER: 0 missing set_resources
9248 22:54:01.313480 Root Device assign_resources, bus 0 link: 0 done
9249 22:54:01.317149 Done setting resources.
9250 22:54:01.319990 Show resources in subtree (Root Device)...After assigning values.
9251 22:54:01.326866 Root Device child on link 0 CPU_CLUSTER: 0
9252 22:54:01.330395 CPU_CLUSTER: 0 child on link 0 CPU: 00
9253 22:54:01.336906 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9254 22:54:01.340244 CPU: 00
9255 22:54:01.340673 Done allocating resources.
9256 22:54:01.346806 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9257 22:54:01.350456 Enabling resources...
9258 22:54:01.350883 done.
9259 22:54:01.353080 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9260 22:54:01.356873 Initializing devices...
9261 22:54:01.357399 Root Device init
9262 22:54:01.359908 init hardware done!
9263 22:54:01.363389 0x00000018: ctrlr->caps
9264 22:54:01.363826 52.000 MHz: ctrlr->f_max
9265 22:54:01.367242 0.400 MHz: ctrlr->f_min
9266 22:54:01.369646 0x40ff8080: ctrlr->voltages
9267 22:54:01.370061 sclk: 390625
9268 22:54:01.370416 Bus Width = 1
9269 22:54:01.372837 sclk: 390625
9270 22:54:01.373250 Bus Width = 1
9271 22:54:01.376354 Early init status = 3
9272 22:54:01.380002 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9273 22:54:01.383699 in-header: 03 fc 00 00 01 00 00 00
9274 22:54:01.387158 in-data: 00
9275 22:54:01.390657 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9276 22:54:01.396180 in-header: 03 fd 00 00 00 00 00 00
9277 22:54:01.399305 in-data:
9278 22:54:01.402413 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9279 22:54:01.407080 in-header: 03 fc 00 00 01 00 00 00
9280 22:54:01.410646 in-data: 00
9281 22:54:01.413566 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9282 22:54:01.419578 in-header: 03 fd 00 00 00 00 00 00
9283 22:54:01.422722 in-data:
9284 22:54:01.426043 [SSUSB] Setting up USB HOST controller...
9285 22:54:01.429083 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9286 22:54:01.432384 [SSUSB] phy power-on done.
9287 22:54:01.435528 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9288 22:54:01.442507 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9289 22:54:01.445561 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9290 22:54:01.452402 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9291 22:54:01.458643 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9292 22:54:01.465795 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9293 22:54:01.472267 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9294 22:54:01.478541 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9295 22:54:01.481581 SPM: binary array size = 0x9dc
9296 22:54:01.485379 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9297 22:54:01.491882 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9298 22:54:01.498469 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9299 22:54:01.505390 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9300 22:54:01.508408 configure_display: Starting display init
9301 22:54:01.542872 anx7625_power_on_init: Init interface.
9302 22:54:01.545896 anx7625_disable_pd_protocol: Disabled PD feature.
9303 22:54:01.549164 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9304 22:54:01.577055 anx7625_start_dp_work: Secure OCM version=00
9305 22:54:01.580240 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9306 22:54:01.595313 sp_tx_get_edid_block: EDID Block = 1
9307 22:54:01.697852 Extracted contents:
9308 22:54:01.701099 header: 00 ff ff ff ff ff ff 00
9309 22:54:01.704316 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9310 22:54:01.707780 version: 01 04
9311 22:54:01.710922 basic params: 95 1f 11 78 0a
9312 22:54:01.714143 chroma info: 76 90 94 55 54 90 27 21 50 54
9313 22:54:01.717141 established: 00 00 00
9314 22:54:01.723768 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9315 22:54:01.730976 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9316 22:54:01.734153 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9317 22:54:01.740635 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9318 22:54:01.747087 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9319 22:54:01.750661 extensions: 00
9320 22:54:01.751206 checksum: fb
9321 22:54:01.751691
9322 22:54:01.756868 Manufacturer: IVO Model 57d Serial Number 0
9323 22:54:01.757324 Made week 0 of 2020
9324 22:54:01.760787 EDID version: 1.4
9325 22:54:01.761354 Digital display
9326 22:54:01.763529 6 bits per primary color channel
9327 22:54:01.763944 DisplayPort interface
9328 22:54:01.766822 Maximum image size: 31 cm x 17 cm
9329 22:54:01.769792 Gamma: 220%
9330 22:54:01.770237 Check DPMS levels
9331 22:54:01.776523 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9332 22:54:01.779901 First detailed timing is preferred timing
9333 22:54:01.783530 Established timings supported:
9334 22:54:01.784035 Standard timings supported:
9335 22:54:01.786372 Detailed timings
9336 22:54:01.789653 Hex of detail: 383680a07038204018303c0035ae10000019
9337 22:54:01.796492 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9338 22:54:01.799528 0780 0798 07c8 0820 hborder 0
9339 22:54:01.802994 0438 043b 0447 0458 vborder 0
9340 22:54:01.806156 -hsync -vsync
9341 22:54:01.806650 Did detailed timing
9342 22:54:01.813073 Hex of detail: 000000000000000000000000000000000000
9343 22:54:01.816244 Manufacturer-specified data, tag 0
9344 22:54:01.819462 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9345 22:54:01.822971 ASCII string: InfoVision
9346 22:54:01.826368 Hex of detail: 000000fe00523134304e574635205248200a
9347 22:54:01.829934 ASCII string: R140NWF5 RH
9348 22:54:01.830519 Checksum
9349 22:54:01.832916 Checksum: 0xfb (valid)
9350 22:54:01.836313 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9351 22:54:01.839155 DSI data_rate: 832800000 bps
9352 22:54:01.846387 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9353 22:54:01.849186 anx7625_parse_edid: pixelclock(138800).
9354 22:54:01.852593 hactive(1920), hsync(48), hfp(24), hbp(88)
9355 22:54:01.856007 vactive(1080), vsync(12), vfp(3), vbp(17)
9356 22:54:01.859724 anx7625_dsi_config: config dsi.
9357 22:54:01.866314 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9358 22:54:01.879932 anx7625_dsi_config: success to config DSI
9359 22:54:01.883375 anx7625_dp_start: MIPI phy setup OK.
9360 22:54:01.886654 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9361 22:54:01.889634 mtk_ddp_mode_set invalid vrefresh 60
9362 22:54:01.893012 main_disp_path_setup
9363 22:54:01.893557 ovl_layer_smi_id_en
9364 22:54:01.896422 ovl_layer_smi_id_en
9365 22:54:01.896969 ccorr_config
9366 22:54:01.897325 aal_config
9367 22:54:01.899348 gamma_config
9368 22:54:01.899796 postmask_config
9369 22:54:01.902614 dither_config
9370 22:54:01.905825 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9371 22:54:01.912571 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9372 22:54:01.916019 Root Device init finished in 555 msecs
9373 22:54:01.919469 CPU_CLUSTER: 0 init
9374 22:54:01.926028 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9375 22:54:01.932288 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9376 22:54:01.932697 APU_MBOX 0x190000b0 = 0x10001
9377 22:54:01.935522 APU_MBOX 0x190001b0 = 0x10001
9378 22:54:01.939123 APU_MBOX 0x190005b0 = 0x10001
9379 22:54:01.942548 APU_MBOX 0x190006b0 = 0x10001
9380 22:54:01.949135 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9381 22:54:01.959039 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9382 22:54:01.970982 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9383 22:54:01.977425 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9384 22:54:01.989379 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9385 22:54:01.998528 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9386 22:54:02.001801 CPU_CLUSTER: 0 init finished in 81 msecs
9387 22:54:02.005142 Devices initialized
9388 22:54:02.008570 Show all devs... After init.
9389 22:54:02.009151 Root Device: enabled 1
9390 22:54:02.011933 CPU_CLUSTER: 0: enabled 1
9391 22:54:02.014928 CPU: 00: enabled 1
9392 22:54:02.018215 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9393 22:54:02.021453 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9394 22:54:02.024815 ELOG: NV offset 0x57f000 size 0x1000
9395 22:54:02.031922 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9396 22:54:02.038144 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9397 22:54:02.042025 ELOG: Event(17) added with size 13 at 2024-05-18 22:54:02 UTC
9398 22:54:02.047983 out: cmd=0x121: 03 db 21 01 00 00 00 00
9399 22:54:02.051605 in-header: 03 80 00 00 2c 00 00 00
9400 22:54:02.064574 in-data: be 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9401 22:54:02.067824 ELOG: Event(A1) added with size 10 at 2024-05-18 22:54:02 UTC
9402 22:54:02.074882 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9403 22:54:02.080782 ELOG: Event(A0) added with size 9 at 2024-05-18 22:54:02 UTC
9404 22:54:02.084662 elog_add_boot_reason: Logged dev mode boot
9405 22:54:02.090751 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9406 22:54:02.091161 Finalize devices...
9407 22:54:02.094288 Devices finalized
9408 22:54:02.097587 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9409 22:54:02.100765 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9410 22:54:02.104432 in-header: 03 07 00 00 08 00 00 00
9411 22:54:02.107445 in-data: aa e4 47 04 13 02 00 00
9412 22:54:02.110818 Chrome EC: UHEPI supported
9413 22:54:02.117548 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9414 22:54:02.120611 in-header: 03 a9 00 00 08 00 00 00
9415 22:54:02.124156 in-data: 84 60 60 08 00 00 00 00
9416 22:54:02.130557 ELOG: Event(91) added with size 10 at 2024-05-18 22:54:02 UTC
9417 22:54:02.134149 Chrome EC: clear events_b mask to 0x0000000020004000
9418 22:54:02.140382 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9419 22:54:02.144109 in-header: 03 fd 00 00 00 00 00 00
9420 22:54:02.144515 in-data:
9421 22:54:02.150866 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9422 22:54:02.154588 Writing coreboot table at 0xffe64000
9423 22:54:02.157650 0. 000000000010a000-0000000000113fff: RAMSTAGE
9424 22:54:02.161249 1. 0000000040000000-00000000400fffff: RAM
9425 22:54:02.167402 2. 0000000040100000-000000004032afff: RAMSTAGE
9426 22:54:02.170959 3. 000000004032b000-00000000545fffff: RAM
9427 22:54:02.174012 4. 0000000054600000-000000005465ffff: BL31
9428 22:54:02.177770 5. 0000000054660000-00000000ffe63fff: RAM
9429 22:54:02.184030 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9430 22:54:02.187726 7. 0000000100000000-000000023fffffff: RAM
9431 22:54:02.191055 Passing 5 GPIOs to payload:
9432 22:54:02.194027 NAME | PORT | POLARITY | VALUE
9433 22:54:02.200343 EC in RW | 0x000000aa | low | undefined
9434 22:54:02.203852 EC interrupt | 0x00000005 | low | undefined
9435 22:54:02.206989 TPM interrupt | 0x000000ab | high | undefined
9436 22:54:02.213651 SD card detect | 0x00000011 | high | undefined
9437 22:54:02.217057 speaker enable | 0x00000093 | high | undefined
9438 22:54:02.220155 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9439 22:54:02.224277 in-header: 03 f9 00 00 02 00 00 00
9440 22:54:02.227720 in-data: 02 00
9441 22:54:02.230595 ADC[4]: Raw value=901922 ID=7
9442 22:54:02.233681 ADC[3]: Raw value=213652 ID=1
9443 22:54:02.234096 RAM Code: 0x71
9444 22:54:02.237740 ADC[6]: Raw value=75036 ID=0
9445 22:54:02.241006 ADC[5]: Raw value=213652 ID=1
9446 22:54:02.241417 SKU Code: 0x1
9447 22:54:02.247211 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7fa8
9448 22:54:02.247766 coreboot table: 964 bytes.
9449 22:54:02.250479 IMD ROOT 0. 0xfffff000 0x00001000
9450 22:54:02.253747 IMD SMALL 1. 0xffffe000 0x00001000
9451 22:54:02.257050 RO MCACHE 2. 0xffffc000 0x00001104
9452 22:54:02.260420 CONSOLE 3. 0xfff7c000 0x00080000
9453 22:54:02.263482 FMAP 4. 0xfff7b000 0x00000452
9454 22:54:02.267138 TIME STAMP 5. 0xfff7a000 0x00000910
9455 22:54:02.270082 VBOOT WORK 6. 0xfff66000 0x00014000
9456 22:54:02.273764 RAMOOPS 7. 0xffe66000 0x00100000
9457 22:54:02.276953 COREBOOT 8. 0xffe64000 0x00002000
9458 22:54:02.279994 IMD small region:
9459 22:54:02.283336 IMD ROOT 0. 0xffffec00 0x00000400
9460 22:54:02.287082 VPD 1. 0xffffeb80 0x0000006c
9461 22:54:02.290019 MMC STATUS 2. 0xffffeb60 0x00000004
9462 22:54:02.297157 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9463 22:54:02.302773 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9464 22:54:02.341409 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9465 22:54:02.344703 Checking segment from ROM address 0x40100000
9466 22:54:02.348061 Checking segment from ROM address 0x4010001c
9467 22:54:02.355174 Loading segment from ROM address 0x40100000
9468 22:54:02.355601 code (compression=0)
9469 22:54:02.364797 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9470 22:54:02.371622 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9471 22:54:02.372037 it's not compressed!
9472 22:54:02.378392 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9473 22:54:02.384639 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9474 22:54:02.401737 Loading segment from ROM address 0x4010001c
9475 22:54:02.402237 Entry Point 0x80000000
9476 22:54:02.405123 Loaded segments
9477 22:54:02.408719 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9478 22:54:02.414840 Jumping to boot code at 0x80000000(0xffe64000)
9479 22:54:02.422142 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9480 22:54:02.428430 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9481 22:54:02.436312 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9482 22:54:02.439829 Checking segment from ROM address 0x40100000
9483 22:54:02.443676 Checking segment from ROM address 0x4010001c
9484 22:54:02.449612 Loading segment from ROM address 0x40100000
9485 22:54:02.450207 code (compression=1)
9486 22:54:02.456558 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9487 22:54:02.466217 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9488 22:54:02.466721 using LZMA
9489 22:54:02.474806 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9490 22:54:02.481685 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9491 22:54:02.484553 Loading segment from ROM address 0x4010001c
9492 22:54:02.484982 Entry Point 0x54601000
9493 22:54:02.488813 Loaded segments
9494 22:54:02.491501 NOTICE: MT8192 bl31_setup
9495 22:54:02.498568 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9496 22:54:02.501885 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9497 22:54:02.504925 WARNING: region 0:
9498 22:54:02.508254 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 22:54:02.508712 WARNING: region 1:
9500 22:54:02.515254 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9501 22:54:02.519010 WARNING: region 2:
9502 22:54:02.521835 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9503 22:54:02.524981 WARNING: region 3:
9504 22:54:02.528296 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9505 22:54:02.531698 WARNING: region 4:
9506 22:54:02.538271 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9507 22:54:02.538816 WARNING: region 5:
9508 22:54:02.541168 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9509 22:54:02.544928 WARNING: region 6:
9510 22:54:02.548176 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9511 22:54:02.551133 WARNING: region 7:
9512 22:54:02.554740 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9513 22:54:02.561070 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9514 22:54:02.564326 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9515 22:54:02.571271 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9516 22:54:02.574296 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9517 22:54:02.577737 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9518 22:54:02.584077 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9519 22:54:02.587905 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9520 22:54:02.590965 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9521 22:54:02.597332 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9522 22:54:02.600948 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9523 22:54:02.607476 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9524 22:54:02.610772 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9525 22:54:02.614157 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9526 22:54:02.620564 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9527 22:54:02.624091 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9528 22:54:02.630498 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9529 22:54:02.633829 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9530 22:54:02.637012 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9531 22:54:02.644076 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9532 22:54:02.647476 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9533 22:54:02.653451 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9534 22:54:02.656992 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9535 22:54:02.660387 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9536 22:54:02.666618 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9537 22:54:02.669936 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9538 22:54:02.676677 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9539 22:54:02.680374 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9540 22:54:02.683350 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9541 22:54:02.689376 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9542 22:54:02.692854 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9543 22:54:02.699687 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9544 22:54:02.703177 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9545 22:54:02.706110 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9546 22:54:02.712557 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9547 22:54:02.715667 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9548 22:54:02.719450 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9549 22:54:02.722694 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9550 22:54:02.728991 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9551 22:54:02.732984 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9552 22:54:02.735585 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9553 22:54:02.739619 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9554 22:54:02.746382 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9555 22:54:02.749067 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9556 22:54:02.752844 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9557 22:54:02.755837 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9558 22:54:02.762473 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9559 22:54:02.765642 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9560 22:54:02.768928 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9561 22:54:02.775367 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9562 22:54:02.779543 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9563 22:54:02.782142 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9564 22:54:02.789361 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9565 22:54:02.792314 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9566 22:54:02.798774 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9567 22:54:02.802271 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9568 22:54:02.809335 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9569 22:54:02.811966 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9570 22:54:02.818962 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9571 22:54:02.821817 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9572 22:54:02.825452 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9573 22:54:02.831347 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9574 22:54:02.834856 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9575 22:54:02.841633 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9576 22:54:02.845003 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9577 22:54:02.851275 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9578 22:54:02.854535 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9579 22:54:02.861268 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9580 22:54:02.864812 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9581 22:54:02.867855 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9582 22:54:02.874434 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9583 22:54:02.877822 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9584 22:54:02.884640 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9585 22:54:02.888031 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9586 22:54:02.894665 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9587 22:54:02.897437 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9588 22:54:02.904457 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9589 22:54:02.907676 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9590 22:54:02.911069 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9591 22:54:02.917767 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9592 22:54:02.921190 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9593 22:54:02.927607 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9594 22:54:02.930696 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9595 22:54:02.937916 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9596 22:54:02.940952 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9597 22:54:02.947266 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9598 22:54:02.950898 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9599 22:54:02.954008 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9600 22:54:02.960642 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9601 22:54:02.963796 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9602 22:54:02.970523 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9603 22:54:02.973840 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9604 22:54:02.980398 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9605 22:54:02.983662 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9606 22:54:02.990433 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9607 22:54:02.993735 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9608 22:54:02.997236 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9609 22:54:03.003395 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9610 22:54:03.006868 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9611 22:54:03.010381 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9612 22:54:03.013589 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9613 22:54:03.020256 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9614 22:54:03.023929 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9615 22:54:03.030428 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9616 22:54:03.033222 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9617 22:54:03.036610 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9618 22:54:03.043007 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9619 22:54:03.046356 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9620 22:54:03.053354 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9621 22:54:03.056655 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9622 22:54:03.059859 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9623 22:54:03.066408 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9624 22:54:03.069910 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9625 22:54:03.076272 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9626 22:54:03.079738 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9627 22:54:03.086273 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9628 22:54:03.089582 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9629 22:54:03.093026 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9630 22:54:03.096743 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9631 22:54:03.102909 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9632 22:54:03.105829 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9633 22:54:03.109098 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9634 22:54:03.112693 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9635 22:54:03.119524 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9636 22:54:03.122582 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9637 22:54:03.125764 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9638 22:54:03.132443 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9639 22:54:03.135887 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9640 22:54:03.142286 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9641 22:54:03.145720 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9642 22:54:03.152416 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9643 22:54:03.155360 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9644 22:54:03.159155 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9645 22:54:03.165499 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9646 22:54:03.168783 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9647 22:54:03.172337 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9648 22:54:03.178719 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9649 22:54:03.181971 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9650 22:54:03.188916 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9651 22:54:03.192146 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9652 22:54:03.195636 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9653 22:54:03.202036 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9654 22:54:03.205328 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9655 22:54:03.211717 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9656 22:54:03.215156 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9657 22:54:03.218236 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9658 22:54:03.224945 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9659 22:54:03.228620 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9660 22:54:03.234840 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9661 22:54:03.238096 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9662 22:54:03.241383 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9663 22:54:03.248561 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9664 22:54:03.251429 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9665 22:54:03.258011 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9666 22:54:03.261013 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9667 22:54:03.265238 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9668 22:54:03.271307 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9669 22:54:03.274526 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9670 22:54:03.281359 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9671 22:54:03.284977 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9672 22:54:03.287492 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9673 22:54:03.294521 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9674 22:54:03.297764 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9675 22:54:03.305018 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9676 22:54:03.307177 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9677 22:54:03.310804 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9678 22:54:03.317069 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9679 22:54:03.320645 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9680 22:54:03.327014 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9681 22:54:03.330275 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9682 22:54:03.333634 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9683 22:54:03.340783 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9684 22:54:03.343283 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9685 22:54:03.350641 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9686 22:54:03.353999 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9687 22:54:03.357172 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9688 22:54:03.363383 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9689 22:54:03.366888 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9690 22:54:03.373440 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9691 22:54:03.376855 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9692 22:54:03.379981 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9693 22:54:03.386524 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9694 22:54:03.389958 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9695 22:54:03.397101 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9696 22:54:03.399767 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9697 22:54:03.403005 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9698 22:54:03.409561 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9699 22:54:03.412866 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9700 22:54:03.419825 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9701 22:54:03.422795 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9702 22:54:03.426087 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9703 22:54:03.432763 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9704 22:54:03.436138 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9705 22:54:03.442583 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9706 22:54:03.445996 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9707 22:54:03.452869 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9708 22:54:03.456049 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9709 22:54:03.459127 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9710 22:54:03.466075 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9711 22:54:03.468959 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9712 22:54:03.475695 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9713 22:54:03.479532 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9714 22:54:03.485480 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9715 22:54:03.489051 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9716 22:54:03.492006 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9717 22:54:03.498856 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9718 22:54:03.502284 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9719 22:54:03.508491 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9720 22:54:03.511798 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9721 22:54:03.518560 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9722 22:54:03.521600 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9723 22:54:03.525107 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9724 22:54:03.531527 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9725 22:54:03.534990 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9726 22:54:03.541575 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9727 22:54:03.544949 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9728 22:54:03.548238 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9729 22:54:03.555016 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9730 22:54:03.558227 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9731 22:54:03.564779 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9732 22:54:03.568332 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9733 22:54:03.575086 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9734 22:54:03.578239 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9735 22:54:03.581587 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9736 22:54:03.587994 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9737 22:54:03.591207 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9738 22:54:03.598016 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9739 22:54:03.601149 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9740 22:54:03.607496 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9741 22:54:03.611577 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9742 22:54:03.614653 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9743 22:54:03.617609 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9744 22:54:03.623902 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9745 22:54:03.627297 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9746 22:54:03.630373 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9747 22:54:03.637357 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9748 22:54:03.640814 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9749 22:54:03.644156 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9750 22:54:03.650613 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9751 22:54:03.653832 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9752 22:54:03.656903 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9753 22:54:03.664218 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9754 22:54:03.667240 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9755 22:54:03.673408 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9756 22:54:03.676576 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9757 22:54:03.680207 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9758 22:54:03.686653 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9759 22:54:03.690125 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9760 22:54:03.697226 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9761 22:54:03.699945 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9762 22:54:03.703019 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9763 22:54:03.710021 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9764 22:54:03.713680 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9765 22:54:03.716327 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9766 22:54:03.722977 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9767 22:54:03.726265 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9768 22:54:03.729797 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9769 22:54:03.736348 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9770 22:54:03.739504 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9771 22:54:03.746028 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9772 22:54:03.749611 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9773 22:54:03.752845 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9774 22:54:03.759633 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9775 22:54:03.762614 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9776 22:54:03.766029 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9777 22:54:03.772600 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9778 22:54:03.775878 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9779 22:54:03.782949 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9780 22:54:03.785757 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9781 22:54:03.789558 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9782 22:54:03.793069 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9783 22:54:03.799685 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9784 22:54:03.803142 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9785 22:54:03.805673 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9786 22:54:03.808709 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9787 22:54:03.815624 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9788 22:54:03.819397 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9789 22:54:03.822636 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9790 22:54:03.825574 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9791 22:54:03.831968 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9792 22:54:03.835325 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9793 22:54:03.838814 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9794 22:54:03.842252 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9795 22:54:03.849293 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9796 22:54:03.852185 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9797 22:54:03.858573 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9798 22:54:03.862237 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9799 22:54:03.869015 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9800 22:54:03.872185 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9801 22:54:03.875057 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9802 22:54:03.882131 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9803 22:54:03.885524 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9804 22:54:03.891709 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9805 22:54:03.895559 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9806 22:54:03.901458 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9807 22:54:03.905125 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9808 22:54:03.908213 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9809 22:54:03.914557 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9810 22:54:03.918268 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9811 22:54:03.924940 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9812 22:54:03.928187 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9813 22:54:03.931106 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9814 22:54:03.937802 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9815 22:54:03.940992 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9816 22:54:03.948113 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9817 22:54:03.950845 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9818 22:54:03.954457 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9819 22:54:03.961650 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9820 22:54:03.963988 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9821 22:54:03.971254 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9822 22:54:03.974348 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9823 22:54:03.980815 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9824 22:54:03.984160 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9825 22:54:03.987478 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9826 22:54:03.993913 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9827 22:54:03.997874 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9828 22:54:04.003610 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9829 22:54:04.007490 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9830 22:54:04.014114 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9831 22:54:04.017318 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9832 22:54:04.020441 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9833 22:54:04.026744 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9834 22:54:04.030020 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9835 22:54:04.036796 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9836 22:54:04.040036 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9837 22:54:04.043041 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9838 22:54:04.050363 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9839 22:54:04.053080 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9840 22:54:04.059739 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9841 22:54:04.062860 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9842 22:54:04.069808 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9843 22:54:04.072809 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9844 22:54:04.076799 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9845 22:54:04.083027 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9846 22:54:04.086565 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9847 22:54:04.092691 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9848 22:54:04.096337 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9849 22:54:04.102437 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9850 22:54:04.106015 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9851 22:54:04.109081 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9852 22:54:04.115393 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9853 22:54:04.118923 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9854 22:54:04.125640 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9855 22:54:04.129114 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9856 22:54:04.132182 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9857 22:54:04.138819 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9858 22:54:04.142270 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9859 22:54:04.148993 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9860 22:54:04.152330 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9861 22:54:04.155929 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9862 22:54:04.162061 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9863 22:54:04.165311 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9864 22:54:04.171984 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9865 22:54:04.175298 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9866 22:54:04.178888 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9867 22:54:04.185074 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9868 22:54:04.188593 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9869 22:54:04.195497 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9870 22:54:04.198609 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9871 22:54:04.204712 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9872 22:54:04.208723 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9873 22:54:04.215487 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9874 22:54:04.218446 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9875 22:54:04.221822 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9876 22:54:04.228213 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9877 22:54:04.231726 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9878 22:54:04.238596 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9879 22:54:04.241940 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9880 22:54:04.248723 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9881 22:54:04.251821 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9882 22:54:04.255164 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9883 22:54:04.261733 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9884 22:54:04.264862 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9885 22:54:04.271172 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9886 22:54:04.274846 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9887 22:54:04.281350 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9888 22:54:04.285023 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9889 22:54:04.291093 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9890 22:54:04.294275 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9891 22:54:04.297495 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9892 22:54:04.304205 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9893 22:54:04.307388 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9894 22:54:04.314359 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9895 22:54:04.317567 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9896 22:54:04.324431 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9897 22:54:04.327425 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9898 22:54:04.334117 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9899 22:54:04.337594 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9900 22:54:04.343566 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9901 22:54:04.347141 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9902 22:54:04.350694 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9903 22:54:04.357294 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9904 22:54:04.360174 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9905 22:54:04.367074 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9906 22:54:04.370091 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9907 22:54:04.377184 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9908 22:54:04.380469 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9909 22:54:04.386665 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9910 22:54:04.389846 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9911 22:54:04.393218 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9912 22:54:04.399895 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9913 22:54:04.403124 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9914 22:54:04.409999 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9915 22:54:04.412926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9916 22:54:04.416658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9917 22:54:04.423152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9918 22:54:04.426620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9919 22:54:04.433427 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9920 22:54:04.436264 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9921 22:54:04.442636 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9922 22:54:04.446183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9923 22:54:04.452947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9924 22:54:04.456434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9925 22:54:04.462925 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9926 22:54:04.466288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9927 22:54:04.472789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9928 22:54:04.476040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9929 22:54:04.482522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9930 22:54:04.486136 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9931 22:54:04.492665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9932 22:54:04.495554 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9933 22:54:04.502637 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9934 22:54:04.505328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9935 22:54:04.512370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9936 22:54:04.515630 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9937 22:54:04.522715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9938 22:54:04.525377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9939 22:54:04.531927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9940 22:54:04.535821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9941 22:54:04.542025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9942 22:54:04.545518 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9943 22:54:04.552184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9944 22:54:04.555218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9945 22:54:04.561934 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9946 22:54:04.565163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9947 22:54:04.571970 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9948 22:54:04.572711 INFO: [APUAPC] vio 0
9949 22:54:04.578354 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9950 22:54:04.581591 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9951 22:54:04.585489 INFO: [APUAPC] D0_APC_0: 0x400510
9952 22:54:04.588771 INFO: [APUAPC] D0_APC_1: 0x0
9953 22:54:04.591581 INFO: [APUAPC] D0_APC_2: 0x1540
9954 22:54:04.595105 INFO: [APUAPC] D0_APC_3: 0x0
9955 22:54:04.598148 INFO: [APUAPC] D1_APC_0: 0xffffffff
9956 22:54:04.601910 INFO: [APUAPC] D1_APC_1: 0xffffffff
9957 22:54:04.604774 INFO: [APUAPC] D1_APC_2: 0x3fffff
9958 22:54:04.608330 INFO: [APUAPC] D1_APC_3: 0x0
9959 22:54:04.611352 INFO: [APUAPC] D2_APC_0: 0xffffffff
9960 22:54:04.615146 INFO: [APUAPC] D2_APC_1: 0xffffffff
9961 22:54:04.618031 INFO: [APUAPC] D2_APC_2: 0x3fffff
9962 22:54:04.621188 INFO: [APUAPC] D2_APC_3: 0x0
9963 22:54:04.624718 INFO: [APUAPC] D3_APC_0: 0xffffffff
9964 22:54:04.628011 INFO: [APUAPC] D3_APC_1: 0xffffffff
9965 22:54:04.631157 INFO: [APUAPC] D3_APC_2: 0x3fffff
9966 22:54:04.634846 INFO: [APUAPC] D3_APC_3: 0x0
9967 22:54:04.637852 INFO: [APUAPC] D4_APC_0: 0xffffffff
9968 22:54:04.641348 INFO: [APUAPC] D4_APC_1: 0xffffffff
9969 22:54:04.644478 INFO: [APUAPC] D4_APC_2: 0x3fffff
9970 22:54:04.647641 INFO: [APUAPC] D4_APC_3: 0x0
9971 22:54:04.651020 INFO: [APUAPC] D5_APC_0: 0xffffffff
9972 22:54:04.654841 INFO: [APUAPC] D5_APC_1: 0xffffffff
9973 22:54:04.658076 INFO: [APUAPC] D5_APC_2: 0x3fffff
9974 22:54:04.658773 INFO: [APUAPC] D5_APC_3: 0x0
9975 22:54:04.664133 INFO: [APUAPC] D6_APC_0: 0xffffffff
9976 22:54:04.667854 INFO: [APUAPC] D6_APC_1: 0xffffffff
9977 22:54:04.671006 INFO: [APUAPC] D6_APC_2: 0x3fffff
9978 22:54:04.671523 INFO: [APUAPC] D6_APC_3: 0x0
9979 22:54:04.673904 INFO: [APUAPC] D7_APC_0: 0xffffffff
9980 22:54:04.680546 INFO: [APUAPC] D7_APC_1: 0xffffffff
9981 22:54:04.684061 INFO: [APUAPC] D7_APC_2: 0x3fffff
9982 22:54:04.684468 INFO: [APUAPC] D7_APC_3: 0x0
9983 22:54:04.687317 INFO: [APUAPC] D8_APC_0: 0xffffffff
9984 22:54:04.690732 INFO: [APUAPC] D8_APC_1: 0xffffffff
9985 22:54:04.693948 INFO: [APUAPC] D8_APC_2: 0x3fffff
9986 22:54:04.697667 INFO: [APUAPC] D8_APC_3: 0x0
9987 22:54:04.701016 INFO: [APUAPC] D9_APC_0: 0xffffffff
9988 22:54:04.704029 INFO: [APUAPC] D9_APC_1: 0xffffffff
9989 22:54:04.707066 INFO: [APUAPC] D9_APC_2: 0x3fffff
9990 22:54:04.710437 INFO: [APUAPC] D9_APC_3: 0x0
9991 22:54:04.713558 INFO: [APUAPC] D10_APC_0: 0xffffffff
9992 22:54:04.716976 INFO: [APUAPC] D10_APC_1: 0xffffffff
9993 22:54:04.720518 INFO: [APUAPC] D10_APC_2: 0x3fffff
9994 22:54:04.723864 INFO: [APUAPC] D10_APC_3: 0x0
9995 22:54:04.726818 INFO: [APUAPC] D11_APC_0: 0xffffffff
9996 22:54:04.730567 INFO: [APUAPC] D11_APC_1: 0xffffffff
9997 22:54:04.733584 INFO: [APUAPC] D11_APC_2: 0x3fffff
9998 22:54:04.737338 INFO: [APUAPC] D11_APC_3: 0x0
9999 22:54:04.740730 INFO: [APUAPC] D12_APC_0: 0xffffffff
10000 22:54:04.746640 INFO: [APUAPC] D12_APC_1: 0xffffffff
10001 22:54:04.750058 INFO: [APUAPC] D12_APC_2: 0x3fffff
10002 22:54:04.750569 INFO: [APUAPC] D12_APC_3: 0x0
10003 22:54:04.756582 INFO: [APUAPC] D13_APC_0: 0xffffffff
10004 22:54:04.759733 INFO: [APUAPC] D13_APC_1: 0xffffffff
10005 22:54:04.763322 INFO: [APUAPC] D13_APC_2: 0x3fffff
10006 22:54:04.766335 INFO: [APUAPC] D13_APC_3: 0x0
10007 22:54:04.769646 INFO: [APUAPC] D14_APC_0: 0xffffffff
10008 22:54:04.773273 INFO: [APUAPC] D14_APC_1: 0xffffffff
10009 22:54:04.776803 INFO: [APUAPC] D14_APC_2: 0x3fffff
10010 22:54:04.779707 INFO: [APUAPC] D14_APC_3: 0x0
10011 22:54:04.784102 INFO: [APUAPC] D15_APC_0: 0xffffffff
10012 22:54:04.785971 INFO: [APUAPC] D15_APC_1: 0xffffffff
10013 22:54:04.789634 INFO: [APUAPC] D15_APC_2: 0x3fffff
10014 22:54:04.792892 INFO: [APUAPC] D15_APC_3: 0x0
10015 22:54:04.793346 INFO: [APUAPC] APC_CON: 0x4
10016 22:54:04.796146 INFO: [NOCDAPC] D0_APC_0: 0x0
10017 22:54:04.799825 INFO: [NOCDAPC] D0_APC_1: 0x0
10018 22:54:04.802911 INFO: [NOCDAPC] D1_APC_0: 0x0
10019 22:54:04.805841 INFO: [NOCDAPC] D1_APC_1: 0xfff
10020 22:54:04.809498 INFO: [NOCDAPC] D2_APC_0: 0x0
10021 22:54:04.812443 INFO: [NOCDAPC] D2_APC_1: 0xfff
10022 22:54:04.816149 INFO: [NOCDAPC] D3_APC_0: 0x0
10023 22:54:04.818983 INFO: [NOCDAPC] D3_APC_1: 0xfff
10024 22:54:04.822924 INFO: [NOCDAPC] D4_APC_0: 0x0
10025 22:54:04.826247 INFO: [NOCDAPC] D4_APC_1: 0xfff
10026 22:54:04.826811 INFO: [NOCDAPC] D5_APC_0: 0x0
10027 22:54:04.829312 INFO: [NOCDAPC] D5_APC_1: 0xfff
10028 22:54:04.832178 INFO: [NOCDAPC] D6_APC_0: 0x0
10029 22:54:04.836050 INFO: [NOCDAPC] D6_APC_1: 0xfff
10030 22:54:04.838973 INFO: [NOCDAPC] D7_APC_0: 0x0
10031 22:54:04.841952 INFO: [NOCDAPC] D7_APC_1: 0xfff
10032 22:54:04.845598 INFO: [NOCDAPC] D8_APC_0: 0x0
10033 22:54:04.849441 INFO: [NOCDAPC] D8_APC_1: 0xfff
10034 22:54:04.851959 INFO: [NOCDAPC] D9_APC_0: 0x0
10035 22:54:04.855619 INFO: [NOCDAPC] D9_APC_1: 0xfff
10036 22:54:04.859439 INFO: [NOCDAPC] D10_APC_0: 0x0
10037 22:54:04.862216 INFO: [NOCDAPC] D10_APC_1: 0xfff
10038 22:54:04.862785 INFO: [NOCDAPC] D11_APC_0: 0x0
10039 22:54:04.865356 INFO: [NOCDAPC] D11_APC_1: 0xfff
10040 22:54:04.869296 INFO: [NOCDAPC] D12_APC_0: 0x0
10041 22:54:04.872288 INFO: [NOCDAPC] D12_APC_1: 0xfff
10042 22:54:04.875426 INFO: [NOCDAPC] D13_APC_0: 0x0
10043 22:54:04.879041 INFO: [NOCDAPC] D13_APC_1: 0xfff
10044 22:54:04.882002 INFO: [NOCDAPC] D14_APC_0: 0x0
10045 22:54:04.885597 INFO: [NOCDAPC] D14_APC_1: 0xfff
10046 22:54:04.888489 INFO: [NOCDAPC] D15_APC_0: 0x0
10047 22:54:04.891753 INFO: [NOCDAPC] D15_APC_1: 0xfff
10048 22:54:04.894916 INFO: [NOCDAPC] APC_CON: 0x4
10049 22:54:04.898478 INFO: [APUAPC] set_apusys_apc done
10050 22:54:04.901594 INFO: [DEVAPC] devapc_init done
10051 22:54:04.905243 INFO: GICv3 without legacy support detected.
10052 22:54:04.908588 INFO: ARM GICv3 driver initialized in EL3
10053 22:54:04.911304 INFO: Maximum SPI INTID supported: 639
10054 22:54:04.918091 INFO: BL31: Initializing runtime services
10055 22:54:04.921606 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10056 22:54:04.925176 INFO: SPM: enable CPC mode
10057 22:54:04.931098 INFO: mcdi ready for mcusys-off-idle and system suspend
10058 22:54:04.934987 INFO: BL31: Preparing for EL3 exit to normal world
10059 22:54:04.938087 INFO: Entry point address = 0x80000000
10060 22:54:04.941075 INFO: SPSR = 0x8
10061 22:54:04.947011
10062 22:54:04.947556
10063 22:54:04.947917
10064 22:54:04.950075 Starting depthcharge on Spherion...
10065 22:54:04.950565
10066 22:54:04.950924 Wipe memory regions:
10067 22:54:04.951255
10068 22:54:04.953593 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10069 22:54:04.954114 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10070 22:54:04.954617 Setting prompt string to ['asurada:']
10071 22:54:04.955035 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10072 22:54:04.955733 [0x00000040000000, 0x00000054600000)
10073 22:54:05.075486
10074 22:54:05.076038 [0x00000054660000, 0x00000080000000)
10075 22:54:05.335820
10076 22:54:05.335973 [0x000000821a7280, 0x000000ffe64000)
10077 22:54:06.080093
10078 22:54:06.080331 [0x00000100000000, 0x00000240000000)
10079 22:54:07.970707
10080 22:54:07.973724 Initializing XHCI USB controller at 0x11200000.
10081 22:54:09.012774
10082 22:54:09.015727 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10083 22:54:09.016188
10084 22:54:09.016547
10085 22:54:09.017358 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10087 22:54:09.118579 asurada: tftpboot 192.168.201.1 13891089/tftp-deploy-o5quonh9/kernel/image.itb 13891089/tftp-deploy-o5quonh9/kernel/cmdline
10088 22:54:09.119164 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10089 22:54:09.119603 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10090 22:54:09.124255 tftpboot 192.168.201.1 13891089/tftp-deploy-o5quonh9/kernel/image.ittp-deploy-o5quonh9/kernel/cmdline
10091 22:54:09.124679
10092 22:54:09.125003 Waiting for link
10093 22:54:09.282780
10094 22:54:09.283281 R8152: Initializing
10095 22:54:09.283631
10096 22:54:09.285940 Version 6 (ocp_data = 5c30)
10097 22:54:09.286487
10098 22:54:09.288934 R8152: Done initializing
10099 22:54:09.289345
10100 22:54:09.289668 Adding net device
10101 22:54:11.191363
10102 22:54:11.191912 done.
10103 22:54:11.192351
10104 22:54:11.192718 MAC: 00:e0:4c:68:02:81
10105 22:54:11.193224
10106 22:54:11.194377 Sending DHCP discover... done.
10107 22:54:11.194936
10108 22:54:14.675855 Waiting for reply... done.
10109 22:54:14.676393
10110 22:54:14.676947 Sending DHCP request... done.
10111 22:54:14.679229
10112 22:54:14.679634 Waiting for reply... done.
10113 22:54:14.679957
10114 22:54:14.682733 My ip is 192.168.201.14
10115 22:54:14.683138
10116 22:54:14.685520 The DHCP server ip is 192.168.201.1
10117 22:54:14.685928
10118 22:54:14.689121 TFTP server IP predefined by user: 192.168.201.1
10119 22:54:14.689541
10120 22:54:14.695467 Bootfile predefined by user: 13891089/tftp-deploy-o5quonh9/kernel/image.itb
10121 22:54:14.696121
10122 22:54:14.698677 Sending tftp read request... done.
10123 22:54:14.699088
10124 22:54:14.701968 Waiting for the transfer...
10125 22:54:14.702449
10126 22:54:15.391415 00000000 ################################################################
10127 22:54:15.391986
10128 22:54:16.046347 00080000 ################################################################
10129 22:54:16.046884
10130 22:54:16.719522 00100000 ################################################################
10131 22:54:16.720127
10132 22:54:17.304245 00180000 ################################################################
10133 22:54:17.304383
10134 22:54:17.863496 00200000 ################################################################
10135 22:54:17.863640
10136 22:54:18.419905 00280000 ################################################################
10137 22:54:18.420046
10138 22:54:18.971093 00300000 ################################################################
10139 22:54:18.971238
10140 22:54:19.493857 00380000 ################################################################
10141 22:54:19.494002
10142 22:54:20.030901 00400000 ################################################################
10143 22:54:20.031072
10144 22:54:20.579952 00480000 ################################################################
10145 22:54:20.580086
10146 22:54:21.110255 00500000 ################################################################
10147 22:54:21.110395
10148 22:54:21.651269 00580000 ################################################################
10149 22:54:21.651412
10150 22:54:22.194764 00600000 ################################################################
10151 22:54:22.194902
10152 22:54:22.733814 00680000 ################################################################
10153 22:54:22.733983
10154 22:54:23.269475 00700000 ################################################################
10155 22:54:23.269616
10156 22:54:23.801848 00780000 ################################################################
10157 22:54:23.801990
10158 22:54:24.340373 00800000 ################################################################
10159 22:54:24.340512
10160 22:54:24.878915 00880000 ################################################################
10161 22:54:24.879045
10162 22:54:25.422663 00900000 ################################################################
10163 22:54:25.422826
10164 22:54:25.955359 00980000 ################################################################
10165 22:54:25.955531
10166 22:54:26.500675 00a00000 ################################################################
10167 22:54:26.500815
10168 22:54:27.032508 00a80000 ################################################################
10169 22:54:27.032678
10170 22:54:27.566875 00b00000 ################################################################
10171 22:54:27.567017
10172 22:54:28.103053 00b80000 ################################################################
10173 22:54:28.103221
10174 22:54:28.642290 00c00000 ################################################################
10175 22:54:28.642460
10176 22:54:29.166403 00c80000 ################################################################
10177 22:54:29.166544
10178 22:54:29.714803 00d00000 ################################################################
10179 22:54:29.714963
10180 22:54:30.253984 00d80000 ################################################################
10181 22:54:30.254137
10182 22:54:30.803800 00e00000 ################################################################
10183 22:54:30.803961
10184 22:54:31.338034 00e80000 ################################################################
10185 22:54:31.338259
10186 22:54:31.863962 00f00000 ################################################################
10187 22:54:31.864100
10188 22:54:32.398051 00f80000 ################################################################
10189 22:54:32.398254
10190 22:54:32.945287 01000000 ################################################################
10191 22:54:32.945454
10192 22:54:33.475562 01080000 ################################################################
10193 22:54:33.475706
10194 22:54:34.006997 01100000 ################################################################
10195 22:54:34.007164
10196 22:54:34.556459 01180000 ################################################################
10197 22:54:34.556593
10198 22:54:35.209028 01200000 ################################################################
10199 22:54:35.209514
10200 22:54:35.863962 01280000 ################################################################
10201 22:54:35.864122
10202 22:54:36.498431 01300000 ################################################################
10203 22:54:36.498577
10204 22:54:37.129923 01380000 ################################################################
10205 22:54:37.130400
10206 22:54:37.714058 01400000 ################################################################
10207 22:54:37.714231
10208 22:54:38.257690 01480000 ################################################################
10209 22:54:38.257850
10210 22:54:38.864463 01500000 ################################################################
10211 22:54:38.865047
10212 22:54:39.521450 01580000 ################################################################
10213 22:54:39.521611
10214 22:54:40.114907 01600000 ################################################################
10215 22:54:40.115181
10216 22:54:40.748333 01680000 ################################################################
10217 22:54:40.748479
10218 22:54:41.389336 01700000 ################################################################
10219 22:54:41.389471
10220 22:54:42.032903 01780000 ################################################################
10221 22:54:42.033441
10222 22:54:42.725334 01800000 ################################################################
10223 22:54:42.725487
10224 22:54:43.398326 01880000 ################################################################
10225 22:54:43.398861
10226 22:54:44.015913 01900000 ################################################################
10227 22:54:44.016057
10228 22:54:44.684559 01980000 ################################################################
10229 22:54:44.684699
10230 22:54:45.331252 01a00000 ################################################################
10231 22:54:45.331398
10232 22:54:46.012904 01a80000 ################################################################
10233 22:54:46.013611
10234 22:54:46.646787 01b00000 ################################################################
10235 22:54:46.646956
10236 22:54:47.222709 01b80000 ################################################################
10237 22:54:47.223181
10238 22:54:47.879534 01c00000 ################################################################
10239 22:54:47.880035
10240 22:54:48.574057 01c80000 ################################################################
10241 22:54:48.574595
10242 22:54:49.290371 01d00000 ################################################################
10243 22:54:49.290873
10244 22:54:49.954668 01d80000 ################################################################
10245 22:54:49.955313
10246 22:54:50.588476 01e00000 ################################################################
10247 22:54:50.588652
10248 22:54:51.148152 01e80000 ################################################################
10249 22:54:51.148309
10250 22:54:51.809832 01f00000 ################################################################
10251 22:54:51.810493
10252 22:54:52.492458 01f80000 ################################################################
10253 22:54:52.492949
10254 22:54:53.134583 02000000 ################################################################
10255 22:54:53.134716
10256 22:54:53.741356 02080000 ################################################################
10257 22:54:53.741517
10258 22:54:54.353628 02100000 ################################################################
10259 22:54:54.353757
10260 22:54:55.016859 02180000 ################################################################
10261 22:54:55.017015
10262 22:54:55.738340 02200000 ################################################################
10263 22:54:55.738520
10264 22:54:56.413905 02280000 ################################################################
10265 22:54:56.414045
10266 22:54:57.013948 02300000 ################################################################
10267 22:54:57.014086
10268 22:54:57.623604 02380000 ################################################################
10269 22:54:57.624089
10270 22:54:57.709288 02400000 ######## done.
10271 22:54:57.709783
10272 22:54:57.711916 The bootfile was 37813766 bytes long.
10273 22:54:57.712309
10274 22:54:57.715523 Sending tftp read request... done.
10275 22:54:57.716036
10276 22:54:57.718944 Waiting for the transfer...
10277 22:54:57.719373
10278 22:54:57.719748 00000000 # done.
10279 22:54:57.720066
10280 22:54:57.725788 Command line loaded dynamically from TFTP file: 13891089/tftp-deploy-o5quonh9/kernel/cmdline
10281 22:54:57.728796
10282 22:54:57.742306 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10283 22:54:57.742743
10284 22:54:57.743071 Loading FIT.
10285 22:54:57.743376
10286 22:54:57.745643 Image ramdisk-1 has 23854042 bytes.
10287 22:54:57.746056
10288 22:54:57.748752 Image fdt-1 has 65308 bytes.
10289 22:54:57.749166
10290 22:54:57.752340 Image kernel-1 has 13892383 bytes.
10291 22:54:57.752752
10292 22:54:57.759394 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10293 22:54:57.759932
10294 22:54:57.778639 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10295 22:54:57.779178
10296 22:54:57.782319 Choosing best match conf-1 for compat google,spherion-rev2.
10297 22:54:57.786605
10298 22:54:57.790757 Connected to device vid:did:rid of 1ae0:0028:00
10299 22:54:57.798221
10300 22:54:57.801389 tpm_get_response: command 0x17b, return code 0x0
10301 22:54:57.801802
10302 22:54:57.805001 ec_init: CrosEC protocol v3 supported (256, 248)
10303 22:54:57.809322
10304 22:54:57.812996 tpm_cleanup: add release locality here.
10305 22:54:57.813402
10306 22:54:57.813722 Shutting down all USB controllers.
10307 22:54:57.814016
10308 22:54:57.815940 Removing current net device
10309 22:54:57.816342
10310 22:54:57.822618 Exiting depthcharge with code 4 at timestamp: 82295501
10311 22:54:57.823023
10312 22:54:57.826084 LZMA decompressing kernel-1 to 0x821a6718
10313 22:54:57.826622
10314 22:54:57.829024 LZMA decompressing kernel-1 to 0x40000000
10315 22:54:59.564216
10316 22:54:59.564752 jumping to kernel
10317 22:54:59.566814 end: 2.2.4 bootloader-commands (duration 00:00:55) [common]
10318 22:54:59.567334 start: 2.2.5 auto-login-action (timeout 00:03:32) [common]
10319 22:54:59.567732 Setting prompt string to ['Linux version [0-9]']
10320 22:54:59.568122 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10321 22:54:59.568495 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10322 22:54:59.605222
10323 22:54:59.608382 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10324 22:54:59.612374 start: 2.2.5.1 login-action (timeout 00:03:32) [common]
10325 22:54:59.612974 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10326 22:54:59.613365 Setting prompt string to []
10327 22:54:59.613767 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10328 22:54:59.614154 Using line separator: #'\n'#
10329 22:54:59.614591 No login prompt set.
10330 22:54:59.614928 Parsing kernel messages
10331 22:54:59.615228 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10332 22:54:59.615797 [login-action] Waiting for messages, (timeout 00:03:32)
10333 22:54:59.616155 Waiting using forced prompt support (timeout 00:01:46)
10334 22:54:59.631588 [ 0.000000] Linux version 6.9.0 (KernelCI@build-j201314-arm64-gcc-10-defconfig-arm64-chromebook-phz59) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat May 18 22:35:38 UTC 2024
10335 22:54:59.634948 [ 0.000000] KASLR enabled
10336 22:54:59.638301 [ 0.000000] random: crng init done
10337 22:54:59.641083 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10338 22:54:59.644311 [ 0.000000] efi: UEFI not found.
10339 22:54:59.654222 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10340 22:54:59.660792 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10341 22:54:59.671083 [ 0.000000] OF: reserved mem: 0x0000000050000000..0x00000000528fffff (41984 KiB) nomap non-reusable scp@50000000
10342 22:54:59.680948 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10343 22:54:59.690674 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10344 22:54:59.700624 [ 0.000000] OF: reserved mem: 0x00000000c0000000..0x00000000c3ffffff (65536 KiB) map non-reusable wifi@c0000000
10345 22:54:59.710758 [ 0.000000] OF: reserved mem: 0x00000000ffe66000..0x00000000fff65fff (1024 KiB) map non-reusable ramoops
10346 22:54:59.716708 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10347 22:54:59.720018 [ 0.000000] printk: legacy bootconsole [mtk8250] enabled
10348 22:54:59.730181 [ 0.000000] NUMA: No NUMA configuration found
10349 22:54:59.736758 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10350 22:54:59.743485 [ 0.000000] NUMA: NODE_DATA [mem 0x23efb59c0-0x23efb7fff]
10351 22:54:59.746810 [ 0.000000] Zone ranges:
10352 22:54:59.750617 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10353 22:54:59.753597 [ 0.000000] DMA32 empty
10354 22:54:59.760118 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10355 22:54:59.762933 [ 0.000000] Movable zone start for each node
10356 22:54:59.770084 [ 0.000000] Early memory node ranges
10357 22:54:59.773205 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10358 22:54:59.780148 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10359 22:54:59.786601 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10360 22:54:59.792457 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10361 22:54:59.799498 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10362 22:54:59.805806 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10363 22:54:59.831035 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10364 22:54:59.870273 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10365 22:54:59.876177 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000 on node -1
10366 22:54:59.883424 [ 0.000000] psci: probing for conduit method from DT.
10367 22:54:59.886578 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10368 22:54:59.892430 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10369 22:54:59.896370 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10370 22:54:59.902534 [ 0.000000] psci: SMC Calling Convention v1.2
10371 22:54:59.909125 [ 0.000000] percpu: Embedded 24 pages/cpu s59752 r8192 d30360 u98304
10372 22:54:59.912651 [ 0.000000] Detected VIPT I-cache on CPU0
10373 22:54:59.919327 [ 0.000000] CPU features: detected: GIC system register CPU interface
10374 22:54:59.925323 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10375 22:54:59.932079 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10376 22:54:59.938602 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10377 22:54:59.945418 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10378 22:54:59.948306 [ 0.000000] alternatives: applying boot alternatives
10379 22:54:59.965431 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10380 22:54:59.975705 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10381 22:54:59.987558 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10382 22:54:59.996975 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10383 22:55:00.000467 <6>[ 0.000000] Fallback order for Node 0: 0
10384 22:55:00.006898 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10385 22:55:00.010279 <6>[ 0.000000] Policy zone: Normal
10386 22:55:00.016499 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10387 22:55:00.023904 <6>[ 0.000000] software IO TLB: area num 8.
10388 22:55:00.078596 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10389 22:55:00.223035 <6>[ 0.000000] Memory: 7933224K/8385536K available (18880K kernel code, 5148K rwdata, 24560K rodata, 10944K init, 752K bss, 419544K reserved, 32768K cma-reserved)
10390 22:55:00.229668 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10391 22:55:00.236215 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10392 22:55:00.239552 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10393 22:55:00.245899 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=8.
10394 22:55:00.252489 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10395 22:55:00.259018 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10396 22:55:00.265747 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10397 22:55:00.272881 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10398 22:55:00.279086 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
10399 22:55:00.288600 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
10400 22:55:00.292206 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10401 22:55:00.299841 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10402 22:55:00.303550 <6>[ 0.000000] GICv3: 608 SPIs implemented
10403 22:55:00.310009 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10404 22:55:00.313243 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10405 22:55:00.316380 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10406 22:55:00.326089 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10407 22:55:00.335951 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10408 22:55:00.349485 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10409 22:55:00.356029 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10410 22:55:00.366698 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10411 22:55:00.379454 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10412 22:55:00.386336 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10413 22:55:00.393604 <6>[ 0.009633] Console: colour dummy device 80x25
10414 22:55:00.403355 <6>[ 0.014365] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10415 22:55:00.410466 <6>[ 0.024808] pid_max: default: 32768 minimum: 301
10416 22:55:00.413229 <6>[ 0.029732] LSM: initializing lsm=capability
10417 22:55:00.419907 <6>[ 0.034354] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10418 22:55:00.429829 <6>[ 0.042167] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10419 22:55:00.436423 <6>[ 0.051939] rcu: Hierarchical SRCU implementation.
10420 22:55:00.439690 <6>[ 0.056962] rcu: Max phase no-delay instances is 1000.
10421 22:55:00.448650 <6>[ 0.064824] EFI services will not be available.
10422 22:55:00.451753 <6>[ 0.069799] smp: Bringing up secondary CPUs ...
10423 22:55:00.461188 <6>[ 0.074905] Detected VIPT I-cache on CPU1
10424 22:55:00.468068 <6>[ 0.074967] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10425 22:55:00.474097 <6>[ 0.074999] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10426 22:55:00.478089 <6>[ 0.075388] Detected VIPT I-cache on CPU2
10427 22:55:00.487884 <6>[ 0.075432] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10428 22:55:00.494376 <6>[ 0.075453] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10429 22:55:00.497596 <6>[ 0.075764] Detected VIPT I-cache on CPU3
10430 22:55:00.504083 <6>[ 0.075801] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10431 22:55:00.511044 <6>[ 0.075817] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10432 22:55:00.514082 <6>[ 0.076162] CPU features: detected: Spectre-v4
10433 22:55:00.520332 <6>[ 0.076169] CPU features: detected: Spectre-BHB
10434 22:55:00.524212 <6>[ 0.076175] Detected PIPT I-cache on CPU4
10435 22:55:00.530223 <6>[ 0.076217] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10436 22:55:00.537140 <6>[ 0.076236] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10437 22:55:00.543617 <6>[ 0.076566] Detected PIPT I-cache on CPU5
10438 22:55:00.550135 <6>[ 0.076612] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10439 22:55:00.556914 <6>[ 0.076630] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10440 22:55:00.560173 <6>[ 0.076940] Detected PIPT I-cache on CPU6
10441 22:55:00.566855 <6>[ 0.076986] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10442 22:55:00.576537 <6>[ 0.077004] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10443 22:55:00.580777 <6>[ 0.077324] Detected PIPT I-cache on CPU7
10444 22:55:00.586158 <6>[ 0.077371] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10445 22:55:00.592866 <6>[ 0.077390] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10446 22:55:00.596158 <6>[ 0.077469] smp: Brought up 1 node, 8 CPUs
10447 22:55:00.602993 <6>[ 0.218884] SMP: Total of 8 processors activated.
10448 22:55:00.605762 <6>[ 0.223805] CPU: All CPU(s) started at EL2
10449 22:55:00.612708 <6>[ 0.228135] CPU features: detected: 32-bit EL0 Support
10450 22:55:00.619078 <6>[ 0.233489] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10451 22:55:00.625624 <6>[ 0.242292] CPU features: detected: Common not Private translations
10452 22:55:00.632289 <6>[ 0.248763] CPU features: detected: CRC32 instructions
10453 22:55:00.638853 <6>[ 0.254157] CPU features: detected: RCpc load-acquire (LDAPR)
10454 22:55:00.645328 <6>[ 0.260148] CPU features: detected: LSE atomic instructions
10455 22:55:00.649381 <6>[ 0.265965] CPU features: detected: Privileged Access Never
10456 22:55:00.655816 <6>[ 0.271781] CPU features: detected: RAS Extension Support
10457 22:55:00.662478 <6>[ 0.277424] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10458 22:55:00.668543 <6>[ 0.284627] alternatives: applying system-wide alternatives
10459 22:55:00.679782 <6>[ 0.293489] CPU features: detected: Hardware dirty bit management on CPU4-7
10460 22:55:00.683620 <6>[ 0.302784] devtmpfs: initialized
10461 22:55:00.703985 <6>[ 0.313948] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10462 22:55:00.711098 <6>[ 0.323908] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10463 22:55:00.717194 <6>[ 0.331942] 2G module region forced by RANDOMIZE_MODULE_REGION_FULL
10464 22:55:00.720986 <6>[ 0.338430] 0 pages in range for non-PLT usage
10465 22:55:00.726977 <6>[ 0.338432] 509152 pages in range for PLT usage
10466 22:55:00.730053 <6>[ 0.343296] pinctrl core: initialized pinctrl subsystem
10467 22:55:00.738331 <6>[ 0.355097] DMI not present or invalid.
10468 22:55:00.745070 <6>[ 0.361296] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10469 22:55:00.755123 <6>[ 0.368147] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10470 22:55:00.761388 <6>[ 0.375658] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10471 22:55:00.771245 <6>[ 0.383885] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10472 22:55:00.774600 <6>[ 0.392137] audit: initializing netlink subsys (disabled)
10473 22:55:00.784696 <5>[ 0.397833] audit: type=2000 audit(0.288:1): state=initialized audit_enabled=0 res=1
10474 22:55:00.790939 <6>[ 0.398773] thermal_sys: Registered thermal governor 'step_wise'
10475 22:55:00.797719 <6>[ 0.405800] thermal_sys: Registered thermal governor 'power_allocator'
10476 22:55:00.800865 <6>[ 0.412060] cpuidle: using governor menu
10477 22:55:00.807861 <6>[ 0.423037] NET: Registered PF_QIPCRTR protocol family
10478 22:55:00.814322 <6>[ 0.428539] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10479 22:55:00.820887 <6>[ 0.435638] ASID allocator initialised with 32768 entries
10480 22:55:00.823976 <6>[ 0.442648] Serial: AMBA PL011 UART driver
10481 22:55:00.847889 <6>[ 0.461443] platform 11230000.pcie: Fixed dependency cycle(s) with /soc/pcie@11230000/interrupt-controller
10482 22:55:00.864488 <6>[ 0.477766] platform 14010000.dsi: Fixed dependency cycle(s) with /soc/i2c@11cb0000/anx7625@58
10483 22:55:00.883444 <6>[ 0.496006] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10484 22:55:00.889404 <6>[ 0.503044] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10485 22:55:00.896046 <6>[ 0.509575] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10486 22:55:00.902253 <6>[ 0.516579] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10487 22:55:00.909712 <6>[ 0.523066] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10488 22:55:00.915766 <6>[ 0.530070] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10489 22:55:00.922463 <6>[ 0.536558] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10490 22:55:00.929105 <6>[ 0.543563] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10491 22:55:00.932336 <6>[ 0.550335] Demotion targets for Node 0: null
10492 22:55:00.939341 <6>[ 0.555816] ACPI: Interpreter disabled.
10493 22:55:00.945810 <6>[ 0.562389] iommu: Default domain type: Translated
10494 22:55:00.952864 <6>[ 0.567412] iommu: DMA domain TLB invalidation policy: strict mode
10495 22:55:00.955681 <5>[ 0.574186] SCSI subsystem initialized
10496 22:55:00.962716 <6>[ 0.578373] usbcore: registered new interface driver usbfs
10497 22:55:00.969584 <6>[ 0.584099] usbcore: registered new interface driver hub
10498 22:55:00.972202 <6>[ 0.589651] usbcore: registered new device driver usb
10499 22:55:00.979705 <6>[ 0.595905] pps_core: LinuxPPS API ver. 1 registered
10500 22:55:00.989823 <6>[ 0.601098] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10501 22:55:00.992584 <6>[ 0.610440] PTP clock support registered
10502 22:55:00.995909 <6>[ 0.614704] EDAC MC: Ver: 3.0.0
10503 22:55:01.002421 <6>[ 0.618469] scmi_core: SCMI protocol bus registered
10504 22:55:01.005638 <6>[ 0.624972] FPGA manager framework
10505 22:55:01.012025 <6>[ 0.628669] Advanced Linux Sound Architecture Driver Initialized.
10506 22:55:01.016211 <6>[ 0.635644] vgaarb: loaded
10507 22:55:01.023070 <6>[ 0.638906] clocksource: Switched to clocksource arch_sys_counter
10508 22:55:01.029126 <5>[ 0.645370] VFS: Disk quotas dquot_6.6.0
10509 22:55:01.035952 <6>[ 0.649554] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10510 22:55:01.039006 <6>[ 0.656795] pnp: PnP ACPI: disabled
10511 22:55:01.047582 <6>[ 0.663842] NET: Registered PF_INET protocol family
10512 22:55:01.057050 <6>[ 0.669426] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10513 22:55:01.068553 <6>[ 0.681768] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10514 22:55:01.078934 <6>[ 0.690575] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10515 22:55:01.084871 <6>[ 0.698546] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10516 22:55:01.091514 <6>[ 0.707228] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10517 22:55:01.103521 <6>[ 0.716964] TCP: Hash tables configured (established 65536 bind 65536)
10518 22:55:01.110449 <6>[ 0.723826] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10519 22:55:01.116337 <6>[ 0.731027] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10520 22:55:01.123141 <6>[ 0.738727] NET: Registered PF_UNIX/PF_LOCAL protocol family
10521 22:55:01.130129 <6>[ 0.744862] RPC: Registered named UNIX socket transport module.
10522 22:55:01.133326 <6>[ 0.751010] RPC: Registered udp transport module.
10523 22:55:01.139909 <6>[ 0.755943] RPC: Registered tcp transport module.
10524 22:55:01.146708 <6>[ 0.760875] RPC: Registered tcp-with-tls transport module.
10525 22:55:01.152806 <6>[ 0.766585] RPC: Registered tcp NFSv4.1 backchannel transport module.
10526 22:55:01.156174 <6>[ 0.773255] PCI: CLS 0 bytes, default 64
10527 22:55:01.159617 <6>[ 0.777657] Unpacking initramfs...
10528 22:55:01.167987 <6>[ 0.784146] kvm [1]: nv: 477 coarse grained trap handlers
10529 22:55:01.174432 <6>[ 0.789980] kvm [1]: IPA Size Limit: 40 bits
10530 22:55:01.177602 <6>[ 0.794505] kvm [1]: GICv3: no GICV resource entry
10531 22:55:01.181181 <6>[ 0.799527] kvm [1]: disabling GICv2 emulation
10532 22:55:01.187746 <6>[ 0.804218] kvm [1]: GIC system register CPU interface enabled
10533 22:55:01.194085 <6>[ 0.810293] kvm [1]: vgic interrupt IRQ18
10534 22:55:01.197470 <6>[ 0.814555] kvm [1]: VHE mode initialized successfully
10535 22:55:01.204419 <5>[ 0.820956] Initialise system trusted keyrings
10536 22:55:01.210704 <6>[ 0.825837] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10537 22:55:01.217412 <6>[ 0.832730] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10538 22:55:01.223909 <5>[ 0.838999] NFS: Registering the id_resolver key type
10539 22:55:01.227577 <5>[ 0.844289] Key type id_resolver registered
10540 22:55:01.230611 <5>[ 0.848701] Key type id_legacy registered
10541 22:55:01.237969 <6>[ 0.852954] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10542 22:55:01.247699 <6>[ 0.859874] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10543 22:55:01.250533 <6>[ 0.867576] 9p: Installing v9fs 9p2000 file system support
10544 22:55:01.298292 <5>[ 0.914567] Key type asymmetric registered
10545 22:55:01.301452 <5>[ 0.918898] Asymmetric key parser 'x509' registered
10546 22:55:01.311689 <6>[ 0.924052] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10547 22:55:01.314790 <6>[ 0.931666] io scheduler mq-deadline registered
10548 22:55:01.318217 <6>[ 0.936428] io scheduler kyber registered
10549 22:55:01.324611 <6>[ 0.940702] io scheduler bfq registered
10550 22:55:01.355030 <4>[ 0.971383] cannot find "mediatek,mt8192-fhctl"
10551 22:55:01.390404 <6>[ 1.003061] mtk-socinfo mtk-socinfo.0.auto: MediaTek Kompanio 820 (MT8192) SoC detected.
10552 22:55:01.404970 <6>[ 1.021288] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10553 22:55:01.413478 <6>[ 1.029907] printk: legacy console [ttyS0] disabled
10554 22:55:01.442311 <6>[ 1.055275] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 252, base_baud = 1625000) is a ST16650V2
10555 22:55:01.449160 <6>[ 1.064758] printk: legacy console [ttyS0] enabled
10556 22:55:01.452004 <6>[ 1.064758] printk: legacy console [ttyS0] enabled
10557 22:55:01.458854 <6>[ 1.074879] printk: legacy bootconsole [mtk8250] disabled
10558 22:55:01.465665 <6>[ 1.074879] printk: legacy bootconsole [mtk8250] disabled
10559 22:55:01.472651 <6>[ 1.088803] msm_serial: driver initialized
10560 22:55:01.476248 <6>[ 1.093561] SuperH (H)SCI(F) driver initialized
10561 22:55:01.482797 <6>[ 1.098555] STM32 USART driver initialized
10562 22:55:01.492292 <4>[ 1.104904] SPI driver tpm_tis_spi has no spi_device_id for atmel,attpm20p
10563 22:55:01.503191 <6>[ 1.119573] loop: module loaded
10564 22:55:01.510104 <4>[ 1.126176] mtk-pmic-keys: Failed to locate of_node [id: -1]
10565 22:55:01.516456 <6>[ 1.126810] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10566 22:55:01.519943 <6>[ 1.133146] megasas: 07.727.03.00-rc1
10567 22:55:01.527445 <6>[ 1.143827] vsram_others: Bringing 850000uV into 800000-800000uV
10568 22:55:01.542194 <6>[ 1.158313] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10569 22:55:01.557912 <6>[ 1.174371] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10570 22:55:01.797328 <4>[ 1.413736] ------------[ cut here ]------------
10571 22:55:01.798661 Setting prompt string to ['-+\\[ end trace \\w* \\]-+[^\\n]*\\r', '/ #', 'Login timed out', 'Login incorrect']
10572 22:55:01.807843 <4>[ 1.418623] WARNING: CPU: 3 PID: 69 at kernel/module/kmod.c:144 __request_module+0x188/0x1f4
10573 22:55:01.811034 <4>[ 1.427326] Modules linked in:
10574 22:55:01.817155 <4>[ 1.430634] CPU: 3 PID: 69 Comm: kworker/u32:3 Not tainted 6.9.0 #1
10575 22:55:01.820456 <4>[ 1.437154] Hardware name: Google Spherion (rev0 - 3) (DT)
10576 22:55:01.827285 <4>[ 1.442889] Workqueue: async async_run_entry_fn
10577 22:55:01.833748 <4>[ 1.447676] pstate: 00400009 (nzcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
10578 22:55:01.837127 <4>[ 1.454888] pc : __request_module+0x188/0x1f4
10579 22:55:01.843891 <4>[ 1.459498] lr : __request_module+0x180/0x1f4
10580 22:55:01.847096 <4>[ 1.464106] sp : ffff8000809f3400
10581 22:55:01.854304 <4>[ 1.467670] x29: ffff8000809f3400 x28: 0000000000281ae0 x27: ffffbc306b4a30d2
10582 22:55:01.860325 <4>[ 1.475058] x26: 0000000000000000 x25: ffff6c5bc08e6780 x24: 00000000ffffffff
10583 22:55:01.867079 <4>[ 1.482445] x23: 000000000000200f x22: ffffbc3068ce5fde x21: 0000000000000001
10584 22:55:01.876875 <4>[ 1.489833] x20: 0000000000000000 x19: ffffbc306a20aa88 x18: 0000000000000014
10585 22:55:01.883760 <4>[ 1.497220] x17: 0000000073b979c6 x16: 000000004e7914c4 x15: 00000000698319fd
10586 22:55:01.890441 <4>[ 1.504606] x14: 0000000000000001 x13: ffff8000809f3850 x12: 0000000000000000
10587 22:55:01.896686 <4>[ 1.511994] x11: 00000000b2489ae1 x10: fffffffffdcfa9f6 x9 : 0000000000000004
10588 22:55:01.906831 <4>[ 1.519381] x8 : ffff6c5bc08e6780 x7 : 3135616873286361 x6 : 0c0406065b07370f
10589 22:55:01.912947 <4>[ 1.526769] x5 : 0f37075b0606040c x4 : 0000000000000000 x3 : 0000000000000008
10590 22:55:01.919670 <4>[ 1.534155] x2 : ffffbc3068ce5fde x1 : ffffbc3067ac5468 x0 : 0000000000000001
10591 22:55:01.923149 <4>[ 1.541542] Call trace:
10592 22:55:01.926575 <4>[ 1.544241] __request_module+0x188/0x1f4
10593 22:55:01.932998 <4>[ 1.548502] crypto_alg_mod_lookup+0x178/0x21c
10594 22:55:01.936324 <4>[ 1.553201] crypto_alloc_tfm_node+0x58/0x114
10595 22:55:01.939985 <4>[ 1.557810] crypto_alloc_shash+0x24/0x30
10596 22:55:01.946098 <4>[ 1.562075] drbg_init_hash_kernel+0x28/0xdc
10597 22:55:01.949297 <4>[ 1.566599] drbg_kcapi_seed+0x21c/0x420
10598 22:55:01.952746 <4>[ 1.570772] crypto_rng_reset+0x84/0xb4
10599 22:55:01.959385 <4>[ 1.574859] crypto_get_default_rng+0xa4/0xd8
10600 22:55:01.962786 <4>[ 1.579466] ecc_gen_privkey+0x58/0xd0
10601 22:55:01.966448 <4>[ 1.583466] ecdh_set_secret+0x90/0x198
10602 22:55:01.969267 <4>[ 1.587553] tpm_buf_append_salt+0x164/0x2dc
10603 22:55:01.976097 <4>[ 1.592079] tpm2_start_auth_session+0xc8/0x29c
10604 22:55:01.979396 <4>[ 1.596862] tpm2_get_random+0x44/0x204
10605 22:55:01.982626 <4>[ 1.600950] tpm_get_random+0x74/0x90
10606 22:55:01.986351 <4>[ 1.604864] tpm_hwrng_read+0x24/0x30
10607 22:55:01.992928 <4>[ 1.608777] add_early_randomness+0x68/0x118
10608 22:55:01.996217 <4>[ 1.613297] hwrng_register+0x16c/0x218
10609 22:55:01.999403 <4>[ 1.617383] tpm_chip_register+0xf0/0x2cc
10610 22:55:02.006245 <4>[ 1.621643] tpm_tis_core_init+0x494/0x7e0
10611 22:55:02.009509 <4>[ 1.625990] tpm_tis_spi_init+0x54/0x70
10612 22:55:02.012685 <4>[ 1.630076] cr50_spi_probe+0xf4/0x27c
10613 22:55:02.018978 <4>[ 1.634074] tpm_tis_spi_driver_probe+0x34/0x64
10614 22:55:02.022009 <4>[ 1.638855] spi_probe+0x84/0xe4
10615 22:55:02.025597 <4>[ 1.642340] really_probe+0xbc/0x2a0
10616 22:55:02.028901 <4>[ 1.646169] __driver_probe_device+0x78/0x12c
10617 22:55:02.032278 <4>[ 1.650775] driver_probe_device+0x40/0x160
10618 22:55:02.038870 <4>[ 1.655208] __device_attach_driver+0xb8/0x134
10619 22:55:02.042527 <4>[ 1.659904] bus_for_each_drv+0x84/0xe0
10620 22:55:02.048559 <4>[ 1.663991] __device_attach_async_helper+0xac/0xd0
10621 22:55:02.051884 <4>[ 1.669118] async_run_entry_fn+0x34/0xe0
10622 22:55:02.055076 <4>[ 1.673379] process_one_work+0x154/0x298
10623 22:55:02.058895 <4>[ 1.677643] worker_thread+0x304/0x408
10624 22:55:02.065810 <4>[ 1.681643] kthread+0x118/0x11c
10625 22:55:02.068572 <4>[ 1.685124] ret_from_fork+0x10/0x20
10626 22:55:02.071876 <4>[ 1.688956] ---[ end trace 0000000000000000 ]---
10627 22:55:02.072706 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10628 22:55:02.073096 login-action: kernel 'warning'
10629 22:55:02.073442 [login-action] Waiting for messages, (timeout 00:03:30)
10630 22:55:02.073760 Waiting using forced prompt support (timeout 00:01:45)
10631 22:55:02.202599 <6>[ 1.819298] Freeing initrd memory: 23292K
10632 22:55:02.221451 <6>[ 1.837759] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10633 22:55:02.232424 <6>[ 1.848973] tun: Universal TUN/TAP device driver, 1.6
10634 22:55:02.235618 <6>[ 1.855265] thunder_xcv, ver 1.0
10635 22:55:02.239014 <6>[ 1.858757] thunder_bgx, ver 1.0
10636 22:55:02.242260 <6>[ 1.862262] nicpf, ver 1.0
10637 22:55:02.253346 <6>[ 1.866413] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10638 22:55:02.256456 <6>[ 1.873898] hns3: Copyright (c) 2017 Huawei Corporation.
10639 22:55:02.261704 <6>[ 1.879514] hclge is initializing
10640 22:55:02.265854 <6>[ 1.883122] e1000: Intel(R) PRO/1000 Network Driver
10641 22:55:02.272692 <6>[ 1.888254] e1000: Copyright (c) 1999-2006 Intel Corporation.
10642 22:55:02.279497 <6>[ 1.894263] e1000e: Intel(R) PRO/1000 Network Driver
10643 22:55:02.293466 <6>[ 1.899479] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10644 22:55:02.293734 <6>[ 1.905659] igb: Intel(R) Gigabit Ethernet Network Driver
10645 22:55:02.297760 <6>[ 1.911310] igb: Copyright (c) 2007-2014 Intel Corporation.
10646 22:55:02.302964 <6>[ 1.917144] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10647 22:55:02.307273 <6>[ 1.923661] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10648 22:55:02.329674 <6>[ 1.930175] sky2: driver version 1.30
10649 22:55:02.329941 <6>[ 1.935417] usbcore: registered new device driver r8152-cfgselector
10650 22:55:02.330338 <6>[ 1.941947] usbcore: registered new interface driver r8152
10651 22:55:02.333625 <6>[ 1.947890] VFIO - User Level meta-driver version: 0.3
10652 22:55:02.344154 <6>[ 1.956423] usbcore: registered new interface driver usb-storage
10653 22:55:02.347935 <6>[ 1.962943] usbcore: registered new device driver onboard-usb-hub
10654 22:55:02.367242 <6>[ 1.972789] mt6397-rtc mt6359-rtc: registered as rtc0
10655 22:55:02.367755 <6>[ 1.973866] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10656 22:55:02.380807 <6>[ 1.978274] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-18T22:55:02 UTC (1716072902)
10657 22:55:02.433773 <6>[ 1.998908] i2c_dev: i2c /dev entries driver
10658 22:55:02.434384 <6>[ 2.004475] platform 14010000.dsi: Fixed dependency cycle(s) with /soc/i2c@11cb0000/anx7625@58
10659 22:55:02.435228 <6>[ 2.013399] i2c 3-0058: Fixed dependency cycle(s) with /soc/i2c@11cb0000/anx7625@58/aux-bus/panel
10660 22:55:02.435611 <6>[ 2.022540] i2c 3-0058: Fixed dependency cycle(s) with /soc/dsi@14010000
10661 22:55:02.436890 <6>[ 2.038004] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10662 22:55:02.437800 <4>[ 2.047239] cpu cpu0: supply cpu not found, using dummy regulator
10663 22:55:02.439952 <4>[ 2.053667] cpu cpu1: supply cpu not found, using dummy regulator
10664 22:55:02.443905 <4>[ 2.060076] cpu cpu2: supply cpu not found, using dummy regulator
10665 22:55:02.453202 <4>[ 2.066485] cpu cpu3: supply cpu not found, using dummy regulator
10666 22:55:02.456791 <4>[ 2.072892] cpu cpu4: supply cpu not found, using dummy regulator
10667 22:55:02.463816 <4>[ 2.079308] cpu cpu5: supply cpu not found, using dummy regulator
10668 22:55:02.476954 <4>[ 2.085712] cpu cpu6: supply cpu not found, using dummy regulator
10669 22:55:02.480558 <4>[ 2.092112] cpu cpu7: supply cpu not found, using dummy regulator
10670 22:55:02.511216 <6>[ 2.113124] cpu cpu0: EM: created perf domain
10671 22:55:02.511525 <6>[ 2.118128] cpu cpu4: EM: created perf domain
10672 22:55:02.511953 <6>[ 2.124031] sdhci: Secure Digital Host Controller Interface driver
10673 22:55:02.514755 <6>[ 2.130465] sdhci: Copyright(c) Pierre Ossman
10674 22:55:02.522047 <6>[ 2.135494] Synopsys Designware Multimedia Card Interface Driver
10675 22:55:02.525551 <6>[ 2.142192] sdhci-pltfm: SDHCI platform and OF driver helper
10676 22:55:02.528987 <6>[ 2.142238] mmc0: CQHCI version 5.10
10677 22:55:02.536043 <6>[ 2.152158] ledtrig-cpu: registered to indicate activity on CPUs
10678 22:55:02.545571 <6>[ 2.158993] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10679 22:55:02.549323 <6>[ 2.166166] usbcore: registered new interface driver usbhid
10680 22:55:02.555696 <6>[ 2.171992] usbhid: USB HID core driver
10681 22:55:02.562450 <6>[ 2.176294] spi_master spi0: will run message pump with realtime priority
10682 22:55:02.573032 <6>[ 2.184716] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10683 22:55:02.579872 <6>[ 2.194097] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10684 22:55:02.594729 <6>[ 2.207623] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10685 22:55:02.607901 <6>[ 2.217345] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10686 22:55:02.617728 <6>[ 2.219126] mt8192_mt6359 sound: audio-routing not found: using legacy probe
10687 22:55:02.620486 <6>[ 2.237807] NET: Registered PF_PACKET protocol family
10688 22:55:02.633903 <6>[ 2.239346] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10689 22:55:02.641279 <6>[ 2.243167] 9pnet: Installing 9P2000 support
10690 22:55:02.647574 <4>[ 2.246730] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10691 22:55:02.657198 <4>[ 2.246782] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10692 22:55:02.667370 <4>[ 2.246828] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10693 22:55:02.676842 <4>[ 2.246874] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10694 22:55:02.687350 <4>[ 2.246946] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10695 22:55:02.693287 <4>[ 2.246993] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10696 22:55:02.703449 <4>[ 2.247038] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10697 22:55:02.713765 <4>[ 2.247083] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10698 22:55:02.722867 <4>[ 2.247131] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10699 22:55:02.733273 <4>[ 2.247176] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10700 22:55:02.739412 <4>[ 2.247220] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10701 22:55:02.749789 <4>[ 2.247264] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10702 22:55:02.759285 <4>[ 2.247312] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10703 22:55:02.769022 <4>[ 2.247356] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10704 22:55:02.778885 <4>[ 2.247399] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10705 22:55:02.785522 <4>[ 2.247443] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10706 22:55:02.795410 <4>[ 2.247487] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10707 22:55:02.805333 <4>[ 2.247535] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10708 22:55:02.815533 <4>[ 2.247579] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10709 22:55:02.818873 <6>[ 2.248514] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16414
10710 22:55:02.825241 <6>[ 2.261466] cros-ec-spi spi0.0: Chrome EC device registered
10711 22:55:02.832197 <5>[ 2.270262] Key type dns_resolver registered
10712 22:55:02.834932 <6>[ 2.270423] mmc0: Command Queue Engine enabled
10713 22:55:02.841250 <6>[ 2.270440] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10714 22:55:02.845207 <6>[ 2.271287] mmcblk0: mmc0:0001 DA4128 116 GiB
10715 22:55:02.851944 <6>[ 2.275038] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10716 22:55:02.858281 <6>[ 2.276433] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10717 22:55:02.861283 <6>[ 2.277126] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10718 22:55:02.868015 <6>[ 2.277751] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10719 22:55:02.880316 <6>[ 2.493736] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
10720 22:55:02.886887 <6>[ 2.502876] registered taskstats version 1
10721 22:55:02.890070 <5>[ 2.507489] Loading compiled-in X.509 certificates
10722 22:55:02.922688 <6>[ 2.538986] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10723 22:55:02.929188 <6>[ 2.545966] xhci-mtk 11200000.usb: xHCI Host Controller
10724 22:55:02.935600 <6>[ 2.551461] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10725 22:55:02.945894 <6>[ 2.559304] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000200010
10726 22:55:02.952703 <6>[ 2.568796] xhci-mtk 11200000.usb: irq 270, io mem 0x11200000
10727 22:55:02.959293 <6>[ 2.574857] xhci-mtk 11200000.usb: xHCI Host Controller
10728 22:55:02.965586 <6>[ 2.580344] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10729 22:55:02.972306 <6>[ 2.587992] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10730 22:55:02.979168 <6>[ 2.595697] hub 1-0:1.0: USB hub found
10731 22:55:02.982551 <6>[ 2.599705] hub 1-0:1.0: 1 port detected
10732 22:55:02.989471 <6>[ 2.603971] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10733 22:55:02.996581 <6>[ 2.612561] hub 2-0:1.0: USB hub found
10734 22:55:02.999161 <6>[ 2.616566] hub 2-0:1.0: 1 port detected
10735 22:55:03.009842 <6>[ 2.626616] mtk-msdc 11f70000.mmc: Got CD GPIO
10736 22:55:03.028560 <4>[ 2.641589] rt5682 1-001a: Using default DAI clk names: rt5682-dai-wclk, rt5682-dai-bclk
10737 22:55:03.390042 <6>[ 3.003433] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10738 22:55:03.419823 <6>[ 3.036340] hub 2-1:1.0: USB hub found
10739 22:55:03.423703 <6>[ 3.040913] hub 2-1:1.0: 3 ports detected
10740 22:55:03.450814 <6>[ 3.066662] hub 2-1:1.0: USB hub found
10741 22:55:03.453331 <6>[ 3.071123] hub 2-1:1.0: 3 ports detected
10742 22:55:03.550346 <6>[ 3.163001] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10743 22:55:03.703570 <6>[ 3.320335] hub 1-1:1.0: USB hub found
10744 22:55:03.706834 <6>[ 3.324739] hub 1-1:1.0: 4 ports detected
10745 22:55:03.742860 <6>[ 3.359026] hub 1-1:1.0: USB hub found
10746 22:55:03.745790 <6>[ 3.363524] hub 1-1:1.0: 4 ports detected
10747 22:55:03.786329 <6>[ 3.399069] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10748 22:55:03.894878 <6>[ 3.507819] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10749 22:55:03.932615 <4>[ 3.545003] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10750 22:55:03.941624 <4>[ 3.554148] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10751 22:55:03.980771 <6>[ 3.596834] r8152 2-1.3:1.0 eth0: v1.12.13
10752 22:55:04.069935 <6>[ 3.683253] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10753 22:55:04.202280 <6>[ 3.818954] hub 1-1.4:1.0: USB hub found
10754 22:55:04.205613 <6>[ 3.823622] hub 1-1.4:1.0: 2 ports detected
10755 22:55:04.265614 <6>[ 3.881747] hub 1-1.4:1.0: USB hub found
10756 22:55:04.268727 <6>[ 3.886461] hub 1-1.4:1.0: 2 ports detected
10757 22:55:04.565845 <6>[ 4.179246] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10758 22:55:04.758918 <6>[ 4.375040] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10759 22:55:05.716677 <6>[ 5.333204] r8152 2-1.3:1.0 eth0: carrier on
10760 22:55:05.762408 <5>[ 5.362992] Sending DHCP requests ., OK
10761 22:55:05.769132 <6>[ 5.383336] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10762 22:55:05.772581 <6>[ 5.391634] IP-Config: Complete:
10763 22:55:05.785860 <6>[ 5.395131] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10764 22:55:05.792572 <6>[ 5.405838] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10765 22:55:05.798786 <6>[ 5.414456] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10766 22:55:05.805577 <6>[ 5.414465] nameserver0=192.168.201.1
10767 22:55:05.809062 <6>[ 5.426578] clk: Disabling unused clocks
10768 22:55:05.815304 <6>[ 5.431804] PM: genpd: Disabling unused power domains
10769 22:55:05.818608 <6>[ 5.437143] ALSA device list:
10770 22:55:05.821922 <6>[ 5.440378] No soundcards found.
10771 22:55:05.832869 <6>[ 5.449235] Freeing unused kernel memory: 10944K
10772 22:55:05.836014 <6>[ 5.454270] Run /init as init process
10773 22:55:05.867790 Starting syslogd: OK
10774 22:55:05.872566 Starting klogd: OK
10775 22:55:05.882122 Running sysctl: OK
10776 22:55:05.889020 Populating /dev using udev: <30>[ 5.506595] udevd[173]: starting version 3.2.9
10777 22:55:05.896984 <27>[ 5.513280] udevd[173]: specified user 'tss' unknown
10778 22:55:05.902917 <27>[ 5.518633] udevd[173]: specified group 'tss' unknown
10779 22:55:05.906981 <30>[ 5.524934] udevd[174]: starting eudev-3.2.9
10780 22:55:05.942502 <27>[ 5.559002] udevd[174]: specified user 'tss' unknown
10781 22:55:05.949005 <27>[ 5.564372] udevd[174]: specified group 'tss' unknown
10782 22:55:06.059067 <6>[ 5.675893] pstore: Using crash dump compression: deflate
10783 22:55:06.065809 <6>[ 5.681649] pstore: Registered ramoops as persistent store backend
10784 22:55:06.073061 <6>[ 5.688124] ramoops: using 0x100000@0xffe66000, ecc: 0
10785 22:55:06.155069 <6>[ 5.768243] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10786 22:55:06.162123 <6>[ 5.772967] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10787 22:55:06.171448 <6>[ 5.775947] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10788 22:55:06.177956 <6>[ 5.792011] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10789 22:55:06.184270 <6>[ 5.795645] remoteproc remoteproc0: scp is available
10790 22:55:06.191570 <6>[ 5.806095] remoteproc remoteproc0: powering up scp
10791 22:55:06.198095 <6>[ 5.810118] mediatek-mipi-tx 11e50000.dsi-phy: can't get nvmem_cell_get, ignore it
10792 22:55:06.204066 <6>[ 5.811270] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10793 22:55:06.210822 <6>[ 5.827829] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10794 22:55:06.239041 <6>[ 5.852182] sbs-battery 8-000b: sbs-battery: battery gas gauge device registered
10795 22:55:06.242306 <6>[ 5.860715] mc: Linux media interface: v0.10
10796 22:55:06.262734 <4>[ 5.876217] sbs-battery 8-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10797 22:55:06.269606 <4>[ 5.876217] Fallback method does not support PEC.
10798 22:55:06.295971 <4>[ 5.909116] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
10799 22:55:06.298728 <6>[ 5.909585] videodev: Linux video capture interface: v2.00
10800 22:55:06.308785 <4>[ 5.916944] elants_i2c 0-0010: supply vccio not found, using dummy regulator
10801 22:55:06.312362 <6>[ 5.918284] Bluetooth: Core ver 2.22
10802 22:55:06.318808 <6>[ 5.918331] NET: Registered PF_BLUETOOTH protocol family
10803 22:55:06.325332 <6>[ 5.918333] Bluetooth: HCI device and connection manager initialized
10804 22:55:06.329122 <6>[ 5.918346] Bluetooth: HCI socket layer initialized
10805 22:55:06.335663 <6>[ 5.918349] Bluetooth: L2CAP socket layer initialized
10806 22:55:06.339285 <6>[ 5.918354] Bluetooth: SCO socket layer initialized
10807 22:55:06.345409 <6>[ 5.920922] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10808 22:55:06.352371 <6>[ 5.920942] pci_bus 0000:00: root bus resource [bus 00-ff]
10809 22:55:06.359206 <6>[ 5.920952] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10810 22:55:06.369294 <6>[ 5.920957] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10811 22:55:06.375380 <6>[ 5.921007] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400 PCIe Root Port
10812 22:55:06.385599 <6>[ 5.921033] pci 0000:00:00.0: BAR 0 [mem 0x00000000-0x00003fff 64bit pref]
10813 22:55:06.389198 <6>[ 5.921042] pci 0000:00:00.0: PCI bridge to [bus 00]
10814 22:55:06.395583 <6>[ 5.921048] pci 0000:00:00.0: bridge window [io 0x0000-0x0fff]
10815 22:55:06.401810 <6>[ 5.921052] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff]
10816 22:55:06.411647 <6>[ 5.921060] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff 64bit pref]
10817 22:55:06.414785 <6>[ 5.921142] pci 0000:00:00.0: supports D1 D2
10818 22:55:06.421133 <6>[ 5.921147] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10819 22:55:06.431308 <6>[ 5.927141] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10820 22:55:06.437731 <6>[ 5.954531] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/ovl@14005000
10821 22:55:06.447465 <6>[ 5.956357] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000 PCIe Endpoint
10822 22:55:06.454100 <6>[ 5.959221] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10823 22:55:06.461074 <6>[ 5.961331] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/ovl@14006000
10824 22:55:06.470640 <6>[ 5.968147] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10825 22:55:06.477371 <6>[ 5.969525] panfrost 13000000.gpu: clock rate = 357999878
10826 22:55:06.483891 <6>[ 5.971764] panfrost 13000000.gpu: mali-g57 id 0x9093 major 0x0 minor 0x0 status 0x0
10827 22:55:06.491073 <6>[ 5.971774] panfrost 13000000.gpu: features: 00000000,000019f7, issues: 00000003,80000400
10828 22:55:06.504118 <6>[ 5.971779] panfrost 13000000.gpu: Features: L2:0x07130206 Shader:0x00000000 Tiler:0x00000809 Mem:0x101 MMU:0x00002830 AS:0xff JS:0x7
10829 22:55:06.510923 <6>[ 5.971785] panfrost 13000000.gpu: shader_present=0x50045 l2_present=0x1
10830 22:55:06.520845 <6>[ 5.972462] [drm] Initialized panfrost 1.2.0 20180908 for 13000000.gpu on minor 0
10831 22:55:06.527190 <3>[ 5.973860] power_supply sbs-8-000b: driver failed to report `time_to_empty_now' property: -5
10832 22:55:06.537069 <6>[ 5.973936] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/rdma@14007000
10833 22:55:06.543977 <6>[ 5.981009] remoteproc remoteproc0: remote processor scp is now up
10834 22:55:06.550432 <6>[ 5.981066] pci 0000:01:00.0: BAR 0 [mem 0x00000000-0x000fffff 64bit pref]
10835 22:55:06.560211 <6>[ 5.990986] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/color@14009000
10836 22:55:06.566640 <6>[ 5.998498] pci 0000:01:00.0: BAR 2 [mem 0x00000000-0x00003fff 64bit pref]
10837 22:55:06.573893 <6>[ 5.998514] pci 0000:01:00.0: BAR 4 [mem 0x00000000-0x00000fff 64bit pref]
10838 22:55:06.579874 <3>[ 6.000252] SVSB_GPU_LOW: cannot get "gpu-thermal" thermal zone
10839 22:55:06.587019 <3>[ 6.000256] mtk-svs 1100bc00.svs: error -ENODEV: svs bank resource setup fail
10840 22:55:06.597070 <6>[ 6.005832] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/ccorr@1400a000
10841 22:55:06.600123 <6>[ 6.011013] pci 0000:01:00.0: supports D1 D2
10842 22:55:06.610228 <6>[ 6.017273] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/aal@1400b000
10843 22:55:06.616252 <6>[ 6.024236] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10844 22:55:06.626074 <4>[ 6.035178] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10845 22:55:06.632981 <6>[ 6.036864] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/gamma@1400c000
10846 22:55:06.642660 <6>[ 6.038363] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-0/0-0010/input/input2
10847 22:55:06.653015 <6>[ 6.040026] elan_i2c 2-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10848 22:55:06.662814 <6>[ 6.040285] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-2/2-0015/input/input3
10849 22:55:06.669069 <6>[ 6.044295] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10850 22:55:06.678940 <6>[ 6.052174] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/dsi@14010000
10851 22:55:06.685761 <6>[ 6.053874] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10852 22:55:06.695592 <6>[ 6.053884] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10853 22:55:06.705515 <6>[ 6.060613] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]: assigned
10854 22:55:06.712064 <6>[ 6.068109] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/ovl@14014000
10855 22:55:06.718536 <4>[ 6.073841] rt5682 1-001a: ASoC: source widget I2S1 overwritten
10856 22:55:06.725216 <6>[ 6.075136] pci 0000:00:00.0: BAR 0 [mem 0x12200000-0x12203fff 64bit pref]: assigned
10857 22:55:06.735306 <6>[ 6.083775] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/rdma@14015000
10858 22:55:06.745182 <6>[ 6.092262] pci 0000:01:00.0: BAR 0 [mem 0x12000000-0x120fffff 64bit pref]: assigned
10859 22:55:06.751575 <3>[ 6.112855] power_supply sbs-8-000b: driver failed to report `time_to_empty_now' property: -5
10860 22:55:06.761962 <6>[ 6.114412] pci 0000:01:00.0: BAR 2 [mem 0x12100000-0x12103fff 64bit pref]: assigned
10861 22:55:06.764731 <6>[ 6.183103] usbcore: registered new interface driver btusb
10862 22:55:06.771378 <6>[ 6.187703] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10863 22:55:06.781004 <6>[ 6.188229] pci 0000:01:00.0: BAR 4 [mem 0x12104000-0x12104fff 64bit pref]: assigned
10864 22:55:06.784280 <6>[ 6.188248] pci 0000:00:00.0: PCI bridge to [bus 01]
10865 22:55:06.794271 <6>[ 6.188261] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10866 22:55:06.804393 <4>[ 6.189249] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10867 22:55:06.811280 <3>[ 6.189258] Bluetooth: hci0: Failed to load firmware file (-2)
10868 22:55:06.817246 <3>[ 6.189261] Bluetooth: hci0: Failed to set up firmware (-2)
10869 22:55:06.827243 <4>[ 6.189264] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10870 22:55:06.834252 <6>[ 6.196501] usbcore: registered new interface driver uvcvideo
10871 22:55:06.840673 <6>[ 6.202058] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10872 22:55:06.847228 <6>[ 6.211238] cros-ec-dev cros-ec-dev.12.auto: CrOS System Control Processor MCU detected
10873 22:55:06.853829 <6>[ 6.219331] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10874 22:55:06.860162 <6>[ 6.225086] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10875 22:55:06.866664 <6>[ 6.231786] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10876 22:55:06.891898 <6>[ 6.505210] input: mt8192_mt6359_rt1015p_rt5682 Headset Jack as /devices/platform/sound/sound/card0/input4
10877 22:55:06.901890 <5>[ 6.505966] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10878 22:55:06.908734 <6>[ 6.519234] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10879 22:55:06.918379 <6>[ 6.531571] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10880 22:55:06.924724 <5>[ 6.539862] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10881 22:55:06.931563 <6>[ 6.539946] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10882 22:55:06.941585 <5>[ 6.546287] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10883 22:55:06.948212 <6>[ 6.554273] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10884 22:55:06.959128 <4>[ 6.561723] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10885 22:55:06.967956 <6>[ 6.570117] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10886 22:55:06.974595 <6>[ 6.578946] cfg80211: failed to load regulatory.db
10887 22:55:06.980711 <6>[ 6.587239] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10888 22:55:06.989357 <6>[ 6.600621] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10889 22:55:06.997028 <6>[ 6.608968] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10890 22:55:07.041857 <6>[ 6.617317] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10891 22:55:07.042463 <6>[ 6.625658] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10892 22:55:07.043611 <6>[ 6.633998] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10893 22:55:07.044018 <6>[ 6.642338] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10894 22:55:07.044360 <6>[ 6.650678] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10895 22:55:07.054401 <6>[ 6.659019] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10896 22:55:07.057654 <6>[ 6.667369] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10897 22:55:07.090038 <6>[ 6.703538] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10898 22:55:07.096655 <6>[ 6.711162] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10899 22:55:07.107958 <6>[ 6.720976] mt7921e 0000:01:00.0: ASIC revision: 79610010
10900 22:55:07.204136 <6>[ 6.817761] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10901 22:55:07.208008 <6>[ 6.817761]
10902 22:55:07.237905 <6>[ 6.850725] panel-simple-dp-aux aux-3-0058: Detected IVO R140NWF5 RH (0x057d)
10903 22:55:07.245735 <6>[ 6.862445] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10904 22:55:07.249115 done
10905 22:55:07.257481 <6>[ 6.874230] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10906 22:55:07.268080 Saving random seed: <6>[ 6.884178] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10907 22:55:07.270745 OK
10908 22:55:07.281156 <6>[ 6.894568] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10909 22:55:07.292620 Starting network: <6>[ 6.905358] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10910 22:55:07.302207 ip: RTNETLINK an<6>[ 6.913147] mediatek-drm mediatek-drm.11.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops [mediatek_drm])
10911 22:55:07.315144 swers: File exis<6>[ 6.924158] mediatek-drm mediatek-drm.11.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops [mediatek_drm])
10912 22:55:07.324809 <6>[ 6.936054] mediatek-drm mediatek-drm.11.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops [mediatek_drm])
10913 22:55:07.325369 ts
10914 22:55:07.334920 FAIL<6>[ 6.946754] mediatek-drm mediatek-drm.11.auto: bound 14009000.color (ops mtk_disp_color_component_ops [mediatek_drm])
10915 22:55:07.337932
10916 22:55:07.348255 <6>[ 6.958303] mediatek-drm mediatek-drm.11.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops [mediatek_drm])
10917 22:55:07.358821 <6>[ 6.969329] mediatek-drm mediatek-drm.11.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops [mediatek_drm])
10918 22:55:07.371060 Starting dropbea<6>[ 6.979843] mediatek-drm mediatek-drm.11.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops [mediatek_drm])
10919 22:55:07.381616 r sshd: <6>[ 6.994178] mediatek-drm mediatek-drm.11.auto: bound 14010000.dsi (ops mtk_dsi_component_ops [mediatek_drm])
10920 22:55:07.394885 <6>[ 7.004286] mediatek-drm mediatek-drm.11.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops [mediatek_drm])
10921 22:55:07.404513 <6>[ 7.014802] mediatek-drm mediatek-drm.11.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops [mediatek_drm])
10922 22:55:07.414334 <6>[ 7.025537] mediatek-drm mediatek-drm.11.auto: Not creating crtc 1 because component 10 is disabled or missing
10923 22:55:07.417607 <6>[ 7.026247] NET: Registered PF_INET6 protocol family
10924 22:55:07.427568 <6>[ 7.036968] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.11.auto on minor 1
10925 22:55:07.431292 <6>[ 7.041818] Segment Routing with IPv6
10926 22:55:07.434559 <6>[ 7.053391] In-situ OAM (IOAM) with IPv6
10927 22:55:07.439353 OK
10928 22:55:07.447501 /bin/sh: can't access tty; job control turned off
10929 22:55:07.448712 Matched prompt #10: / #
10931 22:55:07.450028 Kernel warnings or errors detected.
10932 22:55:07.450432 Setting prompt string to ['/ #']
10933 22:55:07.450883 end: 2.2.5.1 login-action (duration 00:00:08) [common]
10935 22:55:07.452181 end: 2.2.5 auto-login-action (duration 00:00:08) [common]
10936 22:55:07.452673 start: 2.2.6 expect-shell-connection (timeout 00:03:24) [common]
10937 22:55:07.453060 Setting prompt string to ['/ #']
10938 22:55:07.453431 Forcing a shell prompt, looking for ['/ #']
10940 22:55:07.504278 / #
10941 22:55:07.504945 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10942 22:55:07.505430 Waiting using forced prompt support (timeout 00:02:30)
10943 22:55:07.505956 <6>[ 7.084228] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10944 22:55:07.510937
10945 22:55:07.511865 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10946 22:55:07.512395 start: 2.2.7 export-device-env (timeout 00:03:24) [common]
10947 22:55:07.512913 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10948 22:55:07.513374 end: 2.2 depthcharge-retry (duration 00:01:36) [common]
10949 22:55:07.513840 end: 2 depthcharge-action (duration 00:01:36) [common]
10950 22:55:07.514338 start: 3 lava-test-retry (timeout 00:01:00) [common]
10951 22:55:07.514802 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10952 22:55:07.515228 Using namespace: common
10954 22:55:07.616477 / # #
10955 22:55:07.617083 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10956 22:55:07.623435 #
10957 22:55:07.624318 Using /lava-13891089
10959 22:55:07.725734 / # export SHELL=/bin/sh
10960 22:55:07.732385 export SHELL=/bin/sh
10962 22:55:07.834048 / # . /lava-13891089/environment
10963 22:55:07.834967 . /lava-13891089/environment<6>[ 7.417434] Console: switching to colour frame buffer device 240x67
10964 22:55:07.835433 <6>[ 7.442015] mediatek-drm mediatek-drm.11.auto: [drm] fb0: mediatekdrmfb frame buffer device
10965 22:55:07.840379
10967 22:55:07.942035 / # /lava-13891089/bin/lava-test-runner /lava-13891089/0
10968 22:55:07.942714 Test shell timeout: 10s (minimum of the action and connection timeout)
10969 22:55:07.944333 <6>[ 7.473903] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 1
10970 22:55:07.944754 <6>[ 7.483722] mtk-vcodec-dec 16000000.video-codec: Adding to iommu group 1
10971 22:55:07.945106 <6>[ 7.506301] mtk-vdec-comp 16010000.video-codec: Adding to iommu group 1
10972 22:55:07.945439 <6>[ 7.513515] mtk-vdec-comp 16025000.video-codec: Adding to iommu group 1
10973 22:55:07.945754 <4>[ 7.520504] ttyS ttyS0: 1 input overrun(s)
10974 22:55:07.948126 /lava-13891089/bin/lava-test-run /lava-13891089/0
10975 22:55:07.990847 /bin/sh: /lava-13891089/bin/lava-test-run: not found
10976 22:55:08.293987 / # <6>[ 7.910583] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10977 22:55:36.291956 <6>[ 35.915306] vpu: disabling
10978 22:55:36.295184 <6>[ 35.918415] vproc2: disabling
10979 22:55:36.298687 <6>[ 35.921759] vproc1: disabling
10980 22:55:36.302217 <6>[ 35.925059] vaud18: disabling
10981 22:55:36.305273 <6>[ 35.928803] va09: disabling
10982 22:55:36.308616 <6>[ 35.931959] vsram_md: disabling
10983 22:55:36.318405 <6>[ 35.938683] pp1000_dpbrdg: disabling
10984 22:55:36.321626 <6>[ 35.942556] pp1800_dpbrdg: disabling
10985 22:55:36.325098 <6>[ 35.946426] pp3300_dpbrdg: disabling
10987 22:56:07.515041 end: 3.1 lava-test-shell (duration 00:01:00) [common]
10989 22:56:07.515224 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
10991 22:56:07.515371 end: 3 lava-test-retry (duration 00:01:00) [common]
10993 22:56:07.515585 Cleaning after the job
10994 22:56:07.515671 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13891089/tftp-deploy-o5quonh9/ramdisk
10995 22:56:07.518346 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13891089/tftp-deploy-o5quonh9/kernel
10996 22:56:07.530205 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13891089/tftp-deploy-o5quonh9/dtb
10997 22:56:07.530401 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13891089/tftp-deploy-o5quonh9/modules
10998 22:56:07.536984 start: 4.1 power-off (timeout 00:00:30) [common]
10999 22:56:07.537154 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
11000 22:56:07.747635 >> Command sent successfully.
11001 22:56:07.749985 Returned 0 in 0 seconds
11002 22:56:07.850337 end: 4.1 power-off (duration 00:00:00) [common]
11004 22:56:07.850660 start: 4.2 read-feedback (timeout 00:10:00) [common]
11005 22:56:07.850920 Listened to connection for namespace 'common' for up to 1s
11006 22:56:08.851880 Finalising connection for namespace 'common'
11007 22:56:08.852061 Disconnecting from shell: Finalise
11008 22:56:08.952395 end: 4.2 read-feedback (duration 00:00:01) [common]
11009 22:56:08.952563 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13891089
11010 22:56:08.996699 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13891089
11011 22:56:08.996887 TestError: A test failed to run, look at the error message.