Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 2
- Kernel Errors: 24
- Boot result: FAIL
1 17:56:46.512347 lava-dispatcher, installed at version: 2024.01
2 17:56:46.512554 start: 0 validate
3 17:56:46.512683 Start time: 2024-04-25 17:56:46.512675+00:00 (UTC)
4 17:56:46.512805 Using caching service: 'http://localhost/cache/?uri=%s'
5 17:56:46.512931 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 17:56:46.766510 Using caching service: 'http://localhost/cache/?uri=%s'
7 17:56:46.766668 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.9-rc5-53-ge33c4963bf53%2Farm64%2Fdefconfig%2Barm64-chromebook%2Bvideodec%2Fgcc-10%2Fkernel%2FImage exists
8 17:56:47.018864 Using caching service: 'http://localhost/cache/?uri=%s'
9 17:56:47.019077 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.9-rc5-53-ge33c4963bf53%2Farm64%2Fdefconfig%2Barm64-chromebook%2Bvideodec%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 17:57:24.264934 Using caching service: 'http://localhost/cache/?uri=%s'
11 17:57:24.265582 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.9-rc5-53-ge33c4963bf53%2Farm64%2Fdefconfig%2Barm64-chromebook%2Bvideodec%2Fgcc-10%2Fmodules.tar.xz exists
12 17:57:24.768925 validate duration: 38.26
14 17:57:24.769447 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 17:57:24.769667 start: 1.1 download-retry (timeout 00:10:00) [common]
16 17:57:24.769855 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 17:57:24.770110 Not decompressing ramdisk as can be used compressed.
18 17:57:24.770291 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 17:57:24.770431 saving as /var/lib/lava/dispatcher/tmp/13522576/tftp-deploy-b23ke98q/ramdisk/rootfs.cpio.gz
20 17:57:24.770590 total size: 8181887 (7 MB)
21 17:57:35.057055 progress 0 % (0 MB)
22 17:57:35.059551 progress 5 % (0 MB)
23 17:57:35.061871 progress 10 % (0 MB)
24 17:57:35.064283 progress 15 % (1 MB)
25 17:57:35.066510 progress 20 % (1 MB)
26 17:57:35.068900 progress 25 % (1 MB)
27 17:57:35.071079 progress 30 % (2 MB)
28 17:57:35.073407 progress 35 % (2 MB)
29 17:57:35.075593 progress 40 % (3 MB)
30 17:57:35.077887 progress 45 % (3 MB)
31 17:57:35.080090 progress 50 % (3 MB)
32 17:57:35.082412 progress 55 % (4 MB)
33 17:57:35.084530 progress 60 % (4 MB)
34 17:57:35.086832 progress 65 % (5 MB)
35 17:57:35.088915 progress 70 % (5 MB)
36 17:57:35.091214 progress 75 % (5 MB)
37 17:57:35.093310 progress 80 % (6 MB)
38 17:57:35.095674 progress 85 % (6 MB)
39 17:57:35.097814 progress 90 % (7 MB)
40 17:57:35.100106 progress 95 % (7 MB)
41 17:57:35.102301 progress 100 % (7 MB)
42 17:57:35.102501 7 MB downloaded in 10.33 s (0.76 MB/s)
43 17:57:35.102648 end: 1.1.1 http-download (duration 00:00:10) [common]
45 17:57:35.102879 end: 1.1 download-retry (duration 00:00:10) [common]
46 17:57:35.102965 start: 1.2 download-retry (timeout 00:09:50) [common]
47 17:57:35.103052 start: 1.2.1 http-download (timeout 00:09:50) [common]
48 17:57:35.103191 downloading http://storage.kernelci.org/mainline/master/v6.9-rc5-53-ge33c4963bf53/arm64/defconfig+arm64-chromebook+videodec/gcc-10/kernel/Image
49 17:57:35.103261 saving as /var/lib/lava/dispatcher/tmp/13522576/tftp-deploy-b23ke98q/kernel/Image
50 17:57:35.103318 total size: 60293632 (57 MB)
51 17:57:35.103377 No compression specified
52 17:57:35.355555 progress 0 % (0 MB)
53 17:57:35.380026 progress 5 % (2 MB)
54 17:57:35.399500 progress 10 % (5 MB)
55 17:57:35.416662 progress 15 % (8 MB)
56 17:57:35.434170 progress 20 % (11 MB)
57 17:57:35.451447 progress 25 % (14 MB)
58 17:57:35.468857 progress 30 % (17 MB)
59 17:57:35.486443 progress 35 % (20 MB)
60 17:57:35.502633 progress 40 % (23 MB)
61 17:57:35.518384 progress 45 % (25 MB)
62 17:57:35.533476 progress 50 % (28 MB)
63 17:57:35.548669 progress 55 % (31 MB)
64 17:57:35.563988 progress 60 % (34 MB)
65 17:57:35.579459 progress 65 % (37 MB)
66 17:57:35.595654 progress 70 % (40 MB)
67 17:57:35.611526 progress 75 % (43 MB)
68 17:57:35.627329 progress 80 % (46 MB)
69 17:57:35.642687 progress 85 % (48 MB)
70 17:57:35.657944 progress 90 % (51 MB)
71 17:57:35.673554 progress 95 % (54 MB)
72 17:57:35.694587 progress 100 % (57 MB)
73 17:57:35.694791 57 MB downloaded in 0.59 s (97.22 MB/s)
74 17:57:35.695017 end: 1.2.1 http-download (duration 00:00:01) [common]
76 17:57:35.695427 end: 1.2 download-retry (duration 00:00:01) [common]
77 17:57:35.695552 start: 1.3 download-retry (timeout 00:09:49) [common]
78 17:57:35.695691 start: 1.3.1 http-download (timeout 00:09:49) [common]
79 17:57:35.695894 downloading http://storage.kernelci.org/mainline/master/v6.9-rc5-53-ge33c4963bf53/arm64/defconfig+arm64-chromebook+videodec/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 17:57:35.696027 saving as /var/lib/lava/dispatcher/tmp/13522576/tftp-deploy-b23ke98q/dtb/mt8192-asurada-spherion-r0.dtb
81 17:57:35.696145 total size: 65280 (0 MB)
82 17:57:35.696295 No compression specified
83 17:57:35.954222 progress 50 % (0 MB)
84 17:57:35.994169 progress 100 % (0 MB)
85 17:57:35.994606 0 MB downloaded in 0.30 s (0.21 MB/s)
86 17:57:35.994822 end: 1.3.1 http-download (duration 00:00:00) [common]
88 17:57:35.995179 end: 1.3 download-retry (duration 00:00:00) [common]
89 17:57:35.995306 start: 1.4 download-retry (timeout 00:09:49) [common]
90 17:57:35.995434 start: 1.4.1 http-download (timeout 00:09:49) [common]
91 17:57:35.995628 downloading http://storage.kernelci.org/mainline/master/v6.9-rc5-53-ge33c4963bf53/arm64/defconfig+arm64-chromebook+videodec/gcc-10/modules.tar.xz
92 17:57:35.995733 saving as /var/lib/lava/dispatcher/tmp/13522576/tftp-deploy-b23ke98q/modules/modules.tar
93 17:57:35.995827 total size: 10028504 (9 MB)
94 17:57:35.995926 Using unxz to decompress xz
95 17:57:36.252186 progress 0 % (0 MB)
96 17:57:36.278982 progress 5 % (0 MB)
97 17:57:36.310367 progress 10 % (0 MB)
98 17:57:36.342001 progress 15 % (1 MB)
99 17:57:36.374928 progress 20 % (1 MB)
100 17:57:36.402163 progress 25 % (2 MB)
101 17:57:36.431300 progress 30 % (2 MB)
102 17:57:36.463437 progress 35 % (3 MB)
103 17:57:36.493454 progress 40 % (3 MB)
104 17:57:36.523947 progress 45 % (4 MB)
105 17:57:36.555208 progress 50 % (4 MB)
106 17:57:36.584351 progress 55 % (5 MB)
107 17:57:36.612449 progress 60 % (5 MB)
108 17:57:36.640798 progress 65 % (6 MB)
109 17:57:36.672796 progress 70 % (6 MB)
110 17:57:36.707503 progress 75 % (7 MB)
111 17:57:36.737576 progress 80 % (7 MB)
112 17:57:36.766514 progress 85 % (8 MB)
113 17:57:36.793713 progress 90 % (8 MB)
114 17:57:36.821305 progress 95 % (9 MB)
115 17:57:36.850737 progress 100 % (9 MB)
116 17:57:36.855289 9 MB downloaded in 0.86 s (11.13 MB/s)
117 17:57:36.855623 end: 1.4.1 http-download (duration 00:00:01) [common]
119 17:57:36.856044 end: 1.4 download-retry (duration 00:00:01) [common]
120 17:57:36.856189 start: 1.5 prepare-tftp-overlay (timeout 00:09:48) [common]
121 17:57:36.856336 start: 1.5.1 extract-nfsrootfs (timeout 00:09:48) [common]
122 17:57:36.856466 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 17:57:36.856603 start: 1.5.2 lava-overlay (timeout 00:09:48) [common]
124 17:57:36.856913 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i
125 17:57:36.857126 makedir: /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin
126 17:57:36.857286 makedir: /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/tests
127 17:57:36.857443 makedir: /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/results
128 17:57:36.857617 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-add-keys
129 17:57:36.857830 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-add-sources
130 17:57:36.858048 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-background-process-start
131 17:57:36.858259 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-background-process-stop
132 17:57:36.858448 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-common-functions
133 17:57:36.858638 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-echo-ipv4
134 17:57:36.858827 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-install-packages
135 17:57:36.859015 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-installed-packages
136 17:57:36.859204 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-os-build
137 17:57:36.859390 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-probe-channel
138 17:57:36.859581 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-probe-ip
139 17:57:36.859776 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-target-ip
140 17:57:36.859965 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-target-mac
141 17:57:36.860157 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-target-storage
142 17:57:36.860351 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-test-case
143 17:57:36.860543 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-test-event
144 17:57:36.860732 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-test-feedback
145 17:57:36.860921 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-test-raise
146 17:57:36.861111 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-test-reference
147 17:57:36.861300 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-test-runner
148 17:57:36.861489 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-test-set
149 17:57:36.861679 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-test-shell
150 17:57:36.861872 Updating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-install-packages (oe)
151 17:57:36.862165 Updating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/bin/lava-installed-packages (oe)
152 17:57:36.862364 Creating /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/environment
153 17:57:36.862517 LAVA metadata
154 17:57:36.862635 - LAVA_JOB_ID=13522576
155 17:57:36.862743 - LAVA_DISPATCHER_IP=192.168.201.1
156 17:57:36.862901 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:48) [common]
157 17:57:36.863020 skipped lava-vland-overlay
158 17:57:36.863142 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 17:57:36.863270 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
160 17:57:36.863374 skipped lava-multinode-overlay
161 17:57:36.863498 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 17:57:36.863637 start: 1.5.2.3 test-definition (timeout 00:09:48) [common]
163 17:57:36.863758 Loading test definitions
164 17:57:36.863904 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:48) [common]
165 17:57:36.864023 Using /lava-13522576 at stage 0
166 17:57:36.864518 uuid=13522576_1.5.2.3.1 testdef=None
167 17:57:36.864653 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 17:57:36.864783 start: 1.5.2.3.2 test-overlay (timeout 00:09:48) [common]
169 17:57:36.865605 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 17:57:36.865959 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:48) [common]
172 17:57:36.867041 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 17:57:36.867416 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
175 17:57:36.868378 runner path: /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/0/tests/0_dmesg test_uuid 13522576_1.5.2.3.1
176 17:57:36.868598 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 17:57:36.868942 Creating lava-test-runner.conf files
179 17:57:36.869044 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13522576/lava-overlay-g__0k33i/lava-13522576/0 for stage 0
180 17:57:36.869180 - 0_dmesg
181 17:57:36.869328 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 17:57:36.869461 start: 1.5.2.4 compress-overlay (timeout 00:09:48) [common]
183 17:57:36.880062 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 17:57:36.880219 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:48) [common]
185 17:57:36.880352 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 17:57:36.880486 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 17:57:36.880621 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:48) [common]
188 17:57:37.120614 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 17:57:37.121095 start: 1.5.4 extract-modules (timeout 00:09:48) [common]
190 17:57:37.121268 extracting modules file /var/lib/lava/dispatcher/tmp/13522576/tftp-deploy-b23ke98q/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13522576/extract-overlay-ramdisk-wmwe8qgz/ramdisk
191 17:57:37.383647 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 17:57:37.383808 start: 1.5.5 apply-overlay-tftp (timeout 00:09:47) [common]
193 17:57:37.383898 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13522576/compress-overlay-tlvvikw4/overlay-1.5.2.4.tar.gz to ramdisk
194 17:57:37.383970 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13522576/compress-overlay-tlvvikw4/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13522576/extract-overlay-ramdisk-wmwe8qgz/ramdisk
195 17:57:37.390680 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 17:57:37.390801 start: 1.5.6 configure-preseed-file (timeout 00:09:47) [common]
197 17:57:37.390895 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 17:57:37.390983 start: 1.5.7 compress-ramdisk (timeout 00:09:47) [common]
199 17:57:37.391062 Building ramdisk /var/lib/lava/dispatcher/tmp/13522576/extract-overlay-ramdisk-wmwe8qgz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13522576/extract-overlay-ramdisk-wmwe8qgz/ramdisk
200 17:57:37.794771 >> 164006 blocks
201 17:57:40.323646 rename /var/lib/lava/dispatcher/tmp/13522576/extract-overlay-ramdisk-wmwe8qgz/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13522576/tftp-deploy-b23ke98q/ramdisk/ramdisk.cpio.gz
202 17:57:40.324065 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 17:57:40.324187 start: 1.5.8 prepare-kernel (timeout 00:09:44) [common]
204 17:57:40.324292 start: 1.5.8.1 prepare-fit (timeout 00:09:44) [common]
205 17:57:40.324404 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13522576/tftp-deploy-b23ke98q/kernel/Image'
206 17:57:55.333557 Returned 0 in 15 seconds
207 17:57:55.434208 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13522576/tftp-deploy-b23ke98q/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13522576/tftp-deploy-b23ke98q/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13522576/tftp-deploy-b23ke98q/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13522576/tftp-deploy-b23ke98q/kernel/image.itb
208 17:57:55.845009 output: FIT description: Kernel Image image with one or more FDT blobs
209 17:57:55.845405 output: Created: Thu Apr 25 18:57:55 2024
210 17:57:55.845482 output: Image 0 (kernel-1)
211 17:57:55.845548 output: Description:
212 17:57:55.845616 output: Created: Thu Apr 25 18:57:55 2024
213 17:57:55.845683 output: Type: Kernel Image
214 17:57:55.845749 output: Compression: lzma compressed
215 17:57:55.845817 output: Data Size: 13647546 Bytes = 13327.68 KiB = 13.02 MiB
216 17:57:55.845875 output: Architecture: AArch64
217 17:57:55.845934 output: OS: Linux
218 17:57:55.845993 output: Load Address: 0x00000000
219 17:57:55.846106 output: Entry Point: 0x00000000
220 17:57:55.846165 output: Hash algo: crc32
221 17:57:55.846221 output: Hash value: 1ae248b6
222 17:57:55.846277 output: Image 1 (fdt-1)
223 17:57:55.846342 output: Description: mt8192-asurada-spherion-r0
224 17:57:55.846398 output: Created: Thu Apr 25 18:57:55 2024
225 17:57:55.846450 output: Type: Flat Device Tree
226 17:57:55.846502 output: Compression: uncompressed
227 17:57:55.846558 output: Data Size: 65280 Bytes = 63.75 KiB = 0.06 MiB
228 17:57:55.846612 output: Architecture: AArch64
229 17:57:55.846663 output: Hash algo: crc32
230 17:57:55.846714 output: Hash value: 81319159
231 17:57:55.846765 output: Image 2 (ramdisk-1)
232 17:57:55.846822 output: Description: unavailable
233 17:57:55.846874 output: Created: Thu Apr 25 18:57:55 2024
234 17:57:55.846926 output: Type: RAMDisk Image
235 17:57:55.846977 output: Compression: Unknown Compression
236 17:57:55.847039 output: Data Size: 23608191 Bytes = 23054.87 KiB = 22.51 MiB
237 17:57:55.847100 output: Architecture: AArch64
238 17:57:55.847151 output: OS: Linux
239 17:57:55.847202 output: Load Address: unavailable
240 17:57:55.847254 output: Entry Point: unavailable
241 17:57:55.847311 output: Hash algo: crc32
242 17:57:55.847362 output: Hash value: d13ec43b
243 17:57:55.847412 output: Default Configuration: 'conf-1'
244 17:57:55.847463 output: Configuration 0 (conf-1)
245 17:57:55.847514 output: Description: mt8192-asurada-spherion-r0
246 17:57:55.847571 output: Kernel: kernel-1
247 17:57:55.847621 output: Init Ramdisk: ramdisk-1
248 17:57:55.847672 output: FDT: fdt-1
249 17:57:55.847722 output: Loadables: kernel-1
250 17:57:55.847778 output:
251 17:57:55.847980 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 17:57:55.848083 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 17:57:55.848184 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 17:57:55.848278 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:29) [common]
255 17:57:55.848359 No LXC device requested
256 17:57:55.848452 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 17:57:55.848539 start: 1.7 deploy-device-env (timeout 00:09:29) [common]
258 17:57:55.848639 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 17:57:55.848741 Checking files for TFTP limit of 4294967296 bytes.
260 17:57:55.849479 end: 1 tftp-deploy (duration 00:00:31) [common]
261 17:57:55.849596 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 17:57:55.849685 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 17:57:55.849817 substitutions:
264 17:57:55.849882 - {DTB}: 13522576/tftp-deploy-b23ke98q/dtb/mt8192-asurada-spherion-r0.dtb
265 17:57:55.849952 - {INITRD}: 13522576/tftp-deploy-b23ke98q/ramdisk/ramdisk.cpio.gz
266 17:57:55.850011 - {KERNEL}: 13522576/tftp-deploy-b23ke98q/kernel/Image
267 17:57:55.850110 - {LAVA_MAC}: None
268 17:57:55.850167 - {PRESEED_CONFIG}: None
269 17:57:55.850228 - {PRESEED_LOCAL}: None
270 17:57:55.850282 - {RAMDISK}: 13522576/tftp-deploy-b23ke98q/ramdisk/ramdisk.cpio.gz
271 17:57:55.850336 - {ROOT_PART}: None
272 17:57:55.850389 - {ROOT}: None
273 17:57:55.850448 - {SERVER_IP}: 192.168.201.1
274 17:57:55.850500 - {TEE}: None
275 17:57:55.850553 Parsed boot commands:
276 17:57:55.850604 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 17:57:55.850786 Parsed boot commands: tftpboot 192.168.201.1 13522576/tftp-deploy-b23ke98q/kernel/image.itb 13522576/tftp-deploy-b23ke98q/kernel/cmdline
278 17:57:55.850874 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 17:57:55.850966 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 17:57:55.851078 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 17:57:55.851203 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 17:57:55.851306 Not connected, no need to disconnect.
283 17:57:55.851411 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 17:57:55.851493 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 17:57:55.851562 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 17:57:55.855410 Setting prompt string to ['lava-test: # ']
287 17:57:55.855797 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 17:57:55.855903 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 17:57:55.856008 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 17:57:55.856100 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 17:57:55.856321 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
292 17:58:00.982872 >> Command sent successfully.
293 17:58:00.985287 Returned 0 in 5 seconds
294 17:58:01.085675 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 17:58:01.086129 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 17:58:01.086231 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 17:58:01.086316 Setting prompt string to 'Starting depthcharge on Spherion...'
299 17:58:01.086382 Changing prompt to 'Starting depthcharge on Spherion...'
300 17:58:01.086455 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 17:58:01.086717 [Enter `^Ec?' for help]
302 17:58:01.269264
303 17:58:01.269424
304 17:58:01.269513 F0: 102B 0000
305 17:58:01.269580
306 17:58:01.269643 F3: 1001 0000 [0200]
307 17:58:01.272318
308 17:58:01.272390 F3: 1001 0000
309 17:58:01.272450
310 17:58:01.272507 F7: 102D 0000
311 17:58:01.272568
312 17:58:01.275544 F1: 0000 0000
313 17:58:01.275622
314 17:58:01.275685 V0: 0000 0000 [0001]
315 17:58:01.275740
316 17:58:01.278636 00: 0007 8000
317 17:58:01.278723
318 17:58:01.278779 01: 0000 0000
319 17:58:01.278835
320 17:58:01.281873 BP: 0C00 0209 [0000]
321 17:58:01.281978
322 17:58:01.282117 G0: 1182 0000
323 17:58:01.282208
324 17:58:01.285496 EC: 0000 0021 [4000]
325 17:58:01.285569
326 17:58:01.285628 S7: 0000 0000 [0000]
327 17:58:01.285684
328 17:58:01.289428 CC: 0000 0000 [0001]
329 17:58:01.289531
330 17:58:01.289660 T0: 0000 0040 [010F]
331 17:58:01.289763
332 17:58:01.289860 Jump to BL
333 17:58:01.289983
334 17:58:01.316258
335 17:58:01.316375
336 17:58:01.316444
337 17:58:01.323109 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 17:58:01.326585 ARM64: Exception handlers installed.
339 17:58:01.330299 ARM64: Testing exception
340 17:58:01.333239 ARM64: Done test exception
341 17:58:01.340171 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 17:58:01.349840 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 17:58:01.356892 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 17:58:01.367066 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 17:58:01.373533 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 17:58:01.383740 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 17:58:01.394436 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 17:58:01.400823 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 17:58:01.418692 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 17:58:01.421807 WDT: Last reset was cold boot
351 17:58:01.425061 SPI1(PAD0) initialized at 2873684 Hz
352 17:58:01.428804 SPI5(PAD0) initialized at 992727 Hz
353 17:58:01.431938 VBOOT: Loading verstage.
354 17:58:01.438834 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 17:58:01.441891 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 17:58:01.445068 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 17:58:01.448791 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 17:58:01.456198 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 17:58:01.462881 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 17:58:01.473618 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 17:58:01.473707
362 17:58:01.473793
363 17:58:01.483626 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 17:58:01.486846 ARM64: Exception handlers installed.
365 17:58:01.489977 ARM64: Testing exception
366 17:58:01.490090 ARM64: Done test exception
367 17:58:01.496875 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 17:58:01.500616 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 17:58:01.515116 Probing TPM: . done!
370 17:58:01.515201 TPM ready after 0 ms
371 17:58:01.521526 Connected to device vid:did:rid of 1ae0:0028:00
372 17:58:01.528543 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
373 17:58:01.531871 Initialized TPM device CR50 revision 0
374 17:58:01.593311 tlcl_send_startup: Startup return code is 0
375 17:58:01.593470 TPM: setup succeeded
376 17:58:01.605850 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 17:58:01.613581 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 17:58:01.623507 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 17:58:01.632149 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 17:58:01.635441 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 17:58:01.639371 in-header: 03 07 00 00 08 00 00 00
382 17:58:01.642610 in-data: aa e4 47 04 13 02 00 00
383 17:58:01.645953 Chrome EC: UHEPI supported
384 17:58:01.652039 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 17:58:01.664731 in-header: 03 95 00 00 08 00 00 00
386 17:58:01.668604 in-data: 18 20 20 08 00 00 00 00
387 17:58:01.669103 Phase 1
388 17:58:01.672439 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 17:58:01.679416 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 17:58:01.686515 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 17:58:01.686959 Recovery requested (1009000e)
392 17:58:01.697133 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 17:58:01.702859 tlcl_extend: response is 0
394 17:58:01.711756 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 17:58:01.717078 tlcl_extend: response is 0
396 17:58:01.724187 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 17:58:01.745656 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 17:58:01.752671 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 17:58:01.753108
400 17:58:01.753440
401 17:58:01.759647 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 17:58:01.763679 ARM64: Exception handlers installed.
403 17:58:01.766803 ARM64: Testing exception
404 17:58:01.770095 ARM64: Done test exception
405 17:58:01.790013 pmic_efuse_setting: Set efuses in 11 msecs
406 17:58:01.793067 pmwrap_interface_init: Select PMIF_VLD_RDY
407 17:58:01.800005 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 17:58:01.803231 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 17:58:01.810073 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 17:58:01.813150 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 17:58:01.820022 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 17:58:01.822793 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 17:58:01.829798 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 17:58:01.832844 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 17:58:01.836069 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 17:58:01.843027 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 17:58:01.846243 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 17:58:01.853270 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 17:58:01.857083 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 17:58:01.860912 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 17:58:01.868030 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 17:58:01.874871 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 17:58:01.878847 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 17:58:01.885734 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 17:58:01.889526 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 17:58:01.896957 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 17:58:01.900156 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 17:58:01.907242 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 17:58:01.914819 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 17:58:01.917923 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 17:58:01.921608 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 17:58:01.929289 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 17:58:01.936394 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 17:58:01.940134 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 17:58:01.943336 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 17:58:01.947267 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 17:58:01.954387 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 17:58:01.958345 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 17:58:01.965287 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 17:58:01.969284 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 17:58:01.972906 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 17:58:01.979898 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 17:58:01.983768 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 17:58:01.990862 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 17:58:01.994556 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 17:58:01.997705 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 17:58:02.001409 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 17:58:02.005052 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 17:58:02.012629 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 17:58:02.016312 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 17:58:02.019535 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 17:58:02.023419 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 17:58:02.027147 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 17:58:02.034393 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 17:58:02.037584 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 17:58:02.041414 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 17:58:02.044951 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 17:58:02.051952 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 17:58:02.062607 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 17:58:02.066298 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 17:58:02.073929 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 17:58:02.080947 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 17:58:02.087990 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 17:58:02.091940 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 17:58:02.095154 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 17:58:02.102727 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x31
467 17:58:02.106364 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 17:58:02.114532 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 17:58:02.117641 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 17:58:02.127034 [RTC]rtc_get_frequency_meter,154: input=15, output=764
471 17:58:02.136588 [RTC]rtc_get_frequency_meter,154: input=23, output=948
472 17:58:02.145794 [RTC]rtc_get_frequency_meter,154: input=19, output=857
473 17:58:02.155781 [RTC]rtc_get_frequency_meter,154: input=17, output=810
474 17:58:02.165666 [RTC]rtc_get_frequency_meter,154: input=16, output=787
475 17:58:02.174979 [RTC]rtc_get_frequency_meter,154: input=16, output=787
476 17:58:02.184730 [RTC]rtc_get_frequency_meter,154: input=17, output=809
477 17:58:02.187934 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 17:58:02.195146 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 17:58:02.198421 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 17:58:02.202346 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 17:58:02.205389 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 17:58:02.209065 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 17:58:02.213229 ADC[4]: Raw value=670063 ID=5
484 17:58:02.216483 ADC[3]: Raw value=212549 ID=1
485 17:58:02.216569 RAM Code: 0x51
486 17:58:02.220357 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 17:58:02.227124 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 17:58:02.234749 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 17:58:02.241869 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 17:58:02.245111 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 17:58:02.248941 in-header: 03 07 00 00 08 00 00 00
492 17:58:02.249024 in-data: aa e4 47 04 13 02 00 00
493 17:58:02.252181 Chrome EC: UHEPI supported
494 17:58:02.259258 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 17:58:02.263706 in-header: 03 95 00 00 08 00 00 00
496 17:58:02.266876 in-data: 18 20 20 08 00 00 00 00
497 17:58:02.270484 MRC: failed to locate region type 0.
498 17:58:02.277497 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 17:58:02.281414 DRAM-K: Running full calibration
500 17:58:02.284926 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 17:58:02.288256 header.status = 0x0
502 17:58:02.291952 header.version = 0x6 (expected: 0x6)
503 17:58:02.295219 header.size = 0xd00 (expected: 0xd00)
504 17:58:02.295305 header.flags = 0x0
505 17:58:02.302567 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 17:58:02.321253 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
507 17:58:02.328788 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 17:58:02.328877 dram_init: ddr_geometry: 0
509 17:58:02.332504 [EMI] MDL number = 0
510 17:58:02.335703 [EMI] Get MDL freq = 0
511 17:58:02.335789 dram_init: ddr_type: 0
512 17:58:02.339456 is_discrete_lpddr4: 1
513 17:58:02.343422 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 17:58:02.343506
515 17:58:02.343593
516 17:58:02.343674 [Bian_co] ETT version 0.0.0.1
517 17:58:02.350709 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 17:58:02.350794
519 17:58:02.354055 dramc_set_vcore_voltage set vcore to 650000
520 17:58:02.354154 Read voltage for 800, 4
521 17:58:02.357876 Vio18 = 0
522 17:58:02.357961 Vcore = 650000
523 17:58:02.358102 Vdram = 0
524 17:58:02.358208 Vddq = 0
525 17:58:02.361782 Vmddr = 0
526 17:58:02.361868 dram_init: config_dvfs: 1
527 17:58:02.368888 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 17:58:02.372695 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 17:58:02.376660 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 17:58:02.379698 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 17:58:02.383658 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 17:58:02.387493 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 17:58:02.391221 MEM_TYPE=3, freq_sel=18
534 17:58:02.394832 sv_algorithm_assistance_LP4_1600
535 17:58:02.398379 ============ PULL DRAM RESETB DOWN ============
536 17:58:02.401761 ========== PULL DRAM RESETB DOWN end =========
537 17:58:02.405497 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 17:58:02.409281 ===================================
539 17:58:02.412851 LPDDR4 DRAM CONFIGURATION
540 17:58:02.416805 ===================================
541 17:58:02.416893 EX_ROW_EN[0] = 0x0
542 17:58:02.419988 EX_ROW_EN[1] = 0x0
543 17:58:02.420074 LP4Y_EN = 0x0
544 17:58:02.424030 WORK_FSP = 0x0
545 17:58:02.424115 WL = 0x2
546 17:58:02.427610 RL = 0x2
547 17:58:02.427696 BL = 0x2
548 17:58:02.431379 RPST = 0x0
549 17:58:02.431464 RD_PRE = 0x0
550 17:58:02.434568 WR_PRE = 0x1
551 17:58:02.434653 WR_PST = 0x0
552 17:58:02.438350 DBI_WR = 0x0
553 17:58:02.438437 DBI_RD = 0x0
554 17:58:02.442167 OTF = 0x1
555 17:58:02.442253 ===================================
556 17:58:02.445519 ===================================
557 17:58:02.449483 ANA top config
558 17:58:02.453573 ===================================
559 17:58:02.453658 DLL_ASYNC_EN = 0
560 17:58:02.456891 ALL_SLAVE_EN = 1
561 17:58:02.460156 NEW_RANK_MODE = 1
562 17:58:02.463367 DLL_IDLE_MODE = 1
563 17:58:02.463454 LP45_APHY_COMB_EN = 1
564 17:58:02.466679 TX_ODT_DIS = 1
565 17:58:02.469948 NEW_8X_MODE = 1
566 17:58:02.473153 ===================================
567 17:58:02.476334 ===================================
568 17:58:02.480035 data_rate = 1600
569 17:58:02.480120 CKR = 1
570 17:58:02.483184 DQ_P2S_RATIO = 8
571 17:58:02.487143 ===================================
572 17:58:02.490384 CA_P2S_RATIO = 8
573 17:58:02.494313 DQ_CA_OPEN = 0
574 17:58:02.497498 DQ_SEMI_OPEN = 0
575 17:58:02.497583 CA_SEMI_OPEN = 0
576 17:58:02.500658 CA_FULL_RATE = 0
577 17:58:02.503948 DQ_CKDIV4_EN = 1
578 17:58:02.507145 CA_CKDIV4_EN = 1
579 17:58:02.510880 CA_PREDIV_EN = 0
580 17:58:02.514660 PH8_DLY = 0
581 17:58:02.514750 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 17:58:02.518201 DQ_AAMCK_DIV = 4
583 17:58:02.521465 CA_AAMCK_DIV = 4
584 17:58:02.524779 CA_ADMCK_DIV = 4
585 17:58:02.524864 DQ_TRACK_CA_EN = 0
586 17:58:02.527959 CA_PICK = 800
587 17:58:02.531755 CA_MCKIO = 800
588 17:58:02.534642 MCKIO_SEMI = 0
589 17:58:02.538776 PLL_FREQ = 3068
590 17:58:02.542317 DQ_UI_PI_RATIO = 32
591 17:58:02.542395 CA_UI_PI_RATIO = 0
592 17:58:02.546193 ===================================
593 17:58:02.550035 ===================================
594 17:58:02.553105 memory_type:LPDDR4
595 17:58:02.553210 GP_NUM : 10
596 17:58:02.557073 SRAM_EN : 1
597 17:58:02.557177 MD32_EN : 0
598 17:58:02.561091 ===================================
599 17:58:02.564782 [ANA_INIT] >>>>>>>>>>>>>>
600 17:58:02.567979 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 17:58:02.571947 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 17:58:02.575652 ===================================
603 17:58:02.575755 data_rate = 1600,PCW = 0X7600
604 17:58:02.578903 ===================================
605 17:58:02.582172 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 17:58:02.588614 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 17:58:02.595569 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 17:58:02.598866 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 17:58:02.601984 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 17:58:02.605256 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 17:58:02.609107 [ANA_INIT] flow start
612 17:58:02.609192 [ANA_INIT] PLL >>>>>>>>
613 17:58:02.612285 [ANA_INIT] PLL <<<<<<<<
614 17:58:02.615510 [ANA_INIT] MIDPI >>>>>>>>
615 17:58:02.618757 [ANA_INIT] MIDPI <<<<<<<<
616 17:58:02.618841 [ANA_INIT] DLL >>>>>>>>
617 17:58:02.621934 [ANA_INIT] flow end
618 17:58:02.625828 ============ LP4 DIFF to SE enter ============
619 17:58:02.629012 ============ LP4 DIFF to SE exit ============
620 17:58:02.632068 [ANA_INIT] <<<<<<<<<<<<<
621 17:58:02.635175 [Flow] Enable top DCM control >>>>>
622 17:58:02.638722 [Flow] Enable top DCM control <<<<<
623 17:58:02.642236 Enable DLL master slave shuffle
624 17:58:02.645138 ==============================================================
625 17:58:02.648473 Gating Mode config
626 17:58:02.655287 ==============================================================
627 17:58:02.655380 Config description:
628 17:58:02.665413 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 17:58:02.671792 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 17:58:02.678737 SELPH_MODE 0: By rank 1: By Phase
631 17:58:02.681948 ==============================================================
632 17:58:02.685123 GAT_TRACK_EN = 1
633 17:58:02.688423 RX_GATING_MODE = 2
634 17:58:02.692151 RX_GATING_TRACK_MODE = 2
635 17:58:02.695424 SELPH_MODE = 1
636 17:58:02.698746 PICG_EARLY_EN = 1
637 17:58:02.702095 VALID_LAT_VALUE = 1
638 17:58:02.705340 ==============================================================
639 17:58:02.708545 Enter into Gating configuration >>>>
640 17:58:02.711744 Exit from Gating configuration <<<<
641 17:58:02.715564 Enter into DVFS_PRE_config >>>>>
642 17:58:02.728474 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 17:58:02.728559 Exit from DVFS_PRE_config <<<<<
644 17:58:02.731648 Enter into PICG configuration >>>>
645 17:58:02.735400 Exit from PICG configuration <<<<
646 17:58:02.738716 [RX_INPUT] configuration >>>>>
647 17:58:02.741770 [RX_INPUT] configuration <<<<<
648 17:58:02.748794 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 17:58:02.751845 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 17:58:02.758223 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 17:58:02.764946 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 17:58:02.771736 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 17:58:02.778264 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 17:58:02.781638 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 17:58:02.784884 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 17:58:02.788157 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 17:58:02.795082 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 17:58:02.798332 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 17:58:02.801517 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 17:58:02.804813 ===================================
661 17:58:02.807969 LPDDR4 DRAM CONFIGURATION
662 17:58:02.811806 ===================================
663 17:58:02.811913 EX_ROW_EN[0] = 0x0
664 17:58:02.815049 EX_ROW_EN[1] = 0x0
665 17:58:02.818256 LP4Y_EN = 0x0
666 17:58:02.818359 WORK_FSP = 0x0
667 17:58:02.821474 WL = 0x2
668 17:58:02.821565 RL = 0x2
669 17:58:02.824766 BL = 0x2
670 17:58:02.824868 RPST = 0x0
671 17:58:02.827980 RD_PRE = 0x0
672 17:58:02.828085 WR_PRE = 0x1
673 17:58:02.831907 WR_PST = 0x0
674 17:58:02.832012 DBI_WR = 0x0
675 17:58:02.835114 DBI_RD = 0x0
676 17:58:02.835214 OTF = 0x1
677 17:58:02.838362 ===================================
678 17:58:02.841536 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 17:58:02.848513 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 17:58:02.851756 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 17:58:02.854832 ===================================
682 17:58:02.857883 LPDDR4 DRAM CONFIGURATION
683 17:58:02.861471 ===================================
684 17:58:02.861615 EX_ROW_EN[0] = 0x10
685 17:58:02.864986 EX_ROW_EN[1] = 0x0
686 17:58:02.865088 LP4Y_EN = 0x0
687 17:58:02.868190 WORK_FSP = 0x0
688 17:58:02.871239 WL = 0x2
689 17:58:02.871369 RL = 0x2
690 17:58:02.875085 BL = 0x2
691 17:58:02.875188 RPST = 0x0
692 17:58:02.878251 RD_PRE = 0x0
693 17:58:02.878325 WR_PRE = 0x1
694 17:58:02.881443 WR_PST = 0x0
695 17:58:02.881541 DBI_WR = 0x0
696 17:58:02.885160 DBI_RD = 0x0
697 17:58:02.885308 OTF = 0x1
698 17:58:02.888274 ===================================
699 17:58:02.895141 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 17:58:02.899009 nWR fixed to 40
701 17:58:02.901916 [ModeRegInit_LP4] CH0 RK0
702 17:58:02.902029 [ModeRegInit_LP4] CH0 RK1
703 17:58:02.905537 [ModeRegInit_LP4] CH1 RK0
704 17:58:02.908633 [ModeRegInit_LP4] CH1 RK1
705 17:58:02.908765 match AC timing 12
706 17:58:02.915728 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 17:58:02.918877 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 17:58:02.922123 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 17:58:02.928569 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 17:58:02.931843 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 17:58:02.931921 [EMI DOE] emi_dcm 0
712 17:58:02.938892 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 17:58:02.938972 ==
714 17:58:02.941960 Dram Type= 6, Freq= 0, CH_0, rank 0
715 17:58:02.945115 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 17:58:02.945213 ==
717 17:58:02.951953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 17:58:02.958297 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 17:58:02.965964 [CA 0] Center 37 (7~68) winsize 62
720 17:58:02.969130 [CA 1] Center 37 (7~68) winsize 62
721 17:58:02.972609 [CA 2] Center 35 (4~66) winsize 63
722 17:58:02.976037 [CA 3] Center 35 (4~66) winsize 63
723 17:58:02.979209 [CA 4] Center 34 (4~65) winsize 62
724 17:58:02.982394 [CA 5] Center 34 (3~65) winsize 63
725 17:58:02.982469
726 17:58:02.985717 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 17:58:02.985819
728 17:58:02.989435 [CATrainingPosCal] consider 1 rank data
729 17:58:02.992605 u2DelayCellTimex100 = 270/100 ps
730 17:58:02.995903 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
731 17:58:02.999622 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
732 17:58:03.005802 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
733 17:58:03.009277 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
734 17:58:03.012929 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
735 17:58:03.015804 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
736 17:58:03.015911
737 17:58:03.019059 CA PerBit enable=1, Macro0, CA PI delay=34
738 17:58:03.019162
739 17:58:03.022655 [CBTSetCACLKResult] CA Dly = 34
740 17:58:03.022758 CS Dly: 5 (0~36)
741 17:58:03.022850 ==
742 17:58:03.025917 Dram Type= 6, Freq= 0, CH_0, rank 1
743 17:58:03.033104 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 17:58:03.033208 ==
745 17:58:03.036361 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 17:58:03.042768 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 17:58:03.051706 [CA 0] Center 37 (7~68) winsize 62
748 17:58:03.054835 [CA 1] Center 37 (7~68) winsize 62
749 17:58:03.058755 [CA 2] Center 35 (4~66) winsize 63
750 17:58:03.062099 [CA 3] Center 35 (4~66) winsize 63
751 17:58:03.065211 [CA 4] Center 33 (3~64) winsize 62
752 17:58:03.068318 [CA 5] Center 34 (3~65) winsize 63
753 17:58:03.068396
754 17:58:03.071611 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 17:58:03.071721
756 17:58:03.074938 [CATrainingPosCal] consider 2 rank data
757 17:58:03.078806 u2DelayCellTimex100 = 270/100 ps
758 17:58:03.081859 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
759 17:58:03.085390 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
760 17:58:03.092082 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
761 17:58:03.095130 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
762 17:58:03.098429 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
763 17:58:03.101731 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
764 17:58:03.101832
765 17:58:03.104879 CA PerBit enable=1, Macro0, CA PI delay=34
766 17:58:03.104981
767 17:58:03.108603 [CBTSetCACLKResult] CA Dly = 34
768 17:58:03.108704 CS Dly: 5 (0~37)
769 17:58:03.108800
770 17:58:03.111940 ----->DramcWriteLeveling(PI) begin...
771 17:58:03.115070 ==
772 17:58:03.115165 Dram Type= 6, Freq= 0, CH_0, rank 0
773 17:58:03.123025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 17:58:03.123120 ==
775 17:58:03.125962 Write leveling (Byte 0): 27 => 27
776 17:58:03.126101 Write leveling (Byte 1): 28 => 28
777 17:58:03.129608 DramcWriteLeveling(PI) end<-----
778 17:58:03.129729
779 17:58:03.129828 ==
780 17:58:03.133796 Dram Type= 6, Freq= 0, CH_0, rank 0
781 17:58:03.136570 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 17:58:03.136689 ==
783 17:58:03.140443 [Gating] SW mode calibration
784 17:58:03.147527 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 17:58:03.153964 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 17:58:03.157297 0 6 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
787 17:58:03.161037 0 6 4 | B1->B0 | 2f2f 2727 | 1 0 | (1 0) (1 0)
788 17:58:03.167473 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 17:58:03.170573 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 17:58:03.174387 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 17:58:03.180952 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 17:58:03.184273 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 17:58:03.187335 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 17:58:03.194090 0 7 0 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
795 17:58:03.197711 0 7 4 | B1->B0 | 3737 4141 | 0 0 | (0 0) (1 1)
796 17:58:03.200708 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 17:58:03.207636 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 17:58:03.210813 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 17:58:03.214012 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 17:58:03.220696 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 17:58:03.223931 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 17:58:03.227219 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
803 17:58:03.230477 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 17:58:03.237350 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 17:58:03.241019 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 17:58:03.243944 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 17:58:03.250760 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 17:58:03.253885 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 17:58:03.257620 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 17:58:03.264104 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 17:58:03.267291 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 17:58:03.270417 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 17:58:03.277419 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 17:58:03.280679 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 17:58:03.283766 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 17:58:03.290885 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 17:58:03.294087 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 17:58:03.297139 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
819 17:58:03.304140 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
820 17:58:03.304215 Total UI for P1: 0, mck2ui 16
821 17:58:03.310768 best dqsien dly found for B0: ( 0, 10, 2)
822 17:58:03.310876 Total UI for P1: 0, mck2ui 16
823 17:58:03.317380 best dqsien dly found for B1: ( 0, 10, 0)
824 17:58:03.320543 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
825 17:58:03.323718 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
826 17:58:03.323792
827 17:58:03.326991 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
828 17:58:03.330758 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
829 17:58:03.333899 [Gating] SW calibration Done
830 17:58:03.333995 ==
831 17:58:03.337228 Dram Type= 6, Freq= 0, CH_0, rank 0
832 17:58:03.340480 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
833 17:58:03.340603 ==
834 17:58:03.343639 RX Vref Scan: 0
835 17:58:03.343751
836 17:58:03.343851 RX Vref 0 -> 0, step: 1
837 17:58:03.343946
838 17:58:03.347447 RX Delay -130 -> 252, step: 16
839 17:58:03.350646 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
840 17:58:03.357189 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
841 17:58:03.360676 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
842 17:58:03.363992 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
843 17:58:03.367513 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
844 17:58:03.370411 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
845 17:58:03.374069 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
846 17:58:03.380399 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
847 17:58:03.383735 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
848 17:58:03.387536 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
849 17:58:03.390766 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
850 17:58:03.394006 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
851 17:58:03.400466 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
852 17:58:03.403756 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
853 17:58:03.407716 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
854 17:58:03.410909 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
855 17:58:03.410992 ==
856 17:58:03.414154 Dram Type= 6, Freq= 0, CH_0, rank 0
857 17:58:03.420959 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
858 17:58:03.421050 ==
859 17:58:03.421118 DQS Delay:
860 17:58:03.424035 DQS0 = 0, DQS1 = 0
861 17:58:03.424116 DQM Delay:
862 17:58:03.424180 DQM0 = 85, DQM1 = 75
863 17:58:03.427537 DQ Delay:
864 17:58:03.430663 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
865 17:58:03.433934 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
866 17:58:03.437109 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =69
867 17:58:03.440251 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
868 17:58:03.440329
869 17:58:03.440398
870 17:58:03.440458 ==
871 17:58:03.443481 Dram Type= 6, Freq= 0, CH_0, rank 0
872 17:58:03.447334 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 17:58:03.447412 ==
874 17:58:03.447483
875 17:58:03.447543
876 17:58:03.450639 TX Vref Scan disable
877 17:58:03.453850 == TX Byte 0 ==
878 17:58:03.457033 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
879 17:58:03.460212 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
880 17:58:03.463395 == TX Byte 1 ==
881 17:58:03.466557 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
882 17:58:03.470185 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
883 17:58:03.470272 ==
884 17:58:03.473159 Dram Type= 6, Freq= 0, CH_0, rank 0
885 17:58:03.476531 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 17:58:03.479862 ==
887 17:58:03.491082 TX Vref=22, minBit 0, minWin=27, winSum=443
888 17:58:03.494496 TX Vref=24, minBit 3, minWin=27, winSum=447
889 17:58:03.497455 TX Vref=26, minBit 0, minWin=28, winSum=450
890 17:58:03.501250 TX Vref=28, minBit 0, minWin=28, winSum=454
891 17:58:03.504529 TX Vref=30, minBit 0, minWin=28, winSum=455
892 17:58:03.507692 TX Vref=32, minBit 1, minWin=27, winSum=451
893 17:58:03.514748 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
894 17:58:03.514832
895 17:58:03.518141 Final TX Range 1 Vref 30
896 17:58:03.518231
897 17:58:03.518297 ==
898 17:58:03.521318 Dram Type= 6, Freq= 0, CH_0, rank 0
899 17:58:03.524986 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 17:58:03.525090 ==
901 17:58:03.525193
902 17:58:03.525283
903 17:58:03.528251 TX Vref Scan disable
904 17:58:03.531364 == TX Byte 0 ==
905 17:58:03.535079 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
906 17:58:03.537958 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
907 17:58:03.541152 == TX Byte 1 ==
908 17:58:03.544971 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
909 17:58:03.548051 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
910 17:58:03.548182
911 17:58:03.551307 [DATLAT]
912 17:58:03.551406 Freq=800, CH0 RK0
913 17:58:03.551472
914 17:58:03.554573 DATLAT Default: 0xa
915 17:58:03.554647 0, 0xFFFF, sum = 0
916 17:58:03.557776 1, 0xFFFF, sum = 0
917 17:58:03.557886 2, 0xFFFF, sum = 0
918 17:58:03.561085 3, 0xFFFF, sum = 0
919 17:58:03.561187 4, 0xFFFF, sum = 0
920 17:58:03.564850 5, 0xFFFF, sum = 0
921 17:58:03.564963 6, 0xFFFF, sum = 0
922 17:58:03.568098 7, 0xFFFF, sum = 0
923 17:58:03.568199 8, 0x0, sum = 1
924 17:58:03.571355 9, 0x0, sum = 2
925 17:58:03.571462 10, 0x0, sum = 3
926 17:58:03.574503 11, 0x0, sum = 4
927 17:58:03.574609 best_step = 9
928 17:58:03.574707
929 17:58:03.574796 ==
930 17:58:03.577790 Dram Type= 6, Freq= 0, CH_0, rank 0
931 17:58:03.581515 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
932 17:58:03.584620 ==
933 17:58:03.584726 RX Vref Scan: 1
934 17:58:03.584825
935 17:58:03.588158 Set Vref Range= 32 -> 127
936 17:58:03.588255
937 17:58:03.591208 RX Vref 32 -> 127, step: 1
938 17:58:03.591316
939 17:58:03.591412 RX Delay -111 -> 252, step: 8
940 17:58:03.591508
941 17:58:03.594712 Set Vref, RX VrefLevel [Byte0]: 32
942 17:58:03.597551 [Byte1]: 32
943 17:58:03.601842
944 17:58:03.601940 Set Vref, RX VrefLevel [Byte0]: 33
945 17:58:03.605148 [Byte1]: 33
946 17:58:03.609648
947 17:58:03.609751 Set Vref, RX VrefLevel [Byte0]: 34
948 17:58:03.613049 [Byte1]: 34
949 17:58:03.617425
950 17:58:03.617500 Set Vref, RX VrefLevel [Byte0]: 35
951 17:58:03.620855 [Byte1]: 35
952 17:58:03.624619
953 17:58:03.624727 Set Vref, RX VrefLevel [Byte0]: 36
954 17:58:03.627870 [Byte1]: 36
955 17:58:03.632786
956 17:58:03.632889 Set Vref, RX VrefLevel [Byte0]: 37
957 17:58:03.635988 [Byte1]: 37
958 17:58:03.640391
959 17:58:03.640463 Set Vref, RX VrefLevel [Byte0]: 38
960 17:58:03.643458 [Byte1]: 38
961 17:58:03.647646
962 17:58:03.647745 Set Vref, RX VrefLevel [Byte0]: 39
963 17:58:03.650757 [Byte1]: 39
964 17:58:03.655158
965 17:58:03.655270 Set Vref, RX VrefLevel [Byte0]: 40
966 17:58:03.658445 [Byte1]: 40
967 17:58:03.662917
968 17:58:03.663014 Set Vref, RX VrefLevel [Byte0]: 41
969 17:58:03.666147 [Byte1]: 41
970 17:58:03.670611
971 17:58:03.670692 Set Vref, RX VrefLevel [Byte0]: 42
972 17:58:03.673844 [Byte1]: 42
973 17:58:03.678394
974 17:58:03.678488 Set Vref, RX VrefLevel [Byte0]: 43
975 17:58:03.681618 [Byte1]: 43
976 17:58:03.686164
977 17:58:03.686245 Set Vref, RX VrefLevel [Byte0]: 44
978 17:58:03.689380 [Byte1]: 44
979 17:58:03.693794
980 17:58:03.693903 Set Vref, RX VrefLevel [Byte0]: 45
981 17:58:03.696972 [Byte1]: 45
982 17:58:03.701432
983 17:58:03.701550 Set Vref, RX VrefLevel [Byte0]: 46
984 17:58:03.704645 [Byte1]: 46
985 17:58:03.709084
986 17:58:03.709198 Set Vref, RX VrefLevel [Byte0]: 47
987 17:58:03.712190 [Byte1]: 47
988 17:58:03.716413
989 17:58:03.716534 Set Vref, RX VrefLevel [Byte0]: 48
990 17:58:03.719915 [Byte1]: 48
991 17:58:03.723898
992 17:58:03.723982 Set Vref, RX VrefLevel [Byte0]: 49
993 17:58:03.727419 [Byte1]: 49
994 17:58:03.732067
995 17:58:03.732167 Set Vref, RX VrefLevel [Byte0]: 50
996 17:58:03.735069 [Byte1]: 50
997 17:58:03.739744
998 17:58:03.739827 Set Vref, RX VrefLevel [Byte0]: 51
999 17:58:03.742893 [Byte1]: 51
1000 17:58:03.747402
1001 17:58:03.747498 Set Vref, RX VrefLevel [Byte0]: 52
1002 17:58:03.750437 [Byte1]: 52
1003 17:58:03.754763
1004 17:58:03.754845 Set Vref, RX VrefLevel [Byte0]: 53
1005 17:58:03.757958 [Byte1]: 53
1006 17:58:03.762716
1007 17:58:03.762838 Set Vref, RX VrefLevel [Byte0]: 54
1008 17:58:03.765888 [Byte1]: 54
1009 17:58:03.769880
1010 17:58:03.769962 Set Vref, RX VrefLevel [Byte0]: 55
1011 17:58:03.773120 [Byte1]: 55
1012 17:58:03.777589
1013 17:58:03.777672 Set Vref, RX VrefLevel [Byte0]: 56
1014 17:58:03.780804 [Byte1]: 56
1015 17:58:03.785297
1016 17:58:03.785380 Set Vref, RX VrefLevel [Byte0]: 57
1017 17:58:03.788569 [Byte1]: 57
1018 17:58:03.793072
1019 17:58:03.793154 Set Vref, RX VrefLevel [Byte0]: 58
1020 17:58:03.796818 [Byte1]: 58
1021 17:58:03.801297
1022 17:58:03.801380 Set Vref, RX VrefLevel [Byte0]: 59
1023 17:58:03.804514 [Byte1]: 59
1024 17:58:03.809008
1025 17:58:03.809095 Set Vref, RX VrefLevel [Byte0]: 60
1026 17:58:03.812132 [Byte1]: 60
1027 17:58:03.816577
1028 17:58:03.816682 Set Vref, RX VrefLevel [Byte0]: 61
1029 17:58:03.819755 [Byte1]: 61
1030 17:58:03.823582
1031 17:58:03.823660 Set Vref, RX VrefLevel [Byte0]: 62
1032 17:58:03.826668 [Byte1]: 62
1033 17:58:03.831177
1034 17:58:03.831253 Set Vref, RX VrefLevel [Byte0]: 63
1035 17:58:03.834226 [Byte1]: 63
1036 17:58:03.838511
1037 17:58:03.838620 Set Vref, RX VrefLevel [Byte0]: 64
1038 17:58:03.842092 [Byte1]: 64
1039 17:58:03.846260
1040 17:58:03.846359 Set Vref, RX VrefLevel [Byte0]: 65
1041 17:58:03.849927 [Byte1]: 65
1042 17:58:03.853891
1043 17:58:03.853999 Set Vref, RX VrefLevel [Byte0]: 66
1044 17:58:03.857083 [Byte1]: 66
1045 17:58:03.861620
1046 17:58:03.861727 Set Vref, RX VrefLevel [Byte0]: 67
1047 17:58:03.865450 [Byte1]: 67
1048 17:58:03.869658
1049 17:58:03.869770 Set Vref, RX VrefLevel [Byte0]: 68
1050 17:58:03.872813 [Byte1]: 68
1051 17:58:03.877260
1052 17:58:03.877373 Set Vref, RX VrefLevel [Byte0]: 69
1053 17:58:03.880433 [Byte1]: 69
1054 17:58:03.884895
1055 17:58:03.885003 Set Vref, RX VrefLevel [Byte0]: 70
1056 17:58:03.888174 [Byte1]: 70
1057 17:58:03.892659
1058 17:58:03.892765 Set Vref, RX VrefLevel [Byte0]: 71
1059 17:58:03.895842 [Byte1]: 71
1060 17:58:03.899794
1061 17:58:03.899893 Set Vref, RX VrefLevel [Byte0]: 72
1062 17:58:03.903406 [Byte1]: 72
1063 17:58:03.908021
1064 17:58:03.908121 Set Vref, RX VrefLevel [Byte0]: 73
1065 17:58:03.911101 [Byte1]: 73
1066 17:58:03.915086
1067 17:58:03.915193 Final RX Vref Byte 0 = 55 to rank0
1068 17:58:03.918759 Final RX Vref Byte 1 = 56 to rank0
1069 17:58:03.921840 Final RX Vref Byte 0 = 55 to rank1
1070 17:58:03.924969 Final RX Vref Byte 1 = 56 to rank1==
1071 17:58:03.928775 Dram Type= 6, Freq= 0, CH_0, rank 0
1072 17:58:03.935062 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1073 17:58:03.935142 ==
1074 17:58:03.935207 DQS Delay:
1075 17:58:03.935267 DQS0 = 0, DQS1 = 0
1076 17:58:03.938916 DQM Delay:
1077 17:58:03.939015 DQM0 = 83, DQM1 = 74
1078 17:58:03.942113 DQ Delay:
1079 17:58:03.945288 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1080 17:58:03.945372 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1081 17:58:03.949027 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1082 17:58:03.952109 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1083 17:58:03.955376
1084 17:58:03.955455
1085 17:58:03.961536 [DQSOSCAuto] RK0, (LSB)MR18= 0x3838, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1086 17:58:03.965422 CH0 RK0: MR19=606, MR18=3838
1087 17:58:03.971867 CH0_RK0: MR19=0x606, MR18=0x3838, DQSOSC=395, MR23=63, INC=94, DEC=63
1088 17:58:03.971985
1089 17:58:03.974970 ----->DramcWriteLeveling(PI) begin...
1090 17:58:03.975071 ==
1091 17:58:03.978778 Dram Type= 6, Freq= 0, CH_0, rank 1
1092 17:58:03.982094 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1093 17:58:03.982169 ==
1094 17:58:03.985278 Write leveling (Byte 0): 31 => 31
1095 17:58:03.988530 Write leveling (Byte 1): 28 => 28
1096 17:58:03.991632 DramcWriteLeveling(PI) end<-----
1097 17:58:03.991703
1098 17:58:03.991764 ==
1099 17:58:03.994880 Dram Type= 6, Freq= 0, CH_0, rank 1
1100 17:58:03.998219 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1101 17:58:03.998293 ==
1102 17:58:04.002077 [Gating] SW mode calibration
1103 17:58:04.008320 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1104 17:58:04.014946 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1105 17:58:04.018768 0 6 0 | B1->B0 | 3434 3333 | 0 0 | (0 1) (0 1)
1106 17:58:04.021974 0 6 4 | B1->B0 | 2525 2424 | 0 0 | (1 0) (1 0)
1107 17:58:04.028197 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1108 17:58:04.032049 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1109 17:58:04.035198 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1110 17:58:04.041516 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1111 17:58:04.045367 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1112 17:58:04.048667 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1113 17:58:04.055060 0 7 0 | B1->B0 | 2525 2b2a | 0 1 | (0 0) (0 0)
1114 17:58:04.058168 0 7 4 | B1->B0 | 4343 4545 | 0 0 | (0 0) (0 0)
1115 17:58:04.061870 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1116 17:58:04.068145 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1117 17:58:04.071787 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1118 17:58:04.074779 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1119 17:58:04.081730 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1120 17:58:04.084761 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1121 17:58:04.088710 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1122 17:58:04.092038 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1123 17:58:04.098382 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1124 17:58:04.101710 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1125 17:58:04.104934 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1126 17:58:04.111787 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 17:58:04.114966 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 17:58:04.118090 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 17:58:04.125158 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 17:58:04.128364 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 17:58:04.131504 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 17:58:04.138255 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 17:58:04.141381 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 17:58:04.144918 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 17:58:04.151982 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 17:58:04.155102 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 17:58:04.158432 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1138 17:58:04.165015 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1139 17:58:04.165119 Total UI for P1: 0, mck2ui 16
1140 17:58:04.171925 best dqsien dly found for B0: ( 0, 10, 2)
1141 17:58:04.172030 Total UI for P1: 0, mck2ui 16
1142 17:58:04.175005 best dqsien dly found for B1: ( 0, 10, 0)
1143 17:58:04.181578 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1144 17:58:04.185102 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1145 17:58:04.185201
1146 17:58:04.188025 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1147 17:58:04.191569 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1148 17:58:04.235871 [Gating] SW calibration Done
1149 17:58:04.235967 ==
1150 17:58:04.236057 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 17:58:04.236325 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1152 17:58:04.236421 ==
1153 17:58:04.236517 RX Vref Scan: 0
1154 17:58:04.236611
1155 17:58:04.236705 RX Vref 0 -> 0, step: 1
1156 17:58:04.236799
1157 17:58:04.236896 RX Delay -130 -> 252, step: 16
1158 17:58:04.236989 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1159 17:58:04.237081 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1160 17:58:04.237173 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1161 17:58:04.237283 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1162 17:58:04.237373 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1163 17:58:04.237465 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1164 17:58:04.237556 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1165 17:58:04.241532 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1166 17:58:04.244503 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1167 17:58:04.248100 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1168 17:58:04.251037 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1169 17:58:04.258040 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1170 17:58:04.261261 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1171 17:58:04.264550 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1172 17:58:04.267821 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1173 17:58:04.271114 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1174 17:58:04.274883 ==
1175 17:58:04.278124 Dram Type= 6, Freq= 0, CH_0, rank 1
1176 17:58:04.281314 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1177 17:58:04.281387 ==
1178 17:58:04.281449 DQS Delay:
1179 17:58:04.284602 DQS0 = 0, DQS1 = 0
1180 17:58:04.284686 DQM Delay:
1181 17:58:04.287796 DQM0 = 82, DQM1 = 73
1182 17:58:04.287874 DQ Delay:
1183 17:58:04.291544 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =69
1184 17:58:04.294642 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1185 17:58:04.298144 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1186 17:58:04.301214 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1187 17:58:04.301291
1188 17:58:04.301354
1189 17:58:04.301413 ==
1190 17:58:04.304381 Dram Type= 6, Freq= 0, CH_0, rank 1
1191 17:58:04.307740 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1192 17:58:04.307821 ==
1193 17:58:04.307885
1194 17:58:04.307945
1195 17:58:04.311232 TX Vref Scan disable
1196 17:58:04.314256 == TX Byte 0 ==
1197 17:58:04.317923 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1198 17:58:04.321118 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1199 17:58:04.324448 == TX Byte 1 ==
1200 17:58:04.327669 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1201 17:58:04.330863 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1202 17:58:04.330947 ==
1203 17:58:04.334117 Dram Type= 6, Freq= 0, CH_0, rank 1
1204 17:58:04.338017 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1205 17:58:04.341272 ==
1206 17:58:04.352457 TX Vref=22, minBit 8, minWin=27, winSum=444
1207 17:58:04.356052 TX Vref=24, minBit 0, minWin=28, winSum=452
1208 17:58:04.359166 TX Vref=26, minBit 0, minWin=28, winSum=449
1209 17:58:04.362771 TX Vref=28, minBit 3, minWin=28, winSum=459
1210 17:58:04.366805 TX Vref=30, minBit 0, minWin=28, winSum=452
1211 17:58:04.370091 TX Vref=32, minBit 0, minWin=28, winSum=455
1212 17:58:04.377937 [TxChooseVref] Worse bit 3, Min win 28, Win sum 459, Final Vref 28
1213 17:58:04.378036
1214 17:58:04.378111 Final TX Range 1 Vref 28
1215 17:58:04.378174
1216 17:58:04.381142 ==
1217 17:58:04.381211 Dram Type= 6, Freq= 0, CH_0, rank 1
1218 17:58:04.388081 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1219 17:58:04.388165 ==
1220 17:58:04.388231
1221 17:58:04.388291
1222 17:58:04.391392 TX Vref Scan disable
1223 17:58:04.391467 == TX Byte 0 ==
1224 17:58:04.395327 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1225 17:58:04.401748 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1226 17:58:04.401830 == TX Byte 1 ==
1227 17:58:04.405037 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1228 17:58:04.411932 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1229 17:58:04.412008
1230 17:58:04.412088 [DATLAT]
1231 17:58:04.414904 Freq=800, CH0 RK1
1232 17:58:04.414979
1233 17:58:04.415049 DATLAT Default: 0x9
1234 17:58:04.418388 0, 0xFFFF, sum = 0
1235 17:58:04.418462 1, 0xFFFF, sum = 0
1236 17:58:04.421652 2, 0xFFFF, sum = 0
1237 17:58:04.421727 3, 0xFFFF, sum = 0
1238 17:58:04.425311 4, 0xFFFF, sum = 0
1239 17:58:04.425388 5, 0xFFFF, sum = 0
1240 17:58:04.428069 6, 0xFFFF, sum = 0
1241 17:58:04.428145 7, 0xFFFF, sum = 0
1242 17:58:04.431604 8, 0x0, sum = 1
1243 17:58:04.431686 9, 0x0, sum = 2
1244 17:58:04.435189 10, 0x0, sum = 3
1245 17:58:04.435278 11, 0x0, sum = 4
1246 17:58:04.435346 best_step = 9
1247 17:58:04.438442
1248 17:58:04.438521 ==
1249 17:58:04.441643 Dram Type= 6, Freq= 0, CH_0, rank 1
1250 17:58:04.444739 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1251 17:58:04.444825 ==
1252 17:58:04.444918 RX Vref Scan: 0
1253 17:58:04.445009
1254 17:58:04.448547 RX Vref 0 -> 0, step: 1
1255 17:58:04.448627
1256 17:58:04.451809 RX Delay -111 -> 252, step: 8
1257 17:58:04.455112 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1258 17:58:04.461930 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1259 17:58:04.465050 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1260 17:58:04.468099 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1261 17:58:04.471883 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1262 17:58:04.475150 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1263 17:58:04.478406 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1264 17:58:04.484928 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1265 17:58:04.488752 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1266 17:58:04.491940 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1267 17:58:04.495130 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1268 17:58:04.498281 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1269 17:58:04.505236 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1270 17:58:04.508468 iDelay=217, Bit 13, Center 76 (-39 ~ 192) 232
1271 17:58:04.511696 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1272 17:58:04.514991 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1273 17:58:04.515065 ==
1274 17:58:04.518234 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 17:58:04.525131 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1276 17:58:04.525211 ==
1277 17:58:04.525274 DQS Delay:
1278 17:58:04.528193 DQS0 = 0, DQS1 = 0
1279 17:58:04.528262 DQM Delay:
1280 17:58:04.528321 DQM0 = 85, DQM1 = 73
1281 17:58:04.531976 DQ Delay:
1282 17:58:04.535263 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =80
1283 17:58:04.538209 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1284 17:58:04.541892 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1285 17:58:04.545213 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1286 17:58:04.545314
1287 17:58:04.545376
1288 17:58:04.551527 [DQSOSCAuto] RK1, (LSB)MR18= 0x4444, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1289 17:58:04.554826 CH0 RK1: MR19=606, MR18=4444
1290 17:58:04.561913 CH0_RK1: MR19=0x606, MR18=0x4444, DQSOSC=392, MR23=63, INC=96, DEC=64
1291 17:58:04.565077 [RxdqsGatingPostProcess] freq 800
1292 17:58:04.568250 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1293 17:58:04.571531 Pre-setting of DQS Precalculation
1294 17:58:04.578191 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1295 17:58:04.578268 ==
1296 17:58:04.581967 Dram Type= 6, Freq= 0, CH_1, rank 0
1297 17:58:04.585293 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1298 17:58:04.585367 ==
1299 17:58:04.591782 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1300 17:58:04.595047 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1301 17:58:04.605374 [CA 0] Center 37 (6~68) winsize 63
1302 17:58:04.608437 [CA 1] Center 37 (6~68) winsize 63
1303 17:58:04.612166 [CA 2] Center 34 (4~65) winsize 62
1304 17:58:04.615375 [CA 3] Center 34 (4~65) winsize 62
1305 17:58:04.618641 [CA 4] Center 33 (3~64) winsize 62
1306 17:58:04.621797 [CA 5] Center 33 (3~64) winsize 62
1307 17:58:04.621882
1308 17:58:04.625168 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1309 17:58:04.625246
1310 17:58:04.628405 [CATrainingPosCal] consider 1 rank data
1311 17:58:04.631610 u2DelayCellTimex100 = 270/100 ps
1312 17:58:04.635432 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1313 17:58:04.641489 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1314 17:58:04.644698 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1315 17:58:04.648562 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1316 17:58:04.651747 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1317 17:58:04.655184 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1318 17:58:04.655258
1319 17:58:04.658057 CA PerBit enable=1, Macro0, CA PI delay=33
1320 17:58:04.658147
1321 17:58:04.661446 [CBTSetCACLKResult] CA Dly = 33
1322 17:58:04.661533 CS Dly: 4 (0~35)
1323 17:58:04.664780 ==
1324 17:58:04.668238 Dram Type= 6, Freq= 0, CH_1, rank 1
1325 17:58:04.671547 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1326 17:58:04.671627 ==
1327 17:58:04.674637 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1328 17:58:04.681645 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1329 17:58:04.690946 [CA 0] Center 37 (6~68) winsize 63
1330 17:58:04.694107 [CA 1] Center 37 (6~68) winsize 63
1331 17:58:04.698019 [CA 2] Center 34 (4~65) winsize 62
1332 17:58:04.701233 [CA 3] Center 34 (4~65) winsize 62
1333 17:58:04.704457 [CA 4] Center 33 (3~64) winsize 62
1334 17:58:04.707834 [CA 5] Center 33 (3~64) winsize 62
1335 17:58:04.707912
1336 17:58:04.711061 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1337 17:58:04.711149
1338 17:58:04.714283 [CATrainingPosCal] consider 2 rank data
1339 17:58:04.717427 u2DelayCellTimex100 = 270/100 ps
1340 17:58:04.720824 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1341 17:58:04.724632 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1342 17:58:04.731081 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1343 17:58:04.734314 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1344 17:58:04.737544 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1345 17:58:04.740767 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1346 17:58:04.740857
1347 17:58:04.744108 CA PerBit enable=1, Macro0, CA PI delay=33
1348 17:58:04.744195
1349 17:58:04.747875 [CBTSetCACLKResult] CA Dly = 33
1350 17:58:04.747971 CS Dly: 4 (0~36)
1351 17:58:04.748034
1352 17:58:04.751003 ----->DramcWriteLeveling(PI) begin...
1353 17:58:04.754289 ==
1354 17:58:04.757600 Dram Type= 6, Freq= 0, CH_1, rank 0
1355 17:58:04.760799 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1356 17:58:04.760881 ==
1357 17:58:04.763964 Write leveling (Byte 0): 26 => 26
1358 17:58:04.767581 Write leveling (Byte 1): 25 => 25
1359 17:58:04.770716 DramcWriteLeveling(PI) end<-----
1360 17:58:04.770798
1361 17:58:04.770862 ==
1362 17:58:04.774139 Dram Type= 6, Freq= 0, CH_1, rank 0
1363 17:58:04.777511 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1364 17:58:04.777592 ==
1365 17:58:04.780830 [Gating] SW mode calibration
1366 17:58:04.787274 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1367 17:58:04.790587 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1368 17:58:04.797180 0 6 0 | B1->B0 | 3333 2626 | 0 0 | (0 1) (0 0)
1369 17:58:04.800955 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1370 17:58:04.804230 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1371 17:58:04.810711 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1372 17:58:04.813950 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1373 17:58:04.817150 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1374 17:58:04.824151 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1375 17:58:04.827425 0 6 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1376 17:58:04.830730 0 7 0 | B1->B0 | 2b2b 3b3b | 0 0 | (1 1) (0 0)
1377 17:58:04.837221 0 7 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1378 17:58:04.840529 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1379 17:58:04.843817 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1380 17:58:04.850350 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1381 17:58:04.854104 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1382 17:58:04.857159 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1383 17:58:04.863709 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1384 17:58:04.866932 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1385 17:58:04.870821 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1386 17:58:04.877138 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1387 17:58:04.880308 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1388 17:58:04.884182 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1389 17:58:04.890904 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 17:58:04.893801 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 17:58:04.897112 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 17:58:04.903570 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 17:58:04.907173 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 17:58:04.910430 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 17:58:04.917262 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 17:58:04.920549 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 17:58:04.923815 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 17:58:04.927014 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 17:58:04.934126 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1400 17:58:04.937287 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1401 17:58:04.940530 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1402 17:58:04.943895 Total UI for P1: 0, mck2ui 16
1403 17:58:04.947125 best dqsien dly found for B0: ( 0, 9, 30)
1404 17:58:04.950404 Total UI for P1: 0, mck2ui 16
1405 17:58:04.953551 best dqsien dly found for B1: ( 0, 9, 30)
1406 17:58:04.957419 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1407 17:58:04.960663 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1408 17:58:04.960773
1409 17:58:04.967423 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1410 17:58:04.970691 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1411 17:58:04.973889 [Gating] SW calibration Done
1412 17:58:04.973996 ==
1413 17:58:04.977044 Dram Type= 6, Freq= 0, CH_1, rank 0
1414 17:58:04.980211 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1415 17:58:04.980294 ==
1416 17:58:04.980391 RX Vref Scan: 0
1417 17:58:04.980480
1418 17:58:04.983993 RX Vref 0 -> 0, step: 1
1419 17:58:04.984074
1420 17:58:04.987285 RX Delay -130 -> 252, step: 16
1421 17:58:04.990533 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1422 17:58:04.993855 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1423 17:58:05.000703 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1424 17:58:05.003750 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1425 17:58:05.006945 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1426 17:58:05.010248 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1427 17:58:05.013408 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1428 17:58:05.020230 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1429 17:58:05.023755 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1430 17:58:05.027162 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1431 17:58:05.031161 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1432 17:58:05.034634 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1433 17:58:05.038783 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1434 17:58:05.042253 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1435 17:58:05.045446 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1436 17:58:05.052723 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1437 17:58:05.052807 ==
1438 17:58:05.056059 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 17:58:05.060085 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1440 17:58:05.060167 ==
1441 17:58:05.060231 DQS Delay:
1442 17:58:05.060290 DQS0 = 0, DQS1 = 0
1443 17:58:05.064016 DQM Delay:
1444 17:58:05.064097 DQM0 = 81, DQM1 = 73
1445 17:58:05.067285 DQ Delay:
1446 17:58:05.067367 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1447 17:58:05.070386 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1448 17:58:05.074125 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1449 17:58:05.077105 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =85
1450 17:58:05.077186
1451 17:58:05.080817
1452 17:58:05.080898 ==
1453 17:58:05.084148 Dram Type= 6, Freq= 0, CH_1, rank 0
1454 17:58:05.087443 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1455 17:58:05.087525 ==
1456 17:58:05.087589
1457 17:58:05.087649
1458 17:58:05.090629 TX Vref Scan disable
1459 17:58:05.090711 == TX Byte 0 ==
1460 17:58:05.097148 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1461 17:58:05.100362 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1462 17:58:05.100444 == TX Byte 1 ==
1463 17:58:05.106624 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1464 17:58:05.110345 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1465 17:58:05.110427 ==
1466 17:58:05.113644 Dram Type= 6, Freq= 0, CH_1, rank 0
1467 17:58:05.116845 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1468 17:58:05.116927 ==
1469 17:58:05.130579 TX Vref=22, minBit 0, minWin=27, winSum=445
1470 17:58:05.133632 TX Vref=24, minBit 9, minWin=27, winSum=449
1471 17:58:05.136810 TX Vref=26, minBit 3, minWin=27, winSum=453
1472 17:58:05.140637 TX Vref=28, minBit 0, minWin=28, winSum=458
1473 17:58:05.143772 TX Vref=30, minBit 0, minWin=28, winSum=458
1474 17:58:05.147377 TX Vref=32, minBit 9, minWin=27, winSum=456
1475 17:58:05.154014 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1476 17:58:05.154104
1477 17:58:05.157240 Final TX Range 1 Vref 28
1478 17:58:05.157322
1479 17:58:05.157385 ==
1480 17:58:05.160372 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 17:58:05.163627 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1482 17:58:05.163713 ==
1483 17:58:05.163777
1484 17:58:05.166920
1485 17:58:05.167001 TX Vref Scan disable
1486 17:58:05.170611 == TX Byte 0 ==
1487 17:58:05.173897 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1488 17:58:05.180193 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1489 17:58:05.180275 == TX Byte 1 ==
1490 17:58:05.183877 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1491 17:58:05.190604 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1492 17:58:05.190686
1493 17:58:05.190750 [DATLAT]
1494 17:58:05.190809 Freq=800, CH1 RK0
1495 17:58:05.190866
1496 17:58:05.193908 DATLAT Default: 0xa
1497 17:58:05.193989 0, 0xFFFF, sum = 0
1498 17:58:05.197138 1, 0xFFFF, sum = 0
1499 17:58:05.197220 2, 0xFFFF, sum = 0
1500 17:58:05.200423 3, 0xFFFF, sum = 0
1501 17:58:05.203659 4, 0xFFFF, sum = 0
1502 17:58:05.203741 5, 0xFFFF, sum = 0
1503 17:58:05.206866 6, 0xFFFF, sum = 0
1504 17:58:05.206948 7, 0xFFFF, sum = 0
1505 17:58:05.210124 8, 0x0, sum = 1
1506 17:58:05.210209 9, 0x0, sum = 2
1507 17:58:05.210275 10, 0x0, sum = 3
1508 17:58:05.213861 11, 0x0, sum = 4
1509 17:58:05.213970 best_step = 9
1510 17:58:05.214063
1511 17:58:05.214124 ==
1512 17:58:05.216821 Dram Type= 6, Freq= 0, CH_1, rank 0
1513 17:58:05.223903 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1514 17:58:05.223985 ==
1515 17:58:05.224050 RX Vref Scan: 1
1516 17:58:05.224110
1517 17:58:05.227107 Set Vref Range= 32 -> 127
1518 17:58:05.227188
1519 17:58:05.230402 RX Vref 32 -> 127, step: 1
1520 17:58:05.230482
1521 17:58:05.233537 RX Delay -111 -> 252, step: 8
1522 17:58:05.233618
1523 17:58:05.236732 Set Vref, RX VrefLevel [Byte0]: 32
1524 17:58:05.239952 [Byte1]: 32
1525 17:58:05.240033
1526 17:58:05.243253 Set Vref, RX VrefLevel [Byte0]: 33
1527 17:58:05.246606 [Byte1]: 33
1528 17:58:05.246687
1529 17:58:05.250399 Set Vref, RX VrefLevel [Byte0]: 34
1530 17:58:05.253512 [Byte1]: 34
1531 17:58:05.253594
1532 17:58:05.256619 Set Vref, RX VrefLevel [Byte0]: 35
1533 17:58:05.260210 [Byte1]: 35
1534 17:58:05.264572
1535 17:58:05.264654 Set Vref, RX VrefLevel [Byte0]: 36
1536 17:58:05.267779 [Byte1]: 36
1537 17:58:05.272219
1538 17:58:05.272299 Set Vref, RX VrefLevel [Byte0]: 37
1539 17:58:05.275406 [Byte1]: 37
1540 17:58:05.279447
1541 17:58:05.279528 Set Vref, RX VrefLevel [Byte0]: 38
1542 17:58:05.283237 [Byte1]: 38
1543 17:58:05.287117
1544 17:58:05.287197 Set Vref, RX VrefLevel [Byte0]: 39
1545 17:58:05.290882 [Byte1]: 39
1546 17:58:05.295072
1547 17:58:05.295152 Set Vref, RX VrefLevel [Byte0]: 40
1548 17:58:05.301167 [Byte1]: 40
1549 17:58:05.301248
1550 17:58:05.304366 Set Vref, RX VrefLevel [Byte0]: 41
1551 17:58:05.308280 [Byte1]: 41
1552 17:58:05.308360
1553 17:58:05.311440 Set Vref, RX VrefLevel [Byte0]: 42
1554 17:58:05.314734 [Byte1]: 42
1555 17:58:05.314815
1556 17:58:05.317877 Set Vref, RX VrefLevel [Byte0]: 43
1557 17:58:05.321377 [Byte1]: 43
1558 17:58:05.325635
1559 17:58:05.325715 Set Vref, RX VrefLevel [Byte0]: 44
1560 17:58:05.328929 [Byte1]: 44
1561 17:58:05.332914
1562 17:58:05.332995 Set Vref, RX VrefLevel [Byte0]: 45
1563 17:58:05.336733 [Byte1]: 45
1564 17:58:05.340541
1565 17:58:05.340621 Set Vref, RX VrefLevel [Byte0]: 46
1566 17:58:05.344264 [Byte1]: 46
1567 17:58:05.348134
1568 17:58:05.348214 Set Vref, RX VrefLevel [Byte0]: 47
1569 17:58:05.351391 [Byte1]: 47
1570 17:58:05.355889
1571 17:58:05.355970 Set Vref, RX VrefLevel [Byte0]: 48
1572 17:58:05.359188 [Byte1]: 48
1573 17:58:05.363993
1574 17:58:05.364069 Set Vref, RX VrefLevel [Byte0]: 49
1575 17:58:05.366909 [Byte1]: 49
1576 17:58:05.371236
1577 17:58:05.371314 Set Vref, RX VrefLevel [Byte0]: 50
1578 17:58:05.374418 [Byte1]: 50
1579 17:58:05.378893
1580 17:58:05.378965 Set Vref, RX VrefLevel [Byte0]: 51
1581 17:58:05.382117 [Byte1]: 51
1582 17:58:05.386458
1583 17:58:05.386530 Set Vref, RX VrefLevel [Byte0]: 52
1584 17:58:05.389761 [Byte1]: 52
1585 17:58:05.394231
1586 17:58:05.394316 Set Vref, RX VrefLevel [Byte0]: 53
1587 17:58:05.397391 [Byte1]: 53
1588 17:58:05.401819
1589 17:58:05.401892 Set Vref, RX VrefLevel [Byte0]: 54
1590 17:58:05.405316 [Byte1]: 54
1591 17:58:05.409450
1592 17:58:05.409526 Set Vref, RX VrefLevel [Byte0]: 55
1593 17:58:05.412639 [Byte1]: 55
1594 17:58:05.417092
1595 17:58:05.417166 Set Vref, RX VrefLevel [Byte0]: 56
1596 17:58:05.420312 [Byte1]: 56
1597 17:58:05.425000
1598 17:58:05.425072 Set Vref, RX VrefLevel [Byte0]: 57
1599 17:58:05.428215 [Byte1]: 57
1600 17:58:05.432490
1601 17:58:05.432561 Set Vref, RX VrefLevel [Byte0]: 58
1602 17:58:05.435595 [Byte1]: 58
1603 17:58:05.440149
1604 17:58:05.440244 Set Vref, RX VrefLevel [Byte0]: 59
1605 17:58:05.443419 [Byte1]: 59
1606 17:58:05.447975
1607 17:58:05.448078 Set Vref, RX VrefLevel [Byte0]: 60
1608 17:58:05.451139 [Byte1]: 60
1609 17:58:05.455707
1610 17:58:05.455786 Set Vref, RX VrefLevel [Byte0]: 61
1611 17:58:05.458864 [Byte1]: 61
1612 17:58:05.462757
1613 17:58:05.466506 Set Vref, RX VrefLevel [Byte0]: 62
1614 17:58:05.469600 [Byte1]: 62
1615 17:58:05.469701
1616 17:58:05.472783 Set Vref, RX VrefLevel [Byte0]: 63
1617 17:58:05.476362 [Byte1]: 63
1618 17:58:05.476482
1619 17:58:05.479701 Set Vref, RX VrefLevel [Byte0]: 64
1620 17:58:05.483004 [Byte1]: 64
1621 17:58:05.486190
1622 17:58:05.486259 Set Vref, RX VrefLevel [Byte0]: 65
1623 17:58:05.489362 [Byte1]: 65
1624 17:58:05.493887
1625 17:58:05.493990 Set Vref, RX VrefLevel [Byte0]: 66
1626 17:58:05.496998 [Byte1]: 66
1627 17:58:05.501753
1628 17:58:05.501848 Set Vref, RX VrefLevel [Byte0]: 67
1629 17:58:05.504889 [Byte1]: 67
1630 17:58:05.509339
1631 17:58:05.509437 Set Vref, RX VrefLevel [Byte0]: 68
1632 17:58:05.512502 [Byte1]: 68
1633 17:58:05.516772
1634 17:58:05.516858 Set Vref, RX VrefLevel [Byte0]: 69
1635 17:58:05.519734 [Byte1]: 69
1636 17:58:05.524177
1637 17:58:05.524254 Set Vref, RX VrefLevel [Byte0]: 70
1638 17:58:05.527774 [Byte1]: 70
1639 17:58:05.532293
1640 17:58:05.532371 Set Vref, RX VrefLevel [Byte0]: 71
1641 17:58:05.535463 [Byte1]: 71
1642 17:58:05.539741
1643 17:58:05.539829 Set Vref, RX VrefLevel [Byte0]: 72
1644 17:58:05.542840 [Byte1]: 72
1645 17:58:05.547401
1646 17:58:05.547478 Set Vref, RX VrefLevel [Byte0]: 73
1647 17:58:05.550723 [Byte1]: 73
1648 17:58:05.555025
1649 17:58:05.555097 Set Vref, RX VrefLevel [Byte0]: 74
1650 17:58:05.558234 [Byte1]: 74
1651 17:58:05.562807
1652 17:58:05.562888 Set Vref, RX VrefLevel [Byte0]: 75
1653 17:58:05.565810 [Byte1]: 75
1654 17:58:05.570358
1655 17:58:05.570443 Set Vref, RX VrefLevel [Byte0]: 76
1656 17:58:05.573483 [Byte1]: 76
1657 17:58:05.578070
1658 17:58:05.578155 Set Vref, RX VrefLevel [Byte0]: 77
1659 17:58:05.581178 [Byte1]: 77
1660 17:58:05.585640
1661 17:58:05.585739 Set Vref, RX VrefLevel [Byte0]: 78
1662 17:58:05.588784 [Byte1]: 78
1663 17:58:05.593274
1664 17:58:05.593374 Set Vref, RX VrefLevel [Byte0]: 79
1665 17:58:05.596427 [Byte1]: 79
1666 17:58:05.600958
1667 17:58:05.601041 Final RX Vref Byte 0 = 55 to rank0
1668 17:58:05.604291 Final RX Vref Byte 1 = 53 to rank0
1669 17:58:05.607462 Final RX Vref Byte 0 = 55 to rank1
1670 17:58:05.611234 Final RX Vref Byte 1 = 53 to rank1==
1671 17:58:05.614538 Dram Type= 6, Freq= 0, CH_1, rank 0
1672 17:58:05.617820 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1673 17:58:05.617900 ==
1674 17:58:05.621077 DQS Delay:
1675 17:58:05.621185 DQS0 = 0, DQS1 = 0
1676 17:58:05.624390 DQM Delay:
1677 17:58:05.624471 DQM0 = 81, DQM1 = 75
1678 17:58:05.624534 DQ Delay:
1679 17:58:05.628089 DQ0 =88, DQ1 =72, DQ2 =72, DQ3 =80
1680 17:58:05.631231 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =80
1681 17:58:05.634575 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1682 17:58:05.637705 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1683 17:58:05.637785
1684 17:58:05.637849
1685 17:58:05.647616 [DQSOSCAuto] RK0, (LSB)MR18= 0x4949, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1686 17:58:05.651120 CH1 RK0: MR19=606, MR18=4949
1687 17:58:05.657827 CH1_RK0: MR19=0x606, MR18=0x4949, DQSOSC=391, MR23=63, INC=96, DEC=64
1688 17:58:05.657909
1689 17:58:05.660850 ----->DramcWriteLeveling(PI) begin...
1690 17:58:05.660960 ==
1691 17:58:05.664546 Dram Type= 6, Freq= 0, CH_1, rank 1
1692 17:58:05.667656 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1693 17:58:05.667739 ==
1694 17:58:05.670791 Write leveling (Byte 0): 26 => 26
1695 17:58:05.673935 Write leveling (Byte 1): 24 => 24
1696 17:58:05.677654 DramcWriteLeveling(PI) end<-----
1697 17:58:05.677736
1698 17:58:05.677802 ==
1699 17:58:05.680923 Dram Type= 6, Freq= 0, CH_1, rank 1
1700 17:58:05.684099 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1701 17:58:05.684182 ==
1702 17:58:05.687884 [Gating] SW mode calibration
1703 17:58:05.694393 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1704 17:58:05.700818 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1705 17:58:05.704018 0 6 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
1706 17:58:05.707254 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1707 17:58:05.714382 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1708 17:58:05.717540 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1709 17:58:05.720843 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1710 17:58:05.727183 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1711 17:58:05.731004 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1712 17:58:05.734295 0 6 28 | B1->B0 | 2626 2f2f | 0 1 | (0 0) (0 0)
1713 17:58:05.740463 0 7 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
1714 17:58:05.744206 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1715 17:58:05.747414 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1716 17:58:05.753948 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1717 17:58:05.757564 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1718 17:58:05.760652 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1719 17:58:05.764128 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1720 17:58:05.770808 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1721 17:58:05.774131 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1722 17:58:05.777182 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 17:58:05.784329 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 17:58:05.787557 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1725 17:58:05.790651 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 17:58:05.797415 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 17:58:05.800729 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 17:58:05.803851 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1729 17:58:05.810327 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1730 17:58:05.814188 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1731 17:58:05.817399 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1732 17:58:05.823712 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1733 17:58:05.826948 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1734 17:58:05.830805 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1735 17:58:05.837252 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1736 17:58:05.840437 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1737 17:58:05.843542 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1738 17:58:05.847468 Total UI for P1: 0, mck2ui 16
1739 17:58:05.850666 best dqsien dly found for B0: ( 0, 9, 28)
1740 17:58:05.853944 Total UI for P1: 0, mck2ui 16
1741 17:58:05.857118 best dqsien dly found for B1: ( 0, 9, 28)
1742 17:58:05.860252 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1743 17:58:05.863878 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1744 17:58:05.863958
1745 17:58:05.867025 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1746 17:58:05.874060 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1747 17:58:05.874146 [Gating] SW calibration Done
1748 17:58:05.877298 ==
1749 17:58:05.880347 Dram Type= 6, Freq= 0, CH_1, rank 1
1750 17:58:05.883826 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1751 17:58:05.883908 ==
1752 17:58:05.883971 RX Vref Scan: 0
1753 17:58:05.884031
1754 17:58:05.887125 RX Vref 0 -> 0, step: 1
1755 17:58:05.887206
1756 17:58:05.890268 RX Delay -130 -> 252, step: 16
1757 17:58:05.893960 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1758 17:58:05.897092 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1759 17:58:05.900309 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1760 17:58:05.907294 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1761 17:58:05.910517 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1762 17:58:05.913752 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1763 17:58:05.916936 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1764 17:58:05.920195 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1765 17:58:05.927355 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1766 17:58:05.930540 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1767 17:58:05.933788 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1768 17:58:05.936931 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1769 17:58:05.940807 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1770 17:58:05.947103 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1771 17:58:05.950445 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1772 17:58:05.953582 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1773 17:58:05.953661 ==
1774 17:58:05.957298 Dram Type= 6, Freq= 0, CH_1, rank 1
1775 17:58:05.960655 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1776 17:58:05.963803 ==
1777 17:58:05.963883 DQS Delay:
1778 17:58:05.963945 DQS0 = 0, DQS1 = 0
1779 17:58:05.966928 DQM Delay:
1780 17:58:05.967014 DQM0 = 85, DQM1 = 75
1781 17:58:05.970658 DQ Delay:
1782 17:58:05.970738 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1783 17:58:05.973601 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1784 17:58:05.976800 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1785 17:58:05.980115 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1786 17:58:05.983307
1787 17:58:05.983401
1788 17:58:05.983463 ==
1789 17:58:05.987174 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 17:58:05.990441 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1791 17:58:05.990536 ==
1792 17:58:05.990599
1793 17:58:05.990657
1794 17:58:05.993567 TX Vref Scan disable
1795 17:58:05.993649 == TX Byte 0 ==
1796 17:58:06.000299 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1797 17:58:06.003648 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1798 17:58:06.003742 == TX Byte 1 ==
1799 17:58:06.009990 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1800 17:58:06.013665 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1801 17:58:06.013746 ==
1802 17:58:06.017253 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 17:58:06.020343 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1804 17:58:06.020456 ==
1805 17:58:06.033519 TX Vref=22, minBit 0, minWin=27, winSum=447
1806 17:58:06.036798 TX Vref=24, minBit 0, minWin=28, winSum=452
1807 17:58:06.040726 TX Vref=26, minBit 0, minWin=28, winSum=455
1808 17:58:06.043915 TX Vref=28, minBit 0, minWin=28, winSum=456
1809 17:58:06.047192 TX Vref=30, minBit 9, minWin=27, winSum=457
1810 17:58:06.053418 TX Vref=32, minBit 9, minWin=27, winSum=454
1811 17:58:06.057404 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 28
1812 17:58:06.057486
1813 17:58:06.060767 Final TX Range 1 Vref 28
1814 17:58:06.060847
1815 17:58:06.060910 ==
1816 17:58:06.063945 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 17:58:06.067179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1818 17:58:06.067304 ==
1819 17:58:06.067369
1820 17:58:06.070301
1821 17:58:06.070380 TX Vref Scan disable
1822 17:58:06.073503 == TX Byte 0 ==
1823 17:58:06.077268 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1824 17:58:06.080245 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1825 17:58:06.083882 == TX Byte 1 ==
1826 17:58:06.086995 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1827 17:58:06.093424 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1828 17:58:06.093504
1829 17:58:06.093566 [DATLAT]
1830 17:58:06.093625 Freq=800, CH1 RK1
1831 17:58:06.093681
1832 17:58:06.096679 DATLAT Default: 0x9
1833 17:58:06.096758 0, 0xFFFF, sum = 0
1834 17:58:06.100400 1, 0xFFFF, sum = 0
1835 17:58:06.103583 2, 0xFFFF, sum = 0
1836 17:58:06.103664 3, 0xFFFF, sum = 0
1837 17:58:06.106717 4, 0xFFFF, sum = 0
1838 17:58:06.106799 5, 0xFFFF, sum = 0
1839 17:58:06.110371 6, 0xFFFF, sum = 0
1840 17:58:06.110452 7, 0xFFFF, sum = 0
1841 17:58:06.113549 8, 0x0, sum = 1
1842 17:58:06.113629 9, 0x0, sum = 2
1843 17:58:06.113693 10, 0x0, sum = 3
1844 17:58:06.116729 11, 0x0, sum = 4
1845 17:58:06.116810 best_step = 9
1846 17:58:06.116873
1847 17:58:06.116948 ==
1848 17:58:06.119844 Dram Type= 6, Freq= 0, CH_1, rank 1
1849 17:58:06.126390 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1850 17:58:06.126471 ==
1851 17:58:06.126533 RX Vref Scan: 0
1852 17:58:06.126592
1853 17:58:06.129941 RX Vref 0 -> 0, step: 1
1854 17:58:06.130021
1855 17:58:06.133335 RX Delay -111 -> 252, step: 8
1856 17:58:06.136673 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
1857 17:58:06.139940 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
1858 17:58:06.146543 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1859 17:58:06.149781 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1860 17:58:06.152936 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1861 17:58:06.156622 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1862 17:58:06.159732 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1863 17:58:06.166162 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
1864 17:58:06.169454 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1865 17:58:06.173150 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1866 17:58:06.176427 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1867 17:58:06.182808 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1868 17:58:06.186480 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1869 17:58:06.189452 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1870 17:58:06.193200 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1871 17:58:06.196256 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1872 17:58:06.199499 ==
1873 17:58:06.199594 Dram Type= 6, Freq= 0, CH_1, rank 1
1874 17:58:06.205935 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1875 17:58:06.206062 ==
1876 17:58:06.206140 DQS Delay:
1877 17:58:06.209212 DQS0 = 0, DQS1 = 0
1878 17:58:06.209306 DQM Delay:
1879 17:58:06.212916 DQM0 = 85, DQM1 = 74
1880 17:58:06.213011 DQ Delay:
1881 17:58:06.215873 DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =84
1882 17:58:06.219514 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
1883 17:58:06.222746 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =64
1884 17:58:06.225810 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1885 17:58:06.225912
1886 17:58:06.226041
1887 17:58:06.232724 [DQSOSCAuto] RK1, (LSB)MR18= 0x3636, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1888 17:58:06.235915 CH1 RK1: MR19=606, MR18=3636
1889 17:58:06.242436 CH1_RK1: MR19=0x606, MR18=0x3636, DQSOSC=396, MR23=63, INC=94, DEC=62
1890 17:58:06.245910 [RxdqsGatingPostProcess] freq 800
1891 17:58:06.249355 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1892 17:58:06.252904 Pre-setting of DQS Precalculation
1893 17:58:06.259269 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1894 17:58:06.265877 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1895 17:58:06.272929 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1896 17:58:06.273032
1897 17:58:06.273121
1898 17:58:06.276081 [Calibration Summary] 1600 Mbps
1899 17:58:06.276184 CH 0, Rank 0
1900 17:58:06.279266 SW Impedance : PASS
1901 17:58:06.282441 DUTY Scan : NO K
1902 17:58:06.282541 ZQ Calibration : PASS
1903 17:58:06.285684 Jitter Meter : NO K
1904 17:58:06.289562 CBT Training : PASS
1905 17:58:06.289662 Write leveling : PASS
1906 17:58:06.292800 RX DQS gating : PASS
1907 17:58:06.295854 RX DQ/DQS(RDDQC) : PASS
1908 17:58:06.295967 TX DQ/DQS : PASS
1909 17:58:06.299508 RX DATLAT : PASS
1910 17:58:06.302711 RX DQ/DQS(Engine): PASS
1911 17:58:06.302811 TX OE : NO K
1912 17:58:06.302901 All Pass.
1913 17:58:06.305841
1914 17:58:06.305911 CH 0, Rank 1
1915 17:58:06.309111 SW Impedance : PASS
1916 17:58:06.309210 DUTY Scan : NO K
1917 17:58:06.312283 ZQ Calibration : PASS
1918 17:58:06.312380 Jitter Meter : NO K
1919 17:58:06.316102 CBT Training : PASS
1920 17:58:06.319220 Write leveling : PASS
1921 17:58:06.319291 RX DQS gating : PASS
1922 17:58:06.322296 RX DQ/DQS(RDDQC) : PASS
1923 17:58:06.325793 TX DQ/DQS : PASS
1924 17:58:06.325865 RX DATLAT : PASS
1925 17:58:06.329266 RX DQ/DQS(Engine): PASS
1926 17:58:06.332258 TX OE : NO K
1927 17:58:06.332359 All Pass.
1928 17:58:06.332448
1929 17:58:06.332537 CH 1, Rank 0
1930 17:58:06.336051 SW Impedance : PASS
1931 17:58:06.339308 DUTY Scan : NO K
1932 17:58:06.339380 ZQ Calibration : PASS
1933 17:58:06.342551 Jitter Meter : NO K
1934 17:58:06.345622 CBT Training : PASS
1935 17:58:06.345722 Write leveling : PASS
1936 17:58:06.349494 RX DQS gating : PASS
1937 17:58:09.001081 RX DQ/DQS(RDDQC) : PASS
1938 17:58:09.001263 TX DQ/DQS : PASS
1939 17:58:09.001374 RX DATLAT : PASS
1940 17:58:09.001479 RX DQ/DQS(Engine): PASS
1941 17:58:09.001581 TX OE : NO K
1942 17:58:09.001682 All Pass.
1943 17:58:09.001781
1944 17:58:09.001879 CH 1, Rank 1
1945 17:58:09.001979 SW Impedance : PASS
1946 17:58:09.002086 DUTY Scan : NO K
1947 17:58:09.002188 ZQ Calibration : PASS
1948 17:58:09.002287 Jitter Meter : NO K
1949 17:58:09.002385 CBT Training : PASS
1950 17:58:09.002482 Write leveling : PASS
1951 17:58:09.002579 RX DQS gating : PASS
1952 17:58:09.002677 RX DQ/DQS(RDDQC) : PASS
1953 17:58:09.002772 TX DQ/DQS : PASS
1954 17:58:09.002871 RX DATLAT : PASS
1955 17:58:09.002968 RX DQ/DQS(Engine): PASS
1956 17:58:09.003064 TX OE : NO K
1957 17:58:09.003162 All Pass.
1958 17:58:09.003258
1959 17:58:09.003357 DramC Write-DBI off
1960 17:58:09.003455 PER_BANK_REFRESH: Hybrid Mode
1961 17:58:09.003551 TX_TRACKING: ON
1962 17:58:09.003649 [GetDramInforAfterCalByMRR] Vendor 6.
1963 17:58:09.003745 [GetDramInforAfterCalByMRR] Revision 606.
1964 17:58:09.003843 [GetDramInforAfterCalByMRR] Revision 2 0.
1965 17:58:09.003940 MR0 0x3939
1966 17:58:09.004035 MR8 0x1111
1967 17:58:09.004132 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1968 17:58:09.004229
1969 17:58:09.004326 MR0 0x3939
1970 17:58:09.004421 MR8 0x1111
1971 17:58:09.004516 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1972 17:58:09.004612
1973 17:58:09.004707 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1974 17:58:09.004806 [FAST_K] Save calibration result to emmc
1975 17:58:09.004902 [FAST_K] Save calibration result to emmc
1976 17:58:09.005001 dram_init: config_dvfs: 1
1977 17:58:09.005096 dramc_set_vcore_voltage set vcore to 662500
1978 17:58:09.005194 Read voltage for 1200, 2
1979 17:58:09.005290 Vio18 = 0
1980 17:58:09.005384 Vcore = 662500
1981 17:58:09.005480 Vdram = 0
1982 17:58:09.005576 Vddq = 0
1983 17:58:09.005671 Vmddr = 0
1984 17:58:09.005766 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1985 17:58:09.005863 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1986 17:58:09.005962 MEM_TYPE=3, freq_sel=15
1987 17:58:09.006063 sv_algorithm_assistance_LP4_1600
1988 17:58:09.006161 ============ PULL DRAM RESETB DOWN ============
1989 17:58:09.006259 ========== PULL DRAM RESETB DOWN end =========
1990 17:58:09.006356 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1991 17:58:09.006453 ===================================
1992 17:58:09.006549 LPDDR4 DRAM CONFIGURATION
1993 17:58:09.006645 ===================================
1994 17:58:09.006743 EX_ROW_EN[0] = 0x0
1995 17:58:09.006838 EX_ROW_EN[1] = 0x0
1996 17:58:09.006933 LP4Y_EN = 0x0
1997 17:58:09.007029 WORK_FSP = 0x0
1998 17:58:09.007126 WL = 0x4
1999 17:58:09.007222 RL = 0x4
2000 17:58:09.007317 BL = 0x2
2001 17:58:09.007413 RPST = 0x0
2002 17:58:09.007509 RD_PRE = 0x0
2003 17:58:09.007606 WR_PRE = 0x1
2004 17:58:09.007701 WR_PST = 0x0
2005 17:58:09.007795 DBI_WR = 0x0
2006 17:58:09.007891 DBI_RD = 0x0
2007 17:58:09.007986 OTF = 0x1
2008 17:58:09.008084 ===================================
2009 17:58:09.008181 ===================================
2010 17:58:09.008276 ANA top config
2011 17:58:09.008372 ===================================
2012 17:58:09.008467 DLL_ASYNC_EN = 0
2013 17:58:09.008563 ALL_SLAVE_EN = 0
2014 17:58:09.008659 NEW_RANK_MODE = 1
2015 17:58:09.008755 DLL_IDLE_MODE = 1
2016 17:58:09.008858 LP45_APHY_COMB_EN = 1
2017 17:58:09.008965 TX_ODT_DIS = 1
2018 17:58:09.009074 NEW_8X_MODE = 1
2019 17:58:09.009181 ===================================
2020 17:58:09.009288 ===================================
2021 17:58:09.009394 data_rate = 2400
2022 17:58:09.009500 CKR = 1
2023 17:58:09.009607 DQ_P2S_RATIO = 8
2024 17:58:09.009714 ===================================
2025 17:58:09.009817 CA_P2S_RATIO = 8
2026 17:58:09.009917 DQ_CA_OPEN = 0
2027 17:58:09.010017 DQ_SEMI_OPEN = 0
2028 17:58:09.010122 CA_SEMI_OPEN = 0
2029 17:58:09.010221 CA_FULL_RATE = 0
2030 17:58:09.010319 DQ_CKDIV4_EN = 0
2031 17:58:09.010416 CA_CKDIV4_EN = 0
2032 17:58:09.010512 CA_PREDIV_EN = 0
2033 17:58:09.010608 PH8_DLY = 17
2034 17:58:09.010705 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2035 17:58:09.010802 DQ_AAMCK_DIV = 4
2036 17:58:09.010898 CA_AAMCK_DIV = 4
2037 17:58:09.010995 CA_ADMCK_DIV = 4
2038 17:58:09.011092 DQ_TRACK_CA_EN = 0
2039 17:58:09.011188 CA_PICK = 1200
2040 17:58:09.011284 CA_MCKIO = 1200
2041 17:58:09.011379 MCKIO_SEMI = 0
2042 17:58:09.011475 PLL_FREQ = 2366
2043 17:58:09.011570 DQ_UI_PI_RATIO = 32
2044 17:58:09.011666 CA_UI_PI_RATIO = 0
2045 17:58:09.011762 ===================================
2046 17:58:09.011858 ===================================
2047 17:58:09.011956 memory_type:LPDDR4
2048 17:58:09.012051 GP_NUM : 10
2049 17:58:09.012148 SRAM_EN : 1
2050 17:58:09.012245 MD32_EN : 0
2051 17:58:09.012341 ===================================
2052 17:58:09.012437 [ANA_INIT] >>>>>>>>>>>>>>
2053 17:58:09.012532 <<<<<< [CONFIGURE PHASE]: ANA_TX
2054 17:58:09.012630 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2055 17:58:09.012726 ===================================
2056 17:58:09.012824 data_rate = 2400,PCW = 0X5b00
2057 17:58:09.012920 ===================================
2058 17:58:09.013017 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2059 17:58:09.013115 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2060 17:58:09.013211 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2061 17:58:09.013309 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2062 17:58:09.013405 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2063 17:58:09.013500 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2064 17:58:09.013597 [ANA_INIT] flow start
2065 17:58:09.013691 [ANA_INIT] PLL >>>>>>>>
2066 17:58:09.013787 [ANA_INIT] PLL <<<<<<<<
2067 17:58:09.013883 [ANA_INIT] MIDPI >>>>>>>>
2068 17:58:09.013977 [ANA_INIT] MIDPI <<<<<<<<
2069 17:58:09.014078 [ANA_INIT] DLL >>>>>>>>
2070 17:58:09.014174 [ANA_INIT] DLL <<<<<<<<
2071 17:58:09.014269 [ANA_INIT] flow end
2072 17:58:09.014363 ============ LP4 DIFF to SE enter ============
2073 17:58:09.014458 ============ LP4 DIFF to SE exit ============
2074 17:58:09.014754 [ANA_INIT] <<<<<<<<<<<<<
2075 17:58:09.014848 [Flow] Enable top DCM control >>>>>
2076 17:58:09.014944 [Flow] Enable top DCM control <<<<<
2077 17:58:09.015038 Enable DLL master slave shuffle
2078 17:58:09.015132 ==============================================================
2079 17:58:09.015230 Gating Mode config
2080 17:58:09.015323 ==============================================================
2081 17:58:09.015417 Config description:
2082 17:58:09.015511 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2083 17:58:09.015605 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2084 17:58:09.015700 SELPH_MODE 0: By rank 1: By Phase
2085 17:58:09.015794 ==============================================================
2086 17:58:09.015887 GAT_TRACK_EN = 1
2087 17:58:09.015981 RX_GATING_MODE = 2
2088 17:58:09.016073 RX_GATING_TRACK_MODE = 2
2089 17:58:09.016167 SELPH_MODE = 1
2090 17:58:09.016259 PICG_EARLY_EN = 1
2091 17:58:09.016351 VALID_LAT_VALUE = 1
2092 17:58:09.016444 ==============================================================
2093 17:58:09.016537 Enter into Gating configuration >>>>
2094 17:58:09.016630 Exit from Gating configuration <<<<
2095 17:58:09.016722 Enter into DVFS_PRE_config >>>>>
2096 17:58:09.016814 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2097 17:58:09.016910 Exit from DVFS_PRE_config <<<<<
2098 17:58:09.017002 Enter into PICG configuration >>>>
2099 17:58:09.017094 Exit from PICG configuration <<<<
2100 17:58:09.017185 [RX_INPUT] configuration >>>>>
2101 17:58:09.017277 [RX_INPUT] configuration <<<<<
2102 17:58:09.017371 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2103 17:58:09.017464 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2104 17:58:09.017556 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2105 17:58:09.017651 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2106 17:58:09.017743 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2107 17:58:09.017837 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2108 17:58:09.017929 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2109 17:58:09.018021 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2110 17:58:09.018122 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2111 17:58:09.018215 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2112 17:58:09.018306 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2113 17:58:09.018398 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2114 17:58:09.018490 ===================================
2115 17:58:09.018584 LPDDR4 DRAM CONFIGURATION
2116 17:58:09.018677 ===================================
2117 17:58:09.018769 EX_ROW_EN[0] = 0x0
2118 17:58:09.018863 EX_ROW_EN[1] = 0x0
2119 17:58:09.018954 LP4Y_EN = 0x0
2120 17:58:09.019051 WORK_FSP = 0x0
2121 17:58:09.019144 WL = 0x4
2122 17:58:09.019235 RL = 0x4
2123 17:58:09.019329 BL = 0x2
2124 17:58:09.019420 RPST = 0x0
2125 17:58:09.019511 RD_PRE = 0x0
2126 17:58:09.019602 WR_PRE = 0x1
2127 17:58:09.019694 WR_PST = 0x0
2128 17:58:09.019786 DBI_WR = 0x0
2129 17:58:09.019877 DBI_RD = 0x0
2130 17:58:09.019968 OTF = 0x1
2131 17:58:09.020062 ===================================
2132 17:58:09.020154 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2133 17:58:09.020248 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2134 17:58:09.020341 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2135 17:58:09.020432 ===================================
2136 17:58:09.020526 LPDDR4 DRAM CONFIGURATION
2137 17:58:09.020618 ===================================
2138 17:58:09.020709 EX_ROW_EN[0] = 0x10
2139 17:58:09.020801 EX_ROW_EN[1] = 0x0
2140 17:58:09.020892 LP4Y_EN = 0x0
2141 17:58:09.020985 WORK_FSP = 0x0
2142 17:58:09.021076 WL = 0x4
2143 17:58:09.021167 RL = 0x4
2144 17:58:09.021260 BL = 0x2
2145 17:58:09.021351 RPST = 0x0
2146 17:58:09.021442 RD_PRE = 0x0
2147 17:58:09.021533 WR_PRE = 0x1
2148 17:58:09.021623 WR_PST = 0x0
2149 17:58:09.021716 DBI_WR = 0x0
2150 17:58:09.021810 DBI_RD = 0x0
2151 17:58:09.021901 OTF = 0x1
2152 17:58:09.021995 ===================================
2153 17:58:09.022097 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2154 17:58:09.022193 ==
2155 17:58:09.022269 Dram Type= 6, Freq= 0, CH_0, rank 0
2156 17:58:09.022362 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2157 17:58:09.022462 ==
2158 17:58:09.022557 [Duty_Offset_Calibration]
2159 17:58:09.022651 B0:0 B1:2 CA:1
2160 17:58:09.022743
2161 17:58:09.022835 [DutyScan_Calibration_Flow] k_type=0
2162 17:58:09.022930
2163 17:58:09.023022 ==CLK 0==
2164 17:58:09.023114 Final CLK duty delay cell = 0
2165 17:58:09.023209 [0] MAX Duty = 5093%(X100), DQS PI = 12
2166 17:58:09.023301 [0] MIN Duty = 4938%(X100), DQS PI = 54
2167 17:58:09.023394 [0] AVG Duty = 5015%(X100)
2168 17:58:09.023467
2169 17:58:09.023540 CH0 CLK Duty spec in!! Max-Min= 155%
2170 17:58:09.023634 [DutyScan_Calibration_Flow] ====Done====
2171 17:58:09.023726
2172 17:58:09.023817 [DutyScan_Calibration_Flow] k_type=1
2173 17:58:09.023911
2174 17:58:09.024002 ==DQS 0 ==
2175 17:58:09.024093 Final DQS duty delay cell = 0
2176 17:58:09.024185 [0] MAX Duty = 5125%(X100), DQS PI = 32
2177 17:58:09.024277 [0] MIN Duty = 5031%(X100), DQS PI = 4
2178 17:58:09.024370 [0] AVG Duty = 5078%(X100)
2179 17:58:09.024461
2180 17:58:09.024552 ==DQS 1 ==
2181 17:58:09.024646 Final DQS duty delay cell = 0
2182 17:58:09.024738 [0] MAX Duty = 5062%(X100), DQS PI = 58
2183 17:58:09.024829 [0] MIN Duty = 4906%(X100), DQS PI = 16
2184 17:58:09.024921 [0] AVG Duty = 4984%(X100)
2185 17:58:09.025012
2186 17:58:09.025106 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2187 17:58:09.025197
2188 17:58:09.025288 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2189 17:58:09.025381 [DutyScan_Calibration_Flow] ====Done====
2190 17:58:09.025472
2191 17:58:09.025563 [DutyScan_Calibration_Flow] k_type=3
2192 17:58:09.025655
2193 17:58:09.025746 ==DQM 0 ==
2194 17:58:09.025841 Final DQM duty delay cell = 0
2195 17:58:09.025933 [0] MAX Duty = 5124%(X100), DQS PI = 20
2196 17:58:09.026239 [0] MIN Duty = 4969%(X100), DQS PI = 42
2197 17:58:09.026339 [0] AVG Duty = 5046%(X100)
2198 17:58:09.026434
2199 17:58:09.026527 ==DQM 1 ==
2200 17:58:09.026621 Final DQM duty delay cell = 4
2201 17:58:09.026715 [4] MAX Duty = 5187%(X100), DQS PI = 54
2202 17:58:09.026808 [4] MIN Duty = 5000%(X100), DQS PI = 18
2203 17:58:09.026901 [4] AVG Duty = 5093%(X100)
2204 17:58:09.026993
2205 17:58:09.027087 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2206 17:58:09.027179
2207 17:58:09.027271 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2208 17:58:09.027365 [DutyScan_Calibration_Flow] ====Done====
2209 17:58:09.027456
2210 17:58:09.027547 [DutyScan_Calibration_Flow] k_type=2
2211 17:58:09.027638
2212 17:58:09.027729 ==DQ 0 ==
2213 17:58:09.027822 Final DQ duty delay cell = -4
2214 17:58:09.027914 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2215 17:58:09.028006 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2216 17:58:09.028100 [-4] AVG Duty = 4937%(X100)
2217 17:58:09.028191
2218 17:58:09.028282 ==DQ 1 ==
2219 17:58:09.028374 Final DQ duty delay cell = -4
2220 17:58:09.028465 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2221 17:58:09.028558 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2222 17:58:09.028650 [-4] AVG Duty = 4969%(X100)
2223 17:58:09.028741
2224 17:58:09.028835 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2225 17:58:09.028927
2226 17:58:09.029019 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2227 17:58:09.029114 [DutyScan_Calibration_Flow] ====Done====
2228 17:58:09.029206 ==
2229 17:58:09.029297 Dram Type= 6, Freq= 0, CH_1, rank 0
2230 17:58:09.029390 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2231 17:58:09.029482 ==
2232 17:58:09.029575 [Duty_Offset_Calibration]
2233 17:58:09.029667 B0:0 B1:4 CA:-5
2234 17:58:09.029758
2235 17:58:09.029852 [DutyScan_Calibration_Flow] k_type=0
2236 17:58:09.029944
2237 17:58:09.030047 ==CLK 0==
2238 17:58:09.030140 Final CLK duty delay cell = 0
2239 17:58:09.030233 [0] MAX Duty = 5094%(X100), DQS PI = 24
2240 17:58:09.030328 [0] MIN Duty = 4907%(X100), DQS PI = 44
2241 17:58:09.030420 [0] AVG Duty = 5000%(X100)
2242 17:58:09.030511
2243 17:58:09.030604 CH1 CLK Duty spec in!! Max-Min= 187%
2244 17:58:09.030696 [DutyScan_Calibration_Flow] ====Done====
2245 17:58:09.030788
2246 17:58:09.030878 [DutyScan_Calibration_Flow] k_type=1
2247 17:58:09.030970
2248 17:58:09.031063 ==DQS 0 ==
2249 17:58:09.031155 Final DQS duty delay cell = 0
2250 17:58:09.031248 [0] MAX Duty = 5125%(X100), DQS PI = 16
2251 17:58:09.031342 [0] MIN Duty = 4875%(X100), DQS PI = 40
2252 17:58:09.031434 [0] AVG Duty = 5000%(X100)
2253 17:58:09.031525
2254 17:58:09.031616 ==DQS 1 ==
2255 17:58:09.031708 Final DQS duty delay cell = -4
2256 17:58:09.031802 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2257 17:58:09.031894 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2258 17:58:09.031985 [-4] AVG Duty = 4953%(X100)
2259 17:58:09.032079
2260 17:58:09.032171 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2261 17:58:09.032262
2262 17:58:09.032355 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2263 17:58:09.032446 [DutyScan_Calibration_Flow] ====Done====
2264 17:58:09.032538
2265 17:58:09.032628 [DutyScan_Calibration_Flow] k_type=3
2266 17:58:09.032720
2267 17:58:09.032814 ==DQM 0 ==
2268 17:58:09.032906 Final DQM duty delay cell = -4
2269 17:58:09.032998 [-4] MAX Duty = 5093%(X100), DQS PI = 32
2270 17:58:09.033092 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2271 17:58:09.033184 [-4] AVG Duty = 4968%(X100)
2272 17:58:09.033275
2273 17:58:09.033368 ==DQM 1 ==
2274 17:58:09.033460 Final DQM duty delay cell = -4
2275 17:58:09.033554 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2276 17:58:09.033645 [-4] MIN Duty = 4875%(X100), DQS PI = 60
2277 17:58:09.033737 [-4] AVG Duty = 4968%(X100)
2278 17:58:09.033830
2279 17:58:09.033921 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2280 17:58:09.034013
2281 17:58:09.034108 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2282 17:58:09.034200 [DutyScan_Calibration_Flow] ====Done====
2283 17:58:09.034293
2284 17:58:09.034384 [DutyScan_Calibration_Flow] k_type=2
2285 17:58:09.034475
2286 17:58:09.034568 ==DQ 0 ==
2287 17:58:09.034660 Final DQ duty delay cell = 0
2288 17:58:09.034752 [0] MAX Duty = 5062%(X100), DQS PI = 0
2289 17:58:09.034845 [0] MIN Duty = 4969%(X100), DQS PI = 42
2290 17:58:09.034939 [0] AVG Duty = 5015%(X100)
2291 17:58:09.035030
2292 17:58:09.035121 ==DQ 1 ==
2293 17:58:09.035223 Final DQ duty delay cell = 0
2294 17:58:09.035317 [0] MAX Duty = 5000%(X100), DQS PI = 6
2295 17:58:09.035411 [0] MIN Duty = 4907%(X100), DQS PI = 0
2296 17:58:09.035506 [0] AVG Duty = 4953%(X100)
2297 17:58:09.035602
2298 17:58:09.035690 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2299 17:58:09.035778
2300 17:58:09.035864 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2301 17:58:09.035950 [DutyScan_Calibration_Flow] ====Done====
2302 17:58:09.036034 nWR fixed to 30
2303 17:58:09.036121 [ModeRegInit_LP4] CH0 RK0
2304 17:58:09.036203 [ModeRegInit_LP4] CH0 RK1
2305 17:58:09.036288 [ModeRegInit_LP4] CH1 RK0
2306 17:58:09.036373 [ModeRegInit_LP4] CH1 RK1
2307 17:58:09.036455 match AC timing 6
2308 17:58:09.036544 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2309 17:58:09.036628 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2310 17:58:09.036711 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2311 17:58:09.036798 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2312 17:58:09.036883 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2313 17:58:09.036965 ==
2314 17:58:09.037051 Dram Type= 6, Freq= 0, CH_0, rank 0
2315 17:58:09.037135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2316 17:58:09.037218 ==
2317 17:58:09.037304 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2318 17:58:09.037388 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2319 17:58:09.037472 [CA 0] Center 39 (9~70) winsize 62
2320 17:58:09.037555 [CA 1] Center 39 (8~70) winsize 63
2321 17:58:09.037637 [CA 2] Center 36 (5~67) winsize 63
2322 17:58:09.037722 [CA 3] Center 35 (4~66) winsize 63
2323 17:58:09.037805 [CA 4] Center 34 (3~65) winsize 63
2324 17:58:09.037888 [CA 5] Center 34 (3~65) winsize 63
2325 17:58:09.037972
2326 17:58:09.038065 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2327 17:58:09.038149
2328 17:58:09.038236 [CATrainingPosCal] consider 1 rank data
2329 17:58:09.038322 u2DelayCellTimex100 = 270/100 ps
2330 17:58:09.038407 CA0 delay=39 (9~70),Diff = 5 PI (24 cell)
2331 17:58:09.038491 CA1 delay=39 (8~70),Diff = 5 PI (24 cell)
2332 17:58:09.038576 CA2 delay=36 (5~67),Diff = 2 PI (9 cell)
2333 17:58:09.038660 CA3 delay=35 (4~66),Diff = 1 PI (4 cell)
2334 17:58:09.038744 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
2335 17:58:09.038826 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
2336 17:58:09.038911
2337 17:58:09.038994 CA PerBit enable=1, Macro0, CA PI delay=34
2338 17:58:09.039077
2339 17:58:09.039162 [CBTSetCACLKResult] CA Dly = 34
2340 17:58:09.039245 CS Dly: 7 (0~38)
2341 17:58:09.039327 ==
2342 17:58:09.039412 Dram Type= 6, Freq= 0, CH_0, rank 1
2343 17:58:09.039494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2344 17:58:09.039579 ==
2345 17:58:09.039871 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2346 17:58:09.039967 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2347 17:58:09.040056 [CA 0] Center 39 (8~70) winsize 63
2348 17:58:09.040144 [CA 1] Center 39 (8~70) winsize 63
2349 17:58:09.040229 [CA 2] Center 36 (5~67) winsize 63
2350 17:58:09.040316 [CA 3] Center 35 (4~66) winsize 63
2351 17:58:09.040400 [CA 4] Center 33 (3~64) winsize 62
2352 17:58:09.040483 [CA 5] Center 34 (3~65) winsize 63
2353 17:58:09.040568
2354 17:58:09.040650 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2355 17:58:09.040734
2356 17:58:09.040819 [CATrainingPosCal] consider 2 rank data
2357 17:58:09.040902 u2DelayCellTimex100 = 270/100 ps
2358 17:58:09.040986 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2359 17:58:09.041072 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2360 17:58:09.041156 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2361 17:58:09.041238 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2362 17:58:09.041324 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2363 17:58:09.041405 CA5 delay=34 (3~65),Diff = 1 PI (4 cell)
2364 17:58:09.041487
2365 17:58:09.041572 CA PerBit enable=1, Macro0, CA PI delay=33
2366 17:58:09.041656
2367 17:58:09.041738 [CBTSetCACLKResult] CA Dly = 33
2368 17:58:09.041819 CS Dly: 7 (0~39)
2369 17:58:09.041896
2370 17:58:09.041972 ----->DramcWriteLeveling(PI) begin...
2371 17:58:09.042062 ==
2372 17:58:09.042145 Dram Type= 6, Freq= 0, CH_0, rank 0
2373 17:58:09.042232 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2374 17:58:09.042319 ==
2375 17:58:09.042402 Write leveling (Byte 0): 29 => 29
2376 17:58:09.042489 Write leveling (Byte 1): 26 => 26
2377 17:58:09.042574 DramcWriteLeveling(PI) end<-----
2378 17:58:09.042656
2379 17:58:09.042741 ==
2380 17:58:09.042824 Dram Type= 6, Freq= 0, CH_0, rank 0
2381 17:58:09.042905 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2382 17:58:09.042989 ==
2383 17:58:09.043069 [Gating] SW mode calibration
2384 17:58:09.043161 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2385 17:58:09.043258 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2386 17:58:09.043355 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2387 17:58:09.043455 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2388 17:58:09.043549 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2389 17:58:09.043644 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2390 17:58:09.043751 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2391 17:58:09.043851 0 11 20 | B1->B0 | 2d2d 2828 | 0 1 | (0 1) (1 0)
2392 17:58:09.043942 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2393 17:58:09.044029 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2394 17:58:09.044116 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2395 17:58:09.044201 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2396 17:58:09.044284 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2397 17:58:09.044371 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2398 17:58:09.044454 0 12 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2399 17:58:09.044537 0 12 20 | B1->B0 | 3838 4040 | 0 1 | (0 0) (0 0)
2400 17:58:09.044626 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2401 17:58:09.044709 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2402 17:58:09.044800 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2403 17:58:09.044886 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2404 17:58:09.044969 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2405 17:58:09.045056 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2406 17:58:09.045140 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2407 17:58:09.045223 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2408 17:58:09.045310 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2409 17:58:09.045393 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 17:58:09.045475 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 17:58:09.045561 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 17:58:09.045644 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 17:58:09.045727 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 17:58:09.045812 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 17:58:09.045894 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2416 17:58:09.045979 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2417 17:58:09.046064 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2418 17:58:09.046119 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2419 17:58:09.046172 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2420 17:58:09.046228 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2421 17:58:09.046281 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2422 17:58:09.046333 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2423 17:58:09.046385 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2424 17:58:09.046437 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2425 17:58:09.046495 Total UI for P1: 0, mck2ui 16
2426 17:58:09.046549 best dqsien dly found for B0: ( 0, 15, 18)
2427 17:58:09.046603 Total UI for P1: 0, mck2ui 16
2428 17:58:09.046656 best dqsien dly found for B1: ( 0, 15, 18)
2429 17:58:09.046712 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2430 17:58:09.046766 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2431 17:58:09.046819
2432 17:58:09.046871 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2433 17:58:09.046924 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2434 17:58:09.046982 [Gating] SW calibration Done
2435 17:58:09.047035 ==
2436 17:58:09.047087 Dram Type= 6, Freq= 0, CH_0, rank 0
2437 17:58:09.047140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2438 17:58:09.047200 ==
2439 17:58:09.047282 RX Vref Scan: 0
2440 17:58:09.047363
2441 17:58:09.047447 RX Vref 0 -> 0, step: 1
2442 17:58:09.047529
2443 17:58:09.047610 RX Delay -40 -> 252, step: 8
2444 17:58:09.047696 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2445 17:58:09.047779 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2446 17:58:09.047861 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2447 17:58:09.047947 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2448 17:58:09.048029 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2449 17:58:09.048111 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2450 17:58:09.048397 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2451 17:58:09.048489 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2452 17:58:09.048574 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2453 17:58:09.048663 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2454 17:58:09.048748 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2455 17:58:09.048838 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2456 17:58:09.048923 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2457 17:58:09.049006 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2458 17:58:09.049088 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2459 17:58:09.049143 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2460 17:58:09.049196 ==
2461 17:58:09.049249 Dram Type= 6, Freq= 0, CH_0, rank 0
2462 17:58:09.049306 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2463 17:58:09.049361 ==
2464 17:58:09.049414 DQS Delay:
2465 17:58:09.049466 DQS0 = 0, DQS1 = 0
2466 17:58:09.049518 DQM Delay:
2467 17:58:09.049588 DQM0 = 115, DQM1 = 106
2468 17:58:09.049669 DQ Delay:
2469 17:58:09.049751 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2470 17:58:09.049836 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2471 17:58:09.049918 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2472 17:58:09.050000 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2473 17:58:09.050076
2474 17:58:09.050129
2475 17:58:09.050181 ==
2476 17:58:09.050233 Dram Type= 6, Freq= 0, CH_0, rank 0
2477 17:58:09.050290 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2478 17:58:09.050344 ==
2479 17:58:09.050396
2480 17:58:09.050447
2481 17:58:09.050502 TX Vref Scan disable
2482 17:58:09.050556 == TX Byte 0 ==
2483 17:58:09.050608 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2484 17:58:09.050660 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2485 17:58:09.050713 == TX Byte 1 ==
2486 17:58:09.050796 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2487 17:58:09.050878 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2488 17:58:09.050959 ==
2489 17:58:09.051044 Dram Type= 6, Freq= 0, CH_0, rank 0
2490 17:58:09.051127 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2491 17:58:09.051210 ==
2492 17:58:09.051294 TX Vref=22, minBit 10, minWin=24, winSum=411
2493 17:58:09.051377 TX Vref=24, minBit 8, minWin=25, winSum=418
2494 17:58:09.051462 TX Vref=26, minBit 10, minWin=24, winSum=420
2495 17:58:09.051545 TX Vref=28, minBit 8, minWin=26, winSum=431
2496 17:58:09.051628 TX Vref=30, minBit 9, minWin=26, winSum=433
2497 17:58:09.051713 TX Vref=32, minBit 8, minWin=26, winSum=429
2498 17:58:09.051797 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
2499 17:58:09.051878
2500 17:58:09.051963 Final TX Range 1 Vref 30
2501 17:58:09.052045
2502 17:58:09.052126 ==
2503 17:58:09.052210 Dram Type= 6, Freq= 0, CH_0, rank 0
2504 17:58:09.052293 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2505 17:58:09.052381 ==
2506 17:58:09.052467
2507 17:58:09.052550
2508 17:58:09.052634 TX Vref Scan disable
2509 17:58:09.052722 == TX Byte 0 ==
2510 17:58:09.052806 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2511 17:58:09.052890 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2512 17:58:09.052975 == TX Byte 1 ==
2513 17:58:09.053058 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2514 17:58:09.053140 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2515 17:58:09.053202
2516 17:58:09.053254 [DATLAT]
2517 17:58:09.053307 Freq=1200, CH0 RK0
2518 17:58:09.053360
2519 17:58:09.053416 DATLAT Default: 0xd
2520 17:58:09.053470 0, 0xFFFF, sum = 0
2521 17:58:09.053524 1, 0xFFFF, sum = 0
2522 17:58:09.053578 2, 0xFFFF, sum = 0
2523 17:58:09.053636 3, 0xFFFF, sum = 0
2524 17:58:09.053721 4, 0xFFFF, sum = 0
2525 17:58:09.053804 5, 0xFFFF, sum = 0
2526 17:58:09.053892 6, 0xFFFF, sum = 0
2527 17:58:09.053977 7, 0xFFFF, sum = 0
2528 17:58:09.054061 8, 0xFFFF, sum = 0
2529 17:58:09.054120 9, 0xFFFF, sum = 0
2530 17:58:09.054175 10, 0xFFFF, sum = 0
2531 17:58:09.054228 11, 0x0, sum = 1
2532 17:58:09.054280 12, 0x0, sum = 2
2533 17:58:09.054333 13, 0x0, sum = 3
2534 17:58:09.054392 14, 0x0, sum = 4
2535 17:58:09.054445 best_step = 12
2536 17:58:09.054498
2537 17:58:09.054549 ==
2538 17:58:09.054605 Dram Type= 6, Freq= 0, CH_0, rank 0
2539 17:58:09.054658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2540 17:58:09.054711 ==
2541 17:58:09.054763 RX Vref Scan: 1
2542 17:58:09.054818
2543 17:58:09.054871 Set Vref Range= 32 -> 127
2544 17:58:09.054923
2545 17:58:09.054975 RX Vref 32 -> 127, step: 1
2546 17:58:09.055027
2547 17:58:09.055109 RX Delay -21 -> 252, step: 4
2548 17:58:09.055190
2549 17:58:09.055273 Set Vref, RX VrefLevel [Byte0]: 32
2550 17:58:09.055357 [Byte1]: 32
2551 17:58:09.055438
2552 17:58:09.055522 Set Vref, RX VrefLevel [Byte0]: 33
2553 17:58:09.055605 [Byte1]: 33
2554 17:58:09.055686
2555 17:58:09.055770 Set Vref, RX VrefLevel [Byte0]: 34
2556 17:58:09.055852 [Byte1]: 34
2557 17:58:09.055938
2558 17:58:09.056025 Set Vref, RX VrefLevel [Byte0]: 35
2559 17:58:09.056111 [Byte1]: 35
2560 17:58:09.056194
2561 17:58:09.056284 Set Vref, RX VrefLevel [Byte0]: 36
2562 17:58:09.056368 [Byte1]: 36
2563 17:58:09.056452
2564 17:58:09.056535 Set Vref, RX VrefLevel [Byte0]: 37
2565 17:58:09.056617 [Byte1]: 37
2566 17:58:09.056701
2567 17:58:09.056783 Set Vref, RX VrefLevel [Byte0]: 38
2568 17:58:09.056865 [Byte1]: 38
2569 17:58:09.056950
2570 17:58:09.057032 Set Vref, RX VrefLevel [Byte0]: 39
2571 17:58:09.057114 [Byte1]: 39
2572 17:58:09.057191
2573 17:58:09.057245 Set Vref, RX VrefLevel [Byte0]: 40
2574 17:58:09.057297 [Byte1]: 40
2575 17:58:09.057349
2576 17:58:09.057403 Set Vref, RX VrefLevel [Byte0]: 41
2577 17:58:09.057458 [Byte1]: 41
2578 17:58:09.057509
2579 17:58:09.057561 Set Vref, RX VrefLevel [Byte0]: 42
2580 17:58:09.057613 [Byte1]: 42
2581 17:58:09.057695
2582 17:58:09.057777 Set Vref, RX VrefLevel [Byte0]: 43
2583 17:58:09.057861 [Byte1]: 43
2584 17:58:09.057943
2585 17:58:09.058032 Set Vref, RX VrefLevel [Byte0]: 44
2586 17:58:09.058092 [Byte1]: 44
2587 17:58:09.058146
2588 17:58:09.058198 Set Vref, RX VrefLevel [Byte0]: 45
2589 17:58:09.058250 [Byte1]: 45
2590 17:58:09.058302
2591 17:58:09.058358 Set Vref, RX VrefLevel [Byte0]: 46
2592 17:58:09.058410 [Byte1]: 46
2593 17:58:09.058461
2594 17:58:09.058512 Set Vref, RX VrefLevel [Byte0]: 47
2595 17:58:09.058570 [Byte1]: 47
2596 17:58:09.058622
2597 17:58:09.058674 Set Vref, RX VrefLevel [Byte0]: 48
2598 17:58:09.058726 [Byte1]: 48
2599 17:58:09.058782
2600 17:58:09.058835 Set Vref, RX VrefLevel [Byte0]: 49
2601 17:58:09.058887 [Byte1]: 49
2602 17:58:09.058939
2603 17:58:09.058990 Set Vref, RX VrefLevel [Byte0]: 50
2604 17:58:09.059046 [Byte1]: 50
2605 17:58:09.059098
2606 17:58:09.059150 Set Vref, RX VrefLevel [Byte0]: 51
2607 17:58:09.059202 [Byte1]: 51
2608 17:58:09.059274
2609 17:58:09.059356 Set Vref, RX VrefLevel [Byte0]: 52
2610 17:58:09.059635 [Byte1]: 52
2611 17:58:09.059732
2612 17:58:09.059817 Set Vref, RX VrefLevel [Byte0]: 53
2613 17:58:09.059905 [Byte1]: 53
2614 17:58:09.059989
2615 17:58:09.060081 Set Vref, RX VrefLevel [Byte0]: 54
2616 17:58:09.060167 [Byte1]: 54
2617 17:58:09.060250
2618 17:58:09.060333 Set Vref, RX VrefLevel [Byte0]: 55
2619 17:58:09.060417 [Byte1]: 55
2620 17:58:09.060500
2621 17:58:09.060581 Set Vref, RX VrefLevel [Byte0]: 56
2622 17:58:09.060666 [Byte1]: 56
2623 17:58:09.060748
2624 17:58:09.060830 Set Vref, RX VrefLevel [Byte0]: 57
2625 17:58:09.060915 [Byte1]: 57
2626 17:58:09.060996
2627 17:58:09.061078 Set Vref, RX VrefLevel [Byte0]: 58
2628 17:58:09.061149 [Byte1]: 58
2629 17:58:09.061202
2630 17:58:09.061254 Set Vref, RX VrefLevel [Byte0]: 59
2631 17:58:09.061306 [Byte1]: 59
2632 17:58:09.061362
2633 17:58:09.061414 Set Vref, RX VrefLevel [Byte0]: 60
2634 17:58:09.061466 [Byte1]: 60
2635 17:58:09.061519
2636 17:58:09.061570 Set Vref, RX VrefLevel [Byte0]: 61
2637 17:58:09.061650 [Byte1]: 61
2638 17:58:09.061731
2639 17:58:09.061812 Set Vref, RX VrefLevel [Byte0]: 62
2640 17:58:09.061897 [Byte1]: 62
2641 17:58:09.061978
2642 17:58:09.062072 Set Vref, RX VrefLevel [Byte0]: 63
2643 17:58:09.062128 [Byte1]: 63
2644 17:58:09.062180
2645 17:58:09.062232 Set Vref, RX VrefLevel [Byte0]: 64
2646 17:58:09.062284 [Byte1]: 64
2647 17:58:09.062342
2648 17:58:09.062394 Set Vref, RX VrefLevel [Byte0]: 65
2649 17:58:09.062447 [Byte1]: 65
2650 17:58:09.062499
2651 17:58:09.062558 Final RX Vref Byte 0 = 51 to rank0
2652 17:58:09.062611 Final RX Vref Byte 1 = 48 to rank0
2653 17:58:09.062663 Final RX Vref Byte 0 = 51 to rank1
2654 17:58:09.062715 Final RX Vref Byte 1 = 48 to rank1==
2655 17:58:09.062769 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 17:58:09.062826 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2657 17:58:09.062879 ==
2658 17:58:09.062931 DQS Delay:
2659 17:58:09.063004 DQS0 = 0, DQS1 = 0
2660 17:58:09.063076 DQM Delay:
2661 17:58:09.063130 DQM0 = 114, DQM1 = 105
2662 17:58:09.063182 DQ Delay:
2663 17:58:09.063234 DQ0 =110, DQ1 =114, DQ2 =114, DQ3 =110
2664 17:58:09.063307 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =122
2665 17:58:09.063394 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =96
2666 17:58:09.063480 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2667 17:58:09.063564
2668 17:58:09.063654
2669 17:58:09.063739 [DQSOSCAuto] RK0, (LSB)MR18= 0x404, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
2670 17:58:09.063823 CH0 RK0: MR19=404, MR18=404
2671 17:58:09.063910 CH0_RK0: MR19=0x404, MR18=0x404, DQSOSC=408, MR23=63, INC=39, DEC=26
2672 17:58:09.063992
2673 17:58:09.064075 ----->DramcWriteLeveling(PI) begin...
2674 17:58:09.064161 ==
2675 17:58:09.064244 Dram Type= 6, Freq= 0, CH_0, rank 1
2676 17:58:09.064326 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2677 17:58:09.064412 ==
2678 17:58:09.064494 Write leveling (Byte 0): 27 => 27
2679 17:58:09.064579 Write leveling (Byte 1): 24 => 24
2680 17:58:09.064662 DramcWriteLeveling(PI) end<-----
2681 17:58:09.064743
2682 17:58:09.064826 ==
2683 17:58:09.064909 Dram Type= 6, Freq= 0, CH_0, rank 1
2684 17:58:09.064991 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2685 17:58:09.065075 ==
2686 17:58:09.065158 [Gating] SW mode calibration
2687 17:58:09.065242 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2688 17:58:09.065321 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2689 17:58:09.065375 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2690 17:58:09.065428 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2691 17:58:09.065481 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2692 17:58:09.065533 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2693 17:58:09.065609 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2694 17:58:09.065693 0 11 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2695 17:58:09.065776 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2696 17:58:09.065861 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2697 17:58:09.065944 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2698 17:58:09.066032 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2699 17:58:09.066119 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2700 17:58:09.066202 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2701 17:58:09.066286 0 12 16 | B1->B0 | 2626 3535 | 0 0 | (0 0) (0 0)
2702 17:58:09.066354 0 12 20 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
2703 17:58:09.066408 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2704 17:58:09.066461 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2705 17:58:09.066512 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2706 17:58:09.066571 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2707 17:58:09.066655 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2708 17:58:09.066737 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2709 17:58:09.066822 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2710 17:58:09.066905 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2711 17:58:09.066990 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2712 17:58:09.067057 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2713 17:58:09.067147 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2714 17:58:09.067231 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2715 17:58:09.067316 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2716 17:58:09.067403 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2717 17:58:09.067488 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2718 17:58:09.067574 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2719 17:58:09.067658 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2720 17:58:09.067740 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2721 17:58:09.067825 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2722 17:58:09.067908 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2723 17:58:09.067990 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2724 17:58:09.068076 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2725 17:58:09.068158 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2726 17:58:09.068434 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2727 17:58:09.068525 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2728 17:58:09.068609 Total UI for P1: 0, mck2ui 16
2729 17:58:09.068693 best dqsien dly found for B0: ( 0, 15, 18)
2730 17:58:09.068773 Total UI for P1: 0, mck2ui 16
2731 17:58:09.068829 best dqsien dly found for B1: ( 0, 15, 20)
2732 17:58:09.068882 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2733 17:58:09.068934 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2734 17:58:09.068994
2735 17:58:09.069077 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2736 17:58:09.069159 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2737 17:58:09.069243 [Gating] SW calibration Done
2738 17:58:09.069325 ==
2739 17:58:09.069407 Dram Type= 6, Freq= 0, CH_0, rank 1
2740 17:58:09.069492 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2741 17:58:09.069575 ==
2742 17:58:09.069656 RX Vref Scan: 0
2743 17:58:09.069741
2744 17:58:09.069845 RX Vref 0 -> 0, step: 1
2745 17:58:09.069935
2746 17:58:09.070036 RX Delay -40 -> 252, step: 8
2747 17:58:09.070130 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2748 17:58:09.070226 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2749 17:58:09.070311 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2750 17:58:09.070398 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2751 17:58:09.070495 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2752 17:58:09.070554 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2753 17:58:09.070607 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2754 17:58:09.070667 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2755 17:58:09.070721 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2756 17:58:09.070774 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2757 17:58:09.070827 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2758 17:58:09.070886 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2759 17:58:09.070938 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2760 17:58:09.070991 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2761 17:58:09.071043 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2762 17:58:09.071098 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2763 17:58:09.071152 ==
2764 17:58:09.071224 Dram Type= 6, Freq= 0, CH_0, rank 1
2765 17:58:09.071310 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2766 17:58:09.071399 ==
2767 17:58:09.071483 DQS Delay:
2768 17:58:09.071570 DQS0 = 0, DQS1 = 0
2769 17:58:09.071656 DQM Delay:
2770 17:58:09.071738 DQM0 = 116, DQM1 = 107
2771 17:58:09.071820 DQ Delay:
2772 17:58:09.071904 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =111
2773 17:58:09.071987 DQ4 =119, DQ5 =107, DQ6 =123, DQ7 =123
2774 17:58:09.072070 DQ8 =91, DQ9 =91, DQ10 =111, DQ11 =99
2775 17:58:09.072154 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2776 17:58:09.072236
2777 17:58:09.072319
2778 17:58:09.072401 ==
2779 17:58:09.072483 Dram Type= 6, Freq= 0, CH_0, rank 1
2780 17:58:09.072568 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2781 17:58:09.072650 ==
2782 17:58:09.072731
2783 17:58:09.072815
2784 17:58:09.072897 TX Vref Scan disable
2785 17:58:09.072978 == TX Byte 0 ==
2786 17:58:09.073060 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2787 17:58:09.073137 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2788 17:58:09.073192 == TX Byte 1 ==
2789 17:58:09.073244 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2790 17:58:09.073297 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2791 17:58:09.073353 ==
2792 17:58:09.073407 Dram Type= 6, Freq= 0, CH_0, rank 1
2793 17:58:09.073459 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2794 17:58:09.073511 ==
2795 17:58:09.073564 TX Vref=22, minBit 5, minWin=25, winSum=414
2796 17:58:09.073649 TX Vref=24, minBit 1, minWin=26, winSum=428
2797 17:58:09.073732 TX Vref=26, minBit 8, minWin=25, winSum=428
2798 17:58:09.073817 TX Vref=28, minBit 8, minWin=26, winSum=429
2799 17:58:09.073900 TX Vref=30, minBit 8, minWin=26, winSum=435
2800 17:58:09.073983 TX Vref=32, minBit 8, minWin=26, winSum=434
2801 17:58:09.074075 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 30
2802 17:58:09.074146
2803 17:58:09.074200 Final TX Range 1 Vref 30
2804 17:58:09.074252
2805 17:58:09.074304 ==
2806 17:58:09.074356 Dram Type= 6, Freq= 0, CH_0, rank 1
2807 17:58:09.074410 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2808 17:58:09.074470 ==
2809 17:58:09.074522
2810 17:58:09.074574
2811 17:58:09.074625 TX Vref Scan disable
2812 17:58:09.074682 == TX Byte 0 ==
2813 17:58:09.074735 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2814 17:58:09.074788 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2815 17:58:09.074840 == TX Byte 1 ==
2816 17:58:09.074892 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2817 17:58:09.074950 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2818 17:58:09.075038
2819 17:58:09.075121 [DATLAT]
2820 17:58:09.075207 Freq=1200, CH0 RK1
2821 17:58:09.075292
2822 17:58:09.075375 DATLAT Default: 0xc
2823 17:58:09.075460 0, 0xFFFF, sum = 0
2824 17:58:09.075545 1, 0xFFFF, sum = 0
2825 17:58:09.075629 2, 0xFFFF, sum = 0
2826 17:58:09.075716 3, 0xFFFF, sum = 0
2827 17:58:09.075800 4, 0xFFFF, sum = 0
2828 17:58:09.075883 5, 0xFFFF, sum = 0
2829 17:58:09.075970 6, 0xFFFF, sum = 0
2830 17:58:09.076054 7, 0xFFFF, sum = 0
2831 17:58:09.076137 8, 0xFFFF, sum = 0
2832 17:58:09.076224 9, 0xFFFF, sum = 0
2833 17:58:09.076307 10, 0xFFFF, sum = 0
2834 17:58:09.076391 11, 0x0, sum = 1
2835 17:58:09.076477 12, 0x0, sum = 2
2836 17:58:09.076561 13, 0x0, sum = 3
2837 17:58:09.076646 14, 0x0, sum = 4
2838 17:58:09.076731 best_step = 12
2839 17:58:09.076812
2840 17:58:09.076896 ==
2841 17:58:09.076978 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 17:58:09.077061 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2843 17:58:09.077134 ==
2844 17:58:09.077188 RX Vref Scan: 0
2845 17:58:09.077240
2846 17:58:09.077292 RX Vref 0 -> 0, step: 1
2847 17:58:09.077345
2848 17:58:09.077429 RX Delay -21 -> 252, step: 4
2849 17:58:09.077511 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2850 17:58:09.077595 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2851 17:58:09.077679 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2852 17:58:09.077762 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2853 17:58:09.077846 iDelay=199, Bit 4, Center 116 (43 ~ 190) 148
2854 17:58:09.077929 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2855 17:58:09.078011 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2856 17:58:09.078102 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2857 17:58:09.078157 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2858 17:58:09.078210 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2859 17:58:09.078262 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2860 17:58:09.078317 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2861 17:58:09.078372 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2862 17:58:09.078424 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2863 17:58:09.078475 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2864 17:58:09.078722 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2865 17:58:09.078781 ==
2866 17:58:09.078854 Dram Type= 6, Freq= 0, CH_0, rank 1
2867 17:58:09.078940 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2868 17:58:09.079029 ==
2869 17:58:09.079111 DQS Delay:
2870 17:58:09.079202 DQS0 = 0, DQS1 = 0
2871 17:58:09.079286 DQM Delay:
2872 17:58:09.079371 DQM0 = 114, DQM1 = 105
2873 17:58:09.079453 DQ Delay:
2874 17:58:09.079537 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2875 17:58:09.079620 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =124
2876 17:58:09.079703 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2877 17:58:09.079789 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2878 17:58:09.079871
2879 17:58:09.079951
2880 17:58:09.080038 [DQSOSCAuto] RK1, (LSB)MR18= 0xb0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2881 17:58:09.080121 CH0 RK1: MR19=404, MR18=B0B
2882 17:58:09.080206 CH0_RK1: MR19=0x404, MR18=0xB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
2883 17:58:09.080290 [RxdqsGatingPostProcess] freq 1200
2884 17:58:09.080372 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2885 17:58:09.080457 Pre-setting of DQS Precalculation
2886 17:58:09.080540 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2887 17:58:09.080622 ==
2888 17:58:09.080708 Dram Type= 6, Freq= 0, CH_1, rank 0
2889 17:58:09.080792 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2890 17:58:09.080874 ==
2891 17:58:09.081436 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2892 17:58:09.088100 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2893 17:58:09.096992 [CA 0] Center 37 (7~68) winsize 62
2894 17:58:09.099678 [CA 1] Center 37 (7~68) winsize 62
2895 17:58:09.103579 [CA 2] Center 34 (4~65) winsize 62
2896 17:58:09.106778 [CA 3] Center 34 (4~64) winsize 61
2897 17:58:09.109910 [CA 4] Center 32 (2~63) winsize 62
2898 17:58:09.113118 [CA 5] Center 32 (2~63) winsize 62
2899 17:58:09.113187
2900 17:58:09.116393 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2901 17:58:09.116465
2902 17:58:09.119666 [CATrainingPosCal] consider 1 rank data
2903 17:58:09.123338 u2DelayCellTimex100 = 270/100 ps
2904 17:58:09.126369 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2905 17:58:09.133070 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2906 17:58:09.136776 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2907 17:58:09.140045 CA3 delay=34 (4~64),Diff = 2 PI (9 cell)
2908 17:58:09.143277 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2909 17:58:09.146349 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2910 17:58:09.146447
2911 17:58:09.149995 CA PerBit enable=1, Macro0, CA PI delay=32
2912 17:58:09.150078
2913 17:58:09.153158 [CBTSetCACLKResult] CA Dly = 32
2914 17:58:09.153242 CS Dly: 5 (0~36)
2915 17:58:09.156373 ==
2916 17:58:09.156475 Dram Type= 6, Freq= 0, CH_1, rank 1
2917 17:58:09.163544 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2918 17:58:09.163645 ==
2919 17:58:09.166725 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2920 17:58:09.172992 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2921 17:58:09.182327 [CA 0] Center 37 (7~68) winsize 62
2922 17:58:09.185498 [CA 1] Center 37 (7~68) winsize 62
2923 17:58:09.188586 [CA 2] Center 33 (3~64) winsize 62
2924 17:58:09.191682 [CA 3] Center 33 (3~64) winsize 62
2925 17:58:09.195372 [CA 4] Center 32 (2~63) winsize 62
2926 17:58:09.198708 [CA 5] Center 32 (1~63) winsize 63
2927 17:58:09.198782
2928 17:58:10.994861 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2929 17:58:10.995036
2930 17:58:10.995145 [CATrainingPosCal] consider 2 rank data
2931 17:58:10.995248 u2DelayCellTimex100 = 270/100 ps
2932 17:58:10.995348 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2933 17:58:10.995448 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2934 17:58:10.995546 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2935 17:58:10.995644 CA3 delay=34 (4~64),Diff = 2 PI (9 cell)
2936 17:58:10.995742 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2937 17:58:10.995839 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2938 17:58:10.995935
2939 17:58:10.996030 CA PerBit enable=1, Macro0, CA PI delay=32
2940 17:58:10.996143
2941 17:58:10.996252 [CBTSetCACLKResult] CA Dly = 32
2942 17:58:10.996348 CS Dly: 6 (0~38)
2943 17:58:10.996443
2944 17:58:10.996538 ----->DramcWriteLeveling(PI) begin...
2945 17:58:10.996635 ==
2946 17:58:10.996762 Dram Type= 6, Freq= 0, CH_1, rank 0
2947 17:58:10.996857 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2948 17:58:10.996953 ==
2949 17:58:10.997047 Write leveling (Byte 0): 21 => 21
2950 17:58:10.997143 Write leveling (Byte 1): 22 => 22
2951 17:58:10.997237 DramcWriteLeveling(PI) end<-----
2952 17:58:10.997331
2953 17:58:10.997426 ==
2954 17:58:10.997519 Dram Type= 6, Freq= 0, CH_1, rank 0
2955 17:58:10.997614 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2956 17:58:10.997708 ==
2957 17:58:10.997803 [Gating] SW mode calibration
2958 17:58:10.997898 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2959 17:58:10.997993 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2960 17:58:10.998129 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2961 17:58:10.998226 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2962 17:58:10.998322 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2963 17:58:10.998417 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2964 17:58:10.998514 0 11 16 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (0 0)
2965 17:58:10.998619 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2966 17:58:10.998725 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2967 17:58:10.998831 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2968 17:58:10.998935 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2969 17:58:10.999039 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2970 17:58:10.999141 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2971 17:58:10.999240 0 12 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2972 17:58:10.999336 0 12 16 | B1->B0 | 2d2d 3939 | 0 1 | (0 0) (0 0)
2973 17:58:10.999433 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2974 17:58:10.999529 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2975 17:58:10.999626 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2976 17:58:10.999721 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2977 17:58:10.999846 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2978 17:58:10.999942 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2979 17:58:11.000037 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 17:58:11.000133 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2981 17:58:11.000227 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2982 17:58:11.000322 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2983 17:58:11.000416 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 17:58:11.000510 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 17:58:11.000605 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 17:58:11.000699 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 17:58:11.000794 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 17:58:11.000888 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 17:58:11.000983 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 17:58:11.001077 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 17:58:11.001169 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 17:58:11.001263 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 17:58:11.001357 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 17:58:11.001451 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 17:58:11.001545 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 17:58:11.001639 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2997 17:58:11.001733 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2998 17:58:11.001828 Total UI for P1: 0, mck2ui 16
2999 17:58:11.001924 best dqsien dly found for B0: ( 0, 15, 16)
3000 17:58:11.002017 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3001 17:58:11.002152 Total UI for P1: 0, mck2ui 16
3002 17:58:11.002247 best dqsien dly found for B1: ( 0, 15, 18)
3003 17:58:11.002343 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3004 17:58:11.002438 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3005 17:58:11.002533
3006 17:58:11.002627 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3007 17:58:11.002722 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3008 17:58:11.002815 [Gating] SW calibration Done
3009 17:58:11.002909 ==
3010 17:58:11.003003 Dram Type= 6, Freq= 0, CH_1, rank 0
3011 17:58:11.003098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3012 17:58:11.003194 ==
3013 17:58:11.003288 RX Vref Scan: 0
3014 17:58:11.003381
3015 17:58:11.003474 RX Vref 0 -> 0, step: 1
3016 17:58:11.003569
3017 17:58:11.003662 RX Delay -40 -> 252, step: 8
3018 17:58:11.003755 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3019 17:58:11.003850 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3020 17:58:11.003945 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3021 17:58:11.004039 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3022 17:58:11.004163 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3023 17:58:11.004257 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3024 17:58:11.004351 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3025 17:58:11.004445 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3026 17:58:11.004539 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3027 17:58:11.004634 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3028 17:58:11.004728 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3029 17:58:11.004822 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3030 17:58:11.004915 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3031 17:58:11.005213 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3032 17:58:11.005318 iDelay=208, Bit 14, Center 111 (40 ~ 183) 144
3033 17:58:11.005416 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3034 17:58:11.005514 ==
3035 17:58:11.005611 Dram Type= 6, Freq= 0, CH_1, rank 0
3036 17:58:11.005708 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3037 17:58:11.005804 ==
3038 17:58:11.005898 DQS Delay:
3039 17:58:11.005992 DQS0 = 0, DQS1 = 0
3040 17:58:11.006129 DQM Delay:
3041 17:58:11.006224 DQM0 = 116, DQM1 = 108
3042 17:58:11.006318 DQ Delay:
3043 17:58:11.006412 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3044 17:58:11.006506 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3045 17:58:11.006600 DQ8 =87, DQ9 =99, DQ10 =111, DQ11 =99
3046 17:58:11.006695 DQ12 =119, DQ13 =119, DQ14 =111, DQ15 =119
3047 17:58:11.006790
3048 17:58:11.006886
3049 17:58:11.006960 ==
3050 17:58:11.007034 Dram Type= 6, Freq= 0, CH_1, rank 0
3051 17:58:11.007109 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3052 17:58:11.007183 ==
3053 17:58:11.007257
3054 17:58:11.007348
3055 17:58:11.007439 TX Vref Scan disable
3056 17:58:11.007531 == TX Byte 0 ==
3057 17:58:11.007622 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3058 17:58:11.007714 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3059 17:58:11.007805 == TX Byte 1 ==
3060 17:58:11.007896 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3061 17:58:11.007987 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3062 17:58:11.008077 ==
3063 17:58:11.008168 Dram Type= 6, Freq= 0, CH_1, rank 0
3064 17:58:11.008258 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3065 17:58:11.008348 ==
3066 17:58:11.008438 TX Vref=22, minBit 8, minWin=25, winSum=412
3067 17:58:11.008529 TX Vref=24, minBit 9, minWin=25, winSum=420
3068 17:58:11.008620 TX Vref=26, minBit 0, minWin=26, winSum=424
3069 17:58:11.008710 TX Vref=28, minBit 0, minWin=26, winSum=429
3070 17:58:11.008800 TX Vref=30, minBit 0, minWin=26, winSum=428
3071 17:58:11.008890 TX Vref=32, minBit 9, minWin=25, winSum=429
3072 17:58:11.008981 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
3073 17:58:11.009071
3074 17:58:11.009160 Final TX Range 1 Vref 28
3075 17:58:11.009250
3076 17:58:11.009340 ==
3077 17:58:11.009429 Dram Type= 6, Freq= 0, CH_1, rank 0
3078 17:58:11.009519 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3079 17:58:11.009609 ==
3080 17:58:11.009698
3081 17:58:11.009787
3082 17:58:11.009875 TX Vref Scan disable
3083 17:58:11.009965 == TX Byte 0 ==
3084 17:58:11.010083 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3085 17:58:11.010188 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3086 17:58:11.010279 == TX Byte 1 ==
3087 17:58:11.010369 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3088 17:58:11.010460 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3089 17:58:11.010550
3090 17:58:11.010639 [DATLAT]
3091 17:58:11.010729 Freq=1200, CH1 RK0
3092 17:58:11.010820
3093 17:58:11.010909 DATLAT Default: 0xd
3094 17:58:11.010998 0, 0xFFFF, sum = 0
3095 17:58:11.011091 1, 0xFFFF, sum = 0
3096 17:58:11.011183 2, 0xFFFF, sum = 0
3097 17:58:11.011275 3, 0xFFFF, sum = 0
3098 17:58:11.011367 4, 0xFFFF, sum = 0
3099 17:58:11.011457 5, 0xFFFF, sum = 0
3100 17:58:11.011549 6, 0xFFFF, sum = 0
3101 17:58:11.011640 7, 0xFFFF, sum = 0
3102 17:58:11.011732 8, 0xFFFF, sum = 0
3103 17:58:11.011824 9, 0xFFFF, sum = 0
3104 17:58:11.011915 10, 0xFFFF, sum = 0
3105 17:58:11.012007 11, 0x0, sum = 1
3106 17:58:11.012098 12, 0x0, sum = 2
3107 17:58:11.012190 13, 0x0, sum = 3
3108 17:58:11.012281 14, 0x0, sum = 4
3109 17:58:11.012372 best_step = 12
3110 17:58:11.012461
3111 17:58:11.012550 ==
3112 17:58:11.012639 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 17:58:11.012728 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3114 17:58:11.012818 ==
3115 17:58:11.012907 RX Vref Scan: 1
3116 17:58:11.012997
3117 17:58:11.013085 Set Vref Range= 32 -> 127
3118 17:58:11.013174
3119 17:58:11.013263 RX Vref 32 -> 127, step: 1
3120 17:58:11.013351
3121 17:58:11.013440 RX Delay -29 -> 252, step: 4
3122 17:58:11.013529
3123 17:58:11.013617 Set Vref, RX VrefLevel [Byte0]: 32
3124 17:58:11.013706 [Byte1]: 32
3125 17:58:11.013795
3126 17:58:11.013884 Set Vref, RX VrefLevel [Byte0]: 33
3127 17:58:11.013973 [Byte1]: 33
3128 17:58:11.014107
3129 17:58:11.014198 Set Vref, RX VrefLevel [Byte0]: 34
3130 17:58:11.014287 [Byte1]: 34
3131 17:58:11.014377
3132 17:58:11.014466 Set Vref, RX VrefLevel [Byte0]: 35
3133 17:58:11.014555 [Byte1]: 35
3134 17:58:11.014644
3135 17:58:11.014732 Set Vref, RX VrefLevel [Byte0]: 36
3136 17:58:11.014822 [Byte1]: 36
3137 17:58:11.014912
3138 17:58:11.015000 Set Vref, RX VrefLevel [Byte0]: 37
3139 17:58:11.015089 [Byte1]: 37
3140 17:58:11.015178
3141 17:58:11.015267 Set Vref, RX VrefLevel [Byte0]: 38
3142 17:58:11.015356 [Byte1]: 38
3143 17:58:11.015445
3144 17:58:11.015534 Set Vref, RX VrefLevel [Byte0]: 39
3145 17:58:11.015623 [Byte1]: 39
3146 17:58:11.015711
3147 17:58:11.015800 Set Vref, RX VrefLevel [Byte0]: 40
3148 17:58:11.015889 [Byte1]: 40
3149 17:58:11.015978
3150 17:58:11.016066 Set Vref, RX VrefLevel [Byte0]: 41
3151 17:58:11.016155 [Byte1]: 41
3152 17:58:11.016243
3153 17:58:11.016332 Set Vref, RX VrefLevel [Byte0]: 42
3154 17:58:11.016421 [Byte1]: 42
3155 17:58:11.016509
3156 17:58:11.016597 Set Vref, RX VrefLevel [Byte0]: 43
3157 17:58:11.016686 [Byte1]: 43
3158 17:58:11.016775
3159 17:58:11.016863 Set Vref, RX VrefLevel [Byte0]: 44
3160 17:58:11.016952 [Byte1]: 44
3161 17:58:11.017041
3162 17:58:11.017129 Set Vref, RX VrefLevel [Byte0]: 45
3163 17:58:11.017218 [Byte1]: 45
3164 17:58:11.017306
3165 17:58:11.017395 Set Vref, RX VrefLevel [Byte0]: 46
3166 17:58:11.017484 [Byte1]: 46
3167 17:58:11.017573
3168 17:58:11.017662 Set Vref, RX VrefLevel [Byte0]: 47
3169 17:58:11.017766 [Byte1]: 47
3170 17:58:11.017868
3171 17:58:11.017956 Set Vref, RX VrefLevel [Byte0]: 48
3172 17:58:11.018069 [Byte1]: 48
3173 17:58:11.018172
3174 17:58:11.018260 Set Vref, RX VrefLevel [Byte0]: 49
3175 17:58:11.018349 [Byte1]: 49
3176 17:58:11.018438
3177 17:58:11.018527 Set Vref, RX VrefLevel [Byte0]: 50
3178 17:58:11.018616 [Byte1]: 50
3179 17:58:11.018704
3180 17:58:11.018793 Set Vref, RX VrefLevel [Byte0]: 51
3181 17:58:11.018882 [Byte1]: 51
3182 17:58:11.018970
3183 17:58:11.019059 Set Vref, RX VrefLevel [Byte0]: 52
3184 17:58:11.019148 [Byte1]: 52
3185 17:58:11.019237
3186 17:58:11.019325 Set Vref, RX VrefLevel [Byte0]: 53
3187 17:58:11.019414 [Byte1]: 53
3188 17:58:11.019503
3189 17:58:11.019592 Set Vref, RX VrefLevel [Byte0]: 54
3190 17:58:11.019680 [Byte1]: 54
3191 17:58:11.019768
3192 17:58:11.019857 Set Vref, RX VrefLevel [Byte0]: 55
3193 17:58:11.019945 [Byte1]: 55
3194 17:58:11.020034
3195 17:58:11.020121 Set Vref, RX VrefLevel [Byte0]: 56
3196 17:58:11.020403 [Byte1]: 56
3197 17:58:11.020493
3198 17:58:11.020584 Set Vref, RX VrefLevel [Byte0]: 57
3199 17:58:11.020674 [Byte1]: 57
3200 17:58:11.020764
3201 17:58:11.020854 Set Vref, RX VrefLevel [Byte0]: 58
3202 17:58:11.020943 [Byte1]: 58
3203 17:58:11.021033
3204 17:58:11.021122 Set Vref, RX VrefLevel [Byte0]: 59
3205 17:58:11.021211 [Byte1]: 59
3206 17:58:11.021301
3207 17:58:11.021390 Set Vref, RX VrefLevel [Byte0]: 60
3208 17:58:11.021480 [Byte1]: 60
3209 17:58:11.021569
3210 17:58:11.021658 Set Vref, RX VrefLevel [Byte0]: 61
3211 17:58:11.021747 [Byte1]: 61
3212 17:58:11.021837
3213 17:58:11.021925 Set Vref, RX VrefLevel [Byte0]: 62
3214 17:58:11.022014 [Byte1]: 62
3215 17:58:11.022141
3216 17:58:11.022230 Set Vref, RX VrefLevel [Byte0]: 63
3217 17:58:11.022378 [Byte1]: 63
3218 17:58:11.022497
3219 17:58:11.022610 Set Vref, RX VrefLevel [Byte0]: 64
3220 17:58:11.022722 [Byte1]: 64
3221 17:58:11.022834
3222 17:58:11.022946 Set Vref, RX VrefLevel [Byte0]: 65
3223 17:58:11.023028 [Byte1]: 65
3224 17:58:11.023111
3225 17:58:11.023193 Set Vref, RX VrefLevel [Byte0]: 66
3226 17:58:11.023276 [Byte1]: 66
3227 17:58:11.023399
3228 17:58:11.023525 Final RX Vref Byte 0 = 51 to rank0
3229 17:58:11.023607 Final RX Vref Byte 1 = 50 to rank0
3230 17:58:11.023688 Final RX Vref Byte 0 = 51 to rank1
3231 17:58:11.023770 Final RX Vref Byte 1 = 50 to rank1==
3232 17:58:11.023851 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 17:58:11.023932 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3234 17:58:11.024013 ==
3235 17:58:11.024113 DQS Delay:
3236 17:58:11.024244 DQS0 = 0, DQS1 = 0
3237 17:58:11.024334 DQM Delay:
3238 17:58:11.024423 DQM0 = 115, DQM1 = 105
3239 17:58:11.024512 DQ Delay:
3240 17:58:11.024601 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3241 17:58:11.024690 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =114
3242 17:58:11.024779 DQ8 =86, DQ9 =94, DQ10 =110, DQ11 =96
3243 17:58:11.024868 DQ12 =112, DQ13 =116, DQ14 =114, DQ15 =112
3244 17:58:11.024957
3245 17:58:11.025046
3246 17:58:11.025135 [DQSOSCAuto] RK0, (LSB)MR18= 0x1818, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3247 17:58:11.025225 CH1 RK0: MR19=404, MR18=1818
3248 17:58:11.025315 CH1_RK0: MR19=0x404, MR18=0x1818, DQSOSC=400, MR23=63, INC=40, DEC=27
3249 17:58:11.025404
3250 17:58:11.025492 ----->DramcWriteLeveling(PI) begin...
3251 17:58:11.025583 ==
3252 17:58:11.025719 Dram Type= 6, Freq= 0, CH_1, rank 1
3253 17:58:11.025840 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3254 17:58:11.025934 ==
3255 17:58:11.026036 Write leveling (Byte 0): 20 => 20
3256 17:58:11.026123 Write leveling (Byte 1): 22 => 22
3257 17:58:11.026206 DramcWriteLeveling(PI) end<-----
3258 17:58:11.026289
3259 17:58:11.026383 ==
3260 17:58:11.026464 Dram Type= 6, Freq= 0, CH_1, rank 1
3261 17:58:11.026546 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3262 17:58:11.026626 ==
3263 17:58:11.026707 [Gating] SW mode calibration
3264 17:58:11.026789 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3265 17:58:11.026884 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3266 17:58:11.026968 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3267 17:58:11.027050 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3268 17:58:11.027132 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3269 17:58:11.027213 0 11 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
3270 17:58:11.027296 0 11 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
3271 17:58:11.027400 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3272 17:58:11.027472 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3273 17:58:11.027544 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3274 17:58:11.027616 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3275 17:58:11.027688 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3276 17:58:11.027760 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3277 17:58:11.027849 0 12 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
3278 17:58:11.027938 0 12 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
3279 17:58:11.028027 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3280 17:58:11.028116 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3281 17:58:11.028205 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3282 17:58:11.028294 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3283 17:58:11.028383 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3284 17:58:11.028477 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3285 17:58:11.028568 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3286 17:58:11.028667 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3287 17:58:11.028763 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3288 17:58:11.028844 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3289 17:58:11.028925 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3290 17:58:11.029006 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 17:58:11.029088 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 17:58:11.029169 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3293 17:58:11.029249 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3294 17:58:11.029330 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3295 17:58:11.029411 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3296 17:58:11.029492 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3297 17:58:11.029573 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3298 17:58:11.029653 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3299 17:58:11.029734 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3300 17:58:11.029814 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3301 17:58:11.029895 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3302 17:58:11.029975 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3303 17:58:11.030100 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3304 17:58:11.030181 Total UI for P1: 0, mck2ui 16
3305 17:58:11.030262 best dqsien dly found for B0: ( 0, 15, 14)
3306 17:58:11.030343 Total UI for P1: 0, mck2ui 16
3307 17:58:11.030424 best dqsien dly found for B1: ( 0, 15, 16)
3308 17:58:11.030504 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3309 17:58:11.030818 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3310 17:58:11.030942
3311 17:58:11.031023 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3312 17:58:11.031104 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3313 17:58:11.031185 [Gating] SW calibration Done
3314 17:58:11.031264 ==
3315 17:58:11.031345 Dram Type= 6, Freq= 0, CH_1, rank 1
3316 17:58:11.031426 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3317 17:58:11.031507 ==
3318 17:58:11.031587 RX Vref Scan: 0
3319 17:58:11.031666
3320 17:58:11.031774 RX Vref 0 -> 0, step: 1
3321 17:58:11.031856
3322 17:58:11.031909 RX Delay -40 -> 252, step: 8
3323 17:58:11.031960 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3324 17:58:11.032012 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3325 17:58:11.032064 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3326 17:58:11.032116 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3327 17:58:11.032167 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3328 17:58:11.032219 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3329 17:58:11.032270 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3330 17:58:11.032322 iDelay=200, Bit 7, Center 111 (32 ~ 191) 160
3331 17:58:11.032373 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3332 17:58:11.032425 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3333 17:58:11.032475 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3334 17:58:11.032526 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3335 17:58:11.032577 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3336 17:58:11.032652 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3337 17:58:11.032717 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3338 17:58:11.032768 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3339 17:58:11.032819 ==
3340 17:58:11.032870 Dram Type= 6, Freq= 0, CH_1, rank 1
3341 17:58:11.032921 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3342 17:58:11.032973 ==
3343 17:58:11.033025 DQS Delay:
3344 17:58:11.033076 DQS0 = 0, DQS1 = 0
3345 17:58:11.033127 DQM Delay:
3346 17:58:11.033177 DQM0 = 115, DQM1 = 105
3347 17:58:11.033229 DQ Delay:
3348 17:58:11.033279 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =111
3349 17:58:11.033330 DQ4 =119, DQ5 =123, DQ6 =123, DQ7 =111
3350 17:58:11.033381 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =103
3351 17:58:11.033432 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3352 17:58:11.033483
3353 17:58:11.033533
3354 17:58:11.033584 ==
3355 17:58:11.033635 Dram Type= 6, Freq= 0, CH_1, rank 1
3356 17:58:11.033686 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3357 17:58:11.033737 ==
3358 17:58:11.033788
3359 17:58:11.033839
3360 17:58:11.033889 TX Vref Scan disable
3361 17:58:11.033940 == TX Byte 0 ==
3362 17:58:11.033991 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3363 17:58:11.034069 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3364 17:58:11.034136 == TX Byte 1 ==
3365 17:58:11.034187 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3366 17:58:11.034255 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3367 17:58:11.034332 ==
3368 17:58:11.034398 Dram Type= 6, Freq= 0, CH_1, rank 1
3369 17:58:11.034450 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3370 17:58:11.034532 ==
3371 17:58:11.034586 TX Vref=22, minBit 9, minWin=25, winSum=422
3372 17:58:11.034668 TX Vref=24, minBit 9, minWin=25, winSum=420
3373 17:58:11.034720 TX Vref=26, minBit 8, minWin=26, winSum=429
3374 17:58:11.034772 TX Vref=28, minBit 8, minWin=26, winSum=432
3375 17:58:11.034826 TX Vref=30, minBit 8, minWin=26, winSum=431
3376 17:58:11.034895 TX Vref=32, minBit 3, minWin=26, winSum=431
3377 17:58:11.034960 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 28
3378 17:58:11.035011
3379 17:58:11.035062 Final TX Range 1 Vref 28
3380 17:58:11.035128
3381 17:58:11.035192 ==
3382 17:58:11.035243 Dram Type= 6, Freq= 0, CH_1, rank 1
3383 17:58:11.035294 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3384 17:58:11.035346 ==
3385 17:58:11.035396
3386 17:58:11.035477
3387 17:58:11.035528 TX Vref Scan disable
3388 17:58:11.035579 == TX Byte 0 ==
3389 17:58:11.035629 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3390 17:58:11.035681 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3391 17:58:11.035764 == TX Byte 1 ==
3392 17:58:11.035815 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3393 17:58:11.035867 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3394 17:58:11.035917
3395 17:58:11.035968 [DATLAT]
3396 17:58:11.036048 Freq=1200, CH1 RK1
3397 17:58:11.036100
3398 17:58:11.036150 DATLAT Default: 0xc
3399 17:58:11.036201 0, 0xFFFF, sum = 0
3400 17:58:11.036254 1, 0xFFFF, sum = 0
3401 17:58:11.036323 2, 0xFFFF, sum = 0
3402 17:58:11.036387 3, 0xFFFF, sum = 0
3403 17:58:11.036439 4, 0xFFFF, sum = 0
3404 17:58:11.036491 5, 0xFFFF, sum = 0
3405 17:58:11.036543 6, 0xFFFF, sum = 0
3406 17:58:11.036623 7, 0xFFFF, sum = 0
3407 17:58:11.036676 8, 0xFFFF, sum = 0
3408 17:58:11.036740 9, 0xFFFF, sum = 0
3409 17:58:11.036804 10, 0xFFFF, sum = 0
3410 17:58:11.036870 11, 0x0, sum = 1
3411 17:58:11.036937 12, 0x0, sum = 2
3412 17:58:11.036988 13, 0x0, sum = 3
3413 17:58:11.037041 14, 0x0, sum = 4
3414 17:58:11.037093 best_step = 12
3415 17:58:11.037144
3416 17:58:11.037195 ==
3417 17:58:11.037247 Dram Type= 6, Freq= 0, CH_1, rank 1
3418 17:58:11.037298 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3419 17:58:11.037349 ==
3420 17:58:11.037402 RX Vref Scan: 0
3421 17:58:11.037475
3422 17:58:11.037539 RX Vref 0 -> 0, step: 1
3423 17:58:11.037590
3424 17:58:11.037640 RX Delay -29 -> 252, step: 4
3425 17:58:11.037691 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3426 17:58:11.037742 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3427 17:58:11.037793 iDelay=195, Bit 2, Center 106 (35 ~ 178) 144
3428 17:58:11.037844 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
3429 17:58:11.037895 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3430 17:58:11.037946 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3431 17:58:11.037996 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3432 17:58:11.038102 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3433 17:58:11.038156 iDelay=195, Bit 8, Center 86 (19 ~ 154) 136
3434 17:58:11.038207 iDelay=195, Bit 9, Center 90 (23 ~ 158) 136
3435 17:58:11.038258 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3436 17:58:11.038310 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3437 17:58:11.038361 iDelay=195, Bit 12, Center 112 (43 ~ 182) 140
3438 17:58:11.038412 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3439 17:58:11.038463 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3440 17:58:11.038514 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3441 17:58:11.038565 ==
3442 17:58:11.038616 Dram Type= 6, Freq= 0, CH_1, rank 1
3443 17:58:11.038667 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3444 17:58:11.038718 ==
3445 17:58:11.038769 DQS Delay:
3446 17:58:11.038821 DQS0 = 0, DQS1 = 0
3447 17:58:11.038872 DQM Delay:
3448 17:58:11.038942 DQM0 = 114, DQM1 = 103
3449 17:58:11.039000 DQ Delay:
3450 17:58:11.039052 DQ0 =114, DQ1 =110, DQ2 =106, DQ3 =110
3451 17:58:11.039103 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3452 17:58:11.039346 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =96
3453 17:58:11.039405 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =112
3454 17:58:11.039458
3455 17:58:11.039509
3456 17:58:11.039560 [DQSOSCAuto] RK1, (LSB)MR18= 0xb0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3457 17:58:11.039612 CH1 RK1: MR19=404, MR18=B0B
3458 17:58:11.039663 CH1_RK1: MR19=0x404, MR18=0xB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
3459 17:58:11.039715 [RxdqsGatingPostProcess] freq 1200
3460 17:58:11.039766 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3461 17:58:11.039817 Pre-setting of DQS Precalculation
3462 17:58:11.039869 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3463 17:58:11.039920 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3464 17:58:11.039977 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3465 17:58:11.040055
3466 17:58:11.040108
3467 17:58:11.040159 [Calibration Summary] 2400 Mbps
3468 17:58:11.040211 CH 0, Rank 0
3469 17:58:11.040263 SW Impedance : PASS
3470 17:58:11.040314 DUTY Scan : NO K
3471 17:58:11.040365 ZQ Calibration : PASS
3472 17:58:11.040416 Jitter Meter : NO K
3473 17:58:11.040467 CBT Training : PASS
3474 17:58:11.040518 Write leveling : PASS
3475 17:58:11.040569 RX DQS gating : PASS
3476 17:58:11.040620 RX DQ/DQS(RDDQC) : PASS
3477 17:58:11.040670 TX DQ/DQS : PASS
3478 17:58:11.040722 RX DATLAT : PASS
3479 17:58:11.040773 RX DQ/DQS(Engine): PASS
3480 17:58:11.040824 TX OE : NO K
3481 17:58:11.040875 All Pass.
3482 17:58:11.040926
3483 17:58:11.040977 CH 0, Rank 1
3484 17:58:11.041027 SW Impedance : PASS
3485 17:58:11.041078 DUTY Scan : NO K
3486 17:58:11.041129 ZQ Calibration : PASS
3487 17:58:11.041179 Jitter Meter : NO K
3488 17:58:11.041230 CBT Training : PASS
3489 17:58:11.041281 Write leveling : PASS
3490 17:58:11.041331 RX DQS gating : PASS
3491 17:58:11.041382 RX DQ/DQS(RDDQC) : PASS
3492 17:58:11.041432 TX DQ/DQS : PASS
3493 17:58:11.041484 RX DATLAT : PASS
3494 17:58:11.041534 RX DQ/DQS(Engine): PASS
3495 17:58:11.041585 TX OE : NO K
3496 17:58:11.041636 All Pass.
3497 17:58:11.041686
3498 17:58:11.041737 CH 1, Rank 0
3499 17:58:11.041787 SW Impedance : PASS
3500 17:58:11.041837 DUTY Scan : NO K
3501 17:58:11.041888 ZQ Calibration : PASS
3502 17:58:11.041938 Jitter Meter : NO K
3503 17:58:11.041989 CBT Training : PASS
3504 17:58:11.042091 Write leveling : PASS
3505 17:58:11.042147 RX DQS gating : PASS
3506 17:58:11.042198 RX DQ/DQS(RDDQC) : PASS
3507 17:58:11.042250 TX DQ/DQS : PASS
3508 17:58:11.042301 RX DATLAT : PASS
3509 17:58:11.042352 RX DQ/DQS(Engine): PASS
3510 17:58:11.042403 TX OE : NO K
3511 17:58:11.042454 All Pass.
3512 17:58:11.042505
3513 17:58:11.042555 CH 1, Rank 1
3514 17:58:11.042606 SW Impedance : PASS
3515 17:58:11.042658 DUTY Scan : NO K
3516 17:58:11.042709 ZQ Calibration : PASS
3517 17:58:11.042760 Jitter Meter : NO K
3518 17:58:11.042811 CBT Training : PASS
3519 17:58:11.042862 Write leveling : PASS
3520 17:58:11.042914 RX DQS gating : PASS
3521 17:58:11.042965 RX DQ/DQS(RDDQC) : PASS
3522 17:58:11.043016 TX DQ/DQS : PASS
3523 17:58:11.043067 RX DATLAT : PASS
3524 17:58:11.043117 RX DQ/DQS(Engine): PASS
3525 17:58:11.043168 TX OE : NO K
3526 17:58:11.043219 All Pass.
3527 17:58:11.043270
3528 17:58:11.043320 DramC Write-DBI off
3529 17:58:11.043371 PER_BANK_REFRESH: Hybrid Mode
3530 17:58:11.043423 TX_TRACKING: ON
3531 17:58:11.043474 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3532 17:58:11.043526 [FAST_K] Save calibration result to emmc
3533 17:58:11.043577 dramc_set_vcore_voltage set vcore to 650000
3534 17:58:11.043628 Read voltage for 600, 5
3535 17:58:11.043679 Vio18 = 0
3536 17:58:11.043730 Vcore = 650000
3537 17:58:11.043781 Vdram = 0
3538 17:58:11.043831 Vddq = 0
3539 17:58:11.043882 Vmddr = 0
3540 17:58:11.043933 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3541 17:58:11.044001 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3542 17:58:11.044065 MEM_TYPE=3, freq_sel=19
3543 17:58:11.044116 sv_algorithm_assistance_LP4_1600
3544 17:58:11.044166 ============ PULL DRAM RESETB DOWN ============
3545 17:58:11.044218 ========== PULL DRAM RESETB DOWN end =========
3546 17:58:11.044269 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3547 17:58:11.044321 ===================================
3548 17:58:11.044372 LPDDR4 DRAM CONFIGURATION
3549 17:58:11.044423 ===================================
3550 17:58:11.044474 EX_ROW_EN[0] = 0x0
3551 17:58:11.044525 EX_ROW_EN[1] = 0x0
3552 17:58:11.044575 LP4Y_EN = 0x0
3553 17:58:11.044625 WORK_FSP = 0x0
3554 17:58:11.044676 WL = 0x2
3555 17:58:11.044726 RL = 0x2
3556 17:58:11.044777 BL = 0x2
3557 17:58:11.044827 RPST = 0x0
3558 17:58:11.044878 RD_PRE = 0x0
3559 17:58:11.044928 WR_PRE = 0x1
3560 17:58:11.044979 WR_PST = 0x0
3561 17:58:11.045029 DBI_WR = 0x0
3562 17:58:11.045080 DBI_RD = 0x0
3563 17:58:11.045130 OTF = 0x1
3564 17:58:11.045181 ===================================
3565 17:58:11.045233 ===================================
3566 17:58:11.045283 ANA top config
3567 17:58:11.045334 ===================================
3568 17:58:11.045385 DLL_ASYNC_EN = 0
3569 17:58:11.045436 ALL_SLAVE_EN = 1
3570 17:58:11.045486 NEW_RANK_MODE = 1
3571 17:58:11.045538 DLL_IDLE_MODE = 1
3572 17:58:11.045588 LP45_APHY_COMB_EN = 1
3573 17:58:11.045639 TX_ODT_DIS = 1
3574 17:58:11.045690 NEW_8X_MODE = 1
3575 17:58:11.045741 ===================================
3576 17:58:11.045792 ===================================
3577 17:58:11.045844 data_rate = 1200
3578 17:58:11.045894 CKR = 1
3579 17:58:11.045945 DQ_P2S_RATIO = 8
3580 17:58:11.045995 ===================================
3581 17:58:11.046092 CA_P2S_RATIO = 8
3582 17:58:11.046145 DQ_CA_OPEN = 0
3583 17:58:11.046195 DQ_SEMI_OPEN = 0
3584 17:58:11.046246 CA_SEMI_OPEN = 0
3585 17:58:11.046297 CA_FULL_RATE = 0
3586 17:58:11.046348 DQ_CKDIV4_EN = 1
3587 17:58:11.046400 CA_CKDIV4_EN = 1
3588 17:58:11.046451 CA_PREDIV_EN = 0
3589 17:58:11.046502 PH8_DLY = 0
3590 17:58:11.046552 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3591 17:58:11.046603 DQ_AAMCK_DIV = 4
3592 17:58:11.046653 CA_AAMCK_DIV = 4
3593 17:58:11.046704 CA_ADMCK_DIV = 4
3594 17:58:11.046755 DQ_TRACK_CA_EN = 0
3595 17:58:11.046806 CA_PICK = 600
3596 17:58:11.047043 CA_MCKIO = 600
3597 17:58:11.047100 MCKIO_SEMI = 0
3598 17:58:11.047152 PLL_FREQ = 2288
3599 17:58:11.047203 DQ_UI_PI_RATIO = 32
3600 17:58:11.047254 CA_UI_PI_RATIO = 0
3601 17:58:11.047316 ===================================
3602 17:58:11.050668 ===================================
3603 17:58:11.050748 memory_type:LPDDR4
3604 17:58:11.053827 GP_NUM : 10
3605 17:58:11.057427 SRAM_EN : 1
3606 17:58:11.057532 MD32_EN : 0
3607 17:58:11.060565 ===================================
3608 17:58:11.063757 [ANA_INIT] >>>>>>>>>>>>>>
3609 17:58:11.067583 <<<<<< [CONFIGURE PHASE]: ANA_TX
3610 17:58:11.070609 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3611 17:58:11.073798 ===================================
3612 17:58:11.076931 data_rate = 1200,PCW = 0X5800
3613 17:58:11.080549 ===================================
3614 17:58:11.083594 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3615 17:58:11.087413 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3616 17:58:11.093825 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3617 17:58:11.096923 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3618 17:58:11.100417 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3619 17:58:11.104012 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3620 17:58:11.106909 [ANA_INIT] flow start
3621 17:58:11.110184 [ANA_INIT] PLL >>>>>>>>
3622 17:58:11.110264 [ANA_INIT] PLL <<<<<<<<
3623 17:58:11.113930 [ANA_INIT] MIDPI >>>>>>>>
3624 17:58:11.117106 [ANA_INIT] MIDPI <<<<<<<<
3625 17:58:11.117185 [ANA_INIT] DLL >>>>>>>>
3626 17:58:11.120366 [ANA_INIT] flow end
3627 17:58:11.123539 ============ LP4 DIFF to SE enter ============
3628 17:58:11.130113 ============ LP4 DIFF to SE exit ============
3629 17:58:11.130194 [ANA_INIT] <<<<<<<<<<<<<
3630 17:58:11.133788 [Flow] Enable top DCM control >>>>>
3631 17:58:11.137000 [Flow] Enable top DCM control <<<<<
3632 17:58:11.140232 Enable DLL master slave shuffle
3633 17:58:11.146563 ==============================================================
3634 17:58:11.146648 Gating Mode config
3635 17:58:11.153800 ==============================================================
3636 17:58:11.156821 Config description:
3637 17:58:11.163622 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3638 17:58:11.170074 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3639 17:58:11.176523 SELPH_MODE 0: By rank 1: By Phase
3640 17:58:11.183515 ==============================================================
3641 17:58:11.183621 GAT_TRACK_EN = 1
3642 17:58:11.186670 RX_GATING_MODE = 2
3643 17:58:11.189778 RX_GATING_TRACK_MODE = 2
3644 17:58:11.193427 SELPH_MODE = 1
3645 17:58:11.196512 PICG_EARLY_EN = 1
3646 17:58:11.199619 VALID_LAT_VALUE = 1
3647 17:58:11.206636 ==============================================================
3648 17:58:11.209833 Enter into Gating configuration >>>>
3649 17:58:11.212991 Exit from Gating configuration <<<<
3650 17:58:11.216593 Enter into DVFS_PRE_config >>>>>
3651 17:58:11.226316 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3652 17:58:11.229479 Exit from DVFS_PRE_config <<<<<
3653 17:58:11.232665 Enter into PICG configuration >>>>
3654 17:58:11.236428 Exit from PICG configuration <<<<
3655 17:58:11.239425 [RX_INPUT] configuration >>>>>
3656 17:58:11.242707 [RX_INPUT] configuration <<<<<
3657 17:58:11.245916 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3658 17:58:11.252932 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3659 17:58:11.259373 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3660 17:58:11.262524 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3661 17:58:11.269264 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3662 17:58:11.276058 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3663 17:58:11.279056 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3664 17:58:11.285750 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3665 17:58:11.289028 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3666 17:58:11.292358 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3667 17:58:11.295594 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3668 17:58:11.302394 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3669 17:58:11.305524 ===================================
3670 17:58:11.305600 LPDDR4 DRAM CONFIGURATION
3671 17:58:11.308752 ===================================
3672 17:58:11.311970 EX_ROW_EN[0] = 0x0
3673 17:58:11.315772 EX_ROW_EN[1] = 0x0
3674 17:58:11.315871 LP4Y_EN = 0x0
3675 17:58:11.318945 WORK_FSP = 0x0
3676 17:58:11.319019 WL = 0x2
3677 17:58:11.322146 RL = 0x2
3678 17:58:11.322242 BL = 0x2
3679 17:58:11.325233 RPST = 0x0
3680 17:58:11.325300 RD_PRE = 0x0
3681 17:58:11.328963 WR_PRE = 0x1
3682 17:58:11.329057 WR_PST = 0x0
3683 17:58:11.332015 DBI_WR = 0x0
3684 17:58:11.332087 DBI_RD = 0x0
3685 17:58:11.335164 OTF = 0x1
3686 17:58:11.338314 ===================================
3687 17:58:11.342103 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3688 17:58:11.345361 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3689 17:58:11.351626 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3690 17:58:11.354808 ===================================
3691 17:58:11.354878 LPDDR4 DRAM CONFIGURATION
3692 17:58:11.358685 ===================================
3693 17:58:11.361986 EX_ROW_EN[0] = 0x10
3694 17:58:11.364987 EX_ROW_EN[1] = 0x0
3695 17:58:11.365081 LP4Y_EN = 0x0
3696 17:58:11.368200 WORK_FSP = 0x0
3697 17:58:11.368296 WL = 0x2
3698 17:58:11.371364 RL = 0x2
3699 17:58:11.371460 BL = 0x2
3700 17:58:11.375138 RPST = 0x0
3701 17:58:11.375238 RD_PRE = 0x0
3702 17:58:11.378287 WR_PRE = 0x1
3703 17:58:11.378382 WR_PST = 0x0
3704 17:58:11.381357 DBI_WR = 0x0
3705 17:58:11.381425 DBI_RD = 0x0
3706 17:58:11.384760 OTF = 0x1
3707 17:58:11.387807 ===================================
3708 17:58:11.394755 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3709 17:58:11.397843 nWR fixed to 30
3710 17:58:11.401122 [ModeRegInit_LP4] CH0 RK0
3711 17:58:11.401218 [ModeRegInit_LP4] CH0 RK1
3712 17:58:11.404865 [ModeRegInit_LP4] CH1 RK0
3713 17:58:11.407952 [ModeRegInit_LP4] CH1 RK1
3714 17:58:11.408047 match AC timing 16
3715 17:58:11.414643 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3716 17:58:11.417759 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3717 17:58:11.421446 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3718 17:58:11.428146 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3719 17:58:11.431283 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3720 17:58:11.431374 ==
3721 17:58:11.434404 Dram Type= 6, Freq= 0, CH_0, rank 0
3722 17:58:11.438176 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3723 17:58:11.438286 ==
3724 17:58:11.444761 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3725 17:58:11.450880 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3726 17:58:11.454250 [CA 0] Center 35 (5~66) winsize 62
3727 17:58:11.457568 [CA 1] Center 35 (5~66) winsize 62
3728 17:58:11.460744 [CA 2] Center 34 (4~65) winsize 62
3729 17:58:11.464527 [CA 3] Center 34 (3~65) winsize 63
3730 17:58:11.467766 [CA 4] Center 33 (3~64) winsize 62
3731 17:58:11.471042 [CA 5] Center 33 (3~64) winsize 62
3732 17:58:11.471277
3733 17:58:11.474285 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3734 17:58:11.474579
3735 17:58:11.477608 [CATrainingPosCal] consider 1 rank data
3736 17:58:11.481083 u2DelayCellTimex100 = 270/100 ps
3737 17:58:11.484779 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3738 17:58:11.487669 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3739 17:58:11.491319 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3740 17:58:11.494201 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3741 17:58:11.497814 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3742 17:58:11.504212 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3743 17:58:11.504664
3744 17:58:11.507843 CA PerBit enable=1, Macro0, CA PI delay=33
3745 17:58:11.508299
3746 17:58:11.511118 [CBTSetCACLKResult] CA Dly = 33
3747 17:58:11.511574 CS Dly: 5 (0~36)
3748 17:58:11.511928 ==
3749 17:58:11.514270 Dram Type= 6, Freq= 0, CH_0, rank 1
3750 17:58:11.520457 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3751 17:58:11.520869 ==
3752 17:58:11.524099 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3753 17:58:11.530953 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3754 17:58:11.534067 [CA 0] Center 36 (6~66) winsize 61
3755 17:58:11.537096 [CA 1] Center 35 (5~66) winsize 62
3756 17:58:11.540681 [CA 2] Center 34 (4~65) winsize 62
3757 17:58:11.543728 [CA 3] Center 34 (4~65) winsize 62
3758 17:58:11.547410 [CA 4] Center 33 (3~64) winsize 62
3759 17:58:11.550460 [CA 5] Center 33 (3~64) winsize 62
3760 17:58:11.550912
3761 17:58:11.553596 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3762 17:58:11.554109
3763 17:58:11.556954 [CATrainingPosCal] consider 2 rank data
3764 17:58:11.560567 u2DelayCellTimex100 = 270/100 ps
3765 17:58:11.563699 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3766 17:58:11.566830 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3767 17:58:11.570199 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3768 17:58:11.577352 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3769 17:58:11.580585 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3770 17:58:11.583698 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3771 17:58:11.584130
3772 17:58:11.586924 CA PerBit enable=1, Macro0, CA PI delay=33
3773 17:58:11.587613
3774 17:58:11.589997 [CBTSetCACLKResult] CA Dly = 33
3775 17:58:11.590463 CS Dly: 5 (0~37)
3776 17:58:11.590825
3777 17:58:11.593834 ----->DramcWriteLeveling(PI) begin...
3778 17:58:11.596828 ==
3779 17:58:11.597236 Dram Type= 6, Freq= 0, CH_0, rank 0
3780 17:58:11.603315 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3781 17:58:11.603903 ==
3782 17:58:11.606580 Write leveling (Byte 0): 31 => 31
3783 17:58:11.610315 Write leveling (Byte 1): 31 => 31
3784 17:58:11.613352 DramcWriteLeveling(PI) end<-----
3785 17:58:11.613874
3786 17:58:11.614329 ==
3787 17:58:11.616709 Dram Type= 6, Freq= 0, CH_0, rank 0
3788 17:58:11.620096 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3789 17:58:11.620520 ==
3790 17:58:11.623362 [Gating] SW mode calibration
3791 17:58:11.629782 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3792 17:58:11.636681 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3793 17:58:11.639780 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3794 17:58:11.642961 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3795 17:58:11.646716 0 5 8 | B1->B0 | 3232 3232 | 0 0 | (0 1) (0 0)
3796 17:58:11.653683 0 5 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3797 17:58:11.656490 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3798 17:58:11.659761 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3799 17:58:11.666269 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3800 17:58:11.669474 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3801 17:58:11.673267 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3802 17:58:11.679715 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3803 17:58:11.682834 0 6 8 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
3804 17:58:11.686105 0 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3805 17:58:11.692490 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3806 17:58:11.695702 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3807 17:58:11.699621 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3808 17:58:11.705900 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3809 17:58:11.709482 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3810 17:58:11.712499 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3811 17:58:11.719077 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3812 17:58:11.722227 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3813 17:58:11.726043 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3814 17:58:11.732208 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 17:58:11.735326 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 17:58:11.739253 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 17:58:11.745504 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 17:58:11.748375 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 17:58:11.755291 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 17:58:11.758881 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 17:58:11.761712 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 17:58:11.765013 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 17:58:11.772062 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3824 17:58:11.775274 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3825 17:58:11.778412 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3826 17:58:11.784949 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3827 17:58:11.788425 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3828 17:58:11.791868 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3829 17:58:11.795211 Total UI for P1: 0, mck2ui 16
3830 17:58:11.798649 best dqsien dly found for B0: ( 0, 9, 8)
3831 17:58:11.805335 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3832 17:58:11.808172 Total UI for P1: 0, mck2ui 16
3833 17:58:11.811358 best dqsien dly found for B1: ( 0, 9, 12)
3834 17:58:11.815026 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3835 17:58:11.818132 best DQS1 dly(MCK, UI, PI) = (0, 9, 12)
3836 17:58:11.818592
3837 17:58:11.821683 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3838 17:58:11.824840 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 12)
3839 17:58:11.828074 [Gating] SW calibration Done
3840 17:58:11.828528 ==
3841 17:58:11.831209 Dram Type= 6, Freq= 0, CH_0, rank 0
3842 17:58:11.835103 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3843 17:58:11.835519 ==
3844 17:58:11.838181 RX Vref Scan: 0
3845 17:58:11.838602
3846 17:58:11.841289 RX Vref 0 -> 0, step: 1
3847 17:58:11.841916
3848 17:58:11.842311 RX Delay -230 -> 252, step: 16
3849 17:58:11.847529 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3850 17:58:11.850747 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3851 17:58:11.854490 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3852 17:58:11.858009 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3853 17:58:11.864121 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3854 17:58:11.867555 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3855 17:58:11.870909 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3856 17:58:11.874137 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3857 17:58:11.880572 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3858 17:58:11.884486 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3859 17:58:11.887622 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3860 17:58:11.890883 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3861 17:58:11.897288 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3862 17:58:11.900368 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3863 17:58:11.903721 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3864 17:58:11.906742 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3865 17:58:11.907161 ==
3866 17:58:11.910720 Dram Type= 6, Freq= 0, CH_0, rank 0
3867 17:58:11.917301 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3868 17:58:11.917849 ==
3869 17:58:11.918238 DQS Delay:
3870 17:58:11.920371 DQS0 = 0, DQS1 = 0
3871 17:58:11.920825 DQM Delay:
3872 17:58:11.921156 DQM0 = 38, DQM1 = 33
3873 17:58:11.923580 DQ Delay:
3874 17:58:11.927262 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3875 17:58:11.930180 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3876 17:58:11.933448 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3877 17:58:11.936600 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3878 17:58:11.937141
3879 17:58:11.937528
3880 17:58:11.937827 ==
3881 17:58:11.939976 Dram Type= 6, Freq= 0, CH_0, rank 0
3882 17:58:11.943258 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3883 17:58:11.943720 ==
3884 17:58:11.944212
3885 17:58:11.944533
3886 17:58:11.947010 TX Vref Scan disable
3887 17:58:11.949977 == TX Byte 0 ==
3888 17:58:11.953675 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3889 17:58:11.956945 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3890 17:58:11.960034 == TX Byte 1 ==
3891 17:58:11.963397 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3892 17:58:11.966684 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3893 17:58:11.967163 ==
3894 17:58:11.969937 Dram Type= 6, Freq= 0, CH_0, rank 0
3895 17:58:11.973553 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3896 17:58:11.973968 ==
3897 17:58:11.976499
3898 17:58:11.976930
3899 17:58:11.977255 TX Vref Scan disable
3900 17:58:11.980065 == TX Byte 0 ==
3901 17:58:11.983635 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3902 17:58:11.990123 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3903 17:58:11.990538 == TX Byte 1 ==
3904 17:58:11.993306 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3905 17:58:11.999728 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3906 17:58:12.000486
3907 17:58:12.001028 [DATLAT]
3908 17:58:12.001544 Freq=600, CH0 RK0
3909 17:58:12.002099
3910 17:58:12.003492 DATLAT Default: 0x9
3911 17:58:12.004025 0, 0xFFFF, sum = 0
3912 17:58:12.006840 1, 0xFFFF, sum = 0
3913 17:58:12.009951 2, 0xFFFF, sum = 0
3914 17:58:12.010402 3, 0xFFFF, sum = 0
3915 17:58:12.013397 4, 0xFFFF, sum = 0
3916 17:58:12.013917 5, 0xFFFF, sum = 0
3917 17:58:12.016860 6, 0xFFFF, sum = 0
3918 17:58:12.017275 7, 0x0, sum = 1
3919 17:58:12.017600 8, 0x0, sum = 2
3920 17:58:12.020224 9, 0x0, sum = 3
3921 17:58:12.020694 10, 0x0, sum = 4
3922 17:58:12.245454 best_step = 8
3923 17:58:12.245954
3924 17:58:12.246375 ==
3925 17:58:12.246714 Dram Type= 6, Freq= 0, CH_0, rank 0
3926 17:58:12.247039 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3927 17:58:12.247427 ==
3928 17:58:12.247749 RX Vref Scan: 1
3929 17:58:12.248054
3930 17:58:12.248354 RX Vref 0 -> 0, step: 1
3931 17:58:12.248657
3932 17:58:12.248958 RX Delay -195 -> 252, step: 8
3933 17:58:12.249256
3934 17:58:12.249577 Set Vref, RX VrefLevel [Byte0]: 51
3935 17:58:12.249879 [Byte1]: 48
3936 17:58:12.250303
3937 17:58:12.250610 Final RX Vref Byte 0 = 51 to rank0
3938 17:58:12.250911 Final RX Vref Byte 1 = 48 to rank0
3939 17:58:12.251204 Final RX Vref Byte 0 = 51 to rank1
3940 17:58:12.251651 Final RX Vref Byte 1 = 48 to rank1==
3941 17:58:12.251989 Dram Type= 6, Freq= 0, CH_0, rank 0
3942 17:58:12.252265 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3943 17:58:12.252539 ==
3944 17:58:12.252807 DQS Delay:
3945 17:58:12.253075 DQS0 = 0, DQS1 = 0
3946 17:58:12.253340 DQM Delay:
3947 17:58:12.253608 DQM0 = 40, DQM1 = 29
3948 17:58:12.253874 DQ Delay:
3949 17:58:12.254249 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =40
3950 17:58:12.254532 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
3951 17:58:12.254800 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
3952 17:58:12.255069 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
3953 17:58:12.255340
3954 17:58:12.255603
3955 17:58:12.255940 [DQSOSCAuto] RK0, (LSB)MR18= 0x5151, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
3956 17:58:12.256230 CH0 RK0: MR19=808, MR18=5151
3957 17:58:12.256501 CH0_RK0: MR19=0x808, MR18=0x5151, DQSOSC=394, MR23=63, INC=168, DEC=112
3958 17:58:12.256772
3959 17:58:12.257035 ----->DramcWriteLeveling(PI) begin...
3960 17:58:12.257309 ==
3961 17:58:12.257576 Dram Type= 6, Freq= 0, CH_0, rank 1
3962 17:58:12.257846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3963 17:58:12.258173 ==
3964 17:58:12.258455 Write leveling (Byte 0): 31 => 31
3965 17:58:12.258723 Write leveling (Byte 1): 29 => 29
3966 17:58:12.259082 DramcWriteLeveling(PI) end<-----
3967 17:58:12.259355
3968 17:58:12.259620 ==
3969 17:58:12.259885 Dram Type= 6, Freq= 0, CH_0, rank 1
3970 17:58:12.260154 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3971 17:58:12.260421 ==
3972 17:58:12.260687 [Gating] SW mode calibration
3973 17:58:12.260957 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3974 17:58:12.261226 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3975 17:58:12.261496 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 17:58:12.261765 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3977 17:58:12.262054 0 5 8 | B1->B0 | 3333 3333 | 1 1 | (1 0) (1 0)
3978 17:58:12.262330 0 5 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3979 17:58:12.262677 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 17:58:12.262969 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 17:58:12.263161 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 17:58:12.263352 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 17:58:12.263543 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 17:58:12.263734 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 17:58:12.263926 0 6 8 | B1->B0 | 2e2e 3232 | 0 0 | (0 0) (0 0)
3986 17:58:12.264117 0 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3987 17:58:12.264307 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 17:58:12.264498 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 17:58:12.264687 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 17:58:12.264877 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 17:58:12.265067 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 17:58:12.265256 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 17:58:12.265448 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3994 17:58:12.265639 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 17:58:12.265831 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 17:58:12.266046 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 17:58:12.266309 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 17:58:12.266516 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 17:58:12.266710 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 17:58:12.266901 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 17:58:12.267094 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 17:58:12.268246 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 17:58:12.275061 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 17:58:12.278575 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 17:58:12.281781 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 17:58:12.288510 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 17:58:12.291728 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 17:58:12.295070 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 17:58:12.301551 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4010 17:58:12.305287 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4011 17:58:12.308312 Total UI for P1: 0, mck2ui 16
4012 17:58:12.311656 best dqsien dly found for B0: ( 0, 9, 10)
4013 17:58:12.314921 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 17:58:12.318158 Total UI for P1: 0, mck2ui 16
4015 17:58:12.321693 best dqsien dly found for B1: ( 0, 9, 10)
4016 17:58:12.324990 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
4017 17:58:12.328255 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4018 17:58:12.328661
4019 17:58:12.331812 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
4020 17:58:12.337886 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4021 17:58:12.338391 [Gating] SW calibration Done
4022 17:58:12.341797 ==
4023 17:58:12.345012 Dram Type= 6, Freq= 0, CH_0, rank 1
4024 17:58:12.347979 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4025 17:58:12.348618 ==
4026 17:58:12.349231 RX Vref Scan: 0
4027 17:58:12.349808
4028 17:58:12.351228 RX Vref 0 -> 0, step: 1
4029 17:58:12.351843
4030 17:58:12.354389 RX Delay -230 -> 252, step: 16
4031 17:58:12.358156 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4032 17:58:12.361371 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4033 17:58:12.367888 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4034 17:58:12.371136 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4035 17:58:12.374403 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4036 17:58:12.377689 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4037 17:58:12.384405 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4038 17:58:12.387402 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4039 17:58:12.390612 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4040 17:58:12.393800 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4041 17:58:12.397685 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4042 17:58:12.403962 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4043 17:58:12.407329 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4044 17:58:12.410407 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4045 17:58:12.414127 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4046 17:58:12.420360 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4047 17:58:12.420783 ==
4048 17:58:12.423784 Dram Type= 6, Freq= 0, CH_0, rank 1
4049 17:58:12.427342 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4050 17:58:12.427902 ==
4051 17:58:12.428346 DQS Delay:
4052 17:58:12.430814 DQS0 = 0, DQS1 = 0
4053 17:58:12.431224 DQM Delay:
4054 17:58:12.433597 DQM0 = 40, DQM1 = 31
4055 17:58:12.434011 DQ Delay:
4056 17:58:12.437437 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4057 17:58:12.440495 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4058 17:58:12.443715 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4059 17:58:12.446704 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4060 17:58:12.447120
4061 17:58:12.447443
4062 17:58:12.447744 ==
4063 17:58:12.450535 Dram Type= 6, Freq= 0, CH_0, rank 1
4064 17:58:12.453743 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4065 17:58:12.456726 ==
4066 17:58:12.457020
4067 17:58:12.457250
4068 17:58:12.457469 TX Vref Scan disable
4069 17:58:12.459908 == TX Byte 0 ==
4070 17:58:12.463013 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4071 17:58:12.467077 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4072 17:58:12.470400 == TX Byte 1 ==
4073 17:58:12.473597 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4074 17:58:12.476843 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4075 17:58:12.479897 ==
4076 17:58:12.483844 Dram Type= 6, Freq= 0, CH_0, rank 1
4077 17:58:12.486757 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4078 17:58:12.487055 ==
4079 17:58:12.487243
4080 17:58:12.487413
4081 17:58:12.489878 TX Vref Scan disable
4082 17:58:12.490129 == TX Byte 0 ==
4083 17:58:12.496415 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4084 17:58:12.499675 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4085 17:58:12.503133 == TX Byte 1 ==
4086 17:58:12.506333 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4087 17:58:12.510073 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4088 17:58:12.510492
4089 17:58:12.510827 [DATLAT]
4090 17:58:12.513123 Freq=600, CH0 RK1
4091 17:58:12.513535
4092 17:58:12.513859 DATLAT Default: 0x8
4093 17:58:12.516338 0, 0xFFFF, sum = 0
4094 17:58:12.519626 1, 0xFFFF, sum = 0
4095 17:58:12.520045 2, 0xFFFF, sum = 0
4096 17:58:12.522847 3, 0xFFFF, sum = 0
4097 17:58:12.523272 4, 0xFFFF, sum = 0
4098 17:58:12.526597 5, 0xFFFF, sum = 0
4099 17:58:12.527061 6, 0xFFFF, sum = 0
4100 17:58:12.529785 7, 0x0, sum = 1
4101 17:58:12.530290 8, 0x0, sum = 2
4102 17:58:12.530751 9, 0x0, sum = 3
4103 17:58:12.532849 10, 0x0, sum = 4
4104 17:58:12.533283 best_step = 8
4105 17:58:12.533641
4106 17:58:12.533950 ==
4107 17:58:12.536365 Dram Type= 6, Freq= 0, CH_0, rank 1
4108 17:58:12.543044 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4109 17:58:12.543476 ==
4110 17:58:12.543804 RX Vref Scan: 0
4111 17:58:12.544110
4112 17:58:12.545973 RX Vref 0 -> 0, step: 1
4113 17:58:12.546439
4114 17:58:12.549555 RX Delay -195 -> 252, step: 8
4115 17:58:12.552702 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4116 17:58:12.559524 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4117 17:58:12.562811 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4118 17:58:12.565909 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4119 17:58:12.569126 iDelay=205, Bit 4, Center 44 (-115 ~ 204) 320
4120 17:58:12.576535 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4121 17:58:12.579447 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4122 17:58:12.582575 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4123 17:58:12.585922 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4124 17:58:12.589236 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4125 17:58:12.595774 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4126 17:58:12.599439 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4127 17:58:12.602532 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4128 17:58:12.608928 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4129 17:58:12.612140 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4130 17:58:12.615442 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4131 17:58:12.615853 ==
4132 17:58:12.618654 Dram Type= 6, Freq= 0, CH_0, rank 1
4133 17:58:12.622552 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4134 17:58:12.622987 ==
4135 17:58:12.625699 DQS Delay:
4136 17:58:12.626148 DQS0 = 0, DQS1 = 0
4137 17:58:12.628840 DQM Delay:
4138 17:58:12.629312 DQM0 = 41, DQM1 = 31
4139 17:58:12.629693 DQ Delay:
4140 17:58:12.632330 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4141 17:58:12.635203 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4142 17:58:12.639026 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4143 17:58:12.642390 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =44
4144 17:58:12.642830
4145 17:58:12.643231
4146 17:58:12.651638 [DQSOSCAuto] RK1, (LSB)MR18= 0x6262, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4147 17:58:12.655326 CH0 RK1: MR19=808, MR18=6262
4148 17:58:12.661930 CH0_RK1: MR19=0x808, MR18=0x6262, DQSOSC=391, MR23=63, INC=171, DEC=114
4149 17:58:12.662489 [RxdqsGatingPostProcess] freq 600
4150 17:58:12.668551 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4151 17:58:12.671661 Pre-setting of DQS Precalculation
4152 17:58:12.674764 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4153 17:58:12.678224 ==
4154 17:58:12.681921 Dram Type= 6, Freq= 0, CH_1, rank 0
4155 17:58:12.685228 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4156 17:58:12.685648 ==
4157 17:58:12.691967 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4158 17:58:12.695214 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4159 17:58:12.698835 [CA 0] Center 35 (5~66) winsize 62
4160 17:58:12.702378 [CA 1] Center 35 (5~66) winsize 62
4161 17:58:12.705537 [CA 2] Center 33 (3~64) winsize 62
4162 17:58:12.708654 [CA 3] Center 33 (3~64) winsize 62
4163 17:58:12.712206 [CA 4] Center 33 (2~64) winsize 63
4164 17:58:12.715461 [CA 5] Center 33 (2~64) winsize 63
4165 17:58:12.716029
4166 17:58:12.718523 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4167 17:58:12.718937
4168 17:58:12.721685 [CATrainingPosCal] consider 1 rank data
4169 17:58:12.725532 u2DelayCellTimex100 = 270/100 ps
4170 17:58:12.728728 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4171 17:58:12.735174 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4172 17:58:12.738448 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4173 17:58:12.741686 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4174 17:58:12.745537 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4175 17:58:12.748623 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4176 17:58:12.749265
4177 17:58:12.751800 CA PerBit enable=1, Macro0, CA PI delay=33
4178 17:58:12.752310
4179 17:58:12.755023 [CBTSetCACLKResult] CA Dly = 33
4180 17:58:12.758212 CS Dly: 4 (0~35)
4181 17:58:12.758625 ==
4182 17:58:12.761454 Dram Type= 6, Freq= 0, CH_1, rank 1
4183 17:58:12.764944 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4184 17:58:12.765358 ==
4185 17:58:12.771198 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4186 17:58:12.774645 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4187 17:58:12.778801 [CA 0] Center 35 (5~66) winsize 62
4188 17:58:12.782005 [CA 1] Center 34 (4~65) winsize 62
4189 17:58:12.785893 [CA 2] Center 33 (3~64) winsize 62
4190 17:58:12.789370 [CA 3] Center 33 (3~64) winsize 62
4191 17:58:12.792584 [CA 4] Center 32 (2~63) winsize 62
4192 17:58:12.795786 [CA 5] Center 32 (2~63) winsize 62
4193 17:58:12.796206
4194 17:58:12.798942 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4195 17:58:12.799359
4196 17:58:12.802313 [CATrainingPosCal] consider 2 rank data
4197 17:58:12.805514 u2DelayCellTimex100 = 270/100 ps
4198 17:58:12.808453 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4199 17:58:12.815431 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4200 17:58:12.818971 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4201 17:58:12.821961 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4202 17:58:12.825628 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4203 17:58:12.828843 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4204 17:58:12.829299
4205 17:58:12.832112 CA PerBit enable=1, Macro0, CA PI delay=32
4206 17:58:12.832555
4207 17:58:12.835258 [CBTSetCACLKResult] CA Dly = 32
4208 17:58:12.835693 CS Dly: 4 (0~35)
4209 17:58:12.838397
4210 17:58:12.842217 ----->DramcWriteLeveling(PI) begin...
4211 17:58:12.842655 ==
4212 17:58:12.845367 Dram Type= 6, Freq= 0, CH_1, rank 0
4213 17:58:12.848561 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4214 17:58:12.849003 ==
4215 17:58:12.851791 Write leveling (Byte 0): 29 => 29
4216 17:58:12.854990 Write leveling (Byte 1): 29 => 29
4217 17:58:12.858181 DramcWriteLeveling(PI) end<-----
4218 17:58:12.858642
4219 17:58:12.858979 ==
4220 17:58:12.862076 Dram Type= 6, Freq= 0, CH_1, rank 0
4221 17:58:12.865297 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4222 17:58:12.865713 ==
4223 17:58:12.868438 [Gating] SW mode calibration
4224 17:58:12.874657 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4225 17:58:12.881695 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4226 17:58:12.884728 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4227 17:58:12.887962 0 5 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4228 17:58:12.894425 0 5 8 | B1->B0 | 2f2f 2727 | 0 0 | (0 1) (1 1)
4229 17:58:12.898299 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 17:58:12.901528 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 17:58:12.908077 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 17:58:12.911367 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 17:58:12.914626 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 17:58:12.921202 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 17:58:12.924299 0 6 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4236 17:58:12.927538 0 6 8 | B1->B0 | 3535 4444 | 0 0 | (1 1) (0 0)
4237 17:58:12.934132 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 17:58:12.937654 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 17:58:12.940963 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 17:58:12.947414 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 17:58:12.950696 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 17:58:12.953891 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 17:58:12.960473 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4244 17:58:12.963725 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4245 17:58:12.967671 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 17:58:12.973884 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 17:58:12.977085 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 17:58:12.980322 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 17:58:12.986831 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 17:58:12.990016 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 17:58:12.993656 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 17:58:13.000275 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 17:58:13.003524 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 17:58:13.006719 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 17:58:13.013370 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 17:58:13.016563 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 17:58:13.019866 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 17:58:13.026717 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 17:58:13.030198 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4260 17:58:13.033411 Total UI for P1: 0, mck2ui 16
4261 17:58:13.036788 best dqsien dly found for B0: ( 0, 9, 2)
4262 17:58:13.039904 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4263 17:58:13.046625 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 17:58:13.047081 Total UI for P1: 0, mck2ui 16
4265 17:58:13.049737 best dqsien dly found for B1: ( 0, 9, 8)
4266 17:58:13.056207 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4267 17:58:13.059257 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4268 17:58:13.059666
4269 17:58:13.063043 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4270 17:58:13.066357 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4271 17:58:13.069371 [Gating] SW calibration Done
4272 17:58:13.069780 ==
4273 17:58:13.072455 Dram Type= 6, Freq= 0, CH_1, rank 0
4274 17:58:13.076446 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4275 17:58:13.076859 ==
4276 17:58:13.079634 RX Vref Scan: 0
4277 17:58:13.080045
4278 17:58:13.080366 RX Vref 0 -> 0, step: 1
4279 17:58:13.080700
4280 17:58:13.082799 RX Delay -230 -> 252, step: 16
4281 17:58:13.089006 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4282 17:58:13.092613 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4283 17:58:13.095813 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4284 17:58:13.099474 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4285 17:58:13.102589 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4286 17:58:13.108953 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4287 17:58:13.112047 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4288 17:58:13.115410 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4289 17:58:13.118597 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4290 17:58:13.125178 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4291 17:58:13.128958 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4292 17:58:13.132181 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4293 17:58:13.135207 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4294 17:58:13.141975 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4295 17:58:13.145253 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4296 17:58:13.148475 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4297 17:58:13.148689 ==
4298 17:58:13.151351 Dram Type= 6, Freq= 0, CH_1, rank 0
4299 17:58:13.154580 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4300 17:58:13.158233 ==
4301 17:58:13.158382 DQS Delay:
4302 17:58:13.158466 DQS0 = 0, DQS1 = 0
4303 17:58:13.161132 DQM Delay:
4304 17:58:13.161286 DQM0 = 39, DQM1 = 32
4305 17:58:13.164631 DQ Delay:
4306 17:58:13.164775 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4307 17:58:13.167991 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4308 17:58:13.171269 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4309 17:58:13.174450 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4310 17:58:13.174550
4311 17:58:13.178248
4312 17:58:13.178346 ==
4313 17:58:13.181272 Dram Type= 6, Freq= 0, CH_1, rank 0
4314 17:58:13.184594 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4315 17:58:13.184705 ==
4316 17:58:13.184790
4317 17:58:13.184879
4318 17:58:13.187926 TX Vref Scan disable
4319 17:58:13.188026 == TX Byte 0 ==
4320 17:58:13.195069 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4321 17:58:13.198054 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4322 17:58:13.198175 == TX Byte 1 ==
4323 17:58:13.204539 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4324 17:58:13.208174 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4325 17:58:13.208323 ==
4326 17:58:13.211341 Dram Type= 6, Freq= 0, CH_1, rank 0
4327 17:58:13.214794 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4328 17:58:13.214981 ==
4329 17:58:13.215116
4330 17:58:13.215242
4331 17:58:13.218078 TX Vref Scan disable
4332 17:58:13.221322 == TX Byte 0 ==
4333 17:58:13.224543 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4334 17:58:13.227952 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4335 17:58:13.231396 == TX Byte 1 ==
4336 17:58:13.234575 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4337 17:58:13.240935 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4338 17:58:13.241350
4339 17:58:13.241716 [DATLAT]
4340 17:58:13.242082 Freq=600, CH1 RK0
4341 17:58:13.242396
4342 17:58:13.244089 DATLAT Default: 0x9
4343 17:58:13.244499 0, 0xFFFF, sum = 0
4344 17:58:13.247728 1, 0xFFFF, sum = 0
4345 17:58:13.248187 2, 0xFFFF, sum = 0
4346 17:58:13.250844 3, 0xFFFF, sum = 0
4347 17:58:13.254097 4, 0xFFFF, sum = 0
4348 17:58:13.254517 5, 0xFFFF, sum = 0
4349 17:58:13.257920 6, 0xFFFF, sum = 0
4350 17:58:13.258405 7, 0x0, sum = 1
4351 17:58:13.258739 8, 0x0, sum = 2
4352 17:58:13.261092 9, 0x0, sum = 3
4353 17:58:13.261549 10, 0x0, sum = 4
4354 17:58:13.264278 best_step = 8
4355 17:58:13.264703
4356 17:58:13.265065 ==
4357 17:58:13.267483 Dram Type= 6, Freq= 0, CH_1, rank 0
4358 17:58:13.270669 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4359 17:58:13.271120 ==
4360 17:58:13.274343 RX Vref Scan: 1
4361 17:58:13.274754
4362 17:58:13.275099 RX Vref 0 -> 0, step: 1
4363 17:58:13.275408
4364 17:58:13.277428 RX Delay -195 -> 252, step: 8
4365 17:58:13.277899
4366 17:58:13.280823 Set Vref, RX VrefLevel [Byte0]: 51
4367 17:58:13.283518 [Byte1]: 50
4368 17:58:13.288049
4369 17:58:13.288462 Final RX Vref Byte 0 = 51 to rank0
4370 17:58:13.291191 Final RX Vref Byte 1 = 50 to rank0
4371 17:58:13.294560 Final RX Vref Byte 0 = 51 to rank1
4372 17:58:13.297738 Final RX Vref Byte 1 = 50 to rank1==
4373 17:58:13.300956 Dram Type= 6, Freq= 0, CH_1, rank 0
4374 17:58:13.307679 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4375 17:58:13.308097 ==
4376 17:58:13.308423 DQS Delay:
4377 17:58:13.311313 DQS0 = 0, DQS1 = 0
4378 17:58:13.311726 DQM Delay:
4379 17:58:13.312058 DQM0 = 37, DQM1 = 30
4380 17:58:13.314326 DQ Delay:
4381 17:58:13.317553 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4382 17:58:13.321132 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4383 17:58:13.324288 DQ8 =8, DQ9 =20, DQ10 =32, DQ11 =24
4384 17:58:13.327512 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4385 17:58:13.327923
4386 17:58:13.328346
4387 17:58:13.334159 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e6e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4388 17:58:13.337585 CH1 RK0: MR19=808, MR18=6E6E
4389 17:58:13.344640 CH1_RK0: MR19=0x808, MR18=0x6E6E, DQSOSC=389, MR23=63, INC=173, DEC=115
4390 17:58:13.345258
4391 17:58:13.347737 ----->DramcWriteLeveling(PI) begin...
4392 17:58:13.348157 ==
4393 17:58:13.351301 Dram Type= 6, Freq= 0, CH_1, rank 1
4394 17:58:13.354375 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4395 17:58:13.354903 ==
4396 17:58:13.357451 Write leveling (Byte 0): 30 => 30
4397 17:58:13.360665 Write leveling (Byte 1): 27 => 27
4398 17:58:13.364009 DramcWriteLeveling(PI) end<-----
4399 17:58:13.364575
4400 17:58:13.365089 ==
4401 17:58:13.367535 Dram Type= 6, Freq= 0, CH_1, rank 1
4402 17:58:13.370753 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4403 17:58:13.371288 ==
4404 17:58:13.374118 [Gating] SW mode calibration
4405 17:58:13.380833 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4406 17:58:13.387669 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4407 17:58:13.390718 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4408 17:58:13.397363 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
4409 17:58:13.400637 0 5 8 | B1->B0 | 2f2f 2727 | 1 0 | (1 1) (0 0)
4410 17:58:13.403810 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 17:58:13.410943 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 17:58:13.413748 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 17:58:13.417285 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 17:58:13.423987 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 17:58:13.427190 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 17:58:13.430555 0 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4417 17:58:13.436980 0 6 8 | B1->B0 | 3434 4242 | 0 0 | (0 0) (0 0)
4418 17:58:13.440039 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 17:58:13.443886 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 17:58:13.450235 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 17:58:13.453447 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 17:58:13.456648 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 17:58:13.463306 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 17:58:13.466854 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 17:58:13.469896 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 17:58:13.476484 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 17:58:13.479736 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 17:58:13.482856 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 17:58:13.489811 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 17:58:13.492925 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 17:58:13.496124 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 17:58:13.502564 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 17:58:13.506111 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 17:58:13.509306 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 17:58:13.513177 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 17:58:13.519502 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 17:58:13.522420 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 17:58:13.529424 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 17:58:13.532436 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 17:58:13.535936 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4441 17:58:13.542758 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 17:58:13.543182 Total UI for P1: 0, mck2ui 16
4443 17:58:13.545957 best dqsien dly found for B0: ( 0, 9, 4)
4444 17:58:13.548980 Total UI for P1: 0, mck2ui 16
4445 17:58:13.552176 best dqsien dly found for B1: ( 0, 9, 6)
4446 17:58:13.555399 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4447 17:58:13.561714 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4448 17:58:13.561796
4449 17:58:13.565478 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4450 17:58:13.568800 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4451 17:58:13.571746 [Gating] SW calibration Done
4452 17:58:13.571839 ==
4453 17:58:13.575181 Dram Type= 6, Freq= 0, CH_1, rank 1
4454 17:58:13.578627 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4455 17:58:13.578817 ==
4456 17:58:13.578906 RX Vref Scan: 0
4457 17:58:13.581688
4458 17:58:13.581796 RX Vref 0 -> 0, step: 1
4459 17:58:13.581881
4460 17:58:13.584971 RX Delay -230 -> 252, step: 16
4461 17:58:13.588345 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4462 17:58:13.594968 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4463 17:58:13.598272 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4464 17:58:13.601566 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4465 17:58:13.604771 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4466 17:58:13.612058 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4467 17:58:13.615000 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4468 17:58:13.618578 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4469 17:58:13.621863 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4470 17:58:13.625161 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4471 17:58:13.632315 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4472 17:58:13.635093 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4473 17:58:13.638019 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4474 17:58:13.641497 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4475 17:58:13.648766 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4476 17:58:13.651675 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4477 17:58:13.652271 ==
4478 17:58:13.654918 Dram Type= 6, Freq= 0, CH_1, rank 1
4479 17:58:13.658132 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4480 17:58:13.658712 ==
4481 17:58:13.661351 DQS Delay:
4482 17:58:13.661753 DQS0 = 0, DQS1 = 0
4483 17:58:13.662124 DQM Delay:
4484 17:58:13.664633 DQM0 = 39, DQM1 = 33
4485 17:58:13.665134 DQ Delay:
4486 17:58:13.668408 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4487 17:58:13.671433 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4488 17:58:13.674626 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4489 17:58:13.677818 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4490 17:58:13.678436
4491 17:58:13.678919
4492 17:58:13.679248 ==
4493 17:58:13.681451 Dram Type= 6, Freq= 0, CH_1, rank 1
4494 17:58:13.687909 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4495 17:58:13.688613 ==
4496 17:58:13.689140
4497 17:58:13.689602
4498 17:58:13.690973 TX Vref Scan disable
4499 17:58:13.691441 == TX Byte 0 ==
4500 17:58:13.694784 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4501 17:58:13.701064 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4502 17:58:13.701642 == TX Byte 1 ==
4503 17:58:13.704204 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4504 17:58:13.710710 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4505 17:58:13.711215 ==
4506 17:58:13.714507 Dram Type= 6, Freq= 0, CH_1, rank 1
4507 17:58:13.717854 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4508 17:58:13.718440 ==
4509 17:58:13.718778
4510 17:58:13.719078
4511 17:58:13.720998 TX Vref Scan disable
4512 17:58:13.724169 == TX Byte 0 ==
4513 17:58:13.727644 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4514 17:58:13.730751 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4515 17:58:13.734100 == TX Byte 1 ==
4516 17:58:13.737538 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4517 17:58:13.740694 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4518 17:58:13.741099
4519 17:58:13.744237 [DATLAT]
4520 17:58:13.744654 Freq=600, CH1 RK1
4521 17:58:13.744978
4522 17:58:13.747122 DATLAT Default: 0x8
4523 17:58:13.747577 0, 0xFFFF, sum = 0
4524 17:58:13.750728 1, 0xFFFF, sum = 0
4525 17:58:13.751148 2, 0xFFFF, sum = 0
4526 17:58:13.753936 3, 0xFFFF, sum = 0
4527 17:58:13.754500 4, 0xFFFF, sum = 0
4528 17:58:13.757404 5, 0xFFFF, sum = 0
4529 17:58:13.757818 6, 0xFFFF, sum = 0
4530 17:58:13.760513 7, 0x0, sum = 1
4531 17:58:13.760877 8, 0x0, sum = 2
4532 17:58:13.763868 9, 0x0, sum = 3
4533 17:58:13.764278 10, 0x0, sum = 4
4534 17:58:13.767359 best_step = 8
4535 17:58:13.767876
4536 17:58:13.768205 ==
4537 17:58:13.770332 Dram Type= 6, Freq= 0, CH_1, rank 1
4538 17:58:13.773989 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4539 17:58:13.774442 ==
4540 17:58:13.777297 RX Vref Scan: 0
4541 17:58:13.777700
4542 17:58:13.778020 RX Vref 0 -> 0, step: 1
4543 17:58:13.778352
4544 17:58:13.780516 RX Delay -195 -> 252, step: 8
4545 17:58:13.787219 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4546 17:58:13.790290 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4547 17:58:13.793921 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4548 17:58:13.797051 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4549 17:58:13.803418 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4550 17:58:13.807329 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4551 17:58:13.810446 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4552 17:58:13.813662 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4553 17:58:13.820164 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4554 17:58:13.823966 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4555 17:58:13.826928 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4556 17:58:13.830134 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4557 17:58:13.833322 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4558 17:58:13.840176 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4559 17:58:13.843160 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4560 17:58:13.846644 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4561 17:58:13.847063 ==
4562 17:58:13.849668 Dram Type= 6, Freq= 0, CH_1, rank 1
4563 17:58:13.856286 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4564 17:58:13.856832 ==
4565 17:58:13.857302 DQS Delay:
4566 17:58:13.859932 DQS0 = 0, DQS1 = 0
4567 17:58:13.860344 DQM Delay:
4568 17:58:13.860683 DQM0 = 37, DQM1 = 29
4569 17:58:13.863219 DQ Delay:
4570 17:58:13.866476 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4571 17:58:13.869757 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4572 17:58:13.872955 DQ8 =16, DQ9 =16, DQ10 =28, DQ11 =20
4573 17:58:13.876375 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4574 17:58:13.876785
4575 17:58:13.877108
4576 17:58:13.883323 [DQSOSCAuto] RK1, (LSB)MR18= 0x5656, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4577 17:58:13.886259 CH1 RK1: MR19=808, MR18=5656
4578 17:58:13.892791 CH1_RK1: MR19=0x808, MR18=0x5656, DQSOSC=393, MR23=63, INC=169, DEC=113
4579 17:58:13.896496 [RxdqsGatingPostProcess] freq 600
4580 17:58:13.899644 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4581 17:58:13.902547 Pre-setting of DQS Precalculation
4582 17:58:13.909338 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4583 17:58:13.916360 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4584 17:58:13.922743 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4585 17:58:13.923159
4586 17:58:13.923482
4587 17:58:13.925966 [Calibration Summary] 1200 Mbps
4588 17:58:13.926413 CH 0, Rank 0
4589 17:58:13.929380 SW Impedance : PASS
4590 17:58:13.932493 DUTY Scan : NO K
4591 17:58:13.932906 ZQ Calibration : PASS
4592 17:58:13.935874 Jitter Meter : NO K
4593 17:58:13.939053 CBT Training : PASS
4594 17:58:13.939466 Write leveling : PASS
4595 17:58:13.942199 RX DQS gating : PASS
4596 17:58:13.945996 RX DQ/DQS(RDDQC) : PASS
4597 17:58:13.946454 TX DQ/DQS : PASS
4598 17:58:13.949108 RX DATLAT : PASS
4599 17:58:13.952256 RX DQ/DQS(Engine): PASS
4600 17:58:13.952668 TX OE : NO K
4601 17:58:13.955777 All Pass.
4602 17:58:13.956202
4603 17:58:13.956660 CH 0, Rank 1
4604 17:58:13.958808 SW Impedance : PASS
4605 17:58:13.959218 DUTY Scan : NO K
4606 17:58:13.962540 ZQ Calibration : PASS
4607 17:58:13.965433 Jitter Meter : NO K
4608 17:58:13.965845 CBT Training : PASS
4609 17:58:13.969143 Write leveling : PASS
4610 17:58:13.971910 RX DQS gating : PASS
4611 17:58:13.972379 RX DQ/DQS(RDDQC) : PASS
4612 17:58:13.975859 TX DQ/DQS : PASS
4613 17:58:13.976274 RX DATLAT : PASS
4614 17:58:13.978952 RX DQ/DQS(Engine): PASS
4615 17:58:13.982143 TX OE : NO K
4616 17:58:13.982576 All Pass.
4617 17:58:13.982907
4618 17:58:13.983207 CH 1, Rank 0
4619 17:58:13.985245 SW Impedance : PASS
4620 17:58:13.988430 DUTY Scan : NO K
4621 17:58:13.988843 ZQ Calibration : PASS
4622 17:58:13.992337 Jitter Meter : NO K
4623 17:58:13.995589 CBT Training : PASS
4624 17:58:13.996032 Write leveling : PASS
4625 17:58:13.998488 RX DQS gating : PASS
4626 17:58:14.001997 RX DQ/DQS(RDDQC) : PASS
4627 17:58:14.002469 TX DQ/DQS : PASS
4628 17:58:14.005336 RX DATLAT : PASS
4629 17:58:14.008441 RX DQ/DQS(Engine): PASS
4630 17:58:14.008853 TX OE : NO K
4631 17:58:14.011550 All Pass.
4632 17:58:14.011962
4633 17:58:14.012285 CH 1, Rank 1
4634 17:58:14.015196 SW Impedance : PASS
4635 17:58:14.015609 DUTY Scan : NO K
4636 17:58:14.018351 ZQ Calibration : PASS
4637 17:58:14.021497 Jitter Meter : NO K
4638 17:58:14.021907 CBT Training : PASS
4639 17:58:14.024780 Write leveling : PASS
4640 17:58:14.028583 RX DQS gating : PASS
4641 17:58:14.028994 RX DQ/DQS(RDDQC) : PASS
4642 17:58:14.031850 TX DQ/DQS : PASS
4643 17:58:14.035003 RX DATLAT : PASS
4644 17:58:14.035415 RX DQ/DQS(Engine): PASS
4645 17:58:14.038236 TX OE : NO K
4646 17:58:14.038652 All Pass.
4647 17:58:14.038980
4648 17:58:14.041397 DramC Write-DBI off
4649 17:58:14.044538 PER_BANK_REFRESH: Hybrid Mode
4650 17:58:14.045020 TX_TRACKING: ON
4651 17:58:14.054645 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4652 17:58:14.057868 [FAST_K] Save calibration result to emmc
4653 17:58:14.061028 dramc_set_vcore_voltage set vcore to 662500
4654 17:58:14.064756 Read voltage for 933, 3
4655 17:58:14.065150 Vio18 = 0
4656 17:58:14.065470 Vcore = 662500
4657 17:58:14.067785 Vdram = 0
4658 17:58:14.068190 Vddq = 0
4659 17:58:14.068513 Vmddr = 0
4660 17:58:14.074519 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4661 17:58:14.078012 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4662 17:58:14.081384 MEM_TYPE=3, freq_sel=17
4663 17:58:14.084565 sv_algorithm_assistance_LP4_1600
4664 17:58:14.087828 ============ PULL DRAM RESETB DOWN ============
4665 17:58:14.091146 ========== PULL DRAM RESETB DOWN end =========
4666 17:58:14.097531 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4667 17:58:14.101364 ===================================
4668 17:58:14.101772 LPDDR4 DRAM CONFIGURATION
4669 17:58:14.104370 ===================================
4670 17:58:14.107337 EX_ROW_EN[0] = 0x0
4671 17:58:14.111129 EX_ROW_EN[1] = 0x0
4672 17:58:14.111547 LP4Y_EN = 0x0
4673 17:58:14.114373 WORK_FSP = 0x0
4674 17:58:14.114781 WL = 0x3
4675 17:58:14.117378 RL = 0x3
4676 17:58:14.117803 BL = 0x2
4677 17:58:14.121036 RPST = 0x0
4678 17:58:14.121444 RD_PRE = 0x0
4679 17:58:14.124065 WR_PRE = 0x1
4680 17:58:14.124475 WR_PST = 0x0
4681 17:58:14.127275 DBI_WR = 0x0
4682 17:58:14.127827 DBI_RD = 0x0
4683 17:58:14.130454 OTF = 0x1
4684 17:58:14.134328 ===================================
4685 17:58:14.137556 ===================================
4686 17:58:14.137967 ANA top config
4687 17:58:14.140619 ===================================
4688 17:58:14.143697 DLL_ASYNC_EN = 0
4689 17:58:14.146956 ALL_SLAVE_EN = 1
4690 17:58:14.150687 NEW_RANK_MODE = 1
4691 17:58:14.151100 DLL_IDLE_MODE = 1
4692 17:58:14.153977 LP45_APHY_COMB_EN = 1
4693 17:58:14.157062 TX_ODT_DIS = 1
4694 17:58:14.160369 NEW_8X_MODE = 1
4695 17:58:14.163615 ===================================
4696 17:58:14.167370 ===================================
4697 17:58:14.170420 data_rate = 1866
4698 17:58:14.173459 CKR = 1
4699 17:58:14.173874 DQ_P2S_RATIO = 8
4700 17:58:14.177066 ===================================
4701 17:58:14.180151 CA_P2S_RATIO = 8
4702 17:58:14.183525 DQ_CA_OPEN = 0
4703 17:58:14.186502 DQ_SEMI_OPEN = 0
4704 17:58:14.190135 CA_SEMI_OPEN = 0
4705 17:58:14.193384 CA_FULL_RATE = 0
4706 17:58:14.193804 DQ_CKDIV4_EN = 1
4707 17:58:14.196598 CA_CKDIV4_EN = 1
4708 17:58:14.199782 CA_PREDIV_EN = 0
4709 17:58:14.202986 PH8_DLY = 0
4710 17:58:14.206827 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4711 17:58:14.209776 DQ_AAMCK_DIV = 4
4712 17:58:14.210104 CA_AAMCK_DIV = 4
4713 17:58:14.213363 CA_ADMCK_DIV = 4
4714 17:58:14.216151 DQ_TRACK_CA_EN = 0
4715 17:58:14.219934 CA_PICK = 933
4716 17:58:14.223001 CA_MCKIO = 933
4717 17:58:14.226056 MCKIO_SEMI = 0
4718 17:58:14.229279 PLL_FREQ = 3732
4719 17:58:14.229451 DQ_UI_PI_RATIO = 32
4720 17:58:14.233052 CA_UI_PI_RATIO = 0
4721 17:58:14.236210 ===================================
4722 17:58:14.239463 ===================================
4723 17:58:14.242613 memory_type:LPDDR4
4724 17:58:14.245773 GP_NUM : 10
4725 17:58:14.245897 SRAM_EN : 1
4726 17:58:14.249036 MD32_EN : 0
4727 17:58:14.252879 ===================================
4728 17:58:14.256074 [ANA_INIT] >>>>>>>>>>>>>>
4729 17:58:14.256221 <<<<<< [CONFIGURE PHASE]: ANA_TX
4730 17:58:14.259093 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4731 17:58:14.262501 ===================================
4732 17:58:14.265654 data_rate = 1866,PCW = 0X8f00
4733 17:58:14.268767 ===================================
4734 17:58:14.272624 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4735 17:58:14.288246 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4736 17:58:14.288426 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4737 17:58:14.288916 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4738 17:58:14.292074 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4739 17:58:14.295287 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4740 17:58:14.298553 [ANA_INIT] flow start
4741 17:58:14.298642 [ANA_INIT] PLL >>>>>>>>
4742 17:58:14.301772 [ANA_INIT] PLL <<<<<<<<
4743 17:58:14.305622 [ANA_INIT] MIDPI >>>>>>>>
4744 17:58:14.308874 [ANA_INIT] MIDPI <<<<<<<<
4745 17:58:14.308953 [ANA_INIT] DLL >>>>>>>>
4746 17:58:14.312224 [ANA_INIT] flow end
4747 17:58:14.315326 ============ LP4 DIFF to SE enter ============
4748 17:58:14.318438 ============ LP4 DIFF to SE exit ============
4749 17:58:14.321874 [ANA_INIT] <<<<<<<<<<<<<
4750 17:58:14.325196 [Flow] Enable top DCM control >>>>>
4751 17:58:14.328746 [Flow] Enable top DCM control <<<<<
4752 17:58:14.332058 Enable DLL master slave shuffle
4753 17:58:14.338348 ==============================================================
4754 17:58:14.338517 Gating Mode config
4755 17:58:14.344820 ==============================================================
4756 17:58:14.345065 Config description:
4757 17:58:14.355275 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4758 17:58:14.361572 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4759 17:58:14.368163 SELPH_MODE 0: By rank 1: By Phase
4760 17:58:14.371352 ==============================================================
4761 17:58:14.374529 GAT_TRACK_EN = 1
4762 17:58:14.377830 RX_GATING_MODE = 2
4763 17:58:14.381448 RX_GATING_TRACK_MODE = 2
4764 17:58:14.384563 SELPH_MODE = 1
4765 17:58:14.387790 PICG_EARLY_EN = 1
4766 17:58:14.391407 VALID_LAT_VALUE = 1
4767 17:58:14.397648 ==============================================================
4768 17:58:14.401119 Enter into Gating configuration >>>>
4769 17:58:14.404192 Exit from Gating configuration <<<<
4770 17:58:14.407400 Enter into DVFS_PRE_config >>>>>
4771 17:58:14.417978 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4772 17:58:14.421135 Exit from DVFS_PRE_config <<<<<
4773 17:58:14.424416 Enter into PICG configuration >>>>
4774 17:58:14.428073 Exit from PICG configuration <<<<
4775 17:58:14.431181 [RX_INPUT] configuration >>>>>
4776 17:58:14.431703 [RX_INPUT] configuration <<<<<
4777 17:58:14.437656 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4778 17:58:14.444274 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4779 17:58:14.447665 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4780 17:58:14.454328 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4781 17:58:14.460834 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4782 17:58:14.467268 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4783 17:58:14.471020 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4784 17:58:14.474203 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4785 17:58:14.480487 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4786 17:58:14.483658 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4787 17:58:14.486858 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4788 17:58:14.493881 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4789 17:58:14.497034 ===================================
4790 17:58:14.497194 LPDDR4 DRAM CONFIGURATION
4791 17:58:14.500138 ===================================
4792 17:58:14.503669 EX_ROW_EN[0] = 0x0
4793 17:58:14.506780 EX_ROW_EN[1] = 0x0
4794 17:58:14.506903 LP4Y_EN = 0x0
4795 17:58:14.509813 WORK_FSP = 0x0
4796 17:58:14.509949 WL = 0x3
4797 17:58:14.513446 RL = 0x3
4798 17:58:14.513592 BL = 0x2
4799 17:58:14.516596 RPST = 0x0
4800 17:58:14.516734 RD_PRE = 0x0
4801 17:58:14.519904 WR_PRE = 0x1
4802 17:58:14.519998 WR_PST = 0x0
4803 17:58:14.523108 DBI_WR = 0x0
4804 17:58:14.523203 DBI_RD = 0x0
4805 17:58:14.526772 OTF = 0x1
4806 17:58:14.529918 ===================================
4807 17:58:14.533248 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4808 17:58:14.536445 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4809 17:58:14.543215 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4810 17:58:14.546445 ===================================
4811 17:58:14.546553 LPDDR4 DRAM CONFIGURATION
4812 17:58:14.550111 ===================================
4813 17:58:14.553304 EX_ROW_EN[0] = 0x10
4814 17:58:14.556699 EX_ROW_EN[1] = 0x0
4815 17:58:14.556781 LP4Y_EN = 0x0
4816 17:58:14.559810 WORK_FSP = 0x0
4817 17:58:14.559889 WL = 0x3
4818 17:58:14.562764 RL = 0x3
4819 17:58:14.562843 BL = 0x2
4820 17:58:14.566461 RPST = 0x0
4821 17:58:14.566540 RD_PRE = 0x0
4822 17:58:14.569598 WR_PRE = 0x1
4823 17:58:14.569702 WR_PST = 0x0
4824 17:58:14.572678 DBI_WR = 0x0
4825 17:58:14.572820 DBI_RD = 0x0
4826 17:58:14.576068 OTF = 0x1
4827 17:58:14.580089 ===================================
4828 17:58:14.586164 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4829 17:58:14.589532 nWR fixed to 30
4830 17:58:14.589647 [ModeRegInit_LP4] CH0 RK0
4831 17:58:14.592949 [ModeRegInit_LP4] CH0 RK1
4832 17:58:14.596311 [ModeRegInit_LP4] CH1 RK0
4833 17:58:14.599321 [ModeRegInit_LP4] CH1 RK1
4834 17:58:14.599463 match AC timing 8
4835 17:58:14.606243 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4836 17:58:14.609410 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4837 17:58:14.612553 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4838 17:58:14.619124 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4839 17:58:14.622731 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4840 17:58:14.622990 ==
4841 17:58:14.625929 Dram Type= 6, Freq= 0, CH_0, rank 0
4842 17:58:14.629408 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4843 17:58:14.629701 ==
4844 17:58:14.636038 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4845 17:58:14.642359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4846 17:58:14.646007 [CA 0] Center 38 (8~69) winsize 62
4847 17:58:14.649276 [CA 1] Center 38 (8~69) winsize 62
4848 17:58:14.652465 [CA 2] Center 36 (6~67) winsize 62
4849 17:58:14.655675 [CA 3] Center 36 (6~67) winsize 62
4850 17:58:14.658811 [CA 4] Center 35 (5~65) winsize 61
4851 17:58:14.662535 [CA 5] Center 34 (4~65) winsize 62
4852 17:58:14.662741
4853 17:58:14.665596 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4854 17:58:14.665802
4855 17:58:14.668620 [CATrainingPosCal] consider 1 rank data
4856 17:58:14.672185 u2DelayCellTimex100 = 270/100 ps
4857 17:58:14.675235 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4858 17:58:14.678928 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4859 17:58:14.682015 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4860 17:58:14.685227 CA3 delay=36 (6~67),Diff = 2 PI (12 cell)
4861 17:58:14.688641 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4862 17:58:14.691920 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4863 17:58:14.695400
4864 17:58:14.698362 CA PerBit enable=1, Macro0, CA PI delay=34
4865 17:58:14.698509
4866 17:58:14.701638 [CBTSetCACLKResult] CA Dly = 34
4867 17:58:14.701792 CS Dly: 7 (0~38)
4868 17:58:14.701869 ==
4869 17:58:14.704834 Dram Type= 6, Freq= 0, CH_0, rank 1
4870 17:58:14.708428 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4871 17:58:14.708526 ==
4872 17:58:14.714876 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4873 17:58:14.721288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4874 17:58:14.725253 [CA 0] Center 38 (8~69) winsize 62
4875 17:58:14.728286 [CA 1] Center 38 (8~69) winsize 62
4876 17:58:14.731687 [CA 2] Center 36 (6~67) winsize 62
4877 17:58:14.734823 [CA 3] Center 35 (5~66) winsize 62
4878 17:58:14.738136 [CA 4] Center 34 (4~65) winsize 62
4879 17:58:14.741462 [CA 5] Center 34 (4~65) winsize 62
4880 17:58:14.741648
4881 17:58:14.744740 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4882 17:58:14.744960
4883 17:58:14.748032 [CATrainingPosCal] consider 2 rank data
4884 17:58:14.751687 u2DelayCellTimex100 = 270/100 ps
4885 17:58:14.755024 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4886 17:58:14.758307 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4887 17:58:14.761556 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4888 17:58:14.768460 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4889 17:58:14.771348 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4890 17:58:14.774553 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4891 17:58:14.774994
4892 17:58:14.777727 CA PerBit enable=1, Macro0, CA PI delay=34
4893 17:58:14.778203
4894 17:58:14.781283 [CBTSetCACLKResult] CA Dly = 34
4895 17:58:14.781834 CS Dly: 7 (0~39)
4896 17:58:14.782399
4897 17:58:14.784735 ----->DramcWriteLeveling(PI) begin...
4898 17:58:14.787959 ==
4899 17:58:14.788448 Dram Type= 6, Freq= 0, CH_0, rank 0
4900 17:58:14.794384 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4901 17:58:14.794806 ==
4902 17:58:14.797607 Write leveling (Byte 0): 29 => 29
4903 17:58:14.801254 Write leveling (Byte 1): 29 => 29
4904 17:58:14.804861 DramcWriteLeveling(PI) end<-----
4905 17:58:14.805326
4906 17:58:14.805655 ==
4907 17:58:14.807973 Dram Type= 6, Freq= 0, CH_0, rank 0
4908 17:58:14.811528 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4909 17:58:14.812046 ==
4910 17:58:14.814526 [Gating] SW mode calibration
4911 17:58:14.820973 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4912 17:58:14.824161 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4913 17:58:14.831299 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4914 17:58:14.834564 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4915 17:58:14.837478 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4916 17:58:14.843907 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4917 17:58:14.847210 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4918 17:58:14.851010 0 10 20 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (1 0)
4919 17:58:14.857320 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4920 17:58:14.860539 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4921 17:58:14.864409 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4922 17:58:14.870713 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4923 17:58:14.873847 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4924 17:58:14.876893 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4925 17:58:14.883563 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4926 17:58:14.887495 0 11 20 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
4927 17:58:14.890552 0 11 24 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4928 17:58:14.897014 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4929 17:58:14.900459 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4930 17:58:14.903910 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4931 17:58:14.910197 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4932 17:58:14.913550 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4933 17:58:14.916741 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4934 17:58:14.923304 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4935 17:58:14.927102 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4936 17:58:14.930283 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4937 17:58:14.936559 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4938 17:58:14.939761 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4939 17:58:14.943573 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4940 17:58:14.949822 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 17:58:14.953523 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4942 17:58:14.956270 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 17:58:14.963069 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 17:58:14.966366 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 17:58:14.969591 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4946 17:58:14.976342 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4947 17:58:14.979537 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4948 17:58:14.982655 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4949 17:58:14.989461 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4950 17:58:14.992897 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4951 17:58:14.996193 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4952 17:58:14.999845 Total UI for P1: 0, mck2ui 16
4953 17:58:15.003129 best dqsien dly found for B1: ( 0, 14, 20)
4954 17:58:15.009555 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4955 17:58:15.010129 Total UI for P1: 0, mck2ui 16
4956 17:58:15.016216 best dqsien dly found for B0: ( 0, 14, 22)
4957 17:58:15.019811 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
4958 17:58:15.022661 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4959 17:58:15.023224
4960 17:58:15.026619 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
4961 17:58:15.029767 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
4962 17:58:15.033039 [Gating] SW calibration Done
4963 17:58:15.033454 ==
4964 17:58:15.036158 Dram Type= 6, Freq= 0, CH_0, rank 0
4965 17:58:15.039368 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4966 17:58:15.039810 ==
4967 17:58:15.042685 RX Vref Scan: 0
4968 17:58:15.043354
4969 17:58:15.043711 RX Vref 0 -> 0, step: 1
4970 17:58:15.044026
4971 17:58:15.045739 RX Delay -80 -> 252, step: 8
4972 17:58:15.052133 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4973 17:58:15.056112 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4974 17:58:15.059484 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4975 17:58:15.062531 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4976 17:58:15.065969 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4977 17:58:15.068868 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4978 17:58:15.075715 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4979 17:58:15.078750 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4980 17:58:15.082595 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4981 17:58:15.085672 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4982 17:58:15.088806 iDelay=208, Bit 10, Center 79 (-16 ~ 175) 192
4983 17:58:15.095564 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4984 17:58:15.098727 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
4985 17:58:15.101984 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4986 17:58:15.105150 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4987 17:58:15.108431 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
4988 17:58:15.109010 ==
4989 17:58:15.112323 Dram Type= 6, Freq= 0, CH_0, rank 0
4990 17:58:15.118238 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4991 17:58:15.118660 ==
4992 17:58:15.119016 DQS Delay:
4993 17:58:15.122113 DQS0 = 0, DQS1 = 0
4994 17:58:15.122527 DQM Delay:
4995 17:58:15.122855 DQM0 = 95, DQM1 = 85
4996 17:58:15.124966 DQ Delay:
4997 17:58:15.128033 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
4998 17:58:15.131716 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
4999 17:58:15.135155 DQ8 =75, DQ9 =71, DQ10 =79, DQ11 =79
5000 17:58:15.138324 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5001 17:58:15.138734
5002 17:58:15.139190
5003 17:58:15.139677 ==
5004 17:58:15.141448 Dram Type= 6, Freq= 0, CH_0, rank 0
5005 17:58:15.144735 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5006 17:58:15.145198 ==
5007 17:58:15.145668
5008 17:58:15.145996
5009 17:58:15.148389 TX Vref Scan disable
5010 17:58:15.151429 == TX Byte 0 ==
5011 17:58:15.155108 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5012 17:58:15.158366 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5013 17:58:15.161761 == TX Byte 1 ==
5014 17:58:15.164965 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5015 17:58:15.168280 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5016 17:58:15.168693 ==
5017 17:58:15.171504 Dram Type= 6, Freq= 0, CH_0, rank 0
5018 17:58:15.174654 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5019 17:58:15.177688 ==
5020 17:58:15.178140
5021 17:58:15.178475
5022 17:58:15.178781 TX Vref Scan disable
5023 17:58:15.181235 == TX Byte 0 ==
5024 17:58:15.184665 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5025 17:58:15.191252 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5026 17:58:15.191673 == TX Byte 1 ==
5027 17:58:15.194554 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5028 17:58:15.201339 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5029 17:58:15.201768
5030 17:58:15.202298 [DATLAT]
5031 17:58:15.202792 Freq=933, CH0 RK0
5032 17:58:15.203266
5033 17:58:15.204398 DATLAT Default: 0xd
5034 17:58:15.204804 0, 0xFFFF, sum = 0
5035 17:58:15.207656 1, 0xFFFF, sum = 0
5036 17:58:15.210807 2, 0xFFFF, sum = 0
5037 17:58:15.211223 3, 0xFFFF, sum = 0
5038 17:58:15.214586 4, 0xFFFF, sum = 0
5039 17:58:15.215002 5, 0xFFFF, sum = 0
5040 17:58:15.217418 6, 0xFFFF, sum = 0
5041 17:58:15.217835 7, 0xFFFF, sum = 0
5042 17:58:15.221286 8, 0xFFFF, sum = 0
5043 17:58:15.221728 9, 0xFFFF, sum = 0
5044 17:58:15.224526 10, 0x0, sum = 1
5045 17:58:15.224943 11, 0x0, sum = 2
5046 17:58:15.227913 12, 0x0, sum = 3
5047 17:58:15.228332 13, 0x0, sum = 4
5048 17:58:15.228662 best_step = 11
5049 17:58:15.231079
5050 17:58:15.231485 ==
5051 17:58:15.234583 Dram Type= 6, Freq= 0, CH_0, rank 0
5052 17:58:15.237477 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5053 17:58:15.237895 ==
5054 17:58:15.238245 RX Vref Scan: 1
5055 17:58:15.238550
5056 17:58:15.240691 RX Vref 0 -> 0, step: 1
5057 17:58:15.241098
5058 17:58:15.244183 RX Delay -69 -> 252, step: 4
5059 17:58:15.244711
5060 17:58:15.248118 Set Vref, RX VrefLevel [Byte0]: 51
5061 17:58:15.250247 [Byte1]: 48
5062 17:58:15.254336
5063 17:58:15.254744 Final RX Vref Byte 0 = 51 to rank0
5064 17:58:15.257584 Final RX Vref Byte 1 = 48 to rank0
5065 17:58:15.260771 Final RX Vref Byte 0 = 51 to rank1
5066 17:58:15.263972 Final RX Vref Byte 1 = 48 to rank1==
5067 17:58:15.267164 Dram Type= 6, Freq= 0, CH_0, rank 0
5068 17:58:15.273487 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5069 17:58:15.273901 ==
5070 17:58:15.274296 DQS Delay:
5071 17:58:15.277259 DQS0 = 0, DQS1 = 0
5072 17:58:15.277687 DQM Delay:
5073 17:58:15.278013 DQM0 = 96, DQM1 = 87
5074 17:58:15.280355 DQ Delay:
5075 17:58:15.283416 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =92
5076 17:58:15.286807 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =102
5077 17:58:15.289832 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =82
5078 17:58:15.293607 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =98
5079 17:58:15.294061
5080 17:58:15.294427
5081 17:58:15.300253 [DQSOSCAuto] RK0, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5082 17:58:15.303258 CH0 RK0: MR19=505, MR18=2222
5083 17:58:15.309761 CH0_RK0: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5084 17:58:15.310335
5085 17:58:15.313118 ----->DramcWriteLeveling(PI) begin...
5086 17:58:15.313421 ==
5087 17:58:15.316464 Dram Type= 6, Freq= 0, CH_0, rank 1
5088 17:58:15.320094 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5089 17:58:15.320329 ==
5090 17:58:15.323042 Write leveling (Byte 0): 26 => 26
5091 17:58:15.326326 Write leveling (Byte 1): 25 => 25
5092 17:58:15.329217 DramcWriteLeveling(PI) end<-----
5093 17:58:15.329389
5094 17:58:15.329535 ==
5095 17:58:15.332405 Dram Type= 6, Freq= 0, CH_0, rank 1
5096 17:58:15.339378 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5097 17:58:15.339533 ==
5098 17:58:15.339631 [Gating] SW mode calibration
5099 17:58:15.349260 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5100 17:58:15.352454 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5101 17:58:15.355604 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 17:58:15.362019 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 17:58:15.365407 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 17:58:15.369369 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 17:58:15.375822 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 17:58:15.379148 0 10 20 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 1)
5107 17:58:15.382443 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 17:58:15.388971 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 17:58:15.392177 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 17:58:15.395645 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 17:58:15.402171 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 17:58:15.405317 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 17:58:15.409299 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 17:58:15.415657 0 11 20 | B1->B0 | 2e2e 3b3b | 0 0 | (0 0) (0 0)
5115 17:58:15.419155 0 11 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5116 17:58:15.422458 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 17:58:15.428711 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 17:58:15.432284 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 17:58:15.435296 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 17:58:15.441673 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 17:58:15.444970 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 17:58:15.448581 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5123 17:58:15.455418 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5124 17:58:15.458631 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 17:58:15.461826 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 17:58:15.468494 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 17:58:15.471682 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 17:58:15.474930 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 17:58:15.481480 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 17:58:15.485300 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 17:58:15.488423 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 17:58:15.494982 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 17:58:15.498297 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 17:58:15.501510 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 17:58:15.507865 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 17:58:15.510988 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 17:58:15.514947 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 17:58:15.521409 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 17:58:15.524621 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5140 17:58:15.528334 Total UI for P1: 0, mck2ui 16
5141 17:58:15.531051 best dqsien dly found for B0: ( 0, 14, 22)
5142 17:58:15.534669 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 17:58:15.537587 Total UI for P1: 0, mck2ui 16
5144 17:58:15.541309 best dqsien dly found for B1: ( 0, 14, 24)
5145 17:58:15.544600 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5146 17:58:15.547739 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
5147 17:58:15.548271
5148 17:58:15.554697 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5149 17:58:15.557544 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 24)
5150 17:58:15.561203 [Gating] SW calibration Done
5151 17:58:15.561766 ==
5152 17:58:15.564171 Dram Type= 6, Freq= 0, CH_0, rank 1
5153 17:58:15.567570 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5154 17:58:15.567986 ==
5155 17:58:15.568318 RX Vref Scan: 0
5156 17:58:15.568698
5157 17:58:15.570815 RX Vref 0 -> 0, step: 1
5158 17:58:15.571232
5159 17:58:15.574158 RX Delay -80 -> 252, step: 8
5160 17:58:15.577423 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5161 17:58:15.580660 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5162 17:58:15.587610 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5163 17:58:15.590942 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5164 17:58:15.593937 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5165 17:58:15.597160 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5166 17:58:15.600426 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5167 17:58:15.603764 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5168 17:58:15.610606 iDelay=208, Bit 8, Center 79 (-8 ~ 167) 176
5169 17:58:15.613864 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5170 17:58:15.616744 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5171 17:58:15.620507 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5172 17:58:15.623696 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5173 17:58:15.630186 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5174 17:58:15.633277 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5175 17:58:15.636852 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5176 17:58:15.637076 ==
5177 17:58:15.639834 Dram Type= 6, Freq= 0, CH_0, rank 1
5178 17:58:15.643292 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5179 17:58:15.643517 ==
5180 17:58:15.646219 DQS Delay:
5181 17:58:15.646439 DQS0 = 0, DQS1 = 0
5182 17:58:15.649737 DQM Delay:
5183 17:58:15.650083 DQM0 = 97, DQM1 = 86
5184 17:58:15.650269 DQ Delay:
5185 17:58:15.653141 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5186 17:58:15.656331 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5187 17:58:15.659593 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =83
5188 17:58:15.662606 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =95
5189 17:58:15.662826
5190 17:58:15.662999
5191 17:58:15.666337 ==
5192 17:58:15.669496 Dram Type= 6, Freq= 0, CH_0, rank 1
5193 17:58:15.672976 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5194 17:58:15.673199 ==
5195 17:58:15.673372
5196 17:58:15.673553
5197 17:58:15.676079 TX Vref Scan disable
5198 17:58:15.676307 == TX Byte 0 ==
5199 17:58:15.682396 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5200 17:58:15.685637 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5201 17:58:15.685867 == TX Byte 1 ==
5202 17:58:15.692937 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5203 17:58:15.696215 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5204 17:58:15.696437 ==
5205 17:58:15.699445 Dram Type= 6, Freq= 0, CH_0, rank 1
5206 17:58:15.702651 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5207 17:58:15.702953 ==
5208 17:58:15.703141
5209 17:58:15.703307
5210 17:58:15.705916 TX Vref Scan disable
5211 17:58:15.709027 == TX Byte 0 ==
5212 17:58:15.712201 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5213 17:58:15.715542 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5214 17:58:15.718681 == TX Byte 1 ==
5215 17:58:15.722346 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5216 17:58:15.725422 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5217 17:58:15.725503
5218 17:58:15.728655 [DATLAT]
5219 17:58:15.728763 Freq=933, CH0 RK1
5220 17:58:15.728848
5221 17:58:15.731856 DATLAT Default: 0xb
5222 17:58:15.731936 0, 0xFFFF, sum = 0
5223 17:58:15.735674 1, 0xFFFF, sum = 0
5224 17:58:15.735757 2, 0xFFFF, sum = 0
5225 17:58:15.738884 3, 0xFFFF, sum = 0
5226 17:58:15.738966 4, 0xFFFF, sum = 0
5227 17:58:15.741911 5, 0xFFFF, sum = 0
5228 17:58:15.741993 6, 0xFFFF, sum = 0
5229 17:58:15.745448 7, 0xFFFF, sum = 0
5230 17:58:15.745552 8, 0xFFFF, sum = 0
5231 17:58:15.748705 9, 0xFFFF, sum = 0
5232 17:58:15.748787 10, 0x0, sum = 1
5233 17:58:15.751693 11, 0x0, sum = 2
5234 17:58:15.751790 12, 0x0, sum = 3
5235 17:58:15.755383 13, 0x0, sum = 4
5236 17:58:15.755508 best_step = 11
5237 17:58:15.755579
5238 17:58:15.755640 ==
5239 17:58:15.758275 Dram Type= 6, Freq= 0, CH_0, rank 1
5240 17:58:15.764643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5241 17:58:15.764756 ==
5242 17:58:15.764822 RX Vref Scan: 0
5243 17:58:15.764882
5244 17:58:15.768574 RX Vref 0 -> 0, step: 1
5245 17:58:15.768663
5246 17:58:15.771872 RX Delay -69 -> 252, step: 4
5247 17:58:15.775158 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5248 17:58:15.778169 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5249 17:58:15.784809 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5250 17:58:15.787764 iDelay=203, Bit 3, Center 90 (-1 ~ 182) 184
5251 17:58:15.791498 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5252 17:58:15.794775 iDelay=203, Bit 5, Center 90 (-1 ~ 182) 184
5253 17:58:15.797864 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5254 17:58:15.804526 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5255 17:58:15.808239 iDelay=203, Bit 8, Center 74 (-13 ~ 162) 176
5256 17:58:15.811486 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5257 17:58:15.814604 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5258 17:58:15.818293 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5259 17:58:15.824758 iDelay=203, Bit 12, Center 92 (3 ~ 182) 180
5260 17:58:15.827836 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5261 17:58:15.831125 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5262 17:58:15.834177 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5263 17:58:15.834416 ==
5264 17:58:15.838020 Dram Type= 6, Freq= 0, CH_0, rank 1
5265 17:58:15.841333 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5266 17:58:15.841461 ==
5267 17:58:15.844500 DQS Delay:
5268 17:58:15.844629 DQS0 = 0, DQS1 = 0
5269 17:58:15.847523 DQM Delay:
5270 17:58:15.847664 DQM0 = 97, DQM1 = 86
5271 17:58:15.847768 DQ Delay:
5272 17:58:15.851127 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =90
5273 17:58:15.854648 DQ4 =102, DQ5 =90, DQ6 =104, DQ7 =108
5274 17:58:15.857821 DQ8 =74, DQ9 =72, DQ10 =88, DQ11 =78
5275 17:58:15.864424 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =96
5276 17:58:15.864570
5277 17:58:15.864641
5278 17:58:15.870761 [DQSOSCAuto] RK1, (LSB)MR18= 0x2727, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5279 17:58:15.873994 CH0 RK1: MR19=505, MR18=2727
5280 17:58:15.880529 CH0_RK1: MR19=0x505, MR18=0x2727, DQSOSC=409, MR23=63, INC=64, DEC=43
5281 17:58:15.883723 [RxdqsGatingPostProcess] freq 933
5282 17:58:15.887556 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5283 17:58:15.890650 Pre-setting of DQS Precalculation
5284 17:58:15.896825 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5285 17:58:15.896917 ==
5286 17:58:15.900309 Dram Type= 6, Freq= 0, CH_1, rank 0
5287 17:58:15.903510 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5288 17:58:15.903594 ==
5289 17:58:15.910481 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5290 17:58:15.916997 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5291 17:58:15.920191 [CA 0] Center 37 (7~68) winsize 62
5292 17:58:15.923363 [CA 1] Center 37 (6~68) winsize 63
5293 17:58:15.926810 [CA 2] Center 34 (4~65) winsize 62
5294 17:58:15.929864 [CA 3] Center 34 (4~65) winsize 62
5295 17:58:15.933640 [CA 4] Center 33 (2~64) winsize 63
5296 17:58:15.936741 [CA 5] Center 33 (3~64) winsize 62
5297 17:58:15.936826
5298 17:58:15.939899 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5299 17:58:15.939983
5300 17:58:15.943076 [CATrainingPosCal] consider 1 rank data
5301 17:58:15.946379 u2DelayCellTimex100 = 270/100 ps
5302 17:58:15.949565 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5303 17:58:15.953371 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5304 17:58:15.956477 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5305 17:58:15.959672 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5306 17:58:15.962954 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5307 17:58:15.966230 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5308 17:58:15.966312
5309 17:58:15.969912 CA PerBit enable=1, Macro0, CA PI delay=33
5310 17:58:15.972862
5311 17:58:15.972943 [CBTSetCACLKResult] CA Dly = 33
5312 17:58:15.976441 CS Dly: 5 (0~36)
5313 17:58:15.976522 ==
5314 17:58:15.979501 Dram Type= 6, Freq= 0, CH_1, rank 1
5315 17:58:15.983455 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5316 17:58:15.983541 ==
5317 17:58:15.989729 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5318 17:58:15.996038 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5319 17:58:15.999771 [CA 0] Center 37 (6~68) winsize 63
5320 17:58:16.002888 [CA 1] Center 37 (6~68) winsize 63
5321 17:58:16.005898 [CA 2] Center 34 (4~65) winsize 62
5322 17:58:16.009574 [CA 3] Center 34 (3~65) winsize 63
5323 17:58:16.012869 [CA 4] Center 33 (3~64) winsize 62
5324 17:58:16.015894 [CA 5] Center 33 (3~64) winsize 62
5325 17:58:16.016031
5326 17:58:16.019129 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5327 17:58:16.019229
5328 17:58:16.022449 [CATrainingPosCal] consider 2 rank data
5329 17:58:16.025614 u2DelayCellTimex100 = 270/100 ps
5330 17:58:16.028742 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5331 17:58:16.032635 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5332 17:58:16.035959 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5333 17:58:16.039282 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5334 17:58:16.042349 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5335 17:58:16.048747 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5336 17:58:16.048880
5337 17:58:16.052057 CA PerBit enable=1, Macro0, CA PI delay=33
5338 17:58:16.052216
5339 17:58:16.055775 [CBTSetCACLKResult] CA Dly = 33
5340 17:58:16.055861 CS Dly: 5 (0~37)
5341 17:58:16.055924
5342 17:58:16.059090 ----->DramcWriteLeveling(PI) begin...
5343 17:58:16.059198 ==
5344 17:58:16.062228 Dram Type= 6, Freq= 0, CH_1, rank 0
5345 17:58:16.068507 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5346 17:58:16.068691 ==
5347 17:58:16.071894 Write leveling (Byte 0): 24 => 24
5348 17:58:16.071979 Write leveling (Byte 1): 25 => 25
5349 17:58:16.075186 DramcWriteLeveling(PI) end<-----
5350 17:58:16.075265
5351 17:58:16.078251 ==
5352 17:58:16.078330 Dram Type= 6, Freq= 0, CH_1, rank 0
5353 17:58:16.084766 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5354 17:58:16.084871 ==
5355 17:58:16.088262 [Gating] SW mode calibration
5356 17:58:16.094970 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5357 17:58:16.097973 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5358 17:58:16.104774 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 17:58:16.108063 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 17:58:16.111933 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 17:58:16.118461 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 17:58:16.121606 0 10 16 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5363 17:58:16.124882 0 10 20 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
5364 17:58:16.131323 0 10 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5365 17:58:16.135088 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 17:58:16.138380 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 17:58:16.144851 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 17:58:16.147890 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 17:58:16.151630 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 17:58:16.158055 0 11 16 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
5371 17:58:16.161291 0 11 20 | B1->B0 | 2323 4343 | 0 0 | (0 0) (1 1)
5372 17:58:16.164540 0 11 24 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5373 17:58:16.170850 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 17:58:16.174094 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 17:58:16.177876 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 17:58:16.184306 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 17:58:16.187527 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 17:58:16.190731 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5379 17:58:16.197392 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5380 17:58:16.200372 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 17:58:16.203792 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 17:58:16.210583 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 17:58:16.213975 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 17:58:16.216811 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 17:58:16.223398 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 17:58:16.227117 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 17:58:16.230275 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 17:58:16.236819 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 17:58:16.240008 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 17:58:16.243230 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 17:58:16.250328 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 17:58:16.253649 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 17:58:16.256851 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 17:58:16.263491 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5395 17:58:16.263605 Total UI for P1: 0, mck2ui 16
5396 17:58:16.269791 best dqsien dly found for B0: ( 0, 14, 14)
5397 17:58:16.273482 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5398 17:58:16.276726 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5399 17:58:16.283221 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 17:58:16.283307 Total UI for P1: 0, mck2ui 16
5401 17:58:16.289698 best dqsien dly found for B1: ( 0, 14, 20)
5402 17:58:16.292879 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5403 17:58:16.296146 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5404 17:58:16.296254
5405 17:58:16.299945 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5406 17:58:16.303175 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5407 17:58:16.306494 [Gating] SW calibration Done
5408 17:58:16.306595 ==
5409 17:58:16.309648 Dram Type= 6, Freq= 0, CH_1, rank 0
5410 17:58:16.312571 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5411 17:58:16.312679 ==
5412 17:58:16.316395 RX Vref Scan: 0
5413 17:58:16.316500
5414 17:58:16.316603 RX Vref 0 -> 0, step: 1
5415 17:58:16.316690
5416 17:58:16.319561 RX Delay -80 -> 252, step: 8
5417 17:58:16.325924 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5418 17:58:16.329586 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5419 17:58:16.332846 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5420 17:58:16.336001 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5421 17:58:16.338966 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5422 17:58:16.342477 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5423 17:58:16.349398 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5424 17:58:16.352532 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5425 17:58:16.355829 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5426 17:58:16.359011 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5427 17:58:16.362135 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5428 17:58:16.369336 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5429 17:58:16.372070 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5430 17:58:16.375406 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5431 17:58:16.378632 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5432 17:58:16.381854 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5433 17:58:16.381934 ==
5434 17:58:16.385758 Dram Type= 6, Freq= 0, CH_1, rank 0
5435 17:58:16.391667 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5436 17:58:16.391773 ==
5437 17:58:16.391866 DQS Delay:
5438 17:58:16.395628 DQS0 = 0, DQS1 = 0
5439 17:58:16.395709 DQM Delay:
5440 17:58:16.395771 DQM0 = 96, DQM1 = 89
5441 17:58:16.398834 DQ Delay:
5442 17:58:16.402108 DQ0 =103, DQ1 =91, DQ2 =83, DQ3 =91
5443 17:58:16.405332 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5444 17:58:16.408657 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =79
5445 17:58:16.411789 DQ12 =99, DQ13 =103, DQ14 =95, DQ15 =103
5446 17:58:16.411868
5447 17:58:16.411930
5448 17:58:16.411987 ==
5449 17:58:16.415184 Dram Type= 6, Freq= 0, CH_1, rank 0
5450 17:58:16.418250 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5451 17:58:16.418329 ==
5452 17:58:16.418393
5453 17:58:16.418458
5454 17:58:16.421535 TX Vref Scan disable
5455 17:58:16.424823 == TX Byte 0 ==
5456 17:58:16.428579 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5457 17:58:16.431651 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5458 17:58:16.434935 == TX Byte 1 ==
5459 17:58:16.438080 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5460 17:58:16.441335 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5461 17:58:16.441414 ==
5462 17:58:16.444936 Dram Type= 6, Freq= 0, CH_1, rank 0
5463 17:58:16.451266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5464 17:58:16.451345 ==
5465 17:58:16.451407
5466 17:58:16.451464
5467 17:58:16.451519 TX Vref Scan disable
5468 17:58:16.455482 == TX Byte 0 ==
5469 17:58:16.458492 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5470 17:58:16.465651 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5471 17:58:16.465735 == TX Byte 1 ==
5472 17:58:16.468621 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5473 17:58:16.475266 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5474 17:58:16.475350
5475 17:58:16.475423 [DATLAT]
5476 17:58:16.475498 Freq=933, CH1 RK0
5477 17:58:16.475587
5478 17:58:16.478632 DATLAT Default: 0xd
5479 17:58:16.478710 0, 0xFFFF, sum = 0
5480 17:58:16.481600 1, 0xFFFF, sum = 0
5481 17:58:16.484879 2, 0xFFFF, sum = 0
5482 17:58:16.484959 3, 0xFFFF, sum = 0
5483 17:58:16.488726 4, 0xFFFF, sum = 0
5484 17:58:16.488848 5, 0xFFFF, sum = 0
5485 17:58:16.492050 6, 0xFFFF, sum = 0
5486 17:58:16.492130 7, 0xFFFF, sum = 0
5487 17:58:16.495344 8, 0xFFFF, sum = 0
5488 17:58:16.495462 9, 0xFFFF, sum = 0
5489 17:58:16.498647 10, 0x0, sum = 1
5490 17:58:16.498741 11, 0x0, sum = 2
5491 17:58:16.501795 12, 0x0, sum = 3
5492 17:58:16.501875 13, 0x0, sum = 4
5493 17:58:16.501938 best_step = 11
5494 17:58:16.505051
5495 17:58:16.505129 ==
5496 17:58:16.508240 Dram Type= 6, Freq= 0, CH_1, rank 0
5497 17:58:16.511512 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5498 17:58:16.511596 ==
5499 17:58:16.511659 RX Vref Scan: 1
5500 17:58:16.511718
5501 17:58:16.514608 RX Vref 0 -> 0, step: 1
5502 17:58:16.514722
5503 17:58:16.517870 RX Delay -69 -> 252, step: 4
5504 17:58:16.517951
5505 17:58:16.521721 Set Vref, RX VrefLevel [Byte0]: 51
5506 17:58:16.525047 [Byte1]: 50
5507 17:58:16.528311
5508 17:58:16.528392 Final RX Vref Byte 0 = 51 to rank0
5509 17:58:16.531567 Final RX Vref Byte 1 = 50 to rank0
5510 17:58:16.534645 Final RX Vref Byte 0 = 51 to rank1
5511 17:58:16.537771 Final RX Vref Byte 1 = 50 to rank1==
5512 17:58:16.541186 Dram Type= 6, Freq= 0, CH_1, rank 0
5513 17:58:16.548043 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5514 17:58:16.548130 ==
5515 17:58:16.548202 DQS Delay:
5516 17:58:16.551359 DQS0 = 0, DQS1 = 0
5517 17:58:16.551447 DQM Delay:
5518 17:58:16.551510 DQM0 = 94, DQM1 = 88
5519 17:58:16.554621 DQ Delay:
5520 17:58:16.557961 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =90
5521 17:58:16.561142 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =92
5522 17:58:16.564141 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =80
5523 17:58:16.567730 DQ12 =96, DQ13 =100, DQ14 =96, DQ15 =98
5524 17:58:16.567846
5525 17:58:16.567939
5526 17:58:16.574099 [DQSOSCAuto] RK0, (LSB)MR18= 0x3737, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5527 17:58:16.577502 CH1 RK0: MR19=505, MR18=3737
5528 17:58:16.584021 CH1_RK0: MR19=0x505, MR18=0x3737, DQSOSC=404, MR23=63, INC=66, DEC=44
5529 17:58:16.584116
5530 17:58:16.587446 ----->DramcWriteLeveling(PI) begin...
5531 17:58:16.587534 ==
5532 17:58:16.590967 Dram Type= 6, Freq= 0, CH_1, rank 1
5533 17:58:16.593994 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5534 17:58:16.594096 ==
5535 17:58:16.597442 Write leveling (Byte 0): 26 => 26
5536 17:58:16.600781 Write leveling (Byte 1): 26 => 26
5537 17:58:16.603924 DramcWriteLeveling(PI) end<-----
5538 17:58:16.604007
5539 17:58:16.604073 ==
5540 17:58:16.607733 Dram Type= 6, Freq= 0, CH_1, rank 1
5541 17:58:16.610892 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5542 17:58:16.610978 ==
5543 17:58:16.614204 [Gating] SW mode calibration
5544 17:58:16.620601 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5545 17:58:16.627485 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5546 17:58:16.630708 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5547 17:58:16.637194 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5548 17:58:16.640224 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 17:58:16.644163 0 10 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5550 17:58:16.650457 0 10 16 | B1->B0 | 3333 2525 | 1 0 | (1 1) (0 0)
5551 17:58:16.653785 0 10 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5552 17:58:16.656984 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5553 17:58:16.663816 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5554 17:58:16.667088 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5555 17:58:16.670010 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5556 17:58:16.677040 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 17:58:16.680254 0 11 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5558 17:58:16.683471 0 11 16 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
5559 17:58:16.689722 0 11 20 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5560 17:58:16.693227 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5561 17:58:16.696623 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5562 17:58:16.703294 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5563 17:58:16.706762 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 17:58:16.709980 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 17:58:16.716519 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5566 17:58:16.719893 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5567 17:58:16.723103 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5568 17:58:16.729477 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 17:58:16.732682 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 17:58:16.736557 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 17:58:16.742815 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 17:58:16.746102 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 17:58:16.749303 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 17:58:16.756343 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 17:58:16.759398 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 17:58:16.762716 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 17:58:16.769222 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 17:58:16.772909 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 17:58:16.775830 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 17:58:16.782860 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 17:58:16.786102 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5582 17:58:16.789259 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5583 17:58:16.792439 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5584 17:58:16.795731 Total UI for P1: 0, mck2ui 16
5585 17:58:16.799004 best dqsien dly found for B0: ( 0, 14, 14)
5586 17:58:16.805793 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 17:58:16.808880 Total UI for P1: 0, mck2ui 16
5588 17:58:16.812507 best dqsien dly found for B1: ( 0, 14, 20)
5589 17:58:16.815462 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5590 17:58:16.818794 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5591 17:58:16.818876
5592 17:58:16.822035 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5593 17:58:16.825737 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5594 17:58:16.829016 [Gating] SW calibration Done
5595 17:58:16.829127 ==
5596 17:58:16.832286 Dram Type= 6, Freq= 0, CH_1, rank 1
5597 17:58:16.835371 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5598 17:58:16.835452 ==
5599 17:58:16.838546 RX Vref Scan: 0
5600 17:58:16.838659
5601 17:58:16.841739 RX Vref 0 -> 0, step: 1
5602 17:58:16.841815
5603 17:58:16.841882 RX Delay -80 -> 252, step: 8
5604 17:58:16.849157 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5605 17:58:16.852278 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5606 17:58:16.855547 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5607 17:58:16.858670 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5608 17:58:16.861898 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5609 17:58:16.865208 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5610 17:58:16.872259 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5611 17:58:16.875502 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5612 17:58:16.878568 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5613 17:58:16.881829 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5614 17:58:16.884959 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5615 17:58:16.892164 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5616 17:58:16.895339 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5617 17:58:16.898595 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5618 17:58:16.901886 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5619 17:58:16.905169 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5620 17:58:16.905247 ==
5621 17:58:16.908467 Dram Type= 6, Freq= 0, CH_1, rank 1
5622 17:58:16.915445 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5623 17:58:16.915528 ==
5624 17:58:16.915590 DQS Delay:
5625 17:58:16.918504 DQS0 = 0, DQS1 = 0
5626 17:58:16.918584 DQM Delay:
5627 17:58:16.921718 DQM0 = 96, DQM1 = 89
5628 17:58:16.921796 DQ Delay:
5629 17:58:16.924805 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5630 17:58:16.928458 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5631 17:58:16.931501 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5632 17:58:16.934632 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5633 17:58:16.934757
5634 17:58:16.934832
5635 17:58:16.934890 ==
5636 17:58:16.937979 Dram Type= 6, Freq= 0, CH_1, rank 1
5637 17:58:16.941903 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5638 17:58:16.942028 ==
5639 17:58:16.942108
5640 17:58:16.942166
5641 17:58:16.945127 TX Vref Scan disable
5642 17:58:16.948353 == TX Byte 0 ==
5643 17:58:16.951446 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5644 17:58:16.954622 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5645 17:58:16.957823 == TX Byte 1 ==
5646 17:58:16.961493 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5647 17:58:16.964746 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5648 17:58:16.964829 ==
5649 17:58:16.967921 Dram Type= 6, Freq= 0, CH_1, rank 1
5650 17:58:16.970981 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5651 17:58:16.974447 ==
5652 17:58:16.974528
5653 17:58:16.974592
5654 17:58:16.974649 TX Vref Scan disable
5655 17:58:16.978123 == TX Byte 0 ==
5656 17:58:16.981295 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5657 17:58:16.988645 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5658 17:58:16.988750 == TX Byte 1 ==
5659 17:58:16.991826 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5660 17:58:16.998341 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5661 17:58:16.998428
5662 17:58:16.998490 [DATLAT]
5663 17:58:16.998548 Freq=933, CH1 RK1
5664 17:58:16.998604
5665 17:58:17.001598 DATLAT Default: 0xb
5666 17:58:17.001681 0, 0xFFFF, sum = 0
5667 17:58:17.004813 1, 0xFFFF, sum = 0
5668 17:58:17.007965 2, 0xFFFF, sum = 0
5669 17:58:17.008052 3, 0xFFFF, sum = 0
5670 17:58:17.011257 4, 0xFFFF, sum = 0
5671 17:58:17.011345 5, 0xFFFF, sum = 0
5672 17:58:17.014356 6, 0xFFFF, sum = 0
5673 17:58:17.014435 7, 0xFFFF, sum = 0
5674 17:58:17.018153 8, 0xFFFF, sum = 0
5675 17:58:17.018254 9, 0xFFFF, sum = 0
5676 17:58:17.021094 10, 0x0, sum = 1
5677 17:58:17.021200 11, 0x0, sum = 2
5678 17:58:17.024349 12, 0x0, sum = 3
5679 17:58:17.024430 13, 0x0, sum = 4
5680 17:58:17.024492 best_step = 11
5681 17:58:17.024549
5682 17:58:17.027564 ==
5683 17:58:17.031384 Dram Type= 6, Freq= 0, CH_1, rank 1
5684 17:58:17.034650 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5685 17:58:17.034757 ==
5686 17:58:17.034832 RX Vref Scan: 0
5687 17:58:17.034891
5688 17:58:17.037943 RX Vref 0 -> 0, step: 1
5689 17:58:17.038081
5690 17:58:17.041031 RX Delay -61 -> 252, step: 4
5691 17:58:17.044404 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5692 17:58:17.050945 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5693 17:58:17.054484 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5694 17:58:17.057837 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5695 17:58:17.061158 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5696 17:58:17.064507 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5697 17:58:17.071121 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5698 17:58:17.074423 iDelay=203, Bit 7, Center 96 (7 ~ 186) 180
5699 17:58:17.077607 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5700 17:58:17.080779 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5701 17:58:17.083998 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5702 17:58:17.090983 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5703 17:58:17.094054 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5704 17:58:17.097302 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5705 17:58:17.100460 iDelay=203, Bit 14, Center 98 (3 ~ 194) 192
5706 17:58:17.103748 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5707 17:58:17.103846 ==
5708 17:58:17.106805 Dram Type= 6, Freq= 0, CH_1, rank 1
5709 17:58:17.113347 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5710 17:58:17.113434 ==
5711 17:58:17.113500 DQS Delay:
5712 17:58:17.113561 DQS0 = 0, DQS1 = 0
5713 17:58:17.117282 DQM Delay:
5714 17:58:17.117365 DQM0 = 96, DQM1 = 88
5715 17:58:17.120536 DQ Delay:
5716 17:58:17.123763 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =94
5717 17:58:17.126775 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =96
5718 17:58:17.130439 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5719 17:58:17.133733 DQ12 =96, DQ13 =96, DQ14 =98, DQ15 =96
5720 17:58:17.133822
5721 17:58:17.133949
5722 17:58:17.140105 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5723 17:58:17.143321 CH1 RK1: MR19=505, MR18=1D1D
5724 17:58:17.149793 CH1_RK1: MR19=0x505, MR18=0x1D1D, DQSOSC=412, MR23=63, INC=63, DEC=42
5725 17:58:17.153525 [RxdqsGatingPostProcess] freq 933
5726 17:58:17.156449 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5727 17:58:17.159943 Pre-setting of DQS Precalculation
5728 17:58:17.166371 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5729 17:58:17.173216 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5730 17:58:17.179729 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5731 17:58:17.179825
5732 17:58:17.179890
5733 17:58:17.182985 [Calibration Summary] 1866 Mbps
5734 17:58:17.186149 CH 0, Rank 0
5735 17:58:17.186231 SW Impedance : PASS
5736 17:58:17.190021 DUTY Scan : NO K
5737 17:58:17.190111 ZQ Calibration : PASS
5738 17:58:17.193029 Jitter Meter : NO K
5739 17:58:17.196292 CBT Training : PASS
5740 17:58:17.196375 Write leveling : PASS
5741 17:58:17.200070 RX DQS gating : PASS
5742 17:58:17.203225 RX DQ/DQS(RDDQC) : PASS
5743 17:58:17.203315 TX DQ/DQS : PASS
5744 17:58:17.206447 RX DATLAT : PASS
5745 17:58:17.209695 RX DQ/DQS(Engine): PASS
5746 17:58:17.209777 TX OE : NO K
5747 17:58:17.212853 All Pass.
5748 17:58:17.212935
5749 17:58:17.212998 CH 0, Rank 1
5750 17:58:17.216122 SW Impedance : PASS
5751 17:58:17.216203 DUTY Scan : NO K
5752 17:58:17.219330 ZQ Calibration : PASS
5753 17:58:17.222560 Jitter Meter : NO K
5754 17:58:17.222642 CBT Training : PASS
5755 17:58:17.225713 Write leveling : PASS
5756 17:58:17.229549 RX DQS gating : PASS
5757 17:58:17.229649 RX DQ/DQS(RDDQC) : PASS
5758 17:58:17.232692 TX DQ/DQS : PASS
5759 17:58:17.235784 RX DATLAT : PASS
5760 17:58:17.235866 RX DQ/DQS(Engine): PASS
5761 17:58:17.239515 TX OE : NO K
5762 17:58:17.239597 All Pass.
5763 17:58:17.239662
5764 17:58:17.242705 CH 1, Rank 0
5765 17:58:17.242786 SW Impedance : PASS
5766 17:58:17.245977 DUTY Scan : NO K
5767 17:58:17.246069 ZQ Calibration : PASS
5768 17:58:17.249190 Jitter Meter : NO K
5769 17:58:17.253058 CBT Training : PASS
5770 17:58:17.253138 Write leveling : PASS
5771 17:58:17.256205 RX DQS gating : PASS
5772 17:58:17.259411 RX DQ/DQS(RDDQC) : PASS
5773 17:58:17.259490 TX DQ/DQS : PASS
5774 17:58:17.262501 RX DATLAT : PASS
5775 17:58:17.266221 RX DQ/DQS(Engine): PASS
5776 17:58:17.266304 TX OE : NO K
5777 17:58:17.269453 All Pass.
5778 17:58:17.269531
5779 17:58:17.269593 CH 1, Rank 1
5780 17:58:17.272657 SW Impedance : PASS
5781 17:58:17.272736 DUTY Scan : NO K
5782 17:58:17.276222 ZQ Calibration : PASS
5783 17:58:17.279074 Jitter Meter : NO K
5784 17:58:17.279153 CBT Training : PASS
5785 17:58:17.282384 Write leveling : PASS
5786 17:58:17.285551 RX DQS gating : PASS
5787 17:58:17.285630 RX DQ/DQS(RDDQC) : PASS
5788 17:58:17.289323 TX DQ/DQS : PASS
5789 17:58:17.292466 RX DATLAT : PASS
5790 17:58:17.292580 RX DQ/DQS(Engine): PASS
5791 17:58:17.295467 TX OE : NO K
5792 17:58:17.295550 All Pass.
5793 17:58:17.295614
5794 17:58:17.299300 DramC Write-DBI off
5795 17:58:17.299394 PER_BANK_REFRESH: Hybrid Mode
5796 17:58:17.302460 TX_TRACKING: ON
5797 17:58:17.312113 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5798 17:58:17.315897 [FAST_K] Save calibration result to emmc
5799 17:58:17.319209 dramc_set_vcore_voltage set vcore to 650000
5800 17:58:17.322459 Read voltage for 400, 6
5801 17:58:17.322538 Vio18 = 0
5802 17:58:17.322601 Vcore = 650000
5803 17:58:17.325754 Vdram = 0
5804 17:58:17.325833 Vddq = 0
5805 17:58:17.325894 Vmddr = 0
5806 17:58:17.332227 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5807 17:58:17.335530 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5808 17:58:17.338534 MEM_TYPE=3, freq_sel=20
5809 17:58:17.342404 sv_algorithm_assistance_LP4_800
5810 17:58:17.345455 ============ PULL DRAM RESETB DOWN ============
5811 17:58:17.348957 ========== PULL DRAM RESETB DOWN end =========
5812 17:58:17.355462 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5813 17:58:17.358634 ===================================
5814 17:58:17.358734 LPDDR4 DRAM CONFIGURATION
5815 17:58:17.361892 ===================================
5816 17:58:17.365172 EX_ROW_EN[0] = 0x0
5817 17:58:17.368263 EX_ROW_EN[1] = 0x0
5818 17:58:17.368339 LP4Y_EN = 0x0
5819 17:58:17.372117 WORK_FSP = 0x0
5820 17:58:17.372196 WL = 0x2
5821 17:58:17.375370 RL = 0x2
5822 17:58:17.375448 BL = 0x2
5823 17:58:17.378592 RPST = 0x0
5824 17:58:17.378671 RD_PRE = 0x0
5825 17:58:17.381775 WR_PRE = 0x1
5826 17:58:17.381857 WR_PST = 0x0
5827 17:58:17.385070 DBI_WR = 0x0
5828 17:58:17.385149 DBI_RD = 0x0
5829 17:58:17.388952 OTF = 0x1
5830 17:58:17.392018 ===================================
5831 17:58:17.394967 ===================================
5832 17:58:17.395047 ANA top config
5833 17:58:17.398449 ===================================
5834 17:58:17.401800 DLL_ASYNC_EN = 0
5835 17:58:17.404974 ALL_SLAVE_EN = 1
5836 17:58:17.407950 NEW_RANK_MODE = 1
5837 17:58:17.408033 DLL_IDLE_MODE = 1
5838 17:58:17.411223 LP45_APHY_COMB_EN = 1
5839 17:58:17.414580 TX_ODT_DIS = 1
5840 17:58:17.418409 NEW_8X_MODE = 1
5841 17:58:17.421561 ===================================
5842 17:58:17.424871 ===================================
5843 17:58:17.427982 data_rate = 800
5844 17:58:17.428062 CKR = 1
5845 17:58:17.431138 DQ_P2S_RATIO = 4
5846 17:58:17.434387 ===================================
5847 17:58:17.438170 CA_P2S_RATIO = 4
5848 17:58:17.441434 DQ_CA_OPEN = 0
5849 17:58:17.444506 DQ_SEMI_OPEN = 1
5850 17:58:17.447683 CA_SEMI_OPEN = 1
5851 17:58:17.447763 CA_FULL_RATE = 0
5852 17:58:17.451364 DQ_CKDIV4_EN = 0
5853 17:58:17.454547 CA_CKDIV4_EN = 1
5854 17:58:17.457493 CA_PREDIV_EN = 0
5855 17:58:17.461310 PH8_DLY = 0
5856 17:58:17.464422 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5857 17:58:17.464503 DQ_AAMCK_DIV = 0
5858 17:58:17.467571 CA_AAMCK_DIV = 0
5859 17:58:17.470825 CA_ADMCK_DIV = 4
5860 17:58:17.473879 DQ_TRACK_CA_EN = 0
5861 17:58:17.477794 CA_PICK = 800
5862 17:58:17.481068 CA_MCKIO = 400
5863 17:58:17.484172 MCKIO_SEMI = 400
5864 17:58:17.487404 PLL_FREQ = 3016
5865 17:58:17.487485 DQ_UI_PI_RATIO = 32
5866 17:58:17.490642 CA_UI_PI_RATIO = 32
5867 17:58:17.493719 ===================================
5868 17:58:17.497002 ===================================
5869 17:58:17.500258 memory_type:LPDDR4
5870 17:58:17.504120 GP_NUM : 10
5871 17:58:17.504201 SRAM_EN : 1
5872 17:58:17.507189 MD32_EN : 0
5873 17:58:17.510349 ===================================
5874 17:58:17.513870 [ANA_INIT] >>>>>>>>>>>>>>
5875 17:58:17.513995 <<<<<< [CONFIGURE PHASE]: ANA_TX
5876 17:58:17.516799 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5877 17:58:17.520335 ===================================
5878 17:58:17.523908 data_rate = 800,PCW = 0X7400
5879 17:58:17.526809 ===================================
5880 17:58:17.530132 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5881 17:58:17.536858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5882 17:58:17.546915 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5883 17:58:17.553177 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5884 17:58:17.556410 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5885 17:58:17.559719 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5886 17:58:17.563537 [ANA_INIT] flow start
5887 17:58:17.563618 [ANA_INIT] PLL >>>>>>>>
5888 17:58:17.566527 [ANA_INIT] PLL <<<<<<<<
5889 17:58:17.570050 [ANA_INIT] MIDPI >>>>>>>>
5890 17:58:17.570145 [ANA_INIT] MIDPI <<<<<<<<
5891 17:58:17.573326 [ANA_INIT] DLL >>>>>>>>
5892 17:58:17.576573 [ANA_INIT] flow end
5893 17:58:17.579764 ============ LP4 DIFF to SE enter ============
5894 17:58:17.583453 ============ LP4 DIFF to SE exit ============
5895 17:58:17.586609 [ANA_INIT] <<<<<<<<<<<<<
5896 17:58:17.589863 [Flow] Enable top DCM control >>>>>
5897 17:58:17.592934 [Flow] Enable top DCM control <<<<<
5898 17:58:17.596096 Enable DLL master slave shuffle
5899 17:58:17.600069 ==============================================================
5900 17:58:17.603270 Gating Mode config
5901 17:58:17.609705 ==============================================================
5902 17:58:17.609797 Config description:
5903 17:58:17.619811 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5904 17:58:17.626203 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5905 17:58:17.629273 SELPH_MODE 0: By rank 1: By Phase
5906 17:58:17.635928 ==============================================================
5907 17:58:17.639351 GAT_TRACK_EN = 0
5908 17:58:17.642317 RX_GATING_MODE = 2
5909 17:58:17.645955 RX_GATING_TRACK_MODE = 2
5910 17:58:17.648913 SELPH_MODE = 1
5911 17:58:17.652188 PICG_EARLY_EN = 1
5912 17:58:17.656007 VALID_LAT_VALUE = 1
5913 17:58:17.659334 ==============================================================
5914 17:58:17.662406 Enter into Gating configuration >>>>
5915 17:58:17.665609 Exit from Gating configuration <<<<
5916 17:58:17.668877 Enter into DVFS_PRE_config >>>>>
5917 17:58:17.682016 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5918 17:58:17.685267 Exit from DVFS_PRE_config <<<<<
5919 17:58:17.688485 Enter into PICG configuration >>>>
5920 17:58:17.692353 Exit from PICG configuration <<<<
5921 17:58:17.692434 [RX_INPUT] configuration >>>>>
5922 17:58:17.695367 [RX_INPUT] configuration <<<<<
5923 17:58:17.701852 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5924 17:58:17.705092 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5925 17:58:17.712147 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5926 17:58:17.718671 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5927 17:58:17.724970 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5928 17:58:17.732008 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5929 17:58:17.735111 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5930 17:58:17.738336 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5931 17:58:17.745164 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5932 17:58:17.748140 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5933 17:58:17.751686 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5934 17:58:17.755211 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5935 17:58:17.758135 ===================================
5936 17:58:17.761628 LPDDR4 DRAM CONFIGURATION
5937 17:58:17.764831 ===================================
5938 17:58:17.767990 EX_ROW_EN[0] = 0x0
5939 17:58:17.768071 EX_ROW_EN[1] = 0x0
5940 17:58:17.771164 LP4Y_EN = 0x0
5941 17:58:17.771244 WORK_FSP = 0x0
5942 17:58:17.774852 WL = 0x2
5943 17:58:17.774934 RL = 0x2
5944 17:58:17.777997 BL = 0x2
5945 17:58:17.778100 RPST = 0x0
5946 17:58:17.781093 RD_PRE = 0x0
5947 17:58:17.784710 WR_PRE = 0x1
5948 17:58:17.784792 WR_PST = 0x0
5949 17:58:17.787806 DBI_WR = 0x0
5950 17:58:17.787880 DBI_RD = 0x0
5951 17:58:17.791009 OTF = 0x1
5952 17:58:17.794708 ===================================
5953 17:58:17.797833 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5954 17:58:17.801032 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5955 17:58:17.804167 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5956 17:58:17.807240 ===================================
5957 17:58:17.811126 LPDDR4 DRAM CONFIGURATION
5958 17:58:17.814400 ===================================
5959 17:58:17.817501 EX_ROW_EN[0] = 0x10
5960 17:58:17.817581 EX_ROW_EN[1] = 0x0
5961 17:58:17.820752 LP4Y_EN = 0x0
5962 17:58:17.820831 WORK_FSP = 0x0
5963 17:58:17.823912 WL = 0x2
5964 17:58:17.823988 RL = 0x2
5965 17:58:17.827749 BL = 0x2
5966 17:58:17.827822 RPST = 0x0
5967 17:58:17.830840 RD_PRE = 0x0
5968 17:58:17.834137 WR_PRE = 0x1
5969 17:58:17.834214 WR_PST = 0x0
5970 17:58:17.837168 DBI_WR = 0x0
5971 17:58:17.837245 DBI_RD = 0x0
5972 17:58:17.840508 OTF = 0x1
5973 17:58:17.843716 ===================================
5974 17:58:17.846911 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5975 17:58:17.852518 nWR fixed to 30
5976 17:58:17.855787 [ModeRegInit_LP4] CH0 RK0
5977 17:58:17.855861 [ModeRegInit_LP4] CH0 RK1
5978 17:58:17.859250 [ModeRegInit_LP4] CH1 RK0
5979 17:58:17.862338 [ModeRegInit_LP4] CH1 RK1
5980 17:58:17.862415 match AC timing 18
5981 17:58:17.869105 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5982 17:58:17.872813 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5983 17:58:17.875927 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5984 17:58:17.882239 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5985 17:58:17.885482 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5986 17:58:17.885562 ==
5987 17:58:17.889224 Dram Type= 6, Freq= 0, CH_0, rank 0
5988 17:58:17.892191 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5989 17:58:17.892272 ==
5990 17:58:17.898954 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5991 17:58:17.905330 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5992 17:58:17.908560 [CA 0] Center 36 (8~64) winsize 57
5993 17:58:17.911783 [CA 1] Center 36 (8~64) winsize 57
5994 17:58:17.915577 [CA 2] Center 36 (8~64) winsize 57
5995 17:58:17.918920 [CA 3] Center 36 (8~64) winsize 57
5996 17:58:17.921993 [CA 4] Center 36 (8~64) winsize 57
5997 17:58:17.925302 [CA 5] Center 36 (8~64) winsize 57
5998 17:58:17.925378
5999 17:58:17.928458 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6000 17:58:17.928531
6001 17:58:17.931670 [CATrainingPosCal] consider 1 rank data
6002 17:58:17.934949 u2DelayCellTimex100 = 270/100 ps
6003 17:58:17.938756 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6004 17:58:17.941969 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6005 17:58:17.945184 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6006 17:58:17.948428 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6007 17:58:17.951637 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6008 17:58:17.954817 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6009 17:58:17.954914
6010 17:58:17.958570 CA PerBit enable=1, Macro0, CA PI delay=36
6011 17:58:17.958650
6012 17:58:17.961671 [CBTSetCACLKResult] CA Dly = 36
6013 17:58:17.965252 CS Dly: 1 (0~32)
6014 17:58:17.965332 ==
6015 17:58:17.968096 Dram Type= 6, Freq= 0, CH_0, rank 1
6016 17:58:17.971292 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6017 17:58:17.971374 ==
6018 17:58:17.977993 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6019 17:58:17.984584 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6020 17:58:17.988201 [CA 0] Center 36 (8~64) winsize 57
6021 17:58:17.991379 [CA 1] Center 36 (8~64) winsize 57
6022 17:58:17.991460 [CA 2] Center 36 (8~64) winsize 57
6023 17:58:17.994484 [CA 3] Center 36 (8~64) winsize 57
6024 17:58:17.998135 [CA 4] Center 36 (8~64) winsize 57
6025 17:58:18.001196 [CA 5] Center 36 (8~64) winsize 57
6026 17:58:18.001295
6027 17:58:18.004524 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6028 17:58:18.007970
6029 17:58:18.011060 [CATrainingPosCal] consider 2 rank data
6030 17:58:18.011162 u2DelayCellTimex100 = 270/100 ps
6031 17:58:18.017791 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6032 17:58:18.021008 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6033 17:58:18.024186 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6034 17:58:18.027942 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6035 17:58:18.031142 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6036 17:58:18.034326 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6037 17:58:18.034427
6038 17:58:18.037418 CA PerBit enable=1, Macro0, CA PI delay=36
6039 17:58:18.037521
6040 17:58:18.040702 [CBTSetCACLKResult] CA Dly = 36
6041 17:58:18.043801 CS Dly: 1 (0~32)
6042 17:58:18.043901
6043 17:58:18.047691 ----->DramcWriteLeveling(PI) begin...
6044 17:58:18.047791 ==
6045 17:58:18.050888 Dram Type= 6, Freq= 0, CH_0, rank 0
6046 17:58:18.054127 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6047 17:58:18.054227 ==
6048 17:58:18.057426 Write leveling (Byte 0): 32 => 0
6049 17:58:18.060543 Write leveling (Byte 1): 32 => 0
6050 17:58:18.063627 DramcWriteLeveling(PI) end<-----
6051 17:58:18.063727
6052 17:58:18.063817 ==
6053 17:58:18.067400 Dram Type= 6, Freq= 0, CH_0, rank 0
6054 17:58:18.070507 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6055 17:58:18.070588 ==
6056 17:58:18.074043 [Gating] SW mode calibration
6057 17:58:18.080309 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6058 17:58:18.087042 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6059 17:58:18.090502 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6060 17:58:18.093503 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6061 17:58:18.100373 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6062 17:58:18.103585 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6063 17:58:18.106900 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6064 17:58:18.113640 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6065 17:58:18.116595 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6066 17:58:18.119870 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6067 17:58:18.126444 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6068 17:58:18.129657 Total UI for P1: 0, mck2ui 16
6069 17:58:18.133382 best dqsien dly found for B0: ( 0, 10, 16)
6070 17:58:18.136560 Total UI for P1: 0, mck2ui 16
6071 17:58:18.139862 best dqsien dly found for B1: ( 0, 10, 24)
6072 17:58:18.142937 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6073 17:58:18.146688 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6074 17:58:18.146769
6075 17:58:18.149810 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6076 17:58:18.152960 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6077 17:58:18.156255 [Gating] SW calibration Done
6078 17:58:18.156336 ==
6079 17:58:18.159442 Dram Type= 6, Freq= 0, CH_0, rank 0
6080 17:58:18.163254 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6081 17:58:18.166339 ==
6082 17:58:18.166420 RX Vref Scan: 0
6083 17:58:18.166499
6084 17:58:18.169471 RX Vref 0 -> 0, step: 1
6085 17:58:18.169552
6086 17:58:18.172730 RX Delay -410 -> 252, step: 16
6087 17:58:18.175820 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6088 17:58:18.179447 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6089 17:58:18.182442 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6090 17:58:18.189144 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6091 17:58:18.192372 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6092 17:58:18.196242 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6093 17:58:18.199121 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6094 17:58:18.205847 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6095 17:58:18.209011 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6096 17:58:18.212218 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6097 17:58:18.215974 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6098 17:58:18.222322 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6099 17:58:18.225367 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6100 17:58:18.228959 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6101 17:58:18.235692 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6102 17:58:18.238481 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6103 17:58:18.238610 ==
6104 17:58:18.242165 Dram Type= 6, Freq= 0, CH_0, rank 0
6105 17:58:18.245241 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6106 17:58:18.245327 ==
6107 17:58:18.248432 DQS Delay:
6108 17:58:18.248513 DQS0 = 51, DQS1 = 59
6109 17:58:18.248577 DQM Delay:
6110 17:58:18.251690 DQM0 = 12, DQM1 = 16
6111 17:58:18.251771 DQ Delay:
6112 17:58:18.254943 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6113 17:58:18.258785 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6114 17:58:18.262000 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6115 17:58:18.265337 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6116 17:58:18.265418
6117 17:58:18.265482
6118 17:58:18.265541 ==
6119 17:58:18.268407 Dram Type= 6, Freq= 0, CH_0, rank 0
6120 17:58:18.271637 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6121 17:58:18.274905 ==
6122 17:58:18.274986
6123 17:58:18.275048
6124 17:58:18.275106 TX Vref Scan disable
6125 17:58:18.278686 == TX Byte 0 ==
6126 17:58:18.281891 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6127 17:58:18.285078 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6128 17:58:18.288157 == TX Byte 1 ==
6129 17:58:18.291790 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6130 17:58:18.294717 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6131 17:58:18.294818 ==
6132 17:58:18.298479 Dram Type= 6, Freq= 0, CH_0, rank 0
6133 17:58:18.304775 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6134 17:58:18.304856 ==
6135 17:58:18.304920
6136 17:58:18.304978
6137 17:58:18.305035 TX Vref Scan disable
6138 17:58:18.308046 == TX Byte 0 ==
6139 17:58:18.311659 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6140 17:58:18.317863 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6141 17:58:18.317945 == TX Byte 1 ==
6142 17:58:18.321403 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6143 17:58:18.327878 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6144 17:58:18.327959
6145 17:58:18.328023 [DATLAT]
6146 17:58:18.328082 Freq=400, CH0 RK0
6147 17:58:18.328141
6148 17:58:18.330991 DATLAT Default: 0xf
6149 17:58:18.331071 0, 0xFFFF, sum = 0
6150 17:58:18.334790 1, 0xFFFF, sum = 0
6151 17:58:18.337923 2, 0xFFFF, sum = 0
6152 17:58:18.338004 3, 0xFFFF, sum = 0
6153 17:58:18.341130 4, 0xFFFF, sum = 0
6154 17:58:18.341211 5, 0xFFFF, sum = 0
6155 17:58:18.344580 6, 0xFFFF, sum = 0
6156 17:58:18.344662 7, 0xFFFF, sum = 0
6157 17:58:18.347590 8, 0xFFFF, sum = 0
6158 17:58:18.347672 9, 0xFFFF, sum = 0
6159 17:58:18.351083 10, 0xFFFF, sum = 0
6160 17:58:18.351164 11, 0xFFFF, sum = 0
6161 17:58:18.354401 12, 0x0, sum = 1
6162 17:58:18.354492 13, 0x0, sum = 2
6163 17:58:18.357419 14, 0x0, sum = 3
6164 17:58:18.357500 15, 0x0, sum = 4
6165 17:58:18.361158 best_step = 13
6166 17:58:18.361239
6167 17:58:18.361320 ==
6168 17:58:18.364335 Dram Type= 6, Freq= 0, CH_0, rank 0
6169 17:58:18.367486 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6170 17:58:18.367568 ==
6171 17:58:18.370581 RX Vref Scan: 1
6172 17:58:18.370661
6173 17:58:18.370724 RX Vref 0 -> 0, step: 1
6174 17:58:18.370783
6175 17:58:18.374229 RX Delay -359 -> 252, step: 8
6176 17:58:18.374309
6177 17:58:18.377311 Set Vref, RX VrefLevel [Byte0]: 51
6178 17:58:18.380513 [Byte1]: 48
6179 17:58:18.385048
6180 17:58:18.385128 Final RX Vref Byte 0 = 51 to rank0
6181 17:58:18.388354 Final RX Vref Byte 1 = 48 to rank0
6182 17:58:18.391416 Final RX Vref Byte 0 = 51 to rank1
6183 17:58:18.394712 Final RX Vref Byte 1 = 48 to rank1==
6184 17:58:18.398379 Dram Type= 6, Freq= 0, CH_0, rank 0
6185 17:58:18.404626 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6186 17:58:18.404707 ==
6187 17:58:18.404771 DQS Delay:
6188 17:58:18.408382 DQS0 = 52, DQS1 = 68
6189 17:58:18.408462 DQM Delay:
6190 17:58:18.408526 DQM0 = 8, DQM1 = 16
6191 17:58:18.411597 DQ Delay:
6192 17:58:18.414832 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6193 17:58:18.414933 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6194 17:58:18.417923 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6195 17:58:18.421496 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6196 17:58:18.421580
6197 17:58:18.424598
6198 17:58:18.431473 [DQSOSCAuto] RK0, (LSB)MR18= 0x9696, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
6199 17:58:18.434528 CH0 RK0: MR19=C0C, MR18=9696
6200 17:58:18.441514 CH0_RK0: MR19=0xC0C, MR18=0x9696, DQSOSC=391, MR23=63, INC=386, DEC=257
6201 17:58:18.441595 ==
6202 17:58:18.444757 Dram Type= 6, Freq= 0, CH_0, rank 1
6203 17:58:18.447889 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6204 17:58:18.447970 ==
6205 17:58:18.451110 [Gating] SW mode calibration
6206 17:58:18.457971 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6207 17:58:18.464525 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6208 17:58:18.467360 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6209 17:58:18.471152 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6210 17:58:18.477399 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6211 17:58:18.481143 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6212 17:58:18.484343 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6213 17:58:18.490776 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6214 17:58:18.493938 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6215 17:58:18.497093 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6216 17:58:18.503814 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6217 17:58:18.503940 Total UI for P1: 0, mck2ui 16
6218 17:58:18.507583 best dqsien dly found for B0: ( 0, 10, 16)
6219 17:58:18.510779 Total UI for P1: 0, mck2ui 16
6220 17:58:18.513954 best dqsien dly found for B1: ( 0, 10, 24)
6221 17:58:18.520868 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6222 17:58:18.524018 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6223 17:58:18.524098
6224 17:58:18.527068 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6225 17:58:18.530683 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6226 17:58:18.533730 [Gating] SW calibration Done
6227 17:58:18.533812 ==
6228 17:58:18.536753 Dram Type= 6, Freq= 0, CH_0, rank 1
6229 17:58:18.540358 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6230 17:58:18.540460 ==
6231 17:58:18.543846 RX Vref Scan: 0
6232 17:58:18.543928
6233 17:58:18.543992 RX Vref 0 -> 0, step: 1
6234 17:58:18.544054
6235 17:58:18.546773 RX Delay -410 -> 252, step: 16
6236 17:58:18.553265 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6237 17:58:18.557092 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6238 17:58:18.560418 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6239 17:58:18.563511 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6240 17:58:18.570432 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6241 17:58:18.573436 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6242 17:58:18.576941 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6243 17:58:18.579820 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6244 17:58:18.586585 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6245 17:58:18.589810 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6246 17:58:18.593517 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6247 17:58:18.596696 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6248 17:58:18.603044 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6249 17:58:18.606546 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6250 17:58:18.609619 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6251 17:58:18.616249 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6252 17:58:18.616337 ==
6253 17:58:18.619520 Dram Type= 6, Freq= 0, CH_0, rank 1
6254 17:58:18.623243 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6255 17:58:18.623325 ==
6256 17:58:18.623390 DQS Delay:
6257 17:58:18.626488 DQS0 = 43, DQS1 = 59
6258 17:58:18.626605 DQM Delay:
6259 17:58:18.629642 DQM0 = 6, DQM1 = 15
6260 17:58:18.629753 DQ Delay:
6261 17:58:18.632885 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6262 17:58:18.636381 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6263 17:58:18.639399 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6264 17:58:18.642485 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6265 17:58:18.642587
6266 17:58:18.642678
6267 17:58:18.642765 ==
6268 17:58:18.646293 Dram Type= 6, Freq= 0, CH_0, rank 1
6269 17:58:18.649408 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6270 17:58:18.649509 ==
6271 17:58:18.649605
6272 17:58:18.649698
6273 17:58:18.652584 TX Vref Scan disable
6274 17:58:18.652681 == TX Byte 0 ==
6275 17:58:18.659278 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6276 17:58:18.662699 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6277 17:58:18.662797 == TX Byte 1 ==
6278 17:58:18.669311 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6279 17:58:18.672528 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6280 17:58:18.672639 ==
6281 17:58:18.675752 Dram Type= 6, Freq= 0, CH_0, rank 1
6282 17:58:18.678893 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6283 17:58:18.678994 ==
6284 17:58:18.679083
6285 17:58:18.679169
6286 17:58:18.682565 TX Vref Scan disable
6287 17:58:18.682671 == TX Byte 0 ==
6288 17:58:18.688988 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6289 17:58:18.692256 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6290 17:58:18.692337 == TX Byte 1 ==
6291 17:58:18.698957 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6292 17:58:18.702219 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6293 17:58:18.702301
6294 17:58:18.702363 [DATLAT]
6295 17:58:18.705780 Freq=400, CH0 RK1
6296 17:58:18.705861
6297 17:58:18.705923 DATLAT Default: 0xd
6298 17:58:18.708681 0, 0xFFFF, sum = 0
6299 17:58:18.708776 1, 0xFFFF, sum = 0
6300 17:58:18.711800 2, 0xFFFF, sum = 0
6301 17:58:18.711881 3, 0xFFFF, sum = 0
6302 17:58:18.715583 4, 0xFFFF, sum = 0
6303 17:58:18.718843 5, 0xFFFF, sum = 0
6304 17:58:18.718924 6, 0xFFFF, sum = 0
6305 17:58:18.721968 7, 0xFFFF, sum = 0
6306 17:58:18.722103 8, 0xFFFF, sum = 0
6307 17:58:18.725254 9, 0xFFFF, sum = 0
6308 17:58:18.725347 10, 0xFFFF, sum = 0
6309 17:58:18.728474 11, 0xFFFF, sum = 0
6310 17:58:18.728555 12, 0x0, sum = 1
6311 17:58:18.732125 13, 0x0, sum = 2
6312 17:58:18.732206 14, 0x0, sum = 3
6313 17:58:18.734798 15, 0x0, sum = 4
6314 17:58:18.734879 best_step = 13
6315 17:58:18.734942
6316 17:58:18.735001 ==
6317 17:58:18.738514 Dram Type= 6, Freq= 0, CH_0, rank 1
6318 17:58:18.741796 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6319 17:58:18.741877 ==
6320 17:58:18.744805 RX Vref Scan: 0
6321 17:58:18.744901
6322 17:58:18.748531 RX Vref 0 -> 0, step: 1
6323 17:58:18.748611
6324 17:58:18.748674 RX Delay -359 -> 252, step: 8
6325 17:58:18.757365 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6326 17:58:18.760580 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6327 17:58:18.763833 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6328 17:58:18.770510 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6329 17:58:18.774072 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6330 17:58:18.776907 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6331 17:58:18.780133 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6332 17:58:18.787177 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6333 17:58:18.790410 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6334 17:58:18.793624 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6335 17:58:18.796800 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6336 17:58:18.803337 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6337 17:58:18.806702 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6338 17:58:18.810059 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6339 17:58:18.813306 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6340 17:58:18.819756 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6341 17:58:18.819836 ==
6342 17:58:18.823554 Dram Type= 6, Freq= 0, CH_0, rank 1
6343 17:58:18.826727 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6344 17:58:18.826836 ==
6345 17:58:18.826917 DQS Delay:
6346 17:58:18.829940 DQS0 = 52, DQS1 = 64
6347 17:58:18.830080 DQM Delay:
6348 17:58:18.833128 DQM0 = 10, DQM1 = 13
6349 17:58:18.833231 DQ Delay:
6350 17:58:18.836423 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6351 17:58:18.840193 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =20
6352 17:58:18.843363 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6353 17:58:18.846422 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6354 17:58:18.846501
6355 17:58:18.846562
6356 17:58:18.853482 [DQSOSCAuto] RK1, (LSB)MR18= 0xb5b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6357 17:58:18.856565 CH0 RK1: MR19=C0C, MR18=B5B5
6358 17:58:18.862922 CH0_RK1: MR19=0xC0C, MR18=0xB5B5, DQSOSC=387, MR23=63, INC=394, DEC=262
6359 17:58:18.866180 [RxdqsGatingPostProcess] freq 400
6360 17:58:18.872780 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6361 17:58:18.876092 Pre-setting of DQS Precalculation
6362 17:58:18.879745 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6363 17:58:18.879825 ==
6364 17:58:18.882724 Dram Type= 6, Freq= 0, CH_1, rank 0
6365 17:58:18.886479 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6366 17:58:18.889610 ==
6367 17:58:18.892838 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6368 17:58:18.899233 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6369 17:58:18.903050 [CA 0] Center 36 (8~64) winsize 57
6370 17:58:18.905772 [CA 1] Center 36 (8~64) winsize 57
6371 17:58:18.909565 [CA 2] Center 36 (8~64) winsize 57
6372 17:58:18.912814 [CA 3] Center 36 (8~64) winsize 57
6373 17:58:18.915880 [CA 4] Center 36 (8~64) winsize 57
6374 17:58:18.919019 [CA 5] Center 36 (8~64) winsize 57
6375 17:58:18.919104
6376 17:58:18.922609 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6377 17:58:18.922681
6378 17:58:18.926117 [CATrainingPosCal] consider 1 rank data
6379 17:58:18.929167 u2DelayCellTimex100 = 270/100 ps
6380 17:58:18.932385 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6381 17:58:18.935862 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6382 17:58:18.939239 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6383 17:58:18.942422 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6384 17:58:18.945775 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6385 17:58:18.948899 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6386 17:58:18.949010
6387 17:58:18.952522 CA PerBit enable=1, Macro0, CA PI delay=36
6388 17:58:18.955748
6389 17:58:18.955826 [CBTSetCACLKResult] CA Dly = 36
6390 17:58:18.958966 CS Dly: 1 (0~32)
6391 17:58:18.959069 ==
6392 17:58:18.962115 Dram Type= 6, Freq= 0, CH_1, rank 1
6393 17:58:18.965756 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6394 17:58:18.965861 ==
6395 17:58:18.972061 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6396 17:58:18.979018 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6397 17:58:18.982278 [CA 0] Center 36 (8~64) winsize 57
6398 17:58:18.985324 [CA 1] Center 36 (8~64) winsize 57
6399 17:58:18.988680 [CA 2] Center 36 (8~64) winsize 57
6400 17:58:18.988784 [CA 3] Center 36 (8~64) winsize 57
6401 17:58:18.992357 [CA 4] Center 36 (8~64) winsize 57
6402 17:58:18.995652 [CA 5] Center 36 (8~64) winsize 57
6403 17:58:18.995755
6404 17:58:18.998787 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6405 17:58:19.002053
6406 17:58:19.005132 [CATrainingPosCal] consider 2 rank data
6407 17:58:19.008970 u2DelayCellTimex100 = 270/100 ps
6408 17:58:19.012145 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6409 17:58:19.015242 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6410 17:58:19.018495 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6411 17:58:19.022249 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6412 17:58:19.025450 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6413 17:58:19.028672 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6414 17:58:19.028751
6415 17:58:19.031786 CA PerBit enable=1, Macro0, CA PI delay=36
6416 17:58:19.031872
6417 17:58:19.035168 [CBTSetCACLKResult] CA Dly = 36
6418 17:58:19.038315 CS Dly: 1 (0~32)
6419 17:58:19.038400
6420 17:58:19.041814 ----->DramcWriteLeveling(PI) begin...
6421 17:58:19.041917 ==
6422 17:58:19.045312 Dram Type= 6, Freq= 0, CH_1, rank 0
6423 17:58:19.048212 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6424 17:58:19.048313 ==
6425 17:58:19.051725 Write leveling (Byte 0): 32 => 0
6426 17:58:19.055358 Write leveling (Byte 1): 32 => 0
6427 17:58:19.058445 DramcWriteLeveling(PI) end<-----
6428 17:58:19.058525
6429 17:58:19.058587 ==
6430 17:58:19.061567 Dram Type= 6, Freq= 0, CH_1, rank 0
6431 17:58:19.064681 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6432 17:58:19.064760 ==
6433 17:58:19.067916 [Gating] SW mode calibration
6434 17:58:19.074870 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6435 17:58:19.081211 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6436 17:58:19.085084 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6437 17:58:19.088156 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6438 17:58:19.094441 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 17:58:19.097996 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6440 17:58:19.101297 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 17:58:19.107723 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 17:58:19.111504 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 17:58:19.114804 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6444 17:58:19.121128 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 17:58:19.121208 Total UI for P1: 0, mck2ui 16
6446 17:58:19.127478 best dqsien dly found for B0: ( 0, 10, 16)
6447 17:58:19.127565 Total UI for P1: 0, mck2ui 16
6448 17:58:19.134368 best dqsien dly found for B1: ( 0, 10, 16)
6449 17:58:19.137655 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6450 17:58:19.141342 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6451 17:58:19.141427
6452 17:58:19.144260 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6453 17:58:19.147981 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6454 17:58:19.151053 [Gating] SW calibration Done
6455 17:58:19.151132 ==
6456 17:58:19.154002 Dram Type= 6, Freq= 0, CH_1, rank 0
6457 17:58:19.157791 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6458 17:58:19.157874 ==
6459 17:58:19.160625 RX Vref Scan: 0
6460 17:58:19.160700
6461 17:58:19.164090 RX Vref 0 -> 0, step: 1
6462 17:58:19.164170
6463 17:58:19.164232 RX Delay -410 -> 252, step: 16
6464 17:58:19.170905 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6465 17:58:19.174032 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6466 17:58:19.177166 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6467 17:58:19.180905 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6468 17:58:19.187064 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6469 17:58:19.190285 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6470 17:58:19.193925 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6471 17:58:19.200722 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6472 17:58:19.203688 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6473 17:58:19.207359 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6474 17:58:19.210692 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6475 17:58:19.217018 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6476 17:58:19.220212 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6477 17:58:19.223316 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6478 17:58:19.227159 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6479 17:58:19.233410 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6480 17:58:19.233519 ==
6481 17:58:19.236524 Dram Type= 6, Freq= 0, CH_1, rank 0
6482 17:58:19.240282 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6483 17:58:19.240387 ==
6484 17:58:19.240483 DQS Delay:
6485 17:58:19.243498 DQS0 = 43, DQS1 = 59
6486 17:58:19.243603 DQM Delay:
6487 17:58:19.246679 DQM0 = 6, DQM1 = 15
6488 17:58:19.246777 DQ Delay:
6489 17:58:19.249761 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6490 17:58:19.253435 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6491 17:58:19.256405 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6492 17:58:19.260080 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6493 17:58:19.260188
6494 17:58:19.260278
6495 17:58:19.260366 ==
6496 17:58:19.263184 Dram Type= 6, Freq= 0, CH_1, rank 0
6497 17:58:19.266438 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6498 17:58:19.266551 ==
6499 17:58:19.266648
6500 17:58:19.269606
6501 17:58:19.269713 TX Vref Scan disable
6502 17:58:19.273147 == TX Byte 0 ==
6503 17:58:19.276186 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6504 17:58:19.279910 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6505 17:58:19.282722 == TX Byte 1 ==
6506 17:58:19.286515 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6507 17:58:19.289489 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6508 17:58:19.289597 ==
6509 17:58:19.292607 Dram Type= 6, Freq= 0, CH_1, rank 0
6510 17:58:19.299544 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6511 17:58:19.299660 ==
6512 17:58:19.299762
6513 17:58:19.299854
6514 17:58:19.299940 TX Vref Scan disable
6515 17:58:19.302666 == TX Byte 0 ==
6516 17:58:19.305822 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6517 17:58:19.308899 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6518 17:58:19.312584 == TX Byte 1 ==
6519 17:58:19.315801 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6520 17:58:19.319014 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6521 17:58:19.322225
6522 17:58:19.322331 [DATLAT]
6523 17:58:19.322421 Freq=400, CH1 RK0
6524 17:58:19.322508
6525 17:58:19.325428 DATLAT Default: 0xf
6526 17:58:19.325538 0, 0xFFFF, sum = 0
6527 17:58:19.328708 1, 0xFFFF, sum = 0
6528 17:58:19.328825 2, 0xFFFF, sum = 0
6529 17:58:19.332456 3, 0xFFFF, sum = 0
6530 17:58:19.332565 4, 0xFFFF, sum = 0
6531 17:58:19.335820 5, 0xFFFF, sum = 0
6532 17:58:19.339010 6, 0xFFFF, sum = 0
6533 17:58:19.339146 7, 0xFFFF, sum = 0
6534 17:58:19.342165 8, 0xFFFF, sum = 0
6535 17:58:19.342258 9, 0xFFFF, sum = 0
6536 17:58:19.345308 10, 0xFFFF, sum = 0
6537 17:58:19.345417 11, 0xFFFF, sum = 0
6538 17:58:19.349216 12, 0x0, sum = 1
6539 17:58:19.349317 13, 0x0, sum = 2
6540 17:58:19.352394 14, 0x0, sum = 3
6541 17:58:19.352487 15, 0x0, sum = 4
6542 17:58:19.352562 best_step = 13
6543 17:58:19.355515
6544 17:58:19.355626 ==
6545 17:58:19.358487 Dram Type= 6, Freq= 0, CH_1, rank 0
6546 17:58:19.362296 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6547 17:58:19.362383 ==
6548 17:58:19.362449 RX Vref Scan: 1
6549 17:58:19.362517
6550 17:58:19.365076 RX Vref 0 -> 0, step: 1
6551 17:58:19.365157
6552 17:58:19.368694 RX Delay -359 -> 252, step: 8
6553 17:58:19.368775
6554 17:58:19.371933 Set Vref, RX VrefLevel [Byte0]: 51
6555 17:58:19.375350 [Byte1]: 50
6556 17:58:19.379175
6557 17:58:19.379251 Final RX Vref Byte 0 = 51 to rank0
6558 17:58:19.382256 Final RX Vref Byte 1 = 50 to rank0
6559 17:58:19.385788 Final RX Vref Byte 0 = 51 to rank1
6560 17:58:19.389277 Final RX Vref Byte 1 = 50 to rank1==
6561 17:58:19.392595 Dram Type= 6, Freq= 0, CH_1, rank 0
6562 17:58:19.398866 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6563 17:58:19.398950 ==
6564 17:58:19.399014 DQS Delay:
6565 17:58:19.402666 DQS0 = 48, DQS1 = 64
6566 17:58:19.402740 DQM Delay:
6567 17:58:19.402801 DQM0 = 8, DQM1 = 16
6568 17:58:19.405656 DQ Delay:
6569 17:58:19.409179 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =8
6570 17:58:19.409268 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6571 17:58:19.412430 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6572 17:58:19.415416 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6573 17:58:19.415489
6574 17:58:19.419035
6575 17:58:19.425392 [DQSOSCAuto] RK0, (LSB)MR18= 0xd8d8, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6576 17:58:19.428564 CH1 RK0: MR19=C0C, MR18=D8D8
6577 17:58:19.435541 CH1_RK0: MR19=0xC0C, MR18=0xD8D8, DQSOSC=383, MR23=63, INC=402, DEC=268
6578 17:58:19.435654 ==
6579 17:58:19.438706 Dram Type= 6, Freq= 0, CH_1, rank 1
6580 17:58:19.441810 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6581 17:58:19.441917 ==
6582 17:58:19.445687 [Gating] SW mode calibration
6583 17:58:19.451726 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6584 17:58:19.458626 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6585 17:58:19.461746 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6586 17:58:19.464871 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6587 17:58:19.471802 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6588 17:58:19.475158 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6589 17:58:19.478192 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6590 17:58:19.485432 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6591 17:58:19.488488 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6592 17:58:19.491619 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6593 17:58:19.498655 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6594 17:58:19.499053 Total UI for P1: 0, mck2ui 16
6595 17:58:19.501692 best dqsien dly found for B0: ( 0, 10, 16)
6596 17:58:19.505175 Total UI for P1: 0, mck2ui 16
6597 17:58:19.508688 best dqsien dly found for B1: ( 0, 10, 16)
6598 17:58:19.515262 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6599 17:58:19.518672 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6600 17:58:19.519433
6601 17:58:19.521896 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6602 17:58:19.524814 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6603 17:58:19.528981 [Gating] SW calibration Done
6604 17:58:19.529483 ==
6605 17:58:19.531658 Dram Type= 6, Freq= 0, CH_1, rank 1
6606 17:58:19.534908 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6607 17:58:19.535325 ==
6608 17:58:19.538176 RX Vref Scan: 0
6609 17:58:19.538635
6610 17:58:19.538967 RX Vref 0 -> 0, step: 1
6611 17:58:19.539268
6612 17:58:19.541824 RX Delay -410 -> 252, step: 16
6613 17:58:19.548236 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6614 17:58:19.551255 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6615 17:58:19.554556 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6616 17:58:19.558306 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6617 17:58:19.564553 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6618 17:58:19.567769 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6619 17:58:19.570931 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6620 17:58:19.574637 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6621 17:58:19.580931 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6622 17:58:19.584102 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6623 17:58:19.587175 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6624 17:58:19.590974 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6625 17:58:19.597375 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6626 17:58:19.600716 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6627 17:58:19.604350 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6628 17:58:19.610800 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6629 17:58:19.610880 ==
6630 17:58:19.613938 Dram Type= 6, Freq= 0, CH_1, rank 1
6631 17:58:19.617048 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6632 17:58:19.617127 ==
6633 17:58:19.617189 DQS Delay:
6634 17:58:19.620615 DQS0 = 35, DQS1 = 59
6635 17:58:19.620693 DQM Delay:
6636 17:58:19.624113 DQM0 = 3, DQM1 = 18
6637 17:58:19.624193 DQ Delay:
6638 17:58:19.626971 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6639 17:58:19.630411 DQ4 =0, DQ5 =16, DQ6 =8, DQ7 =0
6640 17:58:19.633972 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6641 17:58:19.637046 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6642 17:58:19.637125
6643 17:58:19.637186
6644 17:58:19.637242 ==
6645 17:58:19.640424 Dram Type= 6, Freq= 0, CH_1, rank 1
6646 17:58:19.643817 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6647 17:58:19.643898 ==
6648 17:58:19.643988
6649 17:58:19.644056
6650 17:58:19.647166 TX Vref Scan disable
6651 17:58:19.647245 == TX Byte 0 ==
6652 17:58:19.653784 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6653 17:58:19.656915 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6654 17:58:19.657015 == TX Byte 1 ==
6655 17:58:19.663448 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6656 17:58:19.666600 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6657 17:58:19.666675 ==
6658 17:58:19.670414 Dram Type= 6, Freq= 0, CH_1, rank 1
6659 17:58:19.673511 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6660 17:58:19.673645 ==
6661 17:58:19.673732
6662 17:58:19.673817
6663 17:58:19.676728 TX Vref Scan disable
6664 17:58:19.676821 == TX Byte 0 ==
6665 17:58:19.683147 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6666 17:58:19.687020 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6667 17:58:19.687120 == TX Byte 1 ==
6668 17:58:19.693464 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6669 17:58:19.696623 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6670 17:58:19.696721
6671 17:58:19.696815 [DATLAT]
6672 17:58:19.699678 Freq=400, CH1 RK1
6673 17:58:19.699767
6674 17:58:19.699829 DATLAT Default: 0xd
6675 17:58:19.703444 0, 0xFFFF, sum = 0
6676 17:58:19.703528 1, 0xFFFF, sum = 0
6677 17:58:19.706522 2, 0xFFFF, sum = 0
6678 17:58:19.706621 3, 0xFFFF, sum = 0
6679 17:58:19.709815 4, 0xFFFF, sum = 0
6680 17:58:19.709930 5, 0xFFFF, sum = 0
6681 17:58:19.713350 6, 0xFFFF, sum = 0
6682 17:58:19.713423 7, 0xFFFF, sum = 0
6683 17:58:19.716241 8, 0xFFFF, sum = 0
6684 17:58:19.716342 9, 0xFFFF, sum = 0
6685 17:58:19.720103 10, 0xFFFF, sum = 0
6686 17:58:19.723390 11, 0xFFFF, sum = 0
6687 17:58:19.723470 12, 0x0, sum = 1
6688 17:58:19.723534 13, 0x0, sum = 2
6689 17:58:19.726656 14, 0x0, sum = 3
6690 17:58:19.726725 15, 0x0, sum = 4
6691 17:58:19.729790 best_step = 13
6692 17:58:19.729856
6693 17:58:19.729912 ==
6694 17:58:19.732796 Dram Type= 6, Freq= 0, CH_1, rank 1
6695 17:58:19.736385 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6696 17:58:19.736458 ==
6697 17:58:19.739871 RX Vref Scan: 0
6698 17:58:19.739940
6699 17:58:19.740015 RX Vref 0 -> 0, step: 1
6700 17:58:19.742980
6701 17:58:19.743049 RX Delay -359 -> 252, step: 8
6702 17:58:19.751239 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6703 17:58:19.754640 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6704 17:58:19.757598 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6705 17:58:19.764177 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6706 17:58:19.767850 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6707 17:58:19.770975 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6708 17:58:19.774189 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6709 17:58:19.780709 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6710 17:58:19.784565 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6711 17:58:19.787708 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6712 17:58:19.790888 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6713 17:58:19.797197 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6714 17:58:19.801171 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6715 17:58:19.804247 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6716 17:58:19.807473 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6717 17:58:19.813708 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6718 17:58:19.813807 ==
6719 17:58:19.817290 Dram Type= 6, Freq= 0, CH_1, rank 1
6720 17:58:19.820631 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6721 17:58:19.820727 ==
6722 17:58:19.823591 DQS Delay:
6723 17:58:19.823663 DQS0 = 48, DQS1 = 64
6724 17:58:19.823722 DQM Delay:
6725 17:58:19.827230 DQM0 = 9, DQM1 = 15
6726 17:58:19.827298 DQ Delay:
6727 17:58:19.830495 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6728 17:58:19.833625 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6729 17:58:19.836795 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6730 17:58:19.840020 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6731 17:58:19.840105
6732 17:58:19.840227
6733 17:58:19.847053 [DQSOSCAuto] RK1, (LSB)MR18= 0xadad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6734 17:58:19.849923 CH1 RK1: MR19=C0C, MR18=ADAD
6735 17:58:19.857156 CH1_RK1: MR19=0xC0C, MR18=0xADAD, DQSOSC=388, MR23=63, INC=392, DEC=261
6736 17:58:19.860175 [RxdqsGatingPostProcess] freq 400
6737 17:58:19.866671 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6738 17:58:19.870169 Pre-setting of DQS Precalculation
6739 17:58:19.873254 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6740 17:58:19.879960 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6741 17:58:19.889619 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6742 17:58:19.889695
6743 17:58:19.889756
6744 17:58:19.889818 [Calibration Summary] 800 Mbps
6745 17:58:19.893371 CH 0, Rank 0
6746 17:58:19.893466 SW Impedance : PASS
6747 17:58:19.896507 DUTY Scan : NO K
6748 17:58:19.899681 ZQ Calibration : PASS
6749 17:58:19.899781 Jitter Meter : NO K
6750 17:58:19.902902 CBT Training : PASS
6751 17:58:19.906192 Write leveling : PASS
6752 17:58:19.906271 RX DQS gating : PASS
6753 17:58:19.909403 RX DQ/DQS(RDDQC) : PASS
6754 17:58:19.913157 TX DQ/DQS : PASS
6755 17:58:19.913236 RX DATLAT : PASS
6756 17:58:19.916434 RX DQ/DQS(Engine): PASS
6757 17:58:19.919629 TX OE : NO K
6758 17:58:19.919708 All Pass.
6759 17:58:19.919770
6760 17:58:19.919827 CH 0, Rank 1
6761 17:58:19.922686 SW Impedance : PASS
6762 17:58:19.926462 DUTY Scan : NO K
6763 17:58:19.926541 ZQ Calibration : PASS
6764 17:58:19.929609 Jitter Meter : NO K
6765 17:58:19.933219 CBT Training : PASS
6766 17:58:19.933299 Write leveling : NO K
6767 17:58:19.936132 RX DQS gating : PASS
6768 17:58:19.939298 RX DQ/DQS(RDDQC) : PASS
6769 17:58:19.939378 TX DQ/DQS : PASS
6770 17:58:19.943113 RX DATLAT : PASS
6771 17:58:19.946298 RX DQ/DQS(Engine): PASS
6772 17:58:19.946377 TX OE : NO K
6773 17:58:19.946440 All Pass.
6774 17:58:19.949459
6775 17:58:19.949537 CH 1, Rank 0
6776 17:58:19.952538 SW Impedance : PASS
6777 17:58:19.952617 DUTY Scan : NO K
6778 17:58:19.955922 ZQ Calibration : PASS
6779 17:58:19.956001 Jitter Meter : NO K
6780 17:58:19.959527 CBT Training : PASS
6781 17:58:19.962454 Write leveling : PASS
6782 17:58:19.962533 RX DQS gating : PASS
6783 17:58:19.965874 RX DQ/DQS(RDDQC) : PASS
6784 17:58:19.969091 TX DQ/DQS : PASS
6785 17:58:19.969171 RX DATLAT : PASS
6786 17:58:19.972686 RX DQ/DQS(Engine): PASS
6787 17:58:19.975808 TX OE : NO K
6788 17:58:19.975887 All Pass.
6789 17:58:19.975948
6790 17:58:19.976006 CH 1, Rank 1
6791 17:58:19.979299 SW Impedance : PASS
6792 17:58:19.982340 DUTY Scan : NO K
6793 17:58:19.982418 ZQ Calibration : PASS
6794 17:58:19.985778 Jitter Meter : NO K
6795 17:58:19.988897 CBT Training : PASS
6796 17:58:19.988977 Write leveling : NO K
6797 17:58:19.992128 RX DQS gating : PASS
6798 17:58:19.995890 RX DQ/DQS(RDDQC) : PASS
6799 17:58:19.995969 TX DQ/DQS : PASS
6800 17:58:19.999085 RX DATLAT : PASS
6801 17:58:20.002327 RX DQ/DQS(Engine): PASS
6802 17:58:20.002406 TX OE : NO K
6803 17:58:20.005422 All Pass.
6804 17:58:20.005500
6805 17:58:20.005562 DramC Write-DBI off
6806 17:58:20.008555 PER_BANK_REFRESH: Hybrid Mode
6807 17:58:20.008635 TX_TRACKING: ON
6808 17:58:20.018838 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6809 17:58:20.022195 [FAST_K] Save calibration result to emmc
6810 17:58:20.025400 dramc_set_vcore_voltage set vcore to 725000
6811 17:58:20.028565 Read voltage for 1600, 0
6812 17:58:20.028644 Vio18 = 0
6813 17:58:20.031774 Vcore = 725000
6814 17:58:20.031852 Vdram = 0
6815 17:58:20.031914 Vddq = 0
6816 17:58:20.035427 Vmddr = 0
6817 17:58:20.038549 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6818 17:58:20.045126 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6819 17:58:20.045207 MEM_TYPE=3, freq_sel=13
6820 17:58:20.048773 sv_algorithm_assistance_LP4_3733
6821 17:58:20.055170 ============ PULL DRAM RESETB DOWN ============
6822 17:58:20.058286 ========== PULL DRAM RESETB DOWN end =========
6823 17:58:20.061880 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6824 17:58:20.065077 ===================================
6825 17:58:20.068146 LPDDR4 DRAM CONFIGURATION
6826 17:58:20.071776 ===================================
6827 17:58:20.074608 EX_ROW_EN[0] = 0x0
6828 17:58:20.074687 EX_ROW_EN[1] = 0x0
6829 17:58:20.077852 LP4Y_EN = 0x0
6830 17:58:20.077932 WORK_FSP = 0x1
6831 17:58:20.081426 WL = 0x5
6832 17:58:20.081530 RL = 0x5
6833 17:58:20.084952 BL = 0x2
6834 17:58:20.085049 RPST = 0x0
6835 17:58:20.087821 RD_PRE = 0x0
6836 17:58:20.087893 WR_PRE = 0x1
6837 17:58:20.091568 WR_PST = 0x1
6838 17:58:20.091664 DBI_WR = 0x0
6839 17:58:20.094525 DBI_RD = 0x0
6840 17:58:20.094594 OTF = 0x1
6841 17:58:20.097955 ===================================
6842 17:58:20.101461 ===================================
6843 17:58:20.104599 ANA top config
6844 17:58:20.107813 ===================================
6845 17:58:20.110963 DLL_ASYNC_EN = 0
6846 17:58:20.111036 ALL_SLAVE_EN = 0
6847 17:58:20.114057 NEW_RANK_MODE = 1
6848 17:58:20.117923 DLL_IDLE_MODE = 1
6849 17:58:20.121183 LP45_APHY_COMB_EN = 1
6850 17:58:20.121286 TX_ODT_DIS = 0
6851 17:58:20.124342 NEW_8X_MODE = 1
6852 17:58:20.127459 ===================================
6853 17:58:20.130630 ===================================
6854 17:58:20.133796 data_rate = 3200
6855 17:58:20.137911 CKR = 1
6856 17:58:20.140399 DQ_P2S_RATIO = 8
6857 17:58:20.144316 ===================================
6858 17:58:20.147414 CA_P2S_RATIO = 8
6859 17:58:20.147506 DQ_CA_OPEN = 0
6860 17:58:20.150599 DQ_SEMI_OPEN = 0
6861 17:58:20.154071 CA_SEMI_OPEN = 0
6862 17:58:20.157319 CA_FULL_RATE = 0
6863 17:58:20.160540 DQ_CKDIV4_EN = 0
6864 17:58:20.163747 CA_CKDIV4_EN = 0
6865 17:58:20.166822 CA_PREDIV_EN = 0
6866 17:58:20.166903 PH8_DLY = 12
6867 17:58:20.170488 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6868 17:58:20.173755 DQ_AAMCK_DIV = 4
6869 17:58:20.176948 CA_AAMCK_DIV = 4
6870 17:58:20.180630 CA_ADMCK_DIV = 4
6871 17:58:20.183661 DQ_TRACK_CA_EN = 0
6872 17:58:20.183742 CA_PICK = 1600
6873 17:58:20.187147 CA_MCKIO = 1600
6874 17:58:20.190552 MCKIO_SEMI = 0
6875 17:58:20.193351 PLL_FREQ = 3068
6876 17:58:20.196996 DQ_UI_PI_RATIO = 32
6877 17:58:20.200352 CA_UI_PI_RATIO = 0
6878 17:58:20.203806 ===================================
6879 17:58:20.206750 ===================================
6880 17:58:20.206830 memory_type:LPDDR4
6881 17:58:20.210325 GP_NUM : 10
6882 17:58:20.213325 SRAM_EN : 1
6883 17:58:20.213423 MD32_EN : 0
6884 17:58:20.217121 ===================================
6885 17:58:20.220248 [ANA_INIT] >>>>>>>>>>>>>>
6886 17:58:20.223395 <<<<<< [CONFIGURE PHASE]: ANA_TX
6887 17:58:20.226617 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6888 17:58:20.229757 ===================================
6889 17:58:20.233467 data_rate = 3200,PCW = 0X7600
6890 17:58:20.236741 ===================================
6891 17:58:20.239975 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6892 17:58:20.246325 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6893 17:58:20.249492 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6894 17:58:20.256551 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6895 17:58:20.259433 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6896 17:58:20.262669 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6897 17:58:20.262750 [ANA_INIT] flow start
6898 17:58:20.266141 [ANA_INIT] PLL >>>>>>>>
6899 17:58:20.269157 [ANA_INIT] PLL <<<<<<<<
6900 17:58:20.269236 [ANA_INIT] MIDPI >>>>>>>>
6901 17:58:20.273082 [ANA_INIT] MIDPI <<<<<<<<
6902 17:58:20.276238 [ANA_INIT] DLL >>>>>>>>
6903 17:58:20.276318 [ANA_INIT] DLL <<<<<<<<
6904 17:58:20.279376 [ANA_INIT] flow end
6905 17:58:20.282649 ============ LP4 DIFF to SE enter ============
6906 17:58:20.288984 ============ LP4 DIFF to SE exit ============
6907 17:58:20.289079 [ANA_INIT] <<<<<<<<<<<<<
6908 17:58:20.292626 [Flow] Enable top DCM control >>>>>
6909 17:58:20.295766 [Flow] Enable top DCM control <<<<<
6910 17:58:20.299231 Enable DLL master slave shuffle
6911 17:58:20.305532 ==============================================================
6912 17:58:20.305642 Gating Mode config
6913 17:58:20.312204 ==============================================================
6914 17:58:20.315883 Config description:
6915 17:58:20.325398 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6916 17:58:20.332316 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6917 17:58:20.335536 SELPH_MODE 0: By rank 1: By Phase
6918 17:58:20.341971 ==============================================================
6919 17:58:20.345112 GAT_TRACK_EN = 1
6920 17:58:20.348292 RX_GATING_MODE = 2
6921 17:58:20.348372 RX_GATING_TRACK_MODE = 2
6922 17:58:20.352193 SELPH_MODE = 1
6923 17:58:20.355344 PICG_EARLY_EN = 1
6924 17:58:20.358438 VALID_LAT_VALUE = 1
6925 17:58:20.365298 ==============================================================
6926 17:58:20.368286 Enter into Gating configuration >>>>
6927 17:58:20.380751 Exit from Gating configuration <<<<
6928 17:58:20.380881 Enter into DVFS_PRE_config >>>>>
6929 17:58:20.384724 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6930 17:58:20.387932 Exit from DVFS_PRE_config <<<<<
6931 17:58:20.391043 Enter into PICG configuration >>>>
6932 17:58:20.394887 Exit from PICG configuration <<<<
6933 17:58:20.397806 [RX_INPUT] configuration >>>>>
6934 17:58:20.401348 [RX_INPUT] configuration <<<<<
6935 17:58:20.404712 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6936 17:58:20.410823 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6937 17:58:20.417503 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6938 17:58:20.424498 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6939 17:58:20.430764 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6940 17:58:20.434281 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6941 17:58:20.440588 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6942 17:58:20.444271 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6943 17:58:20.447472 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6944 17:58:20.450560 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6945 17:58:20.457454 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6946 17:58:20.460499 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6947 17:58:20.463616 ===================================
6948 17:58:20.467296 LPDDR4 DRAM CONFIGURATION
6949 17:58:20.470469 ===================================
6950 17:58:20.470553 EX_ROW_EN[0] = 0x0
6951 17:58:20.473683 EX_ROW_EN[1] = 0x0
6952 17:58:20.473777 LP4Y_EN = 0x0
6953 17:58:20.477313 WORK_FSP = 0x1
6954 17:58:20.477396 WL = 0x5
6955 17:58:20.480326 RL = 0x5
6956 17:58:20.483817 BL = 0x2
6957 17:58:20.483900 RPST = 0x0
6958 17:58:20.487131 RD_PRE = 0x0
6959 17:58:20.487213 WR_PRE = 0x1
6960 17:58:20.490082 WR_PST = 0x1
6961 17:58:20.490164 DBI_WR = 0x0
6962 17:58:20.493846 DBI_RD = 0x0
6963 17:58:20.493928 OTF = 0x1
6964 17:58:20.496915 ===================================
6965 17:58:20.500083 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6966 17:58:20.506839 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6967 17:58:20.509852 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6968 17:58:20.513287 ===================================
6969 17:58:20.516814 LPDDR4 DRAM CONFIGURATION
6970 17:58:20.519828 ===================================
6971 17:58:20.519912 EX_ROW_EN[0] = 0x10
6972 17:58:20.523265 EX_ROW_EN[1] = 0x0
6973 17:58:20.523347 LP4Y_EN = 0x0
6974 17:58:20.526873 WORK_FSP = 0x1
6975 17:58:20.526956 WL = 0x5
6976 17:58:20.529966 RL = 0x5
6977 17:58:20.532967 BL = 0x2
6978 17:58:20.533050 RPST = 0x0
6979 17:58:20.536417 RD_PRE = 0x0
6980 17:58:20.536499 WR_PRE = 0x1
6981 17:58:20.539806 WR_PST = 0x1
6982 17:58:20.539890 DBI_WR = 0x0
6983 17:58:20.542808 DBI_RD = 0x0
6984 17:58:20.542891 OTF = 0x1
6985 17:58:20.546530 ===================================
6986 17:58:20.552835 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6987 17:58:20.552937 ==
6988 17:58:20.556558 Dram Type= 6, Freq= 0, CH_0, rank 0
6989 17:58:20.559599 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6990 17:58:20.559683 ==
6991 17:58:20.562727 [Duty_Offset_Calibration]
6992 17:58:20.566497 B0:0 B1:2 CA:1
6993 17:58:20.566578
6994 17:58:20.569561 [DutyScan_Calibration_Flow] k_type=0
6995 17:58:20.578430
6996 17:58:20.578519 ==CLK 0==
6997 17:58:20.581595 Final CLK duty delay cell = 0
6998 17:58:20.584685 [0] MAX Duty = 5156%(X100), DQS PI = 22
6999 17:58:20.587922 [0] MIN Duty = 4938%(X100), DQS PI = 50
7000 17:58:20.591523 [0] AVG Duty = 5047%(X100)
7001 17:58:20.591608
7002 17:58:20.594431 CH0 CLK Duty spec in!! Max-Min= 218%
7003 17:58:20.597779 [DutyScan_Calibration_Flow] ====Done====
7004 17:58:20.597886
7005 17:58:20.601442 [DutyScan_Calibration_Flow] k_type=1
7006 17:58:20.617952
7007 17:58:20.618105 ==DQS 0 ==
7008 17:58:20.621627 Final DQS duty delay cell = 0
7009 17:58:20.625086 [0] MAX Duty = 5156%(X100), DQS PI = 34
7010 17:58:20.627882 [0] MIN Duty = 5031%(X100), DQS PI = 8
7011 17:58:20.631646 [0] AVG Duty = 5093%(X100)
7012 17:58:20.631756
7013 17:58:20.631850 ==DQS 1 ==
7014 17:58:20.635113 Final DQS duty delay cell = 0
7015 17:58:20.638050 [0] MAX Duty = 5031%(X100), DQS PI = 2
7016 17:58:20.641035 [0] MIN Duty = 4876%(X100), DQS PI = 18
7017 17:58:20.644542 [0] AVG Duty = 4953%(X100)
7018 17:58:20.644621
7019 17:58:20.648186 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7020 17:58:20.648261
7021 17:58:20.651180 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7022 17:58:20.654754 [DutyScan_Calibration_Flow] ====Done====
7023 17:58:20.654822
7024 17:58:20.657940 [DutyScan_Calibration_Flow] k_type=3
7025 17:58:20.675062
7026 17:58:20.675186 ==DQM 0 ==
7027 17:58:20.678199 Final DQM duty delay cell = 0
7028 17:58:20.681941 [0] MAX Duty = 5187%(X100), DQS PI = 22
7029 17:58:20.685183 [0] MIN Duty = 4876%(X100), DQS PI = 56
7030 17:58:20.688289 [0] AVG Duty = 5031%(X100)
7031 17:58:20.688379
7032 17:58:20.688464 ==DQM 1 ==
7033 17:58:20.691496 Final DQM duty delay cell = 0
7034 17:58:20.694840 [0] MAX Duty = 5031%(X100), DQS PI = 50
7035 17:58:20.698508 [0] MIN Duty = 4782%(X100), DQS PI = 14
7036 17:58:20.701561 [0] AVG Duty = 4906%(X100)
7037 17:58:20.701676
7038 17:58:20.705118 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7039 17:58:20.705203
7040 17:58:20.707952 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7041 17:58:20.711571 [DutyScan_Calibration_Flow] ====Done====
7042 17:58:20.711657
7043 17:58:20.714627 [DutyScan_Calibration_Flow] k_type=2
7044 17:58:20.731866
7045 17:58:20.732006 ==DQ 0 ==
7046 17:58:20.734980 Final DQ duty delay cell = 0
7047 17:58:20.738032 [0] MAX Duty = 5218%(X100), DQS PI = 18
7048 17:58:20.741560 [0] MIN Duty = 4938%(X100), DQS PI = 56
7049 17:58:20.744965 [0] AVG Duty = 5078%(X100)
7050 17:58:20.745074
7051 17:58:20.745165 ==DQ 1 ==
7052 17:58:20.747971 Final DQ duty delay cell = -4
7053 17:58:20.751797 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7054 17:58:20.754664 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7055 17:58:20.758329 [-4] AVG Duty = 4953%(X100)
7056 17:58:20.758413
7057 17:58:20.761487 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7058 17:58:20.761568
7059 17:58:20.764646 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7060 17:58:20.767918 [DutyScan_Calibration_Flow] ====Done====
7061 17:58:20.767999 ==
7062 17:58:20.771450 Dram Type= 6, Freq= 0, CH_1, rank 0
7063 17:58:20.774639 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7064 17:58:20.774724 ==
7065 17:58:20.777916 [Duty_Offset_Calibration]
7066 17:58:20.778043 B0:0 B1:4 CA:-5
7067 17:58:20.778129
7068 17:58:20.781056 [DutyScan_Calibration_Flow] k_type=0
7069 17:58:20.792240
7070 17:58:20.792350 ==CLK 0==
7071 17:58:20.795286 Final CLK duty delay cell = 0
7072 17:58:20.799119 [0] MAX Duty = 5156%(X100), DQS PI = 18
7073 17:58:20.802194 [0] MIN Duty = 4906%(X100), DQS PI = 50
7074 17:58:20.805185 [0] AVG Duty = 5031%(X100)
7075 17:58:20.805317
7076 17:58:20.808965 CH1 CLK Duty spec in!! Max-Min= 250%
7077 17:58:20.812089 [DutyScan_Calibration_Flow] ====Done====
7078 17:58:20.812173
7079 17:58:20.815001 [DutyScan_Calibration_Flow] k_type=1
7080 17:58:20.831303
7081 17:58:20.831413 ==DQS 0 ==
7082 17:58:20.834321 Final DQS duty delay cell = 0
7083 17:58:20.837999 [0] MAX Duty = 5156%(X100), DQS PI = 20
7084 17:58:20.840897 [0] MIN Duty = 4844%(X100), DQS PI = 44
7085 17:58:20.844407 [0] AVG Duty = 5000%(X100)
7086 17:58:20.844490
7087 17:58:20.844553 ==DQS 1 ==
7088 17:58:20.847536 Final DQS duty delay cell = -4
7089 17:58:20.851042 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7090 17:58:20.853869 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7091 17:58:20.857514 [-4] AVG Duty = 4922%(X100)
7092 17:58:20.857618
7093 17:58:20.860428 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7094 17:58:20.860504
7095 17:58:20.863931 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7096 17:58:20.867132 [DutyScan_Calibration_Flow] ====Done====
7097 17:58:20.867209
7098 17:58:20.870328 [DutyScan_Calibration_Flow] k_type=3
7099 17:58:20.886979
7100 17:58:20.887111 ==DQM 0 ==
7101 17:58:20.890055 Final DQM duty delay cell = -4
7102 17:58:20.893188 [-4] MAX Duty = 5062%(X100), DQS PI = 32
7103 17:58:20.896870 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7104 17:58:20.900077 [-4] AVG Duty = 4922%(X100)
7105 17:58:20.900151
7106 17:58:20.900214 ==DQM 1 ==
7107 17:58:20.903246 Final DQM duty delay cell = -4
7108 17:58:20.906782 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7109 17:58:20.909938 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7110 17:58:20.913081 [-4] AVG Duty = 5000%(X100)
7111 17:58:20.913187
7112 17:58:20.916843 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7113 17:58:20.916952
7114 17:58:20.919933 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7115 17:58:20.923398 [DutyScan_Calibration_Flow] ====Done====
7116 17:58:20.923501
7117 17:58:20.926711 [DutyScan_Calibration_Flow] k_type=2
7118 17:58:20.944526
7119 17:58:20.944635 ==DQ 0 ==
7120 17:58:20.947526 Final DQ duty delay cell = 0
7121 17:58:20.951073 [0] MAX Duty = 5093%(X100), DQS PI = 20
7122 17:58:20.954591 [0] MIN Duty = 4969%(X100), DQS PI = 46
7123 17:58:20.954694 [0] AVG Duty = 5031%(X100)
7124 17:58:20.957537
7125 17:58:20.957637 ==DQ 1 ==
7126 17:58:20.961118 Final DQ duty delay cell = 0
7127 17:58:20.964093 [0] MAX Duty = 5031%(X100), DQS PI = 2
7128 17:58:20.967445 [0] MIN Duty = 4876%(X100), DQS PI = 28
7129 17:58:20.967520 [0] AVG Duty = 4953%(X100)
7130 17:58:20.970930
7131 17:58:20.973950 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7132 17:58:20.974094
7133 17:58:20.977261 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7134 17:58:20.981000 [DutyScan_Calibration_Flow] ====Done====
7135 17:58:20.984109 nWR fixed to 30
7136 17:58:20.984209 [ModeRegInit_LP4] CH0 RK0
7137 17:58:20.987317 [ModeRegInit_LP4] CH0 RK1
7138 17:58:20.990454 [ModeRegInit_LP4] CH1 RK0
7139 17:58:20.993705 [ModeRegInit_LP4] CH1 RK1
7140 17:58:20.993777 match AC timing 4
7141 17:58:21.000623 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7142 17:58:21.003859 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7143 17:58:21.007061 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7144 17:58:21.013975 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7145 17:58:21.017038 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7146 17:58:21.017146 [MiockJmeterHQA]
7147 17:58:21.017237
7148 17:58:21.020106 [DramcMiockJmeter] u1RxGatingPI = 0
7149 17:58:21.023329 0 : 4253, 4026
7150 17:58:21.023401 4 : 4365, 4140
7151 17:58:21.027146 8 : 4252, 4027
7152 17:58:21.027218 12 : 4253, 4027
7153 17:58:21.030172 16 : 4255, 4030
7154 17:58:21.030261 20 : 4363, 4138
7155 17:58:21.030323 24 : 4252, 4027
7156 17:58:21.033258 28 : 4363, 4137
7157 17:58:21.033341 32 : 4252, 4027
7158 17:58:21.036828 36 : 4253, 4027
7159 17:58:21.036930 40 : 4252, 4027
7160 17:58:21.039864 44 : 4254, 4029
7161 17:58:21.039966 48 : 4363, 4138
7162 17:58:21.043602 52 : 4252, 4026
7163 17:58:21.043700 56 : 4363, 4137
7164 17:58:21.043798 60 : 4250, 4027
7165 17:58:21.046790 64 : 4250, 4027
7166 17:58:21.046863 68 : 4250, 4027
7167 17:58:21.049936 72 : 4360, 4138
7168 17:58:21.050071 76 : 4250, 4027
7169 17:58:21.052941 80 : 4360, 4138
7170 17:58:21.053045 84 : 4249, 4027
7171 17:58:21.056546 88 : 4250, 4027
7172 17:58:21.056655 92 : 4250, 4027
7173 17:58:21.056742 96 : 4253, 4029
7174 17:58:21.059646 100 : 4360, 1632
7175 17:58:21.059744 104 : 4250, 0
7176 17:58:21.063153 108 : 4254, 0
7177 17:58:21.063235 112 : 4360, 0
7178 17:58:21.063299 116 : 4252, 0
7179 17:58:21.066262 120 : 4252, 0
7180 17:58:21.066342 124 : 4249, 0
7181 17:58:21.069833 128 : 4249, 0
7182 17:58:21.069919 132 : 4361, 0
7183 17:58:21.070011 136 : 4360, 0
7184 17:58:21.072815 140 : 4249, 0
7185 17:58:21.072895 144 : 4250, 0
7186 17:58:21.076304 148 : 4250, 0
7187 17:58:21.076384 152 : 4252, 0
7188 17:58:21.076448 156 : 4250, 0
7189 17:58:21.079814 160 : 4250, 0
7190 17:58:21.079894 164 : 4252, 0
7191 17:58:21.083320 168 : 4250, 0
7192 17:58:21.083401 172 : 4250, 0
7193 17:58:21.083465 176 : 4249, 0
7194 17:58:21.086231 180 : 4249, 0
7195 17:58:21.086338 184 : 4361, 0
7196 17:58:21.089320 188 : 4361, 0
7197 17:58:21.089424 192 : 4249, 0
7198 17:58:21.089518 196 : 4250, 0
7199 17:58:21.092519 200 : 4250, 0
7200 17:58:21.092599 204 : 4252, 0
7201 17:58:21.092662 208 : 4250, 0
7202 17:58:21.096361 212 : 4250, 0
7203 17:58:21.096442 216 : 4252, 0
7204 17:58:21.099535 220 : 4360, 930
7205 17:58:21.099615 224 : 4250, 4007
7206 17:58:21.102671 228 : 4250, 4026
7207 17:58:21.102752 232 : 4250, 4027
7208 17:58:21.105744 236 : 4360, 4138
7209 17:58:21.105824 240 : 4250, 4027
7210 17:58:21.109539 244 : 4250, 4027
7211 17:58:21.109619 248 : 4360, 4138
7212 17:58:21.109682 252 : 4360, 4138
7213 17:58:21.112700 256 : 4250, 4027
7214 17:58:21.112780 260 : 4363, 4139
7215 17:58:21.115673 264 : 4360, 4138
7216 17:58:21.115784 268 : 4250, 4027
7217 17:58:21.119300 272 : 4249, 4027
7218 17:58:21.119410 276 : 4252, 4029
7219 17:58:21.122342 280 : 4250, 4027
7220 17:58:21.122416 284 : 4250, 4027
7221 17:58:21.125500 288 : 4249, 4027
7222 17:58:21.125605 292 : 4252, 4029
7223 17:58:21.129216 296 : 4250, 4026
7224 17:58:21.129289 300 : 4360, 4138
7225 17:58:21.132340 304 : 4360, 4138
7226 17:58:21.132440 308 : 4250, 4027
7227 17:58:21.132538 312 : 4363, 4140
7228 17:58:21.136102 316 : 4360, 4138
7229 17:58:21.136176 320 : 4250, 4027
7230 17:58:21.139252 324 : 4249, 4027
7231 17:58:21.139351 328 : 4252, 4029
7232 17:58:21.142239 332 : 4250, 4027
7233 17:58:21.142339 336 : 4250, 3714
7234 17:58:21.145617 340 : 4249, 1880
7235 17:58:21.145715
7236 17:58:21.149107 MIOCK jitter meter ch=0
7237 17:58:21.149209
7238 17:58:21.149296 1T = (340-100) = 240 dly cells
7239 17:58:21.155354 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7240 17:58:21.155440 ==
7241 17:58:21.159168 Dram Type= 6, Freq= 0, CH_0, rank 0
7242 17:58:21.162262 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7243 17:58:21.165252 ==
7244 17:58:21.168818 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7245 17:58:21.172277 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7246 17:58:21.178906 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7247 17:58:21.184949 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7248 17:58:21.192015 [CA 0] Center 42 (12~73) winsize 62
7249 17:58:21.194957 [CA 1] Center 42 (12~73) winsize 62
7250 17:58:21.198001 [CA 2] Center 39 (9~69) winsize 61
7251 17:58:21.201916 [CA 3] Center 38 (9~68) winsize 60
7252 17:58:21.205053 [CA 4] Center 37 (7~67) winsize 61
7253 17:58:21.208096 [CA 5] Center 36 (6~66) winsize 61
7254 17:58:21.208170
7255 17:58:21.211361 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7256 17:58:21.211465
7257 17:58:21.215160 [CATrainingPosCal] consider 1 rank data
7258 17:58:21.218292 u2DelayCellTimex100 = 271/100 ps
7259 17:58:21.221916 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7260 17:58:21.228120 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7261 17:58:21.231223 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7262 17:58:21.234988 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7263 17:58:21.237960 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7264 17:58:21.241183 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7265 17:58:21.241257
7266 17:58:21.244371 CA PerBit enable=1, Macro0, CA PI delay=36
7267 17:58:21.244443
7268 17:58:21.248141 [CBTSetCACLKResult] CA Dly = 36
7269 17:58:21.251131 CS Dly: 10 (0~41)
7270 17:58:21.255045 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7271 17:58:21.257726 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7272 17:58:21.257838 ==
7273 17:58:21.260766 Dram Type= 6, Freq= 0, CH_0, rank 1
7274 17:58:21.267779 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7275 17:58:21.267858 ==
7276 17:58:21.270904 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7277 17:58:21.277711 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7278 17:58:21.281137 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7279 17:58:21.287413 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7280 17:58:21.294585 [CA 0] Center 42 (12~73) winsize 62
7281 17:58:21.297547 [CA 1] Center 41 (11~72) winsize 62
7282 17:58:21.301325 [CA 2] Center 38 (9~68) winsize 60
7283 17:58:21.304122 [CA 3] Center 37 (8~67) winsize 60
7284 17:58:21.307458 [CA 4] Center 35 (5~65) winsize 61
7285 17:58:21.311204 [CA 5] Center 35 (5~66) winsize 62
7286 17:58:21.311284
7287 17:58:21.314338 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7288 17:58:21.314418
7289 17:58:21.317476 [CATrainingPosCal] consider 2 rank data
7290 17:58:21.320661 u2DelayCellTimex100 = 271/100 ps
7291 17:58:21.327481 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7292 17:58:21.330633 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
7293 17:58:21.333719 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7294 17:58:21.337579 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7295 17:58:21.340655 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7296 17:58:21.343839 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7297 17:58:21.343959
7298 17:58:21.347665 CA PerBit enable=1, Macro0, CA PI delay=36
7299 17:58:21.347745
7300 17:58:21.350836 [CBTSetCACLKResult] CA Dly = 36
7301 17:58:21.353945 CS Dly: 11 (0~43)
7302 17:58:21.357245 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7303 17:58:21.360847 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7304 17:58:21.360925
7305 17:58:21.363751 ----->DramcWriteLeveling(PI) begin...
7306 17:58:21.363851 ==
7307 17:58:21.367075 Dram Type= 6, Freq= 0, CH_0, rank 0
7308 17:58:21.373550 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7309 17:58:21.373629 ==
7310 17:58:21.376771 Write leveling (Byte 0): 29 => 29
7311 17:58:21.380569 Write leveling (Byte 1): 26 => 26
7312 17:58:21.380641 DramcWriteLeveling(PI) end<-----
7313 17:58:21.380700
7314 17:58:21.383582 ==
7315 17:58:21.387078 Dram Type= 6, Freq= 0, CH_0, rank 0
7316 17:58:21.390028 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7317 17:58:21.390138 ==
7318 17:58:21.393449 [Gating] SW mode calibration
7319 17:58:21.400291 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7320 17:58:21.403379 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7321 17:58:21.409980 0 12 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7322 17:58:21.413578 0 12 4 | B1->B0 | 2626 3333 | 0 0 | (0 0) (0 0)
7323 17:58:21.416748 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7324 17:58:21.423124 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7325 17:58:21.426271 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7326 17:58:21.429540 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7327 17:58:21.436289 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7328 17:58:21.439494 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7329 17:58:21.443237 0 13 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
7330 17:58:21.449918 0 13 4 | B1->B0 | 3434 2727 | 0 0 | (0 1) (0 1)
7331 17:58:21.453095 0 13 8 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
7332 17:58:21.456289 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7333 17:58:21.463201 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7334 17:58:21.466393 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7335 17:58:21.469506 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7336 17:58:21.476068 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7337 17:58:21.479422 0 14 0 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7338 17:58:21.482975 0 14 4 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
7339 17:58:21.489368 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7340 17:58:21.493173 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7341 17:58:21.496155 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7342 17:58:21.502950 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7343 17:58:21.506405 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7344 17:58:21.509285 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7345 17:58:21.516411 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7346 17:58:21.519278 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7347 17:58:21.522266 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7348 17:58:21.529310 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7349 17:58:21.532386 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7350 17:58:21.536022 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7351 17:58:21.542363 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7352 17:58:21.546166 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7353 17:58:21.549375 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7354 17:58:21.555358 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7355 17:58:21.559134 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7356 17:58:21.562356 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7357 17:58:21.565564 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7358 17:58:21.572397 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7359 17:58:21.575383 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7360 17:58:21.578661 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7361 17:58:21.585408 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7362 17:58:21.588753 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7363 17:58:21.592139 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7364 17:58:21.595938 Total UI for P1: 0, mck2ui 16
7365 17:58:21.598955 best dqsien dly found for B0: ( 1, 1, 4)
7366 17:58:21.605685 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7367 17:58:21.608886 Total UI for P1: 0, mck2ui 16
7368 17:58:21.611903 best dqsien dly found for B1: ( 1, 1, 6)
7369 17:58:21.615455 best DQS0 dly(MCK, UI, PI) = (1, 1, 4)
7370 17:58:21.618415 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7371 17:58:21.618496
7372 17:58:21.622011 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 4)
7373 17:58:21.625015 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7374 17:58:21.628555 [Gating] SW calibration Done
7375 17:58:21.628635 ==
7376 17:58:21.632054 Dram Type= 6, Freq= 0, CH_0, rank 0
7377 17:58:21.635247 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7378 17:58:21.635328 ==
7379 17:58:21.638294 RX Vref Scan: 0
7380 17:58:21.638374
7381 17:58:21.638439 RX Vref 0 -> 0, step: 1
7382 17:58:21.638498
7383 17:58:21.641411 RX Delay 0 -> 252, step: 8
7384 17:58:21.645155 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7385 17:58:21.651360 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7386 17:58:21.655165 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7387 17:58:21.658266 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7388 17:58:21.661253 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7389 17:58:21.664995 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7390 17:58:21.671495 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7391 17:58:21.674605 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7392 17:58:21.677829 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7393 17:58:21.681015 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7394 17:58:21.687895 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7395 17:58:21.691004 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7396 17:58:21.694624 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7397 17:58:21.697571 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7398 17:58:21.701083 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7399 17:58:21.707474 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7400 17:58:21.707564 ==
7401 17:58:21.710553 Dram Type= 6, Freq= 0, CH_0, rank 0
7402 17:58:21.714299 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7403 17:58:21.714416 ==
7404 17:58:21.714486 DQS Delay:
7405 17:58:21.717342 DQS0 = 0, DQS1 = 0
7406 17:58:21.717453 DQM Delay:
7407 17:58:21.720473 DQM0 = 130, DQM1 = 122
7408 17:58:21.720578 DQ Delay:
7409 17:58:21.723956 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7410 17:58:21.727433 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7411 17:58:21.730628 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
7412 17:58:21.737105 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7413 17:58:21.737242
7414 17:58:21.737313
7415 17:58:21.737374 ==
7416 17:58:21.740263 Dram Type= 6, Freq= 0, CH_0, rank 0
7417 17:58:21.743926 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7418 17:58:21.744034 ==
7419 17:58:21.744100
7420 17:58:21.744159
7421 17:58:21.747037 TX Vref Scan disable
7422 17:58:21.747147 == TX Byte 0 ==
7423 17:58:21.753419 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7424 17:58:21.756837 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7425 17:58:21.756982 == TX Byte 1 ==
7426 17:58:21.763674 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7427 17:58:21.766689 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7428 17:58:21.766810 ==
7429 17:58:21.770403 Dram Type= 6, Freq= 0, CH_0, rank 0
7430 17:58:21.773507 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7431 17:58:21.773629 ==
7432 17:58:21.787298
7433 17:58:21.790414 TX Vref early break, caculate TX vref
7434 17:58:21.793980 TX Vref=16, minBit 8, minWin=22, winSum=374
7435 17:58:21.797189 TX Vref=18, minBit 8, minWin=23, winSum=380
7436 17:58:21.800397 TX Vref=20, minBit 8, minWin=22, winSum=388
7437 17:58:21.804050 TX Vref=22, minBit 8, minWin=24, winSum=397
7438 17:58:21.807108 TX Vref=24, minBit 8, minWin=24, winSum=403
7439 17:58:21.813854 TX Vref=26, minBit 4, minWin=25, winSum=409
7440 17:58:21.816874 TX Vref=28, minBit 4, minWin=25, winSum=412
7441 17:58:21.820437 TX Vref=30, minBit 0, minWin=25, winSum=408
7442 17:58:21.823710 TX Vref=32, minBit 1, minWin=24, winSum=402
7443 17:58:21.827340 TX Vref=34, minBit 8, minWin=23, winSum=390
7444 17:58:21.833890 [TxChooseVref] Worse bit 4, Min win 25, Win sum 412, Final Vref 28
7445 17:58:21.833972
7446 17:58:21.836755 Final TX Range 0 Vref 28
7447 17:58:21.836837
7448 17:58:21.836901 ==
7449 17:58:21.840645 Dram Type= 6, Freq= 0, CH_0, rank 0
7450 17:58:21.843539 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7451 17:58:21.843641 ==
7452 17:58:21.843730
7453 17:58:21.843792
7454 17:58:21.847052 TX Vref Scan disable
7455 17:58:21.853750 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7456 17:58:21.853832 == TX Byte 0 ==
7457 17:58:21.856944 u2DelayCellOfst[0]=10 cells (3 PI)
7458 17:58:21.860082 u2DelayCellOfst[1]=18 cells (5 PI)
7459 17:58:21.863284 u2DelayCellOfst[2]=14 cells (4 PI)
7460 17:58:21.867021 u2DelayCellOfst[3]=10 cells (3 PI)
7461 17:58:21.869940 u2DelayCellOfst[4]=10 cells (3 PI)
7462 17:58:21.873181 u2DelayCellOfst[5]=0 cells (0 PI)
7463 17:58:21.876378 u2DelayCellOfst[6]=18 cells (5 PI)
7464 17:58:21.880136 u2DelayCellOfst[7]=18 cells (5 PI)
7465 17:58:21.883420 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7466 17:58:21.886582 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7467 17:58:21.889776 == TX Byte 1 ==
7468 17:58:21.893487 u2DelayCellOfst[8]=3 cells (1 PI)
7469 17:58:21.893653 u2DelayCellOfst[9]=0 cells (0 PI)
7470 17:58:21.896632 u2DelayCellOfst[10]=10 cells (3 PI)
7471 17:58:21.899839 u2DelayCellOfst[11]=3 cells (1 PI)
7472 17:58:21.902980 u2DelayCellOfst[12]=14 cells (4 PI)
7473 17:58:21.906697 u2DelayCellOfst[13]=14 cells (4 PI)
7474 17:58:21.909759 u2DelayCellOfst[14]=18 cells (5 PI)
7475 17:58:21.913005 u2DelayCellOfst[15]=18 cells (5 PI)
7476 17:58:21.919735 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7477 17:58:21.923387 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7478 17:58:21.923737 DramC Write-DBI on
7479 17:58:21.924129 ==
7480 17:58:21.926299 Dram Type= 6, Freq= 0, CH_0, rank 0
7481 17:58:21.932741 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7482 17:58:21.933270 ==
7483 17:58:21.933668
7484 17:58:21.933989
7485 17:58:21.934300 TX Vref Scan disable
7486 17:58:21.937004 == TX Byte 0 ==
7487 17:58:21.940662 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7488 17:58:21.943740 == TX Byte 1 ==
7489 17:58:21.947239 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7490 17:58:21.950346 DramC Write-DBI off
7491 17:58:21.950640
7492 17:58:21.950937 [DATLAT]
7493 17:58:21.951237 Freq=1600, CH0 RK0
7494 17:58:21.951452
7495 17:58:21.953891 DATLAT Default: 0xf
7496 17:58:21.956823 0, 0xFFFF, sum = 0
7497 17:58:21.957120 1, 0xFFFF, sum = 0
7498 17:58:21.960404 2, 0xFFFF, sum = 0
7499 17:58:21.960701 3, 0xFFFF, sum = 0
7500 17:58:21.963455 4, 0xFFFF, sum = 0
7501 17:58:21.963839 5, 0xFFFF, sum = 0
7502 17:58:21.966563 6, 0xFFFF, sum = 0
7503 17:58:21.966888 7, 0xFFFF, sum = 0
7504 17:58:21.969688 8, 0xFFFF, sum = 0
7505 17:58:21.969987 9, 0xFFFF, sum = 0
7506 17:58:21.973485 10, 0xFFFF, sum = 0
7507 17:58:21.973782 11, 0xFFFF, sum = 0
7508 17:58:21.976940 12, 0xFFF, sum = 0
7509 17:58:21.977343 13, 0x0, sum = 1
7510 17:58:21.980019 14, 0x0, sum = 2
7511 17:58:21.980315 15, 0x0, sum = 3
7512 17:58:21.983159 16, 0x0, sum = 4
7513 17:58:21.983460 best_step = 14
7514 17:58:21.983691
7515 17:58:21.983909 ==
7516 17:58:21.986366 Dram Type= 6, Freq= 0, CH_0, rank 0
7517 17:58:21.993193 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7518 17:58:21.993491 ==
7519 17:58:21.993725 RX Vref Scan: 1
7520 17:58:21.993942
7521 17:58:21.996516 Set Vref Range= 24 -> 127
7522 17:58:21.996808
7523 17:58:21.999673 RX Vref 24 -> 127, step: 1
7524 17:58:21.999963
7525 17:58:22.000194 RX Delay 11 -> 252, step: 4
7526 17:58:22.000410
7527 17:58:22.002769 Set Vref, RX VrefLevel [Byte0]: 24
7528 17:58:22.006576 [Byte1]: 24
7529 17:58:22.010419
7530 17:58:22.010791 Set Vref, RX VrefLevel [Byte0]: 25
7531 17:58:22.013559 [Byte1]: 25
7532 17:58:22.017985
7533 17:58:22.018435 Set Vref, RX VrefLevel [Byte0]: 26
7534 17:58:22.021267 [Byte1]: 26
7535 17:58:22.025612
7536 17:58:22.026255 Set Vref, RX VrefLevel [Byte0]: 27
7537 17:58:22.028801 [Byte1]: 27
7538 17:58:22.033137
7539 17:58:22.033553 Set Vref, RX VrefLevel [Byte0]: 28
7540 17:58:22.036634 [Byte1]: 28
7541 17:58:22.040987
7542 17:58:22.041151 Set Vref, RX VrefLevel [Byte0]: 29
7543 17:58:22.044040 [Byte1]: 29
7544 17:58:22.048321
7545 17:58:22.048401 Set Vref, RX VrefLevel [Byte0]: 30
7546 17:58:22.051303 [Byte1]: 30
7547 17:58:22.056083
7548 17:58:22.056162 Set Vref, RX VrefLevel [Byte0]: 31
7549 17:58:22.059144 [Byte1]: 31
7550 17:58:22.063572
7551 17:58:22.063651 Set Vref, RX VrefLevel [Byte0]: 32
7552 17:58:22.066630 [Byte1]: 32
7553 17:58:22.070770
7554 17:58:22.070848 Set Vref, RX VrefLevel [Byte0]: 33
7555 17:58:22.074513 [Byte1]: 33
7556 17:58:22.078816
7557 17:58:22.078896 Set Vref, RX VrefLevel [Byte0]: 34
7558 17:58:22.081883 [Byte1]: 34
7559 17:58:22.086088
7560 17:58:22.086167 Set Vref, RX VrefLevel [Byte0]: 35
7561 17:58:22.089333 [Byte1]: 35
7562 17:58:22.094297
7563 17:58:22.094386 Set Vref, RX VrefLevel [Byte0]: 36
7564 17:58:22.097443 [Byte1]: 36
7565 17:58:22.101222
7566 17:58:22.101304 Set Vref, RX VrefLevel [Byte0]: 37
7567 17:58:22.105099 [Byte1]: 37
7568 17:58:22.108856
7569 17:58:22.108935 Set Vref, RX VrefLevel [Byte0]: 38
7570 17:58:22.112587 [Byte1]: 38
7571 17:58:22.116850
7572 17:58:22.116929 Set Vref, RX VrefLevel [Byte0]: 39
7573 17:58:22.119943 [Byte1]: 39
7574 17:58:22.124270
7575 17:58:22.124349 Set Vref, RX VrefLevel [Byte0]: 40
7576 17:58:22.127360 [Byte1]: 40
7577 17:58:22.131871
7578 17:58:22.131949 Set Vref, RX VrefLevel [Byte0]: 41
7579 17:58:22.135052 [Byte1]: 41
7580 17:58:22.139401
7581 17:58:22.139478 Set Vref, RX VrefLevel [Byte0]: 42
7582 17:58:22.142542 [Byte1]: 42
7583 17:58:22.147315
7584 17:58:22.147393 Set Vref, RX VrefLevel [Byte0]: 43
7585 17:58:22.150247 [Byte1]: 43
7586 17:58:22.154801
7587 17:58:22.154879 Set Vref, RX VrefLevel [Byte0]: 44
7588 17:58:22.157928 [Byte1]: 44
7589 17:58:22.162240
7590 17:58:22.162318 Set Vref, RX VrefLevel [Byte0]: 45
7591 17:58:22.165448 [Byte1]: 45
7592 17:58:22.170161
7593 17:58:22.170241 Set Vref, RX VrefLevel [Byte0]: 46
7594 17:58:22.173516 [Byte1]: 46
7595 17:58:22.177409
7596 17:58:22.177487 Set Vref, RX VrefLevel [Byte0]: 47
7597 17:58:22.180944 [Byte1]: 47
7598 17:58:22.184898
7599 17:58:22.184985 Set Vref, RX VrefLevel [Byte0]: 48
7600 17:58:22.188517 [Byte1]: 48
7601 17:58:22.192698
7602 17:58:22.192807 Set Vref, RX VrefLevel [Byte0]: 49
7603 17:58:22.195973 [Byte1]: 49
7604 17:58:22.200481
7605 17:58:22.200561 Set Vref, RX VrefLevel [Byte0]: 50
7606 17:58:22.203711 [Byte1]: 50
7607 17:58:22.208058
7608 17:58:22.208164 Set Vref, RX VrefLevel [Byte0]: 51
7609 17:58:22.211254 [Byte1]: 51
7610 17:58:22.215635
7611 17:58:22.215715 Set Vref, RX VrefLevel [Byte0]: 52
7612 17:58:22.219197 [Byte1]: 52
7613 17:58:22.223532
7614 17:58:22.223641 Set Vref, RX VrefLevel [Byte0]: 53
7615 17:58:22.226670 [Byte1]: 53
7616 17:58:22.230955
7617 17:58:22.231064 Set Vref, RX VrefLevel [Byte0]: 54
7618 17:58:22.234211 [Byte1]: 54
7619 17:58:22.238567
7620 17:58:22.238646 Set Vref, RX VrefLevel [Byte0]: 55
7621 17:58:22.241772 [Byte1]: 55
7622 17:58:22.246244
7623 17:58:22.246322 Set Vref, RX VrefLevel [Byte0]: 56
7624 17:58:22.249385 [Byte1]: 56
7625 17:58:22.253901
7626 17:58:22.254006 Set Vref, RX VrefLevel [Byte0]: 57
7627 17:58:22.257008 [Byte1]: 57
7628 17:58:22.261234
7629 17:58:22.261313 Set Vref, RX VrefLevel [Byte0]: 58
7630 17:58:22.264801 [Byte1]: 58
7631 17:58:22.268931
7632 17:58:22.269010 Set Vref, RX VrefLevel [Byte0]: 59
7633 17:58:22.272448 [Byte1]: 59
7634 17:58:22.276546
7635 17:58:22.276624 Set Vref, RX VrefLevel [Byte0]: 60
7636 17:58:22.279774 [Byte1]: 60
7637 17:58:22.283889
7638 17:58:22.283967 Set Vref, RX VrefLevel [Byte0]: 61
7639 17:58:22.287379 [Byte1]: 61
7640 17:58:22.291673
7641 17:58:22.295068 Set Vref, RX VrefLevel [Byte0]: 62
7642 17:58:22.295184 [Byte1]: 62
7643 17:58:22.299547
7644 17:58:22.299626 Set Vref, RX VrefLevel [Byte0]: 63
7645 17:58:22.302814 [Byte1]: 63
7646 17:58:22.307161
7647 17:58:22.307268 Set Vref, RX VrefLevel [Byte0]: 64
7648 17:58:22.310249 [Byte1]: 64
7649 17:58:22.314466
7650 17:58:22.314567 Set Vref, RX VrefLevel [Byte0]: 65
7651 17:58:22.317680 [Byte1]: 65
7652 17:58:22.321961
7653 17:58:22.322074 Set Vref, RX VrefLevel [Byte0]: 66
7654 17:58:22.325747 [Byte1]: 66
7655 17:58:22.330147
7656 17:58:22.330220 Set Vref, RX VrefLevel [Byte0]: 67
7657 17:58:22.333259 [Byte1]: 67
7658 17:58:22.337718
7659 17:58:22.337824 Set Vref, RX VrefLevel [Byte0]: 68
7660 17:58:22.340884 [Byte1]: 68
7661 17:58:22.345205
7662 17:58:22.345295 Set Vref, RX VrefLevel [Byte0]: 69
7663 17:58:22.348372 [Byte1]: 69
7664 17:58:22.352926
7665 17:58:22.353009 Set Vref, RX VrefLevel [Byte0]: 70
7666 17:58:22.356046 [Byte1]: 70
7667 17:58:22.360354
7668 17:58:22.360427 Final RX Vref Byte 0 = 53 to rank0
7669 17:58:22.363558 Final RX Vref Byte 1 = 55 to rank0
7670 17:58:22.366575 Final RX Vref Byte 0 = 53 to rank1
7671 17:58:22.370272 Final RX Vref Byte 1 = 55 to rank1==
7672 17:58:22.373331 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 17:58:22.379990 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7674 17:58:22.380069 ==
7675 17:58:22.380137 DQS Delay:
7676 17:58:22.380198 DQS0 = 0, DQS1 = 0
7677 17:58:22.383454 DQM Delay:
7678 17:58:22.383530 DQM0 = 126, DQM1 = 120
7679 17:58:22.386448 DQ Delay:
7680 17:58:22.390092 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7681 17:58:22.393283 DQ4 =130, DQ5 =116, DQ6 =136, DQ7 =134
7682 17:58:22.396852 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7683 17:58:22.399954 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7684 17:58:22.400027
7685 17:58:22.400094
7686 17:58:22.400156
7687 17:58:22.403535 [DramC_TX_OE_Calibration] TA2
7688 17:58:22.407032 Original DQ_B0 (3 6) =30, OEN = 27
7689 17:58:22.409812 Original DQ_B1 (3 6) =30, OEN = 27
7690 17:58:22.413299 24, 0x0, End_B0=24 End_B1=24
7691 17:58:22.413377 25, 0x0, End_B0=25 End_B1=25
7692 17:58:22.416481 26, 0x0, End_B0=26 End_B1=26
7693 17:58:22.419880 27, 0x0, End_B0=27 End_B1=27
7694 17:58:22.422991 28, 0x0, End_B0=28 End_B1=28
7695 17:58:22.426620 29, 0x0, End_B0=29 End_B1=29
7696 17:58:22.426695 30, 0x0, End_B0=30 End_B1=30
7697 17:58:22.429750 31, 0x4141, End_B0=30 End_B1=30
7698 17:58:22.432869 Byte0 end_step=30 best_step=27
7699 17:58:22.436652 Byte1 end_step=30 best_step=27
7700 17:58:22.439791 Byte0 TX OE(2T, 0.5T) = (3, 3)
7701 17:58:22.442900 Byte1 TX OE(2T, 0.5T) = (3, 3)
7702 17:58:22.442979
7703 17:58:22.443042
7704 17:58:22.449889 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7705 17:58:22.453138 CH0 RK0: MR19=303, MR18=1B1B
7706 17:58:22.459544 CH0_RK0: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
7707 17:58:22.459624
7708 17:58:22.462649 ----->DramcWriteLeveling(PI) begin...
7709 17:58:22.462728 ==
7710 17:58:22.466352 Dram Type= 6, Freq= 0, CH_0, rank 1
7711 17:58:22.469585 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7712 17:58:22.469661 ==
7713 17:58:22.472617 Write leveling (Byte 0): 30 => 30
7714 17:58:22.475825 Write leveling (Byte 1): 25 => 25
7715 17:58:22.479627 DramcWriteLeveling(PI) end<-----
7716 17:58:22.479698
7717 17:58:22.479768 ==
7718 17:58:22.482532 Dram Type= 6, Freq= 0, CH_0, rank 1
7719 17:58:22.485800 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7720 17:58:22.485878 ==
7721 17:58:22.489383 [Gating] SW mode calibration
7722 17:58:22.495831 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7723 17:58:22.502715 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7724 17:58:22.505823 0 12 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7725 17:58:22.512760 0 12 4 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
7726 17:58:22.515787 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7727 17:58:22.518981 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7728 17:58:22.525439 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7729 17:58:22.528742 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7730 17:58:22.531963 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7731 17:58:22.538961 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7732 17:58:22.542069 0 13 0 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
7733 17:58:22.545256 0 13 4 | B1->B0 | 3030 2323 | 0 0 | (1 0) (1 0)
7734 17:58:22.552217 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7735 17:58:22.555445 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7736 17:58:22.558538 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7737 17:58:22.565607 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7738 17:58:22.568892 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7739 17:58:22.572039 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7740 17:58:22.578782 0 14 0 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7741 17:58:22.581962 0 14 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
7742 17:58:22.585061 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7743 17:58:22.591947 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7744 17:58:22.595059 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7745 17:58:22.598645 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7746 17:58:22.605022 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7747 17:58:22.607999 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7748 17:58:22.611613 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7749 17:58:22.617858 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7750 17:58:22.621477 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7751 17:58:22.624645 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7752 17:58:22.631576 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7753 17:58:22.634474 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7754 17:58:22.637785 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7755 17:58:22.644766 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7756 17:58:22.647767 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7757 17:58:22.651251 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7758 17:58:22.654913 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7759 17:58:22.661315 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7760 17:58:22.664405 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7761 17:58:22.668226 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7762 17:58:22.674776 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7763 17:58:22.677826 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7764 17:58:22.680843 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7765 17:58:22.687605 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7766 17:58:22.690840 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7767 17:58:22.694490 Total UI for P1: 0, mck2ui 16
7768 17:58:22.697786 best dqsien dly found for B0: ( 1, 1, 0)
7769 17:58:22.700798 Total UI for P1: 0, mck2ui 16
7770 17:58:22.704513 best dqsien dly found for B1: ( 1, 1, 2)
7771 17:58:22.707643 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7772 17:58:22.710689 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7773 17:58:22.710821
7774 17:58:22.714298 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7775 17:58:22.717207 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7776 17:58:22.720701 [Gating] SW calibration Done
7777 17:58:22.720883 ==
7778 17:58:22.724294 Dram Type= 6, Freq= 0, CH_0, rank 1
7779 17:58:22.727291 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7780 17:58:22.730588 ==
7781 17:58:22.730726 RX Vref Scan: 0
7782 17:58:22.730801
7783 17:58:22.733714 RX Vref 0 -> 0, step: 1
7784 17:58:22.733887
7785 17:58:22.737382 RX Delay 0 -> 252, step: 8
7786 17:58:22.740558 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7787 17:58:22.744087 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7788 17:58:22.747021 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7789 17:58:22.750706 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7790 17:58:22.756586 iDelay=200, Bit 4, Center 135 (72 ~ 199) 128
7791 17:58:22.760104 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7792 17:58:22.763343 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7793 17:58:22.766635 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7794 17:58:22.769770 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7795 17:58:22.776756 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7796 17:58:22.779856 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7797 17:58:22.783073 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7798 17:58:22.786824 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7799 17:58:22.790004 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7800 17:58:22.796866 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
7801 17:58:22.799958 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7802 17:58:22.800063 ==
7803 17:58:22.803119 Dram Type= 6, Freq= 0, CH_0, rank 1
7804 17:58:22.806971 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7805 17:58:22.807078 ==
7806 17:58:22.809972 DQS Delay:
7807 17:58:22.810102 DQS0 = 0, DQS1 = 0
7808 17:58:22.810203 DQM Delay:
7809 17:58:22.813126 DQM0 = 130, DQM1 = 123
7810 17:58:22.813255 DQ Delay:
7811 17:58:22.816651 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7812 17:58:22.819801 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7813 17:58:22.826176 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7814 17:58:22.829614 DQ12 =131, DQ13 =131, DQ14 =131, DQ15 =131
7815 17:58:22.829763
7816 17:58:22.829863
7817 17:58:22.829961 ==
7818 17:58:22.833158 Dram Type= 6, Freq= 0, CH_0, rank 1
7819 17:58:22.836324 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7820 17:58:22.836470 ==
7821 17:58:22.836574
7822 17:58:22.836665
7823 17:58:22.839522 TX Vref Scan disable
7824 17:58:22.842611 == TX Byte 0 ==
7825 17:58:22.846266 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7826 17:58:22.849271 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7827 17:58:22.853005 == TX Byte 1 ==
7828 17:58:22.856196 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7829 17:58:22.859312 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7830 17:58:22.859434 ==
7831 17:58:22.862750 Dram Type= 6, Freq= 0, CH_0, rank 1
7832 17:58:22.869373 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7833 17:58:22.869515 ==
7834 17:58:22.880832
7835 17:58:22.883982 TX Vref early break, caculate TX vref
7836 17:58:22.887783 TX Vref=16, minBit 9, minWin=21, winSum=369
7837 17:58:22.890915 TX Vref=18, minBit 0, minWin=23, winSum=381
7838 17:58:22.894098 TX Vref=20, minBit 11, minWin=22, winSum=389
7839 17:58:22.897233 TX Vref=22, minBit 1, minWin=24, winSum=399
7840 17:58:22.900880 TX Vref=24, minBit 1, minWin=24, winSum=402
7841 17:58:22.907299 TX Vref=26, minBit 8, minWin=24, winSum=415
7842 17:58:22.910494 TX Vref=28, minBit 8, minWin=24, winSum=414
7843 17:58:22.914348 TX Vref=30, minBit 8, minWin=24, winSum=406
7844 17:58:22.917419 TX Vref=32, minBit 8, minWin=23, winSum=399
7845 17:58:22.920438 TX Vref=34, minBit 8, minWin=23, winSum=392
7846 17:58:22.927147 [TxChooseVref] Worse bit 8, Min win 24, Win sum 415, Final Vref 26
7847 17:58:22.927238
7848 17:58:22.930808 Final TX Range 0 Vref 26
7849 17:58:22.930896
7850 17:58:22.930984 ==
7851 17:58:22.933758 Dram Type= 6, Freq= 0, CH_0, rank 1
7852 17:58:22.937345 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7853 17:58:22.937428 ==
7854 17:58:22.937514
7855 17:58:22.937595
7856 17:58:22.940794 TX Vref Scan disable
7857 17:58:22.947038 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7858 17:58:22.947143 == TX Byte 0 ==
7859 17:58:22.950622 u2DelayCellOfst[0]=10 cells (3 PI)
7860 17:58:22.953615 u2DelayCellOfst[1]=14 cells (4 PI)
7861 17:58:22.956762 u2DelayCellOfst[2]=10 cells (3 PI)
7862 17:58:22.960056 u2DelayCellOfst[3]=10 cells (3 PI)
7863 17:58:22.963973 u2DelayCellOfst[4]=7 cells (2 PI)
7864 17:58:22.966906 u2DelayCellOfst[5]=0 cells (0 PI)
7865 17:58:22.970418 u2DelayCellOfst[6]=14 cells (4 PI)
7866 17:58:22.973237 u2DelayCellOfst[7]=18 cells (5 PI)
7867 17:58:22.976660 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7868 17:58:22.980461 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7869 17:58:22.983593 == TX Byte 1 ==
7870 17:58:22.986741 u2DelayCellOfst[8]=0 cells (0 PI)
7871 17:58:22.986908 u2DelayCellOfst[9]=0 cells (0 PI)
7872 17:58:22.989823 u2DelayCellOfst[10]=10 cells (3 PI)
7873 17:58:22.993287 u2DelayCellOfst[11]=3 cells (1 PI)
7874 17:58:22.996629 u2DelayCellOfst[12]=14 cells (4 PI)
7875 17:58:23.000374 u2DelayCellOfst[13]=14 cells (4 PI)
7876 17:58:23.003379 u2DelayCellOfst[14]=18 cells (5 PI)
7877 17:58:23.006509 u2DelayCellOfst[15]=14 cells (4 PI)
7878 17:58:23.013390 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7879 17:58:23.016605 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7880 17:58:23.016789 DramC Write-DBI on
7881 17:58:23.016905 ==
7882 17:58:23.019697 Dram Type= 6, Freq= 0, CH_0, rank 1
7883 17:58:23.026185 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7884 17:58:23.026357 ==
7885 17:58:23.026474
7886 17:58:23.026576
7887 17:58:23.026673 TX Vref Scan disable
7888 17:58:23.030646 == TX Byte 0 ==
7889 17:58:23.034097 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7890 17:58:23.037044 == TX Byte 1 ==
7891 17:58:23.040202 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7892 17:58:23.043914 DramC Write-DBI off
7893 17:58:23.044092
7894 17:58:23.044240 [DATLAT]
7895 17:58:23.044380 Freq=1600, CH0 RK1
7896 17:58:23.044516
7897 17:58:23.047408 DATLAT Default: 0xe
7898 17:58:23.047554 0, 0xFFFF, sum = 0
7899 17:58:23.050560 1, 0xFFFF, sum = 0
7900 17:58:23.053509 2, 0xFFFF, sum = 0
7901 17:58:23.053724 3, 0xFFFF, sum = 0
7902 17:58:23.057300 4, 0xFFFF, sum = 0
7903 17:58:23.057495 5, 0xFFFF, sum = 0
7904 17:58:23.060209 6, 0xFFFF, sum = 0
7905 17:58:23.060410 7, 0xFFFF, sum = 0
7906 17:58:23.063401 8, 0xFFFF, sum = 0
7907 17:58:23.063620 9, 0xFFFF, sum = 0
7908 17:58:23.067166 10, 0xFFFF, sum = 0
7909 17:58:23.067432 11, 0xFFFF, sum = 0
7910 17:58:23.070341 12, 0xCFFF, sum = 0
7911 17:58:23.070557 13, 0x0, sum = 1
7912 17:58:23.073506 14, 0x0, sum = 2
7913 17:58:23.073706 15, 0x0, sum = 3
7914 17:58:23.076888 16, 0x0, sum = 4
7915 17:58:23.077171 best_step = 14
7916 17:58:23.077355
7917 17:58:23.077514 ==
7918 17:58:23.080286 Dram Type= 6, Freq= 0, CH_0, rank 1
7919 17:58:23.086937 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7920 17:58:23.087135 ==
7921 17:58:23.087300 RX Vref Scan: 0
7922 17:58:23.087427
7923 17:58:23.090034 RX Vref 0 -> 0, step: 1
7924 17:58:23.090177
7925 17:58:23.093152 RX Delay 11 -> 252, step: 4
7926 17:58:23.096876 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7927 17:58:23.100054 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
7928 17:58:23.103162 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7929 17:58:23.109893 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7930 17:58:23.113045 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7931 17:58:23.116301 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7932 17:58:23.120062 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7933 17:58:23.123168 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7934 17:58:23.129527 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7935 17:58:23.132700 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7936 17:58:23.136361 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7937 17:58:23.139335 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7938 17:58:23.142942 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7939 17:58:23.149361 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7940 17:58:23.153088 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
7941 17:58:23.156137 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7942 17:58:23.156213 ==
7943 17:58:23.159557 Dram Type= 6, Freq= 0, CH_0, rank 1
7944 17:58:23.162614 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7945 17:58:23.165989 ==
7946 17:58:23.166087 DQS Delay:
7947 17:58:23.166153 DQS0 = 0, DQS1 = 0
7948 17:58:23.169142 DQM Delay:
7949 17:58:23.169262 DQM0 = 128, DQM1 = 120
7950 17:58:23.172914 DQ Delay:
7951 17:58:23.175983 DQ0 =122, DQ1 =130, DQ2 =126, DQ3 =122
7952 17:58:23.179023 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =138
7953 17:58:23.182869 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7954 17:58:23.185906 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
7955 17:58:23.186057
7956 17:58:23.186125
7957 17:58:23.186185
7958 17:58:23.188957 [DramC_TX_OE_Calibration] TA2
7959 17:58:23.192095 Original DQ_B0 (3 6) =30, OEN = 27
7960 17:58:23.195851 Original DQ_B1 (3 6) =30, OEN = 27
7961 17:58:23.199113 24, 0x0, End_B0=24 End_B1=24
7962 17:58:23.199205 25, 0x0, End_B0=25 End_B1=25
7963 17:58:23.201969 26, 0x0, End_B0=26 End_B1=26
7964 17:58:23.205861 27, 0x0, End_B0=27 End_B1=27
7965 17:58:23.209102 28, 0x0, End_B0=28 End_B1=28
7966 17:58:23.209207 29, 0x0, End_B0=29 End_B1=29
7967 17:58:23.212303 30, 0x0, End_B0=30 End_B1=30
7968 17:58:23.215979 31, 0x4141, End_B0=30 End_B1=30
7969 17:58:23.219024 Byte0 end_step=30 best_step=27
7970 17:58:23.222201 Byte1 end_step=30 best_step=27
7971 17:58:23.225433 Byte0 TX OE(2T, 0.5T) = (3, 3)
7972 17:58:23.229119 Byte1 TX OE(2T, 0.5T) = (3, 3)
7973 17:58:23.229273
7974 17:58:23.229393
7975 17:58:23.235352 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
7976 17:58:23.239300 CH0 RK1: MR19=303, MR18=2323
7977 17:58:23.245162 CH0_RK1: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
7978 17:58:23.248785 [RxdqsGatingPostProcess] freq 1600
7979 17:58:23.251864 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7980 17:58:23.255160 Pre-setting of DQS Precalculation
7981 17:58:23.261934 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7982 17:58:23.262038 ==
7983 17:58:23.265501 Dram Type= 6, Freq= 0, CH_1, rank 0
7984 17:58:23.268817 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7985 17:58:23.268901 ==
7986 17:58:23.275138 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7987 17:58:23.278551 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7988 17:58:23.281534 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7989 17:58:23.288478 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7990 17:58:23.296443 [CA 0] Center 41 (11~72) winsize 62
7991 17:58:23.300031 [CA 1] Center 41 (11~72) winsize 62
7992 17:58:23.303185 [CA 2] Center 37 (8~67) winsize 60
7993 17:58:23.306683 [CA 3] Center 36 (6~66) winsize 61
7994 17:58:23.309839 [CA 4] Center 34 (4~64) winsize 61
7995 17:58:23.313008 [CA 5] Center 34 (4~64) winsize 61
7996 17:58:23.313094
7997 17:58:23.316153 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7998 17:58:23.316234
7999 17:58:23.319884 [CATrainingPosCal] consider 1 rank data
8000 17:58:23.322847 u2DelayCellTimex100 = 271/100 ps
8001 17:58:23.326517 CA0 delay=41 (11~72),Diff = 7 PI (25 cell)
8002 17:58:23.333001 CA1 delay=41 (11~72),Diff = 7 PI (25 cell)
8003 17:58:23.336175 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8004 17:58:23.339946 CA3 delay=36 (6~66),Diff = 2 PI (7 cell)
8005 17:58:23.343121 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8006 17:58:23.346269 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
8007 17:58:23.346348
8008 17:58:23.349443 CA PerBit enable=1, Macro0, CA PI delay=34
8009 17:58:23.349523
8010 17:58:23.352665 [CBTSetCACLKResult] CA Dly = 34
8011 17:58:23.356215 CS Dly: 8 (0~39)
8012 17:58:23.359622 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8013 17:58:23.362841 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8014 17:58:23.362920 ==
8015 17:58:23.365893 Dram Type= 6, Freq= 0, CH_1, rank 1
8016 17:58:23.369736 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8017 17:58:23.372893 ==
8018 17:58:23.375789 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8019 17:58:23.379288 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8020 17:58:23.385923 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8021 17:58:23.392387 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8022 17:58:23.399278 [CA 0] Center 41 (11~71) winsize 61
8023 17:58:23.402245 [CA 1] Center 41 (11~71) winsize 61
8024 17:58:23.405791 [CA 2] Center 36 (7~66) winsize 60
8025 17:58:23.408795 [CA 3] Center 35 (6~65) winsize 60
8026 17:58:23.412494 [CA 4] Center 34 (5~64) winsize 60
8027 17:58:23.415627 [CA 5] Center 34 (4~64) winsize 61
8028 17:58:23.415706
8029 17:58:23.418823 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8030 17:58:23.418923
8031 17:58:23.421925 [CATrainingPosCal] consider 2 rank data
8032 17:58:23.425574 u2DelayCellTimex100 = 271/100 ps
8033 17:58:23.431846 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8034 17:58:23.435580 CA1 delay=41 (11~71),Diff = 7 PI (25 cell)
8035 17:58:23.438761 CA2 delay=37 (8~66),Diff = 3 PI (10 cell)
8036 17:58:23.441961 CA3 delay=35 (6~65),Diff = 1 PI (3 cell)
8037 17:58:23.445809 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
8038 17:58:23.449085 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
8039 17:58:23.449166
8040 17:58:23.452194 CA PerBit enable=1, Macro0, CA PI delay=34
8041 17:58:23.452274
8042 17:58:23.455394 [CBTSetCACLKResult] CA Dly = 34
8043 17:58:23.458556 CS Dly: 9 (0~41)
8044 17:58:23.461658 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8045 17:58:23.465150 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8046 17:58:23.465231
8047 17:58:23.468638 ----->DramcWriteLeveling(PI) begin...
8048 17:58:23.468738 ==
8049 17:58:23.472214 Dram Type= 6, Freq= 0, CH_1, rank 0
8050 17:58:23.478567 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8051 17:58:23.478648 ==
8052 17:58:23.481503 Write leveling (Byte 0): 22 => 22
8053 17:58:23.484958 Write leveling (Byte 1): 21 => 21
8054 17:58:23.485036 DramcWriteLeveling(PI) end<-----
8055 17:58:23.485097
8056 17:58:23.488033 ==
8057 17:58:23.491787 Dram Type= 6, Freq= 0, CH_1, rank 0
8058 17:58:23.494868 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8059 17:58:23.494953 ==
8060 17:58:23.498224 [Gating] SW mode calibration
8061 17:58:23.504869 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8062 17:58:23.508059 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8063 17:58:23.514898 0 12 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8064 17:58:23.517985 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 17:58:23.521176 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 17:58:23.528169 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 17:58:23.531229 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 17:58:23.534483 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 17:58:23.541370 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8070 17:58:23.544570 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8071 17:58:23.547786 0 13 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
8072 17:58:23.554697 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8073 17:58:23.557933 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8074 17:58:23.561008 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 17:58:23.568061 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 17:58:23.571244 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 17:58:23.574201 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 17:58:23.580766 0 13 28 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
8079 17:58:23.584083 0 14 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
8080 17:58:23.587747 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 17:58:23.594174 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 17:58:23.597646 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 17:58:23.600828 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 17:58:23.607408 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 17:58:23.610420 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 17:58:23.613603 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8087 17:58:23.620443 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8088 17:58:23.623322 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8089 17:58:23.627087 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 17:58:23.633757 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 17:58:23.636822 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 17:58:23.639995 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 17:58:23.646354 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 17:58:23.649655 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 17:58:23.653444 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 17:58:23.659814 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 17:58:23.663001 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 17:58:23.666131 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 17:58:23.673054 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 17:58:23.676173 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 17:58:23.679332 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 17:58:23.686195 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8103 17:58:23.689779 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8104 17:58:23.692910 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8105 17:58:23.696078 Total UI for P1: 0, mck2ui 16
8106 17:58:23.699634 best dqsien dly found for B0: ( 1, 0, 30)
8107 17:58:23.703043 Total UI for P1: 0, mck2ui 16
8108 17:58:23.705792 best dqsien dly found for B1: ( 1, 1, 0)
8109 17:58:23.709503 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
8110 17:58:23.712548 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8111 17:58:23.712628
8112 17:58:23.719543 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
8113 17:58:23.722741 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8114 17:58:23.722822 [Gating] SW calibration Done
8115 17:58:23.725905 ==
8116 17:58:23.729590 Dram Type= 6, Freq= 0, CH_1, rank 0
8117 17:58:23.732290 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8118 17:58:23.732367 ==
8119 17:58:23.732429 RX Vref Scan: 0
8120 17:58:23.732487
8121 17:58:23.735637 RX Vref 0 -> 0, step: 1
8122 17:58:23.735719
8123 17:58:23.739520 RX Delay 0 -> 252, step: 8
8124 17:58:23.742211 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8125 17:58:23.745810 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8126 17:58:23.748955 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8127 17:58:23.755377 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8128 17:58:23.759113 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8129 17:58:23.762437 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8130 17:58:23.765642 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8131 17:58:23.768670 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8132 17:58:23.775674 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8133 17:58:23.778744 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8134 17:58:23.781917 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8135 17:58:23.785725 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8136 17:58:23.788932 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8137 17:58:23.795429 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8138 17:58:23.798369 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8139 17:58:23.802219 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8140 17:58:23.802300 ==
8141 17:58:23.805307 Dram Type= 6, Freq= 0, CH_1, rank 0
8142 17:58:23.811844 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8143 17:58:23.811932 ==
8144 17:58:23.811998 DQS Delay:
8145 17:58:23.812058 DQS0 = 0, DQS1 = 0
8146 17:58:23.815159 DQM Delay:
8147 17:58:23.815307 DQM0 = 130, DQM1 = 126
8148 17:58:23.818294 DQ Delay:
8149 17:58:23.821829 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8150 17:58:23.824764 DQ4 =131, DQ5 =139, DQ6 =139, DQ7 =127
8151 17:58:23.828514 DQ8 =107, DQ9 =115, DQ10 =131, DQ11 =115
8152 17:58:23.831699 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8153 17:58:23.831799
8154 17:58:23.831889
8155 17:58:23.831977 ==
8156 17:58:23.834930 Dram Type= 6, Freq= 0, CH_1, rank 0
8157 17:58:23.837996 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8158 17:58:23.841622 ==
8159 17:58:23.841699
8160 17:58:23.841767
8161 17:58:23.841827 TX Vref Scan disable
8162 17:58:23.844553 == TX Byte 0 ==
8163 17:58:23.848120 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8164 17:58:23.851521 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8165 17:58:23.854809 == TX Byte 1 ==
8166 17:58:23.858145 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8167 17:58:23.861409 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8168 17:58:23.864479 ==
8169 17:58:23.864578 Dram Type= 6, Freq= 0, CH_1, rank 0
8170 17:58:23.871299 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8171 17:58:23.871406 ==
8172 17:58:23.882586
8173 17:58:23.885765 TX Vref early break, caculate TX vref
8174 17:58:23.889523 TX Vref=16, minBit 3, minWin=21, winSum=371
8175 17:58:23.892729 TX Vref=18, minBit 1, minWin=22, winSum=377
8176 17:58:23.895980 TX Vref=20, minBit 0, minWin=22, winSum=384
8177 17:58:23.899138 TX Vref=22, minBit 3, minWin=22, winSum=388
8178 17:58:23.902350 TX Vref=24, minBit 0, minWin=24, winSum=400
8179 17:58:23.909171 TX Vref=26, minBit 0, minWin=24, winSum=412
8180 17:58:23.912294 TX Vref=28, minBit 3, minWin=24, winSum=413
8181 17:58:23.915528 TX Vref=30, minBit 0, minWin=25, winSum=409
8182 17:58:23.919283 TX Vref=32, minBit 1, minWin=23, winSum=396
8183 17:58:23.922358 TX Vref=34, minBit 3, minWin=23, winSum=389
8184 17:58:23.928690 [TxChooseVref] Worse bit 0, Min win 25, Win sum 409, Final Vref 30
8185 17:58:23.928773
8186 17:58:23.932122 Final TX Range 0 Vref 30
8187 17:58:23.932204
8188 17:58:23.932268 ==
8189 17:58:23.935718 Dram Type= 6, Freq= 0, CH_1, rank 0
8190 17:58:23.938988 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8191 17:58:23.939070 ==
8192 17:58:23.939134
8193 17:58:23.939193
8194 17:58:23.942122 TX Vref Scan disable
8195 17:58:23.948391 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8196 17:58:23.948473 == TX Byte 0 ==
8197 17:58:23.952137 u2DelayCellOfst[0]=14 cells (4 PI)
8198 17:58:23.955331 u2DelayCellOfst[1]=10 cells (3 PI)
8199 17:58:23.958550 u2DelayCellOfst[2]=0 cells (0 PI)
8200 17:58:23.962252 u2DelayCellOfst[3]=7 cells (2 PI)
8201 17:58:23.965181 u2DelayCellOfst[4]=7 cells (2 PI)
8202 17:58:23.968531 u2DelayCellOfst[5]=18 cells (5 PI)
8203 17:58:23.972102 u2DelayCellOfst[6]=18 cells (5 PI)
8204 17:58:23.974774 u2DelayCellOfst[7]=3 cells (1 PI)
8205 17:58:23.978267 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8206 17:58:23.981387 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8207 17:58:23.985193 == TX Byte 1 ==
8208 17:58:23.988358 u2DelayCellOfst[8]=0 cells (0 PI)
8209 17:58:23.988462 u2DelayCellOfst[9]=3 cells (1 PI)
8210 17:58:23.991519 u2DelayCellOfst[10]=7 cells (2 PI)
8211 17:58:23.994662 u2DelayCellOfst[11]=0 cells (0 PI)
8212 17:58:23.998364 u2DelayCellOfst[12]=14 cells (4 PI)
8213 17:58:24.001553 u2DelayCellOfst[13]=18 cells (5 PI)
8214 17:58:24.004772 u2DelayCellOfst[14]=18 cells (5 PI)
8215 17:58:24.007945 u2DelayCellOfst[15]=18 cells (5 PI)
8216 17:58:24.014752 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8217 17:58:24.018209 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8218 17:58:24.018312 DramC Write-DBI on
8219 17:58:24.018414 ==
8220 17:58:24.020993 Dram Type= 6, Freq= 0, CH_1, rank 0
8221 17:58:24.027600 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8222 17:58:24.027702 ==
8223 17:58:24.027793
8224 17:58:24.027883
8225 17:58:24.027968 TX Vref Scan disable
8226 17:58:24.032088 == TX Byte 0 ==
8227 17:58:24.035223 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8228 17:58:24.038120 == TX Byte 1 ==
8229 17:58:24.041542 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8230 17:58:24.044669 DramC Write-DBI off
8231 17:58:24.044740
8232 17:58:24.044809 [DATLAT]
8233 17:58:24.044869 Freq=1600, CH1 RK0
8234 17:58:24.044926
8235 17:58:24.048396 DATLAT Default: 0xf
8236 17:58:24.051692 0, 0xFFFF, sum = 0
8237 17:58:24.051789 1, 0xFFFF, sum = 0
8238 17:58:24.054821 2, 0xFFFF, sum = 0
8239 17:58:24.054893 3, 0xFFFF, sum = 0
8240 17:58:24.058503 4, 0xFFFF, sum = 0
8241 17:58:24.058579 5, 0xFFFF, sum = 0
8242 17:58:24.061716 6, 0xFFFF, sum = 0
8243 17:58:24.061815 7, 0xFFFF, sum = 0
8244 17:58:24.065059 8, 0xFFFF, sum = 0
8245 17:58:24.065166 9, 0xFFFF, sum = 0
8246 17:58:24.068120 10, 0xFFFF, sum = 0
8247 17:58:24.068235 11, 0xFFFF, sum = 0
8248 17:58:24.071345 12, 0x8FFF, sum = 0
8249 17:58:24.071419 13, 0x0, sum = 1
8250 17:58:24.075071 14, 0x0, sum = 2
8251 17:58:24.075160 15, 0x0, sum = 3
8252 17:58:24.078063 16, 0x0, sum = 4
8253 17:58:24.078151 best_step = 14
8254 17:58:24.078226
8255 17:58:24.078289 ==
8256 17:58:24.081485 Dram Type= 6, Freq= 0, CH_1, rank 0
8257 17:58:24.088247 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8258 17:58:24.088348 ==
8259 17:58:24.088453 RX Vref Scan: 1
8260 17:58:24.088540
8261 17:58:24.091032 Set Vref Range= 24 -> 127
8262 17:58:24.091111
8263 17:58:24.094762 RX Vref 24 -> 127, step: 1
8264 17:58:24.094831
8265 17:58:24.094891 RX Delay 3 -> 252, step: 4
8266 17:58:24.094981
8267 17:58:24.097961 Set Vref, RX VrefLevel [Byte0]: 24
8268 17:58:24.101112 [Byte1]: 24
8269 17:58:24.105488
8270 17:58:24.105585 Set Vref, RX VrefLevel [Byte0]: 25
8271 17:58:24.108668 [Byte1]: 25
8272 17:58:24.113007
8273 17:58:24.113107 Set Vref, RX VrefLevel [Byte0]: 26
8274 17:58:24.116284 [Byte1]: 26
8275 17:58:24.120572
8276 17:58:24.120671 Set Vref, RX VrefLevel [Byte0]: 27
8277 17:58:24.123852 [Byte1]: 27
8278 17:58:24.128004
8279 17:58:24.128098 Set Vref, RX VrefLevel [Byte0]: 28
8280 17:58:24.131288 [Byte1]: 28
8281 17:58:24.135829
8282 17:58:24.135930 Set Vref, RX VrefLevel [Byte0]: 29
8283 17:58:24.138952 [Byte1]: 29
8284 17:58:24.143331
8285 17:58:24.143433 Set Vref, RX VrefLevel [Byte0]: 30
8286 17:58:24.146893 [Byte1]: 30
8287 17:58:24.150939
8288 17:58:24.151007 Set Vref, RX VrefLevel [Byte0]: 31
8289 17:58:24.154179 [Byte1]: 31
8290 17:58:24.158569
8291 17:58:24.158636 Set Vref, RX VrefLevel [Byte0]: 32
8292 17:58:24.162228 [Byte1]: 32
8293 17:58:24.166069
8294 17:58:24.166139 Set Vref, RX VrefLevel [Byte0]: 33
8295 17:58:24.169856 [Byte1]: 33
8296 17:58:24.173724
8297 17:58:24.173843 Set Vref, RX VrefLevel [Byte0]: 34
8298 17:58:24.177467 [Byte1]: 34
8299 17:58:24.181767
8300 17:58:24.181862 Set Vref, RX VrefLevel [Byte0]: 35
8301 17:58:24.185034 [Byte1]: 35
8302 17:58:24.189357
8303 17:58:24.189449 Set Vref, RX VrefLevel [Byte0]: 36
8304 17:58:24.192413 [Byte1]: 36
8305 17:58:24.197026
8306 17:58:24.197107 Set Vref, RX VrefLevel [Byte0]: 37
8307 17:58:24.200113 [Byte1]: 37
8308 17:58:24.204817
8309 17:58:24.204899 Set Vref, RX VrefLevel [Byte0]: 38
8310 17:58:24.207983 [Byte1]: 38
8311 17:58:24.212420
8312 17:58:24.212519 Set Vref, RX VrefLevel [Byte0]: 39
8313 17:58:24.215606 [Byte1]: 39
8314 17:58:24.220134
8315 17:58:24.220215 Set Vref, RX VrefLevel [Byte0]: 40
8316 17:58:24.223348 [Byte1]: 40
8317 17:58:24.227688
8318 17:58:24.227767 Set Vref, RX VrefLevel [Byte0]: 41
8319 17:58:24.230801 [Byte1]: 41
8320 17:58:24.235252
8321 17:58:24.235332 Set Vref, RX VrefLevel [Byte0]: 42
8322 17:58:24.238314 [Byte1]: 42
8323 17:58:24.243064
8324 17:58:24.243143 Set Vref, RX VrefLevel [Byte0]: 43
8325 17:58:24.246360 [Byte1]: 43
8326 17:58:24.250362
8327 17:58:24.250468 Set Vref, RX VrefLevel [Byte0]: 44
8328 17:58:24.254068 [Byte1]: 44
8329 17:58:24.258539
8330 17:58:24.259011 Set Vref, RX VrefLevel [Byte0]: 45
8331 17:58:24.262131 [Byte1]: 45
8332 17:58:24.266401
8333 17:58:24.266959 Set Vref, RX VrefLevel [Byte0]: 46
8334 17:58:24.269493 [Byte1]: 46
8335 17:58:24.274000
8336 17:58:24.274495 Set Vref, RX VrefLevel [Byte0]: 47
8337 17:58:24.277115 [Byte1]: 47
8338 17:58:24.281633
8339 17:58:24.282157 Set Vref, RX VrefLevel [Byte0]: 48
8340 17:58:24.284766 [Byte1]: 48
8341 17:58:24.289116
8342 17:58:24.289562 Set Vref, RX VrefLevel [Byte0]: 49
8343 17:58:24.292363 [Byte1]: 49
8344 17:58:24.296832
8345 17:58:24.297462 Set Vref, RX VrefLevel [Byte0]: 50
8346 17:58:24.299991 [Byte1]: 50
8347 17:58:24.304640
8348 17:58:24.305335 Set Vref, RX VrefLevel [Byte0]: 51
8349 17:58:24.307426 [Byte1]: 51
8350 17:58:24.312043
8351 17:58:24.312619 Set Vref, RX VrefLevel [Byte0]: 52
8352 17:58:24.315272 [Byte1]: 52
8353 17:58:24.319613
8354 17:58:24.320177 Set Vref, RX VrefLevel [Byte0]: 53
8355 17:58:24.322795 [Byte1]: 53
8356 17:58:24.327174
8357 17:58:24.327724 Set Vref, RX VrefLevel [Byte0]: 54
8358 17:58:24.330942 [Byte1]: 54
8359 17:58:24.334854
8360 17:58:24.335272 Set Vref, RX VrefLevel [Byte0]: 55
8361 17:58:24.338412 [Byte1]: 55
8362 17:58:24.342755
8363 17:58:24.343146 Set Vref, RX VrefLevel [Byte0]: 56
8364 17:58:24.345973 [Byte1]: 56
8365 17:58:24.350396
8366 17:58:24.350791 Set Vref, RX VrefLevel [Byte0]: 57
8367 17:58:24.353299 [Byte1]: 57
8368 17:58:24.357912
8369 17:58:24.358255 Set Vref, RX VrefLevel [Byte0]: 58
8370 17:58:24.361251 [Byte1]: 58
8371 17:58:24.365310
8372 17:58:24.365708 Set Vref, RX VrefLevel [Byte0]: 59
8373 17:58:24.368673 [Byte1]: 59
8374 17:58:24.373331
8375 17:58:24.373695 Set Vref, RX VrefLevel [Byte0]: 60
8376 17:58:24.375951 [Byte1]: 60
8377 17:58:24.380303
8378 17:58:24.380399 Set Vref, RX VrefLevel [Byte0]: 61
8379 17:58:24.384053 [Byte1]: 61
8380 17:58:24.388520
8381 17:58:24.388613 Set Vref, RX VrefLevel [Byte0]: 62
8382 17:58:24.391724 [Byte1]: 62
8383 17:58:24.396075
8384 17:58:24.396173 Set Vref, RX VrefLevel [Byte0]: 63
8385 17:58:24.399235 [Byte1]: 63
8386 17:58:24.403585
8387 17:58:24.403679 Set Vref, RX VrefLevel [Byte0]: 64
8388 17:58:24.406815 [Byte1]: 64
8389 17:58:24.411079
8390 17:58:24.411153 Set Vref, RX VrefLevel [Byte0]: 65
8391 17:58:24.414525 [Byte1]: 65
8392 17:58:24.418665
8393 17:58:24.418737 Set Vref, RX VrefLevel [Byte0]: 66
8394 17:58:24.422063 [Byte1]: 66
8395 17:58:24.426317
8396 17:58:24.426395 Set Vref, RX VrefLevel [Byte0]: 67
8397 17:58:24.430100 [Byte1]: 67
8398 17:58:24.433988
8399 17:58:24.434096 Set Vref, RX VrefLevel [Byte0]: 68
8400 17:58:24.437630 [Byte1]: 68
8401 17:58:24.442099
8402 17:58:24.442197 Set Vref, RX VrefLevel [Byte0]: 69
8403 17:58:24.445279 [Byte1]: 69
8404 17:58:24.449727
8405 17:58:24.449831 Set Vref, RX VrefLevel [Byte0]: 70
8406 17:58:24.452949 [Byte1]: 70
8407 17:58:24.457380
8408 17:58:24.457472 Set Vref, RX VrefLevel [Byte0]: 71
8409 17:58:24.460387 [Byte1]: 71
8410 17:58:24.464744
8411 17:58:24.464837 Set Vref, RX VrefLevel [Byte0]: 72
8412 17:58:24.467805 [Byte1]: 72
8413 17:58:24.472725
8414 17:58:24.472827 Final RX Vref Byte 0 = 60 to rank0
8415 17:58:24.475682 Final RX Vref Byte 1 = 58 to rank0
8416 17:58:24.479195 Final RX Vref Byte 0 = 60 to rank1
8417 17:58:24.482115 Final RX Vref Byte 1 = 58 to rank1==
8418 17:58:24.485577 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 17:58:24.492156 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8420 17:58:24.492232 ==
8421 17:58:24.492294 DQS Delay:
8422 17:58:24.495117 DQS0 = 0, DQS1 = 0
8423 17:58:24.495186 DQM Delay:
8424 17:58:24.495248 DQM0 = 128, DQM1 = 124
8425 17:58:24.498906 DQ Delay:
8426 17:58:24.502031 DQ0 =130, DQ1 =122, DQ2 =118, DQ3 =126
8427 17:58:24.505051 DQ4 =130, DQ5 =140, DQ6 =136, DQ7 =124
8428 17:58:24.508901 DQ8 =106, DQ9 =114, DQ10 =128, DQ11 =114
8429 17:58:24.512084 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =134
8430 17:58:24.512178
8431 17:58:24.512269
8432 17:58:24.512355
8433 17:58:24.515284 [DramC_TX_OE_Calibration] TA2
8434 17:58:24.518283 Original DQ_B0 (3 6) =30, OEN = 27
8435 17:58:24.522248 Original DQ_B1 (3 6) =30, OEN = 27
8436 17:58:24.525330 24, 0x0, End_B0=24 End_B1=24
8437 17:58:24.528331 25, 0x0, End_B0=25 End_B1=25
8438 17:58:24.528398 26, 0x0, End_B0=26 End_B1=26
8439 17:58:24.531945 27, 0x0, End_B0=27 End_B1=27
8440 17:58:24.535394 28, 0x0, End_B0=28 End_B1=28
8441 17:58:24.538547 29, 0x0, End_B0=29 End_B1=29
8442 17:58:24.538619 30, 0x0, End_B0=30 End_B1=30
8443 17:58:24.541726 31, 0x4141, End_B0=30 End_B1=30
8444 17:58:24.544914 Byte0 end_step=30 best_step=27
8445 17:58:24.548623 Byte1 end_step=30 best_step=27
8446 17:58:24.551854 Byte0 TX OE(2T, 0.5T) = (3, 3)
8447 17:58:24.554977 Byte1 TX OE(2T, 0.5T) = (3, 3)
8448 17:58:24.555069
8449 17:58:24.555135
8450 17:58:24.561275 [DQSOSCAuto] RK0, (LSB)MR18= 0x2727, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8451 17:58:24.565042 CH1 RK0: MR19=303, MR18=2727
8452 17:58:24.571184 CH1_RK0: MR19=0x303, MR18=0x2727, DQSOSC=390, MR23=63, INC=24, DEC=16
8453 17:58:24.571268
8454 17:58:24.574798 ----->DramcWriteLeveling(PI) begin...
8455 17:58:24.574906 ==
8456 17:58:24.577907 Dram Type= 6, Freq= 0, CH_1, rank 1
8457 17:58:24.581617 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8458 17:58:24.581713 ==
8459 17:58:24.584701 Write leveling (Byte 0): 22 => 22
8460 17:58:24.587794 Write leveling (Byte 1): 22 => 22
8461 17:58:24.591332 DramcWriteLeveling(PI) end<-----
8462 17:58:24.591466
8463 17:58:24.591554 ==
8464 17:58:24.594802 Dram Type= 6, Freq= 0, CH_1, rank 1
8465 17:58:24.597551 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8466 17:58:24.600963 ==
8467 17:58:24.601077 [Gating] SW mode calibration
8468 17:58:24.610991 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8469 17:58:24.614152 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8470 17:58:24.618056 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8471 17:58:24.624098 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8472 17:58:24.627751 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8473 17:58:24.631006 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8474 17:58:24.637961 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8475 17:58:24.640912 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8476 17:58:24.644085 0 12 24 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
8477 17:58:24.651026 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8478 17:58:24.654444 0 13 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8479 17:58:24.657577 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8480 17:58:24.664160 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8481 17:58:24.667261 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8482 17:58:24.671050 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8483 17:58:24.677500 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8484 17:58:24.680707 0 13 24 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8485 17:58:24.683819 0 13 28 | B1->B0 | 2626 4646 | 0 0 | (1 1) (0 0)
8486 17:58:24.690614 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8487 17:58:24.693843 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8488 17:58:24.696995 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8489 17:58:24.703521 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8490 17:58:24.707241 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8491 17:58:24.710629 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8492 17:58:24.717009 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8493 17:58:24.720253 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8494 17:58:24.723477 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8495 17:58:24.730200 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 17:58:24.733159 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 17:58:24.736690 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 17:58:24.743142 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 17:58:24.746897 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 17:58:24.749833 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 17:58:24.756890 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 17:58:24.760265 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 17:58:24.763718 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 17:58:24.769863 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 17:58:24.773216 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 17:58:24.776833 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 17:58:24.783406 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 17:58:24.786277 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8509 17:58:24.789968 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8510 17:58:24.792844 Total UI for P1: 0, mck2ui 16
8511 17:58:24.796664 best dqsien dly found for B0: ( 1, 0, 24)
8512 17:58:24.802841 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8513 17:58:24.806664 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8514 17:58:24.809786 Total UI for P1: 0, mck2ui 16
8515 17:58:24.812849 best dqsien dly found for B1: ( 1, 0, 30)
8516 17:58:24.815986 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8517 17:58:24.819510 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8518 17:58:24.820091
8519 17:58:24.823009 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8520 17:58:24.826430 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8521 17:58:24.829674 [Gating] SW calibration Done
8522 17:58:24.830128 ==
8523 17:58:24.832923 Dram Type= 6, Freq= 0, CH_1, rank 1
8524 17:58:24.836055 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8525 17:58:24.839049 ==
8526 17:58:24.839487 RX Vref Scan: 0
8527 17:58:24.839817
8528 17:58:24.842426 RX Vref 0 -> 0, step: 1
8529 17:58:24.842855
8530 17:58:24.843191 RX Delay 0 -> 252, step: 8
8531 17:58:24.849404 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8532 17:58:24.852695 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8533 17:58:24.855719 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8534 17:58:24.859002 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8535 17:58:24.862555 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8536 17:58:24.869165 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8537 17:58:24.872391 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8538 17:58:24.876106 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8539 17:58:24.879324 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8540 17:58:24.882647 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8541 17:58:24.889242 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8542 17:58:24.892288 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8543 17:58:24.895416 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8544 17:58:24.899113 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8545 17:58:24.905322 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8546 17:58:24.909109 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8547 17:58:24.909652 ==
8548 17:58:24.912160 Dram Type= 6, Freq= 0, CH_1, rank 1
8549 17:58:24.915794 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8550 17:58:24.916336 ==
8551 17:58:24.918930 DQS Delay:
8552 17:58:24.919531 DQS0 = 0, DQS1 = 0
8553 17:58:24.920025 DQM Delay:
8554 17:58:24.922082 DQM0 = 131, DQM1 = 124
8555 17:58:24.922453 DQ Delay:
8556 17:58:24.925220 DQ0 =131, DQ1 =123, DQ2 =119, DQ3 =131
8557 17:58:24.928895 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8558 17:58:24.931847 DQ8 =107, DQ9 =111, DQ10 =123, DQ11 =115
8559 17:58:24.938654 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8560 17:58:24.939072
8561 17:58:24.939550
8562 17:58:24.939994 ==
8563 17:58:24.941638 Dram Type= 6, Freq= 0, CH_1, rank 1
8564 17:58:24.944862 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8565 17:58:24.945434 ==
8566 17:58:24.945917
8567 17:58:24.946373
8568 17:58:24.948523 TX Vref Scan disable
8569 17:58:24.949056 == TX Byte 0 ==
8570 17:58:24.955026 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8571 17:58:24.958183 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8572 17:58:24.958721 == TX Byte 1 ==
8573 17:58:24.965006 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8574 17:58:24.968106 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8575 17:58:24.968663 ==
8576 17:58:24.971315 Dram Type= 6, Freq= 0, CH_1, rank 1
8577 17:58:24.974811 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8578 17:58:24.975353 ==
8579 17:58:24.988693
8580 17:58:24.991555 TX Vref early break, caculate TX vref
8581 17:58:24.995360 TX Vref=16, minBit 0, minWin=22, winSum=373
8582 17:58:24.998438 TX Vref=18, minBit 0, minWin=23, winSum=383
8583 17:58:25.001997 TX Vref=20, minBit 2, minWin=23, winSum=394
8584 17:58:25.004937 TX Vref=22, minBit 1, minWin=24, winSum=401
8585 17:58:25.008446 TX Vref=24, minBit 0, minWin=25, winSum=411
8586 17:58:25.014903 TX Vref=26, minBit 0, minWin=25, winSum=417
8587 17:58:25.017993 TX Vref=28, minBit 0, minWin=25, winSum=418
8588 17:58:25.021544 TX Vref=30, minBit 0, minWin=25, winSum=414
8589 17:58:25.024800 TX Vref=32, minBit 0, minWin=24, winSum=407
8590 17:58:25.028578 TX Vref=34, minBit 0, minWin=23, winSum=396
8591 17:58:25.034719 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8592 17:58:25.035126
8593 17:58:25.038321 Final TX Range 0 Vref 28
8594 17:58:25.038727
8595 17:58:25.039107 ==
8596 17:58:25.041326 Dram Type= 6, Freq= 0, CH_1, rank 1
8597 17:58:25.045043 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8598 17:58:25.045456 ==
8599 17:58:25.045777
8600 17:58:25.046163
8601 17:58:25.048160 TX Vref Scan disable
8602 17:58:25.055106 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8603 17:58:25.055513 == TX Byte 0 ==
8604 17:58:25.058146 u2DelayCellOfst[0]=14 cells (4 PI)
8605 17:58:25.061427 u2DelayCellOfst[1]=7 cells (2 PI)
8606 17:58:25.064413 u2DelayCellOfst[2]=0 cells (0 PI)
8607 17:58:25.068191 u2DelayCellOfst[3]=3 cells (1 PI)
8608 17:58:25.071344 u2DelayCellOfst[4]=7 cells (2 PI)
8609 17:58:25.074507 u2DelayCellOfst[5]=14 cells (4 PI)
8610 17:58:25.077615 u2DelayCellOfst[6]=14 cells (4 PI)
8611 17:58:25.078020 u2DelayCellOfst[7]=3 cells (1 PI)
8612 17:58:25.084675 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8613 17:58:25.087595 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8614 17:58:25.090957 == TX Byte 1 ==
8615 17:58:25.091404 u2DelayCellOfst[8]=0 cells (0 PI)
8616 17:58:25.094709 u2DelayCellOfst[9]=7 cells (2 PI)
8617 17:58:25.097942 u2DelayCellOfst[10]=14 cells (4 PI)
8618 17:58:25.101087 u2DelayCellOfst[11]=7 cells (2 PI)
8619 17:58:25.104308 u2DelayCellOfst[12]=18 cells (5 PI)
8620 17:58:25.107732 u2DelayCellOfst[13]=21 cells (6 PI)
8621 17:58:25.110919 u2DelayCellOfst[14]=21 cells (6 PI)
8622 17:58:25.114415 u2DelayCellOfst[15]=21 cells (6 PI)
8623 17:58:25.117613 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8624 17:58:25.124494 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8625 17:58:25.124904 DramC Write-DBI on
8626 17:58:25.125226 ==
8627 17:58:25.127617 Dram Type= 6, Freq= 0, CH_1, rank 1
8628 17:58:25.130683 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8629 17:58:25.134416 ==
8630 17:58:25.134821
8631 17:58:25.135162
8632 17:58:25.135455 TX Vref Scan disable
8633 17:58:25.137511 == TX Byte 0 ==
8634 17:58:25.140730 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8635 17:58:25.144371 == TX Byte 1 ==
8636 17:58:25.147282 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8637 17:58:25.151104 DramC Write-DBI off
8638 17:58:25.151510
8639 17:58:25.151835 [DATLAT]
8640 17:58:25.152129 Freq=1600, CH1 RK1
8641 17:58:25.152416
8642 17:58:25.154207 DATLAT Default: 0xe
8643 17:58:25.154619 0, 0xFFFF, sum = 0
8644 17:58:25.157478 1, 0xFFFF, sum = 0
8645 17:58:25.160671 2, 0xFFFF, sum = 0
8646 17:58:25.161089 3, 0xFFFF, sum = 0
8647 17:58:25.164239 4, 0xFFFF, sum = 0
8648 17:58:25.164680 5, 0xFFFF, sum = 0
8649 17:58:25.167363 6, 0xFFFF, sum = 0
8650 17:58:25.167805 7, 0xFFFF, sum = 0
8651 17:58:25.170671 8, 0xFFFF, sum = 0
8652 17:58:25.171198 9, 0xFFFF, sum = 0
8653 17:58:25.174282 10, 0xFFFF, sum = 0
8654 17:58:25.174889 11, 0xFFFF, sum = 0
8655 17:58:25.177485 12, 0xF7F, sum = 0
8656 17:58:25.177937 13, 0x0, sum = 1
8657 17:58:25.180723 14, 0x0, sum = 2
8658 17:58:25.181137 15, 0x0, sum = 3
8659 17:58:25.183887 16, 0x0, sum = 4
8660 17:58:25.184302 best_step = 14
8661 17:58:25.184619
8662 17:58:25.184918 ==
8663 17:58:25.187462 Dram Type= 6, Freq= 0, CH_1, rank 1
8664 17:58:25.190420 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8665 17:58:25.193904 ==
8666 17:58:25.194452 RX Vref Scan: 0
8667 17:58:25.194784
8668 17:58:25.196860 RX Vref 0 -> 0, step: 1
8669 17:58:25.197282
8670 17:58:25.200683 RX Delay 3 -> 252, step: 4
8671 17:58:25.203544 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8672 17:58:25.206653 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8673 17:58:25.210368 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8674 17:58:25.216924 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8675 17:58:25.219823 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8676 17:58:25.222972 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8677 17:58:25.226972 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8678 17:58:25.229904 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8679 17:58:25.236662 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8680 17:58:25.239694 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8681 17:58:25.243504 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8682 17:58:25.246756 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8683 17:58:25.249688 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8684 17:58:25.256554 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8685 17:58:25.259805 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8686 17:58:25.262938 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8687 17:58:25.263230 ==
8688 17:58:25.265961 Dram Type= 6, Freq= 0, CH_1, rank 1
8689 17:58:25.269139 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8690 17:58:25.273038 ==
8691 17:58:25.273257 DQS Delay:
8692 17:58:25.273429 DQS0 = 0, DQS1 = 0
8693 17:58:25.276011 DQM Delay:
8694 17:58:25.276229 DQM0 = 127, DQM1 = 122
8695 17:58:25.279638 DQ Delay:
8696 17:58:25.282638 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =124
8697 17:58:25.285972 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8698 17:58:25.289000 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =114
8699 17:58:25.292768 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =130
8700 17:58:25.292989
8701 17:58:25.293160
8702 17:58:25.293320
8703 17:58:25.296024 [DramC_TX_OE_Calibration] TA2
8704 17:58:25.299727 Original DQ_B0 (3 6) =30, OEN = 27
8705 17:58:25.302595 Original DQ_B1 (3 6) =30, OEN = 27
8706 17:58:25.306079 24, 0x0, End_B0=24 End_B1=24
8707 17:58:25.306303 25, 0x0, End_B0=25 End_B1=25
8708 17:58:25.309365 26, 0x0, End_B0=26 End_B1=26
8709 17:58:25.312501 27, 0x0, End_B0=27 End_B1=27
8710 17:58:25.315732 28, 0x0, End_B0=28 End_B1=28
8711 17:58:25.315814 29, 0x0, End_B0=29 End_B1=29
8712 17:58:25.318953 30, 0x0, End_B0=30 End_B1=30
8713 17:58:25.322575 31, 0x5151, End_B0=30 End_B1=30
8714 17:58:25.326148 Byte0 end_step=30 best_step=27
8715 17:58:25.329086 Byte1 end_step=30 best_step=27
8716 17:58:25.332231 Byte0 TX OE(2T, 0.5T) = (3, 3)
8717 17:58:25.332310 Byte1 TX OE(2T, 0.5T) = (3, 3)
8718 17:58:25.332373
8719 17:58:25.336149
8720 17:58:25.342297 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8721 17:58:25.345979 CH1 RK1: MR19=303, MR18=1C1C
8722 17:58:25.352473 CH1_RK1: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8723 17:58:25.355903 [RxdqsGatingPostProcess] freq 1600
8724 17:58:25.358950 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8725 17:58:25.362516 Pre-setting of DQS Precalculation
8726 17:58:25.368733 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8727 17:58:25.375938 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8728 17:58:25.382003 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8729 17:58:25.382489
8730 17:58:25.382818
8731 17:58:25.385529 [Calibration Summary] 3200 Mbps
8732 17:58:25.385942 CH 0, Rank 0
8733 17:58:25.388555 SW Impedance : PASS
8734 17:58:25.391698 DUTY Scan : NO K
8735 17:58:25.392255 ZQ Calibration : PASS
8736 17:58:25.395507 Jitter Meter : NO K
8737 17:58:25.398776 CBT Training : PASS
8738 17:58:25.399190 Write leveling : PASS
8739 17:58:25.401815 RX DQS gating : PASS
8740 17:58:25.404989 RX DQ/DQS(RDDQC) : PASS
8741 17:58:25.405212 TX DQ/DQS : PASS
8742 17:58:25.408445 RX DATLAT : PASS
8743 17:58:25.411324 RX DQ/DQS(Engine): PASS
8744 17:58:25.411509 TX OE : PASS
8745 17:58:25.415039 All Pass.
8746 17:58:25.415217
8747 17:58:25.415358 CH 0, Rank 1
8748 17:58:25.418073 SW Impedance : PASS
8749 17:58:25.418250 DUTY Scan : NO K
8750 17:58:25.421222 ZQ Calibration : PASS
8751 17:58:25.424477 Jitter Meter : NO K
8752 17:58:25.424654 CBT Training : PASS
8753 17:58:25.428173 Write leveling : PASS
8754 17:58:25.431068 RX DQS gating : PASS
8755 17:58:25.431253 RX DQ/DQS(RDDQC) : PASS
8756 17:58:25.434547 TX DQ/DQS : PASS
8757 17:58:25.438199 RX DATLAT : PASS
8758 17:58:25.438379 RX DQ/DQS(Engine): PASS
8759 17:58:25.441330 TX OE : PASS
8760 17:58:25.441512 All Pass.
8761 17:58:25.441655
8762 17:58:25.441788 CH 1, Rank 0
8763 17:58:25.444519 SW Impedance : PASS
8764 17:58:25.447677 DUTY Scan : NO K
8765 17:58:25.447875 ZQ Calibration : PASS
8766 17:58:25.451140 Jitter Meter : NO K
8767 17:58:25.454349 CBT Training : PASS
8768 17:58:25.454530 Write leveling : PASS
8769 17:58:25.458226 RX DQS gating : PASS
8770 17:58:25.461295 RX DQ/DQS(RDDQC) : PASS
8771 17:58:25.461475 TX DQ/DQS : PASS
8772 17:58:25.464326 RX DATLAT : PASS
8773 17:58:25.467979 RX DQ/DQS(Engine): PASS
8774 17:58:25.468152 TX OE : PASS
8775 17:58:25.470992 All Pass.
8776 17:58:25.471179
8777 17:58:25.471322 CH 1, Rank 1
8778 17:58:25.474289 SW Impedance : PASS
8779 17:58:25.474472 DUTY Scan : NO K
8780 17:58:25.477923 ZQ Calibration : PASS
8781 17:58:25.481094 Jitter Meter : NO K
8782 17:58:25.481324 CBT Training : PASS
8783 17:58:25.484305 Write leveling : PASS
8784 17:58:25.487566 RX DQS gating : PASS
8785 17:58:25.487859 RX DQ/DQS(RDDQC) : PASS
8786 17:58:25.491237 TX DQ/DQS : PASS
8787 17:58:25.494280 RX DATLAT : PASS
8788 17:58:25.494598 RX DQ/DQS(Engine): PASS
8789 17:58:25.497663 TX OE : PASS
8790 17:58:25.498170 All Pass.
8791 17:58:25.498606
8792 17:58:25.500874 DramC Write-DBI on
8793 17:58:25.504052 PER_BANK_REFRESH: Hybrid Mode
8794 17:58:25.504437 TX_TRACKING: ON
8795 17:58:25.514258 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8796 17:58:25.520423 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8797 17:58:25.527452 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8798 17:58:25.530237 [FAST_K] Save calibration result to emmc
8799 17:58:25.533593 sync common calibartion params.
8800 17:58:25.537041 sync cbt_mode0:0, 1:0
8801 17:58:25.540456 dram_init: ddr_geometry: 0
8802 17:58:25.540627 dram_init: ddr_geometry: 0
8803 17:58:25.543349 dram_init: ddr_geometry: 0
8804 17:58:25.546654 0:dram_rank_size:80000000
8805 17:58:25.546779 1:dram_rank_size:80000000
8806 17:58:25.553512 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8807 17:58:25.557005 DFS_SHUFFLE_HW_MODE: ON
8808 17:58:25.560164 dramc_set_vcore_voltage set vcore to 725000
8809 17:58:25.563396 Read voltage for 1600, 0
8810 17:58:25.563524 Vio18 = 0
8811 17:58:25.563627 Vcore = 725000
8812 17:58:25.566636 Vdram = 0
8813 17:58:25.566771 Vddq = 0
8814 17:58:25.566877 Vmddr = 0
8815 17:58:25.569645 switch to 3200 Mbps bootup
8816 17:58:25.569829 [DramcRunTimeConfig]
8817 17:58:25.573420 PHYPLL
8818 17:58:25.573542 DPM_CONTROL_AFTERK: ON
8819 17:58:25.576514 PER_BANK_REFRESH: ON
8820 17:58:25.579800 REFRESH_OVERHEAD_REDUCTION: ON
8821 17:58:25.579921 CMD_PICG_NEW_MODE: OFF
8822 17:58:25.583374 XRTWTW_NEW_MODE: ON
8823 17:58:25.583506 XRTRTR_NEW_MODE: ON
8824 17:58:25.586614 TX_TRACKING: ON
8825 17:58:25.586751 RDSEL_TRACKING: OFF
8826 17:58:25.589742 DQS Precalculation for DVFS: ON
8827 17:58:25.592910 RX_TRACKING: OFF
8828 17:58:25.593062 HW_GATING DBG: ON
8829 17:58:25.596666 ZQCS_ENABLE_LP4: ON
8830 17:58:25.596861 RX_PICG_NEW_MODE: ON
8831 17:58:25.599562 TX_PICG_NEW_MODE: ON
8832 17:58:25.603119 ENABLE_RX_DCM_DPHY: ON
8833 17:58:25.603350 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8834 17:58:25.606190 DUMMY_READ_FOR_TRACKING: OFF
8835 17:58:25.609623 !!! SPM_CONTROL_AFTERK: OFF
8836 17:58:25.612793 !!! SPM could not control APHY
8837 17:58:25.616773 IMPEDANCE_TRACKING: ON
8838 17:58:25.617161 TEMP_SENSOR: ON
8839 17:58:25.619905 HW_SAVE_FOR_SR: OFF
8840 17:58:25.620336 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8841 17:58:25.626448 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8842 17:58:25.626805 Read ODT Tracking: ON
8843 17:58:25.629560 Refresh Rate DeBounce: ON
8844 17:58:25.630105 DFS_NO_QUEUE_FLUSH: ON
8845 17:58:25.633051 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8846 17:58:25.635968 ENABLE_DFS_RUNTIME_MRW: OFF
8847 17:58:25.639404 DDR_RESERVE_NEW_MODE: ON
8848 17:58:25.642294 MR_CBT_SWITCH_FREQ: ON
8849 17:58:25.642739 =========================
8850 17:58:25.661961 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8851 17:58:25.665085 dram_init: ddr_geometry: 0
8852 17:58:25.683111 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8853 17:58:25.686149 dram_init: dram init end (result: 0)
8854 17:58:25.693068 DRAM-K: Full calibration passed in 23401 msecs
8855 17:58:25.696189 MRC: failed to locate region type 0.
8856 17:58:25.696377 DRAM rank0 size:0x80000000,
8857 17:58:25.699389 DRAM rank1 size=0x80000000
8858 17:58:25.709152 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8859 17:58:25.715943 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8860 17:58:25.722278 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8861 17:58:25.732530 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8862 17:58:25.732652 DRAM rank0 size:0x80000000,
8863 17:58:25.735686 DRAM rank1 size=0x80000000
8864 17:58:25.735800 CBMEM:
8865 17:58:25.738839 IMD: root @ 0xfffff000 254 entries.
8866 17:58:25.742539 IMD: root @ 0xffffec00 62 entries.
8867 17:58:25.745837 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8868 17:58:25.752491 WARNING: RO_VPD is uninitialized or empty.
8869 17:58:25.755465 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8870 17:58:25.762644 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8871 17:58:25.775457 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8872 17:58:25.787420 BS: romstage times (exec / console): total (unknown) / 22943 ms
8873 17:58:25.787660
8874 17:58:25.787867
8875 17:58:25.797082 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8876 17:58:25.800204 ARM64: Exception handlers installed.
8877 17:58:25.803471 ARM64: Testing exception
8878 17:58:25.806559 ARM64: Done test exception
8879 17:58:25.806977 Enumerating buses...
8880 17:58:25.810269 Show all devs... Before device enumeration.
8881 17:58:25.813437 Root Device: enabled 1
8882 17:58:25.817111 CPU_CLUSTER: 0: enabled 1
8883 17:58:25.817581 CPU: 00: enabled 1
8884 17:58:25.820326 Compare with tree...
8885 17:58:25.820828 Root Device: enabled 1
8886 17:58:25.823510 CPU_CLUSTER: 0: enabled 1
8887 17:58:25.826589 CPU: 00: enabled 1
8888 17:58:25.827065 Root Device scanning...
8889 17:58:25.829775 scan_static_bus for Root Device
8890 17:58:25.833431 CPU_CLUSTER: 0 enabled
8891 17:58:25.836557 scan_static_bus for Root Device done
8892 17:58:25.839711 scan_bus: bus Root Device finished in 8 msecs
8893 17:58:25.840146 done
8894 17:58:25.846869 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8895 17:58:25.849845 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8896 17:58:25.856373 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8897 17:58:25.859978 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8898 17:58:25.863545 Allocating resources...
8899 17:58:25.866457 Reading resources...
8900 17:58:25.870015 Root Device read_resources bus 0 link: 0
8901 17:58:25.870477 DRAM rank0 size:0x80000000,
8902 17:58:25.873191 DRAM rank1 size=0x80000000
8903 17:58:25.876280 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8904 17:58:25.880009 CPU: 00 missing read_resources
8905 17:58:25.886691 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8906 17:58:25.889904 Root Device read_resources bus 0 link: 0 done
8907 17:58:25.890399 Done reading resources.
8908 17:58:25.896265 Show resources in subtree (Root Device)...After reading.
8909 17:58:25.899605 Root Device child on link 0 CPU_CLUSTER: 0
8910 17:58:25.902935 CPU_CLUSTER: 0 child on link 0 CPU: 00
8911 17:58:25.912759 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8912 17:58:25.913372 CPU: 00
8913 17:58:25.916055 Root Device assign_resources, bus 0 link: 0
8914 17:58:25.919822 CPU_CLUSTER: 0 missing set_resources
8915 17:58:25.926127 Root Device assign_resources, bus 0 link: 0 done
8916 17:58:25.926575 Done setting resources.
8917 17:58:25.932518 Show resources in subtree (Root Device)...After assigning values.
8918 17:58:25.936302 Root Device child on link 0 CPU_CLUSTER: 0
8919 17:58:25.939326 CPU_CLUSTER: 0 child on link 0 CPU: 00
8920 17:58:25.949484 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8921 17:58:25.949907 CPU: 00
8922 17:58:25.952540 Done allocating resources.
8923 17:58:25.959112 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8924 17:58:25.959531 Enabling resources...
8925 17:58:25.959860 done.
8926 17:58:25.965785 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8927 17:58:25.966253 Initializing devices...
8928 17:58:25.969001 Root Device init
8929 17:58:25.972136 init hardware done!
8930 17:58:25.972551 0x00000018: ctrlr->caps
8931 17:58:25.975701 52.000 MHz: ctrlr->f_max
8932 17:58:25.978755 0.400 MHz: ctrlr->f_min
8933 17:58:25.979182 0x40ff8080: ctrlr->voltages
8934 17:58:25.981838 sclk: 390625
8935 17:58:25.982251 Bus Width = 1
8936 17:58:25.982573 sclk: 390625
8937 17:58:25.985711 Bus Width = 1
8938 17:58:25.986202 Early init status = 3
8939 17:58:25.992037 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8940 17:58:25.995249 in-header: 03 fc 00 00 01 00 00 00
8941 17:58:25.998950 in-data: 00
8942 17:58:26.001777 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8943 17:58:26.006125 in-header: 03 fd 00 00 00 00 00 00
8944 17:58:26.009141 in-data:
8945 17:58:26.012455 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8946 17:58:26.016321 in-header: 03 fc 00 00 01 00 00 00
8947 17:58:26.019667 in-data: 00
8948 17:58:26.023267 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8949 17:58:26.028711 in-header: 03 fd 00 00 00 00 00 00
8950 17:58:26.031842 in-data:
8951 17:58:26.034991 [SSUSB] Setting up USB HOST controller...
8952 17:58:26.038180 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8953 17:58:26.041374 [SSUSB] phy power-on done.
8954 17:58:26.044957 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8955 17:58:26.051279 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8956 17:58:26.054406 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8957 17:58:26.061273 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8958 17:58:26.067609 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
8959 17:58:26.074468 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8960 17:58:26.081020 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8961 17:58:26.087732 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8962 17:58:26.090907 SPM: binary array size = 0x9dc
8963 17:58:26.094010 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8964 17:58:26.100869 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8965 17:58:26.107184 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8966 17:58:26.114039 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8967 17:58:26.117154 configure_display: Starting display init
8968 17:58:26.151298 anx7625_power_on_init: Init interface.
8969 17:58:26.154513 anx7625_disable_pd_protocol: Disabled PD feature.
8970 17:58:26.157646 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8971 17:58:26.185553 anx7625_start_dp_work: Secure OCM version=00
8972 17:58:26.189080 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8973 17:58:26.203517 sp_tx_get_edid_block: EDID Block = 1
8974 17:58:26.306232 Extracted contents:
8975 17:58:26.309856 header: 00 ff ff ff ff ff ff 00
8976 17:58:26.313182 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8977 17:58:26.316251 version: 01 04
8978 17:58:26.319974 basic params: 95 1f 11 78 0a
8979 17:58:26.322989 chroma info: 76 90 94 55 54 90 27 21 50 54
8980 17:58:26.326088 established: 00 00 00
8981 17:58:26.333089 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8982 17:58:26.339253 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8983 17:58:26.342458 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8984 17:58:26.349424 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8985 17:58:26.355795 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8986 17:58:26.359818 extensions: 00
8987 17:58:26.360223 checksum: fb
8988 17:58:26.360479
8989 17:58:26.365954 Manufacturer: IVO Model 57d Serial Number 0
8990 17:58:26.366329 Made week 0 of 2020
8991 17:58:26.369284 EDID version: 1.4
8992 17:58:26.369580 Digital display
8993 17:58:26.372526 6 bits per primary color channel
8994 17:58:26.372843 DisplayPort interface
8995 17:58:26.375794 Maximum image size: 31 cm x 17 cm
8996 17:58:26.378814 Gamma: 220%
8997 17:58:26.379181 Check DPMS levels
8998 17:58:26.382352 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
8999 17:58:26.389491 First detailed timing is preferred timing
9000 17:58:26.389907 Established timings supported:
9001 17:58:26.392731 Standard timings supported:
9002 17:58:26.395819 Detailed timings
9003 17:58:26.398832 Hex of detail: 383680a07038204018303c0035ae10000019
9004 17:58:26.405678 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9005 17:58:26.408826 0780 0798 07c8 0820 hborder 0
9006 17:58:26.411948 0438 043b 0447 0458 vborder 0
9007 17:58:26.415252 -hsync -vsync
9008 17:58:26.415673 Did detailed timing
9009 17:58:26.421871 Hex of detail: 000000000000000000000000000000000000
9010 17:58:26.425615 Manufacturer-specified data, tag 0
9011 17:58:26.428577 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9012 17:58:26.431683 ASCII string: InfoVision
9013 17:58:26.434960 Hex of detail: 000000fe00523134304e574635205248200a
9014 17:58:26.438202 ASCII string: R140NWF5 RH
9015 17:58:26.438422 Checksum
9016 17:58:26.441872 Checksum: 0xfb (valid)
9017 17:58:26.444991 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9018 17:58:26.448197 DSI data_rate: 832800000 bps
9019 17:58:26.454595 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9020 17:58:26.458407 anx7625_parse_edid: pixelclock(138800).
9021 17:58:26.461485 hactive(1920), hsync(48), hfp(24), hbp(88)
9022 17:58:26.464591 vactive(1080), vsync(12), vfp(3), vbp(17)
9023 17:58:26.468164 anx7625_dsi_config: config dsi.
9024 17:58:26.474558 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9025 17:58:26.488333 anx7625_dsi_config: success to config DSI
9026 17:58:26.491688 anx7625_dp_start: MIPI phy setup OK.
9027 17:58:26.495410 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9028 17:58:26.498572 mtk_ddp_mode_set invalid vrefresh 60
9029 17:58:26.501744 main_disp_path_setup
9030 17:58:26.502189 ovl_layer_smi_id_en
9031 17:58:26.505352 ovl_layer_smi_id_en
9032 17:58:26.505777 ccorr_config
9033 17:58:26.506358 aal_config
9034 17:58:26.508410 gamma_config
9035 17:58:26.508818 postmask_config
9036 17:58:26.511770 dither_config
9037 17:58:26.514799 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9038 17:58:26.521533 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9039 17:58:26.524728 Root Device init finished in 552 msecs
9040 17:58:26.528443 CPU_CLUSTER: 0 init
9041 17:58:26.534953 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9042 17:58:26.541177 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9043 17:58:26.541738 APU_MBOX 0x190000b0 = 0x10001
9044 17:58:26.544353 APU_MBOX 0x190001b0 = 0x10001
9045 17:58:26.548015 APU_MBOX 0x190005b0 = 0x10001
9046 17:58:26.551121 APU_MBOX 0x190006b0 = 0x10001
9047 17:58:26.558067 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9048 17:58:26.567413 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9049 17:58:26.579930 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9050 17:58:26.586314 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9051 17:58:26.597943 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9052 17:58:26.607377 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9053 17:58:26.610684 CPU_CLUSTER: 0 init finished in 81 msecs
9054 17:58:26.613565 Devices initialized
9055 17:58:26.616975 Show all devs... After init.
9056 17:58:26.617154 Root Device: enabled 1
9057 17:58:26.620529 CPU_CLUSTER: 0: enabled 1
9058 17:58:26.624044 CPU: 00: enabled 1
9059 17:58:26.627368 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9060 17:58:26.630593 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9061 17:58:26.633544 ELOG: NV offset 0x57f000 size 0x1000
9062 17:58:26.640183 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9063 17:58:26.646603 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9064 17:58:26.650379 ELOG: Event(17) added with size 13 at 2024-04-25 17:58:25 UTC
9065 17:58:26.656675 out: cmd=0x121: 03 db 21 01 00 00 00 00
9066 17:58:26.659691 in-header: 03 f8 00 00 2c 00 00 00
9067 17:58:26.673464 in-data: 6b 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9068 17:58:26.676665 ELOG: Event(A1) added with size 10 at 2024-04-25 17:58:25 UTC
9069 17:58:26.682983 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9070 17:58:26.689897 ELOG: Event(A0) added with size 9 at 2024-04-25 17:58:25 UTC
9071 17:58:26.692998 elog_add_boot_reason: Logged dev mode boot
9072 17:58:26.699495 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9073 17:58:26.699588 Finalize devices...
9074 17:58:26.703265 Devices finalized
9075 17:58:26.706433 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9076 17:58:26.709399 Writing coreboot table at 0xffe64000
9077 17:58:26.716348 0. 000000000010a000-0000000000113fff: RAMSTAGE
9078 17:58:26.719795 1. 0000000040000000-00000000400fffff: RAM
9079 17:58:26.722710 2. 0000000040100000-000000004032afff: RAMSTAGE
9080 17:58:26.726204 3. 000000004032b000-00000000545fffff: RAM
9081 17:58:26.729433 4. 0000000054600000-000000005465ffff: BL31
9082 17:58:26.732454 5. 0000000054660000-00000000ffe63fff: RAM
9083 17:58:26.739597 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9084 17:58:26.742962 7. 0000000100000000-000000013fffffff: RAM
9085 17:58:26.745972 Passing 5 GPIOs to payload:
9086 17:58:26.749255 NAME | PORT | POLARITY | VALUE
9087 17:58:26.755980 EC in RW | 0x000000aa | low | undefined
9088 17:58:26.759539 EC interrupt | 0x00000005 | low | undefined
9089 17:58:26.765884 TPM interrupt | 0x000000ab | high | undefined
9090 17:58:26.769116 SD card detect | 0x00000011 | high | undefined
9091 17:58:26.772358 speaker enable | 0x00000093 | high | undefined
9092 17:58:26.775592 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9093 17:58:26.779275 in-header: 03 f8 00 00 02 00 00 00
9094 17:58:26.782475 in-data: 03 00
9095 17:58:26.785732 ADC[4]: Raw value=668222 ID=5
9096 17:58:26.789506 ADC[3]: Raw value=212180 ID=1
9097 17:58:26.789794 RAM Code: 0x51
9098 17:58:26.792648 ADC[6]: Raw value=74410 ID=0
9099 17:58:26.795850 ADC[5]: Raw value=211812 ID=1
9100 17:58:26.796039 SKU Code: 0x1
9101 17:58:26.802092 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum bdc
9102 17:58:26.802242 coreboot table: 964 bytes.
9103 17:58:26.805926 IMD ROOT 0. 0xfffff000 0x00001000
9104 17:58:26.809008 IMD SMALL 1. 0xffffe000 0x00001000
9105 17:58:26.812152 RO MCACHE 2. 0xffffc000 0x00001104
9106 17:58:26.815168 CONSOLE 3. 0xfff7c000 0x00080000
9107 17:58:26.819108 FMAP 4. 0xfff7b000 0x00000452
9108 17:58:26.822248 TIME STAMP 5. 0xfff7a000 0x00000910
9109 17:58:26.825359 VBOOT WORK 6. 0xfff66000 0x00014000
9110 17:58:26.828978 RAMOOPS 7. 0xffe66000 0x00100000
9111 17:58:26.831845 COREBOOT 8. 0xffe64000 0x00002000
9112 17:58:26.835605 IMD small region:
9113 17:58:26.838659 IMD ROOT 0. 0xffffec00 0x00000400
9114 17:58:26.841938 VPD 1. 0xffffeb80 0x0000006c
9115 17:58:26.845083 MMC STATUS 2. 0xffffeb60 0x00000004
9116 17:58:26.851887 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9117 17:58:26.851969 Probing TPM: done!
9118 17:58:26.858611 Connected to device vid:did:rid of 1ae0:0028:00
9119 17:58:26.865066 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9120 17:58:26.868952 Initialized TPM device CR50 revision 0
9121 17:58:26.871816 Checking cr50 for pending updates
9122 17:58:26.877743 Reading cr50 TPM mode
9123 17:58:26.885973 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9124 17:58:26.892389 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9125 17:58:26.932991 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9126 17:58:26.936230 Checking segment from ROM address 0x40100000
9127 17:58:26.939905 Checking segment from ROM address 0x4010001c
9128 17:58:26.946386 Loading segment from ROM address 0x40100000
9129 17:58:26.946825 code (compression=0)
9130 17:58:26.956027 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9131 17:58:26.962928 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9132 17:58:26.963384 it's not compressed!
9133 17:58:26.969478 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9134 17:58:26.976287 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9135 17:58:26.993436 Loading segment from ROM address 0x4010001c
9136 17:58:26.993855 Entry Point 0x80000000
9137 17:58:26.996814 Loaded segments
9138 17:58:26.999810 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9139 17:58:27.006879 Jumping to boot code at 0x80000000(0xffe64000)
9140 17:58:27.013717 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9141 17:58:27.020195 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9142 17:58:27.028042 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9143 17:58:27.031324 Checking segment from ROM address 0x40100000
9144 17:58:27.034482 Checking segment from ROM address 0x4010001c
9145 17:58:27.040706 Loading segment from ROM address 0x40100000
9146 17:58:27.041238 code (compression=1)
9147 17:58:27.047521 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9148 17:58:27.057342 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9149 17:58:27.057528 using LZMA
9150 17:58:27.066304 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9151 17:58:27.072559 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9152 17:58:27.076036 Loading segment from ROM address 0x4010001c
9153 17:58:27.076144 Entry Point 0x54601000
9154 17:58:27.079149 Loaded segments
9155 17:58:27.082320 NOTICE: MT8192 bl31_setup
9156 17:58:27.089617 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9157 17:58:27.092514 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9158 17:58:27.096134 WARNING: region 0:
9159 17:58:27.099237 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9160 17:58:27.099318 WARNING: region 1:
9161 17:58:27.106102 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9162 17:58:27.109564 WARNING: region 2:
9163 17:58:27.112739 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9164 17:58:27.116048 WARNING: region 3:
9165 17:58:27.119291 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9166 17:58:27.122501 WARNING: region 4:
9167 17:58:27.129415 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9168 17:58:27.129509 WARNING: region 5:
9169 17:58:27.132598 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9170 17:58:27.136459 WARNING: region 6:
9171 17:58:27.139499 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9172 17:58:27.139608 WARNING: region 7:
9173 17:58:27.146300 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9174 17:58:27.153181 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9175 17:58:27.156417 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9176 17:58:27.159413 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9177 17:58:27.166452 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9178 17:58:27.169717 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9179 17:58:27.172932 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9180 17:58:27.179209 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9181 17:58:27.182785 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9182 17:58:27.189195 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9183 17:58:27.193057 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9184 17:58:27.196080 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9185 17:58:27.202497 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9186 17:58:27.206075 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9187 17:58:27.209116 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9188 17:58:27.216292 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9189 17:58:27.219163 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9190 17:58:27.226291 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9191 17:58:27.229460 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9192 17:58:27.232440 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9193 17:58:27.239198 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9194 17:58:27.242370 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9195 17:58:27.248950 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9196 17:58:27.252243 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9197 17:58:27.255907 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9198 17:58:27.262693 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9199 17:58:27.265875 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9200 17:58:27.272207 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9201 17:58:27.275377 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9202 17:58:27.279123 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9203 17:58:27.285373 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9204 17:58:27.289166 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9205 17:58:27.295984 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9206 17:58:27.299179 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9207 17:58:27.302096 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9208 17:58:27.305863 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9209 17:58:27.308914 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9210 17:58:27.315370 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9211 17:58:27.318908 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9212 17:58:27.321957 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9213 17:58:27.325418 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9214 17:58:27.332080 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9215 17:58:27.335320 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9216 17:58:27.338902 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9217 17:58:27.342103 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9218 17:58:27.348860 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9219 17:58:27.352028 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9220 17:58:27.355576 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9221 17:58:27.362363 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9222 17:58:27.365950 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9223 17:58:27.368976 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9224 17:58:27.375384 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9225 17:58:27.379277 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9226 17:58:27.385604 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9227 17:58:27.388638 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9228 17:58:27.392281 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9229 17:58:27.398864 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9230 17:58:27.402126 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9231 17:58:27.408898 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9232 17:58:27.412410 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9233 17:58:27.419119 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9234 17:58:27.421985 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9235 17:58:27.428829 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9236 17:58:27.432352 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9237 17:58:27.435480 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9238 17:58:27.442128 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9239 17:58:27.445164 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9240 17:58:27.452253 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9241 17:58:27.455353 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9242 17:58:27.462203 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9243 17:58:27.465595 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9244 17:58:27.468655 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9245 17:58:27.475111 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9246 17:58:27.479165 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9247 17:58:27.485265 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9248 17:58:27.488700 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9249 17:58:27.495491 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9250 17:58:27.498486 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9251 17:58:27.502175 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9252 17:58:27.508464 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9253 17:58:27.512237 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9254 17:58:27.518779 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9255 17:58:27.521871 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9256 17:58:27.528702 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9257 17:58:27.532487 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9258 17:58:27.535936 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9259 17:58:27.542654 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9260 17:58:27.545397 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9261 17:58:27.552277 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9262 17:58:27.555504 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9263 17:58:27.562432 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9264 17:58:27.565396 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9265 17:58:27.569055 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9266 17:58:27.575720 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9267 17:58:27.579048 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9268 17:58:27.585658 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9269 17:58:27.588664 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9270 17:58:27.592542 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9271 17:58:27.598989 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9272 17:58:27.601997 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9273 17:58:27.605678 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9274 17:58:27.608453 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9275 17:58:27.615369 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9276 17:58:27.618925 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9277 17:58:27.625677 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9278 17:58:27.628983 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9279 17:58:27.631914 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9280 17:58:27.638760 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9281 17:58:27.641673 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9282 17:58:27.648524 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9283 17:58:27.651877 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9284 17:58:27.655130 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9285 17:58:27.661997 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9286 17:58:27.665230 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9287 17:58:27.672194 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9288 17:58:27.675303 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9289 17:58:27.678436 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9290 17:58:27.685329 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9291 17:58:27.688529 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9292 17:58:27.692032 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9293 17:58:27.698998 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9294 17:58:27.702210 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9295 17:58:27.705271 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9296 17:58:27.708539 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9297 17:58:27.712280 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9298 17:58:27.718883 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9299 17:58:27.721844 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9300 17:58:27.728799 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9301 17:58:27.732000 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9302 17:58:27.735446 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9303 17:58:27.742010 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9304 17:58:27.745075 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9305 17:58:27.752346 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9306 17:58:27.755279 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9307 17:58:27.758309 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9308 17:58:27.765353 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9309 17:58:27.768398 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9310 17:58:27.775260 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9311 17:58:27.778623 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9312 17:58:27.781791 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9313 17:58:27.788695 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9314 17:58:27.792034 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9315 17:58:27.795420 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9316 17:58:27.801920 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9317 17:58:27.805557 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9318 17:58:27.812522 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9319 17:58:27.815399 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9320 17:58:27.819192 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9321 17:58:27.825457 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9322 17:58:27.829232 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9323 17:58:27.835418 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9324 17:58:27.839138 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9325 17:58:27.842172 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9326 17:58:27.849106 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9327 17:58:27.852184 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9328 17:58:27.855203 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9329 17:58:27.862443 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9330 17:58:27.865536 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9331 17:58:27.872143 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9332 17:58:27.875111 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9333 17:58:27.878522 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9334 17:58:27.885291 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9335 17:58:27.888526 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9336 17:58:27.895584 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9337 17:58:27.898634 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9338 17:58:27.901819 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9339 17:58:27.908465 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9340 17:58:27.911797 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9341 17:58:27.918073 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9342 17:58:27.921868 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9343 17:58:27.925002 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9344 17:58:27.931486 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9345 17:58:27.934810 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9346 17:58:27.941223 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9347 17:58:27.944807 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9348 17:58:27.948416 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9349 17:58:27.954637 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9350 17:58:27.957699 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9351 17:58:27.964276 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9352 17:58:27.967694 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9353 17:58:27.970900 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9354 17:58:27.977686 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9355 17:58:27.980714 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9356 17:58:27.987950 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9357 17:58:27.991071 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9358 17:58:27.994164 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9359 17:58:28.001161 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9360 17:58:28.004339 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9361 17:58:28.010470 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9362 17:58:28.014337 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9363 17:58:28.017349 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9364 17:58:28.024270 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9365 17:58:28.027348 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9366 17:58:28.033878 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9367 17:58:28.037117 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9368 17:58:28.043875 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9369 17:58:28.047396 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9370 17:58:28.050245 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9371 17:58:28.057287 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9372 17:58:28.060432 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9373 17:58:28.067416 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9374 17:58:28.070537 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9375 17:58:28.077010 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9376 17:58:28.080404 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9377 17:58:28.083501 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9378 17:58:28.090146 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9379 17:58:28.093005 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9380 17:58:28.099819 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9381 17:58:28.102930 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9382 17:58:28.109996 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9383 17:58:28.112874 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9384 17:58:28.116146 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9385 17:58:28.122830 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9386 17:58:28.125930 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9387 17:58:28.132540 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9388 17:58:28.135779 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9389 17:58:28.139079 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9390 17:58:28.146040 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9391 17:58:28.149224 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9392 17:58:28.155724 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9393 17:58:28.159445 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9394 17:58:28.165604 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9395 17:58:28.168946 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9396 17:58:28.172469 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9397 17:58:28.178811 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9398 17:58:28.182509 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9399 17:58:28.189266 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9400 17:58:28.192264 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9401 17:58:28.199025 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9402 17:58:28.202636 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9403 17:58:28.205849 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9404 17:58:28.209051 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9405 17:58:28.215790 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9406 17:58:28.218854 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9407 17:58:28.222111 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9408 17:58:28.225389 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9409 17:58:28.232347 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9410 17:58:28.235343 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9411 17:58:28.241905 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9412 17:58:28.245551 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9413 17:58:28.248816 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9414 17:58:28.255106 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9415 17:58:28.258950 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9416 17:58:28.262240 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9417 17:58:28.268537 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9418 17:58:28.271719 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9419 17:58:28.278692 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9420 17:58:28.282222 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9421 17:58:28.285514 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9422 17:58:28.291806 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9423 17:58:28.295092 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9424 17:58:28.298551 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9425 17:58:28.305509 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9426 17:58:28.308525 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9427 17:58:28.311535 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9428 17:58:28.318489 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9429 17:58:28.321741 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9430 17:58:28.328595 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9431 17:58:28.331663 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9432 17:58:28.334989 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9433 17:58:28.341444 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9434 17:58:28.344529 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9435 17:58:28.348027 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9436 17:58:28.354766 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9437 17:58:28.358116 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9438 17:58:28.364168 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9439 17:58:28.367332 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9440 17:58:28.370558 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9441 17:58:28.377583 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9442 17:58:28.380858 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9443 17:58:28.384158 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9444 17:58:28.387666 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9445 17:58:28.394174 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9446 17:58:28.397668 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9447 17:58:28.401054 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9448 17:58:28.403832 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9449 17:58:28.410719 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9450 17:58:28.413999 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9451 17:58:28.417163 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9452 17:58:28.420726 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9453 17:58:28.427413 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9454 17:58:28.430532 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9455 17:58:28.434178 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9456 17:58:28.440614 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9457 17:58:28.443857 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9458 17:58:28.447023 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9459 17:58:28.454164 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9460 17:58:28.457638 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9461 17:58:28.463814 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9462 17:58:28.467040 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9463 17:58:28.473991 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9464 17:58:28.477090 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9465 17:58:28.480263 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9466 17:58:28.487336 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9467 17:58:28.490614 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9468 17:58:28.497460 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9469 17:58:28.500437 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9470 17:58:28.504033 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9471 17:58:28.510475 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9472 17:58:28.513956 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9473 17:58:28.520358 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9474 17:58:28.523335 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9475 17:58:28.526820 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9476 17:58:28.533454 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9477 17:58:28.537001 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9478 17:58:28.543577 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9479 17:58:28.546910 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9480 17:58:28.549958 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9481 17:58:28.556544 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9482 17:58:28.560514 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9483 17:58:28.566751 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9484 17:58:28.569838 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9485 17:58:28.576870 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9486 17:58:28.580142 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9487 17:58:28.583365 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9488 17:58:28.589911 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9489 17:58:28.593105 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9490 17:58:28.600131 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9491 17:58:28.603065 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9492 17:58:28.609728 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9493 17:58:28.613015 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9494 17:58:28.616228 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9495 17:58:28.622713 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9496 17:58:28.626276 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9497 17:58:28.632453 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9498 17:58:28.636216 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9499 17:58:28.639085 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9500 17:58:28.645576 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9501 17:58:28.649128 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9502 17:58:28.655913 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9503 17:58:28.659028 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9504 17:58:28.662477 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9505 17:58:28.669579 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9506 17:58:28.672542 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9507 17:58:28.679534 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9508 17:58:28.682524 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9509 17:58:28.689052 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9510 17:58:28.692112 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9511 17:58:28.695261 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9512 17:58:28.702306 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9513 17:58:28.705519 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9514 17:58:28.712636 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9515 17:58:28.715540 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9516 17:58:28.718451 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9517 17:58:28.725275 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9518 17:58:28.728459 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9519 17:58:28.735238 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9520 17:58:28.738463 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9521 17:58:28.741621 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9522 17:58:28.748770 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9523 17:58:28.751844 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9524 17:58:28.758169 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9525 17:58:28.761428 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9526 17:58:28.767950 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9527 17:58:28.771561 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9528 17:58:28.774778 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9529 17:58:28.781576 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9530 17:58:28.784345 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9531 17:58:28.791407 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9532 17:58:28.794541 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9533 17:58:28.801072 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9534 17:58:28.804362 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9535 17:58:28.808115 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9536 17:58:28.814472 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9537 17:58:28.817448 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9538 17:58:28.824230 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9539 17:58:28.827382 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9540 17:58:28.834448 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9541 17:58:28.837479 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9542 17:58:28.843875 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9543 17:58:28.847818 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9544 17:58:28.850673 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9545 17:58:28.857589 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9546 17:58:28.860602 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9547 17:58:28.867299 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9548 17:58:28.870998 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9549 17:58:28.877158 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9550 17:58:28.880547 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9551 17:58:28.887362 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9552 17:58:28.890422 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9553 17:58:28.893628 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9554 17:58:28.900621 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9555 17:58:28.903858 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9556 17:58:28.910060 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9557 17:58:28.913278 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9558 17:58:28.920264 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9559 17:58:28.923229 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9560 17:58:28.929677 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9561 17:58:28.933633 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9562 17:58:28.936802 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9563 17:58:28.943263 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9564 17:58:28.946838 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9565 17:58:28.953390 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9566 17:58:28.956410 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9567 17:58:28.963394 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9568 17:58:28.966630 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9569 17:58:28.969797 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9570 17:58:28.976743 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9571 17:58:28.980003 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9572 17:58:28.986450 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9573 17:58:28.989679 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9574 17:58:28.996426 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9575 17:58:28.999546 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9576 17:58:29.003053 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9577 17:58:29.009764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9578 17:58:29.012913 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9579 17:58:29.019264 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9580 17:58:29.022867 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9581 17:58:29.029219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9582 17:58:29.032438 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9583 17:58:29.039375 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9584 17:58:29.042450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9585 17:58:29.048917 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9586 17:58:29.052269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9587 17:58:29.058966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9588 17:58:29.062512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9589 17:58:29.069030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9590 17:58:29.072027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9591 17:58:29.078781 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9592 17:58:29.081848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9593 17:58:29.088769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9594 17:58:29.091947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9595 17:58:29.098477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9596 17:58:29.102306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9597 17:58:29.108573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9598 17:58:29.111799 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9599 17:58:29.118661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9600 17:58:29.121685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9601 17:58:29.128591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9602 17:58:29.131587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9603 17:58:29.138273 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9604 17:58:29.141415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9605 17:58:29.148112 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9606 17:58:29.151266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9607 17:58:29.157944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9608 17:58:29.161141 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9609 17:58:29.164129 INFO: [APUAPC] vio 0
9610 17:58:29.167537 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9611 17:58:29.174574 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9612 17:58:29.177785 INFO: [APUAPC] D0_APC_0: 0x400510
9613 17:58:29.177927 INFO: [APUAPC] D0_APC_1: 0x0
9614 17:58:29.180958 INFO: [APUAPC] D0_APC_2: 0x1540
9615 17:58:29.184607 INFO: [APUAPC] D0_APC_3: 0x0
9616 17:58:29.187776 INFO: [APUAPC] D1_APC_0: 0xffffffff
9617 17:58:29.190905 INFO: [APUAPC] D1_APC_1: 0xffffffff
9618 17:58:29.194536 INFO: [APUAPC] D1_APC_2: 0x3fffff
9619 17:58:29.197504 INFO: [APUAPC] D1_APC_3: 0x0
9620 17:58:29.201370 INFO: [APUAPC] D2_APC_0: 0xffffffff
9621 17:58:29.204542 INFO: [APUAPC] D2_APC_1: 0xffffffff
9622 17:58:29.207436 INFO: [APUAPC] D2_APC_2: 0x3fffff
9623 17:58:29.210661 INFO: [APUAPC] D2_APC_3: 0x0
9624 17:58:29.214513 INFO: [APUAPC] D3_APC_0: 0xffffffff
9625 17:58:29.217581 INFO: [APUAPC] D3_APC_1: 0xffffffff
9626 17:58:29.220501 INFO: [APUAPC] D3_APC_2: 0x3fffff
9627 17:58:29.223941 INFO: [APUAPC] D3_APC_3: 0x0
9628 17:58:29.227091 INFO: [APUAPC] D4_APC_0: 0xffffffff
9629 17:58:29.230675 INFO: [APUAPC] D4_APC_1: 0xffffffff
9630 17:58:29.233708 INFO: [APUAPC] D4_APC_2: 0x3fffff
9631 17:58:29.237445 INFO: [APUAPC] D4_APC_3: 0x0
9632 17:58:29.240501 INFO: [APUAPC] D5_APC_0: 0xffffffff
9633 17:58:29.244312 INFO: [APUAPC] D5_APC_1: 0xffffffff
9634 17:58:29.247377 INFO: [APUAPC] D5_APC_2: 0x3fffff
9635 17:58:29.250513 INFO: [APUAPC] D5_APC_3: 0x0
9636 17:58:29.253742 INFO: [APUAPC] D6_APC_0: 0xffffffff
9637 17:58:29.256829 INFO: [APUAPC] D6_APC_1: 0xffffffff
9638 17:58:29.260093 INFO: [APUAPC] D6_APC_2: 0x3fffff
9639 17:58:29.263843 INFO: [APUAPC] D6_APC_3: 0x0
9640 17:58:29.266885 INFO: [APUAPC] D7_APC_0: 0xffffffff
9641 17:58:29.269944 INFO: [APUAPC] D7_APC_1: 0xffffffff
9642 17:58:29.273130 INFO: [APUAPC] D7_APC_2: 0x3fffff
9643 17:58:29.276609 INFO: [APUAPC] D7_APC_3: 0x0
9644 17:58:29.279824 INFO: [APUAPC] D8_APC_0: 0xffffffff
9645 17:58:29.283077 INFO: [APUAPC] D8_APC_1: 0xffffffff
9646 17:58:29.286158 INFO: [APUAPC] D8_APC_2: 0x3fffff
9647 17:58:29.289906 INFO: [APUAPC] D8_APC_3: 0x0
9648 17:58:29.293075 INFO: [APUAPC] D9_APC_0: 0xffffffff
9649 17:58:29.296230 INFO: [APUAPC] D9_APC_1: 0xffffffff
9650 17:58:29.299443 INFO: [APUAPC] D9_APC_2: 0x3fffff
9651 17:58:29.302799 INFO: [APUAPC] D9_APC_3: 0x0
9652 17:58:29.306638 INFO: [APUAPC] D10_APC_0: 0xffffffff
9653 17:58:29.309826 INFO: [APUAPC] D10_APC_1: 0xffffffff
9654 17:58:29.313036 INFO: [APUAPC] D10_APC_2: 0x3fffff
9655 17:58:29.315940 INFO: [APUAPC] D10_APC_3: 0x0
9656 17:58:29.319421 INFO: [APUAPC] D11_APC_0: 0xffffffff
9657 17:58:29.322505 INFO: [APUAPC] D11_APC_1: 0xffffffff
9658 17:58:29.326394 INFO: [APUAPC] D11_APC_2: 0x3fffff
9659 17:58:29.329647 INFO: [APUAPC] D11_APC_3: 0x0
9660 17:58:29.333130 INFO: [APUAPC] D12_APC_0: 0xffffffff
9661 17:58:29.336127 INFO: [APUAPC] D12_APC_1: 0xffffffff
9662 17:58:29.339737 INFO: [APUAPC] D12_APC_2: 0x3fffff
9663 17:58:29.343140 INFO: [APUAPC] D12_APC_3: 0x0
9664 17:58:29.345720 INFO: [APUAPC] D13_APC_0: 0xffffffff
9665 17:58:29.349143 INFO: [APUAPC] D13_APC_1: 0xffffffff
9666 17:58:29.352376 INFO: [APUAPC] D13_APC_2: 0x3fffff
9667 17:58:29.355692 INFO: [APUAPC] D13_APC_3: 0x0
9668 17:58:29.359450 INFO: [APUAPC] D14_APC_0: 0xffffffff
9669 17:58:29.362591 INFO: [APUAPC] D14_APC_1: 0xffffffff
9670 17:58:29.365775 INFO: [APUAPC] D14_APC_2: 0x3fffff
9671 17:58:29.368934 INFO: [APUAPC] D14_APC_3: 0x0
9672 17:58:29.372616 INFO: [APUAPC] D15_APC_0: 0xffffffff
9673 17:58:29.375790 INFO: [APUAPC] D15_APC_1: 0xffffffff
9674 17:58:29.378942 INFO: [APUAPC] D15_APC_2: 0x3fffff
9675 17:58:29.382102 INFO: [APUAPC] D15_APC_3: 0x0
9676 17:58:29.385737 INFO: [APUAPC] APC_CON: 0x4
9677 17:58:29.389075 INFO: [NOCDAPC] D0_APC_0: 0x0
9678 17:58:29.392132 INFO: [NOCDAPC] D0_APC_1: 0x0
9679 17:58:29.395662 INFO: [NOCDAPC] D1_APC_0: 0x0
9680 17:58:29.395957 INFO: [NOCDAPC] D1_APC_1: 0xfff
9681 17:58:29.398853 INFO: [NOCDAPC] D2_APC_0: 0x0
9682 17:58:29.401958 INFO: [NOCDAPC] D2_APC_1: 0xfff
9683 17:58:29.405770 INFO: [NOCDAPC] D3_APC_0: 0x0
9684 17:58:29.408957 INFO: [NOCDAPC] D3_APC_1: 0xfff
9685 17:58:29.412116 INFO: [NOCDAPC] D4_APC_0: 0x0
9686 17:58:29.415780 INFO: [NOCDAPC] D4_APC_1: 0xfff
9687 17:58:29.419125 INFO: [NOCDAPC] D5_APC_0: 0x0
9688 17:58:29.422277 INFO: [NOCDAPC] D5_APC_1: 0xfff
9689 17:58:29.425843 INFO: [NOCDAPC] D6_APC_0: 0x0
9690 17:58:29.428675 INFO: [NOCDAPC] D6_APC_1: 0xfff
9691 17:58:29.429176 INFO: [NOCDAPC] D7_APC_0: 0x0
9692 17:58:29.431927 INFO: [NOCDAPC] D7_APC_1: 0xfff
9693 17:58:29.435759 INFO: [NOCDAPC] D8_APC_0: 0x0
9694 17:58:29.438911 INFO: [NOCDAPC] D8_APC_1: 0xfff
9695 17:58:29.442180 INFO: [NOCDAPC] D9_APC_0: 0x0
9696 17:58:29.445088 INFO: [NOCDAPC] D9_APC_1: 0xfff
9697 17:58:29.448917 INFO: [NOCDAPC] D10_APC_0: 0x0
9698 17:58:29.452040 INFO: [NOCDAPC] D10_APC_1: 0xfff
9699 17:58:29.455103 INFO: [NOCDAPC] D11_APC_0: 0x0
9700 17:58:29.458786 INFO: [NOCDAPC] D11_APC_1: 0xfff
9701 17:58:29.461762 INFO: [NOCDAPC] D12_APC_0: 0x0
9702 17:58:29.465373 INFO: [NOCDAPC] D12_APC_1: 0xfff
9703 17:58:29.468226 INFO: [NOCDAPC] D13_APC_0: 0x0
9704 17:58:29.471678 INFO: [NOCDAPC] D13_APC_1: 0xfff
9705 17:58:29.472211 INFO: [NOCDAPC] D14_APC_0: 0x0
9706 17:58:29.475048 INFO: [NOCDAPC] D14_APC_1: 0xfff
9707 17:58:29.478012 INFO: [NOCDAPC] D15_APC_0: 0x0
9708 17:58:29.481793 INFO: [NOCDAPC] D15_APC_1: 0xfff
9709 17:58:29.485132 INFO: [NOCDAPC] APC_CON: 0x4
9710 17:58:29.488391 INFO: [APUAPC] set_apusys_apc done
9711 17:58:29.491453 INFO: [DEVAPC] devapc_init done
9712 17:58:29.494971 INFO: GICv3 without legacy support detected.
9713 17:58:29.501470 INFO: ARM GICv3 driver initialized in EL3
9714 17:58:29.504741 INFO: Maximum SPI INTID supported: 639
9715 17:58:29.507885 INFO: BL31: Initializing runtime services
9716 17:58:29.514792 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9717 17:58:29.515208 INFO: SPM: enable CPC mode
9718 17:58:29.521152 INFO: mcdi ready for mcusys-off-idle and system suspend
9719 17:58:29.524299 INFO: BL31: Preparing for EL3 exit to normal world
9720 17:58:29.531146 INFO: Entry point address = 0x80000000
9721 17:58:29.531361 INFO: SPSR = 0x8
9722 17:58:29.537177
9723 17:58:29.537321
9724 17:58:29.537432
9725 17:58:29.540939 Starting depthcharge on Spherion...
9726 17:58:29.541062
9727 17:58:29.541159 Wipe memory regions:
9728 17:58:29.541266
9729 17:58:29.542079 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9730 17:58:29.542247 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9731 17:58:29.542367 Setting prompt string to ['asurada:']
9732 17:58:29.542482 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9733 17:58:29.543976 [0x00000040000000, 0x00000054600000)
9734 17:58:29.666600
9735 17:58:29.667086 [0x00000054660000, 0x00000080000000)
9736 17:58:29.926865
9737 17:58:29.927513 [0x000000821a7280, 0x000000ffe64000)
9738 17:58:30.671326
9739 17:58:30.671644 [0x00000100000000, 0x00000140000000)
9740 17:58:31.052462
9741 17:58:31.055507 Initializing XHCI USB controller at 0x11200000.
9742 17:58:32.093591
9743 17:58:32.096494 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9744 17:58:32.096908
9745 17:58:32.097230
9746 17:58:32.097528
9747 17:58:32.098319 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9749 17:58:32.199587 asurada: tftpboot 192.168.201.1 13522576/tftp-deploy-b23ke98q/kernel/image.itb 13522576/tftp-deploy-b23ke98q/kernel/cmdline
9750 17:58:32.200330 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9751 17:58:32.200787 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9752 17:58:32.204902 tftpboot 192.168.201.1 13522576/tftp-deploy-b23ke98q/kernel/image.itp-deploy-b23ke98q/kernel/cmdline
9753 17:58:32.205324
9754 17:58:32.205647 Waiting for link
9755 17:58:32.365740
9756 17:58:32.366356 R8152: Initializing
9757 17:58:32.366695
9758 17:58:32.369093 Version 9 (ocp_data = 6010)
9759 17:58:32.369572
9760 17:58:32.372362 R8152: Done initializing
9761 17:58:32.372771
9762 17:58:32.373139 Adding net device
9763 17:58:34.381071
9764 17:58:34.381546 done.
9765 17:58:34.381880
9766 17:58:34.382244 MAC: 00:e0:4c:68:03:bd
9767 17:58:34.382555
9768 17:58:34.384514 Sending DHCP discover... done.
9769 17:58:34.384965
9770 17:58:34.387534 Waiting for reply... done.
9771 17:58:34.387952
9772 17:58:34.390508 Sending DHCP request... done.
9773 17:58:34.390921
9774 17:58:34.394671 Waiting for reply... done.
9775 17:58:34.395086
9776 17:58:34.395494 My ip is 192.168.201.16
9777 17:58:34.395888
9778 17:58:34.398285 The DHCP server ip is 192.168.201.1
9779 17:58:34.398696
9780 17:58:34.404667 TFTP server IP predefined by user: 192.168.201.1
9781 17:58:34.405083
9782 17:58:34.411333 Bootfile predefined by user: 13522576/tftp-deploy-b23ke98q/kernel/image.itb
9783 17:58:34.411748
9784 17:58:34.412069 Sending tftp read request... done.
9785 17:58:34.414728
9786 17:58:34.421028 Waiting for the transfer...
9787 17:58:34.421545
9788 17:58:34.692883 00000000 ################################################################
9789 17:58:34.693021
9790 17:58:34.947235 00080000 ################################################################
9791 17:58:34.947423
9792 17:58:35.219083 00100000 ################################################################
9793 17:58:35.219257
9794 17:58:35.495756 00180000 ################################################################
9795 17:58:35.495950
9796 17:58:35.772701 00200000 ################################################################
9797 17:58:35.772874
9798 17:58:36.034451 00280000 ################################################################
9799 17:58:36.034585
9800 17:58:36.288899 00300000 ################################################################
9801 17:58:36.289061
9802 17:58:36.542170 00380000 ################################################################
9803 17:58:36.542323
9804 17:58:36.794839 00400000 ################################################################
9805 17:58:36.794988
9806 17:58:37.048221 00480000 ################################################################
9807 17:58:37.048374
9808 17:58:37.301676 00500000 ################################################################
9809 17:58:37.301828
9810 17:58:37.560051 00580000 ################################################################
9811 17:58:37.560202
9812 17:58:37.830769 00600000 ################################################################
9813 17:58:37.830923
9814 17:58:38.111705 00680000 ################################################################
9815 17:58:38.111877
9816 17:58:38.390049 00700000 ################################################################
9817 17:58:38.390200
9818 17:58:38.666632 00780000 ################################################################
9819 17:58:38.666797
9820 17:58:38.954663 00800000 ################################################################
9821 17:58:38.954841
9822 17:58:39.215868 00880000 ################################################################
9823 17:58:39.216128
9824 17:58:39.484706 00900000 ################################################################
9825 17:58:39.484861
9826 17:58:39.750020 00980000 ################################################################
9827 17:58:39.750169
9828 17:58:40.018004 00a00000 ################################################################
9829 17:58:40.018195
9830 17:58:40.265490 00a80000 ################################################################
9831 17:58:40.265665
9832 17:58:40.516309 00b00000 ################################################################
9833 17:58:40.516458
9834 17:58:40.769272 00b80000 ################################################################
9835 17:58:40.769418
9836 17:58:41.052314 00c00000 ################################################################
9837 17:58:41.052519
9838 17:58:41.329789 00c80000 ################################################################
9839 17:58:41.329939
9840 17:58:41.596724 00d00000 ################################################################
9841 17:58:41.596871
9842 17:58:41.850791 00d80000 ################################################################
9843 17:58:41.850949
9844 17:58:42.124470 00e00000 ################################################################
9845 17:58:42.124627
9846 17:58:42.413710 00e80000 ################################################################
9847 17:58:42.413858
9848 17:58:42.695994 00f00000 ################################################################
9849 17:58:42.696172
9850 17:58:42.949069 00f80000 ################################################################
9851 17:58:42.949221
9852 17:58:43.221365 01000000 ################################################################
9853 17:58:43.221515
9854 17:58:43.474035 01080000 ################################################################
9855 17:58:43.474195
9856 17:58:43.731861 01100000 ################################################################
9857 17:58:43.732010
9858 17:58:43.985057 01180000 ################################################################
9859 17:58:43.985205
9860 17:58:44.249869 01200000 ################################################################
9861 17:58:44.250017
9862 17:58:44.523530 01280000 ################################################################
9863 17:58:44.523705
9864 17:58:44.791540 01300000 ################################################################
9865 17:58:44.791682
9866 17:58:45.072422 01380000 ################################################################
9867 17:58:45.072596
9868 17:58:45.413900 01400000 ################################################################
9869 17:58:45.414070
9870 17:58:45.694799 01480000 ################################################################
9871 17:58:45.694949
9872 17:58:45.978006 01500000 ################################################################
9873 17:58:45.978180
9874 17:58:46.235189 01580000 ################################################################
9875 17:58:46.235345
9876 17:58:46.481998 01600000 ################################################################
9877 17:58:46.482148
9878 17:58:46.742668 01680000 ################################################################
9879 17:58:46.742800
9880 17:58:47.015560 01700000 ################################################################
9881 17:58:47.015693
9882 17:58:47.286255 01780000 ################################################################
9883 17:58:47.286400
9884 17:58:47.564625 01800000 ################################################################
9885 17:58:47.564754
9886 17:58:47.900088 01880000 ################################################################
9887 17:58:47.900233
9888 17:58:48.213774 01900000 ################################################################
9889 17:58:48.214018
9890 17:58:48.483606 01980000 ################################################################
9891 17:58:48.483777
9892 17:58:48.740418 01a00000 ################################################################
9893 17:58:48.740580
9894 17:58:48.984365 01a80000 ################################################################
9895 17:58:48.984552
9896 17:58:49.252489 01b00000 ################################################################
9897 17:58:49.252624
9898 17:58:49.533881 01b80000 ################################################################
9899 17:58:49.534016
9900 17:58:49.813504 01c00000 ################################################################
9901 17:58:49.813640
9902 17:58:50.063639 01c80000 ################################################################
9903 17:58:50.063799
9904 17:58:50.316523 01d00000 ################################################################
9905 17:58:50.316663
9906 17:58:50.573431 01d80000 ################################################################
9907 17:58:50.573568
9908 17:58:50.847023 01e00000 ################################################################
9909 17:58:50.847161
9910 17:58:51.143777 01e80000 ################################################################
9911 17:58:51.143911
9912 17:58:51.415844 01f00000 ################################################################
9913 17:58:51.415977
9914 17:58:51.677905 01f80000 ################################################################
9915 17:58:51.678062
9916 17:58:51.952246 02000000 ################################################################
9917 17:58:51.952380
9918 17:58:52.203172 02080000 ################################################################
9919 17:58:52.203312
9920 17:58:52.453092 02100000 ################################################################
9921 17:58:52.453242
9922 17:58:52.717653 02180000 ################################################################
9923 17:58:52.717818
9924 17:58:52.974476 02200000 ################################################################
9925 17:58:52.974618
9926 17:58:53.266638 02280000 ################################################################
9927 17:58:53.266788
9928 17:58:53.536337 02300000 ################################################################
9929 17:58:53.536478
9930 17:58:53.585145 02380000 ############# done.
9931 17:58:53.585285
9932 17:58:53.588826 The bootfile was 37323050 bytes long.
9933 17:58:53.588910
9934 17:58:53.591911 Sending tftp read request... done.
9935 17:58:53.591992
9936 17:58:53.592055 Waiting for the transfer...
9937 17:58:53.592114
9938 17:58:53.594971 00000000 # done.
9939 17:58:53.595053
9940 17:58:53.601455 Command line loaded dynamically from TFTP file: 13522576/tftp-deploy-b23ke98q/kernel/cmdline
9941 17:58:53.601537
9942 17:58:53.614740 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
9943 17:58:53.614829
9944 17:58:53.618299 Loading FIT.
9945 17:58:53.618380
9946 17:58:53.621873 Image ramdisk-1 has 23608191 bytes.
9947 17:58:53.621954
9948 17:58:53.625019 Image fdt-1 has 65280 bytes.
9949 17:58:53.625100
9950 17:58:53.628165 Image kernel-1 has 13647546 bytes.
9951 17:58:53.628245
9952 17:58:53.634225 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
9953 17:58:53.634307
9954 17:58:53.654649 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
9955 17:58:53.654741
9956 17:58:53.657678 Choosing best match conf-1 for compat google,spherion-rev3.
9957 17:58:53.662714
9958 17:58:53.667010 Connected to device vid:did:rid of 1ae0:0028:00
9959 17:58:53.674133
9960 17:58:53.677098 tpm_get_response: command 0x17b, return code 0x0
9961 17:58:53.677222
9962 17:58:53.680678 ec_init: CrosEC protocol v3 supported (256, 248)
9963 17:58:53.684464
9964 17:58:53.688246 tpm_cleanup: add release locality here.
9965 17:58:53.688350
9966 17:58:53.688443 Shutting down all USB controllers.
9967 17:58:53.691209
9968 17:58:53.691309 Removing current net device
9969 17:58:53.691400
9970 17:58:53.697905 Exiting depthcharge with code 4 at timestamp: 52378579
9971 17:58:53.698020
9972 17:58:53.701014 LZMA decompressing kernel-1 to 0x821a6718
9973 17:58:53.701114
9974 17:58:53.704641 LZMA decompressing kernel-1 to 0x40000000
9975 17:58:55.408215
9976 17:58:55.408360 jumping to kernel
9977 17:58:55.408841 end: 2.2.4 bootloader-commands (duration 00:00:26) [common]
9978 17:58:55.408938 start: 2.2.5 auto-login-action (timeout 00:04:00) [common]
9979 17:58:55.409013 Setting prompt string to ['Linux version [0-9]']
9980 17:58:55.409084 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9981 17:58:55.409152 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
9982 17:58:55.459373
9983 17:58:55.462331 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
9984 17:58:55.466267 start: 2.2.5.1 login-action (timeout 00:04:00) [common]
9985 17:58:55.466361 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
9986 17:58:55.466432 Setting prompt string to []
9987 17:58:55.466514 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
9988 17:58:55.466591 Using line separator: #'\n'#
9989 17:58:55.466652 No login prompt set.
9990 17:58:55.466709 Parsing kernel messages
9991 17:58:55.466763 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
9992 17:58:55.466862 [login-action] Waiting for messages, (timeout 00:04:00)
9993 17:58:55.466925 Waiting using forced prompt support (timeout 00:02:00)
9994 17:58:55.485432 [ 0.000000] Linux version 6.9.0-rc5 (KernelCI@build-j176989-arm64-gcc-10-defconfig-arm64-chromebook-6w5bs) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Apr 25 17:44:41 UTC 2024
9995 17:58:55.488977 [ 0.000000] KASLR enabled
9996 17:58:55.491955 [ 0.000000] random: crng init done
9997 17:58:55.495020 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
9998 17:58:55.498753 [ 0.000000] efi: UEFI not found.
9999 17:58:55.508389 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10000 17:58:55.515072 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10001 17:58:55.524909 [ 0.000000] OF: reserved mem: 0x0000000050000000..0x00000000528fffff (41984 KiB) nomap non-reusable scp@50000000
10002 17:58:55.534608 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10003 17:58:55.544427 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10004 17:58:55.554400 [ 0.000000] OF: reserved mem: 0x00000000c0000000..0x00000000c3ffffff (65536 KiB) map non-reusable wifi@c0000000
10005 17:58:55.564311 [ 0.000000] OF: reserved mem: 0x00000000ffe66000..0x00000000fff65fff (1024 KiB) map non-reusable ramoops
10006 17:58:55.571147 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10007 17:58:55.577134 [ 0.000000] printk: legacy bootconsole [mtk8250] enabled
10008 17:58:55.584887 [ 0.000000] NUMA: No NUMA configuration found
10009 17:58:55.591504 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10010 17:58:55.597890 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7be9c0-0x13f7c0fff]
10011 17:58:55.601721 [ 0.000000] Zone ranges:
10012 17:58:55.604765 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10013 17:58:55.607979 [ 0.000000] DMA32 empty
10014 17:58:55.614435 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10015 17:58:55.617387 [ 0.000000] Movable zone start for each node
10016 17:58:55.624276 [ 0.000000] Early memory node ranges
10017 17:58:55.627538 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10018 17:58:55.633923 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10019 17:58:55.640647 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10020 17:58:55.647387 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10021 17:58:55.653571 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10022 17:58:55.660190 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10023 17:58:55.685765 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10024 17:58:55.697603 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10025 17:58:55.704421 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000 on node -1
10026 17:58:55.711300 [ 0.000000] psci: probing for conduit method from DT.
10027 17:58:55.714243 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10028 17:58:55.721006 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10029 17:58:55.724222 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10030 17:58:55.727234 [ 0.000000] psci: SMC Calling Convention v1.2
10031 17:58:55.734498 [ 0.000000] percpu: Embedded 24 pages/cpu s59112 r8192 d31000 u98304
10032 17:58:55.740909 [ 0.000000] Detected VIPT I-cache on CPU0
10033 17:58:55.747883 [ 0.000000] CPU features: detected: GIC system register CPU interface
10034 17:58:55.750887 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10035 17:58:55.757794 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10036 17:58:55.764460 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10037 17:58:55.774194 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10038 17:58:55.777542 [ 0.000000] alternatives: applying boot alternatives
10039 17:58:55.794035 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10040 17:58:55.803680 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10041 17:58:55.813639 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10042 17:58:55.823318 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10043 17:58:55.826892 <6>[ 0.000000] Fallback order for Node 0: 0
10044 17:58:55.833626 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10045 17:58:55.836489 <6>[ 0.000000] Policy zone: Normal
10046 17:58:55.843285 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10047 17:58:55.846731 <6>[ 0.000000] software IO TLB: area num 8.
10048 17:58:55.903932 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10049 17:58:55.981808 <6>[ 0.000000] Memory: 3819892K/4191232K available (18624K kernel code, 5120K rwdata, 24180K rodata, 10816K init, 755K bss, 338572K reserved, 32768K cma-reserved)
10050 17:58:55.988666 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10051 17:58:55.995333 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10052 17:58:55.998679 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10053 17:58:56.004964 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=8.
10054 17:58:56.011877 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10055 17:58:56.018072 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10056 17:58:56.024792 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10057 17:58:56.031451 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10058 17:58:56.038273 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
10059 17:58:56.047797 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
10060 17:58:56.051332 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10061 17:58:56.058719 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10062 17:58:56.062206 <6>[ 0.000000] GICv3: 608 SPIs implemented
10063 17:58:56.068702 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10064 17:58:56.072333 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10065 17:58:56.075653 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10066 17:58:56.085499 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10067 17:58:56.095482 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10068 17:58:56.108482 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10069 17:58:56.115030 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10070 17:58:56.125146 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10071 17:58:56.138445 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10072 17:58:56.144565 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10073 17:58:56.152234 <6>[ 0.009677] Console: colour dummy device 80x25
10074 17:58:56.162501 <6>[ 0.014405] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10075 17:58:56.165278 <6>[ 0.024849] pid_max: default: 32768 minimum: 301
10076 17:58:56.171912 <6>[ 0.029773] LSM: initializing lsm=capability
10077 17:58:56.178890 <6>[ 0.034345] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10078 17:58:56.188872 <6>[ 0.041954] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10079 17:58:56.195079 <6>[ 0.050701] spectre-v4 mitigation disabled by command-line option
10080 17:58:56.201867 <6>[ 0.057857] rcu: Hierarchical SRCU implementation.
10081 17:58:56.205502 <6>[ 0.062905] rcu: Max phase no-delay instances is 1000.
10082 17:58:56.213258 <6>[ 0.070765] EFI services will not be available.
10083 17:58:56.216459 <6>[ 0.075742] smp: Bringing up secondary CPUs ...
10084 17:58:56.225808 <6>[ 0.080811] Detected VIPT I-cache on CPU1
10085 17:58:56.232544 <6>[ 0.080869] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10086 17:58:56.238949 <6>[ 0.080902] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10087 17:58:56.242214 <6>[ 0.081283] Detected VIPT I-cache on CPU2
10088 17:58:56.252030 <6>[ 0.081327] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10089 17:58:56.258562 <6>[ 0.081347] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10090 17:58:56.262301 <6>[ 0.081658] Detected VIPT I-cache on CPU3
10091 17:58:56.268399 <6>[ 0.081697] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10092 17:58:56.275032 <6>[ 0.081713] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10093 17:58:56.281950 <6>[ 0.082056] CPU features: detected: Spectre-v4
10094 17:58:56.285200 <6>[ 0.082062] CPU features: detected: Spectre-BHB
10095 17:58:56.288115 <6>[ 0.082068] Detected PIPT I-cache on CPU4
10096 17:58:56.295042 <6>[ 0.082111] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10097 17:58:56.301795 <6>[ 0.082130] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10098 17:58:56.307932 <6>[ 0.082457] Detected PIPT I-cache on CPU5
10099 17:58:56.314673 <6>[ 0.082502] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10100 17:58:56.321306 <6>[ 0.082521] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10101 17:58:56.324969 <6>[ 0.082837] Detected PIPT I-cache on CPU6
10102 17:58:56.334406 <6>[ 0.082882] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10103 17:58:56.341438 <6>[ 0.082900] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10104 17:58:56.344802 <6>[ 0.083228] Detected PIPT I-cache on CPU7
10105 17:58:56.351316 <6>[ 0.083275] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10106 17:58:56.357510 <6>[ 0.083293] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10107 17:58:56.361175 <6>[ 0.083376] smp: Brought up 1 node, 8 CPUs
10108 17:58:56.367350 <6>[ 0.224688] SMP: Total of 8 processors activated.
10109 17:58:56.371080 <6>[ 0.229617] CPU: All CPU(s) started at EL2
10110 17:58:56.377654 <6>[ 0.233946] CPU features: detected: 32-bit EL0 Support
10111 17:58:56.384208 <6>[ 0.239299] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10112 17:58:56.390283 <6>[ 0.248103] CPU features: detected: Common not Private translations
10113 17:58:56.397094 <6>[ 0.254574] CPU features: detected: CRC32 instructions
10114 17:58:56.403726 <6>[ 0.259933] CPU features: detected: RCpc load-acquire (LDAPR)
10115 17:58:56.410484 <6>[ 0.265924] CPU features: detected: LSE atomic instructions
10116 17:58:56.413549 <6>[ 0.271704] CPU features: detected: Privileged Access Never
10117 17:58:56.420216 <6>[ 0.277484] CPU features: detected: RAS Extension Support
10118 17:58:56.426796 <6>[ 0.283092] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10119 17:58:56.433109 <6>[ 0.290289] spectre-bhb mitigation disabled by command line option
10120 17:58:56.439964 <6>[ 0.296701] alternatives: applying system-wide alternatives
10121 17:58:56.451294 <6>[ 0.305462] CPU features: detected: Hardware dirty bit management on CPU4-7
10122 17:58:56.454250 <6>[ 0.313983] devtmpfs: initialized
10123 17:58:56.473051 <6>[ 0.324102] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10124 17:58:56.479503 <6>[ 0.334061] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10125 17:58:56.486260 <6>[ 0.342272] pinctrl core: initialized pinctrl subsystem
10126 17:58:56.489885 <6>[ 0.349299] DMI not present or invalid.
10127 17:58:56.497701 <6>[ 0.355321] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10128 17:58:56.507639 <6>[ 0.362143] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10129 17:58:56.514743 <6>[ 0.369511] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10130 17:58:56.524415 <6>[ 0.377596] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10131 17:58:56.528102 <6>[ 0.385748] audit: initializing netlink subsys (disabled)
10132 17:58:56.537690 <5>[ 0.391451] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10133 17:58:56.543892 <6>[ 0.392364] thermal_sys: Registered thermal governor 'step_wise'
10134 17:58:56.550706 <6>[ 0.399422] thermal_sys: Registered thermal governor 'power_allocator'
10135 17:58:56.554301 <6>[ 0.405697] cpuidle: using governor menu
10136 17:58:56.560601 <6>[ 0.416674] NET: Registered PF_QIPCRTR protocol family
10137 17:58:56.567261 <6>[ 0.422162] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10138 17:58:56.573990 <6>[ 0.429279] ASID allocator initialised with 32768 entries
10139 17:58:56.576960 <6>[ 0.436282] Serial: AMBA PL011 UART driver
10140 17:58:56.607201 <6>[ 0.461490] platform 14010000.dsi: Fixed dependency cycle(s) with /soc/i2c@11cb0000/anx7625@58
10141 17:58:56.624852 <6>[ 0.478999] Modules: 2G module region forced by RANDOMIZE_MODULE_REGION_FULL
10142 17:58:56.628012 <6>[ 0.486273] Modules: 0 pages in range for non-PLT usage
10143 17:58:56.634719 <6>[ 0.486275] Modules: 509360 pages in range for PLT usage
10144 17:58:56.641501 <6>[ 0.492244] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10145 17:58:56.647762 <6>[ 0.504794] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10146 17:58:56.654512 <6>[ 0.511282] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10147 17:58:56.661294 <6>[ 0.518287] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10148 17:58:56.667699 <6>[ 0.524772] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10149 17:58:56.673999 <6>[ 0.531773] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10150 17:58:56.684264 <6>[ 0.538259] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10151 17:58:56.690542 <6>[ 0.545265] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10152 17:58:56.693895 <6>[ 0.552032] Demotion targets for Node 0: null
10153 17:58:56.700531 <6>[ 0.557662] ACPI: Interpreter disabled.
10154 17:58:56.707154 <6>[ 0.564155] iommu: Default domain type: Translated
10155 17:58:56.713811 <6>[ 0.569183] iommu: DMA domain TLB invalidation policy: strict mode
10156 17:58:56.716895 <5>[ 0.575966] SCSI subsystem initialized
10157 17:58:56.723496 <6>[ 0.580150] usbcore: registered new interface driver usbfs
10158 17:58:56.730167 <6>[ 0.585881] usbcore: registered new interface driver hub
10159 17:58:56.733836 <6>[ 0.591432] usbcore: registered new device driver usb
10160 17:58:56.739961 <6>[ 0.597694] pps_core: LinuxPPS API ver. 1 registered
10161 17:58:56.750357 <6>[ 0.602887] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10162 17:58:56.753460 <6>[ 0.612226] PTP clock support registered
10163 17:58:56.756510 <6>[ 0.616497] EDAC MC: Ver: 3.0.0
10164 17:58:56.763183 <6>[ 0.620344] scmi_core: SCMI protocol bus registered
10165 17:58:56.766334 <6>[ 0.626836] FPGA manager framework
10166 17:58:56.773429 <6>[ 0.630531] Advanced Linux Sound Architecture Driver Initialized.
10167 17:58:56.776820 <6>[ 0.637469] vgaarb: loaded
10168 17:58:56.783502 <6>[ 0.640759] clocksource: Switched to clocksource arch_sys_counter
10169 17:58:56.789725 <5>[ 0.647245] VFS: Disk quotas dquot_6.6.0
10170 17:58:56.796285 <6>[ 0.651428] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10171 17:58:56.799759 <6>[ 0.658624] pnp: PnP ACPI: disabled
10172 17:58:56.808353 <6>[ 0.665897] NET: Registered PF_INET protocol family
10173 17:58:56.814976 <6>[ 0.671275] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10174 17:58:56.827174 <6>[ 0.681298] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10175 17:58:56.836908 <6>[ 0.690072] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10176 17:58:56.843688 <6>[ 0.698040] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10177 17:58:56.850356 <6>[ 0.706286] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10178 17:58:56.860998 <6>[ 0.714921] TCP: Hash tables configured (established 32768 bind 32768)
10179 17:58:56.867148 <6>[ 0.721766] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10180 17:58:56.873949 <6>[ 0.728715] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10181 17:58:56.880503 <6>[ 0.736149] NET: Registered PF_UNIX/PF_LOCAL protocol family
10182 17:58:56.886901 <6>[ 0.742229] RPC: Registered named UNIX socket transport module.
10183 17:58:56.890504 <6>[ 0.748377] RPC: Registered udp transport module.
10184 17:58:56.897274 <6>[ 0.753312] RPC: Registered tcp transport module.
10185 17:58:56.900272 <6>[ 0.758245] RPC: Registered tcp-with-tls transport module.
10186 17:58:56.907010 <6>[ 0.763955] RPC: Registered tcp NFSv4.1 backchannel transport module.
10187 17:58:56.913194 <6>[ 0.770619] PCI: CLS 0 bytes, default 64
10188 17:58:56.916663 <6>[ 0.774977] Unpacking initramfs...
10189 17:58:56.923534 <6>[ 0.781309] kvm [1]: nv: 477 coarse grained trap handlers
10190 17:58:56.930266 <6>[ 0.787138] kvm [1]: IPA Size Limit: 40 bits
10191 17:58:56.933521 <6>[ 0.791665] kvm [1]: GICv3: no GICV resource entry
10192 17:58:56.940396 <6>[ 0.796687] kvm [1]: disabling GICv2 emulation
10193 17:58:56.943430 <6>[ 0.801375] kvm [1]: GIC system register CPU interface enabled
10194 17:58:56.950259 <6>[ 0.807449] kvm [1]: vgic interrupt IRQ18
10195 17:58:56.953312 <6>[ 0.811711] kvm [1]: VHE mode initialized successfully
10196 17:58:56.960628 <5>[ 0.818101] Initialise system trusted keyrings
10197 17:58:56.966958 <6>[ 0.822922] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10198 17:58:56.973832 <6>[ 0.829804] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10199 17:58:56.980669 <5>[ 0.836025] NFS: Registering the id_resolver key type
10200 17:58:56.983699 <5>[ 0.841324] Key type id_resolver registered
10201 17:58:56.986800 <5>[ 0.845739] Key type id_legacy registered
10202 17:58:56.993766 <6>[ 0.849988] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10203 17:58:57.003356 <6>[ 0.856911] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10204 17:58:57.006976 <6>[ 0.864593] 9p: Installing v9fs 9p2000 file system support
10205 17:58:57.046786 <5>[ 0.904379] Key type asymmetric registered
10206 17:58:57.049857 <5>[ 0.908711] Asymmetric key parser 'x509' registered
10207 17:58:57.060083 <6>[ 0.913858] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10208 17:58:57.063123 <6>[ 0.921473] io scheduler mq-deadline registered
10209 17:58:57.066838 <6>[ 0.926234] io scheduler kyber registered
10210 17:58:57.073057 <6>[ 0.930500] io scheduler bfq registered
10211 17:58:57.100522 <3>[ 0.958130] cannot find "mediatek,mt8192-fhctl"
10212 17:58:57.135430 <6>[ 0.989459] mtk-socinfo mtk-socinfo.0.auto: MediaTek Kompanio 828 (MT8192T) SoC detected.
10213 17:58:57.149832 <6>[ 1.007706] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10214 17:58:57.158444 <6>[ 1.016217] printk: legacy console [ttyS0] disabled
10215 17:58:57.187394 <6>[ 1.041576] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 252, base_baud = 1625000) is a ST16650V2
10216 17:58:57.193597 <6>[ 1.051049] printk: legacy console [ttyS0] enabled
10217 17:58:57.197213 <6>[ 1.051049] printk: legacy console [ttyS0] enabled
10218 17:58:57.204023 <6>[ 1.061180] printk: legacy bootconsole [mtk8250] disabled
10219 17:58:57.210651 <6>[ 1.061180] printk: legacy bootconsole [mtk8250] disabled
10220 17:58:57.220975 <6>[ 1.078458] msm_serial: driver initialized
10221 17:58:57.224230 <6>[ 1.083195] SuperH (H)SCI(F) driver initialized
10222 17:58:57.230910 <6>[ 1.088201] STM32 USART driver initialized
10223 17:58:57.240388 <4>[ 1.094523] SPI driver tpm_tis_spi has no spi_device_id for atmel,attpm20p
10224 17:58:57.251470 <6>[ 1.109121] loop: module loaded
10225 17:58:57.258173 <4>[ 1.115428] mtk-pmic-keys: Failed to locate of_node [id: -1]
10226 17:58:57.264776 <6>[ 1.116329] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10227 17:58:57.267759 <6>[ 1.122497] megasas: 07.727.03.00-rc1
10228 17:58:57.275637 <6>[ 1.133166] vsram_others: Bringing 850000uV into 800000-800000uV
10229 17:58:57.297938 <6>[ 1.152155] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10230 17:58:57.310595 <6>[ 1.168254] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10231 17:58:57.380403 <6>[ 1.230610] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10232 17:58:57.948607 <6>[ 1.806303] Freeing initrd memory: 23048K
10233 17:58:57.966408 <6>[ 1.823837] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10234 17:58:57.976694 <6>[ 1.834398] tun: Universal TUN/TAP device driver, 1.6
10235 17:58:57.980264 <6>[ 1.840664] thunder_xcv, ver 1.0
10236 17:58:57.983544 <6>[ 1.844181] thunder_bgx, ver 1.0
10237 17:58:57.986927 <6>[ 1.847678] nicpf, ver 1.0
10238 17:58:57.997190 <6>[ 1.851796] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10239 17:58:58.000898 <6>[ 1.859273] hns3: Copyright (c) 2017 Huawei Corporation.
10240 17:58:58.007484 <6>[ 1.864852] hclge is initializing
10241 17:58:58.010455 <6>[ 1.868449] e1000: Intel(R) PRO/1000 Network Driver
10242 17:58:58.017235 <6>[ 1.873580] e1000: Copyright (c) 1999-2006 Intel Corporation.
10243 17:58:58.020507 <6>[ 1.879590] e1000e: Intel(R) PRO/1000 Network Driver
10244 17:58:58.027218 <6>[ 1.884806] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10245 17:58:58.033733 <6>[ 1.890986] igb: Intel(R) Gigabit Ethernet Network Driver
10246 17:58:58.040257 <6>[ 1.896636] igb: Copyright (c) 2007-2014 Intel Corporation.
10247 17:58:58.046956 <6>[ 1.902469] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10248 17:58:58.053556 <6>[ 1.909005] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10249 17:58:58.057126 <6>[ 1.915509] sky2: driver version 1.30
10250 17:58:58.063922 <6>[ 1.920909] VFIO - User Level meta-driver version: 0.3
10251 17:58:58.071732 <6>[ 1.929395] usbcore: registered new interface driver usb-storage
10252 17:58:58.078418 <6>[ 1.935899] usbcore: registered new device driver onboard-usb-hub
10253 17:58:58.087945 <6>[ 1.945612] mt6397-rtc mt6359-rtc: registered as rtc0
10254 17:58:58.098131 <6>[ 1.951105] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-25T17:58:57 UTC (1714067937)
10255 17:58:58.101028 <6>[ 1.960877] i2c_dev: i2c /dev entries driver
10256 17:58:58.112527 <6>[ 1.966527] platform 14010000.dsi: Fixed dependency cycle(s) with /soc/i2c@11cb0000/anx7625@58
10257 17:58:58.122339 <6>[ 1.975442] i2c 3-0058: Fixed dependency cycle(s) with /soc/i2c@11cb0000/anx7625@58/aux-bus/panel
10258 17:58:58.128780 <6>[ 1.984578] i2c 3-0058: Fixed dependency cycle(s) with /soc/dsi@14010000
10259 17:58:58.145406 <6>[ 2.000030] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10260 17:58:58.152155 <4>[ 2.009244] cpu cpu0: supply cpu not found, using dummy regulator
10261 17:58:58.158943 <4>[ 2.015669] cpu cpu1: supply cpu not found, using dummy regulator
10262 17:58:58.165745 <4>[ 2.022072] cpu cpu2: supply cpu not found, using dummy regulator
10263 17:58:58.172024 <4>[ 2.028479] cpu cpu3: supply cpu not found, using dummy regulator
10264 17:58:58.178906 <4>[ 2.034886] cpu cpu4: supply cpu not found, using dummy regulator
10265 17:58:58.185745 <4>[ 2.041290] cpu cpu5: supply cpu not found, using dummy regulator
10266 17:58:58.192800 <4>[ 2.047709] cpu cpu6: supply cpu not found, using dummy regulator
10267 17:58:58.199038 <4>[ 2.054106] cpu cpu7: supply cpu not found, using dummy regulator
10268 17:58:58.217035 <6>[ 2.074789] cpu cpu0: EM: created perf domain
10269 17:58:58.220846 <6>[ 2.079765] cpu cpu4: EM: created perf domain
10270 17:58:58.227866 <6>[ 2.085566] sdhci: Secure Digital Host Controller Interface driver
10271 17:58:58.234325 <6>[ 2.091997] sdhci: Copyright(c) Pierre Ossman
10272 17:58:58.241383 <6>[ 2.096992] Synopsys Designware Multimedia Card Interface Driver
10273 17:58:58.248024 <6>[ 2.103662] sdhci-pltfm: SDHCI platform and OF driver helper
10274 17:58:58.251645 <6>[ 2.103803] mmc0: CQHCI version 5.10
10275 17:58:58.257821 <6>[ 2.113865] ledtrig-cpu: registered to indicate activity on CPUs
10276 17:58:58.264532 <6>[ 2.120604] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10277 17:58:58.271163 <6>[ 2.127698] usbcore: registered new interface driver usbhid
10278 17:58:58.274230 <6>[ 2.133520] usbhid: USB HID core driver
10279 17:58:58.281188 <6>[ 2.137835] spi_master spi0: will run message pump with realtime priority
10280 17:58:58.292267 <6>[ 2.145827] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10281 17:58:58.299660 <6>[ 2.155565] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10282 17:58:58.314575 <6>[ 2.169011] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10283 17:58:58.328119 <6>[ 2.172253] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10284 17:58:58.334892 <6>[ 2.181049] NET: Registered PF_PACKET protocol family
10285 17:58:58.337867 <6>[ 2.196468] 9pnet: Installing 9P2000 support
10286 17:58:58.344674 <5>[ 2.201051] Key type dns_resolver registered
10287 17:58:58.351305 <4>[ 2.203692] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10288 17:58:58.361371 <6>[ 2.207968] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
10289 17:58:58.371003 <4>[ 2.214898] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10290 17:58:58.384381 <6>[ 2.233135] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10291 17:58:58.387457 <6>[ 2.233619] registered taskstats version 1
10292 17:58:58.394278 <6>[ 2.234605] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x14414
10293 17:58:58.403195 <6>[ 2.251997] cros-ec-spi spi0.0: Chrome EC device registered
10294 17:58:58.410459 <5>[ 2.257068] Loading compiled-in X.509 certificates
10295 17:58:58.410544 <6>[ 2.257199] mmc0: Command Queue Engine enabled
10296 17:58:58.417527 <6>[ 2.257216] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10297 17:58:58.420750 <6>[ 2.258043] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10298 17:58:58.427464 <6>[ 2.262067] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10299 17:58:58.430442 <6>[ 2.263117] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10300 17:58:58.437785 <6>[ 2.295729] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10301 17:58:58.444495 <6>[ 2.297529] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10302 17:58:58.451525 <6>[ 2.301831] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10303 17:58:58.457891 <6>[ 2.308205] xhci-mtk 11200000.usb: xHCI Host Controller
10304 17:58:58.464470 <6>[ 2.319104] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10305 17:58:58.474682 <6>[ 2.327070] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000200010
10306 17:58:58.480844 <6>[ 2.336504] xhci-mtk 11200000.usb: irq 270, io mem 0x11200000
10307 17:58:58.484774 <6>[ 2.342597] xhci-mtk 11200000.usb: xHCI Host Controller
10308 17:58:58.494331 <6>[ 2.348083] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10309 17:58:58.500996 <6>[ 2.355733] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10310 17:58:58.504496 <6>[ 2.363575] hub 1-0:1.0: USB hub found
10311 17:58:58.507372 <6>[ 2.367598] hub 1-0:1.0: 1 port detected
10312 17:58:58.517513 <6>[ 2.371902] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10313 17:58:58.520868 <6>[ 2.380699] hub 2-0:1.0: USB hub found
10314 17:58:58.527489 <6>[ 2.384732] hub 2-0:1.0: 1 port detected
10315 17:58:58.534354 <3>[ 2.390549] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10316 17:58:58.551374 <6>[ 2.409134] mtk-msdc 11f70000.mmc: Got CD GPIO
10317 17:58:58.557904 <4>[ 2.411075] rt5682 1-001a: Using default DAI clk names: rt5682-dai-wclk, rt5682-dai-bclk
10318 17:58:58.568350 <3>[ 2.422740] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10319 17:58:58.595430 <3>[ 2.449869] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10320 17:58:58.622871 <3>[ 2.477496] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10321 17:58:58.931025 <6>[ 2.785119] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10322 17:58:59.084561 <6>[ 2.942345] hub 1-1:1.0: USB hub found
10323 17:58:59.087695 <6>[ 2.946814] hub 1-1:1.0: 4 ports detected
10324 17:58:59.118431 <3>[ 2.973281] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10325 17:58:59.125520 <6>[ 2.983177] hub 1-1:1.0: USB hub found
10326 17:58:59.128971 <6>[ 2.987463] hub 1-1:1.0: 4 ports detected
10327 17:58:59.171543 <3>[ 3.025663] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10328 17:58:59.210613 <6>[ 3.065203] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10329 17:58:59.237425 <6>[ 3.095123] hub 2-1:1.0: USB hub found
10330 17:58:59.240536 <6>[ 3.099797] hub 2-1:1.0: 3 ports detected
10331 17:58:59.287218 <3>[ 3.141739] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10332 17:58:59.305470 <6>[ 3.163192] hub 2-1:1.0: USB hub found
10333 17:58:59.308433 <6>[ 3.167586] hub 2-1:1.0: 3 ports detected
10334 17:58:59.331032 <3>[ 3.185650] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10335 17:58:59.454354 <6>[ 3.308870] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10336 17:58:59.587560 <6>[ 3.445031] hub 1-1.4:1.0: USB hub found
10337 17:58:59.590575 <6>[ 3.449716] hub 1-1.4:1.0: 2 ports detected
10338 17:58:59.626860 <3>[ 3.481634] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10339 17:58:59.647800 <6>[ 3.505705] hub 1-1.4:1.0: USB hub found
10340 17:58:59.651486 <6>[ 3.510292] hub 1-1.4:1.0: 2 ports detected
10341 17:58:59.674992 <3>[ 3.529602] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10342 17:58:59.681671 <6>[ 3.537786] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10343 17:58:59.726911 <3>[ 3.581570] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10344 17:58:59.946346 <6>[ 3.801063] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10345 17:59:00.086690 <3>[ 3.941366] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10346 17:59:00.138664 <6>[ 3.992941] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10347 17:59:00.282796 <3>[ 4.137533] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10348 17:59:11.553931 <6>[ 15.413237] clk: Disabling unused clocks
10349 17:59:11.560787 <6>[ 15.418545] PM: genpd: Disabling unused power domains
10350 17:59:11.563918 <6>[ 15.423888] ALSA device list:
10351 17:59:11.567175 <6>[ 15.427135] No soundcards found.
10352 17:59:11.577380 <6>[ 15.436484] Freeing unused kernel memory: 10816K
10353 17:59:11.580421 <6>[ 15.441558] Run /init as init process
10354 17:59:11.605674 Starting syslogd: OK
10355 17:59:11.610063 Starting klogd: OK
10356 17:59:11.619201 Running sysctl: OK
10357 17:59:11.625805 Populating /dev using udev: <30>[ 15.486751] udevd[171]: starting version 3.2.9
10358 17:59:11.635980 <27>[ 15.494960] udevd[171]: specified user 'tss' unknown
10359 17:59:11.642217 <27>[ 15.500379] udevd[171]: specified group 'tss' unknown
10360 17:59:11.648849 <30>[ 15.506961] udevd[172]: starting eudev-3.2.9
10361 17:59:11.666661 <27>[ 15.526122] udevd[172]: specified user 'tss' unknown
10362 17:59:11.673579 <27>[ 15.531525] udevd[172]: specified group 'tss' unknown
10363 17:59:11.743375 <6>[ 15.602379] pstore: Using crash dump compression: deflate
10364 17:59:11.752032 <6>[ 15.611506] pstore: Registered ramoops as persistent store backend
10365 17:59:11.762456 <6>[ 15.621858] ramoops: using 0x100000@0xffe66000, ecc: 0
10366 17:59:11.845818 <6>[ 15.701585] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10367 17:59:11.863962 <3>[ 15.719847] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10368 17:59:11.870302 <6>[ 15.720310] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10369 17:59:11.877111 <6>[ 15.721034] remoteproc remoteproc0: scp is available
10370 17:59:11.880201 <6>[ 15.721168] remoteproc remoteproc0: powering up scp
10371 17:59:11.890458 <6>[ 15.721175] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10372 17:59:11.896736 <6>[ 15.721202] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10373 17:59:11.903431 <6>[ 15.759855] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10374 17:59:11.910228 <6>[ 15.760439] mc: Linux media interface: v0.10
10375 17:59:11.916599 <6>[ 15.768615] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10376 17:59:11.923355 <6>[ 15.782867] usbcore: registered new device driver r8152-cfgselector
10377 17:59:11.958325 <6>[ 15.814093] mediatek-mipi-tx 11e50000.dsi-phy: can't get nvmem_cell_get, ignore it
10378 17:59:11.965006 <6>[ 15.814706] sbs-battery 8-000b: sbs-battery: battery gas gauge device registered
10379 17:59:11.967845 <6>[ 15.816348] Bluetooth: Core ver 2.22
10380 17:59:11.975001 <6>[ 15.816411] NET: Registered PF_BLUETOOTH protocol family
10381 17:59:11.981247 <6>[ 15.816413] Bluetooth: HCI device and connection manager initialized
10382 17:59:11.987610 <6>[ 15.816430] Bluetooth: HCI socket layer initialized
10383 17:59:11.991179 <6>[ 15.816433] Bluetooth: L2CAP socket layer initialized
10384 17:59:11.997765 <6>[ 15.816707] Bluetooth: SCO socket layer initialized
10385 17:59:12.004591 <6>[ 15.826833] videodev: Linux video capture interface: v2.00
10386 17:59:12.011105 <6>[ 15.863822] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/ovl@14005000
10387 17:59:12.017894 <6>[ 15.867407] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10388 17:59:12.027732 <6>[ 15.876312] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/ovl@14006000
10389 17:59:12.037371 <6>[ 15.883609] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10390 17:59:12.043731 <6>[ 15.891706] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/rdma@14007000
10391 17:59:12.054287 <6>[ 15.891733] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/color@14009000
10392 17:59:12.063982 <6>[ 15.891756] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/ccorr@1400a000
10393 17:59:12.070487 <6>[ 15.891776] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/aal@1400b000
10394 17:59:12.080468 <6>[ 15.891798] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/gamma@1400c000
10395 17:59:12.087297 <6>[ 15.891998] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/dsi@14010000
10396 17:59:12.096876 <4>[ 15.892602] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
10397 17:59:12.106103 <4>[ 15.892733] elants_i2c 0-0010: supply vccio not found, using dummy regulator
10398 17:59:12.120888 <6>[ 15.896825] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10399 17:59:12.121041 <6>[ 15.896831] pci_bus 0000:00: root bus resource [bus 00-ff]
10400 17:59:12.124081 <6>[ 15.896835] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10401 17:59:12.133884 <6>[ 15.896838] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10402 17:59:12.140792 <6>[ 15.896865] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400 PCIe Root Port
10403 17:59:12.147001 <6>[ 15.896878] pci 0000:00:00.0: BAR 0 [mem 0x00000000-0x00003fff 64bit pref]
10404 17:59:12.153822 <6>[ 15.896884] pci 0000:00:00.0: PCI bridge to [bus 00]
10405 17:59:12.160419 <6>[ 15.896889] pci 0000:00:00.0: bridge window [io 0x0000-0x0fff]
10406 17:59:12.167018 <6>[ 15.896891] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff]
10407 17:59:12.173514 <6>[ 15.896899] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff 64bit pref]
10408 17:59:12.176921 <6>[ 15.896954] pci 0000:00:00.0: supports D1 D2
10409 17:59:12.187137 <6>[ 15.896955] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10410 17:59:12.193954 <6>[ 15.898125] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10411 17:59:12.200437 <6>[ 15.898217] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000 PCIe Endpoint
10412 17:59:12.206688 <6>[ 15.898242] pci 0000:01:00.0: BAR 0 [mem 0x00000000-0x000fffff 64bit pref]
10413 17:59:12.216818 <6>[ 15.898258] pci 0000:01:00.0: BAR 2 [mem 0x00000000-0x00003fff 64bit pref]
10414 17:59:12.223648 <6>[ 15.898273] pci 0000:01:00.0: BAR 4 [mem 0x00000000-0x00000fff 64bit pref]
10415 17:59:12.226828 <6>[ 15.898382] pci 0000:01:00.0: supports D1 D2
10416 17:59:12.233013 <6>[ 15.898384] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10417 17:59:12.239806 <6>[ 15.900395] remoteproc remoteproc0: remote processor scp is now up
10418 17:59:12.249611 <6>[ 15.900451] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10419 17:59:12.256327 <6>[ 15.909046] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/ovl@14014000
10420 17:59:12.266384 <6>[ 15.909064] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/rdma@14015000
10421 17:59:12.272982 <6>[ 15.913065] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10422 17:59:12.279605 <3>[ 15.918670] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10423 17:59:12.289453 <4>[ 15.921701] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10424 17:59:12.299668 <4>[ 15.921709] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10425 17:59:12.306180 <6>[ 15.926786] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]: assigned
10426 17:59:12.315696 <4>[ 15.937990] sbs-battery 8-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10427 17:59:12.319054 <4>[ 15.937990] Fallback method does not support PEC.
10428 17:59:12.328758 <6>[ 15.944142] pci 0000:00:00.0: BAR 0 [mem 0x12200000-0x12203fff 64bit pref]: assigned
10429 17:59:12.335623 <6>[ 15.944159] pci 0000:01:00.0: BAR 0 [mem 0x12000000-0x120fffff 64bit pref]: assigned
10430 17:59:12.345481 <6>[ 15.944173] pci 0000:01:00.0: BAR 2 [mem 0x12100000-0x12103fff 64bit pref]: assigned
10431 17:59:12.352230 <6>[ 15.944187] pci 0000:01:00.0: BAR 4 [mem 0x12104000-0x12104fff 64bit pref]: assigned
10432 17:59:12.358518 <6>[ 15.966819] panfrost 13000000.gpu: clock rate = 357999878
10433 17:59:12.361776 <6>[ 15.967414] pci 0000:00:00.0: PCI bridge to [bus 01]
10434 17:59:12.372245 <3>[ 15.972127] power_supply sbs-8-000b: driver failed to report `time_to_empty_now' property: -5
10435 17:59:12.381941 <6>[ 15.976677] panfrost 13000000.gpu: mali-g57 id 0x9093 major 0x0 minor 0x0 status 0x0
10436 17:59:12.388691 <6>[ 15.980000] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10437 17:59:12.395234 <6>[ 15.987122] panfrost 13000000.gpu: features: 00000000,000019f7, issues: 00000003,80000400
10438 17:59:12.401745 <6>[ 15.988894] r8152 2-1.3:1.0 eth0: v1.12.13
10439 17:59:12.408363 <6>[ 15.988947] usbcore: registered new interface driver r8152
10440 17:59:12.415108 <3>[ 15.995062] power_supply sbs-8-000b: driver failed to report `time_to_empty_now' property: -5
10441 17:59:12.421808 <6>[ 15.997428] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10442 17:59:12.434744 <6>[ 16.004578] panfrost 13000000.gpu: Features: L2:0x07130206 Shader:0x00000000 Tiler:0x00000809 Mem:0x101 MMU:0x00002830 AS:0xff JS:0x7
10443 17:59:12.441793 <6>[ 16.004581] panfrost 13000000.gpu: shader_present=0x50045 l2_present=0x1
10444 17:59:12.447906 <6>[ 16.005934] [drm] Initialized panfrost 1.2.0 20180908 for 13000000.gpu on minor 0
10445 17:59:12.454746 <6>[ 16.012609] pcieport 0000:00:00.0: PME: Signaling with IRQ 281
10446 17:59:12.464601 <6>[ 16.018915] elan_i2c 2-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10447 17:59:12.474632 <3>[ 16.019689] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10448 17:59:12.484341 <6>[ 16.022206] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-0/0-0010/input/input2
10449 17:59:12.488012 <6>[ 16.023738] pcieport 0000:00:00.0: AER: enabled with IRQ 281
10450 17:59:12.497593 <6>[ 16.031635] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-2/2-0015/input/input3
10451 17:59:12.507256 <4>[ 16.126880] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10452 17:59:12.514050 <6>[ 16.171885] usbcore: registered new interface driver cdc_ether
10453 17:59:12.520625 <6>[ 16.194410] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10454 17:59:12.527642 <6>[ 16.198107] usbcore: registered new interface driver btusb
10455 17:59:12.537229 <4>[ 16.200083] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1a_2_hdr.bin failed with error -2
10456 17:59:12.544280 <3>[ 16.200093] Bluetooth: hci0: Failed to load firmware file (-2)
10457 17:59:12.550599 <3>[ 16.200097] Bluetooth: hci0: Failed to set up firmware (-2)
10458 17:59:12.560369 <4>[ 16.200101] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10459 17:59:12.567260 <6>[ 16.223323] usbcore: registered new interface driver r8153_ecm
10460 17:59:12.573506 <6>[ 16.228440] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10461 17:59:12.583861 <6>[ 16.266178] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10462 17:59:12.593716 <3>[ 16.275541] debugfs: Directory '11210000.syscon:mt8192-afe-pcm' with parent 'mt8192_mt6359_rt1015p_rt5682' already present!
10463 17:59:12.600485 <6>[ 16.299184] usbcore: registered new interface driver uvcvideo
10464 17:59:12.607006 <6>[ 16.301529] cros-ec-dev cros-ec-dev.12.auto: CrOS System Control Processor MCU detected
10465 17:59:12.616643 <6>[ 16.303447] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10466 17:59:12.623276 <5>[ 16.310761] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10467 17:59:12.629757 <4>[ 16.312124] rt5682 1-001a: ASoC: source widget I2S1 overwritten
10468 17:59:12.636555 <6>[ 16.393947] panel-simple-dp-aux aux-3-0058: Detected IVO R140NWF5 RH (0x057d)
10469 17:59:12.642832 <5>[ 16.431045] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10470 17:59:12.649610 <5>[ 16.508035] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10471 17:59:12.659817 <4>[ 16.515706] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10472 17:59:12.666007 <6>[ 16.524584] cfg80211: failed to load regulatory.db
10473 17:59:12.690711 <6>[ 16.546767] input: mt8192_mt6359_rt1015p_rt5682 Headset Jack as /devices/platform/sound/sound/card0/input4
10474 17:59:12.703667 <3>[ 16.562828] SVSB_GPU_LOW: cannot get "gpu" thermal zone
10475 17:59:12.710145 <3>[ 16.568475] mtk-svs 1100bc00.svs: error -ENODEV: svs bank resource setup fail
10476 17:59:12.720216 <6>[ 16.568532] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10477 17:59:12.726890 <6>[ 16.578365] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10478 17:59:12.733116 <6>[ 16.583409] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10479 17:59:12.742914 <6>[ 16.591649] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10480 17:59:12.746463 <6>[ 16.600304] mt7921e 0000:01:00.0: ASIC revision: 79610010
10481 17:59:12.756350 <6>[ 16.606301] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10482 17:59:12.762894 <6>[ 16.620207] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10483 17:59:12.772747 <6>[ 16.628549] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10484 17:59:12.779478 <6>[ 16.636888] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10485 17:59:12.789101 <6>[ 16.645227] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10486 17:59:12.795863 <6>[ 16.653565] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10487 17:59:12.805805 <6>[ 16.661903] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10488 17:59:12.815914 <6>[ 16.670240] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10489 17:59:12.822061 <6>[ 16.678578] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10490 17:59:12.832630 <6>[ 16.686915] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10491 17:59:12.839256 <6>[ 16.695266] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10492 17:59:12.849195 <6>[ 16.703511] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10493 17:59:12.849405 <6>[ 16.703511]
10494 17:59:12.858855 <6>[ 16.703610] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10495 17:59:12.865091 <6>[ 16.722020] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10496 17:59:12.873031 <6>[ 16.732781] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10497 17:59:12.882660 <6>[ 16.741917] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10498 17:59:12.891300 <6>[ 16.750516] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10499 17:59:12.899153 <6>[ 16.758657] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10500 17:59:12.910920 <6>[ 16.766960] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10501 17:59:12.920717 <6>[ 16.773982] mediatek-drm mediatek-drm.11.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops [mediatek_drm])
10502 17:59:12.930924 <6>[ 16.784543] mediatek-drm mediatek-drm.11.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops [mediatek_drm])
10503 17:59:12.940615 <6>[ 16.795060] mediatek-drm mediatek-drm.11.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops [mediatek_drm])
10504 17:59:12.953853 <6>[ 16.805748] mediatek-drm mediatek-drm.11.auto: bound 14009000.color (ops mtk_disp_color_component_ops [mediatek_drm])
10505 17:59:12.963914 <6>[ 16.816609] mediatek-drm mediatek-drm.11.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops [mediatek_drm])
10506 17:59:12.973732 <6>[ 16.827475] mediatek-drm mediatek-drm.11.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops [mediatek_drm])
10507 17:59:12.983658 <6>[ 16.837996] mediatek-drm mediatek-drm.11.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops [mediatek_drm])
10508 17:59:12.983744 done
10509 17:59:12.996844 Saving random seed: <6>[ 16.850616] mediatek-drm mediatek-drm.11.auto: bound 14010000.dsi (ops mtk_dsi_component_ops [mediatek_drm])
10510 17:59:13.006547 <6>[ 16.861275] mediatek-drm mediatek-drm.11.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops [mediatek_drm])
10511 17:59:13.016379 <6>[ 16.871791] mediatek-drm mediatek-drm.11.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops [mediatek_drm])
10512 17:59:13.020011 OK
10513 17:59:13.029901 <6>[ 16.882517] mediatek-drm mediatek-drm.11.auto: Not creating crtc 1 because component 10 is disabled or missing
10514 17:59:13.039694 Starting network<6>[ 16.894131] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.11.auto on minor 1
10515 17:59:13.039783 : OK
10516 17:59:13.082358 Starting dropbear sshd: <6>[ 16.941617] NET: Registered PF_INET6 protocol family
10517 17:59:13.089160 <6>[ 16.947699] Segment Routing with IPv6
10518 17:59:13.092179 <6>[ 16.951707] In-situ OAM (IOAM) with IPv6
10519 17:59:13.092261 OK
10520 17:59:13.103322 /bin/sh: can't access tty; job control turned off
10521 17:59:13.103659 Matched prompt #10: / #
10523 17:59:13.103859 Setting prompt string to ['/ #']
10524 17:59:13.103950 end: 2.2.5.1 login-action (duration 00:00:18) [common]
10526 17:59:13.104141 end: 2.2.5 auto-login-action (duration 00:00:18) [common]
10527 17:59:13.104229 start: 2.2.6 expect-shell-connection (timeout 00:03:43) [common]
10528 17:59:13.104297 Setting prompt string to ['/ #']
10529 17:59:13.104356 Forcing a shell prompt, looking for ['/ #']
10531 17:59:13.154572 / #
10532 17:59:13.154733 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10533 17:59:13.154829 Waiting using forced prompt support (timeout 00:02:30)
10534 17:59:13.154930 <6>[ 16.973838] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10535 17:59:13.159632
10536 17:59:13.159908 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10537 17:59:13.160001 start: 2.2.7 export-device-env (timeout 00:03:43) [common]
10538 17:59:13.160092 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10539 17:59:13.160177 end: 2.2 depthcharge-retry (duration 00:01:17) [common]
10540 17:59:13.160259 end: 2 depthcharge-action (duration 00:01:17) [common]
10541 17:59:13.160344 start: 3 lava-test-retry (timeout 00:01:00) [common]
10542 17:59:13.160427 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10543 17:59:13.160499 Using namespace: common
10545 17:59:13.260843 / # #
10546 17:59:13.261020 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10547 17:59:13.266015 #
10548 17:59:13.266321 Using /lava-13522576
10550 17:59:13.366713 / # export SHELL=/bin/sh
10551 17:59:13.371896 export SHELL=/bin/sh
10553 17:59:13.472436 / # . /lava-13522576/environment
10554 17:59:13.472638 . /lava-13522576/environment<6>[ 17.287096] Console: switching to colour frame buffer device 240x67
10555 17:59:13.472720 <6>[ 17.324804] mediatek-drm mediatek-drm.11.auto: [drm] fb0: mediatekdrmfb frame buffer device
10556 17:59:13.477345
10558 17:59:13.577962 / # /lava-13522576/bin/lava-test-runner /lava-13522576/0
10559 17:59:13.578141 Test shell timeout: 10s (minimum of the action and connection timeout)
10560 17:59:13.578466 <6>[ 17.351494] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 1
10561 17:59:13.578542 <6>[ 17.361558] mtk-vcodec-dec 16000000.video-codec: Adding to iommu group 1
10562 17:59:13.578606 <6>[ 17.384809] mtk-vdec-comp 16010000.video-codec: Adding to iommu group 1
10563 17:59:13.578665 <6>[ 17.392009] mtk-vdec-comp 16025000.video-codec: Adding to iommu group 1
10564 17:59:13.578722 <4>[ 17.399016] ttyS ttyS0: 1 input overrun(s)
10565 17:59:13.583239 /lava-13522576/bin/lava-test-run522576/0
10566 17:59:13.626270 /bin/sh: /lava-13522576/bin/lava-test-run522576/0: not found
10567 17:59:13.937552 / # <6>[ 17.796889] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10568 17:59:42.299930 <6>[ 46.165166] vpu: disabling
10569 17:59:42.302901 <6>[ 46.168277] vproc2: disabling
10570 17:59:42.306005 <6>[ 46.171810] vproc1: disabling
10571 17:59:42.309162 <6>[ 46.175123] vaud18: disabling
10572 17:59:42.313072 <6>[ 46.178869] va09: disabling
10573 17:59:42.319448 <6>[ 46.182112] vsram_md: disabling
10574 17:59:42.327977 <6>[ 46.190255] pp1000_dpbrdg: disabling
10575 17:59:42.331129 <6>[ 46.194111] pp1800_dpbrdg: disabling
10576 17:59:42.334653 <6>[ 46.198081] pp3300_dpbrdg: disabling
10578 18:00:13.160694 end: 3.1 lava-test-shell (duration 00:01:00) [common]
10580 18:00:13.160896 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
10582 18:00:13.161044 end: 3 lava-test-retry (duration 00:01:00) [common]
10584 18:00:13.161252 Cleaning after the job
10585 18:00:13.161343 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13522576/tftp-deploy-b23ke98q/ramdisk
10586 18:00:13.163925 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13522576/tftp-deploy-b23ke98q/kernel
10587 18:00:13.176112 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13522576/tftp-deploy-b23ke98q/dtb
10588 18:00:13.176341 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13522576/tftp-deploy-b23ke98q/modules
10589 18:00:13.182794 start: 4.1 power-off (timeout 00:00:30) [common]
10590 18:00:13.182995 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
10591 18:00:13.258939 >> Command sent successfully.
10592 18:00:13.261243 Returned 0 in 0 seconds
10593 18:00:13.361647 end: 4.1 power-off (duration 00:00:00) [common]
10595 18:00:13.362007 start: 4.2 read-feedback (timeout 00:10:00) [common]
10596 18:00:13.362365 Listened to connection for namespace 'common' for up to 1s
10597 18:00:14.363294 Finalising connection for namespace 'common'
10598 18:00:14.363482 Disconnecting from shell: Finalise
10599 18:00:14.463849 end: 4.2 read-feedback (duration 00:00:01) [common]
10600 18:00:14.464046 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13522576
10601 18:00:14.515550 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13522576
10602 18:00:14.515822 TestError: A test failed to run, look at the error message.