Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 56
- Errors: 2
- Kernel Errors: 8
- Boot result: FAIL
1 08:13:16.718978 lava-dispatcher, installed at version: 2024.01
2 08:13:16.719175 start: 0 validate
3 08:13:16.719298 Start time: 2024-04-26 08:13:16.719291+00:00 (UTC)
4 08:13:16.719411 Using caching service: 'http://localhost/cache/?uri=%s'
5 08:13:16.719536 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 08:13:16.990129 Using caching service: 'http://localhost/cache/?uri=%s'
7 08:13:16.990847 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240426%2Farm64%2Fdefconfig%2Barm64-chromebook%2Bvideodec%2Fgcc-10%2Fkernel%2FImage exists
8 08:13:17.259971 Using caching service: 'http://localhost/cache/?uri=%s'
9 08:13:17.260688 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240426%2Farm64%2Fdefconfig%2Barm64-chromebook%2Bvideodec%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 08:13:17.535710 Using caching service: 'http://localhost/cache/?uri=%s'
11 08:13:17.536484 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240426%2Farm64%2Fdefconfig%2Barm64-chromebook%2Bvideodec%2Fgcc-10%2Fmodules.tar.xz exists
12 08:13:18.078494 validate duration: 1.36
14 08:13:18.078771 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 08:13:18.078870 start: 1.1 download-retry (timeout 00:10:00) [common]
16 08:13:18.078958 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 08:13:18.079078 Not decompressing ramdisk as can be used compressed.
18 08:13:18.079163 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 08:13:18.079227 saving as /var/lib/lava/dispatcher/tmp/13529852/tftp-deploy-9psta492/ramdisk/rootfs.cpio.gz
20 08:13:18.079292 total size: 8181887 (7 MB)
21 08:13:18.080314 progress 0 % (0 MB)
22 08:13:18.082652 progress 5 % (0 MB)
23 08:13:18.084732 progress 10 % (0 MB)
24 08:13:18.087109 progress 15 % (1 MB)
25 08:13:18.089158 progress 20 % (1 MB)
26 08:13:18.091385 progress 25 % (1 MB)
27 08:13:18.093425 progress 30 % (2 MB)
28 08:13:18.095614 progress 35 % (2 MB)
29 08:13:18.097685 progress 40 % (3 MB)
30 08:13:18.099881 progress 45 % (3 MB)
31 08:13:18.102005 progress 50 % (3 MB)
32 08:13:18.104149 progress 55 % (4 MB)
33 08:13:18.106273 progress 60 % (4 MB)
34 08:13:18.108465 progress 65 % (5 MB)
35 08:13:18.110513 progress 70 % (5 MB)
36 08:13:18.112653 progress 75 % (5 MB)
37 08:13:18.114687 progress 80 % (6 MB)
38 08:13:18.116824 progress 85 % (6 MB)
39 08:13:18.118925 progress 90 % (7 MB)
40 08:13:18.121134 progress 95 % (7 MB)
41 08:13:18.123149 progress 100 % (7 MB)
42 08:13:18.123345 7 MB downloaded in 0.04 s (177.13 MB/s)
43 08:13:18.123502 end: 1.1.1 http-download (duration 00:00:00) [common]
45 08:13:18.123740 end: 1.1 download-retry (duration 00:00:00) [common]
46 08:13:18.123826 start: 1.2 download-retry (timeout 00:10:00) [common]
47 08:13:18.123909 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 08:13:18.124037 downloading http://storage.kernelci.org/next/master/next-20240426/arm64/defconfig+arm64-chromebook+videodec/gcc-10/kernel/Image
49 08:13:18.124104 saving as /var/lib/lava/dispatcher/tmp/13529852/tftp-deploy-9psta492/kernel/Image
50 08:13:18.124164 total size: 59617792 (56 MB)
51 08:13:18.124225 No compression specified
52 08:13:18.125304 progress 0 % (0 MB)
53 08:13:18.140158 progress 5 % (2 MB)
54 08:13:18.155215 progress 10 % (5 MB)
55 08:13:18.170581 progress 15 % (8 MB)
56 08:13:18.185788 progress 20 % (11 MB)
57 08:13:18.200675 progress 25 % (14 MB)
58 08:13:18.215762 progress 30 % (17 MB)
59 08:13:18.230670 progress 35 % (19 MB)
60 08:13:18.245566 progress 40 % (22 MB)
61 08:13:18.260502 progress 45 % (25 MB)
62 08:13:18.275425 progress 50 % (28 MB)
63 08:13:18.290343 progress 55 % (31 MB)
64 08:13:18.305081 progress 60 % (34 MB)
65 08:13:18.320508 progress 65 % (36 MB)
66 08:13:18.335383 progress 70 % (39 MB)
67 08:13:18.350168 progress 75 % (42 MB)
68 08:13:18.365136 progress 80 % (45 MB)
69 08:13:18.380121 progress 85 % (48 MB)
70 08:13:18.395212 progress 90 % (51 MB)
71 08:13:18.409987 progress 95 % (54 MB)
72 08:13:18.424676 progress 100 % (56 MB)
73 08:13:18.424849 56 MB downloaded in 0.30 s (189.09 MB/s)
74 08:13:18.425000 end: 1.2.1 http-download (duration 00:00:00) [common]
76 08:13:18.425237 end: 1.2 download-retry (duration 00:00:00) [common]
77 08:13:18.425326 start: 1.3 download-retry (timeout 00:10:00) [common]
78 08:13:18.425460 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 08:13:18.425594 downloading http://storage.kernelci.org/next/master/next-20240426/arm64/defconfig+arm64-chromebook+videodec/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 08:13:18.425661 saving as /var/lib/lava/dispatcher/tmp/13529852/tftp-deploy-9psta492/dtb/mt8192-asurada-spherion-r0.dtb
81 08:13:18.425722 total size: 65337 (0 MB)
82 08:13:18.425783 No compression specified
83 08:13:18.426883 progress 50 % (0 MB)
84 08:13:18.469754 progress 100 % (0 MB)
85 08:13:18.470138 0 MB downloaded in 0.04 s (1.40 MB/s)
86 08:13:18.470339 end: 1.3.1 http-download (duration 00:00:00) [common]
88 08:13:18.470632 end: 1.3 download-retry (duration 00:00:00) [common]
89 08:13:18.470738 start: 1.4 download-retry (timeout 00:10:00) [common]
90 08:13:18.470833 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 08:13:18.470989 downloading http://storage.kernelci.org/next/master/next-20240426/arm64/defconfig+arm64-chromebook+videodec/gcc-10/modules.tar.xz
92 08:13:18.471067 saving as /var/lib/lava/dispatcher/tmp/13529852/tftp-deploy-9psta492/modules/modules.tar
93 08:13:18.471136 total size: 10644924 (10 MB)
94 08:13:18.471207 Using unxz to decompress xz
95 08:13:18.475487 progress 0 % (0 MB)
96 08:13:18.503771 progress 5 % (0 MB)
97 08:13:18.534028 progress 10 % (1 MB)
98 08:13:18.565212 progress 15 % (1 MB)
99 08:13:18.595590 progress 20 % (2 MB)
100 08:13:18.625665 progress 25 % (2 MB)
101 08:13:18.654849 progress 30 % (3 MB)
102 08:13:18.684096 progress 35 % (3 MB)
103 08:13:18.713871 progress 40 % (4 MB)
104 08:13:18.746451 progress 45 % (4 MB)
105 08:13:18.777832 progress 50 % (5 MB)
106 08:13:18.808597 progress 55 % (5 MB)
107 08:13:18.838358 progress 60 % (6 MB)
108 08:13:18.869725 progress 65 % (6 MB)
109 08:13:18.900666 progress 70 % (7 MB)
110 08:13:18.933746 progress 75 % (7 MB)
111 08:13:18.968233 progress 80 % (8 MB)
112 08:13:18.998104 progress 85 % (8 MB)
113 08:13:19.026533 progress 90 % (9 MB)
114 08:13:19.054550 progress 95 % (9 MB)
115 08:13:19.085009 progress 100 % (10 MB)
116 08:13:19.090674 10 MB downloaded in 0.62 s (16.39 MB/s)
117 08:13:19.090922 end: 1.4.1 http-download (duration 00:00:01) [common]
119 08:13:19.091185 end: 1.4 download-retry (duration 00:00:01) [common]
120 08:13:19.091275 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 08:13:19.091370 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 08:13:19.091449 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 08:13:19.091535 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 08:13:19.091753 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a
125 08:13:19.091882 makedir: /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin
126 08:13:19.091982 makedir: /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/tests
127 08:13:19.092076 makedir: /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/results
128 08:13:19.092187 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-add-keys
129 08:13:19.092334 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-add-sources
130 08:13:19.092510 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-background-process-start
131 08:13:19.092638 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-background-process-stop
132 08:13:19.092762 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-common-functions
133 08:13:19.092883 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-echo-ipv4
134 08:13:19.093003 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-install-packages
135 08:13:19.093124 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-installed-packages
136 08:13:19.093242 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-os-build
137 08:13:19.093383 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-probe-channel
138 08:13:19.093531 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-probe-ip
139 08:13:19.093652 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-target-ip
140 08:13:19.093773 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-target-mac
141 08:13:19.093894 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-target-storage
142 08:13:19.094020 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-test-case
143 08:13:19.094141 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-test-event
144 08:13:19.094261 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-test-feedback
145 08:13:19.094388 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-test-raise
146 08:13:19.094513 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-test-reference
147 08:13:19.094634 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-test-runner
148 08:13:19.094755 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-test-set
149 08:13:19.094878 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-test-shell
150 08:13:19.095003 Updating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-install-packages (oe)
151 08:13:19.095149 Updating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/bin/lava-installed-packages (oe)
152 08:13:19.095268 Creating /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/environment
153 08:13:19.095365 LAVA metadata
154 08:13:19.095439 - LAVA_JOB_ID=13529852
155 08:13:19.095503 - LAVA_DISPATCHER_IP=192.168.201.1
156 08:13:19.095605 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 08:13:19.095670 skipped lava-vland-overlay
158 08:13:19.095743 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 08:13:19.095823 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 08:13:19.095886 skipped lava-multinode-overlay
161 08:13:19.095960 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 08:13:19.096041 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 08:13:19.096112 Loading test definitions
164 08:13:19.096200 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 08:13:19.096278 Using /lava-13529852 at stage 0
166 08:13:19.096622 uuid=13529852_1.5.2.3.1 testdef=None
167 08:13:19.096710 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 08:13:19.096796 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 08:13:19.097313 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 08:13:19.097576 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 08:13:19.098201 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 08:13:19.098436 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 08:13:19.099042 runner path: /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/0/tests/0_dmesg test_uuid 13529852_1.5.2.3.1
176 08:13:19.099196 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 08:13:19.099405 Creating lava-test-runner.conf files
179 08:13:19.099468 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13529852/lava-overlay-kochv87a/lava-13529852/0 for stage 0
180 08:13:19.099556 - 0_dmesg
181 08:13:19.099650 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 08:13:19.099735 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 08:13:19.106934 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 08:13:19.107038 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 08:13:19.107124 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 08:13:19.107210 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 08:13:19.107295 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 08:13:19.344461 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 08:13:19.344853 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
190 08:13:19.344976 extracting modules file /var/lib/lava/dispatcher/tmp/13529852/tftp-deploy-9psta492/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13529852/extract-overlay-ramdisk-cme071w_/ramdisk
191 08:13:19.602614 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 08:13:19.602800 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 08:13:19.602894 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13529852/compress-overlay-kkzz5vlf/overlay-1.5.2.4.tar.gz to ramdisk
194 08:13:19.602968 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13529852/compress-overlay-kkzz5vlf/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13529852/extract-overlay-ramdisk-cme071w_/ramdisk
195 08:13:19.609462 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 08:13:19.609570 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 08:13:19.609660 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 08:13:19.609745 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 08:13:19.609817 Building ramdisk /var/lib/lava/dispatcher/tmp/13529852/extract-overlay-ramdisk-cme071w_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13529852/extract-overlay-ramdisk-cme071w_/ramdisk
200 08:13:20.042137 >> 171005 blocks
201 08:13:22.664158 rename /var/lib/lava/dispatcher/tmp/13529852/extract-overlay-ramdisk-cme071w_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13529852/tftp-deploy-9psta492/ramdisk/ramdisk.cpio.gz
202 08:13:22.664600 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 08:13:22.664717 start: 1.5.8 prepare-kernel (timeout 00:09:55) [common]
204 08:13:22.664822 start: 1.5.8.1 prepare-fit (timeout 00:09:55) [common]
205 08:13:22.664928 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13529852/tftp-deploy-9psta492/kernel/Image'
206 08:13:36.392125 Returned 0 in 13 seconds
207 08:13:36.493193 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13529852/tftp-deploy-9psta492/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13529852/tftp-deploy-9psta492/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13529852/tftp-deploy-9psta492/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13529852/tftp-deploy-9psta492/kernel/image.itb
208 08:13:36.932969 output: FIT description: Kernel Image image with one or more FDT blobs
209 08:13:36.933375 output: Created: Fri Apr 26 09:13:36 2024
210 08:13:36.933483 output: Image 0 (kernel-1)
211 08:13:36.933548 output: Description:
212 08:13:36.933610 output: Created: Fri Apr 26 09:13:36 2024
213 08:13:36.933668 output: Type: Kernel Image
214 08:13:36.933726 output: Compression: lzma compressed
215 08:13:36.933782 output: Data Size: 13406858 Bytes = 13092.63 KiB = 12.79 MiB
216 08:13:36.933840 output: Architecture: AArch64
217 08:13:36.933895 output: OS: Linux
218 08:13:36.933948 output: Load Address: 0x00000000
219 08:13:36.934003 output: Entry Point: 0x00000000
220 08:13:36.934060 output: Hash algo: crc32
221 08:13:36.934127 output: Hash value: bf86c78d
222 08:13:36.934214 output: Image 1 (fdt-1)
223 08:13:36.934272 output: Description: mt8192-asurada-spherion-r0
224 08:13:36.934324 output: Created: Fri Apr 26 09:13:36 2024
225 08:13:36.934379 output: Type: Flat Device Tree
226 08:13:36.934499 output: Compression: uncompressed
227 08:13:36.934551 output: Data Size: 65337 Bytes = 63.81 KiB = 0.06 MiB
228 08:13:36.934603 output: Architecture: AArch64
229 08:13:36.934655 output: Hash algo: crc32
230 08:13:36.934706 output: Hash value: 8e06b835
231 08:13:36.934757 output: Image 2 (ramdisk-1)
232 08:13:36.934808 output: Description: unavailable
233 08:13:36.934859 output: Created: Fri Apr 26 09:13:36 2024
234 08:13:36.934910 output: Type: RAMDisk Image
235 08:13:36.934979 output: Compression: Unknown Compression
236 08:13:36.935044 output: Data Size: 24597836 Bytes = 24021.32 KiB = 23.46 MiB
237 08:13:36.935096 output: Architecture: AArch64
238 08:13:36.935156 output: OS: Linux
239 08:13:36.935213 output: Load Address: unavailable
240 08:13:36.935265 output: Entry Point: unavailable
241 08:13:36.935315 output: Hash algo: crc32
242 08:13:36.935366 output: Hash value: 5a3d0528
243 08:13:36.935417 output: Default Configuration: 'conf-1'
244 08:13:36.935468 output: Configuration 0 (conf-1)
245 08:13:36.935519 output: Description: mt8192-asurada-spherion-r0
246 08:13:36.935570 output: Kernel: kernel-1
247 08:13:36.935621 output: Init Ramdisk: ramdisk-1
248 08:13:36.935672 output: FDT: fdt-1
249 08:13:36.935722 output: Loadables: kernel-1
250 08:13:36.935773 output:
251 08:13:36.935974 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 08:13:36.936069 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 08:13:36.936165 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 08:13:36.936255 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 08:13:36.936334 No LXC device requested
256 08:13:36.936444 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 08:13:36.936542 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 08:13:36.936619 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 08:13:36.936689 Checking files for TFTP limit of 4294967296 bytes.
260 08:13:36.937174 end: 1 tftp-deploy (duration 00:00:19) [common]
261 08:13:36.937279 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 08:13:36.937415 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 08:13:36.937544 substitutions:
264 08:13:36.937611 - {DTB}: 13529852/tftp-deploy-9psta492/dtb/mt8192-asurada-spherion-r0.dtb
265 08:13:36.937676 - {INITRD}: 13529852/tftp-deploy-9psta492/ramdisk/ramdisk.cpio.gz
266 08:13:36.937735 - {KERNEL}: 13529852/tftp-deploy-9psta492/kernel/Image
267 08:13:36.937792 - {LAVA_MAC}: None
268 08:13:36.937847 - {PRESEED_CONFIG}: None
269 08:13:36.937901 - {PRESEED_LOCAL}: None
270 08:13:36.937954 - {RAMDISK}: 13529852/tftp-deploy-9psta492/ramdisk/ramdisk.cpio.gz
271 08:13:36.938008 - {ROOT_PART}: None
272 08:13:36.938061 - {ROOT}: None
273 08:13:36.938113 - {SERVER_IP}: 192.168.201.1
274 08:13:36.938165 - {TEE}: None
275 08:13:36.938217 Parsed boot commands:
276 08:13:36.938271 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 08:13:36.938440 Parsed boot commands: tftpboot 192.168.201.1 13529852/tftp-deploy-9psta492/kernel/image.itb 13529852/tftp-deploy-9psta492/kernel/cmdline
278 08:13:36.938528 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 08:13:36.938611 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 08:13:36.938700 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 08:13:36.938784 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 08:13:36.938855 Not connected, no need to disconnect.
283 08:13:36.938927 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 08:13:36.939005 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 08:13:36.939072 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 08:13:36.942976 Setting prompt string to ['lava-test: # ']
287 08:13:36.943372 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 08:13:36.943494 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 08:13:36.943609 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 08:13:36.943732 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 08:13:36.944034 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
292 08:13:42.092522 >> Command sent successfully.
293 08:13:42.102574 Returned 0 in 5 seconds
294 08:13:42.203927 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 08:13:42.206483 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 08:13:42.207045 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 08:13:42.207555 Setting prompt string to 'Starting depthcharge on Spherion...'
299 08:13:42.207936 Changing prompt to 'Starting depthcharge on Spherion...'
300 08:13:42.208313 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 08:13:42.209636 [Enter `^Ec?' for help]
302 08:13:42.599101
303 08:13:42.599693
304 08:13:42.600085 F0: 102B 0000
305 08:13:42.600474
306 08:13:42.600855 F3: 1001 0000 [0200]
307 08:13:42.602210
308 08:13:42.602783 F3: 1001 0000
309 08:13:42.603304
310 08:13:42.603674 F7: 102D 0000
311 08:13:42.604024
312 08:13:42.605169 F1: 0000 0000
313 08:13:42.605680
314 08:13:42.606058 V0: 0000 0000 [0001]
315 08:13:42.606426
316 08:13:42.608646 00: 0007 8000
317 08:13:42.609147
318 08:13:42.609563 01: 0000 0000
319 08:13:42.609929
320 08:13:42.612075 BP: 0C00 0209 [0000]
321 08:13:42.612547
322 08:13:42.612923 G0: 1182 0000
323 08:13:42.613280
324 08:13:42.615597 EC: 0000 0021 [4000]
325 08:13:42.616128
326 08:13:42.616489 S7: 0000 0000 [0000]
327 08:13:42.616851
328 08:13:42.618584 CC: 0000 0000 [0001]
329 08:13:42.619014
330 08:13:42.619355 T0: 0000 0040 [010F]
331 08:13:42.619674
332 08:13:42.622082 Jump to BL
333 08:13:42.622509
334 08:13:42.645587
335 08:13:42.646214
336 08:13:42.646600
337 08:13:42.655545 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 08:13:42.658553 ARM64: Exception handlers installed.
339 08:13:42.659021 ARM64: Testing exception
340 08:13:42.662023 ARM64: Done test exception
341 08:13:42.668792 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 08:13:42.679598 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 08:13:42.686050 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 08:13:42.696329 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 08:13:42.703011 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 08:13:42.713455 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 08:13:42.723777 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 08:13:42.730060 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 08:13:42.748947 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 08:13:42.752577 WDT: Last reset was cold boot
351 08:13:42.755579 SPI1(PAD0) initialized at 2873684 Hz
352 08:13:42.758924 SPI5(PAD0) initialized at 992727 Hz
353 08:13:42.762681 VBOOT: Loading verstage.
354 08:13:42.768795 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 08:13:42.772097 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 08:13:42.775217 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 08:13:42.778458 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 08:13:42.786230 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 08:13:42.792763 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 08:13:42.804172 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 08:13:42.804744
362 08:13:42.805122
363 08:13:42.813791 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 08:13:42.816911 ARM64: Exception handlers installed.
365 08:13:42.820174 ARM64: Testing exception
366 08:13:42.823671 ARM64: Done test exception
367 08:13:42.826659 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 08:13:42.829907 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 08:13:42.844696 Probing TPM: . done!
370 08:13:42.845325 TPM ready after 0 ms
371 08:13:42.851660 Connected to device vid:did:rid of 1ae0:0028:00
372 08:13:42.861397 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 08:13:42.899381 Initialized TPM device CR50 revision 0
374 08:13:42.911486 tlcl_send_startup: Startup return code is 0
375 08:13:42.911920 TPM: setup succeeded
376 08:13:42.922845 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 08:13:42.931466 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 08:13:42.941954 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 08:13:42.950211 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 08:13:42.953714 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 08:13:42.957124 in-header: 03 07 00 00 08 00 00 00
382 08:13:42.960536 in-data: aa e4 47 04 13 02 00 00
383 08:13:42.964090 Chrome EC: UHEPI supported
384 08:13:42.971181 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 08:13:42.975117 in-header: 03 ad 00 00 08 00 00 00
386 08:13:42.978284 in-data: 00 20 20 08 00 00 00 00
387 08:13:42.978739 Phase 1
388 08:13:42.982270 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 08:13:42.989465 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 08:13:42.993443 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 08:13:42.996039 Recovery requested (1009000e)
392 08:13:43.006827 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 08:13:43.012494 tlcl_extend: response is 0
394 08:13:43.023926 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 08:13:43.027536 tlcl_extend: response is 0
396 08:13:43.034712 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 08:13:43.054608 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 08:13:43.061696 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 08:13:43.062436
400 08:13:43.063058
401 08:13:43.071444 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 08:13:43.074317 ARM64: Exception handlers installed.
403 08:13:43.077544 ARM64: Testing exception
404 08:13:43.078151 ARM64: Done test exception
405 08:13:43.100908 pmic_efuse_setting: Set efuses in 11 msecs
406 08:13:43.103310 pmwrap_interface_init: Select PMIF_VLD_RDY
407 08:13:43.110022 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 08:13:43.113540 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 08:13:43.117059 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 08:13:43.123919 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 08:13:43.126856 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 08:13:43.133420 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 08:13:43.136986 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 08:13:43.144060 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 08:13:43.146833 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 08:13:43.153427 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 08:13:43.156797 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 08:13:43.160487 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 08:13:43.166612 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 08:13:43.173826 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 08:13:43.177034 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 08:13:43.183595 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 08:13:43.189933 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 08:13:43.193001 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 08:13:43.199940 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 08:13:43.206665 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 08:13:43.213452 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 08:13:43.216678 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 08:13:43.222849 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 08:13:43.229264 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 08:13:43.233069 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 08:13:43.240020 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 08:13:43.242733 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 08:13:43.249073 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 08:13:43.252659 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 08:13:43.259313 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 08:13:43.262695 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 08:13:43.269621 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 08:13:43.272752 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 08:13:43.279338 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 08:13:43.282550 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 08:13:43.289011 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 08:13:43.292257 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 08:13:43.298946 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 08:13:43.302061 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 08:13:43.308939 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 08:13:43.312294 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 08:13:43.315469 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 08:13:43.321840 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 08:13:43.325253 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 08:13:43.328541 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 08:13:43.335682 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 08:13:43.339140 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 08:13:43.342050 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 08:13:43.345804 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 08:13:43.352307 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 08:13:43.355167 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 08:13:43.362133 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 08:13:43.371582 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 08:13:43.374913 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 08:13:43.384971 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 08:13:43.391440 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 08:13:43.398224 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 08:13:43.401570 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 08:13:43.404841 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 08:13:43.412093 [RTC]rtc_enable_dcxo,68: con=0x406, osc32con=0xde6c, sec=0x1f
467 08:13:43.419404 [RTC]rtc_check_state,173: con=406, pwrkey1=a357, pwrkey2=67d2
468 08:13:43.422430 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
469 08:13:43.426026 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 08:13:43.437203 [RTC]rtc_get_frequency_meter,154: input=15, output=833
471 08:13:43.446980 [RTC]rtc_get_frequency_meter,154: input=7, output=707
472 08:13:43.456211 [RTC]rtc_get_frequency_meter,154: input=11, output=771
473 08:13:43.465780 [RTC]rtc_get_frequency_meter,154: input=13, output=802
474 08:13:43.474984 [RTC]rtc_get_frequency_meter,154: input=12, output=786
475 08:13:43.484732 [RTC]rtc_get_frequency_meter,154: input=12, output=786
476 08:13:43.494194 [RTC]rtc_get_frequency_meter,154: input=13, output=803
477 08:13:43.497290 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
478 08:13:43.504693 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
479 08:13:43.507933 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 08:13:43.510613 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 08:13:43.517969 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 08:13:43.520761 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 08:13:43.524258 ADC[4]: Raw value=905618 ID=7
484 08:13:43.524864 ADC[3]: Raw value=213282 ID=1
485 08:13:43.527619 RAM Code: 0x71
486 08:13:43.530705 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 08:13:43.537861 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 08:13:43.544351 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 08:13:43.550708 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 08:13:43.553765 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 08:13:43.557475 in-header: 03 07 00 00 08 00 00 00
492 08:13:43.560571 in-data: aa e4 47 04 13 02 00 00
493 08:13:43.563995 Chrome EC: UHEPI supported
494 08:13:43.570566 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 08:13:43.574231 in-header: 03 ed 00 00 08 00 00 00
496 08:13:43.577747 in-data: 80 20 60 08 00 00 00 00
497 08:13:43.580957 MRC: failed to locate region type 0.
498 08:13:43.587397 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 08:13:43.590639 DRAM-K: Running full calibration
500 08:13:43.597175 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 08:13:43.597807 header.status = 0x0
502 08:13:43.601061 header.version = 0x6 (expected: 0x6)
503 08:13:43.603752 header.size = 0xd00 (expected: 0xd00)
504 08:13:43.607142 header.flags = 0x0
505 08:13:43.613459 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 08:13:43.631164 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 08:13:43.637628 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 08:13:43.641116 dram_init: ddr_geometry: 2
509 08:13:43.644128 [EMI] MDL number = 2
510 08:13:43.644611 [EMI] Get MDL freq = 0
511 08:13:43.648062 dram_init: ddr_type: 0
512 08:13:43.648647 is_discrete_lpddr4: 1
513 08:13:43.651605 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 08:13:43.652251
515 08:13:43.652712
516 08:13:43.655246 [Bian_co] ETT version 0.0.0.1
517 08:13:43.658939 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 08:13:43.659447
519 08:13:43.662217 dramc_set_vcore_voltage set vcore to 650000
520 08:13:43.666427 Read voltage for 800, 4
521 08:13:43.666934 Vio18 = 0
522 08:13:43.670170 Vcore = 650000
523 08:13:43.670783 Vdram = 0
524 08:13:43.671181 Vddq = 0
525 08:13:43.671536 Vmddr = 0
526 08:13:43.673866 dram_init: config_dvfs: 1
527 08:13:43.677544 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 08:13:43.683843 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 08:13:43.687109 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
530 08:13:43.690882 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
531 08:13:43.693820 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
532 08:13:43.697263 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
533 08:13:43.700571 MEM_TYPE=3, freq_sel=18
534 08:13:43.703941 sv_algorithm_assistance_LP4_1600
535 08:13:43.707110 ============ PULL DRAM RESETB DOWN ============
536 08:13:43.713540 ========== PULL DRAM RESETB DOWN end =========
537 08:13:43.717440 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 08:13:43.720251 ===================================
539 08:13:43.723285 LPDDR4 DRAM CONFIGURATION
540 08:13:43.727273 ===================================
541 08:13:43.727834 EX_ROW_EN[0] = 0x0
542 08:13:43.730202 EX_ROW_EN[1] = 0x0
543 08:13:43.730678 LP4Y_EN = 0x0
544 08:13:43.733246 WORK_FSP = 0x0
545 08:13:43.733801 WL = 0x2
546 08:13:43.736508 RL = 0x2
547 08:13:43.740464 BL = 0x2
548 08:13:43.741043 RPST = 0x0
549 08:13:43.743734 RD_PRE = 0x0
550 08:13:43.744162 WR_PRE = 0x1
551 08:13:43.746835 WR_PST = 0x0
552 08:13:43.747369 DBI_WR = 0x0
553 08:13:43.749971 DBI_RD = 0x0
554 08:13:43.750399 OTF = 0x1
555 08:13:43.753303 ===================================
556 08:13:43.757072 ===================================
557 08:13:43.760058 ANA top config
558 08:13:43.763496 ===================================
559 08:13:43.763930 DLL_ASYNC_EN = 0
560 08:13:43.766396 ALL_SLAVE_EN = 1
561 08:13:43.770345 NEW_RANK_MODE = 1
562 08:13:43.773136 DLL_IDLE_MODE = 1
563 08:13:43.773620 LP45_APHY_COMB_EN = 1
564 08:13:43.776812 TX_ODT_DIS = 1
565 08:13:43.780431 NEW_8X_MODE = 1
566 08:13:43.783635 ===================================
567 08:13:43.786320 ===================================
568 08:13:43.789825 data_rate = 1600
569 08:13:43.793059 CKR = 1
570 08:13:43.796007 DQ_P2S_RATIO = 8
571 08:13:43.799519 ===================================
572 08:13:43.800139 CA_P2S_RATIO = 8
573 08:13:43.803031 DQ_CA_OPEN = 0
574 08:13:43.806315 DQ_SEMI_OPEN = 0
575 08:13:43.809566 CA_SEMI_OPEN = 0
576 08:13:43.812658 CA_FULL_RATE = 0
577 08:13:43.816080 DQ_CKDIV4_EN = 1
578 08:13:43.816644 CA_CKDIV4_EN = 1
579 08:13:43.819378 CA_PREDIV_EN = 0
580 08:13:43.822678 PH8_DLY = 0
581 08:13:43.826571 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 08:13:43.829357 DQ_AAMCK_DIV = 4
583 08:13:43.832513 CA_AAMCK_DIV = 4
584 08:13:43.833104 CA_ADMCK_DIV = 4
585 08:13:43.836128 DQ_TRACK_CA_EN = 0
586 08:13:43.839152 CA_PICK = 800
587 08:13:43.842438 CA_MCKIO = 800
588 08:13:43.845892 MCKIO_SEMI = 0
589 08:13:43.849487 PLL_FREQ = 3068
590 08:13:43.853053 DQ_UI_PI_RATIO = 32
591 08:13:43.853620 CA_UI_PI_RATIO = 0
592 08:13:43.855987 ===================================
593 08:13:43.859818 ===================================
594 08:13:43.863637 memory_type:LPDDR4
595 08:13:43.864069 GP_NUM : 10
596 08:13:43.867253 SRAM_EN : 1
597 08:13:43.870780 MD32_EN : 0
598 08:13:43.871213 ===================================
599 08:13:43.874249 [ANA_INIT] >>>>>>>>>>>>>>
600 08:13:43.877789 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 08:13:43.881162 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 08:13:43.884893 ===================================
603 08:13:43.887803 data_rate = 1600,PCW = 0X7600
604 08:13:43.892031 ===================================
605 08:13:43.892126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 08:13:43.899277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 08:13:43.905790 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 08:13:43.908813 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 08:13:43.912364 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 08:13:43.915602 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 08:13:43.919310 [ANA_INIT] flow start
612 08:13:43.919396 [ANA_INIT] PLL >>>>>>>>
613 08:13:43.922462 [ANA_INIT] PLL <<<<<<<<
614 08:13:43.925752 [ANA_INIT] MIDPI >>>>>>>>
615 08:13:43.928719 [ANA_INIT] MIDPI <<<<<<<<
616 08:13:43.928804 [ANA_INIT] DLL >>>>>>>>
617 08:13:43.932539 [ANA_INIT] flow end
618 08:13:43.935117 ============ LP4 DIFF to SE enter ============
619 08:13:43.938601 ============ LP4 DIFF to SE exit ============
620 08:13:43.941916 [ANA_INIT] <<<<<<<<<<<<<
621 08:13:43.945046 [Flow] Enable top DCM control >>>>>
622 08:13:43.948746 [Flow] Enable top DCM control <<<<<
623 08:13:43.952113 Enable DLL master slave shuffle
624 08:13:43.958675 ==============================================================
625 08:13:43.958760 Gating Mode config
626 08:13:43.965556 ==============================================================
627 08:13:43.965642 Config description:
628 08:13:43.976163 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 08:13:43.983603 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 08:13:43.986940 SELPH_MODE 0: By rank 1: By Phase
631 08:13:43.994355 ==============================================================
632 08:13:43.994445 GAT_TRACK_EN = 1
633 08:13:43.998256 RX_GATING_MODE = 2
634 08:13:44.002103 RX_GATING_TRACK_MODE = 2
635 08:13:44.005506 SELPH_MODE = 1
636 08:13:44.008666 PICG_EARLY_EN = 1
637 08:13:44.012899 VALID_LAT_VALUE = 1
638 08:13:44.016586 ==============================================================
639 08:13:44.019945 Enter into Gating configuration >>>>
640 08:13:44.023850 Exit from Gating configuration <<<<
641 08:13:44.027076 Enter into DVFS_PRE_config >>>>>
642 08:13:44.038165 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 08:13:44.042120 Exit from DVFS_PRE_config <<<<<
644 08:13:44.042207 Enter into PICG configuration >>>>
645 08:13:44.045780 Exit from PICG configuration <<<<
646 08:13:44.049464 [RX_INPUT] configuration >>>>>
647 08:13:44.053613 [RX_INPUT] configuration <<<<<
648 08:13:44.057159 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 08:13:44.064441 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 08:13:44.068394 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 08:13:44.075774 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 08:13:44.082837 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 08:13:44.086030 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 08:13:44.092686 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 08:13:44.095954 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 08:13:44.099289 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 08:13:44.102309 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 08:13:44.109395 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 08:13:44.112623 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 08:13:44.116118 ===================================
661 08:13:44.119031 LPDDR4 DRAM CONFIGURATION
662 08:13:44.122760 ===================================
663 08:13:44.122846 EX_ROW_EN[0] = 0x0
664 08:13:44.125780 EX_ROW_EN[1] = 0x0
665 08:13:44.125865 LP4Y_EN = 0x0
666 08:13:44.129295 WORK_FSP = 0x0
667 08:13:44.129405 WL = 0x2
668 08:13:44.132844 RL = 0x2
669 08:13:44.132928 BL = 0x2
670 08:13:44.135609 RPST = 0x0
671 08:13:44.135695 RD_PRE = 0x0
672 08:13:44.138974 WR_PRE = 0x1
673 08:13:44.142240 WR_PST = 0x0
674 08:13:44.142325 DBI_WR = 0x0
675 08:13:44.145748 DBI_RD = 0x0
676 08:13:44.145833 OTF = 0x1
677 08:13:44.149389 ===================================
678 08:13:44.153013 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 08:13:44.156431 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 08:13:44.163520 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 08:13:44.163606 ===================================
682 08:13:44.166968 LPDDR4 DRAM CONFIGURATION
683 08:13:44.171198 ===================================
684 08:13:44.174865 EX_ROW_EN[0] = 0x10
685 08:13:44.174950 EX_ROW_EN[1] = 0x0
686 08:13:44.178141 LP4Y_EN = 0x0
687 08:13:44.178226 WORK_FSP = 0x0
688 08:13:44.182173 WL = 0x2
689 08:13:44.182257 RL = 0x2
690 08:13:44.182324 BL = 0x2
691 08:13:44.185641 RPST = 0x0
692 08:13:44.185726 RD_PRE = 0x0
693 08:13:44.189074 WR_PRE = 0x1
694 08:13:44.189159 WR_PST = 0x0
695 08:13:44.192950 DBI_WR = 0x0
696 08:13:44.193035 DBI_RD = 0x0
697 08:13:44.196371 OTF = 0x1
698 08:13:44.200650 ===================================
699 08:13:44.203818 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 08:13:44.209214 nWR fixed to 40
701 08:13:44.212244 [ModeRegInit_LP4] CH0 RK0
702 08:13:44.212328 [ModeRegInit_LP4] CH0 RK1
703 08:13:44.216302 [ModeRegInit_LP4] CH1 RK0
704 08:13:44.220065 [ModeRegInit_LP4] CH1 RK1
705 08:13:44.220150 match AC timing 13
706 08:13:44.224205 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 08:13:44.227626 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 08:13:44.234330 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 08:13:44.238328 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 08:13:44.241502 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 08:13:44.244784 [EMI DOE] emi_dcm 0
712 08:13:44.249233 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 08:13:44.249392 ==
714 08:13:44.252310 Dram Type= 6, Freq= 0, CH_0, rank 0
715 08:13:44.255943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 08:13:44.256034 ==
717 08:13:44.263215 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 08:13:44.266793 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 08:13:44.277083 [CA 0] Center 37 (7~68) winsize 62
720 08:13:44.280321 [CA 1] Center 37 (7~68) winsize 62
721 08:13:44.284146 [CA 2] Center 34 (4~65) winsize 62
722 08:13:44.287607 [CA 3] Center 34 (4~65) winsize 62
723 08:13:44.290658 [CA 4] Center 33 (3~64) winsize 62
724 08:13:44.295121 [CA 5] Center 33 (3~64) winsize 62
725 08:13:44.295556
726 08:13:44.298881 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 08:13:44.299450
728 08:13:44.302275 [CATrainingPosCal] consider 1 rank data
729 08:13:44.305484 u2DelayCellTimex100 = 270/100 ps
730 08:13:44.309024 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 08:13:44.312895 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
732 08:13:44.316701 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 08:13:44.320112 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 08:13:44.323492 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 08:13:44.327526 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 08:13:44.328096
737 08:13:44.330890 CA PerBit enable=1, Macro0, CA PI delay=33
738 08:13:44.331330
739 08:13:44.334963 [CBTSetCACLKResult] CA Dly = 33
740 08:13:44.335403 CS Dly: 7 (0~38)
741 08:13:44.335755 ==
742 08:13:44.338664 Dram Type= 6, Freq= 0, CH_0, rank 1
743 08:13:44.342271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 08:13:44.342711 ==
745 08:13:44.349508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 08:13:44.352866 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 08:13:44.363232 [CA 0] Center 37 (6~68) winsize 63
748 08:13:44.366636 [CA 1] Center 37 (7~68) winsize 62
749 08:13:44.370978 [CA 2] Center 34 (4~65) winsize 62
750 08:13:44.374848 [CA 3] Center 34 (4~65) winsize 62
751 08:13:44.378302 [CA 4] Center 33 (3~64) winsize 62
752 08:13:44.381776 [CA 5] Center 33 (2~64) winsize 63
753 08:13:44.382339
754 08:13:44.385192 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 08:13:44.385869
756 08:13:44.389130 [CATrainingPosCal] consider 2 rank data
757 08:13:44.389656 u2DelayCellTimex100 = 270/100 ps
758 08:13:44.392525 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 08:13:44.396106 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 08:13:44.399757 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 08:13:44.403536 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 08:13:44.407388 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 08:13:44.411004 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 08:13:44.411659
765 08:13:44.415001 CA PerBit enable=1, Macro0, CA PI delay=33
766 08:13:44.418561
767 08:13:44.419190 [CBTSetCACLKResult] CA Dly = 33
768 08:13:44.421787 CS Dly: 7 (0~39)
769 08:13:44.422281
770 08:13:44.425548 ----->DramcWriteLeveling(PI) begin...
771 08:13:44.426163 ==
772 08:13:44.429632 Dram Type= 6, Freq= 0, CH_0, rank 0
773 08:13:44.433135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 08:13:44.433813 ==
775 08:13:44.436678 Write leveling (Byte 0): 33 => 33
776 08:13:44.440307 Write leveling (Byte 1): 33 => 33
777 08:13:44.440911 DramcWriteLeveling(PI) end<-----
778 08:13:44.441484
779 08:13:44.441830 ==
780 08:13:44.443919 Dram Type= 6, Freq= 0, CH_0, rank 0
781 08:13:44.448232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 08:13:44.451849 ==
783 08:13:44.452634 [Gating] SW mode calibration
784 08:13:44.458726 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 08:13:44.466088 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 08:13:44.469814 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 08:13:44.473951 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 08:13:44.477525 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 08:13:44.481004 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 08:13:44.484381 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 08:13:44.492210 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 08:13:44.495741 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 08:13:44.499373 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 08:13:44.503331 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 08:13:44.507246 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 08:13:44.510589 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 08:13:44.518654 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 08:13:44.521962 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 08:13:44.525628 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 08:13:44.529595 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 08:13:44.533398 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 08:13:44.540190 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 08:13:44.543650 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 08:13:44.548126 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 08:13:44.551719 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
806 08:13:44.555015 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 08:13:44.562328 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 08:13:44.566277 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 08:13:44.569911 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 08:13:44.573578 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 08:13:44.577269 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 08:13:44.585107 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
813 08:13:44.588333 0 9 12 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
814 08:13:44.592237 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 08:13:44.595800 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 08:13:44.599559 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 08:13:44.606712 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 08:13:44.610876 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 08:13:44.614149 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
820 08:13:44.618639 0 10 8 | B1->B0 | 3333 2d2d | 0 0 | (0 0) (0 0)
821 08:13:44.621913 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
822 08:13:44.625785 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 08:13:44.632920 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 08:13:44.636148 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 08:13:44.640486 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 08:13:44.644309 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 08:13:44.647539 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 08:13:44.655209 0 11 8 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
829 08:13:44.657871 0 11 12 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
830 08:13:44.661723 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 08:13:44.665718 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 08:13:44.669505 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 08:13:44.676596 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 08:13:44.680235 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 08:13:44.683985 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 08:13:44.687763 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 08:13:44.694795 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
838 08:13:44.698249 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 08:13:44.702289 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 08:13:44.705805 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 08:13:44.709706 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 08:13:44.713115 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 08:13:44.720257 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 08:13:44.723954 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 08:13:44.727995 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 08:13:44.733726 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 08:13:44.737220 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 08:13:44.740536 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 08:13:44.746669 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 08:13:44.750149 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 08:13:44.753716 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 08:13:44.759889 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
853 08:13:44.763590 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
854 08:13:44.766358 Total UI for P1: 0, mck2ui 16
855 08:13:44.769766 best dqsien dly found for B0: ( 0, 14, 6)
856 08:13:44.773411 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 08:13:44.776707 Total UI for P1: 0, mck2ui 16
858 08:13:44.780267 best dqsien dly found for B1: ( 0, 14, 12)
859 08:13:44.783154 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
860 08:13:44.786802 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
861 08:13:44.787394
862 08:13:44.789662 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
863 08:13:44.796683 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
864 08:13:44.797268 [Gating] SW calibration Done
865 08:13:44.799879 ==
866 08:13:44.800459 Dram Type= 6, Freq= 0, CH_0, rank 0
867 08:13:44.806616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 08:13:44.807206 ==
869 08:13:44.807615 RX Vref Scan: 0
870 08:13:44.808144
871 08:13:44.809376 RX Vref 0 -> 0, step: 1
872 08:13:44.809861
873 08:13:44.813231 RX Delay -130 -> 252, step: 16
874 08:13:44.816725 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 08:13:44.819681 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 08:13:44.823273 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
877 08:13:44.829756 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 08:13:44.833049 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
879 08:13:44.836387 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
880 08:13:44.839463 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
881 08:13:44.843179 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
882 08:13:44.849496 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
883 08:13:44.852900 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
884 08:13:44.856180 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
885 08:13:44.859788 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 08:13:44.862536 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
887 08:13:44.869956 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
888 08:13:44.872554 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
889 08:13:44.876337 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
890 08:13:44.876917 ==
891 08:13:44.879486 Dram Type= 6, Freq= 0, CH_0, rank 0
892 08:13:44.882926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 08:13:44.886046 ==
894 08:13:44.886627 DQS Delay:
895 08:13:44.887004 DQS0 = 0, DQS1 = 0
896 08:13:44.889551 DQM Delay:
897 08:13:44.890131 DQM0 = 84, DQM1 = 71
898 08:13:44.892238 DQ Delay:
899 08:13:44.896246 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
900 08:13:44.896833 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
901 08:13:44.899858 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
902 08:13:44.902966 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
903 08:13:44.903447
904 08:13:44.903825
905 08:13:44.906485 ==
906 08:13:44.906986 Dram Type= 6, Freq= 0, CH_0, rank 0
907 08:13:44.913819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 08:13:44.914455 ==
909 08:13:44.914871
910 08:13:44.915224
911 08:13:44.915563 TX Vref Scan disable
912 08:13:44.916679 == TX Byte 0 ==
913 08:13:44.920328 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
914 08:13:44.924044 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
915 08:13:44.927907 == TX Byte 1 ==
916 08:13:44.931599 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
917 08:13:44.934980 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
918 08:13:44.935469 ==
919 08:13:44.937906 Dram Type= 6, Freq= 0, CH_0, rank 0
920 08:13:44.941472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 08:13:44.944759 ==
922 08:13:44.956116 TX Vref=22, minBit 12, minWin=26, winSum=438
923 08:13:44.959213 TX Vref=24, minBit 8, minWin=27, winSum=445
924 08:13:44.962269 TX Vref=26, minBit 8, minWin=27, winSum=445
925 08:13:44.965403 TX Vref=28, minBit 10, minWin=27, winSum=450
926 08:13:44.968623 TX Vref=30, minBit 0, minWin=28, winSum=451
927 08:13:44.975946 TX Vref=32, minBit 8, minWin=27, winSum=447
928 08:13:44.978513 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 30
929 08:13:44.978999
930 08:13:44.982172 Final TX Range 1 Vref 30
931 08:13:44.982675
932 08:13:44.983055 ==
933 08:13:44.985439 Dram Type= 6, Freq= 0, CH_0, rank 0
934 08:13:44.988921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 08:13:44.991781 ==
936 08:13:44.992257
937 08:13:44.992634
938 08:13:44.992983 TX Vref Scan disable
939 08:13:44.996269 == TX Byte 0 ==
940 08:13:44.999348 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
941 08:13:45.005856 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
942 08:13:45.006438 == TX Byte 1 ==
943 08:13:45.009608 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
944 08:13:45.015818 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
945 08:13:45.016384
946 08:13:45.016763 [DATLAT]
947 08:13:45.017117 Freq=800, CH0 RK0
948 08:13:45.017492
949 08:13:45.019281 DATLAT Default: 0xa
950 08:13:45.019751 0, 0xFFFF, sum = 0
951 08:13:45.022112 1, 0xFFFF, sum = 0
952 08:13:45.025690 2, 0xFFFF, sum = 0
953 08:13:45.026174 3, 0xFFFF, sum = 0
954 08:13:45.029317 4, 0xFFFF, sum = 0
955 08:13:45.030004 5, 0xFFFF, sum = 0
956 08:13:45.032155 6, 0xFFFF, sum = 0
957 08:13:45.032650 7, 0xFFFF, sum = 0
958 08:13:45.035727 8, 0xFFFF, sum = 0
959 08:13:45.036209 9, 0x0, sum = 1
960 08:13:45.038704 10, 0x0, sum = 2
961 08:13:45.039186 11, 0x0, sum = 3
962 08:13:45.042783 12, 0x0, sum = 4
963 08:13:45.043371 best_step = 10
964 08:13:45.043750
965 08:13:45.044100 ==
966 08:13:45.045314 Dram Type= 6, Freq= 0, CH_0, rank 0
967 08:13:45.048832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 08:13:45.049312 ==
969 08:13:45.051821 RX Vref Scan: 1
970 08:13:45.052295
971 08:13:45.055467 Set Vref Range= 32 -> 127
972 08:13:45.055942
973 08:13:45.056321 RX Vref 32 -> 127, step: 1
974 08:13:45.056667
975 08:13:45.058907 RX Delay -111 -> 252, step: 8
976 08:13:45.059482
977 08:13:45.062175 Set Vref, RX VrefLevel [Byte0]: 32
978 08:13:45.065118 [Byte1]: 32
979 08:13:45.068639
980 08:13:45.069115 Set Vref, RX VrefLevel [Byte0]: 33
981 08:13:45.072081 [Byte1]: 33
982 08:13:45.076283
983 08:13:45.076864 Set Vref, RX VrefLevel [Byte0]: 34
984 08:13:45.079760 [Byte1]: 34
985 08:13:45.084107
986 08:13:45.084603 Set Vref, RX VrefLevel [Byte0]: 35
987 08:13:45.087368 [Byte1]: 35
988 08:13:45.091778
989 08:13:45.092337 Set Vref, RX VrefLevel [Byte0]: 36
990 08:13:45.094691 [Byte1]: 36
991 08:13:45.099599
992 08:13:45.100177 Set Vref, RX VrefLevel [Byte0]: 37
993 08:13:45.102465 [Byte1]: 37
994 08:13:45.106839
995 08:13:45.107433 Set Vref, RX VrefLevel [Byte0]: 38
996 08:13:45.110316 [Byte1]: 38
997 08:13:45.114835
998 08:13:45.115428 Set Vref, RX VrefLevel [Byte0]: 39
999 08:13:45.118544 [Byte1]: 39
1000 08:13:45.122133
1001 08:13:45.122715 Set Vref, RX VrefLevel [Byte0]: 40
1002 08:13:45.125869 [Byte1]: 40
1003 08:13:45.130165
1004 08:13:45.130751 Set Vref, RX VrefLevel [Byte0]: 41
1005 08:13:45.133461 [Byte1]: 41
1006 08:13:45.137255
1007 08:13:45.137919 Set Vref, RX VrefLevel [Byte0]: 42
1008 08:13:45.140771 [Byte1]: 42
1009 08:13:45.145287
1010 08:13:45.145915 Set Vref, RX VrefLevel [Byte0]: 43
1011 08:13:45.148529 [Byte1]: 43
1012 08:13:45.153104
1013 08:13:45.153740 Set Vref, RX VrefLevel [Byte0]: 44
1014 08:13:45.155995 [Byte1]: 44
1015 08:13:45.160937
1016 08:13:45.161567 Set Vref, RX VrefLevel [Byte0]: 45
1017 08:13:45.164019 [Byte1]: 45
1018 08:13:45.167808
1019 08:13:45.168283 Set Vref, RX VrefLevel [Byte0]: 46
1020 08:13:45.171667 [Byte1]: 46
1021 08:13:45.176054
1022 08:13:45.176627 Set Vref, RX VrefLevel [Byte0]: 47
1023 08:13:45.178958 [Byte1]: 47
1024 08:13:45.183533
1025 08:13:45.184158 Set Vref, RX VrefLevel [Byte0]: 48
1026 08:13:45.189891 [Byte1]: 48
1027 08:13:45.190463
1028 08:13:45.193128 Set Vref, RX VrefLevel [Byte0]: 49
1029 08:13:45.196157 [Byte1]: 49
1030 08:13:45.196632
1031 08:13:45.199944 Set Vref, RX VrefLevel [Byte0]: 50
1032 08:13:45.203329 [Byte1]: 50
1033 08:13:45.206545
1034 08:13:45.207021 Set Vref, RX VrefLevel [Byte0]: 51
1035 08:13:45.209326 [Byte1]: 51
1036 08:13:45.214054
1037 08:13:45.214524 Set Vref, RX VrefLevel [Byte0]: 52
1038 08:13:45.216987 [Byte1]: 52
1039 08:13:45.221682
1040 08:13:45.222111 Set Vref, RX VrefLevel [Byte0]: 53
1041 08:13:45.224583 [Byte1]: 53
1042 08:13:45.228941
1043 08:13:45.229601 Set Vref, RX VrefLevel [Byte0]: 54
1044 08:13:45.232178 [Byte1]: 54
1045 08:13:45.236762
1046 08:13:45.237191 Set Vref, RX VrefLevel [Byte0]: 55
1047 08:13:45.240046 [Byte1]: 55
1048 08:13:45.244046
1049 08:13:45.244541 Set Vref, RX VrefLevel [Byte0]: 56
1050 08:13:45.247239 [Byte1]: 56
1051 08:13:45.252020
1052 08:13:45.255505 Set Vref, RX VrefLevel [Byte0]: 57
1053 08:13:45.258413 [Byte1]: 57
1054 08:13:45.258850
1055 08:13:45.261992 Set Vref, RX VrefLevel [Byte0]: 58
1056 08:13:45.264965 [Byte1]: 58
1057 08:13:45.265561
1058 08:13:45.268552 Set Vref, RX VrefLevel [Byte0]: 59
1059 08:13:45.271702 [Byte1]: 59
1060 08:13:45.275032
1061 08:13:45.275450 Set Vref, RX VrefLevel [Byte0]: 60
1062 08:13:45.278060 [Byte1]: 60
1063 08:13:45.282283
1064 08:13:45.282729 Set Vref, RX VrefLevel [Byte0]: 61
1065 08:13:45.285752 [Byte1]: 61
1066 08:13:45.290088
1067 08:13:45.290416 Set Vref, RX VrefLevel [Byte0]: 62
1068 08:13:45.293399 [Byte1]: 62
1069 08:13:45.297810
1070 08:13:45.298069 Set Vref, RX VrefLevel [Byte0]: 63
1071 08:13:45.301047 [Byte1]: 63
1072 08:13:45.305151
1073 08:13:45.305444 Set Vref, RX VrefLevel [Byte0]: 64
1074 08:13:45.308828 [Byte1]: 64
1075 08:13:45.313037
1076 08:13:45.313270 Set Vref, RX VrefLevel [Byte0]: 65
1077 08:13:45.316510 [Byte1]: 65
1078 08:13:45.320539
1079 08:13:45.320765 Set Vref, RX VrefLevel [Byte0]: 66
1080 08:13:45.324211 [Byte1]: 66
1081 08:13:45.328450
1082 08:13:45.328677 Set Vref, RX VrefLevel [Byte0]: 67
1083 08:13:45.331637 [Byte1]: 67
1084 08:13:45.335776
1085 08:13:45.336053 Set Vref, RX VrefLevel [Byte0]: 68
1086 08:13:45.339297 [Byte1]: 68
1087 08:13:45.343577
1088 08:13:45.343937 Set Vref, RX VrefLevel [Byte0]: 69
1089 08:13:45.347070 [Byte1]: 69
1090 08:13:45.351758
1091 08:13:45.352198 Set Vref, RX VrefLevel [Byte0]: 70
1092 08:13:45.354919 [Byte1]: 70
1093 08:13:45.358741
1094 08:13:45.359162 Set Vref, RX VrefLevel [Byte0]: 71
1095 08:13:45.362275 [Byte1]: 71
1096 08:13:45.366878
1097 08:13:45.367302 Set Vref, RX VrefLevel [Byte0]: 72
1098 08:13:45.370291 [Byte1]: 72
1099 08:13:45.374484
1100 08:13:45.374908 Set Vref, RX VrefLevel [Byte0]: 73
1101 08:13:45.377599 [Byte1]: 73
1102 08:13:45.382013
1103 08:13:45.382433 Set Vref, RX VrefLevel [Byte0]: 74
1104 08:13:45.385443 [Byte1]: 74
1105 08:13:45.389672
1106 08:13:45.390235 Set Vref, RX VrefLevel [Byte0]: 75
1107 08:13:45.393171 [Byte1]: 75
1108 08:13:45.397211
1109 08:13:45.397686 Set Vref, RX VrefLevel [Byte0]: 76
1110 08:13:45.400700 [Byte1]: 76
1111 08:13:45.404982
1112 08:13:45.405437 Set Vref, RX VrefLevel [Byte0]: 77
1113 08:13:45.408530 [Byte1]: 77
1114 08:13:45.412422
1115 08:13:45.412846 Set Vref, RX VrefLevel [Byte0]: 78
1116 08:13:45.416217 [Byte1]: 78
1117 08:13:45.420268
1118 08:13:45.420690 Set Vref, RX VrefLevel [Byte0]: 79
1119 08:13:45.423692 [Byte1]: 79
1120 08:13:45.427772
1121 08:13:45.428194 Set Vref, RX VrefLevel [Byte0]: 80
1122 08:13:45.430894 [Byte1]: 80
1123 08:13:45.435962
1124 08:13:45.436385 Set Vref, RX VrefLevel [Byte0]: 81
1125 08:13:45.439066 [Byte1]: 81
1126 08:13:45.443242
1127 08:13:45.443663 Set Vref, RX VrefLevel [Byte0]: 82
1128 08:13:45.446228 [Byte1]: 82
1129 08:13:45.451146
1130 08:13:45.451568 Final RX Vref Byte 0 = 62 to rank0
1131 08:13:45.454008 Final RX Vref Byte 1 = 51 to rank0
1132 08:13:45.457713 Final RX Vref Byte 0 = 62 to rank1
1133 08:13:45.460787 Final RX Vref Byte 1 = 51 to rank1==
1134 08:13:45.463949 Dram Type= 6, Freq= 0, CH_0, rank 0
1135 08:13:45.471141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 08:13:45.471703 ==
1137 08:13:45.472280 DQS Delay:
1138 08:13:45.474021 DQS0 = 0, DQS1 = 0
1139 08:13:45.474480 DQM Delay:
1140 08:13:45.475000 DQM0 = 87, DQM1 = 76
1141 08:13:45.477655 DQ Delay:
1142 08:13:45.480866 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1143 08:13:45.481569 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =100
1144 08:13:45.484198 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1145 08:13:45.488061 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1146 08:13:45.488588
1147 08:13:45.491609
1148 08:13:45.498895 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c1e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 394 ps
1149 08:13:45.499457 CH0 RK0: MR19=606, MR18=3C1E
1150 08:13:45.505171 CH0_RK0: MR19=0x606, MR18=0x3C1E, DQSOSC=394, MR23=63, INC=95, DEC=63
1151 08:13:45.505685
1152 08:13:45.549312 ----->DramcWriteLeveling(PI) begin...
1153 08:13:45.549941 ==
1154 08:13:45.550439 Dram Type= 6, Freq= 0, CH_0, rank 1
1155 08:13:45.550906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1156 08:13:45.551364 ==
1157 08:13:45.551809 Write leveling (Byte 0): 32 => 32
1158 08:13:45.552250 Write leveling (Byte 1): 30 => 30
1159 08:13:45.552829 DramcWriteLeveling(PI) end<-----
1160 08:13:45.553404
1161 08:13:45.553847 ==
1162 08:13:45.554663 Dram Type= 6, Freq= 0, CH_0, rank 1
1163 08:13:45.555256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1164 08:13:45.555813 ==
1165 08:13:45.556177 [Gating] SW mode calibration
1166 08:13:45.556514 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1167 08:13:45.556845 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1168 08:13:45.561965 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1169 08:13:45.562621 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1170 08:13:45.565152 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1171 08:13:45.568071 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1172 08:13:45.571712 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 08:13:45.574641 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 08:13:45.581701 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 08:13:45.584695 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 08:13:45.588419 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 08:13:45.594651 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 08:13:45.597987 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 08:13:45.601035 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 08:13:45.607752 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 08:13:45.611039 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 08:13:45.614676 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 08:13:45.621247 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 08:13:45.624592 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 08:13:45.627948 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1186 08:13:45.634674 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1187 08:13:45.637743 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 08:13:45.641103 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 08:13:45.647406 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 08:13:45.651262 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 08:13:45.654237 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 08:13:45.661017 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 08:13:45.664608 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1194 08:13:45.667179 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
1195 08:13:45.673901 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1196 08:13:45.677490 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 08:13:45.680629 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 08:13:45.687390 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1199 08:13:45.690769 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 08:13:45.693850 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1201 08:13:45.700261 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1202 08:13:45.704294 0 10 8 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (1 0)
1203 08:13:45.707411 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 08:13:45.713691 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 08:13:45.717060 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 08:13:45.720554 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 08:13:45.727058 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 08:13:45.730161 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 08:13:45.733513 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1210 08:13:45.740156 0 11 8 | B1->B0 | 2d2d 3939 | 0 0 | (0 0) (0 0)
1211 08:13:45.743216 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1212 08:13:45.747085 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 08:13:45.753657 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 08:13:45.756686 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 08:13:45.760199 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 08:13:45.766930 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 08:13:45.769915 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 08:13:45.772878 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1219 08:13:45.779852 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 08:13:45.783219 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 08:13:45.786680 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 08:13:45.792869 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 08:13:45.796857 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 08:13:45.799774 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 08:13:45.806179 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 08:13:45.809235 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 08:13:45.813014 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 08:13:45.819949 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 08:13:45.822867 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 08:13:45.826382 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 08:13:45.833137 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 08:13:45.835901 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 08:13:45.839758 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 08:13:45.845969 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1235 08:13:45.849491 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1236 08:13:45.852620 Total UI for P1: 0, mck2ui 16
1237 08:13:45.855583 best dqsien dly found for B0: ( 0, 14, 8)
1238 08:13:45.859069 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 08:13:45.862206 Total UI for P1: 0, mck2ui 16
1240 08:13:45.865793 best dqsien dly found for B1: ( 0, 14, 10)
1241 08:13:45.869409 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1242 08:13:45.872604 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1243 08:13:45.873114
1244 08:13:45.875736 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1245 08:13:45.882232 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1246 08:13:45.882805 [Gating] SW calibration Done
1247 08:13:45.883181 ==
1248 08:13:45.885548 Dram Type= 6, Freq= 0, CH_0, rank 1
1249 08:13:45.892196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1250 08:13:45.892757 ==
1251 08:13:45.893133 RX Vref Scan: 0
1252 08:13:45.893574
1253 08:13:45.895915 RX Vref 0 -> 0, step: 1
1254 08:13:45.896482
1255 08:13:45.898668 RX Delay -130 -> 252, step: 16
1256 08:13:45.902455 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1257 08:13:45.905178 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1258 08:13:45.908368 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1259 08:13:45.915814 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1260 08:13:45.918494 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1261 08:13:45.922278 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1262 08:13:45.925216 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1263 08:13:45.928616 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1264 08:13:45.935216 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1265 08:13:45.938961 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1266 08:13:45.941559 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1267 08:13:45.945091 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1268 08:13:45.951856 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1269 08:13:45.955453 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1270 08:13:45.958533 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1271 08:13:45.961730 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1272 08:13:45.962198 ==
1273 08:13:45.964704 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 08:13:45.971376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 08:13:45.971916 ==
1276 08:13:45.972298 DQS Delay:
1277 08:13:45.972648 DQS0 = 0, DQS1 = 0
1278 08:13:45.974470 DQM Delay:
1279 08:13:45.974935 DQM0 = 83, DQM1 = 78
1280 08:13:45.977863 DQ Delay:
1281 08:13:45.981407 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1282 08:13:45.985079 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1283 08:13:45.987992 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1284 08:13:45.991104 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1285 08:13:45.991572
1286 08:13:45.991941
1287 08:13:45.992284 ==
1288 08:13:45.994757 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 08:13:45.997691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 08:13:45.998161 ==
1291 08:13:45.998565
1292 08:13:45.998919
1293 08:13:46.000745 TX Vref Scan disable
1294 08:13:46.001206 == TX Byte 0 ==
1295 08:13:46.007752 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1296 08:13:46.010639 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1297 08:13:46.011253 == TX Byte 1 ==
1298 08:13:46.017659 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1299 08:13:46.020939 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1300 08:13:46.021391 ==
1301 08:13:46.023872 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 08:13:46.027156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 08:13:46.027463 ==
1304 08:13:46.041874 TX Vref=22, minBit 3, minWin=27, winSum=445
1305 08:13:46.045369 TX Vref=24, minBit 5, minWin=27, winSum=446
1306 08:13:46.048437 TX Vref=26, minBit 2, minWin=27, winSum=448
1307 08:13:46.052156 TX Vref=28, minBit 9, minWin=27, winSum=450
1308 08:13:46.055268 TX Vref=30, minBit 9, minWin=27, winSum=448
1309 08:13:46.062147 TX Vref=32, minBit 9, minWin=27, winSum=448
1310 08:13:46.064953 [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 28
1311 08:13:46.065453
1312 08:13:46.068512 Final TX Range 1 Vref 28
1313 08:13:46.068976
1314 08:13:46.069382 ==
1315 08:13:46.071864 Dram Type= 6, Freq= 0, CH_0, rank 1
1316 08:13:46.075106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1317 08:13:46.075542 ==
1318 08:13:46.078588
1319 08:13:46.079148
1320 08:13:46.079517 TX Vref Scan disable
1321 08:13:46.081907 == TX Byte 0 ==
1322 08:13:46.085297 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1323 08:13:46.088874 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1324 08:13:46.091773 == TX Byte 1 ==
1325 08:13:46.094892 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1326 08:13:46.102142 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1327 08:13:46.102697
1328 08:13:46.103066 [DATLAT]
1329 08:13:46.103409 Freq=800, CH0 RK1
1330 08:13:46.103742
1331 08:13:46.104651 DATLAT Default: 0xa
1332 08:13:46.105111 0, 0xFFFF, sum = 0
1333 08:13:46.108163 1, 0xFFFF, sum = 0
1334 08:13:46.111571 2, 0xFFFF, sum = 0
1335 08:13:46.112134 3, 0xFFFF, sum = 0
1336 08:13:46.114884 4, 0xFFFF, sum = 0
1337 08:13:46.115450 5, 0xFFFF, sum = 0
1338 08:13:46.118484 6, 0xFFFF, sum = 0
1339 08:13:46.119132 7, 0xFFFF, sum = 0
1340 08:13:46.121946 8, 0xFFFF, sum = 0
1341 08:13:46.122510 9, 0x0, sum = 1
1342 08:13:46.125136 10, 0x0, sum = 2
1343 08:13:46.125838 11, 0x0, sum = 3
1344 08:13:46.126227 12, 0x0, sum = 4
1345 08:13:46.128648 best_step = 10
1346 08:13:46.129201
1347 08:13:46.129619 ==
1348 08:13:46.131754 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 08:13:46.134493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 08:13:46.134959 ==
1351 08:13:46.137943 RX Vref Scan: 0
1352 08:13:46.138403
1353 08:13:46.138769 RX Vref 0 -> 0, step: 1
1354 08:13:46.142334
1355 08:13:46.142922 RX Delay -95 -> 252, step: 8
1356 08:13:46.149122 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1357 08:13:46.152702 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1358 08:13:46.156375 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1359 08:13:46.160533 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1360 08:13:46.164119 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1361 08:13:46.167114 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1362 08:13:46.171399 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1363 08:13:46.175094 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1364 08:13:46.178841 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1365 08:13:46.182104 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1366 08:13:46.188730 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1367 08:13:46.192282 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1368 08:13:46.195505 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1369 08:13:46.198515 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1370 08:13:46.201998 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1371 08:13:46.208579 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1372 08:13:46.208997 ==
1373 08:13:46.211932 Dram Type= 6, Freq= 0, CH_0, rank 1
1374 08:13:46.215225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1375 08:13:46.215752 ==
1376 08:13:46.216093 DQS Delay:
1377 08:13:46.218281 DQS0 = 0, DQS1 = 0
1378 08:13:46.218699 DQM Delay:
1379 08:13:46.221707 DQM0 = 84, DQM1 = 76
1380 08:13:46.222220 DQ Delay:
1381 08:13:46.224772 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =80
1382 08:13:46.228139 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1383 08:13:46.231817 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =68
1384 08:13:46.234664 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1385 08:13:46.235182
1386 08:13:46.235515
1387 08:13:46.244476 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b02, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
1388 08:13:46.244984 CH0 RK1: MR19=606, MR18=3B02
1389 08:13:46.250938 CH0_RK1: MR19=0x606, MR18=0x3B02, DQSOSC=394, MR23=63, INC=95, DEC=63
1390 08:13:46.254631 [RxdqsGatingPostProcess] freq 800
1391 08:13:46.261137 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1392 08:13:46.264336 Pre-setting of DQS Precalculation
1393 08:13:46.268070 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1394 08:13:46.268597 ==
1395 08:13:46.271258 Dram Type= 6, Freq= 0, CH_1, rank 0
1396 08:13:46.277473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 08:13:46.277968 ==
1398 08:13:46.281213 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1399 08:13:46.287886 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1400 08:13:46.297077 [CA 0] Center 36 (6~67) winsize 62
1401 08:13:46.299764 [CA 1] Center 36 (6~67) winsize 62
1402 08:13:46.303172 [CA 2] Center 34 (4~65) winsize 62
1403 08:13:46.306610 [CA 3] Center 34 (4~65) winsize 62
1404 08:13:46.309744 [CA 4] Center 34 (4~65) winsize 62
1405 08:13:46.313039 [CA 5] Center 34 (3~65) winsize 63
1406 08:13:46.313506
1407 08:13:46.316937 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1408 08:13:46.317555
1409 08:13:46.320118 [CATrainingPosCal] consider 1 rank data
1410 08:13:46.323437 u2DelayCellTimex100 = 270/100 ps
1411 08:13:46.326315 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1412 08:13:46.333061 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1413 08:13:46.336459 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1414 08:13:46.339487 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1415 08:13:46.343084 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1416 08:13:46.346137 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1417 08:13:46.346576
1418 08:13:46.349522 CA PerBit enable=1, Macro0, CA PI delay=34
1419 08:13:46.349951
1420 08:13:46.353205 [CBTSetCACLKResult] CA Dly = 34
1421 08:13:46.353762 CS Dly: 4 (0~35)
1422 08:13:46.355936 ==
1423 08:13:46.359454 Dram Type= 6, Freq= 0, CH_1, rank 1
1424 08:13:46.362991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 08:13:46.363552 ==
1426 08:13:46.369565 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1427 08:13:46.372870 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1428 08:13:46.382811 [CA 0] Center 36 (6~67) winsize 62
1429 08:13:46.386809 [CA 1] Center 36 (6~67) winsize 62
1430 08:13:46.389223 [CA 2] Center 34 (4~65) winsize 62
1431 08:13:46.392519 [CA 3] Center 34 (3~65) winsize 63
1432 08:13:46.396181 [CA 4] Center 34 (4~65) winsize 62
1433 08:13:46.399351 [CA 5] Center 34 (3~65) winsize 63
1434 08:13:46.399818
1435 08:13:46.402844 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1436 08:13:46.403314
1437 08:13:46.406599 [CATrainingPosCal] consider 2 rank data
1438 08:13:46.409473 u2DelayCellTimex100 = 270/100 ps
1439 08:13:46.412819 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1440 08:13:46.419100 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1441 08:13:46.423181 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1442 08:13:46.425990 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1443 08:13:46.429169 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1444 08:13:46.432755 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1445 08:13:46.433180
1446 08:13:46.436015 CA PerBit enable=1, Macro0, CA PI delay=34
1447 08:13:46.436443
1448 08:13:46.438809 [CBTSetCACLKResult] CA Dly = 34
1449 08:13:46.439247 CS Dly: 5 (0~38)
1450 08:13:46.442506
1451 08:13:46.445917 ----->DramcWriteLeveling(PI) begin...
1452 08:13:46.446353 ==
1453 08:13:46.449142 Dram Type= 6, Freq= 0, CH_1, rank 0
1454 08:13:46.452795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1455 08:13:46.453531 ==
1456 08:13:46.455546 Write leveling (Byte 0): 28 => 28
1457 08:13:46.459008 Write leveling (Byte 1): 28 => 28
1458 08:13:46.462699 DramcWriteLeveling(PI) end<-----
1459 08:13:46.463187
1460 08:13:46.463814 ==
1461 08:13:46.465545 Dram Type= 6, Freq= 0, CH_1, rank 0
1462 08:13:46.469303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1463 08:13:46.469776 ==
1464 08:13:46.472190 [Gating] SW mode calibration
1465 08:13:46.479087 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1466 08:13:46.485447 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1467 08:13:46.489428 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1468 08:13:46.492112 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1469 08:13:46.499411 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1470 08:13:46.502106 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 08:13:46.505520 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 08:13:46.512765 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 08:13:46.515418 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 08:13:46.518977 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 08:13:46.521857 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 08:13:46.528816 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 08:13:46.531961 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 08:13:46.535679 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 08:13:46.541886 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 08:13:46.545614 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 08:13:46.548462 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 08:13:46.555187 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 08:13:46.558781 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1484 08:13:46.562044 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1485 08:13:46.568583 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1486 08:13:46.571995 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 08:13:46.574986 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 08:13:46.581612 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 08:13:46.585019 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 08:13:46.588329 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 08:13:46.594586 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 08:13:46.598219 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 08:13:46.601574 0 9 8 | B1->B0 | 2c2c 3232 | 0 0 | (1 1) (1 1)
1494 08:13:46.608003 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 08:13:46.611058 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 08:13:46.614550 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 08:13:46.621422 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1498 08:13:46.624697 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1499 08:13:46.628161 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1500 08:13:46.634922 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
1501 08:13:46.637931 0 10 8 | B1->B0 | 2525 2a2a | 0 0 | (1 0) (1 1)
1502 08:13:46.641283 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 08:13:46.647597 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 08:13:46.651076 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 08:13:46.654080 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 08:13:46.661147 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 08:13:46.664284 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 08:13:46.667431 0 11 4 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
1509 08:13:46.673871 0 11 8 | B1->B0 | 3838 3f3f | 0 1 | (0 0) (0 0)
1510 08:13:46.677839 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 08:13:46.680568 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 08:13:46.686969 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 08:13:46.690737 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 08:13:46.693493 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 08:13:46.700017 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1516 08:13:46.703408 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1517 08:13:46.707009 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 08:13:46.713322 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 08:13:46.716805 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 08:13:46.719933 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 08:13:46.726946 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 08:13:46.731300 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 08:13:46.733922 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 08:13:46.740610 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 08:13:46.743814 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 08:13:46.747227 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 08:13:46.753728 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 08:13:46.756911 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 08:13:46.759998 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 08:13:46.767054 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 08:13:46.769851 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 08:13:46.773485 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1533 08:13:46.777151 Total UI for P1: 0, mck2ui 16
1534 08:13:46.780808 best dqsien dly found for B0: ( 0, 14, 2)
1535 08:13:46.783861 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1536 08:13:46.790297 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 08:13:46.793514 Total UI for P1: 0, mck2ui 16
1538 08:13:46.796787 best dqsien dly found for B1: ( 0, 14, 6)
1539 08:13:46.800260 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1540 08:13:46.803187 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1541 08:13:46.803749
1542 08:13:46.806691 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1543 08:13:46.810251 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1544 08:13:46.813300 [Gating] SW calibration Done
1545 08:13:46.813903 ==
1546 08:13:46.817189 Dram Type= 6, Freq= 0, CH_1, rank 0
1547 08:13:46.820042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1548 08:13:46.820608 ==
1549 08:13:46.823582 RX Vref Scan: 0
1550 08:13:46.824144
1551 08:13:46.826259 RX Vref 0 -> 0, step: 1
1552 08:13:46.826728
1553 08:13:46.827152 RX Delay -130 -> 252, step: 16
1554 08:13:46.833856 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1555 08:13:46.836251 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1556 08:13:46.840284 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1557 08:13:46.842872 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1558 08:13:46.846352 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1559 08:13:46.852839 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1560 08:13:46.856237 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1561 08:13:46.859619 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1562 08:13:46.862965 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1563 08:13:46.869434 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1564 08:13:46.872681 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1565 08:13:46.876231 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1566 08:13:46.879130 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1567 08:13:46.882316 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1568 08:13:46.889572 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1569 08:13:46.892958 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1570 08:13:46.893567 ==
1571 08:13:46.895983 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 08:13:46.899230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 08:13:46.899803 ==
1574 08:13:46.902558 DQS Delay:
1575 08:13:46.903024 DQS0 = 0, DQS1 = 0
1576 08:13:46.903396 DQM Delay:
1577 08:13:46.905852 DQM0 = 89, DQM1 = 77
1578 08:13:46.906415 DQ Delay:
1579 08:13:46.909473 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1580 08:13:46.912175 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1581 08:13:46.915825 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1582 08:13:46.919065 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1583 08:13:46.919531
1584 08:13:46.919897
1585 08:13:46.920235 ==
1586 08:13:46.922132 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 08:13:46.928766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 08:13:46.929317 ==
1589 08:13:46.929738
1590 08:13:46.930082
1591 08:13:46.932330 TX Vref Scan disable
1592 08:13:46.932792 == TX Byte 0 ==
1593 08:13:46.935143 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1594 08:13:46.942291 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1595 08:13:46.942920 == TX Byte 1 ==
1596 08:13:46.945753 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1597 08:13:46.952273 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1598 08:13:46.952834 ==
1599 08:13:46.955698 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 08:13:46.958176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 08:13:46.958652 ==
1602 08:13:46.971572 TX Vref=22, minBit 13, minWin=26, winSum=441
1603 08:13:46.974767 TX Vref=24, minBit 9, minWin=27, winSum=446
1604 08:13:46.978557 TX Vref=26, minBit 15, minWin=27, winSum=454
1605 08:13:46.981388 TX Vref=28, minBit 15, minWin=27, winSum=456
1606 08:13:46.988571 TX Vref=30, minBit 11, minWin=27, winSum=450
1607 08:13:46.991718 TX Vref=32, minBit 8, minWin=27, winSum=448
1608 08:13:46.995252 [TxChooseVref] Worse bit 15, Min win 27, Win sum 456, Final Vref 28
1609 08:13:46.998645
1610 08:13:46.999198 Final TX Range 1 Vref 28
1611 08:13:46.999572
1612 08:13:46.999917 ==
1613 08:13:47.001257 Dram Type= 6, Freq= 0, CH_1, rank 0
1614 08:13:47.008004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1615 08:13:47.008590 ==
1616 08:13:47.008973
1617 08:13:47.009319
1618 08:13:47.009721 TX Vref Scan disable
1619 08:13:47.012343 == TX Byte 0 ==
1620 08:13:47.015233 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1621 08:13:47.021964 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1622 08:13:47.022521 == TX Byte 1 ==
1623 08:13:47.025886 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1624 08:13:47.032231 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1625 08:13:47.032799
1626 08:13:47.033168 [DATLAT]
1627 08:13:47.033554 Freq=800, CH1 RK0
1628 08:13:47.033889
1629 08:13:47.035509 DATLAT Default: 0xa
1630 08:13:47.035971 0, 0xFFFF, sum = 0
1631 08:13:47.038475 1, 0xFFFF, sum = 0
1632 08:13:47.038962 2, 0xFFFF, sum = 0
1633 08:13:47.041745 3, 0xFFFF, sum = 0
1634 08:13:47.045300 4, 0xFFFF, sum = 0
1635 08:13:47.045896 5, 0xFFFF, sum = 0
1636 08:13:47.048521 6, 0xFFFF, sum = 0
1637 08:13:47.048992 7, 0xFFFF, sum = 0
1638 08:13:47.051853 8, 0xFFFF, sum = 0
1639 08:13:47.052417 9, 0x0, sum = 1
1640 08:13:47.055308 10, 0x0, sum = 2
1641 08:13:47.055781 11, 0x0, sum = 3
1642 08:13:47.056153 12, 0x0, sum = 4
1643 08:13:47.058513 best_step = 10
1644 08:13:47.058974
1645 08:13:47.059335 ==
1646 08:13:47.061905 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 08:13:47.065518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 08:13:47.066150 ==
1649 08:13:47.068549 RX Vref Scan: 1
1650 08:13:47.069014
1651 08:13:47.071483 Set Vref Range= 32 -> 127
1652 08:13:47.071952
1653 08:13:47.072325 RX Vref 32 -> 127, step: 1
1654 08:13:47.072676
1655 08:13:47.075410 RX Delay -95 -> 252, step: 8
1656 08:13:47.075878
1657 08:13:47.078892 Set Vref, RX VrefLevel [Byte0]: 32
1658 08:13:47.081904 [Byte1]: 32
1659 08:13:47.085265
1660 08:13:47.085863 Set Vref, RX VrefLevel [Byte0]: 33
1661 08:13:47.088175 [Byte1]: 33
1662 08:13:47.092862
1663 08:13:47.093485 Set Vref, RX VrefLevel [Byte0]: 34
1664 08:13:47.096100 [Byte1]: 34
1665 08:13:47.100408
1666 08:13:47.100968 Set Vref, RX VrefLevel [Byte0]: 35
1667 08:13:47.103445 [Byte1]: 35
1668 08:13:47.107754
1669 08:13:47.108214 Set Vref, RX VrefLevel [Byte0]: 36
1670 08:13:47.110705 [Byte1]: 36
1671 08:13:47.115104
1672 08:13:47.115563 Set Vref, RX VrefLevel [Byte0]: 37
1673 08:13:47.118930 [Byte1]: 37
1674 08:13:47.122873
1675 08:13:47.123435 Set Vref, RX VrefLevel [Byte0]: 38
1676 08:13:47.125996 [Byte1]: 38
1677 08:13:47.130592
1678 08:13:47.131220 Set Vref, RX VrefLevel [Byte0]: 39
1679 08:13:47.133844 [Byte1]: 39
1680 08:13:47.137792
1681 08:13:47.138248 Set Vref, RX VrefLevel [Byte0]: 40
1682 08:13:47.141294 [Byte1]: 40
1683 08:13:47.145630
1684 08:13:47.146092 Set Vref, RX VrefLevel [Byte0]: 41
1685 08:13:47.148656 [Byte1]: 41
1686 08:13:47.153511
1687 08:13:47.153972 Set Vref, RX VrefLevel [Byte0]: 42
1688 08:13:47.156257 [Byte1]: 42
1689 08:13:47.161279
1690 08:13:47.161898 Set Vref, RX VrefLevel [Byte0]: 43
1691 08:13:47.164166 [Byte1]: 43
1692 08:13:47.168473
1693 08:13:47.169067 Set Vref, RX VrefLevel [Byte0]: 44
1694 08:13:47.171664 [Byte1]: 44
1695 08:13:47.176427
1696 08:13:47.176986 Set Vref, RX VrefLevel [Byte0]: 45
1697 08:13:47.182209 [Byte1]: 45
1698 08:13:47.182677
1699 08:13:47.185827 Set Vref, RX VrefLevel [Byte0]: 46
1700 08:13:47.189604 [Byte1]: 46
1701 08:13:47.190160
1702 08:13:47.192872 Set Vref, RX VrefLevel [Byte0]: 47
1703 08:13:47.195747 [Byte1]: 47
1704 08:13:47.196219
1705 08:13:47.199608 Set Vref, RX VrefLevel [Byte0]: 48
1706 08:13:47.202519 [Byte1]: 48
1707 08:13:47.206696
1708 08:13:47.207255 Set Vref, RX VrefLevel [Byte0]: 49
1709 08:13:47.209760 [Byte1]: 49
1710 08:13:47.213734
1711 08:13:47.214200 Set Vref, RX VrefLevel [Byte0]: 50
1712 08:13:47.217727 [Byte1]: 50
1713 08:13:47.221311
1714 08:13:47.221986 Set Vref, RX VrefLevel [Byte0]: 51
1715 08:13:47.225242 [Byte1]: 51
1716 08:13:47.229300
1717 08:13:47.229889 Set Vref, RX VrefLevel [Byte0]: 52
1718 08:13:47.232678 [Byte1]: 52
1719 08:13:47.236919
1720 08:13:47.237538 Set Vref, RX VrefLevel [Byte0]: 53
1721 08:13:47.240006 [Byte1]: 53
1722 08:13:47.244558
1723 08:13:47.245115 Set Vref, RX VrefLevel [Byte0]: 54
1724 08:13:47.247638 [Byte1]: 54
1725 08:13:47.252096
1726 08:13:47.252653 Set Vref, RX VrefLevel [Byte0]: 55
1727 08:13:47.255172 [Byte1]: 55
1728 08:13:47.259465
1729 08:13:47.259935 Set Vref, RX VrefLevel [Byte0]: 56
1730 08:13:47.263104 [Byte1]: 56
1731 08:13:47.267487
1732 08:13:47.268073 Set Vref, RX VrefLevel [Byte0]: 57
1733 08:13:47.270172 [Byte1]: 57
1734 08:13:47.275022
1735 08:13:47.275486 Set Vref, RX VrefLevel [Byte0]: 58
1736 08:13:47.281279 [Byte1]: 58
1737 08:13:47.281878
1738 08:13:47.284661 Set Vref, RX VrefLevel [Byte0]: 59
1739 08:13:47.288267 [Byte1]: 59
1740 08:13:47.288847
1741 08:13:47.291238 Set Vref, RX VrefLevel [Byte0]: 60
1742 08:13:47.294310 [Byte1]: 60
1743 08:13:47.294799
1744 08:13:47.297898 Set Vref, RX VrefLevel [Byte0]: 61
1745 08:13:47.300983 [Byte1]: 61
1746 08:13:47.305440
1747 08:13:47.305999 Set Vref, RX VrefLevel [Byte0]: 62
1748 08:13:47.308368 [Byte1]: 62
1749 08:13:47.313195
1750 08:13:47.313715 Set Vref, RX VrefLevel [Byte0]: 63
1751 08:13:47.316064 [Byte1]: 63
1752 08:13:47.320033
1753 08:13:47.320500 Set Vref, RX VrefLevel [Byte0]: 64
1754 08:13:47.323823 [Byte1]: 64
1755 08:13:47.328396
1756 08:13:47.328862 Set Vref, RX VrefLevel [Byte0]: 65
1757 08:13:47.331066 [Byte1]: 65
1758 08:13:47.335398
1759 08:13:47.335952 Set Vref, RX VrefLevel [Byte0]: 66
1760 08:13:47.338984 [Byte1]: 66
1761 08:13:47.343391
1762 08:13:47.343943 Set Vref, RX VrefLevel [Byte0]: 67
1763 08:13:47.346912 [Byte1]: 67
1764 08:13:47.351363
1765 08:13:47.351916 Set Vref, RX VrefLevel [Byte0]: 68
1766 08:13:47.354026 [Byte1]: 68
1767 08:13:47.358823
1768 08:13:47.359374 Set Vref, RX VrefLevel [Byte0]: 69
1769 08:13:47.362046 [Byte1]: 69
1770 08:13:47.365887
1771 08:13:47.366556 Set Vref, RX VrefLevel [Byte0]: 70
1772 08:13:47.369360 [Byte1]: 70
1773 08:13:47.373207
1774 08:13:47.373726 Set Vref, RX VrefLevel [Byte0]: 71
1775 08:13:47.380513 [Byte1]: 71
1776 08:13:47.381112
1777 08:13:47.383471 Set Vref, RX VrefLevel [Byte0]: 72
1778 08:13:47.386696 [Byte1]: 72
1779 08:13:47.387264
1780 08:13:47.389885 Set Vref, RX VrefLevel [Byte0]: 73
1781 08:13:47.392988 [Byte1]: 73
1782 08:13:47.396436
1783 08:13:47.396904 Set Vref, RX VrefLevel [Byte0]: 74
1784 08:13:47.399664 [Byte1]: 74
1785 08:13:47.404096
1786 08:13:47.404675 Set Vref, RX VrefLevel [Byte0]: 75
1787 08:13:47.407402 [Byte1]: 75
1788 08:13:47.411322
1789 08:13:47.411791 Set Vref, RX VrefLevel [Byte0]: 76
1790 08:13:47.415247 [Byte1]: 76
1791 08:13:47.419338
1792 08:13:47.419917 Set Vref, RX VrefLevel [Byte0]: 77
1793 08:13:47.422899 [Byte1]: 77
1794 08:13:47.427252
1795 08:13:47.427810 Final RX Vref Byte 0 = 51 to rank0
1796 08:13:47.430301 Final RX Vref Byte 1 = 65 to rank0
1797 08:13:47.433550 Final RX Vref Byte 0 = 51 to rank1
1798 08:13:47.437035 Final RX Vref Byte 1 = 65 to rank1==
1799 08:13:47.440262 Dram Type= 6, Freq= 0, CH_1, rank 0
1800 08:13:47.446704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 08:13:47.447272 ==
1802 08:13:47.447647 DQS Delay:
1803 08:13:47.447993 DQS0 = 0, DQS1 = 0
1804 08:13:47.449989 DQM Delay:
1805 08:13:47.450458 DQM0 = 86, DQM1 = 78
1806 08:13:47.453453 DQ Delay:
1807 08:13:47.456648 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
1808 08:13:47.459577 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1809 08:13:47.463538 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1810 08:13:47.466853 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1811 08:13:47.467321
1812 08:13:47.467685
1813 08:13:47.473226 [DQSOSCAuto] RK0, (LSB)MR18= 0x2815, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
1814 08:13:47.476369 CH1 RK0: MR19=606, MR18=2815
1815 08:13:47.483007 CH1_RK0: MR19=0x606, MR18=0x2815, DQSOSC=399, MR23=63, INC=92, DEC=61
1816 08:13:47.483553
1817 08:13:47.486147 ----->DramcWriteLeveling(PI) begin...
1818 08:13:47.486621 ==
1819 08:13:47.489290 Dram Type= 6, Freq= 0, CH_1, rank 1
1820 08:13:47.493290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1821 08:13:47.493985 ==
1822 08:13:47.496093 Write leveling (Byte 0): 27 => 27
1823 08:13:47.499660 Write leveling (Byte 1): 31 => 31
1824 08:13:47.502778 DramcWriteLeveling(PI) end<-----
1825 08:13:47.503344
1826 08:13:47.503712 ==
1827 08:13:47.506009 Dram Type= 6, Freq= 0, CH_1, rank 1
1828 08:13:47.509289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1829 08:13:47.509790 ==
1830 08:13:47.512583 [Gating] SW mode calibration
1831 08:13:47.519682 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1832 08:13:47.526103 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1833 08:13:47.529099 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1834 08:13:47.535812 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1835 08:13:47.539106 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1836 08:13:47.542937 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 08:13:47.548998 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 08:13:47.552389 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 08:13:47.555796 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 08:13:47.562778 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 08:13:47.565780 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 08:13:47.569193 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 08:13:47.575655 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 08:13:47.578920 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 08:13:47.582125 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 08:13:47.588927 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 08:13:47.592007 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 08:13:47.595514 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 08:13:47.602254 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 08:13:47.605050 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1851 08:13:47.608767 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1852 08:13:47.615061 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 08:13:47.618661 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 08:13:47.621717 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 08:13:47.627976 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 08:13:47.631421 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 08:13:47.634675 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 08:13:47.641173 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 08:13:47.644755 0 9 8 | B1->B0 | 2d2d 2424 | 1 0 | (1 1) (0 0)
1860 08:13:47.648484 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1861 08:13:47.654881 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1862 08:13:47.657919 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1863 08:13:47.661588 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1864 08:13:47.667569 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1865 08:13:47.671282 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1866 08:13:47.674257 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (1 0) (1 0)
1867 08:13:47.681106 0 10 8 | B1->B0 | 2929 2f2f | 0 0 | (0 0) (0 0)
1868 08:13:47.684554 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 08:13:47.687750 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 08:13:47.691082 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 08:13:47.697497 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 08:13:47.700992 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 08:13:47.704813 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 08:13:47.711000 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 08:13:47.714218 0 11 8 | B1->B0 | 3e3e 3636 | 1 1 | (0 0) (0 0)
1876 08:13:47.717439 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1877 08:13:47.724497 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 08:13:47.727443 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 08:13:47.730765 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 08:13:47.737714 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 08:13:47.740980 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 08:13:47.744041 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1883 08:13:47.751063 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 08:13:47.753862 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 08:13:47.757431 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 08:13:47.763964 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 08:13:47.767021 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 08:13:47.770450 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 08:13:47.776955 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 08:13:47.780552 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 08:13:47.783811 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 08:13:47.790647 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 08:13:47.793587 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 08:13:47.796946 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 08:13:47.803904 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 08:13:47.807339 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 08:13:47.810326 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 08:13:47.816891 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 08:13:47.819958 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1900 08:13:47.823772 Total UI for P1: 0, mck2ui 16
1901 08:13:47.826669 best dqsien dly found for B1: ( 0, 14, 6)
1902 08:13:47.830418 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 08:13:47.833317 Total UI for P1: 0, mck2ui 16
1904 08:13:47.836906 best dqsien dly found for B0: ( 0, 14, 8)
1905 08:13:47.839890 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1906 08:13:47.843490 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1907 08:13:47.844058
1908 08:13:47.849817 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1909 08:13:47.853231 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1910 08:13:47.853752 [Gating] SW calibration Done
1911 08:13:47.856438 ==
1912 08:13:47.860008 Dram Type= 6, Freq= 0, CH_1, rank 1
1913 08:13:47.863624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1914 08:13:47.864186 ==
1915 08:13:47.864561 RX Vref Scan: 0
1916 08:13:47.864909
1917 08:13:47.866506 RX Vref 0 -> 0, step: 1
1918 08:13:47.866974
1919 08:13:47.869813 RX Delay -130 -> 252, step: 16
1920 08:13:47.873012 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1921 08:13:47.876250 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1922 08:13:47.882741 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1923 08:13:47.886587 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1924 08:13:47.889137 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1925 08:13:47.892981 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1926 08:13:47.895777 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1927 08:13:47.902865 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1928 08:13:47.905572 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1929 08:13:47.909708 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1930 08:13:47.912724 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1931 08:13:47.916019 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1932 08:13:47.922610 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1933 08:13:47.926255 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1934 08:13:47.929251 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1935 08:13:47.932350 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1936 08:13:47.932819 ==
1937 08:13:47.935696 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 08:13:47.942468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 08:13:47.943016 ==
1940 08:13:47.943391 DQS Delay:
1941 08:13:47.946252 DQS0 = 0, DQS1 = 0
1942 08:13:47.946812 DQM Delay:
1943 08:13:47.947187 DQM0 = 87, DQM1 = 79
1944 08:13:47.949255 DQ Delay:
1945 08:13:47.951907 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =77
1946 08:13:47.956006 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1947 08:13:47.958515 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1948 08:13:47.962265 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1949 08:13:47.962829
1950 08:13:47.963203
1951 08:13:47.963552 ==
1952 08:13:47.965692 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 08:13:47.968830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 08:13:47.969303 ==
1955 08:13:47.969715
1956 08:13:47.970063
1957 08:13:47.972592 TX Vref Scan disable
1958 08:13:47.975305 == TX Byte 0 ==
1959 08:13:47.978873 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1960 08:13:47.982269 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1961 08:13:47.985750 == TX Byte 1 ==
1962 08:13:47.988786 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1963 08:13:47.991732 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1964 08:13:47.992203 ==
1965 08:13:47.995367 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 08:13:47.998169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 08:13:48.001731 ==
1968 08:13:48.013933 TX Vref=22, minBit 1, minWin=27, winSum=446
1969 08:13:48.016853 TX Vref=24, minBit 8, minWin=27, winSum=446
1970 08:13:48.020714 TX Vref=26, minBit 8, minWin=27, winSum=450
1971 08:13:48.023838 TX Vref=28, minBit 8, minWin=27, winSum=451
1972 08:13:48.026988 TX Vref=30, minBit 9, minWin=27, winSum=448
1973 08:13:48.030567 TX Vref=32, minBit 8, minWin=27, winSum=451
1974 08:13:48.036731 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 28
1975 08:13:48.037292
1976 08:13:48.039998 Final TX Range 1 Vref 28
1977 08:13:48.040470
1978 08:13:48.040841 ==
1979 08:13:48.043215 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 08:13:48.046677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 08:13:48.047244 ==
1982 08:13:48.049823
1983 08:13:48.050374
1984 08:13:48.050745 TX Vref Scan disable
1985 08:13:48.053525 == TX Byte 0 ==
1986 08:13:48.056630 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1987 08:13:48.063363 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1988 08:13:48.063927 == TX Byte 1 ==
1989 08:13:48.066725 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1990 08:13:48.073559 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1991 08:13:48.074120
1992 08:13:48.074493 [DATLAT]
1993 08:13:48.074842 Freq=800, CH1 RK1
1994 08:13:48.075181
1995 08:13:48.076485 DATLAT Default: 0xa
1996 08:13:48.076951 0, 0xFFFF, sum = 0
1997 08:13:48.079616 1, 0xFFFF, sum = 0
1998 08:13:48.083495 2, 0xFFFF, sum = 0
1999 08:13:48.084064 3, 0xFFFF, sum = 0
2000 08:13:48.086466 4, 0xFFFF, sum = 0
2001 08:13:48.087035 5, 0xFFFF, sum = 0
2002 08:13:48.090029 6, 0xFFFF, sum = 0
2003 08:13:48.090518 7, 0xFFFF, sum = 0
2004 08:13:48.092983 8, 0xFFFF, sum = 0
2005 08:13:48.093583 9, 0x0, sum = 1
2006 08:13:48.096615 10, 0x0, sum = 2
2007 08:13:48.097093 11, 0x0, sum = 3
2008 08:13:48.097518 12, 0x0, sum = 4
2009 08:13:48.099898 best_step = 10
2010 08:13:48.100365
2011 08:13:48.100735 ==
2012 08:13:48.103365 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 08:13:48.106521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 08:13:48.107096 ==
2015 08:13:48.109930 RX Vref Scan: 0
2016 08:13:48.110499
2017 08:13:48.110874 RX Vref 0 -> 0, step: 1
2018 08:13:48.112882
2019 08:13:48.113367 RX Delay -95 -> 252, step: 8
2020 08:13:48.120217 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
2021 08:13:48.123558 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2022 08:13:48.126715 iDelay=217, Bit 2, Center 72 (-39 ~ 184) 224
2023 08:13:48.129988 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2024 08:13:48.133654 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2025 08:13:48.140300 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2026 08:13:48.143553 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2027 08:13:48.146569 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2028 08:13:48.149910 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2029 08:13:48.153176 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2030 08:13:48.159977 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2031 08:13:48.163450 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2032 08:13:48.166404 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2033 08:13:48.170020 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2034 08:13:48.176536 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2035 08:13:48.179546 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2036 08:13:48.180110 ==
2037 08:13:48.183243 Dram Type= 6, Freq= 0, CH_1, rank 1
2038 08:13:48.186041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2039 08:13:48.186515 ==
2040 08:13:48.189760 DQS Delay:
2041 08:13:48.190317 DQS0 = 0, DQS1 = 0
2042 08:13:48.190692 DQM Delay:
2043 08:13:48.193019 DQM0 = 86, DQM1 = 78
2044 08:13:48.193613 DQ Delay:
2045 08:13:48.196204 DQ0 =88, DQ1 =80, DQ2 =72, DQ3 =84
2046 08:13:48.199074 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2047 08:13:48.202405 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2048 08:13:48.206018 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2049 08:13:48.206486
2050 08:13:48.206856
2051 08:13:48.216281 [DQSOSCAuto] RK1, (LSB)MR18= 0x1008, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
2052 08:13:48.219670 CH1 RK1: MR19=606, MR18=1008
2053 08:13:48.222588 CH1_RK1: MR19=0x606, MR18=0x1008, DQSOSC=405, MR23=63, INC=90, DEC=60
2054 08:13:48.226003 [RxdqsGatingPostProcess] freq 800
2055 08:13:48.232509 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2056 08:13:48.235813 Pre-setting of DQS Precalculation
2057 08:13:48.239471 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2058 08:13:48.249178 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2059 08:13:48.255905 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2060 08:13:48.256456
2061 08:13:48.256822
2062 08:13:48.258641 [Calibration Summary] 1600 Mbps
2063 08:13:48.259115 CH 0, Rank 0
2064 08:13:48.262033 SW Impedance : PASS
2065 08:13:48.262498 DUTY Scan : NO K
2066 08:13:48.265534 ZQ Calibration : PASS
2067 08:13:48.268836 Jitter Meter : NO K
2068 08:13:48.269485 CBT Training : PASS
2069 08:13:48.272852 Write leveling : PASS
2070 08:13:48.275361 RX DQS gating : PASS
2071 08:13:48.275832 RX DQ/DQS(RDDQC) : PASS
2072 08:13:48.279008 TX DQ/DQS : PASS
2073 08:13:48.282510 RX DATLAT : PASS
2074 08:13:48.283067 RX DQ/DQS(Engine): PASS
2075 08:13:48.285378 TX OE : NO K
2076 08:13:48.285854 All Pass.
2077 08:13:48.286224
2078 08:13:48.289093 CH 0, Rank 1
2079 08:13:48.289605 SW Impedance : PASS
2080 08:13:48.292264 DUTY Scan : NO K
2081 08:13:48.295242 ZQ Calibration : PASS
2082 08:13:48.295712 Jitter Meter : NO K
2083 08:13:48.298722 CBT Training : PASS
2084 08:13:48.302166 Write leveling : PASS
2085 08:13:48.302637 RX DQS gating : PASS
2086 08:13:48.305145 RX DQ/DQS(RDDQC) : PASS
2087 08:13:48.305744 TX DQ/DQS : PASS
2088 08:13:48.308673 RX DATLAT : PASS
2089 08:13:48.311787 RX DQ/DQS(Engine): PASS
2090 08:13:48.312360 TX OE : NO K
2091 08:13:48.315089 All Pass.
2092 08:13:48.315647
2093 08:13:48.316018 CH 1, Rank 0
2094 08:13:48.318662 SW Impedance : PASS
2095 08:13:48.319219 DUTY Scan : NO K
2096 08:13:48.322043 ZQ Calibration : PASS
2097 08:13:48.325081 Jitter Meter : NO K
2098 08:13:48.325683 CBT Training : PASS
2099 08:13:48.328382 Write leveling : PASS
2100 08:13:48.331645 RX DQS gating : PASS
2101 08:13:48.332220 RX DQ/DQS(RDDQC) : PASS
2102 08:13:48.334439 TX DQ/DQS : PASS
2103 08:13:48.338083 RX DATLAT : PASS
2104 08:13:48.338642 RX DQ/DQS(Engine): PASS
2105 08:13:48.341443 TX OE : NO K
2106 08:13:48.341910 All Pass.
2107 08:13:48.342282
2108 08:13:48.344919 CH 1, Rank 1
2109 08:13:48.345513 SW Impedance : PASS
2110 08:13:48.348139 DUTY Scan : NO K
2111 08:13:48.351350 ZQ Calibration : PASS
2112 08:13:48.351914 Jitter Meter : NO K
2113 08:13:48.354180 CBT Training : PASS
2114 08:13:48.357996 Write leveling : PASS
2115 08:13:48.358467 RX DQS gating : PASS
2116 08:13:48.360875 RX DQ/DQS(RDDQC) : PASS
2117 08:13:48.364572 TX DQ/DQS : PASS
2118 08:13:48.365218 RX DATLAT : PASS
2119 08:13:48.367961 RX DQ/DQS(Engine): PASS
2120 08:13:48.370841 TX OE : NO K
2121 08:13:48.371327 All Pass.
2122 08:13:48.371701
2123 08:13:48.372048 DramC Write-DBI off
2124 08:13:48.374392 PER_BANK_REFRESH: Hybrid Mode
2125 08:13:48.377631 TX_TRACKING: ON
2126 08:13:48.381498 [GetDramInforAfterCalByMRR] Vendor 6.
2127 08:13:48.384177 [GetDramInforAfterCalByMRR] Revision 606.
2128 08:13:48.387524 [GetDramInforAfterCalByMRR] Revision 2 0.
2129 08:13:48.388090 MR0 0x3b3b
2130 08:13:48.390471 MR8 0x5151
2131 08:13:48.393973 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2132 08:13:48.394442
2133 08:13:48.394813 MR0 0x3b3b
2134 08:13:48.395158 MR8 0x5151
2135 08:13:48.400838 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2136 08:13:48.401431
2137 08:13:48.407374 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2138 08:13:48.411142 [FAST_K] Save calibration result to emmc
2139 08:13:48.413689 [FAST_K] Save calibration result to emmc
2140 08:13:48.417455 dram_init: config_dvfs: 1
2141 08:13:48.420948 dramc_set_vcore_voltage set vcore to 662500
2142 08:13:48.424233 Read voltage for 1200, 2
2143 08:13:48.424797 Vio18 = 0
2144 08:13:48.427732 Vcore = 662500
2145 08:13:48.428325 Vdram = 0
2146 08:13:48.428713 Vddq = 0
2147 08:13:48.430420 Vmddr = 0
2148 08:13:48.433904 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2149 08:13:48.440723 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2150 08:13:48.441293 MEM_TYPE=3, freq_sel=15
2151 08:13:48.443587 sv_algorithm_assistance_LP4_1600
2152 08:13:48.450531 ============ PULL DRAM RESETB DOWN ============
2153 08:13:48.453891 ========== PULL DRAM RESETB DOWN end =========
2154 08:13:48.457224 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2155 08:13:48.460229 ===================================
2156 08:13:48.463966 LPDDR4 DRAM CONFIGURATION
2157 08:13:48.467545 ===================================
2158 08:13:48.468107 EX_ROW_EN[0] = 0x0
2159 08:13:48.470298 EX_ROW_EN[1] = 0x0
2160 08:13:48.473731 LP4Y_EN = 0x0
2161 08:13:48.474212 WORK_FSP = 0x0
2162 08:13:48.476681 WL = 0x4
2163 08:13:48.477149 RL = 0x4
2164 08:13:48.480383 BL = 0x2
2165 08:13:48.480937 RPST = 0x0
2166 08:13:48.483805 RD_PRE = 0x0
2167 08:13:48.484370 WR_PRE = 0x1
2168 08:13:48.486812 WR_PST = 0x0
2169 08:13:48.487368 DBI_WR = 0x0
2170 08:13:48.490249 DBI_RD = 0x0
2171 08:13:48.490851 OTF = 0x1
2172 08:13:48.493546 ===================================
2173 08:13:48.496465 ===================================
2174 08:13:48.499701 ANA top config
2175 08:13:48.503801 ===================================
2176 08:13:48.504392 DLL_ASYNC_EN = 0
2177 08:13:48.506466 ALL_SLAVE_EN = 0
2178 08:13:48.509547 NEW_RANK_MODE = 1
2179 08:13:48.512926 DLL_IDLE_MODE = 1
2180 08:13:48.516767 LP45_APHY_COMB_EN = 1
2181 08:13:48.517385 TX_ODT_DIS = 1
2182 08:13:48.520095 NEW_8X_MODE = 1
2183 08:13:48.523145 ===================================
2184 08:13:48.526796 ===================================
2185 08:13:48.529853 data_rate = 2400
2186 08:13:48.533673 CKR = 1
2187 08:13:48.536424 DQ_P2S_RATIO = 8
2188 08:13:48.539735 ===================================
2189 08:13:48.543321 CA_P2S_RATIO = 8
2190 08:13:48.543793 DQ_CA_OPEN = 0
2191 08:13:48.546003 DQ_SEMI_OPEN = 0
2192 08:13:48.549905 CA_SEMI_OPEN = 0
2193 08:13:48.553119 CA_FULL_RATE = 0
2194 08:13:48.555955 DQ_CKDIV4_EN = 0
2195 08:13:48.559329 CA_CKDIV4_EN = 0
2196 08:13:48.559800 CA_PREDIV_EN = 0
2197 08:13:48.562740 PH8_DLY = 17
2198 08:13:48.566353 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2199 08:13:48.569258 DQ_AAMCK_DIV = 4
2200 08:13:48.573025 CA_AAMCK_DIV = 4
2201 08:13:48.575720 CA_ADMCK_DIV = 4
2202 08:13:48.576155 DQ_TRACK_CA_EN = 0
2203 08:13:48.579691 CA_PICK = 1200
2204 08:13:48.583234 CA_MCKIO = 1200
2205 08:13:48.586296 MCKIO_SEMI = 0
2206 08:13:48.589942 PLL_FREQ = 2366
2207 08:13:48.592903 DQ_UI_PI_RATIO = 32
2208 08:13:48.595533 CA_UI_PI_RATIO = 0
2209 08:13:48.599172 ===================================
2210 08:13:48.602806 ===================================
2211 08:13:48.603370 memory_type:LPDDR4
2212 08:13:48.605872 GP_NUM : 10
2213 08:13:48.609139 SRAM_EN : 1
2214 08:13:48.609755 MD32_EN : 0
2215 08:13:48.612635 ===================================
2216 08:13:48.616240 [ANA_INIT] >>>>>>>>>>>>>>
2217 08:13:48.619414 <<<<<< [CONFIGURE PHASE]: ANA_TX
2218 08:13:48.622532 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2219 08:13:48.626184 ===================================
2220 08:13:48.628809 data_rate = 2400,PCW = 0X5b00
2221 08:13:48.632871 ===================================
2222 08:13:48.635839 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2223 08:13:48.638817 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2224 08:13:48.645512 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2225 08:13:48.648981 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2226 08:13:48.652067 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2227 08:13:48.658462 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2228 08:13:48.658932 [ANA_INIT] flow start
2229 08:13:48.661893 [ANA_INIT] PLL >>>>>>>>
2230 08:13:48.665252 [ANA_INIT] PLL <<<<<<<<
2231 08:13:48.665867 [ANA_INIT] MIDPI >>>>>>>>
2232 08:13:48.668192 [ANA_INIT] MIDPI <<<<<<<<
2233 08:13:48.672271 [ANA_INIT] DLL >>>>>>>>
2234 08:13:48.672735 [ANA_INIT] DLL <<<<<<<<
2235 08:13:48.674914 [ANA_INIT] flow end
2236 08:13:48.678895 ============ LP4 DIFF to SE enter ============
2237 08:13:48.681545 ============ LP4 DIFF to SE exit ============
2238 08:13:48.685312 [ANA_INIT] <<<<<<<<<<<<<
2239 08:13:48.688863 [Flow] Enable top DCM control >>>>>
2240 08:13:48.691780 [Flow] Enable top DCM control <<<<<
2241 08:13:48.695064 Enable DLL master slave shuffle
2242 08:13:48.702221 ==============================================================
2243 08:13:48.702785 Gating Mode config
2244 08:13:48.708452 ==============================================================
2245 08:13:48.709015 Config description:
2246 08:13:48.718242 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2247 08:13:48.724702 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2248 08:13:48.731202 SELPH_MODE 0: By rank 1: By Phase
2249 08:13:48.734775 ==============================================================
2250 08:13:48.737876 GAT_TRACK_EN = 1
2251 08:13:48.741052 RX_GATING_MODE = 2
2252 08:13:48.744668 RX_GATING_TRACK_MODE = 2
2253 08:13:48.747736 SELPH_MODE = 1
2254 08:13:48.751264 PICG_EARLY_EN = 1
2255 08:13:48.754658 VALID_LAT_VALUE = 1
2256 08:13:48.761026 ==============================================================
2257 08:13:48.764158 Enter into Gating configuration >>>>
2258 08:13:48.767903 Exit from Gating configuration <<<<
2259 08:13:48.770612 Enter into DVFS_PRE_config >>>>>
2260 08:13:48.780689 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2261 08:13:48.784315 Exit from DVFS_PRE_config <<<<<
2262 08:13:48.787749 Enter into PICG configuration >>>>
2263 08:13:48.790456 Exit from PICG configuration <<<<
2264 08:13:48.794154 [RX_INPUT] configuration >>>>>
2265 08:13:48.794814 [RX_INPUT] configuration <<<<<
2266 08:13:48.800627 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2267 08:13:48.807765 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2268 08:13:48.810891 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2269 08:13:48.817168 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2270 08:13:48.824223 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2271 08:13:48.830611 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2272 08:13:48.834069 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2273 08:13:48.837131 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2274 08:13:48.843522 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2275 08:13:48.847183 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2276 08:13:48.850132 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2277 08:13:48.856517 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2278 08:13:48.860182 ===================================
2279 08:13:48.860622 LPDDR4 DRAM CONFIGURATION
2280 08:13:48.863768 ===================================
2281 08:13:48.866577 EX_ROW_EN[0] = 0x0
2282 08:13:48.870051 EX_ROW_EN[1] = 0x0
2283 08:13:48.870486 LP4Y_EN = 0x0
2284 08:13:48.873241 WORK_FSP = 0x0
2285 08:13:48.873695 WL = 0x4
2286 08:13:48.876928 RL = 0x4
2287 08:13:48.877564 BL = 0x2
2288 08:13:48.880036 RPST = 0x0
2289 08:13:48.880554 RD_PRE = 0x0
2290 08:13:48.883335 WR_PRE = 0x1
2291 08:13:48.883756 WR_PST = 0x0
2292 08:13:48.886376 DBI_WR = 0x0
2293 08:13:48.886794 DBI_RD = 0x0
2294 08:13:48.889671 OTF = 0x1
2295 08:13:48.893380 ===================================
2296 08:13:48.896341 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2297 08:13:48.899753 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2298 08:13:48.906336 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2299 08:13:48.909806 ===================================
2300 08:13:48.910104 LPDDR4 DRAM CONFIGURATION
2301 08:13:48.913372 ===================================
2302 08:13:48.916668 EX_ROW_EN[0] = 0x10
2303 08:13:48.919746 EX_ROW_EN[1] = 0x0
2304 08:13:48.920137 LP4Y_EN = 0x0
2305 08:13:48.922989 WORK_FSP = 0x0
2306 08:13:48.923287 WL = 0x4
2307 08:13:48.926152 RL = 0x4
2308 08:13:48.926530 BL = 0x2
2309 08:13:48.929858 RPST = 0x0
2310 08:13:48.930246 RD_PRE = 0x0
2311 08:13:48.933174 WR_PRE = 0x1
2312 08:13:48.933581 WR_PST = 0x0
2313 08:13:48.936581 DBI_WR = 0x0
2314 08:13:48.936978 DBI_RD = 0x0
2315 08:13:48.940027 OTF = 0x1
2316 08:13:48.942938 ===================================
2317 08:13:48.949835 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2318 08:13:48.950354 ==
2319 08:13:48.952741 Dram Type= 6, Freq= 0, CH_0, rank 0
2320 08:13:48.956221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2321 08:13:48.957034 ==
2322 08:13:48.959469 [Duty_Offset_Calibration]
2323 08:13:48.960040 B0:1 B1:-1 CA:0
2324 08:13:48.960548
2325 08:13:48.962906 [DutyScan_Calibration_Flow] k_type=0
2326 08:13:48.973280
2327 08:13:48.973831 ==CLK 0==
2328 08:13:48.976187 Final CLK duty delay cell = 0
2329 08:13:48.979799 [0] MAX Duty = 5094%(X100), DQS PI = 16
2330 08:13:48.983539 [0] MIN Duty = 4875%(X100), DQS PI = 8
2331 08:13:48.984052 [0] AVG Duty = 4984%(X100)
2332 08:13:48.986432
2333 08:13:48.989970 CH0 CLK Duty spec in!! Max-Min= 219%
2334 08:13:48.992811 [DutyScan_Calibration_Flow] ====Done====
2335 08:13:48.993355
2336 08:13:48.996404 [DutyScan_Calibration_Flow] k_type=1
2337 08:13:49.011661
2338 08:13:49.012219 ==DQS 0 ==
2339 08:13:49.014853 Final DQS duty delay cell = -4
2340 08:13:49.017925 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2341 08:13:49.021717 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2342 08:13:49.024751 [-4] AVG Duty = 4968%(X100)
2343 08:13:49.025304
2344 08:13:49.025761 ==DQS 1 ==
2345 08:13:49.028283 Final DQS duty delay cell = 0
2346 08:13:49.031120 [0] MAX Duty = 5125%(X100), DQS PI = 54
2347 08:13:49.034943 [0] MIN Duty = 5000%(X100), DQS PI = 22
2348 08:13:49.037923 [0] AVG Duty = 5062%(X100)
2349 08:13:49.038485
2350 08:13:49.041259 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2351 08:13:49.041855
2352 08:13:49.044350 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2353 08:13:49.047982 [DutyScan_Calibration_Flow] ====Done====
2354 08:13:49.048541
2355 08:13:49.050986 [DutyScan_Calibration_Flow] k_type=3
2356 08:13:49.069243
2357 08:13:49.069860 ==DQM 0 ==
2358 08:13:49.073003 Final DQM duty delay cell = 0
2359 08:13:49.076203 [0] MAX Duty = 5062%(X100), DQS PI = 24
2360 08:13:49.079061 [0] MIN Duty = 4875%(X100), DQS PI = 6
2361 08:13:49.082683 [0] AVG Duty = 4968%(X100)
2362 08:13:49.083237
2363 08:13:49.083606 ==DQM 1 ==
2364 08:13:49.085816 Final DQM duty delay cell = 4
2365 08:13:49.089540 [4] MAX Duty = 5187%(X100), DQS PI = 16
2366 08:13:49.092422 [4] MIN Duty = 5000%(X100), DQS PI = 24
2367 08:13:49.095897 [4] AVG Duty = 5093%(X100)
2368 08:13:49.096451
2369 08:13:49.098676 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2370 08:13:49.099140
2371 08:13:49.102338 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2372 08:13:49.105994 [DutyScan_Calibration_Flow] ====Done====
2373 08:13:49.106553
2374 08:13:49.108801 [DutyScan_Calibration_Flow] k_type=2
2375 08:13:49.124031
2376 08:13:49.124633 ==DQ 0 ==
2377 08:13:49.127477 Final DQ duty delay cell = -4
2378 08:13:49.130830 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2379 08:13:49.133893 [-4] MIN Duty = 4875%(X100), DQS PI = 52
2380 08:13:49.137200 [-4] AVG Duty = 4953%(X100)
2381 08:13:49.137696
2382 08:13:49.138099 ==DQ 1 ==
2383 08:13:49.140682 Final DQ duty delay cell = -4
2384 08:13:49.143793 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2385 08:13:49.147319 [-4] MIN Duty = 4876%(X100), DQS PI = 14
2386 08:13:49.150201 [-4] AVG Duty = 4922%(X100)
2387 08:13:49.150667
2388 08:13:49.153516 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2389 08:13:49.153983
2390 08:13:49.157194 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2391 08:13:49.160311 [DutyScan_Calibration_Flow] ====Done====
2392 08:13:49.160750 ==
2393 08:13:49.163567 Dram Type= 6, Freq= 0, CH_1, rank 0
2394 08:13:49.166883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2395 08:13:49.167184 ==
2396 08:13:49.170275 [Duty_Offset_Calibration]
2397 08:13:49.170504 B0:-1 B1:1 CA:1
2398 08:13:49.173192
2399 08:13:49.176870 [DutyScan_Calibration_Flow] k_type=0
2400 08:13:49.184921
2401 08:13:49.185189 ==CLK 0==
2402 08:13:49.187561 Final CLK duty delay cell = 0
2403 08:13:49.191312 [0] MAX Duty = 5156%(X100), DQS PI = 22
2404 08:13:49.194248 [0] MIN Duty = 4969%(X100), DQS PI = 0
2405 08:13:49.194515 [0] AVG Duty = 5062%(X100)
2406 08:13:49.197621
2407 08:13:49.200989 CH1 CLK Duty spec in!! Max-Min= 187%
2408 08:13:49.204199 [DutyScan_Calibration_Flow] ====Done====
2409 08:13:49.204464
2410 08:13:49.207651 [DutyScan_Calibration_Flow] k_type=1
2411 08:13:49.223904
2412 08:13:49.224327 ==DQS 0 ==
2413 08:13:49.227445 Final DQS duty delay cell = 0
2414 08:13:49.230991 [0] MAX Duty = 5156%(X100), DQS PI = 48
2415 08:13:49.233830 [0] MIN Duty = 4875%(X100), DQS PI = 8
2416 08:13:49.237396 [0] AVG Duty = 5015%(X100)
2417 08:13:49.237959
2418 08:13:49.238330 ==DQS 1 ==
2419 08:13:49.240139 Final DQS duty delay cell = 0
2420 08:13:49.243455 [0] MAX Duty = 5062%(X100), DQS PI = 14
2421 08:13:49.246861 [0] MIN Duty = 4969%(X100), DQS PI = 56
2422 08:13:49.250123 [0] AVG Duty = 5015%(X100)
2423 08:13:49.250680
2424 08:13:49.253297 CH1 DQS 0 Duty spec in!! Max-Min= 281%
2425 08:13:49.253795
2426 08:13:49.256313 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2427 08:13:49.260177 [DutyScan_Calibration_Flow] ====Done====
2428 08:13:49.260644
2429 08:13:49.263215 [DutyScan_Calibration_Flow] k_type=3
2430 08:13:49.279531
2431 08:13:49.280085 ==DQM 0 ==
2432 08:13:49.282978 Final DQM duty delay cell = -4
2433 08:13:49.286078 [-4] MAX Duty = 5031%(X100), DQS PI = 16
2434 08:13:49.289302 [-4] MIN Duty = 4844%(X100), DQS PI = 6
2435 08:13:49.292818 [-4] AVG Duty = 4937%(X100)
2436 08:13:49.293428
2437 08:13:49.293808 ==DQM 1 ==
2438 08:13:49.295678 Final DQM duty delay cell = 0
2439 08:13:49.299363 [0] MAX Duty = 5156%(X100), DQS PI = 8
2440 08:13:49.302148 [0] MIN Duty = 4969%(X100), DQS PI = 28
2441 08:13:49.306041 [0] AVG Duty = 5062%(X100)
2442 08:13:49.306605
2443 08:13:49.309085 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2444 08:13:49.309585
2445 08:13:49.312708 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2446 08:13:49.316076 [DutyScan_Calibration_Flow] ====Done====
2447 08:13:49.316541
2448 08:13:49.319105 [DutyScan_Calibration_Flow] k_type=2
2449 08:13:49.336705
2450 08:13:49.337260 ==DQ 0 ==
2451 08:13:49.339807 Final DQ duty delay cell = 0
2452 08:13:49.343191 [0] MAX Duty = 5187%(X100), DQS PI = 30
2453 08:13:49.346009 [0] MIN Duty = 4876%(X100), DQS PI = 8
2454 08:13:49.346479 [0] AVG Duty = 5031%(X100)
2455 08:13:49.349727
2456 08:13:49.350293 ==DQ 1 ==
2457 08:13:49.352936 Final DQ duty delay cell = 0
2458 08:13:49.356080 [0] MAX Duty = 5124%(X100), DQS PI = 12
2459 08:13:49.359714 [0] MIN Duty = 4969%(X100), DQS PI = 0
2460 08:13:49.360246 [0] AVG Duty = 5046%(X100)
2461 08:13:49.360619
2462 08:13:49.366395 CH1 DQ 0 Duty spec in!! Max-Min= 311%
2463 08:13:49.366952
2464 08:13:49.369114 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2465 08:13:49.372732 [DutyScan_Calibration_Flow] ====Done====
2466 08:13:49.376108 nWR fixed to 30
2467 08:13:49.376662 [ModeRegInit_LP4] CH0 RK0
2468 08:13:49.379063 [ModeRegInit_LP4] CH0 RK1
2469 08:13:49.382457 [ModeRegInit_LP4] CH1 RK0
2470 08:13:49.385908 [ModeRegInit_LP4] CH1 RK1
2471 08:13:49.386469 match AC timing 7
2472 08:13:49.391983 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2473 08:13:49.395638 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2474 08:13:49.398581 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2475 08:13:49.405399 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2476 08:13:49.408190 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2477 08:13:49.408603 ==
2478 08:13:49.411595 Dram Type= 6, Freq= 0, CH_0, rank 0
2479 08:13:49.415187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2480 08:13:49.415323 ==
2481 08:13:49.421122 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2482 08:13:49.428344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2483 08:13:49.436113 [CA 0] Center 39 (9~70) winsize 62
2484 08:13:49.439131 [CA 1] Center 39 (9~70) winsize 62
2485 08:13:49.442244 [CA 2] Center 35 (5~66) winsize 62
2486 08:13:49.445870 [CA 3] Center 35 (5~66) winsize 62
2487 08:13:49.449432 [CA 4] Center 34 (4~64) winsize 61
2488 08:13:49.452399 [CA 5] Center 33 (4~63) winsize 60
2489 08:13:49.452613
2490 08:13:49.455845 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2491 08:13:49.456050
2492 08:13:49.458859 [CATrainingPosCal] consider 1 rank data
2493 08:13:49.462391 u2DelayCellTimex100 = 270/100 ps
2494 08:13:49.465778 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2495 08:13:49.472089 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2496 08:13:49.476017 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2497 08:13:49.479441 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2498 08:13:49.482870 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2499 08:13:49.485997 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2500 08:13:49.486469
2501 08:13:49.489139 CA PerBit enable=1, Macro0, CA PI delay=33
2502 08:13:49.489650
2503 08:13:49.492880 [CBTSetCACLKResult] CA Dly = 33
2504 08:13:49.493489 CS Dly: 8 (0~39)
2505 08:13:49.495614 ==
2506 08:13:49.498857 Dram Type= 6, Freq= 0, CH_0, rank 1
2507 08:13:49.502467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 08:13:49.503032 ==
2509 08:13:49.509150 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2510 08:13:49.512076 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2511 08:13:49.522387 [CA 0] Center 39 (9~70) winsize 62
2512 08:13:49.525214 [CA 1] Center 39 (9~70) winsize 62
2513 08:13:49.529171 [CA 2] Center 35 (5~66) winsize 62
2514 08:13:49.532004 [CA 3] Center 34 (4~65) winsize 62
2515 08:13:49.535496 [CA 4] Center 33 (3~64) winsize 62
2516 08:13:49.538323 [CA 5] Center 33 (3~63) winsize 61
2517 08:13:49.538895
2518 08:13:49.541622 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2519 08:13:49.542092
2520 08:13:49.545179 [CATrainingPosCal] consider 2 rank data
2521 08:13:49.548279 u2DelayCellTimex100 = 270/100 ps
2522 08:13:49.551603 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2523 08:13:49.558107 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2524 08:13:49.561267 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2525 08:13:49.564775 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2526 08:13:49.568102 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2527 08:13:49.571537 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2528 08:13:49.572137
2529 08:13:49.574760 CA PerBit enable=1, Macro0, CA PI delay=33
2530 08:13:49.575231
2531 08:13:49.578217 [CBTSetCACLKResult] CA Dly = 33
2532 08:13:49.578737 CS Dly: 9 (0~41)
2533 08:13:49.581085
2534 08:13:49.584832 ----->DramcWriteLeveling(PI) begin...
2535 08:13:49.585464 ==
2536 08:13:49.588466 Dram Type= 6, Freq= 0, CH_0, rank 0
2537 08:13:49.591090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2538 08:13:49.591569 ==
2539 08:13:49.594521 Write leveling (Byte 0): 31 => 31
2540 08:13:49.597787 Write leveling (Byte 1): 28 => 28
2541 08:13:49.600857 DramcWriteLeveling(PI) end<-----
2542 08:13:49.601530
2543 08:13:49.601915 ==
2544 08:13:49.604793 Dram Type= 6, Freq= 0, CH_0, rank 0
2545 08:13:49.608145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2546 08:13:49.608713 ==
2547 08:13:49.610692 [Gating] SW mode calibration
2548 08:13:49.618053 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2549 08:13:49.624808 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2550 08:13:49.627534 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2551 08:13:49.630951 0 15 4 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2552 08:13:49.637514 0 15 8 | B1->B0 | 3231 3434 | 1 1 | (0 0) (1 1)
2553 08:13:49.641232 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2554 08:13:49.644388 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2555 08:13:49.650883 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2556 08:13:49.654308 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2557 08:13:49.657314 0 15 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
2558 08:13:49.663702 1 0 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
2559 08:13:49.667200 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2560 08:13:49.670633 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2561 08:13:49.676987 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2562 08:13:49.680434 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2563 08:13:49.684010 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2564 08:13:49.690309 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2565 08:13:49.693821 1 0 28 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2566 08:13:49.696663 1 1 0 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2567 08:13:49.703647 1 1 4 | B1->B0 | 3f3f 4646 | 1 0 | (1 1) (0 0)
2568 08:13:49.707001 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 08:13:49.710525 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 08:13:49.717130 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2571 08:13:49.720567 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 08:13:49.723734 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 08:13:49.730525 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2574 08:13:49.733496 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2575 08:13:49.736345 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 08:13:49.743036 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 08:13:49.746643 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 08:13:49.750058 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 08:13:49.756485 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 08:13:49.759558 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 08:13:49.763046 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 08:13:49.769774 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 08:13:49.772635 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 08:13:49.776158 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 08:13:49.783101 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 08:13:49.785810 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 08:13:49.789220 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 08:13:49.795966 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2589 08:13:49.799275 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2590 08:13:49.802332 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2591 08:13:49.806228 Total UI for P1: 0, mck2ui 16
2592 08:13:49.809216 best dqsien dly found for B0: ( 1, 3, 26)
2593 08:13:49.815783 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 08:13:49.816302 Total UI for P1: 0, mck2ui 16
2595 08:13:49.822274 best dqsien dly found for B1: ( 1, 4, 0)
2596 08:13:49.825858 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2597 08:13:49.828997 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2598 08:13:49.829523
2599 08:13:49.832461 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2600 08:13:49.835503 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2601 08:13:49.838996 [Gating] SW calibration Done
2602 08:13:49.839418 ==
2603 08:13:49.842749 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 08:13:49.845710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 08:13:49.846178 ==
2606 08:13:49.848809 RX Vref Scan: 0
2607 08:13:49.849411
2608 08:13:49.849795 RX Vref 0 -> 0, step: 1
2609 08:13:49.850141
2610 08:13:49.852287 RX Delay -40 -> 252, step: 8
2611 08:13:49.855917 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2612 08:13:49.861983 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2613 08:13:49.865830 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2614 08:13:49.869012 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2615 08:13:49.872519 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2616 08:13:49.875136 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2617 08:13:49.881888 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2618 08:13:49.885564 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2619 08:13:49.888942 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2620 08:13:49.891693 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2621 08:13:49.895250 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2622 08:13:49.901627 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2623 08:13:49.905289 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2624 08:13:49.908775 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2625 08:13:49.911997 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2626 08:13:49.914984 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2627 08:13:49.918278 ==
2628 08:13:49.921838 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 08:13:49.924539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 08:13:49.924970 ==
2631 08:13:49.925308 DQS Delay:
2632 08:13:49.928152 DQS0 = 0, DQS1 = 0
2633 08:13:49.928575 DQM Delay:
2634 08:13:49.931905 DQM0 = 119, DQM1 = 106
2635 08:13:49.932330 DQ Delay:
2636 08:13:49.934803 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2637 08:13:49.938211 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2638 08:13:49.941694 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2639 08:13:49.944523 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =111
2640 08:13:49.944950
2641 08:13:49.945283
2642 08:13:49.945631 ==
2643 08:13:49.948256 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 08:13:49.954611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 08:13:49.955043 ==
2646 08:13:49.955379
2647 08:13:49.955691
2648 08:13:49.955990 TX Vref Scan disable
2649 08:13:49.957990 == TX Byte 0 ==
2650 08:13:49.961659 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2651 08:13:49.968222 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2652 08:13:49.968750 == TX Byte 1 ==
2653 08:13:49.971991 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2654 08:13:49.978451 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2655 08:13:49.978895 ==
2656 08:13:49.981467 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 08:13:49.984194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 08:13:49.984621 ==
2659 08:13:49.996372 TX Vref=22, minBit 1, minWin=25, winSum=411
2660 08:13:49.999391 TX Vref=24, minBit 1, minWin=25, winSum=417
2661 08:13:50.002939 TX Vref=26, minBit 13, minWin=25, winSum=424
2662 08:13:50.006036 TX Vref=28, minBit 5, minWin=26, winSum=428
2663 08:13:50.009554 TX Vref=30, minBit 5, minWin=26, winSum=431
2664 08:13:50.016442 TX Vref=32, minBit 4, minWin=25, winSum=425
2665 08:13:50.019514 [TxChooseVref] Worse bit 5, Min win 26, Win sum 431, Final Vref 30
2666 08:13:50.020055
2667 08:13:50.023143 Final TX Range 1 Vref 30
2668 08:13:50.023569
2669 08:13:50.023903 ==
2670 08:13:50.026699 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 08:13:50.029653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 08:13:50.030084 ==
2673 08:13:50.032730
2674 08:13:50.033153
2675 08:13:50.033529 TX Vref Scan disable
2676 08:13:50.035947 == TX Byte 0 ==
2677 08:13:50.039154 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2678 08:13:50.042979 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2679 08:13:50.045655 == TX Byte 1 ==
2680 08:13:50.049220 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2681 08:13:50.055838 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2682 08:13:50.056266
2683 08:13:50.056606 [DATLAT]
2684 08:13:50.056921 Freq=1200, CH0 RK0
2685 08:13:50.057476
2686 08:13:50.059259 DATLAT Default: 0xd
2687 08:13:50.059684 0, 0xFFFF, sum = 0
2688 08:13:50.062846 1, 0xFFFF, sum = 0
2689 08:13:50.065493 2, 0xFFFF, sum = 0
2690 08:13:50.065927 3, 0xFFFF, sum = 0
2691 08:13:50.068894 4, 0xFFFF, sum = 0
2692 08:13:50.069327 5, 0xFFFF, sum = 0
2693 08:13:50.072415 6, 0xFFFF, sum = 0
2694 08:13:50.072846 7, 0xFFFF, sum = 0
2695 08:13:50.075897 8, 0xFFFF, sum = 0
2696 08:13:50.076325 9, 0xFFFF, sum = 0
2697 08:13:50.078968 10, 0xFFFF, sum = 0
2698 08:13:50.079435 11, 0xFFFF, sum = 0
2699 08:13:50.083056 12, 0x0, sum = 1
2700 08:13:50.083594 13, 0x0, sum = 2
2701 08:13:50.085901 14, 0x0, sum = 3
2702 08:13:50.086335 15, 0x0, sum = 4
2703 08:13:50.088944 best_step = 13
2704 08:13:50.089402
2705 08:13:50.089745 ==
2706 08:13:50.092395 Dram Type= 6, Freq= 0, CH_0, rank 0
2707 08:13:50.095819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2708 08:13:50.096356 ==
2709 08:13:50.096698 RX Vref Scan: 1
2710 08:13:50.099031
2711 08:13:50.099454 Set Vref Range= 32 -> 127
2712 08:13:50.099869
2713 08:13:50.102491 RX Vref 32 -> 127, step: 1
2714 08:13:50.102915
2715 08:13:50.105510 RX Delay -21 -> 252, step: 4
2716 08:13:50.105936
2717 08:13:50.108857 Set Vref, RX VrefLevel [Byte0]: 32
2718 08:13:50.112129 [Byte1]: 32
2719 08:13:50.112557
2720 08:13:50.115527 Set Vref, RX VrefLevel [Byte0]: 33
2721 08:13:50.118918 [Byte1]: 33
2722 08:13:50.122917
2723 08:13:50.123364 Set Vref, RX VrefLevel [Byte0]: 34
2724 08:13:50.125685 [Byte1]: 34
2725 08:13:50.130764
2726 08:13:50.131285 Set Vref, RX VrefLevel [Byte0]: 35
2727 08:13:50.133681 [Byte1]: 35
2728 08:13:50.138307
2729 08:13:50.138731 Set Vref, RX VrefLevel [Byte0]: 36
2730 08:13:50.141875 [Byte1]: 36
2731 08:13:50.146354
2732 08:13:50.146779 Set Vref, RX VrefLevel [Byte0]: 37
2733 08:13:50.149591 [Byte1]: 37
2734 08:13:50.153910
2735 08:13:50.154333 Set Vref, RX VrefLevel [Byte0]: 38
2736 08:13:50.157368 [Byte1]: 38
2737 08:13:50.162053
2738 08:13:50.162478 Set Vref, RX VrefLevel [Byte0]: 39
2739 08:13:50.165137 [Byte1]: 39
2740 08:13:50.170148
2741 08:13:50.170572 Set Vref, RX VrefLevel [Byte0]: 40
2742 08:13:50.173230 [Byte1]: 40
2743 08:13:50.177670
2744 08:13:50.178091 Set Vref, RX VrefLevel [Byte0]: 41
2745 08:13:50.181327 [Byte1]: 41
2746 08:13:50.185851
2747 08:13:50.186275 Set Vref, RX VrefLevel [Byte0]: 42
2748 08:13:50.189158 [Byte1]: 42
2749 08:13:50.193860
2750 08:13:50.194292 Set Vref, RX VrefLevel [Byte0]: 43
2751 08:13:50.197217 [Byte1]: 43
2752 08:13:50.202045
2753 08:13:50.202593 Set Vref, RX VrefLevel [Byte0]: 44
2754 08:13:50.205153 [Byte1]: 44
2755 08:13:50.209583
2756 08:13:50.210008 Set Vref, RX VrefLevel [Byte0]: 45
2757 08:13:50.213025 [Byte1]: 45
2758 08:13:50.217764
2759 08:13:50.218286 Set Vref, RX VrefLevel [Byte0]: 46
2760 08:13:50.220908 [Byte1]: 46
2761 08:13:50.225837
2762 08:13:50.226359 Set Vref, RX VrefLevel [Byte0]: 47
2763 08:13:50.228928 [Byte1]: 47
2764 08:13:50.233788
2765 08:13:50.234312 Set Vref, RX VrefLevel [Byte0]: 48
2766 08:13:50.237325 [Byte1]: 48
2767 08:13:50.241486
2768 08:13:50.242010 Set Vref, RX VrefLevel [Byte0]: 49
2769 08:13:50.248280 [Byte1]: 49
2770 08:13:50.248809
2771 08:13:50.251576 Set Vref, RX VrefLevel [Byte0]: 50
2772 08:13:50.254974 [Byte1]: 50
2773 08:13:50.255502
2774 08:13:50.257870 Set Vref, RX VrefLevel [Byte0]: 51
2775 08:13:50.260977 [Byte1]: 51
2776 08:13:50.265050
2777 08:13:50.265610 Set Vref, RX VrefLevel [Byte0]: 52
2778 08:13:50.268462 [Byte1]: 52
2779 08:13:50.273445
2780 08:13:50.273978 Set Vref, RX VrefLevel [Byte0]: 53
2781 08:13:50.276335 [Byte1]: 53
2782 08:13:50.280876
2783 08:13:50.281379 Set Vref, RX VrefLevel [Byte0]: 54
2784 08:13:50.284667 [Byte1]: 54
2785 08:13:50.289281
2786 08:13:50.289880 Set Vref, RX VrefLevel [Byte0]: 55
2787 08:13:50.292613 [Byte1]: 55
2788 08:13:50.297009
2789 08:13:50.297603 Set Vref, RX VrefLevel [Byte0]: 56
2790 08:13:50.300484 [Byte1]: 56
2791 08:13:50.305501
2792 08:13:50.306058 Set Vref, RX VrefLevel [Byte0]: 57
2793 08:13:50.308378 [Byte1]: 57
2794 08:13:50.313082
2795 08:13:50.313726 Set Vref, RX VrefLevel [Byte0]: 58
2796 08:13:50.316140 [Byte1]: 58
2797 08:13:50.320747
2798 08:13:50.321304 Set Vref, RX VrefLevel [Byte0]: 59
2799 08:13:50.323936 [Byte1]: 59
2800 08:13:50.328952
2801 08:13:50.329558 Set Vref, RX VrefLevel [Byte0]: 60
2802 08:13:50.332397 [Byte1]: 60
2803 08:13:50.336607
2804 08:13:50.337164 Set Vref, RX VrefLevel [Byte0]: 61
2805 08:13:50.340312 [Byte1]: 61
2806 08:13:50.345471
2807 08:13:50.346036 Set Vref, RX VrefLevel [Byte0]: 62
2808 08:13:50.347674 [Byte1]: 62
2809 08:13:50.352910
2810 08:13:50.353519 Set Vref, RX VrefLevel [Byte0]: 63
2811 08:13:50.355776 [Byte1]: 63
2812 08:13:50.360383
2813 08:13:50.360940 Set Vref, RX VrefLevel [Byte0]: 64
2814 08:13:50.363856 [Byte1]: 64
2815 08:13:50.368101
2816 08:13:50.368670 Set Vref, RX VrefLevel [Byte0]: 65
2817 08:13:50.371951 [Byte1]: 65
2818 08:13:50.376562
2819 08:13:50.377138 Set Vref, RX VrefLevel [Byte0]: 66
2820 08:13:50.379628 [Byte1]: 66
2821 08:13:50.384240
2822 08:13:50.384805 Set Vref, RX VrefLevel [Byte0]: 67
2823 08:13:50.387772 [Byte1]: 67
2824 08:13:50.392253
2825 08:13:50.392720 Set Vref, RX VrefLevel [Byte0]: 68
2826 08:13:50.395403 [Byte1]: 68
2827 08:13:50.399915
2828 08:13:50.400383 Set Vref, RX VrefLevel [Byte0]: 69
2829 08:13:50.403270 [Byte1]: 69
2830 08:13:50.407843
2831 08:13:50.408400 Set Vref, RX VrefLevel [Byte0]: 70
2832 08:13:50.411507 [Byte1]: 70
2833 08:13:50.415933
2834 08:13:50.416494 Set Vref, RX VrefLevel [Byte0]: 71
2835 08:13:50.418942 [Byte1]: 71
2836 08:13:50.423941
2837 08:13:50.424408 Set Vref, RX VrefLevel [Byte0]: 72
2838 08:13:50.427052 [Byte1]: 72
2839 08:13:50.431849
2840 08:13:50.432414 Set Vref, RX VrefLevel [Byte0]: 73
2841 08:13:50.434991 [Byte1]: 73
2842 08:13:50.440390
2843 08:13:50.440957 Set Vref, RX VrefLevel [Byte0]: 74
2844 08:13:50.442905 [Byte1]: 74
2845 08:13:50.447925
2846 08:13:50.448488 Set Vref, RX VrefLevel [Byte0]: 75
2847 08:13:50.450845 [Byte1]: 75
2848 08:13:50.455920
2849 08:13:50.456484 Set Vref, RX VrefLevel [Byte0]: 76
2850 08:13:50.458679 [Byte1]: 76
2851 08:13:50.463177
2852 08:13:50.463643 Final RX Vref Byte 0 = 61 to rank0
2853 08:13:50.466751 Final RX Vref Byte 1 = 56 to rank0
2854 08:13:50.470138 Final RX Vref Byte 0 = 61 to rank1
2855 08:13:50.473624 Final RX Vref Byte 1 = 56 to rank1==
2856 08:13:50.477268 Dram Type= 6, Freq= 0, CH_0, rank 0
2857 08:13:50.483798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2858 08:13:50.484371 ==
2859 08:13:50.484746 DQS Delay:
2860 08:13:50.486468 DQS0 = 0, DQS1 = 0
2861 08:13:50.486934 DQM Delay:
2862 08:13:50.487304 DQM0 = 119, DQM1 = 108
2863 08:13:50.489743 DQ Delay:
2864 08:13:50.493445 DQ0 =116, DQ1 =120, DQ2 =114, DQ3 =116
2865 08:13:50.496739 DQ4 =120, DQ5 =114, DQ6 =124, DQ7 =128
2866 08:13:50.500032 DQ8 =96, DQ9 =94, DQ10 =112, DQ11 =102
2867 08:13:50.503340 DQ12 =114, DQ13 =112, DQ14 =120, DQ15 =116
2868 08:13:50.503815
2869 08:13:50.504190
2870 08:13:50.513583 [DQSOSCAuto] RK0, (LSB)MR18= 0xcf8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 405 ps
2871 08:13:50.514157 CH0 RK0: MR19=403, MR18=CF8
2872 08:13:50.519739 CH0_RK0: MR19=0x403, MR18=0xCF8, DQSOSC=405, MR23=63, INC=39, DEC=26
2873 08:13:50.520425
2874 08:13:50.522884 ----->DramcWriteLeveling(PI) begin...
2875 08:13:50.523359 ==
2876 08:13:50.526198 Dram Type= 6, Freq= 0, CH_0, rank 1
2877 08:13:50.529756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2878 08:13:50.533006 ==
2879 08:13:50.536569 Write leveling (Byte 0): 31 => 31
2880 08:13:50.537142 Write leveling (Byte 1): 29 => 29
2881 08:13:50.539553 DramcWriteLeveling(PI) end<-----
2882 08:13:50.540019
2883 08:13:50.540549 ==
2884 08:13:50.542974 Dram Type= 6, Freq= 0, CH_0, rank 1
2885 08:13:50.549577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2886 08:13:50.550043 ==
2887 08:13:50.552818 [Gating] SW mode calibration
2888 08:13:50.559539 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2889 08:13:50.562835 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2890 08:13:50.569632 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2891 08:13:50.572755 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
2892 08:13:50.576309 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 08:13:50.582621 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 08:13:50.585674 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 08:13:50.589449 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 08:13:50.596030 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2897 08:13:50.599508 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2898 08:13:50.602075 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2899 08:13:50.608976 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2900 08:13:50.612337 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 08:13:50.616014 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 08:13:50.622302 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 08:13:50.625588 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 08:13:50.628947 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 08:13:50.635368 1 0 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
2906 08:13:50.638351 1 1 0 | B1->B0 | 3030 4141 | 0 0 | (0 0) (0 0)
2907 08:13:50.641858 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 08:13:50.648283 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 08:13:50.652034 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 08:13:50.655666 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 08:13:50.661630 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 08:13:50.665226 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 08:13:50.668604 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2914 08:13:50.674969 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2915 08:13:50.678070 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 08:13:50.681597 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 08:13:50.688310 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 08:13:50.691532 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 08:13:50.694681 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 08:13:50.701252 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 08:13:50.705071 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 08:13:50.708150 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 08:13:50.714625 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 08:13:50.717531 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 08:13:50.721532 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 08:13:50.727755 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 08:13:50.731323 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 08:13:50.734687 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 08:13:50.741079 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2930 08:13:50.744314 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2931 08:13:50.747646 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 08:13:50.751278 Total UI for P1: 0, mck2ui 16
2933 08:13:50.753926 best dqsien dly found for B0: ( 1, 3, 30)
2934 08:13:50.757787 Total UI for P1: 0, mck2ui 16
2935 08:13:50.760893 best dqsien dly found for B1: ( 1, 4, 0)
2936 08:13:50.764535 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2937 08:13:50.767320 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2938 08:13:50.767862
2939 08:13:50.770710 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2940 08:13:50.777274 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2941 08:13:50.777852 [Gating] SW calibration Done
2942 08:13:50.778235 ==
2943 08:13:50.780675 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 08:13:50.787684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 08:13:50.788252 ==
2946 08:13:50.788735 RX Vref Scan: 0
2947 08:13:50.789186
2948 08:13:50.791171 RX Vref 0 -> 0, step: 1
2949 08:13:50.791778
2950 08:13:50.794110 RX Delay -40 -> 252, step: 8
2951 08:13:50.796989 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2952 08:13:50.800622 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2953 08:13:50.803908 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2954 08:13:50.810492 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2955 08:13:50.814191 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2956 08:13:50.817252 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2957 08:13:50.820086 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2958 08:13:50.823764 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2959 08:13:50.826886 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2960 08:13:50.833524 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2961 08:13:50.837243 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2962 08:13:50.840384 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2963 08:13:50.843697 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2964 08:13:50.850428 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2965 08:13:50.854031 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2966 08:13:50.857062 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2967 08:13:50.857665 ==
2968 08:13:50.860480 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 08:13:50.863222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 08:13:50.863689 ==
2971 08:13:50.866667 DQS Delay:
2972 08:13:50.867148 DQS0 = 0, DQS1 = 0
2973 08:13:50.870051 DQM Delay:
2974 08:13:50.870509 DQM0 = 117, DQM1 = 108
2975 08:13:50.870875 DQ Delay:
2976 08:13:50.876414 DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115
2977 08:13:50.879769 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2978 08:13:50.883185 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2979 08:13:50.886794 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2980 08:13:50.887382
2981 08:13:50.887751
2982 08:13:50.888088 ==
2983 08:13:50.890066 Dram Type= 6, Freq= 0, CH_0, rank 1
2984 08:13:50.892912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2985 08:13:50.893421 ==
2986 08:13:50.893792
2987 08:13:50.894134
2988 08:13:50.896619 TX Vref Scan disable
2989 08:13:50.899648 == TX Byte 0 ==
2990 08:13:50.903085 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2991 08:13:50.906010 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2992 08:13:50.909455 == TX Byte 1 ==
2993 08:13:50.913156 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2994 08:13:50.916239 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2995 08:13:50.916700 ==
2996 08:13:50.919307 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 08:13:50.925880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 08:13:50.926396 ==
2999 08:13:50.936821 TX Vref=22, minBit 1, minWin=26, winSum=426
3000 08:13:50.940093 TX Vref=24, minBit 0, minWin=26, winSum=424
3001 08:13:50.943105 TX Vref=26, minBit 0, minWin=26, winSum=426
3002 08:13:50.946692 TX Vref=28, minBit 13, minWin=26, winSum=434
3003 08:13:50.949596 TX Vref=30, minBit 10, minWin=26, winSum=432
3004 08:13:50.956373 TX Vref=32, minBit 10, minWin=26, winSum=432
3005 08:13:50.959908 [TxChooseVref] Worse bit 13, Min win 26, Win sum 434, Final Vref 28
3006 08:13:50.960469
3007 08:13:50.962813 Final TX Range 1 Vref 28
3008 08:13:50.963298
3009 08:13:50.963664 ==
3010 08:13:50.966239 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 08:13:50.972800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 08:13:50.973392 ==
3013 08:13:50.973772
3014 08:13:50.974108
3015 08:13:50.974436 TX Vref Scan disable
3016 08:13:50.976971 == TX Byte 0 ==
3017 08:13:50.979800 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3018 08:13:50.986911 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3019 08:13:50.987476 == TX Byte 1 ==
3020 08:13:50.990324 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3021 08:13:50.996278 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3022 08:13:50.996858
3023 08:13:50.997227 [DATLAT]
3024 08:13:50.997654 Freq=1200, CH0 RK1
3025 08:13:50.998005
3026 08:13:51.000179 DATLAT Default: 0xd
3027 08:13:51.000743 0, 0xFFFF, sum = 0
3028 08:13:51.002928 1, 0xFFFF, sum = 0
3029 08:13:51.006302 2, 0xFFFF, sum = 0
3030 08:13:51.006867 3, 0xFFFF, sum = 0
3031 08:13:51.009519 4, 0xFFFF, sum = 0
3032 08:13:51.010191 5, 0xFFFF, sum = 0
3033 08:13:51.012887 6, 0xFFFF, sum = 0
3034 08:13:51.013387 7, 0xFFFF, sum = 0
3035 08:13:51.016277 8, 0xFFFF, sum = 0
3036 08:13:51.016847 9, 0xFFFF, sum = 0
3037 08:13:51.019256 10, 0xFFFF, sum = 0
3038 08:13:51.019727 11, 0xFFFF, sum = 0
3039 08:13:51.022570 12, 0x0, sum = 1
3040 08:13:51.023039 13, 0x0, sum = 2
3041 08:13:51.026075 14, 0x0, sum = 3
3042 08:13:51.026644 15, 0x0, sum = 4
3043 08:13:51.029586 best_step = 13
3044 08:13:51.030140
3045 08:13:51.030505 ==
3046 08:13:51.032603 Dram Type= 6, Freq= 0, CH_0, rank 1
3047 08:13:51.036359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3048 08:13:51.036922 ==
3049 08:13:51.039345 RX Vref Scan: 0
3050 08:13:51.039906
3051 08:13:51.040345 RX Vref 0 -> 0, step: 1
3052 08:13:51.040706
3053 08:13:51.042588 RX Delay -21 -> 252, step: 4
3054 08:13:51.049132 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3055 08:13:51.052361 iDelay=195, Bit 1, Center 120 (47 ~ 194) 148
3056 08:13:51.055485 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3057 08:13:51.059259 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3058 08:13:51.061951 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3059 08:13:51.068935 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3060 08:13:51.071923 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3061 08:13:51.075350 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3062 08:13:51.079259 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3063 08:13:51.081817 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3064 08:13:51.088827 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3065 08:13:51.092643 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3066 08:13:51.095757 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3067 08:13:51.098558 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3068 08:13:51.102124 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3069 08:13:51.108761 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3070 08:13:51.109327 ==
3071 08:13:51.112332 Dram Type= 6, Freq= 0, CH_0, rank 1
3072 08:13:51.115663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 08:13:51.116259 ==
3074 08:13:51.116641 DQS Delay:
3075 08:13:51.118300 DQS0 = 0, DQS1 = 0
3076 08:13:51.118760 DQM Delay:
3077 08:13:51.121728 DQM0 = 116, DQM1 = 108
3078 08:13:51.122288 DQ Delay:
3079 08:13:51.125097 DQ0 =114, DQ1 =120, DQ2 =110, DQ3 =112
3080 08:13:51.128728 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3081 08:13:51.131798 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =102
3082 08:13:51.137865 DQ12 =116, DQ13 =114, DQ14 =120, DQ15 =116
3083 08:13:51.138422
3084 08:13:51.138790
3085 08:13:51.144836 [DQSOSCAuto] RK1, (LSB)MR18= 0x8e3, (MSB)MR19= 0x403, tDQSOscB0 = 422 ps tDQSOscB1 = 406 ps
3086 08:13:51.148601 CH0 RK1: MR19=403, MR18=8E3
3087 08:13:51.154889 CH0_RK1: MR19=0x403, MR18=0x8E3, DQSOSC=406, MR23=63, INC=39, DEC=26
3088 08:13:51.158391 [RxdqsGatingPostProcess] freq 1200
3089 08:13:51.161473 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3090 08:13:51.165063 best DQS0 dly(2T, 0.5T) = (0, 11)
3091 08:13:51.167635 best DQS1 dly(2T, 0.5T) = (0, 12)
3092 08:13:51.171124 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3093 08:13:51.174560 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3094 08:13:51.177525 best DQS0 dly(2T, 0.5T) = (0, 11)
3095 08:13:51.180968 best DQS1 dly(2T, 0.5T) = (0, 12)
3096 08:13:51.184419 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3097 08:13:51.187665 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3098 08:13:51.191001 Pre-setting of DQS Precalculation
3099 08:13:51.194228 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3100 08:13:51.194794 ==
3101 08:13:51.197928 Dram Type= 6, Freq= 0, CH_1, rank 0
3102 08:13:51.204144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3103 08:13:51.204731 ==
3104 08:13:51.207131 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3105 08:13:51.214017 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3106 08:13:51.222592 [CA 0] Center 37 (7~68) winsize 62
3107 08:13:51.225891 [CA 1] Center 38 (8~68) winsize 61
3108 08:13:51.229180 [CA 2] Center 34 (4~64) winsize 61
3109 08:13:51.232861 [CA 3] Center 33 (3~64) winsize 62
3110 08:13:51.236117 [CA 4] Center 34 (4~64) winsize 61
3111 08:13:51.238950 [CA 5] Center 33 (3~64) winsize 62
3112 08:13:51.239418
3113 08:13:51.242380 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3114 08:13:51.242847
3115 08:13:51.245666 [CATrainingPosCal] consider 1 rank data
3116 08:13:51.249371 u2DelayCellTimex100 = 270/100 ps
3117 08:13:51.252384 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3118 08:13:51.259087 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3119 08:13:51.262273 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3120 08:13:51.265725 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3121 08:13:51.268997 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3122 08:13:51.272159 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3123 08:13:51.272627
3124 08:13:51.275349 CA PerBit enable=1, Macro0, CA PI delay=33
3125 08:13:51.275775
3126 08:13:51.279030 [CBTSetCACLKResult] CA Dly = 33
3127 08:13:51.279678 CS Dly: 6 (0~37)
3128 08:13:51.281886 ==
3129 08:13:51.285434 Dram Type= 6, Freq= 0, CH_1, rank 1
3130 08:13:51.288829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 08:13:51.289268 ==
3132 08:13:51.295577 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3133 08:13:51.298768 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3134 08:13:51.308415 [CA 0] Center 38 (8~68) winsize 61
3135 08:13:51.311271 [CA 1] Center 37 (7~68) winsize 62
3136 08:13:51.315185 [CA 2] Center 34 (4~65) winsize 62
3137 08:13:51.318343 [CA 3] Center 34 (3~65) winsize 63
3138 08:13:51.321611 [CA 4] Center 34 (4~64) winsize 61
3139 08:13:51.324684 [CA 5] Center 33 (3~64) winsize 62
3140 08:13:51.325101
3141 08:13:51.328048 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3142 08:13:51.328467
3143 08:13:51.331520 [CATrainingPosCal] consider 2 rank data
3144 08:13:51.334414 u2DelayCellTimex100 = 270/100 ps
3145 08:13:51.337924 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3146 08:13:51.344706 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3147 08:13:51.347660 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3148 08:13:51.350858 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3149 08:13:51.354660 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3150 08:13:51.358046 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3151 08:13:51.358564
3152 08:13:51.361080 CA PerBit enable=1, Macro0, CA PI delay=33
3153 08:13:51.361753
3154 08:13:51.364633 [CBTSetCACLKResult] CA Dly = 33
3155 08:13:51.367530 CS Dly: 7 (0~40)
3156 08:13:51.367945
3157 08:13:51.371118 ----->DramcWriteLeveling(PI) begin...
3158 08:13:51.371565 ==
3159 08:13:51.374284 Dram Type= 6, Freq= 0, CH_1, rank 0
3160 08:13:51.377809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3161 08:13:51.378228 ==
3162 08:13:51.381100 Write leveling (Byte 0): 25 => 25
3163 08:13:51.384420 Write leveling (Byte 1): 27 => 27
3164 08:13:51.387992 DramcWriteLeveling(PI) end<-----
3165 08:13:51.388501
3166 08:13:51.388835 ==
3167 08:13:51.390774 Dram Type= 6, Freq= 0, CH_1, rank 0
3168 08:13:51.394240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3169 08:13:51.394661 ==
3170 08:13:51.397773 [Gating] SW mode calibration
3171 08:13:51.404635 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3172 08:13:51.410983 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3173 08:13:51.413935 0 15 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
3174 08:13:51.417979 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3175 08:13:51.424184 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 08:13:51.427652 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 08:13:51.430989 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 08:13:51.437368 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 08:13:51.440773 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
3180 08:13:51.444409 0 15 28 | B1->B0 | 2b2b 2424 | 0 0 | (1 0) (0 0)
3181 08:13:51.450465 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 08:13:51.454321 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 08:13:51.457121 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 08:13:51.463505 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 08:13:51.467395 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 08:13:51.470153 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 08:13:51.477123 1 0 24 | B1->B0 | 2727 3838 | 0 0 | (0 0) (0 0)
3188 08:13:51.480411 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 08:13:51.483399 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 08:13:51.490168 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 08:13:51.493685 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 08:13:51.496560 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 08:13:51.503371 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 08:13:51.506761 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 08:13:51.509792 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3196 08:13:51.516824 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3197 08:13:51.520107 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3198 08:13:51.523451 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 08:13:51.529954 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 08:13:51.533393 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 08:13:51.536570 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 08:13:51.542661 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 08:13:51.545987 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 08:13:51.549740 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 08:13:51.556678 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 08:13:51.560114 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 08:13:51.562783 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 08:13:51.569782 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 08:13:51.572486 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 08:13:51.576548 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 08:13:51.582716 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3212 08:13:51.585911 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3213 08:13:51.589412 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 08:13:51.592605 Total UI for P1: 0, mck2ui 16
3215 08:13:51.595905 best dqsien dly found for B0: ( 1, 3, 26)
3216 08:13:51.599281 Total UI for P1: 0, mck2ui 16
3217 08:13:51.602281 best dqsien dly found for B1: ( 1, 3, 28)
3218 08:13:51.605663 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3219 08:13:51.609570 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3220 08:13:51.610129
3221 08:13:51.612668 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3222 08:13:51.618962 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3223 08:13:51.619516 [Gating] SW calibration Done
3224 08:13:51.619923 ==
3225 08:13:51.622749 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 08:13:51.629770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 08:13:51.630332 ==
3228 08:13:51.630698 RX Vref Scan: 0
3229 08:13:51.631037
3230 08:13:51.632930 RX Vref 0 -> 0, step: 1
3231 08:13:51.633542
3232 08:13:51.636133 RX Delay -40 -> 252, step: 8
3233 08:13:51.639151 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3234 08:13:51.642427 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3235 08:13:51.645707 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3236 08:13:51.652632 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3237 08:13:51.655680 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3238 08:13:51.659010 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3239 08:13:51.662427 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3240 08:13:51.665795 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3241 08:13:51.671793 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3242 08:13:51.675496 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3243 08:13:51.679112 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3244 08:13:51.681979 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3245 08:13:51.685599 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3246 08:13:51.692202 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3247 08:13:51.695226 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3248 08:13:51.698099 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3249 08:13:51.698568 ==
3250 08:13:51.701819 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 08:13:51.705127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 08:13:51.708074 ==
3253 08:13:51.708541 DQS Delay:
3254 08:13:51.708909 DQS0 = 0, DQS1 = 0
3255 08:13:51.711974 DQM Delay:
3256 08:13:51.712558 DQM0 = 118, DQM1 = 110
3257 08:13:51.715088 DQ Delay:
3258 08:13:51.718032 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =115
3259 08:13:51.721635 DQ4 =111, DQ5 =131, DQ6 =127, DQ7 =115
3260 08:13:51.724676 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =99
3261 08:13:51.728150 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3262 08:13:51.728760
3263 08:13:51.729130
3264 08:13:51.729513 ==
3265 08:13:51.730948 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 08:13:51.734418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 08:13:51.734989 ==
3268 08:13:51.738055
3269 08:13:51.738516
3270 08:13:51.738882 TX Vref Scan disable
3271 08:13:51.741416 == TX Byte 0 ==
3272 08:13:51.744664 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3273 08:13:51.748066 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3274 08:13:51.751346 == TX Byte 1 ==
3275 08:13:51.754775 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3276 08:13:51.758274 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3277 08:13:51.759007 ==
3278 08:13:51.761273 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 08:13:51.767735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 08:13:51.768298 ==
3281 08:13:51.778016 TX Vref=22, minBit 8, minWin=25, winSum=419
3282 08:13:51.782034 TX Vref=24, minBit 9, minWin=25, winSum=423
3283 08:13:51.784749 TX Vref=26, minBit 10, minWin=25, winSum=430
3284 08:13:51.788519 TX Vref=28, minBit 10, minWin=26, winSum=435
3285 08:13:51.791515 TX Vref=30, minBit 8, minWin=26, winSum=434
3286 08:13:51.798310 TX Vref=32, minBit 15, minWin=25, winSum=428
3287 08:13:51.801187 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 28
3288 08:13:51.801810
3289 08:13:51.804623 Final TX Range 1 Vref 28
3290 08:13:51.805182
3291 08:13:51.805693 ==
3292 08:13:51.807705 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 08:13:51.814517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3294 08:13:51.814987 ==
3295 08:13:51.815350
3296 08:13:51.815684
3297 08:13:51.816009 TX Vref Scan disable
3298 08:13:51.817921 == TX Byte 0 ==
3299 08:13:51.821442 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3300 08:13:51.828433 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3301 08:13:51.828895 == TX Byte 1 ==
3302 08:13:51.831179 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3303 08:13:51.838051 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3304 08:13:51.838630
3305 08:13:51.839003 [DATLAT]
3306 08:13:51.839345 Freq=1200, CH1 RK0
3307 08:13:51.839676
3308 08:13:51.841641 DATLAT Default: 0xd
3309 08:13:51.844480 0, 0xFFFF, sum = 0
3310 08:13:51.844952 1, 0xFFFF, sum = 0
3311 08:13:51.848178 2, 0xFFFF, sum = 0
3312 08:13:51.848793 3, 0xFFFF, sum = 0
3313 08:13:51.851161 4, 0xFFFF, sum = 0
3314 08:13:51.851624 5, 0xFFFF, sum = 0
3315 08:13:51.854657 6, 0xFFFF, sum = 0
3316 08:13:51.855328 7, 0xFFFF, sum = 0
3317 08:13:51.857921 8, 0xFFFF, sum = 0
3318 08:13:51.858499 9, 0xFFFF, sum = 0
3319 08:13:51.861159 10, 0xFFFF, sum = 0
3320 08:13:51.861673 11, 0xFFFF, sum = 0
3321 08:13:51.864338 12, 0x0, sum = 1
3322 08:13:51.864824 13, 0x0, sum = 2
3323 08:13:51.868499 14, 0x0, sum = 3
3324 08:13:51.868970 15, 0x0, sum = 4
3325 08:13:51.871296 best_step = 13
3326 08:13:51.871751
3327 08:13:51.872109 ==
3328 08:13:51.874693 Dram Type= 6, Freq= 0, CH_1, rank 0
3329 08:13:51.877641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3330 08:13:51.878102 ==
3331 08:13:51.881298 RX Vref Scan: 1
3332 08:13:51.881799
3333 08:13:51.882198 Set Vref Range= 32 -> 127
3334 08:13:51.882570
3335 08:13:51.884250 RX Vref 32 -> 127, step: 1
3336 08:13:51.884707
3337 08:13:51.888100 RX Delay -21 -> 252, step: 4
3338 08:13:51.888667
3339 08:13:51.891117 Set Vref, RX VrefLevel [Byte0]: 32
3340 08:13:51.893968 [Byte1]: 32
3341 08:13:51.894428
3342 08:13:51.897406 Set Vref, RX VrefLevel [Byte0]: 33
3343 08:13:51.900905 [Byte1]: 33
3344 08:13:51.905286
3345 08:13:51.905926 Set Vref, RX VrefLevel [Byte0]: 34
3346 08:13:51.908227 [Byte1]: 34
3347 08:13:51.912750
3348 08:13:51.913367 Set Vref, RX VrefLevel [Byte0]: 35
3349 08:13:51.915964 [Byte1]: 35
3350 08:13:51.920763
3351 08:13:51.921380 Set Vref, RX VrefLevel [Byte0]: 36
3352 08:13:51.924214 [Byte1]: 36
3353 08:13:51.928648
3354 08:13:51.929201 Set Vref, RX VrefLevel [Byte0]: 37
3355 08:13:51.932275 [Byte1]: 37
3356 08:13:51.936620
3357 08:13:51.937170 Set Vref, RX VrefLevel [Byte0]: 38
3358 08:13:51.940151 [Byte1]: 38
3359 08:13:51.944310
3360 08:13:51.944862 Set Vref, RX VrefLevel [Byte0]: 39
3361 08:13:51.947823 [Byte1]: 39
3362 08:13:51.952830
3363 08:13:51.953429 Set Vref, RX VrefLevel [Byte0]: 40
3364 08:13:51.955577 [Byte1]: 40
3365 08:13:51.960113
3366 08:13:51.960665 Set Vref, RX VrefLevel [Byte0]: 41
3367 08:13:51.963818 [Byte1]: 41
3368 08:13:51.968569
3369 08:13:51.969150 Set Vref, RX VrefLevel [Byte0]: 42
3370 08:13:51.972026 [Byte1]: 42
3371 08:13:51.976340
3372 08:13:51.976911 Set Vref, RX VrefLevel [Byte0]: 43
3373 08:13:51.979428 [Byte1]: 43
3374 08:13:51.984193
3375 08:13:51.984650 Set Vref, RX VrefLevel [Byte0]: 44
3376 08:13:51.987656 [Byte1]: 44
3377 08:13:51.992124
3378 08:13:51.995293 Set Vref, RX VrefLevel [Byte0]: 45
3379 08:13:51.998698 [Byte1]: 45
3380 08:13:51.999310
3381 08:13:52.001676 Set Vref, RX VrefLevel [Byte0]: 46
3382 08:13:52.004927 [Byte1]: 46
3383 08:13:52.005421
3384 08:13:52.008424 Set Vref, RX VrefLevel [Byte0]: 47
3385 08:13:52.011928 [Byte1]: 47
3386 08:13:52.015813
3387 08:13:52.016324 Set Vref, RX VrefLevel [Byte0]: 48
3388 08:13:52.019416 [Byte1]: 48
3389 08:13:52.023802
3390 08:13:52.024361 Set Vref, RX VrefLevel [Byte0]: 49
3391 08:13:52.027071 [Byte1]: 49
3392 08:13:52.031849
3393 08:13:52.032419 Set Vref, RX VrefLevel [Byte0]: 50
3394 08:13:52.035185 [Byte1]: 50
3395 08:13:52.039642
3396 08:13:52.040198 Set Vref, RX VrefLevel [Byte0]: 51
3397 08:13:52.042625 [Byte1]: 51
3398 08:13:52.047453
3399 08:13:52.048006 Set Vref, RX VrefLevel [Byte0]: 52
3400 08:13:52.050815 [Byte1]: 52
3401 08:13:52.055158
3402 08:13:52.055707 Set Vref, RX VrefLevel [Byte0]: 53
3403 08:13:52.061686 [Byte1]: 53
3404 08:13:52.062301
3405 08:13:52.064905 Set Vref, RX VrefLevel [Byte0]: 54
3406 08:13:52.068688 [Byte1]: 54
3407 08:13:52.069249
3408 08:13:52.071743 Set Vref, RX VrefLevel [Byte0]: 55
3409 08:13:52.074554 [Byte1]: 55
3410 08:13:52.078741
3411 08:13:52.079295 Set Vref, RX VrefLevel [Byte0]: 56
3412 08:13:52.082138 [Byte1]: 56
3413 08:13:52.086654
3414 08:13:52.087113 Set Vref, RX VrefLevel [Byte0]: 57
3415 08:13:52.090413 [Byte1]: 57
3416 08:13:52.094651
3417 08:13:52.095165 Set Vref, RX VrefLevel [Byte0]: 58
3418 08:13:52.097897 [Byte1]: 58
3419 08:13:52.102606
3420 08:13:52.103181 Set Vref, RX VrefLevel [Byte0]: 59
3421 08:13:52.105814 [Byte1]: 59
3422 08:13:52.110624
3423 08:13:52.111186 Set Vref, RX VrefLevel [Byte0]: 60
3424 08:13:52.113950 [Byte1]: 60
3425 08:13:52.118596
3426 08:13:52.119215 Set Vref, RX VrefLevel [Byte0]: 61
3427 08:13:52.121793 [Byte1]: 61
3428 08:13:52.126462
3429 08:13:52.127119 Set Vref, RX VrefLevel [Byte0]: 62
3430 08:13:52.129631 [Byte1]: 62
3431 08:13:52.134612
3432 08:13:52.135178 Set Vref, RX VrefLevel [Byte0]: 63
3433 08:13:52.137780 [Byte1]: 63
3434 08:13:52.142590
3435 08:13:52.143157 Set Vref, RX VrefLevel [Byte0]: 64
3436 08:13:52.145760 [Byte1]: 64
3437 08:13:52.150338
3438 08:13:52.150904 Set Vref, RX VrefLevel [Byte0]: 65
3439 08:13:52.154080 [Byte1]: 65
3440 08:13:52.158778
3441 08:13:52.159346 Set Vref, RX VrefLevel [Byte0]: 66
3442 08:13:52.161722 [Byte1]: 66
3443 08:13:52.166217
3444 08:13:52.166680 Final RX Vref Byte 0 = 51 to rank0
3445 08:13:52.169382 Final RX Vref Byte 1 = 51 to rank0
3446 08:13:52.172665 Final RX Vref Byte 0 = 51 to rank1
3447 08:13:52.175926 Final RX Vref Byte 1 = 51 to rank1==
3448 08:13:52.179362 Dram Type= 6, Freq= 0, CH_1, rank 0
3449 08:13:52.186131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3450 08:13:52.186603 ==
3451 08:13:52.186971 DQS Delay:
3452 08:13:52.189019 DQS0 = 0, DQS1 = 0
3453 08:13:52.189520 DQM Delay:
3454 08:13:52.192662 DQM0 = 115, DQM1 = 109
3455 08:13:52.193246 DQ Delay:
3456 08:13:52.195954 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =110
3457 08:13:52.199160 DQ4 =114, DQ5 =128, DQ6 =124, DQ7 =112
3458 08:13:52.202521 DQ8 =96, DQ9 =102, DQ10 =112, DQ11 =98
3459 08:13:52.205654 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =118
3460 08:13:52.206221
3461 08:13:52.206590
3462 08:13:52.215647 [DQSOSCAuto] RK0, (LSB)MR18= 0xfff3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 410 ps
3463 08:13:52.216216 CH1 RK0: MR19=303, MR18=FFF3
3464 08:13:52.221838 CH1_RK0: MR19=0x303, MR18=0xFFF3, DQSOSC=410, MR23=63, INC=39, DEC=26
3465 08:13:52.222304
3466 08:13:52.224808 ----->DramcWriteLeveling(PI) begin...
3467 08:13:52.228397 ==
3468 08:13:52.228889 Dram Type= 6, Freq= 0, CH_1, rank 1
3469 08:13:52.234804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3470 08:13:52.235277 ==
3471 08:13:52.238407 Write leveling (Byte 0): 26 => 26
3472 08:13:52.241420 Write leveling (Byte 1): 27 => 27
3473 08:13:52.244706 DramcWriteLeveling(PI) end<-----
3474 08:13:52.245032
3475 08:13:52.245290 ==
3476 08:13:52.248088 Dram Type= 6, Freq= 0, CH_1, rank 1
3477 08:13:52.251313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3478 08:13:52.251556 ==
3479 08:13:52.254402 [Gating] SW mode calibration
3480 08:13:52.260944 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3481 08:13:52.268348 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3482 08:13:52.270989 0 15 0 | B1->B0 | 3434 3231 | 0 1 | (0 0) (1 1)
3483 08:13:52.274401 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 08:13:52.280748 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 08:13:52.283898 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 08:13:52.287423 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 08:13:52.293677 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 08:13:52.297159 0 15 24 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 1)
3489 08:13:52.300765 0 15 28 | B1->B0 | 2323 2e2e | 1 1 | (1 0) (1 0)
3490 08:13:52.307021 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 08:13:52.310499 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 08:13:52.313480 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 08:13:52.320489 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 08:13:52.323962 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 08:13:52.327228 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 08:13:52.333372 1 0 24 | B1->B0 | 3b3b 2525 | 1 0 | (0 0) (0 0)
3497 08:13:52.336961 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3498 08:13:52.340201 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 08:13:52.346441 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 08:13:52.349932 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 08:13:52.353443 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 08:13:52.359698 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 08:13:52.363238 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 08:13:52.366618 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3505 08:13:52.373294 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3506 08:13:52.376279 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 08:13:52.379968 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 08:13:52.386447 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 08:13:52.389578 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 08:13:52.393238 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 08:13:52.399932 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 08:13:52.402677 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 08:13:52.406187 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 08:13:52.412629 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 08:13:52.416048 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 08:13:52.419182 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 08:13:52.425656 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 08:13:52.429005 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 08:13:52.432267 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 08:13:52.438936 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3521 08:13:52.442199 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3522 08:13:52.445350 Total UI for P1: 0, mck2ui 16
3523 08:13:52.448952 best dqsien dly found for B1: ( 1, 3, 24)
3524 08:13:52.452087 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 08:13:52.455767 Total UI for P1: 0, mck2ui 16
3526 08:13:52.458620 best dqsien dly found for B0: ( 1, 3, 26)
3527 08:13:52.461854 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3528 08:13:52.465310 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3529 08:13:52.465798
3530 08:13:52.471760 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3531 08:13:52.475084 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3532 08:13:52.478530 [Gating] SW calibration Done
3533 08:13:52.478967 ==
3534 08:13:52.481445 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 08:13:52.485126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 08:13:52.485594 ==
3537 08:13:52.485936 RX Vref Scan: 0
3538 08:13:52.486253
3539 08:13:52.488081 RX Vref 0 -> 0, step: 1
3540 08:13:52.488502
3541 08:13:52.491687 RX Delay -40 -> 252, step: 8
3542 08:13:52.494943 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3543 08:13:52.498186 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3544 08:13:52.504608 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3545 08:13:52.507892 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3546 08:13:52.511555 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3547 08:13:52.514503 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3548 08:13:52.518155 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3549 08:13:52.525067 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3550 08:13:52.527792 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3551 08:13:52.531191 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3552 08:13:52.534308 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
3553 08:13:52.537571 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3554 08:13:52.544461 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3555 08:13:52.547835 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3556 08:13:52.551118 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3557 08:13:52.554095 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3558 08:13:52.554568 ==
3559 08:13:52.557809 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 08:13:52.564266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 08:13:52.564844 ==
3562 08:13:52.565221 DQS Delay:
3563 08:13:52.567214 DQS0 = 0, DQS1 = 0
3564 08:13:52.567674 DQM Delay:
3565 08:13:52.571079 DQM0 = 116, DQM1 = 109
3566 08:13:52.571645 DQ Delay:
3567 08:13:52.573882 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3568 08:13:52.576899 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3569 08:13:52.580683 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
3570 08:13:52.583500 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3571 08:13:52.584046
3572 08:13:52.584416
3573 08:13:52.584821 ==
3574 08:13:52.587229 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 08:13:52.593874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 08:13:52.594426 ==
3577 08:13:52.594823
3578 08:13:52.595168
3579 08:13:52.595494 TX Vref Scan disable
3580 08:13:52.597117 == TX Byte 0 ==
3581 08:13:52.601041 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3582 08:13:52.607415 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3583 08:13:52.607979 == TX Byte 1 ==
3584 08:13:52.610013 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3585 08:13:52.616942 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3586 08:13:52.617583 ==
3587 08:13:52.620347 Dram Type= 6, Freq= 0, CH_1, rank 1
3588 08:13:52.623632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3589 08:13:52.624193 ==
3590 08:13:52.635331 TX Vref=22, minBit 1, minWin=26, winSum=423
3591 08:13:52.638278 TX Vref=24, minBit 9, minWin=26, winSum=429
3592 08:13:52.641793 TX Vref=26, minBit 8, minWin=26, winSum=428
3593 08:13:52.644773 TX Vref=28, minBit 9, minWin=26, winSum=432
3594 08:13:52.647999 TX Vref=30, minBit 8, minWin=26, winSum=427
3595 08:13:52.654931 TX Vref=32, minBit 8, minWin=26, winSum=428
3596 08:13:52.658105 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 28
3597 08:13:52.658668
3598 08:13:52.661143 Final TX Range 1 Vref 28
3599 08:13:52.661683
3600 08:13:52.662047 ==
3601 08:13:52.664609 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 08:13:52.668361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 08:13:52.671188 ==
3604 08:13:52.671737
3605 08:13:52.672105
3606 08:13:52.672443 TX Vref Scan disable
3607 08:13:52.674458 == TX Byte 0 ==
3608 08:13:52.677377 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3609 08:13:52.684135 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3610 08:13:52.684599 == TX Byte 1 ==
3611 08:13:52.687825 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3612 08:13:52.694343 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3613 08:13:52.694808
3614 08:13:52.695173 [DATLAT]
3615 08:13:52.695540 Freq=1200, CH1 RK1
3616 08:13:52.695874
3617 08:13:52.697556 DATLAT Default: 0xd
3618 08:13:52.700499 0, 0xFFFF, sum = 0
3619 08:13:52.700970 1, 0xFFFF, sum = 0
3620 08:13:52.704146 2, 0xFFFF, sum = 0
3621 08:13:52.704569 3, 0xFFFF, sum = 0
3622 08:13:52.707280 4, 0xFFFF, sum = 0
3623 08:13:52.707738 5, 0xFFFF, sum = 0
3624 08:13:52.711053 6, 0xFFFF, sum = 0
3625 08:13:52.711657 7, 0xFFFF, sum = 0
3626 08:13:52.713898 8, 0xFFFF, sum = 0
3627 08:13:52.714321 9, 0xFFFF, sum = 0
3628 08:13:52.717520 10, 0xFFFF, sum = 0
3629 08:13:52.718055 11, 0xFFFF, sum = 0
3630 08:13:52.720625 12, 0x0, sum = 1
3631 08:13:52.721147 13, 0x0, sum = 2
3632 08:13:52.724045 14, 0x0, sum = 3
3633 08:13:52.724467 15, 0x0, sum = 4
3634 08:13:52.727205 best_step = 13
3635 08:13:52.727619
3636 08:13:52.727947 ==
3637 08:13:52.730437 Dram Type= 6, Freq= 0, CH_1, rank 1
3638 08:13:52.733938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3639 08:13:52.734361 ==
3640 08:13:52.737258 RX Vref Scan: 0
3641 08:13:52.737821
3642 08:13:52.738155 RX Vref 0 -> 0, step: 1
3643 08:13:52.738466
3644 08:13:52.740609 RX Delay -21 -> 252, step: 4
3645 08:13:52.747055 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3646 08:13:52.750072 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3647 08:13:52.753938 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3648 08:13:52.756637 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3649 08:13:52.763423 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3650 08:13:52.766867 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3651 08:13:52.770204 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3652 08:13:52.773893 iDelay=199, Bit 7, Center 114 (47 ~ 182) 136
3653 08:13:52.776857 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3654 08:13:52.779941 iDelay=199, Bit 9, Center 98 (35 ~ 162) 128
3655 08:13:52.785994 iDelay=199, Bit 10, Center 108 (43 ~ 174) 132
3656 08:13:52.790124 iDelay=199, Bit 11, Center 98 (35 ~ 162) 128
3657 08:13:52.793005 iDelay=199, Bit 12, Center 120 (51 ~ 190) 140
3658 08:13:52.796508 iDelay=199, Bit 13, Center 116 (51 ~ 182) 132
3659 08:13:52.803028 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
3660 08:13:52.806139 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3661 08:13:52.806692 ==
3662 08:13:52.809389 Dram Type= 6, Freq= 0, CH_1, rank 1
3663 08:13:52.812712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3664 08:13:52.813174 ==
3665 08:13:52.816371 DQS Delay:
3666 08:13:52.816923 DQS0 = 0, DQS1 = 0
3667 08:13:52.817293 DQM Delay:
3668 08:13:52.819487 DQM0 = 116, DQM1 = 108
3669 08:13:52.819946 DQ Delay:
3670 08:13:52.822663 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =112
3671 08:13:52.825746 DQ4 =116, DQ5 =126, DQ6 =130, DQ7 =114
3672 08:13:52.828923 DQ8 =96, DQ9 =98, DQ10 =108, DQ11 =98
3673 08:13:52.835991 DQ12 =120, DQ13 =116, DQ14 =116, DQ15 =118
3674 08:13:52.836599
3675 08:13:52.836974
3676 08:13:52.842781 [DQSOSCAuto] RK1, (LSB)MR18= 0xefea, (MSB)MR19= 0x303, tDQSOscB0 = 419 ps tDQSOscB1 = 417 ps
3677 08:13:52.845320 CH1 RK1: MR19=303, MR18=EFEA
3678 08:13:52.852398 CH1_RK1: MR19=0x303, MR18=0xEFEA, DQSOSC=417, MR23=63, INC=37, DEC=25
3679 08:13:52.855901 [RxdqsGatingPostProcess] freq 1200
3680 08:13:52.859005 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3681 08:13:52.862310 best DQS0 dly(2T, 0.5T) = (0, 11)
3682 08:13:52.865881 best DQS1 dly(2T, 0.5T) = (0, 11)
3683 08:13:52.868838 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3684 08:13:52.872476 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3685 08:13:52.875808 best DQS0 dly(2T, 0.5T) = (0, 11)
3686 08:13:52.879128 best DQS1 dly(2T, 0.5T) = (0, 11)
3687 08:13:52.882103 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3688 08:13:52.885162 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3689 08:13:52.889364 Pre-setting of DQS Precalculation
3690 08:13:52.892309 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3691 08:13:52.902200 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3692 08:13:52.908518 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3693 08:13:52.909091
3694 08:13:52.909514
3695 08:13:52.912166 [Calibration Summary] 2400 Mbps
3696 08:13:52.912724 CH 0, Rank 0
3697 08:13:52.914856 SW Impedance : PASS
3698 08:13:52.915319 DUTY Scan : NO K
3699 08:13:52.918811 ZQ Calibration : PASS
3700 08:13:52.921600 Jitter Meter : NO K
3701 08:13:52.922176 CBT Training : PASS
3702 08:13:52.924994 Write leveling : PASS
3703 08:13:52.928317 RX DQS gating : PASS
3704 08:13:52.928923 RX DQ/DQS(RDDQC) : PASS
3705 08:13:52.931298 TX DQ/DQS : PASS
3706 08:13:52.935139 RX DATLAT : PASS
3707 08:13:52.935701 RX DQ/DQS(Engine): PASS
3708 08:13:52.938239 TX OE : NO K
3709 08:13:52.938814 All Pass.
3710 08:13:52.939192
3711 08:13:52.941502 CH 0, Rank 1
3712 08:13:52.942054 SW Impedance : PASS
3713 08:13:52.944874 DUTY Scan : NO K
3714 08:13:52.947720 ZQ Calibration : PASS
3715 08:13:52.948180 Jitter Meter : NO K
3716 08:13:52.950954 CBT Training : PASS
3717 08:13:52.954514 Write leveling : PASS
3718 08:13:52.955126 RX DQS gating : PASS
3719 08:13:52.957671 RX DQ/DQS(RDDQC) : PASS
3720 08:13:52.961532 TX DQ/DQS : PASS
3721 08:13:52.962085 RX DATLAT : PASS
3722 08:13:52.964264 RX DQ/DQS(Engine): PASS
3723 08:13:52.967592 TX OE : NO K
3724 08:13:52.968053 All Pass.
3725 08:13:52.968415
3726 08:13:52.968778 CH 1, Rank 0
3727 08:13:52.971308 SW Impedance : PASS
3728 08:13:52.974344 DUTY Scan : NO K
3729 08:13:52.974923 ZQ Calibration : PASS
3730 08:13:52.977372 Jitter Meter : NO K
3731 08:13:52.980860 CBT Training : PASS
3732 08:13:52.981321 Write leveling : PASS
3733 08:13:52.983882 RX DQS gating : PASS
3734 08:13:52.987076 RX DQ/DQS(RDDQC) : PASS
3735 08:13:52.987536 TX DQ/DQS : PASS
3736 08:13:52.990621 RX DATLAT : PASS
3737 08:13:52.994168 RX DQ/DQS(Engine): PASS
3738 08:13:52.994631 TX OE : NO K
3739 08:13:52.995003 All Pass.
3740 08:13:52.997038
3741 08:13:52.997543 CH 1, Rank 1
3742 08:13:53.000936 SW Impedance : PASS
3743 08:13:53.001545 DUTY Scan : NO K
3744 08:13:53.003840 ZQ Calibration : PASS
3745 08:13:53.004391 Jitter Meter : NO K
3746 08:13:53.007450 CBT Training : PASS
3747 08:13:53.010413 Write leveling : PASS
3748 08:13:53.010970 RX DQS gating : PASS
3749 08:13:53.014137 RX DQ/DQS(RDDQC) : PASS
3750 08:13:53.017057 TX DQ/DQS : PASS
3751 08:13:53.017669 RX DATLAT : PASS
3752 08:13:53.020832 RX DQ/DQS(Engine): PASS
3753 08:13:53.023670 TX OE : NO K
3754 08:13:53.024227 All Pass.
3755 08:13:53.024594
3756 08:13:53.026611 DramC Write-DBI off
3757 08:13:53.027074 PER_BANK_REFRESH: Hybrid Mode
3758 08:13:53.030242 TX_TRACKING: ON
3759 08:13:53.039976 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3760 08:13:53.043658 [FAST_K] Save calibration result to emmc
3761 08:13:53.046631 dramc_set_vcore_voltage set vcore to 650000
3762 08:13:53.047197 Read voltage for 600, 5
3763 08:13:53.050252 Vio18 = 0
3764 08:13:53.050808 Vcore = 650000
3765 08:13:53.051176 Vdram = 0
3766 08:13:53.053102 Vddq = 0
3767 08:13:53.053755 Vmddr = 0
3768 08:13:53.060131 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3769 08:13:53.063375 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3770 08:13:53.066402 MEM_TYPE=3, freq_sel=19
3771 08:13:53.070102 sv_algorithm_assistance_LP4_1600
3772 08:13:53.072680 ============ PULL DRAM RESETB DOWN ============
3773 08:13:53.076328 ========== PULL DRAM RESETB DOWN end =========
3774 08:13:53.082745 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3775 08:13:53.086445 ===================================
3776 08:13:53.086908 LPDDR4 DRAM CONFIGURATION
3777 08:13:53.089440 ===================================
3778 08:13:53.092773 EX_ROW_EN[0] = 0x0
3779 08:13:53.095934 EX_ROW_EN[1] = 0x0
3780 08:13:53.096485 LP4Y_EN = 0x0
3781 08:13:53.099222 WORK_FSP = 0x0
3782 08:13:53.099777 WL = 0x2
3783 08:13:53.102599 RL = 0x2
3784 08:13:53.103060 BL = 0x2
3785 08:13:53.106034 RPST = 0x0
3786 08:13:53.106494 RD_PRE = 0x0
3787 08:13:53.109158 WR_PRE = 0x1
3788 08:13:53.109663 WR_PST = 0x0
3789 08:13:53.112844 DBI_WR = 0x0
3790 08:13:53.113455 DBI_RD = 0x0
3791 08:13:53.115646 OTF = 0x1
3792 08:13:53.119374 ===================================
3793 08:13:53.122849 ===================================
3794 08:13:53.123410 ANA top config
3795 08:13:53.125998 ===================================
3796 08:13:53.128992 DLL_ASYNC_EN = 0
3797 08:13:53.131847 ALL_SLAVE_EN = 1
3798 08:13:53.135686 NEW_RANK_MODE = 1
3799 08:13:53.136250 DLL_IDLE_MODE = 1
3800 08:13:53.138808 LP45_APHY_COMB_EN = 1
3801 08:13:53.142032 TX_ODT_DIS = 1
3802 08:13:53.145724 NEW_8X_MODE = 1
3803 08:13:53.148914 ===================================
3804 08:13:53.152112 ===================================
3805 08:13:53.155743 data_rate = 1200
3806 08:13:53.158796 CKR = 1
3807 08:13:53.159355 DQ_P2S_RATIO = 8
3808 08:13:53.161749 ===================================
3809 08:13:53.165172 CA_P2S_RATIO = 8
3810 08:13:53.168357 DQ_CA_OPEN = 0
3811 08:13:53.171781 DQ_SEMI_OPEN = 0
3812 08:13:53.175434 CA_SEMI_OPEN = 0
3813 08:13:53.177907 CA_FULL_RATE = 0
3814 08:13:53.178403 DQ_CKDIV4_EN = 1
3815 08:13:53.181255 CA_CKDIV4_EN = 1
3816 08:13:53.184813 CA_PREDIV_EN = 0
3817 08:13:53.188656 PH8_DLY = 0
3818 08:13:53.191296 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3819 08:13:53.194982 DQ_AAMCK_DIV = 4
3820 08:13:53.195537 CA_AAMCK_DIV = 4
3821 08:13:53.198016 CA_ADMCK_DIV = 4
3822 08:13:53.201242 DQ_TRACK_CA_EN = 0
3823 08:13:53.204507 CA_PICK = 600
3824 08:13:53.207676 CA_MCKIO = 600
3825 08:13:53.211238 MCKIO_SEMI = 0
3826 08:13:53.214560 PLL_FREQ = 2288
3827 08:13:53.217708 DQ_UI_PI_RATIO = 32
3828 08:13:53.218173 CA_UI_PI_RATIO = 0
3829 08:13:53.221022 ===================================
3830 08:13:53.224589 ===================================
3831 08:13:53.227718 memory_type:LPDDR4
3832 08:13:53.231074 GP_NUM : 10
3833 08:13:53.231638 SRAM_EN : 1
3834 08:13:53.234020 MD32_EN : 0
3835 08:13:53.237845 ===================================
3836 08:13:53.240670 [ANA_INIT] >>>>>>>>>>>>>>
3837 08:13:53.244316 <<<<<< [CONFIGURE PHASE]: ANA_TX
3838 08:13:53.247070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3839 08:13:53.250053 ===================================
3840 08:13:53.253763 data_rate = 1200,PCW = 0X5800
3841 08:13:53.256989 ===================================
3842 08:13:53.260199 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3843 08:13:53.263607 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3844 08:13:53.270706 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3845 08:13:53.273613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3846 08:13:53.277021 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3847 08:13:53.279771 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3848 08:13:53.283781 [ANA_INIT] flow start
3849 08:13:53.286470 [ANA_INIT] PLL >>>>>>>>
3850 08:13:53.286931 [ANA_INIT] PLL <<<<<<<<
3851 08:13:53.289697 [ANA_INIT] MIDPI >>>>>>>>
3852 08:13:53.293280 [ANA_INIT] MIDPI <<<<<<<<
3853 08:13:53.296942 [ANA_INIT] DLL >>>>>>>>
3854 08:13:53.297556 [ANA_INIT] flow end
3855 08:13:53.299915 ============ LP4 DIFF to SE enter ============
3856 08:13:53.306396 ============ LP4 DIFF to SE exit ============
3857 08:13:53.306973 [ANA_INIT] <<<<<<<<<<<<<
3858 08:13:53.309515 [Flow] Enable top DCM control >>>>>
3859 08:13:53.312942 [Flow] Enable top DCM control <<<<<
3860 08:13:53.316367 Enable DLL master slave shuffle
3861 08:13:53.322774 ==============================================================
3862 08:13:53.323459 Gating Mode config
3863 08:13:53.329693 ==============================================================
3864 08:13:53.332734 Config description:
3865 08:13:53.342397 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3866 08:13:53.349108 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3867 08:13:53.352702 SELPH_MODE 0: By rank 1: By Phase
3868 08:13:53.358740 ==============================================================
3869 08:13:53.362034 GAT_TRACK_EN = 1
3870 08:13:53.365159 RX_GATING_MODE = 2
3871 08:13:53.368800 RX_GATING_TRACK_MODE = 2
3872 08:13:53.369397 SELPH_MODE = 1
3873 08:13:53.371828 PICG_EARLY_EN = 1
3874 08:13:53.374999 VALID_LAT_VALUE = 1
3875 08:13:53.381831 ==============================================================
3876 08:13:53.384886 Enter into Gating configuration >>>>
3877 08:13:53.388426 Exit from Gating configuration <<<<
3878 08:13:53.391648 Enter into DVFS_PRE_config >>>>>
3879 08:13:53.401377 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3880 08:13:53.405144 Exit from DVFS_PRE_config <<<<<
3881 08:13:53.408144 Enter into PICG configuration >>>>
3882 08:13:53.411554 Exit from PICG configuration <<<<
3883 08:13:53.414868 [RX_INPUT] configuration >>>>>
3884 08:13:53.418068 [RX_INPUT] configuration <<<<<
3885 08:13:53.424747 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3886 08:13:53.428008 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3887 08:13:53.434595 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3888 08:13:53.440841 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3889 08:13:53.447786 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3890 08:13:53.453970 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3891 08:13:53.457721 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3892 08:13:53.460672 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3893 08:13:53.464189 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3894 08:13:53.470519 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3895 08:13:53.474095 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3896 08:13:53.476947 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3897 08:13:53.480242 ===================================
3898 08:13:53.483220 LPDDR4 DRAM CONFIGURATION
3899 08:13:53.486922 ===================================
3900 08:13:53.490049 EX_ROW_EN[0] = 0x0
3901 08:13:53.490505 EX_ROW_EN[1] = 0x0
3902 08:13:53.493665 LP4Y_EN = 0x0
3903 08:13:53.494169 WORK_FSP = 0x0
3904 08:13:53.496533 WL = 0x2
3905 08:13:53.496993 RL = 0x2
3906 08:13:53.500222 BL = 0x2
3907 08:13:53.500785 RPST = 0x0
3908 08:13:53.503408 RD_PRE = 0x0
3909 08:13:53.503963 WR_PRE = 0x1
3910 08:13:53.506710 WR_PST = 0x0
3911 08:13:53.507172 DBI_WR = 0x0
3912 08:13:53.509786 DBI_RD = 0x0
3913 08:13:53.510247 OTF = 0x1
3914 08:13:53.512806 ===================================
3915 08:13:53.519962 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3916 08:13:53.523199 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3917 08:13:53.526395 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3918 08:13:53.530007 ===================================
3919 08:13:53.532700 LPDDR4 DRAM CONFIGURATION
3920 08:13:53.535723 ===================================
3921 08:13:53.539414 EX_ROW_EN[0] = 0x10
3922 08:13:53.539971 EX_ROW_EN[1] = 0x0
3923 08:13:53.542893 LP4Y_EN = 0x0
3924 08:13:53.543349 WORK_FSP = 0x0
3925 08:13:53.545691 WL = 0x2
3926 08:13:53.546150 RL = 0x2
3927 08:13:53.549103 BL = 0x2
3928 08:13:53.549611 RPST = 0x0
3929 08:13:53.552521 RD_PRE = 0x0
3930 08:13:53.552983 WR_PRE = 0x1
3931 08:13:53.555663 WR_PST = 0x0
3932 08:13:53.559347 DBI_WR = 0x0
3933 08:13:53.559943 DBI_RD = 0x0
3934 08:13:53.562273 OTF = 0x1
3935 08:13:53.565654 ===================================
3936 08:13:53.568698 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3937 08:13:53.574048 nWR fixed to 30
3938 08:13:53.577793 [ModeRegInit_LP4] CH0 RK0
3939 08:13:53.578362 [ModeRegInit_LP4] CH0 RK1
3940 08:13:53.581291 [ModeRegInit_LP4] CH1 RK0
3941 08:13:53.584011 [ModeRegInit_LP4] CH1 RK1
3942 08:13:53.584548 match AC timing 17
3943 08:13:53.590773 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3944 08:13:53.594084 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3945 08:13:53.597237 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3946 08:13:53.603359 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3947 08:13:53.606889 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3948 08:13:53.607310 ==
3949 08:13:53.610303 Dram Type= 6, Freq= 0, CH_0, rank 0
3950 08:13:53.613901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3951 08:13:53.614324 ==
3952 08:13:53.620501 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3953 08:13:53.626713 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3954 08:13:53.630464 [CA 0] Center 36 (6~66) winsize 61
3955 08:13:53.633450 [CA 1] Center 36 (6~66) winsize 61
3956 08:13:53.636857 [CA 2] Center 34 (4~65) winsize 62
3957 08:13:53.640241 [CA 3] Center 34 (4~65) winsize 62
3958 08:13:53.643775 [CA 4] Center 33 (3~64) winsize 62
3959 08:13:53.646896 [CA 5] Center 33 (3~64) winsize 62
3960 08:13:53.647361
3961 08:13:53.649865 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3962 08:13:53.650329
3963 08:13:53.653512 [CATrainingPosCal] consider 1 rank data
3964 08:13:53.656954 u2DelayCellTimex100 = 270/100 ps
3965 08:13:53.659714 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3966 08:13:53.663486 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3967 08:13:53.666234 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3968 08:13:53.673106 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3969 08:13:53.676199 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3970 08:13:53.679274 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3971 08:13:53.679740
3972 08:13:53.682946 CA PerBit enable=1, Macro0, CA PI delay=33
3973 08:13:53.683428
3974 08:13:53.686015 [CBTSetCACLKResult] CA Dly = 33
3975 08:13:53.686507 CS Dly: 5 (0~36)
3976 08:13:53.686935 ==
3977 08:13:53.689277 Dram Type= 6, Freq= 0, CH_0, rank 1
3978 08:13:53.695754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3979 08:13:53.696177 ==
3980 08:13:53.698786 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3981 08:13:53.705599 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3982 08:13:53.709369 [CA 0] Center 36 (6~66) winsize 61
3983 08:13:53.712745 [CA 1] Center 36 (6~66) winsize 61
3984 08:13:53.715722 [CA 2] Center 34 (3~65) winsize 63
3985 08:13:53.718906 [CA 3] Center 33 (3~64) winsize 62
3986 08:13:53.722763 [CA 4] Center 33 (3~64) winsize 62
3987 08:13:53.725575 [CA 5] Center 33 (2~64) winsize 63
3988 08:13:53.726001
3989 08:13:53.729252 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3990 08:13:53.729837
3991 08:13:53.732536 [CATrainingPosCal] consider 2 rank data
3992 08:13:53.735592 u2DelayCellTimex100 = 270/100 ps
3993 08:13:53.739042 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3994 08:13:53.745187 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3995 08:13:53.748311 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3996 08:13:53.751886 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3997 08:13:53.754810 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3998 08:13:53.758639 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3999 08:13:53.758721
4000 08:13:53.761891 CA PerBit enable=1, Macro0, CA PI delay=33
4001 08:13:53.762057
4002 08:13:53.765447 [CBTSetCACLKResult] CA Dly = 33
4003 08:13:53.768047 CS Dly: 6 (0~38)
4004 08:13:53.768183
4005 08:13:53.771505 ----->DramcWriteLeveling(PI) begin...
4006 08:13:53.771649 ==
4007 08:13:53.774955 Dram Type= 6, Freq= 0, CH_0, rank 0
4008 08:13:53.778436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4009 08:13:53.778624 ==
4010 08:13:53.781398 Write leveling (Byte 0): 32 => 32
4011 08:13:53.784698 Write leveling (Byte 1): 26 => 26
4012 08:13:53.788336 DramcWriteLeveling(PI) end<-----
4013 08:13:53.788494
4014 08:13:53.788601 ==
4015 08:13:53.791189 Dram Type= 6, Freq= 0, CH_0, rank 0
4016 08:13:53.795101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4017 08:13:53.795361 ==
4018 08:13:53.797944 [Gating] SW mode calibration
4019 08:13:53.804524 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4020 08:13:53.811713 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4021 08:13:53.814917 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4022 08:13:53.817873 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4023 08:13:53.824778 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4024 08:13:53.827739 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4025 08:13:53.831343 0 9 16 | B1->B0 | 2f2f 2828 | 1 1 | (1 1) (1 0)
4026 08:13:53.838261 0 9 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4027 08:13:53.841408 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 08:13:53.847928 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 08:13:53.850912 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 08:13:53.854325 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 08:13:53.861027 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 08:13:53.863962 0 10 12 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
4033 08:13:53.867569 0 10 16 | B1->B0 | 3030 4343 | 1 0 | (0 0) (0 0)
4034 08:13:53.874306 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4035 08:13:53.876993 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 08:13:53.880463 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 08:13:53.886863 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 08:13:53.892147 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 08:13:53.893504 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 08:13:53.899859 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4041 08:13:53.903051 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4042 08:13:53.906904 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 08:13:53.913089 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 08:13:53.916579 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 08:13:53.919472 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 08:13:53.926104 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 08:13:53.929449 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 08:13:53.932604 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 08:13:53.939337 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 08:13:53.942408 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 08:13:53.946337 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 08:13:53.952347 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 08:13:53.955840 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 08:13:53.959214 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 08:13:53.965784 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 08:13:53.968735 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4057 08:13:53.972402 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4058 08:13:53.978757 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 08:13:53.979365 Total UI for P1: 0, mck2ui 16
4060 08:13:53.985487 best dqsien dly found for B0: ( 0, 13, 14)
4061 08:13:53.986000 Total UI for P1: 0, mck2ui 16
4062 08:13:53.991773 best dqsien dly found for B1: ( 0, 13, 16)
4063 08:13:53.995384 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4064 08:13:53.998936 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4065 08:13:53.999414
4066 08:13:54.001711 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4067 08:13:54.005089 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4068 08:13:54.008768 [Gating] SW calibration Done
4069 08:13:54.009195 ==
4070 08:13:54.011825 Dram Type= 6, Freq= 0, CH_0, rank 0
4071 08:13:54.015519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4072 08:13:54.016049 ==
4073 08:13:54.018299 RX Vref Scan: 0
4074 08:13:54.018783
4075 08:13:54.021721 RX Vref 0 -> 0, step: 1
4076 08:13:54.022147
4077 08:13:54.022481 RX Delay -230 -> 252, step: 16
4078 08:13:54.028162 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4079 08:13:54.031882 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4080 08:13:54.034850 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4081 08:13:54.038030 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4082 08:13:54.044655 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4083 08:13:54.048174 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4084 08:13:54.051408 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4085 08:13:54.054343 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4086 08:13:54.061146 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4087 08:13:54.064386 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4088 08:13:54.067920 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4089 08:13:54.070827 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4090 08:13:54.077416 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4091 08:13:54.080547 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4092 08:13:54.083654 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4093 08:13:54.087140 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4094 08:13:54.087654 ==
4095 08:13:54.090865 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 08:13:54.097298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 08:13:54.097913 ==
4098 08:13:54.098286 DQS Delay:
4099 08:13:54.100600 DQS0 = 0, DQS1 = 0
4100 08:13:54.101161 DQM Delay:
4101 08:13:54.104061 DQM0 = 44, DQM1 = 32
4102 08:13:54.104665 DQ Delay:
4103 08:13:54.106749 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4104 08:13:54.110348 DQ4 =49, DQ5 =41, DQ6 =49, DQ7 =49
4105 08:13:54.113856 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4106 08:13:54.116552 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4107 08:13:54.117109
4108 08:13:54.117547
4109 08:13:54.117897 ==
4110 08:13:54.120392 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 08:13:54.123711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 08:13:54.124275 ==
4113 08:13:54.124665
4114 08:13:54.125006
4115 08:13:54.126766 TX Vref Scan disable
4116 08:13:54.130289 == TX Byte 0 ==
4117 08:13:54.133055 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4118 08:13:54.137035 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4119 08:13:54.140128 == TX Byte 1 ==
4120 08:13:54.143684 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4121 08:13:54.146395 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4122 08:13:54.146862 ==
4123 08:13:54.149714 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 08:13:54.156240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 08:13:54.156810 ==
4126 08:13:54.157183
4127 08:13:54.157580
4128 08:13:54.159619 TX Vref Scan disable
4129 08:13:54.160171 == TX Byte 0 ==
4130 08:13:54.166078 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4131 08:13:54.169646 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4132 08:13:54.170350 == TX Byte 1 ==
4133 08:13:54.176080 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4134 08:13:54.179189 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4135 08:13:54.179750
4136 08:13:54.180117 [DATLAT]
4137 08:13:54.182417 Freq=600, CH0 RK0
4138 08:13:54.182966
4139 08:13:54.183345 DATLAT Default: 0x9
4140 08:13:54.185966 0, 0xFFFF, sum = 0
4141 08:13:54.188905 1, 0xFFFF, sum = 0
4142 08:13:54.189527 2, 0xFFFF, sum = 0
4143 08:13:54.192037 3, 0xFFFF, sum = 0
4144 08:13:54.192507 4, 0xFFFF, sum = 0
4145 08:13:54.195961 5, 0xFFFF, sum = 0
4146 08:13:54.196433 6, 0xFFFF, sum = 0
4147 08:13:54.198686 7, 0xFFFF, sum = 0
4148 08:13:54.199157 8, 0x0, sum = 1
4149 08:13:54.201944 9, 0x0, sum = 2
4150 08:13:54.202417 10, 0x0, sum = 3
4151 08:13:54.205725 11, 0x0, sum = 4
4152 08:13:54.206286 best_step = 9
4153 08:13:54.206655
4154 08:13:54.207008 ==
4155 08:13:54.208704 Dram Type= 6, Freq= 0, CH_0, rank 0
4156 08:13:54.212241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 08:13:54.212740 ==
4158 08:13:54.215270 RX Vref Scan: 1
4159 08:13:54.215832
4160 08:13:54.218802 RX Vref 0 -> 0, step: 1
4161 08:13:54.219308
4162 08:13:54.219677 RX Delay -195 -> 252, step: 8
4163 08:13:54.220025
4164 08:13:54.222279 Set Vref, RX VrefLevel [Byte0]: 61
4165 08:13:54.225107 [Byte1]: 56
4166 08:13:54.229723
4167 08:13:54.230279 Final RX Vref Byte 0 = 61 to rank0
4168 08:13:54.233200 Final RX Vref Byte 1 = 56 to rank0
4169 08:13:54.236396 Final RX Vref Byte 0 = 61 to rank1
4170 08:13:54.240177 Final RX Vref Byte 1 = 56 to rank1==
4171 08:13:54.242950 Dram Type= 6, Freq= 0, CH_0, rank 0
4172 08:13:54.249703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 08:13:54.250272 ==
4174 08:13:54.250639 DQS Delay:
4175 08:13:54.253617 DQS0 = 0, DQS1 = 0
4176 08:13:54.254176 DQM Delay:
4177 08:13:54.254566 DQM0 = 44, DQM1 = 33
4178 08:13:54.256161 DQ Delay:
4179 08:13:54.259682 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4180 08:13:54.262878 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4181 08:13:54.265720 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4182 08:13:54.269203 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4183 08:13:54.269788
4184 08:13:54.270168
4185 08:13:54.275894 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c34, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
4186 08:13:54.279348 CH0 RK0: MR19=808, MR18=5C34
4187 08:13:54.285742 CH0_RK0: MR19=0x808, MR18=0x5C34, DQSOSC=392, MR23=63, INC=170, DEC=113
4188 08:13:54.286242
4189 08:13:54.289085 ----->DramcWriteLeveling(PI) begin...
4190 08:13:54.289618 ==
4191 08:13:54.292384 Dram Type= 6, Freq= 0, CH_0, rank 1
4192 08:13:54.295773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4193 08:13:54.296412 ==
4194 08:13:54.299027 Write leveling (Byte 0): 31 => 31
4195 08:13:54.302192 Write leveling (Byte 1): 31 => 31
4196 08:13:54.305271 DramcWriteLeveling(PI) end<-----
4197 08:13:54.305769
4198 08:13:54.306164 ==
4199 08:13:54.308804 Dram Type= 6, Freq= 0, CH_0, rank 1
4200 08:13:54.315723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 08:13:54.316270 ==
4202 08:13:54.316788 [Gating] SW mode calibration
4203 08:13:54.325463 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4204 08:13:54.328411 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4205 08:13:54.331679 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4206 08:13:54.338541 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4207 08:13:54.342039 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4208 08:13:54.345102 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4209 08:13:54.351771 0 9 16 | B1->B0 | 2f2f 2b2b | 0 0 | (0 0) (0 0)
4210 08:13:54.354798 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 08:13:54.358642 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 08:13:54.365139 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 08:13:54.368230 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 08:13:54.371505 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 08:13:54.378060 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 08:13:54.381758 0 10 12 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
4217 08:13:54.384626 0 10 16 | B1->B0 | 3636 4343 | 0 0 | (0 0) (0 0)
4218 08:13:54.390875 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 08:13:54.394114 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 08:13:54.397742 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 08:13:54.404723 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 08:13:54.407284 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 08:13:54.414401 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 08:13:54.417296 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4225 08:13:54.420705 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4226 08:13:54.424409 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 08:13:54.430579 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 08:13:54.433834 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 08:13:54.437502 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 08:13:54.443936 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 08:13:54.447179 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 08:13:54.453525 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 08:13:54.457370 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 08:13:54.460591 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 08:13:54.467136 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 08:13:54.470117 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 08:13:54.473788 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 08:13:54.480317 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 08:13:54.482998 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 08:13:54.486178 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4241 08:13:54.492704 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4242 08:13:54.493168 Total UI for P1: 0, mck2ui 16
4243 08:13:54.500064 best dqsien dly found for B1: ( 0, 13, 12)
4244 08:13:54.502878 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 08:13:54.506314 Total UI for P1: 0, mck2ui 16
4246 08:13:54.509600 best dqsien dly found for B0: ( 0, 13, 14)
4247 08:13:54.512484 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4248 08:13:54.515882 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4249 08:13:54.516434
4250 08:13:54.519232 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4251 08:13:54.522837 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4252 08:13:54.525661 [Gating] SW calibration Done
4253 08:13:54.526128 ==
4254 08:13:54.529914 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 08:13:54.532598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 08:13:54.535879 ==
4257 08:13:54.536347 RX Vref Scan: 0
4258 08:13:54.536715
4259 08:13:54.539673 RX Vref 0 -> 0, step: 1
4260 08:13:54.540235
4261 08:13:54.542084 RX Delay -230 -> 252, step: 16
4262 08:13:54.545910 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4263 08:13:54.548920 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4264 08:13:54.552230 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4265 08:13:54.559165 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4266 08:13:54.562358 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4267 08:13:54.565620 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4268 08:13:54.568926 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4269 08:13:54.575388 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4270 08:13:54.579024 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4271 08:13:54.581812 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4272 08:13:54.585383 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4273 08:13:54.592051 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4274 08:13:54.595363 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4275 08:13:54.598061 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4276 08:13:54.601676 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4277 08:13:54.608337 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4278 08:13:54.608922 ==
4279 08:13:54.611831 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 08:13:54.614961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 08:13:54.615523 ==
4282 08:13:54.615892 DQS Delay:
4283 08:13:54.618470 DQS0 = 0, DQS1 = 0
4284 08:13:54.618932 DQM Delay:
4285 08:13:54.621781 DQM0 = 41, DQM1 = 35
4286 08:13:54.622249 DQ Delay:
4287 08:13:54.624780 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4288 08:13:54.628067 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4289 08:13:54.631169 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4290 08:13:54.634813 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4291 08:13:54.635372
4292 08:13:54.635742
4293 08:13:54.636082 ==
4294 08:13:54.637737 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 08:13:54.641139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 08:13:54.641646 ==
4297 08:13:54.642018
4298 08:13:54.644378
4299 08:13:54.644841 TX Vref Scan disable
4300 08:13:54.647867 == TX Byte 0 ==
4301 08:13:54.651068 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4302 08:13:54.654441 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4303 08:13:54.657283 == TX Byte 1 ==
4304 08:13:54.660586 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4305 08:13:54.664182 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4306 08:13:54.667436 ==
4307 08:13:54.670692 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 08:13:54.673888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 08:13:54.674612 ==
4310 08:13:54.675143
4311 08:13:54.675641
4312 08:13:54.676889 TX Vref Scan disable
4313 08:13:54.677468 == TX Byte 0 ==
4314 08:13:54.684110 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4315 08:13:54.687308 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4316 08:13:54.690087 == TX Byte 1 ==
4317 08:13:54.693683 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4318 08:13:54.696504 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4319 08:13:54.697077
4320 08:13:54.697605 [DATLAT]
4321 08:13:54.699790 Freq=600, CH0 RK1
4322 08:13:54.700289
4323 08:13:54.700745 DATLAT Default: 0x9
4324 08:13:54.703529 0, 0xFFFF, sum = 0
4325 08:13:54.706928 1, 0xFFFF, sum = 0
4326 08:13:54.707455 2, 0xFFFF, sum = 0
4327 08:13:54.710381 3, 0xFFFF, sum = 0
4328 08:13:54.710810 4, 0xFFFF, sum = 0
4329 08:13:54.713049 5, 0xFFFF, sum = 0
4330 08:13:54.713507 6, 0xFFFF, sum = 0
4331 08:13:54.716586 7, 0xFFFF, sum = 0
4332 08:13:54.717012 8, 0x0, sum = 1
4333 08:13:54.720274 9, 0x0, sum = 2
4334 08:13:54.720793 10, 0x0, sum = 3
4335 08:13:54.722999 11, 0x0, sum = 4
4336 08:13:54.723527 best_step = 9
4337 08:13:54.724167
4338 08:13:54.724713 ==
4339 08:13:54.726774 Dram Type= 6, Freq= 0, CH_0, rank 1
4340 08:13:54.729792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 08:13:54.730217 ==
4342 08:13:54.732971 RX Vref Scan: 0
4343 08:13:54.733432
4344 08:13:54.736536 RX Vref 0 -> 0, step: 1
4345 08:13:54.737147
4346 08:13:54.737608 RX Delay -179 -> 252, step: 8
4347 08:13:54.744142 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4348 08:13:54.747235 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4349 08:13:54.751114 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4350 08:13:54.753840 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4351 08:13:54.760530 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4352 08:13:54.763897 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4353 08:13:54.767469 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4354 08:13:54.770705 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4355 08:13:54.777144 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4356 08:13:54.780558 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4357 08:13:54.783737 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4358 08:13:54.786821 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4359 08:13:54.793427 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4360 08:13:54.796579 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4361 08:13:54.799782 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4362 08:13:54.803921 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4363 08:13:54.804485 ==
4364 08:13:54.806751 Dram Type= 6, Freq= 0, CH_0, rank 1
4365 08:13:54.813057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 08:13:54.813506 ==
4367 08:13:54.813848 DQS Delay:
4368 08:13:54.816357 DQS0 = 0, DQS1 = 0
4369 08:13:54.816887 DQM Delay:
4370 08:13:54.817433 DQM0 = 42, DQM1 = 37
4371 08:13:54.820480 DQ Delay:
4372 08:13:54.822924 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4373 08:13:54.826464 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4374 08:13:54.829699 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =28
4375 08:13:54.833116 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =40
4376 08:13:54.833626
4377 08:13:54.833965
4378 08:13:54.839993 [DQSOSCAuto] RK1, (LSB)MR18= 0x560b, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
4379 08:13:54.843069 CH0 RK1: MR19=808, MR18=560B
4380 08:13:54.849444 CH0_RK1: MR19=0x808, MR18=0x560B, DQSOSC=393, MR23=63, INC=169, DEC=113
4381 08:13:54.853595 [RxdqsGatingPostProcess] freq 600
4382 08:13:54.856576 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4383 08:13:54.859978 Pre-setting of DQS Precalculation
4384 08:13:54.866283 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4385 08:13:54.866798 ==
4386 08:13:54.869473 Dram Type= 6, Freq= 0, CH_1, rank 0
4387 08:13:54.872733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 08:13:54.873255 ==
4389 08:13:54.879205 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4390 08:13:54.885966 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4391 08:13:54.888646 [CA 0] Center 35 (5~66) winsize 62
4392 08:13:54.892149 [CA 1] Center 36 (6~66) winsize 61
4393 08:13:54.895637 [CA 2] Center 34 (4~65) winsize 62
4394 08:13:54.898698 [CA 3] Center 33 (3~64) winsize 62
4395 08:13:54.902045 [CA 4] Center 34 (4~65) winsize 62
4396 08:13:54.905310 [CA 5] Center 33 (3~64) winsize 62
4397 08:13:54.905837
4398 08:13:54.908683 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4399 08:13:54.909215
4400 08:13:54.911993 [CATrainingPosCal] consider 1 rank data
4401 08:13:54.915559 u2DelayCellTimex100 = 270/100 ps
4402 08:13:54.918521 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4403 08:13:54.921836 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4404 08:13:54.925486 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4405 08:13:54.928661 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4406 08:13:54.931973 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4407 08:13:54.938793 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4408 08:13:54.939312
4409 08:13:54.941447 CA PerBit enable=1, Macro0, CA PI delay=33
4410 08:13:54.941872
4411 08:13:54.944998 [CBTSetCACLKResult] CA Dly = 33
4412 08:13:54.945445 CS Dly: 4 (0~35)
4413 08:13:54.945785 ==
4414 08:13:54.948266 Dram Type= 6, Freq= 0, CH_1, rank 1
4415 08:13:54.951982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 08:13:54.954985 ==
4417 08:13:54.958621 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4418 08:13:54.965099 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4419 08:13:54.968127 [CA 0] Center 35 (5~66) winsize 62
4420 08:13:54.971372 [CA 1] Center 36 (6~66) winsize 61
4421 08:13:54.974822 [CA 2] Center 34 (4~65) winsize 62
4422 08:13:54.978277 [CA 3] Center 34 (3~65) winsize 63
4423 08:13:54.981109 [CA 4] Center 34 (4~65) winsize 62
4424 08:13:54.985184 [CA 5] Center 34 (3~65) winsize 63
4425 08:13:54.985695
4426 08:13:54.988100 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4427 08:13:54.988739
4428 08:13:54.991029 [CATrainingPosCal] consider 2 rank data
4429 08:13:54.994450 u2DelayCellTimex100 = 270/100 ps
4430 08:13:54.997938 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4431 08:13:55.001728 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4432 08:13:55.008000 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 08:13:55.011474 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4434 08:13:55.014318 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4435 08:13:55.017701 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4436 08:13:55.018272
4437 08:13:55.020888 CA PerBit enable=1, Macro0, CA PI delay=33
4438 08:13:55.021406
4439 08:13:55.024478 [CBTSetCACLKResult] CA Dly = 33
4440 08:13:55.025037 CS Dly: 4 (0~36)
4441 08:13:55.025461
4442 08:13:55.028189 ----->DramcWriteLeveling(PI) begin...
4443 08:13:55.031002 ==
4444 08:13:55.034397 Dram Type= 6, Freq= 0, CH_1, rank 0
4445 08:13:55.037725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4446 08:13:55.038292 ==
4447 08:13:55.040817 Write leveling (Byte 0): 29 => 29
4448 08:13:55.044529 Write leveling (Byte 1): 29 => 29
4449 08:13:55.047563 DramcWriteLeveling(PI) end<-----
4450 08:13:55.048045
4451 08:13:55.048415 ==
4452 08:13:55.050778 Dram Type= 6, Freq= 0, CH_1, rank 0
4453 08:13:55.053960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 08:13:55.054533 ==
4455 08:13:55.057519 [Gating] SW mode calibration
4456 08:13:55.063981 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4457 08:13:55.070329 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4458 08:13:55.073839 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4459 08:13:55.076954 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4460 08:13:55.083443 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4461 08:13:55.087209 0 9 12 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 1)
4462 08:13:55.089881 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 08:13:55.096818 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 08:13:55.099873 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 08:13:55.103175 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 08:13:55.109894 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 08:13:55.113198 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 08:13:55.116647 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4469 08:13:55.123100 0 10 12 | B1->B0 | 3030 3333 | 0 0 | (0 0) (0 0)
4470 08:13:55.126210 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4471 08:13:55.129699 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 08:13:55.136110 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 08:13:55.139823 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 08:13:55.142789 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 08:13:55.149431 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 08:13:55.152438 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 08:13:55.156473 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4478 08:13:55.162454 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 08:13:55.165870 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 08:13:55.169590 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 08:13:55.175961 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 08:13:55.179571 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 08:13:55.182367 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 08:13:55.189053 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 08:13:55.192835 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 08:13:55.195897 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 08:13:55.201985 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 08:13:55.205688 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 08:13:55.208580 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 08:13:55.214922 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 08:13:55.218674 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 08:13:55.222048 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 08:13:55.228447 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4494 08:13:55.232146 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 08:13:55.235356 Total UI for P1: 0, mck2ui 16
4496 08:13:55.237960 best dqsien dly found for B0: ( 0, 13, 12)
4497 08:13:55.241829 Total UI for P1: 0, mck2ui 16
4498 08:13:55.245094 best dqsien dly found for B1: ( 0, 13, 12)
4499 08:13:55.248407 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4500 08:13:55.250997 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4501 08:13:55.251464
4502 08:13:55.254922 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4503 08:13:55.261229 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4504 08:13:55.261862 [Gating] SW calibration Done
4505 08:13:55.262242 ==
4506 08:13:55.264920 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 08:13:55.271090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 08:13:55.271683 ==
4509 08:13:55.272062 RX Vref Scan: 0
4510 08:13:55.272409
4511 08:13:55.274309 RX Vref 0 -> 0, step: 1
4512 08:13:55.274776
4513 08:13:55.277524 RX Delay -230 -> 252, step: 16
4514 08:13:55.281321 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4515 08:13:55.284166 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4516 08:13:55.290609 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4517 08:13:55.294483 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4518 08:13:55.297378 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4519 08:13:55.300634 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4520 08:13:55.304159 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4521 08:13:55.310393 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4522 08:13:55.313501 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4523 08:13:55.316966 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4524 08:13:55.320714 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4525 08:13:55.327156 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4526 08:13:55.330278 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4527 08:13:55.333288 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4528 08:13:55.336674 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4529 08:13:55.343566 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4530 08:13:55.344148 ==
4531 08:13:55.346560 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 08:13:55.349864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 08:13:55.350354 ==
4534 08:13:55.350845 DQS Delay:
4535 08:13:55.353076 DQS0 = 0, DQS1 = 0
4536 08:13:55.353598 DQM Delay:
4537 08:13:55.356695 DQM0 = 47, DQM1 = 39
4538 08:13:55.357270 DQ Delay:
4539 08:13:55.359701 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4540 08:13:55.363334 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4541 08:13:55.366607 DQ8 =25, DQ9 =33, DQ10 =33, DQ11 =25
4542 08:13:55.369922 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4543 08:13:55.370499
4544 08:13:55.370982
4545 08:13:55.371564 ==
4546 08:13:55.372941 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 08:13:55.379404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 08:13:55.379987 ==
4549 08:13:55.380480
4550 08:13:55.380937
4551 08:13:55.381516 TX Vref Scan disable
4552 08:13:55.382918 == TX Byte 0 ==
4553 08:13:55.385975 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4554 08:13:55.392615 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4555 08:13:55.393089 == TX Byte 1 ==
4556 08:13:55.396332 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4557 08:13:55.402387 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4558 08:13:55.402951 ==
4559 08:13:55.406040 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 08:13:55.409392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 08:13:55.409962 ==
4562 08:13:55.410337
4563 08:13:55.410685
4564 08:13:55.412528 TX Vref Scan disable
4565 08:13:55.415375 == TX Byte 0 ==
4566 08:13:55.419308 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4567 08:13:55.422318 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4568 08:13:55.425322 == TX Byte 1 ==
4569 08:13:55.429073 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4570 08:13:55.432656 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4571 08:13:55.433217
4572 08:13:55.435299 [DATLAT]
4573 08:13:55.435766 Freq=600, CH1 RK0
4574 08:13:55.436171
4575 08:13:55.438948 DATLAT Default: 0x9
4576 08:13:55.439525 0, 0xFFFF, sum = 0
4577 08:13:55.442045 1, 0xFFFF, sum = 0
4578 08:13:55.442531 2, 0xFFFF, sum = 0
4579 08:13:55.445375 3, 0xFFFF, sum = 0
4580 08:13:55.445956 4, 0xFFFF, sum = 0
4581 08:13:55.448335 5, 0xFFFF, sum = 0
4582 08:13:55.448801 6, 0xFFFF, sum = 0
4583 08:13:55.451723 7, 0xFFFF, sum = 0
4584 08:13:55.452191 8, 0x0, sum = 1
4585 08:13:55.454973 9, 0x0, sum = 2
4586 08:13:55.455441 10, 0x0, sum = 3
4587 08:13:55.458595 11, 0x0, sum = 4
4588 08:13:55.459063 best_step = 9
4589 08:13:55.459441
4590 08:13:55.459780 ==
4591 08:13:55.462241 Dram Type= 6, Freq= 0, CH_1, rank 0
4592 08:13:55.465495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 08:13:55.466052 ==
4594 08:13:55.468823 RX Vref Scan: 1
4595 08:13:55.469425
4596 08:13:55.471828 RX Vref 0 -> 0, step: 1
4597 08:13:55.472289
4598 08:13:55.472657 RX Delay -179 -> 252, step: 8
4599 08:13:55.474853
4600 08:13:55.475312 Set Vref, RX VrefLevel [Byte0]: 51
4601 08:13:55.478806 [Byte1]: 51
4602 08:13:55.483481
4603 08:13:55.486280 Final RX Vref Byte 0 = 51 to rank0
4604 08:13:55.486744 Final RX Vref Byte 1 = 51 to rank0
4605 08:13:55.489766 Final RX Vref Byte 0 = 51 to rank1
4606 08:13:55.492693 Final RX Vref Byte 1 = 51 to rank1==
4607 08:13:55.496740 Dram Type= 6, Freq= 0, CH_1, rank 0
4608 08:13:55.503117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 08:13:55.503703 ==
4610 08:13:55.504077 DQS Delay:
4611 08:13:55.506146 DQS0 = 0, DQS1 = 0
4612 08:13:55.506607 DQM Delay:
4613 08:13:55.506971 DQM0 = 46, DQM1 = 37
4614 08:13:55.510005 DQ Delay:
4615 08:13:55.512817 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =40
4616 08:13:55.516070 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4617 08:13:55.519556 DQ8 =28, DQ9 =28, DQ10 =40, DQ11 =28
4618 08:13:55.522471 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =44
4619 08:13:55.523026
4620 08:13:55.523392
4621 08:13:55.529784 [DQSOSCAuto] RK0, (LSB)MR18= 0x492e, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4622 08:13:55.532807 CH1 RK0: MR19=808, MR18=492E
4623 08:13:55.539497 CH1_RK0: MR19=0x808, MR18=0x492E, DQSOSC=396, MR23=63, INC=167, DEC=111
4624 08:13:55.540055
4625 08:13:55.542135 ----->DramcWriteLeveling(PI) begin...
4626 08:13:55.542602 ==
4627 08:13:55.545730 Dram Type= 6, Freq= 0, CH_1, rank 1
4628 08:13:55.549487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4629 08:13:55.550056 ==
4630 08:13:55.552013 Write leveling (Byte 0): 28 => 28
4631 08:13:55.555908 Write leveling (Byte 1): 31 => 31
4632 08:13:55.559180 DramcWriteLeveling(PI) end<-----
4633 08:13:55.559642
4634 08:13:55.560003 ==
4635 08:13:55.562012 Dram Type= 6, Freq= 0, CH_1, rank 1
4636 08:13:55.568784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 08:13:55.569392 ==
4638 08:13:55.569773 [Gating] SW mode calibration
4639 08:13:55.578686 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4640 08:13:55.582442 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4641 08:13:55.585045 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4642 08:13:55.591855 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4643 08:13:55.595674 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4644 08:13:55.601611 0 9 12 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
4645 08:13:55.605124 0 9 16 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
4646 08:13:55.608038 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 08:13:55.614831 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 08:13:55.618355 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 08:13:55.621453 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 08:13:55.628252 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 08:13:55.631432 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 08:13:55.634934 0 10 12 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (0 0)
4653 08:13:55.641902 0 10 16 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
4654 08:13:55.645102 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 08:13:55.647689 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 08:13:55.654859 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 08:13:55.657437 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 08:13:55.661120 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 08:13:55.667451 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 08:13:55.671095 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4661 08:13:55.673820 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4662 08:13:55.680414 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 08:13:55.683913 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 08:13:55.687011 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 08:13:55.693605 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 08:13:55.697297 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 08:13:55.700306 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 08:13:55.707497 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 08:13:55.709994 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 08:13:55.713424 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 08:13:55.720049 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 08:13:55.723602 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 08:13:55.727153 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 08:13:55.733410 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 08:13:55.736694 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 08:13:55.740094 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4677 08:13:55.743705 Total UI for P1: 0, mck2ui 16
4678 08:13:55.746550 best dqsien dly found for B1: ( 0, 13, 10)
4679 08:13:55.753030 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 08:13:55.753635 Total UI for P1: 0, mck2ui 16
4681 08:13:55.759901 best dqsien dly found for B0: ( 0, 13, 12)
4682 08:13:55.763008 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4683 08:13:55.766421 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4684 08:13:55.766986
4685 08:13:55.770042 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4686 08:13:55.772918 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4687 08:13:55.775738 [Gating] SW calibration Done
4688 08:13:55.776201 ==
4689 08:13:55.779509 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 08:13:55.782909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 08:13:55.783474 ==
4692 08:13:55.786110 RX Vref Scan: 0
4693 08:13:55.786718
4694 08:13:55.787104 RX Vref 0 -> 0, step: 1
4695 08:13:55.787452
4696 08:13:55.789235 RX Delay -230 -> 252, step: 16
4697 08:13:55.795636 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4698 08:13:55.799284 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4699 08:13:55.802188 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4700 08:13:55.806088 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4701 08:13:55.812281 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4702 08:13:55.815516 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4703 08:13:55.819217 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4704 08:13:55.822064 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4705 08:13:55.825795 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4706 08:13:55.832326 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4707 08:13:55.835277 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4708 08:13:55.838729 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4709 08:13:55.841969 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4710 08:13:55.848509 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4711 08:13:55.851636 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4712 08:13:55.854964 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4713 08:13:55.855499 ==
4714 08:13:55.858185 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 08:13:55.865221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 08:13:55.865971 ==
4717 08:13:55.866367 DQS Delay:
4718 08:13:55.868067 DQS0 = 0, DQS1 = 0
4719 08:13:55.868527 DQM Delay:
4720 08:13:55.868895 DQM0 = 44, DQM1 = 36
4721 08:13:55.871094 DQ Delay:
4722 08:13:55.874567 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4723 08:13:55.878481 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4724 08:13:55.881302 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4725 08:13:55.884604 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4726 08:13:55.885178
4727 08:13:55.885733
4728 08:13:55.886193 ==
4729 08:13:55.887894 Dram Type= 6, Freq= 0, CH_1, rank 1
4730 08:13:55.890885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4731 08:13:55.891351 ==
4732 08:13:55.891716
4733 08:13:55.892088
4734 08:13:55.894299 TX Vref Scan disable
4735 08:13:55.897810 == TX Byte 0 ==
4736 08:13:55.901064 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4737 08:13:55.904328 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4738 08:13:55.907973 == TX Byte 1 ==
4739 08:13:55.911410 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4740 08:13:55.914308 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4741 08:13:55.914731 ==
4742 08:13:55.917822 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 08:13:55.920594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 08:13:55.924260 ==
4745 08:13:55.924822
4746 08:13:55.925393
4747 08:13:55.925738 TX Vref Scan disable
4748 08:13:55.928388 == TX Byte 0 ==
4749 08:13:55.931462 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4750 08:13:55.938153 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4751 08:13:55.938847 == TX Byte 1 ==
4752 08:13:55.941405 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4753 08:13:55.947933 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4754 08:13:55.948480
4755 08:13:55.948885 [DATLAT]
4756 08:13:55.949376 Freq=600, CH1 RK1
4757 08:13:55.949751
4758 08:13:55.951096 DATLAT Default: 0x9
4759 08:13:55.951625 0, 0xFFFF, sum = 0
4760 08:13:55.954060 1, 0xFFFF, sum = 0
4761 08:13:55.957557 2, 0xFFFF, sum = 0
4762 08:13:55.957979 3, 0xFFFF, sum = 0
4763 08:13:55.960526 4, 0xFFFF, sum = 0
4764 08:13:55.960951 5, 0xFFFF, sum = 0
4765 08:13:55.964016 6, 0xFFFF, sum = 0
4766 08:13:55.964440 7, 0xFFFF, sum = 0
4767 08:13:55.967137 8, 0x0, sum = 1
4768 08:13:55.967648 9, 0x0, sum = 2
4769 08:13:55.970630 10, 0x0, sum = 3
4770 08:13:55.971054 11, 0x0, sum = 4
4771 08:13:55.971413 best_step = 9
4772 08:13:55.971739
4773 08:13:55.974083 ==
4774 08:13:55.977312 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 08:13:55.980949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 08:13:55.981450 ==
4777 08:13:55.981800 RX Vref Scan: 0
4778 08:13:55.982112
4779 08:13:55.983683 RX Vref 0 -> 0, step: 1
4780 08:13:55.984104
4781 08:13:55.987012 RX Delay -195 -> 252, step: 8
4782 08:13:55.993475 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4783 08:13:55.996661 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4784 08:13:56.000157 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4785 08:13:56.004092 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4786 08:13:56.010037 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4787 08:13:56.013992 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4788 08:13:56.016676 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4789 08:13:56.019918 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4790 08:13:56.023340 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4791 08:13:56.029766 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4792 08:13:56.033476 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4793 08:13:56.037271 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4794 08:13:56.040124 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4795 08:13:56.046811 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4796 08:13:56.049638 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4797 08:13:56.053234 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4798 08:13:56.053841 ==
4799 08:13:56.056303 Dram Type= 6, Freq= 0, CH_1, rank 1
4800 08:13:56.060008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4801 08:13:56.062816 ==
4802 08:13:56.063283 DQS Delay:
4803 08:13:56.063650 DQS0 = 0, DQS1 = 0
4804 08:13:56.066481 DQM Delay:
4805 08:13:56.067039 DQM0 = 45, DQM1 = 37
4806 08:13:56.069795 DQ Delay:
4807 08:13:56.072522 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4808 08:13:56.073044 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =40
4809 08:13:56.076159 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4810 08:13:56.083122 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4811 08:13:56.083683
4812 08:13:56.084050
4813 08:13:56.089321 [DQSOSCAuto] RK1, (LSB)MR18= 0x2116, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
4814 08:13:56.092823 CH1 RK1: MR19=808, MR18=2116
4815 08:13:56.099461 CH1_RK1: MR19=0x808, MR18=0x2116, DQSOSC=403, MR23=63, INC=161, DEC=107
4816 08:13:56.102563 [RxdqsGatingPostProcess] freq 600
4817 08:13:56.105605 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4818 08:13:56.108958 Pre-setting of DQS Precalculation
4819 08:13:56.116051 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4820 08:13:56.122476 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4821 08:13:56.128819 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4822 08:13:56.129392
4823 08:13:56.129765
4824 08:13:56.132439 [Calibration Summary] 1200 Mbps
4825 08:13:56.132997 CH 0, Rank 0
4826 08:13:56.135491 SW Impedance : PASS
4827 08:13:56.138799 DUTY Scan : NO K
4828 08:13:56.139371 ZQ Calibration : PASS
4829 08:13:56.141787 Jitter Meter : NO K
4830 08:13:56.145554 CBT Training : PASS
4831 08:13:56.146115 Write leveling : PASS
4832 08:13:56.148509 RX DQS gating : PASS
4833 08:13:56.151814 RX DQ/DQS(RDDQC) : PASS
4834 08:13:56.152284 TX DQ/DQS : PASS
4835 08:13:56.154994 RX DATLAT : PASS
4836 08:13:56.158515 RX DQ/DQS(Engine): PASS
4837 08:13:56.158980 TX OE : NO K
4838 08:13:56.161722 All Pass.
4839 08:13:56.162185
4840 08:13:56.162551 CH 0, Rank 1
4841 08:13:56.165070 SW Impedance : PASS
4842 08:13:56.165565 DUTY Scan : NO K
4843 08:13:56.168452 ZQ Calibration : PASS
4844 08:13:56.171727 Jitter Meter : NO K
4845 08:13:56.172283 CBT Training : PASS
4846 08:13:56.175291 Write leveling : PASS
4847 08:13:56.178165 RX DQS gating : PASS
4848 08:13:56.178730 RX DQ/DQS(RDDQC) : PASS
4849 08:13:56.181762 TX DQ/DQS : PASS
4850 08:13:56.184732 RX DATLAT : PASS
4851 08:13:56.185287 RX DQ/DQS(Engine): PASS
4852 08:13:56.187924 TX OE : NO K
4853 08:13:56.188390 All Pass.
4854 08:13:56.188756
4855 08:13:56.191146 CH 1, Rank 0
4856 08:13:56.191610 SW Impedance : PASS
4857 08:13:56.194699 DUTY Scan : NO K
4858 08:13:56.197881 ZQ Calibration : PASS
4859 08:13:56.198354 Jitter Meter : NO K
4860 08:13:56.201637 CBT Training : PASS
4861 08:13:56.202205 Write leveling : PASS
4862 08:13:56.204548 RX DQS gating : PASS
4863 08:13:56.208189 RX DQ/DQS(RDDQC) : PASS
4864 08:13:56.208752 TX DQ/DQS : PASS
4865 08:13:56.210719 RX DATLAT : PASS
4866 08:13:56.214060 RX DQ/DQS(Engine): PASS
4867 08:13:56.214602 TX OE : NO K
4868 08:13:56.217763 All Pass.
4869 08:13:56.218229
4870 08:13:56.218595 CH 1, Rank 1
4871 08:13:56.220725 SW Impedance : PASS
4872 08:13:56.221187 DUTY Scan : NO K
4873 08:13:56.224479 ZQ Calibration : PASS
4874 08:13:56.227943 Jitter Meter : NO K
4875 08:13:56.228409 CBT Training : PASS
4876 08:13:56.230819 Write leveling : PASS
4877 08:13:56.234427 RX DQS gating : PASS
4878 08:13:56.234979 RX DQ/DQS(RDDQC) : PASS
4879 08:13:56.237405 TX DQ/DQS : PASS
4880 08:13:56.241016 RX DATLAT : PASS
4881 08:13:56.241611 RX DQ/DQS(Engine): PASS
4882 08:13:56.244198 TX OE : NO K
4883 08:13:56.244756 All Pass.
4884 08:13:56.245127
4885 08:13:56.247143 DramC Write-DBI off
4886 08:13:56.250428 PER_BANK_REFRESH: Hybrid Mode
4887 08:13:56.250988 TX_TRACKING: ON
4888 08:13:56.260445 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4889 08:13:56.263363 [FAST_K] Save calibration result to emmc
4890 08:13:56.267067 dramc_set_vcore_voltage set vcore to 662500
4891 08:13:56.270367 Read voltage for 933, 3
4892 08:13:56.270921 Vio18 = 0
4893 08:13:56.271291 Vcore = 662500
4894 08:13:56.273902 Vdram = 0
4895 08:13:56.274462 Vddq = 0
4896 08:13:56.274831 Vmddr = 0
4897 08:13:56.280478 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4898 08:13:56.283532 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4899 08:13:56.286838 MEM_TYPE=3, freq_sel=17
4900 08:13:56.290131 sv_algorithm_assistance_LP4_1600
4901 08:13:56.293542 ============ PULL DRAM RESETB DOWN ============
4902 08:13:56.300425 ========== PULL DRAM RESETB DOWN end =========
4903 08:13:56.303245 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4904 08:13:56.306980 ===================================
4905 08:13:56.309946 LPDDR4 DRAM CONFIGURATION
4906 08:13:56.312918 ===================================
4907 08:13:56.313530 EX_ROW_EN[0] = 0x0
4908 08:13:56.316630 EX_ROW_EN[1] = 0x0
4909 08:13:56.317192 LP4Y_EN = 0x0
4910 08:13:56.319777 WORK_FSP = 0x0
4911 08:13:56.320335 WL = 0x3
4912 08:13:56.323063 RL = 0x3
4913 08:13:56.323625 BL = 0x2
4914 08:13:56.326143 RPST = 0x0
4915 08:13:56.329454 RD_PRE = 0x0
4916 08:13:56.330010 WR_PRE = 0x1
4917 08:13:56.333025 WR_PST = 0x0
4918 08:13:56.333623 DBI_WR = 0x0
4919 08:13:56.336294 DBI_RD = 0x0
4920 08:13:56.336755 OTF = 0x1
4921 08:13:56.339110 ===================================
4922 08:13:56.342756 ===================================
4923 08:13:56.346276 ANA top config
4924 08:13:56.349464 ===================================
4925 08:13:56.350025 DLL_ASYNC_EN = 0
4926 08:13:56.352295 ALL_SLAVE_EN = 1
4927 08:13:56.355593 NEW_RANK_MODE = 1
4928 08:13:56.358909 DLL_IDLE_MODE = 1
4929 08:13:56.362293 LP45_APHY_COMB_EN = 1
4930 08:13:56.362852 TX_ODT_DIS = 1
4931 08:13:56.365809 NEW_8X_MODE = 1
4932 08:13:56.368865 ===================================
4933 08:13:56.372208 ===================================
4934 08:13:56.375698 data_rate = 1866
4935 08:13:56.378838 CKR = 1
4936 08:13:56.382160 DQ_P2S_RATIO = 8
4937 08:13:56.385359 ===================================
4938 08:13:56.385834 CA_P2S_RATIO = 8
4939 08:13:56.388686 DQ_CA_OPEN = 0
4940 08:13:56.392234 DQ_SEMI_OPEN = 0
4941 08:13:56.395171 CA_SEMI_OPEN = 0
4942 08:13:56.398927 CA_FULL_RATE = 0
4943 08:13:56.401667 DQ_CKDIV4_EN = 1
4944 08:13:56.405508 CA_CKDIV4_EN = 1
4945 08:13:56.406071 CA_PREDIV_EN = 0
4946 08:13:56.408641 PH8_DLY = 0
4947 08:13:56.412132 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4948 08:13:56.415101 DQ_AAMCK_DIV = 4
4949 08:13:56.417993 CA_AAMCK_DIV = 4
4950 08:13:56.421990 CA_ADMCK_DIV = 4
4951 08:13:56.422557 DQ_TRACK_CA_EN = 0
4952 08:13:56.425463 CA_PICK = 933
4953 08:13:56.428380 CA_MCKIO = 933
4954 08:13:56.431273 MCKIO_SEMI = 0
4955 08:13:56.434814 PLL_FREQ = 3732
4956 08:13:56.438139 DQ_UI_PI_RATIO = 32
4957 08:13:56.441366 CA_UI_PI_RATIO = 0
4958 08:13:56.444545 ===================================
4959 08:13:56.447768 ===================================
4960 08:13:56.448239 memory_type:LPDDR4
4961 08:13:56.450999 GP_NUM : 10
4962 08:13:56.454048 SRAM_EN : 1
4963 08:13:56.454515 MD32_EN : 0
4964 08:13:56.457388 ===================================
4965 08:13:56.461011 [ANA_INIT] >>>>>>>>>>>>>>
4966 08:13:56.464173 <<<<<< [CONFIGURE PHASE]: ANA_TX
4967 08:13:56.467591 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4968 08:13:56.470706 ===================================
4969 08:13:56.473995 data_rate = 1866,PCW = 0X8f00
4970 08:13:56.477222 ===================================
4971 08:13:56.480973 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4972 08:13:56.483834 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4973 08:13:56.490298 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4974 08:13:56.497133 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4975 08:13:56.500350 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4976 08:13:56.503935 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4977 08:13:56.504406 [ANA_INIT] flow start
4978 08:13:56.507346 [ANA_INIT] PLL >>>>>>>>
4979 08:13:56.510330 [ANA_INIT] PLL <<<<<<<<
4980 08:13:56.510888 [ANA_INIT] MIDPI >>>>>>>>
4981 08:13:56.513795 [ANA_INIT] MIDPI <<<<<<<<
4982 08:13:56.516981 [ANA_INIT] DLL >>>>>>>>
4983 08:13:56.517589 [ANA_INIT] flow end
4984 08:13:56.523586 ============ LP4 DIFF to SE enter ============
4985 08:13:56.526846 ============ LP4 DIFF to SE exit ============
4986 08:13:56.530191 [ANA_INIT] <<<<<<<<<<<<<
4987 08:13:56.533305 [Flow] Enable top DCM control >>>>>
4988 08:13:56.536685 [Flow] Enable top DCM control <<<<<
4989 08:13:56.537272 Enable DLL master slave shuffle
4990 08:13:56.543444 ==============================================================
4991 08:13:56.546123 Gating Mode config
4992 08:13:56.549620 ==============================================================
4993 08:13:56.553008 Config description:
4994 08:13:56.563150 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4995 08:13:56.569428 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4996 08:13:56.572503 SELPH_MODE 0: By rank 1: By Phase
4997 08:13:56.579553 ==============================================================
4998 08:13:56.582480 GAT_TRACK_EN = 1
4999 08:13:56.585947 RX_GATING_MODE = 2
5000 08:13:56.589279 RX_GATING_TRACK_MODE = 2
5001 08:13:56.592128 SELPH_MODE = 1
5002 08:13:56.595942 PICG_EARLY_EN = 1
5003 08:13:56.596521 VALID_LAT_VALUE = 1
5004 08:13:56.602527 ==============================================================
5005 08:13:56.605380 Enter into Gating configuration >>>>
5006 08:13:56.609208 Exit from Gating configuration <<<<
5007 08:13:56.612416 Enter into DVFS_PRE_config >>>>>
5008 08:13:56.622326 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5009 08:13:56.625359 Exit from DVFS_PRE_config <<<<<
5010 08:13:56.628745 Enter into PICG configuration >>>>
5011 08:13:56.632456 Exit from PICG configuration <<<<
5012 08:13:56.635908 [RX_INPUT] configuration >>>>>
5013 08:13:56.638665 [RX_INPUT] configuration <<<<<
5014 08:13:56.645387 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5015 08:13:56.649302 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5016 08:13:56.655452 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5017 08:13:56.661928 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5018 08:13:56.668821 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5019 08:13:56.674904 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5020 08:13:56.678209 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5021 08:13:56.681881 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5022 08:13:56.685718 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5023 08:13:56.691487 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5024 08:13:56.694441 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5025 08:13:56.697694 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5026 08:13:56.701146 ===================================
5027 08:13:56.704726 LPDDR4 DRAM CONFIGURATION
5028 08:13:56.708243 ===================================
5029 08:13:56.710885 EX_ROW_EN[0] = 0x0
5030 08:13:56.711351 EX_ROW_EN[1] = 0x0
5031 08:13:56.714047 LP4Y_EN = 0x0
5032 08:13:56.714511 WORK_FSP = 0x0
5033 08:13:56.717624 WL = 0x3
5034 08:13:56.718090 RL = 0x3
5035 08:13:56.720963 BL = 0x2
5036 08:13:56.721689 RPST = 0x0
5037 08:13:56.724866 RD_PRE = 0x0
5038 08:13:56.725486 WR_PRE = 0x1
5039 08:13:56.727746 WR_PST = 0x0
5040 08:13:56.728209 DBI_WR = 0x0
5041 08:13:56.730847 DBI_RD = 0x0
5042 08:13:56.731310 OTF = 0x1
5043 08:13:56.734403 ===================================
5044 08:13:56.741314 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5045 08:13:56.744155 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5046 08:13:56.747780 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5047 08:13:56.750667 ===================================
5048 08:13:56.754244 LPDDR4 DRAM CONFIGURATION
5049 08:13:56.757439 ===================================
5050 08:13:56.760976 EX_ROW_EN[0] = 0x10
5051 08:13:56.761584 EX_ROW_EN[1] = 0x0
5052 08:13:56.763746 LP4Y_EN = 0x0
5053 08:13:56.764208 WORK_FSP = 0x0
5054 08:13:56.767311 WL = 0x3
5055 08:13:56.767875 RL = 0x3
5056 08:13:56.770561 BL = 0x2
5057 08:13:56.771024 RPST = 0x0
5058 08:13:56.773726 RD_PRE = 0x0
5059 08:13:56.774293 WR_PRE = 0x1
5060 08:13:56.776919 WR_PST = 0x0
5061 08:13:56.777400 DBI_WR = 0x0
5062 08:13:56.780058 DBI_RD = 0x0
5063 08:13:56.783690 OTF = 0x1
5064 08:13:56.786976 ===================================
5065 08:13:56.789861 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5066 08:13:56.795697 nWR fixed to 30
5067 08:13:56.798510 [ModeRegInit_LP4] CH0 RK0
5068 08:13:56.798983 [ModeRegInit_LP4] CH0 RK1
5069 08:13:56.801869 [ModeRegInit_LP4] CH1 RK0
5070 08:13:56.805176 [ModeRegInit_LP4] CH1 RK1
5071 08:13:56.805985 match AC timing 9
5072 08:13:56.811791 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5073 08:13:56.814934 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5074 08:13:56.818066 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5075 08:13:56.825053 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5076 08:13:56.828176 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5077 08:13:56.828742 ==
5078 08:13:56.831748 Dram Type= 6, Freq= 0, CH_0, rank 0
5079 08:13:56.834807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5080 08:13:56.838127 ==
5081 08:13:56.841861 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5082 08:13:56.847925 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5083 08:13:56.851555 [CA 0] Center 37 (7~68) winsize 62
5084 08:13:56.854818 [CA 1] Center 37 (7~68) winsize 62
5085 08:13:56.858313 [CA 2] Center 34 (4~65) winsize 62
5086 08:13:56.860850 [CA 3] Center 35 (5~65) winsize 61
5087 08:13:56.864784 [CA 4] Center 33 (3~64) winsize 62
5088 08:13:56.868363 [CA 5] Center 33 (4~63) winsize 60
5089 08:13:56.868932
5090 08:13:56.871279 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5091 08:13:56.871866
5092 08:13:56.874575 [CATrainingPosCal] consider 1 rank data
5093 08:13:56.877904 u2DelayCellTimex100 = 270/100 ps
5094 08:13:56.881076 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5095 08:13:56.884259 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5096 08:13:56.887434 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5097 08:13:56.894130 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5098 08:13:56.897509 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5099 08:13:56.900703 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5100 08:13:56.901172
5101 08:13:56.903991 CA PerBit enable=1, Macro0, CA PI delay=33
5102 08:13:56.904552
5103 08:13:56.907722 [CBTSetCACLKResult] CA Dly = 33
5104 08:13:56.908279 CS Dly: 7 (0~38)
5105 08:13:56.908650 ==
5106 08:13:56.910597 Dram Type= 6, Freq= 0, CH_0, rank 1
5107 08:13:56.917022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 08:13:56.917526 ==
5109 08:13:56.920756 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5110 08:13:56.927126 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5111 08:13:56.930448 [CA 0] Center 37 (7~68) winsize 62
5112 08:13:56.933624 [CA 1] Center 37 (7~68) winsize 62
5113 08:13:56.937215 [CA 2] Center 34 (4~65) winsize 62
5114 08:13:56.940239 [CA 3] Center 34 (4~65) winsize 62
5115 08:13:56.943904 [CA 4] Center 33 (3~64) winsize 62
5116 08:13:56.947306 [CA 5] Center 33 (3~63) winsize 61
5117 08:13:56.947871
5118 08:13:56.950054 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5119 08:13:56.950522
5120 08:13:56.954096 [CATrainingPosCal] consider 2 rank data
5121 08:13:56.956575 u2DelayCellTimex100 = 270/100 ps
5122 08:13:56.960182 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5123 08:13:56.966885 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5124 08:13:56.969948 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5125 08:13:56.973755 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5126 08:13:56.976577 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5127 08:13:56.979753 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5128 08:13:56.980220
5129 08:13:56.982937 CA PerBit enable=1, Macro0, CA PI delay=33
5130 08:13:56.983502
5131 08:13:56.986495 [CBTSetCACLKResult] CA Dly = 33
5132 08:13:56.989269 CS Dly: 7 (0~39)
5133 08:13:56.989782
5134 08:13:56.992673 ----->DramcWriteLeveling(PI) begin...
5135 08:13:56.993142 ==
5136 08:13:56.996412 Dram Type= 6, Freq= 0, CH_0, rank 0
5137 08:13:56.999318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5138 08:13:56.999863 ==
5139 08:13:57.002694 Write leveling (Byte 0): 33 => 33
5140 08:13:57.005717 Write leveling (Byte 1): 30 => 30
5141 08:13:57.009453 DramcWriteLeveling(PI) end<-----
5142 08:13:57.010033
5143 08:13:57.010545 ==
5144 08:13:57.012739 Dram Type= 6, Freq= 0, CH_0, rank 0
5145 08:13:57.016006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 08:13:57.016645 ==
5147 08:13:57.019577 [Gating] SW mode calibration
5148 08:13:57.025629 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5149 08:13:57.032265 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5150 08:13:57.035181 0 14 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5151 08:13:57.042042 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5152 08:13:57.045548 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 08:13:57.048710 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 08:13:57.055544 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 08:13:57.058855 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 08:13:57.061768 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 08:13:57.068713 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5158 08:13:57.071585 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5159 08:13:57.075099 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 08:13:57.081703 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 08:13:57.085120 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 08:13:57.087838 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 08:13:57.094320 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 08:13:57.098063 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 08:13:57.100798 0 15 28 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
5166 08:13:57.107636 1 0 0 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
5167 08:13:57.111063 1 0 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5168 08:13:57.113881 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 08:13:57.120593 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 08:13:57.124252 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 08:13:57.127724 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 08:13:57.134003 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 08:13:57.137527 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5174 08:13:57.141083 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5175 08:13:57.147010 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 08:13:57.150624 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 08:13:57.154069 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 08:13:57.160705 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 08:13:57.163627 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 08:13:57.167072 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 08:13:57.173656 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 08:13:57.176765 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 08:13:57.180307 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 08:13:57.186641 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 08:13:57.190062 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 08:13:57.193160 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 08:13:57.199696 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 08:13:57.202805 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 08:13:57.206318 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5190 08:13:57.213006 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5191 08:13:57.216374 Total UI for P1: 0, mck2ui 16
5192 08:13:57.219727 best dqsien dly found for B0: ( 1, 2, 28)
5193 08:13:57.222573 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 08:13:57.225807 Total UI for P1: 0, mck2ui 16
5195 08:13:57.229296 best dqsien dly found for B1: ( 1, 3, 0)
5196 08:13:57.232533 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5197 08:13:57.235769 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5198 08:13:57.236504
5199 08:13:57.239138 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5200 08:13:57.242904 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5201 08:13:57.245986 [Gating] SW calibration Done
5202 08:13:57.246410 ==
5203 08:13:57.249022 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 08:13:57.255552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 08:13:57.256115 ==
5206 08:13:57.256731 RX Vref Scan: 0
5207 08:13:57.257193
5208 08:13:57.258648 RX Vref 0 -> 0, step: 1
5209 08:13:57.259071
5210 08:13:57.261788 RX Delay -80 -> 252, step: 8
5211 08:13:57.265232 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5212 08:13:57.268892 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5213 08:13:57.272394 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5214 08:13:57.275203 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5215 08:13:57.281737 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5216 08:13:57.285278 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5217 08:13:57.288265 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5218 08:13:57.291718 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5219 08:13:57.294549 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5220 08:13:57.301241 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5221 08:13:57.304550 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5222 08:13:57.308341 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5223 08:13:57.311130 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5224 08:13:57.317513 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5225 08:13:57.320977 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5226 08:13:57.324251 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5227 08:13:57.325004 ==
5228 08:13:57.327685 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 08:13:57.330901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 08:13:57.331406 ==
5231 08:13:57.334498 DQS Delay:
5232 08:13:57.334957 DQS0 = 0, DQS1 = 0
5233 08:13:57.337105 DQM Delay:
5234 08:13:57.337615 DQM0 = 97, DQM1 = 84
5235 08:13:57.338189 DQ Delay:
5236 08:13:57.340843 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5237 08:13:57.343978 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =111
5238 08:13:57.347764 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
5239 08:13:57.350834 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =91
5240 08:13:57.351397
5241 08:13:57.351760
5242 08:13:57.354250 ==
5243 08:13:57.357564 Dram Type= 6, Freq= 0, CH_0, rank 0
5244 08:13:57.360791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5245 08:13:57.361402 ==
5246 08:13:57.361787
5247 08:13:57.362130
5248 08:13:57.363902 TX Vref Scan disable
5249 08:13:57.364463 == TX Byte 0 ==
5250 08:13:57.370333 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5251 08:13:57.373579 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5252 08:13:57.374044 == TX Byte 1 ==
5253 08:13:57.380482 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5254 08:13:57.383687 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5255 08:13:57.384245 ==
5256 08:13:57.387233 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 08:13:57.390046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 08:13:57.390606 ==
5259 08:13:57.390994
5260 08:13:57.391335
5261 08:13:57.393023 TX Vref Scan disable
5262 08:13:57.396582 == TX Byte 0 ==
5263 08:13:57.400431 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5264 08:13:57.403671 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5265 08:13:57.406508 == TX Byte 1 ==
5266 08:13:57.409743 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5267 08:13:57.413135 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5268 08:13:57.413744
5269 08:13:57.417196 [DATLAT]
5270 08:13:57.417842 Freq=933, CH0 RK0
5271 08:13:57.418217
5272 08:13:57.419514 DATLAT Default: 0xd
5273 08:13:57.419972 0, 0xFFFF, sum = 0
5274 08:13:57.423246 1, 0xFFFF, sum = 0
5275 08:13:57.423813 2, 0xFFFF, sum = 0
5276 08:13:57.426025 3, 0xFFFF, sum = 0
5277 08:13:57.426493 4, 0xFFFF, sum = 0
5278 08:13:57.429314 5, 0xFFFF, sum = 0
5279 08:13:57.429829 6, 0xFFFF, sum = 0
5280 08:13:57.432965 7, 0xFFFF, sum = 0
5281 08:13:57.436099 8, 0xFFFF, sum = 0
5282 08:13:57.436662 9, 0xFFFF, sum = 0
5283 08:13:57.439387 10, 0x0, sum = 1
5284 08:13:57.439853 11, 0x0, sum = 2
5285 08:13:57.440222 12, 0x0, sum = 3
5286 08:13:57.442755 13, 0x0, sum = 4
5287 08:13:57.443222 best_step = 11
5288 08:13:57.443588
5289 08:13:57.445650 ==
5290 08:13:57.446111 Dram Type= 6, Freq= 0, CH_0, rank 0
5291 08:13:57.452745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 08:13:57.453297 ==
5293 08:13:57.453683 RX Vref Scan: 1
5294 08:13:57.453998
5295 08:13:57.455969 RX Vref 0 -> 0, step: 1
5296 08:13:57.456404
5297 08:13:57.459045 RX Delay -69 -> 252, step: 4
5298 08:13:57.459467
5299 08:13:57.462397 Set Vref, RX VrefLevel [Byte0]: 61
5300 08:13:57.465446 [Byte1]: 56
5301 08:13:57.465870
5302 08:13:57.469275 Final RX Vref Byte 0 = 61 to rank0
5303 08:13:57.471884 Final RX Vref Byte 1 = 56 to rank0
5304 08:13:57.475557 Final RX Vref Byte 0 = 61 to rank1
5305 08:13:57.478886 Final RX Vref Byte 1 = 56 to rank1==
5306 08:13:57.482174 Dram Type= 6, Freq= 0, CH_0, rank 0
5307 08:13:57.488711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 08:13:57.489246 ==
5309 08:13:57.489682 DQS Delay:
5310 08:13:57.490003 DQS0 = 0, DQS1 = 0
5311 08:13:57.492056 DQM Delay:
5312 08:13:57.492575 DQM0 = 97, DQM1 = 86
5313 08:13:57.495490 DQ Delay:
5314 08:13:57.498240 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5315 08:13:57.501875 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =106
5316 08:13:57.504933 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =80
5317 08:13:57.508969 DQ12 =90, DQ13 =88, DQ14 =98, DQ15 =92
5318 08:13:57.509542
5319 08:13:57.509888
5320 08:13:57.515227 [DQSOSCAuto] RK0, (LSB)MR18= 0x260d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 409 ps
5321 08:13:57.518175 CH0 RK0: MR19=505, MR18=260D
5322 08:13:57.524801 CH0_RK0: MR19=0x505, MR18=0x260D, DQSOSC=409, MR23=63, INC=64, DEC=43
5323 08:13:57.525323
5324 08:13:57.528423 ----->DramcWriteLeveling(PI) begin...
5325 08:13:57.528956 ==
5326 08:13:57.531318 Dram Type= 6, Freq= 0, CH_0, rank 1
5327 08:13:57.534312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5328 08:13:57.534740 ==
5329 08:13:57.538261 Write leveling (Byte 0): 33 => 33
5330 08:13:57.541092 Write leveling (Byte 1): 28 => 28
5331 08:13:57.544412 DramcWriteLeveling(PI) end<-----
5332 08:13:57.544941
5333 08:13:57.545278 ==
5334 08:13:57.547972 Dram Type= 6, Freq= 0, CH_0, rank 1
5335 08:13:57.551097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 08:13:57.554100 ==
5337 08:13:57.554618 [Gating] SW mode calibration
5338 08:13:57.564204 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5339 08:13:57.567868 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5340 08:13:57.570493 0 14 0 | B1->B0 | 2827 3030 | 1 1 | (0 0) (1 1)
5341 08:13:57.577187 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 08:13:57.581105 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 08:13:57.584393 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 08:13:57.590401 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 08:13:57.593753 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 08:13:57.600344 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 08:13:57.603199 0 14 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
5348 08:13:57.606598 0 15 0 | B1->B0 | 2f2f 2727 | 0 0 | (0 1) (1 0)
5349 08:13:57.613542 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5350 08:13:57.616687 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 08:13:57.619887 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 08:13:57.626258 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 08:13:57.630034 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 08:13:57.633403 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 08:13:57.639545 0 15 28 | B1->B0 | 2424 3535 | 0 1 | (0 0) (0 0)
5356 08:13:57.643524 1 0 0 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
5357 08:13:57.646192 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 08:13:57.653136 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 08:13:57.656291 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 08:13:57.659292 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 08:13:57.665805 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 08:13:57.669270 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 08:13:57.672794 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5364 08:13:57.679390 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5365 08:13:57.682227 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 08:13:57.685937 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 08:13:57.692025 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 08:13:57.695479 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 08:13:57.698520 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 08:13:57.705316 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 08:13:57.708484 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 08:13:57.711718 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 08:13:57.718465 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 08:13:57.721567 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 08:13:57.725298 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 08:13:57.731594 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 08:13:57.735429 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 08:13:57.738724 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 08:13:57.745229 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 08:13:57.748656 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5381 08:13:57.751707 Total UI for P1: 0, mck2ui 16
5382 08:13:57.755062 best dqsien dly found for B0: ( 1, 2, 30)
5383 08:13:57.757845 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 08:13:57.761385 Total UI for P1: 0, mck2ui 16
5385 08:13:57.764690 best dqsien dly found for B1: ( 1, 3, 0)
5386 08:13:57.767552 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5387 08:13:57.771263 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5388 08:13:57.771839
5389 08:13:57.777834 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5390 08:13:57.781456 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5391 08:13:57.782030 [Gating] SW calibration Done
5392 08:13:57.784763 ==
5393 08:13:57.787335 Dram Type= 6, Freq= 0, CH_0, rank 1
5394 08:13:57.791208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5395 08:13:57.791870 ==
5396 08:13:57.792252 RX Vref Scan: 0
5397 08:13:57.792602
5398 08:13:57.794520 RX Vref 0 -> 0, step: 1
5399 08:13:57.795027
5400 08:13:57.797625 RX Delay -80 -> 252, step: 8
5401 08:13:57.801473 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5402 08:13:57.804129 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5403 08:13:57.807748 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5404 08:13:57.813815 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5405 08:13:57.817619 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5406 08:13:57.820742 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5407 08:13:57.824295 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5408 08:13:57.827655 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5409 08:13:57.830281 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5410 08:13:57.837477 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5411 08:13:57.840579 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5412 08:13:57.844059 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5413 08:13:57.847094 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5414 08:13:57.850269 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5415 08:13:57.857047 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5416 08:13:57.860751 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5417 08:13:57.861321 ==
5418 08:13:57.864043 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 08:13:57.866751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 08:13:57.867323 ==
5421 08:13:57.870297 DQS Delay:
5422 08:13:57.870892 DQS0 = 0, DQS1 = 0
5423 08:13:57.871268 DQM Delay:
5424 08:13:57.873758 DQM0 = 96, DQM1 = 89
5425 08:13:57.874325 DQ Delay:
5426 08:13:57.876503 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5427 08:13:57.880437 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5428 08:13:57.883366 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5429 08:13:57.886865 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5430 08:13:57.887426
5431 08:13:57.887787
5432 08:13:57.888122 ==
5433 08:13:57.890208 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 08:13:57.896674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 08:13:57.897246 ==
5436 08:13:57.897672
5437 08:13:57.898024
5438 08:13:57.898351 TX Vref Scan disable
5439 08:13:57.900572 == TX Byte 0 ==
5440 08:13:57.903690 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5441 08:13:57.910595 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5442 08:13:57.911156 == TX Byte 1 ==
5443 08:13:57.913896 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5444 08:13:57.920534 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5445 08:13:57.921122 ==
5446 08:13:57.923438 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 08:13:57.927057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 08:13:57.927545 ==
5449 08:13:57.927920
5450 08:13:57.928275
5451 08:13:57.929722 TX Vref Scan disable
5452 08:13:57.930189 == TX Byte 0 ==
5453 08:13:57.936640 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5454 08:13:57.939933 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5455 08:13:57.943891 == TX Byte 1 ==
5456 08:13:57.946452 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5457 08:13:57.949567 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5458 08:13:57.949997
5459 08:13:57.950335 [DATLAT]
5460 08:13:57.953079 Freq=933, CH0 RK1
5461 08:13:57.953554
5462 08:13:57.953900 DATLAT Default: 0xb
5463 08:13:57.956460 0, 0xFFFF, sum = 0
5464 08:13:57.959490 1, 0xFFFF, sum = 0
5465 08:13:57.959930 2, 0xFFFF, sum = 0
5466 08:13:57.963141 3, 0xFFFF, sum = 0
5467 08:13:57.963572 4, 0xFFFF, sum = 0
5468 08:13:57.966264 5, 0xFFFF, sum = 0
5469 08:13:57.966799 6, 0xFFFF, sum = 0
5470 08:13:57.969629 7, 0xFFFF, sum = 0
5471 08:13:57.970159 8, 0xFFFF, sum = 0
5472 08:13:57.973153 9, 0xFFFF, sum = 0
5473 08:13:57.973767 10, 0x0, sum = 1
5474 08:13:57.976365 11, 0x0, sum = 2
5475 08:13:57.976813 12, 0x0, sum = 3
5476 08:13:57.979464 13, 0x0, sum = 4
5477 08:13:57.979997 best_step = 11
5478 08:13:57.980337
5479 08:13:57.980653 ==
5480 08:13:57.982633 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 08:13:57.986299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 08:13:57.989487 ==
5483 08:13:57.990019 RX Vref Scan: 0
5484 08:13:57.990359
5485 08:13:57.992184 RX Vref 0 -> 0, step: 1
5486 08:13:57.992607
5487 08:13:57.995662 RX Delay -61 -> 252, step: 4
5488 08:13:57.999565 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5489 08:13:58.002621 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5490 08:13:58.009232 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5491 08:13:58.012456 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5492 08:13:58.015585 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5493 08:13:58.018519 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5494 08:13:58.022075 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5495 08:13:58.025897 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5496 08:13:58.032212 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5497 08:13:58.035316 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5498 08:13:58.038278 iDelay=203, Bit 10, Center 88 (-9 ~ 186) 196
5499 08:13:58.041862 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5500 08:13:58.048614 iDelay=203, Bit 12, Center 92 (-5 ~ 190) 196
5501 08:13:58.051576 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5502 08:13:58.055211 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5503 08:13:58.058412 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5504 08:13:58.058943 ==
5505 08:13:58.061533 Dram Type= 6, Freq= 0, CH_0, rank 1
5506 08:13:58.065033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 08:13:58.067906 ==
5508 08:13:58.068447 DQS Delay:
5509 08:13:58.068791 DQS0 = 0, DQS1 = 0
5510 08:13:58.071529 DQM Delay:
5511 08:13:58.072055 DQM0 = 94, DQM1 = 87
5512 08:13:58.074656 DQ Delay:
5513 08:13:58.078117 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
5514 08:13:58.081924 DQ4 =94, DQ5 =86, DQ6 =106, DQ7 =104
5515 08:13:58.084511 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =80
5516 08:13:58.087658 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
5517 08:13:58.088087
5518 08:13:58.088422
5519 08:13:58.094760 [DQSOSCAuto] RK1, (LSB)MR18= 0x22f4, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 411 ps
5520 08:13:58.097559 CH0 RK1: MR19=504, MR18=22F4
5521 08:13:58.104602 CH0_RK1: MR19=0x504, MR18=0x22F4, DQSOSC=411, MR23=63, INC=64, DEC=42
5522 08:13:58.108001 [RxdqsGatingPostProcess] freq 933
5523 08:13:58.110921 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5524 08:13:58.114443 best DQS0 dly(2T, 0.5T) = (0, 10)
5525 08:13:58.117883 best DQS1 dly(2T, 0.5T) = (0, 11)
5526 08:13:58.120631 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5527 08:13:58.124416 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5528 08:13:58.127561 best DQS0 dly(2T, 0.5T) = (0, 10)
5529 08:13:58.130443 best DQS1 dly(2T, 0.5T) = (0, 11)
5530 08:13:58.134058 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5531 08:13:58.137276 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5532 08:13:58.140453 Pre-setting of DQS Precalculation
5533 08:13:58.143478 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5534 08:13:58.146715 ==
5535 08:13:58.150651 Dram Type= 6, Freq= 0, CH_1, rank 0
5536 08:13:58.153788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 08:13:58.154310 ==
5538 08:13:58.156776 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5539 08:13:58.163486 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5540 08:13:58.167710 [CA 0] Center 37 (7~67) winsize 61
5541 08:13:58.170645 [CA 1] Center 37 (7~68) winsize 62
5542 08:13:58.173884 [CA 2] Center 34 (4~65) winsize 62
5543 08:13:58.177615 [CA 3] Center 33 (3~64) winsize 62
5544 08:13:58.180971 [CA 4] Center 35 (5~65) winsize 61
5545 08:13:58.184046 [CA 5] Center 33 (3~64) winsize 62
5546 08:13:58.184585
5547 08:13:58.186908 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5548 08:13:58.187437
5549 08:13:58.193924 [CATrainingPosCal] consider 1 rank data
5550 08:13:58.194466 u2DelayCellTimex100 = 270/100 ps
5551 08:13:58.200560 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5552 08:13:58.203521 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5553 08:13:58.206883 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5554 08:13:58.210309 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5555 08:13:58.213213 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5556 08:13:58.216693 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5557 08:13:58.217220
5558 08:13:58.220365 CA PerBit enable=1, Macro0, CA PI delay=33
5559 08:13:58.220893
5560 08:13:58.223554 [CBTSetCACLKResult] CA Dly = 33
5561 08:13:58.226201 CS Dly: 6 (0~37)
5562 08:13:58.226664 ==
5563 08:13:58.229642 Dram Type= 6, Freq= 0, CH_1, rank 1
5564 08:13:58.233518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 08:13:58.234055 ==
5566 08:13:58.239807 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5567 08:13:58.243353 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5568 08:13:58.247292 [CA 0] Center 37 (7~67) winsize 61
5569 08:13:58.250585 [CA 1] Center 37 (7~68) winsize 62
5570 08:13:58.253883 [CA 2] Center 34 (4~65) winsize 62
5571 08:13:58.257700 [CA 3] Center 34 (4~65) winsize 62
5572 08:13:58.260843 [CA 4] Center 34 (4~65) winsize 62
5573 08:13:58.263586 [CA 5] Center 33 (3~64) winsize 62
5574 08:13:58.264009
5575 08:13:58.267016 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5576 08:13:58.267450
5577 08:13:58.271024 [CATrainingPosCal] consider 2 rank data
5578 08:13:58.273750 u2DelayCellTimex100 = 270/100 ps
5579 08:13:58.277300 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5580 08:13:58.284296 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5581 08:13:58.287713 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5582 08:13:58.290123 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5583 08:13:58.293765 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5584 08:13:58.296624 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5585 08:13:58.297050
5586 08:13:58.300032 CA PerBit enable=1, Macro0, CA PI delay=33
5587 08:13:58.300460
5588 08:13:58.303673 [CBTSetCACLKResult] CA Dly = 33
5589 08:13:58.306375 CS Dly: 7 (0~39)
5590 08:13:58.306983
5591 08:13:58.309643 ----->DramcWriteLeveling(PI) begin...
5592 08:13:58.310072 ==
5593 08:13:58.313195 Dram Type= 6, Freq= 0, CH_1, rank 0
5594 08:13:58.316485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5595 08:13:58.317009 ==
5596 08:13:58.320079 Write leveling (Byte 0): 26 => 26
5597 08:13:58.323160 Write leveling (Byte 1): 25 => 25
5598 08:13:58.326727 DramcWriteLeveling(PI) end<-----
5599 08:13:58.327255
5600 08:13:58.327596 ==
5601 08:13:58.329441 Dram Type= 6, Freq= 0, CH_1, rank 0
5602 08:13:58.332694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5603 08:13:58.333241 ==
5604 08:13:58.336145 [Gating] SW mode calibration
5605 08:13:58.343087 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5606 08:13:58.349271 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5607 08:13:58.353104 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 08:13:58.359076 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 08:13:58.362392 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 08:13:58.365683 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 08:13:58.372477 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 08:13:58.375637 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 08:13:58.379038 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5614 08:13:58.385453 0 14 28 | B1->B0 | 3030 2e2e | 0 0 | (1 1) (1 1)
5615 08:13:58.388430 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 08:13:58.392161 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 08:13:58.399148 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 08:13:58.401918 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 08:13:58.405141 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 08:13:58.411714 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 08:13:58.414954 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 08:13:58.418153 0 15 28 | B1->B0 | 3333 3737 | 0 1 | (0 0) (0 0)
5623 08:13:58.424605 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 08:13:58.428051 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 08:13:58.431359 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 08:13:58.438356 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 08:13:58.441767 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 08:13:58.444731 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 08:13:58.451363 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5630 08:13:58.454227 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5631 08:13:58.457952 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 08:13:58.464349 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 08:13:58.467311 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 08:13:58.471003 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 08:13:58.477174 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 08:13:58.480453 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 08:13:58.483502 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 08:13:58.490084 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 08:13:58.493498 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 08:13:58.496991 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 08:13:58.503504 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 08:13:58.506551 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 08:13:58.509972 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 08:13:58.516632 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5645 08:13:58.519779 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5646 08:13:58.523366 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 08:13:58.526226 Total UI for P1: 0, mck2ui 16
5648 08:13:58.529346 best dqsien dly found for B0: ( 1, 2, 22)
5649 08:13:58.532916 Total UI for P1: 0, mck2ui 16
5650 08:13:58.536615 best dqsien dly found for B1: ( 1, 2, 24)
5651 08:13:58.539502 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5652 08:13:58.543541 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5653 08:13:58.543625
5654 08:13:58.549696 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5655 08:13:58.552837 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5656 08:13:58.556206 [Gating] SW calibration Done
5657 08:13:58.556289 ==
5658 08:13:58.559434 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 08:13:58.563145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 08:13:58.563228 ==
5661 08:13:58.563293 RX Vref Scan: 0
5662 08:13:58.563354
5663 08:13:58.565815 RX Vref 0 -> 0, step: 1
5664 08:13:58.565897
5665 08:13:58.569604 RX Delay -80 -> 252, step: 8
5666 08:13:58.572625 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5667 08:13:58.576334 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5668 08:13:58.582526 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5669 08:13:58.585616 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5670 08:13:58.589415 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5671 08:13:58.592166 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5672 08:13:58.595457 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5673 08:13:58.598689 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5674 08:13:58.605368 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5675 08:13:58.609222 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5676 08:13:58.612283 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5677 08:13:58.615921 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5678 08:13:58.622886 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5679 08:13:58.625060 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5680 08:13:58.629079 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5681 08:13:58.632168 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5682 08:13:58.632633 ==
5683 08:13:58.635329 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 08:13:58.638615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 08:13:58.639188 ==
5686 08:13:58.641994 DQS Delay:
5687 08:13:58.642454 DQS0 = 0, DQS1 = 0
5688 08:13:58.645308 DQM Delay:
5689 08:13:58.645842 DQM0 = 102, DQM1 = 91
5690 08:13:58.646212 DQ Delay:
5691 08:13:58.649201 DQ0 =107, DQ1 =95, DQ2 =95, DQ3 =103
5692 08:13:58.652041 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5693 08:13:58.655812 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5694 08:13:58.662018 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5695 08:13:58.662490
5696 08:13:58.662855
5697 08:13:58.663203 ==
5698 08:13:58.665136 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 08:13:58.668982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 08:13:58.669592 ==
5701 08:13:58.669970
5702 08:13:58.670314
5703 08:13:58.671570 TX Vref Scan disable
5704 08:13:58.672037 == TX Byte 0 ==
5705 08:13:58.677958 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5706 08:13:58.681194 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5707 08:13:58.684615 == TX Byte 1 ==
5708 08:13:58.688271 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5709 08:13:58.690887 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5710 08:13:58.691362 ==
5711 08:13:58.694049 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 08:13:58.697581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 08:13:58.700679 ==
5714 08:13:58.701143
5715 08:13:58.701565
5716 08:13:58.701918 TX Vref Scan disable
5717 08:13:58.704340 == TX Byte 0 ==
5718 08:13:58.707648 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5719 08:13:58.714134 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5720 08:13:58.714693 == TX Byte 1 ==
5721 08:13:58.717429 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5722 08:13:58.724237 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5723 08:13:58.724811
5724 08:13:58.725184 [DATLAT]
5725 08:13:58.725616 Freq=933, CH1 RK0
5726 08:13:58.725963
5727 08:13:58.727282 DATLAT Default: 0xd
5728 08:13:58.730923 0, 0xFFFF, sum = 0
5729 08:13:58.731503 1, 0xFFFF, sum = 0
5730 08:13:58.734199 2, 0xFFFF, sum = 0
5731 08:13:58.734669 3, 0xFFFF, sum = 0
5732 08:13:58.737099 4, 0xFFFF, sum = 0
5733 08:13:58.737647 5, 0xFFFF, sum = 0
5734 08:13:58.740603 6, 0xFFFF, sum = 0
5735 08:13:58.741075 7, 0xFFFF, sum = 0
5736 08:13:58.744144 8, 0xFFFF, sum = 0
5737 08:13:58.744718 9, 0xFFFF, sum = 0
5738 08:13:58.746949 10, 0x0, sum = 1
5739 08:13:58.747525 11, 0x0, sum = 2
5740 08:13:58.750215 12, 0x0, sum = 3
5741 08:13:58.750740 13, 0x0, sum = 4
5742 08:13:58.753953 best_step = 11
5743 08:13:58.754557
5744 08:13:58.754932 ==
5745 08:13:58.756818 Dram Type= 6, Freq= 0, CH_1, rank 0
5746 08:13:58.760566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 08:13:58.761141 ==
5748 08:13:58.761554 RX Vref Scan: 1
5749 08:13:58.763645
5750 08:13:58.764108 RX Vref 0 -> 0, step: 1
5751 08:13:58.764479
5752 08:13:58.766614 RX Delay -61 -> 252, step: 4
5753 08:13:58.767082
5754 08:13:58.770450 Set Vref, RX VrefLevel [Byte0]: 51
5755 08:13:58.773562 [Byte1]: 51
5756 08:13:58.776837
5757 08:13:58.780596 Final RX Vref Byte 0 = 51 to rank0
5758 08:13:58.781066 Final RX Vref Byte 1 = 51 to rank0
5759 08:13:58.783716 Final RX Vref Byte 0 = 51 to rank1
5760 08:13:58.786658 Final RX Vref Byte 1 = 51 to rank1==
5761 08:13:58.790052 Dram Type= 6, Freq= 0, CH_1, rank 0
5762 08:13:58.796249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 08:13:58.796812 ==
5764 08:13:58.797275 DQS Delay:
5765 08:13:58.799840 DQS0 = 0, DQS1 = 0
5766 08:13:58.800409 DQM Delay:
5767 08:13:58.803025 DQM0 = 100, DQM1 = 93
5768 08:13:58.803588 DQ Delay:
5769 08:13:58.806421 DQ0 =104, DQ1 =94, DQ2 =92, DQ3 =98
5770 08:13:58.809451 DQ4 =96, DQ5 =112, DQ6 =110, DQ7 =96
5771 08:13:58.813246 DQ8 =80, DQ9 =84, DQ10 =96, DQ11 =84
5772 08:13:58.816867 DQ12 =102, DQ13 =100, DQ14 =102, DQ15 =102
5773 08:13:58.817564
5774 08:13:58.818126
5775 08:13:58.823058 [DQSOSCAuto] RK0, (LSB)MR18= 0x1202, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 416 ps
5776 08:13:58.826143 CH1 RK0: MR19=505, MR18=1202
5777 08:13:58.832738 CH1_RK0: MR19=0x505, MR18=0x1202, DQSOSC=416, MR23=63, INC=62, DEC=41
5778 08:13:58.833310
5779 08:13:58.836213 ----->DramcWriteLeveling(PI) begin...
5780 08:13:58.836802 ==
5781 08:13:58.839030 Dram Type= 6, Freq= 0, CH_1, rank 1
5782 08:13:58.845983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 08:13:58.846589 ==
5784 08:13:58.849392 Write leveling (Byte 0): 26 => 26
5785 08:13:58.849965 Write leveling (Byte 1): 27 => 27
5786 08:13:58.852693 DramcWriteLeveling(PI) end<-----
5787 08:13:58.853398
5788 08:13:58.856122 ==
5789 08:13:58.858609 Dram Type= 6, Freq= 0, CH_1, rank 1
5790 08:13:58.862055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 08:13:58.862633 ==
5792 08:13:58.865660 [Gating] SW mode calibration
5793 08:13:58.872310 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5794 08:13:58.875182 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5795 08:13:58.882090 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5796 08:13:58.885523 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 08:13:58.888391 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 08:13:58.894859 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 08:13:58.898331 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 08:13:58.901967 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 08:13:58.908382 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5802 08:13:58.911498 0 14 28 | B1->B0 | 2e2e 3333 | 0 0 | (1 1) (0 1)
5803 08:13:58.915253 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5804 08:13:58.921523 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 08:13:58.924728 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 08:13:58.928392 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 08:13:58.934530 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 08:13:58.938040 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 08:13:58.941312 0 15 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5810 08:13:58.948631 0 15 28 | B1->B0 | 3c3c 2e2e | 0 0 | (1 1) (0 0)
5811 08:13:58.951068 1 0 0 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
5812 08:13:58.954631 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 08:13:58.961099 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 08:13:58.964439 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 08:13:58.967492 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 08:13:58.974369 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 08:13:58.977462 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5818 08:13:58.980903 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5819 08:13:58.987787 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 08:13:58.990887 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 08:13:58.994047 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 08:13:59.001212 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 08:13:59.004373 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 08:13:59.007569 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 08:13:59.014239 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 08:13:59.016922 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 08:13:59.020342 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 08:13:59.027200 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 08:13:59.030475 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 08:13:59.033715 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 08:13:59.040044 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 08:13:59.043564 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5833 08:13:59.046658 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5834 08:13:59.053314 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5835 08:13:59.056900 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 08:13:59.059612 Total UI for P1: 0, mck2ui 16
5837 08:13:59.063027 best dqsien dly found for B0: ( 1, 2, 28)
5838 08:13:59.066943 Total UI for P1: 0, mck2ui 16
5839 08:13:59.069570 best dqsien dly found for B1: ( 1, 2, 24)
5840 08:13:59.072893 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5841 08:13:59.076450 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5842 08:13:59.076917
5843 08:13:59.079466 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5844 08:13:59.086169 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5845 08:13:59.086756 [Gating] SW calibration Done
5846 08:13:59.087136 ==
5847 08:13:59.089648 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 08:13:59.096108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 08:13:59.096670 ==
5850 08:13:59.097045 RX Vref Scan: 0
5851 08:13:59.097452
5852 08:13:59.099112 RX Vref 0 -> 0, step: 1
5853 08:13:59.099582
5854 08:13:59.102627 RX Delay -80 -> 252, step: 8
5855 08:13:59.105917 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5856 08:13:59.109419 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5857 08:13:59.112265 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5858 08:13:59.115947 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5859 08:13:59.122307 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5860 08:13:59.125707 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5861 08:13:59.129212 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5862 08:13:59.132056 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5863 08:13:59.135223 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5864 08:13:59.142339 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5865 08:13:59.145214 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5866 08:13:59.148653 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5867 08:13:59.152011 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5868 08:13:59.155247 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5869 08:13:59.161949 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5870 08:13:59.164939 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5871 08:13:59.165556 ==
5872 08:13:59.168437 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 08:13:59.171529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 08:13:59.172099 ==
5875 08:13:59.174421 DQS Delay:
5876 08:13:59.174886 DQS0 = 0, DQS1 = 0
5877 08:13:59.175256 DQM Delay:
5878 08:13:59.178193 DQM0 = 100, DQM1 = 92
5879 08:13:59.178771 DQ Delay:
5880 08:13:59.181504 DQ0 =103, DQ1 =99, DQ2 =91, DQ3 =99
5881 08:13:59.184248 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5882 08:13:59.187754 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5883 08:13:59.191137 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =99
5884 08:13:59.191605
5885 08:13:59.191967
5886 08:13:59.194524 ==
5887 08:13:59.197618 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 08:13:59.201261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 08:13:59.201778 ==
5890 08:13:59.202150
5891 08:13:59.202492
5892 08:13:59.204110 TX Vref Scan disable
5893 08:13:59.204580 == TX Byte 0 ==
5894 08:13:59.207455 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5895 08:13:59.214059 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5896 08:13:59.214307 == TX Byte 1 ==
5897 08:13:59.220672 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5898 08:13:59.223980 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5899 08:13:59.224227 ==
5900 08:13:59.226982 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 08:13:59.230366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 08:13:59.230614 ==
5903 08:13:59.230758
5904 08:13:59.230886
5905 08:13:59.233847 TX Vref Scan disable
5906 08:13:59.237173 == TX Byte 0 ==
5907 08:13:59.240128 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5908 08:13:59.243751 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5909 08:13:59.246650 == TX Byte 1 ==
5910 08:13:59.250224 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5911 08:13:59.253840 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5912 08:13:59.254110
5913 08:13:59.256585 [DATLAT]
5914 08:13:59.256853 Freq=933, CH1 RK1
5915 08:13:59.257012
5916 08:13:59.260258 DATLAT Default: 0xb
5917 08:13:59.260612 0, 0xFFFF, sum = 0
5918 08:13:59.263813 1, 0xFFFF, sum = 0
5919 08:13:59.264172 2, 0xFFFF, sum = 0
5920 08:13:59.266998 3, 0xFFFF, sum = 0
5921 08:13:59.267362 4, 0xFFFF, sum = 0
5922 08:13:59.270468 5, 0xFFFF, sum = 0
5923 08:13:59.270907 6, 0xFFFF, sum = 0
5924 08:13:59.273669 7, 0xFFFF, sum = 0
5925 08:13:59.274204 8, 0xFFFF, sum = 0
5926 08:13:59.276980 9, 0xFFFF, sum = 0
5927 08:13:59.277558 10, 0x0, sum = 1
5928 08:13:59.280634 11, 0x0, sum = 2
5929 08:13:59.281170 12, 0x0, sum = 3
5930 08:13:59.283432 13, 0x0, sum = 4
5931 08:13:59.283960 best_step = 11
5932 08:13:59.284296
5933 08:13:59.284604 ==
5934 08:13:59.287059 Dram Type= 6, Freq= 0, CH_1, rank 1
5935 08:13:59.293539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5936 08:13:59.294101 ==
5937 08:13:59.294471 RX Vref Scan: 0
5938 08:13:59.294811
5939 08:13:59.296751 RX Vref 0 -> 0, step: 1
5940 08:13:59.297211
5941 08:13:59.299486 RX Delay -61 -> 252, step: 4
5942 08:13:59.302857 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5943 08:13:59.309745 iDelay=207, Bit 1, Center 96 (11 ~ 182) 172
5944 08:13:59.313265 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5945 08:13:59.316646 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5946 08:13:59.319583 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
5947 08:13:59.322845 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5948 08:13:59.326755 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5949 08:13:59.332936 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5950 08:13:59.336473 iDelay=207, Bit 8, Center 80 (-9 ~ 170) 180
5951 08:13:59.339976 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
5952 08:13:59.343023 iDelay=207, Bit 10, Center 92 (3 ~ 182) 180
5953 08:13:59.346463 iDelay=207, Bit 11, Center 84 (-1 ~ 170) 172
5954 08:13:59.352973 iDelay=207, Bit 12, Center 106 (15 ~ 198) 184
5955 08:13:59.356144 iDelay=207, Bit 13, Center 102 (15 ~ 190) 176
5956 08:13:59.359618 iDelay=207, Bit 14, Center 100 (15 ~ 186) 172
5957 08:13:59.363155 iDelay=207, Bit 15, Center 102 (15 ~ 190) 176
5958 08:13:59.363717 ==
5959 08:13:59.365832 Dram Type= 6, Freq= 0, CH_1, rank 1
5960 08:13:59.372666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5961 08:13:59.373304 ==
5962 08:13:59.373738 DQS Delay:
5963 08:13:59.376081 DQS0 = 0, DQS1 = 0
5964 08:13:59.376640 DQM Delay:
5965 08:13:59.377005 DQM0 = 101, DQM1 = 93
5966 08:13:59.379039 DQ Delay:
5967 08:13:59.382024 DQ0 =106, DQ1 =96, DQ2 =90, DQ3 =98
5968 08:13:59.385696 DQ4 =100, DQ5 =110, DQ6 =114, DQ7 =98
5969 08:13:59.389512 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =84
5970 08:13:59.392154 DQ12 =106, DQ13 =102, DQ14 =100, DQ15 =102
5971 08:13:59.392624
5972 08:13:59.392993
5973 08:13:59.399093 [DQSOSCAuto] RK1, (LSB)MR18= 0x4fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 420 ps
5974 08:13:59.401925 CH1 RK1: MR19=504, MR18=4FD
5975 08:13:59.409433 CH1_RK1: MR19=0x504, MR18=0x4FD, DQSOSC=420, MR23=63, INC=61, DEC=40
5976 08:13:59.411763 [RxdqsGatingPostProcess] freq 933
5977 08:13:59.418467 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5978 08:13:59.421665 best DQS0 dly(2T, 0.5T) = (0, 10)
5979 08:13:59.422241 best DQS1 dly(2T, 0.5T) = (0, 10)
5980 08:13:59.425308 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5981 08:13:59.428492 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5982 08:13:59.432171 best DQS0 dly(2T, 0.5T) = (0, 10)
5983 08:13:59.435122 best DQS1 dly(2T, 0.5T) = (0, 10)
5984 08:13:59.438642 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5985 08:13:59.441842 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5986 08:13:59.444821 Pre-setting of DQS Precalculation
5987 08:13:59.451361 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5988 08:13:59.457608 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5989 08:13:59.464696 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5990 08:13:59.465160
5991 08:13:59.465615
5992 08:13:59.467752 [Calibration Summary] 1866 Mbps
5993 08:13:59.468214 CH 0, Rank 0
5994 08:13:59.471313 SW Impedance : PASS
5995 08:13:59.474505 DUTY Scan : NO K
5996 08:13:59.474964 ZQ Calibration : PASS
5997 08:13:59.477600 Jitter Meter : NO K
5998 08:13:59.480763 CBT Training : PASS
5999 08:13:59.481181 Write leveling : PASS
6000 08:13:59.484042 RX DQS gating : PASS
6001 08:13:59.487470 RX DQ/DQS(RDDQC) : PASS
6002 08:13:59.487897 TX DQ/DQS : PASS
6003 08:13:59.490814 RX DATLAT : PASS
6004 08:13:59.493833 RX DQ/DQS(Engine): PASS
6005 08:13:59.494256 TX OE : NO K
6006 08:13:59.497610 All Pass.
6007 08:13:59.498078
6008 08:13:59.498420 CH 0, Rank 1
6009 08:13:59.500451 SW Impedance : PASS
6010 08:13:59.500875 DUTY Scan : NO K
6011 08:13:59.503699 ZQ Calibration : PASS
6012 08:13:59.507201 Jitter Meter : NO K
6013 08:13:59.507624 CBT Training : PASS
6014 08:13:59.510660 Write leveling : PASS
6015 08:13:59.514047 RX DQS gating : PASS
6016 08:13:59.514472 RX DQ/DQS(RDDQC) : PASS
6017 08:13:59.517358 TX DQ/DQS : PASS
6018 08:13:59.520656 RX DATLAT : PASS
6019 08:13:59.521078 RX DQ/DQS(Engine): PASS
6020 08:13:59.523706 TX OE : NO K
6021 08:13:59.524129 All Pass.
6022 08:13:59.524464
6023 08:13:59.527040 CH 1, Rank 0
6024 08:13:59.527463 SW Impedance : PASS
6025 08:13:59.529906 DUTY Scan : NO K
6026 08:13:59.533910 ZQ Calibration : PASS
6027 08:13:59.534339 Jitter Meter : NO K
6028 08:13:59.536745 CBT Training : PASS
6029 08:13:59.540329 Write leveling : PASS
6030 08:13:59.540862 RX DQS gating : PASS
6031 08:13:59.543342 RX DQ/DQS(RDDQC) : PASS
6032 08:13:59.543763 TX DQ/DQS : PASS
6033 08:13:59.546919 RX DATLAT : PASS
6034 08:13:59.549791 RX DQ/DQS(Engine): PASS
6035 08:13:59.550218 TX OE : NO K
6036 08:13:59.553289 All Pass.
6037 08:13:59.553764
6038 08:13:59.554106 CH 1, Rank 1
6039 08:13:59.556750 SW Impedance : PASS
6040 08:13:59.557172 DUTY Scan : NO K
6041 08:13:59.559900 ZQ Calibration : PASS
6042 08:13:59.563392 Jitter Meter : NO K
6043 08:13:59.563821 CBT Training : PASS
6044 08:13:59.566689 Write leveling : PASS
6045 08:13:59.569671 RX DQS gating : PASS
6046 08:13:59.570202 RX DQ/DQS(RDDQC) : PASS
6047 08:13:59.573436 TX DQ/DQS : PASS
6048 08:13:59.576703 RX DATLAT : PASS
6049 08:13:59.577224 RX DQ/DQS(Engine): PASS
6050 08:13:59.579645 TX OE : NO K
6051 08:13:59.580106 All Pass.
6052 08:13:59.580445
6053 08:13:59.583388 DramC Write-DBI off
6054 08:13:59.585888 PER_BANK_REFRESH: Hybrid Mode
6055 08:13:59.586305 TX_TRACKING: ON
6056 08:13:59.595906 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6057 08:13:59.599210 [FAST_K] Save calibration result to emmc
6058 08:13:59.602415 dramc_set_vcore_voltage set vcore to 650000
6059 08:13:59.605997 Read voltage for 400, 6
6060 08:13:59.606481 Vio18 = 0
6061 08:13:59.606856 Vcore = 650000
6062 08:13:59.609092 Vdram = 0
6063 08:13:59.609618 Vddq = 0
6064 08:13:59.609988 Vmddr = 0
6065 08:13:59.616011 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6066 08:13:59.622164 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6067 08:13:59.622635 MEM_TYPE=3, freq_sel=20
6068 08:13:59.625441 sv_algorithm_assistance_LP4_800
6069 08:13:59.629322 ============ PULL DRAM RESETB DOWN ============
6070 08:13:59.635746 ========== PULL DRAM RESETB DOWN end =========
6071 08:13:59.639089 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6072 08:13:59.642625 ===================================
6073 08:13:59.645459 LPDDR4 DRAM CONFIGURATION
6074 08:13:59.649052 ===================================
6075 08:13:59.649663 EX_ROW_EN[0] = 0x0
6076 08:13:59.652071 EX_ROW_EN[1] = 0x0
6077 08:13:59.652631 LP4Y_EN = 0x0
6078 08:13:59.655797 WORK_FSP = 0x0
6079 08:13:59.656596 WL = 0x2
6080 08:13:59.658569 RL = 0x2
6081 08:13:59.661937 BL = 0x2
6082 08:13:59.662398 RPST = 0x0
6083 08:13:59.665276 RD_PRE = 0x0
6084 08:13:59.665883 WR_PRE = 0x1
6085 08:13:59.668817 WR_PST = 0x0
6086 08:13:59.669433 DBI_WR = 0x0
6087 08:13:59.671804 DBI_RD = 0x0
6088 08:13:59.672361 OTF = 0x1
6089 08:13:59.675384 ===================================
6090 08:13:59.678075 ===================================
6091 08:13:59.681798 ANA top config
6092 08:13:59.684743 ===================================
6093 08:13:59.685211 DLL_ASYNC_EN = 0
6094 08:13:59.688315 ALL_SLAVE_EN = 1
6095 08:13:59.691760 NEW_RANK_MODE = 1
6096 08:13:59.694932 DLL_IDLE_MODE = 1
6097 08:13:59.695444 LP45_APHY_COMB_EN = 1
6098 08:13:59.697751 TX_ODT_DIS = 1
6099 08:13:59.701282 NEW_8X_MODE = 1
6100 08:13:59.704629 ===================================
6101 08:13:59.708923 ===================================
6102 08:13:59.711858 data_rate = 800
6103 08:13:59.714849 CKR = 1
6104 08:13:59.718202 DQ_P2S_RATIO = 4
6105 08:13:59.721648 ===================================
6106 08:13:59.722147 CA_P2S_RATIO = 4
6107 08:13:59.724420 DQ_CA_OPEN = 0
6108 08:13:59.727930 DQ_SEMI_OPEN = 1
6109 08:13:59.731493 CA_SEMI_OPEN = 1
6110 08:13:59.734678 CA_FULL_RATE = 0
6111 08:13:59.737711 DQ_CKDIV4_EN = 0
6112 08:13:59.738175 CA_CKDIV4_EN = 1
6113 08:13:59.741074 CA_PREDIV_EN = 0
6114 08:13:59.744461 PH8_DLY = 0
6115 08:13:59.747611 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6116 08:13:59.750645 DQ_AAMCK_DIV = 0
6117 08:13:59.754441 CA_AAMCK_DIV = 0
6118 08:13:59.757194 CA_ADMCK_DIV = 4
6119 08:13:59.757715 DQ_TRACK_CA_EN = 0
6120 08:13:59.760639 CA_PICK = 800
6121 08:13:59.764489 CA_MCKIO = 400
6122 08:13:59.767733 MCKIO_SEMI = 400
6123 08:13:59.770508 PLL_FREQ = 3016
6124 08:13:59.774321 DQ_UI_PI_RATIO = 32
6125 08:13:59.776989 CA_UI_PI_RATIO = 32
6126 08:13:59.780222 ===================================
6127 08:13:59.783863 ===================================
6128 08:13:59.784323 memory_type:LPDDR4
6129 08:13:59.787461 GP_NUM : 10
6130 08:13:59.790253 SRAM_EN : 1
6131 08:13:59.790811 MD32_EN : 0
6132 08:13:59.793547 ===================================
6133 08:13:59.796676 [ANA_INIT] >>>>>>>>>>>>>>
6134 08:13:59.799945 <<<<<< [CONFIGURE PHASE]: ANA_TX
6135 08:13:59.803389 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6136 08:13:59.806998 ===================================
6137 08:13:59.809537 data_rate = 800,PCW = 0X7400
6138 08:13:59.813934 ===================================
6139 08:13:59.816519 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6140 08:13:59.819943 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6141 08:13:59.833176 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6142 08:13:59.836386 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6143 08:13:59.839779 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6144 08:13:59.842957 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6145 08:13:59.845856 [ANA_INIT] flow start
6146 08:13:59.849950 [ANA_INIT] PLL >>>>>>>>
6147 08:13:59.850543 [ANA_INIT] PLL <<<<<<<<
6148 08:13:59.852487 [ANA_INIT] MIDPI >>>>>>>>
6149 08:13:59.856061 [ANA_INIT] MIDPI <<<<<<<<
6150 08:13:59.859546 [ANA_INIT] DLL >>>>>>>>
6151 08:13:59.860136 [ANA_INIT] flow end
6152 08:13:59.862989 ============ LP4 DIFF to SE enter ============
6153 08:13:59.869082 ============ LP4 DIFF to SE exit ============
6154 08:13:59.869707 [ANA_INIT] <<<<<<<<<<<<<
6155 08:13:59.872726 [Flow] Enable top DCM control >>>>>
6156 08:13:59.875867 [Flow] Enable top DCM control <<<<<
6157 08:13:59.879175 Enable DLL master slave shuffle
6158 08:13:59.885656 ==============================================================
6159 08:13:59.886243 Gating Mode config
6160 08:13:59.892258 ==============================================================
6161 08:13:59.895643 Config description:
6162 08:13:59.905154 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6163 08:13:59.911603 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6164 08:13:59.915384 SELPH_MODE 0: By rank 1: By Phase
6165 08:13:59.921761 ==============================================================
6166 08:13:59.925216 GAT_TRACK_EN = 0
6167 08:13:59.928398 RX_GATING_MODE = 2
6168 08:13:59.931764 RX_GATING_TRACK_MODE = 2
6169 08:13:59.932320 SELPH_MODE = 1
6170 08:13:59.935219 PICG_EARLY_EN = 1
6171 08:13:59.937932 VALID_LAT_VALUE = 1
6172 08:13:59.944776 ==============================================================
6173 08:13:59.948380 Enter into Gating configuration >>>>
6174 08:13:59.951622 Exit from Gating configuration <<<<
6175 08:13:59.954661 Enter into DVFS_PRE_config >>>>>
6176 08:13:59.964549 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6177 08:13:59.967979 Exit from DVFS_PRE_config <<<<<
6178 08:13:59.970796 Enter into PICG configuration >>>>
6179 08:13:59.974665 Exit from PICG configuration <<<<
6180 08:13:59.977574 [RX_INPUT] configuration >>>>>
6181 08:13:59.980885 [RX_INPUT] configuration <<<<<
6182 08:13:59.987659 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6183 08:13:59.990940 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6184 08:13:59.997679 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6185 08:14:00.004124 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6186 08:14:00.010624 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6187 08:14:00.016915 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6188 08:14:00.020394 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6189 08:14:00.023937 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6190 08:14:00.026847 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6191 08:14:00.033778 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6192 08:14:00.037037 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6193 08:14:00.040083 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6194 08:14:00.043224 ===================================
6195 08:14:00.047017 LPDDR4 DRAM CONFIGURATION
6196 08:14:00.050006 ===================================
6197 08:14:00.053574 EX_ROW_EN[0] = 0x0
6198 08:14:00.054131 EX_ROW_EN[1] = 0x0
6199 08:14:00.056561 LP4Y_EN = 0x0
6200 08:14:00.057118 WORK_FSP = 0x0
6201 08:14:00.059912 WL = 0x2
6202 08:14:00.060470 RL = 0x2
6203 08:14:00.062816 BL = 0x2
6204 08:14:00.063278 RPST = 0x0
6205 08:14:00.066306 RD_PRE = 0x0
6206 08:14:00.066873 WR_PRE = 0x1
6207 08:14:00.069795 WR_PST = 0x0
6208 08:14:00.070350 DBI_WR = 0x0
6209 08:14:00.072908 DBI_RD = 0x0
6210 08:14:00.073512 OTF = 0x1
6211 08:14:00.076635 ===================================
6212 08:14:00.082867 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6213 08:14:00.086090 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6214 08:14:00.089805 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6215 08:14:00.092582 ===================================
6216 08:14:00.096175 LPDDR4 DRAM CONFIGURATION
6217 08:14:00.098904 ===================================
6218 08:14:00.102589 EX_ROW_EN[0] = 0x10
6219 08:14:00.103147 EX_ROW_EN[1] = 0x0
6220 08:14:00.106303 LP4Y_EN = 0x0
6221 08:14:00.106857 WORK_FSP = 0x0
6222 08:14:00.109148 WL = 0x2
6223 08:14:00.109743 RL = 0x2
6224 08:14:00.112985 BL = 0x2
6225 08:14:00.113584 RPST = 0x0
6226 08:14:00.115761 RD_PRE = 0x0
6227 08:14:00.116246 WR_PRE = 0x1
6228 08:14:00.118833 WR_PST = 0x0
6229 08:14:00.119312 DBI_WR = 0x0
6230 08:14:00.122316 DBI_RD = 0x0
6231 08:14:00.125524 OTF = 0x1
6232 08:14:00.129168 ===================================
6233 08:14:00.132183 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6234 08:14:00.137407 nWR fixed to 30
6235 08:14:00.141080 [ModeRegInit_LP4] CH0 RK0
6236 08:14:00.141699 [ModeRegInit_LP4] CH0 RK1
6237 08:14:00.143820 [ModeRegInit_LP4] CH1 RK0
6238 08:14:00.147539 [ModeRegInit_LP4] CH1 RK1
6239 08:14:00.148118 match AC timing 19
6240 08:14:00.153819 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6241 08:14:00.156891 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6242 08:14:00.160534 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6243 08:14:00.167219 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6244 08:14:00.170065 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6245 08:14:00.170581 ==
6246 08:14:00.173796 Dram Type= 6, Freq= 0, CH_0, rank 0
6247 08:14:00.177070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6248 08:14:00.177668 ==
6249 08:14:00.183286 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6250 08:14:00.189680 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6251 08:14:00.193392 [CA 0] Center 36 (8~64) winsize 57
6252 08:14:00.196857 [CA 1] Center 36 (8~64) winsize 57
6253 08:14:00.199674 [CA 2] Center 36 (8~64) winsize 57
6254 08:14:00.203637 [CA 3] Center 36 (8~64) winsize 57
6255 08:14:00.206523 [CA 4] Center 36 (8~64) winsize 57
6256 08:14:00.210188 [CA 5] Center 36 (8~64) winsize 57
6257 08:14:00.210747
6258 08:14:00.212937 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6259 08:14:00.213539
6260 08:14:00.216264 [CATrainingPosCal] consider 1 rank data
6261 08:14:00.219266 u2DelayCellTimex100 = 270/100 ps
6262 08:14:00.222648 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 08:14:00.225979 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 08:14:00.229276 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 08:14:00.232619 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 08:14:00.235696 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 08:14:00.239209 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 08:14:00.239678
6269 08:14:00.245799 CA PerBit enable=1, Macro0, CA PI delay=36
6270 08:14:00.246359
6271 08:14:00.246729 [CBTSetCACLKResult] CA Dly = 36
6272 08:14:00.249229 CS Dly: 1 (0~32)
6273 08:14:00.249923 ==
6274 08:14:00.252173 Dram Type= 6, Freq= 0, CH_0, rank 1
6275 08:14:00.255223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 08:14:00.255718 ==
6277 08:14:00.262216 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6278 08:14:00.269040 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6279 08:14:00.272106 [CA 0] Center 36 (8~64) winsize 57
6280 08:14:00.275784 [CA 1] Center 36 (8~64) winsize 57
6281 08:14:00.278580 [CA 2] Center 36 (8~64) winsize 57
6282 08:14:00.282248 [CA 3] Center 36 (8~64) winsize 57
6283 08:14:00.285115 [CA 4] Center 36 (8~64) winsize 57
6284 08:14:00.288557 [CA 5] Center 36 (8~64) winsize 57
6285 08:14:00.289116
6286 08:14:00.291588 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6287 08:14:00.292152
6288 08:14:00.294780 [CATrainingPosCal] consider 2 rank data
6289 08:14:00.297935 u2DelayCellTimex100 = 270/100 ps
6290 08:14:00.301285 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 08:14:00.304641 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 08:14:00.308055 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 08:14:00.311199 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 08:14:00.314745 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 08:14:00.317873 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 08:14:00.318341
6297 08:14:00.324272 CA PerBit enable=1, Macro0, CA PI delay=36
6298 08:14:00.324739
6299 08:14:00.327184 [CBTSetCACLKResult] CA Dly = 36
6300 08:14:00.327607 CS Dly: 1 (0~32)
6301 08:14:00.327940
6302 08:14:00.330662 ----->DramcWriteLeveling(PI) begin...
6303 08:14:00.331089 ==
6304 08:14:00.333846 Dram Type= 6, Freq= 0, CH_0, rank 0
6305 08:14:00.337411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 08:14:00.341224 ==
6307 08:14:00.341794 Write leveling (Byte 0): 40 => 8
6308 08:14:00.344059 Write leveling (Byte 1): 32 => 0
6309 08:14:00.347189 DramcWriteLeveling(PI) end<-----
6310 08:14:00.347613
6311 08:14:00.347944 ==
6312 08:14:00.351091 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 08:14:00.357136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 08:14:00.357600 ==
6315 08:14:00.360213 [Gating] SW mode calibration
6316 08:14:00.366615 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6317 08:14:00.370470 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6318 08:14:00.376939 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6319 08:14:00.380162 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6320 08:14:00.383639 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6321 08:14:00.390015 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6322 08:14:00.393401 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6323 08:14:00.396734 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6324 08:14:00.403460 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6325 08:14:00.406298 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 08:14:00.409640 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6327 08:14:00.412964 Total UI for P1: 0, mck2ui 16
6328 08:14:00.416481 best dqsien dly found for B0: ( 0, 14, 24)
6329 08:14:00.419401 Total UI for P1: 0, mck2ui 16
6330 08:14:00.422634 best dqsien dly found for B1: ( 0, 14, 24)
6331 08:14:00.425798 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6332 08:14:00.429531 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6333 08:14:00.432848
6334 08:14:00.435635 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6335 08:14:00.439080 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6336 08:14:00.442747 [Gating] SW calibration Done
6337 08:14:00.443209 ==
6338 08:14:00.445315 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 08:14:00.448936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 08:14:00.449446 ==
6341 08:14:00.449821 RX Vref Scan: 0
6342 08:14:00.452549
6343 08:14:00.453005 RX Vref 0 -> 0, step: 1
6344 08:14:00.453413
6345 08:14:00.455373 RX Delay -410 -> 252, step: 16
6346 08:14:00.458972 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6347 08:14:00.465238 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6348 08:14:00.468601 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6349 08:14:00.472050 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6350 08:14:00.475110 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6351 08:14:00.481381 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6352 08:14:00.484823 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6353 08:14:00.487846 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6354 08:14:00.491460 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6355 08:14:00.497924 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6356 08:14:00.500972 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6357 08:14:00.504417 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6358 08:14:00.510730 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6359 08:14:00.514136 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6360 08:14:00.517393 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6361 08:14:00.520761 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6362 08:14:00.523857 ==
6363 08:14:00.527292 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 08:14:00.530542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 08:14:00.530665 ==
6366 08:14:00.530736 DQS Delay:
6367 08:14:00.533563 DQS0 = 43, DQS1 = 59
6368 08:14:00.533707 DQM Delay:
6369 08:14:00.537081 DQM0 = 10, DQM1 = 12
6370 08:14:00.537216 DQ Delay:
6371 08:14:00.540203 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6372 08:14:00.543714 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =16
6373 08:14:00.547166 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6374 08:14:00.550643 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6375 08:14:00.550731
6376 08:14:00.550816
6377 08:14:00.550898 ==
6378 08:14:00.553681 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 08:14:00.557009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 08:14:00.557096 ==
6381 08:14:00.557198
6382 08:14:00.557298
6383 08:14:00.560238 TX Vref Scan disable
6384 08:14:00.560320 == TX Byte 0 ==
6385 08:14:00.566645 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6386 08:14:00.569816 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6387 08:14:00.569898 == TX Byte 1 ==
6388 08:14:00.576767 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6389 08:14:00.580241 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6390 08:14:00.580400 ==
6391 08:14:00.583439 Dram Type= 6, Freq= 0, CH_0, rank 0
6392 08:14:00.586455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6393 08:14:00.586615 ==
6394 08:14:00.589773
6395 08:14:00.589890
6396 08:14:00.589965 TX Vref Scan disable
6397 08:14:00.593373 == TX Byte 0 ==
6398 08:14:00.596554 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6399 08:14:00.599588 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6400 08:14:00.603149 == TX Byte 1 ==
6401 08:14:00.606156 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6402 08:14:00.609448 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6403 08:14:00.609828
6404 08:14:00.613188 [DATLAT]
6405 08:14:00.613701 Freq=400, CH0 RK0
6406 08:14:00.614183
6407 08:14:00.616463 DATLAT Default: 0xf
6408 08:14:00.616892 0, 0xFFFF, sum = 0
6409 08:14:00.619475 1, 0xFFFF, sum = 0
6410 08:14:00.619966 2, 0xFFFF, sum = 0
6411 08:14:00.622950 3, 0xFFFF, sum = 0
6412 08:14:00.623373 4, 0xFFFF, sum = 0
6413 08:14:00.626377 5, 0xFFFF, sum = 0
6414 08:14:00.626814 6, 0xFFFF, sum = 0
6415 08:14:00.629595 7, 0xFFFF, sum = 0
6416 08:14:00.630098 8, 0xFFFF, sum = 0
6417 08:14:00.632827 9, 0xFFFF, sum = 0
6418 08:14:00.633436 10, 0xFFFF, sum = 0
6419 08:14:00.636120 11, 0xFFFF, sum = 0
6420 08:14:00.639404 12, 0xFFFF, sum = 0
6421 08:14:00.639843 13, 0x0, sum = 1
6422 08:14:00.640183 14, 0x0, sum = 2
6423 08:14:00.642807 15, 0x0, sum = 3
6424 08:14:00.643238 16, 0x0, sum = 4
6425 08:14:00.645692 best_step = 14
6426 08:14:00.646113
6427 08:14:00.646448 ==
6428 08:14:00.649106 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 08:14:00.652686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 08:14:00.653115 ==
6431 08:14:00.655923 RX Vref Scan: 1
6432 08:14:00.656435
6433 08:14:00.659002 RX Vref 0 -> 0, step: 1
6434 08:14:00.659430
6435 08:14:00.659767 RX Delay -359 -> 252, step: 8
6436 08:14:00.660084
6437 08:14:00.662247 Set Vref, RX VrefLevel [Byte0]: 61
6438 08:14:00.665712 [Byte1]: 56
6439 08:14:00.671239
6440 08:14:00.671668 Final RX Vref Byte 0 = 61 to rank0
6441 08:14:00.674207 Final RX Vref Byte 1 = 56 to rank0
6442 08:14:00.677631 Final RX Vref Byte 0 = 61 to rank1
6443 08:14:00.680623 Final RX Vref Byte 1 = 56 to rank1==
6444 08:14:00.684212 Dram Type= 6, Freq= 0, CH_0, rank 0
6445 08:14:00.690505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 08:14:00.690935 ==
6447 08:14:00.691272 DQS Delay:
6448 08:14:00.694200 DQS0 = 48, DQS1 = 60
6449 08:14:00.694627 DQM Delay:
6450 08:14:00.694963 DQM0 = 11, DQM1 = 12
6451 08:14:00.697076 DQ Delay:
6452 08:14:00.700961 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6453 08:14:00.703752 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6454 08:14:00.704191 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6455 08:14:00.710843 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6456 08:14:00.711280
6457 08:14:00.711618
6458 08:14:00.716895 [DQSOSCAuto] RK0, (LSB)MR18= 0xaa6e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 388 ps
6459 08:14:00.720080 CH0 RK0: MR19=C0C, MR18=AA6E
6460 08:14:00.726583 CH0_RK0: MR19=0xC0C, MR18=0xAA6E, DQSOSC=388, MR23=63, INC=392, DEC=261
6461 08:14:00.727039 ==
6462 08:14:00.730187 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 08:14:00.733115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 08:14:00.733618 ==
6465 08:14:00.736679 [Gating] SW mode calibration
6466 08:14:00.743662 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6467 08:14:00.750100 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6468 08:14:00.753096 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6469 08:14:00.756184 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6470 08:14:00.763066 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6471 08:14:00.765946 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6472 08:14:00.769426 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 08:14:00.775847 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6474 08:14:00.779160 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 08:14:00.782438 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 08:14:00.788795 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6477 08:14:00.792479 Total UI for P1: 0, mck2ui 16
6478 08:14:00.795672 best dqsien dly found for B0: ( 0, 14, 24)
6479 08:14:00.798906 Total UI for P1: 0, mck2ui 16
6480 08:14:00.802158 best dqsien dly found for B1: ( 0, 14, 24)
6481 08:14:00.805951 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6482 08:14:00.808871 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6483 08:14:00.809120
6484 08:14:00.812096 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6485 08:14:00.815323 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6486 08:14:00.818484 [Gating] SW calibration Done
6487 08:14:00.818682 ==
6488 08:14:00.822033 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 08:14:00.825585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 08:14:00.825788 ==
6491 08:14:00.828510 RX Vref Scan: 0
6492 08:14:00.828702
6493 08:14:00.832188 RX Vref 0 -> 0, step: 1
6494 08:14:00.832486
6495 08:14:00.834982 RX Delay -410 -> 252, step: 16
6496 08:14:00.838671 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6497 08:14:00.841427 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6498 08:14:00.844794 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6499 08:14:00.851651 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6500 08:14:00.854718 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6501 08:14:00.858378 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6502 08:14:00.861313 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6503 08:14:00.867849 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6504 08:14:00.871521 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6505 08:14:00.874568 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6506 08:14:00.881056 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6507 08:14:00.884409 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6508 08:14:00.887606 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6509 08:14:00.890818 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6510 08:14:00.897440 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6511 08:14:00.901112 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6512 08:14:00.901257 ==
6513 08:14:00.904111 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 08:14:00.907867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 08:14:00.907990 ==
6516 08:14:00.910671 DQS Delay:
6517 08:14:00.910787 DQS0 = 43, DQS1 = 59
6518 08:14:00.914091 DQM Delay:
6519 08:14:00.914260 DQM0 = 10, DQM1 = 15
6520 08:14:00.914345 DQ Delay:
6521 08:14:00.917491 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6522 08:14:00.920687 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6523 08:14:00.924365 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6524 08:14:00.927242 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6525 08:14:00.927416
6526 08:14:00.927509
6527 08:14:00.927590 ==
6528 08:14:00.930792 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 08:14:00.937205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 08:14:00.937421 ==
6531 08:14:00.937526
6532 08:14:00.937608
6533 08:14:00.937683 TX Vref Scan disable
6534 08:14:00.940275 == TX Byte 0 ==
6535 08:14:00.944108 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6536 08:14:00.947492 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6537 08:14:00.950655 == TX Byte 1 ==
6538 08:14:00.954281 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6539 08:14:00.957244 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6540 08:14:00.957974 ==
6541 08:14:00.960365 Dram Type= 6, Freq= 0, CH_0, rank 1
6542 08:14:00.966861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6543 08:14:00.967330 ==
6544 08:14:00.967809
6545 08:14:00.968160
6546 08:14:00.970423 TX Vref Scan disable
6547 08:14:00.970917 == TX Byte 0 ==
6548 08:14:00.973542 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6549 08:14:00.980028 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6550 08:14:00.980647 == TX Byte 1 ==
6551 08:14:00.983245 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6552 08:14:00.990204 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6553 08:14:00.990625
6554 08:14:00.990958 [DATLAT]
6555 08:14:00.991268 Freq=400, CH0 RK1
6556 08:14:00.991567
6557 08:14:00.993031 DATLAT Default: 0xe
6558 08:14:00.993506 0, 0xFFFF, sum = 0
6559 08:14:00.996131 1, 0xFFFF, sum = 0
6560 08:14:00.999472 2, 0xFFFF, sum = 0
6561 08:14:00.999919 3, 0xFFFF, sum = 0
6562 08:14:01.003033 4, 0xFFFF, sum = 0
6563 08:14:01.003464 5, 0xFFFF, sum = 0
6564 08:14:01.006930 6, 0xFFFF, sum = 0
6565 08:14:01.007519 7, 0xFFFF, sum = 0
6566 08:14:01.009813 8, 0xFFFF, sum = 0
6567 08:14:01.010420 9, 0xFFFF, sum = 0
6568 08:14:01.013519 10, 0xFFFF, sum = 0
6569 08:14:01.014091 11, 0xFFFF, sum = 0
6570 08:14:01.016558 12, 0xFFFF, sum = 0
6571 08:14:01.017135 13, 0x0, sum = 1
6572 08:14:01.020101 14, 0x0, sum = 2
6573 08:14:01.020578 15, 0x0, sum = 3
6574 08:14:01.022962 16, 0x0, sum = 4
6575 08:14:01.023543 best_step = 14
6576 08:14:01.023916
6577 08:14:01.024263 ==
6578 08:14:01.026205 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 08:14:01.029737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 08:14:01.032986 ==
6581 08:14:01.033500 RX Vref Scan: 0
6582 08:14:01.033879
6583 08:14:01.036147 RX Vref 0 -> 0, step: 1
6584 08:14:01.036682
6585 08:14:01.039577 RX Delay -359 -> 252, step: 8
6586 08:14:01.046096 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6587 08:14:01.049768 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6588 08:14:01.052280 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6589 08:14:01.056044 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6590 08:14:01.062672 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6591 08:14:01.065563 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6592 08:14:01.069000 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6593 08:14:01.072448 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6594 08:14:01.079125 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6595 08:14:01.082093 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6596 08:14:01.085368 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6597 08:14:01.088764 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6598 08:14:01.094987 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6599 08:14:01.098643 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6600 08:14:01.101917 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6601 08:14:01.108369 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6602 08:14:01.109029 ==
6603 08:14:01.111422 Dram Type= 6, Freq= 0, CH_0, rank 1
6604 08:14:01.114797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 08:14:01.115206 ==
6606 08:14:01.115569 DQS Delay:
6607 08:14:01.117868 DQS0 = 44, DQS1 = 60
6608 08:14:01.118248 DQM Delay:
6609 08:14:01.121430 DQM0 = 7, DQM1 = 14
6610 08:14:01.121675 DQ Delay:
6611 08:14:01.124377 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6612 08:14:01.127834 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6613 08:14:01.130806 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6614 08:14:01.134214 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6615 08:14:01.134350
6616 08:14:01.134457
6617 08:14:01.140681 [DQSOSCAuto] RK1, (LSB)MR18= 0xa734, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
6618 08:14:01.144000 CH0 RK1: MR19=C0C, MR18=A734
6619 08:14:01.150558 CH0_RK1: MR19=0xC0C, MR18=0xA734, DQSOSC=389, MR23=63, INC=390, DEC=260
6620 08:14:01.154035 [RxdqsGatingPostProcess] freq 400
6621 08:14:01.160480 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6622 08:14:01.163836 best DQS0 dly(2T, 0.5T) = (0, 10)
6623 08:14:01.167363 best DQS1 dly(2T, 0.5T) = (0, 10)
6624 08:14:01.170137 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6625 08:14:01.173609 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6626 08:14:01.173721 best DQS0 dly(2T, 0.5T) = (0, 10)
6627 08:14:01.176907 best DQS1 dly(2T, 0.5T) = (0, 10)
6628 08:14:01.180156 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6629 08:14:01.183547 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6630 08:14:01.186556 Pre-setting of DQS Precalculation
6631 08:14:01.193129 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6632 08:14:01.193237 ==
6633 08:14:01.196555 Dram Type= 6, Freq= 0, CH_1, rank 0
6634 08:14:01.199961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 08:14:01.200046 ==
6636 08:14:01.206854 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6637 08:14:01.212749 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6638 08:14:01.216703 [CA 0] Center 36 (8~64) winsize 57
6639 08:14:01.219800 [CA 1] Center 36 (8~64) winsize 57
6640 08:14:01.223129 [CA 2] Center 36 (8~64) winsize 57
6641 08:14:01.223286 [CA 3] Center 36 (8~64) winsize 57
6642 08:14:01.226714 [CA 4] Center 36 (8~64) winsize 57
6643 08:14:01.229688 [CA 5] Center 36 (8~64) winsize 57
6644 08:14:01.229815
6645 08:14:01.236160 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6646 08:14:01.236308
6647 08:14:01.239221 [CATrainingPosCal] consider 1 rank data
6648 08:14:01.242629 u2DelayCellTimex100 = 270/100 ps
6649 08:14:01.246180 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 08:14:01.249029 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 08:14:01.252411 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 08:14:01.255667 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 08:14:01.259346 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 08:14:01.262467 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 08:14:01.262646
6656 08:14:01.265743 CA PerBit enable=1, Macro0, CA PI delay=36
6657 08:14:01.265910
6658 08:14:01.268694 [CBTSetCACLKResult] CA Dly = 36
6659 08:14:01.272369 CS Dly: 1 (0~32)
6660 08:14:01.272567 ==
6661 08:14:01.275926 Dram Type= 6, Freq= 0, CH_1, rank 1
6662 08:14:01.278813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 08:14:01.279046 ==
6664 08:14:01.285584 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6665 08:14:01.292277 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6666 08:14:01.295496 [CA 0] Center 36 (8~64) winsize 57
6667 08:14:01.298567 [CA 1] Center 36 (8~64) winsize 57
6668 08:14:01.298962 [CA 2] Center 36 (8~64) winsize 57
6669 08:14:01.301990 [CA 3] Center 36 (8~64) winsize 57
6670 08:14:01.305716 [CA 4] Center 36 (8~64) winsize 57
6671 08:14:01.309017 [CA 5] Center 36 (8~64) winsize 57
6672 08:14:01.309608
6673 08:14:01.312053 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6674 08:14:01.315856
6675 08:14:01.318424 [CATrainingPosCal] consider 2 rank data
6676 08:14:01.321819 u2DelayCellTimex100 = 270/100 ps
6677 08:14:01.325150 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 08:14:01.328258 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 08:14:01.332070 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 08:14:01.334868 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 08:14:01.338309 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 08:14:01.341635 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 08:14:01.342103
6684 08:14:01.344707 CA PerBit enable=1, Macro0, CA PI delay=36
6685 08:14:01.345267
6686 08:14:01.348465 [CBTSetCACLKResult] CA Dly = 36
6687 08:14:01.351272 CS Dly: 1 (0~32)
6688 08:14:01.351828
6689 08:14:01.354950 ----->DramcWriteLeveling(PI) begin...
6690 08:14:01.355691 ==
6691 08:14:01.357665 Dram Type= 6, Freq= 0, CH_1, rank 0
6692 08:14:01.361462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 08:14:01.362019 ==
6694 08:14:01.364340 Write leveling (Byte 0): 40 => 8
6695 08:14:01.367511 Write leveling (Byte 1): 40 => 8
6696 08:14:01.371453 DramcWriteLeveling(PI) end<-----
6697 08:14:01.372013
6698 08:14:01.372385 ==
6699 08:14:01.374498 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 08:14:01.377681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 08:14:01.378234 ==
6702 08:14:01.380659 [Gating] SW mode calibration
6703 08:14:01.387682 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6704 08:14:01.393905 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6705 08:14:01.397312 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6706 08:14:01.403987 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6707 08:14:01.408016 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6708 08:14:01.410920 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6709 08:14:01.417062 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6710 08:14:01.420256 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6711 08:14:01.424121 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6712 08:14:01.430262 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 08:14:01.433807 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6714 08:14:01.437141 Total UI for P1: 0, mck2ui 16
6715 08:14:01.440247 best dqsien dly found for B0: ( 0, 14, 24)
6716 08:14:01.443788 Total UI for P1: 0, mck2ui 16
6717 08:14:01.446807 best dqsien dly found for B1: ( 0, 14, 24)
6718 08:14:01.449935 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6719 08:14:01.453582 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6720 08:14:01.454146
6721 08:14:01.456332 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6722 08:14:01.460458 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6723 08:14:01.463450 [Gating] SW calibration Done
6724 08:14:01.464004 ==
6725 08:14:01.466410 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 08:14:01.472867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 08:14:01.473367 ==
6728 08:14:01.473806 RX Vref Scan: 0
6729 08:14:01.474279
6730 08:14:01.476423 RX Vref 0 -> 0, step: 1
6731 08:14:01.476975
6732 08:14:01.479936 RX Delay -410 -> 252, step: 16
6733 08:14:01.482804 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6734 08:14:01.485971 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6735 08:14:01.492649 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6736 08:14:01.495833 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6737 08:14:01.499480 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6738 08:14:01.502378 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6739 08:14:01.509509 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6740 08:14:01.512644 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6741 08:14:01.516169 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6742 08:14:01.518966 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6743 08:14:01.525904 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6744 08:14:01.528884 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6745 08:14:01.532493 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6746 08:14:01.538833 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6747 08:14:01.542042 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6748 08:14:01.545497 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6749 08:14:01.546048 ==
6750 08:14:01.548608 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 08:14:01.552181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 08:14:01.555105 ==
6753 08:14:01.555598 DQS Delay:
6754 08:14:01.555967 DQS0 = 43, DQS1 = 51
6755 08:14:01.558820 DQM Delay:
6756 08:14:01.559374 DQM0 = 13, DQM1 = 14
6757 08:14:01.561528 DQ Delay:
6758 08:14:01.565301 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6759 08:14:01.565883 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6760 08:14:01.568308 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6761 08:14:01.571741 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6762 08:14:01.572312
6763 08:14:01.572679
6764 08:14:01.574977 ==
6765 08:14:01.578272 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 08:14:01.581058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 08:14:01.581571 ==
6768 08:14:01.581947
6769 08:14:01.582335
6770 08:14:01.584753 TX Vref Scan disable
6771 08:14:01.585216 == TX Byte 0 ==
6772 08:14:01.587551 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 08:14:01.594555 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 08:14:01.595022 == TX Byte 1 ==
6775 08:14:01.597290 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 08:14:01.604248 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 08:14:01.604940 ==
6778 08:14:01.607537 Dram Type= 6, Freq= 0, CH_1, rank 0
6779 08:14:01.610411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6780 08:14:01.610790 ==
6781 08:14:01.611108
6782 08:14:01.611399
6783 08:14:01.613761 TX Vref Scan disable
6784 08:14:01.614078 == TX Byte 0 ==
6785 08:14:01.620338 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6786 08:14:01.623791 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6787 08:14:01.623989 == TX Byte 1 ==
6788 08:14:01.630214 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6789 08:14:01.633095 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6790 08:14:01.633257
6791 08:14:01.633397 [DATLAT]
6792 08:14:01.636750 Freq=400, CH1 RK0
6793 08:14:01.636864
6794 08:14:01.636953 DATLAT Default: 0xf
6795 08:14:01.639731 0, 0xFFFF, sum = 0
6796 08:14:01.639835 1, 0xFFFF, sum = 0
6797 08:14:01.643432 2, 0xFFFF, sum = 0
6798 08:14:01.643549 3, 0xFFFF, sum = 0
6799 08:14:01.646613 4, 0xFFFF, sum = 0
6800 08:14:01.646707 5, 0xFFFF, sum = 0
6801 08:14:01.650084 6, 0xFFFF, sum = 0
6802 08:14:01.650168 7, 0xFFFF, sum = 0
6803 08:14:01.653023 8, 0xFFFF, sum = 0
6804 08:14:01.653107 9, 0xFFFF, sum = 0
6805 08:14:01.656543 10, 0xFFFF, sum = 0
6806 08:14:01.659871 11, 0xFFFF, sum = 0
6807 08:14:01.659953 12, 0xFFFF, sum = 0
6808 08:14:01.663050 13, 0x0, sum = 1
6809 08:14:01.663133 14, 0x0, sum = 2
6810 08:14:01.666038 15, 0x0, sum = 3
6811 08:14:01.666120 16, 0x0, sum = 4
6812 08:14:01.666185 best_step = 14
6813 08:14:01.666244
6814 08:14:01.669679 ==
6815 08:14:01.672590 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 08:14:01.676093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 08:14:01.676174 ==
6818 08:14:01.676239 RX Vref Scan: 1
6819 08:14:01.676299
6820 08:14:01.679367 RX Vref 0 -> 0, step: 1
6821 08:14:01.679447
6822 08:14:01.682721 RX Delay -343 -> 252, step: 8
6823 08:14:01.682803
6824 08:14:01.686280 Set Vref, RX VrefLevel [Byte0]: 51
6825 08:14:01.689295 [Byte1]: 51
6826 08:14:01.692712
6827 08:14:01.692794 Final RX Vref Byte 0 = 51 to rank0
6828 08:14:01.696393 Final RX Vref Byte 1 = 51 to rank0
6829 08:14:01.699657 Final RX Vref Byte 0 = 51 to rank1
6830 08:14:01.703246 Final RX Vref Byte 1 = 51 to rank1==
6831 08:14:01.706262 Dram Type= 6, Freq= 0, CH_1, rank 0
6832 08:14:01.713655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 08:14:01.713812 ==
6834 08:14:01.713887 DQS Delay:
6835 08:14:01.716671 DQS0 = 44, DQS1 = 52
6836 08:14:01.716829 DQM Delay:
6837 08:14:01.716904 DQM0 = 8, DQM1 = 9
6838 08:14:01.719503 DQ Delay:
6839 08:14:01.722963 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6840 08:14:01.723046 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6841 08:14:01.726351 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6842 08:14:01.729722 DQ12 =20, DQ13 =12, DQ14 =16, DQ15 =16
6843 08:14:01.729890
6844 08:14:01.733157
6845 08:14:01.739121 [DQSOSCAuto] RK0, (LSB)MR18= 0x885f, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 392 ps
6846 08:14:01.742695 CH1 RK0: MR19=C0C, MR18=885F
6847 08:14:01.749520 CH1_RK0: MR19=0xC0C, MR18=0x885F, DQSOSC=392, MR23=63, INC=384, DEC=256
6848 08:14:01.749723 ==
6849 08:14:01.752212 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 08:14:01.756198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 08:14:01.756581 ==
6852 08:14:01.759459 [Gating] SW mode calibration
6853 08:14:01.765842 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6854 08:14:01.771897 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6855 08:14:01.775887 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6856 08:14:01.778747 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6857 08:14:01.785259 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6858 08:14:01.788903 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6859 08:14:01.792173 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6860 08:14:01.798855 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6861 08:14:01.802056 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6862 08:14:01.805296 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 08:14:01.811720 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6864 08:14:01.815639 Total UI for P1: 0, mck2ui 16
6865 08:14:01.818153 best dqsien dly found for B0: ( 0, 14, 24)
6866 08:14:01.821883 Total UI for P1: 0, mck2ui 16
6867 08:14:01.824741 best dqsien dly found for B1: ( 0, 14, 24)
6868 08:14:01.827895 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6869 08:14:01.831308 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6870 08:14:01.831731
6871 08:14:01.834709 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6872 08:14:01.838130 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6873 08:14:01.841188 [Gating] SW calibration Done
6874 08:14:01.841775 ==
6875 08:14:01.844746 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 08:14:01.847776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 08:14:01.848503 ==
6878 08:14:01.851287 RX Vref Scan: 0
6879 08:14:01.852109
6880 08:14:01.854329 RX Vref 0 -> 0, step: 1
6881 08:14:01.854750
6882 08:14:01.855079 RX Delay -410 -> 252, step: 16
6883 08:14:01.861617 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6884 08:14:01.864373 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6885 08:14:01.867942 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6886 08:14:01.871685 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6887 08:14:01.877998 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6888 08:14:01.880933 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6889 08:14:01.884199 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6890 08:14:01.890725 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6891 08:14:01.893973 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6892 08:14:01.897177 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6893 08:14:01.900474 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6894 08:14:01.907149 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6895 08:14:01.910532 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6896 08:14:01.913684 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6897 08:14:01.917006 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6898 08:14:01.923679 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6899 08:14:01.923870 ==
6900 08:14:01.926917 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 08:14:01.930059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 08:14:01.930212 ==
6903 08:14:01.930333 DQS Delay:
6904 08:14:01.933552 DQS0 = 51, DQS1 = 51
6905 08:14:01.933684 DQM Delay:
6906 08:14:01.936919 DQM0 = 19, DQM1 = 13
6907 08:14:01.937049 DQ Delay:
6908 08:14:01.939772 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6909 08:14:01.943198 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6910 08:14:01.946488 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6911 08:14:01.949615 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6912 08:14:01.949706
6913 08:14:01.949778
6914 08:14:01.949847 ==
6915 08:14:01.953234 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 08:14:01.959613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 08:14:01.959695 ==
6918 08:14:01.959760
6919 08:14:01.959820
6920 08:14:01.959878 TX Vref Scan disable
6921 08:14:01.962821 == TX Byte 0 ==
6922 08:14:01.966429 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6923 08:14:01.969458 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6924 08:14:01.973095 == TX Byte 1 ==
6925 08:14:01.976170 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6926 08:14:01.979081 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6927 08:14:01.979180 ==
6928 08:14:01.982599 Dram Type= 6, Freq= 0, CH_1, rank 1
6929 08:14:01.989222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6930 08:14:01.989304 ==
6931 08:14:01.989410
6932 08:14:01.989471
6933 08:14:01.989529 TX Vref Scan disable
6934 08:14:01.992319 == TX Byte 0 ==
6935 08:14:01.995606 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6936 08:14:01.999315 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6937 08:14:02.002451 == TX Byte 1 ==
6938 08:14:02.005749 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6939 08:14:02.009000 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6940 08:14:02.011910
6941 08:14:02.011992 [DATLAT]
6942 08:14:02.012058 Freq=400, CH1 RK1
6943 08:14:02.012119
6944 08:14:02.015252 DATLAT Default: 0xe
6945 08:14:02.015334 0, 0xFFFF, sum = 0
6946 08:14:02.018986 1, 0xFFFF, sum = 0
6947 08:14:02.019147 2, 0xFFFF, sum = 0
6948 08:14:02.022308 3, 0xFFFF, sum = 0
6949 08:14:02.022438 4, 0xFFFF, sum = 0
6950 08:14:02.025469 5, 0xFFFF, sum = 0
6951 08:14:02.028980 6, 0xFFFF, sum = 0
6952 08:14:02.029146 7, 0xFFFF, sum = 0
6953 08:14:02.031889 8, 0xFFFF, sum = 0
6954 08:14:02.032053 9, 0xFFFF, sum = 0
6955 08:14:02.035609 10, 0xFFFF, sum = 0
6956 08:14:02.035778 11, 0xFFFF, sum = 0
6957 08:14:02.038920 12, 0xFFFF, sum = 0
6958 08:14:02.039101 13, 0x0, sum = 1
6959 08:14:02.042007 14, 0x0, sum = 2
6960 08:14:02.042152 15, 0x0, sum = 3
6961 08:14:02.045070 16, 0x0, sum = 4
6962 08:14:02.045215 best_step = 14
6963 08:14:02.045313
6964 08:14:02.045417 ==
6965 08:14:02.048749 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 08:14:02.052344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 08:14:02.055078 ==
6968 08:14:02.055292 RX Vref Scan: 0
6969 08:14:02.055410
6970 08:14:02.058215 RX Vref 0 -> 0, step: 1
6971 08:14:02.058431
6972 08:14:02.061723 RX Delay -343 -> 252, step: 8
6973 08:14:02.068070 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
6974 08:14:02.071707 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6975 08:14:02.074747 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
6976 08:14:02.078403 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6977 08:14:02.085082 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6978 08:14:02.088177 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
6979 08:14:02.091775 iDelay=225, Bit 6, Center -20 (-263 ~ 224) 488
6980 08:14:02.094926 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6981 08:14:02.101561 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6982 08:14:02.105217 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6983 08:14:02.108281 iDelay=225, Bit 10, Center -44 (-287 ~ 200) 488
6984 08:14:02.111681 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
6985 08:14:02.118077 iDelay=225, Bit 12, Center -32 (-279 ~ 216) 496
6986 08:14:02.121226 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6987 08:14:02.124633 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6988 08:14:02.131092 iDelay=225, Bit 15, Center -36 (-279 ~ 208) 488
6989 08:14:02.131559 ==
6990 08:14:02.133858 Dram Type= 6, Freq= 0, CH_1, rank 1
6991 08:14:02.137758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6992 08:14:02.138327 ==
6993 08:14:02.138705 DQS Delay:
6994 08:14:02.140720 DQS0 = 44, DQS1 = 56
6995 08:14:02.141182 DQM Delay:
6996 08:14:02.144190 DQM0 = 9, DQM1 = 11
6997 08:14:02.144820 DQ Delay:
6998 08:14:02.147650 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6999 08:14:02.150758 DQ4 =4, DQ5 =16, DQ6 =24, DQ7 =4
7000 08:14:02.153955 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7001 08:14:02.157263 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =20
7002 08:14:02.157858
7003 08:14:02.158225
7004 08:14:02.164112 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b4a, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
7005 08:14:02.167180 CH1 RK1: MR19=C0C, MR18=5B4A
7006 08:14:02.173835 CH1_RK1: MR19=0xC0C, MR18=0x5B4A, DQSOSC=398, MR23=63, INC=372, DEC=248
7007 08:14:02.177129 [RxdqsGatingPostProcess] freq 400
7008 08:14:02.184101 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7009 08:14:02.186910 best DQS0 dly(2T, 0.5T) = (0, 10)
7010 08:14:02.190227 best DQS1 dly(2T, 0.5T) = (0, 10)
7011 08:14:02.193960 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7012 08:14:02.196729 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7013 08:14:02.197285 best DQS0 dly(2T, 0.5T) = (0, 10)
7014 08:14:02.200505 best DQS1 dly(2T, 0.5T) = (0, 10)
7015 08:14:02.203217 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7016 08:14:02.206700 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7017 08:14:02.210225 Pre-setting of DQS Precalculation
7018 08:14:02.216476 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7019 08:14:02.222597 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7020 08:14:02.229658 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7021 08:14:02.230222
7022 08:14:02.230660
7023 08:14:02.233029 [Calibration Summary] 800 Mbps
7024 08:14:02.233524 CH 0, Rank 0
7025 08:14:02.236514 SW Impedance : PASS
7026 08:14:02.239151 DUTY Scan : NO K
7027 08:14:02.239618 ZQ Calibration : PASS
7028 08:14:02.242683 Jitter Meter : NO K
7029 08:14:02.245659 CBT Training : PASS
7030 08:14:02.246126 Write leveling : PASS
7031 08:14:02.249813 RX DQS gating : PASS
7032 08:14:02.252681 RX DQ/DQS(RDDQC) : PASS
7033 08:14:02.253241 TX DQ/DQS : PASS
7034 08:14:02.256427 RX DATLAT : PASS
7035 08:14:02.259246 RX DQ/DQS(Engine): PASS
7036 08:14:02.259805 TX OE : NO K
7037 08:14:02.262347 All Pass.
7038 08:14:02.263034
7039 08:14:02.263417 CH 0, Rank 1
7040 08:14:02.265509 SW Impedance : PASS
7041 08:14:02.265975 DUTY Scan : NO K
7042 08:14:02.269280 ZQ Calibration : PASS
7043 08:14:02.272261 Jitter Meter : NO K
7044 08:14:02.272819 CBT Training : PASS
7045 08:14:02.275768 Write leveling : NO K
7046 08:14:02.278776 RX DQS gating : PASS
7047 08:14:02.279341 RX DQ/DQS(RDDQC) : PASS
7048 08:14:02.282165 TX DQ/DQS : PASS
7049 08:14:02.285184 RX DATLAT : PASS
7050 08:14:02.285684 RX DQ/DQS(Engine): PASS
7051 08:14:02.288938 TX OE : NO K
7052 08:14:02.289535 All Pass.
7053 08:14:02.289907
7054 08:14:02.292430 CH 1, Rank 0
7055 08:14:02.293065 SW Impedance : PASS
7056 08:14:02.295007 DUTY Scan : NO K
7057 08:14:02.298737 ZQ Calibration : PASS
7058 08:14:02.299340 Jitter Meter : NO K
7059 08:14:02.301467 CBT Training : PASS
7060 08:14:02.305094 Write leveling : PASS
7061 08:14:02.305715 RX DQS gating : PASS
7062 08:14:02.308085 RX DQ/DQS(RDDQC) : PASS
7063 08:14:02.311770 TX DQ/DQS : PASS
7064 08:14:02.312317 RX DATLAT : PASS
7065 08:14:02.314883 RX DQ/DQS(Engine): PASS
7066 08:14:02.315347 TX OE : NO K
7067 08:14:02.318097 All Pass.
7068 08:14:02.318574
7069 08:14:02.318902 CH 1, Rank 1
7070 08:14:02.321498 SW Impedance : PASS
7071 08:14:02.321918 DUTY Scan : NO K
7072 08:14:02.324429 ZQ Calibration : PASS
7073 08:14:02.328167 Jitter Meter : NO K
7074 08:14:02.328468 CBT Training : PASS
7075 08:14:02.331617 Write leveling : NO K
7076 08:14:02.334905 RX DQS gating : PASS
7077 08:14:02.335304 RX DQ/DQS(RDDQC) : PASS
7078 08:14:02.338153 TX DQ/DQS : PASS
7079 08:14:02.341140 RX DATLAT : PASS
7080 08:14:02.341465 RX DQ/DQS(Engine): PASS
7081 08:14:02.344701 TX OE : NO K
7082 08:14:02.345134 All Pass.
7083 08:14:02.345437
7084 08:14:02.347910 DramC Write-DBI off
7085 08:14:02.350752 PER_BANK_REFRESH: Hybrid Mode
7086 08:14:02.351068 TX_TRACKING: ON
7087 08:14:02.361101 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7088 08:14:02.364694 [FAST_K] Save calibration result to emmc
7089 08:14:02.368010 dramc_set_vcore_voltage set vcore to 725000
7090 08:14:02.370612 Read voltage for 1600, 0
7091 08:14:02.371187 Vio18 = 0
7092 08:14:02.374013 Vcore = 725000
7093 08:14:02.374475 Vdram = 0
7094 08:14:02.374840 Vddq = 0
7095 08:14:02.375178 Vmddr = 0
7096 08:14:02.380685 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7097 08:14:02.387281 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7098 08:14:02.387749 MEM_TYPE=3, freq_sel=13
7099 08:14:02.390900 sv_algorithm_assistance_LP4_3733
7100 08:14:02.393452 ============ PULL DRAM RESETB DOWN ============
7101 08:14:02.400047 ========== PULL DRAM RESETB DOWN end =========
7102 08:14:02.403452 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7103 08:14:02.407166 ===================================
7104 08:14:02.410606 LPDDR4 DRAM CONFIGURATION
7105 08:14:02.413440 ===================================
7106 08:14:02.414011 EX_ROW_EN[0] = 0x0
7107 08:14:02.416846 EX_ROW_EN[1] = 0x0
7108 08:14:02.419832 LP4Y_EN = 0x0
7109 08:14:02.420398 WORK_FSP = 0x1
7110 08:14:02.423126 WL = 0x5
7111 08:14:02.423593 RL = 0x5
7112 08:14:02.426250 BL = 0x2
7113 08:14:02.426840 RPST = 0x0
7114 08:14:02.429773 RD_PRE = 0x0
7115 08:14:02.430346 WR_PRE = 0x1
7116 08:14:02.432711 WR_PST = 0x1
7117 08:14:02.433243 DBI_WR = 0x0
7118 08:14:02.436662 DBI_RD = 0x0
7119 08:14:02.437127 OTF = 0x1
7120 08:14:02.439436 ===================================
7121 08:14:02.443072 ===================================
7122 08:14:02.446274 ANA top config
7123 08:14:02.449396 ===================================
7124 08:14:02.452712 DLL_ASYNC_EN = 0
7125 08:14:02.453167 ALL_SLAVE_EN = 0
7126 08:14:02.455771 NEW_RANK_MODE = 1
7127 08:14:02.458831 DLL_IDLE_MODE = 1
7128 08:14:02.462377 LP45_APHY_COMB_EN = 1
7129 08:14:02.462744 TX_ODT_DIS = 0
7130 08:14:02.465219 NEW_8X_MODE = 1
7131 08:14:02.468965 ===================================
7132 08:14:02.472052 ===================================
7133 08:14:02.475501 data_rate = 3200
7134 08:14:02.479127 CKR = 1
7135 08:14:02.481887 DQ_P2S_RATIO = 8
7136 08:14:02.485211 ===================================
7137 08:14:02.488782 CA_P2S_RATIO = 8
7138 08:14:02.488874 DQ_CA_OPEN = 0
7139 08:14:02.491885 DQ_SEMI_OPEN = 0
7140 08:14:02.495057 CA_SEMI_OPEN = 0
7141 08:14:02.498607 CA_FULL_RATE = 0
7142 08:14:02.501845 DQ_CKDIV4_EN = 0
7143 08:14:02.505093 CA_CKDIV4_EN = 0
7144 08:14:02.508299 CA_PREDIV_EN = 0
7145 08:14:02.508384 PH8_DLY = 12
7146 08:14:02.511706 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7147 08:14:02.514535 DQ_AAMCK_DIV = 4
7148 08:14:02.518008 CA_AAMCK_DIV = 4
7149 08:14:02.521469 CA_ADMCK_DIV = 4
7150 08:14:02.524456 DQ_TRACK_CA_EN = 0
7151 08:14:02.527960 CA_PICK = 1600
7152 08:14:02.528045 CA_MCKIO = 1600
7153 08:14:02.531541 MCKIO_SEMI = 0
7154 08:14:02.534658 PLL_FREQ = 3068
7155 08:14:02.537946 DQ_UI_PI_RATIO = 32
7156 08:14:02.541225 CA_UI_PI_RATIO = 0
7157 08:14:02.544752 ===================================
7158 08:14:02.547931 ===================================
7159 08:14:02.551371 memory_type:LPDDR4
7160 08:14:02.551453 GP_NUM : 10
7161 08:14:02.554397 SRAM_EN : 1
7162 08:14:02.554480 MD32_EN : 0
7163 08:14:02.557777 ===================================
7164 08:14:02.561433 [ANA_INIT] >>>>>>>>>>>>>>
7165 08:14:02.564713 <<<<<< [CONFIGURE PHASE]: ANA_TX
7166 08:14:02.568233 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7167 08:14:02.571376 ===================================
7168 08:14:02.574476 data_rate = 3200,PCW = 0X7600
7169 08:14:02.578122 ===================================
7170 08:14:02.581273 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7171 08:14:02.587962 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7172 08:14:02.591583 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7173 08:14:02.598037 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7174 08:14:02.601144 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7175 08:14:02.604019 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7176 08:14:02.604506 [ANA_INIT] flow start
7177 08:14:02.607824 [ANA_INIT] PLL >>>>>>>>
7178 08:14:02.610899 [ANA_INIT] PLL <<<<<<<<
7179 08:14:02.614273 [ANA_INIT] MIDPI >>>>>>>>
7180 08:14:02.614838 [ANA_INIT] MIDPI <<<<<<<<
7181 08:14:02.617571 [ANA_INIT] DLL >>>>>>>>
7182 08:14:02.620473 [ANA_INIT] DLL <<<<<<<<
7183 08:14:02.621029 [ANA_INIT] flow end
7184 08:14:02.623873 ============ LP4 DIFF to SE enter ============
7185 08:14:02.630327 ============ LP4 DIFF to SE exit ============
7186 08:14:02.630800 [ANA_INIT] <<<<<<<<<<<<<
7187 08:14:02.633711 [Flow] Enable top DCM control >>>>>
7188 08:14:02.636837 [Flow] Enable top DCM control <<<<<
7189 08:14:02.640597 Enable DLL master slave shuffle
7190 08:14:02.647032 ==============================================================
7191 08:14:02.650269 Gating Mode config
7192 08:14:02.653938 ==============================================================
7193 08:14:02.656854 Config description:
7194 08:14:02.666759 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7195 08:14:02.673097 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7196 08:14:02.676597 SELPH_MODE 0: By rank 1: By Phase
7197 08:14:02.683481 ==============================================================
7198 08:14:02.686239 GAT_TRACK_EN = 1
7199 08:14:02.690003 RX_GATING_MODE = 2
7200 08:14:02.693540 RX_GATING_TRACK_MODE = 2
7201 08:14:02.696310 SELPH_MODE = 1
7202 08:14:02.696780 PICG_EARLY_EN = 1
7203 08:14:02.699734 VALID_LAT_VALUE = 1
7204 08:14:02.705556 ==============================================================
7205 08:14:02.709231 Enter into Gating configuration >>>>
7206 08:14:02.712607 Exit from Gating configuration <<<<
7207 08:14:02.715913 Enter into DVFS_PRE_config >>>>>
7208 08:14:02.725498 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7209 08:14:02.728917 Exit from DVFS_PRE_config <<<<<
7210 08:14:02.732059 Enter into PICG configuration >>>>
7211 08:14:02.735610 Exit from PICG configuration <<<<
7212 08:14:02.738518 [RX_INPUT] configuration >>>>>
7213 08:14:02.741788 [RX_INPUT] configuration <<<<<
7214 08:14:02.747953 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7215 08:14:02.751591 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7216 08:14:02.758191 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7217 08:14:02.764535 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7218 08:14:02.771242 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7219 08:14:02.777737 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7220 08:14:02.781142 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7221 08:14:02.784090 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7222 08:14:02.787921 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7223 08:14:02.794567 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7224 08:14:02.797786 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7225 08:14:02.800713 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7226 08:14:02.804605 ===================================
7227 08:14:02.807321 LPDDR4 DRAM CONFIGURATION
7228 08:14:02.811040 ===================================
7229 08:14:02.814326 EX_ROW_EN[0] = 0x0
7230 08:14:02.814656 EX_ROW_EN[1] = 0x0
7231 08:14:02.818138 LP4Y_EN = 0x0
7232 08:14:02.818559 WORK_FSP = 0x1
7233 08:14:02.820748 WL = 0x5
7234 08:14:02.821076 RL = 0x5
7235 08:14:02.824249 BL = 0x2
7236 08:14:02.824577 RPST = 0x0
7237 08:14:02.827380 RD_PRE = 0x0
7238 08:14:02.827792 WR_PRE = 0x1
7239 08:14:02.831196 WR_PST = 0x1
7240 08:14:02.831636 DBI_WR = 0x0
7241 08:14:02.834493 DBI_RD = 0x0
7242 08:14:02.834914 OTF = 0x1
7243 08:14:02.837277 ===================================
7244 08:14:02.844588 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7245 08:14:02.847772 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7246 08:14:02.851019 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7247 08:14:02.854168 ===================================
7248 08:14:02.857521 LPDDR4 DRAM CONFIGURATION
7249 08:14:02.861265 ===================================
7250 08:14:02.864244 EX_ROW_EN[0] = 0x10
7251 08:14:02.864801 EX_ROW_EN[1] = 0x0
7252 08:14:02.867942 LP4Y_EN = 0x0
7253 08:14:02.868505 WORK_FSP = 0x1
7254 08:14:02.870445 WL = 0x5
7255 08:14:02.870862 RL = 0x5
7256 08:14:02.874121 BL = 0x2
7257 08:14:02.874592 RPST = 0x0
7258 08:14:02.876995 RD_PRE = 0x0
7259 08:14:02.877522 WR_PRE = 0x1
7260 08:14:02.880497 WR_PST = 0x1
7261 08:14:02.880963 DBI_WR = 0x0
7262 08:14:02.884093 DBI_RD = 0x0
7263 08:14:02.887251 OTF = 0x1
7264 08:14:02.890205 ===================================
7265 08:14:02.894000 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7266 08:14:02.894564 ==
7267 08:14:02.897380 Dram Type= 6, Freq= 0, CH_0, rank 0
7268 08:14:02.903499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7269 08:14:02.903974 ==
7270 08:14:02.907050 [Duty_Offset_Calibration]
7271 08:14:02.907709 B0:1 B1:-1 CA:0
7272 08:14:02.908099
7273 08:14:02.910081 [DutyScan_Calibration_Flow] k_type=0
7274 08:14:02.920101
7275 08:14:02.920651 ==CLK 0==
7276 08:14:02.923063 Final CLK duty delay cell = 0
7277 08:14:02.926697 [0] MAX Duty = 5093%(X100), DQS PI = 20
7278 08:14:02.929453 [0] MIN Duty = 4907%(X100), DQS PI = 4
7279 08:14:02.933108 [0] AVG Duty = 5000%(X100)
7280 08:14:02.933644
7281 08:14:02.936291 CH0 CLK Duty spec in!! Max-Min= 186%
7282 08:14:02.939432 [DutyScan_Calibration_Flow] ====Done====
7283 08:14:02.940005
7284 08:14:02.942853 [DutyScan_Calibration_Flow] k_type=1
7285 08:14:02.958580
7286 08:14:02.959007 ==DQS 0 ==
7287 08:14:02.962171 Final DQS duty delay cell = -4
7288 08:14:02.965271 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7289 08:14:02.968660 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7290 08:14:02.971714 [-4] AVG Duty = 4922%(X100)
7291 08:14:02.972558
7292 08:14:02.973027 ==DQS 1 ==
7293 08:14:02.974927 Final DQS duty delay cell = 0
7294 08:14:02.978845 [0] MAX Duty = 5156%(X100), DQS PI = 2
7295 08:14:02.981895 [0] MIN Duty = 5031%(X100), DQS PI = 18
7296 08:14:02.984826 [0] AVG Duty = 5093%(X100)
7297 08:14:02.985446
7298 08:14:02.988158 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7299 08:14:02.988582
7300 08:14:02.991700 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7301 08:14:02.995197 [DutyScan_Calibration_Flow] ====Done====
7302 08:14:02.995619
7303 08:14:02.998338 [DutyScan_Calibration_Flow] k_type=3
7304 08:14:03.016222
7305 08:14:03.016620 ==DQM 0 ==
7306 08:14:03.019557 Final DQM duty delay cell = 0
7307 08:14:03.022720 [0] MAX Duty = 5124%(X100), DQS PI = 20
7308 08:14:03.026066 [0] MIN Duty = 4876%(X100), DQS PI = 8
7309 08:14:03.029629 [0] AVG Duty = 5000%(X100)
7310 08:14:03.029930
7311 08:14:03.030164 ==DQM 1 ==
7312 08:14:03.032651 Final DQM duty delay cell = 0
7313 08:14:03.036434 [0] MAX Duty = 5031%(X100), DQS PI = 54
7314 08:14:03.039205 [0] MIN Duty = 4782%(X100), DQS PI = 20
7315 08:14:03.042957 [0] AVG Duty = 4906%(X100)
7316 08:14:03.043257
7317 08:14:03.045806 CH0 DQM 0 Duty spec in!! Max-Min= 248%
7318 08:14:03.046128
7319 08:14:03.049281 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7320 08:14:03.052412 [DutyScan_Calibration_Flow] ====Done====
7321 08:14:03.052711
7322 08:14:03.056186 [DutyScan_Calibration_Flow] k_type=2
7323 08:14:03.072819
7324 08:14:03.073243 ==DQ 0 ==
7325 08:14:03.076073 Final DQ duty delay cell = -4
7326 08:14:03.079508 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7327 08:14:03.082819 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7328 08:14:03.085894 [-4] AVG Duty = 4953%(X100)
7329 08:14:03.086358
7330 08:14:03.086724 ==DQ 1 ==
7331 08:14:03.089396 Final DQ duty delay cell = 0
7332 08:14:03.092254 [0] MAX Duty = 5125%(X100), DQS PI = 4
7333 08:14:03.095595 [0] MIN Duty = 5000%(X100), DQS PI = 36
7334 08:14:03.098840 [0] AVG Duty = 5062%(X100)
7335 08:14:03.099266
7336 08:14:03.102084 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7337 08:14:03.102509
7338 08:14:03.105449 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7339 08:14:03.108708 [DutyScan_Calibration_Flow] ====Done====
7340 08:14:03.109167 ==
7341 08:14:03.111696 Dram Type= 6, Freq= 0, CH_1, rank 0
7342 08:14:03.115072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7343 08:14:03.115300 ==
7344 08:14:03.118650 [Duty_Offset_Calibration]
7345 08:14:03.118888 B0:-1 B1:1 CA:2
7346 08:14:03.121517
7347 08:14:03.121741 [DutyScan_Calibration_Flow] k_type=0
7348 08:14:03.132806
7349 08:14:03.132943 ==CLK 0==
7350 08:14:03.136264 Final CLK duty delay cell = 0
7351 08:14:03.139186 [0] MAX Duty = 5187%(X100), DQS PI = 22
7352 08:14:03.142803 [0] MIN Duty = 4969%(X100), DQS PI = 0
7353 08:14:03.145874 [0] AVG Duty = 5078%(X100)
7354 08:14:03.145968
7355 08:14:03.149420 CH1 CLK Duty spec in!! Max-Min= 218%
7356 08:14:03.152412 [DutyScan_Calibration_Flow] ====Done====
7357 08:14:03.152495
7358 08:14:03.155372 [DutyScan_Calibration_Flow] k_type=1
7359 08:14:03.172896
7360 08:14:03.173002 ==DQS 0 ==
7361 08:14:03.175782 Final DQS duty delay cell = 0
7362 08:14:03.179011 [0] MAX Duty = 5124%(X100), DQS PI = 18
7363 08:14:03.182523 [0] MIN Duty = 4938%(X100), DQS PI = 8
7364 08:14:03.185801 [0] AVG Duty = 5031%(X100)
7365 08:14:03.185882
7366 08:14:03.185946 ==DQS 1 ==
7367 08:14:03.188921 Final DQS duty delay cell = 0
7368 08:14:03.192544 [0] MAX Duty = 5093%(X100), DQS PI = 28
7369 08:14:03.195933 [0] MIN Duty = 4969%(X100), DQS PI = 54
7370 08:14:03.198953 [0] AVG Duty = 5031%(X100)
7371 08:14:03.199089
7372 08:14:03.202499 CH1 DQS 0 Duty spec in!! Max-Min= 186%
7373 08:14:03.202598
7374 08:14:03.205975 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7375 08:14:03.208620 [DutyScan_Calibration_Flow] ====Done====
7376 08:14:03.208701
7377 08:14:03.211893 [DutyScan_Calibration_Flow] k_type=3
7378 08:14:03.230024
7379 08:14:03.230190 ==DQM 0 ==
7380 08:14:03.232567 Final DQM duty delay cell = 0
7381 08:14:03.236158 [0] MAX Duty = 5218%(X100), DQS PI = 34
7382 08:14:03.239582 [0] MIN Duty = 5000%(X100), DQS PI = 10
7383 08:14:03.243109 [0] AVG Duty = 5109%(X100)
7384 08:14:03.243294
7385 08:14:03.243387 ==DQM 1 ==
7386 08:14:03.246116 Final DQM duty delay cell = 0
7387 08:14:03.249231 [0] MAX Duty = 5125%(X100), DQS PI = 0
7388 08:14:03.252755 [0] MIN Duty = 4969%(X100), DQS PI = 28
7389 08:14:03.255873 [0] AVG Duty = 5047%(X100)
7390 08:14:03.256112
7391 08:14:03.259269 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7392 08:14:03.259529
7393 08:14:03.262857 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7394 08:14:03.265804 [DutyScan_Calibration_Flow] ====Done====
7395 08:14:03.266095
7396 08:14:03.269419 [DutyScan_Calibration_Flow] k_type=2
7397 08:14:03.286889
7398 08:14:03.287464 ==DQ 0 ==
7399 08:14:03.289902 Final DQ duty delay cell = 0
7400 08:14:03.293238 [0] MAX Duty = 5187%(X100), DQS PI = 34
7401 08:14:03.296840 [0] MIN Duty = 4906%(X100), DQS PI = 8
7402 08:14:03.297453 [0] AVG Duty = 5046%(X100)
7403 08:14:03.299536
7404 08:14:03.300011 ==DQ 1 ==
7405 08:14:03.303277 Final DQ duty delay cell = 0
7406 08:14:03.306685 [0] MAX Duty = 5125%(X100), DQS PI = 8
7407 08:14:03.309714 [0] MIN Duty = 4969%(X100), DQS PI = 56
7408 08:14:03.310198 [0] AVG Duty = 5047%(X100)
7409 08:14:03.313090
7410 08:14:03.316387 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7411 08:14:03.316957
7412 08:14:03.319593 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7413 08:14:03.323062 [DutyScan_Calibration_Flow] ====Done====
7414 08:14:03.325931 nWR fixed to 30
7415 08:14:03.326416 [ModeRegInit_LP4] CH0 RK0
7416 08:14:03.329524 [ModeRegInit_LP4] CH0 RK1
7417 08:14:03.332589 [ModeRegInit_LP4] CH1 RK0
7418 08:14:03.335882 [ModeRegInit_LP4] CH1 RK1
7419 08:14:03.336360 match AC timing 5
7420 08:14:03.342841 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7421 08:14:03.345860 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7422 08:14:03.349227 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7423 08:14:03.355699 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7424 08:14:03.359450 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7425 08:14:03.360012 [MiockJmeterHQA]
7426 08:14:03.360388
7427 08:14:03.361970 [DramcMiockJmeter] u1RxGatingPI = 0
7428 08:14:03.365901 0 : 4366, 4139
7429 08:14:03.366468 4 : 4252, 4027
7430 08:14:03.369223 8 : 4258, 4030
7431 08:14:03.369867 12 : 4363, 4137
7432 08:14:03.372207 16 : 4252, 4027
7433 08:14:03.372783 20 : 4365, 4140
7434 08:14:03.373166 24 : 4253, 4027
7435 08:14:03.375755 28 : 4253, 4026
7436 08:14:03.376229 32 : 4253, 4027
7437 08:14:03.378962 36 : 4253, 4026
7438 08:14:03.379532 40 : 4363, 4137
7439 08:14:03.381982 44 : 4363, 4137
7440 08:14:03.382553 48 : 4363, 4137
7441 08:14:03.385595 52 : 4252, 4027
7442 08:14:03.386160 56 : 4255, 4029
7443 08:14:03.386548 60 : 4253, 4029
7444 08:14:03.388350 64 : 4361, 4138
7445 08:14:03.388824 68 : 4360, 4137
7446 08:14:03.391697 72 : 4360, 4138
7447 08:14:03.392234 76 : 4250, 4027
7448 08:14:03.394761 80 : 4253, 4029
7449 08:14:03.395242 84 : 4250, 4027
7450 08:14:03.398640 88 : 4250, 4024
7451 08:14:03.399207 92 : 4360, 690
7452 08:14:03.399587 96 : 4253, 0
7453 08:14:03.402065 100 : 4360, 0
7454 08:14:03.402543 104 : 4250, 0
7455 08:14:03.405179 108 : 4361, 0
7456 08:14:03.405729 112 : 4255, 0
7457 08:14:03.406119 116 : 4250, 0
7458 08:14:03.408511 120 : 4250, 0
7459 08:14:03.408990 124 : 4255, 0
7460 08:14:03.409428 128 : 4250, 0
7461 08:14:03.412206 132 : 4250, 0
7462 08:14:03.412772 136 : 4252, 0
7463 08:14:03.415110 140 : 4363, 0
7464 08:14:03.415585 144 : 4250, 0
7465 08:14:03.415969 148 : 4250, 0
7466 08:14:03.418098 152 : 4361, 0
7467 08:14:03.418578 156 : 4250, 0
7468 08:14:03.421727 160 : 4363, 0
7469 08:14:03.422203 164 : 4255, 0
7470 08:14:03.422583 168 : 4250, 0
7471 08:14:03.424637 172 : 4363, 0
7472 08:14:03.425115 176 : 4250, 0
7473 08:14:03.427981 180 : 4250, 0
7474 08:14:03.428455 184 : 4250, 0
7475 08:14:03.428839 188 : 4253, 0
7476 08:14:03.431333 192 : 4250, 0
7477 08:14:03.431809 196 : 4250, 0
7478 08:14:03.434848 200 : 4255, 0
7479 08:14:03.435327 204 : 4361, 0
7480 08:14:03.435708 208 : 4250, 0
7481 08:14:03.437893 212 : 4361, 0
7482 08:14:03.438325 216 : 4250, 0
7483 08:14:03.441553 220 : 4250, 0
7484 08:14:03.441986 224 : 4250, 80
7485 08:14:03.442329 228 : 4249, 3131
7486 08:14:03.444599 232 : 4250, 4026
7487 08:14:03.445029 236 : 4250, 4026
7488 08:14:03.448129 240 : 4360, 4137
7489 08:14:03.448672 244 : 4360, 4138
7490 08:14:03.451309 248 : 4250, 4027
7491 08:14:03.451767 252 : 4361, 4137
7492 08:14:03.454823 256 : 4250, 4027
7493 08:14:03.455344 260 : 4252, 4027
7494 08:14:03.458038 264 : 4250, 4027
7495 08:14:03.458472 268 : 4363, 4140
7496 08:14:03.461210 272 : 4250, 4027
7497 08:14:03.461783 276 : 4250, 4027
7498 08:14:03.462132 280 : 4361, 4137
7499 08:14:03.464675 284 : 4250, 4027
7500 08:14:03.465202 288 : 4250, 4027
7501 08:14:03.468310 292 : 4360, 4138
7502 08:14:03.468836 296 : 4360, 4138
7503 08:14:03.471174 300 : 4250, 4027
7504 08:14:03.471610 304 : 4250, 4026
7505 08:14:03.474885 308 : 4250, 4027
7506 08:14:03.475408 312 : 4250, 4027
7507 08:14:03.477851 316 : 4250, 4027
7508 08:14:03.478424 320 : 4363, 4140
7509 08:14:03.481269 324 : 4250, 4027
7510 08:14:03.481739 328 : 4250, 4027
7511 08:14:03.484301 332 : 4363, 4140
7512 08:14:03.484733 336 : 4250, 3824
7513 08:14:03.487822 340 : 4250, 2061
7514 08:14:03.488255
7515 08:14:03.488594 MIOCK jitter meter ch=0
7516 08:14:03.488914
7517 08:14:03.490794 1T = (340-92) = 248 dly cells
7518 08:14:03.497308 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7519 08:14:03.497793 ==
7520 08:14:03.500735 Dram Type= 6, Freq= 0, CH_0, rank 0
7521 08:14:03.504116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7522 08:14:03.504545 ==
7523 08:14:03.510524 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7524 08:14:03.513780 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7525 08:14:03.517019 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7526 08:14:03.523760 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7527 08:14:03.533656 [CA 0] Center 44 (14~74) winsize 61
7528 08:14:03.537034 [CA 1] Center 43 (13~74) winsize 62
7529 08:14:03.540037 [CA 2] Center 39 (10~69) winsize 60
7530 08:14:03.543064 [CA 3] Center 39 (9~69) winsize 61
7531 08:14:03.546799 [CA 4] Center 37 (8~66) winsize 59
7532 08:14:03.550379 [CA 5] Center 36 (7~66) winsize 60
7533 08:14:03.550770
7534 08:14:03.553251 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7535 08:14:03.553723
7536 08:14:03.559837 [CATrainingPosCal] consider 1 rank data
7537 08:14:03.560388 u2DelayCellTimex100 = 262/100 ps
7538 08:14:03.567309 CA0 delay=44 (14~74),Diff = 8 PI (29 cell)
7539 08:14:03.569768 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7540 08:14:03.573162 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7541 08:14:03.576921 CA3 delay=39 (9~69),Diff = 3 PI (11 cell)
7542 08:14:03.580277 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7543 08:14:03.583324 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7544 08:14:03.583882
7545 08:14:03.586716 CA PerBit enable=1, Macro0, CA PI delay=36
7546 08:14:03.587185
7547 08:14:03.589730 [CBTSetCACLKResult] CA Dly = 36
7548 08:14:03.593399 CS Dly: 11 (0~42)
7549 08:14:03.596809 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7550 08:14:03.599852 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7551 08:14:03.600409 ==
7552 08:14:03.602959 Dram Type= 6, Freq= 0, CH_0, rank 1
7553 08:14:03.609887 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7554 08:14:03.610358 ==
7555 08:14:03.612899 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7556 08:14:03.619140 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7557 08:14:03.622441 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7558 08:14:03.629075 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7559 08:14:03.637424 [CA 0] Center 43 (13~74) winsize 62
7560 08:14:03.640522 [CA 1] Center 44 (14~74) winsize 61
7561 08:14:03.643710 [CA 2] Center 38 (9~68) winsize 60
7562 08:14:03.647074 [CA 3] Center 38 (9~68) winsize 60
7563 08:14:03.649810 [CA 4] Center 36 (7~66) winsize 60
7564 08:14:03.653088 [CA 5] Center 36 (7~66) winsize 60
7565 08:14:03.653420
7566 08:14:03.656396 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7567 08:14:03.656590
7568 08:14:03.663181 [CATrainingPosCal] consider 2 rank data
7569 08:14:03.663343 u2DelayCellTimex100 = 262/100 ps
7570 08:14:03.669801 CA0 delay=44 (14~74),Diff = 8 PI (29 cell)
7571 08:14:03.672983 CA1 delay=44 (14~74),Diff = 8 PI (29 cell)
7572 08:14:03.676431 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7573 08:14:03.679722 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7574 08:14:03.682818 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7575 08:14:03.686079 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7576 08:14:03.686167
7577 08:14:03.689264 CA PerBit enable=1, Macro0, CA PI delay=36
7578 08:14:03.689392
7579 08:14:03.692878 [CBTSetCACLKResult] CA Dly = 36
7580 08:14:03.696013 CS Dly: 12 (0~44)
7581 08:14:03.699258 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7582 08:14:03.702718 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7583 08:14:03.702802
7584 08:14:03.705626 ----->DramcWriteLeveling(PI) begin...
7585 08:14:03.709277 ==
7586 08:14:03.712404 Dram Type= 6, Freq= 0, CH_0, rank 0
7587 08:14:03.715538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7588 08:14:03.715622 ==
7589 08:14:03.718986 Write leveling (Byte 0): 34 => 34
7590 08:14:03.721914 Write leveling (Byte 1): 25 => 25
7591 08:14:03.725321 DramcWriteLeveling(PI) end<-----
7592 08:14:03.725442
7593 08:14:03.725509 ==
7594 08:14:03.728608 Dram Type= 6, Freq= 0, CH_0, rank 0
7595 08:14:03.732161 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7596 08:14:03.732250 ==
7597 08:14:03.735681 [Gating] SW mode calibration
7598 08:14:03.742165 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7599 08:14:03.748523 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7600 08:14:03.751743 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 08:14:03.755107 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 08:14:03.761278 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 08:14:03.764948 1 4 12 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
7604 08:14:03.768470 1 4 16 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7605 08:14:03.774868 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7606 08:14:03.778404 1 4 24 | B1->B0 | 3130 3434 | 1 1 | (0 0) (1 1)
7607 08:14:03.781105 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7608 08:14:03.787435 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7609 08:14:03.791011 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7610 08:14:03.794296 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 08:14:03.800918 1 5 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
7612 08:14:03.803905 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7613 08:14:03.807203 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7614 08:14:03.813970 1 5 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
7615 08:14:03.817492 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 08:14:03.820317 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 08:14:03.827087 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 08:14:03.830374 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 08:14:03.833719 1 6 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7620 08:14:03.840437 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7621 08:14:03.843657 1 6 20 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7622 08:14:03.846823 1 6 24 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
7623 08:14:03.853896 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 08:14:03.856698 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 08:14:03.859968 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 08:14:03.866951 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 08:14:03.870147 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7628 08:14:03.873077 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7629 08:14:03.879634 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7630 08:14:03.883039 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7631 08:14:03.889670 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 08:14:03.892718 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 08:14:03.896280 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 08:14:03.903039 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 08:14:03.906246 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 08:14:03.909907 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 08:14:03.916129 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 08:14:03.919290 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 08:14:03.922638 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 08:14:03.929209 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 08:14:03.932602 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7642 08:14:03.935890 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7643 08:14:03.942216 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7644 08:14:03.945811 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7645 08:14:03.948754 Total UI for P1: 0, mck2ui 16
7646 08:14:03.952293 best dqsien dly found for B0: ( 1, 9, 8)
7647 08:14:03.955308 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7648 08:14:03.961797 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 08:14:03.961885 Total UI for P1: 0, mck2ui 16
7650 08:14:03.965175 best dqsien dly found for B1: ( 1, 9, 18)
7651 08:14:03.972022 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7652 08:14:03.975163 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7653 08:14:03.975248
7654 08:14:03.978466 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7655 08:14:03.981915 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7656 08:14:03.984792 [Gating] SW calibration Done
7657 08:14:03.984875 ==
7658 08:14:03.988395 Dram Type= 6, Freq= 0, CH_0, rank 0
7659 08:14:03.991310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7660 08:14:03.991393 ==
7661 08:14:03.994795 RX Vref Scan: 0
7662 08:14:03.994877
7663 08:14:03.994942 RX Vref 0 -> 0, step: 1
7664 08:14:03.995002
7665 08:14:03.998239 RX Delay 0 -> 252, step: 8
7666 08:14:04.001723 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7667 08:14:04.008016 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7668 08:14:04.011540 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7669 08:14:04.014189 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7670 08:14:04.018006 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7671 08:14:04.020853 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7672 08:14:04.027423 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7673 08:14:04.031039 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7674 08:14:04.034403 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7675 08:14:04.037359 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7676 08:14:04.044173 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7677 08:14:04.047734 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7678 08:14:04.050552 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7679 08:14:04.054218 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7680 08:14:04.057044 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7681 08:14:04.063958 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7682 08:14:04.064040 ==
7683 08:14:04.067051 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 08:14:04.070289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 08:14:04.070371 ==
7686 08:14:04.070436 DQS Delay:
7687 08:14:04.074013 DQS0 = 0, DQS1 = 0
7688 08:14:04.074099 DQM Delay:
7689 08:14:04.076837 DQM0 = 134, DQM1 = 126
7690 08:14:04.076997 DQ Delay:
7691 08:14:04.080340 DQ0 =131, DQ1 =139, DQ2 =131, DQ3 =131
7692 08:14:04.083840 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =147
7693 08:14:04.087545 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7694 08:14:04.093611 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7695 08:14:04.093785
7696 08:14:04.093877
7697 08:14:04.093958 ==
7698 08:14:04.097575 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 08:14:04.100086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 08:14:04.100245 ==
7701 08:14:04.100353
7702 08:14:04.100450
7703 08:14:04.103787 TX Vref Scan disable
7704 08:14:04.103999 == TX Byte 0 ==
7705 08:14:04.110288 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7706 08:14:04.113451 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7707 08:14:04.113683 == TX Byte 1 ==
7708 08:14:04.120304 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7709 08:14:04.123140 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7710 08:14:04.123392 ==
7711 08:14:04.126646 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 08:14:04.129493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 08:14:04.129912 ==
7714 08:14:04.144966
7715 08:14:04.148253 TX Vref early break, caculate TX vref
7716 08:14:04.151119 TX Vref=16, minBit 3, minWin=22, winSum=367
7717 08:14:04.154693 TX Vref=18, minBit 0, minWin=23, winSum=376
7718 08:14:04.157998 TX Vref=20, minBit 4, minWin=23, winSum=387
7719 08:14:04.161283 TX Vref=22, minBit 1, minWin=24, winSum=396
7720 08:14:04.164685 TX Vref=24, minBit 1, minWin=24, winSum=401
7721 08:14:04.171012 TX Vref=26, minBit 0, minWin=25, winSum=413
7722 08:14:04.174460 TX Vref=28, minBit 0, minWin=25, winSum=417
7723 08:14:04.177792 TX Vref=30, minBit 4, minWin=24, winSum=408
7724 08:14:04.181248 TX Vref=32, minBit 0, minWin=24, winSum=402
7725 08:14:04.184759 TX Vref=34, minBit 4, minWin=23, winSum=389
7726 08:14:04.190976 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
7727 08:14:04.191552
7728 08:14:04.194147 Final TX Range 0 Vref 28
7729 08:14:04.194631
7730 08:14:04.195111 ==
7731 08:14:04.197485 Dram Type= 6, Freq= 0, CH_0, rank 0
7732 08:14:04.200935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7733 08:14:04.201565 ==
7734 08:14:04.202058
7735 08:14:04.202509
7736 08:14:04.204044 TX Vref Scan disable
7737 08:14:04.211062 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7738 08:14:04.211668 == TX Byte 0 ==
7739 08:14:04.213891 u2DelayCellOfst[0]=14 cells (4 PI)
7740 08:14:04.217502 u2DelayCellOfst[1]=18 cells (5 PI)
7741 08:14:04.220763 u2DelayCellOfst[2]=14 cells (4 PI)
7742 08:14:04.223851 u2DelayCellOfst[3]=18 cells (5 PI)
7743 08:14:04.227526 u2DelayCellOfst[4]=11 cells (3 PI)
7744 08:14:04.230449 u2DelayCellOfst[5]=0 cells (0 PI)
7745 08:14:04.233902 u2DelayCellOfst[6]=18 cells (5 PI)
7746 08:14:04.237028 u2DelayCellOfst[7]=22 cells (6 PI)
7747 08:14:04.240118 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7748 08:14:04.243801 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7749 08:14:04.247423 == TX Byte 1 ==
7750 08:14:04.250546 u2DelayCellOfst[8]=0 cells (0 PI)
7751 08:14:04.253645 u2DelayCellOfst[9]=3 cells (1 PI)
7752 08:14:04.256676 u2DelayCellOfst[10]=7 cells (2 PI)
7753 08:14:04.257141 u2DelayCellOfst[11]=3 cells (1 PI)
7754 08:14:04.260349 u2DelayCellOfst[12]=14 cells (4 PI)
7755 08:14:04.263529 u2DelayCellOfst[13]=14 cells (4 PI)
7756 08:14:04.266461 u2DelayCellOfst[14]=14 cells (4 PI)
7757 08:14:04.269852 u2DelayCellOfst[15]=14 cells (4 PI)
7758 08:14:04.276367 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7759 08:14:04.279954 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7760 08:14:04.280393 DramC Write-DBI on
7761 08:14:04.283387 ==
7762 08:14:04.286229 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 08:14:04.290026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 08:14:04.290464 ==
7765 08:14:04.290833
7766 08:14:04.291150
7767 08:14:04.292929 TX Vref Scan disable
7768 08:14:04.293390 == TX Byte 0 ==
7769 08:14:04.299909 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7770 08:14:04.300273 == TX Byte 1 ==
7771 08:14:04.302708 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7772 08:14:04.306241 DramC Write-DBI off
7773 08:14:04.306489
7774 08:14:04.306671 [DATLAT]
7775 08:14:04.309088 Freq=1600, CH0 RK0
7776 08:14:04.309416
7777 08:14:04.309609 DATLAT Default: 0xf
7778 08:14:04.312578 0, 0xFFFF, sum = 0
7779 08:14:04.312769 1, 0xFFFF, sum = 0
7780 08:14:04.315916 2, 0xFFFF, sum = 0
7781 08:14:04.316076 3, 0xFFFF, sum = 0
7782 08:14:04.319278 4, 0xFFFF, sum = 0
7783 08:14:04.322697 5, 0xFFFF, sum = 0
7784 08:14:04.322866 6, 0xFFFF, sum = 0
7785 08:14:04.325808 7, 0xFFFF, sum = 0
7786 08:14:04.325943 8, 0xFFFF, sum = 0
7787 08:14:04.328728 9, 0xFFFF, sum = 0
7788 08:14:04.328859 10, 0xFFFF, sum = 0
7789 08:14:04.331954 11, 0xFFFF, sum = 0
7790 08:14:04.332098 12, 0xFFFF, sum = 0
7791 08:14:04.335613 13, 0xFFFF, sum = 0
7792 08:14:04.335711 14, 0x0, sum = 1
7793 08:14:04.338460 15, 0x0, sum = 2
7794 08:14:04.338576 16, 0x0, sum = 3
7795 08:14:04.342081 17, 0x0, sum = 4
7796 08:14:04.342169 best_step = 15
7797 08:14:04.342257
7798 08:14:04.342340 ==
7799 08:14:04.345462 Dram Type= 6, Freq= 0, CH_0, rank 0
7800 08:14:04.351488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7801 08:14:04.351610 ==
7802 08:14:04.351718 RX Vref Scan: 1
7803 08:14:04.351811
7804 08:14:04.355405 Set Vref Range= 24 -> 127
7805 08:14:04.355826
7806 08:14:04.359178 RX Vref 24 -> 127, step: 1
7807 08:14:04.359696
7808 08:14:04.360034 RX Delay 19 -> 252, step: 4
7809 08:14:04.360351
7810 08:14:04.362193 Set Vref, RX VrefLevel [Byte0]: 24
7811 08:14:04.365429 [Byte1]: 24
7812 08:14:04.369489
7813 08:14:04.370062 Set Vref, RX VrefLevel [Byte0]: 25
7814 08:14:04.372829 [Byte1]: 25
7815 08:14:04.376906
7816 08:14:04.377480 Set Vref, RX VrefLevel [Byte0]: 26
7817 08:14:04.380468 [Byte1]: 26
7818 08:14:04.385010
7819 08:14:04.385574 Set Vref, RX VrefLevel [Byte0]: 27
7820 08:14:04.388295 [Byte1]: 27
7821 08:14:04.392058
7822 08:14:04.392480 Set Vref, RX VrefLevel [Byte0]: 28
7823 08:14:04.395722 [Byte1]: 28
7824 08:14:04.399742
7825 08:14:04.400267 Set Vref, RX VrefLevel [Byte0]: 29
7826 08:14:04.403373 [Byte1]: 29
7827 08:14:04.407504
7828 08:14:04.410349 Set Vref, RX VrefLevel [Byte0]: 30
7829 08:14:04.410820 [Byte1]: 30
7830 08:14:04.415490
7831 08:14:04.416046 Set Vref, RX VrefLevel [Byte0]: 31
7832 08:14:04.418550 [Byte1]: 31
7833 08:14:04.422331
7834 08:14:04.422890 Set Vref, RX VrefLevel [Byte0]: 32
7835 08:14:04.425879 [Byte1]: 32
7836 08:14:04.430051
7837 08:14:04.430608 Set Vref, RX VrefLevel [Byte0]: 33
7838 08:14:04.433628 [Byte1]: 33
7839 08:14:04.437890
7840 08:14:04.438370 Set Vref, RX VrefLevel [Byte0]: 34
7841 08:14:04.444215 [Byte1]: 34
7842 08:14:04.444787
7843 08:14:04.447751 Set Vref, RX VrefLevel [Byte0]: 35
7844 08:14:04.450372 [Byte1]: 35
7845 08:14:04.450854
7846 08:14:04.453782 Set Vref, RX VrefLevel [Byte0]: 36
7847 08:14:04.457118 [Byte1]: 36
7848 08:14:04.460391
7849 08:14:04.460963 Set Vref, RX VrefLevel [Byte0]: 37
7850 08:14:04.463507 [Byte1]: 37
7851 08:14:04.468190
7852 08:14:04.468770 Set Vref, RX VrefLevel [Byte0]: 38
7853 08:14:04.471249 [Byte1]: 38
7854 08:14:04.475648
7855 08:14:04.476130 Set Vref, RX VrefLevel [Byte0]: 39
7856 08:14:04.478700 [Byte1]: 39
7857 08:14:04.483256
7858 08:14:04.483831 Set Vref, RX VrefLevel [Byte0]: 40
7859 08:14:04.486391 [Byte1]: 40
7860 08:14:04.490708
7861 08:14:04.491189 Set Vref, RX VrefLevel [Byte0]: 41
7862 08:14:04.494447 [Byte1]: 41
7863 08:14:04.498525
7864 08:14:04.499097 Set Vref, RX VrefLevel [Byte0]: 42
7865 08:14:04.501233 [Byte1]: 42
7866 08:14:04.506092
7867 08:14:04.506659 Set Vref, RX VrefLevel [Byte0]: 43
7868 08:14:04.508772 [Byte1]: 43
7869 08:14:04.513816
7870 08:14:04.514384 Set Vref, RX VrefLevel [Byte0]: 44
7871 08:14:04.517011 [Byte1]: 44
7872 08:14:04.521083
7873 08:14:04.521703 Set Vref, RX VrefLevel [Byte0]: 45
7874 08:14:04.524610 [Byte1]: 45
7875 08:14:04.528764
7876 08:14:04.529369 Set Vref, RX VrefLevel [Byte0]: 46
7877 08:14:04.532108 [Byte1]: 46
7878 08:14:04.535950
7879 08:14:04.536433 Set Vref, RX VrefLevel [Byte0]: 47
7880 08:14:04.539920 [Byte1]: 47
7881 08:14:04.543416
7882 08:14:04.543894 Set Vref, RX VrefLevel [Byte0]: 48
7883 08:14:04.547071 [Byte1]: 48
7884 08:14:04.551064
7885 08:14:04.551544 Set Vref, RX VrefLevel [Byte0]: 49
7886 08:14:04.554955 [Byte1]: 49
7887 08:14:04.558648
7888 08:14:04.559128 Set Vref, RX VrefLevel [Byte0]: 50
7889 08:14:04.562224 [Byte1]: 50
7890 08:14:04.566636
7891 08:14:04.567208 Set Vref, RX VrefLevel [Byte0]: 51
7892 08:14:04.570205 [Byte1]: 51
7893 08:14:04.573898
7894 08:14:04.574470 Set Vref, RX VrefLevel [Byte0]: 52
7895 08:14:04.577522 [Byte1]: 52
7896 08:14:04.581502
7897 08:14:04.582069 Set Vref, RX VrefLevel [Byte0]: 53
7898 08:14:04.584798 [Byte1]: 53
7899 08:14:04.588987
7900 08:14:04.589525 Set Vref, RX VrefLevel [Byte0]: 54
7901 08:14:04.592701 [Byte1]: 54
7902 08:14:04.596700
7903 08:14:04.597275 Set Vref, RX VrefLevel [Byte0]: 55
7904 08:14:04.600072 [Byte1]: 55
7905 08:14:04.604656
7906 08:14:04.605230 Set Vref, RX VrefLevel [Byte0]: 56
7907 08:14:04.607679 [Byte1]: 56
7908 08:14:04.611619
7909 08:14:04.612099 Set Vref, RX VrefLevel [Byte0]: 57
7910 08:14:04.615609 [Byte1]: 57
7911 08:14:04.619584
7912 08:14:04.620160 Set Vref, RX VrefLevel [Byte0]: 58
7913 08:14:04.622652 [Byte1]: 58
7914 08:14:04.626994
7915 08:14:04.627564 Set Vref, RX VrefLevel [Byte0]: 59
7916 08:14:04.630036 [Byte1]: 59
7917 08:14:04.634790
7918 08:14:04.635356 Set Vref, RX VrefLevel [Byte0]: 60
7919 08:14:04.638082 [Byte1]: 60
7920 08:14:04.642197
7921 08:14:04.642804 Set Vref, RX VrefLevel [Byte0]: 61
7922 08:14:04.645374 [Byte1]: 61
7923 08:14:04.649791
7924 08:14:04.650363 Set Vref, RX VrefLevel [Byte0]: 62
7925 08:14:04.653244 [Byte1]: 62
7926 08:14:04.657731
7927 08:14:04.658303 Set Vref, RX VrefLevel [Byte0]: 63
7928 08:14:04.660463 [Byte1]: 63
7929 08:14:04.665241
7930 08:14:04.665855 Set Vref, RX VrefLevel [Byte0]: 64
7931 08:14:04.668059 [Byte1]: 64
7932 08:14:04.672838
7933 08:14:04.673414 Set Vref, RX VrefLevel [Byte0]: 65
7934 08:14:04.675953 [Byte1]: 65
7935 08:14:04.679888
7936 08:14:04.680352 Set Vref, RX VrefLevel [Byte0]: 66
7937 08:14:04.683753 [Byte1]: 66
7938 08:14:04.687993
7939 08:14:04.688548 Set Vref, RX VrefLevel [Byte0]: 67
7940 08:14:04.690831 [Byte1]: 67
7941 08:14:04.695058
7942 08:14:04.695717 Set Vref, RX VrefLevel [Byte0]: 68
7943 08:14:04.698329 [Byte1]: 68
7944 08:14:04.702429
7945 08:14:04.702908 Set Vref, RX VrefLevel [Byte0]: 69
7946 08:14:04.706498 [Byte1]: 69
7947 08:14:04.710249
7948 08:14:04.710733 Set Vref, RX VrefLevel [Byte0]: 70
7949 08:14:04.713603 [Byte1]: 70
7950 08:14:04.718062
7951 08:14:04.718544 Set Vref, RX VrefLevel [Byte0]: 71
7952 08:14:04.721787 [Byte1]: 71
7953 08:14:04.725742
7954 08:14:04.726316 Set Vref, RX VrefLevel [Byte0]: 72
7955 08:14:04.728660 [Byte1]: 72
7956 08:14:04.733225
7957 08:14:04.733873 Set Vref, RX VrefLevel [Byte0]: 73
7958 08:14:04.736160 [Byte1]: 73
7959 08:14:04.740816
7960 08:14:04.741593 Set Vref, RX VrefLevel [Byte0]: 74
7961 08:14:04.743781 [Byte1]: 74
7962 08:14:04.748078
7963 08:14:04.748634 Set Vref, RX VrefLevel [Byte0]: 75
7964 08:14:04.751369 [Byte1]: 75
7965 08:14:04.756270
7966 08:14:04.756832 Set Vref, RX VrefLevel [Byte0]: 76
7967 08:14:04.759090 [Byte1]: 76
7968 08:14:04.763188
7969 08:14:04.763651 Set Vref, RX VrefLevel [Byte0]: 77
7970 08:14:04.767056 [Byte1]: 77
7971 08:14:04.771050
7972 08:14:04.771625 Set Vref, RX VrefLevel [Byte0]: 78
7973 08:14:04.773851 [Byte1]: 78
7974 08:14:04.778617
7975 08:14:04.779181 Set Vref, RX VrefLevel [Byte0]: 79
7976 08:14:04.782241 [Byte1]: 79
7977 08:14:04.785967
7978 08:14:04.786430 Set Vref, RX VrefLevel [Byte0]: 80
7979 08:14:04.789883 [Byte1]: 80
7980 08:14:04.793892
7981 08:14:04.794451 Final RX Vref Byte 0 = 67 to rank0
7982 08:14:04.796985 Final RX Vref Byte 1 = 58 to rank0
7983 08:14:04.800246 Final RX Vref Byte 0 = 67 to rank1
7984 08:14:04.803504 Final RX Vref Byte 1 = 58 to rank1==
7985 08:14:04.806422 Dram Type= 6, Freq= 0, CH_0, rank 0
7986 08:14:04.813520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 08:14:04.814091 ==
7988 08:14:04.814465 DQS Delay:
7989 08:14:04.816735 DQS0 = 0, DQS1 = 0
7990 08:14:04.817198 DQM Delay:
7991 08:14:04.819841 DQM0 = 133, DQM1 = 122
7992 08:14:04.820403 DQ Delay:
7993 08:14:04.823193 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
7994 08:14:04.826694 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
7995 08:14:04.830051 DQ8 =114, DQ9 =110, DQ10 =122, DQ11 =118
7996 08:14:04.833245 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =128
7997 08:14:04.833866
7998 08:14:04.834357
7999 08:14:04.834809
8000 08:14:04.836107 [DramC_TX_OE_Calibration] TA2
8001 08:14:04.839547 Original DQ_B0 (3 6) =30, OEN = 27
8002 08:14:04.843148 Original DQ_B1 (3 6) =30, OEN = 27
8003 08:14:04.845888 24, 0x0, End_B0=24 End_B1=24
8004 08:14:04.849527 25, 0x0, End_B0=25 End_B1=25
8005 08:14:04.850112 26, 0x0, End_B0=26 End_B1=26
8006 08:14:04.852454 27, 0x0, End_B0=27 End_B1=27
8007 08:14:04.855782 28, 0x0, End_B0=28 End_B1=28
8008 08:14:04.859431 29, 0x0, End_B0=29 End_B1=29
8009 08:14:04.862760 30, 0x0, End_B0=30 End_B1=30
8010 08:14:04.863358 31, 0x4141, End_B0=30 End_B1=30
8011 08:14:04.865862 Byte0 end_step=30 best_step=27
8012 08:14:04.869078 Byte1 end_step=30 best_step=27
8013 08:14:04.872279 Byte0 TX OE(2T, 0.5T) = (3, 3)
8014 08:14:04.875556 Byte1 TX OE(2T, 0.5T) = (3, 3)
8015 08:14:04.876027
8016 08:14:04.876398
8017 08:14:04.882116 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f11, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 394 ps
8018 08:14:04.885583 CH0 RK0: MR19=303, MR18=1F11
8019 08:14:04.891878 CH0_RK0: MR19=0x303, MR18=0x1F11, DQSOSC=394, MR23=63, INC=23, DEC=15
8020 08:14:04.892451
8021 08:14:04.895337 ----->DramcWriteLeveling(PI) begin...
8022 08:14:04.895919 ==
8023 08:14:04.898848 Dram Type= 6, Freq= 0, CH_0, rank 1
8024 08:14:04.904928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 08:14:04.905529 ==
8026 08:14:04.907993 Write leveling (Byte 0): 36 => 36
8027 08:14:04.908467 Write leveling (Byte 1): 28 => 28
8028 08:14:04.911600 DramcWriteLeveling(PI) end<-----
8029 08:14:04.912177
8030 08:14:04.914866 ==
8031 08:14:04.915451 Dram Type= 6, Freq= 0, CH_0, rank 1
8032 08:14:04.921731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8033 08:14:04.922306 ==
8034 08:14:04.924461 [Gating] SW mode calibration
8035 08:14:04.931106 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8036 08:14:04.934021 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8037 08:14:04.940821 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 08:14:04.944370 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 08:14:04.948132 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 08:14:04.954004 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 08:14:04.957869 1 4 16 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8042 08:14:04.960913 1 4 20 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
8043 08:14:04.967033 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8044 08:14:04.970345 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 08:14:04.973797 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8046 08:14:04.980496 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 08:14:04.983568 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8048 08:14:04.987141 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8049 08:14:04.993261 1 5 16 | B1->B0 | 3434 2626 | 1 1 | (1 0) (1 0)
8050 08:14:04.996965 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
8051 08:14:05.003326 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 08:14:05.006517 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 08:14:05.010134 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 08:14:05.016406 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 08:14:05.019635 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 08:14:05.023296 1 6 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8057 08:14:05.026393 1 6 16 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8058 08:14:05.032720 1 6 20 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
8059 08:14:05.036239 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 08:14:05.039924 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 08:14:05.045892 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 08:14:05.049037 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 08:14:05.052702 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 08:14:05.059467 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8065 08:14:05.062801 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8066 08:14:05.065955 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8067 08:14:05.072092 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 08:14:05.075582 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 08:14:05.082229 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 08:14:05.085615 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 08:14:05.088782 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 08:14:05.095726 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 08:14:05.099022 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 08:14:05.102246 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 08:14:05.108613 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 08:14:05.111691 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 08:14:05.115342 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 08:14:05.122022 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 08:14:05.125190 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8080 08:14:05.128638 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8081 08:14:05.135351 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8082 08:14:05.135923 Total UI for P1: 0, mck2ui 16
8083 08:14:05.141706 best dqsien dly found for B0: ( 1, 9, 10)
8084 08:14:05.144709 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8085 08:14:05.148312 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 08:14:05.151622 Total UI for P1: 0, mck2ui 16
8087 08:14:05.154680 best dqsien dly found for B1: ( 1, 9, 18)
8088 08:14:05.158014 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8089 08:14:05.161576 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8090 08:14:05.162143
8091 08:14:05.164673 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8092 08:14:05.171071 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8093 08:14:05.171634 [Gating] SW calibration Done
8094 08:14:05.174643 ==
8095 08:14:05.178061 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 08:14:05.180924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 08:14:05.181444 ==
8098 08:14:05.181830 RX Vref Scan: 0
8099 08:14:05.182181
8100 08:14:05.184736 RX Vref 0 -> 0, step: 1
8101 08:14:05.185307
8102 08:14:05.187838 RX Delay 0 -> 252, step: 8
8103 08:14:05.191085 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8104 08:14:05.194359 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8105 08:14:05.197529 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8106 08:14:05.204300 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8107 08:14:05.207266 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8108 08:14:05.210993 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8109 08:14:05.214575 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8110 08:14:05.217411 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8111 08:14:05.223987 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8112 08:14:05.227004 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8113 08:14:05.230620 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8114 08:14:05.233750 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8115 08:14:05.239989 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8116 08:14:05.243492 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8117 08:14:05.247053 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8118 08:14:05.249847 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8119 08:14:05.250414 ==
8120 08:14:05.253596 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 08:14:05.259993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 08:14:05.260586 ==
8123 08:14:05.260964 DQS Delay:
8124 08:14:05.263625 DQS0 = 0, DQS1 = 0
8125 08:14:05.264184 DQM Delay:
8126 08:14:05.267048 DQM0 = 133, DQM1 = 129
8127 08:14:05.267606 DQ Delay:
8128 08:14:05.269848 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8129 08:14:05.273267 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8130 08:14:05.276595 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8131 08:14:05.279542 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
8132 08:14:05.280009
8133 08:14:05.280426
8134 08:14:05.280783 ==
8135 08:14:05.283076 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 08:14:05.289437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 08:14:05.289923 ==
8138 08:14:05.290336
8139 08:14:05.290697
8140 08:14:05.291070 TX Vref Scan disable
8141 08:14:05.293187 == TX Byte 0 ==
8142 08:14:05.296629 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8143 08:14:05.302989 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8144 08:14:05.303556 == TX Byte 1 ==
8145 08:14:05.306065 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8146 08:14:05.312747 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8147 08:14:05.313214 ==
8148 08:14:05.316285 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 08:14:05.319487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 08:14:05.320049 ==
8151 08:14:05.334052
8152 08:14:05.337482 TX Vref early break, caculate TX vref
8153 08:14:05.341027 TX Vref=16, minBit 0, minWin=23, winSum=378
8154 08:14:05.344046 TX Vref=18, minBit 0, minWin=23, winSum=384
8155 08:14:05.347147 TX Vref=20, minBit 0, minWin=23, winSum=393
8156 08:14:05.350515 TX Vref=22, minBit 1, minWin=24, winSum=409
8157 08:14:05.353732 TX Vref=24, minBit 1, minWin=24, winSum=409
8158 08:14:05.360219 TX Vref=26, minBit 0, minWin=24, winSum=410
8159 08:14:05.363882 TX Vref=28, minBit 4, minWin=24, winSum=411
8160 08:14:05.367071 TX Vref=30, minBit 0, minWin=24, winSum=404
8161 08:14:05.369994 TX Vref=32, minBit 5, minWin=23, winSum=392
8162 08:14:05.373488 TX Vref=34, minBit 1, minWin=23, winSum=391
8163 08:14:05.380265 TX Vref=36, minBit 1, minWin=22, winSum=380
8164 08:14:05.383626 [TxChooseVref] Worse bit 4, Min win 24, Win sum 411, Final Vref 28
8165 08:14:05.384098
8166 08:14:05.386711 Final TX Range 0 Vref 28
8167 08:14:05.387185
8168 08:14:05.387569 ==
8169 08:14:05.390134 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 08:14:05.392993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 08:14:05.393457 ==
8172 08:14:05.396330
8173 08:14:05.396754
8174 08:14:05.397140 TX Vref Scan disable
8175 08:14:05.403259 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8176 08:14:05.403685 == TX Byte 0 ==
8177 08:14:05.406198 u2DelayCellOfst[0]=14 cells (4 PI)
8178 08:14:05.409427 u2DelayCellOfst[1]=18 cells (5 PI)
8179 08:14:05.412924 u2DelayCellOfst[2]=14 cells (4 PI)
8180 08:14:05.416824 u2DelayCellOfst[3]=14 cells (4 PI)
8181 08:14:05.419407 u2DelayCellOfst[4]=11 cells (3 PI)
8182 08:14:05.422908 u2DelayCellOfst[5]=0 cells (0 PI)
8183 08:14:05.426219 u2DelayCellOfst[6]=18 cells (5 PI)
8184 08:14:05.429990 u2DelayCellOfst[7]=22 cells (6 PI)
8185 08:14:05.432649 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8186 08:14:05.436747 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8187 08:14:05.439809 == TX Byte 1 ==
8188 08:14:05.442589 u2DelayCellOfst[8]=0 cells (0 PI)
8189 08:14:05.445963 u2DelayCellOfst[9]=0 cells (0 PI)
8190 08:14:05.449225 u2DelayCellOfst[10]=3 cells (1 PI)
8191 08:14:05.452772 u2DelayCellOfst[11]=0 cells (0 PI)
8192 08:14:05.455752 u2DelayCellOfst[12]=11 cells (3 PI)
8193 08:14:05.459438 u2DelayCellOfst[13]=11 cells (3 PI)
8194 08:14:05.462667 u2DelayCellOfst[14]=14 cells (4 PI)
8195 08:14:05.466025 u2DelayCellOfst[15]=7 cells (2 PI)
8196 08:14:05.469830 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8197 08:14:05.472405 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8198 08:14:05.475640 DramC Write-DBI on
8199 08:14:05.476206 ==
8200 08:14:05.478949 Dram Type= 6, Freq= 0, CH_0, rank 1
8201 08:14:05.482257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8202 08:14:05.482695 ==
8203 08:14:05.483134
8204 08:14:05.483543
8205 08:14:05.485542 TX Vref Scan disable
8206 08:14:05.489024 == TX Byte 0 ==
8207 08:14:05.492306 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8208 08:14:05.492788 == TX Byte 1 ==
8209 08:14:05.498511 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8210 08:14:05.498932 DramC Write-DBI off
8211 08:14:05.499260
8212 08:14:05.499659 [DATLAT]
8213 08:14:05.501850 Freq=1600, CH0 RK1
8214 08:14:05.502272
8215 08:14:05.505418 DATLAT Default: 0xf
8216 08:14:05.505841 0, 0xFFFF, sum = 0
8217 08:14:05.508496 1, 0xFFFF, sum = 0
8218 08:14:05.508925 2, 0xFFFF, sum = 0
8219 08:14:05.511928 3, 0xFFFF, sum = 0
8220 08:14:05.512358 4, 0xFFFF, sum = 0
8221 08:14:05.515174 5, 0xFFFF, sum = 0
8222 08:14:05.515697 6, 0xFFFF, sum = 0
8223 08:14:05.518490 7, 0xFFFF, sum = 0
8224 08:14:05.518917 8, 0xFFFF, sum = 0
8225 08:14:05.521400 9, 0xFFFF, sum = 0
8226 08:14:05.521829 10, 0xFFFF, sum = 0
8227 08:14:05.525178 11, 0xFFFF, sum = 0
8228 08:14:05.525754 12, 0xFFFF, sum = 0
8229 08:14:05.528569 13, 0xFFFF, sum = 0
8230 08:14:05.528998 14, 0x0, sum = 1
8231 08:14:05.531760 15, 0x0, sum = 2
8232 08:14:05.532280 16, 0x0, sum = 3
8233 08:14:05.535592 17, 0x0, sum = 4
8234 08:14:05.536119 best_step = 15
8235 08:14:05.536457
8236 08:14:05.536770 ==
8237 08:14:05.538013 Dram Type= 6, Freq= 0, CH_0, rank 1
8238 08:14:05.545269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8239 08:14:05.545825 ==
8240 08:14:05.546167 RX Vref Scan: 0
8241 08:14:05.546499
8242 08:14:05.547991 RX Vref 0 -> 0, step: 1
8243 08:14:05.548413
8244 08:14:05.551714 RX Delay 11 -> 252, step: 4
8245 08:14:05.554472 iDelay=191, Bit 0, Center 128 (79 ~ 178) 100
8246 08:14:05.557898 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8247 08:14:05.564752 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8248 08:14:05.568328 iDelay=191, Bit 3, Center 128 (75 ~ 182) 108
8249 08:14:05.571200 iDelay=191, Bit 4, Center 132 (79 ~ 186) 108
8250 08:14:05.574341 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8251 08:14:05.577881 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8252 08:14:05.584480 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8253 08:14:05.587606 iDelay=191, Bit 8, Center 116 (63 ~ 170) 108
8254 08:14:05.590778 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8255 08:14:05.594220 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8256 08:14:05.597555 iDelay=191, Bit 11, Center 120 (67 ~ 174) 108
8257 08:14:05.603827 iDelay=191, Bit 12, Center 130 (79 ~ 182) 104
8258 08:14:05.607360 iDelay=191, Bit 13, Center 132 (79 ~ 186) 108
8259 08:14:05.610317 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8260 08:14:05.613744 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8261 08:14:05.617177 ==
8262 08:14:05.620459 Dram Type= 6, Freq= 0, CH_0, rank 1
8263 08:14:05.624119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 08:14:05.624681 ==
8265 08:14:05.625057 DQS Delay:
8266 08:14:05.626788 DQS0 = 0, DQS1 = 0
8267 08:14:05.627347 DQM Delay:
8268 08:14:05.630049 DQM0 = 129, DQM1 = 125
8269 08:14:05.630515 DQ Delay:
8270 08:14:05.633498 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =128
8271 08:14:05.637542 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
8272 08:14:05.640097 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8273 08:14:05.642963 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =134
8274 08:14:05.643429
8275 08:14:05.643799
8276 08:14:05.644143
8277 08:14:05.646426 [DramC_TX_OE_Calibration] TA2
8278 08:14:05.650056 Original DQ_B0 (3 6) =30, OEN = 27
8279 08:14:05.652887 Original DQ_B1 (3 6) =30, OEN = 27
8280 08:14:05.656760 24, 0x0, End_B0=24 End_B1=24
8281 08:14:05.659544 25, 0x0, End_B0=25 End_B1=25
8282 08:14:05.663263 26, 0x0, End_B0=26 End_B1=26
8283 08:14:05.663831 27, 0x0, End_B0=27 End_B1=27
8284 08:14:05.665853 28, 0x0, End_B0=28 End_B1=28
8285 08:14:05.669318 29, 0x0, End_B0=29 End_B1=29
8286 08:14:05.672997 30, 0x0, End_B0=30 End_B1=30
8287 08:14:05.676017 31, 0x4141, End_B0=30 End_B1=30
8288 08:14:05.676492 Byte0 end_step=30 best_step=27
8289 08:14:05.679820 Byte1 end_step=30 best_step=27
8290 08:14:05.682594 Byte0 TX OE(2T, 0.5T) = (3, 3)
8291 08:14:05.686231 Byte1 TX OE(2T, 0.5T) = (3, 3)
8292 08:14:05.686793
8293 08:14:05.687158
8294 08:14:05.695568 [DQSOSCAuto] RK1, (LSB)MR18= 0x1afe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 396 ps
8295 08:14:05.696037 CH0 RK1: MR19=302, MR18=1AFE
8296 08:14:05.702327 CH0_RK1: MR19=0x302, MR18=0x1AFE, DQSOSC=396, MR23=63, INC=23, DEC=15
8297 08:14:05.705641 [RxdqsGatingPostProcess] freq 1600
8298 08:14:05.712262 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8299 08:14:05.715984 best DQS0 dly(2T, 0.5T) = (1, 1)
8300 08:14:05.719296 best DQS1 dly(2T, 0.5T) = (1, 1)
8301 08:14:05.722181 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8302 08:14:05.725129 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8303 08:14:05.725640 best DQS0 dly(2T, 0.5T) = (1, 1)
8304 08:14:05.728437 best DQS1 dly(2T, 0.5T) = (1, 1)
8305 08:14:05.732192 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8306 08:14:05.735316 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8307 08:14:05.738361 Pre-setting of DQS Precalculation
8308 08:14:05.745070 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8309 08:14:05.745762 ==
8310 08:14:05.748276 Dram Type= 6, Freq= 0, CH_1, rank 0
8311 08:14:05.751897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8312 08:14:05.752454 ==
8313 08:14:05.762224 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8314 08:14:05.762687 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8315 08:14:05.765056 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8316 08:14:05.771604 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8317 08:14:05.780475 [CA 0] Center 42 (13~71) winsize 59
8318 08:14:05.783975 [CA 1] Center 42 (13~71) winsize 59
8319 08:14:05.786943 [CA 2] Center 37 (8~66) winsize 59
8320 08:14:05.790519 [CA 3] Center 36 (7~65) winsize 59
8321 08:14:05.794017 [CA 4] Center 37 (7~67) winsize 61
8322 08:14:05.796753 [CA 5] Center 36 (7~66) winsize 60
8323 08:14:05.797303
8324 08:14:05.800502 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8325 08:14:05.801054
8326 08:14:05.806598 [CATrainingPosCal] consider 1 rank data
8327 08:14:05.807167 u2DelayCellTimex100 = 262/100 ps
8328 08:14:05.813290 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8329 08:14:05.816997 CA1 delay=42 (13~71),Diff = 6 PI (22 cell)
8330 08:14:05.820046 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8331 08:14:05.823204 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8332 08:14:05.826714 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8333 08:14:05.829786 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8334 08:14:05.830245
8335 08:14:05.833111 CA PerBit enable=1, Macro0, CA PI delay=36
8336 08:14:05.833687
8337 08:14:05.836572 [CBTSetCACLKResult] CA Dly = 36
8338 08:14:05.839512 CS Dly: 9 (0~40)
8339 08:14:05.842697 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8340 08:14:05.846027 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8341 08:14:05.846489 ==
8342 08:14:05.849460 Dram Type= 6, Freq= 0, CH_1, rank 1
8343 08:14:05.856283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8344 08:14:05.856823 ==
8345 08:14:05.859473 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8346 08:14:05.866064 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8347 08:14:05.869403 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8348 08:14:05.876268 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8349 08:14:05.883961 [CA 0] Center 42 (13~72) winsize 60
8350 08:14:05.886976 [CA 1] Center 42 (12~72) winsize 61
8351 08:14:05.889942 [CA 2] Center 37 (8~67) winsize 60
8352 08:14:05.893615 [CA 3] Center 37 (8~66) winsize 59
8353 08:14:05.896800 [CA 4] Center 37 (8~67) winsize 60
8354 08:14:05.899984 [CA 5] Center 37 (8~66) winsize 59
8355 08:14:05.900451
8356 08:14:05.903914 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8357 08:14:05.904479
8358 08:14:05.906880 [CATrainingPosCal] consider 2 rank data
8359 08:14:05.909858 u2DelayCellTimex100 = 262/100 ps
8360 08:14:05.916767 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8361 08:14:05.920112 CA1 delay=42 (13~71),Diff = 6 PI (22 cell)
8362 08:14:05.923713 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8363 08:14:05.926643 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8364 08:14:05.929775 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8365 08:14:05.933500 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8366 08:14:05.934096
8367 08:14:05.936503 CA PerBit enable=1, Macro0, CA PI delay=36
8368 08:14:05.936985
8369 08:14:05.939759 [CBTSetCACLKResult] CA Dly = 36
8370 08:14:05.942896 CS Dly: 11 (0~44)
8371 08:14:05.946127 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8372 08:14:05.949153 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8373 08:14:05.949680
8374 08:14:05.952333 ----->DramcWriteLeveling(PI) begin...
8375 08:14:05.952821 ==
8376 08:14:05.956213 Dram Type= 6, Freq= 0, CH_1, rank 0
8377 08:14:05.962508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8378 08:14:05.963089 ==
8379 08:14:05.965790 Write leveling (Byte 0): 23 => 23
8380 08:14:05.969014 Write leveling (Byte 1): 27 => 27
8381 08:14:05.972411 DramcWriteLeveling(PI) end<-----
8382 08:14:05.972885
8383 08:14:05.973489 ==
8384 08:14:05.975295 Dram Type= 6, Freq= 0, CH_1, rank 0
8385 08:14:05.978815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8386 08:14:05.979301 ==
8387 08:14:05.981901 [Gating] SW mode calibration
8388 08:14:05.988780 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8389 08:14:05.995255 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8390 08:14:05.999001 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 08:14:06.002178 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 08:14:06.008634 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 08:14:06.011621 1 4 12 | B1->B0 | 2726 3131 | 1 0 | (0 0) (0 0)
8394 08:14:06.015042 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 08:14:06.021643 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 08:14:06.024636 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 08:14:06.028453 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 08:14:06.034317 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 08:14:06.037663 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 08:14:06.041042 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8401 08:14:06.047721 1 5 12 | B1->B0 | 3232 2a2a | 1 0 | (1 0) (0 1)
8402 08:14:06.051249 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8403 08:14:06.054404 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 08:14:06.060621 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 08:14:06.064349 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 08:14:06.067698 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 08:14:06.073868 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 08:14:06.077321 1 6 8 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
8409 08:14:06.080440 1 6 12 | B1->B0 | 3636 4545 | 1 0 | (0 0) (0 0)
8410 08:14:06.086855 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 08:14:06.090833 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 08:14:06.094023 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 08:14:06.100231 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 08:14:06.103349 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 08:14:06.107105 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 08:14:06.113278 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 08:14:06.116995 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8418 08:14:06.119936 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8419 08:14:06.126711 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 08:14:06.129969 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 08:14:06.133627 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 08:14:06.139600 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 08:14:06.142990 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 08:14:06.146496 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 08:14:06.153421 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 08:14:06.156442 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 08:14:06.159520 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 08:14:06.165993 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 08:14:06.169862 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 08:14:06.172932 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 08:14:06.180136 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 08:14:06.182409 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8433 08:14:06.186325 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8434 08:14:06.192621 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8435 08:14:06.195877 Total UI for P1: 0, mck2ui 16
8436 08:14:06.199227 best dqsien dly found for B0: ( 1, 9, 10)
8437 08:14:06.202321 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 08:14:06.205449 Total UI for P1: 0, mck2ui 16
8439 08:14:06.209114 best dqsien dly found for B1: ( 1, 9, 14)
8440 08:14:06.212332 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8441 08:14:06.215642 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8442 08:14:06.216209
8443 08:14:06.218930 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8444 08:14:06.225864 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8445 08:14:06.226427 [Gating] SW calibration Done
8446 08:14:06.226798 ==
8447 08:14:06.229271 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 08:14:06.235696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 08:14:06.236261 ==
8450 08:14:06.236636 RX Vref Scan: 0
8451 08:14:06.236988
8452 08:14:06.238925 RX Vref 0 -> 0, step: 1
8453 08:14:06.239438
8454 08:14:06.242092 RX Delay 0 -> 252, step: 8
8455 08:14:06.245156 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8456 08:14:06.248423 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8457 08:14:06.252491 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8458 08:14:06.258174 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8459 08:14:06.262033 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8460 08:14:06.265103 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8461 08:14:06.268070 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8462 08:14:06.271977 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8463 08:14:06.278295 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8464 08:14:06.281625 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8465 08:14:06.284799 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8466 08:14:06.288120 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8467 08:14:06.291623 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8468 08:14:06.298350 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8469 08:14:06.301472 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8470 08:14:06.304795 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8471 08:14:06.305259 ==
8472 08:14:06.307687 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 08:14:06.314113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 08:14:06.314604 ==
8475 08:14:06.314974 DQS Delay:
8476 08:14:06.315319 DQS0 = 0, DQS1 = 0
8477 08:14:06.317956 DQM Delay:
8478 08:14:06.318518 DQM0 = 138, DQM1 = 130
8479 08:14:06.320837 DQ Delay:
8480 08:14:06.324573 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =139
8481 08:14:06.327793 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8482 08:14:06.330638 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8483 08:14:06.334527 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =143
8484 08:14:06.335100
8485 08:14:06.335475
8486 08:14:06.335819 ==
8487 08:14:06.337569 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 08:14:06.340877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 08:14:06.343518 ==
8490 08:14:06.344151
8491 08:14:06.344536
8492 08:14:06.344882 TX Vref Scan disable
8493 08:14:06.347653 == TX Byte 0 ==
8494 08:14:06.351018 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8495 08:14:06.353938 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8496 08:14:06.357641 == TX Byte 1 ==
8497 08:14:06.360345 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8498 08:14:06.366751 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8499 08:14:06.367302 ==
8500 08:14:06.370007 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 08:14:06.373801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 08:14:06.374364 ==
8503 08:14:06.386214
8504 08:14:06.389491 TX Vref early break, caculate TX vref
8505 08:14:06.392647 TX Vref=16, minBit 5, minWin=21, winSum=372
8506 08:14:06.395715 TX Vref=18, minBit 0, minWin=22, winSum=383
8507 08:14:06.399404 TX Vref=20, minBit 0, minWin=22, winSum=390
8508 08:14:06.402619 TX Vref=22, minBit 0, minWin=24, winSum=406
8509 08:14:06.405895 TX Vref=24, minBit 5, minWin=24, winSum=412
8510 08:14:06.412002 TX Vref=26, minBit 0, minWin=25, winSum=421
8511 08:14:06.415551 TX Vref=28, minBit 5, minWin=24, winSum=420
8512 08:14:06.418913 TX Vref=30, minBit 1, minWin=23, winSum=411
8513 08:14:06.421775 TX Vref=32, minBit 0, minWin=24, winSum=400
8514 08:14:06.425537 TX Vref=34, minBit 0, minWin=23, winSum=389
8515 08:14:06.432068 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 26
8516 08:14:06.432537
8517 08:14:06.435205 Final TX Range 0 Vref 26
8518 08:14:06.435670
8519 08:14:06.436034 ==
8520 08:14:06.438821 Dram Type= 6, Freq= 0, CH_1, rank 0
8521 08:14:06.442371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8522 08:14:06.442955 ==
8523 08:14:06.443328
8524 08:14:06.444729
8525 08:14:06.445190 TX Vref Scan disable
8526 08:14:06.451871 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8527 08:14:06.452492 == TX Byte 0 ==
8528 08:14:06.454473 u2DelayCellOfst[0]=14 cells (4 PI)
8529 08:14:06.458098 u2DelayCellOfst[1]=11 cells (3 PI)
8530 08:14:06.461248 u2DelayCellOfst[2]=0 cells (0 PI)
8531 08:14:06.464897 u2DelayCellOfst[3]=3 cells (1 PI)
8532 08:14:06.467806 u2DelayCellOfst[4]=7 cells (2 PI)
8533 08:14:06.471431 u2DelayCellOfst[5]=18 cells (5 PI)
8534 08:14:06.474814 u2DelayCellOfst[6]=18 cells (5 PI)
8535 08:14:06.477659 u2DelayCellOfst[7]=3 cells (1 PI)
8536 08:14:06.480889 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8537 08:14:06.484356 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8538 08:14:06.488053 == TX Byte 1 ==
8539 08:14:06.491378 u2DelayCellOfst[8]=0 cells (0 PI)
8540 08:14:06.494113 u2DelayCellOfst[9]=3 cells (1 PI)
8541 08:14:06.497708 u2DelayCellOfst[10]=11 cells (3 PI)
8542 08:14:06.501188 u2DelayCellOfst[11]=7 cells (2 PI)
8543 08:14:06.504501 u2DelayCellOfst[12]=14 cells (4 PI)
8544 08:14:06.507559 u2DelayCellOfst[13]=18 cells (5 PI)
8545 08:14:06.508069 u2DelayCellOfst[14]=18 cells (5 PI)
8546 08:14:06.510505 u2DelayCellOfst[15]=18 cells (5 PI)
8547 08:14:06.517188 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8548 08:14:06.520512 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8549 08:14:06.523797 DramC Write-DBI on
8550 08:14:06.524369 ==
8551 08:14:06.527165 Dram Type= 6, Freq= 0, CH_1, rank 0
8552 08:14:06.529963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8553 08:14:06.530432 ==
8554 08:14:06.530802
8555 08:14:06.531488
8556 08:14:06.533706 TX Vref Scan disable
8557 08:14:06.534215 == TX Byte 0 ==
8558 08:14:06.539691 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8559 08:14:06.540188 == TX Byte 1 ==
8560 08:14:06.543373 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8561 08:14:06.546693 DramC Write-DBI off
8562 08:14:06.547112
8563 08:14:06.547444 [DATLAT]
8564 08:14:06.549859 Freq=1600, CH1 RK0
8565 08:14:06.550287
8566 08:14:06.550624 DATLAT Default: 0xf
8567 08:14:06.553322 0, 0xFFFF, sum = 0
8568 08:14:06.556254 1, 0xFFFF, sum = 0
8569 08:14:06.556684 2, 0xFFFF, sum = 0
8570 08:14:06.559430 3, 0xFFFF, sum = 0
8571 08:14:06.559877 4, 0xFFFF, sum = 0
8572 08:14:06.562941 5, 0xFFFF, sum = 0
8573 08:14:06.563370 6, 0xFFFF, sum = 0
8574 08:14:06.566418 7, 0xFFFF, sum = 0
8575 08:14:06.567132 8, 0xFFFF, sum = 0
8576 08:14:06.569308 9, 0xFFFF, sum = 0
8577 08:14:06.569783 10, 0xFFFF, sum = 0
8578 08:14:06.573454 11, 0xFFFF, sum = 0
8579 08:14:06.573974 12, 0xFFFF, sum = 0
8580 08:14:06.576319 13, 0xFFFF, sum = 0
8581 08:14:06.576746 14, 0x0, sum = 1
8582 08:14:06.579460 15, 0x0, sum = 2
8583 08:14:06.580014 16, 0x0, sum = 3
8584 08:14:06.582969 17, 0x0, sum = 4
8585 08:14:06.583395 best_step = 15
8586 08:14:06.583732
8587 08:14:06.584051 ==
8588 08:14:06.586371 Dram Type= 6, Freq= 0, CH_1, rank 0
8589 08:14:06.593173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8590 08:14:06.593835 ==
8591 08:14:06.594246 RX Vref Scan: 1
8592 08:14:06.594603
8593 08:14:06.596456 Set Vref Range= 24 -> 127
8594 08:14:06.596877
8595 08:14:06.599100 RX Vref 24 -> 127, step: 1
8596 08:14:06.599520
8597 08:14:06.599857 RX Delay 11 -> 252, step: 4
8598 08:14:06.602572
8599 08:14:06.602991 Set Vref, RX VrefLevel [Byte0]: 24
8600 08:14:06.606056 [Byte1]: 24
8601 08:14:06.610346
8602 08:14:06.610890 Set Vref, RX VrefLevel [Byte0]: 25
8603 08:14:06.613592 [Byte1]: 25
8604 08:14:06.617670
8605 08:14:06.618170 Set Vref, RX VrefLevel [Byte0]: 26
8606 08:14:06.621091 [Byte1]: 26
8607 08:14:06.626078
8608 08:14:06.626596 Set Vref, RX VrefLevel [Byte0]: 27
8609 08:14:06.628847 [Byte1]: 27
8610 08:14:06.633159
8611 08:14:06.633718 Set Vref, RX VrefLevel [Byte0]: 28
8612 08:14:06.636644 [Byte1]: 28
8613 08:14:06.640694
8614 08:14:06.641214 Set Vref, RX VrefLevel [Byte0]: 29
8615 08:14:06.643783 [Byte1]: 29
8616 08:14:06.648192
8617 08:14:06.648616 Set Vref, RX VrefLevel [Byte0]: 30
8618 08:14:06.651450 [Byte1]: 30
8619 08:14:06.655919
8620 08:14:06.656389 Set Vref, RX VrefLevel [Byte0]: 31
8621 08:14:06.659163 [Byte1]: 31
8622 08:14:06.663900
8623 08:14:06.664413 Set Vref, RX VrefLevel [Byte0]: 32
8624 08:14:06.666744 [Byte1]: 32
8625 08:14:06.671447
8626 08:14:06.671959 Set Vref, RX VrefLevel [Byte0]: 33
8627 08:14:06.674869 [Byte1]: 33
8628 08:14:06.678649
8629 08:14:06.679070 Set Vref, RX VrefLevel [Byte0]: 34
8630 08:14:06.682159 [Byte1]: 34
8631 08:14:06.686434
8632 08:14:06.686871 Set Vref, RX VrefLevel [Byte0]: 35
8633 08:14:06.689555 [Byte1]: 35
8634 08:14:06.694031
8635 08:14:06.694535 Set Vref, RX VrefLevel [Byte0]: 36
8636 08:14:06.697406 [Byte1]: 36
8637 08:14:06.701845
8638 08:14:06.702364 Set Vref, RX VrefLevel [Byte0]: 37
8639 08:14:06.705511 [Byte1]: 37
8640 08:14:06.709324
8641 08:14:06.709959 Set Vref, RX VrefLevel [Byte0]: 38
8642 08:14:06.712587 [Byte1]: 38
8643 08:14:06.717064
8644 08:14:06.717655 Set Vref, RX VrefLevel [Byte0]: 39
8645 08:14:06.720720 [Byte1]: 39
8646 08:14:06.724783
8647 08:14:06.725249 Set Vref, RX VrefLevel [Byte0]: 40
8648 08:14:06.728301 [Byte1]: 40
8649 08:14:06.732386
8650 08:14:06.732945 Set Vref, RX VrefLevel [Byte0]: 41
8651 08:14:06.735053 [Byte1]: 41
8652 08:14:06.740086
8653 08:14:06.740708 Set Vref, RX VrefLevel [Byte0]: 42
8654 08:14:06.743457 [Byte1]: 42
8655 08:14:06.747687
8656 08:14:06.748150 Set Vref, RX VrefLevel [Byte0]: 43
8657 08:14:06.750916 [Byte1]: 43
8658 08:14:06.755599
8659 08:14:06.756158 Set Vref, RX VrefLevel [Byte0]: 44
8660 08:14:06.758257 [Byte1]: 44
8661 08:14:06.762526
8662 08:14:06.763087 Set Vref, RX VrefLevel [Byte0]: 45
8663 08:14:06.766235 [Byte1]: 45
8664 08:14:06.770270
8665 08:14:06.770826 Set Vref, RX VrefLevel [Byte0]: 46
8666 08:14:06.773392 [Byte1]: 46
8667 08:14:06.777806
8668 08:14:06.778357 Set Vref, RX VrefLevel [Byte0]: 47
8669 08:14:06.780878 [Byte1]: 47
8670 08:14:06.785529
8671 08:14:06.786322 Set Vref, RX VrefLevel [Byte0]: 48
8672 08:14:06.788815 [Byte1]: 48
8673 08:14:06.793322
8674 08:14:06.793909 Set Vref, RX VrefLevel [Byte0]: 49
8675 08:14:06.796112 [Byte1]: 49
8676 08:14:06.800889
8677 08:14:06.801493 Set Vref, RX VrefLevel [Byte0]: 50
8678 08:14:06.804001 [Byte1]: 50
8679 08:14:06.808513
8680 08:14:06.809073 Set Vref, RX VrefLevel [Byte0]: 51
8681 08:14:06.811744 [Byte1]: 51
8682 08:14:06.815641
8683 08:14:06.816105 Set Vref, RX VrefLevel [Byte0]: 52
8684 08:14:06.818991 [Byte1]: 52
8685 08:14:06.823527
8686 08:14:06.824088 Set Vref, RX VrefLevel [Byte0]: 53
8687 08:14:06.827089 [Byte1]: 53
8688 08:14:06.831159
8689 08:14:06.831625 Set Vref, RX VrefLevel [Byte0]: 54
8690 08:14:06.834182 [Byte1]: 54
8691 08:14:06.839007
8692 08:14:06.839466 Set Vref, RX VrefLevel [Byte0]: 55
8693 08:14:06.841898 [Byte1]: 55
8694 08:14:06.846497
8695 08:14:06.847268 Set Vref, RX VrefLevel [Byte0]: 56
8696 08:14:06.849384 [Byte1]: 56
8697 08:14:06.854506
8698 08:14:06.855066 Set Vref, RX VrefLevel [Byte0]: 57
8699 08:14:06.857143 [Byte1]: 57
8700 08:14:06.861718
8701 08:14:06.862278 Set Vref, RX VrefLevel [Byte0]: 58
8702 08:14:06.865093 [Byte1]: 58
8703 08:14:06.869160
8704 08:14:06.869834 Set Vref, RX VrefLevel [Byte0]: 59
8705 08:14:06.872215 [Byte1]: 59
8706 08:14:06.876901
8707 08:14:06.877495 Set Vref, RX VrefLevel [Byte0]: 60
8708 08:14:06.880158 [Byte1]: 60
8709 08:14:06.884436
8710 08:14:06.885013 Set Vref, RX VrefLevel [Byte0]: 61
8711 08:14:06.887805 [Byte1]: 61
8712 08:14:06.892361
8713 08:14:06.892922 Set Vref, RX VrefLevel [Byte0]: 62
8714 08:14:06.895333 [Byte1]: 62
8715 08:14:06.899731
8716 08:14:06.900296 Set Vref, RX VrefLevel [Byte0]: 63
8717 08:14:06.902857 [Byte1]: 63
8718 08:14:06.907169
8719 08:14:06.907632 Set Vref, RX VrefLevel [Byte0]: 64
8720 08:14:06.910549 [Byte1]: 64
8721 08:14:06.914809
8722 08:14:06.915269 Set Vref, RX VrefLevel [Byte0]: 65
8723 08:14:06.918560 [Byte1]: 65
8724 08:14:06.922628
8725 08:14:06.923182 Set Vref, RX VrefLevel [Byte0]: 66
8726 08:14:06.926313 [Byte1]: 66
8727 08:14:06.930242
8728 08:14:06.930805 Set Vref, RX VrefLevel [Byte0]: 67
8729 08:14:06.933504 [Byte1]: 67
8730 08:14:06.937640
8731 08:14:06.938101 Set Vref, RX VrefLevel [Byte0]: 68
8732 08:14:06.941462 [Byte1]: 68
8733 08:14:06.945594
8734 08:14:06.946145 Set Vref, RX VrefLevel [Byte0]: 69
8735 08:14:06.948623 [Byte1]: 69
8736 08:14:06.953312
8737 08:14:06.953916 Set Vref, RX VrefLevel [Byte0]: 70
8738 08:14:06.956276 [Byte1]: 70
8739 08:14:06.961160
8740 08:14:06.961787 Set Vref, RX VrefLevel [Byte0]: 71
8741 08:14:06.963900 [Byte1]: 71
8742 08:14:06.968149
8743 08:14:06.968713 Set Vref, RX VrefLevel [Byte0]: 72
8744 08:14:06.971446 [Byte1]: 72
8745 08:14:06.975766
8746 08:14:06.976361 Set Vref, RX VrefLevel [Byte0]: 73
8747 08:14:06.978754 [Byte1]: 73
8748 08:14:06.983882
8749 08:14:06.984446 Set Vref, RX VrefLevel [Byte0]: 74
8750 08:14:06.986944 [Byte1]: 74
8751 08:14:06.991311
8752 08:14:06.991870 Set Vref, RX VrefLevel [Byte0]: 75
8753 08:14:06.994435 [Byte1]: 75
8754 08:14:06.998500
8755 08:14:06.998965 Final RX Vref Byte 0 = 53 to rank0
8756 08:14:07.001541 Final RX Vref Byte 1 = 60 to rank0
8757 08:14:07.004857 Final RX Vref Byte 0 = 53 to rank1
8758 08:14:07.008671 Final RX Vref Byte 1 = 60 to rank1==
8759 08:14:07.011556 Dram Type= 6, Freq= 0, CH_1, rank 0
8760 08:14:07.018705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8761 08:14:07.019234 ==
8762 08:14:07.019576 DQS Delay:
8763 08:14:07.021887 DQS0 = 0, DQS1 = 0
8764 08:14:07.022404 DQM Delay:
8765 08:14:07.022742 DQM0 = 135, DQM1 = 129
8766 08:14:07.024936 DQ Delay:
8767 08:14:07.028127 DQ0 =142, DQ1 =128, DQ2 =126, DQ3 =132
8768 08:14:07.031594 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8769 08:14:07.035309 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
8770 08:14:07.038088 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =138
8771 08:14:07.038606
8772 08:14:07.038943
8773 08:14:07.039444
8774 08:14:07.041727 [DramC_TX_OE_Calibration] TA2
8775 08:14:07.045100 Original DQ_B0 (3 6) =30, OEN = 27
8776 08:14:07.048354 Original DQ_B1 (3 6) =30, OEN = 27
8777 08:14:07.050999 24, 0x0, End_B0=24 End_B1=24
8778 08:14:07.054676 25, 0x0, End_B0=25 End_B1=25
8779 08:14:07.055202 26, 0x0, End_B0=26 End_B1=26
8780 08:14:07.057983 27, 0x0, End_B0=27 End_B1=27
8781 08:14:07.061241 28, 0x0, End_B0=28 End_B1=28
8782 08:14:07.064798 29, 0x0, End_B0=29 End_B1=29
8783 08:14:07.065321 30, 0x0, End_B0=30 End_B1=30
8784 08:14:07.067812 31, 0x4141, End_B0=30 End_B1=30
8785 08:14:07.071510 Byte0 end_step=30 best_step=27
8786 08:14:07.074820 Byte1 end_step=30 best_step=27
8787 08:14:07.077454 Byte0 TX OE(2T, 0.5T) = (3, 3)
8788 08:14:07.081031 Byte1 TX OE(2T, 0.5T) = (3, 3)
8789 08:14:07.081704
8790 08:14:07.082063
8791 08:14:07.087531 [DQSOSCAuto] RK0, (LSB)MR18= 0x140a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
8792 08:14:07.090867 CH1 RK0: MR19=303, MR18=140A
8793 08:14:07.097708 CH1_RK0: MR19=0x303, MR18=0x140A, DQSOSC=399, MR23=63, INC=23, DEC=15
8794 08:14:07.098226
8795 08:14:07.100861 ----->DramcWriteLeveling(PI) begin...
8796 08:14:07.101241 ==
8797 08:14:07.104068 Dram Type= 6, Freq= 0, CH_1, rank 1
8798 08:14:07.107657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8799 08:14:07.108180 ==
8800 08:14:07.110883 Write leveling (Byte 0): 24 => 24
8801 08:14:07.113797 Write leveling (Byte 1): 27 => 27
8802 08:14:07.117580 DramcWriteLeveling(PI) end<-----
8803 08:14:07.118106
8804 08:14:07.118446 ==
8805 08:14:07.120784 Dram Type= 6, Freq= 0, CH_1, rank 1
8806 08:14:07.124365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8807 08:14:07.127786 ==
8808 08:14:07.128303 [Gating] SW mode calibration
8809 08:14:07.133743 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8810 08:14:07.140300 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8811 08:14:07.143913 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 08:14:07.150326 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 08:14:07.153551 1 4 8 | B1->B0 | 2727 2323 | 1 0 | (1 1) (0 0)
8814 08:14:07.156928 1 4 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8815 08:14:07.163392 1 4 16 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
8816 08:14:07.166910 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8817 08:14:07.170228 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 08:14:07.176787 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8819 08:14:07.180368 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8820 08:14:07.183197 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8821 08:14:07.189708 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8822 08:14:07.193398 1 5 12 | B1->B0 | 2c2c 3434 | 0 1 | (0 1) (1 0)
8823 08:14:07.196305 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
8824 08:14:07.203216 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 08:14:07.206047 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 08:14:07.210260 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 08:14:07.215711 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 08:14:07.219433 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 08:14:07.225858 1 6 8 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
8830 08:14:07.228984 1 6 12 | B1->B0 | 4646 2828 | 0 0 | (0 0) (0 0)
8831 08:14:07.232142 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 08:14:07.239169 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 08:14:07.242265 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 08:14:07.245415 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 08:14:07.252283 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 08:14:07.256115 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 08:14:07.258647 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8838 08:14:07.262339 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8839 08:14:07.269180 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8840 08:14:07.271942 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 08:14:07.278410 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 08:14:07.281577 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 08:14:07.285656 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 08:14:07.291636 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 08:14:07.294500 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 08:14:07.298076 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 08:14:07.304721 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 08:14:07.308094 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 08:14:07.311188 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 08:14:07.317652 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 08:14:07.321174 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 08:14:07.325003 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 08:14:07.331236 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8854 08:14:07.334626 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8855 08:14:07.337705 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8856 08:14:07.341014 Total UI for P1: 0, mck2ui 16
8857 08:14:07.344425 best dqsien dly found for B1: ( 1, 9, 10)
8858 08:14:07.350578 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8859 08:14:07.351130 Total UI for P1: 0, mck2ui 16
8860 08:14:07.357403 best dqsien dly found for B0: ( 1, 9, 12)
8861 08:14:07.360755 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8862 08:14:07.363851 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8863 08:14:07.364407
8864 08:14:07.367182 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8865 08:14:07.370402 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8866 08:14:07.373514 [Gating] SW calibration Done
8867 08:14:07.374073 ==
8868 08:14:07.377103 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 08:14:07.380091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 08:14:07.380585 ==
8871 08:14:07.383363 RX Vref Scan: 0
8872 08:14:07.383925
8873 08:14:07.386990 RX Vref 0 -> 0, step: 1
8874 08:14:07.387639
8875 08:14:07.388184 RX Delay 0 -> 252, step: 8
8876 08:14:07.393543 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8877 08:14:07.396737 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8878 08:14:07.399993 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8879 08:14:07.403230 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8880 08:14:07.406415 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8881 08:14:07.412733 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8882 08:14:07.416256 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8883 08:14:07.419620 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8884 08:14:07.423139 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8885 08:14:07.426229 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8886 08:14:07.432582 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8887 08:14:07.436369 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8888 08:14:07.439433 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8889 08:14:07.442677 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8890 08:14:07.449043 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8891 08:14:07.452623 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8892 08:14:07.453088 ==
8893 08:14:07.455869 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 08:14:07.459016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 08:14:07.459486 ==
8896 08:14:07.462611 DQS Delay:
8897 08:14:07.463076 DQS0 = 0, DQS1 = 0
8898 08:14:07.463444 DQM Delay:
8899 08:14:07.465666 DQM0 = 136, DQM1 = 129
8900 08:14:07.466132 DQ Delay:
8901 08:14:07.469447 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8902 08:14:07.472013 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8903 08:14:07.475691 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8904 08:14:07.481988 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8905 08:14:07.482454
8906 08:14:07.482822
8907 08:14:07.483165 ==
8908 08:14:07.485422 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 08:14:07.488699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 08:14:07.489123 ==
8911 08:14:07.489503
8912 08:14:07.489820
8913 08:14:07.491786 TX Vref Scan disable
8914 08:14:07.492203 == TX Byte 0 ==
8915 08:14:07.498746 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8916 08:14:07.502158 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8917 08:14:07.502584 == TX Byte 1 ==
8918 08:14:07.508403 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8919 08:14:07.511733 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8920 08:14:07.512157 ==
8921 08:14:07.514881 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 08:14:07.518503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 08:14:07.518929 ==
8924 08:14:07.533792
8925 08:14:07.537628 TX Vref early break, caculate TX vref
8926 08:14:07.540432 TX Vref=16, minBit 0, minWin=23, winSum=383
8927 08:14:07.543709 TX Vref=18, minBit 0, minWin=23, winSum=390
8928 08:14:07.546836 TX Vref=20, minBit 0, minWin=23, winSum=397
8929 08:14:07.550061 TX Vref=22, minBit 0, minWin=24, winSum=407
8930 08:14:07.553047 TX Vref=24, minBit 0, minWin=25, winSum=416
8931 08:14:07.560290 TX Vref=26, minBit 0, minWin=25, winSum=425
8932 08:14:07.563075 TX Vref=28, minBit 0, minWin=25, winSum=425
8933 08:14:07.566248 TX Vref=30, minBit 0, minWin=25, winSum=422
8934 08:14:07.569834 TX Vref=32, minBit 0, minWin=24, winSum=408
8935 08:14:07.573164 TX Vref=34, minBit 0, minWin=24, winSum=403
8936 08:14:07.579493 TX Vref=36, minBit 0, minWin=23, winSum=390
8937 08:14:07.582811 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26
8938 08:14:07.583372
8939 08:14:07.586023 Final TX Range 0 Vref 26
8940 08:14:07.586489
8941 08:14:07.586857 ==
8942 08:14:07.589846 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 08:14:07.592388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 08:14:07.596443 ==
8945 08:14:07.597003
8946 08:14:07.597420
8947 08:14:07.597777 TX Vref Scan disable
8948 08:14:07.603136 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8949 08:14:07.603699 == TX Byte 0 ==
8950 08:14:07.606154 u2DelayCellOfst[0]=18 cells (5 PI)
8951 08:14:07.609849 u2DelayCellOfst[1]=14 cells (4 PI)
8952 08:14:07.613130 u2DelayCellOfst[2]=0 cells (0 PI)
8953 08:14:07.615834 u2DelayCellOfst[3]=7 cells (2 PI)
8954 08:14:07.619480 u2DelayCellOfst[4]=7 cells (2 PI)
8955 08:14:07.623178 u2DelayCellOfst[5]=22 cells (6 PI)
8956 08:14:07.625751 u2DelayCellOfst[6]=22 cells (6 PI)
8957 08:14:07.629469 u2DelayCellOfst[7]=7 cells (2 PI)
8958 08:14:07.632723 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8959 08:14:07.635992 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8960 08:14:07.639382 == TX Byte 1 ==
8961 08:14:07.642289 u2DelayCellOfst[8]=0 cells (0 PI)
8962 08:14:07.645935 u2DelayCellOfst[9]=7 cells (2 PI)
8963 08:14:07.648978 u2DelayCellOfst[10]=14 cells (4 PI)
8964 08:14:07.652039 u2DelayCellOfst[11]=7 cells (2 PI)
8965 08:14:07.655914 u2DelayCellOfst[12]=18 cells (5 PI)
8966 08:14:07.658957 u2DelayCellOfst[13]=18 cells (5 PI)
8967 08:14:07.661879 u2DelayCellOfst[14]=18 cells (5 PI)
8968 08:14:07.665565 u2DelayCellOfst[15]=18 cells (5 PI)
8969 08:14:07.668477 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8970 08:14:07.672360 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8971 08:14:07.675329 DramC Write-DBI on
8972 08:14:07.675808 ==
8973 08:14:07.678356 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 08:14:07.681684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 08:14:07.682108 ==
8976 08:14:07.682447
8977 08:14:07.682821
8978 08:14:07.684750 TX Vref Scan disable
8979 08:14:07.685172 == TX Byte 0 ==
8980 08:14:07.691910 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8981 08:14:07.692335 == TX Byte 1 ==
8982 08:14:07.698214 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8983 08:14:07.698801 DramC Write-DBI off
8984 08:14:07.699446
8985 08:14:07.700038 [DATLAT]
8986 08:14:07.701134 Freq=1600, CH1 RK1
8987 08:14:07.701592
8988 08:14:07.704671 DATLAT Default: 0xf
8989 08:14:07.705095 0, 0xFFFF, sum = 0
8990 08:14:07.707800 1, 0xFFFF, sum = 0
8991 08:14:07.708227 2, 0xFFFF, sum = 0
8992 08:14:07.711507 3, 0xFFFF, sum = 0
8993 08:14:07.712039 4, 0xFFFF, sum = 0
8994 08:14:07.714393 5, 0xFFFF, sum = 0
8995 08:14:07.714821 6, 0xFFFF, sum = 0
8996 08:14:07.717917 7, 0xFFFF, sum = 0
8997 08:14:07.718347 8, 0xFFFF, sum = 0
8998 08:14:07.721233 9, 0xFFFF, sum = 0
8999 08:14:07.721795 10, 0xFFFF, sum = 0
9000 08:14:07.724760 11, 0xFFFF, sum = 0
9001 08:14:07.725641 12, 0xFFFF, sum = 0
9002 08:14:07.728151 13, 0xFFFF, sum = 0
9003 08:14:07.728584 14, 0x0, sum = 1
9004 08:14:07.731170 15, 0x0, sum = 2
9005 08:14:07.731698 16, 0x0, sum = 3
9006 08:14:07.734701 17, 0x0, sum = 4
9007 08:14:07.735267 best_step = 15
9008 08:14:07.735753
9009 08:14:07.736092 ==
9010 08:14:07.737809 Dram Type= 6, Freq= 0, CH_1, rank 1
9011 08:14:07.744352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9012 08:14:07.744776 ==
9013 08:14:07.745115 RX Vref Scan: 0
9014 08:14:07.745479
9015 08:14:07.747342 RX Vref 0 -> 0, step: 1
9016 08:14:07.747977
9017 08:14:07.750858 RX Delay 11 -> 252, step: 4
9018 08:14:07.753978 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9019 08:14:07.757578 iDelay=203, Bit 1, Center 126 (75 ~ 178) 104
9020 08:14:07.764271 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9021 08:14:07.767157 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9022 08:14:07.770639 iDelay=203, Bit 4, Center 132 (79 ~ 186) 108
9023 08:14:07.773478 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
9024 08:14:07.777134 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9025 08:14:07.783733 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9026 08:14:07.787216 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9027 08:14:07.790289 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9028 08:14:07.793600 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9029 08:14:07.796609 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9030 08:14:07.803579 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9031 08:14:07.807159 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9032 08:14:07.810097 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9033 08:14:07.813369 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9034 08:14:07.816745 ==
9035 08:14:07.817166 Dram Type= 6, Freq= 0, CH_1, rank 1
9036 08:14:07.822926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9037 08:14:07.823406 ==
9038 08:14:07.823747 DQS Delay:
9039 08:14:07.826523 DQS0 = 0, DQS1 = 0
9040 08:14:07.827050 DQM Delay:
9041 08:14:07.829929 DQM0 = 133, DQM1 = 127
9042 08:14:07.830350 DQ Delay:
9043 08:14:07.833087 DQ0 =138, DQ1 =126, DQ2 =122, DQ3 =130
9044 08:14:07.836385 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9045 08:14:07.840076 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =118
9046 08:14:07.843058 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9047 08:14:07.843483
9048 08:14:07.843897
9049 08:14:07.844217
9050 08:14:07.846004 [DramC_TX_OE_Calibration] TA2
9051 08:14:07.849577 Original DQ_B0 (3 6) =30, OEN = 27
9052 08:14:07.852665 Original DQ_B1 (3 6) =30, OEN = 27
9053 08:14:07.856279 24, 0x0, End_B0=24 End_B1=24
9054 08:14:07.859892 25, 0x0, End_B0=25 End_B1=25
9055 08:14:07.860418 26, 0x0, End_B0=26 End_B1=26
9056 08:14:07.862636 27, 0x0, End_B0=27 End_B1=27
9057 08:14:07.866268 28, 0x0, End_B0=28 End_B1=28
9058 08:14:07.869206 29, 0x0, End_B0=29 End_B1=29
9059 08:14:07.872709 30, 0x0, End_B0=30 End_B1=30
9060 08:14:07.873228 31, 0x5151, End_B0=30 End_B1=30
9061 08:14:07.876114 Byte0 end_step=30 best_step=27
9062 08:14:07.879029 Byte1 end_step=30 best_step=27
9063 08:14:07.882393 Byte0 TX OE(2T, 0.5T) = (3, 3)
9064 08:14:07.886145 Byte1 TX OE(2T, 0.5T) = (3, 3)
9065 08:14:07.886670
9066 08:14:07.887008
9067 08:14:07.892180 [DQSOSCAuto] RK1, (LSB)MR18= 0x603, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
9068 08:14:07.895242 CH1 RK1: MR19=303, MR18=603
9069 08:14:07.902004 CH1_RK1: MR19=0x303, MR18=0x603, DQSOSC=406, MR23=63, INC=22, DEC=14
9070 08:14:07.905476 [RxdqsGatingPostProcess] freq 1600
9071 08:14:07.911702 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9072 08:14:07.914852 best DQS0 dly(2T, 0.5T) = (1, 1)
9073 08:14:07.915400 best DQS1 dly(2T, 0.5T) = (1, 1)
9074 08:14:07.918269 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9075 08:14:07.921732 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9076 08:14:07.925039 best DQS0 dly(2T, 0.5T) = (1, 1)
9077 08:14:07.928336 best DQS1 dly(2T, 0.5T) = (1, 1)
9078 08:14:07.931710 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9079 08:14:07.934957 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9080 08:14:07.938023 Pre-setting of DQS Precalculation
9081 08:14:07.945254 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9082 08:14:07.951182 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9083 08:14:07.958021 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9084 08:14:07.958491
9085 08:14:07.958860
9086 08:14:07.961263 [Calibration Summary] 3200 Mbps
9087 08:14:07.961851 CH 0, Rank 0
9088 08:14:07.964046 SW Impedance : PASS
9089 08:14:07.967520 DUTY Scan : NO K
9090 08:14:07.968077 ZQ Calibration : PASS
9091 08:14:07.971244 Jitter Meter : NO K
9092 08:14:07.973803 CBT Training : PASS
9093 08:14:07.974270 Write leveling : PASS
9094 08:14:07.977462 RX DQS gating : PASS
9095 08:14:07.980789 RX DQ/DQS(RDDQC) : PASS
9096 08:14:07.981254 TX DQ/DQS : PASS
9097 08:14:07.984117 RX DATLAT : PASS
9098 08:14:07.987626 RX DQ/DQS(Engine): PASS
9099 08:14:07.988180 TX OE : PASS
9100 08:14:07.990404 All Pass.
9101 08:14:07.990953
9102 08:14:07.991327 CH 0, Rank 1
9103 08:14:07.993704 SW Impedance : PASS
9104 08:14:07.994173 DUTY Scan : NO K
9105 08:14:07.997241 ZQ Calibration : PASS
9106 08:14:08.000870 Jitter Meter : NO K
9107 08:14:08.001474 CBT Training : PASS
9108 08:14:08.003873 Write leveling : PASS
9109 08:14:08.007406 RX DQS gating : PASS
9110 08:14:08.007959 RX DQ/DQS(RDDQC) : PASS
9111 08:14:08.009844 TX DQ/DQS : PASS
9112 08:14:08.013417 RX DATLAT : PASS
9113 08:14:08.013975 RX DQ/DQS(Engine): PASS
9114 08:14:08.016716 TX OE : PASS
9115 08:14:08.017183 All Pass.
9116 08:14:08.017757
9117 08:14:08.020003 CH 1, Rank 0
9118 08:14:08.020560 SW Impedance : PASS
9119 08:14:08.023083 DUTY Scan : NO K
9120 08:14:08.026555 ZQ Calibration : PASS
9121 08:14:08.027108 Jitter Meter : NO K
9122 08:14:08.030126 CBT Training : PASS
9123 08:14:08.032980 Write leveling : PASS
9124 08:14:08.033502 RX DQS gating : PASS
9125 08:14:08.036490 RX DQ/DQS(RDDQC) : PASS
9126 08:14:08.037051 TX DQ/DQS : PASS
9127 08:14:08.039814 RX DATLAT : PASS
9128 08:14:08.043275 RX DQ/DQS(Engine): PASS
9129 08:14:08.043849 TX OE : PASS
9130 08:14:08.046126 All Pass.
9131 08:14:08.046606
9132 08:14:08.046977 CH 1, Rank 1
9133 08:14:08.049683 SW Impedance : PASS
9134 08:14:08.050414 DUTY Scan : NO K
9135 08:14:08.053153 ZQ Calibration : PASS
9136 08:14:08.056057 Jitter Meter : NO K
9137 08:14:08.056530 CBT Training : PASS
9138 08:14:08.059566 Write leveling : PASS
9139 08:14:08.062838 RX DQS gating : PASS
9140 08:14:08.063307 RX DQ/DQS(RDDQC) : PASS
9141 08:14:08.065918 TX DQ/DQS : PASS
9142 08:14:08.069510 RX DATLAT : PASS
9143 08:14:08.070083 RX DQ/DQS(Engine): PASS
9144 08:14:08.072859 TX OE : PASS
9145 08:14:08.073468 All Pass.
9146 08:14:08.073850
9147 08:14:08.075831 DramC Write-DBI on
9148 08:14:08.079419 PER_BANK_REFRESH: Hybrid Mode
9149 08:14:08.079984 TX_TRACKING: ON
9150 08:14:08.088991 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9151 08:14:08.096140 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9152 08:14:08.106130 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9153 08:14:08.108981 [FAST_K] Save calibration result to emmc
9154 08:14:08.109576 sync common calibartion params.
9155 08:14:08.112467 sync cbt_mode0:1, 1:1
9156 08:14:08.115583 dram_init: ddr_geometry: 2
9157 08:14:08.118344 dram_init: ddr_geometry: 2
9158 08:14:08.118809 dram_init: ddr_geometry: 2
9159 08:14:08.121925 0:dram_rank_size:100000000
9160 08:14:08.124870 1:dram_rank_size:100000000
9161 08:14:08.128799 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9162 08:14:08.132065 DFS_SHUFFLE_HW_MODE: ON
9163 08:14:08.135163 dramc_set_vcore_voltage set vcore to 725000
9164 08:14:08.138501 Read voltage for 1600, 0
9165 08:14:08.138972 Vio18 = 0
9166 08:14:08.141953 Vcore = 725000
9167 08:14:08.142529 Vdram = 0
9168 08:14:08.142908 Vddq = 0
9169 08:14:08.143257 Vmddr = 0
9170 08:14:08.145378 switch to 3200 Mbps bootup
9171 08:14:08.148256 [DramcRunTimeConfig]
9172 08:14:08.148724 PHYPLL
9173 08:14:08.151591 DPM_CONTROL_AFTERK: ON
9174 08:14:08.152056 PER_BANK_REFRESH: ON
9175 08:14:08.154597 REFRESH_OVERHEAD_REDUCTION: ON
9176 08:14:08.157818 CMD_PICG_NEW_MODE: OFF
9177 08:14:08.158329 XRTWTW_NEW_MODE: ON
9178 08:14:08.161293 XRTRTR_NEW_MODE: ON
9179 08:14:08.161892 TX_TRACKING: ON
9180 08:14:08.164632 RDSEL_TRACKING: OFF
9181 08:14:08.167991 DQS Precalculation for DVFS: ON
9182 08:14:08.168600 RX_TRACKING: OFF
9183 08:14:08.171368 HW_GATING DBG: ON
9184 08:14:08.171931 ZQCS_ENABLE_LP4: ON
9185 08:14:08.174579 RX_PICG_NEW_MODE: ON
9186 08:14:08.175044 TX_PICG_NEW_MODE: ON
9187 08:14:08.177729 ENABLE_RX_DCM_DPHY: ON
9188 08:14:08.181034 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9189 08:14:08.185087 DUMMY_READ_FOR_TRACKING: OFF
9190 08:14:08.185732 !!! SPM_CONTROL_AFTERK: OFF
9191 08:14:08.188350 !!! SPM could not control APHY
9192 08:14:08.191049 IMPEDANCE_TRACKING: ON
9193 08:14:08.191611 TEMP_SENSOR: ON
9194 08:14:08.194524 HW_SAVE_FOR_SR: OFF
9195 08:14:08.197896 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9196 08:14:08.200976 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9197 08:14:08.204267 Read ODT Tracking: ON
9198 08:14:08.204829 Refresh Rate DeBounce: ON
9199 08:14:08.207659 DFS_NO_QUEUE_FLUSH: ON
9200 08:14:08.210952 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9201 08:14:08.214260 ENABLE_DFS_RUNTIME_MRW: OFF
9202 08:14:08.214727 DDR_RESERVE_NEW_MODE: ON
9203 08:14:08.217076 MR_CBT_SWITCH_FREQ: ON
9204 08:14:08.220982 =========================
9205 08:14:08.238428 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9206 08:14:08.241746 dram_init: ddr_geometry: 2
9207 08:14:08.259755 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9208 08:14:08.263205 dram_init: dram init end (result: 0)
9209 08:14:08.269884 DRAM-K: Full calibration passed in 24667 msecs
9210 08:14:08.273371 MRC: failed to locate region type 0.
9211 08:14:08.273942 DRAM rank0 size:0x100000000,
9212 08:14:08.276149 DRAM rank1 size=0x100000000
9213 08:14:08.285984 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9214 08:14:08.292502 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9215 08:14:08.299507 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9216 08:14:08.309132 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9217 08:14:08.309755 DRAM rank0 size:0x100000000,
9218 08:14:08.312304 DRAM rank1 size=0x100000000
9219 08:14:08.312775 CBMEM:
9220 08:14:08.315603 IMD: root @ 0xfffff000 254 entries.
9221 08:14:08.318545 IMD: root @ 0xffffec00 62 entries.
9222 08:14:08.325476 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9223 08:14:08.328739 WARNING: RO_VPD is uninitialized or empty.
9224 08:14:08.332198 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9225 08:14:08.339678 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9226 08:14:08.352309 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9227 08:14:08.364086 BS: romstage times (exec / console): total (unknown) / 24155 ms
9228 08:14:08.364658
9229 08:14:08.365029
9230 08:14:08.373751 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9231 08:14:08.377421 ARM64: Exception handlers installed.
9232 08:14:08.380444 ARM64: Testing exception
9233 08:14:08.383853 ARM64: Done test exception
9234 08:14:08.384317 Enumerating buses...
9235 08:14:08.387380 Show all devs... Before device enumeration.
9236 08:14:08.390407 Root Device: enabled 1
9237 08:14:08.393910 CPU_CLUSTER: 0: enabled 1
9238 08:14:08.394375 CPU: 00: enabled 1
9239 08:14:08.397225 Compare with tree...
9240 08:14:08.397735 Root Device: enabled 1
9241 08:14:08.400193 CPU_CLUSTER: 0: enabled 1
9242 08:14:08.403618 CPU: 00: enabled 1
9243 08:14:08.404205 Root Device scanning...
9244 08:14:08.407187 scan_static_bus for Root Device
9245 08:14:08.410374 CPU_CLUSTER: 0 enabled
9246 08:14:08.413508 scan_static_bus for Root Device done
9247 08:14:08.416581 scan_bus: bus Root Device finished in 8 msecs
9248 08:14:08.417049 done
9249 08:14:08.423659 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9250 08:14:08.426586 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9251 08:14:08.433578 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9252 08:14:08.439551 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9253 08:14:08.440105 Allocating resources...
9254 08:14:08.442818 Reading resources...
9255 08:14:08.446184 Root Device read_resources bus 0 link: 0
9256 08:14:08.449962 DRAM rank0 size:0x100000000,
9257 08:14:08.450529 DRAM rank1 size=0x100000000
9258 08:14:08.456207 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9259 08:14:08.456764 CPU: 00 missing read_resources
9260 08:14:08.462573 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9261 08:14:08.465923 Root Device read_resources bus 0 link: 0 done
9262 08:14:08.469046 Done reading resources.
9263 08:14:08.472593 Show resources in subtree (Root Device)...After reading.
9264 08:14:08.475733 Root Device child on link 0 CPU_CLUSTER: 0
9265 08:14:08.478999 CPU_CLUSTER: 0 child on link 0 CPU: 00
9266 08:14:08.489232 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9267 08:14:08.489844 CPU: 00
9268 08:14:08.495338 Root Device assign_resources, bus 0 link: 0
9269 08:14:08.498911 CPU_CLUSTER: 0 missing set_resources
9270 08:14:08.501990 Root Device assign_resources, bus 0 link: 0 done
9271 08:14:08.505416 Done setting resources.
9272 08:14:08.508917 Show resources in subtree (Root Device)...After assigning values.
9273 08:14:08.515138 Root Device child on link 0 CPU_CLUSTER: 0
9274 08:14:08.518424 CPU_CLUSTER: 0 child on link 0 CPU: 00
9275 08:14:08.525063 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9276 08:14:08.528574 CPU: 00
9277 08:14:08.529144 Done allocating resources.
9278 08:14:08.534797 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9279 08:14:08.537952 Enabling resources...
9280 08:14:08.538524 done.
9281 08:14:08.541372 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9282 08:14:08.544920 Initializing devices...
9283 08:14:08.545542 Root Device init
9284 08:14:08.548241 init hardware done!
9285 08:14:08.551546 0x00000018: ctrlr->caps
9286 08:14:08.552141 52.000 MHz: ctrlr->f_max
9287 08:14:08.554382 0.400 MHz: ctrlr->f_min
9288 08:14:08.557897 0x40ff8080: ctrlr->voltages
9289 08:14:08.558382 sclk: 390625
9290 08:14:08.558759 Bus Width = 1
9291 08:14:08.560739 sclk: 390625
9292 08:14:08.561210 Bus Width = 1
9293 08:14:08.564188 Early init status = 3
9294 08:14:08.567654 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9295 08:14:08.571158 in-header: 03 fc 00 00 01 00 00 00
9296 08:14:08.574769 in-data: 00
9297 08:14:08.577828 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9298 08:14:08.582226 in-header: 03 fd 00 00 00 00 00 00
9299 08:14:08.585851 in-data:
9300 08:14:08.588858 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9301 08:14:08.592461 in-header: 03 fc 00 00 01 00 00 00
9302 08:14:08.595801 in-data: 00
9303 08:14:08.599362 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9304 08:14:08.603661 in-header: 03 fd 00 00 00 00 00 00
9305 08:14:08.607742 in-data:
9306 08:14:08.610452 [SSUSB] Setting up USB HOST controller...
9307 08:14:08.613883 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9308 08:14:08.617231 [SSUSB] phy power-on done.
9309 08:14:08.620419 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9310 08:14:08.627108 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9311 08:14:08.629992 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9312 08:14:08.636829 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9313 08:14:08.643209 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9314 08:14:08.650707 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9315 08:14:08.656555 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9316 08:14:08.663517 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9317 08:14:08.667020 SPM: binary array size = 0x9dc
9318 08:14:08.669766 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9319 08:14:08.676602 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9320 08:14:08.683406 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9321 08:14:08.690036 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9322 08:14:08.693095 configure_display: Starting display init
9323 08:14:08.726951 anx7625_power_on_init: Init interface.
9324 08:14:08.730439 anx7625_disable_pd_protocol: Disabled PD feature.
9325 08:14:08.734167 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9326 08:14:08.761359 anx7625_start_dp_work: Secure OCM version=00
9327 08:14:08.765021 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9328 08:14:08.780036 sp_tx_get_edid_block: EDID Block = 1
9329 08:14:08.882338 Extracted contents:
9330 08:14:08.886282 header: 00 ff ff ff ff ff ff 00
9331 08:14:08.888890 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9332 08:14:08.892333 version: 01 04
9333 08:14:08.895899 basic params: 95 1f 11 78 0a
9334 08:14:08.898679 chroma info: 76 90 94 55 54 90 27 21 50 54
9335 08:14:08.901755 established: 00 00 00
9336 08:14:08.908606 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9337 08:14:08.915771 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9338 08:14:08.918378 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9339 08:14:08.925168 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9340 08:14:08.931639 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9341 08:14:08.934782 extensions: 00
9342 08:14:08.935251 checksum: fb
9343 08:14:08.935691
9344 08:14:08.941527 Manufacturer: IVO Model 57d Serial Number 0
9345 08:14:08.942093 Made week 0 of 2020
9346 08:14:08.944666 EDID version: 1.4
9347 08:14:08.945134 Digital display
9348 08:14:08.947974 6 bits per primary color channel
9349 08:14:08.951792 DisplayPort interface
9350 08:14:08.952320 Maximum image size: 31 cm x 17 cm
9351 08:14:08.954943 Gamma: 220%
9352 08:14:08.955411 Check DPMS levels
9353 08:14:08.961069 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9354 08:14:08.965079 First detailed timing is preferred timing
9355 08:14:08.965550 Established timings supported:
9356 08:14:08.968420 Standard timings supported:
9357 08:14:08.971103 Detailed timings
9358 08:14:08.974115 Hex of detail: 383680a07038204018303c0035ae10000019
9359 08:14:08.980695 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9360 08:14:08.984668 0780 0798 07c8 0820 hborder 0
9361 08:14:08.988251 0438 043b 0447 0458 vborder 0
9362 08:14:08.991321 -hsync -vsync
9363 08:14:08.991854 Did detailed timing
9364 08:14:08.997808 Hex of detail: 000000000000000000000000000000000000
9365 08:14:09.001257 Manufacturer-specified data, tag 0
9366 08:14:09.003884 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9367 08:14:09.007179 ASCII string: InfoVision
9368 08:14:09.010965 Hex of detail: 000000fe00523134304e574635205248200a
9369 08:14:09.014206 ASCII string: R140NWF5 RH
9370 08:14:09.014778 Checksum
9371 08:14:09.017402 Checksum: 0xfb (valid)
9372 08:14:09.020748 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9373 08:14:09.024257 DSI data_rate: 832800000 bps
9374 08:14:09.030800 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9375 08:14:09.033686 anx7625_parse_edid: pixelclock(138800).
9376 08:14:09.037017 hactive(1920), hsync(48), hfp(24), hbp(88)
9377 08:14:09.040479 vactive(1080), vsync(12), vfp(3), vbp(17)
9378 08:14:09.043523 anx7625_dsi_config: config dsi.
9379 08:14:09.050346 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9380 08:14:09.064422 anx7625_dsi_config: success to config DSI
9381 08:14:09.068371 anx7625_dp_start: MIPI phy setup OK.
9382 08:14:09.071155 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9383 08:14:09.074289 mtk_ddp_mode_set invalid vrefresh 60
9384 08:14:09.077446 main_disp_path_setup
9385 08:14:09.078002 ovl_layer_smi_id_en
9386 08:14:09.080985 ovl_layer_smi_id_en
9387 08:14:09.081499 ccorr_config
9388 08:14:09.081872 aal_config
9389 08:14:09.083743 gamma_config
9390 08:14:09.084239 postmask_config
9391 08:14:09.087360 dither_config
9392 08:14:09.090493 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9393 08:14:09.097405 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9394 08:14:09.100855 Root Device init finished in 551 msecs
9395 08:14:09.103814 CPU_CLUSTER: 0 init
9396 08:14:09.110514 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9397 08:14:09.116770 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9398 08:14:09.117414 APU_MBOX 0x190000b0 = 0x10001
9399 08:14:09.120272 APU_MBOX 0x190001b0 = 0x10001
9400 08:14:09.123356 APU_MBOX 0x190005b0 = 0x10001
9401 08:14:09.127387 APU_MBOX 0x190006b0 = 0x10001
9402 08:14:09.133567 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9403 08:14:09.143287 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9404 08:14:09.155519 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9405 08:14:09.162982 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9406 08:14:09.174069 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9407 08:14:09.183038 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9408 08:14:09.186599 CPU_CLUSTER: 0 init finished in 81 msecs
9409 08:14:09.189439 Devices initialized
9410 08:14:09.193071 Show all devs... After init.
9411 08:14:09.193695 Root Device: enabled 1
9412 08:14:09.196003 CPU_CLUSTER: 0: enabled 1
9413 08:14:09.199757 CPU: 00: enabled 1
9414 08:14:09.202667 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9415 08:14:09.206320 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9416 08:14:09.209457 ELOG: NV offset 0x57f000 size 0x1000
9417 08:14:09.216216 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9418 08:14:09.223379 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9419 08:14:09.226153 ELOG: Event(17) added with size 13 at 2024-04-26 08:14:08 UTC
9420 08:14:09.233003 out: cmd=0x121: 03 db 21 01 00 00 00 00
9421 08:14:09.235910 in-header: 03 a3 00 00 2c 00 00 00
9422 08:14:09.245702 in-data: bb 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9423 08:14:09.252472 ELOG: Event(A1) added with size 10 at 2024-04-26 08:14:08 UTC
9424 08:14:09.258883 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9425 08:14:09.265724 ELOG: Event(A0) added with size 9 at 2024-04-26 08:14:08 UTC
9426 08:14:09.268702 elog_add_boot_reason: Logged dev mode boot
9427 08:14:09.275454 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9428 08:14:09.276032 Finalize devices...
9429 08:14:09.278750 Devices finalized
9430 08:14:09.282066 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9431 08:14:09.285657 Writing coreboot table at 0xffe64000
9432 08:14:09.288688 0. 000000000010a000-0000000000113fff: RAMSTAGE
9433 08:14:09.295419 1. 0000000040000000-00000000400fffff: RAM
9434 08:14:09.298283 2. 0000000040100000-000000004032afff: RAMSTAGE
9435 08:14:09.301899 3. 000000004032b000-00000000545fffff: RAM
9436 08:14:09.305246 4. 0000000054600000-000000005465ffff: BL31
9437 08:14:09.308372 5. 0000000054660000-00000000ffe63fff: RAM
9438 08:14:09.315070 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9439 08:14:09.317768 7. 0000000100000000-000000023fffffff: RAM
9440 08:14:09.321167 Passing 5 GPIOs to payload:
9441 08:14:09.324908 NAME | PORT | POLARITY | VALUE
9442 08:14:09.331488 EC in RW | 0x000000aa | low | undefined
9443 08:14:09.334961 EC interrupt | 0x00000005 | low | undefined
9444 08:14:09.341317 TPM interrupt | 0x000000ab | high | undefined
9445 08:14:09.344607 SD card detect | 0x00000011 | high | undefined
9446 08:14:09.347330 speaker enable | 0x00000093 | high | undefined
9447 08:14:09.351093 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9448 08:14:09.354545 in-header: 03 f9 00 00 02 00 00 00
9449 08:14:09.358142 in-data: 02 00
9450 08:14:09.361046 ADC[4]: Raw value=900813 ID=7
9451 08:14:09.364239 ADC[3]: Raw value=212912 ID=1
9452 08:14:09.364709 RAM Code: 0x71
9453 08:14:09.368367 ADC[6]: Raw value=75036 ID=0
9454 08:14:09.371015 ADC[5]: Raw value=213652 ID=1
9455 08:14:09.371497 SKU Code: 0x1
9456 08:14:09.377911 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum fee0
9457 08:14:09.378492 coreboot table: 964 bytes.
9458 08:14:09.381015 IMD ROOT 0. 0xfffff000 0x00001000
9459 08:14:09.383923 IMD SMALL 1. 0xffffe000 0x00001000
9460 08:14:09.387462 RO MCACHE 2. 0xffffc000 0x00001104
9461 08:14:09.391062 CONSOLE 3. 0xfff7c000 0x00080000
9462 08:14:09.393982 FMAP 4. 0xfff7b000 0x00000452
9463 08:14:09.397498 TIME STAMP 5. 0xfff7a000 0x00000910
9464 08:14:09.400565 VBOOT WORK 6. 0xfff66000 0x00014000
9465 08:14:09.403895 RAMOOPS 7. 0xffe66000 0x00100000
9466 08:14:09.407545 COREBOOT 8. 0xffe64000 0x00002000
9467 08:14:09.410455 IMD small region:
9468 08:14:09.413918 IMD ROOT 0. 0xffffec00 0x00000400
9469 08:14:09.417650 VPD 1. 0xffffeb80 0x0000006c
9470 08:14:09.420199 MMC STATUS 2. 0xffffeb60 0x00000004
9471 08:14:09.426883 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9472 08:14:09.427460 Probing TPM: done!
9473 08:14:09.433751 Connected to device vid:did:rid of 1ae0:0028:00
9474 08:14:09.440453 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9475 08:14:09.443653 Initialized TPM device CR50 revision 0
9476 08:14:09.447598 Checking cr50 for pending updates
9477 08:14:09.453093 Reading cr50 TPM mode
9478 08:14:09.461278 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9479 08:14:09.468181 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9480 08:14:09.508227 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9481 08:14:09.511498 Checking segment from ROM address 0x40100000
9482 08:14:09.514953 Checking segment from ROM address 0x4010001c
9483 08:14:09.521671 Loading segment from ROM address 0x40100000
9484 08:14:09.522230 code (compression=0)
9485 08:14:09.531097 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9486 08:14:09.537999 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9487 08:14:09.538590 it's not compressed!
9488 08:14:09.544744 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9489 08:14:09.551571 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9490 08:14:09.568596 Loading segment from ROM address 0x4010001c
9491 08:14:09.569172 Entry Point 0x80000000
9492 08:14:09.571956 Loaded segments
9493 08:14:09.575558 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9494 08:14:09.582371 Jumping to boot code at 0x80000000(0xffe64000)
9495 08:14:09.588505 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9496 08:14:09.595186 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9497 08:14:09.603391 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9498 08:14:09.606188 Checking segment from ROM address 0x40100000
9499 08:14:09.610054 Checking segment from ROM address 0x4010001c
9500 08:14:09.616244 Loading segment from ROM address 0x40100000
9501 08:14:09.616802 code (compression=1)
9502 08:14:09.623003 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9503 08:14:09.632925 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9504 08:14:09.633538 using LZMA
9505 08:14:09.641244 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9506 08:14:09.647830 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9507 08:14:09.651679 Loading segment from ROM address 0x4010001c
9508 08:14:09.652248 Entry Point 0x54601000
9509 08:14:09.654750 Loaded segments
9510 08:14:09.657759 NOTICE: MT8192 bl31_setup
9511 08:14:09.664914 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9512 08:14:09.668830 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9513 08:14:09.671469 WARNING: region 0:
9514 08:14:09.675265 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9515 08:14:09.675828 WARNING: region 1:
9516 08:14:09.681239 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9517 08:14:09.684430 WARNING: region 2:
9518 08:14:09.688322 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9519 08:14:09.691385 WARNING: region 3:
9520 08:14:09.697814 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9521 08:14:09.698286 WARNING: region 4:
9522 08:14:09.704352 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9523 08:14:09.704922 WARNING: region 5:
9524 08:14:09.708050 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9525 08:14:09.710960 WARNING: region 6:
9526 08:14:09.714504 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9527 08:14:09.717420 WARNING: region 7:
9528 08:14:09.720657 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9529 08:14:09.727398 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9530 08:14:09.730977 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9531 08:14:09.737477 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9532 08:14:09.740971 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9533 08:14:09.744273 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9534 08:14:09.750496 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9535 08:14:09.754019 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9536 08:14:09.757122 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9537 08:14:09.764374 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9538 08:14:09.767447 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9539 08:14:09.774166 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9540 08:14:09.777164 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9541 08:14:09.780538 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9542 08:14:09.787070 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9543 08:14:09.790522 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9544 08:14:09.793786 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9545 08:14:09.800288 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9546 08:14:09.803813 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9547 08:14:09.810416 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9548 08:14:09.813381 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9549 08:14:09.816663 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9550 08:14:09.823629 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9551 08:14:09.827202 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9552 08:14:09.833465 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9553 08:14:09.836961 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9554 08:14:09.839973 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9555 08:14:09.846731 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9556 08:14:09.850145 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9557 08:14:09.856332 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9558 08:14:09.860371 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9559 08:14:09.866136 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9560 08:14:09.869791 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9561 08:14:09.873215 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9562 08:14:09.876299 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9563 08:14:09.883560 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9564 08:14:09.886304 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9565 08:14:09.889898 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9566 08:14:09.893238 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9567 08:14:09.899969 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9568 08:14:09.902875 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9569 08:14:09.906227 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9570 08:14:09.909438 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9571 08:14:09.916090 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9572 08:14:09.919121 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9573 08:14:09.922675 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9574 08:14:09.926436 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9575 08:14:09.932950 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9576 08:14:09.936346 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9577 08:14:09.939829 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9578 08:14:09.945596 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9579 08:14:09.948961 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9580 08:14:09.955754 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9581 08:14:09.958873 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9582 08:14:09.965840 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9583 08:14:09.968997 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9584 08:14:09.972281 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9585 08:14:09.979102 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9586 08:14:09.981944 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9587 08:14:09.988992 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9588 08:14:09.992306 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9589 08:14:09.998965 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9590 08:14:10.002375 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9591 08:14:10.009062 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9592 08:14:10.012151 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9593 08:14:10.015803 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9594 08:14:10.021886 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9595 08:14:10.025247 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9596 08:14:10.032097 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9597 08:14:10.034988 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9598 08:14:10.041860 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9599 08:14:10.045410 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9600 08:14:10.048340 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9601 08:14:10.054973 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9602 08:14:10.058614 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9603 08:14:10.065147 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9604 08:14:10.068331 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9605 08:14:10.074839 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9606 08:14:10.078482 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9607 08:14:10.084891 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9608 08:14:10.087919 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9609 08:14:10.095085 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9610 08:14:10.098522 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9611 08:14:10.101211 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9612 08:14:10.108521 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9613 08:14:10.111654 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9614 08:14:10.118139 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9615 08:14:10.121307 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9616 08:14:10.128063 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9617 08:14:10.131617 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9618 08:14:10.134635 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9619 08:14:10.141013 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9620 08:14:10.144171 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9621 08:14:10.150868 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9622 08:14:10.154232 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9623 08:14:10.160612 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9624 08:14:10.163878 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9625 08:14:10.170502 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9626 08:14:10.174078 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9627 08:14:10.177377 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9628 08:14:10.180547 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9629 08:14:10.187215 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9630 08:14:10.190639 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9631 08:14:10.193773 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9632 08:14:10.200284 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9633 08:14:10.203227 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9634 08:14:10.210227 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9635 08:14:10.213889 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9636 08:14:10.216681 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9637 08:14:10.223159 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9638 08:14:10.226784 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9639 08:14:10.233291 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9640 08:14:10.236760 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9641 08:14:10.240312 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9642 08:14:10.246496 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9643 08:14:10.250228 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9644 08:14:10.256517 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9645 08:14:10.260193 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9646 08:14:10.263030 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9647 08:14:10.269792 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9648 08:14:10.273110 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9649 08:14:10.276513 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9650 08:14:10.279773 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9651 08:14:10.282859 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9652 08:14:10.289821 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9653 08:14:10.292553 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9654 08:14:10.299655 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9655 08:14:10.302707 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9656 08:14:10.305947 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9657 08:14:10.312877 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9658 08:14:10.316438 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9659 08:14:10.322544 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9660 08:14:10.326290 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9661 08:14:10.329715 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9662 08:14:10.336276 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9663 08:14:10.339356 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9664 08:14:10.345988 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9665 08:14:10.349495 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9666 08:14:10.352846 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9667 08:14:10.359255 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9668 08:14:10.362707 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9669 08:14:10.369678 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9670 08:14:10.372700 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9671 08:14:10.375761 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9672 08:14:10.382770 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9673 08:14:10.385615 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9674 08:14:10.389116 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9675 08:14:10.395386 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9676 08:14:10.398694 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9677 08:14:10.405805 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9678 08:14:10.409085 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9679 08:14:10.415967 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9680 08:14:10.418746 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9681 08:14:10.422168 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9682 08:14:10.429225 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9683 08:14:10.432660 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9684 08:14:10.435618 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9685 08:14:10.442258 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9686 08:14:10.445380 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9687 08:14:10.452001 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9688 08:14:10.455704 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9689 08:14:10.458677 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9690 08:14:10.465782 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9691 08:14:10.468707 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9692 08:14:10.475205 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9693 08:14:10.478242 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9694 08:14:10.481730 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9695 08:14:10.488121 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9696 08:14:10.491302 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9697 08:14:10.498010 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9698 08:14:10.501683 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9699 08:14:10.505017 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9700 08:14:10.511573 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9701 08:14:10.514894 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9702 08:14:10.521399 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9703 08:14:10.524614 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9704 08:14:10.527988 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9705 08:14:10.534801 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9706 08:14:10.537776 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9707 08:14:10.544072 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9708 08:14:10.547898 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9709 08:14:10.550526 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9710 08:14:10.557663 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9711 08:14:10.560926 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9712 08:14:10.567133 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9713 08:14:10.571094 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9714 08:14:10.573920 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9715 08:14:10.581100 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9716 08:14:10.583818 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9717 08:14:10.590433 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9718 08:14:10.593756 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9719 08:14:10.600345 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9720 08:14:10.603903 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9721 08:14:10.606850 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9722 08:14:10.613840 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9723 08:14:10.616969 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9724 08:14:10.623323 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9725 08:14:10.626550 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9726 08:14:10.633672 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9727 08:14:10.636654 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9728 08:14:10.639460 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9729 08:14:10.646523 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9730 08:14:10.650058 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9731 08:14:10.656676 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9732 08:14:10.659863 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9733 08:14:10.666273 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9734 08:14:10.669450 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9735 08:14:10.672911 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9736 08:14:10.679736 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9737 08:14:10.682886 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9738 08:14:10.689018 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9739 08:14:10.692602 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9740 08:14:10.698521 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9741 08:14:10.702310 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9742 08:14:10.705986 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9743 08:14:10.712545 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9744 08:14:10.715770 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9745 08:14:10.722320 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9746 08:14:10.725719 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9747 08:14:10.732173 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9748 08:14:10.735259 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9749 08:14:10.738871 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9750 08:14:10.745504 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9751 08:14:10.748589 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9752 08:14:10.755353 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9753 08:14:10.758266 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9754 08:14:10.764802 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9755 08:14:10.768088 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9756 08:14:10.771800 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9757 08:14:10.778365 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9758 08:14:10.781558 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9759 08:14:10.784606 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9760 08:14:10.788219 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9761 08:14:10.794692 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9762 08:14:10.798189 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9763 08:14:10.801192 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9764 08:14:10.807718 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9765 08:14:10.810953 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9766 08:14:10.818235 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9767 08:14:10.821117 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9768 08:14:10.824465 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9769 08:14:10.831100 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9770 08:14:10.834470 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9771 08:14:10.837553 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9772 08:14:10.844238 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9773 08:14:10.847665 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9774 08:14:10.853822 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9775 08:14:10.857496 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9776 08:14:10.861098 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9777 08:14:10.867127 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9778 08:14:10.870494 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9779 08:14:10.873524 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9780 08:14:10.880527 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9781 08:14:10.884414 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9782 08:14:10.886849 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9783 08:14:10.893764 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9784 08:14:10.896578 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9785 08:14:10.903609 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9786 08:14:10.906129 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9787 08:14:10.909928 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9788 08:14:10.916582 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9789 08:14:10.919621 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9790 08:14:10.926184 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9791 08:14:10.929723 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9792 08:14:10.932877 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9793 08:14:10.939628 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9794 08:14:10.943496 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9795 08:14:10.946014 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9796 08:14:10.952970 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9797 08:14:10.956096 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9798 08:14:10.959758 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9799 08:14:10.966327 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9800 08:14:10.968722 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9801 08:14:10.972416 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9802 08:14:10.975702 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9803 08:14:10.982253 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9804 08:14:10.985780 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9805 08:14:10.988514 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9806 08:14:10.992443 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9807 08:14:10.998627 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9808 08:14:11.002431 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9809 08:14:11.005492 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9810 08:14:11.008943 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9811 08:14:11.015323 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9812 08:14:11.018932 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9813 08:14:11.024905 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9814 08:14:11.028335 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9815 08:14:11.035202 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9816 08:14:11.038940 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9817 08:14:11.042266 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9818 08:14:11.048491 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9819 08:14:11.052200 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9820 08:14:11.058542 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9821 08:14:11.061678 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9822 08:14:11.064947 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9823 08:14:11.071583 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9824 08:14:11.074838 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9825 08:14:11.081911 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9826 08:14:11.084426 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9827 08:14:11.091516 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9828 08:14:11.094439 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9829 08:14:11.098173 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9830 08:14:11.104991 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9831 08:14:11.107762 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9832 08:14:11.114302 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9833 08:14:11.118166 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9834 08:14:11.121317 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9835 08:14:11.127838 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9836 08:14:11.131165 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9837 08:14:11.137570 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9838 08:14:11.140752 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9839 08:14:11.147810 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9840 08:14:11.150609 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9841 08:14:11.154136 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9842 08:14:11.160567 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9843 08:14:11.163984 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9844 08:14:11.170048 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9845 08:14:11.173631 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9846 08:14:11.180162 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9847 08:14:11.183342 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9848 08:14:11.186825 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9849 08:14:11.193471 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9850 08:14:11.196346 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9851 08:14:11.203305 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9852 08:14:11.206799 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9853 08:14:11.209726 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9854 08:14:11.216618 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9855 08:14:11.219644 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9856 08:14:11.226493 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9857 08:14:11.229580 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9858 08:14:11.233370 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9859 08:14:11.239986 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9860 08:14:11.242840 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9861 08:14:11.249201 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9862 08:14:11.252658 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9863 08:14:11.259049 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9864 08:14:11.262618 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9865 08:14:11.269117 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9866 08:14:11.272450 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9867 08:14:11.275895 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9868 08:14:11.282514 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9869 08:14:11.286008 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9870 08:14:11.292600 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9871 08:14:11.295621 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9872 08:14:11.298961 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9873 08:14:11.305412 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9874 08:14:11.308754 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9875 08:14:11.315352 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9876 08:14:11.318667 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9877 08:14:11.325247 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9878 08:14:11.328221 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9879 08:14:11.331663 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9880 08:14:11.338050 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9881 08:14:11.341472 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9882 08:14:11.348390 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9883 08:14:11.351569 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9884 08:14:11.357963 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9885 08:14:11.361105 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9886 08:14:11.364658 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9887 08:14:11.370881 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9888 08:14:11.375069 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9889 08:14:11.380890 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9890 08:14:11.384007 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9891 08:14:11.390497 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9892 08:14:11.393765 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9893 08:14:11.400988 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9894 08:14:11.404000 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9895 08:14:11.407524 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9896 08:14:11.413808 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9897 08:14:11.417242 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9898 08:14:11.423479 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9899 08:14:11.427362 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9900 08:14:11.433107 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9901 08:14:11.437256 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9902 08:14:11.443934 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9903 08:14:11.447021 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9904 08:14:11.452988 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9905 08:14:11.456741 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9906 08:14:11.460043 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9907 08:14:11.466185 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9908 08:14:11.469853 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9909 08:14:11.476451 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9910 08:14:11.479387 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9911 08:14:11.485922 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9912 08:14:11.489142 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9913 08:14:11.496438 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9914 08:14:11.499255 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9915 08:14:11.502471 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9916 08:14:11.508847 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9917 08:14:11.512836 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9918 08:14:11.518780 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9919 08:14:11.522585 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9920 08:14:11.529479 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9921 08:14:11.532318 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9922 08:14:11.538653 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9923 08:14:11.541729 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9924 08:14:11.545042 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9925 08:14:11.551775 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9926 08:14:11.555405 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9927 08:14:11.561555 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9928 08:14:11.565254 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9929 08:14:11.571411 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9930 08:14:11.574573 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9931 08:14:11.578651 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9932 08:14:11.584952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9933 08:14:11.588314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9934 08:14:11.594500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9935 08:14:11.597825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9936 08:14:11.604749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9937 08:14:11.608183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9938 08:14:11.614896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9939 08:14:11.617814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9940 08:14:11.623987 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9941 08:14:11.627612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9942 08:14:11.634667 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9943 08:14:11.637838 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9944 08:14:11.644748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9945 08:14:11.647166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9946 08:14:11.653809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9947 08:14:11.657630 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9948 08:14:11.663766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9949 08:14:11.667692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9950 08:14:11.673793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9951 08:14:11.676792 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9952 08:14:11.683670 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9953 08:14:11.686978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9954 08:14:11.693262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9955 08:14:11.696465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9956 08:14:11.703137 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9957 08:14:11.706475 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9958 08:14:11.712980 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9959 08:14:11.716179 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9960 08:14:11.722632 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9961 08:14:11.726062 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9962 08:14:11.733030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9963 08:14:11.736518 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9964 08:14:11.739470 INFO: [APUAPC] vio 0
9965 08:14:11.743314 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9966 08:14:11.749523 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9967 08:14:11.753078 INFO: [APUAPC] D0_APC_0: 0x400510
9968 08:14:11.756091 INFO: [APUAPC] D0_APC_1: 0x0
9969 08:14:11.759538 INFO: [APUAPC] D0_APC_2: 0x1540
9970 08:14:11.760012 INFO: [APUAPC] D0_APC_3: 0x0
9971 08:14:11.762585 INFO: [APUAPC] D1_APC_0: 0xffffffff
9972 08:14:11.766089 INFO: [APUAPC] D1_APC_1: 0xffffffff
9973 08:14:11.769924 INFO: [APUAPC] D1_APC_2: 0x3fffff
9974 08:14:11.772360 INFO: [APUAPC] D1_APC_3: 0x0
9975 08:14:11.776053 INFO: [APUAPC] D2_APC_0: 0xffffffff
9976 08:14:11.779771 INFO: [APUAPC] D2_APC_1: 0xffffffff
9977 08:14:11.782655 INFO: [APUAPC] D2_APC_2: 0x3fffff
9978 08:14:11.786010 INFO: [APUAPC] D2_APC_3: 0x0
9979 08:14:11.789208 INFO: [APUAPC] D3_APC_0: 0xffffffff
9980 08:14:11.792494 INFO: [APUAPC] D3_APC_1: 0xffffffff
9981 08:14:11.796079 INFO: [APUAPC] D3_APC_2: 0x3fffff
9982 08:14:11.799449 INFO: [APUAPC] D3_APC_3: 0x0
9983 08:14:11.802232 INFO: [APUAPC] D4_APC_0: 0xffffffff
9984 08:14:11.805650 INFO: [APUAPC] D4_APC_1: 0xffffffff
9985 08:14:11.809325 INFO: [APUAPC] D4_APC_2: 0x3fffff
9986 08:14:11.812267 INFO: [APUAPC] D4_APC_3: 0x0
9987 08:14:11.815649 INFO: [APUAPC] D5_APC_0: 0xffffffff
9988 08:14:11.819045 INFO: [APUAPC] D5_APC_1: 0xffffffff
9989 08:14:11.822327 INFO: [APUAPC] D5_APC_2: 0x3fffff
9990 08:14:11.825493 INFO: [APUAPC] D5_APC_3: 0x0
9991 08:14:11.828676 INFO: [APUAPC] D6_APC_0: 0xffffffff
9992 08:14:11.831993 INFO: [APUAPC] D6_APC_1: 0xffffffff
9993 08:14:11.834965 INFO: [APUAPC] D6_APC_2: 0x3fffff
9994 08:14:11.838465 INFO: [APUAPC] D6_APC_3: 0x0
9995 08:14:11.841725 INFO: [APUAPC] D7_APC_0: 0xffffffff
9996 08:14:11.845440 INFO: [APUAPC] D7_APC_1: 0xffffffff
9997 08:14:11.848273 INFO: [APUAPC] D7_APC_2: 0x3fffff
9998 08:14:11.851190 INFO: [APUAPC] D7_APC_3: 0x0
9999 08:14:11.855360 INFO: [APUAPC] D8_APC_0: 0xffffffff
10000 08:14:11.858115 INFO: [APUAPC] D8_APC_1: 0xffffffff
10001 08:14:11.862077 INFO: [APUAPC] D8_APC_2: 0x3fffff
10002 08:14:11.864837 INFO: [APUAPC] D8_APC_3: 0x0
10003 08:14:11.868425 INFO: [APUAPC] D9_APC_0: 0xffffffff
10004 08:14:11.871259 INFO: [APUAPC] D9_APC_1: 0xffffffff
10005 08:14:11.874579 INFO: [APUAPC] D9_APC_2: 0x3fffff
10006 08:14:11.877616 INFO: [APUAPC] D9_APC_3: 0x0
10007 08:14:11.881070 INFO: [APUAPC] D10_APC_0: 0xffffffff
10008 08:14:11.884787 INFO: [APUAPC] D10_APC_1: 0xffffffff
10009 08:14:11.888261 INFO: [APUAPC] D10_APC_2: 0x3fffff
10010 08:14:11.891164 INFO: [APUAPC] D10_APC_3: 0x0
10011 08:14:11.894105 INFO: [APUAPC] D11_APC_0: 0xffffffff
10012 08:14:11.897856 INFO: [APUAPC] D11_APC_1: 0xffffffff
10013 08:14:11.900906 INFO: [APUAPC] D11_APC_2: 0x3fffff
10014 08:14:11.903877 INFO: [APUAPC] D11_APC_3: 0x0
10015 08:14:11.907700 INFO: [APUAPC] D12_APC_0: 0xffffffff
10016 08:14:11.910683 INFO: [APUAPC] D12_APC_1: 0xffffffff
10017 08:14:11.914255 INFO: [APUAPC] D12_APC_2: 0x3fffff
10018 08:14:11.917148 INFO: [APUAPC] D12_APC_3: 0x0
10019 08:14:11.920721 INFO: [APUAPC] D13_APC_0: 0xffffffff
10020 08:14:11.923906 INFO: [APUAPC] D13_APC_1: 0xffffffff
10021 08:14:11.927046 INFO: [APUAPC] D13_APC_2: 0x3fffff
10022 08:14:11.930589 INFO: [APUAPC] D13_APC_3: 0x0
10023 08:14:11.933540 INFO: [APUAPC] D14_APC_0: 0xffffffff
10024 08:14:11.937036 INFO: [APUAPC] D14_APC_1: 0xffffffff
10025 08:14:11.940301 INFO: [APUAPC] D14_APC_2: 0x3fffff
10026 08:14:11.943787 INFO: [APUAPC] D14_APC_3: 0x0
10027 08:14:11.946572 INFO: [APUAPC] D15_APC_0: 0xffffffff
10028 08:14:11.950210 INFO: [APUAPC] D15_APC_1: 0xffffffff
10029 08:14:11.953368 INFO: [APUAPC] D15_APC_2: 0x3fffff
10030 08:14:11.956524 INFO: [APUAPC] D15_APC_3: 0x0
10031 08:14:11.960218 INFO: [APUAPC] APC_CON: 0x4
10032 08:14:11.963106 INFO: [NOCDAPC] D0_APC_0: 0x0
10033 08:14:11.966717 INFO: [NOCDAPC] D0_APC_1: 0x0
10034 08:14:11.970376 INFO: [NOCDAPC] D1_APC_0: 0x0
10035 08:14:11.972934 INFO: [NOCDAPC] D1_APC_1: 0xfff
10036 08:14:11.976100 INFO: [NOCDAPC] D2_APC_0: 0x0
10037 08:14:11.979766 INFO: [NOCDAPC] D2_APC_1: 0xfff
10038 08:14:11.982839 INFO: [NOCDAPC] D3_APC_0: 0x0
10039 08:14:11.986565 INFO: [NOCDAPC] D3_APC_1: 0xfff
10040 08:14:11.987036 INFO: [NOCDAPC] D4_APC_0: 0x0
10041 08:14:11.989442 INFO: [NOCDAPC] D4_APC_1: 0xfff
10042 08:14:11.993314 INFO: [NOCDAPC] D5_APC_0: 0x0
10043 08:14:11.996126 INFO: [NOCDAPC] D5_APC_1: 0xfff
10044 08:14:11.999214 INFO: [NOCDAPC] D6_APC_0: 0x0
10045 08:14:12.002988 INFO: [NOCDAPC] D6_APC_1: 0xfff
10046 08:14:12.005865 INFO: [NOCDAPC] D7_APC_0: 0x0
10047 08:14:12.009254 INFO: [NOCDAPC] D7_APC_1: 0xfff
10048 08:14:12.012772 INFO: [NOCDAPC] D8_APC_0: 0x0
10049 08:14:12.016025 INFO: [NOCDAPC] D8_APC_1: 0xfff
10050 08:14:12.019791 INFO: [NOCDAPC] D9_APC_0: 0x0
10051 08:14:12.020358 INFO: [NOCDAPC] D9_APC_1: 0xfff
10052 08:14:12.022246 INFO: [NOCDAPC] D10_APC_0: 0x0
10053 08:14:12.025681 INFO: [NOCDAPC] D10_APC_1: 0xfff
10054 08:14:12.029240 INFO: [NOCDAPC] D11_APC_0: 0x0
10055 08:14:12.032431 INFO: [NOCDAPC] D11_APC_1: 0xfff
10056 08:14:12.035876 INFO: [NOCDAPC] D12_APC_0: 0x0
10057 08:14:12.039181 INFO: [NOCDAPC] D12_APC_1: 0xfff
10058 08:14:12.042594 INFO: [NOCDAPC] D13_APC_0: 0x0
10059 08:14:12.045520 INFO: [NOCDAPC] D13_APC_1: 0xfff
10060 08:14:12.048928 INFO: [NOCDAPC] D14_APC_0: 0x0
10061 08:14:12.052252 INFO: [NOCDAPC] D14_APC_1: 0xfff
10062 08:14:12.055509 INFO: [NOCDAPC] D15_APC_0: 0x0
10063 08:14:12.058958 INFO: [NOCDAPC] D15_APC_1: 0xfff
10064 08:14:12.061932 INFO: [NOCDAPC] APC_CON: 0x4
10065 08:14:12.065591 INFO: [APUAPC] set_apusys_apc done
10066 08:14:12.068850 INFO: [DEVAPC] devapc_init done
10067 08:14:12.072146 INFO: GICv3 without legacy support detected.
10068 08:14:12.075146 INFO: ARM GICv3 driver initialized in EL3
10069 08:14:12.078356 INFO: Maximum SPI INTID supported: 639
10070 08:14:12.081805 INFO: BL31: Initializing runtime services
10071 08:14:12.088364 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10072 08:14:12.092023 INFO: SPM: enable CPC mode
10073 08:14:12.098325 INFO: mcdi ready for mcusys-off-idle and system suspend
10074 08:14:12.101882 INFO: BL31: Preparing for EL3 exit to normal world
10075 08:14:12.104427 INFO: Entry point address = 0x80000000
10076 08:14:12.107948 INFO: SPSR = 0x8
10077 08:14:12.113087
10078 08:14:12.113685
10079 08:14:12.114064
10080 08:14:12.116558 Starting depthcharge on Spherion...
10081 08:14:12.117121
10082 08:14:12.117536 Wipe memory regions:
10083 08:14:12.117884
10084 08:14:12.120410 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10085 08:14:12.120958 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10086 08:14:12.121442 Setting prompt string to ['asurada:']
10087 08:14:12.121880 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10088 08:14:12.122601 [0x00000040000000, 0x00000054600000)
10089 08:14:12.242340
10090 08:14:12.242898 [0x00000054660000, 0x00000080000000)
10091 08:14:12.501667
10092 08:14:12.501820 [0x000000821a7280, 0x000000ffe64000)
10093 08:14:13.246887
10094 08:14:13.247441 [0x00000100000000, 0x00000240000000)
10095 08:14:15.136307
10096 08:14:15.140027 Initializing XHCI USB controller at 0x11200000.
10097 08:14:16.178256
10098 08:14:16.181442 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10099 08:14:16.182045
10100 08:14:16.182422
10101 08:14:16.182773
10102 08:14:16.183610 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10104 08:14:16.284881 asurada: tftpboot 192.168.201.1 13529852/tftp-deploy-9psta492/kernel/image.itb 13529852/tftp-deploy-9psta492/kernel/cmdline
10105 08:14:16.285543 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10106 08:14:16.286072 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10107 08:14:16.290043 tftpboot 192.168.201.1 13529852/tftp-deploy-9psta492/kernel/image.itp-deploy-9psta492/kernel/cmdline
10108 08:14:16.290617
10109 08:14:16.291011 Waiting for link
10110 08:14:16.448754
10111 08:14:16.449319 R8152: Initializing
10112 08:14:16.449761
10113 08:14:16.451736 Version 6 (ocp_data = 5c30)
10114 08:14:16.452293
10115 08:14:16.455605 R8152: Done initializing
10116 08:14:16.456164
10117 08:14:16.456540 Adding net device
10118 08:14:18.357133
10119 08:14:18.357743 done.
10120 08:14:18.358126
10121 08:14:18.358481 MAC: 00:e0:4c:68:02:81
10122 08:14:18.358822
10123 08:14:18.360304 Sending DHCP discover... done.
10124 08:14:18.360774
10125 08:14:21.403438 Waiting for reply... done.
10126 08:14:21.404155
10127 08:14:21.404547 Sending DHCP request... done.
10128 08:14:21.406819
10129 08:14:21.407285 Waiting for reply... done.
10130 08:14:21.407660
10131 08:14:21.409845 My ip is 192.168.201.14
10132 08:14:21.410314
10133 08:14:21.413479 The DHCP server ip is 192.168.201.1
10134 08:14:21.414041
10135 08:14:21.416279 TFTP server IP predefined by user: 192.168.201.1
10136 08:14:21.416749
10137 08:14:21.423208 Bootfile predefined by user: 13529852/tftp-deploy-9psta492/kernel/image.itb
10138 08:14:21.423767
10139 08:14:21.426027 Sending tftp read request... done.
10140 08:14:21.426720
10141 08:14:21.435357 Waiting for the transfer...
10142 08:14:21.435917
10143 08:14:22.128593 00000000 ################################################################
10144 08:14:22.129122
10145 08:14:22.840597 00080000 ################################################################
10146 08:14:22.841124
10147 08:14:23.556149 00100000 ################################################################
10148 08:14:23.556678
10149 08:14:24.237132 00180000 ################################################################
10150 08:14:24.237825
10151 08:14:24.943700 00200000 ################################################################
10152 08:14:24.944215
10153 08:14:25.666029 00280000 ################################################################
10154 08:14:25.666564
10155 08:14:26.380240 00300000 ################################################################
10156 08:14:26.380768
10157 08:14:27.101507 00380000 ################################################################
10158 08:14:27.102211
10159 08:14:27.807298 00400000 ################################################################
10160 08:14:27.807835
10161 08:14:28.520172 00480000 ################################################################
10162 08:14:28.520765
10163 08:14:29.228350 00500000 ################################################################
10164 08:14:29.228904
10165 08:14:29.936607 00580000 ################################################################
10166 08:14:29.937127
10167 08:14:30.647752 00600000 ################################################################
10168 08:14:30.648447
10169 08:14:31.349998 00680000 ################################################################
10170 08:14:31.350516
10171 08:14:32.055962 00700000 ################################################################
10172 08:14:32.056493
10173 08:14:32.759504 00780000 ################################################################
10174 08:14:32.760016
10175 08:14:33.446333 00800000 ################################################################
10176 08:14:33.446891
10177 08:14:34.165494 00880000 ################################################################
10178 08:14:34.166103
10179 08:14:34.877008 00900000 ################################################################
10180 08:14:34.877549
10181 08:14:35.579664 00980000 ################################################################
10182 08:14:35.580252
10183 08:14:36.295902 00a00000 ################################################################
10184 08:14:36.296413
10185 08:14:36.997013 00a80000 ################################################################
10186 08:14:36.997563
10187 08:14:37.724148 00b00000 ################################################################
10188 08:14:37.724711
10189 08:14:38.412606 00b80000 ################################################################
10190 08:14:38.413149
10191 08:14:39.112390 00c00000 ################################################################
10192 08:14:39.112976
10193 08:14:39.829061 00c80000 ################################################################
10194 08:14:39.829730
10195 08:14:40.517424 00d00000 ################################################################
10196 08:14:40.517956
10197 08:14:41.215812 00d80000 ################################################################
10198 08:14:41.216325
10199 08:14:41.912669 00e00000 ################################################################
10200 08:14:41.913249
10201 08:14:42.633443 00e80000 ################################################################
10202 08:14:42.633962
10203 08:14:43.325991 00f00000 ################################################################
10204 08:14:43.326602
10205 08:14:44.014684 00f80000 ################################################################
10206 08:14:44.015198
10207 08:14:44.724459 01000000 ################################################################
10208 08:14:44.724991
10209 08:14:45.408929 01080000 ################################################################
10210 08:14:45.409484
10211 08:14:46.119343 01100000 ################################################################
10212 08:14:46.119938
10213 08:14:46.830112 01180000 ################################################################
10214 08:14:46.830667
10215 08:14:47.543573 01200000 ################################################################
10216 08:14:47.544096
10217 08:14:48.253384 01280000 ################################################################
10218 08:14:48.253933
10219 08:14:48.949896 01300000 ################################################################
10220 08:14:48.950428
10221 08:14:49.672512 01380000 ################################################################
10222 08:14:49.673028
10223 08:14:50.384380 01400000 ################################################################
10224 08:14:50.384895
10225 08:14:51.089775 01480000 ################################################################
10226 08:14:51.090293
10227 08:14:51.774690 01500000 ################################################################
10228 08:14:51.775212
10229 08:14:52.475680 01580000 ################################################################
10230 08:14:52.476203
10231 08:14:53.191744 01600000 ################################################################
10232 08:14:53.192257
10233 08:14:53.909202 01680000 ################################################################
10234 08:14:53.909768
10235 08:14:54.630967 01700000 ################################################################
10236 08:14:54.631563
10237 08:14:55.341775 01780000 ################################################################
10238 08:14:55.342307
10239 08:14:56.043340 01800000 ################################################################
10240 08:14:56.043837
10241 08:14:56.742708 01880000 ################################################################
10242 08:14:56.743223
10243 08:14:57.456960 01900000 ################################################################
10244 08:14:57.457533
10245 08:14:58.134865 01980000 ################################################################
10246 08:14:58.135414
10247 08:14:58.842420 01a00000 ################################################################
10248 08:14:58.842947
10249 08:14:59.552825 01a80000 ################################################################
10250 08:14:59.553379
10251 08:15:00.275015 01b00000 ################################################################
10252 08:15:00.275563
10253 08:15:00.951217 01b80000 ################################################################
10254 08:15:00.951746
10255 08:15:01.652599 01c00000 ################################################################
10256 08:15:01.653128
10257 08:15:02.351891 01c80000 ################################################################
10258 08:15:02.352444
10259 08:15:03.067127 01d00000 ################################################################
10260 08:15:03.067649
10261 08:15:03.785958 01d80000 ################################################################
10262 08:15:03.786540
10263 08:15:04.495305 01e00000 ################################################################
10264 08:15:04.495927
10265 08:15:05.217608 01e80000 ################################################################
10266 08:15:05.218178
10267 08:15:05.922302 01f00000 ################################################################
10268 08:15:05.922898
10269 08:15:06.628493 01f80000 ################################################################
10270 08:15:06.629025
10271 08:15:07.329428 02000000 ################################################################
10272 08:15:07.329954
10273 08:15:08.029324 02080000 ################################################################
10274 08:15:08.029870
10275 08:15:08.728948 02100000 ################################################################
10276 08:15:08.729498
10277 08:15:09.422070 02180000 ################################################################
10278 08:15:09.422600
10279 08:15:10.121599 02200000 ################################################################
10280 08:15:10.122112
10281 08:15:10.817431 02280000 ################################################################
10282 08:15:10.818023
10283 08:15:11.508769 02300000 ################################################################
10284 08:15:11.509287
10285 08:15:12.215856 02380000 ################################################################
10286 08:15:12.216387
10287 08:15:12.632035 02400000 ######################################## done.
10288 08:15:12.632595
10289 08:15:12.635507 The bootfile was 38072066 bytes long.
10290 08:15:12.635938
10291 08:15:12.639148 Sending tftp read request... done.
10292 08:15:12.639813
10293 08:15:12.642564 Waiting for the transfer...
10294 08:15:12.643229
10295 08:15:12.643685 00000000 # done.
10296 08:15:12.644078
10297 08:15:12.648653 Command line loaded dynamically from TFTP file: 13529852/tftp-deploy-9psta492/kernel/cmdline
10298 08:15:12.652017
10299 08:15:12.665819 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10300 08:15:12.666619
10301 08:15:12.667218 Loading FIT.
10302 08:15:12.667689
10303 08:15:12.670746 Image ramdisk-1 has 24597836 bytes.
10304 08:15:12.671243
10305 08:15:12.674272 Image fdt-1 has 65337 bytes.
10306 08:15:12.674679
10307 08:15:12.675338 Image kernel-1 has 13406858 bytes.
10308 08:15:12.675842
10309 08:15:12.681619 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10310 08:15:12.682061
10311 08:15:12.701519 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10312 08:15:12.701969
10313 08:15:12.704676 Choosing best match conf-1 for compat google,spherion-rev2.
10314 08:15:12.709846
10315 08:15:12.714502 Connected to device vid:did:rid of 1ae0:0028:00
10316 08:15:12.721472
10317 08:15:12.724425 tpm_get_response: command 0x17b, return code 0x0
10318 08:15:12.724863
10319 08:15:12.727947 ec_init: CrosEC protocol v3 supported (256, 248)
10320 08:15:12.732396
10321 08:15:12.735659 tpm_cleanup: add release locality here.
10322 08:15:12.736084
10323 08:15:12.736413 Shutting down all USB controllers.
10324 08:15:12.738678
10325 08:15:12.739261 Removing current net device
10326 08:15:12.739606
10327 08:15:12.745216 Exiting depthcharge with code 4 at timestamp: 90095751
10328 08:15:12.745703
10329 08:15:12.748909 LZMA decompressing kernel-1 to 0x821a6718
10330 08:15:12.749373
10331 08:15:12.752263 LZMA decompressing kernel-1 to 0x40000000
10332 08:15:14.432167
10333 08:15:14.432736 jumping to kernel
10334 08:15:14.434654 end: 2.2.4 bootloader-commands (duration 00:01:02) [common]
10335 08:15:14.435189 start: 2.2.5 auto-login-action (timeout 00:03:23) [common]
10336 08:15:14.435616 Setting prompt string to ['Linux version [0-9]']
10337 08:15:14.436003 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10338 08:15:14.436383 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10339 08:15:14.470943
10340 08:15:14.474446 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10341 08:15:14.478572 start: 2.2.5.1 login-action (timeout 00:03:22) [common]
10342 08:15:14.479159 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10343 08:15:14.479569 Setting prompt string to []
10344 08:15:14.480003 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10345 08:15:14.480503 Using line separator: #'\n'#
10346 08:15:14.480989 No login prompt set.
10347 08:15:14.481654 Parsing kernel messages
10348 08:15:14.482227 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10349 08:15:14.482848 [login-action] Waiting for messages, (timeout 00:03:22)
10350 08:15:14.483230 Waiting using forced prompt support (timeout 00:01:41)
10351 08:15:14.496941 [ 0.000000] Linux version 6.9.0-rc5-next-20240426 (KernelCI@build-j177802-arm64-gcc-10-defconfig-arm64-chromebook-wmnzg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Apr 26 07:50:50 UTC 2024
10352 08:15:14.500788 [ 0.000000] KASLR enabled
10353 08:15:14.503994 [ 0.000000] random: crng init done
10354 08:15:14.510133 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10355 08:15:14.513814 [ 0.000000] efi: UEFI not found.
10356 08:15:14.520383 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10357 08:15:14.530597 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10358 08:15:14.539829 [ 0.000000] OF: reserved mem: 0x0000000050000000..0x00000000528fffff (41984 KiB) nomap non-reusable scp@50000000
10359 08:15:14.549833 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10360 08:15:14.556527 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10361 08:15:14.566158 [ 0.000000] OF: reserved mem: 0x00000000c0000000..0x00000000c3ffffff (65536 KiB) map non-reusable wifi@c0000000
10362 08:15:14.576417 [ 0.000000] OF: reserved mem: 0x00000000ffe66000..0x00000000fff65fff (1024 KiB) map non-reusable ramoops
10363 08:15:14.582423 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10364 08:15:14.589384 [ 0.000000] printk: legacy bootconsole [mtk8250] enabled
10365 08:15:14.597913 [ 0.000000] NUMA: No NUMA configuration found
10366 08:15:14.604825 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10367 08:15:14.610990 [ 0.000000] NUMA: NODE_DATA [mem 0x23efb49c0-0x23efb6fff]
10368 08:15:14.614297 [ 0.000000] Zone ranges:
10369 08:15:14.617399 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10370 08:15:14.621064 [ 0.000000] DMA32 empty
10371 08:15:14.627237 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10372 08:15:14.630812 [ 0.000000] Movable zone start for each node
10373 08:15:14.637478 [ 0.000000] Early memory node ranges
10374 08:15:14.640406 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10375 08:15:14.647032 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10376 08:15:14.653706 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10377 08:15:14.660228 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10378 08:15:14.666940 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10379 08:15:14.673449 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10380 08:15:14.698789 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10381 08:15:14.737735 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10382 08:15:14.743889 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000 on node -1
10383 08:15:14.750743 [ 0.000000] psci: probing for conduit method from DT.
10384 08:15:14.754192 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10385 08:15:14.760445 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10386 08:15:14.764228 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10387 08:15:14.767350 [ 0.000000] psci: SMC Calling Convention v1.2
10388 08:15:14.774200 [ 0.000000] percpu: Embedded 24 pages/cpu s60136 r8192 d29976 u98304
10389 08:15:14.781100 [ 0.000000] Detected VIPT I-cache on CPU0
10390 08:15:14.787728 [ 0.000000] CPU features: detected: GIC system register CPU interface
10391 08:15:14.790582 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10392 08:15:14.800674 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10393 08:15:14.804142 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10394 08:15:14.814010 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10395 08:15:14.817162 [ 0.000000] alternatives: applying boot alternatives
10396 08:15:14.833599 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10397 08:15:14.843042 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10398 08:15:14.854241 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10399 08:15:14.863884 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10400 08:15:14.867711 <6>[ 0.000000] Fallback order for Node 0: 0
10401 08:15:14.873644 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2096384
10402 08:15:14.877151 <6>[ 0.000000] Policy zone: Normal
10403 08:15:14.886874 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off, mlocked free:off
10404 08:15:14.890097 <6>[ 0.000000] software IO TLB: area num 8.
10405 08:15:14.946921 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10406 08:15:15.092378 <6>[ 0.000000] Memory: 7933964K/8385536K available (18112K kernel code, 5100K rwdata, 23956K rodata, 10880K init, 752K bss, 418804K reserved, 32768K cma-reserved)
10407 08:15:15.098884 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10408 08:15:15.105437 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10409 08:15:15.108807 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10410 08:15:15.115414 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=8.
10411 08:15:15.121670 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10412 08:15:15.128633 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10413 08:15:15.135192 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10414 08:15:15.141528 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10415 08:15:15.148400 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
10416 08:15:15.157809 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
10417 08:15:15.161252 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10418 08:15:15.170025 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10419 08:15:15.172819 <6>[ 0.000000] GICv3: 608 SPIs implemented
10420 08:15:15.179137 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10421 08:15:15.182339 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10422 08:15:15.189652 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10423 08:15:15.195965 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10424 08:15:15.205672 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10425 08:15:15.218946 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10426 08:15:15.225387 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10427 08:15:15.235777 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10428 08:15:15.249394 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10429 08:15:15.255955 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10430 08:15:15.262652 <6>[ 0.009650] Console: colour dummy device 80x25
10431 08:15:15.272787 <6>[ 0.014384] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10432 08:15:15.279164 <6>[ 0.024826] pid_max: default: 32768 minimum: 301
10433 08:15:15.282453 <6>[ 0.029721] LSM: initializing lsm=capability
10434 08:15:15.288930 <6>[ 0.034318] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10435 08:15:15.298830 <6>[ 0.042130] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10436 08:15:15.305374 <6>[ 0.051019] spectre-v4 mitigation disabled by command-line option
10437 08:15:15.312248 <6>[ 0.058250] rcu: Hierarchical SRCU implementation.
10438 08:15:15.315348 <6>[ 0.063269] rcu: Max phase no-delay instances is 1000.
10439 08:15:15.324468 <6>[ 0.071117] EFI services will not be available.
10440 08:15:15.327536 <6>[ 0.076090] smp: Bringing up secondary CPUs ...
10441 08:15:15.336856 <6>[ 0.081191] Detected VIPT I-cache on CPU1
10442 08:15:15.343435 <6>[ 0.081257] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10443 08:15:15.350158 <6>[ 0.081290] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10444 08:15:15.353374 <6>[ 0.081661] Detected VIPT I-cache on CPU2
10445 08:15:15.363854 <6>[ 0.081696] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10446 08:15:15.370139 <6>[ 0.081712] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10447 08:15:15.373397 <6>[ 0.082013] Detected VIPT I-cache on CPU3
10448 08:15:15.380172 <6>[ 0.082047] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10449 08:15:15.386686 <6>[ 0.082062] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10450 08:15:15.389621 <6>[ 0.082403] CPU features: detected: Spectre-v4
10451 08:15:15.396452 <6>[ 0.082410] CPU features: detected: Spectre-BHB
10452 08:15:15.399688 <6>[ 0.082416] Detected PIPT I-cache on CPU4
10453 08:15:15.406120 <6>[ 0.082458] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10454 08:15:15.413003 <6>[ 0.082477] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10455 08:15:15.419571 <6>[ 0.082806] Detected PIPT I-cache on CPU5
10456 08:15:15.426291 <6>[ 0.082852] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10457 08:15:15.432984 <6>[ 0.082870] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10458 08:15:15.435995 <6>[ 0.083196] Detected PIPT I-cache on CPU6
10459 08:15:15.445616 <6>[ 0.083243] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10460 08:15:15.453012 <6>[ 0.083260] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10461 08:15:15.455684 <6>[ 0.083571] Detected PIPT I-cache on CPU7
10462 08:15:15.462701 <6>[ 0.083619] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10463 08:15:15.468773 <6>[ 0.083636] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10464 08:15:15.472371 <6>[ 0.083721] smp: Brought up 1 node, 8 CPUs
10465 08:15:15.478826 <6>[ 0.225077] SMP: Total of 8 processors activated.
10466 08:15:15.481957 <6>[ 0.229998] CPU: All CPU(s) started at EL2
10467 08:15:15.489084 <6>[ 0.234326] CPU features: detected: 32-bit EL0 Support
10468 08:15:15.495407 <6>[ 0.239713] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10469 08:15:15.501654 <6>[ 0.248516] CPU features: detected: Common not Private translations
10470 08:15:15.508825 <6>[ 0.255027] CPU features: detected: CRC32 instructions
10471 08:15:15.514984 <6>[ 0.260387] CPU features: detected: RCpc load-acquire (LDAPR)
10472 08:15:15.521495 <6>[ 0.266341] CPU features: detected: LSE atomic instructions
10473 08:15:15.524608 <6>[ 0.272157] CPU features: detected: Privileged Access Never
10474 08:15:15.531627 <6>[ 0.277937] CPU features: detected: RAS Extension Support
10475 08:15:15.538192 <6>[ 0.283546] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10476 08:15:15.544814 <6>[ 0.290742] spectre-bhb mitigation disabled by command line option
10477 08:15:15.551337 <6>[ 0.297155] alternatives: applying system-wide alternatives
10478 08:15:15.562301 <6>[ 0.305934] CPU features: detected: Hardware dirty bit management on CPU4-7
10479 08:15:15.565971 <6>[ 0.315171] devtmpfs: initialized
10480 08:15:15.585919 <6>[ 0.326175] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10481 08:15:15.592611 <6>[ 0.336132] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10482 08:15:15.599708 <6>[ 0.343992] 2G module region forced by RANDOMIZE_MODULE_REGION_FULL
10483 08:15:15.602473 <6>[ 0.350480] 0 pages in range for non-PLT usage
10484 08:15:15.609069 <6>[ 0.350483] 509520 pages in range for PLT usage
10485 08:15:15.612424 <6>[ 0.355360] pinctrl core: initialized pinctrl subsystem
10486 08:15:15.620624 <6>[ 0.367115] DMI not present or invalid.
10487 08:15:15.626942 <6>[ 0.373205] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10488 08:15:15.637375 <6>[ 0.380016] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10489 08:15:15.643587 <6>[ 0.387523] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10490 08:15:15.653438 <6>[ 0.395734] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10491 08:15:15.656724 <6>[ 0.403970] audit: initializing netlink subsys (disabled)
10492 08:15:15.666455 <5>[ 0.409668] audit: type=2000 audit(0.296:1): state=initialized audit_enabled=0 res=1
10493 08:15:15.673382 <6>[ 0.410611] thermal_sys: Registered thermal governor 'step_wise'
10494 08:15:15.679789 <6>[ 0.417633] thermal_sys: Registered thermal governor 'power_allocator'
10495 08:15:15.683121 <6>[ 0.423893] cpuidle: using governor menu
10496 08:15:15.689402 <6>[ 0.434865] NET: Registered PF_QIPCRTR protocol family
10497 08:15:15.696450 <6>[ 0.440374] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10498 08:15:15.702673 <6>[ 0.447488] ASID allocator initialised with 32768 entries
10499 08:15:15.706053 <6>[ 0.454489] Serial: AMBA PL011 UART driver
10500 08:15:15.736901 <6>[ 0.480069] platform 14010000.dsi: Fixed dependency cycle(s) with /soc/i2c@11cb0000/anx7625@58
10501 08:15:15.755042 <6>[ 0.498244] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10502 08:15:15.761603 <6>[ 0.505260] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10503 08:15:15.768077 <6>[ 0.511748] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10504 08:15:15.774519 <6>[ 0.518753] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10505 08:15:15.781081 <6>[ 0.525240] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10506 08:15:15.788025 <6>[ 0.532239] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10507 08:15:15.794529 <6>[ 0.538724] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10508 08:15:15.801150 <6>[ 0.545731] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10509 08:15:15.804813 <6>[ 0.552497] Demotion targets for Node 0: null
10510 08:15:15.811053 <6>[ 0.558220] ACPI: Interpreter disabled.
10511 08:15:15.817912 <6>[ 0.564760] iommu: Default domain type: Translated
10512 08:15:15.824884 <6>[ 0.569783] iommu: DMA domain TLB invalidation policy: strict mode
10513 08:15:15.827899 <5>[ 0.576552] SCSI subsystem initialized
10514 08:15:15.835039 <6>[ 0.580733] usbcore: registered new interface driver usbfs
10515 08:15:15.840932 <6>[ 0.586460] usbcore: registered new interface driver hub
10516 08:15:15.844662 <6>[ 0.592011] usbcore: registered new device driver usb
10517 08:15:15.851562 <6>[ 0.598261] pps_core: LinuxPPS API ver. 1 registered
10518 08:15:15.861272 <6>[ 0.603455] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10519 08:15:15.864792 <6>[ 0.612795] PTP clock support registered
10520 08:15:15.867927 <6>[ 0.617059] EDAC MC: Ver: 3.0.0
10521 08:15:15.874751 <6>[ 0.620826] scmi_core: SCMI protocol bus registered
10522 08:15:15.877639 <6>[ 0.627294] FPGA manager framework
10523 08:15:15.884585 <6>[ 0.630987] Advanced Linux Sound Architecture Driver Initialized.
10524 08:15:15.887773 <6>[ 0.637947] vgaarb: loaded
10525 08:15:15.894980 <6>[ 0.641230] clocksource: Switched to clocksource arch_sys_counter
10526 08:15:15.901287 <5>[ 0.647693] VFS: Disk quotas dquot_6.6.0
10527 08:15:15.908029 <6>[ 0.651868] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10528 08:15:15.910826 <6>[ 0.659066] pnp: PnP ACPI: disabled
10529 08:15:15.919365 <6>[ 0.666134] NET: Registered PF_INET protocol family
10530 08:15:15.929524 <6>[ 0.671716] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10531 08:15:15.940552 <6>[ 0.684084] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10532 08:15:15.950373 <6>[ 0.692887] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10533 08:15:15.957639 <6>[ 0.700858] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10534 08:15:15.963412 <6>[ 0.709220] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10535 08:15:15.975263 <6>[ 0.718944] TCP: Hash tables configured (established 65536 bind 65536)
10536 08:15:15.982003 <6>[ 0.725807] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10537 08:15:15.988571 <6>[ 0.732874] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10538 08:15:15.995548 <6>[ 0.740436] NET: Registered PF_UNIX/PF_LOCAL protocol family
10539 08:15:16.001497 <6>[ 0.746529] RPC: Registered named UNIX socket transport module.
10540 08:15:16.004942 <6>[ 0.752678] RPC: Registered udp transport module.
10541 08:15:16.011741 <6>[ 0.757609] RPC: Registered tcp transport module.
10542 08:15:16.015282 <6>[ 0.762538] RPC: Registered tcp-with-tls transport module.
10543 08:15:16.022037 <6>[ 0.768247] RPC: Registered tcp NFSv4.1 backchannel transport module.
10544 08:15:16.028533 <6>[ 0.774910] PCI: CLS 0 bytes, default 64
10545 08:15:16.032203 <6>[ 0.779258] Unpacking initramfs...
10546 08:15:16.039072 <6>[ 0.785528] kvm [1]: nv: 477 coarse grained trap handlers
10547 08:15:16.045573 <6>[ 0.791368] kvm [1]: IPA Size Limit: 40 bits
10548 08:15:16.048829 <6>[ 0.795893] kvm [1]: GICv3: no GICV resource entry
10549 08:15:16.055051 <6>[ 0.800911] kvm [1]: disabling GICv2 emulation
10550 08:15:16.058691 <6>[ 0.805594] kvm [1]: GIC system register CPU interface enabled
10551 08:15:16.065232 <6>[ 0.811668] kvm [1]: vgic interrupt IRQ18
10552 08:15:16.068511 <6>[ 0.815929] kvm [1]: VHE mode initialized successfully
10553 08:15:16.075429 <5>[ 0.822335] Initialise system trusted keyrings
10554 08:15:16.082654 <6>[ 0.827150] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10555 08:15:16.088821 <6>[ 0.834028] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10556 08:15:16.095799 <5>[ 0.840267] NFS: Registering the id_resolver key type
10557 08:15:16.098912 <5>[ 0.845569] Key type id_resolver registered
10558 08:15:16.102069 <5>[ 0.849984] Key type id_legacy registered
10559 08:15:16.108694 <6>[ 0.854234] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10560 08:15:16.118702 <6>[ 0.861156] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10561 08:15:16.121707 <6>[ 0.868883] 9p: Installing v9fs 9p2000 file system support
10562 08:15:16.161894 <5>[ 0.908646] Key type asymmetric registered
10563 08:15:16.165375 <5>[ 0.912977] Asymmetric key parser 'x509' registered
10564 08:15:16.174755 <6>[ 0.918123] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 242)
10565 08:15:16.178919 <6>[ 0.925738] io scheduler mq-deadline registered
10566 08:15:16.181657 <6>[ 0.930496] io scheduler kyber registered
10567 08:15:16.188331 <6>[ 0.934772] io scheduler bfq registered
10568 08:15:16.218817 <4>[ 0.965615] cannot find "mediatek,mt8192-fhctl"
10569 08:15:16.253134 <6>[ 0.996672] mtk-socinfo mtk-socinfo.0.auto: MediaTek Kompanio 820 (MT8192) SoC detected.
10570 08:15:16.267841 <6>[ 1.014594] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10571 08:15:16.276594 <6>[ 1.023157] printk: legacy console [ttyS0] disabled
10572 08:15:16.305436 <6>[ 1.048523] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 252, base_baud = 1625000) is a ST16650V2
10573 08:15:16.311476 <6>[ 1.057999] printk: legacy console [ttyS0] enabled
10574 08:15:16.314950 <6>[ 1.057999] printk: legacy console [ttyS0] enabled
10575 08:15:16.321911 <6>[ 1.068115] printk: legacy bootconsole [mtk8250] disabled
10576 08:15:16.327902 <6>[ 1.068115] printk: legacy bootconsole [mtk8250] disabled
10577 08:15:16.336154 <6>[ 1.083142] msm_serial: driver initialized
10578 08:15:16.339205 <6>[ 1.087928] SuperH (H)SCI(F) driver initialized
10579 08:15:16.346135 <6>[ 1.092920] STM32 USART driver initialized
10580 08:15:16.355981 <4>[ 1.099272] SPI driver tpm_tis_spi has no spi_device_id for atmel,attpm20p
10581 08:15:16.365363 <6>[ 1.112247] loop: module loaded
10582 08:15:16.372202 <4>[ 1.118875] mtk-pmic-keys: Failed to locate of_node [id: -1]
10583 08:15:16.378772 <6>[ 1.119478] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10584 08:15:16.382367 <6>[ 1.125920] megasas: 07.727.03.00-rc1
10585 08:15:16.389668 <6>[ 1.136379] vsram_others: Bringing 850000uV into 800000-800000uV
10586 08:15:16.401959 <6>[ 1.148629] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10587 08:15:16.417685 <6>[ 1.164385] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10588 08:15:16.487975 <6>[ 1.230296] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10589 08:15:17.082461 <6>[ 1.829648] Freeing initrd memory: 24016K
10590 08:15:17.100264 <6>[ 1.847622] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10591 08:15:17.111009 <6>[ 1.858551] tun: Universal TUN/TAP device driver, 1.6
10592 08:15:17.114465 <6>[ 1.864800] thunder_xcv, ver 1.0
10593 08:15:17.117831 <6>[ 1.868303] thunder_bgx, ver 1.0
10594 08:15:17.121445 <6>[ 1.871798] nicpf, ver 1.0
10595 08:15:17.132024 <6>[ 1.875920] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10596 08:15:17.135414 <6>[ 1.883396] hns3: Copyright (c) 2017 Huawei Corporation.
10597 08:15:17.141588 <6>[ 1.888976] hclge is initializing
10598 08:15:17.144900 <6>[ 1.892581] e1000: Intel(R) PRO/1000 Network Driver
10599 08:15:17.151695 <6>[ 1.897711] e1000: Copyright (c) 1999-2006 Intel Corporation.
10600 08:15:17.158383 <6>[ 1.903723] e1000e: Intel(R) PRO/1000 Network Driver
10601 08:15:17.161580 <6>[ 1.908945] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10602 08:15:17.167918 <6>[ 1.915141] igb: Intel(R) Gigabit Ethernet Network Driver
10603 08:15:17.174503 <6>[ 1.920795] igb: Copyright (c) 2007-2014 Intel Corporation.
10604 08:15:17.181167 <6>[ 1.926630] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10605 08:15:17.187519 <6>[ 1.933148] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10606 08:15:17.190930 <6>[ 1.939655] sky2: driver version 1.30
10607 08:15:17.197348 <6>[ 1.945055] VFIO - User Level meta-driver version: 0.3
10608 08:15:17.205966 <6>[ 1.953546] usbcore: registered new interface driver usb-storage
10609 08:15:17.216086 <6>[ 1.963167] mt6397-rtc mt6359-rtc: registered as rtc0
10610 08:15:17.225588 <6>[ 1.968659] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-26T08:15:16 UTC (1714119316)
10611 08:15:17.229123 <6>[ 1.978438] i2c_dev: i2c /dev entries driver
10612 08:15:17.240189 <6>[ 1.984058] platform 14010000.dsi: Fixed dependency cycle(s) with /soc/i2c@11cb0000/anx7625@58
10613 08:15:17.250006 <6>[ 1.992972] i2c 3-0058: Fixed dependency cycle(s) with /soc/i2c@11cb0000/anx7625@58/aux-bus/panel
10614 08:15:17.256694 <6>[ 2.002112] i2c 3-0058: Fixed dependency cycle(s) with /soc/dsi@14010000
10615 08:15:17.273346 <6>[ 2.017446] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10616 08:15:17.280266 <4>[ 2.026638] cpu cpu0: supply cpu not found, using dummy regulator
10617 08:15:17.286828 <4>[ 2.033088] cpu cpu1: supply cpu not found, using dummy regulator
10618 08:15:17.293510 <4>[ 2.039498] cpu cpu2: supply cpu not found, using dummy regulator
10619 08:15:17.299489 <4>[ 2.045915] cpu cpu3: supply cpu not found, using dummy regulator
10620 08:15:17.306307 <4>[ 2.052312] cpu cpu4: supply cpu not found, using dummy regulator
10621 08:15:17.313151 <4>[ 2.058714] cpu cpu5: supply cpu not found, using dummy regulator
10622 08:15:17.319640 <4>[ 2.065121] cpu cpu6: supply cpu not found, using dummy regulator
10623 08:15:17.326056 <4>[ 2.071536] cpu cpu7: supply cpu not found, using dummy regulator
10624 08:15:17.344621 <6>[ 2.092207] cpu cpu0: EM: created perf domain
10625 08:15:17.348086 <6>[ 2.097062] cpu cpu4: EM: created perf domain
10626 08:15:17.355773 <6>[ 2.103016] sdhci: Secure Digital Host Controller Interface driver
10627 08:15:17.362520 <6>[ 2.109452] sdhci: Copyright(c) Pierre Ossman
10628 08:15:17.369063 <6>[ 2.114494] Synopsys Designware Multimedia Card Interface Driver
10629 08:15:17.375674 <6>[ 2.121187] sdhci-pltfm: SDHCI platform and OF driver helper
10630 08:15:17.379191 <6>[ 2.121351] mmc0: CQHCI version 5.10
10631 08:15:17.385326 <6>[ 2.131790] ledtrig-cpu: registered to indicate activity on CPUs
10632 08:15:17.391908 <6>[ 2.138579] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10633 08:15:17.398666 <6>[ 2.145765] usbcore: registered new interface driver usbhid
10634 08:15:17.401474 <6>[ 2.151590] usbhid: USB HID core driver
10635 08:15:17.411937 <6>[ 2.155943] spi_master spi0: will run message pump with realtime priority
10636 08:15:17.418421 <6>[ 2.163754] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10637 08:15:17.429184 <6>[ 2.172865] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10638 08:15:17.442348 <6>[ 2.186302] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10639 08:15:17.455306 <6>[ 2.191769] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10640 08:15:17.462461 <6>[ 2.198528] mt8192_mt6359 sound: audio-routing not found: using legacy probe
10641 08:15:17.475096 <6>[ 2.213738] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10642 08:15:17.482256 <6>[ 2.216161] NET: Registered PF_PACKET protocol family
10643 08:15:17.492390 <4>[ 2.222477] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10644 08:15:17.499224 <4>[ 2.222529] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10645 08:15:17.514004 <4>[ 2.222575] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10646 08:15:17.521553 <4>[ 2.222621] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10647 08:15:17.527819 <4>[ 2.222666] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10648 08:15:17.537877 <4>[ 2.222711] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10649 08:15:17.547725 <4>[ 2.222757] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10650 08:15:17.554455 <4>[ 2.222807] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10651 08:15:17.564027 <4>[ 2.222852] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10652 08:15:17.574042 <4>[ 2.222897] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10653 08:15:17.584050 <4>[ 2.222941] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10654 08:15:17.593763 <4>[ 2.222985] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10655 08:15:17.600422 <4>[ 2.223032] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10656 08:15:17.610806 <4>[ 2.223077] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10657 08:15:17.620678 <4>[ 2.223121] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10658 08:15:17.630408 <4>[ 2.223165] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10659 08:15:17.637175 <4>[ 2.223209] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10660 08:15:17.647060 <4>[ 2.223258] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10661 08:15:17.656801 <4>[ 2.223303] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10662 08:15:17.666765 <4>[ 2.223346] mtk-msdc 11f60000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000002
10663 08:15:17.673502 <6>[ 2.224215] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16814
10664 08:15:17.676489 <6>[ 2.232277] cros-ec-spi spi0.0: Chrome EC device registered
10665 08:15:17.683239 <6>[ 2.234387] 9pnet: Installing 9P2000 support
10666 08:15:17.686755 <6>[ 2.234506] mmc0: Command Queue Engine enabled
10667 08:15:17.693087 <6>[ 2.234529] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10668 08:15:17.699713 <6>[ 2.235415] mmcblk0: mmc0:0001 DA4128 116 GiB
10669 08:15:17.702860 <6>[ 2.239602] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10670 08:15:17.709920 <6>[ 2.240699] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10671 08:15:17.712890 <6>[ 2.241344] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10672 08:15:17.719641 <6>[ 2.241998] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (506:0)
10673 08:15:17.726204 <5>[ 2.473317] Key type dns_resolver registered
10674 08:15:17.736607 <6>[ 2.480387] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
10675 08:15:17.743035 <6>[ 2.489677] registered taskstats version 1
10676 08:15:17.746453 <5>[ 2.494284] Loading compiled-in X.509 certificates
10677 08:15:17.753986 <6>[ 2.501555] Demotion targets for Node 0: null
10678 08:15:17.783812 <6>[ 2.531071] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10679 08:15:17.790446 <6>[ 2.538007] xhci-mtk 11200000.usb: xHCI Host Controller
10680 08:15:17.797653 <6>[ 2.543501] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10681 08:15:17.807513 <6>[ 2.551404] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000200010
10682 08:15:17.813833 <6>[ 2.560864] xhci-mtk 11200000.usb: irq 270, io mem 0x11200000
10683 08:15:17.820527 <6>[ 2.566968] xhci-mtk 11200000.usb: xHCI Host Controller
10684 08:15:17.827251 <6>[ 2.572451] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10685 08:15:17.833712 <6>[ 2.580106] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10686 08:15:17.840704 <6>[ 2.588045] hub 1-0:1.0: USB hub found
10687 08:15:17.843798 <6>[ 2.592064] hub 1-0:1.0: 1 port detected
10688 08:15:17.853904 <6>[ 2.596347] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10689 08:15:17.856941 <6>[ 2.605147] hub 2-0:1.0: USB hub found
10690 08:15:17.860497 <6>[ 2.609172] hub 2-0:1.0: 1 port detected
10691 08:15:17.869131 <6>[ 2.616770] mtk-msdc 11f70000.mmc: Got CD GPIO
10692 08:15:17.879495 <4>[ 2.623153] rt5682 1-001a: Using default DAI clk names: rt5682-dai-wclk, rt5682-dai-bclk
10693 08:15:18.265651 <6>[ 3.009705] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10694 08:15:18.423095 <6>[ 3.170785] hub 1-1:1.0: USB hub found
10695 08:15:18.426696 <6>[ 3.175212] hub 1-1:1.0: 4 ports detected
10696 08:15:18.546602 <6>[ 3.293606] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10697 08:15:18.577220 <6>[ 3.324257] hub 2-1:1.0: USB hub found
10698 08:15:18.579714 <6>[ 3.328849] hub 2-1:1.0: 3 ports detected
10699 08:15:18.776535 <6>[ 3.493587] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10700 08:15:18.880538 <6>[ 3.628318] hub 1-1.4:1.0: USB hub found
10701 08:15:18.883897 <6>[ 3.632874] hub 1-1.4:1.0: 2 ports detected
10702 08:15:18.960992 <6>[ 3.705466] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10703 08:15:19.181091 <6>[ 3.925631] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10704 08:15:19.377175 <6>[ 4.121267] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10705 08:15:30.788837 <6>[ 15.537769] clk: Disabling unused clocks
10706 08:15:30.795730 <6>[ 15.543162] PM: genpd: Disabling unused power domains
10707 08:15:30.798614 <6>[ 15.548517] ALSA device list:
10708 08:15:30.802052 <6>[ 15.551767] No soundcards found.
10709 08:15:30.812099 <6>[ 15.561084] Freeing unused kernel memory: 10880K
10710 08:15:30.815652 <6>[ 15.566207] Run /init as init process
10711 08:15:30.843802 Starting syslogd: OK
10712 08:15:30.847943 Starting klogd: OK
10713 08:15:30.856414 Running sysctl: OK
10714 08:15:30.866612 Populating /dev using udev: <30>[ 15.614577] udevd[148]: starting version 3.2.9
10715 08:15:30.874430 <27>[ 15.623218] udevd[148]: specified user 'tss' unknown
10716 08:15:30.880717 <27>[ 15.628686] udevd[148]: specified group 'tss' unknown
10717 08:15:30.884102 <30>[ 15.635031] udevd[149]: starting eudev-3.2.9
10718 08:15:30.905909 <27>[ 15.654786] udevd[149]: specified user 'tss' unknown
10719 08:15:30.912541 <27>[ 15.660440] udevd[149]: specified group 'tss' unknown
10720 08:15:31.007560 <6>[ 15.756240] pstore: Using crash dump compression: deflate
10721 08:15:31.014357 <6>[ 15.762177] pstore: Registered ramoops as persistent store backend
10722 08:15:31.020391 <6>[ 15.768737] ramoops: using 0x100000@0xffe66000, ecc: 0
10723 08:15:31.171495 <6>[ 15.916781] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10724 08:15:31.178006 <6>[ 15.924686] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10725 08:15:31.187718 <6>[ 15.933465] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10726 08:15:31.208671 <6>[ 15.957609] usbcore: registered new device driver onboard-usb-dev
10727 08:15:31.223483 <6>[ 15.969171] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10728 08:15:31.227057 <6>[ 15.974754] usb 1-1.4: USB disconnect, device number 3
10729 08:15:31.233325 <6>[ 15.980696] mc: Linux media interface: v0.10
10730 08:15:31.237171 <6>[ 15.981929] usb 1-1.4.1: USB disconnect, device number 4
10731 08:15:31.243741 <6>[ 15.987001] remoteproc remoteproc0: scp is available
10732 08:15:31.249848 <6>[ 15.987212] usbcore: registered new device driver r8152-cfgselector
10733 08:15:31.256641 <6>[ 15.993347] usb 1-1.4.2: USB disconnect, device number 5
10734 08:15:31.259830 <6>[ 15.998379] remoteproc remoteproc0: powering up scp
10735 08:15:31.270028 <6>[ 16.014808] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10736 08:15:31.276289 <6>[ 16.023425] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10737 08:15:31.279802 <6>[ 16.023594] videodev: Linux video capture interface: v2.00
10738 08:15:31.297505 <6>[ 16.042856] sbs-battery 8-000b: sbs-battery: battery gas gauge device registered
10739 08:15:31.306951 <6>[ 16.055766] Bluetooth: Core ver 2.22
10740 08:15:31.310279 <6>[ 16.060236] NET: Registered PF_BLUETOOTH protocol family
10741 08:15:31.318463 <6>[ 16.067454] Bluetooth: HCI device and connection manager initialized
10742 08:15:31.325177 <6>[ 16.068355] usbcore: registered new interface driver uvcvideo
10743 08:15:31.331694 <6>[ 16.074908] Bluetooth: HCI socket layer initialized
10744 08:15:31.338422 <6>[ 16.077544] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10745 08:15:31.345123 <6>[ 16.077570] pci_bus 0000:00: root bus resource [bus 00-ff]
10746 08:15:31.351483 <6>[ 16.077583] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10747 08:15:31.361182 <6>[ 16.077589] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10748 08:15:31.367928 <6>[ 16.077678] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400 PCIe Root Port
10749 08:15:31.377789 <6>[ 16.077698] mediatek-mipi-tx 11e50000.dsi-phy: can't get nvmem_cell_get, ignore it
10750 08:15:31.384496 <6>[ 16.077706] pci 0000:00:00.0: BAR 0 [mem 0x00000000-0x00003fff 64bit pref]
10751 08:15:31.387468 <6>[ 16.077727] pci 0000:00:00.0: PCI bridge to [bus 00]
10752 08:15:31.394093 <6>[ 16.077734] pci 0000:00:00.0: bridge window [io 0x0000-0x0fff]
10753 08:15:31.404336 <6>[ 16.077742] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff]
10754 08:15:31.410629 <6>[ 16.077754] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff 64bit pref]
10755 08:15:31.414261 <6>[ 16.077877] pci 0000:00:00.0: supports D1 D2
10756 08:15:31.420922 <6>[ 16.077883] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10757 08:15:31.430747 <6>[ 16.080142] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10758 08:15:31.437346 <6>[ 16.080401] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000 PCIe Endpoint
10759 08:15:31.447274 <6>[ 16.081945] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10760 08:15:31.450498 <6>[ 16.085502] Bluetooth: L2CAP socket layer initialized
10761 08:15:31.457500 <6>[ 16.085624] Bluetooth: SCO socket layer initialized
10762 08:15:31.464029 <6>[ 16.092962] pci 0000:01:00.0: BAR 0 [mem 0x00000000-0x000fffff 64bit pref]
10763 08:15:31.470750 <4>[ 16.106334] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
10764 08:15:31.480528 <4>[ 16.110016] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10765 08:15:31.487102 <4>[ 16.110037] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10766 08:15:31.494844 <6>[ 16.115413] pci 0000:01:00.0: BAR 2 [mem 0x00000000-0x00003fff 64bit pref]
10767 08:15:31.500591 <6>[ 16.128049] panfrost 13000000.gpu: clock rate = 357999878
10768 08:15:31.507339 <4>[ 16.129895] elants_i2c 0-0010: supply vccio not found, using dummy regulator
10769 08:15:31.517209 <6>[ 16.130865] pci 0000:01:00.0: BAR 4 [mem 0x00000000-0x00000fff 64bit pref]
10770 08:15:31.523531 <6>[ 16.141151] panfrost 13000000.gpu: mali-g57 id 0x9093 major 0x0 minor 0x0 status 0x0
10771 08:15:31.533590 <6>[ 16.142102] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/ovl@14005000
10772 08:15:31.540123 <6>[ 16.142128] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/ovl@14006000
10773 08:15:31.550038 <6>[ 16.142147] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/rdma@14007000
10774 08:15:31.556718 <6>[ 16.142160] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/color@14009000
10775 08:15:31.566468 <6>[ 16.142169] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/ccorr@1400a000
10776 08:15:31.576773 <6>[ 16.142184] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/aal@1400b000
10777 08:15:31.583303 <6>[ 16.142197] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/gamma@1400c000
10778 08:15:31.592712 <6>[ 16.142262] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/dsi@14010000
10779 08:15:31.602976 <6>[ 16.142273] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/ovl@14014000
10780 08:15:31.609832 <6>[ 16.142285] mediatek-drm mediatek-drm.11.auto: Adding component match for /soc/rdma@14015000
10781 08:15:31.616066 <6>[ 16.143448] pci 0000:01:00.0: supports D1 D2
10782 08:15:31.622657 <6>[ 16.149545] panfrost 13000000.gpu: features: 00000000,000019f7, issues: 00000003,80000400
10783 08:15:31.636088 <6>[ 16.149548] panfrost 13000000.gpu: Features: L2:0x07130206 Shader:0x00000000 Tiler:0x00000809 Mem:0x101 MMU:0x00002830 AS:0xff JS:0x7
10784 08:15:31.642404 <6>[ 16.156618] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10785 08:15:31.649012 <6>[ 16.164579] panfrost 13000000.gpu: shader_present=0x50045 l2_present=0x1
10786 08:15:31.655683 <6>[ 16.165184] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10787 08:15:31.665611 <6>[ 16.165499] [drm] Initialized panfrost 1.2.0 20180908 for 13000000.gpu on minor 0
10788 08:15:31.671899 <6>[ 16.169120] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10789 08:15:31.678485 <6>[ 16.169132] remoteproc remoteproc0: remote processor scp is now up
10790 08:15:31.685290 <6>[ 16.181401] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10791 08:15:31.692110 <6>[ 16.184636] r8152 2-1.3:1.0 eth0: v1.12.13
10792 08:15:31.698691 <6>[ 16.191930] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]: assigned
10793 08:15:31.708507 <6>[ 16.192113] elan_i2c 2-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10794 08:15:31.718270 <6>[ 16.192498] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-2/2-0015/input/input2
10795 08:15:31.728323 <4>[ 16.196199] sbs-battery 8-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10796 08:15:31.731392 <4>[ 16.196199] Fallback method does not support PEC.
10797 08:15:31.738070 <6>[ 16.200268] usbcore: registered new interface driver r8152
10798 08:15:31.744919 <6>[ 16.205510] pci 0000:00:00.0: BAR 0 [mem 0x12200000-0x12203fff 64bit pref]: assigned
10799 08:15:31.754900 <6>[ 16.205520] pci 0000:01:00.0: BAR 0 [mem 0x12000000-0x120fffff 64bit pref]: assigned
10800 08:15:31.757894 <6>[ 16.206351] hub 1-1:1.0: USB hub found
10801 08:15:31.760924 <6>[ 16.206582] hub 1-1:1.0: 4 ports detected
10802 08:15:31.767691 <6>[ 16.208340] r8152-cfgselector 2-1.3: USB disconnect, device number 3
10803 08:15:31.778189 <3>[ 16.213366] power_supply sbs-8-000b: driver failed to report `time_to_empty_now' property: -5
10804 08:15:31.784340 <6>[ 16.217777] pci 0000:01:00.0: BAR 2 [mem 0x12100000-0x12103fff 64bit pref]: assigned
10805 08:15:31.794298 <6>[ 16.242062] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-0/0-0010/input/input3
10806 08:15:31.803768 <6>[ 16.242195] pci 0000:01:00.0: BAR 4 [mem 0x12104000-0x12104fff 64bit pref]: assigned
10807 08:15:31.810470 <3>[ 16.246332] power_supply sbs-8-000b: driver failed to report `time_to_empty_now' property: -5
10808 08:15:31.820429 <4>[ 16.330627] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10809 08:15:31.826997 <6>[ 16.338243] pci 0000:00:00.0: PCI bridge to [bus 01]
10810 08:15:31.830389 <6>[ 16.347904] usbcore: registered new interface driver cdc_ether
10811 08:15:31.840344 <6>[ 16.349610] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10812 08:15:31.849949 <6>[ 16.349622] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10813 08:15:31.856935 <6>[ 16.355494] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10814 08:15:31.863268 <6>[ 16.356082] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10815 08:15:31.870161 <4>[ 16.374366] rt5682 1-001a: ASoC: source widget I2S1 overwritten
10816 08:15:31.876436 <6>[ 16.377831] usbcore: registered new interface driver btusb
10817 08:15:31.879980 <6>[ 16.378273] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10818 08:15:31.886297 <6>[ 16.378593] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10819 08:15:31.893031 <6>[ 16.391710] usbcore: registered new interface driver r8153_ecm
10820 08:15:31.899558 <6>[ 16.463314] cros-ec-dev cros-ec-dev.12.auto: CrOS System Control Processor MCU detected
10821 08:15:31.909442 <5>[ 16.466419] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10822 08:15:31.916358 <5>[ 16.493077] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10823 08:15:31.922531 <6>[ 16.502782] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10824 08:15:31.932405 <5>[ 16.508185] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10825 08:15:31.939325 <6>[ 16.517350] usb 1-1.4: new high-speed USB device number 6 using xhci-mtk
10826 08:15:31.945929 <4>[ 16.523202] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10827 08:15:31.956068 <6>[ 16.556334] panel-simple-dp-aux aux-3-0058: Detected IVO R140NWF5 RH (0x057d)
10828 08:15:31.959419 <6>[ 16.556707] cfg80211: failed to load regulatory.db
10829 08:15:31.962240 <6>[ 16.664840] hub 1-1.4:1.0: USB hub found
10830 08:15:31.968729 <6>[ 16.709722] hub 2-1:1.0: USB hub found
10831 08:15:31.972368 <6>[ 16.713885] hub 1-1.4:1.0: 2 ports detected
10832 08:15:31.978716 <6>[ 16.714498] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10833 08:15:31.985399 <6>[ 16.714616] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10834 08:15:31.991865 <6>[ 16.716967] mt7921e 0000:01:00.0: ASIC revision: 79610010
10835 08:15:31.995125 <6>[ 16.717934] hub 2-1:1.0: 3 ports detected
10836 08:15:32.029436 <6>[ 16.775117] input: mt8192_mt6359_rt1015p_rt5682 Headset Jack as /devices/platform/sound/sound/card0/input4
10837 08:15:32.045964 <6>[ 16.791443] SVSB_GPU_LOW: svs_init02_isr_handler: VOP74~30:0x1c1d1f20~0x21222325, DC:0x00000000
10838 08:15:32.055647 <6>[ 16.801055] SVSB_GPU_HIGH: svs_init02_isr_handler: VOP74~30:0x1a2d2e30~0x32333537, DC:0x00000000
10839 08:15:32.065612 <6>[ 16.810483] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10840 08:15:32.065758 <6>[ 16.810483]
10841 08:15:32.075283 <6>[ 16.816914] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10842 08:15:32.081934 <6>[ 16.829204] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10843 08:15:32.092075 <6>[ 16.837602] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10844 08:15:32.101552 <6>[ 16.845971] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10845 08:15:32.108708 <6>[ 16.854324] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10846 08:15:32.118269 <6>[ 16.862678] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10847 08:15:32.125282 <6>[ 16.871031] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10848 08:15:32.134836 <6>[ 16.879385] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10849 08:15:32.141279 <6>[ 16.887883] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10850 08:15:32.151674 <6>[ 16.896270] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10851 08:15:32.157882 <6>[ 16.904621] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10852 08:15:32.167767 <6>[ 16.912965] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10853 08:15:32.174474 <6>[ 16.921307] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10854 08:15:32.184497 <6>[ 16.929649] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10855 08:15:32.190810 <6>[ 16.937989] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10856 08:15:32.199482 <6>[ 16.948299] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10857 08:15:32.207920 <6>[ 16.956954] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10858 08:15:32.215376 <6>[ 16.964311] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10859 08:15:32.219197 done
10860 08:15:32.225712 <6>[ 16.973825] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10861 08:15:32.235693 Saving random seed: <6>[ 16.983653] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10862 08:15:32.235834 OK
10863 08:15:32.249014 <6>[ 16.990940] mediatek-drm mediatek-drm.11.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops [mediatek_drm])
10864 08:15:32.258672 <6>[ 17.001507] mediatek-drm mediatek-drm.11.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops [mediatek_drm])
10865 08:15:32.268510 <6>[ 17.012020] mediatek-drm mediatek-drm.11.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops [mediatek_drm])
10866 08:15:32.278668 <6>[ 17.022707] mediatek-drm mediatek-drm.11.auto: bound 14009000.color (ops mtk_disp_color_component_ops [mediatek_drm])
10867 08:15:32.285065 <6>[ 17.025328] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10868 08:15:32.298335 <6>[ 17.033569] mediatek-drm mediatek-drm.11.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops [mediatek_drm])
10869 08:15:32.308401 <6>[ 17.033582] mediatek-drm mediatek-drm.11.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops [mediatek_drm])
10870 08:15:32.317978 <6>[ 17.033592] mediatek-drm mediatek-drm.11.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops [mediatek_drm])
10871 08:15:32.321096 Starting network: OK
10872 08:15:32.331153 Starting d<6>[ 17.074989] mediatek-drm mediatek-drm.11.auto: bound 14010000.dsi (ops mtk_dsi_component_ops [mediatek_drm])
10873 08:15:32.340949 <6>[ 17.076828] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10874 08:15:32.351468 <6>[ 17.085874] mediatek-drm mediatek-drm.11.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops [mediatek_drm])
10875 08:15:32.364081 ropbear sshd: <6>[ 17.105155] mediatek-drm mediatek-drm.11.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops [mediatek_drm])
10876 08:15:32.373902 <6>[ 17.117091] mediatek-drm mediatek-drm.11.auto: Not creating crtc 1 because component 10 is disabled or missing
10877 08:15:32.380455 <6>[ 17.128289] NET: Registered PF_INET6 protocol family
10878 08:15:32.387502 <6>[ 17.128316] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.11.auto on minor 1
10879 08:15:32.390571 <6>[ 17.134482] Segment Routing with IPv6
10880 08:15:32.396959 <6>[ 17.145870] In-situ OAM (IOAM) with IPv6
10881 08:15:32.403740 <6>[ 17.147939] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10882 08:15:32.403831 OK
10883 08:15:32.413294 /bin/sh: can't access tty; job control turned off
10884 08:15:32.413663 Matched prompt #10: / #
10886 08:15:32.413876 Setting prompt string to ['/ #']
10887 08:15:32.413972 end: 2.2.5.1 login-action (duration 00:00:18) [common]
10889 08:15:32.414169 end: 2.2.5 auto-login-action (duration 00:00:18) [common]
10890 08:15:32.414257 start: 2.2.6 expect-shell-connection (timeout 00:03:05) [common]
10891 08:15:32.414328 Setting prompt string to ['/ #']
10892 08:15:32.414388 Forcing a shell prompt, looking for ['/ #']
10894 08:15:32.464616 / #
10895 08:15:32.464802 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10896 08:15:32.464881 Waiting using forced prompt support (timeout 00:02:30)
10897 08:15:32.469909
10898 08:15:32.470204 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10899 08:15:32.470301 start: 2.2.7 export-device-env (timeout 00:03:04) [common]
10900 08:15:32.470400 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10901 08:15:32.470487 end: 2.2 depthcharge-retry (duration 00:01:56) [common]
10902 08:15:32.470570 end: 2 depthcharge-action (duration 00:01:56) [common]
10903 08:15:32.470655 start: 3 lava-test-retry (timeout 00:01:00) [common]
10904 08:15:32.470739 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10905 08:15:32.470812 Using namespace: common
10907 08:15:32.571171 / # #
10908 08:15:32.571348 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10909 08:15:32.571466 <6>[ 17.229470] usb 2-1.3: new SuperSpeed USB device number 4 using xhci-mtk
10910 08:15:32.576435 #
10911 08:15:32.576702 Using /lava-13529852
10913 08:15:32.677027 / # export SHELL=/bin/sh
10914 08:15:32.682609 export SHELL=/bin/sh
10916 08:15:32.783138 / # . /lava-13529852/environment
10917 08:15:32.788363 . /lava-13529852/environment
10919 08:15:32.888995 / # /lava-13529852/bin/lava-test-runner /lava-13529852/0
10920 08:15:32.889182 Test shell timeout: 10s (minimum of the action and connection timeout)
10921 08:15:32.889596 <6>[ 17.337535] usb 1-1.4.2: new high-speed USB device number 8 using xhci-mtk
10922 08:15:32.889673 <4>[ 17.444711] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10923 08:15:32.889738 <3>[ 17.444735] Bluetooth: hci0: Failed to load firmware file (-2)
10924 08:15:32.889799 <3>[ 17.444742] Bluetooth: hci0: Failed to set up firmware (-2)
10925 08:15:32.889859 <4>[ 17.444747] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10926 08:15:32.889919 <6>[ 17.517850] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 4 using xhci-mtk
10927 08:15:32.889976 <6>[ 17.520197] Console: switching to colour frame buffer device 240x67
10928 08:15:32.890032 <4>[ 17.549322] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10929 08:15:32.890088 <4>[ 17.549354] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10930 08:15:32.890143 <6>[ 17.622331] mediatek-drm mediatek-drm.11.auto: [drm] fb0: mediatekdrmfb frame buffer device
10931 08:15:32.890199 <4>[ 17.631015] ttyS ttyS0: 1 input overrun(s)
10932 08:15:32.933571 /lava-13529852/bin/lava-test-run<6>[ 17.645676] usb 1-1.4: USB disconnect, device number 6
10933 08:15:32.933732 <6>[ 17.651102] usb 1-1.4.1: USB disconnect, device number 7
10934 08:15:32.933802
10935 08:15:32.933864 /bin/sh: /lava-13529852/bin/lava<6>[ 17.659201] usb 1-1.4.2: USB disconnect, device number 8
10936 08:15:32.933923 -test-run: not found
10937 08:15:32.934001 / # <6>[ 17.668085] r8152 2-1.3:1.0 eth0: v1.12.13
10938 08:15:32.934063 <6>[ 17.668814] hub 1-1:1.0: USB hub found
10939 08:15:32.934120 <6>[ 17.673569] r8152-cfgselector 2-1.3: USB disconnect, device number 4
10940 08:15:32.934177 <6>[ 17.677087] hub 1-1:1.0: 4 ports detected
10941 08:15:32.941306 <6>[ 17.690736] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 1
10942 08:15:32.953135 <6>[ 17.699155] mtk-vcodec-dec 16000000.video-codec: Adding to iommu group 1
10943 08:15:33.004724 <6>[ 17.750657] mtk-vdec-comp 16010000.video-codec: Adding to iommu group 1
10944 08:15:33.011388 <6>[ 17.758699] mtk-vdec-comp 16025000.video-codec: Adding to iommu group 1
10945 08:15:33.140341 <6>[ 17.886081] usb 2-1: reset SuperSpeed USB device number 2 using xhci-mtk
10946 08:15:33.162591 <6>[ 17.911941] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10947 08:15:33.267370 <6>[ 18.013495] usb 1-1.4: new high-speed USB device number 9 using xhci-mtk
10948 08:15:33.399668 <6>[ 18.149061] hub 1-1.4:1.0: USB hub found
10949 08:15:33.402982 <6>[ 18.153729] hub 1-1.4:1.0: 2 ports detected
10950 08:15:33.491866 <6>[ 18.237729] usb 2-1.3: new SuperSpeed USB device number 5 using xhci-mtk
10951 08:15:33.600328 <6>[ 18.346183] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 5 using xhci-mtk
10952 08:15:33.638158 <4>[ 18.384037] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10953 08:15:33.648145 <4>[ 18.393193] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10954 08:15:33.686427 <6>[ 18.435528] r8152 2-1.3:1.0 eth0: v1.12.13
10955 08:15:33.692703 <6>[ 18.440996] r8152-cfgselector 2-1.3: USB disconnect, device number 5
10956 08:15:33.716265 <6>[ 18.461437] usb 1-1.4.1: new high-speed USB device number 10 using xhci-mtk
10957 08:15:33.746422 <6>[ 18.495466] hub 2-1:1.0: USB hub found
10958 08:15:33.749735 <6>[ 18.499806] hub 2-1:1.0: 3 ports detected
10959 08:15:33.836548 <6>[ 18.582295] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10960 08:15:33.932178 <6>[ 18.677559] usb 1-1.4.2: new high-speed USB device number 11 using xhci-mtk
10961 08:15:34.051134 <4>[ 18.792950] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10962 08:15:34.054203 <6>[ 18.793097] usb 1-1.4.1: USB disconnect, device number 10
10963 08:15:34.060642 <3>[ 18.803492] Bluetooth: hci0: Failed to load firmware file (-2)
10964 08:15:34.067529 <3>[ 18.803497] Bluetooth: hci0: Failed to set up firmware (-2)
10965 08:15:34.077255 <4>[ 18.803501] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10966 08:15:34.084367 <6>[ 18.833105] usb 1-1.4.2: USB disconnect, device number 11
10967 08:15:34.092051 <6>[ 18.840667] hub 1-1.4:1.0: USB hub found
10968 08:15:34.095083 <6>[ 18.845240] hub 1-1.4:1.0: 2 ports detected
10969 08:15:34.147985 <6>[ 18.893467] usb 2-1.3: new SuperSpeed USB device number 6 using xhci-mtk
10970 08:15:34.256933 <6>[ 19.002245] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 6 using xhci-mtk
10971 08:15:34.294029 <4>[ 19.039463] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10972 08:15:34.303668 <4>[ 19.048602] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10973 08:15:34.342866 <6>[ 19.091613] r8152 2-1.3:1.0 eth0: v1.12.13
10974 08:15:34.350230 <6>[ 19.096476] r8152-cfgselector 2-1.3: USB disconnect, device number 6
10975 08:15:34.371721 <6>[ 19.117429] usb 1-1.4.1: new high-speed USB device number 12 using xhci-mtk
10976 08:15:34.481455 <6>[ 19.226759] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10977 08:15:34.604776 <6>[ 19.350155] usb 2-1: reset SuperSpeed USB device number 2 using xhci-mtk
10978 08:15:34.708661 <6>[ 19.453553] usb 1-1.4.2: new high-speed USB device number 13 using xhci-mtk
10979 08:15:34.828305 <4>[ 19.570367] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10980 08:15:34.835067 <3>[ 19.580924] Bluetooth: hci0: Failed to load firmware file (-2)
10981 08:15:34.838281 <3>[ 19.587021] Bluetooth: hci0: Failed to set up firmware (-2)
10982 08:15:34.848181 <4>[ 19.592848] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10983 08:15:34.931925 <6>[ 19.677667] usb 2-1.3: new SuperSpeed USB device number 7 using xhci-mtk
10984 08:15:35.040574 <6>[ 19.786127] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 7 using xhci-mtk
10985 08:15:35.072640 <4>[ 19.818322] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10986 08:15:35.082259 <4>[ 19.827499] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10987 08:15:35.118319 <6>[ 19.867560] r8152 2-1.3:1.0 eth0: v1.12.13
10988 08:16:01.519964 <6>[ 46.161644] vpu: disabling
10989 08:16:01.520850 <6>[ 46.164753] vproc2: disabling
10990 08:16:01.521249 <6>[ 46.168118] vproc1: disabling
10991 08:16:01.521660 <6>[ 46.171425] vaud18: disabling
10992 08:16:01.522006 <6>[ 46.175180] va09: disabling
10993 08:16:01.522336 <6>[ 46.178344] vsram_md: disabling
10994 08:16:01.522676 <6>[ 46.185904] pp1800_dpbrdg: disabling
10995 08:16:01.522996 <6>[ 46.189773] pp1000_dpbrdg: disabling
10996 08:16:01.523310 <6>[ 46.193648] pp3300_dpbrdg: disabling
10998 08:16:32.471559 end: 3.1 lava-test-shell (duration 00:01:00) [common]
11000 08:16:32.472636 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
11002 08:16:32.473546 end: 3 lava-test-retry (duration 00:01:00) [common]
11004 08:16:32.474617 Cleaning after the job
11005 08:16:32.475055 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13529852/tftp-deploy-9psta492/ramdisk
11006 08:16:32.486403 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13529852/tftp-deploy-9psta492/kernel
11007 08:16:32.517165 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13529852/tftp-deploy-9psta492/dtb
11008 08:16:32.517489 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13529852/tftp-deploy-9psta492/modules
11009 08:16:32.526963 start: 4.1 power-off (timeout 00:00:30) [common]
11010 08:16:32.527196 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11011 08:16:32.611453 >> Command sent successfully.
11012 08:16:32.622628 Returned 0 in 0 seconds
11013 08:16:32.724149 end: 4.1 power-off (duration 00:00:00) [common]
11015 08:16:32.725739 start: 4.2 read-feedback (timeout 00:10:00) [common]
11016 08:16:32.727287 Listened to connection for namespace 'common' for up to 1s
11017 08:16:33.727554 Finalising connection for namespace 'common'
11018 08:16:33.727766 Disconnecting from shell: Finalise
11019 08:16:33.828122 end: 4.2 read-feedback (duration 00:00:01) [common]
11020 08:16:33.828303 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13529852
11021 08:16:33.879264 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13529852
11022 08:16:33.879488 TestError: A test failed to run, look at the error message.