Trying 192.168.56.21... Connected to conserv1. Escape character is '^]'. ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux) G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0. bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 L0:00000000 L1:20000703 L2:00008067 L3:14000000 B2:00402000 B1:e0f83180 TE: 58159 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz Board ID = 1 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 00012ab4 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01 board id: 1 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done fastboot data load fastboot data verify verify result: 266 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg LPDDR4 probe ddr clk to 1584MHz Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0 dmc_version 0001 Check phy result INFO : End of CA training INFO : End of initialization INFO : Training has run successfully! Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of Write leveling coarse delay INFO : Training has run successfully! Check phy result INFO : End of initialization INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! channel==0 RxClkDly_Margin_A0==88 ps 9 TxDqDly_Margin_A0==98 ps 10 RxClkDly_Margin_A1==88 ps 9 TxDqDly_Margin_A1==98 ps 10 TrainedVREFDQ_A0==74 TrainedVREFDQ_A1==74 VrefDac_Margin_A0==25 DeviceVref_Margin_A0==40 VrefDac_Margin_A1==25 DeviceVref_Margin_A1==40 channel==1 RxClkDly_Margin_A0==98 ps 10 TxDqDly_Margin_A0==88 ps 9 RxClkDly_Margin_A1==88 ps 9 TxDqDly_Margin_A1==88 ps 9 TrainedVREFDQ_A0==77 TrainedVREFDQ_A1==77 VrefDac_Margin_A0==23 DeviceVref_Margin_A0==37 VrefDac_Margin_A1==23 DeviceVref_Margin_A1==37 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060 2D training succeed aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19 auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00e00024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass 100bdlr_step_size ps== 420 result report boot times 0Enable ddr reg access Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0 0.0;M3 CHK:0;cm4_sp_mode 0 MVN_1=0x00000000 MVN_2=0x00000000 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz] OPS=0x10 ring efuse init chipver efuse init 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 [0.018961 Inits done] secure task start! high task start! low task start! run into bl31 NOTICE: BL31: v1.3(release):4fc40b1 NOTICE: BL31: Built : 15:58:17, May 22 2019 NOTICE: BL31: G12A normal boot! NOTICE: BL31: BL33 decompress pass ERROR: Error initializing runtime service opteed_fast U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC Model: Libre Computer AML-A311D-CC Alta SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2) DRAM: 2 GiB (effective 3.8 GiB) Core: 408 devices, 31 uclasses, devicetree: separate WDT: Not starting watchdog@f0d0 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0 Loading Environment from FAT... Card did not respond to voltage select! : -110 ** Bad device specification mmc 0 ** Card did not respond to voltage select! : -110 ** Bad device specification mmc 0 ** Couldn't find partition mmc 0 Card did not respond to voltage select! : -110 ** Bad device specification mmc 0 ** Couldn't find partition mmc 0 Error: could not access storage. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0. bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 L0:00000000 L1:20000703 L2:00008067 L3:14000000 B2:00402000 B1:e0f83180 TE: 58159 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz Board ID = 1 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 00012ab5 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01 board id: 1 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done fastboot data load fastboot data verify verify result: 266 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg LPDDR4 probe ddr clk to 1584MHz Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0 dmc_version 0001 Check phy result INFO : End of CA training INFO : End of initialization INFO : Training has run successfully! Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of Write leveling coarse delay INFO : Training has run successfully! Check phy result INFO : End of initialization INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! channel==0 RxClkDly_Margin_A0==88 ps 9 TxDqDly_Margin_A0==98 ps 10 RxClkDly_Margin_A1==88 ps 9 TxDqDly_Margin_A1==88 ps 9 TrainedVREFDQ_A0==74 TrainedVREFDQ_A1==74 VrefDac_Margin_A0==25 DeviceVref_Margin_A0==40 VrefDac_Margin_A1==25 DeviceVref_Margin_A1==40 channel==1 RxClkDly_Margin_A0==88 ps 9 TxDqDly_Margin_A0==88 ps 9 RxClkDly_Margin_A1==88 ps 9 TxDqDly_Margin_A1==98 ps 10 TrainedVREFDQ_A0==77 TrainedVREFDQ_A1==77 VrefDac_Margin_A0==23 DeviceVref_Margin_A0==37 VrefDac_Margin_A1==24 DeviceVref_Margin_A1==37 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f 2D training succeed aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19 auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00e00024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass 100bdlr_step_size ps== 420 result report boot times 0Enable ddr reg access Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0 0.0;M3 CHK:0;cm4_sp_mode 0 MVN_1=0x00000000 MVN_2=0x00000000 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz] OPS=0x10 ring efuse init chipver efuse init 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 [0.018960 Inits done] secure task start! high task start! low task start! run into bl31 NOTICE: BL31: v1.3(release):4fc40b1 NOTICE: BL31: Built : 15:58:17, May 22 2019 NOTICE: BL31: G12A normal boot! NOTICE: BL31: BL33 decompress pass ERROR: Error initializing runtime service opteed_fast U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC Model: Libre Computer AML-A311D-CC Alta SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2) DRAM: 2 GiB (effective 3.8 GiB) Core: 408 devices, 31 uclasses, devicetree: separate WDT: Not starting watchdog@f0d0 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0 Loading Environment from FAT... Card did not respond to voltage select! : -110 ** Bad device specification mmc 0 ** Card did not respond to voltage select! : -110 ** Bad device specification mmc 0 ** Couldn't find partition mmc 0 Card did not respond to voltage select! : -110 ** Bad device specification mmc 0 ** Couldn't find partition mmc 0 Error: could not access storage. Net: eth0: ethernet@ff3f0000 starting USB... Bus usb@ff500000: Register 3000140 NbrPorts 3 Starting the controller USB XHCI 1.10 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0. bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 L0:00000000 L1:20000703 L2:00008067 L3:14000000 B2:00402000 B1:e0f83180 TE: 58159 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz Board ID = 1 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 00012ab5 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01 board id: 1 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done fastboot data load fastboot data verify verify result: 266 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg LPDDR4 probe ddr clk to 1584MHz Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0 dmc_version 0001 Check phy result INFO : End of CA training INFO : End of initialization INFO : Training has run successfully! Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of Write leveling coarse delay INFO : Training has run successfully! Check phy result INFO : End of initialization INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! channel==0 RxClkDly_Margin_A0==88 ps 9 TxDqDly_Margin_A0==98 ps 10 RxClkDly_Margin_A1==88 ps 9 TxDqDly_Margin_A1==88 ps 9 TrainedVREFDQ_A0==74 TrainedVREFDQ_A1==74 VrefDac_Margin_A0==24 DeviceVref_Margin_A0==40 VrefDac_Margin_A1==24 DeviceVref_Margin_A1==40 channel==1 RxClkDly_Margin_A0==98 ps 10 TxDqDly_Margin_A0==98 ps 10 RxClkDly_Margin_A1==88 ps 9 TxDqDly_Margin_A1==88 ps 9 TrainedVREFDQ_A0==77 TrainedVREFDQ_A1==77 VrefDac_Margin_A0==22 DeviceVref_Margin_A0==37 VrefDac_Margin_A1==24 DeviceVref_Margin_A1==37 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060 2D training succeed aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19 auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00e00024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass 100bdlr_step_size ps== 420 result report boot times 0Enable ddr reg access Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0 0.0;M3 CHK:0;cm4_sp_mode 0 MVN_1=0x00000000 MVN_2=0x00000000 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz] OPS=0x10 ring efuse init chipver efuse init 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 [0.018960 Inits done] secure task start! high task start! low task start! run into bl31 NOTICE: BL31: v1.3(release):4fc40b1 NOTICE: BL31: Built : 15:58:17, May 22 2019 NOTICE: BL31: G12A normal boot! NOTICE: BL31: BL33 decompress pass ERROR: Error initializing runtime service opteed_fast U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC Model: Libre Computer AML-A311D-CC Alta SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2) DRAM: 2 GiB (effective 3.8 GiB) Core: 408 devices, 31 uclasses, devicetree: separate WDT: Not starting watchdog@f0d0 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0 Loading Environment from FAT... Card did not respond to voltage select! : -110 ** Bad device specification mmc 0 ** Card did not respond to voltage select! : -110 ** Bad device specification mmc 0 ** Couldn't find partition mmc 0 Card did not respond to voltage select! : -110 ** Bad device specification mmc 0 ** Couldn't find partition mmc 0 Error: could not access storage. Net: eth0: ethernet@ff3f0000 starting USB... Bus usb@ff500000: Register 3000140 NbrPorts 3 Starting the controller USB XHCI 1.10 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0. bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 L0:00000000 L1:20000703 L2:00008067 L3:14000000 B2:00402000 B1:e0f83180 TE: 58124 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz Board ID = 1 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 00012a92 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01 board id: 1 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done fastboot data load fastboot data verify verify result: 266 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg LPDDR4 probe ddr clk to 1584MHz Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0 dmc_version 0001 Check phy result INFO : End of CA training INFO : End of initialization INFO : Training has run successfully! Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of Write leveling coarse delay INFO : Training has run successfully! Check phy result INFO : End of initialization INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! channel==0 RxClkDly_Margin_A0==88 ps 9 TxDqDly_Margin_A0==98 ps 10 RxClkDly_Margin_A1==88 ps 9 TxDqDly_Margin_A1==98 ps 10 TrainedVREFDQ_A0==74 TrainedVREFDQ_A1==76 VrefDac_Margin_A0==25 DeviceVref_Margin_A0==40 VrefDac_Margin_A1==25 DeviceVref_Margin_A1==38 channel==1 RxClkDly_Margin_A0==98 ps 10 TxDqDly_Margin_A0==88 ps 9 RxClkDly_Margin_A1==88 ps 9 TxDqDly_Margin_A1==88 ps 9 TrainedVREFDQ_A0==75 TrainedVREFDQ_A1==77 VrefDac_Margin_A0==23 DeviceVref_Margin_A0==38 VrefDac_Margin_A1==24 DeviceVref_Margin_A1==37 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 00000019 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060 2D training succeed aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19 auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00e00024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass 100bdlr_step_size ps== 420 result report boot times 0Enable ddr reg access Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0 0.0;M3 CHK:0;cm4_sp_mode 0 MVN_1=0x00000000 MVN_2=0x00000000 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz] OPS=0x10 ring efuse init chipver efuse init 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 [0.018961 Inits done] secure task start! high task start! low task start! run into bl31 NOTICE: BL31: v1.3(release):4fc40b1 NOTICE: BL31: Built : 15:58:17, May 22 2019 NOTICE: BL31: G12A normal boot! NOTICE: BL31: BL33 decompress pass ERROR: Error initializing runtime service opteed_fast U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC Model: Libre Computer AML-A311D-CC Alta SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2) DRAM: 2 GiB (effective 3.8 GiB) Core: 408 devices, 31 uclasses, devicetree: separate WDT: Not starting watchdog@f0d0 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0 Loading Environment from FAT... Card did not respond to voltage select! : -110 ** Bad device specification mmc 0 ** Card did not respond to voltage select! : -110 ** Bad device specification mmc 0 ** Couldn't find partition mmc 0 Card did not respond to voltage select! : -110 ** Bad device specification mmc 0 ** Couldn't find partition mmc 0 Error: could not access storage. Net: eth0: ethernet@ff3f0000 starting USB... Bus usb@ff500000: Register 3000140 NbrPorts 3 Starting the controller USB XHCI 1.10 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0. bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 L0:00000000 L1:20000703 L2:00008067 L3:14000000 B2:00402000 B1:e0f83180 TE: 58167 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz Board ID = 1 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 00012abe DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01 board id: 1 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done fastboot data load fastboot data verify verify result: 266 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg LPDDR4 probe ddr clk to 1584MHz Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0 dmc_version 0001 Check phy result INFO : End of CA training INFO : End of initialization INFO : Training has run successfully! Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of Write leveling coarse delay INFO : Training has run successfully! Check phy result INFO : End of initialization INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! channel==0 RxClkDly_Margin_A0==88 ps 9 TxDqDly_Margin_A0==98 ps 10 RxClkDly_Margin_A1==88 ps 9 TxDqDly_Margin_A1==98 ps 10 TrainedVREFDQ_A0==74 TrainedVREFDQ_A1==74 VrefDac_Margin_A0==25 DeviceVref_Margin_A0==40 VrefDac_Margin_A1==25 DeviceVref_Margin_A1==40 channel==1 RxClkDly_Margin_A0==88 ps 9 TxDqDly_Margin_A0==98 ps 10 RxClkDly_Margin_A1==88 ps 9 TxDqDly_Margin_A1==88 ps 9 TrainedVREFDQ_A0==77 TrainedVREFDQ_A1==77 VrefDac_Margin_A0==23 DeviceVref_Margin_A0==37 VrefDac_Margin_A1==24 DeviceVref_Margin_A1==37 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f 2D training succeed aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19 auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00e00024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass 100bdlr_step_size ps== 420 result report boot times 0Enable ddr reg access Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0 0.0;M3 CHK:0;cm4_sp_mode 0 MVN_1=0x00000000 MVN_2=0x00000000 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz] OPS=0x10 ring efuse init chipver efuse init 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 [0.018961 Inits done] secure task start! high task start! low task start! run into bl31 NOTICE: BL31: v1.3(release):4fc40b1 NOTICE: BL31: Built : 15:58:17, May 22 2019 NOTICE: BL31: G12A normal boot! NOTICE: BL31: BL33 decompress pass ERROR: Error initializing runtime service opteed_fast U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC Model: Libre Computer AML-A311D-CC Alta SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2) DRAM: 2 GiB (effective 3.8 GiB) Core: 408 devices, 31 uclasses, devicetree: separate WDT: Not starting watchdog@f0d0 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0 Loading Environment from FAT... Card did not respond to voltage select! : -110 ** Bad device specification mmc 0 ** Card did not respond to voltage select! : -110 ** Bad device specification mmc 0 ** Couldn't find partition mmc 0 Card did not respond to voltage select! : -110 ** Bad device specification mmc 0 ** Couldn't find partition mmc 0 Error: could not access storage. Net: eth0: ethernet@ff3f0000 starting USB... Bus usb@ff500000: Register 3000140 NbrPorts 3 Starting the controller USB XHCI 1.10 scanning bus usb@ff500000 for devices... 3 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found Hit any key to stop autoboot: 1  0 => setenv autoload no setenv autoload no => setenv initrd_high 0xffffffff setenv initrd_high 0xffffffff => setenv fdt_high 0xffffffff setenv fdt_high 0xffffffff => dhcp dhcp Speed: 1000, full duplex BOOTP broadcast 1 BOOTP broadcast 2 DHCP client bound to address 192.168.6.33 (338 ms) => setenv serverip 192.168.6.2 setenv serverip 192.168.6.2 => tftpboot 0x01080000 742823/tftp-deploy-s4rj64z6/kernel/uImage tftpboot 0x01080000 742823/tftp-deploy-s4rj64z6/kernel/uImage Speed: 1000, full duplex Using ethernet@ff3f0000 device TFTP from server 192.168.6.2; our IP address is 192.168.6.33 Filename '742823/tftp-deploy-s4rj64z6/kernel/uImage'. Load address: 0x1080000 Loading: *########## UDP wrong checksum 000000ff 00000be2 # UDP wrong checksum 000000ff 000090d4 ####################################### 43.6 MiB 12.1 MiB/s done Bytes transferred = 45724224 (2b9b240 hex) => tftpboot 0x08000000 742823/tftp-deploy-s4rj64z6/ramdisk/ramdisk.cpio.gz.uboot tftpboot 0x08000000 742823/tftp-deploy-s4rj64z6/ramdisk/ramdisk.cpio.gz.uboot Speed: 1000, full duplex Using ethernet@ff3f0000 device TFTP from server 192.168.6.2; our IP address is 192.168.6.33 Filename '742823/tftp-deploy-s4rj64z6/ramdisk/ramdisk.cpio.gz.uboot'. Load address: 0x8000000 Loading: *################################################## 24.9 MiB 12.9 MiB/s done Bytes transferred = 26064736 (18db760 hex) => tftpboot 0x01070000 742823/tftp-deploy-s4rj64z6/dtb/meson-g12b-a311d-libretech-cc.dtb tftpboot 0x01070000 742823/tftp-deploy-s4rj64z6/dtb/meson-g12b-a311d-libretech-cc.dtb Speed: 1000, full duplex Using ethernet@ff3f0000 device TFTP from server 192.168.6.2; our IP address is 192.168.6.33 Filename '742823/tftp-deploy-s4rj64z6/dtb/meson-g12b-a311d-libretech-cc.dtb'. Load address: 0x1070000 Loading: *################################################## 53.4 KiB 3.1 MiB/s done Bytes transferred = 54703 (d5af hex) => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp' setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp' => bootm 0x01080000 0x08000000 0x01070000 bootm 0x01080000 0x08000000 0x01070000 ## Booting kernel from Legacy Image at 01080000 ... Image Name: Image Type: AArch64 Linux Kernel Image (uncompressed) Data Size: 45724160 Bytes = 43.6 MiB Load Address: 01080000 Entry Point: 01080000 Verifying Checksum ... OK ## Loading init Ramdisk from Legacy Image at 08000000 ... Image Name: Image Type: AArch64 Linux RAMDisk Image (uncompressed) Data Size: 26064672 Bytes = 24.9 MiB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK ## Flattened Device Tree blob at 01070000 Booting using the fdt blob at 0x1070000 Working FDT set to 1070000 Loading Kernel Image Loading Ramdisk to 7e724000, end 7ffff720 ... OK Loading Device Tree to 000000007e713000, end 000000007e7235ae ... OK Working FDT set to 7e713000 Starting kernel ... [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034] [ 0.000000] Linux version 6.11.0-next-20240919 (KernelCI@build-j314369-arm64-gcc-12-defconfig-9mqgb) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Sep 19 06:58:18 UTC 2024 [ 0.000000] KASLR disabled due to lack of seed [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta [ 0.000000] efi: UEFI not found. [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader! [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8') [ 0.000000] printk: legacy bootconsole [meson0] enabled [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff] [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf] [ 0.000000] Zone ranges: [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff] [ 0.000000] DMA32 empty [ 0.000000] Normal empty [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff] [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff] [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff] [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff] [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.0 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] psci: SMC Calling Convention v1.1 [ 0.000000] percpu: Embedded 25 pages/cpu s61720 r8192 d32488 u102400 [ 0.000000] Detected VIPT I-cache on CPU0 [ 0.000000] CPU features: detected: ARM erratum 845719 [ 0.000000] alternatives: applying boot alternatives [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear) <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear) <6>[ 0.000000] Fallback order for Node 0: 0 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099 <6>[ 0.000000] Policy zone: DMA <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB <6>[ 0.000000] software IO TLB: area num 8. <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB) <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation. <6>[ 0.000000] rcu: RCU event tracing is enabled. <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6. <6>[ 0.000000] Trampoline variant of Tasks RCU enabled. <6>[ 0.000000] Tracing variant of Tasks RCU enabled. <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6. <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6. <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 <6>[ 0.000000] Root IRQ handler: gic_handle_irq <6>[ 0.000000] GIC: Using split EOI/Deactivate mode <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys). <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns <6>[ 0.000001] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns <6>[ 0.008773] Console: colour dummy device 80x25 <6>[ 0.012935] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000) <6>[ 0.023294] pid_max: default: 32768 minimum: 301 <6>[ 0.028189] LSM: initializing lsm=capability <6>[ 0.032730] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) <6>[ 0.040211] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) <6>[ 0.050770] rcu: Hierarchical SRCU implementation. <6>[ 0.053266] rcu: Max phase no-delay instances is 1000. <6>[ 0.058880] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level <6>[ 0.071428] EFI services will not be available. <6>[ 0.075094] smp: Bringing up secondary CPUs ... <6>[ 0.077132] Detected VIPT I-cache on CPU1 <6>[ 0.077251] CPU1: Booted secondary processor 0x0000000001 [0x410fd034] <6>[ 0.078594] CPU features: detected: Spectre-v2 <6>[ 0.078608] CPU features: detected: Spectre-v4 <6>[ 0.078613] CPU features: detected: Spectre-BHB <6>[ 0.078618] CPU features: detected: ARM erratum 858921 <6>[ 0.078625] Detected VIPT I-cache on CPU2 <6>[ 0.078701] arch_timer: Enabling local workaround for ARM erratum 858921 <6>[ 0.078719] arch_timer: CPU2: Trapping CNTVCT access <6>[ 0.078729] CPU2: Booted secondary processor 0x0000000100 [0x410fd092] <6>[ 0.083447] Detected VIPT I-cache on CPU3 <6>[ 0.083492] arch_timer: Enabling local workaround for ARM erratum 858921 <6>[ 0.083502] arch_timer: CPU3: Trapping CNTVCT access <6>[ 0.083509] CPU3: Booted secondary processor 0x0000000101 [0x410fd092] <6>[ 0.087486] Detected VIPT I-cache on CPU4 <6>[ 0.087533] arch_timer: Enabling local workaround for ARM erratum 858921 <6>[ 0.087543] arch_timer: CPU4: Trapping CNTVCT access <6>[ 0.087550] CPU4: Booted secondary processor 0x0000000102 [0x410fd092] <6>[ 0.095508] Detected VIPT I-cache on CPU5 <6>[ 0.095556] arch_timer: Enabling local workaround for ARM erratum 858921 <6>[ 0.095566] arch_timer: CPU5: Trapping CNTVCT access <6>[ 0.095573] CPU5: Booted secondary processor 0x0000000103 [0x410fd092] <6>[ 0.095693] smp: Brought up 1 node, 6 CPUs <6>[ 0.216922] SMP: Total of 6 processors activated. <6>[ 0.221825] CPU: All CPU(s) started at EL2 <6>[ 0.2# # # # #