Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 22
- Errors: 2
- Kernel Errors: 44
- Boot result: FAIL
1 13:52:54.241637 lava-dispatcher, installed at version: 2024.03
2 13:52:54.241836 start: 0 validate
3 13:52:54.241975 Start time: 2024-05-16 13:52:54.241968+00:00 (UTC)
4 13:52:54.242105 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:52:54.242239 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 13:52:54.492793 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:52:54.492959 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fstable-rc%2Fqueue-6.6%2Fv6.6.30-308-g54de3aade1b7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:52:54.494080 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:52:54.494196 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fstable-rc%2Fqueue-6.6%2Fv6.6.30-308-g54de3aade1b7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:52:54.761297 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:52:54.761518 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fstable-rc%2Fqueue-6.6%2Fv6.6.30-308-g54de3aade1b7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:52:55.285231 validate duration: 1.04
14 13:52:55.285530 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:52:55.285645 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:52:55.285754 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:52:55.285892 Not decompressing ramdisk as can be used compressed.
18 13:52:55.285983 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 13:52:55.286047 saving as /var/lib/lava/dispatcher/tmp/13842491/tftp-deploy-jr0n5hf8/ramdisk/rootfs.cpio.gz
20 13:52:55.286118 total size: 8181887 (7 MB)
21 13:52:55.287281 progress 0 % (0 MB)
22 13:52:55.289728 progress 5 % (0 MB)
23 13:52:55.291842 progress 10 % (0 MB)
24 13:52:55.294218 progress 15 % (1 MB)
25 13:52:55.296466 progress 20 % (1 MB)
26 13:52:55.298785 progress 25 % (1 MB)
27 13:52:55.300949 progress 30 % (2 MB)
28 13:52:55.303339 progress 35 % (2 MB)
29 13:52:55.305573 progress 40 % (3 MB)
30 13:52:55.307894 progress 45 % (3 MB)
31 13:52:55.310091 progress 50 % (3 MB)
32 13:52:55.312418 progress 55 % (4 MB)
33 13:52:55.314533 progress 60 % (4 MB)
34 13:52:55.316872 progress 65 % (5 MB)
35 13:52:55.318985 progress 70 % (5 MB)
36 13:52:55.321374 progress 75 % (5 MB)
37 13:52:55.323472 progress 80 % (6 MB)
38 13:52:55.325832 progress 85 % (6 MB)
39 13:52:55.327909 progress 90 % (7 MB)
40 13:52:55.330220 progress 95 % (7 MB)
41 13:52:55.332306 progress 100 % (7 MB)
42 13:52:55.332555 7 MB downloaded in 0.05 s (168.05 MB/s)
43 13:52:55.332708 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:52:55.332964 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:52:55.333089 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:52:55.333180 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:52:55.333334 downloading http://storage.kernelci.org/stable-rc/queue-6.6/v6.6.30-308-g54de3aade1b7/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:52:55.333407 saving as /var/lib/lava/dispatcher/tmp/13842491/tftp-deploy-jr0n5hf8/kernel/Image
50 13:52:55.333469 total size: 58055168 (55 MB)
51 13:52:55.333536 No compression specified
52 13:52:55.334645 progress 0 % (0 MB)
53 13:52:55.349951 progress 5 % (2 MB)
54 13:52:55.365454 progress 10 % (5 MB)
55 13:52:55.380885 progress 15 % (8 MB)
56 13:52:55.396421 progress 20 % (11 MB)
57 13:52:55.411948 progress 25 % (13 MB)
58 13:52:55.427719 progress 30 % (16 MB)
59 13:52:55.443325 progress 35 % (19 MB)
60 13:52:55.458779 progress 40 % (22 MB)
61 13:52:55.474408 progress 45 % (24 MB)
62 13:52:55.491546 progress 50 % (27 MB)
63 13:52:55.508139 progress 55 % (30 MB)
64 13:52:55.524174 progress 60 % (33 MB)
65 13:52:55.539684 progress 65 % (36 MB)
66 13:52:55.555426 progress 70 % (38 MB)
67 13:52:55.571051 progress 75 % (41 MB)
68 13:52:55.586678 progress 80 % (44 MB)
69 13:52:55.602153 progress 85 % (47 MB)
70 13:52:55.617945 progress 90 % (49 MB)
71 13:52:55.633370 progress 95 % (52 MB)
72 13:52:55.648642 progress 100 % (55 MB)
73 13:52:55.648899 55 MB downloaded in 0.32 s (175.53 MB/s)
74 13:52:55.649067 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:52:55.649315 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:52:55.649410 start: 1.3 download-retry (timeout 00:10:00) [common]
78 13:52:55.649496 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 13:52:55.649642 downloading http://storage.kernelci.org/stable-rc/queue-6.6/v6.6.30-308-g54de3aade1b7/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:52:55.649712 saving as /var/lib/lava/dispatcher/tmp/13842491/tftp-deploy-jr0n5hf8/dtb/mt8192-asurada-spherion-r0.dtb
81 13:52:55.649772 total size: 58971 (0 MB)
82 13:52:55.649841 No compression specified
83 13:52:55.650992 progress 55 % (0 MB)
84 13:52:55.651284 progress 100 % (0 MB)
85 13:52:55.651499 0 MB downloaded in 0.00 s (32.59 MB/s)
86 13:52:55.651632 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:52:55.651864 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:52:55.651957 start: 1.4 download-retry (timeout 00:10:00) [common]
90 13:52:55.652039 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 13:52:55.652159 downloading http://storage.kernelci.org/stable-rc/queue-6.6/v6.6.30-308-g54de3aade1b7/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:52:55.652227 saving as /var/lib/lava/dispatcher/tmp/13842491/tftp-deploy-jr0n5hf8/modules/modules.tar
93 13:52:55.652294 total size: 9555840 (9 MB)
94 13:52:55.652370 Using unxz to decompress xz
95 13:52:55.656448 progress 0 % (0 MB)
96 13:52:55.681707 progress 5 % (0 MB)
97 13:52:55.712595 progress 10 % (0 MB)
98 13:52:55.740375 progress 15 % (1 MB)
99 13:52:55.770141 progress 20 % (1 MB)
100 13:52:55.795810 progress 25 % (2 MB)
101 13:52:55.825492 progress 30 % (2 MB)
102 13:52:55.854984 progress 35 % (3 MB)
103 13:52:55.882680 progress 40 % (3 MB)
104 13:52:55.912385 progress 45 % (4 MB)
105 13:52:55.940169 progress 50 % (4 MB)
106 13:52:55.971087 progress 55 % (5 MB)
107 13:52:55.998332 progress 60 % (5 MB)
108 13:52:56.029135 progress 65 % (5 MB)
109 13:52:56.059717 progress 70 % (6 MB)
110 13:52:56.094011 progress 75 % (6 MB)
111 13:52:56.124400 progress 80 % (7 MB)
112 13:52:56.151346 progress 85 % (7 MB)
113 13:52:56.179953 progress 90 % (8 MB)
114 13:52:56.209024 progress 95 % (8 MB)
115 13:52:56.235319 progress 100 % (9 MB)
116 13:52:56.241004 9 MB downloaded in 0.59 s (15.48 MB/s)
117 13:52:56.241259 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:52:56.241533 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:52:56.241649 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:52:56.241762 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:52:56.241884 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:52:56.242014 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:52:56.242298 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb
125 13:52:56.242485 makedir: /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin
126 13:52:56.242674 makedir: /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/tests
127 13:52:56.242791 makedir: /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/results
128 13:52:56.242945 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-add-keys
129 13:52:56.243132 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-add-sources
130 13:52:56.243281 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-background-process-start
131 13:52:56.243431 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-background-process-stop
132 13:52:56.243576 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-common-functions
133 13:52:56.243725 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-echo-ipv4
134 13:52:56.243896 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-install-packages
135 13:52:56.244063 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-installed-packages
136 13:52:56.244208 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-os-build
137 13:52:56.244421 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-probe-channel
138 13:52:56.244567 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-probe-ip
139 13:52:56.244711 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-target-ip
140 13:52:56.244853 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-target-mac
141 13:52:56.244999 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-target-storage
142 13:52:56.245181 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-test-case
143 13:52:56.245349 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-test-event
144 13:52:56.245491 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-test-feedback
145 13:52:56.245637 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-test-raise
146 13:52:56.245802 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-test-reference
147 13:52:56.245944 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-test-runner
148 13:52:56.246086 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-test-set
149 13:52:56.246235 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-test-shell
150 13:52:56.246387 Updating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-install-packages (oe)
151 13:52:56.246585 Updating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/bin/lava-installed-packages (oe)
152 13:52:56.246750 Creating /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/environment
153 13:52:56.246873 LAVA metadata
154 13:52:56.246955 - LAVA_JOB_ID=13842491
155 13:52:56.247058 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:52:56.247212 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:52:56.247312 skipped lava-vland-overlay
158 13:52:56.247410 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:52:56.247513 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:52:56.247611 skipped lava-multinode-overlay
161 13:52:56.247729 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:52:56.247865 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:52:56.247956 Loading test definitions
164 13:52:56.248095 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:52:56.248205 Using /lava-13842491 at stage 0
166 13:52:56.248690 uuid=13842491_1.5.2.3.1 testdef=None
167 13:52:56.248817 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:52:56.248945 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:52:56.249711 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:52:56.249995 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:52:56.250652 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:52:56.250909 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:52:56.251810 runner path: /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/0/tests/0_dmesg test_uuid 13842491_1.5.2.3.1
176 13:52:56.252009 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:52:56.252341 Creating lava-test-runner.conf files
179 13:52:56.252476 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13842491/lava-overlay-sb_1_btb/lava-13842491/0 for stage 0
180 13:52:56.252612 - 0_dmesg
181 13:52:56.252749 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:52:56.252875 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:52:56.260511 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:52:56.260649 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:52:56.260756 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:52:56.260862 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:52:56.260962 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:52:56.506930 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 13:52:56.507304 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
190 13:52:56.507440 extracting modules file /var/lib/lava/dispatcher/tmp/13842491/tftp-deploy-jr0n5hf8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13842491/extract-overlay-ramdisk-yxtju8z_/ramdisk
191 13:52:56.760463 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:52:56.760640 start: 1.5.5 apply-overlay-tftp (timeout 00:09:59) [common]
193 13:52:56.760755 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13842491/compress-overlay-vvein10i/overlay-1.5.2.4.tar.gz to ramdisk
194 13:52:56.760837 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13842491/compress-overlay-vvein10i/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13842491/extract-overlay-ramdisk-yxtju8z_/ramdisk
195 13:52:56.767744 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:52:56.767884 start: 1.5.6 configure-preseed-file (timeout 00:09:59) [common]
197 13:52:56.767993 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:52:56.768104 start: 1.5.7 compress-ramdisk (timeout 00:09:59) [common]
199 13:52:56.768199 Building ramdisk /var/lib/lava/dispatcher/tmp/13842491/extract-overlay-ramdisk-yxtju8z_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13842491/extract-overlay-ramdisk-yxtju8z_/ramdisk
200 13:52:57.312539 >> 158407 blocks
201 13:52:59.869444 rename /var/lib/lava/dispatcher/tmp/13842491/extract-overlay-ramdisk-yxtju8z_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13842491/tftp-deploy-jr0n5hf8/ramdisk/ramdisk.cpio.gz
202 13:52:59.870004 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 13:52:59.870182 start: 1.5.8 prepare-kernel (timeout 00:09:55) [common]
204 13:52:59.870330 start: 1.5.8.1 prepare-fit (timeout 00:09:55) [common]
205 13:52:59.870495 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/13842491/tftp-deploy-jr0n5hf8/kernel/Image']
206 13:53:15.435892 Returned 0 in 15 seconds
207 13:53:15.536464 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13842491/tftp-deploy-jr0n5hf8/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13842491/tftp-deploy-jr0n5hf8/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13842491/tftp-deploy-jr0n5hf8/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13842491/tftp-deploy-jr0n5hf8/kernel/image.itb
208 13:53:15.950244 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:53:15.950611 output: Created: Thu May 16 14:53:15 2024
210 13:53:15.950717 output: Image 0 (kernel-1)
211 13:53:15.950801 output: Description:
212 13:53:15.950886 output: Created: Thu May 16 14:53:15 2024
213 13:53:15.950986 output: Type: Kernel Image
214 13:53:15.951091 output: Compression: lzma compressed
215 13:53:15.951193 output: Data Size: 13484083 Bytes = 13168.05 KiB = 12.86 MiB
216 13:53:15.951296 output: Architecture: AArch64
217 13:53:15.951398 output: OS: Linux
218 13:53:15.951507 output: Load Address: 0x00000000
219 13:53:15.951608 output: Entry Point: 0x00000000
220 13:53:15.951705 output: Hash algo: crc32
221 13:53:15.951802 output: Hash value: 5831605f
222 13:53:15.951899 output: Image 1 (fdt-1)
223 13:53:15.951994 output: Description: mt8192-asurada-spherion-r0
224 13:53:15.952088 output: Created: Thu May 16 14:53:15 2024
225 13:53:15.952182 output: Type: Flat Device Tree
226 13:53:15.952284 output: Compression: uncompressed
227 13:53:15.952384 output: Data Size: 58971 Bytes = 57.59 KiB = 0.06 MiB
228 13:53:15.952478 output: Architecture: AArch64
229 13:53:15.952573 output: Hash algo: crc32
230 13:53:15.952666 output: Hash value: ee554a0e
231 13:53:15.952759 output: Image 2 (ramdisk-1)
232 13:53:15.952852 output: Description: unavailable
233 13:53:15.952945 output: Created: Thu May 16 14:53:15 2024
234 13:53:15.953038 output: Type: RAMDisk Image
235 13:53:15.953130 output: Compression: Unknown Compression
236 13:53:15.953226 output: Data Size: 22871760 Bytes = 22335.70 KiB = 21.81 MiB
237 13:53:15.953322 output: Architecture: AArch64
238 13:53:15.953415 output: OS: Linux
239 13:53:15.953508 output: Load Address: unavailable
240 13:53:15.953601 output: Entry Point: unavailable
241 13:53:15.953694 output: Hash algo: crc32
242 13:53:15.953786 output: Hash value: a4d57915
243 13:53:15.953879 output: Default Configuration: 'conf-1'
244 13:53:15.953981 output: Configuration 0 (conf-1)
245 13:53:15.954074 output: Description: mt8192-asurada-spherion-r0
246 13:53:15.954166 output: Kernel: kernel-1
247 13:53:15.954258 output: Init Ramdisk: ramdisk-1
248 13:53:15.954350 output: FDT: fdt-1
249 13:53:15.954442 output: Loadables: kernel-1
250 13:53:15.954533 output:
251 13:53:15.954797 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 13:53:15.954949 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 13:53:15.955106 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 13:53:15.955245 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 13:53:15.955364 No LXC device requested
256 13:53:15.955495 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:53:15.955626 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 13:53:15.955737 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:53:15.955835 Checking files for TFTP limit of 4294967296 bytes.
260 13:53:15.956521 end: 1 tftp-deploy (duration 00:00:21) [common]
261 13:53:15.956662 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:53:15.956790 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:53:15.956958 substitutions:
264 13:53:15.957055 - {DTB}: 13842491/tftp-deploy-jr0n5hf8/dtb/mt8192-asurada-spherion-r0.dtb
265 13:53:15.957165 - {INITRD}: 13842491/tftp-deploy-jr0n5hf8/ramdisk/ramdisk.cpio.gz
266 13:53:15.957233 - {KERNEL}: 13842491/tftp-deploy-jr0n5hf8/kernel/Image
267 13:53:15.957293 - {LAVA_MAC}: None
268 13:53:15.957352 - {PRESEED_CONFIG}: None
269 13:53:15.957409 - {PRESEED_LOCAL}: None
270 13:53:15.957466 - {RAMDISK}: 13842491/tftp-deploy-jr0n5hf8/ramdisk/ramdisk.cpio.gz
271 13:53:15.957525 - {ROOT_PART}: None
272 13:53:15.957603 - {ROOT}: None
273 13:53:15.957680 - {SERVER_IP}: 192.168.201.1
274 13:53:15.957757 - {TEE}: None
275 13:53:15.957833 Parsed boot commands:
276 13:53:15.957907 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:53:15.958127 Parsed boot commands: tftpboot 192.168.201.1 13842491/tftp-deploy-jr0n5hf8/kernel/image.itb 13842491/tftp-deploy-jr0n5hf8/kernel/cmdline
278 13:53:15.958254 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:53:15.958385 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:53:15.958520 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:53:15.958626 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:53:15.958736 Not connected, no need to disconnect.
283 13:53:15.958856 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:53:15.958984 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:53:15.959108 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 13:53:15.962956 Setting prompt string to ['lava-test: # ']
287 13:53:15.963454 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:53:15.963621 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:53:15.963781 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:53:15.963908 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:53:15.964146 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
292 13:53:21.101090 >> Command sent successfully.
293 13:53:21.103893 Returned 0 in 5 seconds
294 13:53:21.204274 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 13:53:21.204620 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 13:53:21.204746 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 13:53:21.204850 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:53:21.204927 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:53:21.204994 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:53:21.205546 [Enter `^Ec?' for help]
302 13:53:21.607020
303 13:53:21.607164
304 13:53:21.607238 F0: 102B 0000
305 13:53:21.607304
306 13:53:21.607382 F3: 1001 0000 [0200]
307 13:53:21.610702
308 13:53:21.610808 F3: 1001 0000
309 13:53:21.610911
310 13:53:21.610999 F7: 102D 0000
311 13:53:21.611089
312 13:53:21.614310 F1: 0000 0000
313 13:53:21.614409
314 13:53:21.614484 V0: 0000 0000 [0001]
315 13:53:21.614546
316 13:53:21.617119 00: 0007 8000
317 13:53:21.617223
318 13:53:21.617297 01: 0000 0000
319 13:53:21.617374
320 13:53:21.620783 BP: 0C00 0209 [0000]
321 13:53:21.620864
322 13:53:21.620940 G0: 1182 0000
323 13:53:21.621006
324 13:53:21.623609 EC: 0000 0021 [4000]
325 13:53:21.623681
326 13:53:21.623767 S7: 0000 0000 [0000]
327 13:53:21.623827
328 13:53:21.627291 CC: 0000 0000 [0001]
329 13:53:21.627364
330 13:53:21.627427 T0: 0000 0040 [010F]
331 13:53:21.627491
332 13:53:21.630713 Jump to BL
333 13:53:21.630784
334 13:53:21.654224
335 13:53:21.654341
336 13:53:21.663895 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 13:53:21.667206 ARM64: Exception handlers installed.
338 13:53:21.667317 ARM64: Testing exception
339 13:53:21.670406 ARM64: Done test exception
340 13:53:21.677032 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 13:53:21.687340 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 13:53:21.694587 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 13:53:21.705241 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 13:53:21.711616 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 13:53:21.722080 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 13:53:21.731744 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 13:53:21.738402 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 13:53:21.757038 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 13:53:21.760421 WDT: Last reset was cold boot
350 13:53:21.764137 SPI1(PAD0) initialized at 2873684 Hz
351 13:53:21.766773 SPI5(PAD0) initialized at 992727 Hz
352 13:53:21.770057 VBOOT: Loading verstage.
353 13:53:21.777243 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 13:53:21.780285 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 13:53:21.783414 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 13:53:21.786787 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 13:53:21.794312 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 13:53:21.801146 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 13:53:21.812314 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 13:53:21.812461
361 13:53:21.812544
362 13:53:21.822284 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 13:53:21.825801 ARM64: Exception handlers installed.
364 13:53:21.829402 ARM64: Testing exception
365 13:53:21.829505 ARM64: Done test exception
366 13:53:21.836199 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 13:53:21.838988 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 13:53:21.852943 Probing TPM: . done!
369 13:53:21.853092 TPM ready after 0 ms
370 13:53:21.859904 Connected to device vid:did:rid of 1ae0:0028:00
371 13:53:21.869730 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 13:53:21.982067 Initialized TPM device CR50 revision 0
373 13:53:21.997123 tlcl_send_startup: Startup return code is 0
374 13:53:21.997269 TPM: setup succeeded
375 13:53:22.011295 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 13:53:22.020925 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 13:53:22.031588 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 13:53:22.041077 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 13:53:22.044052 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 13:53:22.047772 in-header: 03 07 00 00 08 00 00 00
381 13:53:22.050620 in-data: aa e4 47 04 13 02 00 00
382 13:53:22.054177 Chrome EC: UHEPI supported
383 13:53:22.060888 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 13:53:22.064310 in-header: 03 ad 00 00 08 00 00 00
385 13:53:22.067950 in-data: 00 20 20 08 00 00 00 00
386 13:53:22.068049 Phase 1
387 13:53:22.071587 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 13:53:22.078292 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 13:53:22.085341 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 13:53:22.085463 Recovery requested (1009000e)
391 13:53:22.095415 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 13:53:22.101391 tlcl_extend: response is 0
393 13:53:22.109329 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 13:53:22.114669 tlcl_extend: response is 0
395 13:53:22.120998 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 13:53:22.141621 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
397 13:53:22.148658 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 13:53:22.148807
399 13:53:22.148913
400 13:53:22.158462 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 13:53:22.162183 ARM64: Exception handlers installed.
402 13:53:22.164887 ARM64: Testing exception
403 13:53:22.164975 ARM64: Done test exception
404 13:53:22.187131 pmic_efuse_setting: Set efuses in 11 msecs
405 13:53:22.190807 pmwrap_interface_init: Select PMIF_VLD_RDY
406 13:53:22.197300 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 13:53:22.200856 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 13:53:22.207368 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 13:53:22.210530 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 13:53:22.217126 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 13:53:22.220681 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 13:53:22.223969 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 13:53:22.231003 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 13:53:22.233967 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 13:53:22.240436 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 13:53:22.244032 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 13:53:22.247414 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 13:53:22.253934 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 13:53:22.260817 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 13:53:22.264017 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 13:53:22.270145 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 13:53:22.277398 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 13:53:22.283561 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 13:53:22.287213 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 13:53:22.293659 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 13:53:22.300177 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 13:53:22.303887 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 13:53:22.310348 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 13:53:22.317555 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 13:53:22.320924 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 13:53:22.326905 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 13:53:22.330926 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 13:53:22.337328 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 13:53:22.340526 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 13:53:22.347327 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 13:53:22.350908 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 13:53:22.356860 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 13:53:22.360273 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 13:53:22.367017 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 13:53:22.370590 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 13:53:22.377389 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 13:53:22.380648 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 13:53:22.387187 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 13:53:22.390753 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 13:53:22.394345 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 13:53:22.401120 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 13:53:22.403993 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 13:53:22.407617 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 13:53:22.414235 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 13:53:22.417303 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 13:53:22.421013 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 13:53:22.424519 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 13:53:22.431039 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 13:53:22.433865 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 13:53:22.437269 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 13:53:22.440868 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 13:53:22.450607 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 13:53:22.457458 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 13:53:22.464100 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 13:53:22.471055 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 13:53:22.480499 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 13:53:22.484001 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 13:53:22.487405 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 13:53:22.494380 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:53:22.501006 [RTC]rtc_enable_dcxo,68: con=0x406, osc32con=0xde70, sec=0x19
466 13:53:22.507404 [RTC]rtc_check_state,173: con=406, pwrkey1=a357, pwrkey2=67d2
467 13:53:22.511016 [RTC]rtc_osc_init,62: osc32con val = 0xde70
468 13:53:22.513850 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 13:53:22.524510 [RTC]rtc_get_frequency_meter,154: input=15, output=757
470 13:53:22.534060 [RTC]rtc_get_frequency_meter,154: input=23, output=941
471 13:53:22.543581 [RTC]rtc_get_frequency_meter,154: input=19, output=851
472 13:53:22.553663 [RTC]rtc_get_frequency_meter,154: input=17, output=804
473 13:53:22.563197 [RTC]rtc_get_frequency_meter,154: input=16, output=782
474 13:53:22.571935 [RTC]rtc_get_frequency_meter,154: input=16, output=781
475 13:53:22.581615 [RTC]rtc_get_frequency_meter,154: input=17, output=804
476 13:53:22.585087 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
477 13:53:22.592276 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
478 13:53:22.595693 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 13:53:22.599101 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 13:53:22.605770 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 13:53:22.608662 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 13:53:22.612379 ADC[4]: Raw value=905834 ID=7
483 13:53:22.612504 ADC[3]: Raw value=213441 ID=1
484 13:53:22.616011 RAM Code: 0x71
485 13:53:22.618811 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 13:53:22.626077 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 13:53:22.632503 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 13:53:22.639080 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 13:53:22.642292 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 13:53:22.645271 in-header: 03 07 00 00 08 00 00 00
491 13:53:22.649462 in-data: aa e4 47 04 13 02 00 00
492 13:53:22.653001 Chrome EC: UHEPI supported
493 13:53:22.660930 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 13:53:22.664621 in-header: 03 ed 00 00 08 00 00 00
495 13:53:22.664746 in-data: 80 20 60 08 00 00 00 00
496 13:53:22.668166 MRC: failed to locate region type 0.
497 13:53:22.675324 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 13:53:22.678972 DRAM-K: Running full calibration
499 13:53:22.686320 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 13:53:22.686489 header.status = 0x0
501 13:53:22.689801 header.version = 0x6 (expected: 0x6)
502 13:53:22.693263 header.size = 0xd00 (expected: 0xd00)
503 13:53:22.693376 header.flags = 0x0
504 13:53:22.699937 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 13:53:22.718994 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
506 13:53:22.725352 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 13:53:22.728868 dram_init: ddr_geometry: 2
508 13:53:22.731807 [EMI] MDL number = 2
509 13:53:22.731934 [EMI] Get MDL freq = 0
510 13:53:22.735407 dram_init: ddr_type: 0
511 13:53:22.735490 is_discrete_lpddr4: 1
512 13:53:22.738913 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 13:53:22.739015
514 13:53:22.739079
515 13:53:22.741751 [Bian_co] ETT version 0.0.0.1
516 13:53:22.748972 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 13:53:22.749098
518 13:53:22.751839 dramc_set_vcore_voltage set vcore to 650000
519 13:53:22.751960 Read voltage for 800, 4
520 13:53:22.755377 Vio18 = 0
521 13:53:22.755461 Vcore = 650000
522 13:53:22.755530 Vdram = 0
523 13:53:22.758825 Vddq = 0
524 13:53:22.758915 Vmddr = 0
525 13:53:22.761969 dram_init: config_dvfs: 1
526 13:53:22.765141 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 13:53:22.771742 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 13:53:22.775340 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
529 13:53:22.778887 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
530 13:53:22.781856 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
531 13:53:22.785495 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
532 13:53:22.788929 MEM_TYPE=3, freq_sel=18
533 13:53:22.792535 sv_algorithm_assistance_LP4_1600
534 13:53:22.795297 ============ PULL DRAM RESETB DOWN ============
535 13:53:22.798561 ========== PULL DRAM RESETB DOWN end =========
536 13:53:22.805421 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 13:53:22.808636 ===================================
538 13:53:22.812044 LPDDR4 DRAM CONFIGURATION
539 13:53:22.812177 ===================================
540 13:53:22.815558 EX_ROW_EN[0] = 0x0
541 13:53:22.818653 EX_ROW_EN[1] = 0x0
542 13:53:22.818778 LP4Y_EN = 0x0
543 13:53:22.822150 WORK_FSP = 0x0
544 13:53:22.822270 WL = 0x2
545 13:53:22.825545 RL = 0x2
546 13:53:22.825646 BL = 0x2
547 13:53:22.829140 RPST = 0x0
548 13:53:22.829252 RD_PRE = 0x0
549 13:53:22.832490 WR_PRE = 0x1
550 13:53:22.832597 WR_PST = 0x0
551 13:53:22.836050 DBI_WR = 0x0
552 13:53:22.836169 DBI_RD = 0x0
553 13:53:22.839380 OTF = 0x1
554 13:53:22.842044 ===================================
555 13:53:22.846451 ===================================
556 13:53:22.846559 ANA top config
557 13:53:22.850130 ===================================
558 13:53:22.853726 DLL_ASYNC_EN = 0
559 13:53:22.853835 ALL_SLAVE_EN = 1
560 13:53:22.857162 NEW_RANK_MODE = 1
561 13:53:22.860795 DLL_IDLE_MODE = 1
562 13:53:22.860905 LP45_APHY_COMB_EN = 1
563 13:53:22.864453 TX_ODT_DIS = 1
564 13:53:22.868628 NEW_8X_MODE = 1
565 13:53:22.872080 ===================================
566 13:53:22.876384 ===================================
567 13:53:22.876514 data_rate = 1600
568 13:53:22.879916 CKR = 1
569 13:53:22.883524 DQ_P2S_RATIO = 8
570 13:53:22.887118 ===================================
571 13:53:22.890759 CA_P2S_RATIO = 8
572 13:53:22.890878 DQ_CA_OPEN = 0
573 13:53:22.894356 DQ_SEMI_OPEN = 0
574 13:53:22.897306 CA_SEMI_OPEN = 0
575 13:53:22.900946 CA_FULL_RATE = 0
576 13:53:22.904350 DQ_CKDIV4_EN = 1
577 13:53:22.904443 CA_CKDIV4_EN = 1
578 13:53:22.907214 CA_PREDIV_EN = 0
579 13:53:22.910698 PH8_DLY = 0
580 13:53:22.914239 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 13:53:22.917687 DQ_AAMCK_DIV = 4
582 13:53:22.920975 CA_AAMCK_DIV = 4
583 13:53:22.921084 CA_ADMCK_DIV = 4
584 13:53:22.924492 DQ_TRACK_CA_EN = 0
585 13:53:22.927911 CA_PICK = 800
586 13:53:22.930730 CA_MCKIO = 800
587 13:53:22.934361 MCKIO_SEMI = 0
588 13:53:22.937545 PLL_FREQ = 3068
589 13:53:22.937685 DQ_UI_PI_RATIO = 32
590 13:53:22.941167 CA_UI_PI_RATIO = 0
591 13:53:22.943927 ===================================
592 13:53:22.947434 ===================================
593 13:53:22.951210 memory_type:LPDDR4
594 13:53:22.954714 GP_NUM : 10
595 13:53:22.954832 SRAM_EN : 1
596 13:53:22.958289 MD32_EN : 0
597 13:53:22.962350 ===================================
598 13:53:22.962496 [ANA_INIT] >>>>>>>>>>>>>>
599 13:53:22.966000 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 13:53:22.969676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 13:53:22.972853 ===================================
602 13:53:22.977122 data_rate = 1600,PCW = 0X7600
603 13:53:22.977226 ===================================
604 13:53:22.980473 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 13:53:22.988184 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 13:53:22.991889 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 13:53:22.999281 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 13:53:22.999420 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 13:53:23.002966 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 13:53:23.007281 [ANA_INIT] flow start
611 13:53:23.007392 [ANA_INIT] PLL >>>>>>>>
612 13:53:23.010911 [ANA_INIT] PLL <<<<<<<<
613 13:53:23.014215 [ANA_INIT] MIDPI >>>>>>>>
614 13:53:23.014330 [ANA_INIT] MIDPI <<<<<<<<
615 13:53:23.017938 [ANA_INIT] DLL >>>>>>>>
616 13:53:23.018051 [ANA_INIT] flow end
617 13:53:23.025761 ============ LP4 DIFF to SE enter ============
618 13:53:23.028967 ============ LP4 DIFF to SE exit ============
619 13:53:23.029075 [ANA_INIT] <<<<<<<<<<<<<
620 13:53:23.033057 [Flow] Enable top DCM control >>>>>
621 13:53:23.036371 [Flow] Enable top DCM control <<<<<
622 13:53:23.040277 Enable DLL master slave shuffle
623 13:53:23.047449 ==============================================================
624 13:53:23.047588 Gating Mode config
625 13:53:23.051513 ==============================================================
626 13:53:23.054771 Config description:
627 13:53:23.064860 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 13:53:23.071634 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 13:53:23.075047 SELPH_MODE 0: By rank 1: By Phase
630 13:53:23.082324 ==============================================================
631 13:53:23.085829 GAT_TRACK_EN = 1
632 13:53:23.085940 RX_GATING_MODE = 2
633 13:53:23.089233 RX_GATING_TRACK_MODE = 2
634 13:53:23.092673 SELPH_MODE = 1
635 13:53:23.096056 PICG_EARLY_EN = 1
636 13:53:23.098834 VALID_LAT_VALUE = 1
637 13:53:23.105890 ==============================================================
638 13:53:23.108788 Enter into Gating configuration >>>>
639 13:53:23.112295 Exit from Gating configuration <<<<
640 13:53:23.115946 Enter into DVFS_PRE_config >>>>>
641 13:53:23.125952 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 13:53:23.129423 Exit from DVFS_PRE_config <<<<<
643 13:53:23.132983 Enter into PICG configuration >>>>
644 13:53:23.136473 Exit from PICG configuration <<<<
645 13:53:23.136600 [RX_INPUT] configuration >>>>>
646 13:53:23.139916 [RX_INPUT] configuration <<<<<
647 13:53:23.147462 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 13:53:23.150845 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 13:53:23.159205 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 13:53:23.162822 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 13:53:23.170051 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 13:53:23.177797 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 13:53:23.181219 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 13:53:23.185388 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 13:53:23.188788 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 13:53:23.192284 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 13:53:23.196290 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 13:53:23.199946 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 13:53:23.204191 ===================================
660 13:53:23.207624 LPDDR4 DRAM CONFIGURATION
661 13:53:23.211140 ===================================
662 13:53:23.211292 EX_ROW_EN[0] = 0x0
663 13:53:23.215359 EX_ROW_EN[1] = 0x0
664 13:53:23.215509 LP4Y_EN = 0x0
665 13:53:23.219081 WORK_FSP = 0x0
666 13:53:23.219225 WL = 0x2
667 13:53:23.222555 RL = 0x2
668 13:53:23.222666 BL = 0x2
669 13:53:23.222736 RPST = 0x0
670 13:53:23.226093 RD_PRE = 0x0
671 13:53:23.226233 WR_PRE = 0x1
672 13:53:23.229631 WR_PST = 0x0
673 13:53:23.229781 DBI_WR = 0x0
674 13:53:23.233978 DBI_RD = 0x0
675 13:53:23.234130 OTF = 0x1
676 13:53:23.237433 ===================================
677 13:53:23.240978 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 13:53:23.244787 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 13:53:23.251849 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 13:53:23.252052 ===================================
681 13:53:23.255413 LPDDR4 DRAM CONFIGURATION
682 13:53:23.259324 ===================================
683 13:53:23.263359 EX_ROW_EN[0] = 0x10
684 13:53:23.263550 EX_ROW_EN[1] = 0x0
685 13:53:23.266602 LP4Y_EN = 0x0
686 13:53:23.266723 WORK_FSP = 0x0
687 13:53:23.270585 WL = 0x2
688 13:53:23.270724 RL = 0x2
689 13:53:23.270824 BL = 0x2
690 13:53:23.274151 RPST = 0x0
691 13:53:23.274257 RD_PRE = 0x0
692 13:53:23.277574 WR_PRE = 0x1
693 13:53:23.277684 WR_PST = 0x0
694 13:53:23.281322 DBI_WR = 0x0
695 13:53:23.281456 DBI_RD = 0x0
696 13:53:23.285298 OTF = 0x1
697 13:53:23.288612 ===================================
698 13:53:23.292005 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 13:53:23.297587 nWR fixed to 40
700 13:53:23.301115 [ModeRegInit_LP4] CH0 RK0
701 13:53:23.301234 [ModeRegInit_LP4] CH0 RK1
702 13:53:23.304938 [ModeRegInit_LP4] CH1 RK0
703 13:53:23.305054 [ModeRegInit_LP4] CH1 RK1
704 13:53:23.308306 match AC timing 13
705 13:53:23.311879 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 13:53:23.316080 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 13:53:23.319759 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 13:53:23.326871 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 13:53:23.331042 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 13:53:23.331191 [EMI DOE] emi_dcm 0
711 13:53:23.338069 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 13:53:23.338258 ==
713 13:53:23.341636 Dram Type= 6, Freq= 0, CH_0, rank 0
714 13:53:23.345042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 13:53:23.345201 ==
716 13:53:23.349128 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 13:53:23.356233 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 13:53:23.365063 [CA 0] Center 36 (6~67) winsize 62
719 13:53:23.368502 [CA 1] Center 36 (6~67) winsize 62
720 13:53:23.372432 [CA 2] Center 34 (4~65) winsize 62
721 13:53:23.375641 [CA 3] Center 33 (3~64) winsize 62
722 13:53:23.379428 [CA 4] Center 33 (2~64) winsize 63
723 13:53:23.383442 [CA 5] Center 32 (2~62) winsize 61
724 13:53:23.383564
725 13:53:23.387493 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 13:53:23.387610
727 13:53:23.391152 [CATrainingPosCal] consider 1 rank data
728 13:53:23.391266 u2DelayCellTimex100 = 270/100 ps
729 13:53:23.394611 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
730 13:53:23.398656 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
731 13:53:23.401936 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
732 13:53:23.405786 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
733 13:53:23.409823 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
734 13:53:23.413205 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
735 13:53:23.413371
736 13:53:23.416634 CA PerBit enable=1, Macro0, CA PI delay=32
737 13:53:23.416768
738 13:53:23.419931 [CBTSetCACLKResult] CA Dly = 32
739 13:53:23.423226 CS Dly: 5 (0~36)
740 13:53:23.423374 ==
741 13:53:23.427495 Dram Type= 6, Freq= 0, CH_0, rank 1
742 13:53:23.431008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 13:53:23.431146 ==
744 13:53:23.434633 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 13:53:23.441481 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 13:53:23.451104 [CA 0] Center 36 (6~67) winsize 62
747 13:53:23.454610 [CA 1] Center 36 (6~67) winsize 62
748 13:53:23.458169 [CA 2] Center 34 (4~65) winsize 62
749 13:53:23.462494 [CA 3] Center 34 (3~65) winsize 63
750 13:53:23.466118 [CA 4] Center 33 (3~63) winsize 61
751 13:53:23.466239 [CA 5] Center 32 (2~63) winsize 62
752 13:53:23.469598
753 13:53:23.473803 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 13:53:23.473951
755 13:53:23.476766 [CATrainingPosCal] consider 2 rank data
756 13:53:23.476860 u2DelayCellTimex100 = 270/100 ps
757 13:53:23.481041 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
758 13:53:23.485097 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
759 13:53:23.489065 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
760 13:53:23.492999 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
761 13:53:23.496925 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
762 13:53:23.501075 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
763 13:53:23.501229
764 13:53:23.504172 CA PerBit enable=1, Macro0, CA PI delay=32
765 13:53:23.504317
766 13:53:23.508086 [CBTSetCACLKResult] CA Dly = 32
767 13:53:23.508220 CS Dly: 5 (0~36)
768 13:53:23.508318
769 13:53:23.511904 ----->DramcWriteLeveling(PI) begin...
770 13:53:23.512034 ==
771 13:53:23.515595 Dram Type= 6, Freq= 0, CH_0, rank 0
772 13:53:23.518786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 13:53:23.518933 ==
774 13:53:23.523127 Write leveling (Byte 0): 31 => 31
775 13:53:23.526464 Write leveling (Byte 1): 29 => 29
776 13:53:23.530536 DramcWriteLeveling(PI) end<-----
777 13:53:23.530679
778 13:53:23.530777 ==
779 13:53:23.534462 Dram Type= 6, Freq= 0, CH_0, rank 0
780 13:53:23.538001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 13:53:23.538153 ==
782 13:53:23.541529 [Gating] SW mode calibration
783 13:53:23.549415 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 13:53:23.552895 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 13:53:23.556371 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 13:53:23.559916 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 13:53:23.567736 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
788 13:53:23.571367 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 13:53:23.575000 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:53:23.579092 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:53:23.582747 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:53:23.586338 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:53:23.590603 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:53:23.597794 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:53:23.602036 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:53:23.605475 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:53:23.609410 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:53:23.612483 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:53:23.619856 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:53:23.623851 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:53:23.627605 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:53:23.631106 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 13:53:23.635586 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
804 13:53:23.639577 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 13:53:23.646748 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:53:23.650641 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:53:23.654070 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:53:23.658128 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:53:23.661735 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:53:23.665842 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 13:53:23.669433 0 9 8 | B1->B0 | 2323 3030 | 1 0 | (0 0) (1 1)
812 13:53:23.676582 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (1 1) (1 1)
813 13:53:23.680164 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 13:53:23.683660 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 13:53:23.687970 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 13:53:23.691644 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 13:53:23.699353 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 13:53:23.702759 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
819 13:53:23.705760 0 10 8 | B1->B0 | 3030 2828 | 1 0 | (1 0) (1 0)
820 13:53:23.709340 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
821 13:53:23.716204 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 13:53:23.719087 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:53:23.722242 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:53:23.729339 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 13:53:23.732898 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 13:53:23.736016 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
827 13:53:23.743038 0 11 8 | B1->B0 | 2b2b 3e3e | 0 1 | (0 0) (0 0)
828 13:53:23.746162 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
829 13:53:23.749145 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 13:53:23.752611 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 13:53:23.759251 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 13:53:23.762565 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 13:53:23.766450 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 13:53:23.773080 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
835 13:53:23.776336 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 13:53:23.779664 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 13:53:23.786152 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 13:53:23.789643 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:53:23.793170 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:53:23.799488 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:53:23.802866 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:53:23.806434 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:53:23.812816 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:53:23.816584 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:53:23.819604 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:53:23.826672 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:53:23.829910 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:53:23.832680 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:53:23.836219 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:53:23.843251 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
851 13:53:23.845960 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
852 13:53:23.849440 Total UI for P1: 0, mck2ui 16
853 13:53:23.852888 best dqsien dly found for B0: ( 0, 14, 4)
854 13:53:23.856267 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
855 13:53:23.859746 Total UI for P1: 0, mck2ui 16
856 13:53:23.863012 best dqsien dly found for B1: ( 0, 14, 10)
857 13:53:23.866366 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
858 13:53:23.869318 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
859 13:53:23.872937
860 13:53:23.876688 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
861 13:53:23.879396 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
862 13:53:23.882672 [Gating] SW calibration Done
863 13:53:23.882786 ==
864 13:53:23.886404 Dram Type= 6, Freq= 0, CH_0, rank 0
865 13:53:23.889406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 13:53:23.889511 ==
867 13:53:23.889600 RX Vref Scan: 0
868 13:53:23.889682
869 13:53:23.893500 RX Vref 0 -> 0, step: 1
870 13:53:23.893593
871 13:53:23.897396 RX Delay -130 -> 252, step: 16
872 13:53:23.901095 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
873 13:53:23.904708 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
874 13:53:23.908877 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 13:53:23.912215 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
876 13:53:23.916484 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
877 13:53:23.920298 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
878 13:53:23.923697 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
879 13:53:23.928095 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
880 13:53:23.931435 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
881 13:53:23.934985 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
882 13:53:23.941219 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
883 13:53:23.944835 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
884 13:53:23.948192 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
885 13:53:23.951600 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
886 13:53:23.955323 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
887 13:53:23.961718 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
888 13:53:23.961855 ==
889 13:53:23.965218 Dram Type= 6, Freq= 0, CH_0, rank 0
890 13:53:23.968029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 13:53:23.968166 ==
892 13:53:23.968270 DQS Delay:
893 13:53:23.971707 DQS0 = 0, DQS1 = 0
894 13:53:23.971842 DQM Delay:
895 13:53:23.975042 DQM0 = 91, DQM1 = 84
896 13:53:23.975172 DQ Delay:
897 13:53:23.977999 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =93
898 13:53:23.981576 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
899 13:53:23.985090 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
900 13:53:23.987937 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
901 13:53:23.988051
902 13:53:23.988148
903 13:53:23.988238 ==
904 13:53:23.991515 Dram Type= 6, Freq= 0, CH_0, rank 0
905 13:53:23.995059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 13:53:23.995176 ==
907 13:53:23.995274
908 13:53:23.995364
909 13:53:23.998333 TX Vref Scan disable
910 13:53:24.001684 == TX Byte 0 ==
911 13:53:24.004895 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
912 13:53:24.008543 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
913 13:53:24.011602 == TX Byte 1 ==
914 13:53:24.015238 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
915 13:53:24.018367 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
916 13:53:24.018511 ==
917 13:53:24.021907 Dram Type= 6, Freq= 0, CH_0, rank 0
918 13:53:24.028157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 13:53:24.028299 ==
920 13:53:24.040050 TX Vref=22, minBit 9, minWin=27, winSum=447
921 13:53:24.043396 TX Vref=24, minBit 8, minWin=27, winSum=452
922 13:53:24.046892 TX Vref=26, minBit 8, minWin=27, winSum=454
923 13:53:24.049577 TX Vref=28, minBit 8, minWin=28, winSum=458
924 13:53:24.053480 TX Vref=30, minBit 8, minWin=28, winSum=458
925 13:53:24.057072 TX Vref=32, minBit 11, minWin=27, winSum=456
926 13:53:24.063296 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 28
927 13:53:24.063452
928 13:53:24.066879 Final TX Range 1 Vref 28
929 13:53:24.067004
930 13:53:24.067101 ==
931 13:53:24.069783 Dram Type= 6, Freq= 0, CH_0, rank 0
932 13:53:24.073345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 13:53:24.073444 ==
934 13:53:24.076231
935 13:53:24.076349
936 13:53:24.076420 TX Vref Scan disable
937 13:53:24.080440 == TX Byte 0 ==
938 13:53:24.083754 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
939 13:53:24.087080 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
940 13:53:24.090599 == TX Byte 1 ==
941 13:53:24.094051 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
942 13:53:24.097636 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
943 13:53:24.097762
944 13:53:24.100503 [DATLAT]
945 13:53:24.100585 Freq=800, CH0 RK0
946 13:53:24.100655
947 13:53:24.104105 DATLAT Default: 0xa
948 13:53:24.104216 0, 0xFFFF, sum = 0
949 13:53:24.107594 1, 0xFFFF, sum = 0
950 13:53:24.107703 2, 0xFFFF, sum = 0
951 13:53:24.110461 3, 0xFFFF, sum = 0
952 13:53:24.110575 4, 0xFFFF, sum = 0
953 13:53:24.113859 5, 0xFFFF, sum = 0
954 13:53:24.113989 6, 0xFFFF, sum = 0
955 13:53:24.117574 7, 0xFFFF, sum = 0
956 13:53:24.117707 8, 0xFFFF, sum = 0
957 13:53:24.120930 9, 0x0, sum = 1
958 13:53:24.121064 10, 0x0, sum = 2
959 13:53:24.124128 11, 0x0, sum = 3
960 13:53:24.124250 12, 0x0, sum = 4
961 13:53:24.127399 best_step = 10
962 13:53:24.127506
963 13:53:24.127634 ==
964 13:53:24.130527 Dram Type= 6, Freq= 0, CH_0, rank 0
965 13:53:24.134042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 13:53:24.134164 ==
967 13:53:24.134259 RX Vref Scan: 1
968 13:53:24.134364
969 13:53:24.137466 Set Vref Range= 32 -> 127
970 13:53:24.137637
971 13:53:24.140869 RX Vref 32 -> 127, step: 1
972 13:53:24.140977
973 13:53:24.144026 RX Delay -95 -> 252, step: 8
974 13:53:24.144152
975 13:53:24.147627 Set Vref, RX VrefLevel [Byte0]: 32
976 13:53:24.151049 [Byte1]: 32
977 13:53:24.151166
978 13:53:24.154021 Set Vref, RX VrefLevel [Byte0]: 33
979 13:53:24.157517 [Byte1]: 33
980 13:53:24.157663
981 13:53:24.160853 Set Vref, RX VrefLevel [Byte0]: 34
982 13:53:24.164051 [Byte1]: 34
983 13:53:24.167878
984 13:53:24.167991 Set Vref, RX VrefLevel [Byte0]: 35
985 13:53:24.171521 [Byte1]: 35
986 13:53:24.175766
987 13:53:24.175897 Set Vref, RX VrefLevel [Byte0]: 36
988 13:53:24.178691 [Byte1]: 36
989 13:53:24.183072
990 13:53:24.183187 Set Vref, RX VrefLevel [Byte0]: 37
991 13:53:24.186481 [Byte1]: 37
992 13:53:24.190787
993 13:53:24.190926 Set Vref, RX VrefLevel [Byte0]: 38
994 13:53:24.194035 [Byte1]: 38
995 13:53:24.198378
996 13:53:24.198525 Set Vref, RX VrefLevel [Byte0]: 39
997 13:53:24.201925 [Byte1]: 39
998 13:53:24.205557
999 13:53:24.205690 Set Vref, RX VrefLevel [Byte0]: 40
1000 13:53:24.209382 [Byte1]: 40
1001 13:53:24.213430
1002 13:53:24.213534 Set Vref, RX VrefLevel [Byte0]: 41
1003 13:53:24.216772 [Byte1]: 41
1004 13:53:24.221097
1005 13:53:24.221227 Set Vref, RX VrefLevel [Byte0]: 42
1006 13:53:24.223988 [Byte1]: 42
1007 13:53:24.228407
1008 13:53:24.232242 Set Vref, RX VrefLevel [Byte0]: 43
1009 13:53:24.232387 [Byte1]: 43
1010 13:53:24.236641
1011 13:53:24.236747 Set Vref, RX VrefLevel [Byte0]: 44
1012 13:53:24.239349 [Byte1]: 44
1013 13:53:24.243968
1014 13:53:24.244093 Set Vref, RX VrefLevel [Byte0]: 45
1015 13:53:24.247219 [Byte1]: 45
1016 13:53:24.251672
1017 13:53:24.251780 Set Vref, RX VrefLevel [Byte0]: 46
1018 13:53:24.254676 [Byte1]: 46
1019 13:53:24.259066
1020 13:53:24.259193 Set Vref, RX VrefLevel [Byte0]: 47
1021 13:53:24.262482 [Byte1]: 47
1022 13:53:24.266626
1023 13:53:24.266718 Set Vref, RX VrefLevel [Byte0]: 48
1024 13:53:24.269872 [Byte1]: 48
1025 13:53:24.274209
1026 13:53:24.274306 Set Vref, RX VrefLevel [Byte0]: 49
1027 13:53:24.277532 [Byte1]: 49
1028 13:53:24.282076
1029 13:53:24.282181 Set Vref, RX VrefLevel [Byte0]: 50
1030 13:53:24.284850 [Byte1]: 50
1031 13:53:24.289081
1032 13:53:24.289182 Set Vref, RX VrefLevel [Byte0]: 51
1033 13:53:24.292608 [Byte1]: 51
1034 13:53:24.297344
1035 13:53:24.297469 Set Vref, RX VrefLevel [Byte0]: 52
1036 13:53:24.300586 [Byte1]: 52
1037 13:53:24.304786
1038 13:53:24.304911 Set Vref, RX VrefLevel [Byte0]: 53
1039 13:53:24.308348 [Byte1]: 53
1040 13:53:24.311924
1041 13:53:24.312028 Set Vref, RX VrefLevel [Byte0]: 54
1042 13:53:24.315523 [Byte1]: 54
1043 13:53:24.319691
1044 13:53:24.319802 Set Vref, RX VrefLevel [Byte0]: 55
1045 13:53:24.323239 [Byte1]: 55
1046 13:53:24.327520
1047 13:53:24.331100 Set Vref, RX VrefLevel [Byte0]: 56
1048 13:53:24.331202 [Byte1]: 56
1049 13:53:24.335345
1050 13:53:24.335442 Set Vref, RX VrefLevel [Byte0]: 57
1051 13:53:24.338352 [Byte1]: 57
1052 13:53:24.342677
1053 13:53:24.342818 Set Vref, RX VrefLevel [Byte0]: 58
1054 13:53:24.345732 [Byte1]: 58
1055 13:53:24.350063
1056 13:53:24.350172 Set Vref, RX VrefLevel [Byte0]: 59
1057 13:53:24.353705 [Byte1]: 59
1058 13:53:24.357883
1059 13:53:24.357988 Set Vref, RX VrefLevel [Byte0]: 60
1060 13:53:24.360866 [Byte1]: 60
1061 13:53:24.365248
1062 13:53:24.365353 Set Vref, RX VrefLevel [Byte0]: 61
1063 13:53:24.368641 [Byte1]: 61
1064 13:53:24.372921
1065 13:53:24.373028 Set Vref, RX VrefLevel [Byte0]: 62
1066 13:53:24.376385 [Byte1]: 62
1067 13:53:24.380491
1068 13:53:24.380592 Set Vref, RX VrefLevel [Byte0]: 63
1069 13:53:24.383674 [Byte1]: 63
1070 13:53:24.388332
1071 13:53:24.388479 Set Vref, RX VrefLevel [Byte0]: 64
1072 13:53:24.391364 [Byte1]: 64
1073 13:53:24.395893
1074 13:53:24.396038 Set Vref, RX VrefLevel [Byte0]: 65
1075 13:53:24.398833 [Byte1]: 65
1076 13:53:24.403562
1077 13:53:24.403664 Set Vref, RX VrefLevel [Byte0]: 66
1078 13:53:24.406953 [Byte1]: 66
1079 13:53:24.410972
1080 13:53:24.411078 Set Vref, RX VrefLevel [Byte0]: 67
1081 13:53:24.414175 [Byte1]: 67
1082 13:53:24.418473
1083 13:53:24.418585 Set Vref, RX VrefLevel [Byte0]: 68
1084 13:53:24.421950 [Byte1]: 68
1085 13:53:24.426318
1086 13:53:24.426424 Set Vref, RX VrefLevel [Byte0]: 69
1087 13:53:24.429798 [Byte1]: 69
1088 13:53:24.433654
1089 13:53:24.433760 Set Vref, RX VrefLevel [Byte0]: 70
1090 13:53:24.437269 [Byte1]: 70
1091 13:53:24.440934
1092 13:53:24.444500 Set Vref, RX VrefLevel [Byte0]: 71
1093 13:53:24.448152 [Byte1]: 71
1094 13:53:24.448275
1095 13:53:24.451046 Set Vref, RX VrefLevel [Byte0]: 72
1096 13:53:24.454543 [Byte1]: 72
1097 13:53:24.454659
1098 13:53:24.458014 Set Vref, RX VrefLevel [Byte0]: 73
1099 13:53:24.460820 [Byte1]: 73
1100 13:53:24.460943
1101 13:53:24.464310 Set Vref, RX VrefLevel [Byte0]: 74
1102 13:53:24.468007 [Byte1]: 74
1103 13:53:24.472221
1104 13:53:24.472356 Set Vref, RX VrefLevel [Byte0]: 75
1105 13:53:24.475864 [Byte1]: 75
1106 13:53:24.479399
1107 13:53:24.479510 Set Vref, RX VrefLevel [Byte0]: 76
1108 13:53:24.482913 [Byte1]: 76
1109 13:53:24.487229
1110 13:53:24.487350 Final RX Vref Byte 0 = 55 to rank0
1111 13:53:24.490861 Final RX Vref Byte 1 = 65 to rank0
1112 13:53:24.493847 Final RX Vref Byte 0 = 55 to rank1
1113 13:53:24.497318 Final RX Vref Byte 1 = 65 to rank1==
1114 13:53:24.501014 Dram Type= 6, Freq= 0, CH_0, rank 0
1115 13:53:24.504781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1116 13:53:24.504912 ==
1117 13:53:24.507577 DQS Delay:
1118 13:53:24.507687 DQS0 = 0, DQS1 = 0
1119 13:53:24.511154 DQM Delay:
1120 13:53:24.511250 DQM0 = 91, DQM1 = 86
1121 13:53:24.511318 DQ Delay:
1122 13:53:24.514492 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1123 13:53:24.517484 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1124 13:53:24.520921 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =76
1125 13:53:24.524150 DQ12 =92, DQ13 =92, DQ14 =100, DQ15 =92
1126 13:53:24.524275
1127 13:53:24.524389
1128 13:53:24.534220 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d42, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1129 13:53:24.537767 CH0 RK0: MR19=606, MR18=4D42
1130 13:53:24.544387 CH0_RK0: MR19=0x606, MR18=0x4D42, DQSOSC=390, MR23=63, INC=97, DEC=64
1131 13:53:24.544520
1132 13:53:24.547524 ----->DramcWriteLeveling(PI) begin...
1133 13:53:24.547614 ==
1134 13:53:24.551316 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 13:53:24.554251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 13:53:24.554403 ==
1137 13:53:24.557388 Write leveling (Byte 0): 34 => 34
1138 13:53:24.561147 Write leveling (Byte 1): 30 => 30
1139 13:53:24.564601 DramcWriteLeveling(PI) end<-----
1140 13:53:24.564705
1141 13:53:24.564773 ==
1142 13:53:24.568120 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 13:53:24.571029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 13:53:24.571135 ==
1145 13:53:24.574584 [Gating] SW mode calibration
1146 13:53:24.581416 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1147 13:53:24.587934 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1148 13:53:24.591547 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1149 13:53:24.594365 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 13:53:24.598025 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1151 13:53:24.604330 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 13:53:24.607820 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 13:53:24.611450 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 13:53:24.617578 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 13:53:24.621075 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 13:53:24.624843 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 13:53:24.631106 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 13:53:24.634812 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 13:53:24.638258 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 13:53:24.644994 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 13:53:24.648486 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:53:24.651274 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:53:24.658252 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:53:24.661661 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 13:53:24.664966 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 13:53:24.667999 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1167 13:53:24.674994 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 13:53:24.678068 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 13:53:24.681569 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 13:53:24.688455 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 13:53:24.691500 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:53:24.694981 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 13:53:24.701499 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:53:24.704907 0 9 8 | B1->B0 | 2e2e 2929 | 1 1 | (0 0) (1 1)
1175 13:53:24.708557 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 13:53:24.714986 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 13:53:24.717900 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 13:53:24.721369 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 13:53:24.728362 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 13:53:24.731254 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 13:53:24.734606 0 10 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1182 13:53:24.741657 0 10 8 | B1->B0 | 2727 2727 | 1 1 | (1 0) (1 1)
1183 13:53:24.745083 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 13:53:24.748603 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 13:53:24.751326 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 13:53:24.758432 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 13:53:24.761272 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 13:53:24.764967 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 13:53:24.771332 0 11 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1190 13:53:24.774984 0 11 8 | B1->B0 | 3e3e 3636 | 0 0 | (0 0) (0 0)
1191 13:53:24.778457 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 13:53:24.784828 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 13:53:24.788465 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 13:53:24.791849 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 13:53:24.798934 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 13:53:24.802161 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 13:53:24.805442 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 13:53:24.808803 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1199 13:53:24.815580 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 13:53:24.818669 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 13:53:24.822009 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 13:53:24.828956 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 13:53:24.832237 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 13:53:24.835039 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 13:53:24.842082 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 13:53:24.845628 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:53:24.848454 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 13:53:24.855378 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 13:53:24.858429 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:53:24.861657 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 13:53:24.868639 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 13:53:24.872201 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 13:53:24.875092 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1214 13:53:24.881641 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1215 13:53:24.885265 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 13:53:24.888745 Total UI for P1: 0, mck2ui 16
1217 13:53:24.892171 best dqsien dly found for B0: ( 0, 14, 6)
1218 13:53:24.895072 Total UI for P1: 0, mck2ui 16
1219 13:53:24.898607 best dqsien dly found for B1: ( 0, 14, 8)
1220 13:53:24.902089 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1221 13:53:24.905582 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1222 13:53:24.905713
1223 13:53:24.908945 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1224 13:53:24.912365 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1225 13:53:24.915746 [Gating] SW calibration Done
1226 13:53:24.915841 ==
1227 13:53:24.918460 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 13:53:24.921908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1229 13:53:24.922029 ==
1230 13:53:24.925301 RX Vref Scan: 0
1231 13:53:24.925383
1232 13:53:24.925446 RX Vref 0 -> 0, step: 1
1233 13:53:24.929132
1234 13:53:24.929230 RX Delay -130 -> 252, step: 16
1235 13:53:24.935483 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1236 13:53:24.938809 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1237 13:53:24.942075 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1238 13:53:24.945926 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1239 13:53:24.948812 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1240 13:53:24.952600 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1241 13:53:24.958833 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1242 13:53:24.962438 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1243 13:53:24.965358 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1244 13:53:24.969256 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1245 13:53:24.972562 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1246 13:53:24.979096 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1247 13:53:24.982660 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1248 13:53:24.985563 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1249 13:53:24.989151 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1250 13:53:24.995587 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1251 13:53:24.995729 ==
1252 13:53:24.999012 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 13:53:25.002551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1254 13:53:25.002669 ==
1255 13:53:25.002764 DQS Delay:
1256 13:53:25.005495 DQS0 = 0, DQS1 = 0
1257 13:53:25.005617 DQM Delay:
1258 13:53:25.008984 DQM0 = 90, DQM1 = 81
1259 13:53:25.009105 DQ Delay:
1260 13:53:25.012602 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1261 13:53:25.016116 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1262 13:53:25.019645 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1263 13:53:25.022442 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1264 13:53:25.022571
1265 13:53:25.022669
1266 13:53:25.022759 ==
1267 13:53:25.025892 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 13:53:25.029451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 13:53:25.029582 ==
1270 13:53:25.029679
1271 13:53:25.029772
1272 13:53:25.032324 TX Vref Scan disable
1273 13:53:25.035965 == TX Byte 0 ==
1274 13:53:25.039533 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1275 13:53:25.043176 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1276 13:53:25.045878 == TX Byte 1 ==
1277 13:53:25.049607 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1278 13:53:25.052316 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1279 13:53:25.052453 ==
1280 13:53:25.055803 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 13:53:25.059265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 13:53:25.062284 ==
1283 13:53:25.074252 TX Vref=22, minBit 8, minWin=27, winSum=447
1284 13:53:25.077290 TX Vref=24, minBit 9, minWin=27, winSum=453
1285 13:53:25.081142 TX Vref=26, minBit 1, minWin=28, winSum=456
1286 13:53:25.084131 TX Vref=28, minBit 4, minWin=28, winSum=458
1287 13:53:25.087872 TX Vref=30, minBit 4, minWin=28, winSum=459
1288 13:53:25.090992 TX Vref=32, minBit 2, minWin=28, winSum=457
1289 13:53:25.097592 [TxChooseVref] Worse bit 4, Min win 28, Win sum 459, Final Vref 30
1290 13:53:25.097745
1291 13:53:25.100925 Final TX Range 1 Vref 30
1292 13:53:25.101019
1293 13:53:25.101115 ==
1294 13:53:25.104368 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 13:53:25.107788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 13:53:25.107900 ==
1297 13:53:25.107967
1298 13:53:25.108028
1299 13:53:25.111083 TX Vref Scan disable
1300 13:53:25.114267 == TX Byte 0 ==
1301 13:53:25.117787 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1302 13:53:25.120556 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1303 13:53:25.124052 == TX Byte 1 ==
1304 13:53:25.127499 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1305 13:53:25.134328 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1306 13:53:25.134481
1307 13:53:25.134581 [DATLAT]
1308 13:53:25.134674 Freq=800, CH0 RK1
1309 13:53:25.134764
1310 13:53:25.138152 DATLAT Default: 0xa
1311 13:53:25.138267 0, 0xFFFF, sum = 0
1312 13:53:25.141586 1, 0xFFFF, sum = 0
1313 13:53:25.141708 2, 0xFFFF, sum = 0
1314 13:53:25.145227 3, 0xFFFF, sum = 0
1315 13:53:25.145323 4, 0xFFFF, sum = 0
1316 13:53:25.148866 5, 0xFFFF, sum = 0
1317 13:53:25.148990 6, 0xFFFF, sum = 0
1318 13:53:25.152365 7, 0xFFFF, sum = 0
1319 13:53:25.152485 8, 0xFFFF, sum = 0
1320 13:53:25.152585 9, 0x0, sum = 1
1321 13:53:25.155973 10, 0x0, sum = 2
1322 13:53:25.156067 11, 0x0, sum = 3
1323 13:53:25.160166 12, 0x0, sum = 4
1324 13:53:25.160298 best_step = 10
1325 13:53:25.160397
1326 13:53:25.160461 ==
1327 13:53:25.163714 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 13:53:25.168056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 13:53:25.168191 ==
1330 13:53:25.171607 RX Vref Scan: 0
1331 13:53:25.171713
1332 13:53:25.171807 RX Vref 0 -> 0, step: 1
1333 13:53:25.171906
1334 13:53:25.175163 RX Delay -79 -> 252, step: 8
1335 13:53:25.178386 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1336 13:53:25.185228 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1337 13:53:25.188047 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1338 13:53:25.191634 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1339 13:53:25.195247 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1340 13:53:25.198066 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1341 13:53:25.204657 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1342 13:53:25.208257 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1343 13:53:25.211575 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1344 13:53:25.214745 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1345 13:53:25.218086 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1346 13:53:25.224664 iDelay=209, Bit 11, Center 72 (-31 ~ 176) 208
1347 13:53:25.228181 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1348 13:53:25.231731 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1349 13:53:25.235174 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1350 13:53:25.238764 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1351 13:53:25.241248 ==
1352 13:53:25.241367 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 13:53:25.247987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 13:53:25.248125 ==
1355 13:53:25.248221 DQS Delay:
1356 13:53:25.251646 DQS0 = 0, DQS1 = 0
1357 13:53:25.251740 DQM Delay:
1358 13:53:25.255319 DQM0 = 92, DQM1 = 82
1359 13:53:25.255437 DQ Delay:
1360 13:53:25.258130 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =88
1361 13:53:25.261802 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1362 13:53:25.264659 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =72
1363 13:53:25.268069 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =88
1364 13:53:25.268179
1365 13:53:25.268270
1366 13:53:25.275294 [DQSOSCAuto] RK1, (LSB)MR18= 0x4516, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1367 13:53:25.278039 CH0 RK1: MR19=606, MR18=4516
1368 13:53:25.284963 CH0_RK1: MR19=0x606, MR18=0x4516, DQSOSC=392, MR23=63, INC=96, DEC=64
1369 13:53:25.288675 [RxdqsGatingPostProcess] freq 800
1370 13:53:25.291361 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1371 13:53:25.295042 Pre-setting of DQS Precalculation
1372 13:53:25.301501 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1373 13:53:25.301648 ==
1374 13:53:25.305100 Dram Type= 6, Freq= 0, CH_1, rank 0
1375 13:53:25.308212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 13:53:25.308350 ==
1377 13:53:25.314750 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1378 13:53:25.321149 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1379 13:53:25.329021 [CA 0] Center 36 (6~67) winsize 62
1380 13:53:25.332401 [CA 1] Center 36 (6~67) winsize 62
1381 13:53:25.335969 [CA 2] Center 35 (4~66) winsize 63
1382 13:53:25.338881 [CA 3] Center 34 (4~65) winsize 62
1383 13:53:25.342368 [CA 4] Center 34 (4~65) winsize 62
1384 13:53:25.345656 [CA 5] Center 34 (3~65) winsize 63
1385 13:53:25.345778
1386 13:53:25.348998 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1387 13:53:25.349113
1388 13:53:25.352360 [CATrainingPosCal] consider 1 rank data
1389 13:53:25.356170 u2DelayCellTimex100 = 270/100 ps
1390 13:53:25.359112 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1391 13:53:25.362456 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1392 13:53:25.365921 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1393 13:53:25.372785 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1394 13:53:25.376380 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1395 13:53:25.379206 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1396 13:53:25.379317
1397 13:53:25.382511 CA PerBit enable=1, Macro0, CA PI delay=34
1398 13:53:25.382620
1399 13:53:25.385987 [CBTSetCACLKResult] CA Dly = 34
1400 13:53:25.386096 CS Dly: 6 (0~37)
1401 13:53:25.386192 ==
1402 13:53:25.389362 Dram Type= 6, Freq= 0, CH_1, rank 1
1403 13:53:25.396259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 13:53:25.396403 ==
1405 13:53:25.399785 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1406 13:53:25.406243 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1407 13:53:25.414960 [CA 0] Center 36 (6~67) winsize 62
1408 13:53:25.418425 [CA 1] Center 37 (6~68) winsize 63
1409 13:53:25.421629 [CA 2] Center 35 (5~66) winsize 62
1410 13:53:25.425402 [CA 3] Center 34 (4~65) winsize 62
1411 13:53:25.428240 [CA 4] Center 35 (4~66) winsize 63
1412 13:53:25.431795 [CA 5] Center 34 (4~65) winsize 62
1413 13:53:25.431924
1414 13:53:25.435100 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1415 13:53:25.435268
1416 13:53:25.438600 [CATrainingPosCal] consider 2 rank data
1417 13:53:25.442200 u2DelayCellTimex100 = 270/100 ps
1418 13:53:25.445188 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1419 13:53:25.448598 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1420 13:53:25.455232 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1421 13:53:25.458266 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1422 13:53:25.461780 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1423 13:53:25.465384 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1424 13:53:25.465508
1425 13:53:25.468862 CA PerBit enable=1, Macro0, CA PI delay=34
1426 13:53:25.468974
1427 13:53:25.472202 [CBTSetCACLKResult] CA Dly = 34
1428 13:53:25.472316 CS Dly: 6 (0~38)
1429 13:53:25.472424
1430 13:53:25.475290 ----->DramcWriteLeveling(PI) begin...
1431 13:53:25.478472 ==
1432 13:53:25.478587 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 13:53:25.485511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 13:53:25.485659 ==
1435 13:53:25.488395 Write leveling (Byte 0): 28 => 28
1436 13:53:25.491990 Write leveling (Byte 1): 29 => 29
1437 13:53:25.495120 DramcWriteLeveling(PI) end<-----
1438 13:53:25.495256
1439 13:53:25.495354 ==
1440 13:53:25.498317 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 13:53:25.502081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 13:53:25.502195 ==
1443 13:53:25.505441 [Gating] SW mode calibration
1444 13:53:25.512260 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1445 13:53:25.515134 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1446 13:53:25.522384 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1447 13:53:25.525108 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1448 13:53:25.528406 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 13:53:25.535634 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 13:53:25.538301 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 13:53:25.541741 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 13:53:25.548781 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 13:53:25.552303 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 13:53:25.555006 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 13:53:25.562183 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:53:25.565142 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 13:53:25.568745 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:53:25.575238 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 13:53:25.578801 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 13:53:25.581671 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 13:53:25.585227 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 13:53:25.592223 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1463 13:53:25.595623 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1464 13:53:25.598921 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 13:53:25.605171 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 13:53:25.608564 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 13:53:25.611802 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 13:53:25.618718 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 13:53:25.621935 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 13:53:25.625070 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 13:53:25.632224 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1472 13:53:25.635635 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1473 13:53:25.639024 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 13:53:25.645602 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 13:53:25.648920 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 13:53:25.652355 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 13:53:25.658736 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 13:53:25.662257 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1479 13:53:25.665170 0 10 4 | B1->B0 | 3232 2e2e | 1 0 | (0 0) (0 0)
1480 13:53:25.672452 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1481 13:53:25.675276 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 13:53:25.678856 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 13:53:25.682357 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 13:53:25.688800 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 13:53:25.692211 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 13:53:25.695834 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 13:53:25.702361 0 11 4 | B1->B0 | 2b2b 3131 | 0 0 | (0 0) (0 0)
1488 13:53:25.705348 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1489 13:53:25.708789 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 13:53:25.715540 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 13:53:25.719006 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 13:53:25.723297 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 13:53:25.726164 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 13:53:25.733237 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 13:53:25.736201 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1496 13:53:25.739851 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1497 13:53:25.746135 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 13:53:25.749411 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 13:53:25.753290 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 13:53:25.759609 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 13:53:25.762963 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 13:53:25.766489 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 13:53:25.772850 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 13:53:25.776153 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 13:53:25.779823 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 13:53:25.783449 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 13:53:25.789794 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 13:53:25.793354 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 13:53:25.796319 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 13:53:25.803169 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1511 13:53:25.806753 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1512 13:53:25.809652 Total UI for P1: 0, mck2ui 16
1513 13:53:25.813153 best dqsien dly found for B1: ( 0, 14, 0)
1514 13:53:25.816713 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 13:53:25.820008 Total UI for P1: 0, mck2ui 16
1516 13:53:25.822794 best dqsien dly found for B0: ( 0, 14, 4)
1517 13:53:25.826370 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1518 13:53:25.829985 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1519 13:53:25.830137
1520 13:53:25.836509 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1521 13:53:25.840184 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1522 13:53:25.840315 [Gating] SW calibration Done
1523 13:53:25.843040 ==
1524 13:53:25.843158 Dram Type= 6, Freq= 0, CH_1, rank 0
1525 13:53:25.849805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1526 13:53:25.849951 ==
1527 13:53:25.850050 RX Vref Scan: 0
1528 13:53:25.850140
1529 13:53:25.853122 RX Vref 0 -> 0, step: 1
1530 13:53:25.853242
1531 13:53:25.856149 RX Delay -130 -> 252, step: 16
1532 13:53:25.859412 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1533 13:53:25.862840 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1534 13:53:25.866298 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1535 13:53:25.873183 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1536 13:53:25.876235 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1537 13:53:25.880049 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1538 13:53:25.883162 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1539 13:53:25.886449 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1540 13:53:25.892954 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1541 13:53:25.896503 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1542 13:53:25.900142 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1543 13:53:25.903614 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1544 13:53:25.906257 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1545 13:53:25.913246 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1546 13:53:25.916868 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1547 13:53:25.919641 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1548 13:53:25.919778 ==
1549 13:53:25.923318 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 13:53:25.926618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1551 13:53:25.926741 ==
1552 13:53:25.929866 DQS Delay:
1553 13:53:25.929977 DQS0 = 0, DQS1 = 0
1554 13:53:25.933162 DQM Delay:
1555 13:53:25.933280 DQM0 = 93, DQM1 = 91
1556 13:53:25.933373 DQ Delay:
1557 13:53:25.936807 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1558 13:53:25.939661 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1559 13:53:25.943191 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1560 13:53:25.946833 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1561 13:53:25.949598
1562 13:53:25.949727
1563 13:53:25.949797 ==
1564 13:53:25.953071 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 13:53:25.956525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 13:53:25.956668 ==
1567 13:53:25.956766
1568 13:53:25.956856
1569 13:53:25.960058 TX Vref Scan disable
1570 13:53:25.960184 == TX Byte 0 ==
1571 13:53:25.966408 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1572 13:53:25.970047 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1573 13:53:25.970178 == TX Byte 1 ==
1574 13:53:25.976824 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1575 13:53:25.979917 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1576 13:53:25.980051 ==
1577 13:53:25.983207 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 13:53:25.986223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 13:53:25.986349 ==
1580 13:53:25.999779 TX Vref=22, minBit 3, minWin=26, winSum=435
1581 13:53:26.003382 TX Vref=24, minBit 0, minWin=27, winSum=440
1582 13:53:26.006862 TX Vref=26, minBit 0, minWin=27, winSum=448
1583 13:53:26.009931 TX Vref=28, minBit 0, minWin=27, winSum=446
1584 13:53:26.013247 TX Vref=30, minBit 7, minWin=27, winSum=452
1585 13:53:26.016609 TX Vref=32, minBit 2, minWin=27, winSum=450
1586 13:53:26.023157 [TxChooseVref] Worse bit 7, Min win 27, Win sum 452, Final Vref 30
1587 13:53:26.023322
1588 13:53:26.026746 Final TX Range 1 Vref 30
1589 13:53:26.026879
1590 13:53:26.026985 ==
1591 13:53:26.030254 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 13:53:26.033720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 13:53:26.033819 ==
1594 13:53:26.033921
1595 13:53:26.034020
1596 13:53:26.036996 TX Vref Scan disable
1597 13:53:26.040309 == TX Byte 0 ==
1598 13:53:26.043303 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1599 13:53:26.046819 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1600 13:53:26.050451 == TX Byte 1 ==
1601 13:53:26.053867 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1602 13:53:26.056679 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1603 13:53:26.056803
1604 13:53:26.060005 [DATLAT]
1605 13:53:26.060156 Freq=800, CH1 RK0
1606 13:53:26.060269
1607 13:53:26.063378 DATLAT Default: 0xa
1608 13:53:26.063512 0, 0xFFFF, sum = 0
1609 13:53:26.066948 1, 0xFFFF, sum = 0
1610 13:53:26.067082 2, 0xFFFF, sum = 0
1611 13:53:26.070508 3, 0xFFFF, sum = 0
1612 13:53:26.070642 4, 0xFFFF, sum = 0
1613 13:53:26.074175 5, 0xFFFF, sum = 0
1614 13:53:26.074290 6, 0xFFFF, sum = 0
1615 13:53:26.077196 7, 0xFFFF, sum = 0
1616 13:53:26.077329 8, 0xFFFF, sum = 0
1617 13:53:26.080280 9, 0x0, sum = 1
1618 13:53:26.080409 10, 0x0, sum = 2
1619 13:53:26.083673 11, 0x0, sum = 3
1620 13:53:26.083787 12, 0x0, sum = 4
1621 13:53:26.087033 best_step = 10
1622 13:53:26.087144
1623 13:53:26.087236 ==
1624 13:53:26.090583 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 13:53:26.093500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 13:53:26.093613 ==
1627 13:53:26.097157 RX Vref Scan: 1
1628 13:53:26.097263
1629 13:53:26.097358 Set Vref Range= 32 -> 127
1630 13:53:26.097451
1631 13:53:26.100533 RX Vref 32 -> 127, step: 1
1632 13:53:26.100639
1633 13:53:26.104054 RX Delay -79 -> 252, step: 8
1634 13:53:26.104160
1635 13:53:26.107353 Set Vref, RX VrefLevel [Byte0]: 32
1636 13:53:26.110581 [Byte1]: 32
1637 13:53:26.110701
1638 13:53:26.113872 Set Vref, RX VrefLevel [Byte0]: 33
1639 13:53:26.116972 [Byte1]: 33
1640 13:53:26.117094
1641 13:53:26.120801 Set Vref, RX VrefLevel [Byte0]: 34
1642 13:53:26.123842 [Byte1]: 34
1643 13:53:26.127435
1644 13:53:26.127604 Set Vref, RX VrefLevel [Byte0]: 35
1645 13:53:26.130967 [Byte1]: 35
1646 13:53:26.135369
1647 13:53:26.135524 Set Vref, RX VrefLevel [Byte0]: 36
1648 13:53:26.138377 [Byte1]: 36
1649 13:53:26.142590
1650 13:53:26.142722 Set Vref, RX VrefLevel [Byte0]: 37
1651 13:53:26.146325 [Byte1]: 37
1652 13:53:26.150319
1653 13:53:26.150456 Set Vref, RX VrefLevel [Byte0]: 38
1654 13:53:26.153793 [Byte1]: 38
1655 13:53:26.158160
1656 13:53:26.158308 Set Vref, RX VrefLevel [Byte0]: 39
1657 13:53:26.160816 [Byte1]: 39
1658 13:53:26.165652
1659 13:53:26.165782 Set Vref, RX VrefLevel [Byte0]: 40
1660 13:53:26.168438 [Byte1]: 40
1661 13:53:26.172901
1662 13:53:26.173012 Set Vref, RX VrefLevel [Byte0]: 41
1663 13:53:26.176518 [Byte1]: 41
1664 13:53:26.180766
1665 13:53:26.180904 Set Vref, RX VrefLevel [Byte0]: 42
1666 13:53:26.183726 [Byte1]: 42
1667 13:53:26.188260
1668 13:53:26.188409 Set Vref, RX VrefLevel [Byte0]: 43
1669 13:53:26.191661 [Byte1]: 43
1670 13:53:26.196041
1671 13:53:26.196180 Set Vref, RX VrefLevel [Byte0]: 44
1672 13:53:26.199001 [Byte1]: 44
1673 13:53:26.203152
1674 13:53:26.203298 Set Vref, RX VrefLevel [Byte0]: 45
1675 13:53:26.206200 [Byte1]: 45
1676 13:53:26.211100
1677 13:53:26.211242 Set Vref, RX VrefLevel [Byte0]: 46
1678 13:53:26.213932 [Byte1]: 46
1679 13:53:26.217956
1680 13:53:26.218098 Set Vref, RX VrefLevel [Byte0]: 47
1681 13:53:26.221437 [Byte1]: 47
1682 13:53:26.225796
1683 13:53:26.225945 Set Vref, RX VrefLevel [Byte0]: 48
1684 13:53:26.229407 [Byte1]: 48
1685 13:53:26.233641
1686 13:53:26.233777 Set Vref, RX VrefLevel [Byte0]: 49
1687 13:53:26.236525 [Byte1]: 49
1688 13:53:26.240654
1689 13:53:26.240753 Set Vref, RX VrefLevel [Byte0]: 50
1690 13:53:26.243872 [Byte1]: 50
1691 13:53:26.248260
1692 13:53:26.248426 Set Vref, RX VrefLevel [Byte0]: 51
1693 13:53:26.251654 [Byte1]: 51
1694 13:53:26.255973
1695 13:53:26.256105 Set Vref, RX VrefLevel [Byte0]: 52
1696 13:53:26.259414 [Byte1]: 52
1697 13:53:26.263768
1698 13:53:26.263864 Set Vref, RX VrefLevel [Byte0]: 53
1699 13:53:26.266736 [Byte1]: 53
1700 13:53:26.271247
1701 13:53:26.271373 Set Vref, RX VrefLevel [Byte0]: 54
1702 13:53:26.274291 [Byte1]: 54
1703 13:53:26.278904
1704 13:53:26.279041 Set Vref, RX VrefLevel [Byte0]: 55
1705 13:53:26.282031 [Byte1]: 55
1706 13:53:26.286082
1707 13:53:26.286188 Set Vref, RX VrefLevel [Byte0]: 56
1708 13:53:26.289423 [Byte1]: 56
1709 13:53:26.293551
1710 13:53:26.293650 Set Vref, RX VrefLevel [Byte0]: 57
1711 13:53:26.296934 [Byte1]: 57
1712 13:53:26.301408
1713 13:53:26.301517 Set Vref, RX VrefLevel [Byte0]: 58
1714 13:53:26.304240 [Byte1]: 58
1715 13:53:26.309046
1716 13:53:26.309176 Set Vref, RX VrefLevel [Byte0]: 59
1717 13:53:26.311842 [Byte1]: 59
1718 13:53:26.316095
1719 13:53:26.316231 Set Vref, RX VrefLevel [Byte0]: 60
1720 13:53:26.319511 [Byte1]: 60
1721 13:53:26.323691
1722 13:53:26.323816 Set Vref, RX VrefLevel [Byte0]: 61
1723 13:53:26.327492 [Byte1]: 61
1724 13:53:26.331780
1725 13:53:26.331888 Set Vref, RX VrefLevel [Byte0]: 62
1726 13:53:26.334591 [Byte1]: 62
1727 13:53:26.338773
1728 13:53:26.338902 Set Vref, RX VrefLevel [Byte0]: 63
1729 13:53:26.342384 [Byte1]: 63
1730 13:53:26.346566
1731 13:53:26.346697 Set Vref, RX VrefLevel [Byte0]: 64
1732 13:53:26.350019 [Byte1]: 64
1733 13:53:26.354137
1734 13:53:26.354274 Set Vref, RX VrefLevel [Byte0]: 65
1735 13:53:26.357254 [Byte1]: 65
1736 13:53:26.361812
1737 13:53:26.361930 Set Vref, RX VrefLevel [Byte0]: 66
1738 13:53:26.364686 [Byte1]: 66
1739 13:53:26.368932
1740 13:53:26.369026 Set Vref, RX VrefLevel [Byte0]: 67
1741 13:53:26.372325 [Byte1]: 67
1742 13:53:26.376944
1743 13:53:26.377118 Set Vref, RX VrefLevel [Byte0]: 68
1744 13:53:26.379779 [Byte1]: 68
1745 13:53:26.384115
1746 13:53:26.384246 Set Vref, RX VrefLevel [Byte0]: 69
1747 13:53:26.387585 [Byte1]: 69
1748 13:53:26.391656
1749 13:53:26.391791 Set Vref, RX VrefLevel [Byte0]: 70
1750 13:53:26.394873 [Byte1]: 70
1751 13:53:26.399339
1752 13:53:26.399466 Set Vref, RX VrefLevel [Byte0]: 71
1753 13:53:26.402424 [Byte1]: 71
1754 13:53:26.407189
1755 13:53:26.407294 Final RX Vref Byte 0 = 57 to rank0
1756 13:53:26.410263 Final RX Vref Byte 1 = 56 to rank0
1757 13:53:26.413827 Final RX Vref Byte 0 = 57 to rank1
1758 13:53:26.416766 Final RX Vref Byte 1 = 56 to rank1==
1759 13:53:26.420038 Dram Type= 6, Freq= 0, CH_1, rank 0
1760 13:53:26.423494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1761 13:53:26.426912 ==
1762 13:53:26.427059 DQS Delay:
1763 13:53:26.427175 DQS0 = 0, DQS1 = 0
1764 13:53:26.430501 DQM Delay:
1765 13:53:26.430628 DQM0 = 96, DQM1 = 90
1766 13:53:26.434017 DQ Delay:
1767 13:53:26.434145 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1768 13:53:26.440498 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =96
1769 13:53:26.440632 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1770 13:53:26.446970 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1771 13:53:26.447096
1772 13:53:26.447193
1773 13:53:26.453469 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1774 13:53:26.457129 CH1 RK0: MR19=606, MR18=2D4A
1775 13:53:26.464035 CH1_RK0: MR19=0x606, MR18=0x2D4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1776 13:53:26.464182
1777 13:53:26.467266 ----->DramcWriteLeveling(PI) begin...
1778 13:53:26.467370 ==
1779 13:53:26.470121 Dram Type= 6, Freq= 0, CH_1, rank 1
1780 13:53:26.473586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1781 13:53:26.473715 ==
1782 13:53:26.477185 Write leveling (Byte 0): 25 => 25
1783 13:53:26.480209 Write leveling (Byte 1): 27 => 27
1784 13:53:26.483535 DramcWriteLeveling(PI) end<-----
1785 13:53:26.483661
1786 13:53:26.483756 ==
1787 13:53:26.486851 Dram Type= 6, Freq= 0, CH_1, rank 1
1788 13:53:26.490320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1789 13:53:26.490457 ==
1790 13:53:26.493493 [Gating] SW mode calibration
1791 13:53:26.500119 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1792 13:53:26.507143 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1793 13:53:26.510701 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1794 13:53:26.514145 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1795 13:53:26.520316 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1796 13:53:26.523680 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1797 13:53:26.527237 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1798 13:53:26.533843 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 13:53:26.537010 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 13:53:26.540048 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 13:53:26.547126 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 13:53:26.550444 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 13:53:26.553908 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 13:53:26.560413 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 13:53:26.563767 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 13:53:26.566618 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 13:53:26.570017 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 13:53:26.576811 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 13:53:26.580193 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1810 13:53:26.583761 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1811 13:53:26.590244 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 13:53:26.593572 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 13:53:26.596917 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 13:53:26.603810 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 13:53:26.607037 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 13:53:26.610651 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 13:53:26.617102 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 13:53:26.620484 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1819 13:53:26.623890 0 9 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1820 13:53:26.630374 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1821 13:53:26.633609 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1822 13:53:26.637097 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1823 13:53:26.643602 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 13:53:26.647272 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 13:53:26.650655 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1826 13:53:26.657158 0 10 4 | B1->B0 | 2828 3131 | 0 0 | (0 0) (0 0)
1827 13:53:26.660643 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
1828 13:53:26.663835 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 13:53:26.666945 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 13:53:26.674323 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 13:53:26.677072 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 13:53:26.680412 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 13:53:26.687686 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1834 13:53:26.690422 0 11 4 | B1->B0 | 3b3b 2d2d | 0 0 | (0 0) (0 0)
1835 13:53:26.694020 0 11 8 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
1836 13:53:26.700304 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1837 13:53:26.703875 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1838 13:53:26.707344 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1839 13:53:26.714178 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 13:53:26.717016 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 13:53:26.720515 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1842 13:53:26.727003 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1843 13:53:26.730576 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1844 13:53:26.733936 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1845 13:53:26.740698 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1846 13:53:26.743961 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 13:53:26.747359 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 13:53:26.750963 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 13:53:26.757402 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 13:53:26.760308 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 13:53:26.763671 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 13:53:26.770832 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 13:53:26.773568 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 13:53:26.777017 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 13:53:26.783918 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 13:53:26.787333 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 13:53:26.790969 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 13:53:26.797206 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1859 13:53:26.797341 Total UI for P1: 0, mck2ui 16
1860 13:53:26.803661 best dqsien dly found for B1: ( 0, 14, 2)
1861 13:53:26.807160 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 13:53:26.810621 Total UI for P1: 0, mck2ui 16
1863 13:53:26.814019 best dqsien dly found for B0: ( 0, 14, 4)
1864 13:53:26.817528 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1865 13:53:26.820402 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1866 13:53:26.820520
1867 13:53:26.823989 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1868 13:53:26.827684 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1869 13:53:26.830439 [Gating] SW calibration Done
1870 13:53:26.830523 ==
1871 13:53:26.833990 Dram Type= 6, Freq= 0, CH_1, rank 1
1872 13:53:26.837524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1873 13:53:26.837609 ==
1874 13:53:26.841116 RX Vref Scan: 0
1875 13:53:26.841215
1876 13:53:26.841283 RX Vref 0 -> 0, step: 1
1877 13:53:26.843898
1878 13:53:26.844003 RX Delay -130 -> 252, step: 16
1879 13:53:26.850657 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1880 13:53:26.854095 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1881 13:53:26.857680 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1882 13:53:26.860431 iDelay=222, Bit 3, Center 93 (-2 ~ 189) 192
1883 13:53:26.864052 iDelay=222, Bit 4, Center 93 (-2 ~ 189) 192
1884 13:53:26.871018 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1885 13:53:26.873868 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1886 13:53:26.877447 iDelay=222, Bit 7, Center 101 (-2 ~ 205) 208
1887 13:53:26.880952 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1888 13:53:26.883779 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1889 13:53:26.887339 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1890 13:53:26.893954 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1891 13:53:26.897174 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1892 13:53:26.900874 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1893 13:53:26.904173 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1894 13:53:26.910482 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1895 13:53:26.910610 ==
1896 13:53:26.914050 Dram Type= 6, Freq= 0, CH_1, rank 1
1897 13:53:26.917322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1898 13:53:26.917452 ==
1899 13:53:26.917543 DQS Delay:
1900 13:53:26.920774 DQS0 = 0, DQS1 = 0
1901 13:53:26.920901 DQM Delay:
1902 13:53:26.924037 DQM0 = 96, DQM1 = 91
1903 13:53:26.924150 DQ Delay:
1904 13:53:26.927412 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =93
1905 13:53:26.931209 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =101
1906 13:53:26.941916 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1907 13:53:26.942050 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1908 13:53:26.942119
1909 13:53:26.942181
1910 13:53:26.942240 ==
1911 13:53:26.942298 Dram Type= 6, Freq= 0, CH_1, rank 1
1912 13:53:26.944106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1913 13:53:26.944192 ==
1914 13:53:26.947686
1915 13:53:26.947783
1916 13:53:26.947850 TX Vref Scan disable
1917 13:53:26.951154 == TX Byte 0 ==
1918 13:53:26.954226 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1919 13:53:26.957709 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1920 13:53:26.961118 == TX Byte 1 ==
1921 13:53:26.964358 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1922 13:53:26.967855 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1923 13:53:26.967960 ==
1924 13:53:26.971429 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 13:53:26.977794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 13:53:26.977921 ==
1927 13:53:26.989483 TX Vref=22, minBit 1, minWin=26, winSum=433
1928 13:53:26.992408 TX Vref=24, minBit 1, minWin=26, winSum=437
1929 13:53:26.995964 TX Vref=26, minBit 1, minWin=26, winSum=443
1930 13:53:26.999566 TX Vref=28, minBit 5, minWin=26, winSum=447
1931 13:53:27.002886 TX Vref=30, minBit 4, minWin=26, winSum=446
1932 13:53:27.006349 TX Vref=32, minBit 1, minWin=26, winSum=442
1933 13:53:27.012859 [TxChooseVref] Worse bit 5, Min win 26, Win sum 447, Final Vref 28
1934 13:53:27.012986
1935 13:53:27.015634 Final TX Range 1 Vref 28
1936 13:53:27.015737
1937 13:53:27.015843 ==
1938 13:53:27.019296 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 13:53:27.022976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 13:53:27.023101 ==
1941 13:53:27.023195
1942 13:53:27.025735
1943 13:53:27.025834 TX Vref Scan disable
1944 13:53:27.029129 == TX Byte 0 ==
1945 13:53:27.032454 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1946 13:53:27.035803 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1947 13:53:27.039602 == TX Byte 1 ==
1948 13:53:27.042947 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1949 13:53:27.045834 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1950 13:53:27.045931
1951 13:53:27.049569 [DATLAT]
1952 13:53:27.049664 Freq=800, CH1 RK1
1953 13:53:27.049748
1954 13:53:27.053074 DATLAT Default: 0xa
1955 13:53:27.053156 0, 0xFFFF, sum = 0
1956 13:53:27.055920 1, 0xFFFF, sum = 0
1957 13:53:27.056033 2, 0xFFFF, sum = 0
1958 13:53:27.059407 3, 0xFFFF, sum = 0
1959 13:53:27.059496 4, 0xFFFF, sum = 0
1960 13:53:27.062689 5, 0xFFFF, sum = 0
1961 13:53:27.062787 6, 0xFFFF, sum = 0
1962 13:53:27.065823 7, 0xFFFF, sum = 0
1963 13:53:27.065940 8, 0xFFFF, sum = 0
1964 13:53:27.069234 9, 0x0, sum = 1
1965 13:53:27.069350 10, 0x0, sum = 2
1966 13:53:27.073147 11, 0x0, sum = 3
1967 13:53:27.073255 12, 0x0, sum = 4
1968 13:53:27.076647 best_step = 10
1969 13:53:27.076736
1970 13:53:27.076803 ==
1971 13:53:27.079490 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 13:53:27.083258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 13:53:27.083372 ==
1974 13:53:27.086083 RX Vref Scan: 0
1975 13:53:27.086184
1976 13:53:27.086276 RX Vref 0 -> 0, step: 1
1977 13:53:27.086366
1978 13:53:27.089669 RX Delay -79 -> 252, step: 8
1979 13:53:27.096143 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1980 13:53:27.099794 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1981 13:53:27.102720 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1982 13:53:27.106332 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1983 13:53:27.109636 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1984 13:53:27.112982 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
1985 13:53:27.120098 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1986 13:53:27.122911 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1987 13:53:27.126709 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1988 13:53:27.129543 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1989 13:53:27.133041 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
1990 13:53:27.136527 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
1991 13:53:27.142984 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1992 13:53:27.146328 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
1993 13:53:27.149850 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
1994 13:53:27.152710 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
1995 13:53:27.152826 ==
1996 13:53:27.156171 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 13:53:27.163247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 13:53:27.163398 ==
1999 13:53:27.163497 DQS Delay:
2000 13:53:27.163588 DQS0 = 0, DQS1 = 0
2001 13:53:27.166243 DQM Delay:
2002 13:53:27.166346 DQM0 = 97, DQM1 = 91
2003 13:53:27.169563 DQ Delay:
2004 13:53:27.172948 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2005 13:53:27.176406 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2006 13:53:27.179723 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2007 13:53:27.183147 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2008 13:53:27.183272
2009 13:53:27.183367
2010 13:53:27.189493 [DQSOSCAuto] RK1, (LSB)MR18= 0x460f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2011 13:53:27.193119 CH1 RK1: MR19=606, MR18=460F
2012 13:53:27.199411 CH1_RK1: MR19=0x606, MR18=0x460F, DQSOSC=392, MR23=63, INC=96, DEC=64
2013 13:53:27.203175 [RxdqsGatingPostProcess] freq 800
2014 13:53:27.206207 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2015 13:53:27.210035 Pre-setting of DQS Precalculation
2016 13:53:27.216364 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2017 13:53:27.223219 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2018 13:53:27.229749 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2019 13:53:27.229901
2020 13:53:27.230007
2021 13:53:27.233241 [Calibration Summary] 1600 Mbps
2022 13:53:27.233348 CH 0, Rank 0
2023 13:53:27.236714 SW Impedance : PASS
2024 13:53:27.240023 DUTY Scan : NO K
2025 13:53:27.240141 ZQ Calibration : PASS
2026 13:53:27.242964 Jitter Meter : NO K
2027 13:53:27.246497 CBT Training : PASS
2028 13:53:27.246628 Write leveling : PASS
2029 13:53:27.249590 RX DQS gating : PASS
2030 13:53:27.253137 RX DQ/DQS(RDDQC) : PASS
2031 13:53:27.253245 TX DQ/DQS : PASS
2032 13:53:27.256082 RX DATLAT : PASS
2033 13:53:27.256191 RX DQ/DQS(Engine): PASS
2034 13:53:27.259618 TX OE : NO K
2035 13:53:27.259701 All Pass.
2036 13:53:27.259765
2037 13:53:27.263143 CH 0, Rank 1
2038 13:53:27.263256 SW Impedance : PASS
2039 13:53:27.266690 DUTY Scan : NO K
2040 13:53:27.269543 ZQ Calibration : PASS
2041 13:53:27.269658 Jitter Meter : NO K
2042 13:53:27.273173 CBT Training : PASS
2043 13:53:27.276766 Write leveling : PASS
2044 13:53:27.276887 RX DQS gating : PASS
2045 13:53:27.279463 RX DQ/DQS(RDDQC) : PASS
2046 13:53:27.282926 TX DQ/DQS : PASS
2047 13:53:27.283044 RX DATLAT : PASS
2048 13:53:27.286464 RX DQ/DQS(Engine): PASS
2049 13:53:27.289994 TX OE : NO K
2050 13:53:27.290111 All Pass.
2051 13:53:27.290204
2052 13:53:27.290299 CH 1, Rank 0
2053 13:53:27.293422 SW Impedance : PASS
2054 13:53:27.296479 DUTY Scan : NO K
2055 13:53:27.296562 ZQ Calibration : PASS
2056 13:53:27.300201 Jitter Meter : NO K
2057 13:53:27.300279 CBT Training : PASS
2058 13:53:27.303045 Write leveling : PASS
2059 13:53:27.306608 RX DQS gating : PASS
2060 13:53:27.306696 RX DQ/DQS(RDDQC) : PASS
2061 13:53:27.310213 TX DQ/DQS : PASS
2062 13:53:27.313673 RX DATLAT : PASS
2063 13:53:27.313764 RX DQ/DQS(Engine): PASS
2064 13:53:27.316975 TX OE : NO K
2065 13:53:27.317088 All Pass.
2066 13:53:27.317181
2067 13:53:27.320305 CH 1, Rank 1
2068 13:53:27.320430 SW Impedance : PASS
2069 13:53:27.323336 DUTY Scan : NO K
2070 13:53:27.326407 ZQ Calibration : PASS
2071 13:53:27.326496 Jitter Meter : NO K
2072 13:53:27.329837 CBT Training : PASS
2073 13:53:27.333148 Write leveling : PASS
2074 13:53:27.333245 RX DQS gating : PASS
2075 13:53:27.336901 RX DQ/DQS(RDDQC) : PASS
2076 13:53:27.337015 TX DQ/DQS : PASS
2077 13:53:27.340087 RX DATLAT : PASS
2078 13:53:27.343591 RX DQ/DQS(Engine): PASS
2079 13:53:27.343706 TX OE : NO K
2080 13:53:27.346937 All Pass.
2081 13:53:27.347046
2082 13:53:27.347148 DramC Write-DBI off
2083 13:53:27.350311 PER_BANK_REFRESH: Hybrid Mode
2084 13:53:27.353420 TX_TRACKING: ON
2085 13:53:27.356665 [GetDramInforAfterCalByMRR] Vendor 6.
2086 13:53:27.360172 [GetDramInforAfterCalByMRR] Revision 606.
2087 13:53:27.363832 [GetDramInforAfterCalByMRR] Revision 2 0.
2088 13:53:27.363949 MR0 0x3b3b
2089 13:53:27.364050 MR8 0x5151
2090 13:53:27.366624 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2091 13:53:27.370260
2092 13:53:27.370379 MR0 0x3b3b
2093 13:53:27.370479 MR8 0x5151
2094 13:53:27.373600 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2095 13:53:27.373714
2096 13:53:27.383581 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2097 13:53:27.387073 [FAST_K] Save calibration result to emmc
2098 13:53:27.389911 [FAST_K] Save calibration result to emmc
2099 13:53:27.393410 dram_init: config_dvfs: 1
2100 13:53:27.397065 dramc_set_vcore_voltage set vcore to 662500
2101 13:53:27.400501 Read voltage for 1200, 2
2102 13:53:27.400594 Vio18 = 0
2103 13:53:27.400659 Vcore = 662500
2104 13:53:27.403455 Vdram = 0
2105 13:53:27.403538 Vddq = 0
2106 13:53:27.403603 Vmddr = 0
2107 13:53:27.410451 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2108 13:53:27.413332 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2109 13:53:27.416761 MEM_TYPE=3, freq_sel=15
2110 13:53:27.420149 sv_algorithm_assistance_LP4_1600
2111 13:53:27.423754 ============ PULL DRAM RESETB DOWN ============
2112 13:53:27.426689 ========== PULL DRAM RESETB DOWN end =========
2113 13:53:27.433894 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2114 13:53:27.436749 ===================================
2115 13:53:27.436846 LPDDR4 DRAM CONFIGURATION
2116 13:53:27.440546 ===================================
2117 13:53:27.443395 EX_ROW_EN[0] = 0x0
2118 13:53:27.446808 EX_ROW_EN[1] = 0x0
2119 13:53:27.446984 LP4Y_EN = 0x0
2120 13:53:27.449975 WORK_FSP = 0x0
2121 13:53:27.450064 WL = 0x4
2122 13:53:27.453510 RL = 0x4
2123 13:53:27.453606 BL = 0x2
2124 13:53:27.457140 RPST = 0x0
2125 13:53:27.457228 RD_PRE = 0x0
2126 13:53:27.460263 WR_PRE = 0x1
2127 13:53:27.460397 WR_PST = 0x0
2128 13:53:27.463545 DBI_WR = 0x0
2129 13:53:27.463634 DBI_RD = 0x0
2130 13:53:27.466616 OTF = 0x1
2131 13:53:27.470373 ===================================
2132 13:53:27.473766 ===================================
2133 13:53:27.473856 ANA top config
2134 13:53:27.476556 ===================================
2135 13:53:27.480159 DLL_ASYNC_EN = 0
2136 13:53:27.483193 ALL_SLAVE_EN = 0
2137 13:53:27.483348 NEW_RANK_MODE = 1
2138 13:53:27.487063 DLL_IDLE_MODE = 1
2139 13:53:27.490125 LP45_APHY_COMB_EN = 1
2140 13:53:27.493745 TX_ODT_DIS = 1
2141 13:53:27.497125 NEW_8X_MODE = 1
2142 13:53:27.500285 ===================================
2143 13:53:27.503526 ===================================
2144 13:53:27.503626 data_rate = 2400
2145 13:53:27.507038 CKR = 1
2146 13:53:27.510263 DQ_P2S_RATIO = 8
2147 13:53:27.513882 ===================================
2148 13:53:27.516647 CA_P2S_RATIO = 8
2149 13:53:27.520197 DQ_CA_OPEN = 0
2150 13:53:27.523245 DQ_SEMI_OPEN = 0
2151 13:53:27.523368 CA_SEMI_OPEN = 0
2152 13:53:27.526869 CA_FULL_RATE = 0
2153 13:53:27.530338 DQ_CKDIV4_EN = 0
2154 13:53:27.533882 CA_CKDIV4_EN = 0
2155 13:53:27.536796 CA_PREDIV_EN = 0
2156 13:53:27.540092 PH8_DLY = 17
2157 13:53:27.540207 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2158 13:53:27.543661 DQ_AAMCK_DIV = 4
2159 13:53:27.547206 CA_AAMCK_DIV = 4
2160 13:53:27.550014 CA_ADMCK_DIV = 4
2161 13:53:27.553470 DQ_TRACK_CA_EN = 0
2162 13:53:27.557028 CA_PICK = 1200
2163 13:53:27.557163 CA_MCKIO = 1200
2164 13:53:27.560630 MCKIO_SEMI = 0
2165 13:53:27.563713 PLL_FREQ = 2366
2166 13:53:27.567014 DQ_UI_PI_RATIO = 32
2167 13:53:27.570618 CA_UI_PI_RATIO = 0
2168 13:53:27.573436 ===================================
2169 13:53:27.576952 ===================================
2170 13:53:27.580387 memory_type:LPDDR4
2171 13:53:27.580523 GP_NUM : 10
2172 13:53:27.583908 SRAM_EN : 1
2173 13:53:27.584043 MD32_EN : 0
2174 13:53:27.586636 ===================================
2175 13:53:27.590024 [ANA_INIT] >>>>>>>>>>>>>>
2176 13:53:27.593289 <<<<<< [CONFIGURE PHASE]: ANA_TX
2177 13:53:27.596835 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2178 13:53:27.600073 ===================================
2179 13:53:27.603846 data_rate = 2400,PCW = 0X5b00
2180 13:53:27.606938 ===================================
2181 13:53:27.610258 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2182 13:53:27.613652 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2183 13:53:27.620224 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2184 13:53:27.623365 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2185 13:53:27.629971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2186 13:53:27.633545 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2187 13:53:27.633650 [ANA_INIT] flow start
2188 13:53:27.637146 [ANA_INIT] PLL >>>>>>>>
2189 13:53:27.640498 [ANA_INIT] PLL <<<<<<<<
2190 13:53:27.640593 [ANA_INIT] MIDPI >>>>>>>>
2191 13:53:27.643496 [ANA_INIT] MIDPI <<<<<<<<
2192 13:53:27.646994 [ANA_INIT] DLL >>>>>>>>
2193 13:53:27.647090 [ANA_INIT] DLL <<<<<<<<
2194 13:53:27.650607 [ANA_INIT] flow end
2195 13:53:27.653473 ============ LP4 DIFF to SE enter ============
2196 13:53:27.656995 ============ LP4 DIFF to SE exit ============
2197 13:53:27.660618 [ANA_INIT] <<<<<<<<<<<<<
2198 13:53:27.663404 [Flow] Enable top DCM control >>>>>
2199 13:53:27.666941 [Flow] Enable top DCM control <<<<<
2200 13:53:27.670274 Enable DLL master slave shuffle
2201 13:53:27.677058 ==============================================================
2202 13:53:27.677178 Gating Mode config
2203 13:53:27.683543 ==============================================================
2204 13:53:27.683656 Config description:
2205 13:53:27.693446 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2206 13:53:27.700359 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2207 13:53:27.706615 SELPH_MODE 0: By rank 1: By Phase
2208 13:53:27.710204 ==============================================================
2209 13:53:27.713845 GAT_TRACK_EN = 1
2210 13:53:27.716706 RX_GATING_MODE = 2
2211 13:53:27.720177 RX_GATING_TRACK_MODE = 2
2212 13:53:27.723695 SELPH_MODE = 1
2213 13:53:27.727222 PICG_EARLY_EN = 1
2214 13:53:27.730007 VALID_LAT_VALUE = 1
2215 13:53:27.733531 ==============================================================
2216 13:53:27.737301 Enter into Gating configuration >>>>
2217 13:53:27.740115 Exit from Gating configuration <<<<
2218 13:53:27.743243 Enter into DVFS_PRE_config >>>>>
2219 13:53:27.757005 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2220 13:53:27.760109 Exit from DVFS_PRE_config <<<<<
2221 13:53:27.763463 Enter into PICG configuration >>>>
2222 13:53:27.763590 Exit from PICG configuration <<<<
2223 13:53:27.766509 [RX_INPUT] configuration >>>>>
2224 13:53:27.769938 [RX_INPUT] configuration <<<<<
2225 13:53:27.776658 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2226 13:53:27.780131 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2227 13:53:27.786585 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2228 13:53:27.793749 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2229 13:53:27.800174 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2230 13:53:27.806997 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2231 13:53:27.809804 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2232 13:53:27.813410 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2233 13:53:27.816933 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2234 13:53:27.824119 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2235 13:53:27.826854 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2236 13:53:27.830266 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2237 13:53:27.833839 ===================================
2238 13:53:27.837487 LPDDR4 DRAM CONFIGURATION
2239 13:53:27.840370 ===================================
2240 13:53:27.840465 EX_ROW_EN[0] = 0x0
2241 13:53:27.844108 EX_ROW_EN[1] = 0x0
2242 13:53:27.847145 LP4Y_EN = 0x0
2243 13:53:27.847296 WORK_FSP = 0x0
2244 13:53:27.850662 WL = 0x4
2245 13:53:27.850782 RL = 0x4
2246 13:53:27.853601 BL = 0x2
2247 13:53:27.853693 RPST = 0x0
2248 13:53:27.856972 RD_PRE = 0x0
2249 13:53:27.857058 WR_PRE = 0x1
2250 13:53:27.860246 WR_PST = 0x0
2251 13:53:27.860365 DBI_WR = 0x0
2252 13:53:27.863718 DBI_RD = 0x0
2253 13:53:27.863841 OTF = 0x1
2254 13:53:27.867047 ===================================
2255 13:53:27.870285 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2256 13:53:27.876989 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2257 13:53:27.880542 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2258 13:53:27.883952 ===================================
2259 13:53:27.887242 LPDDR4 DRAM CONFIGURATION
2260 13:53:27.890629 ===================================
2261 13:53:27.890780 EX_ROW_EN[0] = 0x10
2262 13:53:27.894153 EX_ROW_EN[1] = 0x0
2263 13:53:27.894252 LP4Y_EN = 0x0
2264 13:53:27.897012 WORK_FSP = 0x0
2265 13:53:27.897123 WL = 0x4
2266 13:53:27.900867 RL = 0x4
2267 13:53:27.900976 BL = 0x2
2268 13:53:27.903791 RPST = 0x0
2269 13:53:27.903913 RD_PRE = 0x0
2270 13:53:27.907311 WR_PRE = 0x1
2271 13:53:27.907450 WR_PST = 0x0
2272 13:53:27.910488 DBI_WR = 0x0
2273 13:53:27.913657 DBI_RD = 0x0
2274 13:53:27.913799 OTF = 0x1
2275 13:53:27.917153 ===================================
2276 13:53:27.924135 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2277 13:53:27.924288 ==
2278 13:53:27.926986 Dram Type= 6, Freq= 0, CH_0, rank 0
2279 13:53:27.930487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2280 13:53:27.930579 ==
2281 13:53:27.933981 [Duty_Offset_Calibration]
2282 13:53:27.934071 B0:2 B1:1 CA:1
2283 13:53:27.934136
2284 13:53:27.937510 [DutyScan_Calibration_Flow] k_type=0
2285 13:53:27.948353
2286 13:53:27.948475 ==CLK 0==
2287 13:53:27.951350 Final CLK duty delay cell = 0
2288 13:53:27.954971 [0] MAX Duty = 5218%(X100), DQS PI = 24
2289 13:53:27.957913 [0] MIN Duty = 4844%(X100), DQS PI = 48
2290 13:53:27.958002 [0] AVG Duty = 5031%(X100)
2291 13:53:27.961292
2292 13:53:27.964865 CH0 CLK Duty spec in!! Max-Min= 374%
2293 13:53:27.968169 [DutyScan_Calibration_Flow] ====Done====
2294 13:53:27.968301
2295 13:53:27.971560 [DutyScan_Calibration_Flow] k_type=1
2296 13:53:27.986532
2297 13:53:27.986674 ==DQS 0 ==
2298 13:53:27.990003 Final DQS duty delay cell = -4
2299 13:53:27.993278 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2300 13:53:27.996761 [-4] MIN Duty = 4751%(X100), DQS PI = 62
2301 13:53:28.000194 [-4] AVG Duty = 4937%(X100)
2302 13:53:28.000279
2303 13:53:28.000376 ==DQS 1 ==
2304 13:53:28.003050 Final DQS duty delay cell = 0
2305 13:53:28.006614 [0] MAX Duty = 5156%(X100), DQS PI = 0
2306 13:53:28.010349 [0] MIN Duty = 5000%(X100), DQS PI = 34
2307 13:53:28.013222 [0] AVG Duty = 5078%(X100)
2308 13:53:28.013316
2309 13:53:28.017047 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2310 13:53:28.017136
2311 13:53:28.019918 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2312 13:53:28.023326 [DutyScan_Calibration_Flow] ====Done====
2313 13:53:28.023417
2314 13:53:28.026561 [DutyScan_Calibration_Flow] k_type=3
2315 13:53:28.043829
2316 13:53:28.043993 ==DQM 0 ==
2317 13:53:28.046635 Final DQM duty delay cell = 0
2318 13:53:28.050250 [0] MAX Duty = 5156%(X100), DQS PI = 30
2319 13:53:28.053505 [0] MIN Duty = 4875%(X100), DQS PI = 58
2320 13:53:28.053629 [0] AVG Duty = 5015%(X100)
2321 13:53:28.057179
2322 13:53:28.057261 ==DQM 1 ==
2323 13:53:28.060034 Final DQM duty delay cell = 0
2324 13:53:28.063728 [0] MAX Duty = 5093%(X100), DQS PI = 0
2325 13:53:28.066646 [0] MIN Duty = 5031%(X100), DQS PI = 14
2326 13:53:28.066737 [0] AVG Duty = 5062%(X100)
2327 13:53:28.070328
2328 13:53:28.073894 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2329 13:53:28.073994
2330 13:53:28.077373 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2331 13:53:28.080133 [DutyScan_Calibration_Flow] ====Done====
2332 13:53:28.080217
2333 13:53:28.083520 [DutyScan_Calibration_Flow] k_type=2
2334 13:53:28.099816
2335 13:53:28.099957 ==DQ 0 ==
2336 13:53:28.103455 Final DQ duty delay cell = 0
2337 13:53:28.106799 [0] MAX Duty = 5031%(X100), DQS PI = 26
2338 13:53:28.110293 [0] MIN Duty = 4875%(X100), DQS PI = 0
2339 13:53:28.110428 [0] AVG Duty = 4953%(X100)
2340 13:53:28.110522
2341 13:53:28.113250 ==DQ 1 ==
2342 13:53:28.116863 Final DQ duty delay cell = 0
2343 13:53:28.119710 [0] MAX Duty = 5093%(X100), DQS PI = 26
2344 13:53:28.123662 [0] MIN Duty = 4907%(X100), DQS PI = 36
2345 13:53:28.123820 [0] AVG Duty = 5000%(X100)
2346 13:53:28.123922
2347 13:53:28.126445 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2348 13:53:28.126548
2349 13:53:28.129889 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2350 13:53:28.136503 [DutyScan_Calibration_Flow] ====Done====
2351 13:53:28.136658 ==
2352 13:53:28.139957 Dram Type= 6, Freq= 0, CH_1, rank 0
2353 13:53:28.143360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2354 13:53:28.143482 ==
2355 13:53:28.146569 [Duty_Offset_Calibration]
2356 13:53:28.146680 B0:1 B1:0 CA:0
2357 13:53:28.146780
2358 13:53:28.149982 [DutyScan_Calibration_Flow] k_type=0
2359 13:53:28.159144
2360 13:53:28.159278 ==CLK 0==
2361 13:53:28.162213 Final CLK duty delay cell = -4
2362 13:53:28.165967 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2363 13:53:28.168941 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2364 13:53:28.172249 [-4] AVG Duty = 4953%(X100)
2365 13:53:28.172391
2366 13:53:28.175776 CH1 CLK Duty spec in!! Max-Min= 93%
2367 13:53:28.179125 [DutyScan_Calibration_Flow] ====Done====
2368 13:53:28.179221
2369 13:53:28.181968 [DutyScan_Calibration_Flow] k_type=1
2370 13:53:28.199169
2371 13:53:28.199316 ==DQS 0 ==
2372 13:53:28.201872 Final DQS duty delay cell = 0
2373 13:53:28.205398 [0] MAX Duty = 5062%(X100), DQS PI = 24
2374 13:53:28.208877 [0] MIN Duty = 4844%(X100), DQS PI = 0
2375 13:53:28.208973 [0] AVG Duty = 4953%(X100)
2376 13:53:28.212070
2377 13:53:28.212164 ==DQS 1 ==
2378 13:53:28.215465 Final DQS duty delay cell = 0
2379 13:53:28.218694 [0] MAX Duty = 5187%(X100), DQS PI = 18
2380 13:53:28.222202 [0] MIN Duty = 4969%(X100), DQS PI = 8
2381 13:53:28.222338 [0] AVG Duty = 5078%(X100)
2382 13:53:28.222442
2383 13:53:28.225893 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2384 13:53:28.228560
2385 13:53:28.232015 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2386 13:53:28.235567 [DutyScan_Calibration_Flow] ====Done====
2387 13:53:28.235656
2388 13:53:28.239051 [DutyScan_Calibration_Flow] k_type=3
2389 13:53:28.255150
2390 13:53:28.255318 ==DQM 0 ==
2391 13:53:28.258542 Final DQM duty delay cell = 0
2392 13:53:28.262295 [0] MAX Duty = 5156%(X100), DQS PI = 6
2393 13:53:28.265198 [0] MIN Duty = 5000%(X100), DQS PI = 0
2394 13:53:28.265317 [0] AVG Duty = 5078%(X100)
2395 13:53:28.268701
2396 13:53:28.268820 ==DQM 1 ==
2397 13:53:28.272050 Final DQM duty delay cell = 0
2398 13:53:28.275387 [0] MAX Duty = 5031%(X100), DQS PI = 26
2399 13:53:28.278590 [0] MIN Duty = 4875%(X100), DQS PI = 52
2400 13:53:28.278711 [0] AVG Duty = 4953%(X100)
2401 13:53:28.278803
2402 13:53:28.285543 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2403 13:53:28.285656
2404 13:53:28.288800 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2405 13:53:28.291970 [DutyScan_Calibration_Flow] ====Done====
2406 13:53:28.292075
2407 13:53:28.295117 [DutyScan_Calibration_Flow] k_type=2
2408 13:53:28.311031
2409 13:53:28.311202 ==DQ 0 ==
2410 13:53:28.314566 Final DQ duty delay cell = -4
2411 13:53:28.317456 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2412 13:53:28.321006 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2413 13:53:28.321099 [-4] AVG Duty = 4984%(X100)
2414 13:53:28.324395
2415 13:53:28.324490 ==DQ 1 ==
2416 13:53:28.327792 Final DQ duty delay cell = 0
2417 13:53:28.331162 [0] MAX Duty = 5125%(X100), DQS PI = 18
2418 13:53:28.334339 [0] MIN Duty = 4969%(X100), DQS PI = 12
2419 13:53:28.334449 [0] AVG Duty = 5047%(X100)
2420 13:53:28.334550
2421 13:53:28.337778 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2422 13:53:28.341203
2423 13:53:28.344490 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2424 13:53:28.347530 [DutyScan_Calibration_Flow] ====Done====
2425 13:53:28.350800 nWR fixed to 30
2426 13:53:28.350913 [ModeRegInit_LP4] CH0 RK0
2427 13:53:28.354423 [ModeRegInit_LP4] CH0 RK1
2428 13:53:28.358054 [ModeRegInit_LP4] CH1 RK0
2429 13:53:28.360948 [ModeRegInit_LP4] CH1 RK1
2430 13:53:28.361031 match AC timing 7
2431 13:53:28.364530 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2432 13:53:28.370810 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2433 13:53:28.374155 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2434 13:53:28.377570 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2435 13:53:28.384684 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2436 13:53:28.384836 ==
2437 13:53:28.387932 Dram Type= 6, Freq= 0, CH_0, rank 0
2438 13:53:28.390772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2439 13:53:28.390888 ==
2440 13:53:28.397447 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2441 13:53:28.400906 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2442 13:53:28.411309 [CA 0] Center 39 (8~70) winsize 63
2443 13:53:28.414306 [CA 1] Center 39 (8~70) winsize 63
2444 13:53:28.417948 [CA 2] Center 35 (5~66) winsize 62
2445 13:53:28.420812 [CA 3] Center 34 (4~65) winsize 62
2446 13:53:28.424410 [CA 4] Center 33 (3~64) winsize 62
2447 13:53:28.427708 [CA 5] Center 32 (3~62) winsize 60
2448 13:53:28.427803
2449 13:53:28.431276 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2450 13:53:28.431393
2451 13:53:28.434815 [CATrainingPosCal] consider 1 rank data
2452 13:53:28.437655 u2DelayCellTimex100 = 270/100 ps
2453 13:53:28.441051 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2454 13:53:28.444229 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2455 13:53:28.451239 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2456 13:53:28.454358 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2457 13:53:28.457737 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2458 13:53:28.461237 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2459 13:53:28.461337
2460 13:53:28.464852 CA PerBit enable=1, Macro0, CA PI delay=32
2461 13:53:28.464965
2462 13:53:28.467668 [CBTSetCACLKResult] CA Dly = 32
2463 13:53:28.467749 CS Dly: 6 (0~37)
2464 13:53:28.467814 ==
2465 13:53:28.471284 Dram Type= 6, Freq= 0, CH_0, rank 1
2466 13:53:28.478287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2467 13:53:28.478426 ==
2468 13:53:28.481113 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2469 13:53:28.487758 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2470 13:53:28.497326 [CA 0] Center 38 (8~69) winsize 62
2471 13:53:28.499912 [CA 1] Center 38 (8~69) winsize 62
2472 13:53:28.503303 [CA 2] Center 35 (5~66) winsize 62
2473 13:53:28.507057 [CA 3] Center 34 (4~65) winsize 62
2474 13:53:28.510667 [CA 4] Center 33 (3~63) winsize 61
2475 13:53:28.513577 [CA 5] Center 32 (3~62) winsize 60
2476 13:53:28.513676
2477 13:53:28.516958 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2478 13:53:28.517049
2479 13:53:28.520316 [CATrainingPosCal] consider 2 rank data
2480 13:53:28.523577 u2DelayCellTimex100 = 270/100 ps
2481 13:53:28.526657 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2482 13:53:28.530268 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2483 13:53:28.536855 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2484 13:53:28.540406 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2485 13:53:28.543940 CA4 delay=33 (3~63),Diff = 1 PI (4 cell)
2486 13:53:28.547249 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2487 13:53:28.547347
2488 13:53:28.550580 CA PerBit enable=1, Macro0, CA PI delay=32
2489 13:53:28.550667
2490 13:53:28.553568 [CBTSetCACLKResult] CA Dly = 32
2491 13:53:28.553689 CS Dly: 6 (0~38)
2492 13:53:28.553759
2493 13:53:28.557110 ----->DramcWriteLeveling(PI) begin...
2494 13:53:28.557202 ==
2495 13:53:28.560656 Dram Type= 6, Freq= 0, CH_0, rank 0
2496 13:53:28.567161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2497 13:53:28.567297 ==
2498 13:53:28.570697 Write leveling (Byte 0): 33 => 33
2499 13:53:28.573598 Write leveling (Byte 1): 29 => 29
2500 13:53:28.573692 DramcWriteLeveling(PI) end<-----
2501 13:53:28.577266
2502 13:53:28.577395 ==
2503 13:53:28.580749 Dram Type= 6, Freq= 0, CH_0, rank 0
2504 13:53:28.583544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2505 13:53:28.583673 ==
2506 13:53:28.586843 [Gating] SW mode calibration
2507 13:53:28.593392 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2508 13:53:28.596784 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2509 13:53:28.603870 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2510 13:53:28.607201 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2511 13:53:28.610071 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2512 13:53:28.617045 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2513 13:53:28.619978 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2514 13:53:28.623424 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 13:53:28.630542 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
2516 13:53:28.633466 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2517 13:53:28.636812 1 0 0 | B1->B0 | 2626 2323 | 1 0 | (1 0) (1 0)
2518 13:53:28.643602 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2519 13:53:28.647128 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2520 13:53:28.650275 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2521 13:53:28.657032 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 13:53:28.660591 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 13:53:28.663462 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
2524 13:53:28.667368 1 0 28 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2525 13:53:28.673610 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2526 13:53:28.677238 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2527 13:53:28.680361 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2528 13:53:28.686936 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2529 13:53:28.690379 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 13:53:28.693913 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 13:53:28.700224 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 13:53:28.703695 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2533 13:53:28.707184 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2534 13:53:28.713960 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2535 13:53:28.717411 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2536 13:53:28.720259 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2537 13:53:28.727542 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 13:53:28.730474 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 13:53:28.734204 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 13:53:28.740689 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 13:53:28.743588 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 13:53:28.747375 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 13:53:28.753692 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 13:53:28.756998 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 13:53:28.760644 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 13:53:28.764263 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 13:53:28.770533 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 13:53:28.773964 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2549 13:53:28.777091 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2550 13:53:28.780345 Total UI for P1: 0, mck2ui 16
2551 13:53:28.783659 best dqsien dly found for B0: ( 1, 3, 28)
2552 13:53:28.790614 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 13:53:28.790800 Total UI for P1: 0, mck2ui 16
2554 13:53:28.797128 best dqsien dly found for B1: ( 1, 4, 0)
2555 13:53:28.800530 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2556 13:53:28.804300 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2557 13:53:28.804433
2558 13:53:28.807385 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2559 13:53:28.811159 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2560 13:53:28.813915 [Gating] SW calibration Done
2561 13:53:28.814015 ==
2562 13:53:28.817176 Dram Type= 6, Freq= 0, CH_0, rank 0
2563 13:53:28.820458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2564 13:53:28.820553 ==
2565 13:53:28.823978 RX Vref Scan: 0
2566 13:53:28.824108
2567 13:53:28.824208 RX Vref 0 -> 0, step: 1
2568 13:53:28.824307
2569 13:53:28.827487 RX Delay -40 -> 252, step: 8
2570 13:53:28.830942 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2571 13:53:28.837595 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2572 13:53:28.840441 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2573 13:53:28.844151 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2574 13:53:28.847048 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2575 13:53:28.850628 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2576 13:53:28.856928 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2577 13:53:28.860465 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2578 13:53:28.864071 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2579 13:53:28.867300 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2580 13:53:28.870813 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2581 13:53:28.874406 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2582 13:53:28.880806 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2583 13:53:28.884268 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2584 13:53:28.887102 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2585 13:53:28.890553 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2586 13:53:28.890700 ==
2587 13:53:28.894021 Dram Type= 6, Freq= 0, CH_0, rank 0
2588 13:53:28.901075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2589 13:53:28.901245 ==
2590 13:53:28.901347 DQS Delay:
2591 13:53:28.904475 DQS0 = 0, DQS1 = 0
2592 13:53:28.904585 DQM Delay:
2593 13:53:28.904690 DQM0 = 121, DQM1 = 113
2594 13:53:28.907736 DQ Delay:
2595 13:53:28.911027 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2596 13:53:28.914181 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2597 13:53:28.917712 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2598 13:53:28.921308 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2599 13:53:28.921411
2600 13:53:28.921478
2601 13:53:28.921538 ==
2602 13:53:28.924215 Dram Type= 6, Freq= 0, CH_0, rank 0
2603 13:53:28.927576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2604 13:53:28.927674 ==
2605 13:53:28.927741
2606 13:53:28.930909
2607 13:53:28.930986 TX Vref Scan disable
2608 13:53:28.934103 == TX Byte 0 ==
2609 13:53:28.937855 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2610 13:53:28.940848 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2611 13:53:28.944151 == TX Byte 1 ==
2612 13:53:28.947637 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2613 13:53:28.950979 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2614 13:53:28.951104 ==
2615 13:53:28.954473 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 13:53:28.960900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 13:53:28.961013 ==
2618 13:53:28.971591 TX Vref=22, minBit 10, minWin=24, winSum=405
2619 13:53:28.974967 TX Vref=24, minBit 0, minWin=25, winSum=415
2620 13:53:28.978452 TX Vref=26, minBit 7, minWin=25, winSum=420
2621 13:53:28.981359 TX Vref=28, minBit 0, minWin=26, winSum=422
2622 13:53:28.984742 TX Vref=30, minBit 0, minWin=26, winSum=425
2623 13:53:28.991805 TX Vref=32, minBit 1, minWin=26, winSum=424
2624 13:53:28.995277 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 30
2625 13:53:28.995427
2626 13:53:28.998142 Final TX Range 1 Vref 30
2627 13:53:28.998264
2628 13:53:28.998364 ==
2629 13:53:29.001778 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 13:53:29.005214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 13:53:29.005306 ==
2632 13:53:29.005370
2633 13:53:29.007994
2634 13:53:29.008112 TX Vref Scan disable
2635 13:53:29.011480 == TX Byte 0 ==
2636 13:53:29.014930 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2637 13:53:29.018427 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2638 13:53:29.021642 == TX Byte 1 ==
2639 13:53:29.024972 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2640 13:53:29.028191 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2641 13:53:29.028291
2642 13:53:29.032084 [DATLAT]
2643 13:53:29.032184 Freq=1200, CH0 RK0
2644 13:53:29.032251
2645 13:53:29.035338 DATLAT Default: 0xd
2646 13:53:29.035443 0, 0xFFFF, sum = 0
2647 13:53:29.038274 1, 0xFFFF, sum = 0
2648 13:53:29.038355 2, 0xFFFF, sum = 0
2649 13:53:29.041769 3, 0xFFFF, sum = 0
2650 13:53:29.041861 4, 0xFFFF, sum = 0
2651 13:53:29.045260 5, 0xFFFF, sum = 0
2652 13:53:29.045355 6, 0xFFFF, sum = 0
2653 13:53:29.048061 7, 0xFFFF, sum = 0
2654 13:53:29.048151 8, 0xFFFF, sum = 0
2655 13:53:29.052091 9, 0xFFFF, sum = 0
2656 13:53:29.055305 10, 0xFFFF, sum = 0
2657 13:53:29.055431 11, 0xFFFF, sum = 0
2658 13:53:29.058280 12, 0x0, sum = 1
2659 13:53:29.058383 13, 0x0, sum = 2
2660 13:53:29.058451 14, 0x0, sum = 3
2661 13:53:29.061780 15, 0x0, sum = 4
2662 13:53:29.061872 best_step = 13
2663 13:53:29.061938
2664 13:53:29.061999 ==
2665 13:53:29.064946 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 13:53:29.071736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 13:53:29.071851 ==
2668 13:53:29.071948 RX Vref Scan: 1
2669 13:53:29.072028
2670 13:53:29.075272 Set Vref Range= 32 -> 127
2671 13:53:29.075364
2672 13:53:29.078748 RX Vref 32 -> 127, step: 1
2673 13:53:29.078852
2674 13:53:29.081593 RX Delay -13 -> 252, step: 4
2675 13:53:29.081683
2676 13:53:29.084843 Set Vref, RX VrefLevel [Byte0]: 32
2677 13:53:29.088092 [Byte1]: 32
2678 13:53:29.088219
2679 13:53:29.091621 Set Vref, RX VrefLevel [Byte0]: 33
2680 13:53:29.095006 [Byte1]: 33
2681 13:53:29.095137
2682 13:53:29.098563 Set Vref, RX VrefLevel [Byte0]: 34
2683 13:53:29.101337 [Byte1]: 34
2684 13:53:29.105596
2685 13:53:29.105726 Set Vref, RX VrefLevel [Byte0]: 35
2686 13:53:29.109099 [Byte1]: 35
2687 13:53:29.113993
2688 13:53:29.114133 Set Vref, RX VrefLevel [Byte0]: 36
2689 13:53:29.116975 [Byte1]: 36
2690 13:53:29.121733
2691 13:53:29.121859 Set Vref, RX VrefLevel [Byte0]: 37
2692 13:53:29.124653 [Byte1]: 37
2693 13:53:29.129725
2694 13:53:29.129853 Set Vref, RX VrefLevel [Byte0]: 38
2695 13:53:29.132550 [Byte1]: 38
2696 13:53:29.137195
2697 13:53:29.137293 Set Vref, RX VrefLevel [Byte0]: 39
2698 13:53:29.140402 [Byte1]: 39
2699 13:53:29.145187
2700 13:53:29.145287 Set Vref, RX VrefLevel [Byte0]: 40
2701 13:53:29.148475 [Byte1]: 40
2702 13:53:29.153325
2703 13:53:29.153474 Set Vref, RX VrefLevel [Byte0]: 41
2704 13:53:29.156168 [Byte1]: 41
2705 13:53:29.161177
2706 13:53:29.161308 Set Vref, RX VrefLevel [Byte0]: 42
2707 13:53:29.164597 [Byte1]: 42
2708 13:53:29.169090
2709 13:53:29.169219 Set Vref, RX VrefLevel [Byte0]: 43
2710 13:53:29.171856 [Byte1]: 43
2711 13:53:29.177000
2712 13:53:29.177153 Set Vref, RX VrefLevel [Byte0]: 44
2713 13:53:29.180277 [Byte1]: 44
2714 13:53:29.185002
2715 13:53:29.185163 Set Vref, RX VrefLevel [Byte0]: 45
2716 13:53:29.187813 [Byte1]: 45
2717 13:53:29.192617
2718 13:53:29.192726 Set Vref, RX VrefLevel [Byte0]: 46
2719 13:53:29.196032 [Byte1]: 46
2720 13:53:29.200073
2721 13:53:29.200203 Set Vref, RX VrefLevel [Byte0]: 47
2722 13:53:29.203888 [Byte1]: 47
2723 13:53:29.208144
2724 13:53:29.208273 Set Vref, RX VrefLevel [Byte0]: 48
2725 13:53:29.211639 [Byte1]: 48
2726 13:53:29.215883
2727 13:53:29.216021 Set Vref, RX VrefLevel [Byte0]: 49
2728 13:53:29.219564 [Byte1]: 49
2729 13:53:29.223800
2730 13:53:29.223911 Set Vref, RX VrefLevel [Byte0]: 50
2731 13:53:29.227421 [Byte1]: 50
2732 13:53:29.231698
2733 13:53:29.231807 Set Vref, RX VrefLevel [Byte0]: 51
2734 13:53:29.235265 [Byte1]: 51
2735 13:53:29.239700
2736 13:53:29.239818 Set Vref, RX VrefLevel [Byte0]: 52
2737 13:53:29.243236 [Byte1]: 52
2738 13:53:29.247914
2739 13:53:29.248012 Set Vref, RX VrefLevel [Byte0]: 53
2740 13:53:29.251188 [Byte1]: 53
2741 13:53:29.255274
2742 13:53:29.255397 Set Vref, RX VrefLevel [Byte0]: 54
2743 13:53:29.258581 [Byte1]: 54
2744 13:53:29.263567
2745 13:53:29.263670 Set Vref, RX VrefLevel [Byte0]: 55
2746 13:53:29.267022 [Byte1]: 55
2747 13:53:29.271365
2748 13:53:29.271480 Set Vref, RX VrefLevel [Byte0]: 56
2749 13:53:29.274754 [Byte1]: 56
2750 13:53:29.279626
2751 13:53:29.279723 Set Vref, RX VrefLevel [Byte0]: 57
2752 13:53:29.282992 [Byte1]: 57
2753 13:53:29.287062
2754 13:53:29.287197 Set Vref, RX VrefLevel [Byte0]: 58
2755 13:53:29.290534 [Byte1]: 58
2756 13:53:29.295176
2757 13:53:29.295320 Set Vref, RX VrefLevel [Byte0]: 59
2758 13:53:29.298691 [Byte1]: 59
2759 13:53:29.303012
2760 13:53:29.303107 Set Vref, RX VrefLevel [Byte0]: 60
2761 13:53:29.306168 [Byte1]: 60
2762 13:53:29.310828
2763 13:53:29.310943 Set Vref, RX VrefLevel [Byte0]: 61
2764 13:53:29.314305 [Byte1]: 61
2765 13:53:29.319136
2766 13:53:29.319287 Set Vref, RX VrefLevel [Byte0]: 62
2767 13:53:29.321747 [Byte1]: 62
2768 13:53:29.326564
2769 13:53:29.326675 Set Vref, RX VrefLevel [Byte0]: 63
2770 13:53:29.329990 [Byte1]: 63
2771 13:53:29.334292
2772 13:53:29.334385 Set Vref, RX VrefLevel [Byte0]: 64
2773 13:53:29.338010 [Byte1]: 64
2774 13:53:29.342139
2775 13:53:29.342239 Set Vref, RX VrefLevel [Byte0]: 65
2776 13:53:29.345830 [Byte1]: 65
2777 13:53:29.350147
2778 13:53:29.350238 Set Vref, RX VrefLevel [Byte0]: 66
2779 13:53:29.353494 [Byte1]: 66
2780 13:53:29.357871
2781 13:53:29.357991 Set Vref, RX VrefLevel [Byte0]: 67
2782 13:53:29.361270 [Byte1]: 67
2783 13:53:29.366205
2784 13:53:29.366322 Set Vref, RX VrefLevel [Byte0]: 68
2785 13:53:29.369681 [Byte1]: 68
2786 13:53:29.373938
2787 13:53:29.374041 Set Vref, RX VrefLevel [Byte0]: 69
2788 13:53:29.377260 [Byte1]: 69
2789 13:53:29.382144
2790 13:53:29.382228 Final RX Vref Byte 0 = 56 to rank0
2791 13:53:29.384925 Final RX Vref Byte 1 = 49 to rank0
2792 13:53:29.388267 Final RX Vref Byte 0 = 56 to rank1
2793 13:53:29.391607 Final RX Vref Byte 1 = 49 to rank1==
2794 13:53:29.394931 Dram Type= 6, Freq= 0, CH_0, rank 0
2795 13:53:29.402031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2796 13:53:29.402126 ==
2797 13:53:29.402192 DQS Delay:
2798 13:53:29.402258 DQS0 = 0, DQS1 = 0
2799 13:53:29.404929 DQM Delay:
2800 13:53:29.405042 DQM0 = 120, DQM1 = 111
2801 13:53:29.408324 DQ Delay:
2802 13:53:29.412052 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =118
2803 13:53:29.415309 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2804 13:53:29.418854 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =104
2805 13:53:29.422178 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2806 13:53:29.422288
2807 13:53:29.422388
2808 13:53:29.428736 [DQSOSCAuto] RK0, (LSB)MR18= 0x140d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2809 13:53:29.432065 CH0 RK0: MR19=404, MR18=140D
2810 13:53:29.438724 CH0_RK0: MR19=0x404, MR18=0x140D, DQSOSC=402, MR23=63, INC=40, DEC=27
2811 13:53:29.438822
2812 13:53:29.441929 ----->DramcWriteLeveling(PI) begin...
2813 13:53:29.442039 ==
2814 13:53:29.445325 Dram Type= 6, Freq= 0, CH_0, rank 1
2815 13:53:29.448894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2816 13:53:29.448999 ==
2817 13:53:29.452349 Write leveling (Byte 0): 34 => 34
2818 13:53:29.455862 Write leveling (Byte 1): 30 => 30
2819 13:53:29.458569 DramcWriteLeveling(PI) end<-----
2820 13:53:29.458703
2821 13:53:29.458809 ==
2822 13:53:29.462181 Dram Type= 6, Freq= 0, CH_0, rank 1
2823 13:53:29.465769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2824 13:53:29.469044 ==
2825 13:53:29.469125 [Gating] SW mode calibration
2826 13:53:29.479014 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2827 13:53:29.482330 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2828 13:53:29.485918 0 15 0 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
2829 13:53:29.492295 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2830 13:53:29.495752 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2831 13:53:29.498978 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2832 13:53:29.505785 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2833 13:53:29.508606 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 13:53:29.512061 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 13:53:29.518605 0 15 28 | B1->B0 | 3434 3131 | 0 0 | (0 1) (0 0)
2836 13:53:29.522102 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2837 13:53:29.525816 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2838 13:53:29.532305 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2839 13:53:29.535847 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2840 13:53:29.538558 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2841 13:53:29.545418 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 13:53:29.548776 1 0 24 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
2843 13:53:29.552043 1 0 28 | B1->B0 | 3a3a 3b3b | 0 1 | (0 0) (0 0)
2844 13:53:29.555353 1 1 0 | B1->B0 | 4646 4444 | 0 1 | (0 0) (0 0)
2845 13:53:29.562165 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2846 13:53:29.565397 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2847 13:53:29.569031 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2848 13:53:29.575156 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2849 13:53:29.578449 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 13:53:29.581984 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2851 13:53:29.588948 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2852 13:53:29.591928 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2853 13:53:29.595438 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2854 13:53:29.602468 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2855 13:53:29.605243 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2856 13:53:29.608652 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 13:53:29.615713 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 13:53:29.618549 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 13:53:29.622285 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 13:53:29.628756 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 13:53:29.632357 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 13:53:29.635127 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 13:53:29.641955 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 13:53:29.645404 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 13:53:29.649115 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 13:53:29.655275 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 13:53:29.658781 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2868 13:53:29.662459 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2869 13:53:29.665882 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 13:53:29.668746 Total UI for P1: 0, mck2ui 16
2871 13:53:29.672165 best dqsien dly found for B0: ( 1, 3, 30)
2872 13:53:29.675698 Total UI for P1: 0, mck2ui 16
2873 13:53:29.679008 best dqsien dly found for B1: ( 1, 3, 30)
2874 13:53:29.682137 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2875 13:53:29.685162 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2876 13:53:29.685250
2877 13:53:29.692350 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2878 13:53:29.695283 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2879 13:53:29.698533 [Gating] SW calibration Done
2880 13:53:29.698620 ==
2881 13:53:29.702003 Dram Type= 6, Freq= 0, CH_0, rank 1
2882 13:53:29.705640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2883 13:53:29.705743 ==
2884 13:53:29.705810 RX Vref Scan: 0
2885 13:53:29.705871
2886 13:53:29.708463 RX Vref 0 -> 0, step: 1
2887 13:53:29.708547
2888 13:53:29.712495 RX Delay -40 -> 252, step: 8
2889 13:53:29.715305 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2890 13:53:29.719047 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2891 13:53:29.725614 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2892 13:53:29.729035 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2893 13:53:29.732095 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2894 13:53:29.735681 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2895 13:53:29.739140 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2896 13:53:29.742140 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2897 13:53:29.748967 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2898 13:53:29.752522 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2899 13:53:29.756014 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2900 13:53:29.758800 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2901 13:53:29.762347 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2902 13:53:29.768836 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2903 13:53:29.772299 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2904 13:53:29.775934 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2905 13:53:29.776056 ==
2906 13:53:29.779137 Dram Type= 6, Freq= 0, CH_0, rank 1
2907 13:53:29.782771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2908 13:53:29.782889 ==
2909 13:53:29.785637 DQS Delay:
2910 13:53:29.785722 DQS0 = 0, DQS1 = 0
2911 13:53:29.789174 DQM Delay:
2912 13:53:29.789259 DQM0 = 121, DQM1 = 112
2913 13:53:29.789324 DQ Delay:
2914 13:53:29.795375 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2915 13:53:29.798958 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2916 13:53:29.802302 DQ8 =99, DQ9 =103, DQ10 =107, DQ11 =107
2917 13:53:29.805516 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2918 13:53:29.805623
2919 13:53:29.805717
2920 13:53:29.805817 ==
2921 13:53:29.809198 Dram Type= 6, Freq= 0, CH_0, rank 1
2922 13:53:29.812325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2923 13:53:29.812432 ==
2924 13:53:29.812497
2925 13:53:29.812557
2926 13:53:29.815947 TX Vref Scan disable
2927 13:53:29.819249 == TX Byte 0 ==
2928 13:53:29.822207 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2929 13:53:29.825914 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2930 13:53:29.829007 == TX Byte 1 ==
2931 13:53:29.832599 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2932 13:53:29.835980 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2933 13:53:29.836089 ==
2934 13:53:29.839624 Dram Type= 6, Freq= 0, CH_0, rank 1
2935 13:53:29.842307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2936 13:53:29.842391 ==
2937 13:53:29.856051 TX Vref=22, minBit 1, minWin=25, winSum=415
2938 13:53:29.859524 TX Vref=24, minBit 3, minWin=25, winSum=419
2939 13:53:29.862367 TX Vref=26, minBit 3, minWin=25, winSum=416
2940 13:53:29.865740 TX Vref=28, minBit 12, minWin=25, winSum=425
2941 13:53:29.869362 TX Vref=30, minBit 12, minWin=25, winSum=423
2942 13:53:29.875713 TX Vref=32, minBit 10, minWin=25, winSum=419
2943 13:53:29.879128 [TxChooseVref] Worse bit 12, Min win 25, Win sum 425, Final Vref 28
2944 13:53:29.879234
2945 13:53:29.882685 Final TX Range 1 Vref 28
2946 13:53:29.882790
2947 13:53:29.882880 ==
2948 13:53:29.885906 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 13:53:29.889431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 13:53:29.889515 ==
2951 13:53:29.892821
2952 13:53:29.892926
2953 13:53:29.893020 TX Vref Scan disable
2954 13:53:29.896129 == TX Byte 0 ==
2955 13:53:29.899572 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2956 13:53:29.902526 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2957 13:53:29.906050 == TX Byte 1 ==
2958 13:53:29.909597 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2959 13:53:29.913193 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2960 13:53:29.916023
2961 13:53:29.916135 [DATLAT]
2962 13:53:29.916231 Freq=1200, CH0 RK1
2963 13:53:29.916328
2964 13:53:29.919401 DATLAT Default: 0xd
2965 13:53:29.919502 0, 0xFFFF, sum = 0
2966 13:53:29.922946 1, 0xFFFF, sum = 0
2967 13:53:29.923054 2, 0xFFFF, sum = 0
2968 13:53:29.926376 3, 0xFFFF, sum = 0
2969 13:53:29.926490 4, 0xFFFF, sum = 0
2970 13:53:29.929722 5, 0xFFFF, sum = 0
2971 13:53:29.933203 6, 0xFFFF, sum = 0
2972 13:53:29.933324 7, 0xFFFF, sum = 0
2973 13:53:29.935877 8, 0xFFFF, sum = 0
2974 13:53:29.936002 9, 0xFFFF, sum = 0
2975 13:53:29.939611 10, 0xFFFF, sum = 0
2976 13:53:29.939692 11, 0xFFFF, sum = 0
2977 13:53:29.942840 12, 0x0, sum = 1
2978 13:53:29.942960 13, 0x0, sum = 2
2979 13:53:29.943064 14, 0x0, sum = 3
2980 13:53:29.946482 15, 0x0, sum = 4
2981 13:53:29.946565 best_step = 13
2982 13:53:29.946627
2983 13:53:29.949420 ==
2984 13:53:29.949502 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 13:53:29.956229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 13:53:29.956363 ==
2987 13:53:29.956451 RX Vref Scan: 0
2988 13:53:29.956538
2989 13:53:29.960015 RX Vref 0 -> 0, step: 1
2990 13:53:29.960119
2991 13:53:29.963079 RX Delay -13 -> 252, step: 4
2992 13:53:29.966321 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
2993 13:53:29.969588 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
2994 13:53:29.975889 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
2995 13:53:29.979471 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
2996 13:53:29.983027 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
2997 13:53:29.986535 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
2998 13:53:29.989334 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
2999 13:53:29.996383 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3000 13:53:29.999910 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3001 13:53:30.002770 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3002 13:53:30.006331 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3003 13:53:30.009886 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3004 13:53:30.016162 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3005 13:53:30.019633 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3006 13:53:30.023344 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3007 13:53:30.026152 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3008 13:53:30.026268 ==
3009 13:53:30.029580 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 13:53:30.036354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 13:53:30.036474 ==
3012 13:53:30.036577 DQS Delay:
3013 13:53:30.036666 DQS0 = 0, DQS1 = 0
3014 13:53:30.039934 DQM Delay:
3015 13:53:30.040061 DQM0 = 121, DQM1 = 110
3016 13:53:30.043586 DQ Delay:
3017 13:53:30.046452 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3018 13:53:30.049976 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3019 13:53:30.052890 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3020 13:53:30.056394 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3021 13:53:30.056509
3022 13:53:30.056603
3023 13:53:30.063125 [DQSOSCAuto] RK1, (LSB)MR18= 0xced, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3024 13:53:30.066380 CH0 RK1: MR19=403, MR18=CED
3025 13:53:30.073403 CH0_RK1: MR19=0x403, MR18=0xCED, DQSOSC=405, MR23=63, INC=39, DEC=26
3026 13:53:30.076297 [RxdqsGatingPostProcess] freq 1200
3027 13:53:30.082838 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3028 13:53:30.086406 best DQS0 dly(2T, 0.5T) = (0, 11)
3029 13:53:30.086547 best DQS1 dly(2T, 0.5T) = (0, 12)
3030 13:53:30.089931 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3031 13:53:30.093111 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3032 13:53:30.096632 best DQS0 dly(2T, 0.5T) = (0, 11)
3033 13:53:30.099837 best DQS1 dly(2T, 0.5T) = (0, 11)
3034 13:53:30.103269 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3035 13:53:30.106278 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3036 13:53:30.109822 Pre-setting of DQS Precalculation
3037 13:53:30.113029 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3038 13:53:30.116499 ==
3039 13:53:30.119985 Dram Type= 6, Freq= 0, CH_1, rank 0
3040 13:53:30.123448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 13:53:30.123580 ==
3042 13:53:30.126426 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3043 13:53:30.133469 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3044 13:53:30.142394 [CA 0] Center 37 (7~68) winsize 62
3045 13:53:30.146146 [CA 1] Center 37 (7~68) winsize 62
3046 13:53:30.148958 [CA 2] Center 35 (5~65) winsize 61
3047 13:53:30.152640 [CA 3] Center 34 (4~64) winsize 61
3048 13:53:30.155494 [CA 4] Center 34 (4~64) winsize 61
3049 13:53:30.159079 [CA 5] Center 33 (3~63) winsize 61
3050 13:53:30.159184
3051 13:53:30.162642 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3052 13:53:30.162752
3053 13:53:30.166089 [CATrainingPosCal] consider 1 rank data
3054 13:53:30.169120 u2DelayCellTimex100 = 270/100 ps
3055 13:53:30.172658 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3056 13:53:30.175493 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3057 13:53:30.182599 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3058 13:53:30.186018 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3059 13:53:30.188777 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3060 13:53:30.192425 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3061 13:53:30.192504
3062 13:53:30.195796 CA PerBit enable=1, Macro0, CA PI delay=33
3063 13:53:30.195901
3064 13:53:30.199391 [CBTSetCACLKResult] CA Dly = 33
3065 13:53:30.199480 CS Dly: 8 (0~39)
3066 13:53:30.199545 ==
3067 13:53:30.202202 Dram Type= 6, Freq= 0, CH_1, rank 1
3068 13:53:30.208776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3069 13:53:30.208902 ==
3070 13:53:30.212566 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3071 13:53:30.218698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3072 13:53:30.227962 [CA 0] Center 37 (7~68) winsize 62
3073 13:53:30.231331 [CA 1] Center 37 (7~68) winsize 62
3074 13:53:30.234791 [CA 2] Center 35 (5~65) winsize 61
3075 13:53:30.238252 [CA 3] Center 34 (4~65) winsize 62
3076 13:53:30.241629 [CA 4] Center 34 (4~65) winsize 62
3077 13:53:30.244958 [CA 5] Center 33 (4~63) winsize 60
3078 13:53:30.245053
3079 13:53:30.248128 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3080 13:53:30.248247
3081 13:53:30.251531 [CATrainingPosCal] consider 2 rank data
3082 13:53:30.254864 u2DelayCellTimex100 = 270/100 ps
3083 13:53:30.257922 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3084 13:53:30.261401 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3085 13:53:30.267913 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3086 13:53:30.271487 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3087 13:53:30.274929 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3088 13:53:30.277766 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3089 13:53:30.277852
3090 13:53:30.281321 CA PerBit enable=1, Macro0, CA PI delay=33
3091 13:53:30.281408
3092 13:53:30.284899 [CBTSetCACLKResult] CA Dly = 33
3093 13:53:30.285009 CS Dly: 9 (0~41)
3094 13:53:30.285103
3095 13:53:30.288399 ----->DramcWriteLeveling(PI) begin...
3096 13:53:30.291667 ==
3097 13:53:30.291788 Dram Type= 6, Freq= 0, CH_1, rank 0
3098 13:53:30.297981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 13:53:30.298091 ==
3100 13:53:30.301568 Write leveling (Byte 0): 27 => 27
3101 13:53:30.305247 Write leveling (Byte 1): 27 => 27
3102 13:53:30.305347 DramcWriteLeveling(PI) end<-----
3103 13:53:30.307923
3104 13:53:30.308010 ==
3105 13:53:30.311703 Dram Type= 6, Freq= 0, CH_1, rank 0
3106 13:53:30.315308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 13:53:30.315409 ==
3108 13:53:30.318106 [Gating] SW mode calibration
3109 13:53:30.324995 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3110 13:53:30.328465 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3111 13:53:30.334859 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
3112 13:53:30.338078 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3113 13:53:30.341445 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3114 13:53:30.348320 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3115 13:53:30.351695 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 13:53:30.354933 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 13:53:30.361425 0 15 24 | B1->B0 | 3232 2b2b | 0 0 | (0 0) (0 0)
3118 13:53:30.364588 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3119 13:53:30.368290 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3120 13:53:30.374533 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3121 13:53:30.378172 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3122 13:53:30.381543 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3123 13:53:30.387776 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 13:53:30.391325 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 13:53:30.394811 1 0 24 | B1->B0 | 3030 3d3d | 0 0 | (1 1) (0 0)
3126 13:53:30.401147 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3127 13:53:30.404544 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3128 13:53:30.408121 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3129 13:53:30.414442 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3130 13:53:30.418158 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 13:53:30.421638 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 13:53:30.425009 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 13:53:30.431647 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3134 13:53:30.435021 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3135 13:53:30.437992 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3136 13:53:30.444918 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3137 13:53:30.448314 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 13:53:30.451622 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 13:53:30.458280 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 13:53:30.461250 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 13:53:30.464636 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 13:53:30.471799 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 13:53:30.475007 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 13:53:30.478198 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 13:53:30.481437 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 13:53:30.488682 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 13:53:30.491959 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 13:53:30.495105 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 13:53:30.502039 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3150 13:53:30.504834 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3151 13:53:30.508246 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 13:53:30.511883 Total UI for P1: 0, mck2ui 16
3153 13:53:30.515211 best dqsien dly found for B0: ( 1, 3, 26)
3154 13:53:30.518114 Total UI for P1: 0, mck2ui 16
3155 13:53:30.521757 best dqsien dly found for B1: ( 1, 3, 26)
3156 13:53:30.525221 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3157 13:53:30.528628 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3158 13:53:30.528744
3159 13:53:30.534957 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3160 13:53:30.538466 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3161 13:53:30.538576 [Gating] SW calibration Done
3162 13:53:30.542026 ==
3163 13:53:30.544867 Dram Type= 6, Freq= 0, CH_1, rank 0
3164 13:53:30.548418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3165 13:53:30.548521 ==
3166 13:53:30.548589 RX Vref Scan: 0
3167 13:53:30.548650
3168 13:53:30.551810 RX Vref 0 -> 0, step: 1
3169 13:53:30.551904
3170 13:53:30.555347 RX Delay -40 -> 252, step: 8
3171 13:53:30.558785 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3172 13:53:30.561995 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3173 13:53:30.565335 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3174 13:53:30.572234 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3175 13:53:30.575305 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3176 13:53:30.578734 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3177 13:53:30.582168 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3178 13:53:30.585047 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3179 13:53:30.591640 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3180 13:53:30.595228 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3181 13:53:30.598587 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3182 13:53:30.602209 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3183 13:53:30.605493 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3184 13:53:30.612006 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3185 13:53:30.615309 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3186 13:53:30.618958 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3187 13:53:30.619047 ==
3188 13:53:30.621850 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 13:53:30.625478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 13:53:30.625589 ==
3191 13:53:30.629025 DQS Delay:
3192 13:53:30.629106 DQS0 = 0, DQS1 = 0
3193 13:53:30.631818 DQM Delay:
3194 13:53:30.631917 DQM0 = 120, DQM1 = 116
3195 13:53:30.632009 DQ Delay:
3196 13:53:30.635256 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3197 13:53:30.638768 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3198 13:53:30.645856 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3199 13:53:30.648726 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3200 13:53:30.648831
3201 13:53:30.648943
3202 13:53:30.649034 ==
3203 13:53:30.652254 Dram Type= 6, Freq= 0, CH_1, rank 0
3204 13:53:30.655796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3205 13:53:30.655910 ==
3206 13:53:30.656006
3207 13:53:30.656097
3208 13:53:30.658590 TX Vref Scan disable
3209 13:53:30.658689 == TX Byte 0 ==
3210 13:53:30.665595 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3211 13:53:30.669061 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3212 13:53:30.669180 == TX Byte 1 ==
3213 13:53:30.675871 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3214 13:53:30.678741 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3215 13:53:30.678851 ==
3216 13:53:30.682067 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 13:53:30.685315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 13:53:30.685437 ==
3219 13:53:30.698207 TX Vref=22, minBit 9, minWin=24, winSum=409
3220 13:53:30.701305 TX Vref=24, minBit 9, minWin=24, winSum=412
3221 13:53:30.704715 TX Vref=26, minBit 1, minWin=26, winSum=423
3222 13:53:30.708389 TX Vref=28, minBit 11, minWin=25, winSum=423
3223 13:53:30.711907 TX Vref=30, minBit 1, minWin=26, winSum=431
3224 13:53:30.714744 TX Vref=32, minBit 9, minWin=26, winSum=430
3225 13:53:30.721509 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
3226 13:53:30.721648
3227 13:53:30.724861 Final TX Range 1 Vref 30
3228 13:53:30.724979
3229 13:53:30.725079 ==
3230 13:53:30.727949 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 13:53:30.731530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 13:53:30.731621 ==
3233 13:53:30.731686
3234 13:53:30.735325
3235 13:53:30.735437 TX Vref Scan disable
3236 13:53:30.738011 == TX Byte 0 ==
3237 13:53:30.741439 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3238 13:53:30.745019 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3239 13:53:30.748498 == TX Byte 1 ==
3240 13:53:30.751293 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3241 13:53:30.754955 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3242 13:53:30.755059
3243 13:53:30.758436 [DATLAT]
3244 13:53:30.758512 Freq=1200, CH1 RK0
3245 13:53:30.758583
3246 13:53:30.761927 DATLAT Default: 0xd
3247 13:53:30.762006 0, 0xFFFF, sum = 0
3248 13:53:30.764841 1, 0xFFFF, sum = 0
3249 13:53:30.764921 2, 0xFFFF, sum = 0
3250 13:53:30.768382 3, 0xFFFF, sum = 0
3251 13:53:30.768460 4, 0xFFFF, sum = 0
3252 13:53:30.771139 5, 0xFFFF, sum = 0
3253 13:53:30.771216 6, 0xFFFF, sum = 0
3254 13:53:30.774528 7, 0xFFFF, sum = 0
3255 13:53:30.774647 8, 0xFFFF, sum = 0
3256 13:53:30.777905 9, 0xFFFF, sum = 0
3257 13:53:30.781614 10, 0xFFFF, sum = 0
3258 13:53:30.781733 11, 0xFFFF, sum = 0
3259 13:53:30.785133 12, 0x0, sum = 1
3260 13:53:30.785263 13, 0x0, sum = 2
3261 13:53:30.785340 14, 0x0, sum = 3
3262 13:53:30.787976 15, 0x0, sum = 4
3263 13:53:30.788098 best_step = 13
3264 13:53:30.788194
3265 13:53:30.788306 ==
3266 13:53:30.791264 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 13:53:30.798111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 13:53:30.798227 ==
3269 13:53:30.798325 RX Vref Scan: 1
3270 13:53:30.798414
3271 13:53:30.802102 Set Vref Range= 32 -> 127
3272 13:53:30.802212
3273 13:53:30.804720 RX Vref 32 -> 127, step: 1
3274 13:53:30.804824
3275 13:53:30.808590 RX Delay -5 -> 252, step: 4
3276 13:53:30.808684
3277 13:53:30.808752 Set Vref, RX VrefLevel [Byte0]: 32
3278 13:53:30.811815 [Byte1]: 32
3279 13:53:30.816329
3280 13:53:30.816423 Set Vref, RX VrefLevel [Byte0]: 33
3281 13:53:30.822864 [Byte1]: 33
3282 13:53:30.822990
3283 13:53:30.825817 Set Vref, RX VrefLevel [Byte0]: 34
3284 13:53:30.829219 [Byte1]: 34
3285 13:53:30.829355
3286 13:53:30.832990 Set Vref, RX VrefLevel [Byte0]: 35
3287 13:53:30.835761 [Byte1]: 35
3288 13:53:30.839813
3289 13:53:30.839920 Set Vref, RX VrefLevel [Byte0]: 36
3290 13:53:30.843064 [Byte1]: 36
3291 13:53:30.847501
3292 13:53:30.847582 Set Vref, RX VrefLevel [Byte0]: 37
3293 13:53:30.850683 [Byte1]: 37
3294 13:53:30.855696
3295 13:53:30.855820 Set Vref, RX VrefLevel [Byte0]: 38
3296 13:53:30.858672 [Byte1]: 38
3297 13:53:30.863673
3298 13:53:30.863773 Set Vref, RX VrefLevel [Byte0]: 39
3299 13:53:30.866464 [Byte1]: 39
3300 13:53:30.871433
3301 13:53:30.871525 Set Vref, RX VrefLevel [Byte0]: 40
3302 13:53:30.874239 [Byte1]: 40
3303 13:53:30.879087
3304 13:53:30.879190 Set Vref, RX VrefLevel [Byte0]: 41
3305 13:53:30.882568 [Byte1]: 41
3306 13:53:30.886811
3307 13:53:30.886913 Set Vref, RX VrefLevel [Byte0]: 42
3308 13:53:30.890316 [Byte1]: 42
3309 13:53:30.894580
3310 13:53:30.894724 Set Vref, RX VrefLevel [Byte0]: 43
3311 13:53:30.898100 [Byte1]: 43
3312 13:53:30.902789
3313 13:53:30.902924 Set Vref, RX VrefLevel [Byte0]: 44
3314 13:53:30.906128 [Byte1]: 44
3315 13:53:30.910154
3316 13:53:30.910282 Set Vref, RX VrefLevel [Byte0]: 45
3317 13:53:30.914069 [Byte1]: 45
3318 13:53:30.918210
3319 13:53:30.918329 Set Vref, RX VrefLevel [Byte0]: 46
3320 13:53:30.921394 [Byte1]: 46
3321 13:53:30.926100
3322 13:53:30.926216 Set Vref, RX VrefLevel [Byte0]: 47
3323 13:53:30.929859 [Byte1]: 47
3324 13:53:30.934012
3325 13:53:30.934130 Set Vref, RX VrefLevel [Byte0]: 48
3326 13:53:30.937480 [Byte1]: 48
3327 13:53:30.941647
3328 13:53:30.941768 Set Vref, RX VrefLevel [Byte0]: 49
3329 13:53:30.945059 [Byte1]: 49
3330 13:53:30.949383
3331 13:53:30.949498 Set Vref, RX VrefLevel [Byte0]: 50
3332 13:53:30.952872 [Byte1]: 50
3333 13:53:30.957714
3334 13:53:30.957823 Set Vref, RX VrefLevel [Byte0]: 51
3335 13:53:30.960633 [Byte1]: 51
3336 13:53:30.965447
3337 13:53:30.965557 Set Vref, RX VrefLevel [Byte0]: 52
3338 13:53:30.968677 [Byte1]: 52
3339 13:53:30.973048
3340 13:53:30.973138 Set Vref, RX VrefLevel [Byte0]: 53
3341 13:53:30.976933 [Byte1]: 53
3342 13:53:30.981375
3343 13:53:30.981492 Set Vref, RX VrefLevel [Byte0]: 54
3344 13:53:30.984368 [Byte1]: 54
3345 13:53:30.988665
3346 13:53:30.988776 Set Vref, RX VrefLevel [Byte0]: 55
3347 13:53:30.992325 [Byte1]: 55
3348 13:53:30.996465
3349 13:53:30.996576 Set Vref, RX VrefLevel [Byte0]: 56
3350 13:53:30.999934 [Byte1]: 56
3351 13:53:31.004949
3352 13:53:31.005061 Set Vref, RX VrefLevel [Byte0]: 57
3353 13:53:31.007648 [Byte1]: 57
3354 13:53:31.012409
3355 13:53:31.012491 Set Vref, RX VrefLevel [Byte0]: 58
3356 13:53:31.015752 [Byte1]: 58
3357 13:53:31.020273
3358 13:53:31.020395 Set Vref, RX VrefLevel [Byte0]: 59
3359 13:53:31.023393 [Byte1]: 59
3360 13:53:31.027958
3361 13:53:31.028074 Set Vref, RX VrefLevel [Byte0]: 60
3362 13:53:31.031348 [Byte1]: 60
3363 13:53:31.036035
3364 13:53:31.036153 Set Vref, RX VrefLevel [Byte0]: 61
3365 13:53:31.039548 [Byte1]: 61
3366 13:53:31.043839
3367 13:53:31.044017 Set Vref, RX VrefLevel [Byte0]: 62
3368 13:53:31.047320 [Byte1]: 62
3369 13:53:31.051595
3370 13:53:31.051710 Set Vref, RX VrefLevel [Byte0]: 63
3371 13:53:31.055243 [Byte1]: 63
3372 13:53:31.059954
3373 13:53:31.060080 Set Vref, RX VrefLevel [Byte0]: 64
3374 13:53:31.062821 [Byte1]: 64
3375 13:53:31.067758
3376 13:53:31.067878 Set Vref, RX VrefLevel [Byte0]: 65
3377 13:53:31.070557 [Byte1]: 65
3378 13:53:31.075486
3379 13:53:31.075622 Set Vref, RX VrefLevel [Byte0]: 66
3380 13:53:31.078891 [Byte1]: 66
3381 13:53:31.082901
3382 13:53:31.083021 Set Vref, RX VrefLevel [Byte0]: 67
3383 13:53:31.086654 [Byte1]: 67
3384 13:53:31.091183
3385 13:53:31.091313 Set Vref, RX VrefLevel [Byte0]: 68
3386 13:53:31.094195 [Byte1]: 68
3387 13:53:31.099208
3388 13:53:31.099317 Set Vref, RX VrefLevel [Byte0]: 69
3389 13:53:31.102019 [Byte1]: 69
3390 13:53:31.107087
3391 13:53:31.107233 Final RX Vref Byte 0 = 53 to rank0
3392 13:53:31.109925 Final RX Vref Byte 1 = 48 to rank0
3393 13:53:31.113523 Final RX Vref Byte 0 = 53 to rank1
3394 13:53:31.117116 Final RX Vref Byte 1 = 48 to rank1==
3395 13:53:31.119830 Dram Type= 6, Freq= 0, CH_1, rank 0
3396 13:53:31.126397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3397 13:53:31.126587 ==
3398 13:53:31.126712 DQS Delay:
3399 13:53:31.126804 DQS0 = 0, DQS1 = 0
3400 13:53:31.129612 DQM Delay:
3401 13:53:31.129738 DQM0 = 119, DQM1 = 116
3402 13:53:31.133598 DQ Delay:
3403 13:53:31.136731 DQ0 =122, DQ1 =114, DQ2 =110, DQ3 =114
3404 13:53:31.139825 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3405 13:53:31.143070 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3406 13:53:31.146244 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3407 13:53:31.146375
3408 13:53:31.146469
3409 13:53:31.156362 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3410 13:53:31.156515 CH1 RK0: MR19=404, MR18=114
3411 13:53:31.162980 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3412 13:53:31.163143
3413 13:53:31.166558 ----->DramcWriteLeveling(PI) begin...
3414 13:53:31.166700 ==
3415 13:53:31.170176 Dram Type= 6, Freq= 0, CH_1, rank 1
3416 13:53:31.173034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3417 13:53:31.176601 ==
3418 13:53:31.176729 Write leveling (Byte 0): 26 => 26
3419 13:53:31.180199 Write leveling (Byte 1): 29 => 29
3420 13:53:31.183123 DramcWriteLeveling(PI) end<-----
3421 13:53:31.183279
3422 13:53:31.183385 ==
3423 13:53:31.186738 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 13:53:31.192983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3425 13:53:31.193108 ==
3426 13:53:31.196810 [Gating] SW mode calibration
3427 13:53:31.203244 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3428 13:53:31.205945 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3429 13:53:31.213001 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3430 13:53:31.216149 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3431 13:53:31.219772 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3432 13:53:31.226042 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3433 13:53:31.229590 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3434 13:53:31.233151 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3435 13:53:31.239648 0 15 24 | B1->B0 | 2727 3333 | 0 1 | (1 0) (1 0)
3436 13:53:31.242485 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 0)
3437 13:53:31.245874 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3438 13:53:31.249336 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3439 13:53:31.256027 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3440 13:53:31.259200 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3441 13:53:31.262293 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3442 13:53:31.269608 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3443 13:53:31.272192 1 0 24 | B1->B0 | 4646 302f | 0 1 | (0 0) (0 0)
3444 13:53:31.276055 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3445 13:53:31.282307 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3446 13:53:31.285971 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3447 13:53:31.288855 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3448 13:53:31.295774 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 13:53:31.298630 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 13:53:31.302224 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3451 13:53:31.308771 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3452 13:53:31.312321 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3453 13:53:31.315915 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 13:53:31.322072 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 13:53:31.325769 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 13:53:31.328967 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 13:53:31.335846 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 13:53:31.338631 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 13:53:31.342273 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 13:53:31.349374 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 13:53:31.352110 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 13:53:31.355548 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 13:53:31.361921 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 13:53:31.365418 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 13:53:31.368760 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 13:53:31.375635 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3467 13:53:31.378540 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3468 13:53:31.381954 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3469 13:53:31.385311 Total UI for P1: 0, mck2ui 16
3470 13:53:31.388519 best dqsien dly found for B1: ( 1, 3, 22)
3471 13:53:31.395602 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 13:53:31.395774 Total UI for P1: 0, mck2ui 16
3473 13:53:31.398430 best dqsien dly found for B0: ( 1, 3, 26)
3474 13:53:31.404814 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3475 13:53:31.408241 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3476 13:53:31.408405
3477 13:53:31.411898 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3478 13:53:31.415409 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3479 13:53:31.418269 [Gating] SW calibration Done
3480 13:53:31.418377 ==
3481 13:53:31.421746 Dram Type= 6, Freq= 0, CH_1, rank 1
3482 13:53:31.425378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3483 13:53:31.425472 ==
3484 13:53:31.428052 RX Vref Scan: 0
3485 13:53:31.428133
3486 13:53:31.428202 RX Vref 0 -> 0, step: 1
3487 13:53:31.428310
3488 13:53:31.431596 RX Delay -40 -> 252, step: 8
3489 13:53:31.435113 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3490 13:53:31.441487 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3491 13:53:31.444823 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3492 13:53:31.448140 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3493 13:53:31.451365 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3494 13:53:31.454894 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3495 13:53:31.461241 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3496 13:53:31.464843 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3497 13:53:31.468326 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3498 13:53:31.471573 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3499 13:53:31.474948 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3500 13:53:31.481606 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3501 13:53:31.484358 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3502 13:53:31.488005 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3503 13:53:31.491447 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3504 13:53:31.494849 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3505 13:53:31.498211 ==
3506 13:53:31.501012 Dram Type= 6, Freq= 0, CH_1, rank 1
3507 13:53:31.504398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3508 13:53:31.504486 ==
3509 13:53:31.504549 DQS Delay:
3510 13:53:31.507688 DQS0 = 0, DQS1 = 0
3511 13:53:31.507788 DQM Delay:
3512 13:53:31.511177 DQM0 = 121, DQM1 = 118
3513 13:53:31.511277 DQ Delay:
3514 13:53:31.514756 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3515 13:53:31.518143 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3516 13:53:31.521012 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3517 13:53:31.524592 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3518 13:53:31.524676
3519 13:53:31.524745
3520 13:53:31.524806 ==
3521 13:53:31.527373 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 13:53:31.534627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 13:53:31.534747 ==
3524 13:53:31.534856
3525 13:53:31.534951
3526 13:53:31.535036 TX Vref Scan disable
3527 13:53:31.538340 == TX Byte 0 ==
3528 13:53:31.541174 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3529 13:53:31.548376 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3530 13:53:31.548480 == TX Byte 1 ==
3531 13:53:31.551072 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3532 13:53:31.558296 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3533 13:53:31.558440 ==
3534 13:53:31.561412 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 13:53:31.564279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 13:53:31.564413 ==
3537 13:53:31.575616 TX Vref=22, minBit 1, minWin=25, winSum=420
3538 13:53:31.579146 TX Vref=24, minBit 1, minWin=26, winSum=425
3539 13:53:31.582625 TX Vref=26, minBit 1, minWin=26, winSum=426
3540 13:53:31.586160 TX Vref=28, minBit 6, minWin=26, winSum=433
3541 13:53:31.589324 TX Vref=30, minBit 9, minWin=26, winSum=433
3542 13:53:31.595621 TX Vref=32, minBit 9, minWin=26, winSum=436
3543 13:53:31.599131 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 32
3544 13:53:31.599241
3545 13:53:31.602192 Final TX Range 1 Vref 32
3546 13:53:31.602296
3547 13:53:31.602387 ==
3548 13:53:31.605634 Dram Type= 6, Freq= 0, CH_1, rank 1
3549 13:53:31.609120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3550 13:53:31.612678 ==
3551 13:53:31.612802
3552 13:53:31.612913
3553 13:53:31.613026 TX Vref Scan disable
3554 13:53:31.615355 == TX Byte 0 ==
3555 13:53:31.619285 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3556 13:53:31.625448 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3557 13:53:31.625549 == TX Byte 1 ==
3558 13:53:31.629031 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3559 13:53:31.635295 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3560 13:53:31.635422
3561 13:53:31.635526 [DATLAT]
3562 13:53:31.635616 Freq=1200, CH1 RK1
3563 13:53:31.635705
3564 13:53:31.638861 DATLAT Default: 0xd
3565 13:53:31.638969 0, 0xFFFF, sum = 0
3566 13:53:31.642482 1, 0xFFFF, sum = 0
3567 13:53:31.642595 2, 0xFFFF, sum = 0
3568 13:53:31.645421 3, 0xFFFF, sum = 0
3569 13:53:31.648776 4, 0xFFFF, sum = 0
3570 13:53:31.648895 5, 0xFFFF, sum = 0
3571 13:53:31.652317 6, 0xFFFF, sum = 0
3572 13:53:31.652431 7, 0xFFFF, sum = 0
3573 13:53:31.655847 8, 0xFFFF, sum = 0
3574 13:53:31.655955 9, 0xFFFF, sum = 0
3575 13:53:31.658899 10, 0xFFFF, sum = 0
3576 13:53:31.659009 11, 0xFFFF, sum = 0
3577 13:53:31.662509 12, 0x0, sum = 1
3578 13:53:31.662617 13, 0x0, sum = 2
3579 13:53:31.665303 14, 0x0, sum = 3
3580 13:53:31.665417 15, 0x0, sum = 4
3581 13:53:31.665515 best_step = 13
3582 13:53:31.668763
3583 13:53:31.668862 ==
3584 13:53:31.672183 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 13:53:31.675613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 13:53:31.675714 ==
3587 13:53:31.675812 RX Vref Scan: 0
3588 13:53:31.675903
3589 13:53:31.678870 RX Vref 0 -> 0, step: 1
3590 13:53:31.678969
3591 13:53:31.681773 RX Delay -5 -> 252, step: 4
3592 13:53:31.685362 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3593 13:53:31.692157 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3594 13:53:31.695567 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3595 13:53:31.698869 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3596 13:53:31.702258 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3597 13:53:31.705515 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3598 13:53:31.711738 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3599 13:53:31.715180 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3600 13:53:31.718763 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3601 13:53:31.721628 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3602 13:53:31.725072 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3603 13:53:31.732172 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3604 13:53:31.735292 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3605 13:53:31.738476 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3606 13:53:31.742194 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3607 13:53:31.744963 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3608 13:53:31.748658 ==
3609 13:53:31.748746 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 13:53:31.755171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 13:53:31.755258 ==
3612 13:53:31.755324 DQS Delay:
3613 13:53:31.758850 DQS0 = 0, DQS1 = 0
3614 13:53:31.758932 DQM Delay:
3615 13:53:31.761689 DQM0 = 120, DQM1 = 116
3616 13:53:31.761772 DQ Delay:
3617 13:53:31.765213 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3618 13:53:31.768680 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3619 13:53:31.772174 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3620 13:53:31.774995 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =124
3621 13:53:31.775079
3622 13:53:31.775144
3623 13:53:31.784898 [DQSOSCAuto] RK1, (LSB)MR18= 0x14f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3624 13:53:31.788329 CH1 RK1: MR19=403, MR18=14F1
3625 13:53:31.791770 CH1_RK1: MR19=0x403, MR18=0x14F1, DQSOSC=402, MR23=63, INC=40, DEC=27
3626 13:53:31.795058 [RxdqsGatingPostProcess] freq 1200
3627 13:53:31.801595 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3628 13:53:31.804940 best DQS0 dly(2T, 0.5T) = (0, 11)
3629 13:53:31.808045 best DQS1 dly(2T, 0.5T) = (0, 11)
3630 13:53:31.811758 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3631 13:53:31.814504 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3632 13:53:31.817991 best DQS0 dly(2T, 0.5T) = (0, 11)
3633 13:53:31.821679 best DQS1 dly(2T, 0.5T) = (0, 11)
3634 13:53:31.824903 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3635 13:53:31.827946 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3636 13:53:31.831194 Pre-setting of DQS Precalculation
3637 13:53:31.834744 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3638 13:53:31.841057 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3639 13:53:31.847977 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3640 13:53:31.851338
3641 13:53:31.851469
3642 13:53:31.851555 [Calibration Summary] 2400 Mbps
3643 13:53:31.854140 CH 0, Rank 0
3644 13:53:31.854249 SW Impedance : PASS
3645 13:53:31.857716 DUTY Scan : NO K
3646 13:53:31.861367 ZQ Calibration : PASS
3647 13:53:31.861468 Jitter Meter : NO K
3648 13:53:31.864171 CBT Training : PASS
3649 13:53:31.867800 Write leveling : PASS
3650 13:53:31.867899 RX DQS gating : PASS
3651 13:53:31.870649 RX DQ/DQS(RDDQC) : PASS
3652 13:53:31.874057 TX DQ/DQS : PASS
3653 13:53:31.874161 RX DATLAT : PASS
3654 13:53:31.877568 RX DQ/DQS(Engine): PASS
3655 13:53:31.881074 TX OE : NO K
3656 13:53:31.881193 All Pass.
3657 13:53:31.881288
3658 13:53:31.881393 CH 0, Rank 1
3659 13:53:31.883957 SW Impedance : PASS
3660 13:53:31.887432 DUTY Scan : NO K
3661 13:53:31.887548 ZQ Calibration : PASS
3662 13:53:31.891084 Jitter Meter : NO K
3663 13:53:31.893868 CBT Training : PASS
3664 13:53:31.893986 Write leveling : PASS
3665 13:53:31.897661 RX DQS gating : PASS
3666 13:53:31.897771 RX DQ/DQS(RDDQC) : PASS
3667 13:53:31.901183 TX DQ/DQS : PASS
3668 13:53:31.903926 RX DATLAT : PASS
3669 13:53:31.904050 RX DQ/DQS(Engine): PASS
3670 13:53:31.907209 TX OE : NO K
3671 13:53:31.907293 All Pass.
3672 13:53:31.907395
3673 13:53:31.910845 CH 1, Rank 0
3674 13:53:31.910935 SW Impedance : PASS
3675 13:53:31.914461 DUTY Scan : NO K
3676 13:53:31.917384 ZQ Calibration : PASS
3677 13:53:31.917509 Jitter Meter : NO K
3678 13:53:31.920758 CBT Training : PASS
3679 13:53:31.923967 Write leveling : PASS
3680 13:53:31.924052 RX DQS gating : PASS
3681 13:53:31.927194 RX DQ/DQS(RDDQC) : PASS
3682 13:53:31.930924 TX DQ/DQS : PASS
3683 13:53:31.931019 RX DATLAT : PASS
3684 13:53:31.934029 RX DQ/DQS(Engine): PASS
3685 13:53:31.937434 TX OE : NO K
3686 13:53:31.937529 All Pass.
3687 13:53:31.937617
3688 13:53:31.937698 CH 1, Rank 1
3689 13:53:31.940576 SW Impedance : PASS
3690 13:53:31.944075 DUTY Scan : NO K
3691 13:53:31.944190 ZQ Calibration : PASS
3692 13:53:31.947178 Jitter Meter : NO K
3693 13:53:31.947295 CBT Training : PASS
3694 13:53:31.950804 Write leveling : PASS
3695 13:53:31.953864 RX DQS gating : PASS
3696 13:53:31.953954 RX DQ/DQS(RDDQC) : PASS
3697 13:53:31.957093 TX DQ/DQS : PASS
3698 13:53:31.960934 RX DATLAT : PASS
3699 13:53:31.961027 RX DQ/DQS(Engine): PASS
3700 13:53:31.963602 TX OE : NO K
3701 13:53:31.963691 All Pass.
3702 13:53:31.963793
3703 13:53:31.966998 DramC Write-DBI off
3704 13:53:31.970522 PER_BANK_REFRESH: Hybrid Mode
3705 13:53:31.970611 TX_TRACKING: ON
3706 13:53:31.980274 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3707 13:53:31.983646 [FAST_K] Save calibration result to emmc
3708 13:53:31.987350 dramc_set_vcore_voltage set vcore to 650000
3709 13:53:31.990184 Read voltage for 600, 5
3710 13:53:31.990311 Vio18 = 0
3711 13:53:31.990416 Vcore = 650000
3712 13:53:31.993712 Vdram = 0
3713 13:53:31.993810 Vddq = 0
3714 13:53:31.993875 Vmddr = 0
3715 13:53:32.000082 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3716 13:53:32.003693 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3717 13:53:32.007160 MEM_TYPE=3, freq_sel=19
3718 13:53:32.010675 sv_algorithm_assistance_LP4_1600
3719 13:53:32.014056 ============ PULL DRAM RESETB DOWN ============
3720 13:53:32.016933 ========== PULL DRAM RESETB DOWN end =========
3721 13:53:32.023366 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3722 13:53:32.026977 ===================================
3723 13:53:32.030512 LPDDR4 DRAM CONFIGURATION
3724 13:53:32.033236 ===================================
3725 13:53:32.033332 EX_ROW_EN[0] = 0x0
3726 13:53:32.037009 EX_ROW_EN[1] = 0x0
3727 13:53:32.037100 LP4Y_EN = 0x0
3728 13:53:32.040268 WORK_FSP = 0x0
3729 13:53:32.040357 WL = 0x2
3730 13:53:32.043745 RL = 0x2
3731 13:53:32.043833 BL = 0x2
3732 13:53:32.046651 RPST = 0x0
3733 13:53:32.046735 RD_PRE = 0x0
3734 13:53:32.049965 WR_PRE = 0x1
3735 13:53:32.050047 WR_PST = 0x0
3736 13:53:32.053332 DBI_WR = 0x0
3737 13:53:32.056497 DBI_RD = 0x0
3738 13:53:32.056595 OTF = 0x1
3739 13:53:32.060335 ===================================
3740 13:53:32.063388 ===================================
3741 13:53:32.063468 ANA top config
3742 13:53:32.066599 ===================================
3743 13:53:32.069814 DLL_ASYNC_EN = 0
3744 13:53:32.072846 ALL_SLAVE_EN = 1
3745 13:53:32.076551 NEW_RANK_MODE = 1
3746 13:53:32.079885 DLL_IDLE_MODE = 1
3747 13:53:32.080001 LP45_APHY_COMB_EN = 1
3748 13:53:32.082998 TX_ODT_DIS = 1
3749 13:53:32.086402 NEW_8X_MODE = 1
3750 13:53:32.089485 ===================================
3751 13:53:32.093129 ===================================
3752 13:53:32.096411 data_rate = 1200
3753 13:53:32.100055 CKR = 1
3754 13:53:32.100158 DQ_P2S_RATIO = 8
3755 13:53:32.102938 ===================================
3756 13:53:32.106366 CA_P2S_RATIO = 8
3757 13:53:32.109331 DQ_CA_OPEN = 0
3758 13:53:32.112780 DQ_SEMI_OPEN = 0
3759 13:53:32.116015 CA_SEMI_OPEN = 0
3760 13:53:32.119514 CA_FULL_RATE = 0
3761 13:53:32.119621 DQ_CKDIV4_EN = 1
3762 13:53:32.123159 CA_CKDIV4_EN = 1
3763 13:53:32.125962 CA_PREDIV_EN = 0
3764 13:53:32.129479 PH8_DLY = 0
3765 13:53:32.133050 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3766 13:53:32.136521 DQ_AAMCK_DIV = 4
3767 13:53:32.136623 CA_AAMCK_DIV = 4
3768 13:53:32.139490 CA_ADMCK_DIV = 4
3769 13:53:32.142885 DQ_TRACK_CA_EN = 0
3770 13:53:32.146485 CA_PICK = 600
3771 13:53:32.149645 CA_MCKIO = 600
3772 13:53:32.152622 MCKIO_SEMI = 0
3773 13:53:32.155947 PLL_FREQ = 2288
3774 13:53:32.156070 DQ_UI_PI_RATIO = 32
3775 13:53:32.159645 CA_UI_PI_RATIO = 0
3776 13:53:32.163037 ===================================
3777 13:53:32.165839 ===================================
3778 13:53:32.169376 memory_type:LPDDR4
3779 13:53:32.172838 GP_NUM : 10
3780 13:53:32.172930 SRAM_EN : 1
3781 13:53:32.176362 MD32_EN : 0
3782 13:53:32.179104 ===================================
3783 13:53:32.182968 [ANA_INIT] >>>>>>>>>>>>>>
3784 13:53:32.183063 <<<<<< [CONFIGURE PHASE]: ANA_TX
3785 13:53:32.186470 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3786 13:53:32.189174 ===================================
3787 13:53:32.192669 data_rate = 1200,PCW = 0X5800
3788 13:53:32.196037 ===================================
3789 13:53:32.199355 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3790 13:53:32.206054 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3791 13:53:32.209990 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3792 13:53:32.216086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3793 13:53:32.219637 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3794 13:53:32.222888 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3795 13:53:32.226322 [ANA_INIT] flow start
3796 13:53:32.226422 [ANA_INIT] PLL >>>>>>>>
3797 13:53:32.229185 [ANA_INIT] PLL <<<<<<<<
3798 13:53:32.232803 [ANA_INIT] MIDPI >>>>>>>>
3799 13:53:32.232924 [ANA_INIT] MIDPI <<<<<<<<
3800 13:53:32.236330 [ANA_INIT] DLL >>>>>>>>
3801 13:53:32.239101 [ANA_INIT] flow end
3802 13:53:32.242704 ============ LP4 DIFF to SE enter ============
3803 13:53:32.246084 ============ LP4 DIFF to SE exit ============
3804 13:53:32.249037 [ANA_INIT] <<<<<<<<<<<<<
3805 13:53:32.252480 [Flow] Enable top DCM control >>>>>
3806 13:53:32.255643 [Flow] Enable top DCM control <<<<<
3807 13:53:32.259301 Enable DLL master slave shuffle
3808 13:53:32.262222 ==============================================================
3809 13:53:32.265647 Gating Mode config
3810 13:53:32.272681 ==============================================================
3811 13:53:32.272807 Config description:
3812 13:53:32.282535 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3813 13:53:32.289226 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3814 13:53:32.292618 SELPH_MODE 0: By rank 1: By Phase
3815 13:53:32.298952 ==============================================================
3816 13:53:32.302486 GAT_TRACK_EN = 1
3817 13:53:32.306026 RX_GATING_MODE = 2
3818 13:53:32.308883 RX_GATING_TRACK_MODE = 2
3819 13:53:32.312281 SELPH_MODE = 1
3820 13:53:32.315848 PICG_EARLY_EN = 1
3821 13:53:32.318812 VALID_LAT_VALUE = 1
3822 13:53:32.322192 ==============================================================
3823 13:53:32.325490 Enter into Gating configuration >>>>
3824 13:53:32.328621 Exit from Gating configuration <<<<
3825 13:53:32.331874 Enter into DVFS_PRE_config >>>>>
3826 13:53:32.345265 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3827 13:53:32.345390 Exit from DVFS_PRE_config <<<<<
3828 13:53:32.349024 Enter into PICG configuration >>>>
3829 13:53:32.352071 Exit from PICG configuration <<<<
3830 13:53:32.355576 [RX_INPUT] configuration >>>>>
3831 13:53:32.358926 [RX_INPUT] configuration <<<<<
3832 13:53:32.365271 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3833 13:53:32.368900 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3834 13:53:32.375719 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3835 13:53:32.382053 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3836 13:53:32.389029 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3837 13:53:32.395168 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3838 13:53:32.399026 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3839 13:53:32.401794 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3840 13:53:32.405187 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3841 13:53:32.412394 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3842 13:53:32.415218 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3843 13:53:32.418910 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3844 13:53:32.421752 ===================================
3845 13:53:32.425374 LPDDR4 DRAM CONFIGURATION
3846 13:53:32.428203 ===================================
3847 13:53:32.428293 EX_ROW_EN[0] = 0x0
3848 13:53:32.431855 EX_ROW_EN[1] = 0x0
3849 13:53:32.435197 LP4Y_EN = 0x0
3850 13:53:32.435288 WORK_FSP = 0x0
3851 13:53:32.438159 WL = 0x2
3852 13:53:32.438243 RL = 0x2
3853 13:53:32.441638 BL = 0x2
3854 13:53:32.441723 RPST = 0x0
3855 13:53:32.445194 RD_PRE = 0x0
3856 13:53:32.445282 WR_PRE = 0x1
3857 13:53:32.448521 WR_PST = 0x0
3858 13:53:32.448608 DBI_WR = 0x0
3859 13:53:32.451904 DBI_RD = 0x0
3860 13:53:32.451991 OTF = 0x1
3861 13:53:32.454826 ===================================
3862 13:53:32.458456 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3863 13:53:32.464665 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3864 13:53:32.468689 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3865 13:53:32.471332 ===================================
3866 13:53:32.474736 LPDDR4 DRAM CONFIGURATION
3867 13:53:32.478626 ===================================
3868 13:53:32.478725 EX_ROW_EN[0] = 0x10
3869 13:53:32.481805 EX_ROW_EN[1] = 0x0
3870 13:53:32.485146 LP4Y_EN = 0x0
3871 13:53:32.485238 WORK_FSP = 0x0
3872 13:53:32.487853 WL = 0x2
3873 13:53:32.487937 RL = 0x2
3874 13:53:32.491279 BL = 0x2
3875 13:53:32.491365 RPST = 0x0
3876 13:53:32.494802 RD_PRE = 0x0
3877 13:53:32.494889 WR_PRE = 0x1
3878 13:53:32.497627 WR_PST = 0x0
3879 13:53:32.497715 DBI_WR = 0x0
3880 13:53:32.501152 DBI_RD = 0x0
3881 13:53:32.501234 OTF = 0x1
3882 13:53:32.504498 ===================================
3883 13:53:32.511043 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3884 13:53:32.515264 nWR fixed to 30
3885 13:53:32.518846 [ModeRegInit_LP4] CH0 RK0
3886 13:53:32.518941 [ModeRegInit_LP4] CH0 RK1
3887 13:53:32.522327 [ModeRegInit_LP4] CH1 RK0
3888 13:53:32.525294 [ModeRegInit_LP4] CH1 RK1
3889 13:53:32.525387 match AC timing 17
3890 13:53:32.532397 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3891 13:53:32.535249 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3892 13:53:32.538915 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3893 13:53:32.545416 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3894 13:53:32.548921 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3895 13:53:32.549009 ==
3896 13:53:32.551814 Dram Type= 6, Freq= 0, CH_0, rank 0
3897 13:53:32.555381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3898 13:53:32.555493 ==
3899 13:53:32.561742 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3900 13:53:32.568634 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3901 13:53:32.571881 [CA 0] Center 35 (5~66) winsize 62
3902 13:53:32.575457 [CA 1] Center 35 (5~66) winsize 62
3903 13:53:32.578501 [CA 2] Center 33 (3~64) winsize 62
3904 13:53:32.581525 [CA 3] Center 33 (2~64) winsize 63
3905 13:53:32.585408 [CA 4] Center 33 (2~64) winsize 63
3906 13:53:32.588836 [CA 5] Center 32 (1~63) winsize 63
3907 13:53:32.588955
3908 13:53:32.592036 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3909 13:53:32.592120
3910 13:53:32.595089 [CATrainingPosCal] consider 1 rank data
3911 13:53:32.598157 u2DelayCellTimex100 = 270/100 ps
3912 13:53:32.601741 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3913 13:53:32.605026 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3914 13:53:32.608312 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3915 13:53:32.611641 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3916 13:53:32.615108 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3917 13:53:32.621334 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
3918 13:53:32.621441
3919 13:53:32.624906 CA PerBit enable=1, Macro0, CA PI delay=32
3920 13:53:32.625017
3921 13:53:32.628592 [CBTSetCACLKResult] CA Dly = 32
3922 13:53:32.628673 CS Dly: 4 (0~35)
3923 13:53:32.628761 ==
3924 13:53:32.631453 Dram Type= 6, Freq= 0, CH_0, rank 1
3925 13:53:32.635015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3926 13:53:32.637932 ==
3927 13:53:32.641458 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3928 13:53:32.647897 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3929 13:53:32.651284 [CA 0] Center 35 (5~66) winsize 62
3930 13:53:32.654752 [CA 1] Center 35 (5~66) winsize 62
3931 13:53:32.658289 [CA 2] Center 34 (3~65) winsize 63
3932 13:53:32.661123 [CA 3] Center 34 (3~65) winsize 63
3933 13:53:32.664575 [CA 4] Center 33 (2~64) winsize 63
3934 13:53:32.667970 [CA 5] Center 32 (2~63) winsize 62
3935 13:53:32.668048
3936 13:53:32.671402 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3937 13:53:32.671489
3938 13:53:32.675020 [CATrainingPosCal] consider 2 rank data
3939 13:53:32.677741 u2DelayCellTimex100 = 270/100 ps
3940 13:53:32.681502 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3941 13:53:32.684374 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3942 13:53:32.687838 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3943 13:53:32.694500 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3944 13:53:32.698034 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3945 13:53:32.701496 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3946 13:53:32.701586
3947 13:53:32.704306 CA PerBit enable=1, Macro0, CA PI delay=32
3948 13:53:32.704404
3949 13:53:32.707571 [CBTSetCACLKResult] CA Dly = 32
3950 13:53:32.707682 CS Dly: 5 (0~37)
3951 13:53:32.707773
3952 13:53:32.710868 ----->DramcWriteLeveling(PI) begin...
3953 13:53:32.710972 ==
3954 13:53:32.714663 Dram Type= 6, Freq= 0, CH_0, rank 0
3955 13:53:32.720745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3956 13:53:32.720860 ==
3957 13:53:32.724497 Write leveling (Byte 0): 35 => 35
3958 13:53:32.727499 Write leveling (Byte 1): 31 => 31
3959 13:53:32.727605 DramcWriteLeveling(PI) end<-----
3960 13:53:32.730979
3961 13:53:32.731087 ==
3962 13:53:32.734295 Dram Type= 6, Freq= 0, CH_0, rank 0
3963 13:53:32.737905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 13:53:32.737996 ==
3965 13:53:32.741316 [Gating] SW mode calibration
3966 13:53:32.747950 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3967 13:53:32.750867 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3968 13:53:32.758053 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3969 13:53:32.760707 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3970 13:53:32.764130 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3971 13:53:32.771156 0 9 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 1)
3972 13:53:32.774077 0 9 16 | B1->B0 | 3232 2323 | 1 0 | (0 1) (0 0)
3973 13:53:32.777476 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3974 13:53:32.784572 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 13:53:32.787328 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 13:53:32.791061 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 13:53:32.797983 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 13:53:32.800669 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 13:53:32.804030 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
3980 13:53:32.810889 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
3981 13:53:32.814321 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 13:53:32.817895 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 13:53:32.824167 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 13:53:32.827805 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 13:53:32.830626 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 13:53:32.837564 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 13:53:32.840895 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3988 13:53:32.844029 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 13:53:32.847493 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 13:53:32.853628 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 13:53:32.856976 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 13:53:32.863502 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 13:53:32.867263 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 13:53:32.870229 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 13:53:32.873672 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 13:53:32.880677 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 13:53:32.884174 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 13:53:32.887043 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 13:53:32.893465 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 13:53:32.897000 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 13:53:32.900711 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 13:53:32.907004 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 13:53:32.910294 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 13:53:32.913663 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4005 13:53:32.917214 Total UI for P1: 0, mck2ui 16
4006 13:53:32.919984 best dqsien dly found for B0: ( 0, 13, 14)
4007 13:53:32.926962 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 13:53:32.927074 Total UI for P1: 0, mck2ui 16
4009 13:53:32.933795 best dqsien dly found for B1: ( 0, 13, 18)
4010 13:53:32.936656 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4011 13:53:32.940172 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4012 13:53:32.940257
4013 13:53:32.943078 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4014 13:53:32.946927 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4015 13:53:32.949625 [Gating] SW calibration Done
4016 13:53:32.949761 ==
4017 13:53:32.953291 Dram Type= 6, Freq= 0, CH_0, rank 0
4018 13:53:32.956763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 13:53:32.956871 ==
4020 13:53:32.959627 RX Vref Scan: 0
4021 13:53:32.959756
4022 13:53:32.959869 RX Vref 0 -> 0, step: 1
4023 13:53:32.962941
4024 13:53:32.963044 RX Delay -230 -> 252, step: 16
4025 13:53:32.969931 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4026 13:53:32.973385 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4027 13:53:32.976601 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4028 13:53:32.979682 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4029 13:53:32.986788 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4030 13:53:32.989805 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4031 13:53:32.992910 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4032 13:53:32.996221 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4033 13:53:32.999782 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4034 13:53:33.006332 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4035 13:53:33.009806 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4036 13:53:33.013107 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4037 13:53:33.016625 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4038 13:53:33.022770 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4039 13:53:33.026319 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4040 13:53:33.030004 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4041 13:53:33.030096 ==
4042 13:53:33.032849 Dram Type= 6, Freq= 0, CH_0, rank 0
4043 13:53:33.036258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 13:53:33.039973 ==
4045 13:53:33.040081 DQS Delay:
4046 13:53:33.040149 DQS0 = 0, DQS1 = 0
4047 13:53:33.042632 DQM Delay:
4048 13:53:33.042718 DQM0 = 52, DQM1 = 49
4049 13:53:33.046354 DQ Delay:
4050 13:53:33.046455 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4051 13:53:33.050012 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4052 13:53:33.053008 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4053 13:53:33.056451 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4054 13:53:33.056557
4055 13:53:33.059343
4056 13:53:33.059447 ==
4057 13:53:33.063020 Dram Type= 6, Freq= 0, CH_0, rank 0
4058 13:53:33.066389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4059 13:53:33.066495 ==
4060 13:53:33.066592
4061 13:53:33.066686
4062 13:53:33.069229 TX Vref Scan disable
4063 13:53:33.069313 == TX Byte 0 ==
4064 13:53:33.076326 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4065 13:53:33.079226 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4066 13:53:33.079319 == TX Byte 1 ==
4067 13:53:33.086292 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4068 13:53:33.089923 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4069 13:53:33.090025 ==
4070 13:53:33.092508 Dram Type= 6, Freq= 0, CH_0, rank 0
4071 13:53:33.095949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4072 13:53:33.096044 ==
4073 13:53:33.096113
4074 13:53:33.096174
4075 13:53:33.099556 TX Vref Scan disable
4076 13:53:33.103017 == TX Byte 0 ==
4077 13:53:33.106166 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4078 13:53:33.109462 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4079 13:53:33.112571 == TX Byte 1 ==
4080 13:53:33.116258 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4081 13:53:33.119386 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4082 13:53:33.119487
4083 13:53:33.122956 [DATLAT]
4084 13:53:33.123059 Freq=600, CH0 RK0
4085 13:53:33.123142
4086 13:53:33.125962 DATLAT Default: 0x9
4087 13:53:33.126049 0, 0xFFFF, sum = 0
4088 13:53:33.129332 1, 0xFFFF, sum = 0
4089 13:53:33.129423 2, 0xFFFF, sum = 0
4090 13:53:33.132511 3, 0xFFFF, sum = 0
4091 13:53:33.132634 4, 0xFFFF, sum = 0
4092 13:53:33.136382 5, 0xFFFF, sum = 0
4093 13:53:33.136532 6, 0xFFFF, sum = 0
4094 13:53:33.139043 7, 0xFFFF, sum = 0
4095 13:53:33.139141 8, 0x0, sum = 1
4096 13:53:33.142919 9, 0x0, sum = 2
4097 13:53:33.143054 10, 0x0, sum = 3
4098 13:53:33.146077 11, 0x0, sum = 4
4099 13:53:33.146188 best_step = 9
4100 13:53:33.146255
4101 13:53:33.146314 ==
4102 13:53:33.149485 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 13:53:33.156105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 13:53:33.156254 ==
4105 13:53:33.156382 RX Vref Scan: 1
4106 13:53:33.156478
4107 13:53:33.159074 RX Vref 0 -> 0, step: 1
4108 13:53:33.159197
4109 13:53:33.162735 RX Delay -147 -> 252, step: 8
4110 13:53:33.162878
4111 13:53:33.165527 Set Vref, RX VrefLevel [Byte0]: 56
4112 13:53:33.168997 [Byte1]: 49
4113 13:53:33.169106
4114 13:53:33.172440 Final RX Vref Byte 0 = 56 to rank0
4115 13:53:33.175323 Final RX Vref Byte 1 = 49 to rank0
4116 13:53:33.178782 Final RX Vref Byte 0 = 56 to rank1
4117 13:53:33.182356 Final RX Vref Byte 1 = 49 to rank1==
4118 13:53:33.185285 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 13:53:33.188860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 13:53:33.188986 ==
4121 13:53:33.192230 DQS Delay:
4122 13:53:33.192336 DQS0 = 0, DQS1 = 0
4123 13:53:33.192415 DQM Delay:
4124 13:53:33.195768 DQM0 = 53, DQM1 = 48
4125 13:53:33.195883 DQ Delay:
4126 13:53:33.198643 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4127 13:53:33.202268 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4128 13:53:33.205868 DQ8 =36, DQ9 =40, DQ10 =48, DQ11 =40
4129 13:53:33.208609 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =56
4130 13:53:33.208709
4131 13:53:33.208800
4132 13:53:33.218463 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f62, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4133 13:53:33.218627 CH0 RK0: MR19=808, MR18=6F62
4134 13:53:33.225511 CH0_RK0: MR19=0x808, MR18=0x6F62, DQSOSC=389, MR23=63, INC=173, DEC=115
4135 13:53:33.225662
4136 13:53:33.228500 ----->DramcWriteLeveling(PI) begin...
4137 13:53:33.232140 ==
4138 13:53:33.232290 Dram Type= 6, Freq= 0, CH_0, rank 1
4139 13:53:33.238774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 13:53:33.238922 ==
4141 13:53:33.242039 Write leveling (Byte 0): 34 => 34
4142 13:53:33.245255 Write leveling (Byte 1): 31 => 31
4143 13:53:33.248300 DramcWriteLeveling(PI) end<-----
4144 13:53:33.248439
4145 13:53:33.248537 ==
4146 13:53:33.251982 Dram Type= 6, Freq= 0, CH_0, rank 1
4147 13:53:33.255366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 13:53:33.255509 ==
4149 13:53:33.258617 [Gating] SW mode calibration
4150 13:53:33.265392 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4151 13:53:33.268399 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4152 13:53:33.275432 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4153 13:53:33.278897 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4154 13:53:33.281879 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4155 13:53:33.288593 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4156 13:53:33.292250 0 9 16 | B1->B0 | 2f2f 2b2b | 0 0 | (0 0) (0 0)
4157 13:53:33.295048 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4158 13:53:33.301982 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4159 13:53:33.305317 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 13:53:33.308221 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 13:53:33.315344 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 13:53:33.318050 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 13:53:33.321590 0 10 12 | B1->B0 | 2525 2828 | 0 0 | (0 0) (1 1)
4164 13:53:33.328544 0 10 16 | B1->B0 | 3f3f 4242 | 0 1 | (0 0) (0 0)
4165 13:53:33.331362 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4166 13:53:33.334895 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 13:53:33.341682 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 13:53:33.344620 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 13:53:33.348083 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 13:53:33.354456 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4171 13:53:33.358016 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 13:53:33.361201 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 13:53:33.367719 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 13:53:33.371150 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 13:53:33.374570 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 13:53:33.381233 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 13:53:33.384779 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 13:53:33.387479 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 13:53:33.394528 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 13:53:33.397645 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 13:53:33.400835 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 13:53:33.407769 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 13:53:33.411282 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 13:53:33.414130 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 13:53:33.421074 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 13:53:33.424499 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 13:53:33.427439 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4188 13:53:33.434526 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4189 13:53:33.434691 Total UI for P1: 0, mck2ui 16
4190 13:53:33.437430 best dqsien dly found for B0: ( 0, 13, 12)
4191 13:53:33.444439 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 13:53:33.447974 Total UI for P1: 0, mck2ui 16
4193 13:53:33.450853 best dqsien dly found for B1: ( 0, 13, 16)
4194 13:53:33.454425 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4195 13:53:33.457390 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4196 13:53:33.457480
4197 13:53:33.461012 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4198 13:53:33.463979 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4199 13:53:33.467372 [Gating] SW calibration Done
4200 13:53:33.467460 ==
4201 13:53:33.470900 Dram Type= 6, Freq= 0, CH_0, rank 1
4202 13:53:33.474321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 13:53:33.474414 ==
4204 13:53:33.477649 RX Vref Scan: 0
4205 13:53:33.477739
4206 13:53:33.481166 RX Vref 0 -> 0, step: 1
4207 13:53:33.481262
4208 13:53:33.481329 RX Delay -230 -> 252, step: 16
4209 13:53:33.487907 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4210 13:53:33.491347 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4211 13:53:33.494291 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4212 13:53:33.497810 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4213 13:53:33.503953 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4214 13:53:33.507199 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4215 13:53:33.510713 iDelay=218, Bit 6, Center 73 (-70 ~ 217) 288
4216 13:53:33.514167 iDelay=218, Bit 7, Center 73 (-70 ~ 217) 288
4217 13:53:33.517552 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4218 13:53:33.523941 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4219 13:53:33.527416 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4220 13:53:33.530591 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4221 13:53:33.534170 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4222 13:53:33.540436 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4223 13:53:33.543880 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4224 13:53:33.547927 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4225 13:53:33.548046 ==
4226 13:53:33.550817 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 13:53:33.553622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 13:53:33.557296 ==
4229 13:53:33.557395 DQS Delay:
4230 13:53:33.557463 DQS0 = 0, DQS1 = 0
4231 13:53:33.560820 DQM Delay:
4232 13:53:33.560911 DQM0 = 54, DQM1 = 43
4233 13:53:33.563731 DQ Delay:
4234 13:53:33.563849 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4235 13:53:33.567209 DQ4 =49, DQ5 =41, DQ6 =73, DQ7 =73
4236 13:53:33.570077 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4237 13:53:33.573433 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4238 13:53:33.573549
4239 13:53:33.576891
4240 13:53:33.576994 ==
4241 13:53:33.580459 Dram Type= 6, Freq= 0, CH_0, rank 1
4242 13:53:33.583890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 13:53:33.583989 ==
4244 13:53:33.584056
4245 13:53:33.584116
4246 13:53:33.586860 TX Vref Scan disable
4247 13:53:33.586951 == TX Byte 0 ==
4248 13:53:33.593552 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4249 13:53:33.596973 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4250 13:53:33.597076 == TX Byte 1 ==
4251 13:53:33.603650 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4252 13:53:33.607156 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4253 13:53:33.607268 ==
4254 13:53:33.609846 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 13:53:33.613227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 13:53:33.613313 ==
4257 13:53:33.613378
4258 13:53:33.613439
4259 13:53:33.616936 TX Vref Scan disable
4260 13:53:33.619771 == TX Byte 0 ==
4261 13:53:33.623225 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4262 13:53:33.626602 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4263 13:53:33.630280 == TX Byte 1 ==
4264 13:53:33.633115 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4265 13:53:33.636560 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4266 13:53:33.640046
4267 13:53:33.640135 [DATLAT]
4268 13:53:33.640236 Freq=600, CH0 RK1
4269 13:53:33.640348
4270 13:53:33.643486 DATLAT Default: 0x9
4271 13:53:33.643573 0, 0xFFFF, sum = 0
4272 13:53:33.646758 1, 0xFFFF, sum = 0
4273 13:53:33.646848 2, 0xFFFF, sum = 0
4274 13:53:33.649973 3, 0xFFFF, sum = 0
4275 13:53:33.650062 4, 0xFFFF, sum = 0
4276 13:53:33.653131 5, 0xFFFF, sum = 0
4277 13:53:33.656780 6, 0xFFFF, sum = 0
4278 13:53:33.656875 7, 0xFFFF, sum = 0
4279 13:53:33.656944 8, 0x0, sum = 1
4280 13:53:33.659833 9, 0x0, sum = 2
4281 13:53:33.659920 10, 0x0, sum = 3
4282 13:53:33.663396 11, 0x0, sum = 4
4283 13:53:33.663485 best_step = 9
4284 13:53:33.663552
4285 13:53:33.663613 ==
4286 13:53:33.666276 Dram Type= 6, Freq= 0, CH_0, rank 1
4287 13:53:33.673412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4288 13:53:33.673571 ==
4289 13:53:33.673669 RX Vref Scan: 0
4290 13:53:33.673780
4291 13:53:33.676168 RX Vref 0 -> 0, step: 1
4292 13:53:33.676286
4293 13:53:33.679607 RX Delay -163 -> 252, step: 8
4294 13:53:33.683109 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4295 13:53:33.686837 iDelay=197, Bit 1, Center 52 (-91 ~ 196) 288
4296 13:53:33.693168 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4297 13:53:33.696292 iDelay=197, Bit 3, Center 48 (-99 ~ 196) 296
4298 13:53:33.700191 iDelay=197, Bit 4, Center 52 (-91 ~ 196) 288
4299 13:53:33.703050 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4300 13:53:33.706315 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4301 13:53:33.713383 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4302 13:53:33.716983 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4303 13:53:33.720274 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4304 13:53:33.723627 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4305 13:53:33.726432 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4306 13:53:33.732972 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4307 13:53:33.736668 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4308 13:53:33.740117 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4309 13:53:33.743559 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4310 13:53:33.743683 ==
4311 13:53:33.746546 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 13:53:33.753627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 13:53:33.753729 ==
4314 13:53:33.753810 DQS Delay:
4315 13:53:33.756432 DQS0 = 0, DQS1 = 0
4316 13:53:33.756534 DQM Delay:
4317 13:53:33.756597 DQM0 = 51, DQM1 = 46
4318 13:53:33.759944 DQ Delay:
4319 13:53:33.763291 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =48
4320 13:53:33.766718 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =56
4321 13:53:33.769565 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4322 13:53:33.773009 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4323 13:53:33.773098
4324 13:53:33.773163
4325 13:53:33.780126 [DQSOSCAuto] RK1, (LSB)MR18= 0x6829, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4326 13:53:33.783229 CH0 RK1: MR19=808, MR18=6829
4327 13:53:33.790075 CH0_RK1: MR19=0x808, MR18=0x6829, DQSOSC=390, MR23=63, INC=172, DEC=114
4328 13:53:33.792939 [RxdqsGatingPostProcess] freq 600
4329 13:53:33.796581 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4330 13:53:33.799971 Pre-setting of DQS Precalculation
4331 13:53:33.806500 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4332 13:53:33.806592 ==
4333 13:53:33.809854 Dram Type= 6, Freq= 0, CH_1, rank 0
4334 13:53:33.813174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 13:53:33.813266 ==
4336 13:53:33.819551 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4337 13:53:33.823223 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4338 13:53:33.827375 [CA 0] Center 36 (5~67) winsize 63
4339 13:53:33.830899 [CA 1] Center 36 (5~67) winsize 63
4340 13:53:33.834311 [CA 2] Center 34 (4~65) winsize 62
4341 13:53:33.837927 [CA 3] Center 34 (4~65) winsize 62
4342 13:53:33.840770 [CA 4] Center 34 (4~65) winsize 62
4343 13:53:33.844350 [CA 5] Center 33 (3~64) winsize 62
4344 13:53:33.844438
4345 13:53:33.847228 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4346 13:53:33.847313
4347 13:53:33.850757 [CATrainingPosCal] consider 1 rank data
4348 13:53:33.854355 u2DelayCellTimex100 = 270/100 ps
4349 13:53:33.857132 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4350 13:53:33.864275 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4351 13:53:33.867183 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4352 13:53:33.870502 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4353 13:53:33.874010 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4354 13:53:33.877614 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4355 13:53:33.877691
4356 13:53:33.880468 CA PerBit enable=1, Macro0, CA PI delay=33
4357 13:53:33.880545
4358 13:53:33.883944 [CBTSetCACLKResult] CA Dly = 33
4359 13:53:33.884053 CS Dly: 5 (0~36)
4360 13:53:33.887348 ==
4361 13:53:33.890695 Dram Type= 6, Freq= 0, CH_1, rank 1
4362 13:53:33.894213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 13:53:33.894297 ==
4364 13:53:33.897074 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4365 13:53:33.903886 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4366 13:53:33.907511 [CA 0] Center 36 (5~67) winsize 63
4367 13:53:33.911192 [CA 1] Center 36 (5~67) winsize 63
4368 13:53:33.914290 [CA 2] Center 34 (4~65) winsize 62
4369 13:53:33.917717 [CA 3] Center 34 (4~65) winsize 62
4370 13:53:33.921195 [CA 4] Center 34 (4~65) winsize 62
4371 13:53:33.924320 [CA 5] Center 34 (3~65) winsize 63
4372 13:53:33.924455
4373 13:53:33.927494 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4374 13:53:33.927616
4375 13:53:33.931179 [CATrainingPosCal] consider 2 rank data
4376 13:53:33.934575 u2DelayCellTimex100 = 270/100 ps
4377 13:53:33.937764 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4378 13:53:33.940758 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4379 13:53:33.947657 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4380 13:53:33.950443 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4381 13:53:33.953977 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4382 13:53:33.957531 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4383 13:53:33.957636
4384 13:53:33.960351 CA PerBit enable=1, Macro0, CA PI delay=33
4385 13:53:33.960452
4386 13:53:33.964087 [CBTSetCACLKResult] CA Dly = 33
4387 13:53:33.964205 CS Dly: 6 (0~39)
4388 13:53:33.966901
4389 13:53:33.970316 ----->DramcWriteLeveling(PI) begin...
4390 13:53:33.970432 ==
4391 13:53:33.973732 Dram Type= 6, Freq= 0, CH_1, rank 0
4392 13:53:33.977088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4393 13:53:33.977196 ==
4394 13:53:33.980409 Write leveling (Byte 0): 31 => 31
4395 13:53:33.983248 Write leveling (Byte 1): 30 => 30
4396 13:53:33.986891 DramcWriteLeveling(PI) end<-----
4397 13:53:33.986997
4398 13:53:33.987092 ==
4399 13:53:33.990333 Dram Type= 6, Freq= 0, CH_1, rank 0
4400 13:53:33.993735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 13:53:33.993839 ==
4402 13:53:33.996563 [Gating] SW mode calibration
4403 13:53:34.003750 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4404 13:53:34.010323 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4405 13:53:34.013743 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4406 13:53:34.016636 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4407 13:53:34.023642 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4408 13:53:34.027122 0 9 12 | B1->B0 | 3232 2d2d | 1 0 | (1 1) (1 0)
4409 13:53:34.029942 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 13:53:34.037030 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 13:53:34.040084 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 13:53:34.043575 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 13:53:34.049901 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 13:53:34.052916 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 13:53:34.056491 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 13:53:34.063195 0 10 12 | B1->B0 | 3535 3838 | 0 1 | (0 0) (0 0)
4417 13:53:34.066256 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 13:53:34.069651 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 13:53:34.076440 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 13:53:34.079841 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 13:53:34.083350 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 13:53:34.086201 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 13:53:34.093411 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 13:53:34.096261 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 13:53:34.099789 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 13:53:34.106200 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 13:53:34.109772 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 13:53:34.113277 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 13:53:34.119635 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 13:53:34.122946 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 13:53:34.126511 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 13:53:34.132814 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 13:53:34.136362 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 13:53:34.139976 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 13:53:34.146361 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 13:53:34.149822 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 13:53:34.152931 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 13:53:34.159375 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 13:53:34.162758 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4440 13:53:34.166127 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4441 13:53:34.169660 Total UI for P1: 0, mck2ui 16
4442 13:53:34.172549 best dqsien dly found for B0: ( 0, 13, 8)
4443 13:53:34.179252 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 13:53:34.179386 Total UI for P1: 0, mck2ui 16
4445 13:53:34.186354 best dqsien dly found for B1: ( 0, 13, 12)
4446 13:53:34.189099 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4447 13:53:34.192747 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4448 13:53:34.192865
4449 13:53:34.196043 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4450 13:53:34.199458 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4451 13:53:34.202467 [Gating] SW calibration Done
4452 13:53:34.202563 ==
4453 13:53:34.205850 Dram Type= 6, Freq= 0, CH_1, rank 0
4454 13:53:34.209184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4455 13:53:34.209282 ==
4456 13:53:34.212560 RX Vref Scan: 0
4457 13:53:34.212703
4458 13:53:34.212802 RX Vref 0 -> 0, step: 1
4459 13:53:34.212899
4460 13:53:34.216122 RX Delay -230 -> 252, step: 16
4461 13:53:34.222485 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4462 13:53:34.225895 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4463 13:53:34.229462 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4464 13:53:34.232285 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4465 13:53:34.235814 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4466 13:53:34.242300 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4467 13:53:34.245833 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4468 13:53:34.248746 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4469 13:53:34.252179 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4470 13:53:34.255736 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4471 13:53:34.262538 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4472 13:53:34.266020 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4473 13:53:34.269252 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4474 13:53:34.272526 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4475 13:53:34.279042 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4476 13:53:34.282414 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4477 13:53:34.282506 ==
4478 13:53:34.285946 Dram Type= 6, Freq= 0, CH_1, rank 0
4479 13:53:34.288837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4480 13:53:34.288925 ==
4481 13:53:34.292322 DQS Delay:
4482 13:53:34.292418 DQS0 = 0, DQS1 = 0
4483 13:53:34.295824 DQM Delay:
4484 13:53:34.295915 DQM0 = 47, DQM1 = 46
4485 13:53:34.295981 DQ Delay:
4486 13:53:34.299236 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4487 13:53:34.302050 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4488 13:53:34.305789 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4489 13:53:34.308590 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4490 13:53:34.308702
4491 13:53:34.308797
4492 13:53:34.308866 ==
4493 13:53:34.312073 Dram Type= 6, Freq= 0, CH_1, rank 0
4494 13:53:34.318571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4495 13:53:34.318659 ==
4496 13:53:34.318724
4497 13:53:34.318784
4498 13:53:34.322340 TX Vref Scan disable
4499 13:53:34.322424 == TX Byte 0 ==
4500 13:53:34.325233 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4501 13:53:34.331809 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4502 13:53:34.331898 == TX Byte 1 ==
4503 13:53:34.335177 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4504 13:53:34.341864 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4505 13:53:34.342009 ==
4506 13:53:34.345458 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 13:53:34.348320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 13:53:34.348434 ==
4509 13:53:34.348549
4510 13:53:34.348640
4511 13:53:34.351961 TX Vref Scan disable
4512 13:53:34.354911 == TX Byte 0 ==
4513 13:53:34.358400 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4514 13:53:34.361774 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4515 13:53:34.365391 == TX Byte 1 ==
4516 13:53:34.368869 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4517 13:53:34.371637 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4518 13:53:34.371725
4519 13:53:34.375066 [DATLAT]
4520 13:53:34.375191 Freq=600, CH1 RK0
4521 13:53:34.375287
4522 13:53:34.378618 DATLAT Default: 0x9
4523 13:53:34.378722 0, 0xFFFF, sum = 0
4524 13:53:34.381988 1, 0xFFFF, sum = 0
4525 13:53:34.382074 2, 0xFFFF, sum = 0
4526 13:53:34.385466 3, 0xFFFF, sum = 0
4527 13:53:34.385555 4, 0xFFFF, sum = 0
4528 13:53:34.388749 5, 0xFFFF, sum = 0
4529 13:53:34.388837 6, 0xFFFF, sum = 0
4530 13:53:34.392059 7, 0xFFFF, sum = 0
4531 13:53:34.392170 8, 0x0, sum = 1
4532 13:53:34.394963 9, 0x0, sum = 2
4533 13:53:34.395074 10, 0x0, sum = 3
4534 13:53:34.398517 11, 0x0, sum = 4
4535 13:53:34.398595 best_step = 9
4536 13:53:34.398657
4537 13:53:34.398715 ==
4538 13:53:34.401970 Dram Type= 6, Freq= 0, CH_1, rank 0
4539 13:53:34.405240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4540 13:53:34.405326 ==
4541 13:53:34.408077 RX Vref Scan: 1
4542 13:53:34.408192
4543 13:53:34.411600 RX Vref 0 -> 0, step: 1
4544 13:53:34.411687
4545 13:53:34.411751 RX Delay -163 -> 252, step: 8
4546 13:53:34.415046
4547 13:53:34.415151 Set Vref, RX VrefLevel [Byte0]: 53
4548 13:53:34.417977 [Byte1]: 48
4549 13:53:34.423479
4550 13:53:34.423611 Final RX Vref Byte 0 = 53 to rank0
4551 13:53:34.426285 Final RX Vref Byte 1 = 48 to rank0
4552 13:53:34.429732 Final RX Vref Byte 0 = 53 to rank1
4553 13:53:34.433130 Final RX Vref Byte 1 = 48 to rank1==
4554 13:53:34.436600 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 13:53:34.443070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 13:53:34.443210 ==
4557 13:53:34.443305 DQS Delay:
4558 13:53:34.443406 DQS0 = 0, DQS1 = 0
4559 13:53:34.446392 DQM Delay:
4560 13:53:34.446511 DQM0 = 48, DQM1 = 45
4561 13:53:34.449778 DQ Delay:
4562 13:53:34.452964 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4563 13:53:34.453047 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4564 13:53:34.456486 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4565 13:53:34.463005 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4566 13:53:34.463132
4567 13:53:34.463228
4568 13:53:34.469617 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c71, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4569 13:53:34.473181 CH1 RK0: MR19=808, MR18=4C71
4570 13:53:34.479647 CH1_RK0: MR19=0x808, MR18=0x4C71, DQSOSC=388, MR23=63, INC=174, DEC=116
4571 13:53:34.479744
4572 13:53:34.483076 ----->DramcWriteLeveling(PI) begin...
4573 13:53:34.483187 ==
4574 13:53:34.486001 Dram Type= 6, Freq= 0, CH_1, rank 1
4575 13:53:34.489418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 13:53:34.489516 ==
4577 13:53:34.492977 Write leveling (Byte 0): 30 => 30
4578 13:53:34.496465 Write leveling (Byte 1): 31 => 31
4579 13:53:34.499329 DramcWriteLeveling(PI) end<-----
4580 13:53:34.499447
4581 13:53:34.499543 ==
4582 13:53:34.503048 Dram Type= 6, Freq= 0, CH_1, rank 1
4583 13:53:34.506558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 13:53:34.506661 ==
4585 13:53:34.510101 [Gating] SW mode calibration
4586 13:53:34.516520 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4587 13:53:34.523180 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4588 13:53:34.526109 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4589 13:53:34.529518 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4590 13:53:34.536135 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4591 13:53:34.539667 0 9 12 | B1->B0 | 2c2c 2f2f | 0 0 | (0 1) (0 1)
4592 13:53:34.542592 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4593 13:53:34.549707 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4594 13:53:34.552569 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 13:53:34.555691 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 13:53:34.562933 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 13:53:34.565758 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 13:53:34.569504 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4599 13:53:34.575629 0 10 12 | B1->B0 | 3939 3838 | 0 0 | (0 0) (0 0)
4600 13:53:34.579344 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 13:53:34.582445 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4602 13:53:34.589447 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 13:53:34.592254 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 13:53:34.595817 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 13:53:34.602322 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 13:53:34.605733 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 13:53:34.609084 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 13:53:34.615634 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 13:53:34.619357 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 13:53:34.622774 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 13:53:34.629382 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 13:53:34.632190 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 13:53:34.635805 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 13:53:34.642299 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 13:53:34.645864 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 13:53:34.648753 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 13:53:34.655159 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 13:53:34.658936 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 13:53:34.662675 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 13:53:34.668427 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 13:53:34.672024 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 13:53:34.675663 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4623 13:53:34.681851 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4624 13:53:34.681939 Total UI for P1: 0, mck2ui 16
4625 13:53:34.685056 best dqsien dly found for B1: ( 0, 13, 8)
4626 13:53:34.691858 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 13:53:34.695462 Total UI for P1: 0, mck2ui 16
4628 13:53:34.698230 best dqsien dly found for B0: ( 0, 13, 12)
4629 13:53:34.701865 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4630 13:53:34.705253 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4631 13:53:34.705370
4632 13:53:34.708647 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4633 13:53:34.711941 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4634 13:53:34.714889 [Gating] SW calibration Done
4635 13:53:34.714996 ==
4636 13:53:34.717920 Dram Type= 6, Freq= 0, CH_1, rank 1
4637 13:53:34.721247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 13:53:34.721374 ==
4639 13:53:34.724971 RX Vref Scan: 0
4640 13:53:34.725095
4641 13:53:34.728288 RX Vref 0 -> 0, step: 1
4642 13:53:34.728412
4643 13:53:34.728509 RX Delay -230 -> 252, step: 16
4644 13:53:34.735378 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4645 13:53:34.738348 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4646 13:53:34.741487 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4647 13:53:34.744722 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4648 13:53:34.751935 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4649 13:53:34.754825 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4650 13:53:34.758296 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4651 13:53:34.761296 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4652 13:53:34.764904 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4653 13:53:34.771480 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4654 13:53:34.775012 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4655 13:53:34.777969 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4656 13:53:34.781591 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4657 13:53:34.788101 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4658 13:53:34.791543 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4659 13:53:34.794948 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4660 13:53:34.795058 ==
4661 13:53:34.798090 Dram Type= 6, Freq= 0, CH_1, rank 1
4662 13:53:34.801322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4663 13:53:34.804804 ==
4664 13:53:34.804915 DQS Delay:
4665 13:53:34.804984 DQS0 = 0, DQS1 = 0
4666 13:53:34.807634 DQM Delay:
4667 13:53:34.807746 DQM0 = 48, DQM1 = 46
4668 13:53:34.811421 DQ Delay:
4669 13:53:34.811529 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4670 13:53:34.814320 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4671 13:53:34.817901 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4672 13:53:34.821398 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4673 13:53:34.824825
4674 13:53:34.824953
4675 13:53:34.825045 ==
4676 13:53:34.828010 Dram Type= 6, Freq= 0, CH_1, rank 1
4677 13:53:34.831029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4678 13:53:34.831147 ==
4679 13:53:34.831248
4680 13:53:34.831354
4681 13:53:34.834347 TX Vref Scan disable
4682 13:53:34.834458 == TX Byte 0 ==
4683 13:53:34.841233 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4684 13:53:34.844746 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4685 13:53:34.844874 == TX Byte 1 ==
4686 13:53:34.850850 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4687 13:53:34.854318 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4688 13:53:34.854435 ==
4689 13:53:34.857665 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 13:53:34.861282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 13:53:34.861401 ==
4692 13:53:34.861523
4693 13:53:34.861630
4694 13:53:34.864590 TX Vref Scan disable
4695 13:53:34.867906 == TX Byte 0 ==
4696 13:53:34.871125 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4697 13:53:34.874643 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4698 13:53:34.877561 == TX Byte 1 ==
4699 13:53:34.881226 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4700 13:53:34.884017 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4701 13:53:34.887721
4702 13:53:34.887837 [DATLAT]
4703 13:53:34.887938 Freq=600, CH1 RK1
4704 13:53:34.888036
4705 13:53:34.890602 DATLAT Default: 0x9
4706 13:53:34.890713 0, 0xFFFF, sum = 0
4707 13:53:34.894149 1, 0xFFFF, sum = 0
4708 13:53:34.894257 2, 0xFFFF, sum = 0
4709 13:53:34.897665 3, 0xFFFF, sum = 0
4710 13:53:34.897771 4, 0xFFFF, sum = 0
4711 13:53:34.900619 5, 0xFFFF, sum = 0
4712 13:53:34.904262 6, 0xFFFF, sum = 0
4713 13:53:34.904386 7, 0xFFFF, sum = 0
4714 13:53:34.904492 8, 0x0, sum = 1
4715 13:53:34.907614 9, 0x0, sum = 2
4716 13:53:34.907725 10, 0x0, sum = 3
4717 13:53:34.910848 11, 0x0, sum = 4
4718 13:53:34.910957 best_step = 9
4719 13:53:34.911048
4720 13:53:34.911146 ==
4721 13:53:34.913967 Dram Type= 6, Freq= 0, CH_1, rank 1
4722 13:53:34.920336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4723 13:53:34.920483 ==
4724 13:53:34.920591 RX Vref Scan: 0
4725 13:53:34.920684
4726 13:53:34.923882 RX Vref 0 -> 0, step: 1
4727 13:53:34.924014
4728 13:53:34.927662 RX Delay -163 -> 252, step: 8
4729 13:53:34.930618 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4730 13:53:34.934289 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4731 13:53:34.940891 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4732 13:53:34.944000 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4733 13:53:34.947054 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4734 13:53:34.950929 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4735 13:53:34.953967 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4736 13:53:34.960751 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4737 13:53:34.964191 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4738 13:53:34.966959 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4739 13:53:34.970521 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4740 13:53:34.977389 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4741 13:53:34.980207 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4742 13:53:34.983966 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4743 13:53:34.987244 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4744 13:53:34.990335 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4745 13:53:34.993762 ==
4746 13:53:34.996758 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 13:53:35.000269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 13:53:35.000389 ==
4749 13:53:35.000484 DQS Delay:
4750 13:53:35.003957 DQS0 = 0, DQS1 = 0
4751 13:53:35.004059 DQM Delay:
4752 13:53:35.006998 DQM0 = 48, DQM1 = 44
4753 13:53:35.007082 DQ Delay:
4754 13:53:35.010457 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4755 13:53:35.014170 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =48
4756 13:53:35.016943 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =36
4757 13:53:35.020357 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4758 13:53:35.020489
4759 13:53:35.020584
4760 13:53:35.026871 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4761 13:53:35.030303 CH1 RK1: MR19=808, MR18=6B21
4762 13:53:35.036897 CH1_RK1: MR19=0x808, MR18=0x6B21, DQSOSC=389, MR23=63, INC=173, DEC=115
4763 13:53:35.040583 [RxdqsGatingPostProcess] freq 600
4764 13:53:35.046997 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4765 13:53:35.047124 Pre-setting of DQS Precalculation
4766 13:53:35.053189 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4767 13:53:35.060452 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4768 13:53:35.066996 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4769 13:53:35.067128
4770 13:53:35.067225
4771 13:53:35.070283 [Calibration Summary] 1200 Mbps
4772 13:53:35.073374 CH 0, Rank 0
4773 13:53:35.073481 SW Impedance : PASS
4774 13:53:35.076997 DUTY Scan : NO K
4775 13:53:35.077105 ZQ Calibration : PASS
4776 13:53:35.080492 Jitter Meter : NO K
4777 13:53:35.083639 CBT Training : PASS
4778 13:53:35.083751 Write leveling : PASS
4779 13:53:35.086696 RX DQS gating : PASS
4780 13:53:35.090261 RX DQ/DQS(RDDQC) : PASS
4781 13:53:35.090369 TX DQ/DQS : PASS
4782 13:53:35.093682 RX DATLAT : PASS
4783 13:53:35.096986 RX DQ/DQS(Engine): PASS
4784 13:53:35.097088 TX OE : NO K
4785 13:53:35.099747 All Pass.
4786 13:53:35.099861
4787 13:53:35.099954 CH 0, Rank 1
4788 13:53:35.103001 SW Impedance : PASS
4789 13:53:35.103104 DUTY Scan : NO K
4790 13:53:35.106316 ZQ Calibration : PASS
4791 13:53:35.109767 Jitter Meter : NO K
4792 13:53:35.109875 CBT Training : PASS
4793 13:53:35.113076 Write leveling : PASS
4794 13:53:35.116466 RX DQS gating : PASS
4795 13:53:35.116580 RX DQ/DQS(RDDQC) : PASS
4796 13:53:35.120117 TX DQ/DQS : PASS
4797 13:53:35.122888 RX DATLAT : PASS
4798 13:53:35.122990 RX DQ/DQS(Engine): PASS
4799 13:53:35.126509 TX OE : NO K
4800 13:53:35.126623 All Pass.
4801 13:53:35.126727
4802 13:53:35.130081 CH 1, Rank 0
4803 13:53:35.130188 SW Impedance : PASS
4804 13:53:35.133599 DUTY Scan : NO K
4805 13:53:35.133717 ZQ Calibration : PASS
4806 13:53:35.136310 Jitter Meter : NO K
4807 13:53:35.140089 CBT Training : PASS
4808 13:53:35.140219 Write leveling : PASS
4809 13:53:35.143063 RX DQS gating : PASS
4810 13:53:35.146846 RX DQ/DQS(RDDQC) : PASS
4811 13:53:35.146963 TX DQ/DQS : PASS
4812 13:53:35.150396 RX DATLAT : PASS
4813 13:53:35.153190 RX DQ/DQS(Engine): PASS
4814 13:53:35.153301 TX OE : NO K
4815 13:53:35.156773 All Pass.
4816 13:53:35.156886
4817 13:53:35.156979 CH 1, Rank 1
4818 13:53:35.160304 SW Impedance : PASS
4819 13:53:35.160405 DUTY Scan : NO K
4820 13:53:35.163636 ZQ Calibration : PASS
4821 13:53:35.166400 Jitter Meter : NO K
4822 13:53:35.166517 CBT Training : PASS
4823 13:53:35.170125 Write leveling : PASS
4824 13:53:35.170236 RX DQS gating : PASS
4825 13:53:35.173054 RX DQ/DQS(RDDQC) : PASS
4826 13:53:35.176557 TX DQ/DQS : PASS
4827 13:53:35.176685 RX DATLAT : PASS
4828 13:53:35.180092 RX DQ/DQS(Engine): PASS
4829 13:53:35.183564 TX OE : NO K
4830 13:53:35.183677 All Pass.
4831 13:53:35.183781
4832 13:53:35.186576 DramC Write-DBI off
4833 13:53:35.186692 PER_BANK_REFRESH: Hybrid Mode
4834 13:53:35.189780 TX_TRACKING: ON
4835 13:53:35.196658 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4836 13:53:35.203087 [FAST_K] Save calibration result to emmc
4837 13:53:35.206624 dramc_set_vcore_voltage set vcore to 662500
4838 13:53:35.206743 Read voltage for 933, 3
4839 13:53:35.209468 Vio18 = 0
4840 13:53:35.209577 Vcore = 662500
4841 13:53:35.209671 Vdram = 0
4842 13:53:35.212995 Vddq = 0
4843 13:53:35.213097 Vmddr = 0
4844 13:53:35.216819 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4845 13:53:35.222739 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4846 13:53:35.225934 MEM_TYPE=3, freq_sel=17
4847 13:53:35.229783 sv_algorithm_assistance_LP4_1600
4848 13:53:35.233255 ============ PULL DRAM RESETB DOWN ============
4849 13:53:35.235925 ========== PULL DRAM RESETB DOWN end =========
4850 13:53:35.243041 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4851 13:53:35.246315 ===================================
4852 13:53:35.246443 LPDDR4 DRAM CONFIGURATION
4853 13:53:35.249381 ===================================
4854 13:53:35.252471 EX_ROW_EN[0] = 0x0
4855 13:53:35.252592 EX_ROW_EN[1] = 0x0
4856 13:53:35.255992 LP4Y_EN = 0x0
4857 13:53:35.259651 WORK_FSP = 0x0
4858 13:53:35.259754 WL = 0x3
4859 13:53:35.262420 RL = 0x3
4860 13:53:35.262510 BL = 0x2
4861 13:53:35.266039 RPST = 0x0
4862 13:53:35.266130 RD_PRE = 0x0
4863 13:53:35.269435 WR_PRE = 0x1
4864 13:53:35.269528 WR_PST = 0x0
4865 13:53:35.273086 DBI_WR = 0x0
4866 13:53:35.273258 DBI_RD = 0x0
4867 13:53:35.276067 OTF = 0x1
4868 13:53:35.279432 ===================================
4869 13:53:35.283027 ===================================
4870 13:53:35.283167 ANA top config
4871 13:53:35.285964 ===================================
4872 13:53:35.289083 DLL_ASYNC_EN = 0
4873 13:53:35.292781 ALL_SLAVE_EN = 1
4874 13:53:35.292959 NEW_RANK_MODE = 1
4875 13:53:35.296080 DLL_IDLE_MODE = 1
4876 13:53:35.299605 LP45_APHY_COMB_EN = 1
4877 13:53:35.302948 TX_ODT_DIS = 1
4878 13:53:35.303092 NEW_8X_MODE = 1
4879 13:53:35.306135 ===================================
4880 13:53:35.309412 ===================================
4881 13:53:35.312877 data_rate = 1866
4882 13:53:35.315756 CKR = 1
4883 13:53:35.319470 DQ_P2S_RATIO = 8
4884 13:53:35.322427 ===================================
4885 13:53:35.326066 CA_P2S_RATIO = 8
4886 13:53:35.329687 DQ_CA_OPEN = 0
4887 13:53:35.332442 DQ_SEMI_OPEN = 0
4888 13:53:35.332556 CA_SEMI_OPEN = 0
4889 13:53:35.335890 CA_FULL_RATE = 0
4890 13:53:35.339309 DQ_CKDIV4_EN = 1
4891 13:53:35.342126 CA_CKDIV4_EN = 1
4892 13:53:35.345506 CA_PREDIV_EN = 0
4893 13:53:35.348900 PH8_DLY = 0
4894 13:53:35.349014 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4895 13:53:35.352160 DQ_AAMCK_DIV = 4
4896 13:53:35.355675 CA_AAMCK_DIV = 4
4897 13:53:35.359039 CA_ADMCK_DIV = 4
4898 13:53:35.362195 DQ_TRACK_CA_EN = 0
4899 13:53:35.365345 CA_PICK = 933
4900 13:53:35.365485 CA_MCKIO = 933
4901 13:53:35.368651 MCKIO_SEMI = 0
4902 13:53:35.372065 PLL_FREQ = 3732
4903 13:53:35.375326 DQ_UI_PI_RATIO = 32
4904 13:53:35.378978 CA_UI_PI_RATIO = 0
4905 13:53:35.382662 ===================================
4906 13:53:35.385527 ===================================
4907 13:53:35.389326 memory_type:LPDDR4
4908 13:53:35.389419 GP_NUM : 10
4909 13:53:35.392380 SRAM_EN : 1
4910 13:53:35.392495 MD32_EN : 0
4911 13:53:35.395136 ===================================
4912 13:53:35.398984 [ANA_INIT] >>>>>>>>>>>>>>
4913 13:53:35.401808 <<<<<< [CONFIGURE PHASE]: ANA_TX
4914 13:53:35.405507 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4915 13:53:35.409069 ===================================
4916 13:53:35.411952 data_rate = 1866,PCW = 0X8f00
4917 13:53:35.415422 ===================================
4918 13:53:35.418576 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4919 13:53:35.425409 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4920 13:53:35.428322 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4921 13:53:35.434987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4922 13:53:35.438594 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4923 13:53:35.442239 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4924 13:53:35.442370 [ANA_INIT] flow start
4925 13:53:35.445124 [ANA_INIT] PLL >>>>>>>>
4926 13:53:35.448877 [ANA_INIT] PLL <<<<<<<<
4927 13:53:35.448995 [ANA_INIT] MIDPI >>>>>>>>
4928 13:53:35.451714 [ANA_INIT] MIDPI <<<<<<<<
4929 13:53:35.455316 [ANA_INIT] DLL >>>>>>>>
4930 13:53:35.455440 [ANA_INIT] flow end
4931 13:53:35.462031 ============ LP4 DIFF to SE enter ============
4932 13:53:35.465424 ============ LP4 DIFF to SE exit ============
4933 13:53:35.465534 [ANA_INIT] <<<<<<<<<<<<<
4934 13:53:35.468513 [Flow] Enable top DCM control >>>>>
4935 13:53:35.472401 [Flow] Enable top DCM control <<<<<
4936 13:53:35.475114 Enable DLL master slave shuffle
4937 13:53:35.481985 ==============================================================
4938 13:53:35.485370 Gating Mode config
4939 13:53:35.488488 ==============================================================
4940 13:53:35.491757 Config description:
4941 13:53:35.502142 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4942 13:53:35.508483 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4943 13:53:35.511462 SELPH_MODE 0: By rank 1: By Phase
4944 13:53:35.518195 ==============================================================
4945 13:53:35.521886 GAT_TRACK_EN = 1
4946 13:53:35.525521 RX_GATING_MODE = 2
4947 13:53:35.525642 RX_GATING_TRACK_MODE = 2
4948 13:53:35.528453 SELPH_MODE = 1
4949 13:53:35.531737 PICG_EARLY_EN = 1
4950 13:53:35.535029 VALID_LAT_VALUE = 1
4951 13:53:35.541756 ==============================================================
4952 13:53:35.545507 Enter into Gating configuration >>>>
4953 13:53:35.548565 Exit from Gating configuration <<<<
4954 13:53:35.551571 Enter into DVFS_PRE_config >>>>>
4955 13:53:35.561894 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4956 13:53:35.564872 Exit from DVFS_PRE_config <<<<<
4957 13:53:35.568380 Enter into PICG configuration >>>>
4958 13:53:35.571314 Exit from PICG configuration <<<<
4959 13:53:35.574874 [RX_INPUT] configuration >>>>>
4960 13:53:35.578527 [RX_INPUT] configuration <<<<<
4961 13:53:35.581445 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4962 13:53:35.588418 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4963 13:53:35.594336 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4964 13:53:35.601484 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4965 13:53:35.604690 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4966 13:53:35.610906 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4967 13:53:35.617924 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4968 13:53:35.621006 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4969 13:53:35.624287 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4970 13:53:35.627510 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4971 13:53:35.634147 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4972 13:53:35.637474 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4973 13:53:35.640985 ===================================
4974 13:53:35.644607 LPDDR4 DRAM CONFIGURATION
4975 13:53:35.647342 ===================================
4976 13:53:35.647540 EX_ROW_EN[0] = 0x0
4977 13:53:35.650796 EX_ROW_EN[1] = 0x0
4978 13:53:35.650921 LP4Y_EN = 0x0
4979 13:53:35.654226 WORK_FSP = 0x0
4980 13:53:35.654315 WL = 0x3
4981 13:53:35.657559 RL = 0x3
4982 13:53:35.657696 BL = 0x2
4983 13:53:35.660709 RPST = 0x0
4984 13:53:35.660817 RD_PRE = 0x0
4985 13:53:35.664154 WR_PRE = 0x1
4986 13:53:35.667158 WR_PST = 0x0
4987 13:53:35.667276 DBI_WR = 0x0
4988 13:53:35.671111 DBI_RD = 0x0
4989 13:53:35.671191 OTF = 0x1
4990 13:53:35.673954 ===================================
4991 13:53:35.677371 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4992 13:53:35.681055 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4993 13:53:35.687662 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4994 13:53:35.690368 ===================================
4995 13:53:35.694110 LPDDR4 DRAM CONFIGURATION
4996 13:53:35.697515 ===================================
4997 13:53:35.697635 EX_ROW_EN[0] = 0x10
4998 13:53:35.700410 EX_ROW_EN[1] = 0x0
4999 13:53:35.700498 LP4Y_EN = 0x0
5000 13:53:35.703879 WORK_FSP = 0x0
5001 13:53:35.703993 WL = 0x3
5002 13:53:35.707489 RL = 0x3
5003 13:53:35.707619 BL = 0x2
5004 13:53:35.710385 RPST = 0x0
5005 13:53:35.710510 RD_PRE = 0x0
5006 13:53:35.713568 WR_PRE = 0x1
5007 13:53:35.713678 WR_PST = 0x0
5008 13:53:35.716974 DBI_WR = 0x0
5009 13:53:35.717064 DBI_RD = 0x0
5010 13:53:35.720754 OTF = 0x1
5011 13:53:35.723546 ===================================
5012 13:53:35.730066 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5013 13:53:35.733893 nWR fixed to 30
5014 13:53:35.736842 [ModeRegInit_LP4] CH0 RK0
5015 13:53:35.736976 [ModeRegInit_LP4] CH0 RK1
5016 13:53:35.740363 [ModeRegInit_LP4] CH1 RK0
5017 13:53:35.743929 [ModeRegInit_LP4] CH1 RK1
5018 13:53:35.744046 match AC timing 9
5019 13:53:35.750481 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5020 13:53:35.753914 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5021 13:53:35.756887 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5022 13:53:35.763607 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5023 13:53:35.767253 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5024 13:53:35.767375 ==
5025 13:53:35.770388 Dram Type= 6, Freq= 0, CH_0, rank 0
5026 13:53:35.773623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5027 13:53:35.773742 ==
5028 13:53:35.780084 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5029 13:53:35.786466 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5030 13:53:35.790025 [CA 0] Center 37 (6~68) winsize 63
5031 13:53:35.793543 [CA 1] Center 37 (7~68) winsize 62
5032 13:53:35.796394 [CA 2] Center 34 (4~65) winsize 62
5033 13:53:35.800240 [CA 3] Center 34 (3~65) winsize 63
5034 13:53:35.803680 [CA 4] Center 33 (3~64) winsize 62
5035 13:53:35.806543 [CA 5] Center 32 (2~62) winsize 61
5036 13:53:35.806637
5037 13:53:35.810196 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5038 13:53:35.810276
5039 13:53:35.813894 [CATrainingPosCal] consider 1 rank data
5040 13:53:35.816906 u2DelayCellTimex100 = 270/100 ps
5041 13:53:35.819892 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5042 13:53:35.823507 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5043 13:53:35.826612 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5044 13:53:35.830167 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5045 13:53:35.832966 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5046 13:53:35.839638 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5047 13:53:35.839736
5048 13:53:35.843253 CA PerBit enable=1, Macro0, CA PI delay=32
5049 13:53:35.843367
5050 13:53:35.846667 [CBTSetCACLKResult] CA Dly = 32
5051 13:53:35.846758 CS Dly: 5 (0~36)
5052 13:53:35.846824 ==
5053 13:53:35.849757 Dram Type= 6, Freq= 0, CH_0, rank 1
5054 13:53:35.853215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5055 13:53:35.853320 ==
5056 13:53:35.859788 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5057 13:53:35.866956 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5058 13:53:35.869751 [CA 0] Center 37 (6~68) winsize 63
5059 13:53:35.873435 [CA 1] Center 37 (6~68) winsize 63
5060 13:53:35.876738 [CA 2] Center 34 (4~65) winsize 62
5061 13:53:35.880066 [CA 3] Center 34 (3~65) winsize 63
5062 13:53:35.883352 [CA 4] Center 32 (2~63) winsize 62
5063 13:53:35.886691 [CA 5] Center 32 (2~62) winsize 61
5064 13:53:35.886825
5065 13:53:35.889894 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5066 13:53:35.889989
5067 13:53:35.892893 [CATrainingPosCal] consider 2 rank data
5068 13:53:35.896278 u2DelayCellTimex100 = 270/100 ps
5069 13:53:35.899751 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5070 13:53:35.903298 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5071 13:53:35.906285 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5072 13:53:35.909888 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5073 13:53:35.913185 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5074 13:53:35.919899 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5075 13:53:35.920010
5076 13:53:35.922861 CA PerBit enable=1, Macro0, CA PI delay=32
5077 13:53:35.922949
5078 13:53:35.926507 [CBTSetCACLKResult] CA Dly = 32
5079 13:53:35.926597 CS Dly: 5 (0~37)
5080 13:53:35.926662
5081 13:53:35.930313 ----->DramcWriteLeveling(PI) begin...
5082 13:53:35.930400 ==
5083 13:53:35.933155 Dram Type= 6, Freq= 0, CH_0, rank 0
5084 13:53:35.939658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5085 13:53:35.939759 ==
5086 13:53:35.942710 Write leveling (Byte 0): 31 => 31
5087 13:53:35.942797 Write leveling (Byte 1): 28 => 28
5088 13:53:35.946309 DramcWriteLeveling(PI) end<-----
5089 13:53:35.946399
5090 13:53:35.950008 ==
5091 13:53:35.950093 Dram Type= 6, Freq= 0, CH_0, rank 0
5092 13:53:35.956276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5093 13:53:35.956400 ==
5094 13:53:35.959513 [Gating] SW mode calibration
5095 13:53:35.966459 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5096 13:53:35.969283 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5097 13:53:35.976317 0 14 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
5098 13:53:35.979911 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 13:53:35.982809 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 13:53:35.989985 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 13:53:35.992977 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 13:53:35.996639 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 13:53:36.002938 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
5104 13:53:36.006295 0 14 28 | B1->B0 | 3030 2929 | 1 0 | (1 1) (0 0)
5105 13:53:36.009798 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
5106 13:53:36.013152 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 13:53:36.019389 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 13:53:36.022862 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 13:53:36.029486 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 13:53:36.032476 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 13:53:36.035904 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5112 13:53:36.039100 0 15 28 | B1->B0 | 2424 3a3a | 0 0 | (0 0) (1 1)
5113 13:53:36.045835 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5114 13:53:36.049465 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 13:53:36.052443 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 13:53:36.059086 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 13:53:36.062632 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 13:53:36.065871 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 13:53:36.072097 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5120 13:53:36.075811 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5121 13:53:36.079411 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 13:53:36.085618 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 13:53:36.089053 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 13:53:36.091949 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 13:53:36.098750 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 13:53:36.102466 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 13:53:36.105328 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 13:53:36.112433 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 13:53:36.115419 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 13:53:36.118512 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 13:53:36.125546 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 13:53:36.128354 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 13:53:36.132136 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 13:53:36.138659 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 13:53:36.141618 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 13:53:36.145133 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5137 13:53:36.151839 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5138 13:53:36.154924 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 13:53:36.158426 Total UI for P1: 0, mck2ui 16
5140 13:53:36.161727 best dqsien dly found for B0: ( 1, 2, 30)
5141 13:53:36.165315 Total UI for P1: 0, mck2ui 16
5142 13:53:36.168542 best dqsien dly found for B1: ( 1, 3, 0)
5143 13:53:36.171803 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5144 13:53:36.175247 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5145 13:53:36.175344
5146 13:53:36.178496 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5147 13:53:36.182052 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5148 13:53:36.184899 [Gating] SW calibration Done
5149 13:53:36.184995 ==
5150 13:53:36.188461 Dram Type= 6, Freq= 0, CH_0, rank 0
5151 13:53:36.191885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5152 13:53:36.191980 ==
5153 13:53:36.195620 RX Vref Scan: 0
5154 13:53:36.195713
5155 13:53:36.198461 RX Vref 0 -> 0, step: 1
5156 13:53:36.198545
5157 13:53:36.198611 RX Delay -80 -> 252, step: 8
5158 13:53:36.205036 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5159 13:53:36.208600 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5160 13:53:36.211679 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5161 13:53:36.215345 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5162 13:53:36.218866 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5163 13:53:36.221934 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5164 13:53:36.228558 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5165 13:53:36.231946 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5166 13:53:36.235353 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5167 13:53:36.238360 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5168 13:53:36.242158 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5169 13:53:36.248636 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5170 13:53:36.251544 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5171 13:53:36.255312 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5172 13:53:36.258337 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5173 13:53:36.261792 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5174 13:53:36.261901 ==
5175 13:53:36.264746 Dram Type= 6, Freq= 0, CH_0, rank 0
5176 13:53:36.271926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5177 13:53:36.272043 ==
5178 13:53:36.272146 DQS Delay:
5179 13:53:36.274722 DQS0 = 0, DQS1 = 0
5180 13:53:36.274834 DQM Delay:
5181 13:53:36.278459 DQM0 = 104, DQM1 = 95
5182 13:53:36.278583 DQ Delay:
5183 13:53:36.281763 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5184 13:53:36.284874 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =111
5185 13:53:36.288246 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87
5186 13:53:36.291486 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5187 13:53:36.291608
5188 13:53:36.291706
5189 13:53:36.291795 ==
5190 13:53:36.294849 Dram Type= 6, Freq= 0, CH_0, rank 0
5191 13:53:36.297985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5192 13:53:36.298125 ==
5193 13:53:36.301228
5194 13:53:36.301366
5195 13:53:36.301462 TX Vref Scan disable
5196 13:53:36.304477 == TX Byte 0 ==
5197 13:53:36.308024 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5198 13:53:36.311138 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5199 13:53:36.314881 == TX Byte 1 ==
5200 13:53:36.318340 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5201 13:53:36.321324 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5202 13:53:36.321423 ==
5203 13:53:36.324375 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 13:53:36.331677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 13:53:36.331835 ==
5206 13:53:36.331920
5207 13:53:36.331982
5208 13:53:36.332041 TX Vref Scan disable
5209 13:53:36.335864 == TX Byte 0 ==
5210 13:53:36.339103 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5211 13:53:36.342492 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5212 13:53:36.345912 == TX Byte 1 ==
5213 13:53:36.348779 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5214 13:53:36.355303 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5215 13:53:36.355424
5216 13:53:36.355516 [DATLAT]
5217 13:53:36.355579 Freq=933, CH0 RK0
5218 13:53:36.355639
5219 13:53:36.358978 DATLAT Default: 0xd
5220 13:53:36.359055 0, 0xFFFF, sum = 0
5221 13:53:36.362010 1, 0xFFFF, sum = 0
5222 13:53:36.362087 2, 0xFFFF, sum = 0
5223 13:53:36.365518 3, 0xFFFF, sum = 0
5224 13:53:36.369161 4, 0xFFFF, sum = 0
5225 13:53:36.369240 5, 0xFFFF, sum = 0
5226 13:53:36.371994 6, 0xFFFF, sum = 0
5227 13:53:36.372099 7, 0xFFFF, sum = 0
5228 13:53:36.375522 8, 0xFFFF, sum = 0
5229 13:53:36.375598 9, 0xFFFF, sum = 0
5230 13:53:36.379309 10, 0x0, sum = 1
5231 13:53:36.379384 11, 0x0, sum = 2
5232 13:53:36.382103 12, 0x0, sum = 3
5233 13:53:36.382178 13, 0x0, sum = 4
5234 13:53:36.382241 best_step = 11
5235 13:53:36.382300
5236 13:53:36.385092 ==
5237 13:53:36.388815 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 13:53:36.391678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 13:53:36.391755 ==
5240 13:53:36.391817 RX Vref Scan: 1
5241 13:53:36.391877
5242 13:53:36.395229 RX Vref 0 -> 0, step: 1
5243 13:53:36.395302
5244 13:53:36.399042 RX Delay -53 -> 252, step: 4
5245 13:53:36.399119
5246 13:53:36.401779 Set Vref, RX VrefLevel [Byte0]: 56
5247 13:53:36.405169 [Byte1]: 49
5248 13:53:36.405268
5249 13:53:36.408703 Final RX Vref Byte 0 = 56 to rank0
5250 13:53:36.411922 Final RX Vref Byte 1 = 49 to rank0
5251 13:53:36.415311 Final RX Vref Byte 0 = 56 to rank1
5252 13:53:36.418597 Final RX Vref Byte 1 = 49 to rank1==
5253 13:53:36.421521 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 13:53:36.425295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 13:53:36.428658 ==
5256 13:53:36.428752 DQS Delay:
5257 13:53:36.428818 DQS0 = 0, DQS1 = 0
5258 13:53:36.431943 DQM Delay:
5259 13:53:36.432030 DQM0 = 104, DQM1 = 95
5260 13:53:36.435280 DQ Delay:
5261 13:53:36.438658 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102
5262 13:53:36.442108 DQ4 =104, DQ5 =96, DQ6 =114, DQ7 =110
5263 13:53:36.445154 DQ8 =84, DQ9 =84, DQ10 =98, DQ11 =90
5264 13:53:36.448123 DQ12 =100, DQ13 =98, DQ14 =108, DQ15 =102
5265 13:53:36.448218
5266 13:53:36.448285
5267 13:53:36.455036 [DQSOSCAuto] RK0, (LSB)MR18= 0x3129, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5268 13:53:36.458129 CH0 RK0: MR19=505, MR18=3129
5269 13:53:36.464763 CH0_RK0: MR19=0x505, MR18=0x3129, DQSOSC=406, MR23=63, INC=65, DEC=43
5270 13:53:36.464904
5271 13:53:36.468074 ----->DramcWriteLeveling(PI) begin...
5272 13:53:36.468175 ==
5273 13:53:36.471420 Dram Type= 6, Freq= 0, CH_0, rank 1
5274 13:53:36.475203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 13:53:36.475294 ==
5276 13:53:36.478025 Write leveling (Byte 0): 34 => 34
5277 13:53:36.481147 Write leveling (Byte 1): 31 => 31
5278 13:53:36.484710 DramcWriteLeveling(PI) end<-----
5279 13:53:36.484814
5280 13:53:36.484880 ==
5281 13:53:36.488481 Dram Type= 6, Freq= 0, CH_0, rank 1
5282 13:53:36.491442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 13:53:36.494906 ==
5284 13:53:36.494986 [Gating] SW mode calibration
5285 13:53:36.504376 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5286 13:53:36.508133 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5287 13:53:36.511623 0 14 0 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5288 13:53:36.517981 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5289 13:53:36.521656 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5290 13:53:36.524606 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5291 13:53:36.531256 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 13:53:36.534345 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 13:53:36.538047 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5294 13:53:36.544232 0 14 28 | B1->B0 | 2d2d 2b2b | 1 1 | (0 0) (0 0)
5295 13:53:36.547589 0 15 0 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
5296 13:53:36.551210 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5297 13:53:36.557898 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5298 13:53:36.561312 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5299 13:53:36.564218 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 13:53:36.570988 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 13:53:36.574140 0 15 24 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
5302 13:53:36.577294 0 15 28 | B1->B0 | 3d3d 3d3d | 0 0 | (1 1) (1 1)
5303 13:53:36.584153 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 13:53:36.587638 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 13:53:36.590736 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5306 13:53:36.597374 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 13:53:36.601065 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 13:53:36.603982 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 13:53:36.610363 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 13:53:36.613885 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5311 13:53:36.617539 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 13:53:36.623981 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 13:53:36.627640 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 13:53:36.630604 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 13:53:36.634285 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 13:53:36.640995 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 13:53:36.643963 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 13:53:36.646887 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 13:53:36.653797 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 13:53:36.657222 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 13:53:36.660549 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 13:53:36.667635 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 13:53:36.670367 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 13:53:36.673961 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 13:53:36.680526 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 13:53:36.684224 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5327 13:53:36.687297 Total UI for P1: 0, mck2ui 16
5328 13:53:36.690964 best dqsien dly found for B0: ( 1, 2, 26)
5329 13:53:36.693699 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 13:53:36.697335 Total UI for P1: 0, mck2ui 16
5331 13:53:36.700779 best dqsien dly found for B1: ( 1, 2, 28)
5332 13:53:36.704118 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5333 13:53:36.707416 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5334 13:53:36.707528
5335 13:53:36.713587 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5336 13:53:36.717347 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5337 13:53:36.717432 [Gating] SW calibration Done
5338 13:53:36.720537 ==
5339 13:53:36.723961 Dram Type= 6, Freq= 0, CH_0, rank 1
5340 13:53:36.727330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5341 13:53:36.727411 ==
5342 13:53:36.727474 RX Vref Scan: 0
5343 13:53:36.727533
5344 13:53:36.730656 RX Vref 0 -> 0, step: 1
5345 13:53:36.730737
5346 13:53:36.733381 RX Delay -80 -> 252, step: 8
5347 13:53:36.737120 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5348 13:53:36.740098 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5349 13:53:36.744073 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5350 13:53:36.750504 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5351 13:53:36.753535 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5352 13:53:36.757093 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5353 13:53:36.759981 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5354 13:53:36.763323 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5355 13:53:36.770029 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5356 13:53:36.773538 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5357 13:53:36.777019 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5358 13:53:36.779963 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5359 13:53:36.783728 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5360 13:53:36.786647 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5361 13:53:36.793167 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5362 13:53:36.796677 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5363 13:53:36.796788 ==
5364 13:53:36.800226 Dram Type= 6, Freq= 0, CH_0, rank 1
5365 13:53:36.803190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5366 13:53:36.803276 ==
5367 13:53:36.806830 DQS Delay:
5368 13:53:36.806913 DQS0 = 0, DQS1 = 0
5369 13:53:36.806978 DQM Delay:
5370 13:53:36.810119 DQM0 = 105, DQM1 = 95
5371 13:53:36.810207 DQ Delay:
5372 13:53:36.813076 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =103
5373 13:53:36.816744 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5374 13:53:36.819619 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5375 13:53:36.823077 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =103
5376 13:53:36.823182
5377 13:53:36.823274
5378 13:53:36.826525 ==
5379 13:53:36.829835 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 13:53:36.833231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 13:53:36.833321 ==
5382 13:53:36.833387
5383 13:53:36.833447
5384 13:53:36.836627 TX Vref Scan disable
5385 13:53:36.836735 == TX Byte 0 ==
5386 13:53:36.839597 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5387 13:53:36.846176 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5388 13:53:36.846302 == TX Byte 1 ==
5389 13:53:36.849454 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5390 13:53:36.856265 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5391 13:53:36.856375 ==
5392 13:53:36.859865 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 13:53:36.862676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 13:53:36.862771 ==
5395 13:53:36.862867
5396 13:53:36.862957
5397 13:53:36.866239 TX Vref Scan disable
5398 13:53:36.869672 == TX Byte 0 ==
5399 13:53:36.872560 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5400 13:53:36.876080 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5401 13:53:36.879290 == TX Byte 1 ==
5402 13:53:36.882533 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5403 13:53:36.886088 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5404 13:53:36.886173
5405 13:53:36.889526 [DATLAT]
5406 13:53:36.889640 Freq=933, CH0 RK1
5407 13:53:36.889737
5408 13:53:36.892306 DATLAT Default: 0xb
5409 13:53:36.892425 0, 0xFFFF, sum = 0
5410 13:53:36.896116 1, 0xFFFF, sum = 0
5411 13:53:36.896229 2, 0xFFFF, sum = 0
5412 13:53:36.899070 3, 0xFFFF, sum = 0
5413 13:53:36.899175 4, 0xFFFF, sum = 0
5414 13:53:36.902779 5, 0xFFFF, sum = 0
5415 13:53:36.902895 6, 0xFFFF, sum = 0
5416 13:53:36.906378 7, 0xFFFF, sum = 0
5417 13:53:36.906470 8, 0xFFFF, sum = 0
5418 13:53:36.909378 9, 0xFFFF, sum = 0
5419 13:53:36.909465 10, 0x0, sum = 1
5420 13:53:36.912866 11, 0x0, sum = 2
5421 13:53:36.912952 12, 0x0, sum = 3
5422 13:53:36.915795 13, 0x0, sum = 4
5423 13:53:36.915881 best_step = 11
5424 13:53:36.915945
5425 13:53:36.916005 ==
5426 13:53:36.919180 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 13:53:36.925668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 13:53:36.925792 ==
5429 13:53:36.925874 RX Vref Scan: 0
5430 13:53:36.925937
5431 13:53:36.929362 RX Vref 0 -> 0, step: 1
5432 13:53:36.929449
5433 13:53:36.932617 RX Delay -45 -> 252, step: 4
5434 13:53:36.935968 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5435 13:53:36.939185 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5436 13:53:36.945654 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5437 13:53:36.949458 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5438 13:53:36.952410 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5439 13:53:36.956031 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5440 13:53:36.959025 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5441 13:53:36.966013 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5442 13:53:36.968770 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5443 13:53:36.972364 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5444 13:53:36.976010 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5445 13:53:36.979028 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5446 13:53:36.982173 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5447 13:53:36.989185 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5448 13:53:36.992544 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5449 13:53:36.995841 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5450 13:53:36.995964 ==
5451 13:53:36.999193 Dram Type= 6, Freq= 0, CH_0, rank 1
5452 13:53:37.002126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5453 13:53:37.002224 ==
5454 13:53:37.005911 DQS Delay:
5455 13:53:37.006022 DQS0 = 0, DQS1 = 0
5456 13:53:37.008771 DQM Delay:
5457 13:53:37.008865 DQM0 = 104, DQM1 = 94
5458 13:53:37.008951 DQ Delay:
5459 13:53:37.015236 DQ0 =102, DQ1 =104, DQ2 =102, DQ3 =100
5460 13:53:37.018624 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5461 13:53:37.021982 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =88
5462 13:53:37.025557 DQ12 =98, DQ13 =98, DQ14 =104, DQ15 =102
5463 13:53:37.025667
5464 13:53:37.025769
5465 13:53:37.032092 [DQSOSCAuto] RK1, (LSB)MR18= 0x26fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps
5466 13:53:37.035742 CH0 RK1: MR19=504, MR18=26FE
5467 13:53:37.041996 CH0_RK1: MR19=0x504, MR18=0x26FE, DQSOSC=409, MR23=63, INC=64, DEC=43
5468 13:53:37.045293 [RxdqsGatingPostProcess] freq 933
5469 13:53:37.048573 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5470 13:53:37.052031 best DQS0 dly(2T, 0.5T) = (0, 10)
5471 13:53:37.054859 best DQS1 dly(2T, 0.5T) = (0, 11)
5472 13:53:37.058615 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5473 13:53:37.062399 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5474 13:53:37.065264 best DQS0 dly(2T, 0.5T) = (0, 10)
5475 13:53:37.068223 best DQS1 dly(2T, 0.5T) = (0, 10)
5476 13:53:37.071692 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5477 13:53:37.074922 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5478 13:53:37.078177 Pre-setting of DQS Precalculation
5479 13:53:37.081446 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5480 13:53:37.081545 ==
5481 13:53:37.085255 Dram Type= 6, Freq= 0, CH_1, rank 0
5482 13:53:37.091770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5483 13:53:37.091856 ==
5484 13:53:37.094752 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5485 13:53:37.101721 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5486 13:53:37.105133 [CA 0] Center 36 (6~67) winsize 62
5487 13:53:37.108361 [CA 1] Center 37 (6~68) winsize 63
5488 13:53:37.111985 [CA 2] Center 35 (5~65) winsize 61
5489 13:53:37.114799 [CA 3] Center 34 (4~65) winsize 62
5490 13:53:37.118026 [CA 4] Center 34 (4~65) winsize 62
5491 13:53:37.122077 [CA 5] Center 33 (3~64) winsize 62
5492 13:53:37.122195
5493 13:53:37.125140 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5494 13:53:37.125253
5495 13:53:37.128373 [CATrainingPosCal] consider 1 rank data
5496 13:53:37.131356 u2DelayCellTimex100 = 270/100 ps
5497 13:53:37.134968 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5498 13:53:37.141400 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5499 13:53:37.145160 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5500 13:53:37.148057 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5501 13:53:37.151612 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5502 13:53:37.155113 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5503 13:53:37.155226
5504 13:53:37.158365 CA PerBit enable=1, Macro0, CA PI delay=33
5505 13:53:37.158486
5506 13:53:37.161201 [CBTSetCACLKResult] CA Dly = 33
5507 13:53:37.161286 CS Dly: 7 (0~38)
5508 13:53:37.164864 ==
5509 13:53:37.167991 Dram Type= 6, Freq= 0, CH_1, rank 1
5510 13:53:37.171669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5511 13:53:37.171779 ==
5512 13:53:37.174749 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5513 13:53:37.181308 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5514 13:53:37.185007 [CA 0] Center 36 (6~67) winsize 62
5515 13:53:37.188453 [CA 1] Center 37 (7~68) winsize 62
5516 13:53:37.191800 [CA 2] Center 35 (5~66) winsize 62
5517 13:53:37.194950 [CA 3] Center 34 (4~65) winsize 62
5518 13:53:37.198026 [CA 4] Center 34 (4~65) winsize 62
5519 13:53:37.201871 [CA 5] Center 33 (3~64) winsize 62
5520 13:53:37.201973
5521 13:53:37.205009 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5522 13:53:37.205106
5523 13:53:37.208455 [CATrainingPosCal] consider 2 rank data
5524 13:53:37.212124 u2DelayCellTimex100 = 270/100 ps
5525 13:53:37.214840 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5526 13:53:37.218192 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5527 13:53:37.224856 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5528 13:53:37.228891 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5529 13:53:37.231735 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5530 13:53:37.234839 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5531 13:53:37.234988
5532 13:53:37.238472 CA PerBit enable=1, Macro0, CA PI delay=33
5533 13:53:37.238608
5534 13:53:37.241319 [CBTSetCACLKResult] CA Dly = 33
5535 13:53:37.241426 CS Dly: 8 (0~40)
5536 13:53:37.244831
5537 13:53:37.248354 ----->DramcWriteLeveling(PI) begin...
5538 13:53:37.248453 ==
5539 13:53:37.251208 Dram Type= 6, Freq= 0, CH_1, rank 0
5540 13:53:37.254806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 13:53:37.254912 ==
5542 13:53:37.258329 Write leveling (Byte 0): 28 => 28
5543 13:53:37.261289 Write leveling (Byte 1): 30 => 30
5544 13:53:37.264646 DramcWriteLeveling(PI) end<-----
5545 13:53:37.264737
5546 13:53:37.264803 ==
5547 13:53:37.267961 Dram Type= 6, Freq= 0, CH_1, rank 0
5548 13:53:37.271359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5549 13:53:37.271443 ==
5550 13:53:37.275006 [Gating] SW mode calibration
5551 13:53:37.281397 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5552 13:53:37.287870 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5553 13:53:37.291363 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 13:53:37.294260 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5555 13:53:37.301310 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 13:53:37.304855 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 13:53:37.307522 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 13:53:37.314656 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 13:53:37.317880 0 14 24 | B1->B0 | 3333 2b2b | 1 1 | (1 0) (1 0)
5560 13:53:37.320802 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
5561 13:53:37.327675 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 13:53:37.331190 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 13:53:37.334700 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 13:53:37.340984 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 13:53:37.344197 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 13:53:37.347345 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 13:53:37.354272 0 15 24 | B1->B0 | 2424 3535 | 0 0 | (0 0) (0 0)
5568 13:53:37.357858 0 15 28 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
5569 13:53:37.360644 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 13:53:37.364354 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 13:53:37.370721 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 13:53:37.374221 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 13:53:37.377482 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 13:53:37.384312 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 13:53:37.387191 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5576 13:53:37.390860 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5577 13:53:37.397220 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 13:53:37.400816 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 13:53:37.404346 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 13:53:37.410640 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 13:53:37.413999 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 13:53:37.417556 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 13:53:37.423652 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 13:53:37.427551 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 13:53:37.430754 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 13:53:37.437372 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 13:53:37.440246 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 13:53:37.443791 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 13:53:37.450142 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 13:53:37.454148 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 13:53:37.456908 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5592 13:53:37.460345 Total UI for P1: 0, mck2ui 16
5593 13:53:37.463655 best dqsien dly found for B0: ( 1, 2, 22)
5594 13:53:37.470393 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 13:53:37.470519 Total UI for P1: 0, mck2ui 16
5596 13:53:37.474027 best dqsien dly found for B1: ( 1, 2, 24)
5597 13:53:37.480499 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5598 13:53:37.484003 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5599 13:53:37.484129
5600 13:53:37.487286 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5601 13:53:37.490561 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5602 13:53:37.494044 [Gating] SW calibration Done
5603 13:53:37.494185 ==
5604 13:53:37.496956 Dram Type= 6, Freq= 0, CH_1, rank 0
5605 13:53:37.500451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5606 13:53:37.500601 ==
5607 13:53:37.503625 RX Vref Scan: 0
5608 13:53:37.503746
5609 13:53:37.503813 RX Vref 0 -> 0, step: 1
5610 13:53:37.503875
5611 13:53:37.507195 RX Delay -80 -> 252, step: 8
5612 13:53:37.510646 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5613 13:53:37.514124 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5614 13:53:37.520622 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5615 13:53:37.524056 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5616 13:53:37.526938 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5617 13:53:37.530262 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5618 13:53:37.533827 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5619 13:53:37.537095 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5620 13:53:37.543965 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5621 13:53:37.547157 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5622 13:53:37.550404 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5623 13:53:37.553489 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5624 13:53:37.557100 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5625 13:53:37.560362 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5626 13:53:37.567166 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5627 13:53:37.570664 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5628 13:53:37.570793 ==
5629 13:53:37.573427 Dram Type= 6, Freq= 0, CH_1, rank 0
5630 13:53:37.576661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5631 13:53:37.576750 ==
5632 13:53:37.579952 DQS Delay:
5633 13:53:37.580037 DQS0 = 0, DQS1 = 0
5634 13:53:37.580102 DQM Delay:
5635 13:53:37.583569 DQM0 = 103, DQM1 = 98
5636 13:53:37.583651 DQ Delay:
5637 13:53:37.587226 DQ0 =111, DQ1 =95, DQ2 =91, DQ3 =99
5638 13:53:37.590096 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5639 13:53:37.593479 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5640 13:53:37.596921 DQ12 =107, DQ13 =103, DQ14 =107, DQ15 =107
5641 13:53:37.600247
5642 13:53:37.600369
5643 13:53:37.600438 ==
5644 13:53:37.603864 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 13:53:37.606792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 13:53:37.606889 ==
5647 13:53:37.606993
5648 13:53:37.607091
5649 13:53:37.610080 TX Vref Scan disable
5650 13:53:37.610287 == TX Byte 0 ==
5651 13:53:37.617037 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5652 13:53:37.619848 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5653 13:53:37.619959 == TX Byte 1 ==
5654 13:53:37.626993 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5655 13:53:37.630406 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5656 13:53:37.630532 ==
5657 13:53:37.633364 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 13:53:37.636616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 13:53:37.636786 ==
5660 13:53:37.636868
5661 13:53:37.636972
5662 13:53:37.640088 TX Vref Scan disable
5663 13:53:37.643672 == TX Byte 0 ==
5664 13:53:37.646404 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5665 13:53:37.649845 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5666 13:53:37.653308 == TX Byte 1 ==
5667 13:53:37.656725 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5668 13:53:37.660115 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5669 13:53:37.660264
5670 13:53:37.663579 [DATLAT]
5671 13:53:37.663703 Freq=933, CH1 RK0
5672 13:53:37.663771
5673 13:53:37.666738 DATLAT Default: 0xd
5674 13:53:37.666879 0, 0xFFFF, sum = 0
5675 13:53:37.669944 1, 0xFFFF, sum = 0
5676 13:53:37.670063 2, 0xFFFF, sum = 0
5677 13:53:37.673312 3, 0xFFFF, sum = 0
5678 13:53:37.673489 4, 0xFFFF, sum = 0
5679 13:53:37.676224 5, 0xFFFF, sum = 0
5680 13:53:37.676399 6, 0xFFFF, sum = 0
5681 13:53:37.679874 7, 0xFFFF, sum = 0
5682 13:53:37.680059 8, 0xFFFF, sum = 0
5683 13:53:37.682810 9, 0xFFFF, sum = 0
5684 13:53:37.682957 10, 0x0, sum = 1
5685 13:53:37.686217 11, 0x0, sum = 2
5686 13:53:37.686395 12, 0x0, sum = 3
5687 13:53:37.689508 13, 0x0, sum = 4
5688 13:53:37.689616 best_step = 11
5689 13:53:37.689706
5690 13:53:37.689794 ==
5691 13:53:37.692878 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 13:53:37.699912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 13:53:37.700029 ==
5694 13:53:37.700129 RX Vref Scan: 1
5695 13:53:37.700222
5696 13:53:37.702589 RX Vref 0 -> 0, step: 1
5697 13:53:37.702700
5698 13:53:37.706177 RX Delay -45 -> 252, step: 4
5699 13:53:37.706269
5700 13:53:37.709624 Set Vref, RX VrefLevel [Byte0]: 53
5701 13:53:37.713150 [Byte1]: 48
5702 13:53:37.713236
5703 13:53:37.715975 Final RX Vref Byte 0 = 53 to rank0
5704 13:53:37.719403 Final RX Vref Byte 1 = 48 to rank0
5705 13:53:37.722909 Final RX Vref Byte 0 = 53 to rank1
5706 13:53:37.725973 Final RX Vref Byte 1 = 48 to rank1==
5707 13:53:37.729641 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 13:53:37.733195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 13:53:37.733283 ==
5710 13:53:37.736018 DQS Delay:
5711 13:53:37.736102 DQS0 = 0, DQS1 = 0
5712 13:53:37.736167 DQM Delay:
5713 13:53:37.739567 DQM0 = 102, DQM1 = 98
5714 13:53:37.739742 DQ Delay:
5715 13:53:37.742900 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5716 13:53:37.746511 DQ4 =104, DQ5 =114, DQ6 =110, DQ7 =102
5717 13:53:37.749493 DQ8 =88, DQ9 =88, DQ10 =98, DQ11 =90
5718 13:53:37.752804 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106
5719 13:53:37.752961
5720 13:53:37.753106
5721 13:53:37.762648 [DQSOSCAuto] RK0, (LSB)MR18= 0x1930, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5722 13:53:37.766288 CH1 RK0: MR19=505, MR18=1930
5723 13:53:37.772940 CH1_RK0: MR19=0x505, MR18=0x1930, DQSOSC=406, MR23=63, INC=65, DEC=43
5724 13:53:37.773088
5725 13:53:37.776148 ----->DramcWriteLeveling(PI) begin...
5726 13:53:37.776271 ==
5727 13:53:37.779162 Dram Type= 6, Freq= 0, CH_1, rank 1
5728 13:53:37.782981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 13:53:37.783118 ==
5730 13:53:37.785960 Write leveling (Byte 0): 25 => 25
5731 13:53:37.789317 Write leveling (Byte 1): 27 => 27
5732 13:53:37.793021 DramcWriteLeveling(PI) end<-----
5733 13:53:37.793202
5734 13:53:37.793350 ==
5735 13:53:37.796245 Dram Type= 6, Freq= 0, CH_1, rank 1
5736 13:53:37.798987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 13:53:37.799156 ==
5738 13:53:37.802547 [Gating] SW mode calibration
5739 13:53:37.809381 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5740 13:53:37.816411 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5741 13:53:37.818998 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 13:53:37.822499 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 13:53:37.829446 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 13:53:37.832830 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5745 13:53:37.835841 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 13:53:37.843022 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 13:53:37.845834 0 14 24 | B1->B0 | 2f2f 3333 | 0 0 | (1 0) (0 1)
5748 13:53:37.849105 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5749 13:53:37.856398 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 13:53:37.859185 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 13:53:37.862618 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 13:53:37.866352 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 13:53:37.872911 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 13:53:37.875854 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 13:53:37.879524 0 15 24 | B1->B0 | 3636 2626 | 1 0 | (0 0) (0 0)
5756 13:53:37.886087 0 15 28 | B1->B0 | 4646 3c3c | 0 0 | (0 0) (0 0)
5757 13:53:37.888860 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 13:53:37.892669 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 13:53:37.899057 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 13:53:37.902485 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 13:53:37.905791 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 13:53:37.912498 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 13:53:37.915979 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 13:53:37.919211 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 13:53:37.925591 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 13:53:37.929211 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 13:53:37.932729 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 13:53:37.938864 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 13:53:37.942440 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 13:53:37.946102 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 13:53:37.952371 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 13:53:37.955337 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 13:53:37.958944 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 13:53:37.965385 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 13:53:37.968912 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 13:53:37.971949 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 13:53:37.978913 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 13:53:37.981748 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 13:53:37.985391 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5780 13:53:37.991954 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5781 13:53:37.992048 Total UI for P1: 0, mck2ui 16
5782 13:53:37.998540 best dqsien dly found for B1: ( 1, 2, 24)
5783 13:53:38.002035 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 13:53:38.005251 Total UI for P1: 0, mck2ui 16
5785 13:53:38.008857 best dqsien dly found for B0: ( 1, 2, 26)
5786 13:53:38.011927 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5787 13:53:38.015507 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5788 13:53:38.015655
5789 13:53:38.019073 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5790 13:53:38.021876 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5791 13:53:38.025563 [Gating] SW calibration Done
5792 13:53:38.025672 ==
5793 13:53:38.028864 Dram Type= 6, Freq= 0, CH_1, rank 1
5794 13:53:38.031940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5795 13:53:38.032063 ==
5796 13:53:38.035145 RX Vref Scan: 0
5797 13:53:38.035235
5798 13:53:38.038524 RX Vref 0 -> 0, step: 1
5799 13:53:38.038621
5800 13:53:38.038688 RX Delay -80 -> 252, step: 8
5801 13:53:38.045444 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5802 13:53:38.048581 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5803 13:53:38.051867 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5804 13:53:38.055136 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5805 13:53:38.058463 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5806 13:53:38.062039 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5807 13:53:38.068522 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5808 13:53:38.072059 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5809 13:53:38.075147 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5810 13:53:38.078755 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5811 13:53:38.081695 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5812 13:53:38.085198 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5813 13:53:38.091773 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5814 13:53:38.095407 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5815 13:53:38.098272 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5816 13:53:38.101787 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5817 13:53:38.101861 ==
5818 13:53:38.104734 Dram Type= 6, Freq= 0, CH_1, rank 1
5819 13:53:38.111426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 13:53:38.111503 ==
5821 13:53:38.111570 DQS Delay:
5822 13:53:38.114717 DQS0 = 0, DQS1 = 0
5823 13:53:38.114793 DQM Delay:
5824 13:53:38.114856 DQM0 = 101, DQM1 = 98
5825 13:53:38.118025 DQ Delay:
5826 13:53:38.121390 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =99
5827 13:53:38.125005 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5828 13:53:38.128406 DQ8 =87, DQ9 =87, DQ10 =103, DQ11 =91
5829 13:53:38.131411 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5830 13:53:38.131514
5831 13:53:38.131588
5832 13:53:38.131681 ==
5833 13:53:38.134758 Dram Type= 6, Freq= 0, CH_1, rank 1
5834 13:53:38.138080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5835 13:53:38.138183 ==
5836 13:53:38.138282
5837 13:53:38.138372
5838 13:53:38.141475 TX Vref Scan disable
5839 13:53:38.144605 == TX Byte 0 ==
5840 13:53:38.147946 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5841 13:53:38.151396 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5842 13:53:38.154761 == TX Byte 1 ==
5843 13:53:38.158043 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5844 13:53:38.161367 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5845 13:53:38.161529 ==
5846 13:53:38.164442 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 13:53:38.171385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 13:53:38.171477 ==
5849 13:53:38.171540
5850 13:53:38.171598
5851 13:53:38.171657 TX Vref Scan disable
5852 13:53:38.175462 == TX Byte 0 ==
5853 13:53:38.178606 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5854 13:53:38.185004 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5855 13:53:38.185113 == TX Byte 1 ==
5856 13:53:38.188757 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5857 13:53:38.195316 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5858 13:53:38.195397
5859 13:53:38.195466 [DATLAT]
5860 13:53:38.195559 Freq=933, CH1 RK1
5861 13:53:38.195651
5862 13:53:38.198255 DATLAT Default: 0xb
5863 13:53:38.198356 0, 0xFFFF, sum = 0
5864 13:53:38.201964 1, 0xFFFF, sum = 0
5865 13:53:38.202053 2, 0xFFFF, sum = 0
5866 13:53:38.204971 3, 0xFFFF, sum = 0
5867 13:53:38.208451 4, 0xFFFF, sum = 0
5868 13:53:38.208537 5, 0xFFFF, sum = 0
5869 13:53:38.212024 6, 0xFFFF, sum = 0
5870 13:53:38.212107 7, 0xFFFF, sum = 0
5871 13:53:38.214886 8, 0xFFFF, sum = 0
5872 13:53:38.214970 9, 0xFFFF, sum = 0
5873 13:53:38.218285 10, 0x0, sum = 1
5874 13:53:38.218368 11, 0x0, sum = 2
5875 13:53:38.221953 12, 0x0, sum = 3
5876 13:53:38.222036 13, 0x0, sum = 4
5877 13:53:38.222105 best_step = 11
5878 13:53:38.222198
5879 13:53:38.225442 ==
5880 13:53:38.228638 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 13:53:38.232259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 13:53:38.232376 ==
5883 13:53:38.232463 RX Vref Scan: 0
5884 13:53:38.232544
5885 13:53:38.235098 RX Vref 0 -> 0, step: 1
5886 13:53:38.235203
5887 13:53:38.238773 RX Delay -45 -> 252, step: 4
5888 13:53:38.242193 iDelay=199, Bit 0, Center 106 (23 ~ 190) 168
5889 13:53:38.248689 iDelay=199, Bit 1, Center 98 (15 ~ 182) 168
5890 13:53:38.251425 iDelay=199, Bit 2, Center 94 (11 ~ 178) 168
5891 13:53:38.254738 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5892 13:53:38.258276 iDelay=199, Bit 4, Center 100 (19 ~ 182) 164
5893 13:53:38.261847 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5894 13:53:38.268152 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5895 13:53:38.271833 iDelay=199, Bit 7, Center 102 (19 ~ 186) 168
5896 13:53:38.274728 iDelay=199, Bit 8, Center 92 (11 ~ 174) 164
5897 13:53:38.278167 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5898 13:53:38.281630 iDelay=199, Bit 10, Center 102 (19 ~ 186) 168
5899 13:53:38.284903 iDelay=199, Bit 11, Center 94 (11 ~ 178) 168
5900 13:53:38.291302 iDelay=199, Bit 12, Center 108 (19 ~ 198) 180
5901 13:53:38.294939 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5902 13:53:38.298142 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5903 13:53:38.301570 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5904 13:53:38.301677 ==
5905 13:53:38.305086 Dram Type= 6, Freq= 0, CH_1, rank 1
5906 13:53:38.311773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5907 13:53:38.311857 ==
5908 13:53:38.311944 DQS Delay:
5909 13:53:38.314809 DQS0 = 0, DQS1 = 0
5910 13:53:38.314911 DQM Delay:
5911 13:53:38.315013 DQM0 = 103, DQM1 = 99
5912 13:53:38.318568 DQ Delay:
5913 13:53:38.327022 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5914 13:53:38.327134 DQ4 =100, DQ5 =116, DQ6 =112, DQ7 =102
5915 13:53:38.328023 DQ8 =92, DQ9 =88, DQ10 =102, DQ11 =94
5916 13:53:38.331388 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =106
5917 13:53:38.331526
5918 13:53:38.331627
5919 13:53:38.341230 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5920 13:53:38.341314 CH1 RK1: MR19=505, MR18=2F03
5921 13:53:38.347786 CH1_RK1: MR19=0x505, MR18=0x2F03, DQSOSC=407, MR23=63, INC=65, DEC=43
5922 13:53:38.351366 [RxdqsGatingPostProcess] freq 933
5923 13:53:38.357694 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5924 13:53:38.360965 best DQS0 dly(2T, 0.5T) = (0, 10)
5925 13:53:38.364641 best DQS1 dly(2T, 0.5T) = (0, 10)
5926 13:53:38.368174 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5927 13:53:38.370938 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5928 13:53:38.371056 best DQS0 dly(2T, 0.5T) = (0, 10)
5929 13:53:38.374390 best DQS1 dly(2T, 0.5T) = (0, 10)
5930 13:53:38.377383 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5931 13:53:38.381032 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5932 13:53:38.384744 Pre-setting of DQS Precalculation
5933 13:53:38.391269 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5934 13:53:38.397646 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5935 13:53:38.404304 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5936 13:53:38.404484
5937 13:53:38.404581
5938 13:53:38.407726 [Calibration Summary] 1866 Mbps
5939 13:53:38.407835 CH 0, Rank 0
5940 13:53:38.411049 SW Impedance : PASS
5941 13:53:38.414068 DUTY Scan : NO K
5942 13:53:38.414183 ZQ Calibration : PASS
5943 13:53:38.417278 Jitter Meter : NO K
5944 13:53:38.420573 CBT Training : PASS
5945 13:53:38.420694 Write leveling : PASS
5946 13:53:38.424313 RX DQS gating : PASS
5947 13:53:38.427191 RX DQ/DQS(RDDQC) : PASS
5948 13:53:38.427305 TX DQ/DQS : PASS
5949 13:53:38.430815 RX DATLAT : PASS
5950 13:53:38.433714 RX DQ/DQS(Engine): PASS
5951 13:53:38.433817 TX OE : NO K
5952 13:53:38.437296 All Pass.
5953 13:53:38.437407
5954 13:53:38.437499 CH 0, Rank 1
5955 13:53:38.440897 SW Impedance : PASS
5956 13:53:38.441016 DUTY Scan : NO K
5957 13:53:38.444249 ZQ Calibration : PASS
5958 13:53:38.447111 Jitter Meter : NO K
5959 13:53:38.447222 CBT Training : PASS
5960 13:53:38.450502 Write leveling : PASS
5961 13:53:38.450610 RX DQS gating : PASS
5962 13:53:38.454086 RX DQ/DQS(RDDQC) : PASS
5963 13:53:38.457454 TX DQ/DQS : PASS
5964 13:53:38.457561 RX DATLAT : PASS
5965 13:53:38.460277 RX DQ/DQS(Engine): PASS
5966 13:53:38.464004 TX OE : NO K
5967 13:53:38.464112 All Pass.
5968 13:53:38.464210
5969 13:53:38.464301 CH 1, Rank 0
5970 13:53:38.467480 SW Impedance : PASS
5971 13:53:38.470430 DUTY Scan : NO K
5972 13:53:38.470532 ZQ Calibration : PASS
5973 13:53:38.474026 Jitter Meter : NO K
5974 13:53:38.477624 CBT Training : PASS
5975 13:53:38.477753 Write leveling : PASS
5976 13:53:38.480357 RX DQS gating : PASS
5977 13:53:38.483932 RX DQ/DQS(RDDQC) : PASS
5978 13:53:38.484048 TX DQ/DQS : PASS
5979 13:53:38.487501 RX DATLAT : PASS
5980 13:53:38.490365 RX DQ/DQS(Engine): PASS
5981 13:53:38.490439 TX OE : NO K
5982 13:53:38.490507 All Pass.
5983 13:53:38.494082
5984 13:53:38.494174 CH 1, Rank 1
5985 13:53:38.496939 SW Impedance : PASS
5986 13:53:38.497020 DUTY Scan : NO K
5987 13:53:38.500635 ZQ Calibration : PASS
5988 13:53:38.500706 Jitter Meter : NO K
5989 13:53:38.503490 CBT Training : PASS
5990 13:53:38.506829 Write leveling : PASS
5991 13:53:38.506904 RX DQS gating : PASS
5992 13:53:38.510424 RX DQ/DQS(RDDQC) : PASS
5993 13:53:38.513309 TX DQ/DQS : PASS
5994 13:53:38.513411 RX DATLAT : PASS
5995 13:53:38.517055 RX DQ/DQS(Engine): PASS
5996 13:53:38.520312 TX OE : NO K
5997 13:53:38.520400 All Pass.
5998 13:53:38.520461
5999 13:53:38.523788 DramC Write-DBI off
6000 13:53:38.523862 PER_BANK_REFRESH: Hybrid Mode
6001 13:53:38.527147 TX_TRACKING: ON
6002 13:53:38.533625 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6003 13:53:38.540542 [FAST_K] Save calibration result to emmc
6004 13:53:38.543578 dramc_set_vcore_voltage set vcore to 650000
6005 13:53:38.543695 Read voltage for 400, 6
6006 13:53:38.546857 Vio18 = 0
6007 13:53:38.546944 Vcore = 650000
6008 13:53:38.547016 Vdram = 0
6009 13:53:38.550348 Vddq = 0
6010 13:53:38.550458 Vmddr = 0
6011 13:53:38.553645 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6012 13:53:38.560213 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6013 13:53:38.563380 MEM_TYPE=3, freq_sel=20
6014 13:53:38.566931 sv_algorithm_assistance_LP4_800
6015 13:53:38.570438 ============ PULL DRAM RESETB DOWN ============
6016 13:53:38.573299 ========== PULL DRAM RESETB DOWN end =========
6017 13:53:38.576847 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6018 13:53:38.580417 ===================================
6019 13:53:38.583212 LPDDR4 DRAM CONFIGURATION
6020 13:53:38.586591 ===================================
6021 13:53:38.590138 EX_ROW_EN[0] = 0x0
6022 13:53:38.590213 EX_ROW_EN[1] = 0x0
6023 13:53:38.593691 LP4Y_EN = 0x0
6024 13:53:38.593762 WORK_FSP = 0x0
6025 13:53:38.597208 WL = 0x2
6026 13:53:38.597276 RL = 0x2
6027 13:53:38.600088 BL = 0x2
6028 13:53:38.600155 RPST = 0x0
6029 13:53:38.603748 RD_PRE = 0x0
6030 13:53:38.603843 WR_PRE = 0x1
6031 13:53:38.606631 WR_PST = 0x0
6032 13:53:38.606702 DBI_WR = 0x0
6033 13:53:38.609934 DBI_RD = 0x0
6034 13:53:38.613623 OTF = 0x1
6035 13:53:38.613698 ===================================
6036 13:53:38.617255 ===================================
6037 13:53:38.620159 ANA top config
6038 13:53:38.623650 ===================================
6039 13:53:38.626458 DLL_ASYNC_EN = 0
6040 13:53:38.626565 ALL_SLAVE_EN = 1
6041 13:53:38.629825 NEW_RANK_MODE = 1
6042 13:53:38.633506 DLL_IDLE_MODE = 1
6043 13:53:38.637181 LP45_APHY_COMB_EN = 1
6044 13:53:38.640077 TX_ODT_DIS = 1
6045 13:53:38.640161 NEW_8X_MODE = 1
6046 13:53:38.643598 ===================================
6047 13:53:38.647241 ===================================
6048 13:53:38.649971 data_rate = 800
6049 13:53:38.653281 CKR = 1
6050 13:53:38.656581 DQ_P2S_RATIO = 4
6051 13:53:38.659883 ===================================
6052 13:53:38.663615 CA_P2S_RATIO = 4
6053 13:53:38.666936 DQ_CA_OPEN = 0
6054 13:53:38.667055 DQ_SEMI_OPEN = 1
6055 13:53:38.670389 CA_SEMI_OPEN = 1
6056 13:53:38.673237 CA_FULL_RATE = 0
6057 13:53:38.676482 DQ_CKDIV4_EN = 0
6058 13:53:38.680238 CA_CKDIV4_EN = 1
6059 13:53:38.683426 CA_PREDIV_EN = 0
6060 13:53:38.683542 PH8_DLY = 0
6061 13:53:38.686378 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6062 13:53:38.689848 DQ_AAMCK_DIV = 0
6063 13:53:38.693223 CA_AAMCK_DIV = 0
6064 13:53:38.696758 CA_ADMCK_DIV = 4
6065 13:53:38.696870 DQ_TRACK_CA_EN = 0
6066 13:53:38.699718 CA_PICK = 800
6067 13:53:38.703395 CA_MCKIO = 400
6068 13:53:38.706215 MCKIO_SEMI = 400
6069 13:53:38.709834 PLL_FREQ = 3016
6070 13:53:38.713387 DQ_UI_PI_RATIO = 32
6071 13:53:38.716393 CA_UI_PI_RATIO = 32
6072 13:53:38.720083 ===================================
6073 13:53:38.723595 ===================================
6074 13:53:38.723671 memory_type:LPDDR4
6075 13:53:38.726428 GP_NUM : 10
6076 13:53:38.729913 SRAM_EN : 1
6077 13:53:38.729988 MD32_EN : 0
6078 13:53:38.733338 ===================================
6079 13:53:38.736079 [ANA_INIT] >>>>>>>>>>>>>>
6080 13:53:38.739366 <<<<<< [CONFIGURE PHASE]: ANA_TX
6081 13:53:38.742934 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6082 13:53:38.746329 ===================================
6083 13:53:38.749671 data_rate = 800,PCW = 0X7400
6084 13:53:38.753281 ===================================
6085 13:53:38.756159 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6086 13:53:38.759720 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6087 13:53:38.772608 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6088 13:53:38.776437 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6089 13:53:38.779654 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6090 13:53:38.783006 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6091 13:53:38.785884 [ANA_INIT] flow start
6092 13:53:38.789744 [ANA_INIT] PLL >>>>>>>>
6093 13:53:38.789855 [ANA_INIT] PLL <<<<<<<<
6094 13:53:38.792989 [ANA_INIT] MIDPI >>>>>>>>
6095 13:53:38.796138 [ANA_INIT] MIDPI <<<<<<<<
6096 13:53:38.796207 [ANA_INIT] DLL >>>>>>>>
6097 13:53:38.799636 [ANA_INIT] flow end
6098 13:53:38.802647 ============ LP4 DIFF to SE enter ============
6099 13:53:38.805858 ============ LP4 DIFF to SE exit ============
6100 13:53:38.809456 [ANA_INIT] <<<<<<<<<<<<<
6101 13:53:38.812739 [Flow] Enable top DCM control >>>>>
6102 13:53:38.816220 [Flow] Enable top DCM control <<<<<
6103 13:53:38.818974 Enable DLL master slave shuffle
6104 13:53:38.826144 ==============================================================
6105 13:53:38.826250 Gating Mode config
6106 13:53:38.832542 ==============================================================
6107 13:53:38.836030 Config description:
6108 13:53:38.842311 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6109 13:53:38.849201 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6110 13:53:38.855409 SELPH_MODE 0: By rank 1: By Phase
6111 13:53:38.862523 ==============================================================
6112 13:53:38.862614 GAT_TRACK_EN = 0
6113 13:53:38.865361 RX_GATING_MODE = 2
6114 13:53:38.868904 RX_GATING_TRACK_MODE = 2
6115 13:53:38.872317 SELPH_MODE = 1
6116 13:53:38.875994 PICG_EARLY_EN = 1
6117 13:53:38.878785 VALID_LAT_VALUE = 1
6118 13:53:38.885726 ==============================================================
6119 13:53:38.889083 Enter into Gating configuration >>>>
6120 13:53:38.892352 Exit from Gating configuration <<<<
6121 13:53:38.895737 Enter into DVFS_PRE_config >>>>>
6122 13:53:38.905844 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6123 13:53:38.909136 Exit from DVFS_PRE_config <<<<<
6124 13:53:38.912271 Enter into PICG configuration >>>>
6125 13:53:38.915466 Exit from PICG configuration <<<<
6126 13:53:38.918794 [RX_INPUT] configuration >>>>>
6127 13:53:38.918896 [RX_INPUT] configuration <<<<<
6128 13:53:38.925643 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6129 13:53:38.931991 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6130 13:53:38.935301 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6131 13:53:38.941801 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6132 13:53:38.948756 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6133 13:53:38.955576 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6134 13:53:38.958308 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6135 13:53:38.961878 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6136 13:53:38.968189 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6137 13:53:38.971769 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6138 13:53:38.975284 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6139 13:53:38.981575 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6140 13:53:38.985243 ===================================
6141 13:53:38.985322 LPDDR4 DRAM CONFIGURATION
6142 13:53:38.988942 ===================================
6143 13:53:38.991823 EX_ROW_EN[0] = 0x0
6144 13:53:38.991893 EX_ROW_EN[1] = 0x0
6145 13:53:38.995353 LP4Y_EN = 0x0
6146 13:53:38.995433 WORK_FSP = 0x0
6147 13:53:38.998774 WL = 0x2
6148 13:53:39.001618 RL = 0x2
6149 13:53:39.001697 BL = 0x2
6150 13:53:39.004850 RPST = 0x0
6151 13:53:39.004931 RD_PRE = 0x0
6152 13:53:39.008441 WR_PRE = 0x1
6153 13:53:39.008521 WR_PST = 0x0
6154 13:53:39.011794 DBI_WR = 0x0
6155 13:53:39.011892 DBI_RD = 0x0
6156 13:53:39.014725 OTF = 0x1
6157 13:53:39.018214 ===================================
6158 13:53:39.021664 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6159 13:53:39.024989 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6160 13:53:39.028474 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6161 13:53:39.031336 ===================================
6162 13:53:39.034928 LPDDR4 DRAM CONFIGURATION
6163 13:53:39.038244 ===================================
6164 13:53:39.041455 EX_ROW_EN[0] = 0x10
6165 13:53:39.041568 EX_ROW_EN[1] = 0x0
6166 13:53:39.044816 LP4Y_EN = 0x0
6167 13:53:39.044890 WORK_FSP = 0x0
6168 13:53:39.047943 WL = 0x2
6169 13:53:39.048028 RL = 0x2
6170 13:53:39.051784 BL = 0x2
6171 13:53:39.051859 RPST = 0x0
6172 13:53:39.054588 RD_PRE = 0x0
6173 13:53:39.057894 WR_PRE = 0x1
6174 13:53:39.057991 WR_PST = 0x0
6175 13:53:39.061296 DBI_WR = 0x0
6176 13:53:39.061368 DBI_RD = 0x0
6177 13:53:39.064874 OTF = 0x1
6178 13:53:39.068251 ===================================
6179 13:53:39.071122 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6180 13:53:39.076807 nWR fixed to 30
6181 13:53:39.080253 [ModeRegInit_LP4] CH0 RK0
6182 13:53:39.080407 [ModeRegInit_LP4] CH0 RK1
6183 13:53:39.083700 [ModeRegInit_LP4] CH1 RK0
6184 13:53:39.086610 [ModeRegInit_LP4] CH1 RK1
6185 13:53:39.086688 match AC timing 19
6186 13:53:39.093281 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6187 13:53:39.096871 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6188 13:53:39.099536 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6189 13:53:39.106599 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6190 13:53:39.109950 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6191 13:53:39.110062 ==
6192 13:53:39.113327 Dram Type= 6, Freq= 0, CH_0, rank 0
6193 13:53:39.116605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6194 13:53:39.116687 ==
6195 13:53:39.122866 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6196 13:53:39.130010 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6197 13:53:39.132718 [CA 0] Center 36 (8~64) winsize 57
6198 13:53:39.136279 [CA 1] Center 36 (8~64) winsize 57
6199 13:53:39.139733 [CA 2] Center 36 (8~64) winsize 57
6200 13:53:39.143250 [CA 3] Center 36 (8~64) winsize 57
6201 13:53:39.143395 [CA 4] Center 36 (8~64) winsize 57
6202 13:53:39.146238 [CA 5] Center 36 (8~64) winsize 57
6203 13:53:39.146337
6204 13:53:39.152920 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6205 13:53:39.152995
6206 13:53:39.156289 [CATrainingPosCal] consider 1 rank data
6207 13:53:39.159620 u2DelayCellTimex100 = 270/100 ps
6208 13:53:39.163316 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6209 13:53:39.166499 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 13:53:39.169824 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6211 13:53:39.173143 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 13:53:39.176551 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 13:53:39.179325 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 13:53:39.179421
6215 13:53:39.182751 CA PerBit enable=1, Macro0, CA PI delay=36
6216 13:53:39.182864
6217 13:53:39.186216 [CBTSetCACLKResult] CA Dly = 36
6218 13:53:39.189669 CS Dly: 1 (0~32)
6219 13:53:39.189835 ==
6220 13:53:39.193449 Dram Type= 6, Freq= 0, CH_0, rank 1
6221 13:53:39.196229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6222 13:53:39.196390 ==
6223 13:53:39.203330 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6224 13:53:39.206101 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6225 13:53:39.209798 [CA 0] Center 36 (8~64) winsize 57
6226 13:53:39.212695 [CA 1] Center 36 (8~64) winsize 57
6227 13:53:39.216212 [CA 2] Center 36 (8~64) winsize 57
6228 13:53:39.219764 [CA 3] Center 36 (8~64) winsize 57
6229 13:53:39.222442 [CA 4] Center 36 (8~64) winsize 57
6230 13:53:39.225842 [CA 5] Center 36 (8~64) winsize 57
6231 13:53:39.225913
6232 13:53:39.229096 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6233 13:53:39.229172
6234 13:53:39.232608 [CATrainingPosCal] consider 2 rank data
6235 13:53:39.236267 u2DelayCellTimex100 = 270/100 ps
6236 13:53:39.239451 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 13:53:39.242671 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 13:53:39.249251 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 13:53:39.252770 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 13:53:39.256191 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 13:53:39.259014 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 13:53:39.259110
6243 13:53:39.262681 CA PerBit enable=1, Macro0, CA PI delay=36
6244 13:53:39.262756
6245 13:53:39.266168 [CBTSetCACLKResult] CA Dly = 36
6246 13:53:39.266244 CS Dly: 1 (0~32)
6247 13:53:39.266317
6248 13:53:39.268917 ----->DramcWriteLeveling(PI) begin...
6249 13:53:39.272293 ==
6250 13:53:39.275430 Dram Type= 6, Freq= 0, CH_0, rank 0
6251 13:53:39.279239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6252 13:53:39.279315 ==
6253 13:53:39.282506 Write leveling (Byte 0): 40 => 8
6254 13:53:39.285472 Write leveling (Byte 1): 40 => 8
6255 13:53:39.288828 DramcWriteLeveling(PI) end<-----
6256 13:53:39.288902
6257 13:53:39.288961 ==
6258 13:53:39.292570 Dram Type= 6, Freq= 0, CH_0, rank 0
6259 13:53:39.295871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6260 13:53:39.295941 ==
6261 13:53:39.299360 [Gating] SW mode calibration
6262 13:53:39.305826 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6263 13:53:39.309301 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6264 13:53:39.315805 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6265 13:53:39.318684 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6266 13:53:39.322424 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6267 13:53:39.328822 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6268 13:53:39.332442 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6269 13:53:39.335322 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6270 13:53:39.342456 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6271 13:53:39.345252 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 13:53:39.348652 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6273 13:53:39.352006 Total UI for P1: 0, mck2ui 16
6274 13:53:39.355211 best dqsien dly found for B0: ( 0, 14, 24)
6275 13:53:39.359088 Total UI for P1: 0, mck2ui 16
6276 13:53:39.362193 best dqsien dly found for B1: ( 0, 14, 24)
6277 13:53:39.365773 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6278 13:53:39.368651 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6279 13:53:39.371928
6280 13:53:39.375648 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6281 13:53:39.378366 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6282 13:53:39.381805 [Gating] SW calibration Done
6283 13:53:39.381903 ==
6284 13:53:39.385348 Dram Type= 6, Freq= 0, CH_0, rank 0
6285 13:53:39.388508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6286 13:53:39.388605 ==
6287 13:53:39.388667 RX Vref Scan: 0
6288 13:53:39.391638
6289 13:53:39.391706 RX Vref 0 -> 0, step: 1
6290 13:53:39.391766
6291 13:53:39.395494 RX Delay -410 -> 252, step: 16
6292 13:53:39.398365 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6293 13:53:39.405435 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6294 13:53:39.408776 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6295 13:53:39.412097 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6296 13:53:39.415355 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6297 13:53:39.421856 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6298 13:53:39.425441 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6299 13:53:39.428216 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6300 13:53:39.431682 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6301 13:53:39.438291 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6302 13:53:39.441780 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6303 13:53:39.445193 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6304 13:53:39.448743 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6305 13:53:39.455249 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6306 13:53:39.458596 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6307 13:53:39.461441 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6308 13:53:39.461559 ==
6309 13:53:39.465034 Dram Type= 6, Freq= 0, CH_0, rank 0
6310 13:53:39.472024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 13:53:39.472132 ==
6312 13:53:39.472239 DQS Delay:
6313 13:53:39.474646 DQS0 = 27, DQS1 = 35
6314 13:53:39.474742 DQM Delay:
6315 13:53:39.474833 DQM0 = 8, DQM1 = 11
6316 13:53:39.478475 DQ Delay:
6317 13:53:39.481529 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6318 13:53:39.481625 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6319 13:53:39.485166 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6320 13:53:39.488549 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6321 13:53:39.488653
6322 13:53:39.488743
6323 13:53:39.491731 ==
6324 13:53:39.494524 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 13:53:39.498009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 13:53:39.498109 ==
6327 13:53:39.498197
6328 13:53:39.498281
6329 13:53:39.501495 TX Vref Scan disable
6330 13:53:39.501567 == TX Byte 0 ==
6331 13:53:39.504697 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6332 13:53:39.511592 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6333 13:53:39.511673 == TX Byte 1 ==
6334 13:53:39.514735 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6335 13:53:39.521286 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6336 13:53:39.521366 ==
6337 13:53:39.524405 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 13:53:39.527661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 13:53:39.527742 ==
6340 13:53:39.527804
6341 13:53:39.527862
6342 13:53:39.531064 TX Vref Scan disable
6343 13:53:39.531168 == TX Byte 0 ==
6344 13:53:39.534622 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6345 13:53:39.541195 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6346 13:53:39.541288 == TX Byte 1 ==
6347 13:53:39.544667 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 13:53:39.551050 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 13:53:39.551162
6350 13:53:39.551260 [DATLAT]
6351 13:53:39.551345 Freq=400, CH0 RK0
6352 13:53:39.553971
6353 13:53:39.554067 DATLAT Default: 0xf
6354 13:53:39.557543 0, 0xFFFF, sum = 0
6355 13:53:39.557643 1, 0xFFFF, sum = 0
6356 13:53:39.561152 2, 0xFFFF, sum = 0
6357 13:53:39.561252 3, 0xFFFF, sum = 0
6358 13:53:39.564024 4, 0xFFFF, sum = 0
6359 13:53:39.564120 5, 0xFFFF, sum = 0
6360 13:53:39.567308 6, 0xFFFF, sum = 0
6361 13:53:39.567409 7, 0xFFFF, sum = 0
6362 13:53:39.570886 8, 0xFFFF, sum = 0
6363 13:53:39.570957 9, 0xFFFF, sum = 0
6364 13:53:39.574598 10, 0xFFFF, sum = 0
6365 13:53:39.574669 11, 0xFFFF, sum = 0
6366 13:53:39.577383 12, 0xFFFF, sum = 0
6367 13:53:39.577453 13, 0x0, sum = 1
6368 13:53:39.580991 14, 0x0, sum = 2
6369 13:53:39.581059 15, 0x0, sum = 3
6370 13:53:39.583923 16, 0x0, sum = 4
6371 13:53:39.583992 best_step = 14
6372 13:53:39.584051
6373 13:53:39.584106 ==
6374 13:53:39.587260 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 13:53:39.593890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 13:53:39.593965 ==
6377 13:53:39.594025 RX Vref Scan: 1
6378 13:53:39.594082
6379 13:53:39.597678 RX Vref 0 -> 0, step: 1
6380 13:53:39.597751
6381 13:53:39.600831 RX Delay -311 -> 252, step: 8
6382 13:53:39.600899
6383 13:53:39.603910 Set Vref, RX VrefLevel [Byte0]: 56
6384 13:53:39.607296 [Byte1]: 49
6385 13:53:39.607393
6386 13:53:39.610321 Final RX Vref Byte 0 = 56 to rank0
6387 13:53:39.613703 Final RX Vref Byte 1 = 49 to rank0
6388 13:53:39.617626 Final RX Vref Byte 0 = 56 to rank1
6389 13:53:39.620781 Final RX Vref Byte 1 = 49 to rank1==
6390 13:53:39.624069 Dram Type= 6, Freq= 0, CH_0, rank 0
6391 13:53:39.627390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6392 13:53:39.630729 ==
6393 13:53:39.630841 DQS Delay:
6394 13:53:39.630937 DQS0 = 28, DQS1 = 36
6395 13:53:39.634064 DQM Delay:
6396 13:53:39.634137 DQM0 = 10, DQM1 = 12
6397 13:53:39.637148 DQ Delay:
6398 13:53:39.637217 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6399 13:53:39.640082 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6400 13:53:39.643960 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6401 13:53:39.646784 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6402 13:53:39.646884
6403 13:53:39.646973
6404 13:53:39.657273 [DQSOSCAuto] RK0, (LSB)MR18= 0xcbb9, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6405 13:53:39.660163 CH0 RK0: MR19=C0C, MR18=CBB9
6406 13:53:39.666661 CH0_RK0: MR19=0xC0C, MR18=0xCBB9, DQSOSC=384, MR23=63, INC=400, DEC=267
6407 13:53:39.666762 ==
6408 13:53:39.670175 Dram Type= 6, Freq= 0, CH_0, rank 1
6409 13:53:39.673628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 13:53:39.673731 ==
6411 13:53:39.676512 [Gating] SW mode calibration
6412 13:53:39.683670 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6413 13:53:39.686570 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6414 13:53:39.693609 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6415 13:53:39.696407 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6416 13:53:39.700017 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6417 13:53:39.706843 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6418 13:53:39.710035 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6419 13:53:39.713314 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6420 13:53:39.720054 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6421 13:53:39.723367 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6422 13:53:39.726740 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6423 13:53:39.729995 Total UI for P1: 0, mck2ui 16
6424 13:53:39.733561 best dqsien dly found for B0: ( 0, 14, 24)
6425 13:53:39.736331 Total UI for P1: 0, mck2ui 16
6426 13:53:39.739925 best dqsien dly found for B1: ( 0, 14, 24)
6427 13:53:39.743470 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6428 13:53:39.746088 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6429 13:53:39.750160
6430 13:53:39.753374 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6431 13:53:39.756488 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6432 13:53:39.759460 [Gating] SW calibration Done
6433 13:53:39.759544 ==
6434 13:53:39.762798 Dram Type= 6, Freq= 0, CH_0, rank 1
6435 13:53:39.765991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 13:53:39.766076 ==
6437 13:53:39.766159 RX Vref Scan: 0
6438 13:53:39.766238
6439 13:53:39.769519 RX Vref 0 -> 0, step: 1
6440 13:53:39.769602
6441 13:53:39.772928 RX Delay -410 -> 252, step: 16
6442 13:53:39.775935 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6443 13:53:39.782792 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6444 13:53:39.786501 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6445 13:53:39.789383 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6446 13:53:39.792889 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6447 13:53:39.799386 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6448 13:53:39.802916 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6449 13:53:39.806356 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6450 13:53:39.809141 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6451 13:53:39.812890 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6452 13:53:39.819589 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6453 13:53:39.822893 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6454 13:53:39.825833 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6455 13:53:39.832531 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6456 13:53:39.836058 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6457 13:53:39.839294 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6458 13:53:39.839378 ==
6459 13:53:39.842675 Dram Type= 6, Freq= 0, CH_0, rank 1
6460 13:53:39.846033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 13:53:39.849628 ==
6462 13:53:39.849712 DQS Delay:
6463 13:53:39.849795 DQS0 = 19, DQS1 = 35
6464 13:53:39.853044 DQM Delay:
6465 13:53:39.853128 DQM0 = 5, DQM1 = 11
6466 13:53:39.855958 DQ Delay:
6467 13:53:39.856041 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6468 13:53:39.859526 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6469 13:53:39.862403 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6470 13:53:39.866035 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6471 13:53:39.866118
6472 13:53:39.866202
6473 13:53:39.866281 ==
6474 13:53:39.869539 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 13:53:39.875834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 13:53:39.875918 ==
6477 13:53:39.876003
6478 13:53:39.876082
6479 13:53:39.876159 TX Vref Scan disable
6480 13:53:39.879648 == TX Byte 0 ==
6481 13:53:39.882629 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6482 13:53:39.886226 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6483 13:53:39.889436 == TX Byte 1 ==
6484 13:53:39.892722 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6485 13:53:39.896266 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6486 13:53:39.896359 ==
6487 13:53:39.899091 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 13:53:39.906258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 13:53:39.906344 ==
6490 13:53:39.906436
6491 13:53:39.906516
6492 13:53:39.906611 TX Vref Scan disable
6493 13:53:39.909040 == TX Byte 0 ==
6494 13:53:39.912495 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6495 13:53:39.916045 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6496 13:53:39.918925 == TX Byte 1 ==
6497 13:53:39.922334 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6498 13:53:39.926255 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6499 13:53:39.926340
6500 13:53:39.928901 [DATLAT]
6501 13:53:39.928985 Freq=400, CH0 RK1
6502 13:53:39.929070
6503 13:53:39.932128 DATLAT Default: 0xe
6504 13:53:39.932214 0, 0xFFFF, sum = 0
6505 13:53:39.935606 1, 0xFFFF, sum = 0
6506 13:53:39.935692 2, 0xFFFF, sum = 0
6507 13:53:39.939273 3, 0xFFFF, sum = 0
6508 13:53:39.939358 4, 0xFFFF, sum = 0
6509 13:53:39.942767 5, 0xFFFF, sum = 0
6510 13:53:39.942852 6, 0xFFFF, sum = 0
6511 13:53:39.946180 7, 0xFFFF, sum = 0
6512 13:53:39.946266 8, 0xFFFF, sum = 0
6513 13:53:39.949550 9, 0xFFFF, sum = 0
6514 13:53:39.949635 10, 0xFFFF, sum = 0
6515 13:53:39.952880 11, 0xFFFF, sum = 0
6516 13:53:39.956191 12, 0xFFFF, sum = 0
6517 13:53:39.956275 13, 0x0, sum = 1
6518 13:53:39.956413 14, 0x0, sum = 2
6519 13:53:39.959499 15, 0x0, sum = 3
6520 13:53:39.959581 16, 0x0, sum = 4
6521 13:53:39.962414 best_step = 14
6522 13:53:39.962494
6523 13:53:39.962558 ==
6524 13:53:39.965848 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 13:53:39.969264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 13:53:39.969346 ==
6527 13:53:39.972839 RX Vref Scan: 0
6528 13:53:39.972920
6529 13:53:39.972983 RX Vref 0 -> 0, step: 1
6530 13:53:39.973042
6531 13:53:39.975620 RX Delay -311 -> 252, step: 8
6532 13:53:39.984078 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6533 13:53:39.987489 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6534 13:53:39.990282 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6535 13:53:39.994441 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6536 13:53:40.000352 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6537 13:53:40.003632 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6538 13:53:40.006979 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6539 13:53:40.010283 iDelay=217, Bit 7, Center -4 (-223 ~ 216) 440
6540 13:53:40.019491 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6541 13:53:40.020211 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6542 13:53:40.023590 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6543 13:53:40.027316 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6544 13:53:40.033969 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6545 13:53:40.036811 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6546 13:53:40.040089 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6547 13:53:40.047065 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6548 13:53:40.047174 ==
6549 13:53:40.050055 Dram Type= 6, Freq= 0, CH_0, rank 1
6550 13:53:40.053711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6551 13:53:40.053811 ==
6552 13:53:40.053901 DQS Delay:
6553 13:53:40.057082 DQS0 = 24, DQS1 = 32
6554 13:53:40.057183 DQM Delay:
6555 13:53:40.060431 DQM0 = 8, DQM1 = 10
6556 13:53:40.060506 DQ Delay:
6557 13:53:40.063570 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6558 13:53:40.066930 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =20
6559 13:53:40.070285 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6560 13:53:40.073739 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6561 13:53:40.073834
6562 13:53:40.073930
6563 13:53:40.080414 [DQSOSCAuto] RK1, (LSB)MR18= 0xbd5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6564 13:53:40.083117 CH0 RK1: MR19=C0C, MR18=BD5C
6565 13:53:40.090059 CH0_RK1: MR19=0xC0C, MR18=0xBD5C, DQSOSC=386, MR23=63, INC=396, DEC=264
6566 13:53:40.093665 [RxdqsGatingPostProcess] freq 400
6567 13:53:40.096413 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6568 13:53:40.099938 best DQS0 dly(2T, 0.5T) = (0, 10)
6569 13:53:40.103411 best DQS1 dly(2T, 0.5T) = (0, 10)
6570 13:53:40.106384 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6571 13:53:40.109660 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6572 13:53:40.113180 best DQS0 dly(2T, 0.5T) = (0, 10)
6573 13:53:40.116659 best DQS1 dly(2T, 0.5T) = (0, 10)
6574 13:53:40.120068 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6575 13:53:40.123346 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6576 13:53:40.126537 Pre-setting of DQS Precalculation
6577 13:53:40.129937 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6578 13:53:40.132793 ==
6579 13:53:40.136198 Dram Type= 6, Freq= 0, CH_1, rank 0
6580 13:53:40.140153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6581 13:53:40.140239 ==
6582 13:53:40.143449 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6583 13:53:40.149651 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6584 13:53:40.153047 [CA 0] Center 36 (8~64) winsize 57
6585 13:53:40.156632 [CA 1] Center 36 (8~64) winsize 57
6586 13:53:40.159632 [CA 2] Center 36 (8~64) winsize 57
6587 13:53:40.163371 [CA 3] Center 36 (8~64) winsize 57
6588 13:53:40.166316 [CA 4] Center 36 (8~64) winsize 57
6589 13:53:40.169654 [CA 5] Center 36 (8~64) winsize 57
6590 13:53:40.169734
6591 13:53:40.173066 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6592 13:53:40.173147
6593 13:53:40.176399 [CATrainingPosCal] consider 1 rank data
6594 13:53:40.179744 u2DelayCellTimex100 = 270/100 ps
6595 13:53:40.182620 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6596 13:53:40.186102 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 13:53:40.189800 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6598 13:53:40.192595 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 13:53:40.199009 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 13:53:40.202607 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 13:53:40.202688
6602 13:53:40.206000 CA PerBit enable=1, Macro0, CA PI delay=36
6603 13:53:40.206081
6604 13:53:40.209503 [CBTSetCACLKResult] CA Dly = 36
6605 13:53:40.209584 CS Dly: 1 (0~32)
6606 13:53:40.209648 ==
6607 13:53:40.212231 Dram Type= 6, Freq= 0, CH_1, rank 1
6608 13:53:40.219329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 13:53:40.219410 ==
6610 13:53:40.222320 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6611 13:53:40.229540 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6612 13:53:40.232806 [CA 0] Center 36 (8~64) winsize 57
6613 13:53:40.236066 [CA 1] Center 36 (8~64) winsize 57
6614 13:53:40.239296 [CA 2] Center 36 (8~64) winsize 57
6615 13:53:40.242541 [CA 3] Center 36 (8~64) winsize 57
6616 13:53:40.245865 [CA 4] Center 36 (8~64) winsize 57
6617 13:53:40.249181 [CA 5] Center 36 (8~64) winsize 57
6618 13:53:40.249265
6619 13:53:40.252473 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6620 13:53:40.252557
6621 13:53:40.255632 [CATrainingPosCal] consider 2 rank data
6622 13:53:40.258983 u2DelayCellTimex100 = 270/100 ps
6623 13:53:40.262494 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 13:53:40.265985 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 13:53:40.269026 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 13:53:40.272484 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 13:53:40.275461 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 13:53:40.278893 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 13:53:40.278976
6630 13:53:40.285482 CA PerBit enable=1, Macro0, CA PI delay=36
6631 13:53:40.285565
6632 13:53:40.288956 [CBTSetCACLKResult] CA Dly = 36
6633 13:53:40.289039 CS Dly: 1 (0~32)
6634 13:53:40.289123
6635 13:53:40.292430 ----->DramcWriteLeveling(PI) begin...
6636 13:53:40.292514 ==
6637 13:53:40.295905 Dram Type= 6, Freq= 0, CH_1, rank 0
6638 13:53:40.298786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6639 13:53:40.298871 ==
6640 13:53:40.302455 Write leveling (Byte 0): 40 => 8
6641 13:53:40.305690 Write leveling (Byte 1): 40 => 8
6642 13:53:40.308523 DramcWriteLeveling(PI) end<-----
6643 13:53:40.308606
6644 13:53:40.308689 ==
6645 13:53:40.312032 Dram Type= 6, Freq= 0, CH_1, rank 0
6646 13:53:40.318967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 13:53:40.319050 ==
6648 13:53:40.319133 [Gating] SW mode calibration
6649 13:53:40.328209 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6650 13:53:40.331954 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6651 13:53:40.334799 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6652 13:53:40.341885 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6653 13:53:40.345343 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6654 13:53:40.348665 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6655 13:53:40.355339 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6656 13:53:40.358633 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6657 13:53:40.361802 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6658 13:53:40.368044 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 13:53:40.371935 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6660 13:53:40.375072 Total UI for P1: 0, mck2ui 16
6661 13:53:40.378548 best dqsien dly found for B0: ( 0, 14, 24)
6662 13:53:40.381424 Total UI for P1: 0, mck2ui 16
6663 13:53:40.385107 best dqsien dly found for B1: ( 0, 14, 24)
6664 13:53:40.388628 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6665 13:53:40.392013 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6666 13:53:40.392098
6667 13:53:40.395287 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6668 13:53:40.398691 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6669 13:53:40.401615 [Gating] SW calibration Done
6670 13:53:40.401714 ==
6671 13:53:40.405240 Dram Type= 6, Freq= 0, CH_1, rank 0
6672 13:53:40.411692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6673 13:53:40.411777 ==
6674 13:53:40.411860 RX Vref Scan: 0
6675 13:53:40.411938
6676 13:53:40.415318 RX Vref 0 -> 0, step: 1
6677 13:53:40.415401
6678 13:53:40.418127 RX Delay -410 -> 252, step: 16
6679 13:53:40.421526 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6680 13:53:40.424991 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6681 13:53:40.428594 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6682 13:53:40.435011 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6683 13:53:40.438549 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6684 13:53:40.441362 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6685 13:53:40.444835 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6686 13:53:40.451281 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6687 13:53:40.454846 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6688 13:53:40.458193 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6689 13:53:40.461567 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6690 13:53:40.468024 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6691 13:53:40.471423 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6692 13:53:40.474886 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6693 13:53:40.480910 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6694 13:53:40.484715 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6695 13:53:40.484798 ==
6696 13:53:40.487850 Dram Type= 6, Freq= 0, CH_1, rank 0
6697 13:53:40.490990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 13:53:40.491073 ==
6699 13:53:40.494667 DQS Delay:
6700 13:53:40.494750 DQS0 = 35, DQS1 = 35
6701 13:53:40.494834 DQM Delay:
6702 13:53:40.497430 DQM0 = 17, DQM1 = 13
6703 13:53:40.497512 DQ Delay:
6704 13:53:40.500960 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6705 13:53:40.504808 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6706 13:53:40.508032 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6707 13:53:40.511189 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6708 13:53:40.511283
6709 13:53:40.511407
6710 13:53:40.511500 ==
6711 13:53:40.514801 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 13:53:40.517620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 13:53:40.521131 ==
6714 13:53:40.521214
6715 13:53:40.521295
6716 13:53:40.521410 TX Vref Scan disable
6717 13:53:40.524484 == TX Byte 0 ==
6718 13:53:40.527383 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6719 13:53:40.530834 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6720 13:53:40.534259 == TX Byte 1 ==
6721 13:53:40.537877 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6722 13:53:40.541357 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6723 13:53:40.541477 ==
6724 13:53:40.544199 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 13:53:40.547890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 13:53:40.551365 ==
6727 13:53:40.551448
6728 13:53:40.551513
6729 13:53:40.551572 TX Vref Scan disable
6730 13:53:40.554138 == TX Byte 0 ==
6731 13:53:40.557776 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6732 13:53:40.561428 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6733 13:53:40.564067 == TX Byte 1 ==
6734 13:53:40.567635 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 13:53:40.571075 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 13:53:40.571155
6737 13:53:40.574539 [DATLAT]
6738 13:53:40.574619 Freq=400, CH1 RK0
6739 13:53:40.574682
6740 13:53:40.577400 DATLAT Default: 0xf
6741 13:53:40.577480 0, 0xFFFF, sum = 0
6742 13:53:40.580829 1, 0xFFFF, sum = 0
6743 13:53:40.580910 2, 0xFFFF, sum = 0
6744 13:53:40.584441 3, 0xFFFF, sum = 0
6745 13:53:40.584522 4, 0xFFFF, sum = 0
6746 13:53:40.587900 5, 0xFFFF, sum = 0
6747 13:53:40.587981 6, 0xFFFF, sum = 0
6748 13:53:40.590716 7, 0xFFFF, sum = 0
6749 13:53:40.590798 8, 0xFFFF, sum = 0
6750 13:53:40.594181 9, 0xFFFF, sum = 0
6751 13:53:40.594263 10, 0xFFFF, sum = 0
6752 13:53:40.597871 11, 0xFFFF, sum = 0
6753 13:53:40.597954 12, 0xFFFF, sum = 0
6754 13:53:40.601151 13, 0x0, sum = 1
6755 13:53:40.601232 14, 0x0, sum = 2
6756 13:53:40.604425 15, 0x0, sum = 3
6757 13:53:40.604507 16, 0x0, sum = 4
6758 13:53:40.607788 best_step = 14
6759 13:53:40.607893
6760 13:53:40.607981 ==
6761 13:53:40.611296 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 13:53:40.614537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 13:53:40.614617 ==
6764 13:53:40.617989 RX Vref Scan: 1
6765 13:53:40.618069
6766 13:53:40.618132 RX Vref 0 -> 0, step: 1
6767 13:53:40.618191
6768 13:53:40.621262 RX Delay -311 -> 252, step: 8
6769 13:53:40.621342
6770 13:53:40.624309 Set Vref, RX VrefLevel [Byte0]: 53
6771 13:53:40.627629 [Byte1]: 48
6772 13:53:40.632298
6773 13:53:40.632429 Final RX Vref Byte 0 = 53 to rank0
6774 13:53:40.635087 Final RX Vref Byte 1 = 48 to rank0
6775 13:53:40.638591 Final RX Vref Byte 0 = 53 to rank1
6776 13:53:40.641973 Final RX Vref Byte 1 = 48 to rank1==
6777 13:53:40.645518 Dram Type= 6, Freq= 0, CH_1, rank 0
6778 13:53:40.652066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6779 13:53:40.652148 ==
6780 13:53:40.652211 DQS Delay:
6781 13:53:40.654828 DQS0 = 32, DQS1 = 32
6782 13:53:40.654911 DQM Delay:
6783 13:53:40.654975 DQM0 = 13, DQM1 = 11
6784 13:53:40.658324 DQ Delay:
6785 13:53:40.661751 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6786 13:53:40.665362 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6787 13:53:40.665443 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6788 13:53:40.668165 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6789 13:53:40.671652
6790 13:53:40.671744
6791 13:53:40.678504 [DQSOSCAuto] RK0, (LSB)MR18= 0x94cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6792 13:53:40.681498 CH1 RK0: MR19=C0C, MR18=94CC
6793 13:53:40.688291 CH1_RK0: MR19=0xC0C, MR18=0x94CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6794 13:53:40.688423 ==
6795 13:53:40.691339 Dram Type= 6, Freq= 0, CH_1, rank 1
6796 13:53:40.694879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 13:53:40.694958 ==
6798 13:53:40.697777 [Gating] SW mode calibration
6799 13:53:40.704777 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6800 13:53:40.710943 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6801 13:53:40.714356 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6802 13:53:40.717685 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6803 13:53:40.724429 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6804 13:53:40.728030 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6805 13:53:40.731442 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6806 13:53:40.737567 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6807 13:53:40.740903 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6808 13:53:40.744548 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6809 13:53:40.750648 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6810 13:53:40.750731 Total UI for P1: 0, mck2ui 16
6811 13:53:40.757902 best dqsien dly found for B0: ( 0, 14, 24)
6812 13:53:40.757983 Total UI for P1: 0, mck2ui 16
6813 13:53:40.760658 best dqsien dly found for B1: ( 0, 14, 24)
6814 13:53:40.767805 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6815 13:53:40.770689 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6816 13:53:40.770769
6817 13:53:40.774384 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6818 13:53:40.777245 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6819 13:53:40.780604 [Gating] SW calibration Done
6820 13:53:40.780685 ==
6821 13:53:40.783902 Dram Type= 6, Freq= 0, CH_1, rank 1
6822 13:53:40.787346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 13:53:40.787427 ==
6824 13:53:40.790693 RX Vref Scan: 0
6825 13:53:40.790773
6826 13:53:40.790839 RX Vref 0 -> 0, step: 1
6827 13:53:40.790898
6828 13:53:40.794097 RX Delay -410 -> 252, step: 16
6829 13:53:40.801257 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6830 13:53:40.804130 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6831 13:53:40.807614 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6832 13:53:40.811172 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6833 13:53:40.817746 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6834 13:53:40.820597 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6835 13:53:40.824138 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6836 13:53:40.827431 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6837 13:53:40.830790 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6838 13:53:40.837250 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6839 13:53:40.840644 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6840 13:53:40.844046 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6841 13:53:40.850491 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6842 13:53:40.853965 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6843 13:53:40.857185 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6844 13:53:40.860608 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6845 13:53:40.860710 ==
6846 13:53:40.864059 Dram Type= 6, Freq= 0, CH_1, rank 1
6847 13:53:40.870481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 13:53:40.870618 ==
6849 13:53:40.870724 DQS Delay:
6850 13:53:40.874146 DQS0 = 35, DQS1 = 35
6851 13:53:40.874243 DQM Delay:
6852 13:53:40.874326 DQM0 = 17, DQM1 = 13
6853 13:53:40.877066 DQ Delay:
6854 13:53:40.880701 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6855 13:53:40.884334 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6856 13:53:40.887274 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6857 13:53:40.890706 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6858 13:53:40.890804
6859 13:53:40.890898
6860 13:53:40.890973 ==
6861 13:53:40.893962 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 13:53:40.897678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 13:53:40.897760 ==
6864 13:53:40.897825
6865 13:53:40.897885
6866 13:53:40.900830 TX Vref Scan disable
6867 13:53:40.900913 == TX Byte 0 ==
6868 13:53:40.904254 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6869 13:53:40.910804 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6870 13:53:40.910891 == TX Byte 1 ==
6871 13:53:40.914100 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6872 13:53:40.920517 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6873 13:53:40.920601 ==
6874 13:53:40.924124 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 13:53:40.927061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 13:53:40.927144 ==
6877 13:53:40.927209
6878 13:53:40.927270
6879 13:53:40.930607 TX Vref Scan disable
6880 13:53:40.930729 == TX Byte 0 ==
6881 13:53:40.934130 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6882 13:53:40.940329 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6883 13:53:40.940426 == TX Byte 1 ==
6884 13:53:40.943697 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6885 13:53:40.950819 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6886 13:53:40.950908
6887 13:53:40.950972 [DATLAT]
6888 13:53:40.951033 Freq=400, CH1 RK1
6889 13:53:40.953990
6890 13:53:40.954073 DATLAT Default: 0xe
6891 13:53:40.957378 0, 0xFFFF, sum = 0
6892 13:53:40.957472 1, 0xFFFF, sum = 0
6893 13:53:40.960778 2, 0xFFFF, sum = 0
6894 13:53:40.960852 3, 0xFFFF, sum = 0
6895 13:53:40.964095 4, 0xFFFF, sum = 0
6896 13:53:40.964169 5, 0xFFFF, sum = 0
6897 13:53:40.966844 6, 0xFFFF, sum = 0
6898 13:53:40.966917 7, 0xFFFF, sum = 0
6899 13:53:40.970885 8, 0xFFFF, sum = 0
6900 13:53:40.970960 9, 0xFFFF, sum = 0
6901 13:53:40.974096 10, 0xFFFF, sum = 0
6902 13:53:40.974167 11, 0xFFFF, sum = 0
6903 13:53:40.977543 12, 0xFFFF, sum = 0
6904 13:53:40.977610 13, 0x0, sum = 1
6905 13:53:40.980225 14, 0x0, sum = 2
6906 13:53:40.980301 15, 0x0, sum = 3
6907 13:53:40.983554 16, 0x0, sum = 4
6908 13:53:40.983625 best_step = 14
6909 13:53:40.983684
6910 13:53:40.983739 ==
6911 13:53:40.987224 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 13:53:40.993666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 13:53:40.993741 ==
6914 13:53:40.993801 RX Vref Scan: 0
6915 13:53:40.993859
6916 13:53:40.997326 RX Vref 0 -> 0, step: 1
6917 13:53:40.997393
6918 13:53:41.000092 RX Delay -311 -> 252, step: 8
6919 13:53:41.007146 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6920 13:53:41.010289 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6921 13:53:41.013406 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6922 13:53:41.017359 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6923 13:53:41.023787 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6924 13:53:41.026783 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6925 13:53:41.030318 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6926 13:53:41.033950 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6927 13:53:41.036978 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6928 13:53:41.043254 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6929 13:53:41.046777 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6930 13:53:41.050348 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6931 13:53:41.053808 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6932 13:53:41.060022 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6933 13:53:41.063378 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6934 13:53:41.066545 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6935 13:53:41.066629 ==
6936 13:53:41.069969 Dram Type= 6, Freq= 0, CH_1, rank 1
6937 13:53:41.077014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6938 13:53:41.077100 ==
6939 13:53:41.077166 DQS Delay:
6940 13:53:41.080309 DQS0 = 28, DQS1 = 36
6941 13:53:41.080401 DQM Delay:
6942 13:53:41.083685 DQM0 = 10, DQM1 = 14
6943 13:53:41.083769 DQ Delay:
6944 13:53:41.087033 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6945 13:53:41.090196 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6946 13:53:41.090280 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6947 13:53:41.096533 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6948 13:53:41.096615
6949 13:53:41.096679
6950 13:53:41.103046 [DQSOSCAuto] RK1, (LSB)MR18= 0xc151, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6951 13:53:41.106660 CH1 RK1: MR19=C0C, MR18=C151
6952 13:53:41.113259 CH1_RK1: MR19=0xC0C, MR18=0xC151, DQSOSC=385, MR23=63, INC=398, DEC=265
6953 13:53:41.116665 [RxdqsGatingPostProcess] freq 400
6954 13:53:41.120084 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6955 13:53:41.123317 best DQS0 dly(2T, 0.5T) = (0, 10)
6956 13:53:41.126555 best DQS1 dly(2T, 0.5T) = (0, 10)
6957 13:53:41.129802 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6958 13:53:41.133268 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6959 13:53:41.136081 best DQS0 dly(2T, 0.5T) = (0, 10)
6960 13:53:41.139823 best DQS1 dly(2T, 0.5T) = (0, 10)
6961 13:53:41.143278 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6962 13:53:41.146883 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6963 13:53:41.149518 Pre-setting of DQS Precalculation
6964 13:53:41.153032 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6965 13:53:41.162690 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6966 13:53:41.169705 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6967 13:53:41.169794
6968 13:53:41.169858
6969 13:53:41.173207 [Calibration Summary] 800 Mbps
6970 13:53:41.173289 CH 0, Rank 0
6971 13:53:41.175994 SW Impedance : PASS
6972 13:53:41.176079 DUTY Scan : NO K
6973 13:53:41.179416 ZQ Calibration : PASS
6974 13:53:41.182717 Jitter Meter : NO K
6975 13:53:41.182799 CBT Training : PASS
6976 13:53:41.186187 Write leveling : PASS
6977 13:53:41.189548 RX DQS gating : PASS
6978 13:53:41.189629 RX DQ/DQS(RDDQC) : PASS
6979 13:53:41.192921 TX DQ/DQS : PASS
6980 13:53:41.193002 RX DATLAT : PASS
6981 13:53:41.196074 RX DQ/DQS(Engine): PASS
6982 13:53:41.199404 TX OE : NO K
6983 13:53:41.199486 All Pass.
6984 13:53:41.199550
6985 13:53:41.199623 CH 0, Rank 1
6986 13:53:41.203096 SW Impedance : PASS
6987 13:53:41.206247 DUTY Scan : NO K
6988 13:53:41.206374 ZQ Calibration : PASS
6989 13:53:41.209716 Jitter Meter : NO K
6990 13:53:41.212535 CBT Training : PASS
6991 13:53:41.212607 Write leveling : NO K
6992 13:53:41.215985 RX DQS gating : PASS
6993 13:53:41.219540 RX DQ/DQS(RDDQC) : PASS
6994 13:53:41.219632 TX DQ/DQS : PASS
6995 13:53:41.222465 RX DATLAT : PASS
6996 13:53:41.225994 RX DQ/DQS(Engine): PASS
6997 13:53:41.226063 TX OE : NO K
6998 13:53:41.229327 All Pass.
6999 13:53:41.229431
7000 13:53:41.229519 CH 1, Rank 0
7001 13:53:41.232495 SW Impedance : PASS
7002 13:53:41.232593 DUTY Scan : NO K
7003 13:53:41.235652 ZQ Calibration : PASS
7004 13:53:41.239525 Jitter Meter : NO K
7005 13:53:41.239607 CBT Training : PASS
7006 13:53:41.242947 Write leveling : PASS
7007 13:53:41.243054 RX DQS gating : PASS
7008 13:53:41.245767 RX DQ/DQS(RDDQC) : PASS
7009 13:53:41.249402 TX DQ/DQS : PASS
7010 13:53:41.249473 RX DATLAT : PASS
7011 13:53:41.252880 RX DQ/DQS(Engine): PASS
7012 13:53:41.255659 TX OE : NO K
7013 13:53:41.255769 All Pass.
7014 13:53:41.255857
7015 13:53:41.255951 CH 1, Rank 1
7016 13:53:41.259233 SW Impedance : PASS
7017 13:53:41.262670 DUTY Scan : NO K
7018 13:53:41.262754 ZQ Calibration : PASS
7019 13:53:41.266292 Jitter Meter : NO K
7020 13:53:41.269644 CBT Training : PASS
7021 13:53:41.269726 Write leveling : NO K
7022 13:53:41.272533 RX DQS gating : PASS
7023 13:53:41.275840 RX DQ/DQS(RDDQC) : PASS
7024 13:53:41.275921 TX DQ/DQS : PASS
7025 13:53:41.279394 RX DATLAT : PASS
7026 13:53:41.282829 RX DQ/DQS(Engine): PASS
7027 13:53:41.282939 TX OE : NO K
7028 13:53:41.283033 All Pass.
7029 13:53:41.285774
7030 13:53:41.285872 DramC Write-DBI off
7031 13:53:41.289309 PER_BANK_REFRESH: Hybrid Mode
7032 13:53:41.289410 TX_TRACKING: ON
7033 13:53:41.299036 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7034 13:53:41.302395 [FAST_K] Save calibration result to emmc
7035 13:53:41.306017 dramc_set_vcore_voltage set vcore to 725000
7036 13:53:41.308809 Read voltage for 1600, 0
7037 13:53:41.308891 Vio18 = 0
7038 13:53:41.312683 Vcore = 725000
7039 13:53:41.312788 Vdram = 0
7040 13:53:41.312867 Vddq = 0
7041 13:53:41.312943 Vmddr = 0
7042 13:53:41.318887 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7043 13:53:41.325850 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7044 13:53:41.325980 MEM_TYPE=3, freq_sel=13
7045 13:53:41.329370 sv_algorithm_assistance_LP4_3733
7046 13:53:41.332192 ============ PULL DRAM RESETB DOWN ============
7047 13:53:41.339286 ========== PULL DRAM RESETB DOWN end =========
7048 13:53:41.342562 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7049 13:53:41.345795 ===================================
7050 13:53:41.349055 LPDDR4 DRAM CONFIGURATION
7051 13:53:41.352293 ===================================
7052 13:53:41.352423 EX_ROW_EN[0] = 0x0
7053 13:53:41.355765 EX_ROW_EN[1] = 0x0
7054 13:53:41.355863 LP4Y_EN = 0x0
7055 13:53:41.358666 WORK_FSP = 0x1
7056 13:53:41.358761 WL = 0x5
7057 13:53:41.362135 RL = 0x5
7058 13:53:41.365641 BL = 0x2
7059 13:53:41.365743 RPST = 0x0
7060 13:53:41.369084 RD_PRE = 0x0
7061 13:53:41.369158 WR_PRE = 0x1
7062 13:53:41.372540 WR_PST = 0x1
7063 13:53:41.372636 DBI_WR = 0x0
7064 13:53:41.375369 DBI_RD = 0x0
7065 13:53:41.375463 OTF = 0x1
7066 13:53:41.378976 ===================================
7067 13:53:41.382346 ===================================
7068 13:53:41.385895 ANA top config
7069 13:53:41.388703 ===================================
7070 13:53:41.388799 DLL_ASYNC_EN = 0
7071 13:53:41.392425 ALL_SLAVE_EN = 0
7072 13:53:41.395804 NEW_RANK_MODE = 1
7073 13:53:41.399267 DLL_IDLE_MODE = 1
7074 13:53:41.399366 LP45_APHY_COMB_EN = 1
7075 13:53:41.402158 TX_ODT_DIS = 0
7076 13:53:41.405741 NEW_8X_MODE = 1
7077 13:53:41.408601 ===================================
7078 13:53:41.412202 ===================================
7079 13:53:41.415599 data_rate = 3200
7080 13:53:41.419319 CKR = 1
7081 13:53:41.419417 DQ_P2S_RATIO = 8
7082 13:53:41.422058 ===================================
7083 13:53:41.425244 CA_P2S_RATIO = 8
7084 13:53:41.428645 DQ_CA_OPEN = 0
7085 13:53:41.432293 DQ_SEMI_OPEN = 0
7086 13:53:41.435583 CA_SEMI_OPEN = 0
7087 13:53:41.439014 CA_FULL_RATE = 0
7088 13:53:41.439115 DQ_CKDIV4_EN = 0
7089 13:53:41.441803 CA_CKDIV4_EN = 0
7090 13:53:41.445360 CA_PREDIV_EN = 0
7091 13:53:41.448655 PH8_DLY = 12
7092 13:53:41.452186 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7093 13:53:41.455424 DQ_AAMCK_DIV = 4
7094 13:53:41.455495 CA_AAMCK_DIV = 4
7095 13:53:41.458774 CA_ADMCK_DIV = 4
7096 13:53:41.462122 DQ_TRACK_CA_EN = 0
7097 13:53:41.465780 CA_PICK = 1600
7098 13:53:41.468634 CA_MCKIO = 1600
7099 13:53:41.472019 MCKIO_SEMI = 0
7100 13:53:41.475596 PLL_FREQ = 3068
7101 13:53:41.475668 DQ_UI_PI_RATIO = 32
7102 13:53:41.478915 CA_UI_PI_RATIO = 0
7103 13:53:41.482258 ===================================
7104 13:53:41.485609 ===================================
7105 13:53:41.488433 memory_type:LPDDR4
7106 13:53:41.491973 GP_NUM : 10
7107 13:53:41.492070 SRAM_EN : 1
7108 13:53:41.495622 MD32_EN : 0
7109 13:53:41.498486 ===================================
7110 13:53:41.501980 [ANA_INIT] >>>>>>>>>>>>>>
7111 13:53:41.502052 <<<<<< [CONFIGURE PHASE]: ANA_TX
7112 13:53:41.505533 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7113 13:53:41.509097 ===================================
7114 13:53:41.511850 data_rate = 3200,PCW = 0X7600
7115 13:53:41.515384 ===================================
7116 13:53:41.518969 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7117 13:53:41.525434 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7118 13:53:41.531658 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7119 13:53:41.535053 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7120 13:53:41.538343 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7121 13:53:41.541756 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7122 13:53:41.545003 [ANA_INIT] flow start
7123 13:53:41.545105 [ANA_INIT] PLL >>>>>>>>
7124 13:53:41.548102 [ANA_INIT] PLL <<<<<<<<
7125 13:53:41.552003 [ANA_INIT] MIDPI >>>>>>>>
7126 13:53:41.552173 [ANA_INIT] MIDPI <<<<<<<<
7127 13:53:41.555296 [ANA_INIT] DLL >>>>>>>>
7128 13:53:41.558689 [ANA_INIT] DLL <<<<<<<<
7129 13:53:41.558794 [ANA_INIT] flow end
7130 13:53:41.564871 ============ LP4 DIFF to SE enter ============
7131 13:53:41.568319 ============ LP4 DIFF to SE exit ============
7132 13:53:41.571893 [ANA_INIT] <<<<<<<<<<<<<
7133 13:53:41.574625 [Flow] Enable top DCM control >>>>>
7134 13:53:41.578095 [Flow] Enable top DCM control <<<<<
7135 13:53:41.578199 Enable DLL master slave shuffle
7136 13:53:41.585132 ==============================================================
7137 13:53:41.587956 Gating Mode config
7138 13:53:41.591694 ==============================================================
7139 13:53:41.594838 Config description:
7140 13:53:41.604552 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7141 13:53:41.611663 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7142 13:53:41.614509 SELPH_MODE 0: By rank 1: By Phase
7143 13:53:41.621732 ==============================================================
7144 13:53:41.624536 GAT_TRACK_EN = 1
7145 13:53:41.628205 RX_GATING_MODE = 2
7146 13:53:41.631055 RX_GATING_TRACK_MODE = 2
7147 13:53:41.634563 SELPH_MODE = 1
7148 13:53:41.634637 PICG_EARLY_EN = 1
7149 13:53:41.638185 VALID_LAT_VALUE = 1
7150 13:53:41.644556 ==============================================================
7151 13:53:41.647937 Enter into Gating configuration >>>>
7152 13:53:41.651486 Exit from Gating configuration <<<<
7153 13:53:41.654981 Enter into DVFS_PRE_config >>>>>
7154 13:53:41.664880 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7155 13:53:41.667852 Exit from DVFS_PRE_config <<<<<
7156 13:53:41.671227 Enter into PICG configuration >>>>
7157 13:53:41.675004 Exit from PICG configuration <<<<
7158 13:53:41.678199 [RX_INPUT] configuration >>>>>
7159 13:53:41.681556 [RX_INPUT] configuration <<<<<
7160 13:53:41.684883 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7161 13:53:41.691076 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7162 13:53:41.698011 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7163 13:53:41.704444 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7164 13:53:41.711023 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7165 13:53:41.714981 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7166 13:53:41.721373 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7167 13:53:41.724210 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7168 13:53:41.727652 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7169 13:53:41.731239 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7170 13:53:41.737664 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7171 13:53:41.741267 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7172 13:53:41.744118 ===================================
7173 13:53:41.747801 LPDDR4 DRAM CONFIGURATION
7174 13:53:41.751166 ===================================
7175 13:53:41.751268 EX_ROW_EN[0] = 0x0
7176 13:53:41.754028 EX_ROW_EN[1] = 0x0
7177 13:53:41.754122 LP4Y_EN = 0x0
7178 13:53:41.757581 WORK_FSP = 0x1
7179 13:53:41.757680 WL = 0x5
7180 13:53:41.761017 RL = 0x5
7181 13:53:41.761115 BL = 0x2
7182 13:53:41.763742 RPST = 0x0
7183 13:53:41.767187 RD_PRE = 0x0
7184 13:53:41.767285 WR_PRE = 0x1
7185 13:53:41.770800 WR_PST = 0x1
7186 13:53:41.770903 DBI_WR = 0x0
7187 13:53:41.773772 DBI_RD = 0x0
7188 13:53:41.773868 OTF = 0x1
7189 13:53:41.777153 ===================================
7190 13:53:41.780290 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7191 13:53:41.787662 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7192 13:53:41.790185 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7193 13:53:41.793365 ===================================
7194 13:53:41.797201 LPDDR4 DRAM CONFIGURATION
7195 13:53:41.800403 ===================================
7196 13:53:41.800503 EX_ROW_EN[0] = 0x10
7197 13:53:41.803421 EX_ROW_EN[1] = 0x0
7198 13:53:41.803520 LP4Y_EN = 0x0
7199 13:53:41.806885 WORK_FSP = 0x1
7200 13:53:41.806981 WL = 0x5
7201 13:53:41.810228 RL = 0x5
7202 13:53:41.813798 BL = 0x2
7203 13:53:41.813896 RPST = 0x0
7204 13:53:41.816638 RD_PRE = 0x0
7205 13:53:41.816709 WR_PRE = 0x1
7206 13:53:41.820011 WR_PST = 0x1
7207 13:53:41.820082 DBI_WR = 0x0
7208 13:53:41.823210 DBI_RD = 0x0
7209 13:53:41.823306 OTF = 0x1
7210 13:53:41.827025 ===================================
7211 13:53:41.833354 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7212 13:53:41.833430 ==
7213 13:53:41.836523 Dram Type= 6, Freq= 0, CH_0, rank 0
7214 13:53:41.840175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7215 13:53:41.840275 ==
7216 13:53:41.843058 [Duty_Offset_Calibration]
7217 13:53:41.846530 B0:2 B1:1 CA:1
7218 13:53:41.846613
7219 13:53:41.850063 [DutyScan_Calibration_Flow] k_type=0
7220 13:53:41.858420
7221 13:53:41.858500 ==CLK 0==
7222 13:53:41.862037 Final CLK duty delay cell = 0
7223 13:53:41.864795 [0] MAX Duty = 5156%(X100), DQS PI = 22
7224 13:53:41.868244 [0] MIN Duty = 4875%(X100), DQS PI = 62
7225 13:53:41.868379 [0] AVG Duty = 5015%(X100)
7226 13:53:41.871713
7227 13:53:41.875276 CH0 CLK Duty spec in!! Max-Min= 281%
7228 13:53:41.878063 [DutyScan_Calibration_Flow] ====Done====
7229 13:53:41.878144
7230 13:53:41.881599 [DutyScan_Calibration_Flow] k_type=1
7231 13:53:41.897595
7232 13:53:41.897679 ==DQS 0 ==
7233 13:53:41.901143 Final DQS duty delay cell = -4
7234 13:53:41.904548 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7235 13:53:41.907687 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7236 13:53:41.910818 [-4] AVG Duty = 4891%(X100)
7237 13:53:41.910899
7238 13:53:41.910963 ==DQS 1 ==
7239 13:53:41.914522 Final DQS duty delay cell = 0
7240 13:53:41.917395 [0] MAX Duty = 5187%(X100), DQS PI = 20
7241 13:53:41.920573 [0] MIN Duty = 5031%(X100), DQS PI = 52
7242 13:53:41.923850 [0] AVG Duty = 5109%(X100)
7243 13:53:41.923932
7244 13:53:41.927451 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7245 13:53:41.927533
7246 13:53:41.930884 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7247 13:53:41.934282 [DutyScan_Calibration_Flow] ====Done====
7248 13:53:41.934364
7249 13:53:41.937020 [DutyScan_Calibration_Flow] k_type=3
7250 13:53:41.954789
7251 13:53:41.954880 ==DQM 0 ==
7252 13:53:41.958273 Final DQM duty delay cell = 0
7253 13:53:41.961903 [0] MAX Duty = 5218%(X100), DQS PI = 34
7254 13:53:41.964743 [0] MIN Duty = 4875%(X100), DQS PI = 58
7255 13:53:41.968275 [0] AVG Duty = 5046%(X100)
7256 13:53:41.968388
7257 13:53:41.968456 ==DQM 1 ==
7258 13:53:41.971868 Final DQM duty delay cell = 0
7259 13:53:41.975195 [0] MAX Duty = 5187%(X100), DQS PI = 4
7260 13:53:41.977995 [0] MIN Duty = 5062%(X100), DQS PI = 48
7261 13:53:41.981698 [0] AVG Duty = 5124%(X100)
7262 13:53:41.981779
7263 13:53:41.984601 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7264 13:53:41.984725
7265 13:53:41.988222 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7266 13:53:41.991183 [DutyScan_Calibration_Flow] ====Done====
7267 13:53:41.991265
7268 13:53:41.994787 [DutyScan_Calibration_Flow] k_type=2
7269 13:53:42.011937
7270 13:53:42.012048 ==DQ 0 ==
7271 13:53:42.015490 Final DQ duty delay cell = 0
7272 13:53:42.018996 [0] MAX Duty = 5062%(X100), DQS PI = 26
7273 13:53:42.022244 [0] MIN Duty = 4907%(X100), DQS PI = 0
7274 13:53:42.022325 [0] AVG Duty = 4984%(X100)
7275 13:53:42.022393
7276 13:53:42.025788 ==DQ 1 ==
7277 13:53:42.028970 Final DQ duty delay cell = 0
7278 13:53:42.032139 [0] MAX Duty = 5125%(X100), DQS PI = 6
7279 13:53:42.035227 [0] MIN Duty = 4907%(X100), DQS PI = 34
7280 13:53:42.035309 [0] AVG Duty = 5016%(X100)
7281 13:53:42.035373
7282 13:53:42.038613 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7283 13:53:42.038695
7284 13:53:42.045558 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7285 13:53:42.048322 [DutyScan_Calibration_Flow] ====Done====
7286 13:53:42.048456 ==
7287 13:53:42.051827 Dram Type= 6, Freq= 0, CH_1, rank 0
7288 13:53:42.055048 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7289 13:53:42.055132 ==
7290 13:53:42.058150 [Duty_Offset_Calibration]
7291 13:53:42.058232 B0:1 B1:0 CA:0
7292 13:53:42.058296
7293 13:53:42.061599 [DutyScan_Calibration_Flow] k_type=0
7294 13:53:42.071067
7295 13:53:42.071164 ==CLK 0==
7296 13:53:42.074508 Final CLK duty delay cell = -4
7297 13:53:42.078032 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7298 13:53:42.081460 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7299 13:53:42.084948 [-4] AVG Duty = 4906%(X100)
7300 13:53:42.085033
7301 13:53:42.087846 CH1 CLK Duty spec in!! Max-Min= 125%
7302 13:53:42.091374 [DutyScan_Calibration_Flow] ====Done====
7303 13:53:42.091456
7304 13:53:42.094889 [DutyScan_Calibration_Flow] k_type=1
7305 13:53:42.111374
7306 13:53:42.111461 ==DQS 0 ==
7307 13:53:42.114704 Final DQS duty delay cell = 0
7308 13:53:42.118280 [0] MAX Duty = 5062%(X100), DQS PI = 8
7309 13:53:42.121207 [0] MIN Duty = 4844%(X100), DQS PI = 0
7310 13:53:42.121290 [0] AVG Duty = 4953%(X100)
7311 13:53:42.124826
7312 13:53:42.124908 ==DQS 1 ==
7313 13:53:42.127653 Final DQS duty delay cell = 0
7314 13:53:42.131137 [0] MAX Duty = 5249%(X100), DQS PI = 18
7315 13:53:42.134815 [0] MIN Duty = 4938%(X100), DQS PI = 8
7316 13:53:42.134918 [0] AVG Duty = 5093%(X100)
7317 13:53:42.137696
7318 13:53:42.141296 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7319 13:53:42.141379
7320 13:53:42.144957 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7321 13:53:42.148157 [DutyScan_Calibration_Flow] ====Done====
7322 13:53:42.148264
7323 13:53:42.150932 [DutyScan_Calibration_Flow] k_type=3
7324 13:53:42.168158
7325 13:53:42.168247 ==DQM 0 ==
7326 13:53:42.171328 Final DQM duty delay cell = 0
7327 13:53:42.174620 [0] MAX Duty = 5187%(X100), DQS PI = 8
7328 13:53:42.178289 [0] MIN Duty = 4969%(X100), DQS PI = 48
7329 13:53:42.178371 [0] AVG Duty = 5078%(X100)
7330 13:53:42.181255
7331 13:53:42.181336 ==DQM 1 ==
7332 13:53:42.184757 Final DQM duty delay cell = 0
7333 13:53:42.188199 [0] MAX Duty = 5062%(X100), DQS PI = 16
7334 13:53:42.191439 [0] MIN Duty = 4876%(X100), DQS PI = 52
7335 13:53:42.191524 [0] AVG Duty = 4969%(X100)
7336 13:53:42.194694
7337 13:53:42.198178 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7338 13:53:42.198262
7339 13:53:42.201065 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7340 13:53:42.204580 [DutyScan_Calibration_Flow] ====Done====
7341 13:53:42.204665
7342 13:53:42.208108 [DutyScan_Calibration_Flow] k_type=2
7343 13:53:42.224363
7344 13:53:42.224448 ==DQ 0 ==
7345 13:53:42.227352 Final DQ duty delay cell = -4
7346 13:53:42.230751 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7347 13:53:42.234387 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7348 13:53:42.237197 [-4] AVG Duty = 4968%(X100)
7349 13:53:42.237279
7350 13:53:42.237343 ==DQ 1 ==
7351 13:53:42.240770 Final DQ duty delay cell = 0
7352 13:53:42.244335 [0] MAX Duty = 5124%(X100), DQS PI = 16
7353 13:53:42.248118 [0] MIN Duty = 4938%(X100), DQS PI = 8
7354 13:53:42.248201 [0] AVG Duty = 5031%(X100)
7355 13:53:42.248266
7356 13:53:42.254211 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7357 13:53:42.254319
7358 13:53:42.257851 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7359 13:53:42.260679 [DutyScan_Calibration_Flow] ====Done====
7360 13:53:42.264220 nWR fixed to 30
7361 13:53:42.264318 [ModeRegInit_LP4] CH0 RK0
7362 13:53:42.267774 [ModeRegInit_LP4] CH0 RK1
7363 13:53:42.271183 [ModeRegInit_LP4] CH1 RK0
7364 13:53:42.273903 [ModeRegInit_LP4] CH1 RK1
7365 13:53:42.274003 match AC timing 5
7366 13:53:42.277951 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7367 13:53:42.284188 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7368 13:53:42.287705 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7369 13:53:42.290784 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7370 13:53:42.297691 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7371 13:53:42.297806 [MiockJmeterHQA]
7372 13:53:42.297901
7373 13:53:42.301037 [DramcMiockJmeter] u1RxGatingPI = 0
7374 13:53:42.304272 0 : 4258, 4029
7375 13:53:42.304414 4 : 4252, 4027
7376 13:53:42.304482 8 : 4255, 4029
7377 13:53:42.307511 12 : 4363, 4137
7378 13:53:42.307623 16 : 4252, 4027
7379 13:53:42.310769 20 : 4360, 4137
7380 13:53:42.310881 24 : 4252, 4027
7381 13:53:42.314360 28 : 4255, 4029
7382 13:53:42.314473 32 : 4255, 4029
7383 13:53:42.317671 36 : 4363, 4138
7384 13:53:42.317784 40 : 4363, 4138
7385 13:53:42.317885 44 : 4252, 4027
7386 13:53:42.321157 48 : 4252, 4027
7387 13:53:42.321255 52 : 4255, 4029
7388 13:53:42.324219 56 : 4252, 4027
7389 13:53:42.324306 60 : 4252, 4027
7390 13:53:42.327313 64 : 4250, 4026
7391 13:53:42.327396 68 : 4252, 4027
7392 13:53:42.327465 72 : 4255, 4029
7393 13:53:42.331007 76 : 4250, 4027
7394 13:53:42.331106 80 : 4252, 4029
7395 13:53:42.334205 84 : 4250, 4026
7396 13:53:42.334348 88 : 4362, 88
7397 13:53:42.337489 92 : 4250, 0
7398 13:53:42.337590 96 : 4361, 0
7399 13:53:42.337691 100 : 4250, 0
7400 13:53:42.340975 104 : 4250, 0
7401 13:53:42.341085 108 : 4361, 0
7402 13:53:42.341190 112 : 4250, 0
7403 13:53:42.343937 116 : 4250, 0
7404 13:53:42.344053 120 : 4252, 0
7405 13:53:42.347580 124 : 4250, 0
7406 13:53:42.347707 128 : 4363, 0
7407 13:53:42.347803 132 : 4255, 0
7408 13:53:42.351173 136 : 4361, 0
7409 13:53:42.351301 140 : 4250, 0
7410 13:53:42.354001 144 : 4250, 0
7411 13:53:42.354109 148 : 4250, 0
7412 13:53:42.354220 152 : 4250, 0
7413 13:53:42.357527 156 : 4252, 0
7414 13:53:42.357638 160 : 4250, 0
7415 13:53:42.360824 164 : 4250, 0
7416 13:53:42.360941 168 : 4252, 0
7417 13:53:42.361031 172 : 4250, 0
7418 13:53:42.364519 176 : 4361, 0
7419 13:53:42.364632 180 : 4361, 0
7420 13:53:42.367254 184 : 4250, 0
7421 13:53:42.367362 188 : 4250, 0
7422 13:53:42.367465 192 : 4254, 0
7423 13:53:42.370833 196 : 4255, 0
7424 13:53:42.370935 200 : 4250, 0
7425 13:53:42.374458 204 : 4360, 1499
7426 13:53:42.374573 208 : 4250, 3993
7427 13:53:42.374678 212 : 4250, 4027
7428 13:53:42.377325 216 : 4250, 4027
7429 13:53:42.377436 220 : 4250, 4027
7430 13:53:42.380869 224 : 4250, 4027
7431 13:53:42.380991 228 : 4361, 4137
7432 13:53:42.384284 232 : 4250, 4027
7433 13:53:42.384430 236 : 4361, 4137
7434 13:53:42.387706 240 : 4250, 4027
7435 13:53:42.387791 244 : 4250, 4026
7436 13:53:42.390410 248 : 4250, 4027
7437 13:53:42.390493 252 : 4250, 4027
7438 13:53:42.393927 256 : 4250, 4027
7439 13:53:42.394009 260 : 4250, 4027
7440 13:53:42.397471 264 : 4250, 4027
7441 13:53:42.397555 268 : 4253, 4029
7442 13:53:42.397621 272 : 4250, 4026
7443 13:53:42.401095 276 : 4250, 4027
7444 13:53:42.401178 280 : 4361, 4137
7445 13:53:42.403883 284 : 4250, 4027
7446 13:53:42.403965 288 : 4363, 4140
7447 13:53:42.407559 292 : 4250, 4027
7448 13:53:42.407642 296 : 4250, 4026
7449 13:53:42.410454 300 : 4250, 4027
7450 13:53:42.410539 304 : 4250, 4027
7451 13:53:42.413874 308 : 4250, 3950
7452 13:53:42.413959 312 : 4250, 2031
7453 13:53:42.414038
7454 13:53:42.417358 MIOCK jitter meter ch=0
7455 13:53:42.417439
7456 13:53:42.420776 1T = (312-88) = 224 dly cells
7457 13:53:42.424287 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7458 13:53:42.424390 ==
7459 13:53:42.427062 Dram Type= 6, Freq= 0, CH_0, rank 0
7460 13:53:42.434358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7461 13:53:42.434436 ==
7462 13:53:42.437623 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7463 13:53:42.443866 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7464 13:53:42.447406 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7465 13:53:42.453561 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7466 13:53:42.462134 [CA 0] Center 43 (13~74) winsize 62
7467 13:53:42.464815 [CA 1] Center 43 (13~74) winsize 62
7468 13:53:42.468346 [CA 2] Center 38 (9~68) winsize 60
7469 13:53:42.471790 [CA 3] Center 38 (8~68) winsize 61
7470 13:53:42.474793 [CA 4] Center 37 (7~67) winsize 61
7471 13:53:42.478301 [CA 5] Center 35 (6~65) winsize 60
7472 13:53:42.478382
7473 13:53:42.481956 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7474 13:53:42.482039
7475 13:53:42.485576 [CATrainingPosCal] consider 1 rank data
7476 13:53:42.488220 u2DelayCellTimex100 = 290/100 ps
7477 13:53:42.491630 CA0 delay=43 (13~74),Diff = 8 PI (26 cell)
7478 13:53:42.498432 CA1 delay=43 (13~74),Diff = 8 PI (26 cell)
7479 13:53:42.501990 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7480 13:53:42.504856 CA3 delay=38 (8~68),Diff = 3 PI (10 cell)
7481 13:53:42.508380 CA4 delay=37 (7~67),Diff = 2 PI (6 cell)
7482 13:53:42.511117 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7483 13:53:42.511217
7484 13:53:42.514569 CA PerBit enable=1, Macro0, CA PI delay=35
7485 13:53:42.514670
7486 13:53:42.518256 [CBTSetCACLKResult] CA Dly = 35
7487 13:53:42.521789 CS Dly: 9 (0~40)
7488 13:53:42.524581 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7489 13:53:42.528002 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7490 13:53:42.528108 ==
7491 13:53:42.531595 Dram Type= 6, Freq= 0, CH_0, rank 1
7492 13:53:42.537793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7493 13:53:42.537903 ==
7494 13:53:42.541313 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7495 13:53:42.544892 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7496 13:53:42.551231 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7497 13:53:42.557822 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7498 13:53:42.565219 [CA 0] Center 42 (12~73) winsize 62
7499 13:53:42.568233 [CA 1] Center 42 (12~73) winsize 62
7500 13:53:42.571807 [CA 2] Center 38 (8~68) winsize 61
7501 13:53:42.575238 [CA 3] Center 37 (8~67) winsize 60
7502 13:53:42.580531 [CA 4] Center 36 (6~66) winsize 61
7503 13:53:42.581494 [CA 5] Center 35 (5~65) winsize 61
7504 13:53:42.581590
7505 13:53:42.584856 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7506 13:53:42.584931
7507 13:53:42.588649 [CATrainingPosCal] consider 2 rank data
7508 13:53:42.591465 u2DelayCellTimex100 = 290/100 ps
7509 13:53:42.595106 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7510 13:53:42.601669 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7511 13:53:42.604963 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7512 13:53:42.608287 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7513 13:53:42.611806 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7514 13:53:42.614636 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7515 13:53:42.614745
7516 13:53:42.618053 CA PerBit enable=1, Macro0, CA PI delay=35
7517 13:53:42.618193
7518 13:53:42.621565 [CBTSetCACLKResult] CA Dly = 35
7519 13:53:42.625090 CS Dly: 10 (0~42)
7520 13:53:42.628431 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7521 13:53:42.631139 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7522 13:53:42.631276
7523 13:53:42.634701 ----->DramcWriteLeveling(PI) begin...
7524 13:53:42.634807 ==
7525 13:53:42.638408 Dram Type= 6, Freq= 0, CH_0, rank 0
7526 13:53:42.644479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 13:53:42.644625 ==
7528 13:53:42.647989 Write leveling (Byte 0): 36 => 36
7529 13:53:42.648108 Write leveling (Byte 1): 28 => 28
7530 13:53:42.651642 DramcWriteLeveling(PI) end<-----
7531 13:53:42.651746
7532 13:53:42.651842 ==
7533 13:53:42.654499 Dram Type= 6, Freq= 0, CH_0, rank 0
7534 13:53:42.661602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7535 13:53:42.661717 ==
7536 13:53:42.664424 [Gating] SW mode calibration
7537 13:53:42.671583 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7538 13:53:42.674455 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7539 13:53:42.681402 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7540 13:53:42.684922 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7541 13:53:42.687739 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7542 13:53:42.694604 1 4 12 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)
7543 13:53:42.697911 1 4 16 | B1->B0 | 2323 3737 | 0 1 | (0 0) (1 1)
7544 13:53:42.701093 1 4 20 | B1->B0 | 3333 3737 | 1 0 | (0 0) (0 0)
7545 13:53:42.707575 1 4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7546 13:53:42.711106 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7547 13:53:42.714664 1 5 0 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7548 13:53:42.721121 1 5 4 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7549 13:53:42.724259 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7550 13:53:42.727861 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
7551 13:53:42.731229 1 5 16 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
7552 13:53:42.737854 1 5 20 | B1->B0 | 2727 2828 | 0 0 | (0 0) (0 0)
7553 13:53:42.740925 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7554 13:53:42.744683 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7555 13:53:42.750794 1 6 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (1 1)
7556 13:53:42.754413 1 6 4 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7557 13:53:42.758079 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
7558 13:53:42.764503 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7559 13:53:42.767386 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7560 13:53:42.771049 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7561 13:53:42.778064 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7562 13:53:42.781056 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7563 13:53:42.784377 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7564 13:53:42.791230 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 13:53:42.794125 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7566 13:53:42.797797 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7567 13:53:42.804132 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7568 13:53:42.807754 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7569 13:53:42.810557 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 13:53:42.817791 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 13:53:42.820604 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 13:53:42.823969 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 13:53:42.830873 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 13:53:42.834038 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 13:53:42.837374 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 13:53:42.844083 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 13:53:42.847072 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 13:53:42.850274 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 13:53:42.857264 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 13:53:42.860913 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 13:53:42.863923 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 13:53:42.870538 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7583 13:53:42.873596 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7584 13:53:42.877141 Total UI for P1: 0, mck2ui 16
7585 13:53:42.880250 best dqsien dly found for B0: ( 1, 9, 12)
7586 13:53:42.883885 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7587 13:53:42.886763 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 13:53:42.890207 Total UI for P1: 0, mck2ui 16
7589 13:53:42.893635 best dqsien dly found for B1: ( 1, 9, 18)
7590 13:53:42.897203 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7591 13:53:42.903446 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7592 13:53:42.903530
7593 13:53:42.906877 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7594 13:53:42.910555 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7595 13:53:42.913446 [Gating] SW calibration Done
7596 13:53:42.913534 ==
7597 13:53:42.917013 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 13:53:42.919988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 13:53:42.920072 ==
7600 13:53:42.923445 RX Vref Scan: 0
7601 13:53:42.923527
7602 13:53:42.923591 RX Vref 0 -> 0, step: 1
7603 13:53:42.923652
7604 13:53:42.926733 RX Delay 0 -> 252, step: 8
7605 13:53:42.930266 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7606 13:53:42.933155 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7607 13:53:42.940082 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7608 13:53:42.943019 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7609 13:53:42.946405 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7610 13:53:42.950133 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7611 13:53:42.953065 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7612 13:53:42.960179 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7613 13:53:42.963139 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7614 13:53:42.966601 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7615 13:53:42.970260 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7616 13:53:42.973156 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7617 13:53:42.979650 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7618 13:53:42.983049 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7619 13:53:42.986241 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7620 13:53:42.990119 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7621 13:53:42.990237 ==
7622 13:53:42.993686 Dram Type= 6, Freq= 0, CH_0, rank 0
7623 13:53:42.999915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7624 13:53:43.000028 ==
7625 13:53:43.000138 DQS Delay:
7626 13:53:43.003188 DQS0 = 0, DQS1 = 0
7627 13:53:43.003286 DQM Delay:
7628 13:53:43.003392 DQM0 = 137, DQM1 = 130
7629 13:53:43.006495 DQ Delay:
7630 13:53:43.009797 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7631 13:53:43.012811 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7632 13:53:43.016137 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7633 13:53:43.019485 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7634 13:53:43.019615
7635 13:53:43.019738
7636 13:53:43.019799 ==
7637 13:53:43.023045 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 13:53:43.029725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 13:53:43.029834 ==
7640 13:53:43.029926
7641 13:53:43.030013
7642 13:53:43.030073 TX Vref Scan disable
7643 13:53:43.032643 == TX Byte 0 ==
7644 13:53:43.036124 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7645 13:53:43.040034 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7646 13:53:43.042582 == TX Byte 1 ==
7647 13:53:43.046201 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7648 13:53:43.052939 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7649 13:53:43.053153 ==
7650 13:53:43.055825 Dram Type= 6, Freq= 0, CH_0, rank 0
7651 13:53:43.059159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7652 13:53:43.059340 ==
7653 13:53:43.072275
7654 13:53:43.076303 TX Vref early break, caculate TX vref
7655 13:53:43.079128 TX Vref=16, minBit 7, minWin=22, winSum=376
7656 13:53:43.082175 TX Vref=18, minBit 7, minWin=22, winSum=383
7657 13:53:43.085842 TX Vref=20, minBit 7, minWin=23, winSum=400
7658 13:53:43.089479 TX Vref=22, minBit 1, minWin=24, winSum=406
7659 13:53:43.092378 TX Vref=24, minBit 3, minWin=25, winSum=415
7660 13:53:43.098971 TX Vref=26, minBit 0, minWin=25, winSum=423
7661 13:53:43.102408 TX Vref=28, minBit 1, minWin=24, winSum=422
7662 13:53:43.105367 TX Vref=30, minBit 1, minWin=24, winSum=414
7663 13:53:43.109056 TX Vref=32, minBit 2, minWin=23, winSum=402
7664 13:53:43.112449 TX Vref=34, minBit 1, minWin=23, winSum=390
7665 13:53:43.118751 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 26
7666 13:53:43.118853
7667 13:53:43.122023 Final TX Range 0 Vref 26
7668 13:53:43.122119
7669 13:53:43.122215 ==
7670 13:53:43.125527 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 13:53:43.128902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 13:53:43.129001 ==
7673 13:53:43.129097
7674 13:53:43.129192
7675 13:53:43.132024 TX Vref Scan disable
7676 13:53:43.139155 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7677 13:53:43.139271 == TX Byte 0 ==
7678 13:53:43.142002 u2DelayCellOfst[0]=10 cells (3 PI)
7679 13:53:43.145768 u2DelayCellOfst[1]=13 cells (4 PI)
7680 13:53:43.148892 u2DelayCellOfst[2]=10 cells (3 PI)
7681 13:53:43.152388 u2DelayCellOfst[3]=6 cells (2 PI)
7682 13:53:43.156046 u2DelayCellOfst[4]=6 cells (2 PI)
7683 13:53:43.159255 u2DelayCellOfst[5]=0 cells (0 PI)
7684 13:53:43.159368 u2DelayCellOfst[6]=16 cells (5 PI)
7685 13:53:43.162391 u2DelayCellOfst[7]=16 cells (5 PI)
7686 13:53:43.169070 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7687 13:53:43.171940 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7688 13:53:43.172049 == TX Byte 1 ==
7689 13:53:43.175447 u2DelayCellOfst[8]=0 cells (0 PI)
7690 13:53:43.179168 u2DelayCellOfst[9]=0 cells (0 PI)
7691 13:53:43.182191 u2DelayCellOfst[10]=6 cells (2 PI)
7692 13:53:43.185907 u2DelayCellOfst[11]=3 cells (1 PI)
7693 13:53:43.188785 u2DelayCellOfst[12]=13 cells (4 PI)
7694 13:53:43.192522 u2DelayCellOfst[13]=13 cells (4 PI)
7695 13:53:43.195412 u2DelayCellOfst[14]=13 cells (4 PI)
7696 13:53:43.199310 u2DelayCellOfst[15]=10 cells (3 PI)
7697 13:53:43.202250 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7698 13:53:43.205275 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7699 13:53:43.208904 DramC Write-DBI on
7700 13:53:43.209010 ==
7701 13:53:43.212445 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 13:53:43.215401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 13:53:43.215481 ==
7704 13:53:43.215568
7705 13:53:43.218541
7706 13:53:43.218642 TX Vref Scan disable
7707 13:53:43.222213 == TX Byte 0 ==
7708 13:53:43.225184 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7709 13:53:43.228662 == TX Byte 1 ==
7710 13:53:43.232417 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7711 13:53:43.232501 DramC Write-DBI off
7712 13:53:43.232575
7713 13:53:43.235281 [DATLAT]
7714 13:53:43.235377 Freq=1600, CH0 RK0
7715 13:53:43.235473
7716 13:53:43.238859 DATLAT Default: 0xf
7717 13:53:43.238955 0, 0xFFFF, sum = 0
7718 13:53:43.242403 1, 0xFFFF, sum = 0
7719 13:53:43.242505 2, 0xFFFF, sum = 0
7720 13:53:43.245140 3, 0xFFFF, sum = 0
7721 13:53:43.245242 4, 0xFFFF, sum = 0
7722 13:53:43.248646 5, 0xFFFF, sum = 0
7723 13:53:43.248725 6, 0xFFFF, sum = 0
7724 13:53:43.251889 7, 0xFFFF, sum = 0
7725 13:53:43.255420 8, 0xFFFF, sum = 0
7726 13:53:43.255524 9, 0xFFFF, sum = 0
7727 13:53:43.258489 10, 0xFFFF, sum = 0
7728 13:53:43.258565 11, 0xFFFF, sum = 0
7729 13:53:43.262319 12, 0xFFFF, sum = 0
7730 13:53:43.262397 13, 0xFFFF, sum = 0
7731 13:53:43.265243 14, 0x0, sum = 1
7732 13:53:43.265345 15, 0x0, sum = 2
7733 13:53:43.268873 16, 0x0, sum = 3
7734 13:53:43.268949 17, 0x0, sum = 4
7735 13:53:43.271774 best_step = 15
7736 13:53:43.271854
7737 13:53:43.271917 ==
7738 13:53:43.275018 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 13:53:43.278644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 13:53:43.278757 ==
7741 13:53:43.278856 RX Vref Scan: 1
7742 13:53:43.278941
7743 13:53:43.281924 Set Vref Range= 24 -> 127
7744 13:53:43.282009
7745 13:53:43.285389 RX Vref 24 -> 127, step: 1
7746 13:53:43.285494
7747 13:53:43.288380 RX Delay 27 -> 252, step: 4
7748 13:53:43.288473
7749 13:53:43.292005 Set Vref, RX VrefLevel [Byte0]: 24
7750 13:53:43.295039 [Byte1]: 24
7751 13:53:43.295145
7752 13:53:43.298808 Set Vref, RX VrefLevel [Byte0]: 25
7753 13:53:43.301783 [Byte1]: 25
7754 13:53:43.301870
7755 13:53:43.304800 Set Vref, RX VrefLevel [Byte0]: 26
7756 13:53:43.308353 [Byte1]: 26
7757 13:53:43.311700
7758 13:53:43.311782 Set Vref, RX VrefLevel [Byte0]: 27
7759 13:53:43.315303 [Byte1]: 27
7760 13:53:43.319759
7761 13:53:43.319848 Set Vref, RX VrefLevel [Byte0]: 28
7762 13:53:43.322676 [Byte1]: 28
7763 13:53:43.327043
7764 13:53:43.327127 Set Vref, RX VrefLevel [Byte0]: 29
7765 13:53:43.330077 [Byte1]: 29
7766 13:53:43.334360
7767 13:53:43.337822 Set Vref, RX VrefLevel [Byte0]: 30
7768 13:53:43.340938 [Byte1]: 30
7769 13:53:43.341050
7770 13:53:43.344465 Set Vref, RX VrefLevel [Byte0]: 31
7771 13:53:43.348106 [Byte1]: 31
7772 13:53:43.348218
7773 13:53:43.350931 Set Vref, RX VrefLevel [Byte0]: 32
7774 13:53:43.354572 [Byte1]: 32
7775 13:53:43.354655
7776 13:53:43.357454 Set Vref, RX VrefLevel [Byte0]: 33
7777 13:53:43.361191 [Byte1]: 33
7778 13:53:43.364781
7779 13:53:43.364882 Set Vref, RX VrefLevel [Byte0]: 34
7780 13:53:43.368299 [Byte1]: 34
7781 13:53:43.372564
7782 13:53:43.372654 Set Vref, RX VrefLevel [Byte0]: 35
7783 13:53:43.376278 [Byte1]: 35
7784 13:53:43.379897
7785 13:53:43.380034 Set Vref, RX VrefLevel [Byte0]: 36
7786 13:53:43.383268 [Byte1]: 36
7787 13:53:43.387497
7788 13:53:43.387647 Set Vref, RX VrefLevel [Byte0]: 37
7789 13:53:43.390609 [Byte1]: 37
7790 13:53:43.394484
7791 13:53:43.394629 Set Vref, RX VrefLevel [Byte0]: 38
7792 13:53:43.398303 [Byte1]: 38
7793 13:53:43.402513
7794 13:53:43.402647 Set Vref, RX VrefLevel [Byte0]: 39
7795 13:53:43.405829 [Byte1]: 39
7796 13:53:43.409855
7797 13:53:43.409970 Set Vref, RX VrefLevel [Byte0]: 40
7798 13:53:43.413306 [Byte1]: 40
7799 13:53:43.417564
7800 13:53:43.417674 Set Vref, RX VrefLevel [Byte0]: 41
7801 13:53:43.420950 [Byte1]: 41
7802 13:53:43.424675
7803 13:53:43.424775 Set Vref, RX VrefLevel [Byte0]: 42
7804 13:53:43.428359 [Byte1]: 42
7805 13:53:43.432686
7806 13:53:43.432780 Set Vref, RX VrefLevel [Byte0]: 43
7807 13:53:43.435458 [Byte1]: 43
7808 13:53:43.440276
7809 13:53:43.440377 Set Vref, RX VrefLevel [Byte0]: 44
7810 13:53:43.443144 [Byte1]: 44
7811 13:53:43.447563
7812 13:53:43.447648 Set Vref, RX VrefLevel [Byte0]: 45
7813 13:53:43.451188 [Byte1]: 45
7814 13:53:43.454854
7815 13:53:43.454967 Set Vref, RX VrefLevel [Byte0]: 46
7816 13:53:43.458511 [Byte1]: 46
7817 13:53:43.462668
7818 13:53:43.462781 Set Vref, RX VrefLevel [Byte0]: 47
7819 13:53:43.466106 [Byte1]: 47
7820 13:53:43.470354
7821 13:53:43.470432 Set Vref, RX VrefLevel [Byte0]: 48
7822 13:53:43.473412 [Byte1]: 48
7823 13:53:43.477947
7824 13:53:43.478059 Set Vref, RX VrefLevel [Byte0]: 49
7825 13:53:43.480746 [Byte1]: 49
7826 13:53:43.485151
7827 13:53:43.485266 Set Vref, RX VrefLevel [Byte0]: 50
7828 13:53:43.488458 [Byte1]: 50
7829 13:53:43.492873
7830 13:53:43.492983 Set Vref, RX VrefLevel [Byte0]: 51
7831 13:53:43.496374 [Byte1]: 51
7832 13:53:43.500016
7833 13:53:43.500102 Set Vref, RX VrefLevel [Byte0]: 52
7834 13:53:43.503486 [Byte1]: 52
7835 13:53:43.507945
7836 13:53:43.508058 Set Vref, RX VrefLevel [Byte0]: 53
7837 13:53:43.511155 [Byte1]: 53
7838 13:53:43.515209
7839 13:53:43.515324 Set Vref, RX VrefLevel [Byte0]: 54
7840 13:53:43.518612 [Byte1]: 54
7841 13:53:43.522608
7842 13:53:43.522707 Set Vref, RX VrefLevel [Byte0]: 55
7843 13:53:43.526364 [Byte1]: 55
7844 13:53:43.530729
7845 13:53:43.530857 Set Vref, RX VrefLevel [Byte0]: 56
7846 13:53:43.533567 [Byte1]: 56
7847 13:53:43.537837
7848 13:53:43.537923 Set Vref, RX VrefLevel [Byte0]: 57
7849 13:53:43.541351 [Byte1]: 57
7850 13:53:43.545527
7851 13:53:43.545634 Set Vref, RX VrefLevel [Byte0]: 58
7852 13:53:43.549170 [Byte1]: 58
7853 13:53:43.552819
7854 13:53:43.552932 Set Vref, RX VrefLevel [Byte0]: 59
7855 13:53:43.556348 [Byte1]: 59
7856 13:53:43.560699
7857 13:53:43.560778 Set Vref, RX VrefLevel [Byte0]: 60
7858 13:53:43.563569 [Byte1]: 60
7859 13:53:43.567798
7860 13:53:43.567874 Set Vref, RX VrefLevel [Byte0]: 61
7861 13:53:43.571342 [Byte1]: 61
7862 13:53:43.575711
7863 13:53:43.575788 Set Vref, RX VrefLevel [Byte0]: 62
7864 13:53:43.578590 [Byte1]: 62
7865 13:53:43.583001
7866 13:53:43.583103 Set Vref, RX VrefLevel [Byte0]: 63
7867 13:53:43.586389 [Byte1]: 63
7868 13:53:43.590526
7869 13:53:43.590596 Set Vref, RX VrefLevel [Byte0]: 64
7870 13:53:43.594291 [Byte1]: 64
7871 13:53:43.598421
7872 13:53:43.601428 Set Vref, RX VrefLevel [Byte0]: 65
7873 13:53:43.605119 [Byte1]: 65
7874 13:53:43.605191
7875 13:53:43.607871 Set Vref, RX VrefLevel [Byte0]: 66
7876 13:53:43.611425 [Byte1]: 66
7877 13:53:43.611535
7878 13:53:43.614328 Set Vref, RX VrefLevel [Byte0]: 67
7879 13:53:43.618097 [Byte1]: 67
7880 13:53:43.618185
7881 13:53:43.621071 Set Vref, RX VrefLevel [Byte0]: 68
7882 13:53:43.624574 [Byte1]: 68
7883 13:53:43.628199
7884 13:53:43.628274 Set Vref, RX VrefLevel [Byte0]: 69
7885 13:53:43.631748 [Byte1]: 69
7886 13:53:43.636086
7887 13:53:43.636162 Set Vref, RX VrefLevel [Byte0]: 70
7888 13:53:43.638967 [Byte1]: 70
7889 13:53:43.643752
7890 13:53:43.643832 Set Vref, RX VrefLevel [Byte0]: 71
7891 13:53:43.646423 [Byte1]: 71
7892 13:53:43.650905
7893 13:53:43.650993 Set Vref, RX VrefLevel [Byte0]: 72
7894 13:53:43.654425 [Byte1]: 72
7895 13:53:43.658312
7896 13:53:43.658425 Set Vref, RX VrefLevel [Byte0]: 73
7897 13:53:43.662009 [Byte1]: 73
7898 13:53:43.666272
7899 13:53:43.666361 Final RX Vref Byte 0 = 54 to rank0
7900 13:53:43.669358 Final RX Vref Byte 1 = 63 to rank0
7901 13:53:43.672831 Final RX Vref Byte 0 = 54 to rank1
7902 13:53:43.675947 Final RX Vref Byte 1 = 63 to rank1==
7903 13:53:43.679544 Dram Type= 6, Freq= 0, CH_0, rank 0
7904 13:53:43.686057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7905 13:53:43.686158 ==
7906 13:53:43.686247 DQS Delay:
7907 13:53:43.686329 DQS0 = 0, DQS1 = 0
7908 13:53:43.688965 DQM Delay:
7909 13:53:43.689055 DQM0 = 133, DQM1 = 127
7910 13:53:43.692316 DQ Delay:
7911 13:53:43.695968 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7912 13:53:43.699317 DQ4 =132, DQ5 =124, DQ6 =138, DQ7 =138
7913 13:53:43.702880 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7914 13:53:43.705795 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7915 13:53:43.705897
7916 13:53:43.705999
7917 13:53:43.706094
7918 13:53:43.708826 [DramC_TX_OE_Calibration] TA2
7919 13:53:43.712620 Original DQ_B0 (3 6) =30, OEN = 27
7920 13:53:43.715370 Original DQ_B1 (3 6) =30, OEN = 27
7921 13:53:43.719081 24, 0x0, End_B0=24 End_B1=24
7922 13:53:43.719174 25, 0x0, End_B0=25 End_B1=25
7923 13:53:43.722120 26, 0x0, End_B0=26 End_B1=26
7924 13:53:43.725891 27, 0x0, End_B0=27 End_B1=27
7925 13:53:43.729577 28, 0x0, End_B0=28 End_B1=28
7926 13:53:43.729664 29, 0x0, End_B0=29 End_B1=29
7927 13:53:43.732393 30, 0x0, End_B0=30 End_B1=30
7928 13:53:43.736218 31, 0x4141, End_B0=30 End_B1=30
7929 13:53:43.739120 Byte0 end_step=30 best_step=27
7930 13:53:43.742789 Byte1 end_step=30 best_step=27
7931 13:53:43.745685 Byte0 TX OE(2T, 0.5T) = (3, 3)
7932 13:53:43.745781 Byte1 TX OE(2T, 0.5T) = (3, 3)
7933 13:53:43.749327
7934 13:53:43.749412
7935 13:53:43.755764 [DQSOSCAuto] RK0, (LSB)MR18= 0x241f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 391 ps
7936 13:53:43.759269 CH0 RK0: MR19=303, MR18=241F
7937 13:53:43.765726 CH0_RK0: MR19=0x303, MR18=0x241F, DQSOSC=391, MR23=63, INC=24, DEC=16
7938 13:53:43.765862
7939 13:53:43.768635 ----->DramcWriteLeveling(PI) begin...
7940 13:53:43.768737 ==
7941 13:53:43.772419 Dram Type= 6, Freq= 0, CH_0, rank 1
7942 13:53:43.775239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7943 13:53:43.775354 ==
7944 13:53:43.778884 Write leveling (Byte 0): 38 => 38
7945 13:53:43.782398 Write leveling (Byte 1): 27 => 27
7946 13:53:43.785663 DramcWriteLeveling(PI) end<-----
7947 13:53:43.785795
7948 13:53:43.785899 ==
7949 13:53:43.788665 Dram Type= 6, Freq= 0, CH_0, rank 1
7950 13:53:43.792262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7951 13:53:43.792386 ==
7952 13:53:43.795213 [Gating] SW mode calibration
7953 13:53:43.801775 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7954 13:53:43.808786 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7955 13:53:43.811944 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7956 13:53:43.815481 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7957 13:53:43.821983 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7958 13:53:43.825740 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
7959 13:53:43.828747 1 4 16 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7960 13:53:43.835162 1 4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
7961 13:53:43.838801 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7962 13:53:43.841785 1 4 28 | B1->B0 | 3434 2323 | 1 1 | (1 1) (1 1)
7963 13:53:43.848407 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7964 13:53:43.852126 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7965 13:53:43.855061 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7966 13:53:43.861725 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
7967 13:53:43.864744 1 5 16 | B1->B0 | 2e2e 2424 | 0 0 | (1 0) (1 0)
7968 13:53:43.868580 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7969 13:53:43.875476 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7970 13:53:43.878273 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7971 13:53:43.881811 1 6 0 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7972 13:53:43.888475 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7973 13:53:43.891369 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7974 13:53:43.894933 1 6 12 | B1->B0 | 2424 2f2e | 0 1 | (0 0) (0 0)
7975 13:53:43.901718 1 6 16 | B1->B0 | 3f3f 4544 | 0 1 | (0 0) (1 1)
7976 13:53:43.905190 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7977 13:53:43.908276 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7978 13:53:43.915245 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7979 13:53:43.917949 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7980 13:53:43.921313 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7981 13:53:43.928247 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7982 13:53:43.931606 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7983 13:53:43.935057 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7984 13:53:43.941165 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7985 13:53:43.944446 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 13:53:43.948013 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 13:53:43.954936 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 13:53:43.957998 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 13:53:43.961639 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 13:53:43.964560 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 13:53:43.971152 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 13:53:43.974766 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 13:53:43.978194 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 13:53:43.984785 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 13:53:43.987820 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 13:53:43.991442 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 13:53:43.998100 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7998 13:53:44.001070 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7999 13:53:44.004574 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8000 13:53:44.011192 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 13:53:44.014798 Total UI for P1: 0, mck2ui 16
8002 13:53:44.017559 best dqsien dly found for B0: ( 1, 9, 12)
8003 13:53:44.017636 Total UI for P1: 0, mck2ui 16
8004 13:53:44.024298 best dqsien dly found for B1: ( 1, 9, 12)
8005 13:53:44.027857 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8006 13:53:44.030857 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8007 13:53:44.030954
8008 13:53:44.034477 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8009 13:53:44.037483 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8010 13:53:44.041137 [Gating] SW calibration Done
8011 13:53:44.041251 ==
8012 13:53:44.044570 Dram Type= 6, Freq= 0, CH_0, rank 1
8013 13:53:44.047790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 13:53:44.047901 ==
8015 13:53:44.051215 RX Vref Scan: 0
8016 13:53:44.051299
8017 13:53:44.051369 RX Vref 0 -> 0, step: 1
8018 13:53:44.054035
8019 13:53:44.054117 RX Delay 0 -> 252, step: 8
8020 13:53:44.060682 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8021 13:53:44.064411 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8022 13:53:44.067293 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8023 13:53:44.070950 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8024 13:53:44.074492 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8025 13:53:44.077579 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8026 13:53:44.084291 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8027 13:53:44.087734 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8028 13:53:44.090509 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8029 13:53:44.094200 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8030 13:53:44.097640 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8031 13:53:44.104055 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8032 13:53:44.107598 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8033 13:53:44.110403 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8034 13:53:44.113993 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8035 13:53:44.120405 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8036 13:53:44.120480 ==
8037 13:53:44.123966 Dram Type= 6, Freq= 0, CH_0, rank 1
8038 13:53:44.127212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8039 13:53:44.127289 ==
8040 13:53:44.127352 DQS Delay:
8041 13:53:44.130604 DQS0 = 0, DQS1 = 0
8042 13:53:44.130675 DQM Delay:
8043 13:53:44.134015 DQM0 = 136, DQM1 = 130
8044 13:53:44.134099 DQ Delay:
8045 13:53:44.137454 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8046 13:53:44.140945 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8047 13:53:44.143798 DQ8 =123, DQ9 =119, DQ10 =127, DQ11 =123
8048 13:53:44.147295 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8049 13:53:44.147381
8050 13:53:44.147446
8051 13:53:44.150918 ==
8052 13:53:44.151001 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 13:53:44.157265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 13:53:44.157350 ==
8055 13:53:44.157415
8056 13:53:44.157476
8057 13:53:44.160885 TX Vref Scan disable
8058 13:53:44.160967 == TX Byte 0 ==
8059 13:53:44.164212 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
8060 13:53:44.170292 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8061 13:53:44.170375 == TX Byte 1 ==
8062 13:53:44.174081 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8063 13:53:44.180289 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8064 13:53:44.180385 ==
8065 13:53:44.183471 Dram Type= 6, Freq= 0, CH_0, rank 1
8066 13:53:44.187392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8067 13:53:44.187474 ==
8068 13:53:44.201135
8069 13:53:44.204668 TX Vref early break, caculate TX vref
8070 13:53:44.207791 TX Vref=16, minBit 1, minWin=23, winSum=385
8071 13:53:44.211633 TX Vref=18, minBit 3, minWin=23, winSum=399
8072 13:53:44.214666 TX Vref=20, minBit 1, minWin=24, winSum=405
8073 13:53:44.218314 TX Vref=22, minBit 1, minWin=25, winSum=413
8074 13:53:44.221280 TX Vref=24, minBit 1, minWin=25, winSum=418
8075 13:53:44.227732 TX Vref=26, minBit 1, minWin=25, winSum=431
8076 13:53:44.231198 TX Vref=28, minBit 2, minWin=25, winSum=423
8077 13:53:44.234553 TX Vref=30, minBit 2, minWin=25, winSum=418
8078 13:53:44.237912 TX Vref=32, minBit 4, minWin=24, winSum=411
8079 13:53:44.241417 TX Vref=34, minBit 0, minWin=24, winSum=403
8080 13:53:44.247707 [TxChooseVref] Worse bit 1, Min win 25, Win sum 431, Final Vref 26
8081 13:53:44.247816
8082 13:53:44.251342 Final TX Range 0 Vref 26
8083 13:53:44.251461
8084 13:53:44.251529 ==
8085 13:53:44.254158 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 13:53:44.257696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 13:53:44.257803 ==
8088 13:53:44.257904
8089 13:53:44.258001
8090 13:53:44.261380 TX Vref Scan disable
8091 13:53:44.268048 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8092 13:53:44.268188 == TX Byte 0 ==
8093 13:53:44.271534 u2DelayCellOfst[0]=13 cells (4 PI)
8094 13:53:44.274299 u2DelayCellOfst[1]=16 cells (5 PI)
8095 13:53:44.277512 u2DelayCellOfst[2]=10 cells (3 PI)
8096 13:53:44.280841 u2DelayCellOfst[3]=10 cells (3 PI)
8097 13:53:44.284426 u2DelayCellOfst[4]=10 cells (3 PI)
8098 13:53:44.288064 u2DelayCellOfst[5]=0 cells (0 PI)
8099 13:53:44.290919 u2DelayCellOfst[6]=16 cells (5 PI)
8100 13:53:44.294323 u2DelayCellOfst[7]=16 cells (5 PI)
8101 13:53:44.298000 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8102 13:53:44.300805 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8103 13:53:44.304085 == TX Byte 1 ==
8104 13:53:44.304209 u2DelayCellOfst[8]=0 cells (0 PI)
8105 13:53:44.307647 u2DelayCellOfst[9]=0 cells (0 PI)
8106 13:53:44.310957 u2DelayCellOfst[10]=3 cells (1 PI)
8107 13:53:44.314361 u2DelayCellOfst[11]=3 cells (1 PI)
8108 13:53:44.317777 u2DelayCellOfst[12]=6 cells (2 PI)
8109 13:53:44.320904 u2DelayCellOfst[13]=10 cells (3 PI)
8110 13:53:44.324096 u2DelayCellOfst[14]=10 cells (3 PI)
8111 13:53:44.327424 u2DelayCellOfst[15]=6 cells (2 PI)
8112 13:53:44.331096 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8113 13:53:44.337663 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8114 13:53:44.337788 DramC Write-DBI on
8115 13:53:44.337887 ==
8116 13:53:44.340989 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 13:53:44.344528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 13:53:44.347309 ==
8119 13:53:44.347427
8120 13:53:44.347494
8121 13:53:44.347554 TX Vref Scan disable
8122 13:53:44.350749 == TX Byte 0 ==
8123 13:53:44.354405 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8124 13:53:44.357330 == TX Byte 1 ==
8125 13:53:44.360900 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8126 13:53:44.363882 DramC Write-DBI off
8127 13:53:44.363959
8128 13:53:44.364041 [DATLAT]
8129 13:53:44.364129 Freq=1600, CH0 RK1
8130 13:53:44.364223
8131 13:53:44.367485 DATLAT Default: 0xf
8132 13:53:44.367556 0, 0xFFFF, sum = 0
8133 13:53:44.371195 1, 0xFFFF, sum = 0
8134 13:53:44.373965 2, 0xFFFF, sum = 0
8135 13:53:44.374044 3, 0xFFFF, sum = 0
8136 13:53:44.377479 4, 0xFFFF, sum = 0
8137 13:53:44.377549 5, 0xFFFF, sum = 0
8138 13:53:44.380448 6, 0xFFFF, sum = 0
8139 13:53:44.380537 7, 0xFFFF, sum = 0
8140 13:53:44.383866 8, 0xFFFF, sum = 0
8141 13:53:44.383950 9, 0xFFFF, sum = 0
8142 13:53:44.387245 10, 0xFFFF, sum = 0
8143 13:53:44.387330 11, 0xFFFF, sum = 0
8144 13:53:44.390983 12, 0xFFFF, sum = 0
8145 13:53:44.391070 13, 0xFFFF, sum = 0
8146 13:53:44.393822 14, 0x0, sum = 1
8147 13:53:44.393907 15, 0x0, sum = 2
8148 13:53:44.397361 16, 0x0, sum = 3
8149 13:53:44.397450 17, 0x0, sum = 4
8150 13:53:44.401060 best_step = 15
8151 13:53:44.401145
8152 13:53:44.401212 ==
8153 13:53:44.403861 Dram Type= 6, Freq= 0, CH_0, rank 1
8154 13:53:44.407497 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8155 13:53:44.407583 ==
8156 13:53:44.411063 RX Vref Scan: 0
8157 13:53:44.411146
8158 13:53:44.411212 RX Vref 0 -> 0, step: 1
8159 13:53:44.411274
8160 13:53:44.413896 RX Delay 19 -> 252, step: 4
8161 13:53:44.417344 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8162 13:53:44.424349 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8163 13:53:44.427996 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8164 13:53:44.430758 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8165 13:53:44.434345 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8166 13:53:44.437713 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8167 13:53:44.440974 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8168 13:53:44.447396 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8169 13:53:44.450913 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8170 13:53:44.454139 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8171 13:53:44.457443 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8172 13:53:44.463863 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8173 13:53:44.467623 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8174 13:53:44.470995 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8175 13:53:44.474036 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8176 13:53:44.477611 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8177 13:53:44.477690 ==
8178 13:53:44.480478 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 13:53:44.486980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 13:53:44.487073 ==
8181 13:53:44.487138 DQS Delay:
8182 13:53:44.490786 DQS0 = 0, DQS1 = 0
8183 13:53:44.490871 DQM Delay:
8184 13:53:44.493605 DQM0 = 133, DQM1 = 126
8185 13:53:44.493686 DQ Delay:
8186 13:53:44.496998 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =132
8187 13:53:44.500131 DQ4 =134, DQ5 =124, DQ6 =138, DQ7 =140
8188 13:53:44.503814 DQ8 =118, DQ9 =116, DQ10 =126, DQ11 =118
8189 13:53:44.507306 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =134
8190 13:53:44.507432
8191 13:53:44.507508
8192 13:53:44.507569
8193 13:53:44.510348 [DramC_TX_OE_Calibration] TA2
8194 13:53:44.513947 Original DQ_B0 (3 6) =30, OEN = 27
8195 13:53:44.516899 Original DQ_B1 (3 6) =30, OEN = 27
8196 13:53:44.520509 24, 0x0, End_B0=24 End_B1=24
8197 13:53:44.523330 25, 0x0, End_B0=25 End_B1=25
8198 13:53:44.523444 26, 0x0, End_B0=26 End_B1=26
8199 13:53:44.526699 27, 0x0, End_B0=27 End_B1=27
8200 13:53:44.530317 28, 0x0, End_B0=28 End_B1=28
8201 13:53:44.533329 29, 0x0, End_B0=29 End_B1=29
8202 13:53:44.536913 30, 0x0, End_B0=30 End_B1=30
8203 13:53:44.537016 31, 0x4545, End_B0=30 End_B1=30
8204 13:53:44.539870 Byte0 end_step=30 best_step=27
8205 13:53:44.543400 Byte1 end_step=30 best_step=27
8206 13:53:44.546434 Byte0 TX OE(2T, 0.5T) = (3, 3)
8207 13:53:44.550003 Byte1 TX OE(2T, 0.5T) = (3, 3)
8208 13:53:44.550083
8209 13:53:44.550166
8210 13:53:44.556610 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
8211 13:53:44.560229 CH0 RK1: MR19=303, MR18=1F08
8212 13:53:44.566330 CH0_RK1: MR19=0x303, MR18=0x1F08, DQSOSC=394, MR23=63, INC=23, DEC=15
8213 13:53:44.569743 [RxdqsGatingPostProcess] freq 1600
8214 13:53:44.576272 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8215 13:53:44.576385 best DQS0 dly(2T, 0.5T) = (1, 1)
8216 13:53:44.580099 best DQS1 dly(2T, 0.5T) = (1, 1)
8217 13:53:44.583116 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8218 13:53:44.586495 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8219 13:53:44.589903 best DQS0 dly(2T, 0.5T) = (1, 1)
8220 13:53:44.593172 best DQS1 dly(2T, 0.5T) = (1, 1)
8221 13:53:44.596122 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8222 13:53:44.599813 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8223 13:53:44.602699 Pre-setting of DQS Precalculation
8224 13:53:44.606140 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8225 13:53:44.606227 ==
8226 13:53:44.610019 Dram Type= 6, Freq= 0, CH_1, rank 0
8227 13:53:44.616329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8228 13:53:44.616428 ==
8229 13:53:44.619513 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8230 13:53:44.626013 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8231 13:53:44.629647 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8232 13:53:44.636284 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8233 13:53:44.644189 [CA 0] Center 42 (13~72) winsize 60
8234 13:53:44.647009 [CA 1] Center 42 (13~72) winsize 60
8235 13:53:44.650558 [CA 2] Center 39 (9~69) winsize 61
8236 13:53:44.654197 [CA 3] Center 38 (9~67) winsize 59
8237 13:53:44.657083 [CA 4] Center 38 (9~68) winsize 60
8238 13:53:44.660557 [CA 5] Center 37 (8~67) winsize 60
8239 13:53:44.660629
8240 13:53:44.663483 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8241 13:53:44.663551
8242 13:53:44.667086 [CATrainingPosCal] consider 1 rank data
8243 13:53:44.670408 u2DelayCellTimex100 = 290/100 ps
8244 13:53:44.673763 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8245 13:53:44.680166 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8246 13:53:44.683758 CA2 delay=39 (9~69),Diff = 2 PI (6 cell)
8247 13:53:44.687219 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8248 13:53:44.690766 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8249 13:53:44.693563 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8250 13:53:44.693646
8251 13:53:44.696959 CA PerBit enable=1, Macro0, CA PI delay=37
8252 13:53:44.697029
8253 13:53:44.700206 [CBTSetCACLKResult] CA Dly = 37
8254 13:53:44.703363 CS Dly: 11 (0~42)
8255 13:53:44.706867 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8256 13:53:44.710047 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8257 13:53:44.710134 ==
8258 13:53:44.713843 Dram Type= 6, Freq= 0, CH_1, rank 1
8259 13:53:44.716783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8260 13:53:44.719916 ==
8261 13:53:44.723578 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8262 13:53:44.726977 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8263 13:53:44.733416 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8264 13:53:44.736571 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8265 13:53:44.747218 [CA 0] Center 42 (12~72) winsize 61
8266 13:53:44.750254 [CA 1] Center 42 (13~72) winsize 60
8267 13:53:44.753334 [CA 2] Center 39 (10~68) winsize 59
8268 13:53:44.756970 [CA 3] Center 38 (8~68) winsize 61
8269 13:53:44.760797 [CA 4] Center 38 (8~68) winsize 61
8270 13:53:44.763553 [CA 5] Center 37 (8~67) winsize 60
8271 13:53:44.763636
8272 13:53:44.767193 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8273 13:53:44.767265
8274 13:53:44.770046 [CATrainingPosCal] consider 2 rank data
8275 13:53:44.773598 u2DelayCellTimex100 = 290/100 ps
8276 13:53:44.777008 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8277 13:53:44.783878 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8278 13:53:44.786751 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8279 13:53:44.790476 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8280 13:53:44.793874 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8281 13:53:44.796780 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8282 13:53:44.796854
8283 13:53:44.800412 CA PerBit enable=1, Macro0, CA PI delay=37
8284 13:53:44.800516
8285 13:53:44.803277 [CBTSetCACLKResult] CA Dly = 37
8286 13:53:44.806656 CS Dly: 12 (0~44)
8287 13:53:44.810440 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8288 13:53:44.813337 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8289 13:53:44.813444
8290 13:53:44.816883 ----->DramcWriteLeveling(PI) begin...
8291 13:53:44.816988 ==
8292 13:53:44.820352 Dram Type= 6, Freq= 0, CH_1, rank 0
8293 13:53:44.826827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 13:53:44.826921 ==
8295 13:53:44.830317 Write leveling (Byte 0): 25 => 25
8296 13:53:44.830400 Write leveling (Byte 1): 28 => 28
8297 13:53:44.833146 DramcWriteLeveling(PI) end<-----
8298 13:53:44.833222
8299 13:53:44.836583 ==
8300 13:53:44.836659 Dram Type= 6, Freq= 0, CH_1, rank 0
8301 13:53:44.843301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8302 13:53:44.843410 ==
8303 13:53:44.846555 [Gating] SW mode calibration
8304 13:53:44.853242 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8305 13:53:44.856538 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8306 13:53:44.863301 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8307 13:53:44.866226 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8308 13:53:44.869668 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8309 13:53:44.876227 1 4 12 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
8310 13:53:44.879806 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8311 13:53:44.883149 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8312 13:53:44.889899 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8313 13:53:44.892933 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8314 13:53:44.896370 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 13:53:44.902825 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8316 13:53:44.906420 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8317 13:53:44.910062 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
8318 13:53:44.916138 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 13:53:44.919456 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 13:53:44.922902 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 13:53:44.929262 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 13:53:44.932850 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 13:53:44.936350 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 13:53:44.939257 1 6 8 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8325 13:53:44.945851 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8326 13:53:44.949480 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8327 13:53:44.953246 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8328 13:53:44.959306 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8329 13:53:44.962586 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8330 13:53:44.966145 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 13:53:44.972617 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 13:53:44.976454 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8333 13:53:44.979212 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8334 13:53:44.985858 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8335 13:53:44.989771 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8336 13:53:44.992812 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 13:53:44.999159 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 13:53:45.002580 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 13:53:45.005860 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 13:53:45.012698 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 13:53:45.015819 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 13:53:45.019115 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 13:53:45.026477 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 13:53:45.029598 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 13:53:45.032895 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 13:53:45.039117 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 13:53:45.042954 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 13:53:45.045860 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8349 13:53:45.049518 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8350 13:53:45.056158 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 13:53:45.059216 Total UI for P1: 0, mck2ui 16
8352 13:53:45.062773 best dqsien dly found for B0: ( 1, 9, 10)
8353 13:53:45.066278 Total UI for P1: 0, mck2ui 16
8354 13:53:45.068947 best dqsien dly found for B1: ( 1, 9, 10)
8355 13:53:45.072264 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8356 13:53:45.075590 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8357 13:53:45.075677
8358 13:53:45.079207 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8359 13:53:45.082847 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8360 13:53:45.085714 [Gating] SW calibration Done
8361 13:53:45.085797 ==
8362 13:53:45.089409 Dram Type= 6, Freq= 0, CH_1, rank 0
8363 13:53:45.092233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8364 13:53:45.092316 ==
8365 13:53:45.095794 RX Vref Scan: 0
8366 13:53:45.095877
8367 13:53:45.099518 RX Vref 0 -> 0, step: 1
8368 13:53:45.099604
8369 13:53:45.099670 RX Delay 0 -> 252, step: 8
8370 13:53:45.105832 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8371 13:53:45.109428 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8372 13:53:45.112287 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8373 13:53:45.115871 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8374 13:53:45.119097 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8375 13:53:45.122368 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8376 13:53:45.128984 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8377 13:53:45.132485 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8378 13:53:45.135503 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8379 13:53:45.139222 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8380 13:53:45.142420 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8381 13:53:45.149276 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8382 13:53:45.152479 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8383 13:53:45.155168 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8384 13:53:45.158787 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8385 13:53:45.165196 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8386 13:53:45.165305 ==
8387 13:53:45.168938 Dram Type= 6, Freq= 0, CH_1, rank 0
8388 13:53:45.172233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8389 13:53:45.172332 ==
8390 13:53:45.172448 DQS Delay:
8391 13:53:45.175156 DQS0 = 0, DQS1 = 0
8392 13:53:45.175264 DQM Delay:
8393 13:53:45.178637 DQM0 = 136, DQM1 = 133
8394 13:53:45.178750 DQ Delay:
8395 13:53:45.181903 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8396 13:53:45.185381 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8397 13:53:45.188887 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8398 13:53:45.191648 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =139
8399 13:53:45.191725
8400 13:53:45.191804
8401 13:53:45.195255 ==
8402 13:53:45.198824 Dram Type= 6, Freq= 0, CH_1, rank 0
8403 13:53:45.201772 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 13:53:45.201881 ==
8405 13:53:45.201985
8406 13:53:45.202073
8407 13:53:45.205391 TX Vref Scan disable
8408 13:53:45.205480 == TX Byte 0 ==
8409 13:53:45.208223 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8410 13:53:45.214846 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8411 13:53:45.214950 == TX Byte 1 ==
8412 13:53:45.218454 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8413 13:53:45.224967 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8414 13:53:45.225044 ==
8415 13:53:45.228329 Dram Type= 6, Freq= 0, CH_1, rank 0
8416 13:53:45.231879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8417 13:53:45.231984 ==
8418 13:53:45.246041
8419 13:53:45.249472 TX Vref early break, caculate TX vref
8420 13:53:45.252936 TX Vref=16, minBit 0, minWin=23, winSum=377
8421 13:53:45.255469 TX Vref=18, minBit 5, minWin=23, winSum=384
8422 13:53:45.258894 TX Vref=20, minBit 0, minWin=24, winSum=396
8423 13:53:45.262800 TX Vref=22, minBit 1, minWin=24, winSum=406
8424 13:53:45.265957 TX Vref=24, minBit 0, minWin=25, winSum=418
8425 13:53:45.272105 TX Vref=26, minBit 0, minWin=25, winSum=421
8426 13:53:45.275887 TX Vref=28, minBit 0, minWin=25, winSum=424
8427 13:53:45.278970 TX Vref=30, minBit 0, minWin=24, winSum=419
8428 13:53:45.282666 TX Vref=32, minBit 6, minWin=24, winSum=411
8429 13:53:45.285797 TX Vref=34, minBit 0, minWin=24, winSum=402
8430 13:53:45.289081 TX Vref=36, minBit 2, minWin=23, winSum=389
8431 13:53:45.295689 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 28
8432 13:53:45.295777
8433 13:53:45.298801 Final TX Range 0 Vref 28
8434 13:53:45.298886
8435 13:53:45.298952 ==
8436 13:53:45.302165 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 13:53:45.305808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 13:53:45.305892 ==
8439 13:53:45.305957
8440 13:53:45.306018
8441 13:53:45.309133 TX Vref Scan disable
8442 13:53:45.315466 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8443 13:53:45.315550 == TX Byte 0 ==
8444 13:53:45.319243 u2DelayCellOfst[0]=20 cells (6 PI)
8445 13:53:45.322168 u2DelayCellOfst[1]=13 cells (4 PI)
8446 13:53:45.325806 u2DelayCellOfst[2]=0 cells (0 PI)
8447 13:53:45.328708 u2DelayCellOfst[3]=10 cells (3 PI)
8448 13:53:45.332199 u2DelayCellOfst[4]=10 cells (3 PI)
8449 13:53:45.335788 u2DelayCellOfst[5]=20 cells (6 PI)
8450 13:53:45.338609 u2DelayCellOfst[6]=20 cells (6 PI)
8451 13:53:45.342172 u2DelayCellOfst[7]=6 cells (2 PI)
8452 13:53:45.345714 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8453 13:53:45.348720 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8454 13:53:45.352270 == TX Byte 1 ==
8455 13:53:45.355799 u2DelayCellOfst[8]=0 cells (0 PI)
8456 13:53:45.355886 u2DelayCellOfst[9]=3 cells (1 PI)
8457 13:53:45.358580 u2DelayCellOfst[10]=13 cells (4 PI)
8458 13:53:45.362158 u2DelayCellOfst[11]=6 cells (2 PI)
8459 13:53:45.365515 u2DelayCellOfst[12]=16 cells (5 PI)
8460 13:53:45.369177 u2DelayCellOfst[13]=16 cells (5 PI)
8461 13:53:45.371913 u2DelayCellOfst[14]=16 cells (5 PI)
8462 13:53:45.375386 u2DelayCellOfst[15]=16 cells (5 PI)
8463 13:53:45.381865 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8464 13:53:45.385328 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8465 13:53:45.385407 DramC Write-DBI on
8466 13:53:45.385477 ==
8467 13:53:45.388721 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 13:53:45.395727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 13:53:45.395811 ==
8470 13:53:45.395875
8471 13:53:45.395935
8472 13:53:45.395992 TX Vref Scan disable
8473 13:53:45.399494 == TX Byte 0 ==
8474 13:53:45.402526 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8475 13:53:45.405999 == TX Byte 1 ==
8476 13:53:45.408871 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8477 13:53:45.412260 DramC Write-DBI off
8478 13:53:45.412411
8479 13:53:45.412501 [DATLAT]
8480 13:53:45.412595 Freq=1600, CH1 RK0
8481 13:53:45.412680
8482 13:53:45.415872 DATLAT Default: 0xf
8483 13:53:45.415939 0, 0xFFFF, sum = 0
8484 13:53:45.419340 1, 0xFFFF, sum = 0
8485 13:53:45.422334 2, 0xFFFF, sum = 0
8486 13:53:45.422443 3, 0xFFFF, sum = 0
8487 13:53:45.425888 4, 0xFFFF, sum = 0
8488 13:53:45.425996 5, 0xFFFF, sum = 0
8489 13:53:45.429105 6, 0xFFFF, sum = 0
8490 13:53:45.429266 7, 0xFFFF, sum = 0
8491 13:53:45.432558 8, 0xFFFF, sum = 0
8492 13:53:45.432631 9, 0xFFFF, sum = 0
8493 13:53:45.436031 10, 0xFFFF, sum = 0
8494 13:53:45.436129 11, 0xFFFF, sum = 0
8495 13:53:45.438790 12, 0xFFFF, sum = 0
8496 13:53:45.438885 13, 0xFFFF, sum = 0
8497 13:53:45.442550 14, 0x0, sum = 1
8498 13:53:45.442637 15, 0x0, sum = 2
8499 13:53:45.445363 16, 0x0, sum = 3
8500 13:53:45.445445 17, 0x0, sum = 4
8501 13:53:45.448948 best_step = 15
8502 13:53:45.449062
8503 13:53:45.449156 ==
8504 13:53:45.452650 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 13:53:45.455443 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 13:53:45.455548 ==
8507 13:53:45.459057 RX Vref Scan: 1
8508 13:53:45.459154
8509 13:53:45.459249 Set Vref Range= 24 -> 127
8510 13:53:45.459339
8511 13:53:45.462572 RX Vref 24 -> 127, step: 1
8512 13:53:45.462678
8513 13:53:45.465354 RX Delay 27 -> 252, step: 4
8514 13:53:45.465454
8515 13:53:45.468879 Set Vref, RX VrefLevel [Byte0]: 24
8516 13:53:45.471913 [Byte1]: 24
8517 13:53:45.472012
8518 13:53:45.475784 Set Vref, RX VrefLevel [Byte0]: 25
8519 13:53:45.478618 [Byte1]: 25
8520 13:53:45.478699
8521 13:53:45.482076 Set Vref, RX VrefLevel [Byte0]: 26
8522 13:53:45.485716 [Byte1]: 26
8523 13:53:45.489106
8524 13:53:45.489187 Set Vref, RX VrefLevel [Byte0]: 27
8525 13:53:45.492641 [Byte1]: 27
8526 13:53:45.496964
8527 13:53:45.497045 Set Vref, RX VrefLevel [Byte0]: 28
8528 13:53:45.500469 [Byte1]: 28
8529 13:53:45.504524
8530 13:53:45.504624 Set Vref, RX VrefLevel [Byte0]: 29
8531 13:53:45.508036 [Byte1]: 29
8532 13:53:45.511732
8533 13:53:45.511814 Set Vref, RX VrefLevel [Byte0]: 30
8534 13:53:45.515245 [Byte1]: 30
8535 13:53:45.519578
8536 13:53:45.519659 Set Vref, RX VrefLevel [Byte0]: 31
8537 13:53:45.522498 [Byte1]: 31
8538 13:53:45.526684
8539 13:53:45.526797 Set Vref, RX VrefLevel [Byte0]: 32
8540 13:53:45.530107 [Byte1]: 32
8541 13:53:45.534421
8542 13:53:45.534562 Set Vref, RX VrefLevel [Byte0]: 33
8543 13:53:45.537856 [Byte1]: 33
8544 13:53:45.542470
8545 13:53:45.542553 Set Vref, RX VrefLevel [Byte0]: 34
8546 13:53:45.545576 [Byte1]: 34
8547 13:53:45.549873
8548 13:53:45.549954 Set Vref, RX VrefLevel [Byte0]: 35
8549 13:53:45.552826 [Byte1]: 35
8550 13:53:45.556971
8551 13:53:45.557054 Set Vref, RX VrefLevel [Byte0]: 36
8552 13:53:45.560590 [Byte1]: 36
8553 13:53:45.564762
8554 13:53:45.564853 Set Vref, RX VrefLevel [Byte0]: 37
8555 13:53:45.568236 [Byte1]: 37
8556 13:53:45.572501
8557 13:53:45.572618 Set Vref, RX VrefLevel [Byte0]: 38
8558 13:53:45.575941 [Byte1]: 38
8559 13:53:45.579536
8560 13:53:45.579646 Set Vref, RX VrefLevel [Byte0]: 39
8561 13:53:45.582931 [Byte1]: 39
8562 13:53:45.587301
8563 13:53:45.587405 Set Vref, RX VrefLevel [Byte0]: 40
8564 13:53:45.591030 [Byte1]: 40
8565 13:53:45.594588
8566 13:53:45.594668 Set Vref, RX VrefLevel [Byte0]: 41
8567 13:53:45.598044 [Byte1]: 41
8568 13:53:45.602369
8569 13:53:45.602451 Set Vref, RX VrefLevel [Byte0]: 42
8570 13:53:45.606063 [Byte1]: 42
8571 13:53:45.610276
8572 13:53:45.610357 Set Vref, RX VrefLevel [Byte0]: 43
8573 13:53:45.612950 [Byte1]: 43
8574 13:53:45.617669
8575 13:53:45.617751 Set Vref, RX VrefLevel [Byte0]: 44
8576 13:53:45.620498 [Byte1]: 44
8577 13:53:45.625267
8578 13:53:45.625350 Set Vref, RX VrefLevel [Byte0]: 45
8579 13:53:45.628034 [Byte1]: 45
8580 13:53:45.632326
8581 13:53:45.632431 Set Vref, RX VrefLevel [Byte0]: 46
8582 13:53:45.635689 [Byte1]: 46
8583 13:53:45.639904
8584 13:53:45.639986 Set Vref, RX VrefLevel [Byte0]: 47
8585 13:53:45.643379 [Byte1]: 47
8586 13:53:45.647820
8587 13:53:45.647902 Set Vref, RX VrefLevel [Byte0]: 48
8588 13:53:45.650692 [Byte1]: 48
8589 13:53:45.654971
8590 13:53:45.655053 Set Vref, RX VrefLevel [Byte0]: 49
8591 13:53:45.658461 [Byte1]: 49
8592 13:53:45.662463
8593 13:53:45.662544 Set Vref, RX VrefLevel [Byte0]: 50
8594 13:53:45.665768 [Byte1]: 50
8595 13:53:45.669895
8596 13:53:45.669976 Set Vref, RX VrefLevel [Byte0]: 51
8597 13:53:45.673399 [Byte1]: 51
8598 13:53:45.677495
8599 13:53:45.677576 Set Vref, RX VrefLevel [Byte0]: 52
8600 13:53:45.680821 [Byte1]: 52
8601 13:53:45.685190
8602 13:53:45.685271 Set Vref, RX VrefLevel [Byte0]: 53
8603 13:53:45.688808 [Byte1]: 53
8604 13:53:45.692796
8605 13:53:45.692883 Set Vref, RX VrefLevel [Byte0]: 54
8606 13:53:45.696162 [Byte1]: 54
8607 13:53:45.700412
8608 13:53:45.700518 Set Vref, RX VrefLevel [Byte0]: 55
8609 13:53:45.703268 [Byte1]: 55
8610 13:53:45.708139
8611 13:53:45.708250 Set Vref, RX VrefLevel [Byte0]: 56
8612 13:53:45.711017 [Byte1]: 56
8613 13:53:45.715514
8614 13:53:45.715592 Set Vref, RX VrefLevel [Byte0]: 57
8615 13:53:45.718920 [Byte1]: 57
8616 13:53:45.722878
8617 13:53:45.722962 Set Vref, RX VrefLevel [Byte0]: 58
8618 13:53:45.726241 [Byte1]: 58
8619 13:53:45.730336
8620 13:53:45.730445 Set Vref, RX VrefLevel [Byte0]: 59
8621 13:53:45.733936 [Byte1]: 59
8622 13:53:45.738017
8623 13:53:45.738089 Set Vref, RX VrefLevel [Byte0]: 60
8624 13:53:45.741369 [Byte1]: 60
8625 13:53:45.745648
8626 13:53:45.745757 Set Vref, RX VrefLevel [Byte0]: 61
8627 13:53:45.748579 [Byte1]: 61
8628 13:53:45.752961
8629 13:53:45.753045 Set Vref, RX VrefLevel [Byte0]: 62
8630 13:53:45.756563 [Byte1]: 62
8631 13:53:45.760954
8632 13:53:45.761036 Set Vref, RX VrefLevel [Byte0]: 63
8633 13:53:45.763718 [Byte1]: 63
8634 13:53:45.768106
8635 13:53:45.768187 Set Vref, RX VrefLevel [Byte0]: 64
8636 13:53:45.771899 [Byte1]: 64
8637 13:53:45.776002
8638 13:53:45.776112 Set Vref, RX VrefLevel [Byte0]: 65
8639 13:53:45.778842 [Byte1]: 65
8640 13:53:45.783002
8641 13:53:45.783085 Set Vref, RX VrefLevel [Byte0]: 66
8642 13:53:45.786324 [Byte1]: 66
8643 13:53:45.790405
8644 13:53:45.790482 Set Vref, RX VrefLevel [Byte0]: 67
8645 13:53:45.794318 [Byte1]: 67
8646 13:53:45.798153
8647 13:53:45.798226 Set Vref, RX VrefLevel [Byte0]: 68
8648 13:53:45.801198 [Byte1]: 68
8649 13:53:45.805800
8650 13:53:45.805881 Set Vref, RX VrefLevel [Byte0]: 69
8651 13:53:45.808767 [Byte1]: 69
8652 13:53:45.812935
8653 13:53:45.813016 Set Vref, RX VrefLevel [Byte0]: 70
8654 13:53:45.816748 [Byte1]: 70
8655 13:53:45.820691
8656 13:53:45.820773 Set Vref, RX VrefLevel [Byte0]: 71
8657 13:53:45.824116 [Byte1]: 71
8658 13:53:45.828301
8659 13:53:45.828428 Set Vref, RX VrefLevel [Byte0]: 72
8660 13:53:45.831658 [Byte1]: 72
8661 13:53:45.835749
8662 13:53:45.835829 Set Vref, RX VrefLevel [Byte0]: 73
8663 13:53:45.839218 [Byte1]: 73
8664 13:53:45.843399
8665 13:53:45.843479 Set Vref, RX VrefLevel [Byte0]: 74
8666 13:53:45.846867 [Byte1]: 74
8667 13:53:45.851192
8668 13:53:45.851273 Set Vref, RX VrefLevel [Byte0]: 75
8669 13:53:45.853988 [Byte1]: 75
8670 13:53:45.858325
8671 13:53:45.858406 Set Vref, RX VrefLevel [Byte0]: 76
8672 13:53:45.861827 [Byte1]: 76
8673 13:53:45.866196
8674 13:53:45.866277 Final RX Vref Byte 0 = 57 to rank0
8675 13:53:45.869001 Final RX Vref Byte 1 = 55 to rank0
8676 13:53:45.872749 Final RX Vref Byte 0 = 57 to rank1
8677 13:53:45.875599 Final RX Vref Byte 1 = 55 to rank1==
8678 13:53:45.878976 Dram Type= 6, Freq= 0, CH_1, rank 0
8679 13:53:45.886093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8680 13:53:45.886174 ==
8681 13:53:45.886239 DQS Delay:
8682 13:53:45.886299 DQS0 = 0, DQS1 = 0
8683 13:53:45.889470 DQM Delay:
8684 13:53:45.889551 DQM0 = 134, DQM1 = 131
8685 13:53:45.892786 DQ Delay:
8686 13:53:45.896322 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8687 13:53:45.899151 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8688 13:53:45.902699 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =122
8689 13:53:45.905662 DQ12 =140, DQ13 =138, DQ14 =140, DQ15 =140
8690 13:53:45.905743
8691 13:53:45.905843
8692 13:53:45.905936
8693 13:53:45.909312 [DramC_TX_OE_Calibration] TA2
8694 13:53:45.912537 Original DQ_B0 (3 6) =30, OEN = 27
8695 13:53:45.916008 Original DQ_B1 (3 6) =30, OEN = 27
8696 13:53:45.919590 24, 0x0, End_B0=24 End_B1=24
8697 13:53:45.919673 25, 0x0, End_B0=25 End_B1=25
8698 13:53:45.922503 26, 0x0, End_B0=26 End_B1=26
8699 13:53:45.925791 27, 0x0, End_B0=27 End_B1=27
8700 13:53:45.928974 28, 0x0, End_B0=28 End_B1=28
8701 13:53:45.929056 29, 0x0, End_B0=29 End_B1=29
8702 13:53:45.932184 30, 0x0, End_B0=30 End_B1=30
8703 13:53:45.935828 31, 0x4545, End_B0=30 End_B1=30
8704 13:53:45.938907 Byte0 end_step=30 best_step=27
8705 13:53:45.942547 Byte1 end_step=30 best_step=27
8706 13:53:45.945484 Byte0 TX OE(2T, 0.5T) = (3, 3)
8707 13:53:45.945559 Byte1 TX OE(2T, 0.5T) = (3, 3)
8708 13:53:45.948873
8709 13:53:45.948951
8710 13:53:45.955375 [DQSOSCAuto] RK0, (LSB)MR18= 0x1724, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8711 13:53:45.959333 CH1 RK0: MR19=303, MR18=1724
8712 13:53:45.966019 CH1_RK0: MR19=0x303, MR18=0x1724, DQSOSC=391, MR23=63, INC=24, DEC=16
8713 13:53:45.966113
8714 13:53:45.968765 ----->DramcWriteLeveling(PI) begin...
8715 13:53:45.968839 ==
8716 13:53:45.972372 Dram Type= 6, Freq= 0, CH_1, rank 1
8717 13:53:45.975942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8718 13:53:45.976014 ==
8719 13:53:45.978884 Write leveling (Byte 0): 24 => 24
8720 13:53:45.982423 Write leveling (Byte 1): 28 => 28
8721 13:53:45.986027 DramcWriteLeveling(PI) end<-----
8722 13:53:45.986099
8723 13:53:45.986160 ==
8724 13:53:45.988948 Dram Type= 6, Freq= 0, CH_1, rank 1
8725 13:53:45.992535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 13:53:45.992611 ==
8727 13:53:45.995525 [Gating] SW mode calibration
8728 13:53:46.002246 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8729 13:53:46.009357 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8730 13:53:46.012094 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8731 13:53:46.015521 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8732 13:53:46.022587 1 4 8 | B1->B0 | 2626 2323 | 1 0 | (1 1) (0 0)
8733 13:53:46.025429 1 4 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
8734 13:53:46.029006 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8735 13:53:46.035405 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8736 13:53:46.038776 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8737 13:53:46.042212 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8738 13:53:46.048531 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8739 13:53:46.052046 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8740 13:53:46.055366 1 5 8 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 0)
8741 13:53:46.061985 1 5 12 | B1->B0 | 2424 3131 | 0 0 | (1 0) (0 0)
8742 13:53:46.065602 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 13:53:46.068875 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 13:53:46.075143 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 13:53:46.078546 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 13:53:46.082181 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 13:53:46.088722 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8748 13:53:46.091719 1 6 8 | B1->B0 | 3f3f 2828 | 1 0 | (0 0) (0 0)
8749 13:53:46.095297 1 6 12 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
8750 13:53:46.101703 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 13:53:46.105229 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 13:53:46.108821 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 13:53:46.114932 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 13:53:46.118377 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8755 13:53:46.121753 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 13:53:46.128460 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8757 13:53:46.131766 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8758 13:53:46.135313 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8759 13:53:46.138171 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 13:53:46.145008 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 13:53:46.148574 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 13:53:46.151417 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 13:53:46.158674 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 13:53:46.161363 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 13:53:46.164635 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 13:53:46.171673 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 13:53:46.174619 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 13:53:46.177882 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 13:53:46.185041 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 13:53:46.188360 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 13:53:46.191649 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8772 13:53:46.198328 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8773 13:53:46.201665 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8774 13:53:46.204766 Total UI for P1: 0, mck2ui 16
8775 13:53:46.208104 best dqsien dly found for B1: ( 1, 9, 6)
8776 13:53:46.210857 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 13:53:46.214314 Total UI for P1: 0, mck2ui 16
8778 13:53:46.217752 best dqsien dly found for B0: ( 1, 9, 12)
8779 13:53:46.221388 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8780 13:53:46.223929 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8781 13:53:46.224004
8782 13:53:46.230681 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8783 13:53:46.234100 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8784 13:53:46.237265 [Gating] SW calibration Done
8785 13:53:46.237337 ==
8786 13:53:46.240664 Dram Type= 6, Freq= 0, CH_1, rank 1
8787 13:53:46.244179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8788 13:53:46.244251 ==
8789 13:53:46.244327 RX Vref Scan: 0
8790 13:53:46.244429
8791 13:53:46.247571 RX Vref 0 -> 0, step: 1
8792 13:53:46.247644
8793 13:53:46.251040 RX Delay 0 -> 252, step: 8
8794 13:53:46.254600 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8795 13:53:46.257397 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8796 13:53:46.260979 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8797 13:53:46.267322 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8798 13:53:46.270617 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8799 13:53:46.274162 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8800 13:53:46.277949 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8801 13:53:46.280632 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8802 13:53:46.287777 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8803 13:53:46.290730 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8804 13:53:46.294401 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8805 13:53:46.297238 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8806 13:53:46.304158 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8807 13:53:46.307618 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8808 13:53:46.310421 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8809 13:53:46.313955 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8810 13:53:46.314029 ==
8811 13:53:46.317401 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 13:53:46.320622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 13:53:46.323902 ==
8814 13:53:46.323979 DQS Delay:
8815 13:53:46.324041 DQS0 = 0, DQS1 = 0
8816 13:53:46.327432 DQM Delay:
8817 13:53:46.327509 DQM0 = 136, DQM1 = 133
8818 13:53:46.330875 DQ Delay:
8819 13:53:46.334212 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8820 13:53:46.337097 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8821 13:53:46.340711 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8822 13:53:46.344208 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8823 13:53:46.344305
8824 13:53:46.344420
8825 13:53:46.344483 ==
8826 13:53:46.347282 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 13:53:46.350414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 13:53:46.350495 ==
8829 13:53:46.350559
8830 13:53:46.353607
8831 13:53:46.353689 TX Vref Scan disable
8832 13:53:46.357080 == TX Byte 0 ==
8833 13:53:46.360512 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8834 13:53:46.364233 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8835 13:53:46.367262 == TX Byte 1 ==
8836 13:53:46.370726 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8837 13:53:46.373639 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8838 13:53:46.373724 ==
8839 13:53:46.376991 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 13:53:46.383830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 13:53:46.383905 ==
8842 13:53:46.395917
8843 13:53:46.398924 TX Vref early break, caculate TX vref
8844 13:53:46.402731 TX Vref=16, minBit 0, minWin=23, winSum=383
8845 13:53:46.405446 TX Vref=18, minBit 0, minWin=24, winSum=397
8846 13:53:46.409112 TX Vref=20, minBit 0, minWin=23, winSum=398
8847 13:53:46.412521 TX Vref=22, minBit 2, minWin=24, winSum=409
8848 13:53:46.415408 TX Vref=24, minBit 0, minWin=25, winSum=422
8849 13:53:46.422354 TX Vref=26, minBit 0, minWin=25, winSum=425
8850 13:53:46.425125 TX Vref=28, minBit 0, minWin=26, winSum=428
8851 13:53:46.428525 TX Vref=30, minBit 1, minWin=25, winSum=420
8852 13:53:46.432069 TX Vref=32, minBit 0, minWin=24, winSum=416
8853 13:53:46.435465 TX Vref=34, minBit 0, minWin=24, winSum=405
8854 13:53:46.442188 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
8855 13:53:46.442309
8856 13:53:46.445296 Final TX Range 0 Vref 28
8857 13:53:46.445380
8858 13:53:46.445448 ==
8859 13:53:46.449113 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 13:53:46.451919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 13:53:46.452039 ==
8862 13:53:46.452128
8863 13:53:46.452231
8864 13:53:46.455003 TX Vref Scan disable
8865 13:53:46.461810 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8866 13:53:46.461923 == TX Byte 0 ==
8867 13:53:46.465468 u2DelayCellOfst[0]=16 cells (5 PI)
8868 13:53:46.468689 u2DelayCellOfst[1]=13 cells (4 PI)
8869 13:53:46.472263 u2DelayCellOfst[2]=0 cells (0 PI)
8870 13:53:46.475129 u2DelayCellOfst[3]=6 cells (2 PI)
8871 13:53:46.478687 u2DelayCellOfst[4]=10 cells (3 PI)
8872 13:53:46.481613 u2DelayCellOfst[5]=20 cells (6 PI)
8873 13:53:46.485273 u2DelayCellOfst[6]=20 cells (6 PI)
8874 13:53:46.485374 u2DelayCellOfst[7]=6 cells (2 PI)
8875 13:53:46.492152 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8876 13:53:46.495274 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8877 13:53:46.495351 == TX Byte 1 ==
8878 13:53:46.498388 u2DelayCellOfst[8]=0 cells (0 PI)
8879 13:53:46.501974 u2DelayCellOfst[9]=3 cells (1 PI)
8880 13:53:46.505021 u2DelayCellOfst[10]=10 cells (3 PI)
8881 13:53:46.508401 u2DelayCellOfst[11]=3 cells (1 PI)
8882 13:53:46.512213 u2DelayCellOfst[12]=13 cells (4 PI)
8883 13:53:46.514887 u2DelayCellOfst[13]=13 cells (4 PI)
8884 13:53:46.518407 u2DelayCellOfst[14]=16 cells (5 PI)
8885 13:53:46.522008 u2DelayCellOfst[15]=16 cells (5 PI)
8886 13:53:46.524861 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8887 13:53:46.528363 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8888 13:53:46.531927 DramC Write-DBI on
8889 13:53:46.532000 ==
8890 13:53:46.535507 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 13:53:46.538358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 13:53:46.538429 ==
8893 13:53:46.538504
8894 13:53:46.541937
8895 13:53:46.542032 TX Vref Scan disable
8896 13:53:46.545497 == TX Byte 0 ==
8897 13:53:46.548519 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8898 13:53:46.551861 == TX Byte 1 ==
8899 13:53:46.555283 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8900 13:53:46.555424 DramC Write-DBI off
8901 13:53:46.555513
8902 13:53:46.558505 [DATLAT]
8903 13:53:46.558578 Freq=1600, CH1 RK1
8904 13:53:46.558638
8905 13:53:46.561932 DATLAT Default: 0xf
8906 13:53:46.562020 0, 0xFFFF, sum = 0
8907 13:53:46.564875 1, 0xFFFF, sum = 0
8908 13:53:46.564950 2, 0xFFFF, sum = 0
8909 13:53:46.568576 3, 0xFFFF, sum = 0
8910 13:53:46.568651 4, 0xFFFF, sum = 0
8911 13:53:46.571833 5, 0xFFFF, sum = 0
8912 13:53:46.575151 6, 0xFFFF, sum = 0
8913 13:53:46.575253 7, 0xFFFF, sum = 0
8914 13:53:46.578312 8, 0xFFFF, sum = 0
8915 13:53:46.578394 9, 0xFFFF, sum = 0
8916 13:53:46.581315 10, 0xFFFF, sum = 0
8917 13:53:46.581390 11, 0xFFFF, sum = 0
8918 13:53:46.584767 12, 0xFFFF, sum = 0
8919 13:53:46.584839 13, 0xFFFF, sum = 0
8920 13:53:46.588132 14, 0x0, sum = 1
8921 13:53:46.588237 15, 0x0, sum = 2
8922 13:53:46.591402 16, 0x0, sum = 3
8923 13:53:46.591524 17, 0x0, sum = 4
8924 13:53:46.595210 best_step = 15
8925 13:53:46.595315
8926 13:53:46.595413 ==
8927 13:53:46.598236 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 13:53:46.601430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 13:53:46.601538 ==
8930 13:53:46.601631 RX Vref Scan: 0
8931 13:53:46.604846
8932 13:53:46.604944 RX Vref 0 -> 0, step: 1
8933 13:53:46.605043
8934 13:53:46.608032 RX Delay 19 -> 252, step: 4
8935 13:53:46.611027 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8936 13:53:46.618305 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8937 13:53:46.621099 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8938 13:53:46.624543 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8939 13:53:46.627953 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8940 13:53:46.631495 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8941 13:53:46.634346 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8942 13:53:46.640761 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8943 13:53:46.644200 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8944 13:53:46.647866 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8945 13:53:46.651367 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8946 13:53:46.654344 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8947 13:53:46.661410 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8948 13:53:46.664356 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8949 13:53:46.667780 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8950 13:53:46.671182 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
8951 13:53:46.671283 ==
8952 13:53:46.674792 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 13:53:46.681208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 13:53:46.681325 ==
8955 13:53:46.681427 DQS Delay:
8956 13:53:46.684108 DQS0 = 0, DQS1 = 0
8957 13:53:46.684228 DQM Delay:
8958 13:53:46.687870 DQM0 = 134, DQM1 = 130
8959 13:53:46.687950 DQ Delay:
8960 13:53:46.691085 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8961 13:53:46.694335 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8962 13:53:46.697494 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8963 13:53:46.700603 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =142
8964 13:53:46.700688
8965 13:53:46.700777
8966 13:53:46.700864
8967 13:53:46.704258 [DramC_TX_OE_Calibration] TA2
8968 13:53:46.707269 Original DQ_B0 (3 6) =30, OEN = 27
8969 13:53:46.710499 Original DQ_B1 (3 6) =30, OEN = 27
8970 13:53:46.713969 24, 0x0, End_B0=24 End_B1=24
8971 13:53:46.714078 25, 0x0, End_B0=25 End_B1=25
8972 13:53:46.717550 26, 0x0, End_B0=26 End_B1=26
8973 13:53:46.720934 27, 0x0, End_B0=27 End_B1=27
8974 13:53:46.723995 28, 0x0, End_B0=28 End_B1=28
8975 13:53:46.727168 29, 0x0, End_B0=29 End_B1=29
8976 13:53:46.727254 30, 0x0, End_B0=30 End_B1=30
8977 13:53:46.730902 31, 0x4141, End_B0=30 End_B1=30
8978 13:53:46.734005 Byte0 end_step=30 best_step=27
8979 13:53:46.737230 Byte1 end_step=30 best_step=27
8980 13:53:46.740476 Byte0 TX OE(2T, 0.5T) = (3, 3)
8981 13:53:46.743847 Byte1 TX OE(2T, 0.5T) = (3, 3)
8982 13:53:46.743952
8983 13:53:46.744082
8984 13:53:46.751010 [DQSOSCAuto] RK1, (LSB)MR18= 0x2409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
8985 13:53:46.753762 CH1 RK1: MR19=303, MR18=2409
8986 13:53:46.761043 CH1_RK1: MR19=0x303, MR18=0x2409, DQSOSC=391, MR23=63, INC=24, DEC=16
8987 13:53:46.763907 [RxdqsGatingPostProcess] freq 1600
8988 13:53:46.767258 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8989 13:53:46.770950 best DQS0 dly(2T, 0.5T) = (1, 1)
8990 13:53:46.773805 best DQS1 dly(2T, 0.5T) = (1, 1)
8991 13:53:46.777416 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8992 13:53:46.780878 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8993 13:53:46.784006 best DQS0 dly(2T, 0.5T) = (1, 1)
8994 13:53:46.787016 best DQS1 dly(2T, 0.5T) = (1, 1)
8995 13:53:46.790607 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8996 13:53:46.793583 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8997 13:53:46.797100 Pre-setting of DQS Precalculation
8998 13:53:46.800727 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8999 13:53:46.806915 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9000 13:53:46.817403 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9001 13:53:46.817557
9002 13:53:46.817651
9003 13:53:46.817723 [Calibration Summary] 3200 Mbps
9004 13:53:46.820639 CH 0, Rank 0
9005 13:53:46.820722 SW Impedance : PASS
9006 13:53:46.823629 DUTY Scan : NO K
9007 13:53:46.826877 ZQ Calibration : PASS
9008 13:53:46.826959 Jitter Meter : NO K
9009 13:53:46.830381 CBT Training : PASS
9010 13:53:46.833963 Write leveling : PASS
9011 13:53:46.834049 RX DQS gating : PASS
9012 13:53:46.837305 RX DQ/DQS(RDDQC) : PASS
9013 13:53:46.840025 TX DQ/DQS : PASS
9014 13:53:46.840102 RX DATLAT : PASS
9015 13:53:46.844037 RX DQ/DQS(Engine): PASS
9016 13:53:46.847351 TX OE : PASS
9017 13:53:46.847447 All Pass.
9018 13:53:46.847548
9019 13:53:46.847645 CH 0, Rank 1
9020 13:53:46.850524 SW Impedance : PASS
9021 13:53:46.854243 DUTY Scan : NO K
9022 13:53:46.854334 ZQ Calibration : PASS
9023 13:53:46.856856 Jitter Meter : NO K
9024 13:53:46.860631 CBT Training : PASS
9025 13:53:46.860713 Write leveling : PASS
9026 13:53:46.863468 RX DQS gating : PASS
9027 13:53:46.866984 RX DQ/DQS(RDDQC) : PASS
9028 13:53:46.867059 TX DQ/DQS : PASS
9029 13:53:46.870432 RX DATLAT : PASS
9030 13:53:46.870533 RX DQ/DQS(Engine): PASS
9031 13:53:46.873285 TX OE : PASS
9032 13:53:46.873389 All Pass.
9033 13:53:46.873484
9034 13:53:46.877002 CH 1, Rank 0
9035 13:53:46.877114 SW Impedance : PASS
9036 13:53:46.880520 DUTY Scan : NO K
9037 13:53:46.883469 ZQ Calibration : PASS
9038 13:53:46.883548 Jitter Meter : NO K
9039 13:53:46.887152 CBT Training : PASS
9040 13:53:46.890076 Write leveling : PASS
9041 13:53:46.890180 RX DQS gating : PASS
9042 13:53:46.893510 RX DQ/DQS(RDDQC) : PASS
9043 13:53:46.896900 TX DQ/DQS : PASS
9044 13:53:46.897018 RX DATLAT : PASS
9045 13:53:46.900548 RX DQ/DQS(Engine): PASS
9046 13:53:46.903323 TX OE : PASS
9047 13:53:46.903399 All Pass.
9048 13:53:46.903462
9049 13:53:46.903525 CH 1, Rank 1
9050 13:53:46.906892 SW Impedance : PASS
9051 13:53:46.910448 DUTY Scan : NO K
9052 13:53:46.910527 ZQ Calibration : PASS
9053 13:53:46.913311 Jitter Meter : NO K
9054 13:53:46.917073 CBT Training : PASS
9055 13:53:46.917181 Write leveling : PASS
9056 13:53:46.919946 RX DQS gating : PASS
9057 13:53:46.920025 RX DQ/DQS(RDDQC) : PASS
9058 13:53:46.923628 TX DQ/DQS : PASS
9059 13:53:46.926609 RX DATLAT : PASS
9060 13:53:46.926686 RX DQ/DQS(Engine): PASS
9061 13:53:46.930055 TX OE : PASS
9062 13:53:46.930165 All Pass.
9063 13:53:46.930259
9064 13:53:46.933863 DramC Write-DBI on
9065 13:53:46.937115 PER_BANK_REFRESH: Hybrid Mode
9066 13:53:46.937193 TX_TRACKING: ON
9067 13:53:46.946657 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9068 13:53:46.953778 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9069 13:53:46.960232 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9070 13:53:46.963497 [FAST_K] Save calibration result to emmc
9071 13:53:46.966878 sync common calibartion params.
9072 13:53:46.969976 sync cbt_mode0:1, 1:1
9073 13:53:46.973266 dram_init: ddr_geometry: 2
9074 13:53:46.973394 dram_init: ddr_geometry: 2
9075 13:53:46.977223 dram_init: ddr_geometry: 2
9076 13:53:46.979984 0:dram_rank_size:100000000
9077 13:53:46.983699 1:dram_rank_size:100000000
9078 13:53:46.987096 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9079 13:53:46.989975 DFS_SHUFFLE_HW_MODE: ON
9080 13:53:46.993463 dramc_set_vcore_voltage set vcore to 725000
9081 13:53:46.997078 Read voltage for 1600, 0
9082 13:53:46.997154 Vio18 = 0
9083 13:53:46.997226 Vcore = 725000
9084 13:53:47.000382 Vdram = 0
9085 13:53:47.000463 Vddq = 0
9086 13:53:47.000524 Vmddr = 0
9087 13:53:47.003153 switch to 3200 Mbps bootup
9088 13:53:47.006485 [DramcRunTimeConfig]
9089 13:53:47.006586 PHYPLL
9090 13:53:47.006685 DPM_CONTROL_AFTERK: ON
9091 13:53:47.010251 PER_BANK_REFRESH: ON
9092 13:53:47.013570 REFRESH_OVERHEAD_REDUCTION: ON
9093 13:53:47.013651 CMD_PICG_NEW_MODE: OFF
9094 13:53:47.017026 XRTWTW_NEW_MODE: ON
9095 13:53:47.019903 XRTRTR_NEW_MODE: ON
9096 13:53:47.019993 TX_TRACKING: ON
9097 13:53:47.023518 RDSEL_TRACKING: OFF
9098 13:53:47.023596 DQS Precalculation for DVFS: ON
9099 13:53:47.026474 RX_TRACKING: OFF
9100 13:53:47.026590 HW_GATING DBG: ON
9101 13:53:47.030174 ZQCS_ENABLE_LP4: ON
9102 13:53:47.030259 RX_PICG_NEW_MODE: ON
9103 13:53:47.032997 TX_PICG_NEW_MODE: ON
9104 13:53:47.036614 ENABLE_RX_DCM_DPHY: ON
9105 13:53:47.040006 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9106 13:53:47.040085 DUMMY_READ_FOR_TRACKING: OFF
9107 13:53:47.043255 !!! SPM_CONTROL_AFTERK: OFF
9108 13:53:47.046648 !!! SPM could not control APHY
9109 13:53:47.049988 IMPEDANCE_TRACKING: ON
9110 13:53:47.050096 TEMP_SENSOR: ON
9111 13:53:47.053330 HW_SAVE_FOR_SR: OFF
9112 13:53:47.053467 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9113 13:53:47.059896 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9114 13:53:47.060047 Read ODT Tracking: ON
9115 13:53:47.063307 Refresh Rate DeBounce: ON
9116 13:53:47.063438 DFS_NO_QUEUE_FLUSH: ON
9117 13:53:47.066771 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9118 13:53:47.069444 ENABLE_DFS_RUNTIME_MRW: OFF
9119 13:53:47.072917 DDR_RESERVE_NEW_MODE: ON
9120 13:53:47.073042 MR_CBT_SWITCH_FREQ: ON
9121 13:53:47.076541 =========================
9122 13:53:47.095869 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9123 13:53:47.098768 dram_init: ddr_geometry: 2
9124 13:53:47.117076 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9125 13:53:47.120523 dram_init: dram init end (result: 0)
9126 13:53:47.127521 DRAM-K: Full calibration passed in 24436 msecs
9127 13:53:47.130676 MRC: failed to locate region type 0.
9128 13:53:47.130765 DRAM rank0 size:0x100000000,
9129 13:53:47.134289 DRAM rank1 size=0x100000000
9130 13:53:47.144120 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9131 13:53:47.150345 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9132 13:53:47.157592 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9133 13:53:47.163570 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9134 13:53:47.167054 DRAM rank0 size:0x100000000,
9135 13:53:47.170515 DRAM rank1 size=0x100000000
9136 13:53:47.170621 CBMEM:
9137 13:53:47.173372 IMD: root @ 0xfffff000 254 entries.
9138 13:53:47.176627 IMD: root @ 0xffffec00 62 entries.
9139 13:53:47.179914 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9140 13:53:47.186756 WARNING: RO_VPD is uninitialized or empty.
9141 13:53:47.190065 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9142 13:53:47.197468 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9143 13:53:47.210093 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9144 13:53:47.221480 BS: romstage times (exec / console): total (unknown) / 23971 ms
9145 13:53:47.221572
9146 13:53:47.221637
9147 13:53:47.231890 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9148 13:53:47.234651 ARM64: Exception handlers installed.
9149 13:53:47.237845 ARM64: Testing exception
9150 13:53:47.241741 ARM64: Done test exception
9151 13:53:47.241824 Enumerating buses...
9152 13:53:47.245097 Show all devs... Before device enumeration.
9153 13:53:47.247946 Root Device: enabled 1
9154 13:53:47.251508 CPU_CLUSTER: 0: enabled 1
9155 13:53:47.251593 CPU: 00: enabled 1
9156 13:53:47.254867 Compare with tree...
9157 13:53:47.254961 Root Device: enabled 1
9158 13:53:47.258268 CPU_CLUSTER: 0: enabled 1
9159 13:53:47.261623 CPU: 00: enabled 1
9160 13:53:47.261706 Root Device scanning...
9161 13:53:47.264462 scan_static_bus for Root Device
9162 13:53:47.267984 CPU_CLUSTER: 0 enabled
9163 13:53:47.271184 scan_static_bus for Root Device done
9164 13:53:47.274676 scan_bus: bus Root Device finished in 8 msecs
9165 13:53:47.274778 done
9166 13:53:47.281072 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9167 13:53:47.284534 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9168 13:53:47.291369 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9169 13:53:47.294640 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9170 13:53:47.297986 Allocating resources...
9171 13:53:47.301186 Reading resources...
9172 13:53:47.304310 Root Device read_resources bus 0 link: 0
9173 13:53:47.304404 DRAM rank0 size:0x100000000,
9174 13:53:47.307558 DRAM rank1 size=0x100000000
9175 13:53:47.310868 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9176 13:53:47.314267 CPU: 00 missing read_resources
9177 13:53:47.321273 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9178 13:53:47.324078 Root Device read_resources bus 0 link: 0 done
9179 13:53:47.324151 Done reading resources.
9180 13:53:47.330655 Show resources in subtree (Root Device)...After reading.
9181 13:53:47.334290 Root Device child on link 0 CPU_CLUSTER: 0
9182 13:53:47.337819 CPU_CLUSTER: 0 child on link 0 CPU: 00
9183 13:53:47.347686 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9184 13:53:47.347798 CPU: 00
9185 13:53:47.351064 Root Device assign_resources, bus 0 link: 0
9186 13:53:47.354241 CPU_CLUSTER: 0 missing set_resources
9187 13:53:47.361009 Root Device assign_resources, bus 0 link: 0 done
9188 13:53:47.361093 Done setting resources.
9189 13:53:47.367576 Show resources in subtree (Root Device)...After assigning values.
9190 13:53:47.371123 Root Device child on link 0 CPU_CLUSTER: 0
9191 13:53:47.374022 CPU_CLUSTER: 0 child on link 0 CPU: 00
9192 13:53:47.384161 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9193 13:53:47.384246 CPU: 00
9194 13:53:47.387121 Done allocating resources.
9195 13:53:47.390657 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9196 13:53:47.394118 Enabling resources...
9197 13:53:47.394200 done.
9198 13:53:47.401026 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9199 13:53:47.401107 Initializing devices...
9200 13:53:47.403777 Root Device init
9201 13:53:47.403859 init hardware done!
9202 13:53:47.407328 0x00000018: ctrlr->caps
9203 13:53:47.411012 52.000 MHz: ctrlr->f_max
9204 13:53:47.411094 0.400 MHz: ctrlr->f_min
9205 13:53:47.414441 0x40ff8080: ctrlr->voltages
9206 13:53:47.414534 sclk: 390625
9207 13:53:47.417707 Bus Width = 1
9208 13:53:47.417787 sclk: 390625
9209 13:53:47.420225 Bus Width = 1
9210 13:53:47.420306 Early init status = 3
9211 13:53:47.427362 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9212 13:53:47.430766 in-header: 03 fc 00 00 01 00 00 00
9213 13:53:47.430869 in-data: 00
9214 13:53:47.437211 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9215 13:53:47.440799 in-header: 03 fd 00 00 00 00 00 00
9216 13:53:47.444287 in-data:
9217 13:53:47.447169 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9218 13:53:47.452189 in-header: 03 fc 00 00 01 00 00 00
9219 13:53:47.454934 in-data: 00
9220 13:53:47.458450 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9221 13:53:47.464079 in-header: 03 fd 00 00 00 00 00 00
9222 13:53:47.467246 in-data:
9223 13:53:47.470407 [SSUSB] Setting up USB HOST controller...
9224 13:53:47.474025 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9225 13:53:47.477052 [SSUSB] phy power-on done.
9226 13:53:47.480849 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9227 13:53:47.487358 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9228 13:53:47.490667 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9229 13:53:47.497084 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9230 13:53:47.504092 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9231 13:53:47.510245 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9232 13:53:47.517386 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9233 13:53:47.523852 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9234 13:53:47.527383 SPM: binary array size = 0x9dc
9235 13:53:47.530831 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9236 13:53:47.536907 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9237 13:53:47.543788 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9238 13:53:47.547282 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9239 13:53:47.553579 configure_display: Starting display init
9240 13:53:47.587407 anx7625_power_on_init: Init interface.
9241 13:53:47.590855 anx7625_disable_pd_protocol: Disabled PD feature.
9242 13:53:47.594070 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9243 13:53:47.621719 anx7625_start_dp_work: Secure OCM version=00
9244 13:53:47.625206 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9245 13:53:47.639453 sp_tx_get_edid_block: EDID Block = 1
9246 13:53:47.742436 Extracted contents:
9247 13:53:47.746088 header: 00 ff ff ff ff ff ff 00
9248 13:53:47.748976 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9249 13:53:47.752539 version: 01 04
9250 13:53:47.755993 basic params: 95 1f 11 78 0a
9251 13:53:47.758758 chroma info: 76 90 94 55 54 90 27 21 50 54
9252 13:53:47.762156 established: 00 00 00
9253 13:53:47.768990 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9254 13:53:47.771918 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9255 13:53:47.779094 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9256 13:53:47.785553 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9257 13:53:47.792059 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9258 13:53:47.795386 extensions: 00
9259 13:53:47.795470 checksum: fb
9260 13:53:47.795555
9261 13:53:47.799183 Manufacturer: IVO Model 57d Serial Number 0
9262 13:53:47.802583 Made week 0 of 2020
9263 13:53:47.802705 EDID version: 1.4
9264 13:53:47.805368 Digital display
9265 13:53:47.808990 6 bits per primary color channel
9266 13:53:47.809076 DisplayPort interface
9267 13:53:47.811779 Maximum image size: 31 cm x 17 cm
9268 13:53:47.815411 Gamma: 220%
9269 13:53:47.815495 Check DPMS levels
9270 13:53:47.818946 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9271 13:53:47.821800 First detailed timing is preferred timing
9272 13:53:47.825244 Established timings supported:
9273 13:53:47.828938 Standard timings supported:
9274 13:53:47.829031 Detailed timings
9275 13:53:47.835050 Hex of detail: 383680a07038204018303c0035ae10000019
9276 13:53:47.838823 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9277 13:53:47.845457 0780 0798 07c8 0820 hborder 0
9278 13:53:47.848703 0438 043b 0447 0458 vborder 0
9279 13:53:47.851748 -hsync -vsync
9280 13:53:47.851855 Did detailed timing
9281 13:53:47.855267 Hex of detail: 000000000000000000000000000000000000
9282 13:53:47.858393 Manufacturer-specified data, tag 0
9283 13:53:47.865323 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9284 13:53:47.865444 ASCII string: InfoVision
9285 13:53:47.871724 Hex of detail: 000000fe00523134304e574635205248200a
9286 13:53:47.875529 ASCII string: R140NWF5 RH
9287 13:53:47.875653 Checksum
9288 13:53:47.875779 Checksum: 0xfb (valid)
9289 13:53:47.881759 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9290 13:53:47.885340 DSI data_rate: 832800000 bps
9291 13:53:47.888255 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9292 13:53:47.895345 anx7625_parse_edid: pixelclock(138800).
9293 13:53:47.898275 hactive(1920), hsync(48), hfp(24), hbp(88)
9294 13:53:47.901723 vactive(1080), vsync(12), vfp(3), vbp(17)
9295 13:53:47.905205 anx7625_dsi_config: config dsi.
9296 13:53:47.911580 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9297 13:53:47.924528 anx7625_dsi_config: success to config DSI
9298 13:53:47.927405 anx7625_dp_start: MIPI phy setup OK.
9299 13:53:47.931137 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9300 13:53:47.934597 mtk_ddp_mode_set invalid vrefresh 60
9301 13:53:47.937503 main_disp_path_setup
9302 13:53:47.937588 ovl_layer_smi_id_en
9303 13:53:47.941220 ovl_layer_smi_id_en
9304 13:53:47.941305 ccorr_config
9305 13:53:47.941369 aal_config
9306 13:53:47.944115 gamma_config
9307 13:53:47.944224 postmask_config
9308 13:53:47.947471 dither_config
9309 13:53:47.951068 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9310 13:53:47.957623 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9311 13:53:47.961130 Root Device init finished in 553 msecs
9312 13:53:47.964105 CPU_CLUSTER: 0 init
9313 13:53:47.971038 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9314 13:53:47.974429 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9315 13:53:47.977127 APU_MBOX 0x190000b0 = 0x10001
9316 13:53:47.980585 APU_MBOX 0x190001b0 = 0x10001
9317 13:53:47.983830 APU_MBOX 0x190005b0 = 0x10001
9318 13:53:47.987655 APU_MBOX 0x190006b0 = 0x10001
9319 13:53:47.990339 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9320 13:53:48.003593 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9321 13:53:48.015974 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9322 13:53:48.022189 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9323 13:53:48.034166 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9324 13:53:48.043450 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9325 13:53:48.046430 CPU_CLUSTER: 0 init finished in 81 msecs
9326 13:53:48.050015 Devices initialized
9327 13:53:48.053592 Show all devs... After init.
9328 13:53:48.053677 Root Device: enabled 1
9329 13:53:48.056377 CPU_CLUSTER: 0: enabled 1
9330 13:53:48.060002 CPU: 00: enabled 1
9331 13:53:48.063193 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9332 13:53:48.066768 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9333 13:53:48.069484 ELOG: NV offset 0x57f000 size 0x1000
9334 13:53:48.075968 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9335 13:53:48.083111 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9336 13:53:48.086695 ELOG: Event(17) added with size 13 at 2024-05-16 13:49:09 UTC
9337 13:53:48.089619 out: cmd=0x121: 03 db 21 01 00 00 00 00
9338 13:53:48.094018 in-header: 03 d2 00 00 2c 00 00 00
9339 13:53:48.106615 in-data: 8c 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9340 13:53:48.113737 ELOG: Event(A1) added with size 10 at 2024-05-16 13:49:09 UTC
9341 13:53:48.120200 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9342 13:53:48.123769 ELOG: Event(A0) added with size 9 at 2024-05-16 13:49:09 UTC
9343 13:53:48.130253 elog_add_boot_reason: Logged dev mode boot
9344 13:53:48.133827 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9345 13:53:48.136631 Finalize devices...
9346 13:53:48.136714 Devices finalized
9347 13:53:48.143724 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9348 13:53:48.146594 Writing coreboot table at 0xffe64000
9349 13:53:48.150371 0. 000000000010a000-0000000000113fff: RAMSTAGE
9350 13:53:48.153280 1. 0000000040000000-00000000400fffff: RAM
9351 13:53:48.156779 2. 0000000040100000-000000004032afff: RAMSTAGE
9352 13:53:48.160050 3. 000000004032b000-00000000545fffff: RAM
9353 13:53:48.166751 4. 0000000054600000-000000005465ffff: BL31
9354 13:53:48.170400 5. 0000000054660000-00000000ffe63fff: RAM
9355 13:53:48.173362 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9356 13:53:48.179859 7. 0000000100000000-000000023fffffff: RAM
9357 13:53:48.179939 Passing 5 GPIOs to payload:
9358 13:53:48.186945 NAME | PORT | POLARITY | VALUE
9359 13:53:48.190340 EC in RW | 0x000000aa | low | undefined
9360 13:53:48.193140 EC interrupt | 0x00000005 | low | undefined
9361 13:53:48.200478 TPM interrupt | 0x000000ab | high | undefined
9362 13:53:48.203439 SD card detect | 0x00000011 | high | undefined
9363 13:53:48.210234 speaker enable | 0x00000093 | high | undefined
9364 13:53:48.213550 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9365 13:53:48.216876 in-header: 03 f9 00 00 02 00 00 00
9366 13:53:48.216972 in-data: 02 00
9367 13:53:48.220264 ADC[4]: Raw value=904726 ID=7
9368 13:53:48.223547 ADC[3]: Raw value=213810 ID=1
9369 13:53:48.223661 RAM Code: 0x71
9370 13:53:48.226595 ADC[6]: Raw value=75701 ID=0
9371 13:53:48.230149 ADC[5]: Raw value=212703 ID=1
9372 13:53:48.230243 SKU Code: 0x1
9373 13:53:48.237036 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 6f92
9374 13:53:48.240232 coreboot table: 964 bytes.
9375 13:53:48.243010 IMD ROOT 0. 0xfffff000 0x00001000
9376 13:53:48.246742 IMD SMALL 1. 0xffffe000 0x00001000
9377 13:53:48.249691 RO MCACHE 2. 0xffffc000 0x00001104
9378 13:53:48.253407 CONSOLE 3. 0xfff7c000 0x00080000
9379 13:53:48.256351 FMAP 4. 0xfff7b000 0x00000452
9380 13:53:48.259899 TIME STAMP 5. 0xfff7a000 0x00000910
9381 13:53:48.263289 VBOOT WORK 6. 0xfff66000 0x00014000
9382 13:53:48.266575 RAMOOPS 7. 0xffe66000 0x00100000
9383 13:53:48.270297 COREBOOT 8. 0xffe64000 0x00002000
9384 13:53:48.270387 IMD small region:
9385 13:53:48.273182 IMD ROOT 0. 0xffffec00 0x00000400
9386 13:53:48.276860 VPD 1. 0xffffeb80 0x0000006c
9387 13:53:48.279708 MMC STATUS 2. 0xffffeb60 0x00000004
9388 13:53:48.286872 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9389 13:53:48.286960 Probing TPM: done!
9390 13:53:48.293249 Connected to device vid:did:rid of 1ae0:0028:00
9391 13:53:48.300099 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9392 13:53:48.303042 Initialized TPM device CR50 revision 0
9393 13:53:48.307352 Checking cr50 for pending updates
9394 13:53:48.313281 Reading cr50 TPM mode
9395 13:53:48.321666 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9396 13:53:48.327685 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9397 13:53:48.368306 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9398 13:53:48.371645 Checking segment from ROM address 0x40100000
9399 13:53:48.375144 Checking segment from ROM address 0x4010001c
9400 13:53:48.381442 Loading segment from ROM address 0x40100000
9401 13:53:48.381525 code (compression=0)
9402 13:53:48.388594 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9403 13:53:48.398444 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9404 13:53:48.398548 it's not compressed!
9405 13:53:48.404875 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9406 13:53:48.408373 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9407 13:53:48.428893 Loading segment from ROM address 0x4010001c
9408 13:53:48.428986 Entry Point 0x80000000
9409 13:53:48.432215 Loaded segments
9410 13:53:48.435510 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9411 13:53:48.441904 Jumping to boot code at 0x80000000(0xffe64000)
9412 13:53:48.448770 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9413 13:53:48.455194 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9414 13:53:48.463183 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9415 13:53:48.466351 Checking segment from ROM address 0x40100000
9416 13:53:48.469394 Checking segment from ROM address 0x4010001c
9417 13:53:48.476474 Loading segment from ROM address 0x40100000
9418 13:53:48.476560 code (compression=1)
9419 13:53:48.482997 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9420 13:53:48.492861 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9421 13:53:48.492957 using LZMA
9422 13:53:48.501684 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9423 13:53:48.508090 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9424 13:53:48.511522 Loading segment from ROM address 0x4010001c
9425 13:53:48.511598 Entry Point 0x54601000
9426 13:53:48.514960 Loaded segments
9427 13:53:48.517844 NOTICE: MT8192 bl31_setup
9428 13:53:48.525150 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9429 13:53:48.528151 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9430 13:53:48.531857 WARNING: region 0:
9431 13:53:48.535428 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9432 13:53:48.535521 WARNING: region 1:
9433 13:53:48.541540 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9434 13:53:48.544987 WARNING: region 2:
9435 13:53:48.548506 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9436 13:53:48.551441 WARNING: region 3:
9437 13:53:48.554950 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9438 13:53:48.558369 WARNING: region 4:
9439 13:53:48.565455 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9440 13:53:48.565557 WARNING: region 5:
9441 13:53:48.568679 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9442 13:53:48.571907 WARNING: region 6:
9443 13:53:48.575160 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9444 13:53:48.578336 WARNING: region 7:
9445 13:53:48.581903 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9446 13:53:48.588503 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9447 13:53:48.592022 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9448 13:53:48.595223 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9449 13:53:48.601633 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9450 13:53:48.604904 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9451 13:53:48.608364 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9452 13:53:48.615423 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9453 13:53:48.618268 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9454 13:53:48.625254 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9455 13:53:48.628707 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9456 13:53:48.631632 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9457 13:53:48.638616 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9458 13:53:48.641396 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9459 13:53:48.644981 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9460 13:53:48.651724 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9461 13:53:48.655234 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9462 13:53:48.658067 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9463 13:53:48.665354 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9464 13:53:48.668233 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9465 13:53:48.675363 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9466 13:53:48.678260 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9467 13:53:48.681573 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9468 13:53:48.688626 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9469 13:53:48.692018 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9470 13:53:48.698717 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9471 13:53:48.701609 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9472 13:53:48.705061 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9473 13:53:48.712216 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9474 13:53:48.715517 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9475 13:53:48.718752 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9476 13:53:48.725660 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9477 13:53:48.728834 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9478 13:53:48.732232 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9479 13:53:48.738346 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9480 13:53:48.742093 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9481 13:53:48.745666 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9482 13:53:48.748564 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9483 13:53:48.755021 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9484 13:53:48.759048 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9485 13:53:48.761930 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9486 13:53:48.765571 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9487 13:53:48.771837 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9488 13:53:48.775415 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9489 13:53:48.779111 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9490 13:53:48.781890 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9491 13:53:48.788873 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9492 13:53:48.792502 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9493 13:53:48.795310 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9494 13:53:48.802282 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9495 13:53:48.805823 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9496 13:53:48.809295 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9497 13:53:48.815294 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9498 13:53:48.819171 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9499 13:53:48.825626 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9500 13:53:48.828810 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9501 13:53:48.835805 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9502 13:53:48.838986 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9503 13:53:48.842251 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9504 13:53:48.849172 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9505 13:53:48.852432 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9506 13:53:48.859248 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9507 13:53:48.862017 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9508 13:53:48.868765 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9509 13:53:48.872266 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9510 13:53:48.875867 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9511 13:53:48.882332 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9512 13:53:48.885910 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9513 13:53:48.892123 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9514 13:53:48.895757 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9515 13:53:48.899179 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9516 13:53:48.906357 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9517 13:53:48.909107 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9518 13:53:48.916399 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9519 13:53:48.919353 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9520 13:53:48.926060 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9521 13:53:48.929713 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9522 13:53:48.933093 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9523 13:53:48.939506 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9524 13:53:48.942891 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9525 13:53:48.949975 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9526 13:53:48.952712 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9527 13:53:48.959814 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9528 13:53:48.963194 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9529 13:53:48.966437 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9530 13:53:48.972892 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9531 13:53:48.976560 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9532 13:53:48.982913 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9533 13:53:48.986227 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9534 13:53:48.989727 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9535 13:53:48.996720 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9536 13:53:49.000130 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9537 13:53:49.006486 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9538 13:53:49.009935 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9539 13:53:49.016246 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9540 13:53:49.019906 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9541 13:53:49.026395 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9542 13:53:49.029755 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9543 13:53:49.033085 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9544 13:53:49.036615 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9545 13:53:49.040167 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9546 13:53:49.046589 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9547 13:53:49.049900 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9548 13:53:49.056917 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9549 13:53:49.059777 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9550 13:53:49.063252 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9551 13:53:49.070238 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9552 13:53:49.073752 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9553 13:53:49.079994 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9554 13:53:49.083415 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9555 13:53:49.086854 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9556 13:53:49.093784 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9557 13:53:49.096927 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9558 13:53:49.100154 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9559 13:53:49.106738 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9560 13:53:49.110095 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9561 13:53:49.117207 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9562 13:53:49.120078 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9563 13:53:49.123612 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9564 13:53:49.130151 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9565 13:53:49.133710 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9566 13:53:49.137007 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9567 13:53:49.140344 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9568 13:53:49.143824 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9569 13:53:49.150252 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9570 13:53:49.153739 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9571 13:53:49.157307 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9572 13:53:49.163535 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9573 13:53:49.166858 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9574 13:53:49.173956 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9575 13:53:49.177479 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9576 13:53:49.180265 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9577 13:53:49.187231 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9578 13:53:49.190890 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9579 13:53:49.197227 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9580 13:53:49.200759 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9581 13:53:49.203982 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9582 13:53:49.210455 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9583 13:53:49.213713 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9584 13:53:49.217014 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9585 13:53:49.224099 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9586 13:53:49.227433 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9587 13:53:49.233700 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9588 13:53:49.237405 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9589 13:53:49.240761 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9590 13:53:49.247415 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9591 13:53:49.250861 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9592 13:53:49.253728 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9593 13:53:49.260855 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9594 13:53:49.264217 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9595 13:53:49.271061 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9596 13:53:49.273823 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9597 13:53:49.277462 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9598 13:53:49.283958 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9599 13:53:49.287248 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9600 13:53:49.290720 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9601 13:53:49.297315 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9602 13:53:49.300757 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9603 13:53:49.307283 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9604 13:53:49.310764 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9605 13:53:49.314317 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9606 13:53:49.320612 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9607 13:53:49.323920 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9608 13:53:49.330548 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9609 13:53:49.333940 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9610 13:53:49.337473 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9611 13:53:49.343946 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9612 13:53:49.347434 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9613 13:53:49.353843 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9614 13:53:49.357239 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9615 13:53:49.360802 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9616 13:53:49.367352 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9617 13:53:49.370771 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9618 13:53:49.374101 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9619 13:53:49.380689 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9620 13:53:49.384439 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9621 13:53:49.390736 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9622 13:53:49.394197 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9623 13:53:49.397427 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9624 13:53:49.403698 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9625 13:53:49.407390 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9626 13:53:49.413845 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9627 13:53:49.417379 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9628 13:53:49.420934 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9629 13:53:49.427138 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9630 13:53:49.430778 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9631 13:53:49.437489 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9632 13:53:49.440978 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9633 13:53:49.443774 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9634 13:53:49.450460 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9635 13:53:49.453849 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9636 13:53:49.460644 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9637 13:53:49.463653 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9638 13:53:49.466808 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9639 13:53:49.474067 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9640 13:53:49.476845 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9641 13:53:49.483953 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9642 13:53:49.486690 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9643 13:53:49.490567 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9644 13:53:49.496912 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9645 13:53:49.500451 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9646 13:53:49.506752 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9647 13:53:49.510352 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9648 13:53:49.513874 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9649 13:53:49.520184 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9650 13:53:49.523647 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9651 13:53:49.529906 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9652 13:53:49.533283 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9653 13:53:49.540397 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9654 13:53:49.543915 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9655 13:53:49.546741 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9656 13:53:49.553561 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9657 13:53:49.556455 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9658 13:53:49.563490 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9659 13:53:49.567070 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9660 13:53:49.569808 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9661 13:53:49.576519 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9662 13:53:49.580219 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9663 13:53:49.586852 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9664 13:53:49.589872 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9665 13:53:49.596696 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9666 13:53:49.600080 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9667 13:53:49.603595 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9668 13:53:49.609961 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9669 13:53:49.613449 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9670 13:53:49.619828 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9671 13:53:49.623467 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9672 13:53:49.626269 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9673 13:53:49.633256 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9674 13:53:49.636777 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9675 13:53:49.640255 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9676 13:53:49.646460 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9677 13:53:49.649925 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9678 13:53:49.653337 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9679 13:53:49.656843 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9680 13:53:49.663231 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9681 13:53:49.666877 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9682 13:53:49.673324 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9683 13:53:49.676187 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9684 13:53:49.679792 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9685 13:53:49.686263 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9686 13:53:49.689624 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9687 13:53:49.693095 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9688 13:53:49.699670 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9689 13:53:49.702732 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9690 13:53:49.706319 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9691 13:53:49.713045 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9692 13:53:49.716184 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9693 13:53:49.722590 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9694 13:53:49.726463 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9695 13:53:49.729631 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9696 13:53:49.735902 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9697 13:53:49.739306 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9698 13:53:49.742759 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9699 13:53:49.749277 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9700 13:53:49.752813 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9701 13:53:49.759122 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9702 13:53:49.762521 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9703 13:53:49.766082 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9704 13:53:49.772804 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9705 13:53:49.775802 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9706 13:53:49.779559 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9707 13:53:49.785811 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9708 13:53:49.789300 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9709 13:53:49.792852 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9710 13:53:49.799180 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9711 13:53:49.802742 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9712 13:53:49.809300 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9713 13:53:49.812160 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9714 13:53:49.815627 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9715 13:53:49.818976 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9716 13:53:49.825632 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9717 13:53:49.828879 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9718 13:53:49.832004 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9719 13:53:49.835477 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9720 13:53:49.841969 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9721 13:53:49.845682 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9722 13:53:49.848833 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9723 13:53:49.852213 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9724 13:53:49.858556 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9725 13:53:49.862001 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9726 13:53:49.865245 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9727 13:53:49.868466 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9728 13:53:49.875651 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9729 13:53:49.879173 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9730 13:53:49.885655 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9731 13:53:49.889234 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9732 13:53:49.895355 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9733 13:53:49.898862 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9734 13:53:49.902399 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9735 13:53:49.908715 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9736 13:53:49.912357 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9737 13:53:49.918854 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9738 13:53:49.921959 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9739 13:53:49.925418 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9740 13:53:49.932241 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9741 13:53:49.935670 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9742 13:53:49.942014 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9743 13:53:49.945389 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9744 13:53:49.948868 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9745 13:53:49.955187 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9746 13:53:49.958783 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9747 13:53:49.965423 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9748 13:53:49.968687 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9749 13:53:49.972040 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9750 13:53:49.978238 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9751 13:53:49.982018 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9752 13:53:49.988825 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9753 13:53:49.992169 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9754 13:53:49.995211 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9755 13:53:50.002109 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9756 13:53:50.005309 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9757 13:53:50.012322 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9758 13:53:50.015113 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9759 13:53:50.018751 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9760 13:53:50.025265 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9761 13:53:50.028813 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9762 13:53:50.034957 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9763 13:53:50.038710 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9764 13:53:50.045132 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9765 13:53:50.048640 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9766 13:53:50.052146 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9767 13:53:50.058312 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9768 13:53:50.061799 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9769 13:53:50.065442 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9770 13:53:50.072244 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9771 13:53:50.075025 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9772 13:53:50.082093 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9773 13:53:50.085534 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9774 13:53:50.091821 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9775 13:53:50.095270 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9776 13:53:50.098664 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9777 13:53:50.105133 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9778 13:53:50.108655 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9779 13:53:50.114971 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9780 13:53:50.118628 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9781 13:53:50.121999 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9782 13:53:50.128407 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9783 13:53:50.131448 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9784 13:53:50.138552 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9785 13:53:50.141366 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9786 13:53:50.145093 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9787 13:53:50.151497 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9788 13:53:50.154986 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9789 13:53:50.161809 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9790 13:53:50.164786 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9791 13:53:50.168280 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9792 13:53:50.175030 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9793 13:53:50.178274 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9794 13:53:50.184643 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9795 13:53:50.188325 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9796 13:53:50.191924 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9797 13:53:50.198176 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9798 13:53:50.201771 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9799 13:53:50.208367 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9800 13:53:50.211186 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9801 13:53:50.214770 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9802 13:53:50.221177 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9803 13:53:50.225036 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9804 13:53:50.231577 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9805 13:53:50.234730 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9806 13:53:50.241497 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9807 13:53:50.244551 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9808 13:53:50.251554 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9809 13:53:50.254410 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9810 13:53:50.257857 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9811 13:53:50.264388 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9812 13:53:50.267714 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9813 13:53:50.274550 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9814 13:53:50.278004 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9815 13:53:50.281393 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9816 13:53:50.288093 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9817 13:53:50.291034 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9818 13:53:50.298106 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9819 13:53:50.301603 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9820 13:53:50.308047 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9821 13:53:50.311633 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9822 13:53:50.317988 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9823 13:53:50.321528 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9824 13:53:50.324427 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9825 13:53:50.331534 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9826 13:53:50.334217 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9827 13:53:50.341256 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9828 13:53:50.344731 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9829 13:53:50.351466 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9830 13:53:50.354273 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9831 13:53:50.357904 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9832 13:53:50.364577 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9833 13:53:50.367928 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9834 13:53:50.374402 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9835 13:53:50.377936 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9836 13:53:50.384688 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9837 13:53:50.387842 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9838 13:53:50.394406 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9839 13:53:50.397758 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9840 13:53:50.401149 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9841 13:53:50.407903 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9842 13:53:50.410761 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9843 13:53:50.418103 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9844 13:53:50.421062 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9845 13:53:50.424472 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9846 13:53:50.430910 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9847 13:53:50.434561 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9848 13:53:50.440893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9849 13:53:50.444547 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9850 13:53:50.448108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9851 13:53:50.454416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9852 13:53:50.457716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9853 13:53:50.464056 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9854 13:53:50.467550 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9855 13:53:50.473997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9856 13:53:50.477592 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9857 13:53:50.484000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9858 13:53:50.487394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9859 13:53:50.494324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9860 13:53:50.497705 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9861 13:53:50.504279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9862 13:53:50.507413 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9863 13:53:50.514186 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9864 13:53:50.517542 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9865 13:53:50.524389 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9866 13:53:50.527121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9867 13:53:50.533681 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9868 13:53:50.537687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9869 13:53:50.543961 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9870 13:53:50.547573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9871 13:53:50.554095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9872 13:53:50.557145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9873 13:53:50.563899 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9874 13:53:50.567231 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9875 13:53:50.573584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9876 13:53:50.577341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9877 13:53:50.583693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9878 13:53:50.587168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9879 13:53:50.594125 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9880 13:53:50.597035 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9881 13:53:50.600662 INFO: [APUAPC] vio 0
9882 13:53:50.603541 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9883 13:53:50.607263 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9884 13:53:50.610153 INFO: [APUAPC] D0_APC_0: 0x400510
9885 13:53:50.613536 INFO: [APUAPC] D0_APC_1: 0x0
9886 13:53:50.617145 INFO: [APUAPC] D0_APC_2: 0x1540
9887 13:53:50.620713 INFO: [APUAPC] D0_APC_3: 0x0
9888 13:53:50.623497 INFO: [APUAPC] D1_APC_0: 0xffffffff
9889 13:53:50.626971 INFO: [APUAPC] D1_APC_1: 0xffffffff
9890 13:53:50.630593 INFO: [APUAPC] D1_APC_2: 0x3fffff
9891 13:53:50.633961 INFO: [APUAPC] D1_APC_3: 0x0
9892 13:53:50.637402 INFO: [APUAPC] D2_APC_0: 0xffffffff
9893 13:53:50.640834 INFO: [APUAPC] D2_APC_1: 0xffffffff
9894 13:53:50.643988 INFO: [APUAPC] D2_APC_2: 0x3fffff
9895 13:53:50.647150 INFO: [APUAPC] D2_APC_3: 0x0
9896 13:53:50.650222 INFO: [APUAPC] D3_APC_0: 0xffffffff
9897 13:53:50.653476 INFO: [APUAPC] D3_APC_1: 0xffffffff
9898 13:53:50.657074 INFO: [APUAPC] D3_APC_2: 0x3fffff
9899 13:53:50.660526 INFO: [APUAPC] D3_APC_3: 0x0
9900 13:53:50.663839 INFO: [APUAPC] D4_APC_0: 0xffffffff
9901 13:53:50.667062 INFO: [APUAPC] D4_APC_1: 0xffffffff
9902 13:53:50.670316 INFO: [APUAPC] D4_APC_2: 0x3fffff
9903 13:53:50.673779 INFO: [APUAPC] D4_APC_3: 0x0
9904 13:53:50.676925 INFO: [APUAPC] D5_APC_0: 0xffffffff
9905 13:53:50.680709 INFO: [APUAPC] D5_APC_1: 0xffffffff
9906 13:53:50.683847 INFO: [APUAPC] D5_APC_2: 0x3fffff
9907 13:53:50.687059 INFO: [APUAPC] D5_APC_3: 0x0
9908 13:53:50.690474 INFO: [APUAPC] D6_APC_0: 0xffffffff
9909 13:53:50.693430 INFO: [APUAPC] D6_APC_1: 0xffffffff
9910 13:53:50.696887 INFO: [APUAPC] D6_APC_2: 0x3fffff
9911 13:53:50.700409 INFO: [APUAPC] D6_APC_3: 0x0
9912 13:53:50.703369 INFO: [APUAPC] D7_APC_0: 0xffffffff
9913 13:53:50.707104 INFO: [APUAPC] D7_APC_1: 0xffffffff
9914 13:53:50.709962 INFO: [APUAPC] D7_APC_2: 0x3fffff
9915 13:53:50.710039 INFO: [APUAPC] D7_APC_3: 0x0
9916 13:53:50.713552 INFO: [APUAPC] D8_APC_0: 0xffffffff
9917 13:53:50.719947 INFO: [APUAPC] D8_APC_1: 0xffffffff
9918 13:53:50.723450 INFO: [APUAPC] D8_APC_2: 0x3fffff
9919 13:53:50.723533 INFO: [APUAPC] D8_APC_3: 0x0
9920 13:53:50.726981 INFO: [APUAPC] D9_APC_0: 0xffffffff
9921 13:53:50.730436 INFO: [APUAPC] D9_APC_1: 0xffffffff
9922 13:53:50.733878 INFO: [APUAPC] D9_APC_2: 0x3fffff
9923 13:53:50.736661 INFO: [APUAPC] D9_APC_3: 0x0
9924 13:53:50.740156 INFO: [APUAPC] D10_APC_0: 0xffffffff
9925 13:53:50.743706 INFO: [APUAPC] D10_APC_1: 0xffffffff
9926 13:53:50.747186 INFO: [APUAPC] D10_APC_2: 0x3fffff
9927 13:53:50.749961 INFO: [APUAPC] D10_APC_3: 0x0
9928 13:53:50.753549 INFO: [APUAPC] D11_APC_0: 0xffffffff
9929 13:53:50.756442 INFO: [APUAPC] D11_APC_1: 0xffffffff
9930 13:53:50.760097 INFO: [APUAPC] D11_APC_2: 0x3fffff
9931 13:53:50.763494 INFO: [APUAPC] D11_APC_3: 0x0
9932 13:53:50.766789 INFO: [APUAPC] D12_APC_0: 0xffffffff
9933 13:53:50.770321 INFO: [APUAPC] D12_APC_1: 0xffffffff
9934 13:53:50.773517 INFO: [APUAPC] D12_APC_2: 0x3fffff
9935 13:53:50.776687 INFO: [APUAPC] D12_APC_3: 0x0
9936 13:53:50.780015 INFO: [APUAPC] D13_APC_0: 0xffffffff
9937 13:53:50.783270 INFO: [APUAPC] D13_APC_1: 0xffffffff
9938 13:53:50.786459 INFO: [APUAPC] D13_APC_2: 0x3fffff
9939 13:53:50.790280 INFO: [APUAPC] D13_APC_3: 0x0
9940 13:53:50.793375 INFO: [APUAPC] D14_APC_0: 0xffffffff
9941 13:53:50.796896 INFO: [APUAPC] D14_APC_1: 0xffffffff
9942 13:53:50.803190 INFO: [APUAPC] D14_APC_2: 0x3fffff
9943 13:53:50.803276 INFO: [APUAPC] D14_APC_3: 0x0
9944 13:53:50.806604 INFO: [APUAPC] D15_APC_0: 0xffffffff
9945 13:53:50.813517 INFO: [APUAPC] D15_APC_1: 0xffffffff
9946 13:53:50.813601 INFO: [APUAPC] D15_APC_2: 0x3fffff
9947 13:53:50.816414 INFO: [APUAPC] D15_APC_3: 0x0
9948 13:53:50.819896 INFO: [APUAPC] APC_CON: 0x4
9949 13:53:50.823540 INFO: [NOCDAPC] D0_APC_0: 0x0
9950 13:53:50.826347 INFO: [NOCDAPC] D0_APC_1: 0x0
9951 13:53:50.830007 INFO: [NOCDAPC] D1_APC_0: 0x0
9952 13:53:50.833543 INFO: [NOCDAPC] D1_APC_1: 0xfff
9953 13:53:50.836469 INFO: [NOCDAPC] D2_APC_0: 0x0
9954 13:53:50.839775 INFO: [NOCDAPC] D2_APC_1: 0xfff
9955 13:53:50.843400 INFO: [NOCDAPC] D3_APC_0: 0x0
9956 13:53:50.843474 INFO: [NOCDAPC] D3_APC_1: 0xfff
9957 13:53:50.846322 INFO: [NOCDAPC] D4_APC_0: 0x0
9958 13:53:50.849873 INFO: [NOCDAPC] D4_APC_1: 0xfff
9959 13:53:50.853321 INFO: [NOCDAPC] D5_APC_0: 0x0
9960 13:53:50.856178 INFO: [NOCDAPC] D5_APC_1: 0xfff
9961 13:53:50.859846 INFO: [NOCDAPC] D6_APC_0: 0x0
9962 13:53:50.863334 INFO: [NOCDAPC] D6_APC_1: 0xfff
9963 13:53:50.866136 INFO: [NOCDAPC] D7_APC_0: 0x0
9964 13:53:50.869535 INFO: [NOCDAPC] D7_APC_1: 0xfff
9965 13:53:50.873120 INFO: [NOCDAPC] D8_APC_0: 0x0
9966 13:53:50.876658 INFO: [NOCDAPC] D8_APC_1: 0xfff
9967 13:53:50.876741 INFO: [NOCDAPC] D9_APC_0: 0x0
9968 13:53:50.879494 INFO: [NOCDAPC] D9_APC_1: 0xfff
9969 13:53:50.882830 INFO: [NOCDAPC] D10_APC_0: 0x0
9970 13:53:50.886199 INFO: [NOCDAPC] D10_APC_1: 0xfff
9971 13:53:50.889569 INFO: [NOCDAPC] D11_APC_0: 0x0
9972 13:53:50.893137 INFO: [NOCDAPC] D11_APC_1: 0xfff
9973 13:53:50.896523 INFO: [NOCDAPC] D12_APC_0: 0x0
9974 13:53:50.899446 INFO: [NOCDAPC] D12_APC_1: 0xfff
9975 13:53:50.902893 INFO: [NOCDAPC] D13_APC_0: 0x0
9976 13:53:50.906392 INFO: [NOCDAPC] D13_APC_1: 0xfff
9977 13:53:50.909746 INFO: [NOCDAPC] D14_APC_0: 0x0
9978 13:53:50.912977 INFO: [NOCDAPC] D14_APC_1: 0xfff
9979 13:53:50.916190 INFO: [NOCDAPC] D15_APC_0: 0x0
9980 13:53:50.919361 INFO: [NOCDAPC] D15_APC_1: 0xfff
9981 13:53:50.919438 INFO: [NOCDAPC] APC_CON: 0x4
9982 13:53:50.923002 INFO: [APUAPC] set_apusys_apc done
9983 13:53:50.925991 INFO: [DEVAPC] devapc_init done
9984 13:53:50.932598 INFO: GICv3 without legacy support detected.
9985 13:53:50.936219 INFO: ARM GICv3 driver initialized in EL3
9986 13:53:50.939771 INFO: Maximum SPI INTID supported: 639
9987 13:53:50.942459 INFO: BL31: Initializing runtime services
9988 13:53:50.949650 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9989 13:53:50.952495 INFO: SPM: enable CPC mode
9990 13:53:50.956029 INFO: mcdi ready for mcusys-off-idle and system suspend
9991 13:53:50.963001 INFO: BL31: Preparing for EL3 exit to normal world
9992 13:53:50.965880 INFO: Entry point address = 0x80000000
9993 13:53:50.965965 INFO: SPSR = 0x8
9994 13:53:50.973117
9995 13:53:50.973220
9996 13:53:50.973287
9997 13:53:50.973966 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
9998 13:53:50.974073 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
9999 13:53:50.974154 Setting prompt string to ['asurada:']
10000 13:53:50.974241 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10001 13:53:50.976356 Starting depthcharge on Spherion...
10002 13:53:50.976443
10003 13:53:50.976509 Wipe memory regions:
10004 13:53:50.976569
10005 13:53:50.980040 [0x00000040000000, 0x00000054600000)
10006 13:53:51.101925
10007 13:53:51.102058 [0x00000054660000, 0x00000080000000)
10008 13:53:51.362700
10009 13:53:51.362833 [0x000000821a7280, 0x000000ffe64000)
10010 13:53:52.107441
10011 13:53:52.107582 [0x00000100000000, 0x00000240000000)
10012 13:53:53.997480
10013 13:53:54.001093 Initializing XHCI USB controller at 0x11200000.
10014 13:53:55.039158
10015 13:53:55.042521 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10016 13:53:55.042624
10017 13:53:55.042689
10018 13:53:55.042967 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10020 13:53:55.143319 asurada: tftpboot 192.168.201.1 13842491/tftp-deploy-jr0n5hf8/kernel/image.itb 13842491/tftp-deploy-jr0n5hf8/kernel/cmdline
10021 13:53:55.143479 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10022 13:53:55.143596 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10023 13:53:55.148145 tftpboot 192.168.201.1 13842491/tftp-deploy-jr0n5hf8/kernel/image.itp-deploy-jr0n5hf8/kernel/cmdline
10024 13:53:55.148249
10025 13:53:55.148378 Waiting for link
10026 13:53:55.305905
10027 13:53:55.306049 R8152: Initializing
10028 13:53:55.306141
10029 13:53:55.309289 Version 9 (ocp_data = 6010)
10030 13:53:55.309365
10031 13:53:55.312668 R8152: Done initializing
10032 13:53:55.312741
10033 13:53:55.312821 Adding net device
10034 13:53:57.260830
10035 13:53:57.260964 done.
10036 13:53:57.261028
10037 13:53:57.261086 MAC: 00:e0:4c:78:7a:aa
10038 13:53:57.261142
10039 13:53:57.264233 Sending DHCP discover... done.
10040 13:53:57.264366
10041 13:53:57.267863 Waiting for reply... done.
10042 13:53:57.267945
10043 13:53:57.270991 Sending DHCP request... done.
10044 13:53:57.271073
10045 13:53:57.271136 Waiting for reply... done.
10046 13:53:57.274183
10047 13:53:57.274276 My ip is 192.168.201.12
10048 13:53:57.274339
10049 13:53:57.277471 The DHCP server ip is 192.168.201.1
10050 13:53:57.277552
10051 13:53:57.280623 TFTP server IP predefined by user: 192.168.201.1
10052 13:53:57.280705
10053 13:53:57.287500 Bootfile predefined by user: 13842491/tftp-deploy-jr0n5hf8/kernel/image.itb
10054 13:53:57.287599
10055 13:53:57.291041 Sending tftp read request... done.
10056 13:53:57.291123
10057 13:53:57.293963 Waiting for the transfer...
10058 13:53:57.294045
10059 13:53:57.595390 00000000 ################################################################
10060 13:53:57.595548
10061 13:53:57.863837 00080000 ################################################################
10062 13:53:57.863980
10063 13:53:58.111844 00100000 ################################################################
10064 13:53:58.111992
10065 13:53:58.363391 00180000 ################################################################
10066 13:53:58.363559
10067 13:53:58.627099 00200000 ################################################################
10068 13:53:58.627240
10069 13:53:58.887105 00280000 ################################################################
10070 13:53:58.887235
10071 13:53:59.137902 00300000 ################################################################
10072 13:53:59.138034
10073 13:53:59.406548 00380000 ################################################################
10074 13:53:59.406718
10075 13:53:59.676227 00400000 ################################################################
10076 13:53:59.676447
10077 13:53:59.935432 00480000 ################################################################
10078 13:53:59.935605
10079 13:54:00.185369 00500000 ################################################################
10080 13:54:00.185518
10081 13:54:00.432778 00580000 ################################################################
10082 13:54:00.432937
10083 13:54:00.687286 00600000 ################################################################
10084 13:54:00.687427
10085 13:54:00.939448 00680000 ################################################################
10086 13:54:00.939629
10087 13:54:01.191411 00700000 ################################################################
10088 13:54:01.191586
10089 13:54:01.440827 00780000 ################################################################
10090 13:54:01.441003
10091 13:54:01.692426 00800000 ################################################################
10092 13:54:01.692605
10093 13:54:01.953310 00880000 ################################################################
10094 13:54:01.953482
10095 13:54:02.216593 00900000 ################################################################
10096 13:54:02.216832
10097 13:54:02.477536 00980000 ################################################################
10098 13:54:02.477720
10099 13:54:02.736918 00a00000 ################################################################
10100 13:54:02.737078
10101 13:54:02.996568 00a80000 ################################################################
10102 13:54:02.996741
10103 13:54:03.253238 00b00000 ################################################################
10104 13:54:03.253386
10105 13:54:03.502785 00b80000 ################################################################
10106 13:54:03.502946
10107 13:54:03.760032 00c00000 ################################################################
10108 13:54:03.760187
10109 13:54:04.015626 00c80000 ################################################################
10110 13:54:04.015783
10111 13:54:04.280049 00d00000 ################################################################
10112 13:54:04.280222
10113 13:54:04.535766 00d80000 ################################################################
10114 13:54:04.535949
10115 13:54:04.798460 00e00000 ################################################################
10116 13:54:04.798636
10117 13:54:05.054688 00e80000 ################################################################
10118 13:54:05.054836
10119 13:54:05.309477 00f00000 ################################################################
10120 13:54:05.309626
10121 13:54:05.564784 00f80000 ################################################################
10122 13:54:05.564957
10123 13:54:05.827104 01000000 ################################################################
10124 13:54:05.827251
10125 13:54:06.085024 01080000 ################################################################
10126 13:54:06.085185
10127 13:54:06.340238 01100000 ################################################################
10128 13:54:06.340421
10129 13:54:06.605196 01180000 ################################################################
10130 13:54:06.605331
10131 13:54:06.862937 01200000 ################################################################
10132 13:54:06.863082
10133 13:54:07.121835 01280000 ################################################################
10134 13:54:07.121967
10135 13:54:07.384372 01300000 ################################################################
10136 13:54:07.384528
10137 13:54:07.641007 01380000 ################################################################
10138 13:54:07.641139
10139 13:54:07.895865 01400000 ################################################################
10140 13:54:07.896023
10141 13:54:08.163605 01480000 ################################################################
10142 13:54:08.163741
10143 13:54:08.427819 01500000 ################################################################
10144 13:54:08.427966
10145 13:54:08.690228 01580000 ################################################################
10146 13:54:08.690379
10147 13:54:08.942357 01600000 ################################################################
10148 13:54:08.942516
10149 13:54:09.191253 01680000 ################################################################
10150 13:54:09.191411
10151 13:54:09.444620 01700000 ################################################################
10152 13:54:09.444784
10153 13:54:09.702848 01780000 ################################################################
10154 13:54:09.703024
10155 13:54:09.962439 01800000 ################################################################
10156 13:54:09.962595
10157 13:54:10.221871 01880000 ################################################################
10158 13:54:10.222040
10159 13:54:10.482895 01900000 ################################################################
10160 13:54:10.483028
10161 13:54:10.733562 01980000 ################################################################
10162 13:54:10.733696
10163 13:54:10.994295 01a00000 ################################################################
10164 13:54:10.994426
10165 13:54:11.259412 01a80000 ################################################################
10166 13:54:11.259547
10167 13:54:11.515948 01b00000 ################################################################
10168 13:54:11.516091
10169 13:54:11.776099 01b80000 ################################################################
10170 13:54:11.776246
10171 13:54:12.034512 01c00000 ################################################################
10172 13:54:12.034644
10173 13:54:12.284162 01c80000 ################################################################
10174 13:54:12.284293
10175 13:54:12.536302 01d00000 ################################################################
10176 13:54:12.536473
10177 13:54:12.801628 01d80000 ################################################################
10178 13:54:12.801776
10179 13:54:13.061468 01e00000 ################################################################
10180 13:54:13.061615
10181 13:54:13.323237 01e80000 ################################################################
10182 13:54:13.323383
10183 13:54:13.596307 01f00000 ################################################################
10184 13:54:13.596460
10185 13:54:13.875369 01f80000 ################################################################
10186 13:54:13.875508
10187 13:54:14.126145 02000000 ################################################################
10188 13:54:14.126284
10189 13:54:14.373835 02080000 ################################################################
10190 13:54:14.373970
10191 13:54:14.632223 02100000 ################################################################
10192 13:54:14.632403
10193 13:54:14.905470 02180000 ################################################################
10194 13:54:14.905627
10195 13:54:15.156509 02200000 ################################################################
10196 13:54:15.156665
10197 13:54:15.271280 02280000 ############################## done.
10198 13:54:15.271408
10199 13:54:15.274201 The bootfile was 36416846 bytes long.
10200 13:54:15.274277
10201 13:54:15.277511 Sending tftp read request... done.
10202 13:54:15.277591
10203 13:54:15.280554 Waiting for the transfer...
10204 13:54:15.280634
10205 13:54:15.280696 00000000 # done.
10206 13:54:15.280757
10207 13:54:15.290906 Command line loaded dynamically from TFTP file: 13842491/tftp-deploy-jr0n5hf8/kernel/cmdline
10208 13:54:15.291025
10209 13:54:15.304158 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10210 13:54:15.304308
10211 13:54:15.304464 Loading FIT.
10212 13:54:15.304552
10213 13:54:15.307479 Image ramdisk-1 has 22871760 bytes.
10214 13:54:15.307558
10215 13:54:15.310662 Image fdt-1 has 58971 bytes.
10216 13:54:15.310766
10217 13:54:15.313991 Image kernel-1 has 13484083 bytes.
10218 13:54:15.314084
10219 13:54:15.323931 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10220 13:54:15.324115
10221 13:54:15.340478 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10222 13:54:15.340602
10223 13:54:15.343323 Choosing best match conf-1 for compat google,spherion-rev2.
10224 13:54:15.346973
10225 13:54:15.350859 Connected to device vid:did:rid of 1ae0:0028:00
10226 13:54:15.362734
10227 13:54:15.365712 tpm_get_response: command 0x17b, return code 0x0
10228 13:54:15.365849
10229 13:54:15.369416 ec_init: CrosEC protocol v3 supported (256, 248)
10230 13:54:15.372996
10231 13:54:15.376580 tpm_cleanup: add release locality here.
10232 13:54:15.376684
10233 13:54:15.376774 Shutting down all USB controllers.
10234 13:54:15.376861
10235 13:54:15.380180 Removing current net device
10236 13:54:15.380296
10237 13:54:15.386501 Exiting depthcharge with code 4 at timestamp: 53728365
10238 13:54:15.386596
10239 13:54:15.390018 LZMA decompressing kernel-1 to 0x821a6718
10240 13:54:15.390124
10241 13:54:15.393555 LZMA decompressing kernel-1 to 0x40000000
10242 13:54:17.067132
10243 13:54:17.067309 jumping to kernel
10244 13:54:17.068217 end: 2.2.4 bootloader-commands (duration 00:00:26) [common]
10245 13:54:17.068363 start: 2.2.5 auto-login-action (timeout 00:03:59) [common]
10246 13:54:17.068448 Setting prompt string to ['Linux version [0-9]']
10247 13:54:17.068559 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10248 13:54:17.068667 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10249 13:54:17.148593
10250 13:54:17.151511 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10251 13:54:17.155278 start: 2.2.5.1 login-action (timeout 00:03:59) [common]
10252 13:54:17.155422 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10253 13:54:17.155517 Setting prompt string to []
10254 13:54:17.155611 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10255 13:54:17.155716 Using line separator: #'\n'#
10256 13:54:17.155822 No login prompt set.
10257 13:54:17.155925 Parsing kernel messages
10258 13:54:17.156023 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10259 13:54:17.156199 [login-action] Waiting for messages, (timeout 00:03:59)
10260 13:54:17.156297 Waiting using forced prompt support (timeout 00:01:59)
10261 13:54:17.174697 [ 0.000000] Linux version 6.6.30 (KernelCI@build-j198248-arm64-gcc-10-defconfig-arm64-chromebook-k96dq) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu May 16 13:35:18 UTC 2024
10262 13:54:17.178277 [ 0.000000] KASLR enabled
10263 13:54:17.181906 [ 0.000000] random: crng init done
10264 13:54:17.184814 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10265 13:54:17.188239 [ 0.000000] efi: UEFI not found.
10266 13:54:17.198244 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10267 13:54:17.204842 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10268 13:54:17.214865 [ 0.000000] OF: reserved mem: 0x0000000050000000..0x00000000528fffff (41984 KiB) nomap non-reusable scp@50000000
10269 13:54:17.224286 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10270 13:54:17.234682 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10271 13:54:17.244285 [ 0.000000] OF: reserved mem: 0x00000000c0000000..0x00000000c3ffffff (65536 KiB) map non-reusable wifi@c0000000
10272 13:54:17.251178 [ 0.000000] OF: reserved mem: 0x00000000ffe66000..0x00000000fff65fff (1024 KiB) map non-reusable ramoops
10273 13:54:17.261047 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10274 13:54:17.264795 [ 0.000000] printk: bootconsole [mtk8250] enabled
10275 13:54:17.272740 [ 0.000000] NUMA: No NUMA configuration found
10276 13:54:17.279412 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10277 13:54:17.286041 [ 0.000000] NUMA: NODE_DATA [mem 0x23efc09c0-0x23efc2fff]
10278 13:54:17.286125 [ 0.000000] Zone ranges:
10279 13:54:17.292508 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10280 13:54:17.295742 [ 0.000000] DMA32 empty
10281 13:54:17.302342 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10282 13:54:17.305783 [ 0.000000] Movable zone start for each node
10283 13:54:17.309031 [ 0.000000] Early memory node ranges
10284 13:54:17.315683 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10285 13:54:17.322140 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10286 13:54:17.328787 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10287 13:54:17.335826 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10288 13:54:17.342092 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10289 13:54:17.348564 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10290 13:54:17.405770 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10291 13:54:17.412285 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10292 13:54:17.419044 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000 on node -1
10293 13:54:17.425316 [ 0.000000] psci: probing for conduit method from DT.
10294 13:54:17.428612 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10295 13:54:17.431969 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10296 13:54:17.438703 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10297 13:54:17.442264 [ 0.000000] psci: SMC Calling Convention v1.2
10298 13:54:17.448692 [ 0.000000] percpu: Embedded 22 pages/cpu s51112 r8192 d30808 u90112
10299 13:54:17.455451 [ 0.000000] Detected VIPT I-cache on CPU0
10300 13:54:17.458969 [ 0.000000] CPU features: detected: GIC system register CPU interface
10301 13:54:17.465020 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10302 13:54:17.471780 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10303 13:54:17.478222 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10304 13:54:17.488215 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10305 13:54:17.494821 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10306 13:54:17.497696 [ 0.000000] alternatives: applying boot alternatives
10307 13:54:17.515221 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10308 13:54:17.525346 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10309 13:54:17.536066 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10310 13:54:17.546158 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10311 13:54:17.549746 <6>[ 0.000000] Fallback order for Node 0: 0
10312 13:54:17.556261 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10313 13:54:17.559562 <6>[ 0.000000] Policy zone: Normal
10314 13:54:17.565901 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10315 13:54:17.572930 <6>[ 0.000000] software IO TLB: area num 8.
10316 13:54:17.627840 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10317 13:54:17.772931 <6>[ 0.000000] Memory: 7938476K/8385536K available (18432K kernel code, 4598K rwdata, 23556K rodata, 9984K init, 612K bss, 414292K reserved, 32768K cma-reserved)
10318 13:54:17.779308 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10319 13:54:17.785825 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10320 13:54:17.789557 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10321 13:54:17.796219 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10322 13:54:17.802445 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10323 13:54:17.805938 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10324 13:54:17.815904 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10325 13:54:17.822793 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10326 13:54:17.829185 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10327 13:54:17.835752 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
10328 13:54:17.842126 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10329 13:54:17.845582 <6>[ 0.000000] GICv3: 608 SPIs implemented
10330 13:54:17.852525 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10331 13:54:17.855340 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10332 13:54:17.859072 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10333 13:54:17.868563 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10334 13:54:17.878648 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10335 13:54:17.892110 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10336 13:54:17.898397 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10337 13:54:17.908601 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10338 13:54:17.921574 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10339 13:54:17.928032 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10340 13:54:17.934552 <6>[ 0.009423] Console: colour dummy device 80x25
10341 13:54:17.944887 <6>[ 0.014152] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10342 13:54:17.950985 <6>[ 0.024594] pid_max: default: 32768 minimum: 301
10343 13:54:17.954419 <6>[ 0.029487] LSM: initializing lsm=capability,integrity
10344 13:54:17.964115 <6>[ 0.034972] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10345 13:54:17.970899 <6>[ 0.042785] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10346 13:54:17.981005 <6>[ 0.052290] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
10347 13:54:17.987630 <6>[ 0.059589] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
10348 13:54:17.994083 <6>[ 0.067534] rcu: Hierarchical SRCU implementation.
10349 13:54:17.997627 <6>[ 0.072578] rcu: Max phase no-delay instances is 1000.
10350 13:54:18.005587 <6>[ 0.079977] EFI services will not be available.
10351 13:54:18.008458 <6>[ 0.084966] smp: Bringing up secondary CPUs ...
10352 13:54:18.017619 <6>[ 0.090042] Detected VIPT I-cache on CPU1
10353 13:54:18.024242 <6>[ 0.090097] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10354 13:54:18.031308 <6>[ 0.090128] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10355 13:54:18.034245 <6>[ 0.090469] Detected VIPT I-cache on CPU2
10356 13:54:18.041171 <6>[ 0.090504] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10357 13:54:18.050975 <6>[ 0.090521] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10358 13:54:18.054361 <6>[ 0.090809] Detected VIPT I-cache on CPU3
10359 13:54:18.060633 <6>[ 0.090842] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10360 13:54:18.067622 <6>[ 0.090857] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10361 13:54:18.070546 <6>[ 0.091185] CPU features: detected: Spectre-v4
10362 13:54:18.077636 <6>[ 0.091191] CPU features: detected: Spectre-BHB
10363 13:54:18.081052 <6>[ 0.091196] Detected PIPT I-cache on CPU4
10364 13:54:18.087474 <6>[ 0.091234] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10365 13:54:18.094053 <6>[ 0.091251] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10366 13:54:18.100612 <6>[ 0.091557] Detected PIPT I-cache on CPU5
10367 13:54:18.107144 <6>[ 0.091599] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10368 13:54:18.113779 <6>[ 0.091617] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10369 13:54:18.117268 <6>[ 0.091909] Detected PIPT I-cache on CPU6
10370 13:54:18.123772 <6>[ 0.091954] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10371 13:54:18.130514 <6>[ 0.091971] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10372 13:54:18.137177 <6>[ 0.092297] Detected PIPT I-cache on CPU7
10373 13:54:18.143360 <6>[ 0.092344] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10374 13:54:18.150477 <6>[ 0.092361] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10375 13:54:18.153206 <6>[ 0.092423] smp: Brought up 1 node, 8 CPUs
10376 13:54:18.160296 <6>[ 0.233774] SMP: Total of 8 processors activated.
10377 13:54:18.163659 <6>[ 0.238695] CPU features: detected: 32-bit EL0 Support
10378 13:54:18.173045 <6>[ 0.244064] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10379 13:54:18.180003 <6>[ 0.252864] CPU features: detected: Common not Private translations
10380 13:54:18.183580 <6>[ 0.259341] CPU features: detected: CRC32 instructions
10381 13:54:18.190107 <6>[ 0.264692] CPU features: detected: RCpc load-acquire (LDAPR)
10382 13:54:18.196342 <6>[ 0.270652] CPU features: detected: LSE atomic instructions
10383 13:54:18.203315 <6>[ 0.276435] CPU features: detected: Privileged Access Never
10384 13:54:18.206599 <6>[ 0.282250] CPU features: detected: RAS Extension Support
10385 13:54:18.216114 <6>[ 0.287894] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10386 13:54:18.220026 <6>[ 0.295112] CPU: All CPU(s) started at EL2
10387 13:54:18.226249 <6>[ 0.299429] alternatives: applying system-wide alternatives
10388 13:54:18.235462 <6>[ 0.310254] devtmpfs: initialized
10389 13:54:18.252800 <6>[ 0.320567] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10390 13:54:18.258908 <6>[ 0.330530] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10391 13:54:18.265184 <6>[ 0.338543] pinctrl core: initialized pinctrl subsystem
10392 13:54:18.268706 <6>[ 0.345389] DMI not present or invalid.
10393 13:54:18.275845 <6>[ 0.349860] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10394 13:54:18.285435 <6>[ 0.356824] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10395 13:54:18.291903 <6>[ 0.364410] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10396 13:54:18.301749 <6>[ 0.372638] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10397 13:54:18.305156 <6>[ 0.380926] audit: initializing netlink subsys (disabled)
10398 13:54:18.315244 <5>[ 0.386656] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10399 13:54:18.322014 <6>[ 0.387566] thermal_sys: Registered thermal governor 'step_wise'
10400 13:54:18.328315 <6>[ 0.394621] thermal_sys: Registered thermal governor 'power_allocator'
10401 13:54:18.331729 <6>[ 0.400880] cpuidle: using governor menu
10402 13:54:18.338371 <6>[ 0.411865] NET: Registered PF_QIPCRTR protocol family
10403 13:54:18.344887 <6>[ 0.417373] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10404 13:54:18.351840 <6>[ 0.424488] ASID allocator initialised with 32768 entries
10405 13:54:18.354990 <6>[ 0.431383] Serial: AMBA PL011 UART driver
10406 13:54:18.382382 <6>[ 0.454335] platform 14010000.dsi: Fixed dependency cycle(s) with /soc/i2c@11cb0000/anx7625@58
10407 13:54:18.400052 <6>[ 0.471886] Modules: 2G module region forced by RANDOMIZE_MODULE_REGION_FULL
10408 13:54:18.403761 <6>[ 0.479178] Modules: 0 pages in range for non-PLT usage
10409 13:54:18.410582 <6>[ 0.479181] Modules: 509952 pages in range for PLT usage
10410 13:54:18.416663 <6>[ 0.485238] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10411 13:54:18.423306 <6>[ 0.497787] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10412 13:54:18.429962 <6>[ 0.504276] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10413 13:54:18.437189 <6>[ 0.511282] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10414 13:54:18.443566 <6>[ 0.517765] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10415 13:54:18.450401 <6>[ 0.524767] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10416 13:54:18.456874 <6>[ 0.531253] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10417 13:54:18.463171 <6>[ 0.538260] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10418 13:54:18.471359 <6>[ 0.545947] ACPI: Interpreter disabled.
10419 13:54:18.477747 <6>[ 0.552693] iommu: Default domain type: Translated
10420 13:54:18.484537 <6>[ 0.557721] iommu: DMA domain TLB invalidation policy: strict mode
10421 13:54:18.488056 <5>[ 0.564310] SCSI subsystem initialized
10422 13:54:18.494492 <6>[ 0.568474] usbcore: registered new interface driver usbfs
10423 13:54:18.500702 <6>[ 0.574202] usbcore: registered new interface driver hub
10424 13:54:18.504443 <6>[ 0.579751] usbcore: registered new device driver usb
10425 13:54:18.510932 <6>[ 0.585976] pps_core: LinuxPPS API ver. 1 registered
10426 13:54:18.521206 <6>[ 0.591170] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10427 13:54:18.523958 <6>[ 0.600518] PTP clock support registered
10428 13:54:18.527606 <6>[ 0.604780] EDAC MC: Ver: 3.0.0
10429 13:54:18.534104 <6>[ 0.608733] scmi_core: SCMI protocol bus registered
10430 13:54:18.537158 <6>[ 0.614810] FPGA manager framework
10431 13:54:18.544094 <6>[ 0.618504] Advanced Linux Sound Architecture Driver Initialized.
10432 13:54:18.547679 <6>[ 0.625481] vgaarb: loaded
10433 13:54:18.553838 <6>[ 0.628867] clocksource: Switched to clocksource arch_sys_counter
10434 13:54:18.560814 <5>[ 0.635341] VFS: Disk quotas dquot_6.6.0
10435 13:54:18.567279 <6>[ 0.639525] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10436 13:54:18.570802 <6>[ 0.646705] pnp: PnP ACPI: disabled
10437 13:54:18.579215 <6>[ 0.653772] NET: Registered PF_INET protocol family
10438 13:54:18.585688 <6>[ 0.659344] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10439 13:54:18.600308 <6>[ 0.671696] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10440 13:54:18.609884 <6>[ 0.680504] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10441 13:54:18.616836 <6>[ 0.688475] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10442 13:54:18.626157 <6>[ 0.697124] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10443 13:54:18.632907 <6>[ 0.706865] TCP: Hash tables configured (established 65536 bind 65536)
10444 13:54:18.639521 <6>[ 0.713664] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10445 13:54:18.649719 <6>[ 0.720865] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10446 13:54:18.653243 <6>[ 0.728558] NET: Registered PF_UNIX/PF_LOCAL protocol family
10447 13:54:18.660322 <6>[ 0.734696] RPC: Registered named UNIX socket transport module.
10448 13:54:18.666181 <6>[ 0.740849] RPC: Registered udp transport module.
10449 13:54:18.669942 <6>[ 0.745786] RPC: Registered tcp transport module.
10450 13:54:18.676709 <6>[ 0.750718] RPC: Registered tcp-with-tls transport module.
10451 13:54:18.683341 <6>[ 0.756430] RPC: Registered tcp NFSv4.1 backchannel transport module.
10452 13:54:18.686086 <6>[ 0.763095] PCI: CLS 0 bytes, default 64
10453 13:54:18.689682 <6>[ 0.767466] Unpacking initramfs...
10454 13:54:18.696267 <6>[ 0.771466] kvm [1]: IPA Size Limit: 40 bits
10455 13:54:18.700001 <6>[ 0.775995] kvm [1]: GICv3: no GICV resource entry
10456 13:54:18.706652 <6>[ 0.781018] kvm [1]: disabling GICv2 emulation
10457 13:54:18.712997 <6>[ 0.785709] kvm [1]: GIC system register CPU interface enabled
10458 13:54:18.716415 <6>[ 0.791783] kvm [1]: vgic interrupt IRQ18
10459 13:54:18.722924 <6>[ 0.796047] kvm [1]: VHE mode initialized successfully
10460 13:54:18.726289 <5>[ 0.802386] Initialise system trusted keyrings
10461 13:54:18.732811 <6>[ 0.807180] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10462 13:54:18.739479 <6>[ 0.814090] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10463 13:54:18.745961 <5>[ 0.820325] NFS: Registering the id_resolver key type
10464 13:54:18.749548 <5>[ 0.825620] Key type id_resolver registered
10465 13:54:18.753042 <5>[ 0.830032] Key type id_legacy registered
10466 13:54:18.762889 <6>[ 0.834284] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10467 13:54:18.769180 <6>[ 0.841205] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10468 13:54:18.775802 <6>[ 0.848915] 9p: Installing v9fs 9p2000 file system support
10469 13:54:18.801741 <5>[ 0.876942] Key type asymmetric registered
10470 13:54:18.805334 <5>[ 0.881276] Asymmetric key parser 'x509' registered
10471 13:54:18.815466 <6>[ 0.886418] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10472 13:54:18.818788 <6>[ 0.894041] io scheduler mq-deadline registered
10473 13:54:18.822204 <6>[ 0.898801] io scheduler kyber registered
10474 13:54:18.828425 <6>[ 0.903085] io scheduler bfq registered
10475 13:54:18.847985 <6>[ 0.922940] EINJ: ACPI disabled.
10476 13:54:18.859459 <3>[ 0.934651] cannot find "mediatek,mt8192-fhctl"
10477 13:54:18.899874 <6>[ 0.974402] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10478 13:54:18.907706 <6>[ 0.982897] printk: console [ttyS0] disabled
10479 13:54:18.936159 <6>[ 1.007657] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 252, base_baud = 1625000) is a ST16650V2
10480 13:54:18.943028 <6>[ 1.017128] printk: console [ttyS0] enabled
10481 13:54:18.946307 <6>[ 1.017128] printk: console [ttyS0] enabled
10482 13:54:18.949623 <6>[ 1.026019] printk: bootconsole [mtk8250] disabled
10483 13:54:18.956184 <6>[ 1.026019] printk: bootconsole [mtk8250] disabled
10484 13:54:18.962743 <6>[ 1.037830] SuperH (H)SCI(F) driver initialized
10485 13:54:18.965943 <6>[ 1.043192] msm_serial: driver initialized
10486 13:54:18.973528 <6>[ 1.048324] STM32 USART driver initialized
10487 13:54:18.986471 <6>[ 1.061187] loop: module loaded
10488 13:54:18.992945 <4>[ 1.066923] mtk-pmic-keys: Failed to locate of_node [id: -1]
10489 13:54:18.999446 <6>[ 1.067907] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10490 13:54:19.002498 <6>[ 1.073948] megasas: 07.725.01.00-rc1
10491 13:54:19.009636 <6>[ 1.084616] vsram_others: Bringing 850000uV into 800000-800000uV
10492 13:54:19.017689 <6>[ 1.092328] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10493 13:54:19.024062 <6>[ 1.096269] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10494 13:54:19.038861 <6>[ 1.113379] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10495 13:54:19.106308 <6>[ 1.174706] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10496 13:54:19.661422 <6>[ 1.736124] Freeing initrd memory: 22332K
10497 13:54:19.678853 <6>[ 1.754225] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10498 13:54:19.690236 <6>[ 1.764998] tun: Universal TUN/TAP device driver, 1.6
10499 13:54:19.693590 <6>[ 1.771224] thunder_xcv, ver 1.0
10500 13:54:19.696906 <6>[ 1.774726] thunder_bgx, ver 1.0
10501 13:54:19.700348 <6>[ 1.778222] nicpf, ver 1.0
10502 13:54:19.710586 <6>[ 1.782343] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10503 13:54:19.714142 <6>[ 1.789819] hns3: Copyright (c) 2017 Huawei Corporation.
10504 13:54:19.720948 <6>[ 1.795399] hclge is initializing
10505 13:54:19.723874 <6>[ 1.798998] e1000: Intel(R) PRO/1000 Network Driver
10506 13:54:19.730601 <6>[ 1.804129] e1000: Copyright (c) 1999-2006 Intel Corporation.
10507 13:54:19.734297 <6>[ 1.810140] e1000e: Intel(R) PRO/1000 Network Driver
10508 13:54:19.740744 <6>[ 1.815357] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10509 13:54:19.747373 <6>[ 1.821538] igb: Intel(R) Gigabit Ethernet Network Driver
10510 13:54:19.754389 <6>[ 1.827188] igb: Copyright (c) 2007-2014 Intel Corporation.
10511 13:54:19.760522 <6>[ 1.833023] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10512 13:54:19.764005 <6>[ 1.839541] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10513 13:54:19.770949 <6>[ 1.846040] sky2: driver version 1.30
10514 13:54:19.777462 <6>[ 1.851219] usbcore: registered new device driver r8152-cfgselector
10515 13:54:19.784602 <6>[ 1.857751] usbcore: registered new interface driver r8152
10516 13:54:19.787340 <6>[ 1.863693] VFIO - User Level meta-driver version: 0.3
10517 13:54:19.796987 <6>[ 1.872010] usbcore: registered new interface driver usb-storage
10518 13:54:19.803885 <6>[ 1.878527] usbcore: registered new device driver onboard-usb-hub
10519 13:54:19.813025 <6>[ 1.888060] mt6397-rtc mt6359-rtc: registered as rtc0
10520 13:54:19.822990 <6>[ 1.893521] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-16T13:49:40 UTC (1715867380)
10521 13:54:19.826648 <6>[ 1.903240] i2c_dev: i2c /dev entries driver
10522 13:54:19.837422 <6>[ 1.908915] platform 14010000.dsi: Fixed dependency cycle(s) with /soc/i2c@11cb0000/anx7625@58
10523 13:54:19.847036 <6>[ 1.917833] i2c 3-0058: Fixed dependency cycle(s) with /soc/i2c@11cb0000/anx7625@58/aux-bus/panel
10524 13:54:19.854152 <6>[ 1.926974] i2c 3-0058: Fixed dependency cycle(s) with /soc/dsi@14010000
10525 13:54:19.870518 <6>[ 1.942433] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10526 13:54:19.877435 <4>[ 1.951671] cpu cpu0: supply cpu not found, using dummy regulator
10527 13:54:19.883953 <4>[ 1.958109] cpu cpu1: supply cpu not found, using dummy regulator
10528 13:54:19.890674 <4>[ 1.964520] cpu cpu2: supply cpu not found, using dummy regulator
10529 13:54:19.897376 <4>[ 1.970924] cpu cpu3: supply cpu not found, using dummy regulator
10530 13:54:19.904258 <4>[ 1.977359] cpu cpu4: supply cpu not found, using dummy regulator
10531 13:54:19.910989 <4>[ 1.983759] cpu cpu5: supply cpu not found, using dummy regulator
10532 13:54:19.917312 <4>[ 1.990163] cpu cpu6: supply cpu not found, using dummy regulator
10533 13:54:19.923984 <4>[ 1.996569] cpu cpu7: supply cpu not found, using dummy regulator
10534 13:54:19.942722 <6>[ 2.018035] cpu cpu0: EM: created perf domain
10535 13:54:19.946303 <6>[ 2.022950] cpu cpu4: EM: created perf domain
10536 13:54:19.953730 <6>[ 2.028745] sdhci: Secure Digital Host Controller Interface driver
10537 13:54:19.960087 <6>[ 2.035177] sdhci: Copyright(c) Pierre Ossman
10538 13:54:19.966765 <6>[ 2.040232] Synopsys Designware Multimedia Card Interface Driver
10539 13:54:19.973988 <6>[ 2.046924] sdhci-pltfm: SDHCI platform and OF driver helper
10540 13:54:19.976836 <6>[ 2.046979] mmc0: CQHCI version 5.10
10541 13:54:19.983553 <6>[ 2.057993] ledtrig-cpu: registered to indicate activity on CPUs
10542 13:54:19.993759 <6>[ 2.065747] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10543 13:54:19.997184 <6>[ 2.073086] usbcore: registered new interface driver usbhid
10544 13:54:20.004184 <6>[ 2.078916] usbhid: USB HID core driver
10545 13:54:20.010329 <6>[ 2.083273] spi_master spi0: will run message pump with realtime priority
10546 13:54:20.021520 <6>[ 2.091563] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10547 13:54:20.028333 <6>[ 2.100880] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10548 13:54:20.041445 <6>[ 2.113067] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10549 13:54:20.054573 <6>[ 2.122573] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10550 13:54:20.061819 <6>[ 2.124266] NET: Registered PF_PACKET protocol family
10551 13:54:20.064696 <6>[ 2.140641] 9pnet: Installing 9P2000 support
10552 13:54:20.068374 <5>[ 2.145201] Key type dns_resolver registered
10553 13:54:20.086556 <6>[ 2.151521] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10554 13:54:20.090267 <6>[ 2.152631] registered taskstats version 1
10555 13:54:20.097358 <6>[ 2.168351] cros-ec-spi spi0.0: Chrome EC device registered
10556 13:54:20.100273 <5>[ 2.169650] Loading compiled-in X.509 certificates
10557 13:54:20.103783 <6>[ 2.180359] mmc0: Command Queue Engine enabled
10558 13:54:20.110686 <6>[ 2.185109] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10559 13:54:20.117714 <6>[ 2.192935] mmcblk0: mmc0:0001 DA4128 116 GiB
10560 13:54:20.130161 <6>[ 2.202697] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10561 13:54:20.136652 <6>[ 2.210284] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10562 13:54:20.143463 <6>[ 2.215776] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10563 13:54:20.146878 <6>[ 2.216223] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10564 13:54:20.153433 <6>[ 2.222708] xhci-mtk 11200000.usb: xHCI Host Controller
10565 13:54:20.160252 <6>[ 2.227802] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10566 13:54:20.166561 <6>[ 2.232614] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10567 13:54:20.176284 <6>[ 2.247057] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000200010
10568 13:54:20.183549 <6>[ 2.256498] xhci-mtk 11200000.usb: irq 270, io mem 0x11200000
10569 13:54:20.186375 <6>[ 2.262573] xhci-mtk 11200000.usb: xHCI Host Controller
10570 13:54:20.196623 <6>[ 2.268049] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10571 13:54:20.203430 <6>[ 2.275698] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10572 13:54:20.206458 <6>[ 2.283518] hub 1-0:1.0: USB hub found
10573 13:54:20.213023 <6>[ 2.287561] hub 1-0:1.0: 1 port detected
10574 13:54:20.219910 <6>[ 2.291844] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10575 13:54:20.223396 <6>[ 2.300605] hub 2-0:1.0: USB hub found
10576 13:54:20.229979 <6>[ 2.304632] hub 2-0:1.0: 1 port detected
10577 13:54:20.236483 <3>[ 2.309642] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10578 13:54:20.246752 <6>[ 2.322039] mtk-msdc 11f70000.mmc: Got CD GPIO
10579 13:54:20.258822 <4>[ 2.330304] rt5682 1-001a: Using default DAI clk names: rt5682-dai-wclk, rt5682-dai-bclk
10580 13:54:20.265772 <3>[ 2.337829] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10581 13:54:20.287050 <3>[ 2.359069] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10582 13:54:20.307311 <3>[ 2.378799] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10583 13:54:20.617892 <6>[ 2.689560] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10584 13:54:20.646944 <6>[ 2.722258] hub 2-1:1.0: USB hub found
10585 13:54:20.650210 <6>[ 2.726820] hub 2-1:1.0: 3 ports detected
10586 13:54:20.675773 <3>[ 2.747222] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10587 13:54:20.678997 <6>[ 2.756320] hub 2-1:1.0: USB hub found
10588 13:54:20.685462 <6>[ 2.760699] hub 2-1:1.0: 3 ports detected
10589 13:54:20.711654 <3>[ 2.783883] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10590 13:54:20.769379 <6>[ 2.841118] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10591 13:54:20.922776 <6>[ 2.997969] hub 1-1:1.0: USB hub found
10592 13:54:20.925868 <6>[ 3.002389] hub 1-1:1.0: 4 ports detected
10593 13:54:20.964640 <3>[ 3.036669] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10594 13:54:20.971888 <6>[ 3.046125] hub 1-1:1.0: USB hub found
10595 13:54:20.974792 <6>[ 3.050520] hub 1-1:1.0: 4 ports detected
10596 13:54:21.005178 <3>[ 3.076548] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10597 13:54:21.011132 <6>[ 3.084514] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10598 13:54:21.121632 <6>[ 3.193579] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10599 13:54:21.160021 <4>[ 3.230754] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10600 13:54:21.166513 <4>[ 3.239885] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10601 13:54:21.215387 <6>[ 3.290733] r8152 2-1.3:1.0 eth0: v1.12.13
10602 13:54:21.262637 <3>[ 3.334231] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10603 13:54:21.300952 <6>[ 3.373096] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10604 13:54:21.434018 <6>[ 3.508948] hub 1-1.4:1.0: USB hub found
10605 13:54:21.437079 <6>[ 3.513612] hub 1-1.4:1.0: 2 ports detected
10606 13:54:21.493654 <3>[ 3.565690] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10607 13:54:21.500966 <6>[ 3.576084] hub 1-1.4:1.0: USB hub found
10608 13:54:21.503960 <6>[ 3.580684] hub 1-1.4:1.0: 2 ports detected
10609 13:54:21.554070 <3>[ 3.625896] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10610 13:54:21.800963 <6>[ 3.873193] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10611 13:54:21.959658 <3>[ 4.031450] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10612 13:54:21.997053 <6>[ 4.069069] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10613 13:54:22.154757 <3>[ 4.226546] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10614 13:54:22.836931 <6>[ 4.912039] r8152 2-1.3:1.0 eth0: carrier on
10615 13:54:25.657383 <5>[ 4.940975] Sending DHCP requests .., OK
10616 13:54:25.663770 <6>[ 7.737379] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10617 13:54:25.667273 <6>[ 7.745684] IP-Config: Complete:
10618 13:54:25.680244 <6>[ 7.749180] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10619 13:54:25.686973 <6>[ 7.759890] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10620 13:54:25.693503 <6>[ 7.768507] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10621 13:54:25.700485 <6>[ 7.768516] nameserver0=192.168.201.1
10622 13:54:25.704011 <6>[ 7.780640] clk: Disabling unused clocks
10623 13:54:25.707555 <6>[ 7.785886] ALSA device list:
10624 13:54:25.710417 <6>[ 7.789144] No soundcards found.
10625 13:54:25.722095 <6>[ 7.797608] Freeing unused kernel memory: 9984K
10626 13:54:25.724983 <6>[ 7.802601] Run /init as init process
10627 13:54:25.756061 Starting syslogd: OK
10628 13:54:25.760621 Starting klogd: OK
10629 13:54:25.766654 Running sysctl: OK
10630 13:54:25.773292 Populating /dev using udev: <30>[ 7.850572] udevd[170]: starting version 3.2.9
10631 13:54:25.781692 <27>[ 7.857184] udevd[170]: specified user 'tss' unknown
10632 13:54:25.787884 <27>[ 7.862516] udevd[170]: specified group 'tss' unknown
10633 13:54:25.791497 <30>[ 7.869045] udevd[171]: starting eudev-3.2.9
10634 13:54:26.050682 <3>[ 8.122789] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10635 13:54:26.057256 <6>[ 8.124090] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10636 13:54:26.066991 <6>[ 8.138394] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10637 13:54:26.074032 <6>[ 8.147315] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10638 13:54:26.080521 <6>[ 8.149718] mc: Linux media interface: v0.10
10639 13:54:26.087070 <6>[ 8.157579] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10640 13:54:26.100963 <6>[ 8.176765] remoteproc remoteproc0: scp is available
10641 13:54:26.110802 <6>[ 8.177896] mediatek-mipi-tx 11e50000.dsi-phy: can't get nvmem_cell_get, ignore it
10642 13:54:26.114702 <6>[ 8.182232] remoteproc remoteproc0: powering up scp
10643 13:54:26.124241 <6>[ 8.182245] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10644 13:54:26.127767 <6>[ 8.182303] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10645 13:54:26.151536 <6>[ 8.227198] videodev: Linux video capture interface: v2.00
10646 13:54:26.161409 <4>[ 8.227325] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
10647 13:54:26.167904 <4>[ 8.227797] elants_i2c 0-0010: supply vccio not found, using dummy regulator
10648 13:54:26.171406 <6>[ 8.233175] Bluetooth: Core ver 2.22
10649 13:54:26.178281 <6>[ 8.234438] NET: Registered PF_BLUETOOTH protocol family
10650 13:54:26.184887 <3>[ 8.234648] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10651 13:54:26.191360 <3>[ 8.234728] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10652 13:54:26.201320 <3>[ 8.234751] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10653 13:54:26.207769 <3>[ 8.234940] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10654 13:54:26.218385 <3>[ 8.234961] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10655 13:54:26.224763 <3>[ 8.234976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10656 13:54:26.234626 <3>[ 8.234998] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10657 13:54:26.241380 <3>[ 8.235023] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10658 13:54:26.248145 <3>[ 8.235048] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10659 13:54:26.258176 <3>[ 8.235122] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10660 13:54:26.265313 <3>[ 8.235137] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10661 13:54:26.272449 <3>[ 8.235259] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10662 13:54:26.282827 <3>[ 8.235273] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10663 13:54:26.289097 <3>[ 8.235291] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10664 13:54:26.299260 <3>[ 8.235448] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10665 13:54:26.305486 <3>[ 8.235467] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10666 13:54:26.315666 <3>[ 8.235490] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10667 13:54:26.321988 <3>[ 8.235518] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10668 13:54:26.331859 <3>[ 8.235538] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10669 13:54:26.338889 <3>[ 8.235550] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10670 13:54:26.345686 <3>[ 8.235618] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10671 13:54:26.355398 <3>[ 8.235637] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10672 13:54:26.362449 <6>[ 8.258078] sbs-battery 8-000b: sbs-battery: battery gas gauge device registered
10673 13:54:26.368759 <6>[ 8.265529] Bluetooth: HCI device and connection manager initialized
10674 13:54:26.375533 <3>[ 8.268971] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10675 13:54:26.385221 <6>[ 8.279258] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10676 13:54:26.388839 <6>[ 8.281792] Bluetooth: HCI socket layer initialized
10677 13:54:26.395708 <6>[ 8.289940] pci_bus 0000:00: root bus resource [bus 00-ff]
10678 13:54:26.398447 <6>[ 8.297980] Bluetooth: L2CAP socket layer initialized
10679 13:54:26.408701 <6>[ 8.306212] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10680 13:54:26.415627 <4>[ 8.310676] sbs-battery 8-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10681 13:54:26.422073 <4>[ 8.310676] Fallback method does not support PEC.
10682 13:54:26.425229 <6>[ 8.314195] Bluetooth: SCO socket layer initialized
10683 13:54:26.431668 <6>[ 8.314246] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10684 13:54:26.441912 <6>[ 8.314375] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10685 13:54:26.448067 <6>[ 8.314391] remoteproc remoteproc0: remote processor scp is now up
10686 13:54:26.455167 <6>[ 8.317663] panfrost 13000000.gpu: clock rate = 357999878
10687 13:54:26.461285 <6>[ 8.319026] panfrost 13000000.gpu: mali-g57 id 0x9093 major 0x4 minor 0x0 status 0x0
10688 13:54:26.471197 <6>[ 8.319029] panfrost 13000000.gpu: features: 00000000,000019f7, issues: 00000001,80000400
10689 13:54:26.481607 <6>[ 8.319035] panfrost 13000000.gpu: Features: L2:0x07130206 Shader:0x00000000 Tiler:0x00000809 Mem:0x101 MMU:0x00002830 AS:0xff JS:0x7
10690 13:54:26.488062 <6>[ 8.319041] panfrost 13000000.gpu: shader_present=0x50045 l2_present=0x1
10691 13:54:26.497597 <6>[ 8.319992] [drm] Initialized panfrost 1.2.0 20180908 for 13000000.gpu on minor 0
10692 13:54:26.507875 <6>[ 8.322248] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10693 13:54:26.514253 <3>[ 8.322960] anx7625 3-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
10694 13:54:26.524363 <3>[ 8.327730] power_supply sbs-8-000b: driver failed to report `time_to_empty_now' property: -5
10695 13:54:26.530901 <6>[ 8.336209] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/ovl@14005000
10696 13:54:26.537937 <6>[ 8.338554] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10697 13:54:26.547812 <6>[ 8.346680] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/ovl@14006000
10698 13:54:26.554073 <3>[ 8.350674] power_supply sbs-8-000b: driver failed to report `time_to_empty_now' property: -5
10699 13:54:26.564718 <4>[ 8.354669] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10700 13:54:26.571033 <6>[ 8.354700] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10701 13:54:26.580936 <6>[ 8.355253] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10702 13:54:26.587270 <6>[ 8.355259] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10703 13:54:26.600747 <3>[ 8.357583] debugfs: Directory '11210000.syscon:mt8192-afe-pcm' with parent 'mt8192_mt6359_rt1015p_rt5682' already present!
10704 13:54:26.610850 <6>[ 8.361531] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-0/0-0010/input/input2
10705 13:54:26.617187 <6>[ 8.362797] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/rdma@14007000
10706 13:54:26.624272 <4>[ 8.363700] rt5682 1-001a: ASoC: source widget I2S1 overwritten
10707 13:54:26.627196 <6>[ 8.370915] pci 0000:00:00.0: supports D1 D2
10708 13:54:26.637290 <6>[ 8.378956] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/color@14009000
10709 13:54:26.643962 <6>[ 8.387038] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10710 13:54:26.653806 <6>[ 8.395112] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/ccorr@1400a000
10711 13:54:26.664069 <6>[ 8.401768] elan_i2c 2-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10712 13:54:26.673921 <6>[ 8.402252] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-2/2-0015/input/input3
10713 13:54:26.680258 <6>[ 8.405294] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10714 13:54:26.690592 <6>[ 8.411310] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/aal@1400b000
10715 13:54:26.696511 <6>[ 8.419445] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10716 13:54:26.703489 <6>[ 8.427771] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/gamma@1400c000
10717 13:54:26.709787 <6>[ 8.435585] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10718 13:54:26.720122 <6>[ 8.443503] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/dsi@14010000
10719 13:54:26.726636 <6>[ 8.449828] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10720 13:54:26.733117 <6>[ 8.449849] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10721 13:54:26.742997 <6>[ 8.457950] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/ovl@14014000
10722 13:54:26.746731 <6>[ 8.464667] pci 0000:01:00.0: supports D1 D2
10723 13:54:26.756731 <6>[ 8.469875] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/rdma@14015000
10724 13:54:26.763040 <6>[ 8.475429] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10725 13:54:26.769920 <6>[ 8.486494] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10726 13:54:26.776484 <6>[ 8.578595] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10727 13:54:26.782912 <6>[ 8.578700] usbcore: registered new interface driver btusb
10728 13:54:26.792758 <4>[ 8.581480] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10729 13:54:26.799510 <3>[ 8.581489] Bluetooth: hci0: Failed to load firmware file (-2)
10730 13:54:26.806209 <3>[ 8.581492] Bluetooth: hci0: Failed to set up firmware (-2)
10731 13:54:26.815929 <4>[ 8.581495] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10732 13:54:26.822647 <6>[ 8.587585] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10733 13:54:26.832467 <6>[ 8.588841] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10734 13:54:26.838884 <6>[ 8.591308] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10735 13:54:26.845619 <6>[ 8.596612] usbcore: registered new interface driver uvcvideo
10736 13:54:26.855376 <6>[ 8.604172] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10737 13:54:26.862451 <6>[ 8.604189] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10738 13:54:26.872036 <6>[ 8.604204] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10739 13:54:26.878524 <6>[ 8.604217] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10740 13:54:26.882183 <6>[ 8.604230] pci 0000:00:00.0: PCI bridge to [bus 01]
10741 13:54:26.891474 <6>[ 8.604236] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10742 13:54:26.898458 <6>[ 8.604467] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10743 13:54:26.904861 <6>[ 8.979415] pcieport 0000:00:00.0: PME: Signaling with IRQ 281
10744 13:54:26.911828 <6>[ 8.986710] pcieport 0000:00:00.0: AER: enabled with IRQ 281
10745 13:54:26.938477 <6>[ 9.011093] input: mt8192_mt6359_rt1015p_rt5682 Headset Jack as /devices/platform/sound/sound/card0/input4
10746 13:54:26.948696 <5>[ 9.012816] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10747 13:54:26.955153 <6>[ 9.025662] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10748 13:54:26.965095 <6>[ 9.037512] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10749 13:54:26.971297 <5>[ 9.042681] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10750 13:54:26.978073 <6>[ 9.045908] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10751 13:54:26.988182 <5>[ 9.052831] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10752 13:54:26.995234 <6>[ 9.060181] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10753 13:54:27.004888 <4>[ 9.067743] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10754 13:54:27.011202 <6>[ 9.076051] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10755 13:54:27.018263 <6>[ 9.084957] cfg80211: failed to load regulatory.db
10756 13:54:27.024665 <6>[ 9.093225] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10757 13:54:27.034387 <6>[ 9.093233] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10758 13:54:27.041480 <6>[ 9.115129] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10759 13:54:27.051059 <6>[ 9.123554] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10760 13:54:27.060881 <6>[ 9.131903] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10761 13:54:27.067407 <6>[ 9.140251] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10762 13:54:27.077277 <6>[ 9.148593] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10763 13:54:27.084453 <6>[ 9.156934] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10764 13:54:27.094378 <6>[ 9.165275] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10765 13:54:27.101007 <6>[ 9.173620] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10766 13:54:27.142121 <6>[ 9.214402] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10767 13:54:27.148389 <6>[ 9.221914] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10768 13:54:27.155065 <6>[ 9.230671] mt7921e 0000:01:00.0: ASIC revision: 79610010
10769 13:54:27.257294 <6>[ 9.330024] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10770 13:54:27.260899 <6>[ 9.330024]
10771 13:54:27.277332 <6>[ 9.350022] panel-simple-dp-aux aux-3-0058: Detected IVO R140NWF5 RH (0x057d)
10772 13:54:27.285792 <6>[ 9.361390] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10773 13:54:27.288619 done
10774 13:54:27.296179 <6>[ 9.372283] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10775 13:54:27.306653 Saving random seed: <6>[ 9.382281] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10776 13:54:27.309747 OK
10777 13:54:27.320814 <6>[ 9.393276] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10778 13:54:27.331332 Starting network: <6>[ 9.403857] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10779 13:54:27.341447 ip: RTNETLINK an<6>[ 9.411296] mediatek-drm mediatek-drm.9.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops [mediatek_drm])
10780 13:54:27.354362 swers: File exis<6>[ 9.422486] mediatek-drm mediatek-drm.9.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops [mediatek_drm])
10781 13:54:27.354496 ts
10782 13:54:27.354567 FAIL
10783 13:54:27.364587 Starti<6>[ 9.434537] mediatek-drm mediatek-drm.9.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops [mediatek_drm])
10784 13:54:27.377849 <6>[ 9.446387] mediatek-drm mediatek-drm.9.auto: bound 14009000.color (ops mtk_disp_color_component_ops [mediatek_drm])
10785 13:54:27.387726 ng dropbear sshd<6>[ 9.457179] mediatek-drm mediatek-drm.9.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops [mediatek_drm])
10786 13:54:27.397519 <6>[ 9.469333] mediatek-drm mediatek-drm.9.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops [mediatek_drm])
10787 13:54:27.411113 <6>[ 9.479771] mediatek-drm mediatek-drm.9.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops [mediatek_drm])
10788 13:54:27.418023 : <6>[ 9.491701] NET: Registered PF_INET6 protocol family
10789 13:54:27.427721 <6>[ 9.492565] mediatek-drm mediatek-drm.9.auto: bound 14010000.dsi (ops mtk_dsi_component_ops [mediatek_drm])
10790 13:54:27.430997 <6>[ 9.497771] Segment Routing with IPv6
10791 13:54:27.440920 <6>[ 9.506919] mediatek-drm mediatek-drm.9.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops [mediatek_drm])
10792 13:54:27.450499 <6>[ 9.506933] mediatek-drm mediatek-drm.9.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops [mediatek_drm])
10793 13:54:27.453724 <6>[ 9.510896] In-situ OAM (IOAM) with IPv6
10794 13:54:27.463569 <6>[ 9.521308] mediatek-drm mediatek-drm.9.auto: Not creating crtc 1 because component 10 is disabled or missing
10795 13:54:27.466844 OK
10796 13:54:27.473585 <6>[ 9.547266] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.9.auto on minor 1
10797 13:54:27.480132 /bin/sh: can't access tty; job control turned off
10798 13:54:27.480503 Matched prompt #10: / #
10800 13:54:27.480723 Setting prompt string to ['/ #']
10801 13:54:27.480828 end: 2.2.5.1 login-action (duration 00:00:10) [common]
10803 13:54:27.481025 end: 2.2.5 auto-login-action (duration 00:00:10) [common]
10804 13:54:27.481127 start: 2.2.6 expect-shell-connection (timeout 00:03:48) [common]
10805 13:54:27.481200 Setting prompt string to ['/ #']
10806 13:54:27.481262 Forcing a shell prompt, looking for ['/ #']
10808 13:54:27.531460 / #
10809 13:54:27.531626 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10810 13:54:27.531704 Waiting using forced prompt support (timeout 00:02:30)
10811 13:54:27.531807 <6>[ 9.599808] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10812 13:54:27.536672
10813 13:54:27.536967 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10814 13:54:27.537071 start: 2.2.7 export-device-env (timeout 00:03:48) [common]
10815 13:54:27.537163 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10816 13:54:27.537256 end: 2.2 depthcharge-retry (duration 00:01:12) [common]
10817 13:54:27.537347 end: 2 depthcharge-action (duration 00:01:12) [common]
10818 13:54:27.537442 start: 3 lava-test-retry (timeout 00:01:00) [common]
10819 13:54:27.537534 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10820 13:54:27.537624 Using namespace: common
10822 13:54:27.637979 / # #
10823 13:54:27.638139 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10824 13:54:27.642866 #
10825 13:54:27.643138 Using /lava-13842491
10827 13:54:27.743436 / # export SHELL=/bin/sh
10828 13:54:27.748505 export SHELL=/bin/sh
10830 13:54:27.848995 / # . /lava-13842491/environment
10831 13:54:27.857871 . /lava-13842491/environment
10833 13:54:27.958459 / # /lava-13842491/bin/lava-test-runner /lava-13842491/0
10834 13:54:27.958630 Test shell timeout: 10s (minimum of the action and connection timeout)
10835 13:54:27.959013 <6>[ 9.941013] Console: switching to colour frame buffer device 240x67
10836 13:54:27.959094 <6>[ 9.961875] mediatek-drm mediatek-drm.9.auto: [drm] fb0: mediatekdrmfb frame buffer device
10837 13:54:27.959202 <6>[ 9.992574] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 1
10838 13:54:27.959304 <4>[ 9.999293] ttyS ttyS0: 1 input overrun(s)
10839 13:54:27.959393 /lava-13842491/bin/lava-test-runner /l<6>[ 10.006431] mtk-vcodec-dec 16000000.video-codec: Adding to iommu group 1
10840 13:54:27.961840 <6>[ 10.034142] mtk-vdec-comp 16010000.video-codec: Adding to iommu group 1
10841 13:54:28.004489 <6>[ 10.041639] mtk-vdec-comp 16025000.video-codec: Adding to iommu group 1
10842 13:54:28.004665
10843 13:54:28.004938 /lava-13842491/bin/lava-test-runner: .: line 18: can't open '/l/../bin/lava-common-functions': No such file or directory
10844 13:54:28.343933 / # <6>[ 10.419617] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10845 13:54:55.886883 <6>[ 37.969220] vpu: disabling
10846 13:54:55.890100 <6>[ 37.972325] vproc2: disabling
10847 13:54:55.893587 <6>[ 37.975663] vproc1: disabling
10848 13:54:55.896949 <6>[ 37.979207] vaud18: disabling
10849 13:54:55.900858 <6>[ 37.982957] va09: disabling
10850 13:54:55.904072 <6>[ 37.986114] vsram_md: disabling
10851 13:54:55.914396 <6>[ 37.993630] pp1000_dpbrdg: disabling
10852 13:54:55.917871 <6>[ 37.997468] pp1800_dpbrdg: disabling
10853 13:54:55.921368 <6>[ 38.001311] pp3300_dpbrdg: disabling
10855 13:55:27.537790 end: 3.1 lava-test-shell (duration 00:01:00) [common]
10857 13:55:27.537980 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
10859 13:55:27.538136 end: 3 lava-test-retry (duration 00:01:00) [common]
10861 13:55:27.538370 Cleaning after the job
10862 13:55:27.538461 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13842491/tftp-deploy-jr0n5hf8/ramdisk
10863 13:55:27.541143 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13842491/tftp-deploy-jr0n5hf8/kernel
10864 13:55:27.552538 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13842491/tftp-deploy-jr0n5hf8/dtb
10865 13:55:27.552767 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13842491/tftp-deploy-jr0n5hf8/modules
10866 13:55:27.559003 start: 4.1 power-off (timeout 00:00:30) [common]
10867 13:55:27.559211 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
10868 13:55:27.634910 >> Command sent successfully.
10869 13:55:27.637922 Returned 0 in 0 seconds
10870 13:55:27.738340 end: 4.1 power-off (duration 00:00:00) [common]
10872 13:55:27.738723 start: 4.2 read-feedback (timeout 00:10:00) [common]
10873 13:55:27.739001 Listened to connection for namespace 'common' for up to 1s
10874 13:55:28.739915 Finalising connection for namespace 'common'
10875 13:55:28.740121 Disconnecting from shell: Finalise
10876 13:55:28.840485 end: 4.2 read-feedback (duration 00:00:01) [common]
10877 13:55:28.840642 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13842491
10878 13:55:28.886875 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13842491
10879 13:55:28.887072 TestError: A test failed to run, look at the error message.