Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 19:14:44.652408 lava-dispatcher, installed at version: 2024.01
2 19:14:44.653128 start: 0 validate
3 19:14:44.653584 Start time: 2024-11-05 19:14:44.653553+00:00 (UTC)
4 19:14:44.654125 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 19:14:44.654654 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 19:14:44.692884 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 19:14:44.693546 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fardb%2Ffor-kernelci%2Fv6.12-rc1-122-g309bfa414d7e4%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 19:14:44.725116 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 19:14:44.725846 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fardb%2Ffor-kernelci%2Fv6.12-rc1-122-g309bfa414d7e4%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 19:14:44.758681 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 19:14:44.759260 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:14:44.787620 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 19:14:44.788115 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fardb%2Ffor-kernelci%2Fv6.12-rc1-122-g309bfa414d7e4%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 19:14:44.825128 validate duration: 0.17
16 19:14:44.825987 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:14:44.826325 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:14:44.826651 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:14:44.827231 Not decompressing ramdisk as can be used compressed.
20 19:14:44.827680 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 19:14:44.827976 saving as /var/lib/lava/dispatcher/tmp/941864/tftp-deploy-ydf8efhn/ramdisk/initrd.cpio.gz
22 19:14:44.828272 total size: 5628140 (5 MB)
23 19:14:44.865998 progress 0 % (0 MB)
24 19:14:44.869898 progress 5 % (0 MB)
25 19:14:44.873951 progress 10 % (0 MB)
26 19:14:44.877503 progress 15 % (0 MB)
27 19:14:44.881396 progress 20 % (1 MB)
28 19:14:44.884969 progress 25 % (1 MB)
29 19:14:44.888873 progress 30 % (1 MB)
30 19:14:44.892805 progress 35 % (1 MB)
31 19:14:44.896381 progress 40 % (2 MB)
32 19:14:44.900351 progress 45 % (2 MB)
33 19:14:44.903864 progress 50 % (2 MB)
34 19:14:44.907782 progress 55 % (2 MB)
35 19:14:44.911737 progress 60 % (3 MB)
36 19:14:44.915255 progress 65 % (3 MB)
37 19:14:44.919135 progress 70 % (3 MB)
38 19:14:44.922674 progress 75 % (4 MB)
39 19:14:44.926609 progress 80 % (4 MB)
40 19:14:44.930126 progress 85 % (4 MB)
41 19:14:44.933956 progress 90 % (4 MB)
42 19:14:44.937554 progress 95 % (5 MB)
43 19:14:44.940869 progress 100 % (5 MB)
44 19:14:44.941530 5 MB downloaded in 0.11 s (47.40 MB/s)
45 19:14:44.942091 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:14:44.943024 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:14:44.943340 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:14:44.943630 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:14:44.944137 downloading http://storage.kernelci.org/ardb/for-kernelci/v6.12-rc1-122-g309bfa414d7e4/arm64/defconfig/gcc-12/kernel/Image
51 19:14:44.944407 saving as /var/lib/lava/dispatcher/tmp/941864/tftp-deploy-ydf8efhn/kernel/Image
52 19:14:44.944628 total size: 45713920 (43 MB)
53 19:14:44.944851 No compression specified
54 19:14:44.982645 progress 0 % (0 MB)
55 19:14:45.011421 progress 5 % (2 MB)
56 19:14:45.040074 progress 10 % (4 MB)
57 19:14:45.068753 progress 15 % (6 MB)
58 19:14:45.097436 progress 20 % (8 MB)
59 19:14:45.125518 progress 25 % (10 MB)
60 19:14:45.154212 progress 30 % (13 MB)
61 19:14:45.182943 progress 35 % (15 MB)
62 19:14:45.211575 progress 40 % (17 MB)
63 19:14:45.239774 progress 45 % (19 MB)
64 19:14:45.268281 progress 50 % (21 MB)
65 19:14:45.297118 progress 55 % (24 MB)
66 19:14:45.325590 progress 60 % (26 MB)
67 19:14:45.353858 progress 65 % (28 MB)
68 19:14:45.382793 progress 70 % (30 MB)
69 19:14:45.411412 progress 75 % (32 MB)
70 19:14:45.440118 progress 80 % (34 MB)
71 19:14:45.468329 progress 85 % (37 MB)
72 19:14:45.497122 progress 90 % (39 MB)
73 19:14:45.525639 progress 95 % (41 MB)
74 19:14:45.553364 progress 100 % (43 MB)
75 19:14:45.553884 43 MB downloaded in 0.61 s (71.56 MB/s)
76 19:14:45.554372 end: 1.2.1 http-download (duration 00:00:01) [common]
78 19:14:45.555199 end: 1.2 download-retry (duration 00:00:01) [common]
79 19:14:45.555477 start: 1.3 download-retry (timeout 00:09:59) [common]
80 19:14:45.555744 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 19:14:45.556244 downloading http://storage.kernelci.org/ardb/for-kernelci/v6.12-rc1-122-g309bfa414d7e4/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 19:14:45.556526 saving as /var/lib/lava/dispatcher/tmp/941864/tftp-deploy-ydf8efhn/dtb/meson-g12b-a311d-libretech-cc.dtb
83 19:14:45.556739 total size: 54703 (0 MB)
84 19:14:45.556951 No compression specified
85 19:14:45.600636 progress 59 % (0 MB)
86 19:14:45.601486 progress 100 % (0 MB)
87 19:14:45.602031 0 MB downloaded in 0.05 s (1.15 MB/s)
88 19:14:45.602516 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:14:45.603339 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:14:45.603604 start: 1.4 download-retry (timeout 00:09:59) [common]
92 19:14:45.603869 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 19:14:45.604350 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 19:14:45.604595 saving as /var/lib/lava/dispatcher/tmp/941864/tftp-deploy-ydf8efhn/nfsrootfs/full.rootfs.tar
95 19:14:45.604801 total size: 474398908 (452 MB)
96 19:14:45.605012 Using unxz to decompress xz
97 19:14:45.642897 progress 0 % (0 MB)
98 19:14:46.727537 progress 5 % (22 MB)
99 19:14:48.209306 progress 10 % (45 MB)
100 19:14:48.658034 progress 15 % (67 MB)
101 19:14:49.439491 progress 20 % (90 MB)
102 19:14:49.970832 progress 25 % (113 MB)
103 19:14:50.325230 progress 30 % (135 MB)
104 19:14:50.938943 progress 35 % (158 MB)
105 19:14:51.841375 progress 40 % (181 MB)
106 19:14:52.682051 progress 45 % (203 MB)
107 19:14:53.335120 progress 50 % (226 MB)
108 19:14:53.980873 progress 55 % (248 MB)
109 19:14:55.226242 progress 60 % (271 MB)
110 19:14:56.725084 progress 65 % (294 MB)
111 19:14:58.363711 progress 70 % (316 MB)
112 19:15:01.435817 progress 75 % (339 MB)
113 19:15:03.895965 progress 80 % (361 MB)
114 19:15:06.774811 progress 85 % (384 MB)
115 19:15:09.903470 progress 90 % (407 MB)
116 19:15:13.045170 progress 95 % (429 MB)
117 19:15:16.165304 progress 100 % (452 MB)
118 19:15:16.178116 452 MB downloaded in 30.57 s (14.80 MB/s)
119 19:15:16.178851 end: 1.4.1 http-download (duration 00:00:31) [common]
121 19:15:16.180585 end: 1.4 download-retry (duration 00:00:31) [common]
122 19:15:16.181122 start: 1.5 download-retry (timeout 00:09:29) [common]
123 19:15:16.181643 start: 1.5.1 http-download (timeout 00:09:29) [common]
124 19:15:16.182638 downloading http://storage.kernelci.org/ardb/for-kernelci/v6.12-rc1-122-g309bfa414d7e4/arm64/defconfig/gcc-12/modules.tar.xz
125 19:15:16.183118 saving as /var/lib/lava/dispatcher/tmp/941864/tftp-deploy-ydf8efhn/modules/modules.tar
126 19:15:16.183536 total size: 11611380 (11 MB)
127 19:15:16.183961 Using unxz to decompress xz
128 19:15:16.227862 progress 0 % (0 MB)
129 19:15:16.293920 progress 5 % (0 MB)
130 19:15:16.366880 progress 10 % (1 MB)
131 19:15:16.461186 progress 15 % (1 MB)
132 19:15:16.554509 progress 20 % (2 MB)
133 19:15:16.632832 progress 25 % (2 MB)
134 19:15:16.707401 progress 30 % (3 MB)
135 19:15:16.784633 progress 35 % (3 MB)
136 19:15:16.857670 progress 40 % (4 MB)
137 19:15:16.932879 progress 45 % (5 MB)
138 19:15:17.015827 progress 50 % (5 MB)
139 19:15:17.091601 progress 55 % (6 MB)
140 19:15:17.175439 progress 60 % (6 MB)
141 19:15:17.256377 progress 65 % (7 MB)
142 19:15:17.335581 progress 70 % (7 MB)
143 19:15:17.412480 progress 75 % (8 MB)
144 19:15:17.494806 progress 80 % (8 MB)
145 19:15:17.574872 progress 85 % (9 MB)
146 19:15:17.653401 progress 90 % (9 MB)
147 19:15:17.730307 progress 95 % (10 MB)
148 19:15:17.806216 progress 100 % (11 MB)
149 19:15:17.819120 11 MB downloaded in 1.64 s (6.77 MB/s)
150 19:15:17.820090 end: 1.5.1 http-download (duration 00:00:02) [common]
152 19:15:17.821759 end: 1.5 download-retry (duration 00:00:02) [common]
153 19:15:17.822283 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 19:15:17.822805 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 19:15:33.469745 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/941864/extract-nfsrootfs-_2v4cjao
156 19:15:33.470345 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 19:15:33.470667 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 19:15:33.471296 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9
159 19:15:33.471739 makedir: /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin
160 19:15:33.472095 makedir: /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/tests
161 19:15:33.472419 makedir: /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/results
162 19:15:33.472748 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-add-keys
163 19:15:33.473268 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-add-sources
164 19:15:33.473766 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-background-process-start
165 19:15:33.474316 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-background-process-stop
166 19:15:33.474855 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-common-functions
167 19:15:33.475351 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-echo-ipv4
168 19:15:33.475834 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-install-packages
169 19:15:33.476371 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-installed-packages
170 19:15:33.476847 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-os-build
171 19:15:33.477322 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-probe-channel
172 19:15:33.477793 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-probe-ip
173 19:15:33.478260 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-target-ip
174 19:15:33.478732 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-target-mac
175 19:15:33.479208 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-target-storage
176 19:15:33.479691 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-test-case
177 19:15:33.480193 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-test-event
178 19:15:33.480673 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-test-feedback
179 19:15:33.481146 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-test-raise
180 19:15:33.481614 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-test-reference
181 19:15:33.482214 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-test-runner
182 19:15:33.482730 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-test-set
183 19:15:33.483204 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-test-shell
184 19:15:33.483700 Updating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-install-packages (oe)
185 19:15:33.484331 Updating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/bin/lava-installed-packages (oe)
186 19:15:33.484793 Creating /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/environment
187 19:15:33.485162 LAVA metadata
188 19:15:33.485423 - LAVA_JOB_ID=941864
189 19:15:33.485638 - LAVA_DISPATCHER_IP=192.168.6.2
190 19:15:33.485988 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 19:15:33.486933 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 19:15:33.487278 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 19:15:33.487491 skipped lava-vland-overlay
194 19:15:33.487731 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 19:15:33.488027 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 19:15:33.488248 skipped lava-multinode-overlay
197 19:15:33.488489 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 19:15:33.488740 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 19:15:33.488992 Loading test definitions
200 19:15:33.489268 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 19:15:33.489486 Using /lava-941864 at stage 0
202 19:15:33.490664 uuid=941864_1.6.2.4.1 testdef=None
203 19:15:33.490971 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 19:15:33.491235 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 19:15:33.492973 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 19:15:33.493777 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 19:15:33.495887 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 19:15:33.496741 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 19:15:33.498773 runner path: /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/0/tests/0_v4l2-decoder-conformance-h265 test_uuid 941864_1.6.2.4.1
212 19:15:33.499327 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 19:15:33.500142 Creating lava-test-runner.conf files
215 19:15:33.500346 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/941864/lava-overlay-wa26z9z9/lava-941864/0 for stage 0
216 19:15:33.500675 - 0_v4l2-decoder-conformance-h265
217 19:15:33.501012 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 19:15:33.501282 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 19:15:33.522555 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 19:15:33.522910 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 19:15:33.523167 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 19:15:33.523430 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 19:15:33.523690 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 19:15:34.135538 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 19:15:34.136009 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
226 19:15:34.136289 extracting modules file /var/lib/lava/dispatcher/tmp/941864/tftp-deploy-ydf8efhn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/941864/extract-nfsrootfs-_2v4cjao
227 19:15:35.475763 extracting modules file /var/lib/lava/dispatcher/tmp/941864/tftp-deploy-ydf8efhn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/941864/extract-overlay-ramdisk-q8ca_b09/ramdisk
228 19:15:36.849812 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 19:15:36.850300 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 19:15:36.850602 [common] Applying overlay to NFS
231 19:15:36.850837 [common] Applying overlay /var/lib/lava/dispatcher/tmp/941864/compress-overlay-_w8nl_rw/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/941864/extract-nfsrootfs-_2v4cjao
232 19:15:36.880012 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 19:15:36.880395 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
234 19:15:36.880691 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
235 19:15:36.880934 Converting downloaded kernel to a uImage
236 19:15:36.881259 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/941864/tftp-deploy-ydf8efhn/kernel/Image /var/lib/lava/dispatcher/tmp/941864/tftp-deploy-ydf8efhn/kernel/uImage
237 19:15:37.346369 output: Image Name:
238 19:15:37.346803 output: Created: Tue Nov 5 19:15:36 2024
239 19:15:37.347035 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 19:15:37.347255 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 19:15:37.347469 output: Load Address: 01080000
242 19:15:37.347679 output: Entry Point: 01080000
243 19:15:37.347886 output:
244 19:15:37.348297 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 19:15:37.348594 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 19:15:37.348882 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 19:15:37.349158 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 19:15:37.349436 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 19:15:37.349714 Building ramdisk /var/lib/lava/dispatcher/tmp/941864/extract-overlay-ramdisk-q8ca_b09/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/941864/extract-overlay-ramdisk-q8ca_b09/ramdisk
250 19:15:39.498259 >> 166780 blocks
251 19:15:48.392128 Adding RAMdisk u-boot header.
252 19:15:48.392830 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/941864/extract-overlay-ramdisk-q8ca_b09/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/941864/extract-overlay-ramdisk-q8ca_b09/ramdisk.cpio.gz.uboot
253 19:15:48.658843 output: Image Name:
254 19:15:48.659272 output: Created: Tue Nov 5 19:15:48 2024
255 19:15:48.659762 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 19:15:48.660248 output: Data Size: 23431445 Bytes = 22882.27 KiB = 22.35 MiB
257 19:15:48.660688 output: Load Address: 00000000
258 19:15:48.661096 output: Entry Point: 00000000
259 19:15:48.661499 output:
260 19:15:48.662593 rename /var/lib/lava/dispatcher/tmp/941864/extract-overlay-ramdisk-q8ca_b09/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/941864/tftp-deploy-ydf8efhn/ramdisk/ramdisk.cpio.gz.uboot
261 19:15:48.663319 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
262 19:15:48.663875 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
263 19:15:48.664452 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
264 19:15:48.664934 No LXC device requested
265 19:15:48.665451 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 19:15:48.665973 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
267 19:15:48.666481 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 19:15:48.666899 Checking files for TFTP limit of 4294967296 bytes.
269 19:15:48.669614 end: 1 tftp-deploy (duration 00:01:04) [common]
270 19:15:48.670195 start: 2 uboot-action (timeout 00:05:00) [common]
271 19:15:48.670732 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 19:15:48.671240 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 19:15:48.671754 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 19:15:48.672326 Using kernel file from prepare-kernel: 941864/tftp-deploy-ydf8efhn/kernel/uImage
275 19:15:48.672970 substitutions:
276 19:15:48.673385 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 19:15:48.673789 - {DTB_ADDR}: 0x01070000
278 19:15:48.674194 - {DTB}: 941864/tftp-deploy-ydf8efhn/dtb/meson-g12b-a311d-libretech-cc.dtb
279 19:15:48.674592 - {INITRD}: 941864/tftp-deploy-ydf8efhn/ramdisk/ramdisk.cpio.gz.uboot
280 19:15:48.674992 - {KERNEL_ADDR}: 0x01080000
281 19:15:48.675386 - {KERNEL}: 941864/tftp-deploy-ydf8efhn/kernel/uImage
282 19:15:48.675782 - {LAVA_MAC}: None
283 19:15:48.676254 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/941864/extract-nfsrootfs-_2v4cjao
284 19:15:48.676666 - {NFS_SERVER_IP}: 192.168.6.2
285 19:15:48.677063 - {PRESEED_CONFIG}: None
286 19:15:48.677460 - {PRESEED_LOCAL}: None
287 19:15:48.677856 - {RAMDISK_ADDR}: 0x08000000
288 19:15:48.678243 - {RAMDISK}: 941864/tftp-deploy-ydf8efhn/ramdisk/ramdisk.cpio.gz.uboot
289 19:15:48.678632 - {ROOT_PART}: None
290 19:15:48.679023 - {ROOT}: None
291 19:15:48.679407 - {SERVER_IP}: 192.168.6.2
292 19:15:48.679797 - {TEE_ADDR}: 0x83000000
293 19:15:48.680219 - {TEE}: None
294 19:15:48.680612 Parsed boot commands:
295 19:15:48.680993 - setenv autoload no
296 19:15:48.681383 - setenv initrd_high 0xffffffff
297 19:15:48.681770 - setenv fdt_high 0xffffffff
298 19:15:48.682155 - dhcp
299 19:15:48.682542 - setenv serverip 192.168.6.2
300 19:15:48.682929 - tftpboot 0x01080000 941864/tftp-deploy-ydf8efhn/kernel/uImage
301 19:15:48.683316 - tftpboot 0x08000000 941864/tftp-deploy-ydf8efhn/ramdisk/ramdisk.cpio.gz.uboot
302 19:15:48.683704 - tftpboot 0x01070000 941864/tftp-deploy-ydf8efhn/dtb/meson-g12b-a311d-libretech-cc.dtb
303 19:15:48.684144 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/941864/extract-nfsrootfs-_2v4cjao,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 19:15:48.684553 - bootm 0x01080000 0x08000000 0x01070000
305 19:15:48.685063 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 19:15:48.686562 start: 2.3 connect-device (timeout 00:05:00) [common]
308 19:15:48.686992 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 19:15:48.701253 Setting prompt string to ['lava-test: # ']
310 19:15:48.702788 end: 2.3 connect-device (duration 00:00:00) [common]
311 19:15:48.703449 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 19:15:48.704062 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 19:15:48.704735 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 19:15:48.705893 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 19:15:48.742084 >> OK - accepted request
316 19:15:48.744469 Returned 0 in 0 seconds
317 19:15:48.845611 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 19:15:48.847330 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 19:15:48.847911 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 19:15:48.848511 Setting prompt string to ['Hit any key to stop autoboot']
322 19:15:48.848993 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 19:15:48.850569 Trying 192.168.56.21...
324 19:15:48.851068 Connected to conserv1.
325 19:15:48.851502 Escape character is '^]'.
326 19:15:48.851924
327 19:15:48.852385 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 19:15:48.852826
329 19:16:00.330582 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 19:16:00.331218 bl2_stage_init 0x01
331 19:16:00.331683 bl2_stage_init 0x81
332 19:16:00.336195 hw id: 0x0000 - pwm id 0x01
333 19:16:00.336698 bl2_stage_init 0xc1
334 19:16:00.337152 bl2_stage_init 0x02
335 19:16:00.337592
336 19:16:00.341781 L0:00000000
337 19:16:00.342286 L1:20000703
338 19:16:00.342721 L2:00008067
339 19:16:00.343162 L3:14000000
340 19:16:00.347378 B2:00402000
341 19:16:00.347860 B1:e0f83180
342 19:16:00.348339
343 19:16:00.348774 TE: 58167
344 19:16:00.349205
345 19:16:00.352956 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 19:16:00.353444
347 19:16:00.353883 Board ID = 1
348 19:16:00.358530 Set A53 clk to 24M
349 19:16:00.359016 Set A73 clk to 24M
350 19:16:00.359449 Set clk81 to 24M
351 19:16:00.364176 A53 clk: 1200 MHz
352 19:16:00.364654 A73 clk: 1200 MHz
353 19:16:00.365088 CLK81: 166.6M
354 19:16:00.365513 smccc: 00012abe
355 19:16:00.369759 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 19:16:00.375405 board id: 1
357 19:16:00.381086 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 19:16:00.391907 fw parse done
359 19:16:00.397869 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 19:16:00.440489 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 19:16:00.451419 PIEI prepare done
362 19:16:00.451904 fastboot data load
363 19:16:00.452382 fastboot data verify
364 19:16:00.457127 verify result: 266
365 19:16:00.462630 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 19:16:00.463105 LPDDR4 probe
367 19:16:00.463538 ddr clk to 1584MHz
368 19:16:00.470587 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 19:16:00.507907
370 19:16:00.508427 dmc_version 0001
371 19:16:00.514555 Check phy result
372 19:16:00.520475 INFO : End of CA training
373 19:16:00.520953 INFO : End of initialization
374 19:16:00.526059 INFO : Training has run successfully!
375 19:16:00.526537 Check phy result
376 19:16:00.531633 INFO : End of initialization
377 19:16:00.532149 INFO : End of read enable training
378 19:16:00.537242 INFO : End of fine write leveling
379 19:16:00.542869 INFO : End of Write leveling coarse delay
380 19:16:00.543348 INFO : Training has run successfully!
381 19:16:00.543783 Check phy result
382 19:16:00.548435 INFO : End of initialization
383 19:16:00.548920 INFO : End of read dq deskew training
384 19:16:00.553994 INFO : End of MPR read delay center optimization
385 19:16:00.559591 INFO : End of write delay center optimization
386 19:16:00.565209 INFO : End of read delay center optimization
387 19:16:00.565734 INFO : End of max read latency training
388 19:16:00.570784 INFO : Training has run successfully!
389 19:16:00.571268 1D training succeed
390 19:16:00.580000 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 19:16:00.627605 Check phy result
392 19:16:00.628203 INFO : End of initialization
393 19:16:00.649336 INFO : End of 2D read delay Voltage center optimization
394 19:16:00.669600 INFO : End of 2D read delay Voltage center optimization
395 19:16:00.721687 INFO : End of 2D write delay Voltage center optimization
396 19:16:00.770929 INFO : End of 2D write delay Voltage center optimization
397 19:16:00.776533 INFO : Training has run successfully!
398 19:16:00.777013
399 19:16:00.777459 channel==0
400 19:16:00.782163 RxClkDly_Margin_A0==88 ps 9
401 19:16:00.782646 TxDqDly_Margin_A0==98 ps 10
402 19:16:00.787771 RxClkDly_Margin_A1==88 ps 9
403 19:16:00.788298 TxDqDly_Margin_A1==98 ps 10
404 19:16:00.788742 TrainedVREFDQ_A0==74
405 19:16:00.793342 TrainedVREFDQ_A1==74
406 19:16:00.793821 VrefDac_Margin_A0==25
407 19:16:00.794255 DeviceVref_Margin_A0==40
408 19:16:00.798932 VrefDac_Margin_A1==25
409 19:16:00.799409 DeviceVref_Margin_A1==40
410 19:16:00.799841
411 19:16:00.800319
412 19:16:00.804529 channel==1
413 19:16:00.805012 RxClkDly_Margin_A0==88 ps 9
414 19:16:00.805448 TxDqDly_Margin_A0==98 ps 10
415 19:16:00.810167 RxClkDly_Margin_A1==98 ps 10
416 19:16:00.810668 TxDqDly_Margin_A1==88 ps 9
417 19:16:00.815719 TrainedVREFDQ_A0==77
418 19:16:00.816236 TrainedVREFDQ_A1==77
419 19:16:00.816676 VrefDac_Margin_A0==22
420 19:16:00.821362 DeviceVref_Margin_A0==37
421 19:16:00.821842 VrefDac_Margin_A1==24
422 19:16:00.826927 DeviceVref_Margin_A1==37
423 19:16:00.827400
424 19:16:00.827835 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 19:16:00.828302
426 19:16:00.860522 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
427 19:16:00.861089 2D training succeed
428 19:16:00.866150 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 19:16:00.871723 auto size-- 65535DDR cs0 size: 2048MB
430 19:16:00.872237 DDR cs1 size: 2048MB
431 19:16:00.877379 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 19:16:00.877855 cs0 DataBus test pass
433 19:16:00.882880 cs1 DataBus test pass
434 19:16:00.883357 cs0 AddrBus test pass
435 19:16:00.883791 cs1 AddrBus test pass
436 19:16:00.884256
437 19:16:00.888551 100bdlr_step_size ps== 420
438 19:16:00.889036 result report
439 19:16:00.894147 boot times 0Enable ddr reg access
440 19:16:00.899589 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 19:16:00.913091 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 19:16:01.486100 0.0;M3 CHK:0;cm4_sp_mode 0
443 19:16:01.486733 MVN_1=0x00000000
444 19:16:01.491513 MVN_2=0x00000000
445 19:16:01.497342 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 19:16:01.497847 OPS=0x10
447 19:16:01.498303 ring efuse init
448 19:16:01.498746 chipver efuse init
449 19:16:01.502916 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 19:16:01.508578 [0.018960 Inits done]
451 19:16:01.509083 secure task start!
452 19:16:01.509535 high task start!
453 19:16:01.513059 low task start!
454 19:16:01.513557 run into bl31
455 19:16:01.519706 NOTICE: BL31: v1.3(release):4fc40b1
456 19:16:01.527583 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 19:16:01.528147 NOTICE: BL31: G12A normal boot!
458 19:16:01.552933 NOTICE: BL31: BL33 decompress pass
459 19:16:01.557750 ERROR: Error initializing runtime service opteed_fast
460 19:16:02.791615
461 19:16:02.792278
462 19:16:02.799935 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 19:16:02.800573
464 19:16:02.801064 Model: Libre Computer AML-A311D-CC Alta
465 19:16:03.008718 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 19:16:03.031870 DRAM: 2 GiB (effective 3.8 GiB)
467 19:16:03.174888 Core: 408 devices, 31 uclasses, devicetree: separate
468 19:16:03.180603 WDT: Not starting watchdog@f0d0
469 19:16:03.212867 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 19:16:03.225279 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 19:16:03.230215 ** Bad device specification mmc 0 **
472 19:16:03.240559 Card did not respond to voltage select! : -110
473 19:16:03.248190 ** Bad device specification mmc 0 **
474 19:16:03.248690 Couldn't find partition mmc 0
475 19:16:03.256468 Card did not respond to voltage select! : -110
476 19:16:03.262066 ** Bad device specification mmc 0 **
477 19:16:03.262566 Couldn't find partition mmc 0
478 19:16:03.267079 Error: could not access storage.
479 19:16:04.531265 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 19:16:04.531875 bl2_stage_init 0x01
481 19:16:04.532403 bl2_stage_init 0x81
482 19:16:04.536904 hw id: 0x0000 - pwm id 0x01
483 19:16:04.537404 bl2_stage_init 0xc1
484 19:16:04.537863 bl2_stage_init 0x02
485 19:16:04.538308
486 19:16:04.542616 L0:00000000
487 19:16:04.543106 L1:20000703
488 19:16:04.543556 L2:00008067
489 19:16:04.544026 L3:14000000
490 19:16:04.548073 B2:00402000
491 19:16:04.548563 B1:e0f83180
492 19:16:04.549011
493 19:16:04.549453 TE: 58159
494 19:16:04.549891
495 19:16:04.553721 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 19:16:04.554215
497 19:16:04.554667 Board ID = 1
498 19:16:04.559353 Set A53 clk to 24M
499 19:16:04.559837 Set A73 clk to 24M
500 19:16:04.560324 Set clk81 to 24M
501 19:16:04.564773 A53 clk: 1200 MHz
502 19:16:04.565261 A73 clk: 1200 MHz
503 19:16:04.565715 CLK81: 166.6M
504 19:16:04.566153 smccc: 00012ab5
505 19:16:04.570416 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 19:16:04.576154 board id: 1
507 19:16:04.581897 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 19:16:04.592498 fw parse done
509 19:16:04.598525 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 19:16:04.640942 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 19:16:04.651840 PIEI prepare done
512 19:16:04.652367 fastboot data load
513 19:16:04.652829 fastboot data verify
514 19:16:04.657522 verify result: 266
515 19:16:04.663282 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 19:16:04.663800 LPDDR4 probe
517 19:16:04.664296 ddr clk to 1584MHz
518 19:16:04.671437 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 19:16:04.708628
520 19:16:04.709194 dmc_version 0001
521 19:16:04.715181 Check phy result
522 19:16:04.721317 INFO : End of CA training
523 19:16:04.721895 INFO : End of initialization
524 19:16:04.726850 INFO : Training has run successfully!
525 19:16:04.727386 Check phy result
526 19:16:04.732577 INFO : End of initialization
527 19:16:04.733129 INFO : End of read enable training
528 19:16:04.737793 INFO : End of fine write leveling
529 19:16:04.743382 INFO : End of Write leveling coarse delay
530 19:16:04.743933 INFO : Training has run successfully!
531 19:16:04.744434 Check phy result
532 19:16:04.748931 INFO : End of initialization
533 19:16:04.749533 INFO : End of read dq deskew training
534 19:16:04.754463 INFO : End of MPR read delay center optimization
535 19:16:04.760051 INFO : End of write delay center optimization
536 19:16:04.765694 INFO : End of read delay center optimization
537 19:16:04.766285 INFO : End of max read latency training
538 19:16:04.771401 INFO : Training has run successfully!
539 19:16:04.772036 1D training succeed
540 19:16:04.780651 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 19:16:04.828169 Check phy result
542 19:16:04.828562 INFO : End of initialization
543 19:16:04.849931 INFO : End of 2D read delay Voltage center optimization
544 19:16:04.870394 INFO : End of 2D read delay Voltage center optimization
545 19:16:04.922242 INFO : End of 2D write delay Voltage center optimization
546 19:16:04.971816 INFO : End of 2D write delay Voltage center optimization
547 19:16:04.986067 INFO : Training has run successfully!
548 19:16:04.986780
549 19:16:04.987286 channel==0
550 19:16:04.987780 RxClkDly_Margin_A0==88 ps 9
551 19:16:04.988322 TxDqDly_Margin_A0==98 ps 10
552 19:16:04.989383 RxClkDly_Margin_A1==88 ps 9
553 19:16:04.989959 TxDqDly_Margin_A1==98 ps 10
554 19:16:04.990429 TrainedVREFDQ_A0==74
555 19:16:04.993849 TrainedVREFDQ_A1==74
556 19:16:04.994628 VrefDac_Margin_A0==25
557 19:16:04.995347 DeviceVref_Margin_A0==40
558 19:16:04.999589 VrefDac_Margin_A1==25
559 19:16:05.000182 DeviceVref_Margin_A1==40
560 19:16:05.000676
561 19:16:05.001107
562 19:16:05.005164 channel==1
563 19:16:05.005712 RxClkDly_Margin_A0==98 ps 10
564 19:16:05.006166 TxDqDly_Margin_A0==88 ps 9
565 19:16:05.010664 RxClkDly_Margin_A1==98 ps 10
566 19:16:05.011189 TxDqDly_Margin_A1==88 ps 9
567 19:16:05.016341 TrainedVREFDQ_A0==76
568 19:16:05.016943 TrainedVREFDQ_A1==77
569 19:16:05.017409 VrefDac_Margin_A0==22
570 19:16:05.021959 DeviceVref_Margin_A0==38
571 19:16:05.022547 VrefDac_Margin_A1==23
572 19:16:05.027569 DeviceVref_Margin_A1==37
573 19:16:05.028200
574 19:16:05.028724 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 19:16:05.029092
576 19:16:05.061186 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
577 19:16:05.062009 2D training succeed
578 19:16:05.066699 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 19:16:05.072349 auto size-- 65535DDR cs0 size: 2048MB
580 19:16:05.072979 DDR cs1 size: 2048MB
581 19:16:05.078018 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 19:16:05.078511 cs0 DataBus test pass
583 19:16:05.083730 cs1 DataBus test pass
584 19:16:05.084489 cs0 AddrBus test pass
585 19:16:05.085039 cs1 AddrBus test pass
586 19:16:05.085547
587 19:16:05.089243 100bdlr_step_size ps== 420
588 19:16:05.089827 result report
589 19:16:05.094666 boot times 0Enable ddr reg access
590 19:16:05.100159 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 19:16:05.113545 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 19:16:05.687877 0.0;M3 CHK:0;cm4_sp_mode 0
593 19:16:05.688610 MVN_1=0x00000000
594 19:16:05.692710 MVN_2=0x00000000
595 19:16:05.698440 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 19:16:05.698995 OPS=0x10
597 19:16:05.699518 ring efuse init
598 19:16:05.700029 chipver efuse init
599 19:16:05.704041 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 19:16:05.709591 [0.018960 Inits done]
601 19:16:05.710092 secure task start!
602 19:16:05.710529 high task start!
603 19:16:05.714171 low task start!
604 19:16:05.714659 run into bl31
605 19:16:05.720835 NOTICE: BL31: v1.3(release):4fc40b1
606 19:16:05.728644 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 19:16:05.729136 NOTICE: BL31: G12A normal boot!
608 19:16:05.754277 NOTICE: BL31: BL33 decompress pass
609 19:16:05.759727 ERROR: Error initializing runtime service opteed_fast
610 19:16:06.992680
611 19:16:06.993375
612 19:16:07.000974 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 19:16:07.001544
614 19:16:07.002045 Model: Libre Computer AML-A311D-CC Alta
615 19:16:07.209511 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 19:16:07.232752 DRAM: 2 GiB (effective 3.8 GiB)
617 19:16:07.375806 Core: 408 devices, 31 uclasses, devicetree: separate
618 19:16:07.381613 WDT: Not starting watchdog@f0d0
619 19:16:07.413875 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 19:16:07.426325 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 19:16:07.431305 ** Bad device specification mmc 0 **
622 19:16:07.441754 Card did not respond to voltage select! : -110
623 19:16:07.449334 ** Bad device specification mmc 0 **
624 19:16:07.449845 Couldn't find partition mmc 0
625 19:16:07.457701 Card did not respond to voltage select! : -110
626 19:16:07.463160 ** Bad device specification mmc 0 **
627 19:16:07.463664 Couldn't find partition mmc 0
628 19:16:07.468216 Error: could not access storage.
629 19:16:07.810725 Net: eth0: ethernet@ff3f0000
630 19:16:07.811335 starting USB...
631 19:16:08.062537 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 19:16:08.063108 Starting the controller
633 19:16:08.069417 USB XHCI 1.10
634 19:16:09.641388 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 19:16:09.642059 bl2_stage_init 0x01
636 19:16:09.642534 bl2_stage_init 0x81
637 19:16:09.646916 hw id: 0x0000 - pwm id 0x01
638 19:16:09.647448 bl2_stage_init 0xc1
639 19:16:09.648013 bl2_stage_init 0x02
640 19:16:09.648549
641 19:16:09.652495 L0:00000000
642 19:16:09.653029 L1:20000703
643 19:16:09.653519 L2:00008067
644 19:16:09.653991 L3:14000000
645 19:16:09.658343 B2:00402000
646 19:16:09.658873 B1:e0f83180
647 19:16:09.659367
648 19:16:09.659845 TE: 58124
649 19:16:09.660357
650 19:16:09.663647 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 19:16:09.664182
652 19:16:09.664676 Board ID = 1
653 19:16:09.669347 Set A53 clk to 24M
654 19:16:09.669876 Set A73 clk to 24M
655 19:16:09.670311 Set clk81 to 24M
656 19:16:09.674894 A53 clk: 1200 MHz
657 19:16:09.675398 A73 clk: 1200 MHz
658 19:16:09.675973 CLK81: 166.6M
659 19:16:09.676438 smccc: 00012a92
660 19:16:09.680553 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 19:16:09.686054 board id: 1
662 19:16:09.692023 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 19:16:09.702772 fw parse done
664 19:16:09.708658 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 19:16:09.751054 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 19:16:09.761958 PIEI prepare done
667 19:16:09.762414 fastboot data load
668 19:16:09.762820 fastboot data verify
669 19:16:09.767705 verify result: 266
670 19:16:09.773271 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 19:16:09.773748 LPDDR4 probe
672 19:16:09.774151 ddr clk to 1584MHz
673 19:16:09.781233 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 19:16:09.818565
675 19:16:09.819090 dmc_version 0001
676 19:16:09.825200 Check phy result
677 19:16:09.831048 INFO : End of CA training
678 19:16:09.831524 INFO : End of initialization
679 19:16:09.836649 INFO : Training has run successfully!
680 19:16:09.837126 Check phy result
681 19:16:09.842227 INFO : End of initialization
682 19:16:09.842702 INFO : End of read enable training
683 19:16:09.845520 INFO : End of fine write leveling
684 19:16:09.851103 INFO : End of Write leveling coarse delay
685 19:16:09.856671 INFO : Training has run successfully!
686 19:16:09.857142 Check phy result
687 19:16:09.857544 INFO : End of initialization
688 19:16:09.862344 INFO : End of read dq deskew training
689 19:16:09.867879 INFO : End of MPR read delay center optimization
690 19:16:09.868405 INFO : End of write delay center optimization
691 19:16:09.873451 INFO : End of read delay center optimization
692 19:16:09.879066 INFO : End of max read latency training
693 19:16:09.879543 INFO : Training has run successfully!
694 19:16:09.884681 1D training succeed
695 19:16:09.890700 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 19:16:09.938217 Check phy result
697 19:16:09.938710 INFO : End of initialization
698 19:16:09.960802 INFO : End of 2D read delay Voltage center optimization
699 19:16:09.981019 INFO : End of 2D read delay Voltage center optimization
700 19:16:10.033143 INFO : End of 2D write delay Voltage center optimization
701 19:16:10.082442 INFO : End of 2D write delay Voltage center optimization
702 19:16:10.088068 INFO : Training has run successfully!
703 19:16:10.088558
704 19:16:10.089007 channel==0
705 19:16:10.093654 RxClkDly_Margin_A0==88 ps 9
706 19:16:10.094190 TxDqDly_Margin_A0==98 ps 10
707 19:16:10.099224 RxClkDly_Margin_A1==88 ps 9
708 19:16:10.099714 TxDqDly_Margin_A1==98 ps 10
709 19:16:10.100162 TrainedVREFDQ_A0==74
710 19:16:10.104829 TrainedVREFDQ_A1==75
711 19:16:10.105314 VrefDac_Margin_A0==24
712 19:16:10.105711 DeviceVref_Margin_A0==40
713 19:16:10.110424 VrefDac_Margin_A1==24
714 19:16:10.110907 DeviceVref_Margin_A1==39
715 19:16:10.111300
716 19:16:10.111691
717 19:16:10.116051 channel==1
718 19:16:10.116542 RxClkDly_Margin_A0==98 ps 10
719 19:16:10.116942 TxDqDly_Margin_A0==88 ps 9
720 19:16:10.121591 RxClkDly_Margin_A1==98 ps 10
721 19:16:10.122079 TxDqDly_Margin_A1==88 ps 9
722 19:16:10.127239 TrainedVREFDQ_A0==77
723 19:16:10.127730 TrainedVREFDQ_A1==77
724 19:16:10.128173 VrefDac_Margin_A0==22
725 19:16:10.132830 DeviceVref_Margin_A0==37
726 19:16:10.133317 VrefDac_Margin_A1==22
727 19:16:10.138417 DeviceVref_Margin_A1==37
728 19:16:10.138966
729 19:16:10.139372 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 19:16:10.139763
731 19:16:10.171959 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
732 19:16:10.172524 2D training succeed
733 19:16:10.177688 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 19:16:10.183190 auto size-- 65535DDR cs0 size: 2048MB
735 19:16:10.183689 DDR cs1 size: 2048MB
736 19:16:10.188787 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 19:16:10.189290 cs0 DataBus test pass
738 19:16:10.194466 cs1 DataBus test pass
739 19:16:10.194992 cs0 AddrBus test pass
740 19:16:10.195390 cs1 AddrBus test pass
741 19:16:10.195781
742 19:16:10.200065 100bdlr_step_size ps== 420
743 19:16:10.200564 result report
744 19:16:10.205620 boot times 0Enable ddr reg access
745 19:16:10.210970 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 19:16:10.224415 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 19:16:10.798028 0.0;M3 CHK:0;cm4_sp_mode 0
748 19:16:10.798661 MVN_1=0x00000000
749 19:16:10.803502 MVN_2=0x00000000
750 19:16:10.809567 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 19:16:10.810176 OPS=0x10
752 19:16:10.810654 ring efuse init
753 19:16:10.811262 chipver efuse init
754 19:16:10.815001 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 19:16:10.820562 [0.018961 Inits done]
756 19:16:10.821257 secure task start!
757 19:16:10.821806 high task start!
758 19:16:10.825190 low task start!
759 19:16:10.825796 run into bl31
760 19:16:10.831949 NOTICE: BL31: v1.3(release):4fc40b1
761 19:16:10.839779 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 19:16:10.840428 NOTICE: BL31: G12A normal boot!
763 19:16:10.865050 NOTICE: BL31: BL33 decompress pass
764 19:16:10.870688 ERROR: Error initializing runtime service opteed_fast
765 19:16:12.103675
766 19:16:12.104407
767 19:16:12.111901 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 19:16:12.112398
769 19:16:12.112825 Model: Libre Computer AML-A311D-CC Alta
770 19:16:12.320919 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 19:16:12.343681 DRAM: 2 GiB (effective 3.8 GiB)
772 19:16:12.486754 Core: 408 devices, 31 uclasses, devicetree: separate
773 19:16:12.492540 WDT: Not starting watchdog@f0d0
774 19:16:12.524810 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 19:16:12.537257 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 19:16:12.542217 ** Bad device specification mmc 0 **
777 19:16:12.552598 Card did not respond to voltage select! : -110
778 19:16:12.560205 ** Bad device specification mmc 0 **
779 19:16:12.560678 Couldn't find partition mmc 0
780 19:16:12.568501 Card did not respond to voltage select! : -110
781 19:16:12.574114 ** Bad device specification mmc 0 **
782 19:16:12.574580 Couldn't find partition mmc 0
783 19:16:12.579055 Error: could not access storage.
784 19:16:12.921550 Net: eth0: ethernet@ff3f0000
785 19:16:12.922115 starting USB...
786 19:16:13.173394 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 19:16:13.174349 Starting the controller
788 19:16:13.180369 USB XHCI 1.10
789 19:16:15.341527 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 19:16:15.342088 bl2_stage_init 0x01
791 19:16:15.342518 bl2_stage_init 0x81
792 19:16:15.347108 hw id: 0x0000 - pwm id 0x01
793 19:16:15.347553 bl2_stage_init 0xc1
794 19:16:15.347961 bl2_stage_init 0x02
795 19:16:15.348441
796 19:16:15.352732 L0:00000000
797 19:16:15.353217 L1:20000703
798 19:16:15.353649 L2:00008067
799 19:16:15.354061 L3:14000000
800 19:16:15.358188 B2:00402000
801 19:16:15.358634 B1:e0f83180
802 19:16:15.359043
803 19:16:15.359453 TE: 58167
804 19:16:15.359860
805 19:16:15.363912 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 19:16:15.364385
807 19:16:15.364796 Board ID = 1
808 19:16:15.369478 Set A53 clk to 24M
809 19:16:15.369917 Set A73 clk to 24M
810 19:16:15.370324 Set clk81 to 24M
811 19:16:15.375012 A53 clk: 1200 MHz
812 19:16:15.375447 A73 clk: 1200 MHz
813 19:16:15.375858 CLK81: 166.6M
814 19:16:15.376301 smccc: 00012abe
815 19:16:15.380604 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 19:16:15.386283 board id: 1
817 19:16:15.392166 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 19:16:15.402820 fw parse done
819 19:16:15.408721 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 19:16:15.451257 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 19:16:15.462163 PIEI prepare done
822 19:16:15.462602 fastboot data load
823 19:16:15.463012 fastboot data verify
824 19:16:15.467820 verify result: 266
825 19:16:15.473402 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 19:16:15.473836 LPDDR4 probe
827 19:16:15.474239 ddr clk to 1584MHz
828 19:16:15.481440 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 19:16:15.518849
830 19:16:15.519296 dmc_version 0001
831 19:16:15.525342 Check phy result
832 19:16:15.531197 INFO : End of CA training
833 19:16:15.531633 INFO : End of initialization
834 19:16:15.536791 INFO : Training has run successfully!
835 19:16:15.537228 Check phy result
836 19:16:15.542432 INFO : End of initialization
837 19:16:15.542867 INFO : End of read enable training
838 19:16:15.548052 INFO : End of fine write leveling
839 19:16:15.553583 INFO : End of Write leveling coarse delay
840 19:16:15.554020 INFO : Training has run successfully!
841 19:16:15.554425 Check phy result
842 19:16:15.559212 INFO : End of initialization
843 19:16:15.559641 INFO : End of read dq deskew training
844 19:16:15.564784 INFO : End of MPR read delay center optimization
845 19:16:15.570366 INFO : End of write delay center optimization
846 19:16:15.576009 INFO : End of read delay center optimization
847 19:16:15.576452 INFO : End of max read latency training
848 19:16:15.581619 INFO : Training has run successfully!
849 19:16:15.582050 1D training succeed
850 19:16:15.590818 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 19:16:15.638357 Check phy result
852 19:16:15.638796 INFO : End of initialization
853 19:16:15.660140 INFO : End of 2D read delay Voltage center optimization
854 19:16:15.680321 INFO : End of 2D read delay Voltage center optimization
855 19:16:15.732377 INFO : End of 2D write delay Voltage center optimization
856 19:16:15.781698 INFO : End of 2D write delay Voltage center optimization
857 19:16:15.787323 INFO : Training has run successfully!
858 19:16:15.787809
859 19:16:15.788293 channel==0
860 19:16:15.793011 RxClkDly_Margin_A0==88 ps 9
861 19:16:15.793461 TxDqDly_Margin_A0==98 ps 10
862 19:16:15.798488 RxClkDly_Margin_A1==88 ps 9
863 19:16:15.798928 TxDqDly_Margin_A1==98 ps 10
864 19:16:15.799360 TrainedVREFDQ_A0==74
865 19:16:15.804151 TrainedVREFDQ_A1==74
866 19:16:15.804630 VrefDac_Margin_A0==25
867 19:16:15.805046 DeviceVref_Margin_A0==40
868 19:16:15.809732 VrefDac_Margin_A1==25
869 19:16:15.810197 DeviceVref_Margin_A1==40
870 19:16:15.810587
871 19:16:15.810971
872 19:16:15.815279 channel==1
873 19:16:15.815700 RxClkDly_Margin_A0==98 ps 10
874 19:16:15.816121 TxDqDly_Margin_A0==88 ps 9
875 19:16:15.820896 RxClkDly_Margin_A1==98 ps 10
876 19:16:15.821312 TxDqDly_Margin_A1==88 ps 9
877 19:16:15.826539 TrainedVREFDQ_A0==76
878 19:16:15.826957 TrainedVREFDQ_A1==77
879 19:16:15.827348 VrefDac_Margin_A0==22
880 19:16:15.832178 DeviceVref_Margin_A0==38
881 19:16:15.832598 VrefDac_Margin_A1==22
882 19:16:15.837702 DeviceVref_Margin_A1==37
883 19:16:15.838122
884 19:16:15.838509 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 19:16:15.838891
886 19:16:15.871293 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000017 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
887 19:16:15.871741 2D training succeed
888 19:16:15.876890 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 19:16:15.882532 auto size-- 65535DDR cs0 size: 2048MB
890 19:16:15.882949 DDR cs1 size: 2048MB
891 19:16:15.888191 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 19:16:15.888664 cs0 DataBus test pass
893 19:16:15.893701 cs1 DataBus test pass
894 19:16:15.894131 cs0 AddrBus test pass
895 19:16:15.894522 cs1 AddrBus test pass
896 19:16:15.894906
897 19:16:15.899316 100bdlr_step_size ps== 420
898 19:16:15.899749 result report
899 19:16:15.904890 boot times 0Enable ddr reg access
900 19:16:15.910266 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 19:16:15.923739 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 19:16:16.497553 0.0;M3 CHK:0;cm4_sp_mode 0
903 19:16:16.498158 MVN_1=0x00000000
904 19:16:16.502945 MVN_2=0x00000000
905 19:16:16.508656 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 19:16:16.509098 OPS=0x10
907 19:16:16.509516 ring efuse init
908 19:16:16.509921 chipver efuse init
909 19:16:16.514274 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 19:16:16.519861 [0.018960 Inits done]
911 19:16:16.520343 secure task start!
912 19:16:16.520748 high task start!
913 19:16:16.524423 low task start!
914 19:16:16.524853 run into bl31
915 19:16:16.531098 NOTICE: BL31: v1.3(release):4fc40b1
916 19:16:16.538923 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 19:16:16.539363 NOTICE: BL31: G12A normal boot!
918 19:16:16.564297 NOTICE: BL31: BL33 decompress pass
919 19:16:16.569961 ERROR: Error initializing runtime service opteed_fast
920 19:16:17.802940
921 19:16:17.803502
922 19:16:17.811241 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 19:16:17.811694
924 19:16:17.812158 Model: Libre Computer AML-A311D-CC Alta
925 19:16:18.019692 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 19:16:18.043080 DRAM: 2 GiB (effective 3.8 GiB)
927 19:16:18.186078 Core: 408 devices, 31 uclasses, devicetree: separate
928 19:16:18.191913 WDT: Not starting watchdog@f0d0
929 19:16:18.224216 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 19:16:18.236702 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 19:16:18.241643 ** Bad device specification mmc 0 **
932 19:16:18.252016 Card did not respond to voltage select! : -110
933 19:16:18.259669 ** Bad device specification mmc 0 **
934 19:16:18.260195 Couldn't find partition mmc 0
935 19:16:18.267932 Card did not respond to voltage select! : -110
936 19:16:18.273488 ** Bad device specification mmc 0 **
937 19:16:18.273961 Couldn't find partition mmc 0
938 19:16:18.278529 Error: could not access storage.
939 19:16:18.621000 Net: eth0: ethernet@ff3f0000
940 19:16:18.621531 starting USB...
941 19:16:18.872841 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 19:16:18.873325 Starting the controller
943 19:16:18.879750 USB XHCI 1.10
944 19:16:20.741003 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 19:16:20.741584 bl2_stage_init 0x01
946 19:16:20.742009 bl2_stage_init 0x81
947 19:16:20.746843 hw id: 0x0000 - pwm id 0x01
948 19:16:20.747311 bl2_stage_init 0xc1
949 19:16:20.747740 bl2_stage_init 0x02
950 19:16:20.748217
951 19:16:20.752300 L0:00000000
952 19:16:20.752756 L1:20000703
953 19:16:20.753162 L2:00008067
954 19:16:20.753586 L3:14000000
955 19:16:20.758042 B2:00402000
956 19:16:20.758500 B1:e0f83180
957 19:16:20.758907
958 19:16:20.759331 TE: 58124
959 19:16:20.759764
960 19:16:20.763483 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 19:16:20.763946
962 19:16:20.764401 Board ID = 1
963 19:16:20.769056 Set A53 clk to 24M
964 19:16:20.769509 Set A73 clk to 24M
965 19:16:20.769930 Set clk81 to 24M
966 19:16:20.774503 A53 clk: 1200 MHz
967 19:16:20.774991 A73 clk: 1200 MHz
968 19:16:20.775434 CLK81: 166.6M
969 19:16:20.775856 smccc: 00012a92
970 19:16:20.780138 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 19:16:20.785763 board id: 1
972 19:16:20.791637 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 19:16:20.802238 fw parse done
974 19:16:20.808218 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 19:16:20.850894 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 19:16:20.861766 PIEI prepare done
977 19:16:20.862223 fastboot data load
978 19:16:20.862636 fastboot data verify
979 19:16:20.867467 verify result: 266
980 19:16:20.873150 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 19:16:20.873618 LPDDR4 probe
982 19:16:20.874010 ddr clk to 1584MHz
983 19:16:20.881029 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 19:16:20.918272
985 19:16:20.918742 dmc_version 0001
986 19:16:20.925033 Check phy result
987 19:16:20.930938 INFO : End of CA training
988 19:16:20.931423 INFO : End of initialization
989 19:16:20.936463 INFO : Training has run successfully!
990 19:16:20.936927 Check phy result
991 19:16:20.942046 INFO : End of initialization
992 19:16:20.942512 INFO : End of read enable training
993 19:16:20.945352 INFO : End of fine write leveling
994 19:16:20.950954 INFO : End of Write leveling coarse delay
995 19:16:20.956577 INFO : Training has run successfully!
996 19:16:20.957084 Check phy result
997 19:16:20.957544 INFO : End of initialization
998 19:16:20.962203 INFO : End of read dq deskew training
999 19:16:20.967755 INFO : End of MPR read delay center optimization
1000 19:16:20.968303 INFO : End of write delay center optimization
1001 19:16:20.973437 INFO : End of read delay center optimization
1002 19:16:20.978913 INFO : End of max read latency training
1003 19:16:20.979367 INFO : Training has run successfully!
1004 19:16:20.984464 1D training succeed
1005 19:16:20.990382 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 19:16:21.038027 Check phy result
1007 19:16:21.038511 INFO : End of initialization
1008 19:16:21.060592 INFO : End of 2D read delay Voltage center optimization
1009 19:16:21.080050 INFO : End of 2D read delay Voltage center optimization
1010 19:16:21.132871 INFO : End of 2D write delay Voltage center optimization
1011 19:16:21.182362 INFO : End of 2D write delay Voltage center optimization
1012 19:16:21.187874 INFO : Training has run successfully!
1013 19:16:21.188475
1014 19:16:21.188966 channel==0
1015 19:16:21.193583 RxClkDly_Margin_A0==88 ps 9
1016 19:16:21.194097 TxDqDly_Margin_A0==98 ps 10
1017 19:16:21.199132 RxClkDly_Margin_A1==88 ps 9
1018 19:16:21.199643 TxDqDly_Margin_A1==98 ps 10
1019 19:16:21.200146 TrainedVREFDQ_A0==74
1020 19:16:21.204710 TrainedVREFDQ_A1==74
1021 19:16:21.205232 VrefDac_Margin_A0==25
1022 19:16:21.205690 DeviceVref_Margin_A0==40
1023 19:16:21.210425 VrefDac_Margin_A1==24
1024 19:16:21.210937 DeviceVref_Margin_A1==40
1025 19:16:21.211392
1026 19:16:21.211839
1027 19:16:21.215872 channel==1
1028 19:16:21.216412 RxClkDly_Margin_A0==98 ps 10
1029 19:16:21.216867 TxDqDly_Margin_A0==88 ps 9
1030 19:16:21.221570 RxClkDly_Margin_A1==98 ps 10
1031 19:16:21.222080 TxDqDly_Margin_A1==88 ps 9
1032 19:16:21.227108 TrainedVREFDQ_A0==77
1033 19:16:21.227623 TrainedVREFDQ_A1==77
1034 19:16:21.228119 VrefDac_Margin_A0==22
1035 19:16:21.232766 DeviceVref_Margin_A0==37
1036 19:16:21.233276 VrefDac_Margin_A1==22
1037 19:16:21.238419 DeviceVref_Margin_A1==37
1038 19:16:21.238927
1039 19:16:21.239381 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 19:16:21.239826
1041 19:16:21.271843 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000016 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1042 19:16:21.272421 2D training succeed
1043 19:16:21.277615 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 19:16:21.283062 auto size-- 65535DDR cs0 size: 2048MB
1045 19:16:21.283575 DDR cs1 size: 2048MB
1046 19:16:21.288679 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 19:16:21.289191 cs0 DataBus test pass
1048 19:16:21.294201 cs1 DataBus test pass
1049 19:16:21.294708 cs0 AddrBus test pass
1050 19:16:21.295167 cs1 AddrBus test pass
1051 19:16:21.295616
1052 19:16:21.299802 100bdlr_step_size ps== 420
1053 19:16:21.300357 result report
1054 19:16:21.305449 boot times 0Enable ddr reg access
1055 19:16:21.310827 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 19:16:21.324374 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 19:16:21.897885 0.0;M3 CHK:0;cm4_sp_mode 0
1058 19:16:21.898542 MVN_1=0x00000000
1059 19:16:21.903505 MVN_2=0x00000000
1060 19:16:21.909104 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 19:16:21.909752 OPS=0x10
1062 19:16:21.910323 ring efuse init
1063 19:16:21.910849 chipver efuse init
1064 19:16:21.917273 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 19:16:21.917915 [0.018961 Inits done]
1066 19:16:21.924856 secure task start!
1067 19:16:21.925490 high task start!
1068 19:16:21.926076 low task start!
1069 19:16:21.926638 run into bl31
1070 19:16:21.931479 NOTICE: BL31: v1.3(release):4fc40b1
1071 19:16:21.939345 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 19:16:21.940010 NOTICE: BL31: G12A normal boot!
1073 19:16:21.965305 NOTICE: BL31: BL33 decompress pass
1074 19:16:21.970866 ERROR: Error initializing runtime service opteed_fast
1075 19:16:23.203841
1076 19:16:23.204342
1077 19:16:23.212277 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 19:16:23.212673
1079 19:16:23.212919 Model: Libre Computer AML-A311D-CC Alta
1080 19:16:23.420664 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 19:16:23.443892 DRAM: 2 GiB (effective 3.8 GiB)
1082 19:16:23.587067 Core: 408 devices, 31 uclasses, devicetree: separate
1083 19:16:23.592802 WDT: Not starting watchdog@f0d0
1084 19:16:23.625138 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 19:16:23.637588 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 19:16:23.642586 ** Bad device specification mmc 0 **
1087 19:16:23.652924 Card did not respond to voltage select! : -110
1088 19:16:23.660569 ** Bad device specification mmc 0 **
1089 19:16:23.661035 Couldn't find partition mmc 0
1090 19:16:23.668817 Card did not respond to voltage select! : -110
1091 19:16:23.674383 ** Bad device specification mmc 0 **
1092 19:16:23.674914 Couldn't find partition mmc 0
1093 19:16:23.679476 Error: could not access storage.
1094 19:16:24.021989 Net: eth0: ethernet@ff3f0000
1095 19:16:24.022582 starting USB...
1096 19:16:24.273782 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 19:16:24.274374 Starting the controller
1098 19:16:24.280676 USB XHCI 1.10
1099 19:16:25.837843 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 19:16:25.846203 scanning usb for storage devices... 0 Storage Device(s) found
1102 19:16:25.897957 Hit any key to stop autoboot: 1
1103 19:16:25.898951 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 19:16:25.899678 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 19:16:25.900260 Setting prompt string to ['=>']
1106 19:16:25.900783 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 19:16:25.913707 0
1108 19:16:25.914752 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 19:16:25.915349 Sending with 10 millisecond of delay
1111 19:16:27.051422 => setenv autoload no
1112 19:16:27.062402 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 19:16:27.068071 setenv autoload no
1114 19:16:27.069146 Sending with 10 millisecond of delay
1116 19:16:28.867506 => setenv initrd_high 0xffffffff
1117 19:16:28.878486 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 19:16:28.879810 setenv initrd_high 0xffffffff
1119 19:16:28.880716 Sending with 10 millisecond of delay
1121 19:16:30.500258 => setenv fdt_high 0xffffffff
1122 19:16:30.511398 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 19:16:30.512597 setenv fdt_high 0xffffffff
1124 19:16:30.513380 Sending with 10 millisecond of delay
1126 19:16:30.805949 => dhcp
1127 19:16:30.817044 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 19:16:30.818004 dhcp
1129 19:16:30.818756 Speed: 1000, full duplex
1130 19:16:30.819303 BOOTP broadcast 1
1131 19:16:30.829074 DHCP client bound to address 192.168.6.27 (13 ms)
1132 19:16:30.830041 Sending with 10 millisecond of delay
1134 19:16:32.511004 => setenv serverip 192.168.6.2
1135 19:16:32.521880 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 19:16:32.522894 setenv serverip 192.168.6.2
1137 19:16:32.524414 Sending with 10 millisecond of delay
1139 19:16:36.263402 => tftpboot 0x01080000 941864/tftp-deploy-ydf8efhn/kernel/uImage
1140 19:16:36.274356 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1141 19:16:36.275331 tftpboot 0x01080000 941864/tftp-deploy-ydf8efhn/kernel/uImage
1142 19:16:36.275856 Speed: 1000, full duplex
1143 19:16:36.276383 Using ethernet@ff3f0000 device
1144 19:16:36.277195 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 19:16:36.282608 Filename '941864/tftp-deploy-ydf8efhn/kernel/uImage'.
1146 19:16:36.286700 Load address: 0x1080000
1147 19:16:37.213051 Loading: *############### UDP wrong checksum 000000ff 0000c3a5
1148 19:16:37.273137 # UDP wrong checksum 000000ff 00004f98
1149 19:16:39.228142 ################################## 43.6 MiB
1150 19:16:39.228751 14.8 MiB/s
1151 19:16:39.229194 done
1152 19:16:39.231665 Bytes transferred = 45713984 (2b98a40 hex)
1153 19:16:39.232488 Sending with 10 millisecond of delay
1155 19:16:43.922364 => tftpboot 0x08000000 941864/tftp-deploy-ydf8efhn/ramdisk/ramdisk.cpio.gz.uboot
1156 19:16:43.932936 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1157 19:16:43.933509 tftpboot 0x08000000 941864/tftp-deploy-ydf8efhn/ramdisk/ramdisk.cpio.gz.uboot
1158 19:16:43.933781 Speed: 1000, full duplex
1159 19:16:43.934018 Using ethernet@ff3f0000 device
1160 19:16:43.935667 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1161 19:16:43.944321 Filename '941864/tftp-deploy-ydf8efhn/ramdisk/ramdisk.cpio.gz.uboot'.
1162 19:16:43.944653 Load address: 0x8000000
1163 19:16:50.519029 Loading: *#####################T ############################ UDP wrong checksum 00000005 00005417
1164 19:16:55.519897 T UDP wrong checksum 00000005 00005417
1165 19:17:05.521477 T T UDP wrong checksum 00000005 00005417
1166 19:17:21.536198 T T T UDP wrong checksum 000000ff 00008aba
1167 19:17:21.576120 UDP wrong checksum 000000ff 000026ad
1168 19:17:25.522093 UDP wrong checksum 00000005 00005417
1169 19:17:40.529963 T T T
1170 19:17:40.530410 Retry count exceeded; starting again
1172 19:17:40.531308 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1175 19:17:40.532340 end: 2.4 uboot-commands (duration 00:01:52) [common]
1177 19:17:40.533145 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1179 19:17:40.534222 end: 2 uboot-action (duration 00:01:52) [common]
1181 19:17:40.535901 Cleaning after the job
1182 19:17:40.536547 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/941864/tftp-deploy-ydf8efhn/ramdisk
1183 19:17:40.538258 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/941864/tftp-deploy-ydf8efhn/kernel
1184 19:17:40.588824 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/941864/tftp-deploy-ydf8efhn/dtb
1185 19:17:40.590536 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/941864/tftp-deploy-ydf8efhn/nfsrootfs
1186 19:17:40.911367 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/941864/tftp-deploy-ydf8efhn/modules
1187 19:17:40.933947 start: 4.1 power-off (timeout 00:00:30) [common]
1188 19:17:40.934655 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1189 19:17:40.975652 >> OK - accepted request
1190 19:17:40.977676 Returned 0 in 0 seconds
1191 19:17:41.078411 end: 4.1 power-off (duration 00:00:00) [common]
1193 19:17:41.079352 start: 4.2 read-feedback (timeout 00:10:00) [common]
1194 19:17:41.080014 Listened to connection for namespace 'common' for up to 1s
1195 19:17:42.080932 Finalising connection for namespace 'common'
1196 19:17:42.081387 Disconnecting from shell: Finalise
1197 19:17:42.081641 =>
1198 19:17:42.182265 end: 4.2 read-feedback (duration 00:00:01) [common]
1199 19:17:42.182642 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/941864
1200 19:17:44.797553 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/941864
1201 19:17:44.798162 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.