Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 17:10:29.709888 lava-dispatcher, installed at version: 2024.01
2 17:10:29.710702 start: 0 validate
3 17:10:29.711181 Start time: 2024-11-04 17:10:29.711150+00:00 (UTC)
4 17:10:29.711719 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 17:10:29.712294 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 17:10:29.754361 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 17:10:29.754945 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-regmap%2Ffor-next%2Fv6.12-rc3-7-g953e549471ca%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 17:10:29.783723 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 17:10:29.784598 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-regmap%2Ffor-next%2Fv6.12-rc3-7-g953e549471ca%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 17:10:29.815328 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 17:10:29.815865 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 17:10:29.849648 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 17:10:29.850129 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-regmap%2Ffor-next%2Fv6.12-rc3-7-g953e549471ca%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 17:10:29.898542 validate duration: 0.19
16 17:10:29.899511 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 17:10:29.899925 start: 1.1 download-retry (timeout 00:10:00) [common]
18 17:10:29.900319 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 17:10:29.900926 Not decompressing ramdisk as can be used compressed.
20 17:10:29.901366 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 17:10:29.901628 saving as /var/lib/lava/dispatcher/tmp/935269/tftp-deploy-9x3d1pu7/ramdisk/initrd.cpio.gz
22 17:10:29.901904 total size: 4775763 (4 MB)
23 17:10:29.935265 progress 0 % (0 MB)
24 17:10:29.939375 progress 5 % (0 MB)
25 17:10:29.942733 progress 10 % (0 MB)
26 17:10:29.946105 progress 15 % (0 MB)
27 17:10:29.949872 progress 20 % (0 MB)
28 17:10:29.953191 progress 25 % (1 MB)
29 17:10:29.956451 progress 30 % (1 MB)
30 17:10:29.960172 progress 35 % (1 MB)
31 17:10:29.963349 progress 40 % (1 MB)
32 17:10:29.966497 progress 45 % (2 MB)
33 17:10:29.969683 progress 50 % (2 MB)
34 17:10:29.973358 progress 55 % (2 MB)
35 17:10:29.976624 progress 60 % (2 MB)
36 17:10:29.980018 progress 65 % (2 MB)
37 17:10:29.983788 progress 70 % (3 MB)
38 17:10:29.987059 progress 75 % (3 MB)
39 17:10:29.990154 progress 80 % (3 MB)
40 17:10:29.993238 progress 85 % (3 MB)
41 17:10:29.996720 progress 90 % (4 MB)
42 17:10:29.999806 progress 95 % (4 MB)
43 17:10:30.003041 progress 100 % (4 MB)
44 17:10:30.003828 4 MB downloaded in 0.10 s (44.70 MB/s)
45 17:10:30.004447 end: 1.1.1 http-download (duration 00:00:00) [common]
47 17:10:30.005473 end: 1.1 download-retry (duration 00:00:00) [common]
48 17:10:30.005820 start: 1.2 download-retry (timeout 00:10:00) [common]
49 17:10:30.006156 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 17:10:30.006691 downloading http://storage.kernelci.org/broonie-regmap/for-next/v6.12-rc3-7-g953e549471ca/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 17:10:30.006965 saving as /var/lib/lava/dispatcher/tmp/935269/tftp-deploy-9x3d1pu7/kernel/zImage
52 17:10:30.007190 total size: 11444736 (10 MB)
53 17:10:30.007504 No compression specified
54 17:10:30.047578 progress 0 % (0 MB)
55 17:10:30.055687 progress 5 % (0 MB)
56 17:10:30.064410 progress 10 % (1 MB)
57 17:10:30.073485 progress 15 % (1 MB)
58 17:10:30.081935 progress 20 % (2 MB)
59 17:10:30.089910 progress 25 % (2 MB)
60 17:10:30.101123 progress 30 % (3 MB)
61 17:10:30.109318 progress 35 % (3 MB)
62 17:10:30.117231 progress 40 % (4 MB)
63 17:10:30.125405 progress 45 % (4 MB)
64 17:10:30.133561 progress 50 % (5 MB)
65 17:10:30.142247 progress 55 % (6 MB)
66 17:10:30.149913 progress 60 % (6 MB)
67 17:10:30.158196 progress 65 % (7 MB)
68 17:10:30.165818 progress 70 % (7 MB)
69 17:10:30.173392 progress 75 % (8 MB)
70 17:10:30.182806 progress 80 % (8 MB)
71 17:10:30.192779 progress 85 % (9 MB)
72 17:10:30.201760 progress 90 % (9 MB)
73 17:10:30.210353 progress 95 % (10 MB)
74 17:10:30.219603 progress 100 % (10 MB)
75 17:10:30.220406 10 MB downloaded in 0.21 s (51.19 MB/s)
76 17:10:30.221109 end: 1.2.1 http-download (duration 00:00:00) [common]
78 17:10:30.222316 end: 1.2 download-retry (duration 00:00:00) [common]
79 17:10:30.222752 start: 1.3 download-retry (timeout 00:10:00) [common]
80 17:10:30.223170 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 17:10:30.223847 downloading http://storage.kernelci.org/broonie-regmap/for-next/v6.12-rc3-7-g953e549471ca/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 17:10:30.224322 saving as /var/lib/lava/dispatcher/tmp/935269/tftp-deploy-9x3d1pu7/dtb/am335x-boneblack.dtb
83 17:10:30.224607 total size: 70568 (0 MB)
84 17:10:30.224894 No compression specified
85 17:10:30.271589 progress 46 % (0 MB)
86 17:10:30.272529 progress 92 % (0 MB)
87 17:10:30.273247 progress 100 % (0 MB)
88 17:10:30.273680 0 MB downloaded in 0.05 s (1.37 MB/s)
89 17:10:30.274164 end: 1.3.1 http-download (duration 00:00:00) [common]
91 17:10:30.274981 end: 1.3 download-retry (duration 00:00:00) [common]
92 17:10:30.275246 start: 1.4 download-retry (timeout 00:10:00) [common]
93 17:10:30.275509 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 17:10:30.276035 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 17:10:30.276317 saving as /var/lib/lava/dispatcher/tmp/935269/tftp-deploy-9x3d1pu7/nfsrootfs/full.rootfs.tar
96 17:10:30.276526 total size: 117747780 (112 MB)
97 17:10:30.276740 Using unxz to decompress xz
98 17:10:30.314460 progress 0 % (0 MB)
99 17:10:31.061589 progress 5 % (5 MB)
100 17:10:31.873041 progress 10 % (11 MB)
101 17:10:32.647932 progress 15 % (16 MB)
102 17:10:33.384655 progress 20 % (22 MB)
103 17:10:33.966053 progress 25 % (28 MB)
104 17:10:34.769318 progress 30 % (33 MB)
105 17:10:35.580617 progress 35 % (39 MB)
106 17:10:35.925176 progress 40 % (44 MB)
107 17:10:36.271870 progress 45 % (50 MB)
108 17:10:36.934511 progress 50 % (56 MB)
109 17:10:37.746236 progress 55 % (61 MB)
110 17:10:38.472028 progress 60 % (67 MB)
111 17:10:39.183852 progress 65 % (73 MB)
112 17:10:39.938437 progress 70 % (78 MB)
113 17:10:40.690824 progress 75 % (84 MB)
114 17:10:41.415706 progress 80 % (89 MB)
115 17:10:42.119316 progress 85 % (95 MB)
116 17:10:42.933536 progress 90 % (101 MB)
117 17:10:43.728391 progress 95 % (106 MB)
118 17:10:44.549844 progress 100 % (112 MB)
119 17:10:44.562285 112 MB downloaded in 14.29 s (7.86 MB/s)
120 17:10:44.562897 end: 1.4.1 http-download (duration 00:00:14) [common]
122 17:10:44.563797 end: 1.4 download-retry (duration 00:00:14) [common]
123 17:10:44.564155 start: 1.5 download-retry (timeout 00:09:45) [common]
124 17:10:44.564460 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 17:10:44.564983 downloading http://storage.kernelci.org/broonie-regmap/for-next/v6.12-rc3-7-g953e549471ca/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 17:10:44.565250 saving as /var/lib/lava/dispatcher/tmp/935269/tftp-deploy-9x3d1pu7/modules/modules.tar
127 17:10:44.565469 total size: 6607888 (6 MB)
128 17:10:44.565696 Using unxz to decompress xz
129 17:10:44.604912 progress 0 % (0 MB)
130 17:10:44.641108 progress 5 % (0 MB)
131 17:10:44.685236 progress 10 % (0 MB)
132 17:10:44.729388 progress 15 % (0 MB)
133 17:10:44.774076 progress 20 % (1 MB)
134 17:10:44.821024 progress 25 % (1 MB)
135 17:10:44.864179 progress 30 % (1 MB)
136 17:10:44.907021 progress 35 % (2 MB)
137 17:10:44.951277 progress 40 % (2 MB)
138 17:10:44.995076 progress 45 % (2 MB)
139 17:10:45.039000 progress 50 % (3 MB)
140 17:10:45.081915 progress 55 % (3 MB)
141 17:10:45.127482 progress 60 % (3 MB)
142 17:10:45.174506 progress 65 % (4 MB)
143 17:10:45.218105 progress 70 % (4 MB)
144 17:10:45.264313 progress 75 % (4 MB)
145 17:10:45.307329 progress 80 % (5 MB)
146 17:10:45.350132 progress 85 % (5 MB)
147 17:10:45.393681 progress 90 % (5 MB)
148 17:10:45.437319 progress 95 % (6 MB)
149 17:10:45.481659 progress 100 % (6 MB)
150 17:10:45.494587 6 MB downloaded in 0.93 s (6.78 MB/s)
151 17:10:45.495190 end: 1.5.1 http-download (duration 00:00:01) [common]
153 17:10:45.496064 end: 1.5 download-retry (duration 00:00:01) [common]
154 17:10:45.496661 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 17:10:45.497231 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 17:11:03.302167 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/935269/extract-nfsrootfs-j5tyg99w
157 17:11:03.302775 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
158 17:11:03.303064 start: 1.6.2 lava-overlay (timeout 00:09:27) [common]
159 17:11:03.303656 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx
160 17:11:03.304121 makedir: /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin
161 17:11:03.304488 makedir: /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/tests
162 17:11:03.304816 makedir: /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/results
163 17:11:03.305149 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-add-keys
164 17:11:03.305682 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-add-sources
165 17:11:03.306247 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-background-process-start
166 17:11:03.306771 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-background-process-stop
167 17:11:03.307318 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-common-functions
168 17:11:03.307828 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-echo-ipv4
169 17:11:03.308354 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-install-packages
170 17:11:03.308843 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-installed-packages
171 17:11:03.309331 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-os-build
172 17:11:03.309830 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-probe-channel
173 17:11:03.310379 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-probe-ip
174 17:11:03.310961 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-target-ip
175 17:11:03.311559 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-target-mac
176 17:11:03.312126 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-target-storage
177 17:11:03.312656 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-test-case
178 17:11:03.313160 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-test-event
179 17:11:03.313652 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-test-feedback
180 17:11:03.314173 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-test-raise
181 17:11:03.314694 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-test-reference
182 17:11:03.315183 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-test-runner
183 17:11:03.315676 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-test-set
184 17:11:03.316216 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-test-shell
185 17:11:03.316808 Updating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-add-keys (debian)
186 17:11:03.317371 Updating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-add-sources (debian)
187 17:11:03.317938 Updating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-install-packages (debian)
188 17:11:03.318484 Updating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-installed-packages (debian)
189 17:11:03.319019 Updating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/bin/lava-os-build (debian)
190 17:11:03.319491 Creating /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/environment
191 17:11:03.319908 LAVA metadata
192 17:11:03.320205 - LAVA_JOB_ID=935269
193 17:11:03.320422 - LAVA_DISPATCHER_IP=192.168.6.2
194 17:11:03.320797 start: 1.6.2.1 ssh-authorize (timeout 00:09:27) [common]
195 17:11:03.321788 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 17:11:03.322108 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:27) [common]
197 17:11:03.322313 skipped lava-vland-overlay
198 17:11:03.322554 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 17:11:03.322808 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:27) [common]
200 17:11:03.323028 skipped lava-multinode-overlay
201 17:11:03.323269 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 17:11:03.323520 start: 1.6.2.4 test-definition (timeout 00:09:27) [common]
203 17:11:03.323771 Loading test definitions
204 17:11:03.324081 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:27) [common]
205 17:11:03.324309 Using /lava-935269 at stage 0
206 17:11:03.325438 uuid=935269_1.6.2.4.1 testdef=None
207 17:11:03.325751 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 17:11:03.326014 start: 1.6.2.4.2 test-overlay (timeout 00:09:27) [common]
209 17:11:03.327736 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 17:11:03.328567 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:27) [common]
212 17:11:03.330592 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 17:11:03.331420 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:27) [common]
215 17:11:03.333370 runner path: /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/0/tests/0_timesync-off test_uuid 935269_1.6.2.4.1
216 17:11:03.333976 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 17:11:03.334806 start: 1.6.2.4.5 git-repo-action (timeout 00:09:27) [common]
219 17:11:03.335050 Using /lava-935269 at stage 0
220 17:11:03.335416 Fetching tests from https://github.com/kernelci/test-definitions.git
221 17:11:03.335707 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/0/tests/1_kselftest-dt'
222 17:11:06.736051 Running '/usr/bin/git checkout kernelci.org
223 17:11:07.182946 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 17:11:07.184434 uuid=935269_1.6.2.4.5 testdef=None
225 17:11:07.184785 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 17:11:07.185551 start: 1.6.2.4.6 test-overlay (timeout 00:09:23) [common]
228 17:11:07.188482 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 17:11:07.189977 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:23) [common]
231 17:11:07.195002 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 17:11:07.195879 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:23) [common]
234 17:11:07.199480 runner path: /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/0/tests/1_kselftest-dt test_uuid 935269_1.6.2.4.5
235 17:11:07.199760 BOARD='beaglebone-black'
236 17:11:07.199974 BRANCH='broonie-regmap'
237 17:11:07.200199 SKIPFILE='/dev/null'
238 17:11:07.200402 SKIP_INSTALL='True'
239 17:11:07.200601 TESTPROG_URL='http://storage.kernelci.org/broonie-regmap/for-next/v6.12-rc3-7-g953e549471ca/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 17:11:07.200829 TST_CASENAME=''
241 17:11:07.201032 TST_CMDFILES='dt'
242 17:11:07.201599 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 17:11:07.202523 Creating lava-test-runner.conf files
245 17:11:07.202783 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/935269/lava-overlay-6cgo87xx/lava-935269/0 for stage 0
246 17:11:07.203222 - 0_timesync-off
247 17:11:07.203526 - 1_kselftest-dt
248 17:11:07.203927 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 17:11:07.204322 start: 1.6.2.5 compress-overlay (timeout 00:09:23) [common]
250 17:11:30.764869 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 17:11:30.765324 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
252 17:11:30.765619 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 17:11:30.765924 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 17:11:30.766216 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
255 17:11:31.128342 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 17:11:31.128830 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
257 17:11:31.129106 extracting modules file /var/lib/lava/dispatcher/tmp/935269/tftp-deploy-9x3d1pu7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/935269/extract-nfsrootfs-j5tyg99w
258 17:11:32.028794 extracting modules file /var/lib/lava/dispatcher/tmp/935269/tftp-deploy-9x3d1pu7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/935269/extract-overlay-ramdisk-sz013tae/ramdisk
259 17:11:32.937888 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 17:11:32.938372 start: 1.6.5 apply-overlay-tftp (timeout 00:08:57) [common]
261 17:11:32.938669 [common] Applying overlay to NFS
262 17:11:32.938887 [common] Applying overlay /var/lib/lava/dispatcher/tmp/935269/compress-overlay-g2e7q_y2/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/935269/extract-nfsrootfs-j5tyg99w
263 17:11:35.684184 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 17:11:35.684637 start: 1.6.6 prepare-kernel (timeout 00:08:54) [common]
265 17:11:35.684913 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:54) [common]
266 17:11:35.685190 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 17:11:35.685441 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 17:11:35.685699 start: 1.6.7 configure-preseed-file (timeout 00:08:54) [common]
269 17:11:35.685947 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 17:11:35.686201 start: 1.6.8 compress-ramdisk (timeout 00:08:54) [common]
271 17:11:35.686450 Building ramdisk /var/lib/lava/dispatcher/tmp/935269/extract-overlay-ramdisk-sz013tae/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/935269/extract-overlay-ramdisk-sz013tae/ramdisk
272 17:11:36.720015 >> 74887 blocks
273 17:11:41.613654 Adding RAMdisk u-boot header.
274 17:11:41.614120 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/935269/extract-overlay-ramdisk-sz013tae/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/935269/extract-overlay-ramdisk-sz013tae/ramdisk.cpio.gz.uboot
275 17:11:41.777090 output: Image Name:
276 17:11:41.777518 output: Created: Mon Nov 4 17:11:41 2024
277 17:11:41.777728 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 17:11:41.777931 output: Data Size: 14792475 Bytes = 14445.78 KiB = 14.11 MiB
279 17:11:41.778133 output: Load Address: 00000000
280 17:11:41.778330 output: Entry Point: 00000000
281 17:11:41.778525 output:
282 17:11:41.779126 rename /var/lib/lava/dispatcher/tmp/935269/extract-overlay-ramdisk-sz013tae/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/935269/tftp-deploy-9x3d1pu7/ramdisk/ramdisk.cpio.gz.uboot
283 17:11:41.779543 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 17:11:41.779827 end: 1.6 prepare-tftp-overlay (duration 00:00:56) [common]
285 17:11:41.780243 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:48) [common]
286 17:11:41.780700 No LXC device requested
287 17:11:41.781186 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 17:11:41.781684 start: 1.8 deploy-device-env (timeout 00:08:48) [common]
289 17:11:41.782163 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 17:11:41.782568 Checking files for TFTP limit of 4294967296 bytes.
291 17:11:41.785213 end: 1 tftp-deploy (duration 00:01:12) [common]
292 17:11:41.785779 start: 2 uboot-action (timeout 00:05:00) [common]
293 17:11:41.786291 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 17:11:41.786778 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 17:11:41.787268 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 17:11:41.788033 substitutions:
297 17:11:41.788452 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 17:11:41.788854 - {DTB_ADDR}: 0x88000000
299 17:11:41.789245 - {DTB}: 935269/tftp-deploy-9x3d1pu7/dtb/am335x-boneblack.dtb
300 17:11:41.789635 - {INITRD}: 935269/tftp-deploy-9x3d1pu7/ramdisk/ramdisk.cpio.gz.uboot
301 17:11:41.790020 - {KERNEL_ADDR}: 0x82000000
302 17:11:41.790401 - {KERNEL}: 935269/tftp-deploy-9x3d1pu7/kernel/zImage
303 17:11:41.790783 - {LAVA_MAC}: None
304 17:11:41.791205 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/935269/extract-nfsrootfs-j5tyg99w
305 17:11:41.791594 - {NFS_SERVER_IP}: 192.168.6.2
306 17:11:41.791976 - {PRESEED_CONFIG}: None
307 17:11:41.792382 - {PRESEED_LOCAL}: None
308 17:11:41.792761 - {RAMDISK_ADDR}: 0x83000000
309 17:11:41.793139 - {RAMDISK}: 935269/tftp-deploy-9x3d1pu7/ramdisk/ramdisk.cpio.gz.uboot
310 17:11:41.793524 - {ROOT_PART}: None
311 17:11:41.793901 - {ROOT}: None
312 17:11:41.794288 - {SERVER_IP}: 192.168.6.2
313 17:11:41.794667 - {TEE_ADDR}: 0x83000000
314 17:11:41.795040 - {TEE}: None
315 17:11:41.795416 Parsed boot commands:
316 17:11:41.795782 - setenv autoload no
317 17:11:41.796257 - setenv initrd_high 0xffffffff
318 17:11:41.796638 - setenv fdt_high 0xffffffff
319 17:11:41.797013 - dhcp
320 17:11:41.797384 - setenv serverip 192.168.6.2
321 17:11:41.797759 - tftp 0x82000000 935269/tftp-deploy-9x3d1pu7/kernel/zImage
322 17:11:41.798136 - tftp 0x83000000 935269/tftp-deploy-9x3d1pu7/ramdisk/ramdisk.cpio.gz.uboot
323 17:11:41.798514 - setenv initrd_size ${filesize}
324 17:11:41.798885 - tftp 0x88000000 935269/tftp-deploy-9x3d1pu7/dtb/am335x-boneblack.dtb
325 17:11:41.799260 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/935269/extract-nfsrootfs-j5tyg99w,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 17:11:41.799650 - bootz 0x82000000 0x83000000 0x88000000
327 17:11:41.800165 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 17:11:41.801626 start: 2.3 connect-device (timeout 00:05:00) [common]
330 17:11:41.802036 [common] connect-device Connecting to device using 'telnet conserv1 3003'
331 17:11:41.816222 Setting prompt string to ['lava-test: # ']
332 17:11:41.817720 end: 2.3 connect-device (duration 00:00:00) [common]
333 17:11:41.818315 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 17:11:41.818842 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 17:11:41.819358 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 17:11:41.820551 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-01'
337 17:11:41.854777 >> OK - accepted request
338 17:11:41.856654 Returned 0 in 0 seconds
339 17:11:41.957745 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 17:11:41.959345 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 17:11:41.959907 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 17:11:41.960490 Setting prompt string to ['Hit any key to stop autoboot']
344 17:11:41.960942 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 17:11:41.962492 Trying 192.168.56.21...
346 17:11:41.962958 Connected to conserv1.
347 17:11:41.963372 Escape character is '^]'.
348 17:11:41.963781
349 17:11:41.964222 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 17:11:41.964627
351 17:11:49.387528
352 17:11:49.387939 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
353 17:11:49.392586 Trying to boot from MMC1
354 17:11:49.964802
355 17:11:49.965423
356 17:11:49.965849 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
357 17:11:49.966261
358 17:11:49.970184 CPU : AM335X-GP rev 2.1
359 17:11:49.970628 Model: TI AM335x BeagleBone Black
360 17:11:49.974325 DRAM: 512 MiB
361 17:11:50.057027 Core: 160 devices, 18 uclasses, devicetree: separate
362 17:11:50.066722 WDT: Started wdt@44e35000 with servicing (60s timeout)
363 17:11:53.435775 7[r[999;999H[6n8NAND:
364 17:11:53.436432 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
365 17:11:53.440937 Trying to boot from MMC1
366 17:11:54.013076
367 17:11:54.013720
368 17:11:54.014211 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
369 17:11:54.014682
370 17:11:54.018523 CPU : AM335X-GP rev 2.1
371 17:11:54.019057 Model: TI AM335x BeagleBone Black
372 17:11:54.022604 DRAM: 512 MiB
373 17:11:54.105416 Core: 160 devices, 18 uclasses, devicetree: separate
374 17:11:54.115114 WDT: Started wdt@44e35000 with servicing (60s timeout)
375 17:11:56.136266 7[r[999;999H[6n8NAND:
376 17:11:56.136888 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
377 17:11:56.140522 Trying to boot from MMC1
378 17:11:56.713944
379 17:11:56.714550
380 17:11:56.715015 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
381 17:11:56.715467
382 17:11:56.719542 CPU : AM335X-GP rev 2.1
383 17:11:56.720132 Model: TI AM335x BeagleBone Black
384 17:11:56.723710 DRAM: 512 MiB
385 17:11:56.806425 Core: 160 devices, 18 uclasses, devicetree: separate
386 17:11:56.815965 WDT: Started wdt@44e35000 with servicing (60s timeout)
387 17:11:57.321066 7[r[999;999H[6n8NAND: 0 MiB
388 17:11:57.331300 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
389 17:11:57.404216 Loading Environment from FAT... Unable to use mmc 0:1...
390 17:11:57.425132 <ethaddr> not set. Validating first E-fuse MAC
391 17:11:57.456012 Net: eth2: ethernet@4a100000, eth3: usb_ether
393 17:11:57.514682 Hit any key to stop autoboot: 2
394 17:11:57.515599 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
395 17:11:57.516362 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
396 17:11:57.516919 Setting prompt string to ['=>']
397 17:11:57.517463 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
398 17:11:57.524499 0
399 17:11:57.525457 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
400 17:11:57.526004 Sending with 10 millisecond of delay
402 17:11:58.660746 => setenv autoload no
403 17:11:58.671605 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
404 17:11:58.677059 setenv autoload no
405 17:11:58.677835 Sending with 10 millisecond of delay
407 17:12:00.474582 => setenv initrd_high 0xffffffff
408 17:12:00.485422 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
409 17:12:00.486351 setenv initrd_high 0xffffffff
410 17:12:00.487121 Sending with 10 millisecond of delay
412 17:12:02.103410 => setenv fdt_high 0xffffffff
413 17:12:02.114269 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
414 17:12:02.115186 setenv fdt_high 0xffffffff
415 17:12:02.115955 Sending with 10 millisecond of delay
417 17:12:02.407884 => dhcp
418 17:12:02.418718 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
419 17:12:02.419671 dhcp
420 17:12:02.420231 link up on port 0, speed 100, full duplex
421 17:12:02.420694 BOOTP broadcast 1
422 17:12:02.458224 DHCP client bound to address 192.168.6.12 (33 ms)
423 17:12:02.459055 Sending with 10 millisecond of delay
425 17:12:04.135751 => setenv serverip 192.168.6.2
426 17:12:04.146641 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
427 17:12:04.147612 setenv serverip 192.168.6.2
428 17:12:04.148451 Sending with 10 millisecond of delay
430 17:12:07.632944 => tftp 0x82000000 935269/tftp-deploy-9x3d1pu7/kernel/zImage
431 17:12:07.643781 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
432 17:12:07.644985 tftp 0x82000000 935269/tftp-deploy-9x3d1pu7/kernel/zImage
433 17:12:07.645510 link up on port 0, speed 100, full duplex
434 17:12:07.648632 Using ethernet@4a100000 device
435 17:12:07.654320 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
436 17:12:07.654804 Filename '935269/tftp-deploy-9x3d1pu7/kernel/zImage'.
437 17:12:07.661475 Load address: 0x82000000
438 17:12:09.959609 Loading: *################################################## 10.9 MiB
439 17:12:09.960028 4.8 MiB/s
440 17:12:09.960266 done
441 17:12:09.963806 Bytes transferred = 11444736 (aea200 hex)
442 17:12:09.964390 Sending with 10 millisecond of delay
444 17:12:14.409411 => tftp 0x83000000 935269/tftp-deploy-9x3d1pu7/ramdisk/ramdisk.cpio.gz.uboot
445 17:12:14.420176 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
446 17:12:14.420997 tftp 0x83000000 935269/tftp-deploy-9x3d1pu7/ramdisk/ramdisk.cpio.gz.uboot
447 17:12:14.421442 link up on port 0, speed 100, full duplex
448 17:12:14.425248 Using ethernet@4a100000 device
449 17:12:14.430810 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
450 17:12:14.439281 Filename '935269/tftp-deploy-9x3d1pu7/ramdisk/ramdisk.cpio.gz.uboot'.
451 17:12:14.439761 Load address: 0x83000000
452 17:12:17.388246 Loading: *################################################## 14.1 MiB
453 17:12:17.388668 4.8 MiB/s
454 17:12:17.388888 done
455 17:12:17.392578 Bytes transferred = 14792539 (e1b75b hex)
456 17:12:17.393113 Sending with 10 millisecond of delay
458 17:12:19.249676 => setenv initrd_size ${filesize}
459 17:12:19.260271 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
460 17:12:19.260795 setenv initrd_size ${filesize}
461 17:12:19.261272 Sending with 10 millisecond of delay
463 17:12:23.407033 => tftp 0x88000000 935269/tftp-deploy-9x3d1pu7/dtb/am335x-boneblack.dtb
464 17:12:23.417840 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
465 17:12:23.418709 tftp 0x88000000 935269/tftp-deploy-9x3d1pu7/dtb/am335x-boneblack.dtb
466 17:12:23.419133 link up on port 0, speed 100, full duplex
467 17:12:23.422614 Using ethernet@4a100000 device
468 17:12:23.428222 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
469 17:12:23.439170 Filename '935269/tftp-deploy-9x3d1pu7/dtb/am335x-boneblack.dtb'.
470 17:12:23.439643 Load address: 0x88000000
471 17:12:23.450254 Loading: *################################################## 68.9 KiB
472 17:12:23.450717 4.5 MiB/s
473 17:12:23.458755 done
474 17:12:23.459207 Bytes transferred = 70568 (113a8 hex)
475 17:12:23.459866 Sending with 10 millisecond of delay
477 17:12:36.641860 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/935269/extract-nfsrootfs-j5tyg99w,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 17:12:36.653798 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
479 17:12:36.654683 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/935269/extract-nfsrootfs-j5tyg99w,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 17:12:36.655423 Sending with 10 millisecond of delay
482 17:12:38.995446 => bootz 0x82000000 0x83000000 0x88000000
483 17:12:39.006324 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 17:12:39.006910 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
485 17:12:39.007893 bootz 0x82000000 0x83000000 0x88000000
486 17:12:39.008406 Kernel image @ 0x82000000 [ 0x000000 - 0xaea200 ]
487 17:12:39.008940 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 17:12:39.014167 Image Name:
489 17:12:39.014675 Created: 2024-11-04 17:11:41 UTC
490 17:12:39.023021 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 17:12:39.023555 Data Size: 14792475 Bytes = 14.1 MiB
492 17:12:39.031499 Load Address: 00000000
493 17:12:39.032067 Entry Point: 00000000
494 17:12:39.199955 Verifying Checksum ... OK
495 17:12:39.200613 ## Flattened Device Tree blob at 88000000
496 17:12:39.206440 Booting using the fdt blob at 0x88000000
497 17:12:39.211467 Using Device Tree in place at 88000000, end 880143a7
498 17:12:39.224950
499 17:12:39.225515 Starting kernel ...
500 17:12:39.225953
501 17:12:39.226844 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 17:12:39.227443 start: 2.4.4 auto-login-action (timeout 00:04:03) [common]
503 17:12:39.227899 Setting prompt string to ['Linux version [0-9]']
504 17:12:39.228389 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
505 17:12:39.228855 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
506 17:12:40.068240 [ 0.000000] Booting Linux on physical CPU 0x0
507 17:12:40.074204 start: 2.4.4.1 login-action (timeout 00:04:02) [common]
508 17:12:40.074940 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 17:12:40.075518 Setting prompt string to []
510 17:12:40.076142 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 17:12:40.076688 Using line separator: #'\n'#
512 17:12:40.077160 No login prompt set.
513 17:12:40.077672 Parsing kernel messages
514 17:12:40.078178 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 17:12:40.079099 [login-action] Waiting for messages, (timeout 00:04:02)
516 17:12:40.079620 Waiting using forced prompt support (timeout 00:02:01)
517 17:12:40.090773 [ 0.000000] Linux version 6.12.0-rc3 (KernelCI@build-j361843-arm-gcc-12-multi-v7-defconfig-8q874) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Mon Nov 4 16:41:30 UTC 2024
518 17:12:40.096430 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 17:12:40.102303 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 17:12:40.113583 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 17:12:40.119423 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 17:12:40.125118 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 17:12:40.125608 [ 0.000000] Memory policy: Data cache writeback
524 17:12:40.131641 [ 0.000000] efi: UEFI not found.
525 17:12:40.140550 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 17:12:40.141057 [ 0.000000] Zone ranges:
527 17:12:40.146443 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 17:12:40.151810 [ 0.000000] Normal empty
529 17:12:40.157724 [ 0.000000] HighMem empty
530 17:12:40.158222 [ 0.000000] Movable zone start for each node
531 17:12:40.163377 [ 0.000000] Early memory node ranges
532 17:12:40.169088 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 17:12:40.176788 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 17:12:40.202147 [ 0.000000] CPU: All CPU(s) started in SVC mode.
535 17:12:40.207750 [ 0.000000] AM335X ES2.1 (sgx neon)
536 17:12:40.219405 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
537 17:12:40.237152 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/935269/extract-nfsrootfs-j5tyg99w,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
538 17:12:40.248713 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
539 17:12:40.254468 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
540 17:12:40.260285 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
541 17:12:40.270276 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
542 17:12:40.299282 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
543 17:12:40.305327 <6>[ 0.000000] trace event string verifier disabled
544 17:12:40.305865 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
545 17:12:40.310954 <6>[ 0.000000] rcu: RCU event tracing is enabled.
546 17:12:40.322379 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
547 17:12:40.328141 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
548 17:12:40.335462 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
549 17:12:40.350383 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
550 17:12:40.367530 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
551 17:12:40.374344 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
552 17:12:40.465973 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
553 17:12:40.477478 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
554 17:12:40.484246 <6>[ 0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
555 17:12:40.497284 <6>[ 0.019153] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
556 17:12:40.504493 <6>[ 0.033949] Console: colour dummy device 80x30
557 17:12:40.510733 Matched prompt #6: WARNING:
558 17:12:40.511287 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
559 17:12:40.516109 <3>[ 0.038846] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
560 17:12:40.521835 <3>[ 0.045916] This ensures that you still see kernel messages. Please
561 17:12:40.525017 <3>[ 0.052641] update your kernel commandline.
562 17:12:40.565730 <6>[ 0.057254] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
563 17:12:40.571463 <6>[ 0.096161] CPU: Testing write buffer coherency: ok
564 17:12:40.574365 <6>[ 0.101528] CPU0: Spectre v2: using BPIALL workaround
565 17:12:40.580308 <6>[ 0.106995] pid_max: default: 32768 minimum: 301
566 17:12:40.586027 <6>[ 0.112184] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 17:12:40.598594 <6>[ 0.120003] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 17:12:40.602761 <6>[ 0.129347] CPU0: thread -1, cpu 0, socket -1, mpidr 0
569 17:12:40.668383 <6>[ 0.189543] Setting up static identity map for 0x80300000 - 0x803000ac
570 17:12:40.674179 <6>[ 0.199114] rcu: Hierarchical SRCU implementation.
571 17:12:40.677839 <6>[ 0.204400] rcu: Max phase no-delay instances is 1000.
572 17:12:40.686317 <6>[ 0.215378] EFI services will not be available.
573 17:12:40.692104 <6>[ 0.220732] smp: Bringing up secondary CPUs ...
574 17:12:40.697884 <6>[ 0.225703] smp: Brought up 1 node, 1 CPU
575 17:12:40.706053 <6>[ 0.230190] SMP: Total of 1 processors activated (996.14 BogoMIPS).
576 17:12:40.711968 <6>[ 0.236913] CPU: All CPU(s) started in SVC mode.
577 17:12:40.724197 <6>[ 0.242118] Memory: 405996K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
578 17:12:40.729866 <6>[ 0.258382] devtmpfs: initialized
579 17:12:40.752476 <6>[ 0.275816] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
580 17:12:40.764022 <6>[ 0.284419] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
581 17:12:40.769911 <6>[ 0.294862] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
582 17:12:40.780752 <6>[ 0.307147] pinctrl core: initialized pinctrl subsystem
583 17:12:40.790020 <6>[ 0.317769] DMI not present or invalid.
584 17:12:40.798424 <6>[ 0.323616] NET: Registered PF_NETLINK/PF_ROUTE protocol family
585 17:12:40.807705 <6>[ 0.332555] DMA: preallocated 256 KiB pool for atomic coherent allocations
586 17:12:40.822787 <6>[ 0.343976] thermal_sys: Registered thermal governor 'step_wise'
587 17:12:40.823306 <6>[ 0.344145] cpuidle: using governor menu
588 17:12:40.850253 <6>[ 0.379689] No ATAGs?
589 17:12:40.856400 <6>[ 0.382330] hw-breakpoint: debug architecture 0x4 unsupported.
590 17:12:40.866502 <6>[ 0.394171] Serial: AMBA PL011 UART driver
591 17:12:40.896173 <6>[ 0.425295] iommu: Default domain type: Translated
592 17:12:40.905092 <6>[ 0.430645] iommu: DMA domain TLB invalidation policy: strict mode
593 17:12:40.931955 <5>[ 0.460674] SCSI subsystem initialized
594 17:12:40.937806 <6>[ 0.465561] usbcore: registered new interface driver usbfs
595 17:12:40.943563 <6>[ 0.471615] usbcore: registered new interface driver hub
596 17:12:40.952323 <6>[ 0.477402] usbcore: registered new device driver usb
597 17:12:40.958041 <6>[ 0.483914] pps_core: LinuxPPS API ver. 1 registered
598 17:12:40.963960 <6>[ 0.489303] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
599 17:12:40.969852 <6>[ 0.499031] PTP clock support registered
600 17:12:40.975176 <6>[ 0.503493] EDAC MC: Ver: 3.0.0
601 17:12:41.026654 <6>[ 0.553334] scmi_core: SCMI protocol bus registered
602 17:12:41.051162 <6>[ 0.579815] vgaarb: loaded
603 17:12:41.057245 <6>[ 0.583587] clocksource: Switched to clocksource dmtimer
604 17:12:41.081514 <6>[ 0.610540] NET: Registered PF_INET protocol family
605 17:12:41.094035 <6>[ 0.616227] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
606 17:12:41.099886 <6>[ 0.625063] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
607 17:12:41.111390 <6>[ 0.633996] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
608 17:12:41.117122 <6>[ 0.642239] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
609 17:12:41.128735 <6>[ 0.650525] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
610 17:12:41.134505 <6>[ 0.658242] TCP: Hash tables configured (established 4096 bind 4096)
611 17:12:41.140535 <6>[ 0.665171] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
612 17:12:41.146169 <6>[ 0.672179] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
613 17:12:41.153840 <6>[ 0.679786] NET: Registered PF_UNIX/PF_LOCAL protocol family
614 17:12:41.239629 <6>[ 0.763345] RPC: Registered named UNIX socket transport module.
615 17:12:41.240295 <6>[ 0.769778] RPC: Registered udp transport module.
616 17:12:41.245453 <6>[ 0.774906] RPC: Registered tcp transport module.
617 17:12:41.253966 <6>[ 0.780009] RPC: Registered tcp-with-tls transport module.
618 17:12:41.259755 <6>[ 0.785930] RPC: Registered tcp NFSv4.1 backchannel transport module.
619 17:12:41.267036 <6>[ 0.792837] PCI: CLS 0 bytes, default 64
620 17:12:41.269381 <5>[ 0.798653] Initialise system trusted keyrings
621 17:12:41.292514 <6>[ 0.818737] Trying to unpack rootfs image as initramfs...
622 17:12:41.371440 <6>[ 0.894556] workingset: timestamp_bits=30 max_order=17 bucket_order=0
623 17:12:41.376201 <6>[ 0.902062] squashfs: version 4.0 (2009/01/31) Phillip Lougher
624 17:12:41.415074 <5>[ 0.944362] NFS: Registering the id_resolver key type
625 17:12:41.420887 <5>[ 0.949960] Key type id_resolver registered
626 17:12:41.426642 <5>[ 0.954631] Key type id_legacy registered
627 17:12:41.435050 <6>[ 0.959068] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
628 17:12:41.442015 <6>[ 0.966272] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
629 17:12:41.511100 <5>[ 1.040415] Key type asymmetric registered
630 17:12:41.516920 <5>[ 1.044992] Asymmetric key parser 'x509' registered
631 17:12:41.525304 <6>[ 1.050415] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
632 17:12:41.531119 <6>[ 1.058335] io scheduler mq-deadline registered
633 17:12:41.539914 <6>[ 1.063269] io scheduler kyber registered
634 17:12:41.540500 <6>[ 1.067758] io scheduler bfq registered
635 17:12:41.644343 <6>[ 1.170056] ledtrig-cpu: registered to indicate activity on CPUs
636 17:12:41.929960 <6>[ 1.455366] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
637 17:12:41.959546 <6>[ 1.488570] msm_serial: driver initialized
638 17:12:41.965617 <6>[ 1.493351] SuperH (H)SCI(F) driver initialized
639 17:12:41.971730 <6>[ 1.498698] STMicroelectronics ASC driver initialized
640 17:12:41.976827 <6>[ 1.504375] STM32 USART driver initialized
641 17:12:42.091472 <6>[ 1.619998] brd: module loaded
642 17:12:42.139503 <6>[ 1.668025] loop: module loaded
643 17:12:42.163192 <6>[ 1.691461] CAN device driver interface
644 17:12:42.169697 <6>[ 1.696739] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
645 17:12:42.175420 <6>[ 1.703780] e1000e: Intel(R) PRO/1000 Network Driver
646 17:12:42.181130 <6>[ 1.709166] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
647 17:12:42.186848 <6>[ 1.715618] igb: Intel(R) Gigabit Ethernet Network Driver
648 17:12:42.195305 <6>[ 1.721439] igb: Copyright (c) 2007-2014 Intel Corporation.
649 17:12:42.206952 <6>[ 1.730590] pegasus: Pegasus/Pegasus II USB Ethernet driver
650 17:12:42.212752 <6>[ 1.736742] usbcore: registered new interface driver pegasus
651 17:12:42.215606 <6>[ 1.742868] usbcore: registered new interface driver asix
652 17:12:42.221328 <6>[ 1.748750] usbcore: registered new interface driver ax88179_178a
653 17:12:42.227051 <6>[ 1.755340] usbcore: registered new interface driver cdc_ether
654 17:12:42.232757 <6>[ 1.761638] usbcore: registered new interface driver smsc75xx
655 17:12:42.244384 <6>[ 1.767878] usbcore: registered new interface driver smsc95xx
656 17:12:42.250052 <6>[ 1.774118] usbcore: registered new interface driver net1080
657 17:12:42.256167 <6>[ 1.780239] usbcore: registered new interface driver cdc_subset
658 17:12:42.261712 <6>[ 1.786649] usbcore: registered new interface driver zaurus
659 17:12:42.266713 <6>[ 1.792692] usbcore: registered new interface driver cdc_ncm
660 17:12:42.276376 <6>[ 1.802011] usbcore: registered new interface driver usb-storage
661 17:12:42.558819 <6>[ 2.086261] i2c_dev: i2c /dev entries driver
662 17:12:42.628868 <5>[ 2.150152] cpuidle: enable-method property 'ti,am3352' found operations
663 17:12:42.634751 <6>[ 2.159764] sdhci: Secure Digital Host Controller Interface driver
664 17:12:42.642151 <6>[ 2.166544] sdhci: Copyright(c) Pierre Ossman
665 17:12:42.649386 <6>[ 2.172950] Synopsys Designware Multimedia Card Interface Driver
666 17:12:42.655016 <6>[ 2.180915] sdhci-pltfm: SDHCI platform and OF driver helper
667 17:12:42.783037 <6>[ 2.304954] usbcore: registered new interface driver usbhid
668 17:12:42.783687 <6>[ 2.310999] usbhid: USB HID core driver
669 17:12:42.813603 <6>[ 2.340309] NET: Registered PF_INET6 protocol family
670 17:12:42.845762 <6>[ 2.375245] Segment Routing with IPv6
671 17:12:42.851806 <6>[ 2.379392] In-situ OAM (IOAM) with IPv6
672 17:12:42.858412 <6>[ 2.383925] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
673 17:12:42.865971 <6>[ 2.391156] NET: Registered PF_PACKET protocol family
674 17:12:42.871830 <6>[ 2.396738] can: controller area network core
675 17:12:42.872410 <6>[ 2.401562] NET: Registered PF_CAN protocol family
676 17:12:42.877615 <6>[ 2.406792] can: raw protocol
677 17:12:42.883398 <6>[ 2.410120] can: broadcast manager protocol
678 17:12:42.890306 <6>[ 2.414718] can: netlink gateway - max_hops=1
679 17:12:42.890846 <5>[ 2.420245] Key type dns_resolver registered
680 17:12:42.896028 <6>[ 2.425311] ThumbEE CPU extension supported.
681 17:12:42.902273 <5>[ 2.429998] Registering SWP/SWPB emulation handler
682 17:12:42.910438 <3>[ 2.435693] omap_voltage_late_init: Voltage driver support not added
683 17:12:43.117487 <5>[ 2.644315] Loading compiled-in X.509 certificates
684 17:12:43.246252 <6>[ 2.762788] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
685 17:12:43.253419 <6>[ 2.779450] pinctrl-single 44e10800.pinmux: 142 pins, size 568
686 17:12:43.279761 <3>[ 2.803044] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
687 17:12:43.493102 <3>[ 3.016513] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
688 17:12:43.687066 <6>[ 3.214757] OMAP GPIO hardware version 0.1
689 17:12:43.707678 <6>[ 3.233316] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
690 17:12:43.809952 <4>[ 3.335268] at24 2-0054: supply vcc not found, using dummy regulator
691 17:12:43.851284 <4>[ 3.376766] at24 2-0055: supply vcc not found, using dummy regulator
692 17:12:43.892542 <4>[ 3.417949] at24 2-0056: supply vcc not found, using dummy regulator
693 17:12:43.932366 <4>[ 3.457807] at24 2-0057: supply vcc not found, using dummy regulator
694 17:12:43.971565 <6>[ 3.497851] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
695 17:12:44.047438 <3>[ 3.569690] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
696 17:12:44.072092 <6>[ 3.590471] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
697 17:12:44.094004 <4>[ 3.616710] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
698 17:12:44.101796 <4>[ 3.625988] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
699 17:12:44.228337 <6>[ 3.753980] omap_rng 48310000.rng: Random Number Generator ver. 20
700 17:12:44.251663 <5>[ 3.780111] random: crng init done
701 17:12:44.304963 <6>[ 3.834233] Freeing initrd memory: 14448K
702 17:12:44.314601 <6>[ 3.838847] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
703 17:12:44.363244 <6>[ 3.886039] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
704 17:12:44.368620 <6>[ 3.896368] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
705 17:12:44.376967 <6>[ 3.903731] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
706 17:12:44.388371 <6>[ 3.911202] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
707 17:12:44.399952 <6>[ 3.919346] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
708 17:12:44.407338 <6>[ 3.930980] cpsw-switch 4a100000.switch: Detected MACID = 78:a5:04:e2:4c:3d
709 17:12:44.418276 <5>[ 3.940015] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
710 17:12:44.445946 <3>[ 3.969733] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
711 17:12:44.451726 <6>[ 3.978334] edma 49000000.dma: TI EDMA DMA engine driver
712 17:12:44.522542 <3>[ 4.045603] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
713 17:12:44.537183 <6>[ 4.059904] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
714 17:12:44.550184 <3>[ 4.076998] l3-aon-clkctrl:0000:0: failed to disable
715 17:12:44.598397 <6>[ 4.122070] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
716 17:12:44.604100 <6>[ 4.131583] printk: legacy console [ttyS0] enabled
717 17:12:44.606884 <6>[ 4.131583] printk: legacy console [ttyS0] enabled
718 17:12:44.612431 <6>[ 4.141931] printk: legacy bootconsole [omap8250] disabled
719 17:12:44.618221 <6>[ 4.141931] printk: legacy bootconsole [omap8250] disabled
720 17:12:44.661599 <4>[ 4.184333] tps65217-pmic: Failed to locate of_node [id: -1]
721 17:12:44.665199 <4>[ 4.191746] tps65217-bl: Failed to locate of_node [id: -1]
722 17:12:44.681445 <6>[ 4.211225] tps65217 0-0024: TPS65217 ID 0xe version 1.2
723 17:12:44.699888 <6>[ 4.218151] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
724 17:12:44.711569 <6>[ 4.231834] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
725 17:12:44.717265 <6>[ 4.243735] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
726 17:12:44.739155 <6>[ 4.263194] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
727 17:12:44.745038 <6>[ 4.272392] sdhci-omap 48060000.mmc: Got CD GPIO
728 17:12:44.753041 <4>[ 4.277561] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
729 17:12:44.767677 <4>[ 4.291047] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
730 17:12:44.774241 <4>[ 4.299717] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
731 17:12:44.784083 <4>[ 4.308354] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
732 17:12:44.882524 <6>[ 4.407740] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
733 17:12:44.912996 <6>[ 4.437169] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
734 17:12:44.946245 <6>[ 4.469551] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
735 17:12:44.953038 <6>[ 4.478434] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
736 17:12:44.979164 <6>[ 4.499537] mmc0: new high speed SDHC card at address 1234
737 17:12:44.979699 <6>[ 4.506864] mmcblk0: mmc0:1234 SA32G 29.1 GiB
738 17:12:44.985179 <6>[ 4.514699] mmcblk0: p1
739 17:12:45.032362 <6>[ 4.555136] mmc1: new high speed MMC card at address 0001
740 17:12:45.039283 <6>[ 4.562205] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
741 17:12:45.046804 <6>[ 4.574388] mmcblk1: mmc1:0001 MMC04G 3.60 GiB
742 17:12:45.069591 <6>[ 4.597293] mmcblk1boot0: mmc1:0001 MMC04G 2.00 MiB
743 17:12:45.076839 <6>[ 4.604553] mmcblk1boot1: mmc1:0001 MMC04G 2.00 MiB
744 17:12:45.085426 <6>[ 4.611324] mmcblk1rpmb: mmc1:0001 MMC04G 128 KiB, chardev (236:0)
745 17:12:47.150940 <6>[ 6.674657] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
746 17:12:47.234295 <5>[ 6.703614] Sending DHCP requests ., OK
747 17:12:47.245486 <6>[ 6.768098] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.12
748 17:12:47.246014 <6>[ 6.776239] IP-Config: Complete:
749 17:12:47.259499 <6>[ 6.779777] device=eth0, hwaddr=78:a5:04:e2:4c:3d, ipaddr=192.168.6.12, mask=255.255.255.0, gw=192.168.6.1
750 17:12:47.265363 <6>[ 6.790318] host=192.168.6.12, domain=, nis-domain=(none)
751 17:12:47.271028 <6>[ 6.796572] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
752 17:12:47.277559 <6>[ 6.796606] nameserver0=10.255.253.1
753 17:12:47.287453 <6>[ 6.809162] clk: Disabling unused clocks
754 17:12:47.287974 <6>[ 6.813916] PM: genpd: Disabling unused power domains
755 17:12:47.306596 <6>[ 6.832749] Freeing unused kernel image (initmem) memory: 2048K
756 17:12:47.314029 <6>[ 6.842433] Run /init as init process
757 17:12:47.336727 Loading, please wait...
758 17:12:47.412175 Starting systemd-udevd version 252.22-1~deb12u1
759 17:12:50.514563 <4>[ 10.037024] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
760 17:12:50.702911 <4>[ 10.225287] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
761 17:12:50.850080 <6>[ 10.380021] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
762 17:12:50.860997 <6>[ 10.385842] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
763 17:12:51.106067 <6>[ 10.634369] hub 1-0:1.0: USB hub found
764 17:12:51.128444 <6>[ 10.656771] hub 1-0:1.0: 1 port detected
765 17:12:51.139172 <6>[ 10.667299] tda998x 0-0070: found TDA19988
766 17:12:54.400457 Begin: Loading essential drivers ... done.
767 17:12:54.405699 Begin: Running /scripts/init-premount ... done.
768 17:12:54.411481 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
769 17:12:54.421397 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
770 17:12:54.426311 Device /sys/class/net/eth0 found
771 17:12:54.426784 done.
772 17:12:54.485989 Begin: Waiting up to 180 secs for any network device to become available ... done.
773 17:12:54.557469 IP-Config: eth0 hardware address 78:a5:04:e2:4c:3d mtu 1500 DHCP
774 17:12:54.580505 IP-Config: eth0 guessed broadcast address 192.168.6.255
775 17:12:54.585972 IP-Config: eth0 complete (dhcp from 192.168.6.1):
776 17:12:54.591577 address: 192.168.6.12 broadcast: 192.168.6.255 netmask: 255.255.255.0
777 17:12:54.602883 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
778 17:12:54.603412 rootserver: 192.168.6.1 rootpath:
779 17:12:54.606280 filename :
780 17:12:54.729473 done.
781 17:12:54.736219 Begin: Running /scripts/nfs-bottom ... done.
782 17:12:54.802804 Begin: Running /scripts/init-bottom ... done.
783 17:12:56.294918 <30>[ 15.820651] systemd[1]: System time before build time, advancing clock.
784 17:12:56.448666 <30>[ 15.948362] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
785 17:12:56.461812 <30>[ 15.989359] systemd[1]: Detected architecture arm.
786 17:12:56.475187
787 17:12:56.475693 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
788 17:12:56.476206
789 17:12:56.496680 <30>[ 16.023220] systemd[1]: Hostname set to <debian-bookworm-armhf>.
790 17:12:58.700726 <30>[ 18.226112] systemd[1]: Queued start job for default target graphical.target.
791 17:12:58.717407 <30>[ 18.240640] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
792 17:12:58.725006 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
793 17:12:58.756577 <30>[ 18.279454] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
794 17:12:58.764076 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
795 17:12:58.793840 <30>[ 18.316330] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
796 17:12:58.801104 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
797 17:12:58.834614 <30>[ 18.357358] systemd[1]: Created slice user.slice - User and Session Slice.
798 17:12:58.841290 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
799 17:12:58.866646 <30>[ 18.384879] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
800 17:12:58.872748 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
801 17:12:58.890781 <30>[ 18.414669] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
802 17:12:58.899732 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
803 17:12:58.931733 <30>[ 18.444771] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
804 17:12:58.938180 <30>[ 18.465249] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
805 17:12:58.946728 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
806 17:12:58.969815 <30>[ 18.494078] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
807 17:12:58.978072 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
808 17:12:59.001445 <30>[ 18.525262] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
809 17:12:59.013780 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
810 17:12:59.040181 <30>[ 18.564374] systemd[1]: Reached target paths.target - Path Units.
811 17:12:59.045259 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
812 17:12:59.069925 <30>[ 18.594182] systemd[1]: Reached target remote-fs.target - Remote File Systems.
813 17:12:59.077333 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
814 17:12:59.100068 <30>[ 18.624183] systemd[1]: Reached target slices.target - Slice Units.
815 17:12:59.105483 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
816 17:12:59.130257 <30>[ 18.654452] systemd[1]: Reached target swap.target - Swaps.
817 17:12:59.134310 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
818 17:12:59.160369 <30>[ 18.684334] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
819 17:12:59.169285 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
820 17:12:59.191425 <30>[ 18.715306] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
821 17:12:59.199696 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
822 17:12:59.278917 <30>[ 18.798015] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
823 17:12:59.291598 <30>[ 18.815635] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
824 17:12:59.300098 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
825 17:12:59.323172 <30>[ 18.846326] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
826 17:12:59.330523 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
827 17:12:59.352868 <30>[ 18.876792] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
828 17:12:59.361019 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
829 17:12:59.385745 <30>[ 18.908558] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
830 17:12:59.391303 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
831 17:12:59.422663 <30>[ 18.945329] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
832 17:12:59.430215 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
833 17:12:59.457391 <30>[ 18.975366] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
834 17:12:59.476021 <30>[ 18.993924] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
835 17:12:59.525730 <30>[ 19.050568] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
836 17:12:59.549055 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
837 17:12:59.600078 <30>[ 19.124740] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
838 17:12:59.629441 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
839 17:12:59.693883 <30>[ 19.217599] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
840 17:12:59.718604 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
841 17:12:59.770447 <30>[ 19.294840] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
842 17:12:59.794511 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
843 17:12:59.851288 <30>[ 19.375957] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
844 17:12:59.888569 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
845 17:12:59.941663 <30>[ 19.466927] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
846 17:12:59.969030 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
847 17:13:00.021419 <30>[ 19.545487] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
848 17:13:00.035034 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
849 17:13:00.069617 <30>[ 19.594751] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
850 17:13:00.098163 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
851 17:13:00.149743 <30>[ 19.674819] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
852 17:13:00.172305 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
853 17:13:00.207482 <28>[ 19.725878] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
854 17:13:00.216101 <28>[ 19.740246] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
855 17:13:00.259511 <30>[ 19.785072] systemd[1]: Starting systemd-journald.service - Journal Service...
856 17:13:00.278322 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
857 17:13:00.360946 <30>[ 19.885787] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
858 17:13:00.374189 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
859 17:13:00.401018 <30>[ 19.926062] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
860 17:13:00.453774 Starting [0;1;39msystemd-network-g… units from Kernel command line...
861 17:13:00.515569 <30>[ 20.039141] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
862 17:13:00.570141 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
863 17:13:00.633636 <30>[ 20.158005] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
864 17:13:00.673153 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
865 17:13:00.716964 <30>[ 20.242197] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
866 17:13:00.800746 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
867 17:13:00.833112 <30>[ 20.358146] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
868 17:13:00.882413 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
869 17:13:00.903140 <30>[ 20.427145] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
870 17:13:00.941335 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
871 17:13:01.103592 <30>[ 20.629347] systemd[1]: modprobe@configfs.service: Deactivated successfully.
872 17:13:01.140652 <30>[ 20.665275] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
873 17:13:01.169765 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
874 17:13:01.191138 <30>[ 20.715432] systemd[1]: Started systemd-journald.service - Journal Service.
875 17:13:01.197898 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
876 17:13:01.231604 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
877 17:13:01.255418 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
878 17:13:01.292223 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
879 17:13:01.319723 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
880 17:13:01.354265 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
881 17:13:01.390005 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
882 17:13:01.413295 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
883 17:13:01.442329 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
884 17:13:01.469977 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
885 17:13:01.519397 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
886 17:13:01.569961 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
887 17:13:01.621757 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
888 17:13:01.675344 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
889 17:13:01.756405 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
890 17:13:01.913366 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
891 17:13:01.989364 <46>[ 21.514515] systemd-journald[163]: Received client request to flush runtime journal.
892 17:13:02.096366 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
893 17:13:02.129823 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
894 17:13:02.969483 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
895 17:13:03.026745 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
896 17:13:03.723948 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
897 17:13:03.882071 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
898 17:13:03.901799 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
899 17:13:03.920620 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
900 17:13:03.992389 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
901 17:13:04.055125 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
902 17:13:04.951749 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
903 17:13:05.020585 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
904 17:13:05.129040 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
905 17:13:05.202583 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
906 17:13:05.250425 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
907 17:13:06.143589 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
908 17:13:07.454640 <5>[ 26.979944] cfg80211: Loading compiled-in X.509 certificates for regulatory database
909 17:13:08.160524 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
910 17:13:09.121722 <5>[ 28.649077] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
911 17:13:09.235322 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m -<5>[ 28.756347] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
912 17:13:09.235916 /dev/ttyS0.
913 17:13:09.250112 <4>[ 28.775291] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
914 17:13:09.256027 <6>[ 28.784387] cfg80211: failed to load regulatory.db
915 17:13:10.019639 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
916 17:13:10.064327 <46>[ 29.579682] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
917 17:13:10.249770 <46>[ 29.768151] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
918 17:13:10.442119 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
919 17:13:19.018306 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
920 17:13:19.044020 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
921 17:13:19.071486 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
922 17:13:19.091531 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
923 17:13:19.164999 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
924 17:13:19.241152 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
925 17:13:19.281682 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
926 17:13:19.323648 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
927 17:13:19.386211 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
928 17:13:19.417950 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
929 17:13:19.446744 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
930 17:13:19.476335 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
931 17:13:19.504870 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
932 17:13:19.556747 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
933 17:13:19.590983 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
934 17:13:19.617098 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
935 17:13:19.676071 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
936 17:13:19.705539 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
937 17:13:19.736267 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
938 17:13:19.759716 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
939 17:13:19.789983 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
940 17:13:19.809846 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
941 17:13:19.836846 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
942 17:13:19.914365 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
943 17:13:19.954657 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
944 17:13:20.046787 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
945 17:13:20.121534 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
946 17:13:20.170673 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
947 17:13:20.198720 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
948 17:13:20.228826 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
949 17:13:20.422176 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
950 17:13:20.499047 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
951 17:13:20.543831 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
952 17:13:20.568299 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
953 17:13:20.580988 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
954 17:13:20.850828 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
955 17:13:21.171667 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
956 17:13:21.211283 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
957 17:13:21.234424 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
958 17:13:21.302191 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
959 17:13:21.469459 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
960 17:13:21.581724
961 17:13:21.586511 Debian GNU/Linux 12 debian-bookworm-aworm-armhf login: root (automatic login)
962 17:13:21.587068
963 17:13:21.896525 Linux debian-bookworm-armhf 6.12.0-rc3 #1 SMP Mon Nov 4 16:41:30 UTC 2024 armv7l
964 17:13:21.905769
965 17:13:21.911299 The programs included with the Debian GNU/Linux system are free software;
966 17:13:21.916912 the exact distribution terms for each program are described in the
967 17:13:21.922629 individual files in /usr/share/doc/*/copyright.
968 17:13:21.923185
969 17:13:21.928995 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
970 17:13:21.929567 permitted by applicable law.
971 17:13:26.636218 Unable to match end of the kernel message
973 17:13:26.637144 Setting prompt string to ['/ #']
974 17:13:26.637463 end: 2.4.4.1 login-action (duration 00:00:47) [common]
976 17:13:26.638202 end: 2.4.4 auto-login-action (duration 00:00:47) [common]
977 17:13:26.638495 start: 2.4.5 expect-shell-connection (timeout 00:03:15) [common]
978 17:13:26.638733 Setting prompt string to ['/ #']
979 17:13:26.638950 Forcing a shell prompt, looking for ['/ #']
981 17:13:26.689774 / #
982 17:13:26.690515 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
983 17:13:26.690805 Waiting using forced prompt support (timeout 00:02:30)
984 17:13:26.695121
985 17:13:26.699031 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
986 17:13:26.699387 start: 2.4.6 export-device-env (timeout 00:03:15) [common]
987 17:13:26.699648 Sending with 10 millisecond of delay
989 17:13:31.688298 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/935269/extract-nfsrootfs-j5tyg99w'
990 17:13:31.698964 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/935269/extract-nfsrootfs-j5tyg99w'
991 17:13:31.700151 Sending with 10 millisecond of delay
993 17:13:33.797289 / # export NFS_SERVER_IP='192.168.6.2'
994 17:13:33.808213 export NFS_SERVER_IP='192.168.6.2'
995 17:13:33.809551 end: 2.4.6 export-device-env (duration 00:00:07) [common]
996 17:13:33.810358 end: 2.4 uboot-commands (duration 00:01:52) [common]
997 17:13:33.811134 end: 2 uboot-action (duration 00:01:52) [common]
998 17:13:33.811887 start: 3 lava-test-retry (timeout 00:06:56) [common]
999 17:13:33.812718 start: 3.1 lava-test-shell (timeout 00:06:56) [common]
1000 17:13:33.813354 Using namespace: common
1002 17:13:33.914837 / # #
1003 17:13:33.916083 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1004 17:13:33.920833 #
1005 17:13:33.926873 Using /lava-935269
1007 17:13:34.028395 / # export SHELL=/bin/bash
1008 17:13:34.034205 export SHELL=/bin/bash
1010 17:13:34.141773 / # . /lava-935269/environment
1011 17:13:34.147600 . /lava-935269/environment
1013 17:13:34.261215 / # /lava-935269/bin/lava-test-runner /lava-935269/0
1014 17:13:34.262125 Test shell timeout: 10s (minimum of the action and connection timeout)
1015 17:13:34.265760 /lava-935269/bin/lava-test-runner /lava-935269/0
1016 17:13:34.644219 + export TESTRUN_ID=0_timesync-off
1017 17:13:34.651921 + TESTRUN_ID=0_timesync-off
1018 17:13:34.652471 + cd /lava-935269/0/tests/0_timesync-off
1019 17:13:34.652899 ++ cat uuid
1020 17:13:34.667880 + UUID=935269_1.6.2.4.1
1021 17:13:34.668421 + set +x
1022 17:13:34.676752 <LAVA_SIGNAL_STARTRUN 0_timesync-off 935269_1.6.2.4.1>
1023 17:13:34.677458 + systemctl stop systemd-timesyncd
1024 17:13:34.678361 Received signal: <STARTRUN> 0_timesync-off 935269_1.6.2.4.1
1025 17:13:34.678949 Starting test lava.0_timesync-off (935269_1.6.2.4.1)
1026 17:13:34.679646 Skipping test definition patterns.
1027 17:13:34.976706 + set +x
1028 17:13:34.977133 <LAVA_SIGNAL_ENDRUN 0_timesync-off 935269_1.6.2.4.1>
1029 17:13:34.977653 Received signal: <ENDRUN> 0_timesync-off 935269_1.6.2.4.1
1030 17:13:34.978081 Ending use of test pattern.
1031 17:13:34.978432 Ending test lava.0_timesync-off (935269_1.6.2.4.1), duration 0.30
1033 17:13:35.174807 + export TESTRUN_ID=1_kselftest-dt
1034 17:13:35.182863 + TESTRUN_ID=1_kselftest-dt
1035 17:13:35.183188 + cd /lava-935269/0/tests/1_kselftest-dt
1036 17:13:35.183566 ++ cat uuid
1037 17:13:35.198875 + UUID=935269_1.6.2.4.5
1038 17:13:35.199225 + set +x
1039 17:13:35.204431 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 935269_1.6.2.4.5>
1040 17:13:35.204738 + cd ./automated/linux/kselftest/
1041 17:13:35.205196 Received signal: <STARTRUN> 1_kselftest-dt 935269_1.6.2.4.5
1042 17:13:35.205437 Starting test lava.1_kselftest-dt (935269_1.6.2.4.5)
1043 17:13:35.205698 Skipping test definition patterns.
1044 17:13:35.233661 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-regmap/for-next/v6.12-rc3-7-g953e549471ca/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g broonie-regmap -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1045 17:13:35.334992 INFO: install_deps skipped
1046 17:13:35.918985 --2024-11-04 17:13:35-- http://storage.kernelci.org/broonie-regmap/for-next/v6.12-rc3-7-g953e549471ca/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1047 17:13:35.943944 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1048 17:13:36.085941 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1049 17:13:36.226138 HTTP request sent, awaiting response... 200 OK
1050 17:13:36.226559 Length: 4105444 (3.9M) [application/octet-stream]
1051 17:13:36.231668 Saving to: 'kselftest_armhf.tar.gz'
1052 17:13:36.232051
1053 17:13:37.500974
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 181KB/s
kselftest_armhf.tar 4%[ ] 200.39K 359KB/s
kselftest_armhf.tar 18%[==> ] 733.79K 884KB/s
kselftest_armhf.tar 54%[=========> ] 2.13M 2.07MB/s
kselftest_armhf.tar 95%[==================> ] 3.72M 2.99MB/s
kselftest_armhf.tar 100%[===================>] 3.92M 3.09MB/s in 1.3s
1054 17:13:37.501816
1055 17:13:38.258643 2024-11-04 17:13:37 (3.09 MB/s) - 'kselftest_armhf.tar.gz' saved [4105444/4105444]
1056 17:13:38.259451
1057 17:13:50.793783 skiplist:
1058 17:13:50.794600 ========================================
1059 17:13:50.799188 ========================================
1060 17:13:50.913589 dt:test_unprobed_devices.sh
1061 17:13:50.955629 ============== Tests to run ===============
1062 17:13:50.965531 dt:test_unprobed_devices.sh
1063 17:13:50.969616 ===========End Tests to run ===============
1064 17:13:50.980343 shardfile-dt pass
1065 17:13:51.263274 <12>[ 70.794250] kselftest: Running tests in dt
1066 17:13:51.290414 TAP version 13
1067 17:13:51.314475 1..1
1068 17:13:51.368479 # timeout set to 45
1069 17:13:51.369104 # selftests: dt: test_unprobed_devices.sh
1070 17:13:52.294379 # TAP version 13
1071 17:14:17.131581 # 1..257
1072 17:14:17.304054 # ok 1 / # SKIP
1073 17:14:17.328097 # ok 2 /clk_mcasp0
1074 17:14:17.399040 # ok 3 /clk_mcasp0_fixed # SKIP
1075 17:14:17.467373 # ok 4 /cpus/cpu@0 # SKIP
1076 17:14:17.540134 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1077 17:14:17.563420 # ok 6 /fixedregulator0
1078 17:14:17.584416 # ok 7 /leds
1079 17:14:17.600514 # ok 8 /ocp
1080 17:14:17.627165 # ok 9 /ocp/interconnect@44c00000
1081 17:14:17.655171 # ok 10 /ocp/interconnect@44c00000/segment@0
1082 17:14:17.673383 # ok 11 /ocp/interconnect@44c00000/segment@100000
1083 17:14:17.698172 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1084 17:14:17.769062 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1085 17:14:17.791046 # ok 14 /ocp/interconnect@44c00000/segment@200000
1086 17:14:17.818415 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1087 17:14:17.923560 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1088 17:14:17.992545 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1089 17:14:18.064896 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1090 17:14:18.140430 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1091 17:14:18.212711 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1092 17:14:18.284097 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1093 17:14:18.355272 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1094 17:14:18.423606 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1095 17:14:18.497417 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1096 17:14:18.571352 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1097 17:14:18.642497 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1098 17:14:18.714336 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1099 17:14:18.785307 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1100 17:14:18.852450 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1101 17:14:18.922448 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1102 17:14:18.994110 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1103 17:14:19.064526 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1104 17:14:19.135681 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1105 17:14:19.206768 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1106 17:14:19.278525 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1107 17:14:19.348615 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1108 17:14:19.420649 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1109 17:14:19.492349 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1110 17:14:19.563142 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1111 17:14:19.634606 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1112 17:14:19.710642 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1113 17:14:19.782764 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1114 17:14:19.856291 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1115 17:14:19.926326 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1116 17:14:19.994428 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1117 17:14:20.066238 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1118 17:14:20.142703 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1119 17:14:20.216080 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1120 17:14:20.286021 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1121 17:14:20.355324 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1122 17:14:20.427261 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1123 17:14:20.502282 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1124 17:14:20.574224 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1125 17:14:20.646769 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1126 17:14:20.713983 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1127 17:14:20.786366 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1128 17:14:20.861406 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1129 17:14:20.929143 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1130 17:14:21.001283 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1131 17:14:21.073973 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1132 17:14:21.149527 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1133 17:14:21.217809 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1134 17:14:21.288810 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1135 17:14:21.361436 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1136 17:14:21.431525 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1137 17:14:21.503821 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1138 17:14:21.576052 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1139 17:14:21.646753 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1140 17:14:21.723033 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1141 17:14:21.795409 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1142 17:14:21.865990 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1143 17:14:21.938448 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1144 17:14:22.010318 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1145 17:14:22.081687 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1146 17:14:22.152184 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1147 17:14:22.224755 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1148 17:14:22.299548 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1149 17:14:22.369804 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1150 17:14:22.441542 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1151 17:14:22.513096 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1152 17:14:22.585166 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1153 17:14:22.656892 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1154 17:14:22.730946 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1155 17:14:22.803408 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1156 17:14:22.880248 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1157 17:14:22.952207 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1158 17:14:23.023877 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1159 17:14:23.094940 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1160 17:14:23.164039 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1161 17:14:23.239006 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1162 17:14:23.306011 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1163 17:14:23.383114 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1164 17:14:23.450423 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1165 17:14:23.522307 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1166 17:14:23.542486 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1167 17:14:23.565755 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1168 17:14:23.593478 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1169 17:14:23.618499 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1170 17:14:23.636740 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1171 17:14:23.660991 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1172 17:14:23.689279 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1173 17:14:23.712325 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1174 17:14:23.817720 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1175 17:14:23.841876 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1176 17:14:23.863972 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1177 17:14:23.889716 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1178 17:14:23.994448 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1179 17:14:24.065837 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1180 17:14:24.142330 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1181 17:14:24.210174 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1182 17:14:24.281814 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1183 17:14:24.353199 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1184 17:14:24.425000 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1185 17:14:24.496063 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1186 17:14:24.572070 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1187 17:14:24.643863 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1188 17:14:24.714877 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1189 17:14:24.786614 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1190 17:14:24.856012 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1191 17:14:24.926431 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1192 17:14:25.001179 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1193 17:14:25.070241 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1194 17:14:25.092280 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1195 17:14:25.162367 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1196 17:14:25.231798 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1197 17:14:25.308397 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1198 17:14:25.331232 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1199 17:14:25.402347 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1200 17:14:25.422598 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1201 17:14:25.491729 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1202 17:14:25.514118 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1203 17:14:25.538143 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1204 17:14:25.560354 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1205 17:14:25.585311 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1206 17:14:25.611563 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1207 17:14:25.632865 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1208 17:14:25.661976 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1209 17:14:25.735001 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1210 17:14:25.753950 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1211 17:14:25.775751 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1212 17:14:25.846911 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1213 17:14:25.917526 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1214 17:14:25.937948 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1215 17:14:26.037756 # not ok 144 /ocp/interconnect@47c00000
1216 17:14:26.109426 # not ok 145 /ocp/interconnect@47c00000/segment@0
1217 17:14:26.129953 # ok 146 /ocp/interconnect@48000000
1218 17:14:26.157730 # ok 147 /ocp/interconnect@48000000/segment@0
1219 17:14:26.178017 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1220 17:14:26.199475 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1221 17:14:26.228041 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1222 17:14:26.251154 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1223 17:14:26.272120 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1224 17:14:26.298759 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1225 17:14:26.320967 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1226 17:14:26.392261 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1227 17:14:26.460961 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1228 17:14:26.482749 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1229 17:14:26.506990 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1230 17:14:26.529231 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1231 17:14:26.557663 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1232 17:14:26.579848 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1233 17:14:26.602682 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1234 17:14:26.623936 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1235 17:14:26.651179 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1236 17:14:26.672174 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1237 17:14:26.697957 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1238 17:14:26.721394 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1239 17:14:26.742474 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1240 17:14:26.764152 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1241 17:14:26.791836 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1242 17:14:26.812125 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1243 17:14:26.834812 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1244 17:14:26.856576 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1245 17:14:26.880954 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1246 17:14:26.902482 # ok 175 /ocp/interconnect@48000000/segment@100000
1247 17:14:26.931150 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1248 17:14:26.953000 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1249 17:14:27.026676 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1250 17:14:27.097346 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1251 17:14:27.168336 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1252 17:14:27.241693 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1253 17:14:27.311580 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1254 17:14:27.385135 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1255 17:14:27.459436 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1256 17:14:27.533484 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1257 17:14:27.551476 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1258 17:14:27.573823 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1259 17:14:27.594915 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1260 17:14:27.620801 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1261 17:14:27.643791 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1262 17:14:27.672527 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1263 17:14:27.692364 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1264 17:14:27.715265 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1265 17:14:27.737506 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1266 17:14:27.762402 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1267 17:14:27.788271 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1268 17:14:27.812334 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1269 17:14:27.831817 # ok 198 /ocp/interconnect@48000000/segment@200000
1270 17:14:27.853844 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1271 17:14:27.926496 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1272 17:14:27.949749 # ok 201 /ocp/interconnect@48000000/segment@300000
1273 17:14:27.978451 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1274 17:14:27.995972 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1275 17:14:28.022921 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1276 17:14:28.042912 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1277 17:14:28.071455 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1278 17:14:28.092205 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1279 17:14:28.162592 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1280 17:14:28.181092 # ok 209 /ocp/interconnect@4a000000
1281 17:14:28.207936 # ok 210 /ocp/interconnect@4a000000/segment@0
1282 17:14:28.232170 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1283 17:14:28.257618 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1284 17:14:28.278798 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1285 17:14:28.302049 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1286 17:14:28.371507 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1287 17:14:28.477693 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1288 17:14:28.549746 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1289 17:14:28.652519 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1290 17:14:28.724317 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1291 17:14:28.795571 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1292 17:14:28.892147 # not ok 221 /ocp/interconnect@4b140000
1293 17:14:28.964275 # not ok 222 /ocp/interconnect@4b140000/segment@0
1294 17:14:29.038971 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1295 17:14:29.059519 # ok 224 /ocp/target-module@40300000
1296 17:14:29.078922 # ok 225 /ocp/target-module@40300000/sram@0
1297 17:14:29.156337 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1298 17:14:29.228061 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1299 17:14:29.247550 # ok 228 /ocp/target-module@47400000
1300 17:14:29.271187 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1301 17:14:29.290403 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1302 17:14:29.312629 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1303 17:14:29.338359 # ok 232 /ocp/target-module@47400000/usb@1400
1304 17:14:29.361694 # ok 233 /ocp/target-module@47400000/usb@1800
1305 17:14:29.377055 # ok 234 /ocp/target-module@47810000
1306 17:14:29.408388 # ok 235 /ocp/target-module@49000000
1307 17:14:29.423753 # ok 236 /ocp/target-module@49000000/dma@0
1308 17:14:29.446255 # ok 237 /ocp/target-module@49800000
1309 17:14:29.469918 # ok 238 /ocp/target-module@49800000/dma@0
1310 17:14:29.491103 # ok 239 /ocp/target-module@49900000
1311 17:14:29.517620 # ok 240 /ocp/target-module@49900000/dma@0
1312 17:14:29.539741 # ok 241 /ocp/target-module@49a00000
1313 17:14:29.559920 # ok 242 /ocp/target-module@49a00000/dma@0
1314 17:14:29.579812 # ok 243 /ocp/target-module@4c000000
1315 17:14:29.650838 # not ok 244 /ocp/target-module@4c000000/emif@0
1316 17:14:29.676851 # ok 245 /ocp/target-module@50000000
1317 17:14:29.699436 # ok 246 /ocp/target-module@53100000
1318 17:14:29.766365 # not ok 247 /ocp/target-module@53100000/sham@0
1319 17:14:29.789416 # ok 248 /ocp/target-module@53500000
1320 17:14:29.858627 # not ok 249 /ocp/target-module@53500000/aes@0
1321 17:14:29.880024 # ok 250 /ocp/target-module@56000000
1322 17:14:29.988220 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1323 17:14:30.057242 # ok 252 /opp-table # SKIP
1324 17:14:30.121671 # ok 253 /soc # SKIP
1325 17:14:30.147500 # ok 254 /sound
1326 17:14:30.168922 # ok 255 /target-module@4b000000
1327 17:14:30.191270 # ok 256 /target-module@4b000000/target-module@140000
1328 17:14:30.211941 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1329 17:14:30.220420 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1330 17:14:30.228334 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1331 17:14:32.513790 dt_test_unprobed_devices_sh_ skip
1332 17:14:32.519158 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1333 17:14:32.524767 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1334 17:14:32.525248 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1335 17:14:32.530344 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1336 17:14:32.535866 dt_test_unprobed_devices_sh_fixedregulator0 pass
1337 17:14:32.541518 dt_test_unprobed_devices_sh_leds pass
1338 17:14:32.541983 dt_test_unprobed_devices_sh_ocp pass
1339 17:14:32.546987 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1340 17:14:32.552745 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1341 17:14:32.558314 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1342 17:14:32.569505 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1343 17:14:32.575114 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1344 17:14:32.580622 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1345 17:14:32.591877 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1346 17:14:32.597540 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1347 17:14:32.608807 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1348 17:14:32.619800 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1349 17:14:32.631055 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1350 17:14:32.636668 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1351 17:14:32.647826 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1352 17:14:32.659031 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1353 17:14:32.670294 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1354 17:14:32.681468 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1355 17:14:32.687058 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1356 17:14:32.698258 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1357 17:14:32.709514 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1358 17:14:32.720674 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1359 17:14:32.731895 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1360 17:14:32.737509 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1361 17:14:32.748664 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1362 17:14:32.759877 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1363 17:14:32.771048 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1364 17:14:32.776674 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1365 17:14:32.787829 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1366 17:14:32.799108 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1367 17:14:32.810169 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1368 17:14:32.821367 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1369 17:14:32.826978 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1370 17:14:32.838127 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1371 17:14:32.849344 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1372 17:14:32.860641 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1373 17:14:32.871725 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1374 17:14:32.882965 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1375 17:14:32.894148 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1376 17:14:32.905353 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1377 17:14:32.916543 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1378 17:14:32.927711 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1379 17:14:32.938883 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1380 17:14:32.950090 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1381 17:14:32.961317 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1382 17:14:32.972480 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1383 17:14:32.983661 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1384 17:14:32.994907 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1385 17:14:33.006077 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1386 17:14:33.017284 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1387 17:14:33.028419 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1388 17:14:33.039661 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1389 17:14:33.050791 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1390 17:14:33.061999 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1391 17:14:33.073226 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1392 17:14:33.084445 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1393 17:14:33.095526 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1394 17:14:33.106770 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1395 17:14:33.112338 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1396 17:14:33.123534 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1397 17:14:33.134719 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1398 17:14:33.145960 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1399 17:14:33.157111 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1400 17:14:33.168332 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1401 17:14:33.179510 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1402 17:14:33.190698 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1403 17:14:33.201869 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1404 17:14:33.213079 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1405 17:14:33.224287 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1406 17:14:33.235487 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1407 17:14:33.246677 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1408 17:14:33.257820 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1409 17:14:33.269030 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1410 17:14:33.280243 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1411 17:14:33.291395 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1412 17:14:33.302597 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1413 17:14:33.308254 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1414 17:14:33.319356 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1415 17:14:33.330548 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1416 17:14:33.341820 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1417 17:14:33.352951 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1418 17:14:33.358556 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1419 17:14:33.375504 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1420 17:14:33.386528 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1421 17:14:33.392153 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1422 17:14:33.408884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1423 17:14:33.420086 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clogks_clock_700_clock-clkout2_7 skip
1424 17:14:33.431353 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1425 17:14:33.436853 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1426 17:14:33.448098 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1427 17:14:33.459223 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1428 17:14:33.464855 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1429 17:14:33.476040 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1430 17:14:33.487226 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1431 17:14:33.492841 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1432 17:14:33.504098 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1433 17:14:33.509657 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1434 17:14:33.520819 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1435 17:14:33.532067 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1436 17:14:33.543230 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1437 17:14:33.554563 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1438 17:14:33.565676 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1439 17:14:33.576849 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1440 17:14:33.588259 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1441 17:14:33.599422 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1442 17:14:33.634758 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1443 17:14:33.635113 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1444 17:14:33.635359 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1445 17:14:33.644089 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1446 17:14:33.660785 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1447 17:14:33.672232 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1448 17:14:33.683200 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1449 17:14:33.694423 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1450 17:14:33.705582 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1451 17:14:33.722267 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1452 17:14:33.733419 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1453 17:14:33.744628 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1454 17:14:33.755836 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1455 17:14:33.761462 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1456 17:14:33.772629 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1457 17:14:33.783831 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1458 17:14:33.789442 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1459 17:14:33.800590 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1460 17:14:33.806217 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1461 17:14:33.817352 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1462 17:14:33.822997 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1463 17:14:33.834145 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1464 17:14:33.839797 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1465 17:14:33.850945 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1466 17:14:33.856551 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1467 17:14:33.867779 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1468 17:14:33.878926 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1469 17:14:33.890104 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1470 17:14:33.901360 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1471 17:14:33.912494 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1472 17:14:33.918230 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1473 17:14:33.929327 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1474 17:14:33.934922 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1475 17:14:33.940902 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1476 17:14:33.946099 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1477 17:14:33.951784 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1478 17:14:33.957261 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1479 17:14:33.968446 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1480 17:14:33.974066 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1481 17:14:33.979659 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1482 17:14:33.990824 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1483 17:14:33.996453 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1484 17:14:34.007648 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1485 17:14:34.013298 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1486 17:14:34.024433 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1487 17:14:34.030037 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1488 17:14:34.041233 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1489 17:14:34.046854 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1490 17:14:34.057977 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1491 17:14:34.063618 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1492 17:14:34.074780 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1493 17:14:34.080401 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1494 17:14:34.091755 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1495 17:14:34.097298 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1496 17:14:34.102852 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1497 17:14:34.114011 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1498 17:14:34.119656 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1499 17:14:34.130858 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1500 17:14:34.136466 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1501 17:14:34.147650 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1502 17:14:34.153264 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1503 17:14:34.164439 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1504 17:14:34.171028 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1505 17:14:34.175641 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1506 17:14:34.186865 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1507 17:14:34.192608 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1508 17:14:34.203767 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1509 17:14:34.214874 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1510 17:14:34.226103 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1511 17:14:34.237275 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1512 17:14:34.248506 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1513 17:14:34.259715 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1514 17:14:34.270894 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1515 17:14:34.282057 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1516 17:14:34.287722 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1517 17:14:34.298842 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1518 17:14:34.304499 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1519 17:14:34.315645 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1520 17:14:34.321271 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1521 17:14:34.332461 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1522 17:14:34.338062 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1523 17:14:34.349228 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1524 17:14:34.354863 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1525 17:14:34.366012 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1526 17:14:34.371649 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1527 17:14:34.382798 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1528 17:14:34.388438 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1529 17:14:34.399584 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1530 17:14:34.405210 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1531 17:14:34.410817 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1532 17:14:34.421926 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1533 17:14:34.427569 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1534 17:14:34.438748 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1535 17:14:34.444366 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1536 17:14:34.455529 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1537 17:14:34.468584 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1538 17:14:34.471858 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1539 17:14:34.477498 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1540 17:14:34.483109 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1541 17:14:34.488672 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1542 17:14:34.499864 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1543 17:14:34.511094 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1544 17:14:34.516712 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1545 17:14:34.527900 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1546 17:14:34.533469 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1547 17:14:34.544645 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1548 17:14:34.555946 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1549 17:14:34.567139 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1550 17:14:34.572714 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1551 17:14:34.578338 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1552 17:14:34.583956 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1553 17:14:34.595140 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1554 17:14:34.595686 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1555 17:14:34.606281 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1556 17:14:34.611938 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1557 17:14:34.617525 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1558 17:14:34.623128 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1559 17:14:34.628835 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1560 17:14:34.639951 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1561 17:14:34.645536 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1562 17:14:34.651128 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1563 17:14:34.656794 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1564 17:14:34.662371 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1565 17:14:34.668051 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1566 17:14:34.673626 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1567 17:14:34.679275 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1568 17:14:34.684768 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1569 17:14:34.690361 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1570 17:14:34.696051 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1571 17:14:34.701603 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1572 17:14:34.707170 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1573 17:14:34.712769 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1574 17:14:34.718350 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1575 17:14:34.723975 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1576 17:14:34.729602 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1577 17:14:34.735176 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1578 17:14:34.740780 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1579 17:14:34.746367 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1580 17:14:34.752044 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1581 17:14:34.757598 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1582 17:14:34.763188 dt_test_unprobed_devices_sh_opp-table skip
1583 17:14:34.763720 dt_test_unprobed_devices_sh_soc skip
1584 17:14:34.768786 dt_test_unprobed_devices_sh_sound pass
1585 17:14:34.774372 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1586 17:14:34.780042 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1587 17:14:34.785576 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1588 17:14:34.791153 dt_test_unprobed_devices_sh fail
1589 17:14:34.791665 + ../../utils/send-to-lava.sh ./output/result.txt
1590 17:14:34.799215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1591 17:14:34.800208 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1593 17:14:34.808863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1594 17:14:34.809665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1596 17:14:34.894608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1597 17:14:34.895458 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1599 17:14:34.986635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1600 17:14:34.987525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1602 17:14:35.076151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1603 17:14:35.077025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1605 17:14:35.162605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1606 17:14:35.163458 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1608 17:14:35.253270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1609 17:14:35.254092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1611 17:14:35.343276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1612 17:14:35.344193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1614 17:14:35.435314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1615 17:14:35.436279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1617 17:14:35.522214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1618 17:14:35.523085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1620 17:14:35.607659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1621 17:14:35.608625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1623 17:14:35.694127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1624 17:14:35.695155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1626 17:14:35.787908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1627 17:14:35.788849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1629 17:14:35.879206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1630 17:14:35.880073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1632 17:14:35.961918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1633 17:14:35.962772 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1635 17:14:36.049197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1636 17:14:36.050017 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1638 17:14:36.142556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1639 17:14:36.143312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1641 17:14:36.353942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1642 17:14:36.354613 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1644 17:14:36.461552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1645 17:14:36.462424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1647 17:14:36.552903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1648 17:14:36.553837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1650 17:14:36.644930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1651 17:14:36.645878 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1653 17:14:36.731735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1654 17:14:36.732642 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1656 17:14:36.818006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1657 17:14:36.818949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1659 17:14:36.903547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1660 17:14:36.904486 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1662 17:14:36.996483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1663 17:14:36.997397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1665 17:14:37.090067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1666 17:14:37.091028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1668 17:14:37.175801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1669 17:14:37.176769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1671 17:14:37.261090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1672 17:14:37.262053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1674 17:14:37.346407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1675 17:14:37.347401 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1677 17:14:37.432110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1678 17:14:37.433010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1680 17:14:37.517461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1681 17:14:37.518332 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1683 17:14:37.604649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1684 17:14:37.605609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1686 17:14:37.695824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1687 17:14:37.696798 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1689 17:14:37.788408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1690 17:14:37.789404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1692 17:14:37.873636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1693 17:14:37.874594 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1695 17:14:37.966641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1696 17:14:37.967540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1698 17:14:38.057758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1699 17:14:38.058687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1701 17:14:38.145131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1702 17:14:38.145968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1704 17:14:38.237046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1705 17:14:38.237934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1707 17:14:38.323380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1708 17:14:38.324294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1710 17:14:38.408689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1711 17:14:38.409551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1713 17:14:38.495255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1714 17:14:38.496137 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1716 17:14:38.586493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1717 17:14:38.587354 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1719 17:14:38.677824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1720 17:14:38.678657 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1722 17:14:38.764107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1723 17:14:38.764959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1725 17:14:38.855180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1726 17:14:38.856052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1728 17:14:38.942709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1729 17:14:38.943604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1731 17:14:39.034338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1732 17:14:39.035220 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1734 17:14:39.127536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1735 17:14:39.128500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1737 17:14:39.220903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1738 17:14:39.221778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1740 17:14:39.312466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1741 17:14:39.313330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1743 17:14:39.403556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1744 17:14:39.404432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1746 17:14:39.494723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1747 17:14:39.495572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1749 17:14:39.580201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1750 17:14:39.581049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1752 17:14:39.674366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1753 17:14:39.675182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1755 17:14:39.765918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1756 17:14:39.766744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1758 17:14:39.856754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1759 17:14:39.857583 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1761 17:14:39.943134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1762 17:14:39.944008 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1764 17:14:40.032624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1765 17:14:40.033452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1767 17:14:40.118127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1768 17:14:40.119326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1770 17:14:40.211878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1771 17:14:40.212811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1773 17:14:40.313103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1774 17:14:40.314041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1776 17:14:40.404855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1777 17:14:40.405807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1779 17:14:40.497625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1780 17:14:40.498558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1782 17:14:40.592187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1783 17:14:40.593142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1785 17:14:40.685194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1786 17:14:40.686067 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1788 17:14:40.781207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1789 17:14:40.782076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1791 17:14:40.875197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1792 17:14:40.876150 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1794 17:14:40.960888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1795 17:14:40.961777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1797 17:14:41.051833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1798 17:14:41.052733 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1800 17:14:41.144146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1801 17:14:41.144724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1803 17:14:41.230570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1804 17:14:41.231154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1806 17:14:41.323435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1807 17:14:41.324042 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1809 17:14:41.413842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1810 17:14:41.414450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1812 17:14:41.504542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1813 17:14:41.505121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1815 17:14:41.592238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1816 17:14:41.593050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1818 17:14:41.683146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1819 17:14:41.684052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1821 17:14:41.776762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1822 17:14:41.777610 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1824 17:14:41.870475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1825 17:14:41.871319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1827 17:14:41.962576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1828 17:14:41.963359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1830 17:14:42.052522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1831 17:14:42.053345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1833 17:14:42.139014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1834 17:14:42.139845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1836 17:14:42.231262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1837 17:14:42.232093 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1839 17:14:42.321206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1840 17:14:42.322077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1842 17:14:42.407605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1843 17:14:42.408483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1845 17:14:42.497364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1846 17:14:42.498224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1848 17:14:42.587971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1849 17:14:42.589650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1851 17:14:42.681366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1852 17:14:42.682202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1854 17:14:42.766335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1855 17:14:42.767106 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1857 17:14:42.862376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1858 17:14:42.863141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1860 17:14:42.951893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1861 17:14:42.952718 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1863 17:14:43.042070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1864 17:14:43.042829 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1866 17:14:43.129797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1867 17:14:43.130585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1869 17:14:43.221728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1870 17:14:43.222477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1872 17:14:43.313651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1873 17:14:43.314388 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1875 17:14:43.396240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1876 17:14:43.397027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1878 17:14:43.486645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1879 17:14:43.487430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1881 17:14:43.572288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1882 17:14:43.573060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1884 17:14:43.657964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1885 17:14:43.658753 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1887 17:14:43.750832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1888 17:14:43.751578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1890 17:14:43.839493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1891 17:14:43.840399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1893 17:14:43.925594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1894 17:14:43.926388 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1896 17:14:44.009946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1897 17:14:44.010745 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1899 17:14:44.102853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1900 17:14:44.103709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1902 17:14:44.191903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1903 17:14:44.192765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1905 17:14:44.282407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1906 17:14:44.283168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1908 17:14:44.373070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1909 17:14:44.373885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1911 17:14:44.458285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1912 17:14:44.459164 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1914 17:14:44.552313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1915 17:14:44.553179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1917 17:14:44.646156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1918 17:14:44.647006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1920 17:14:44.736409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1921 17:14:44.737277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1923 17:14:44.818976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1924 17:14:44.819886 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1926 17:14:44.905966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1927 17:14:44.906803 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1929 17:14:45.000463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1930 17:14:45.001323 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1932 17:14:45.092020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1933 17:14:45.092916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1935 17:14:45.183183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1936 17:14:45.184051 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1938 17:14:45.270090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1939 17:14:45.270941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1941 17:14:45.361096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1942 17:14:45.361909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1944 17:14:45.446139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1945 17:14:45.446924 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1947 17:14:45.536270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1948 17:14:45.537059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1950 17:14:45.621072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1952 17:14:45.624158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1953 17:14:45.711901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1955 17:14:45.715005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1956 17:14:45.797895 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1958 17:14:45.800834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1959 17:14:45.894873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1960 17:14:45.895762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1962 17:14:45.984689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1963 17:14:45.985516 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1965 17:14:46.073647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1966 17:14:46.074529 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1968 17:14:46.160306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1969 17:14:46.161145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1971 17:14:46.245897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1972 17:14:46.246735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1974 17:14:46.332871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1975 17:14:46.333681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1977 17:14:46.423357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1978 17:14:46.424167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1980 17:14:46.509756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1981 17:14:46.510585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1983 17:14:46.599781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1984 17:14:46.600639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1986 17:14:46.686376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1987 17:14:46.687164 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1989 17:14:46.771514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1990 17:14:46.772381 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1992 17:14:46.862409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1993 17:14:46.863218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1995 17:14:46.946648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1996 17:14:46.947450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1998 17:14:47.039033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1999 17:14:47.039842 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2001 17:14:47.132397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2002 17:14:47.133185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2004 17:14:47.222937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2005 17:14:47.223751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2007 17:14:47.311882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2008 17:14:47.312714 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2010 17:14:47.401452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2011 17:14:47.402249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2013 17:14:47.487659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2014 17:14:47.488497 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2016 17:14:47.578021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2017 17:14:47.578895 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2019 17:14:47.661916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2020 17:14:47.662771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2022 17:14:47.748781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2023 17:14:47.749648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2025 17:14:47.834853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2026 17:14:47.835601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2028 17:14:47.925440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2029 17:14:47.926195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2031 17:14:48.016879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2032 17:14:48.017652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2034 17:14:48.109543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2035 17:14:48.110415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2037 17:14:48.199515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2038 17:14:48.200393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2040 17:14:48.288254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2041 17:14:48.289072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2043 17:14:48.378357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2044 17:14:48.379231 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2046 17:14:48.463410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2047 17:14:48.464189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2049 17:14:48.548846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2050 17:14:48.549620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2052 17:14:48.640520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2053 17:14:48.641348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2055 17:14:48.730524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2056 17:14:48.731383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2058 17:14:48.816350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2059 17:14:48.817147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2061 17:14:48.908478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2062 17:14:48.909315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2064 17:14:49.000120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2065 17:14:49.001046 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2067 17:14:49.083312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2068 17:14:49.084129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2070 17:14:49.176438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2071 17:14:49.177314 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2073 17:14:49.261266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2074 17:14:49.262081 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2076 17:14:49.354631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2077 17:14:49.355601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2079 17:14:49.459860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2080 17:14:49.460792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2082 17:14:49.555172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2083 17:14:49.556349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2085 17:14:49.646287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2086 17:14:49.647011 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2088 17:14:49.738866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2089 17:14:49.739633 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2091 17:14:49.828845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2092 17:14:49.829599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2094 17:14:49.915685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2095 17:14:49.916432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2097 17:14:50.001687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2098 17:14:50.002419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2100 17:14:50.088028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2101 17:14:50.088762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2103 17:14:50.172817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2104 17:14:50.173547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2106 17:14:50.259706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2107 17:14:50.260470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2109 17:14:50.349658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2110 17:14:50.350426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2112 17:14:50.436426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2113 17:14:50.437178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2115 17:14:50.525477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2116 17:14:50.526217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2118 17:14:50.613136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2119 17:14:50.613908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2121 17:14:50.699504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2122 17:14:50.700287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2124 17:14:50.791579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2125 17:14:50.792325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2127 17:14:50.878353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2128 17:14:50.879083 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2130 17:14:50.969365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2131 17:14:50.970104 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2133 17:14:51.061382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2134 17:14:51.062166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2136 17:14:51.150803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2137 17:14:51.151431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2139 17:14:51.237888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2140 17:14:51.238499 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2142 17:14:51.328042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2143 17:14:51.328779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2145 17:14:51.420550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2146 17:14:51.421154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2148 17:14:51.509151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2149 17:14:51.509939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2151 17:14:51.594003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2152 17:14:51.594806 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2154 17:14:51.686086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2155 17:14:51.686837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2157 17:14:51.777315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2158 17:14:51.778063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2160 17:14:51.863407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2161 17:14:51.864166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2163 17:14:51.955105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2164 17:14:51.955855 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2166 17:14:52.040885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2167 17:14:52.041706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2169 17:14:52.127156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2170 17:14:52.128018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2172 17:14:52.212990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2173 17:14:52.213769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2175 17:14:52.304558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2176 17:14:52.305305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2178 17:14:52.395335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2179 17:14:52.396116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2181 17:14:52.482523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2182 17:14:52.483292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2184 17:14:52.571720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2185 17:14:52.572565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2187 17:14:52.658840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2188 17:14:52.659580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2190 17:14:52.746623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2191 17:14:52.747532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2193 17:14:52.836653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2194 17:14:52.837510 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2196 17:14:52.930271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2197 17:14:52.931101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2199 17:14:53.020919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2200 17:14:53.021749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2202 17:14:53.109775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2203 17:14:53.110515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2205 17:14:53.199443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2206 17:14:53.200156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2208 17:14:53.285450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2209 17:14:53.286184 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2211 17:14:53.378300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2212 17:14:53.379029 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2214 17:14:53.469899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2215 17:14:53.470658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2217 17:14:53.558036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2218 17:14:53.558795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2220 17:14:53.646870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2221 17:14:53.647603 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2223 17:14:53.737878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2224 17:14:53.738611 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2226 17:14:53.830789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2227 17:14:53.831508 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2229 17:14:53.917504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2230 17:14:53.918228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2232 17:14:54.008214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2233 17:14:54.008953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2235 17:14:54.100844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2236 17:14:54.101578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2238 17:14:54.187675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2239 17:14:54.188469 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2241 17:14:54.280933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2242 17:14:54.281668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2244 17:14:54.371168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2245 17:14:54.371931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2247 17:14:54.457462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2248 17:14:54.458237 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2250 17:14:54.550012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2251 17:14:54.550817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2253 17:14:54.638325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2254 17:14:54.639112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2256 17:14:54.727444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2257 17:14:54.728273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2259 17:14:54.818585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2260 17:14:54.819427 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2262 17:14:54.920265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2263 17:14:54.921146 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2265 17:14:55.013861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2266 17:14:55.014620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2268 17:14:55.107109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2269 17:14:55.107888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2271 17:14:55.195935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2273 17:14:55.199074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2274 17:14:55.281995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2275 17:14:55.282739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2277 17:14:55.374860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2278 17:14:55.375609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2280 17:14:55.476801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2281 17:14:55.477596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2283 17:14:55.567466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2284 17:14:55.568311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2286 17:14:55.653087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2287 17:14:55.653854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2289 17:14:55.746987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2290 17:14:55.747769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2292 17:14:55.838056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2293 17:14:55.838838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2295 17:14:55.930154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2296 17:14:55.930917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2298 17:14:56.016482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2299 17:14:56.017266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2301 17:14:56.106375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2302 17:14:56.107161 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2304 17:14:56.190498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2305 17:14:56.191274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2307 17:14:56.275817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2308 17:14:56.276607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2310 17:14:56.368285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2311 17:14:56.369001 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2313 17:14:56.457666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2314 17:14:56.458386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2316 17:14:56.544591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2317 17:14:56.545372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2319 17:14:56.636374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2320 17:14:56.637117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2322 17:14:56.723004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2323 17:14:56.723734 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2325 17:14:56.817310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2326 17:14:56.818041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2328 17:14:56.909159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2329 17:14:56.909875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2331 17:14:56.995697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2332 17:14:56.996484 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2334 17:14:57.085640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2335 17:14:57.086356 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2337 17:14:57.170983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2338 17:14:57.171691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2340 17:14:57.263317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2341 17:14:57.264077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2343 17:14:57.355768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2344 17:14:57.356546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2346 17:14:57.439863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2347 17:14:57.440637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2349 17:14:57.530225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2350 17:14:57.530988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2352 17:14:57.617830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2353 17:14:57.618578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2355 17:14:57.709876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2356 17:14:57.710630 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2358 17:14:57.797261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2359 17:14:57.797990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2361 17:14:57.889384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2362 17:14:57.890171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2364 17:14:57.977272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2365 17:14:57.977765 + set +x
2366 17:14:57.978407 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2368 17:14:57.984467 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 935269_1.6.2.4.5>
2369 17:14:57.984893 <LAVA_TEST_RUNNER EXIT>
2370 17:14:57.985519 Received signal: <ENDRUN> 1_kselftest-dt 935269_1.6.2.4.5
2371 17:14:57.985947 Ending use of test pattern.
2372 17:14:57.986335 Ending test lava.1_kselftest-dt (935269_1.6.2.4.5), duration 82.78
2374 17:14:57.987796 ok: lava_test_shell seems to have completed
2375 17:14:58.000432 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2376 17:14:58.002276 end: 3.1 lava-test-shell (duration 00:01:24) [common]
2377 17:14:58.002793 end: 3 lava-test-retry (duration 00:01:24) [common]
2378 17:14:58.003332 start: 4 finalize (timeout 00:05:32) [common]
2379 17:14:58.003865 start: 4.1 power-off (timeout 00:00:30) [common]
2380 17:14:58.004842 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-01'
2381 17:14:58.039185 >> OK - accepted request
2382 17:14:58.041312 Returned 0 in 0 seconds
2383 17:14:58.142478 end: 4.1 power-off (duration 00:00:00) [common]
2385 17:14:58.144258 start: 4.2 read-feedback (timeout 00:05:32) [common]
2386 17:14:58.145359 Listened to connection for namespace 'common' for up to 1s
2387 17:14:58.146214 Listened to connection for namespace 'common' for up to 1s
2388 17:14:59.146156 Finalising connection for namespace 'common'
2389 17:14:59.146880 Disconnecting from shell: Finalise
2390 17:14:59.147403 / #
2391 17:14:59.248326 end: 4.2 read-feedback (duration 00:00:01) [common]
2392 17:14:59.249008 end: 4 finalize (duration 00:00:01) [common]
2393 17:14:59.249669 Cleaning after the job
2394 17:14:59.250261 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935269/tftp-deploy-9x3d1pu7/ramdisk
2395 17:14:59.252678 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935269/tftp-deploy-9x3d1pu7/kernel
2396 17:14:59.254641 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935269/tftp-deploy-9x3d1pu7/dtb
2397 17:14:59.255764 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935269/tftp-deploy-9x3d1pu7/nfsrootfs
2398 17:14:59.342687 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935269/tftp-deploy-9x3d1pu7/modules
2399 17:14:59.351328 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/935269
2400 17:15:02.285689 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/935269
2401 17:15:02.286256 Job finished correctly