Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 22:16:30.819376 lava-dispatcher, installed at version: 2024.01
2 22:16:30.820184 start: 0 validate
3 22:16:30.820679 Start time: 2024-11-08 22:16:30.820649+00:00 (UTC)
4 22:16:30.821233 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 22:16:30.821769 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 22:16:30.854218 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 22:16:30.854779 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-regmap%2Ffor-next%2Fv6.12-rc3-8-gd1f4390dd28b%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 22:16:30.877941 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 22:16:30.878597 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-regmap%2Ffor-next%2Fv6.12-rc3-8-gd1f4390dd28b%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 22:16:30.902722 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 22:16:30.903250 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 22:16:30.926240 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 22:16:30.926737 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-regmap%2Ffor-next%2Fv6.12-rc3-8-gd1f4390dd28b%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 22:16:30.956725 validate duration: 0.14
16 22:16:30.957656 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:16:30.958020 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:16:30.958318 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:16:30.958944 Not decompressing ramdisk as can be used compressed.
20 22:16:30.959396 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 22:16:30.959673 saving as /var/lib/lava/dispatcher/tmp/962873/tftp-deploy-z5xrqvop/ramdisk/initrd.cpio.gz
22 22:16:30.959941 total size: 4775763 (4 MB)
23 22:16:30.985549 progress 0 % (0 MB)
24 22:16:30.989602 progress 5 % (0 MB)
25 22:16:30.992808 progress 10 % (0 MB)
26 22:16:30.995887 progress 15 % (0 MB)
27 22:16:30.999295 progress 20 % (0 MB)
28 22:16:31.002354 progress 25 % (1 MB)
29 22:16:31.005416 progress 30 % (1 MB)
30 22:16:31.008882 progress 35 % (1 MB)
31 22:16:31.011905 progress 40 % (1 MB)
32 22:16:31.014863 progress 45 % (2 MB)
33 22:16:31.017828 progress 50 % (2 MB)
34 22:16:31.021197 progress 55 % (2 MB)
35 22:16:31.024215 progress 60 % (2 MB)
36 22:16:31.027226 progress 65 % (2 MB)
37 22:16:31.030545 progress 70 % (3 MB)
38 22:16:31.033504 progress 75 % (3 MB)
39 22:16:31.036477 progress 80 % (3 MB)
40 22:16:31.039471 progress 85 % (3 MB)
41 22:16:31.043238 progress 90 % (4 MB)
42 22:16:31.046306 progress 95 % (4 MB)
43 22:16:31.049263 progress 100 % (4 MB)
44 22:16:31.049939 4 MB downloaded in 0.09 s (50.62 MB/s)
45 22:16:31.050528 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:16:31.051431 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:16:31.051744 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:16:31.052030 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:16:31.052663 downloading http://storage.kernelci.org/broonie-regmap/for-next/v6.12-rc3-8-gd1f4390dd28b/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 22:16:31.052938 saving as /var/lib/lava/dispatcher/tmp/962873/tftp-deploy-z5xrqvop/kernel/zImage
52 22:16:31.053183 total size: 11444736 (10 MB)
53 22:16:31.053411 No compression specified
54 22:16:31.080705 progress 0 % (0 MB)
55 22:16:31.088805 progress 5 % (0 MB)
56 22:16:31.095950 progress 10 % (1 MB)
57 22:16:31.103374 progress 15 % (1 MB)
58 22:16:31.110346 progress 20 % (2 MB)
59 22:16:31.117836 progress 25 % (2 MB)
60 22:16:31.124960 progress 30 % (3 MB)
61 22:16:31.132463 progress 35 % (3 MB)
62 22:16:31.139765 progress 40 % (4 MB)
63 22:16:31.147497 progress 45 % (4 MB)
64 22:16:31.154445 progress 50 % (5 MB)
65 22:16:31.161660 progress 55 % (6 MB)
66 22:16:31.168582 progress 60 % (6 MB)
67 22:16:31.176240 progress 65 % (7 MB)
68 22:16:31.183209 progress 70 % (7 MB)
69 22:16:31.190166 progress 75 % (8 MB)
70 22:16:31.197109 progress 80 % (8 MB)
71 22:16:31.203692 progress 85 % (9 MB)
72 22:16:31.212825 progress 90 % (9 MB)
73 22:16:31.219636 progress 95 % (10 MB)
74 22:16:31.226686 progress 100 % (10 MB)
75 22:16:31.227178 10 MB downloaded in 0.17 s (62.73 MB/s)
76 22:16:31.227645 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:16:31.228519 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:16:31.228815 start: 1.3 download-retry (timeout 00:10:00) [common]
80 22:16:31.229077 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 22:16:31.229546 downloading http://storage.kernelci.org/broonie-regmap/for-next/v6.12-rc3-8-gd1f4390dd28b/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 22:16:31.229784 saving as /var/lib/lava/dispatcher/tmp/962873/tftp-deploy-z5xrqvop/dtb/am335x-boneblack.dtb
83 22:16:31.230135 total size: 70568 (0 MB)
84 22:16:31.230364 No compression specified
85 22:16:31.256206 progress 46 % (0 MB)
86 22:16:31.257040 progress 92 % (0 MB)
87 22:16:31.257741 progress 100 % (0 MB)
88 22:16:31.258176 0 MB downloaded in 0.03 s (2.40 MB/s)
89 22:16:31.258627 end: 1.3.1 http-download (duration 00:00:00) [common]
91 22:16:31.259432 end: 1.3 download-retry (duration 00:00:00) [common]
92 22:16:31.259694 start: 1.4 download-retry (timeout 00:10:00) [common]
93 22:16:31.259956 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 22:16:31.260418 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 22:16:31.260653 saving as /var/lib/lava/dispatcher/tmp/962873/tftp-deploy-z5xrqvop/nfsrootfs/full.rootfs.tar
96 22:16:31.260854 total size: 117747780 (112 MB)
97 22:16:31.261061 Using unxz to decompress xz
98 22:16:31.293759 progress 0 % (0 MB)
99 22:16:32.017050 progress 5 % (5 MB)
100 22:16:32.760523 progress 10 % (11 MB)
101 22:16:33.526527 progress 15 % (16 MB)
102 22:16:34.239966 progress 20 % (22 MB)
103 22:16:34.814700 progress 25 % (28 MB)
104 22:16:35.615651 progress 30 % (33 MB)
105 22:16:36.415990 progress 35 % (39 MB)
106 22:16:36.743792 progress 40 % (44 MB)
107 22:16:37.107050 progress 45 % (50 MB)
108 22:16:37.757597 progress 50 % (56 MB)
109 22:16:38.555668 progress 55 % (61 MB)
110 22:16:39.280113 progress 60 % (67 MB)
111 22:16:39.987670 progress 65 % (73 MB)
112 22:16:40.741432 progress 70 % (78 MB)
113 22:16:41.496986 progress 75 % (84 MB)
114 22:16:42.220829 progress 80 % (89 MB)
115 22:16:42.925024 progress 85 % (95 MB)
116 22:16:43.709228 progress 90 % (101 MB)
117 22:16:44.465238 progress 95 % (106 MB)
118 22:16:45.272685 progress 100 % (112 MB)
119 22:16:45.284946 112 MB downloaded in 14.02 s (8.01 MB/s)
120 22:16:45.285956 end: 1.4.1 http-download (duration 00:00:14) [common]
122 22:16:45.287929 end: 1.4 download-retry (duration 00:00:14) [common]
123 22:16:45.288511 start: 1.5 download-retry (timeout 00:09:46) [common]
124 22:16:45.289075 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 22:16:45.290020 downloading http://storage.kernelci.org/broonie-regmap/for-next/v6.12-rc3-8-gd1f4390dd28b/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 22:16:45.290561 saving as /var/lib/lava/dispatcher/tmp/962873/tftp-deploy-z5xrqvop/modules/modules.tar
127 22:16:45.291013 total size: 6608648 (6 MB)
128 22:16:45.291470 Using unxz to decompress xz
129 22:16:45.331850 progress 0 % (0 MB)
130 22:16:45.366894 progress 5 % (0 MB)
131 22:16:45.409726 progress 10 % (0 MB)
132 22:16:45.453973 progress 15 % (0 MB)
133 22:16:45.499557 progress 20 % (1 MB)
134 22:16:45.547235 progress 25 % (1 MB)
135 22:16:45.591214 progress 30 % (1 MB)
136 22:16:45.633508 progress 35 % (2 MB)
137 22:16:45.677166 progress 40 % (2 MB)
138 22:16:45.720173 progress 45 % (2 MB)
139 22:16:45.763740 progress 50 % (3 MB)
140 22:16:45.806322 progress 55 % (3 MB)
141 22:16:45.855914 progress 60 % (3 MB)
142 22:16:45.898163 progress 65 % (4 MB)
143 22:16:45.941361 progress 70 % (4 MB)
144 22:16:45.987728 progress 75 % (4 MB)
145 22:16:46.030733 progress 80 % (5 MB)
146 22:16:46.073898 progress 85 % (5 MB)
147 22:16:46.116660 progress 90 % (5 MB)
148 22:16:46.160210 progress 95 % (6 MB)
149 22:16:46.204115 progress 100 % (6 MB)
150 22:16:46.217679 6 MB downloaded in 0.93 s (6.80 MB/s)
151 22:16:46.218314 end: 1.5.1 http-download (duration 00:00:01) [common]
153 22:16:46.219204 end: 1.5 download-retry (duration 00:00:01) [common]
154 22:16:46.219495 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 22:16:46.219781 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 22:17:03.760666 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/962873/extract-nfsrootfs-7xjd04yq
157 22:17:03.761307 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
158 22:17:03.761604 start: 1.6.2 lava-overlay (timeout 00:09:27) [common]
159 22:17:03.762296 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363
160 22:17:03.762780 makedir: /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin
161 22:17:03.763121 makedir: /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/tests
162 22:17:03.763438 makedir: /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/results
163 22:17:03.763791 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-add-keys
164 22:17:03.764439 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-add-sources
165 22:17:03.765061 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-background-process-start
166 22:17:03.765747 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-background-process-stop
167 22:17:03.766484 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-common-functions
168 22:17:03.767051 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-echo-ipv4
169 22:17:03.767606 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-install-packages
170 22:17:03.768170 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-installed-packages
171 22:17:03.768721 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-os-build
172 22:17:03.769325 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-probe-channel
173 22:17:03.769943 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-probe-ip
174 22:17:03.770529 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-target-ip
175 22:17:03.771097 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-target-mac
176 22:17:03.771635 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-target-storage
177 22:17:03.772181 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-test-case
178 22:17:03.772705 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-test-event
179 22:17:03.773247 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-test-feedback
180 22:17:03.773912 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-test-raise
181 22:17:03.774576 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-test-reference
182 22:17:03.775177 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-test-runner
183 22:17:03.775708 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-test-set
184 22:17:03.776218 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-test-shell
185 22:17:03.776720 Updating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-add-keys (debian)
186 22:17:03.777267 Updating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-add-sources (debian)
187 22:17:03.777858 Updating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-install-packages (debian)
188 22:17:03.778604 Updating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-installed-packages (debian)
189 22:17:03.779207 Updating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/bin/lava-os-build (debian)
190 22:17:03.779701 Creating /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/environment
191 22:17:03.780140 LAVA metadata
192 22:17:03.780428 - LAVA_JOB_ID=962873
193 22:17:03.780652 - LAVA_DISPATCHER_IP=192.168.6.3
194 22:17:03.781065 start: 1.6.2.1 ssh-authorize (timeout 00:09:27) [common]
195 22:17:03.782185 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 22:17:03.782595 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:27) [common]
197 22:17:03.782811 skipped lava-vland-overlay
198 22:17:03.783057 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 22:17:03.783315 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:27) [common]
200 22:17:03.783542 skipped lava-multinode-overlay
201 22:17:03.783791 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 22:17:03.784048 start: 1.6.2.4 test-definition (timeout 00:09:27) [common]
203 22:17:03.784310 Loading test definitions
204 22:17:03.784595 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:27) [common]
205 22:17:03.784835 Using /lava-962873 at stage 0
206 22:17:03.786089 uuid=962873_1.6.2.4.1 testdef=None
207 22:17:03.786445 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 22:17:03.786713 start: 1.6.2.4.2 test-overlay (timeout 00:09:27) [common]
209 22:17:03.788418 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 22:17:03.789314 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:27) [common]
212 22:17:03.791587 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 22:17:03.792493 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:27) [common]
215 22:17:03.794570 runner path: /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/0/tests/0_timesync-off test_uuid 962873_1.6.2.4.1
216 22:17:03.795312 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 22:17:03.796195 start: 1.6.2.4.5 git-repo-action (timeout 00:09:27) [common]
219 22:17:03.796448 Using /lava-962873 at stage 0
220 22:17:03.796836 Fetching tests from https://github.com/kernelci/test-definitions.git
221 22:17:03.797130 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/0/tests/1_kselftest-dt'
222 22:17:07.591850 Running '/usr/bin/git checkout kernelci.org
223 22:17:08.035530 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 22:17:08.037004 uuid=962873_1.6.2.4.5 testdef=None
225 22:17:08.037364 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 22:17:08.038187 start: 1.6.2.4.6 test-overlay (timeout 00:09:23) [common]
228 22:17:08.041065 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 22:17:08.041934 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:23) [common]
231 22:17:08.045707 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 22:17:08.046633 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:23) [common]
234 22:17:08.050308 runner path: /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/0/tests/1_kselftest-dt test_uuid 962873_1.6.2.4.5
235 22:17:08.050608 BOARD='beaglebone-black'
236 22:17:08.050825 BRANCH='broonie-regmap'
237 22:17:08.051029 SKIPFILE='/dev/null'
238 22:17:08.051231 SKIP_INSTALL='True'
239 22:17:08.051431 TESTPROG_URL='http://storage.kernelci.org/broonie-regmap/for-next/v6.12-rc3-8-gd1f4390dd28b/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 22:17:08.051662 TST_CASENAME=''
241 22:17:08.051864 TST_CMDFILES='dt'
242 22:17:08.052437 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 22:17:08.053245 Creating lava-test-runner.conf files
245 22:17:08.053460 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/962873/lava-overlay-hzb1y363/lava-962873/0 for stage 0
246 22:17:08.053851 - 0_timesync-off
247 22:17:08.054114 - 1_kselftest-dt
248 22:17:08.054470 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 22:17:08.054768 start: 1.6.2.5 compress-overlay (timeout 00:09:23) [common]
250 22:17:31.366906 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 22:17:31.367342 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
252 22:17:31.367607 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 22:17:31.367878 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 22:17:31.368142 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
255 22:17:31.726581 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 22:17:31.727064 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
257 22:17:31.727334 extracting modules file /var/lib/lava/dispatcher/tmp/962873/tftp-deploy-z5xrqvop/modules/modules.tar to /var/lib/lava/dispatcher/tmp/962873/extract-nfsrootfs-7xjd04yq
258 22:17:32.751281 extracting modules file /var/lib/lava/dispatcher/tmp/962873/tftp-deploy-z5xrqvop/modules/modules.tar to /var/lib/lava/dispatcher/tmp/962873/extract-overlay-ramdisk-fefpstga/ramdisk
259 22:17:33.671339 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 22:17:33.671824 start: 1.6.5 apply-overlay-tftp (timeout 00:08:57) [common]
261 22:17:33.672122 [common] Applying overlay to NFS
262 22:17:33.672350 [common] Applying overlay /var/lib/lava/dispatcher/tmp/962873/compress-overlay-jdpwa_st/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/962873/extract-nfsrootfs-7xjd04yq
263 22:17:36.399457 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 22:17:36.399939 start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
265 22:17:36.400243 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
266 22:17:36.400561 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 22:17:36.400843 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 22:17:36.401114 start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
269 22:17:36.401383 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 22:17:36.401664 start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
271 22:17:36.401963 Building ramdisk /var/lib/lava/dispatcher/tmp/962873/extract-overlay-ramdisk-fefpstga/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/962873/extract-overlay-ramdisk-fefpstga/ramdisk
272 22:17:37.400620 >> 74887 blocks
273 22:17:42.038893 Adding RAMdisk u-boot header.
274 22:17:42.039480 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/962873/extract-overlay-ramdisk-fefpstga/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/962873/extract-overlay-ramdisk-fefpstga/ramdisk.cpio.gz.uboot
275 22:17:42.202844 output: Image Name:
276 22:17:42.203275 output: Created: Fri Nov 8 22:17:42 2024
277 22:17:42.203492 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 22:17:42.203700 output: Data Size: 14791586 Bytes = 14444.91 KiB = 14.11 MiB
279 22:17:42.203904 output: Load Address: 00000000
280 22:17:42.204103 output: Entry Point: 00000000
281 22:17:42.204301 output:
282 22:17:42.204949 rename /var/lib/lava/dispatcher/tmp/962873/extract-overlay-ramdisk-fefpstga/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/962873/tftp-deploy-z5xrqvop/ramdisk/ramdisk.cpio.gz.uboot
283 22:17:42.205552 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 22:17:42.206204 end: 1.6 prepare-tftp-overlay (duration 00:00:56) [common]
285 22:17:42.206746 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:49) [common]
286 22:17:42.207201 No LXC device requested
287 22:17:42.207700 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 22:17:42.208207 start: 1.8 deploy-device-env (timeout 00:08:49) [common]
289 22:17:42.208695 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 22:17:42.209103 Checking files for TFTP limit of 4294967296 bytes.
291 22:17:42.211809 end: 1 tftp-deploy (duration 00:01:11) [common]
292 22:17:42.212393 start: 2 uboot-action (timeout 00:05:00) [common]
293 22:17:42.212920 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 22:17:42.213413 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 22:17:42.213933 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 22:17:42.214691 substitutions:
297 22:17:42.215107 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 22:17:42.215509 - {DTB_ADDR}: 0x88000000
299 22:17:42.215907 - {DTB}: 962873/tftp-deploy-z5xrqvop/dtb/am335x-boneblack.dtb
300 22:17:42.216300 - {INITRD}: 962873/tftp-deploy-z5xrqvop/ramdisk/ramdisk.cpio.gz.uboot
301 22:17:42.216690 - {KERNEL_ADDR}: 0x82000000
302 22:17:42.217076 - {KERNEL}: 962873/tftp-deploy-z5xrqvop/kernel/zImage
303 22:17:42.217462 - {LAVA_MAC}: None
304 22:17:42.217917 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/962873/extract-nfsrootfs-7xjd04yq
305 22:17:42.218322 - {NFS_SERVER_IP}: 192.168.6.3
306 22:17:42.218713 - {PRESEED_CONFIG}: None
307 22:17:42.219097 - {PRESEED_LOCAL}: None
308 22:17:42.219480 - {RAMDISK_ADDR}: 0x83000000
309 22:17:42.219862 - {RAMDISK}: 962873/tftp-deploy-z5xrqvop/ramdisk/ramdisk.cpio.gz.uboot
310 22:17:42.220249 - {ROOT_PART}: None
311 22:17:42.220627 - {ROOT}: None
312 22:17:42.221010 - {SERVER_IP}: 192.168.6.3
313 22:17:42.221389 - {TEE_ADDR}: 0x83000000
314 22:17:42.221765 - {TEE}: None
315 22:17:42.222171 Parsed boot commands:
316 22:17:42.222544 - setenv autoload no
317 22:17:42.222923 - setenv initrd_high 0xffffffff
318 22:17:42.223302 - setenv fdt_high 0xffffffff
319 22:17:42.223679 - dhcp
320 22:17:42.224053 - setenv serverip 192.168.6.3
321 22:17:42.224431 - tftp 0x82000000 962873/tftp-deploy-z5xrqvop/kernel/zImage
322 22:17:42.224812 - tftp 0x83000000 962873/tftp-deploy-z5xrqvop/ramdisk/ramdisk.cpio.gz.uboot
323 22:17:42.225188 - setenv initrd_size ${filesize}
324 22:17:42.225565 - tftp 0x88000000 962873/tftp-deploy-z5xrqvop/dtb/am335x-boneblack.dtb
325 22:17:42.225970 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/962873/extract-nfsrootfs-7xjd04yq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 22:17:42.226363 - bootz 0x82000000 0x83000000 0x88000000
327 22:17:42.226852 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 22:17:42.228315 start: 2.3 connect-device (timeout 00:05:00) [common]
330 22:17:42.228734 [common] connect-device Connecting to device using 'telnet conserv3 3000'
331 22:17:42.243574 Setting prompt string to ['lava-test: # ']
332 22:17:42.245064 end: 2.3 connect-device (duration 00:00:00) [common]
333 22:17:42.245661 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 22:17:42.246290 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 22:17:42.246820 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 22:17:42.248013 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-03'
337 22:17:42.283371 >> OK - accepted request
338 22:17:42.285638 Returned 0 in 0 seconds
339 22:17:42.386850 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 22:17:42.388847 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 22:17:42.389437 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 22:17:42.390029 Setting prompt string to ['Hit any key to stop autoboot']
344 22:17:42.390529 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 22:17:42.392121 Trying 192.168.56.22...
346 22:17:42.392632 Connected to conserv3.
347 22:17:42.393063 Escape character is '^]'.
348 22:17:42.393496
349 22:17:42.393965 ser2net port telnet,3000 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 22:17:42.394401
351 22:17:50.943524
352 22:17:50.950420 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
353 22:17:50.950806 Trying to boot from MMC1
354 22:17:51.537521
355 22:17:51.538629
356 22:17:51.543018 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
357 22:17:51.543796
358 22:17:51.544489 CPU : AM335X-GP rev 2.0
359 22:17:51.548192 Model: TI AM335x BeagleBone Black
360 22:17:51.548991 DRAM: 512 MiB
361 22:17:54.996934
362 22:17:55.003514 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
363 22:17:55.003904 Trying to boot from MMC1
364 22:17:55.589696
365 22:17:55.590194
366 22:17:55.595016 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
367 22:17:55.595347
368 22:17:55.595594 CPU : AM335X-GP rev 2.0
369 22:17:55.600227 Model: TI AM335x BeagleBone Black
370 22:17:55.600701 DRAM: 512 MiB
371 22:17:57.693515
372 22:17:57.700488 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
373 22:17:57.700903 Trying to boot from MMC1
374 22:17:58.286759
375 22:17:58.287187
376 22:17:58.292282 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
377 22:17:58.292589
378 22:17:58.292825 CPU : AM335X-GP rev 2.0
379 22:17:58.297382 Model: TI AM335x BeagleBone Black
380 22:17:58.297775 DRAM: 512 MiB
381 22:17:58.381925 Core: 160 devices, 18 uclasses, devicetree: separate
382 22:17:58.394753 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
383 22:17:58.796581 NAND: 0 MiB
384 22:17:58.806638 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
385 22:17:58.880908 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
386 22:17:58.902755 <ethaddr> not set. Validating first E-fuse MAC
387 22:17:58.932542 Net: eth2: ethernet@4a100000, eth3: usb_ether
389 22:17:58.991139 Hit any key to stop autoboot: 2
390 22:17:58.991807 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
391 22:17:58.992174 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
392 22:17:58.992469 Setting prompt string to ['=>']
393 22:17:58.992764 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
394 22:17:58.999890 0
395 22:17:59.000519 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
396 22:17:59.000834 Sending with 10 millisecond of delay
398 22:18:00.135804 => setenv autoload no
399 22:18:00.146652 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
400 22:18:00.152061 setenv autoload no
401 22:18:00.152860 Sending with 10 millisecond of delay
403 22:18:01.949758 => setenv initrd_high 0xffffffff
404 22:18:01.960297 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
405 22:18:01.960765 setenv initrd_high 0xffffffff
406 22:18:01.961240 Sending with 10 millisecond of delay
408 22:18:03.577658 => setenv fdt_high 0xffffffff
409 22:18:03.588486 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
410 22:18:03.589381 setenv fdt_high 0xffffffff
411 22:18:03.590117 Sending with 10 millisecond of delay
413 22:18:03.882309 => dhcp
414 22:18:03.893054 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
415 22:18:03.893863 dhcp
416 22:18:03.895456 link up on port 0, speed 100, full duplex
417 22:18:03.895885 BOOTP broadcast 1
418 22:18:04.147640 BOOTP broadcast 2
419 22:18:04.648960 BOOTP broadcast 3
420 22:18:05.651821 BOOTP broadcast 4
421 22:18:05.734890 DHCP client bound to address 192.168.6.23 (1836 ms)
422 22:18:05.735836 Sending with 10 millisecond of delay
424 22:18:07.420991 => setenv serverip 192.168.6.3
425 22:18:07.431630 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
426 22:18:07.432229 setenv serverip 192.168.6.3
427 22:18:07.432728 Sending with 10 millisecond of delay
429 22:18:10.918415 => tftp 0x82000000 962873/tftp-deploy-z5xrqvop/kernel/zImage
430 22:18:10.929185 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:31)
431 22:18:10.930052 tftp 0x82000000 962873/tftp-deploy-z5xrqvop/kernel/zImage
432 22:18:10.930491 link up on port 0, speed 100, full duplex
433 22:18:10.933462 Using ethernet@4a100000 device
434 22:18:10.939161 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
435 22:18:10.946387 Filename '962873/tftp-deploy-z5xrqvop/kernel/zImage'.
436 22:18:10.946818 Load address: 0x82000000
437 22:18:12.997437 Loading: *################################################## 10.9 MiB
438 22:18:12.997875 5.3 MiB/s
439 22:18:12.998098 done
440 22:18:13.001591 Bytes transferred = 11444736 (aea200 hex)
441 22:18:13.002217 Sending with 10 millisecond of delay
443 22:18:17.448666 => tftp 0x83000000 962873/tftp-deploy-z5xrqvop/ramdisk/ramdisk.cpio.gz.uboot
444 22:18:17.459495 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
445 22:18:17.460460 tftp 0x83000000 962873/tftp-deploy-z5xrqvop/ramdisk/ramdisk.cpio.gz.uboot
446 22:18:17.460922 link up on port 0, speed 100, full duplex
447 22:18:17.463900 Using ethernet@4a100000 device
448 22:18:17.469508 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
449 22:18:17.478240 Filename '962873/tftp-deploy-z5xrqvop/ramdisk/ramdisk.cpio.gz.uboot'.
450 22:18:17.478747 Load address: 0x83000000
451 22:18:20.281410 Loading: *################################################## 14.1 MiB
452 22:18:20.282114 5 MiB/s
453 22:18:20.282587 done
454 22:18:20.285492 Bytes transferred = 14791650 (e1b3e2 hex)
455 22:18:20.286356 Sending with 10 millisecond of delay
457 22:18:22.144006 => setenv initrd_size ${filesize}
458 22:18:22.154805 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
459 22:18:22.155645 setenv initrd_size ${filesize}
460 22:18:22.156396 Sending with 10 millisecond of delay
462 22:18:26.302818 => tftp 0x88000000 962873/tftp-deploy-z5xrqvop/dtb/am335x-boneblack.dtb
463 22:18:26.313310 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
464 22:18:26.313842 tftp 0x88000000 962873/tftp-deploy-z5xrqvop/dtb/am335x-boneblack.dtb
465 22:18:26.314827 link up on port 0, speed 100, full duplex
466 22:18:26.317919 Using ethernet@4a100000 device
467 22:18:26.323436 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
468 22:18:26.334554 Filename '962873/tftp-deploy-z5xrqvop/dtb/am335x-boneblack.dtb'.
469 22:18:26.334896 Load address: 0x88000000
470 22:18:26.345130 Loading: *################################################## 68.9 KiB
471 22:18:26.345449 4.5 MiB/s
472 22:18:26.353873 done
473 22:18:26.354231 Bytes transferred = 70568 (113a8 hex)
474 22:18:26.354680 Sending with 10 millisecond of delay
476 22:18:39.542468 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/962873/extract-nfsrootfs-7xjd04yq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
477 22:18:39.553337 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
478 22:18:39.554336 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/962873/extract-nfsrootfs-7xjd04yq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
479 22:18:39.555053 Sending with 10 millisecond of delay
481 22:18:41.896186 => bootz 0x82000000 0x83000000 0x88000000
482 22:18:41.907054 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
483 22:18:41.907669 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
484 22:18:41.908786 bootz 0x82000000 0x83000000 0x88000000
485 22:18:41.909314 Kernel image @ 0x82000000 [ 0x000000 - 0xaea200 ]
486 22:18:41.909914 ## Loading init Ramdisk from Legacy Image at 83000000 ...
487 22:18:41.914660 Image Name:
488 22:18:41.915192 Created: 2024-11-08 22:17:42 UTC
489 22:18:41.923415 Image Type: ARM Linux RAMDisk Image (uncompressed)
490 22:18:41.923958 Data Size: 14791586 Bytes = 14.1 MiB
491 22:18:41.931535 Load Address: 00000000
492 22:18:41.932074 Entry Point: 00000000
493 22:18:42.100251 Verifying Checksum ... OK
494 22:18:42.100922 ## Flattened Device Tree blob at 88000000
495 22:18:42.106731 Booting using the fdt blob at 0x88000000
496 22:18:42.107254 Working FDT set to 88000000
497 22:18:42.112220 Using Device Tree in place at 88000000, end 880143a7
498 22:18:42.116571 Working FDT set to 88000000
499 22:18:42.129108
500 22:18:42.129629 Starting kernel ...
501 22:18:42.130555
502 22:18:42.131538 end: 2.4.3 bootloader-commands (duration 00:00:43) [common]
503 22:18:42.132172 start: 2.4.4 auto-login-action (timeout 00:04:00) [common]
504 22:18:42.132713 Setting prompt string to ['Linux version [0-9]']
505 22:18:42.133225 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
506 22:18:42.133762 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
507 22:18:42.972847 [ 0.000000] Booting Linux on physical CPU 0x0
508 22:18:42.978682 start: 2.4.4.1 login-action (timeout 00:03:59) [common]
509 22:18:42.979053 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
510 22:18:42.979306 Setting prompt string to []
511 22:18:42.979567 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
512 22:18:42.979825 Using line separator: #'\n'#
513 22:18:42.980035 No login prompt set.
514 22:18:42.980278 Parsing kernel messages
515 22:18:42.980484 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
516 22:18:42.980915 [login-action] Waiting for messages, (timeout 00:03:59)
517 22:18:42.981161 Waiting using forced prompt support (timeout 00:02:00)
518 22:18:42.992698 [ 0.000000] Linux version 6.12.0-rc3 (KernelCI@build-j369923-arm-gcc-12-multi-v7-defconfig-lvxsd) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Fri Nov 8 21:29:37 UTC 2024
519 22:18:43.004118 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
520 22:18:43.007080 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
521 22:18:43.018490 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
522 22:18:43.024211 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
523 22:18:43.027202 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
524 22:18:43.033957 [ 0.000000] Memory policy: Data cache writeback
525 22:18:43.034310 [ 0.000000] efi: UEFI not found.
526 22:18:43.042038 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
527 22:18:43.047693 [ 0.000000] Zone ranges:
528 22:18:43.053378 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
529 22:18:43.059375 [ 0.000000] Normal empty
530 22:18:43.059677 [ 0.000000] HighMem empty
531 22:18:43.065015 [ 0.000000] Movable zone start for each node
532 22:18:43.065326 [ 0.000000] Early memory node ranges
533 22:18:43.076387 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
534 22:18:43.081713 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
535 22:18:43.107052 [ 0.000000] CPU: All CPU(s) started in SVC mode.
536 22:18:43.112635 [ 0.000000] AM335X ES2.0 (sgx neon)
537 22:18:43.124284 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
538 22:18:43.142003 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/962873/extract-nfsrootfs-7xjd04yq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
539 22:18:43.153526 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
540 22:18:43.159341 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
541 22:18:43.165307 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
542 22:18:43.174103 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
543 22:18:43.203941 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
544 22:18:43.209909 <6>[ 0.000000] trace event string verifier disabled
545 22:18:43.210207 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
546 22:18:43.215762 <6>[ 0.000000] rcu: RCU event tracing is enabled.
547 22:18:43.227095 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
548 22:18:43.232811 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
549 22:18:43.239970 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
550 22:18:43.254584 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
551 22:18:43.272294 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
552 22:18:43.278801 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
553 22:18:43.370615 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
554 22:18:43.382073 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
555 22:18:43.388794 <6>[ 0.008335] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
556 22:18:43.401361 <6>[ 0.019140] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
557 22:18:43.409172 <6>[ 0.033929] Console: colour dummy device 80x30
558 22:18:43.415128 Matched prompt #6: WARNING:
559 22:18:43.415469 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
560 22:18:43.420612 <3>[ 0.038826] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
561 22:18:43.426351 <3>[ 0.045898] This ensures that you still see kernel messages. Please
562 22:18:43.429486 <3>[ 0.052625] update your kernel commandline.
563 22:18:43.470286 <6>[ 0.057236] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
564 22:18:43.476098 <6>[ 0.096145] CPU: Testing write buffer coherency: ok
565 22:18:43.482076 <6>[ 0.101512] CPU0: Spectre v2: using BPIALL workaround
566 22:18:43.482404 <6>[ 0.106980] pid_max: default: 32768 minimum: 301
567 22:18:43.493486 <6>[ 0.112181] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 22:18:43.500532 <6>[ 0.120005] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
569 22:18:43.507510 <6>[ 0.129351] CPU0: thread -1, cpu 0, socket -1, mpidr 0
570 22:18:43.515265 <6>[ 0.136329] Setting up static identity map for 0x80300000 - 0x803000ac
571 22:18:43.521128 <6>[ 0.145951] rcu: Hierarchical SRCU implementation.
572 22:18:43.529101 <6>[ 0.151239] rcu: Max phase no-delay instances is 1000.
573 22:18:43.537912 <6>[ 0.162351] EFI services will not be available.
574 22:18:43.543742 <6>[ 0.167620] smp: Bringing up secondary CPUs ...
575 22:18:43.549392 <6>[ 0.172658] smp: Brought up 1 node, 1 CPU
576 22:18:43.555205 <6>[ 0.177061] SMP: Total of 1 processors activated (996.14 BogoMIPS).
577 22:18:43.561097 <6>[ 0.183831] CPU: All CPU(s) started in SVC mode.
578 22:18:43.581351 <6>[ 0.189009] Memory: 405996K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
579 22:18:43.581723 <6>[ 0.205277] devtmpfs: initialized
580 22:18:43.604044 <6>[ 0.222723] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
581 22:18:43.615539 <6>[ 0.231303] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
582 22:18:43.620911 <6>[ 0.241756] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
583 22:18:43.631968 <6>[ 0.254050] pinctrl core: initialized pinctrl subsystem
584 22:18:43.641485 <6>[ 0.264679] DMI not present or invalid.
585 22:18:43.649942 <6>[ 0.270522] NET: Registered PF_NETLINK/PF_ROUTE protocol family
586 22:18:43.658397 <6>[ 0.279384] DMA: preallocated 256 KiB pool for atomic coherent allocations
587 22:18:43.673301 <6>[ 0.290921] thermal_sys: Registered thermal governor 'step_wise'
588 22:18:43.673630 <6>[ 0.291078] cpuidle: using governor menu
589 22:18:43.701704 <6>[ 0.326457] No ATAGs?
590 22:18:43.707796 <6>[ 0.329099] hw-breakpoint: debug architecture 0x4 unsupported.
591 22:18:43.717355 <6>[ 0.341079] Serial: AMBA PL011 UART driver
592 22:18:43.750592 <6>[ 0.375211] iommu: Default domain type: Translated
593 22:18:43.758646 <6>[ 0.380563] iommu: DMA domain TLB invalidation policy: strict mode
594 22:18:43.786459 <5>[ 0.410516] SCSI subsystem initialized
595 22:18:43.792271 <6>[ 0.415403] usbcore: registered new interface driver usbfs
596 22:18:43.798058 <6>[ 0.421465] usbcore: registered new interface driver hub
597 22:18:43.804882 <6>[ 0.427245] usbcore: registered new device driver usb
598 22:18:43.810506 <6>[ 0.433747] pps_core: LinuxPPS API ver. 1 registered
599 22:18:43.822021 <6>[ 0.439133] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
600 22:18:43.828421 <6>[ 0.448859] PTP clock support registered
601 22:18:43.828728 <6>[ 0.453312] EDAC MC: Ver: 3.0.0
602 22:18:43.877248 <6>[ 0.500190] scmi_core: SCMI protocol bus registered
603 22:18:43.892408 <6>[ 0.517511] vgaarb: loaded
604 22:18:43.905658 <6>[ 0.530514] clocksource: Switched to clocksource dmtimer
605 22:18:43.942170 <6>[ 0.566631] NET: Registered PF_INET protocol family
606 22:18:43.954696 <6>[ 0.572316] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
607 22:18:43.961932 <6>[ 0.581119] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
608 22:18:43.973348 <6>[ 0.590052] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
609 22:18:43.979078 <6>[ 0.598310] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
610 22:18:43.984933 <6>[ 0.606600] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
611 22:18:43.990894 <6>[ 0.614325] TCP: Hash tables configured (established 4096 bind 4096)
612 22:18:44.002273 <6>[ 0.621228] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
613 22:18:44.008168 <6>[ 0.628263] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
614 22:18:44.013490 <6>[ 0.635864] NET: Registered PF_UNIX/PF_LOCAL protocol family
615 22:18:44.091149 <6>[ 0.710312] RPC: Registered named UNIX socket transport module.
616 22:18:44.091560 <6>[ 0.716741] RPC: Registered udp transport module.
617 22:18:44.096927 <6>[ 0.721869] RPC: Registered tcp transport module.
618 22:18:44.102647 <6>[ 0.726972] RPC: Registered tcp-with-tls transport module.
619 22:18:44.115665 <6>[ 0.732895] RPC: Registered tcp NFSv4.1 backchannel transport module.
620 22:18:44.116021 <6>[ 0.739804] PCI: CLS 0 bytes, default 64
621 22:18:44.122381 <5>[ 0.745597] Initialise system trusted keyrings
622 22:18:44.143513 <6>[ 0.765676] Trying to unpack rootfs image as initramfs...
623 22:18:44.223020 <6>[ 0.841584] workingset: timestamp_bits=30 max_order=17 bucket_order=0
624 22:18:44.227177 <6>[ 0.849096] squashfs: version 4.0 (2009/01/31) Phillip Lougher
625 22:18:44.267706 <5>[ 0.892455] NFS: Registering the id_resolver key type
626 22:18:44.273503 <5>[ 0.898045] Key type id_resolver registered
627 22:18:44.279341 <5>[ 0.902740] Key type id_legacy registered
628 22:18:44.285078 <6>[ 0.907180] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
629 22:18:44.293662 <6>[ 0.914382] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
630 22:18:44.367378 <5>[ 0.992055] Key type asymmetric registered
631 22:18:44.373194 <5>[ 0.996579] Asymmetric key parser 'x509' registered
632 22:18:44.384650 <6>[ 1.002053] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
633 22:18:44.385196 <6>[ 1.009937] io scheduler mq-deadline registered
634 22:18:44.390540 <6>[ 1.014917] io scheduler kyber registered
635 22:18:44.395227 <6>[ 1.019372] io scheduler bfq registered
636 22:18:44.495566 <6>[ 1.117092] ledtrig-cpu: registered to indicate activity on CPUs
637 22:18:44.797350 <6>[ 1.418810] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
638 22:18:44.841512 <6>[ 1.466224] msm_serial: driver initialized
639 22:18:44.847549 <6>[ 1.470995] SuperH (H)SCI(F) driver initialized
640 22:18:44.853429 <6>[ 1.476252] STMicroelectronics ASC driver initialized
641 22:18:44.858715 <6>[ 1.481895] STM32 USART driver initialized
642 22:18:44.969624 <6>[ 1.594141] brd: module loaded
643 22:18:45.001793 <6>[ 1.626205] loop: module loaded
644 22:18:45.045038 <6>[ 1.668827] CAN device driver interface
645 22:18:45.051817 <6>[ 1.674106] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
646 22:18:45.057282 <6>[ 1.681029] e1000e: Intel(R) PRO/1000 Network Driver
647 22:18:45.063150 <6>[ 1.686494] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
648 22:18:45.068793 <6>[ 1.692929] igb: Intel(R) Gigabit Ethernet Network Driver
649 22:18:45.076125 <6>[ 1.698751] igb: Copyright (c) 2007-2014 Intel Corporation.
650 22:18:45.088877 <6>[ 1.707908] pegasus: Pegasus/Pegasus II USB Ethernet driver
651 22:18:45.094679 <6>[ 1.714056] usbcore: registered new interface driver pegasus
652 22:18:45.100516 <6>[ 1.720183] usbcore: registered new interface driver asix
653 22:18:45.106228 <6>[ 1.726076] usbcore: registered new interface driver ax88179_178a
654 22:18:45.112032 <6>[ 1.732667] usbcore: registered new interface driver cdc_ether
655 22:18:45.117716 <6>[ 1.738963] usbcore: registered new interface driver smsc75xx
656 22:18:45.123567 <6>[ 1.745198] usbcore: registered new interface driver smsc95xx
657 22:18:45.129216 <6>[ 1.751429] usbcore: registered new interface driver net1080
658 22:18:45.135084 <6>[ 1.757547] usbcore: registered new interface driver cdc_subset
659 22:18:45.140868 <6>[ 1.763956] usbcore: registered new interface driver zaurus
660 22:18:45.148539 <6>[ 1.770001] usbcore: registered new interface driver cdc_ncm
661 22:18:45.158096 <6>[ 1.779347] usbcore: registered new interface driver usb-storage
662 22:18:45.440299 <6>[ 2.063910] i2c_dev: i2c /dev entries driver
663 22:18:45.496511 <5>[ 2.117602] cpuidle: enable-method property 'ti,am3352' found operations
664 22:18:45.509979 <6>[ 2.127204] sdhci: Secure Digital Host Controller Interface driver
665 22:18:45.510617 <6>[ 2.133977] sdhci: Copyright(c) Pierre Ossman
666 22:18:45.516775 <6>[ 2.140384] Synopsys Designware Multimedia Card Interface Driver
667 22:18:45.525992 <6>[ 2.148323] sdhci-pltfm: SDHCI platform and OF driver helper
668 22:18:45.659381 <6>[ 2.276632] usbcore: registered new interface driver usbhid
669 22:18:45.660017 <6>[ 2.282809] usbhid: USB HID core driver
670 22:18:45.696029 <6>[ 2.318195] NET: Registered PF_INET6 protocol family
671 22:18:45.728327 <6>[ 2.353211] Segment Routing with IPv6
672 22:18:45.734467 <6>[ 2.357357] In-situ OAM (IOAM) with IPv6
673 22:18:45.740914 <6>[ 2.361892] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
674 22:18:45.748538 <6>[ 2.369129] NET: Registered PF_PACKET protocol family
675 22:18:45.754350 <6>[ 2.374699] can: controller area network core
676 22:18:45.754841 <6>[ 2.379523] NET: Registered PF_CAN protocol family
677 22:18:45.760128 <6>[ 2.384752] can: raw protocol
678 22:18:45.765889 <6>[ 2.388077] can: broadcast manager protocol
679 22:18:45.772771 <6>[ 2.392671] can: netlink gateway - max_hops=1
680 22:18:45.773314 <5>[ 2.398163] Key type dns_resolver registered
681 22:18:45.778554 <6>[ 2.403250] ThumbEE CPU extension supported.
682 22:18:45.784820 <5>[ 2.407934] Registering SWP/SWPB emulation handler
683 22:18:45.792097 <3>[ 2.413625] omap_voltage_late_init: Voltage driver support not added
684 22:18:46.009943 <5>[ 2.632161] Loading compiled-in X.509 certificates
685 22:18:46.138660 <6>[ 2.750492] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
686 22:18:46.145657 <6>[ 2.767146] pinctrl-single 44e10800.pinmux: 142 pins, size 568
687 22:18:46.171506 <3>[ 2.790706] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
688 22:18:46.385532 <3>[ 3.004242] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
689 22:18:46.578687 <6>[ 3.202252] OMAP GPIO hardware version 0.1
690 22:18:46.598904 <6>[ 3.220795] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
691 22:18:46.682570 <4>[ 3.303548] at24 2-0054: supply vcc not found, using dummy regulator
692 22:18:46.716094 <4>[ 3.337492] at24 2-0055: supply vcc not found, using dummy regulator
693 22:18:46.754339 <4>[ 3.375702] at24 2-0056: supply vcc not found, using dummy regulator
694 22:18:46.795127 <4>[ 3.416124] at24 2-0057: supply vcc not found, using dummy regulator
695 22:18:46.834967 <6>[ 3.456956] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
696 22:18:46.905788 <3>[ 3.523598] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
697 22:18:46.930133 <6>[ 3.544491] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
698 22:18:46.951127 <4>[ 3.570525] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
699 22:18:46.963992 <4>[ 3.584273] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
700 22:18:47.090349 <6>[ 3.711689] omap_rng 48310000.rng: Random Number Generator ver. 20
701 22:18:47.113503 <5>[ 3.737834] random: crng init done
702 22:18:47.154660 <6>[ 3.778920] Freeing initrd memory: 14448K
703 22:18:47.163839 <6>[ 3.783662] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
704 22:18:47.215280 <6>[ 3.833775] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
705 22:18:47.221089 <6>[ 3.844106] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
706 22:18:47.232789 <6>[ 3.851438] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
707 22:18:47.238687 <6>[ 3.858884] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
708 22:18:47.250161 <6>[ 3.867010] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
709 22:18:47.257613 <6>[ 3.878644] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5c:d5:d8
710 22:18:47.270516 <5>[ 3.887656] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
711 22:18:47.298278 <3>[ 3.917351] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
712 22:18:47.303862 <6>[ 3.925939] edma 49000000.dma: TI EDMA DMA engine driver
713 22:18:47.373804 <3>[ 3.993103] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
714 22:18:47.388472 <6>[ 4.007436] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
715 22:18:47.401541 <3>[ 4.024547] l3-aon-clkctrl:0000:0: failed to disable
716 22:18:47.450201 <6>[ 4.069075] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
717 22:18:47.455705 <6>[ 4.078582] printk: legacy console [ttyS0] enabled
718 22:18:47.461352 <6>[ 4.078582] printk: legacy console [ttyS0] enabled
719 22:18:47.467096 <6>[ 4.088921] printk: legacy bootconsole [omap8250] disabled
720 22:18:47.472000 <6>[ 4.088921] printk: legacy bootconsole [omap8250] disabled
721 22:18:47.514243 <4>[ 4.132092] tps65217-pmic: Failed to locate of_node [id: -1]
722 22:18:47.517502 <4>[ 4.139483] tps65217-bl: Failed to locate of_node [id: -1]
723 22:18:47.533672 <6>[ 4.158814] tps65217 0-0024: TPS65217 ID 0xe version 1.2
724 22:18:47.552128 <6>[ 4.165733] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
725 22:18:47.563809 <6>[ 4.179415] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
726 22:18:47.568833 <6>[ 4.191272] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
727 22:18:47.591494 <6>[ 4.210848] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
728 22:18:47.597370 <6>[ 4.220094] sdhci-omap 48060000.mmc: Got CD GPIO
729 22:18:47.604590 <4>[ 4.225282] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
730 22:18:47.620089 <4>[ 4.238773] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
731 22:18:47.626473 <4>[ 4.247516] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
732 22:18:47.635337 <4>[ 4.256143] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
733 22:18:47.734282 <6>[ 4.355784] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
734 22:18:47.764263 <6>[ 4.384837] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
735 22:18:47.785781 <6>[ 4.404502] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
736 22:18:47.792541 <6>[ 4.413419] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
737 22:18:47.835341 <6>[ 4.450497] mmc0: new high speed SDHC card at address 0001
738 22:18:47.836055 <6>[ 4.458393] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
739 22:18:47.841690 <6>[ 4.466615] mmcblk0: p1
740 22:18:47.874839 <6>[ 4.492527] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
741 22:18:47.897512 <6>[ 4.513358] mmc1: new high speed MMC card at address 0001
742 22:18:47.898320 <6>[ 4.520473] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
743 22:18:47.906212 <6>[ 4.530672] mmcblk1:
744 22:18:47.913653 <6>[ 4.533915] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
745 22:18:47.921052 <6>[ 4.540944] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
746 22:18:47.926351 <6>[ 4.547884] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
747 22:18:49.983158 <6>[ 6.602413] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
748 22:18:50.096545 <5>[ 6.641450] Sending DHCP requests ., OK
749 22:18:50.107847 <6>[ 6.725912] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.23
750 22:18:50.108142 <6>[ 6.734079] IP-Config: Complete:
751 22:18:50.122087 <6>[ 6.737616] device=eth0, hwaddr=90:59:af:5c:d5:d8, ipaddr=192.168.6.23, mask=255.255.255.0, gw=192.168.6.1
752 22:18:50.127759 <6>[ 6.748131] host=192.168.6.23, domain=, nis-domain=(none)
753 22:18:50.133427 <6>[ 6.754343] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
754 22:18:50.140088 <6>[ 6.754375] nameserver0=10.255.253.1
755 22:18:50.149093 <6>[ 6.766941] clk: Disabling unused clocks
756 22:18:50.149357 <6>[ 6.771644] PM: genpd: Disabling unused power domains
757 22:18:50.168233 <6>[ 6.789940] Freeing unused kernel image (initmem) memory: 2048K
758 22:18:50.175690 <6>[ 6.799682] Run /init as init process
759 22:18:50.201199 Loading, please wait...
760 22:18:50.277083 Starting systemd-udevd version 252.22-1~deb12u1
761 22:18:53.294837 <4>[ 9.912559] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
762 22:18:53.486211 <4>[ 10.103870] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
763 22:18:53.694388 <6>[ 10.319669] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
764 22:18:53.705312 <6>[ 10.325500] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
765 22:18:53.820040 <6>[ 10.443422] tda998x 0-0070: found TDA19988
766 22:18:53.939179 <6>[ 10.562826] hub 1-0:1.0: USB hub found
767 22:18:53.948513 <6>[ 10.572037] hub 1-0:1.0: 1 port detected
768 22:18:57.232813 Begin: Loading essential drivers ... done.
769 22:18:57.238947 Begin: Running /scripts/init-premount ... done.
770 22:18:57.243917 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
771 22:18:57.254201 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
772 22:18:57.262047 Device /sys/class/net/eth0 found
773 22:18:57.262338 done.
774 22:18:57.340465 Begin: Waiting up to 180 secs for any network device to become available ... done.
775 22:18:57.438355 IP-Config: eth0 hardware address 90:59:af:5c:d5:d8 mtu 1500 DHCP
776 22:18:57.541220 IP-Config: eth0 guessed broadcast address 192.168.6.255
777 22:18:57.546742 IP-Config: eth0 complete (dhcp from 192.168.6.1):
778 22:18:57.552193 address: 192.168.6.23 broadcast: 192.168.6.255 netmask: 255.255.255.0
779 22:18:57.563552 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
780 22:18:57.563913 rootserver: 192.168.6.1 rootpath:
781 22:18:57.566069 filename :
782 22:18:57.621737 done.
783 22:18:57.634233 Begin: Running /scripts/nfs-bottom ... done.
784 22:18:57.706910 Begin: Running /scripts/init-bottom ... done.
785 22:18:59.220884 <30>[ 15.842040] systemd[1]: System time before build time, advancing clock.
786 22:18:59.386891 <30>[ 15.981880] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
787 22:18:59.396112 <30>[ 16.019157] systemd[1]: Detected architecture arm.
788 22:18:59.408604
789 22:18:59.408958 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
790 22:18:59.409203
791 22:18:59.438931 <30>[ 16.060780] systemd[1]: Hostname set to <debian-bookworm-armhf>.
792 22:19:01.583621 <30>[ 18.204442] systemd[1]: Queued start job for default target graphical.target.
793 22:19:01.600212 <30>[ 18.218886] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
794 22:19:01.607807 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
795 22:19:01.639095 <30>[ 18.257194] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
796 22:19:01.646479 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
797 22:19:01.676285 <30>[ 18.294083] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
798 22:19:01.683592 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
799 22:19:01.716808 <30>[ 18.335068] systemd[1]: Created slice user.slice - User and Session Slice.
800 22:19:01.723470 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
801 22:19:01.749191 <30>[ 18.362587] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
802 22:19:01.755287 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
803 22:19:01.773354 <30>[ 18.392482] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
804 22:19:01.784453 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
805 22:19:01.812126 <30>[ 18.422405] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
806 22:19:01.824337 <30>[ 18.443270] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
807 22:19:01.829830 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
808 22:19:01.852493 <30>[ 18.471795] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
809 22:19:01.860826 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
810 22:19:01.883248 <30>[ 18.502175] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
811 22:19:01.891554 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
812 22:19:01.912950 <30>[ 18.532332] systemd[1]: Reached target paths.target - Path Units.
813 22:19:01.918105 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
814 22:19:01.942675 <30>[ 18.562031] systemd[1]: Reached target remote-fs.target - Remote File Systems.
815 22:19:01.950085 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
816 22:19:01.974218 <30>[ 18.592899] systemd[1]: Reached target slices.target - Slice Units.
817 22:19:01.979625 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
818 22:19:02.002630 <30>[ 18.622045] systemd[1]: Reached target swap.target - Swaps.
819 22:19:02.006718 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
820 22:19:02.033419 <30>[ 18.652061] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
821 22:19:02.041282 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
822 22:19:02.064238 <30>[ 18.683128] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
823 22:19:02.072396 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
824 22:19:02.150836 <30>[ 18.765193] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
825 22:19:02.164899 <30>[ 18.782948] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
826 22:19:02.172358 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
827 22:19:02.196433 <30>[ 18.814057] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
828 22:19:02.203394 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
829 22:19:02.225567 <30>[ 18.844496] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
830 22:19:02.233778 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
831 22:19:02.261351 <30>[ 18.876462] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
832 22:19:02.264202 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
833 22:19:02.295324 <30>[ 18.913100] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
834 22:19:02.303663 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
835 22:19:02.331014 <30>[ 18.943170] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
836 22:19:02.348681 <30>[ 18.961731] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
837 22:19:02.396548 <30>[ 19.016575] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
838 22:19:02.426848 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
839 22:19:02.495007 <30>[ 19.114236] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
840 22:19:02.509081 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
841 22:19:02.573762 <30>[ 19.192586] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
842 22:19:02.602949 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
843 22:19:02.655525 <30>[ 19.274014] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
844 22:19:02.679168 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
845 22:19:02.733449 <30>[ 19.353296] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
846 22:19:02.752686 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
847 22:19:02.812521 <30>[ 19.432915] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
848 22:19:02.824806 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
849 22:19:02.874181 <30>[ 19.491974] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
850 22:19:02.902783 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
851 22:19:02.952868 <30>[ 19.574039] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
852 22:19:02.979447 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
853 22:19:03.033521 <30>[ 19.654654] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
854 22:19:03.061513 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
855 22:19:03.089412 <28>[ 19.703606] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
856 22:19:03.098990 <28>[ 19.717219] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
857 22:19:03.142388 <30>[ 19.762791] systemd[1]: Starting systemd-journald.service - Journal Service...
858 22:19:03.160494 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
859 22:19:03.234516 <30>[ 19.852736] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
860 22:19:03.245725 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
861 22:19:03.312854 <30>[ 19.932958] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
862 22:19:03.362161 Starting [0;1;39msystemd-network-g… units from Kernel command line...
863 22:19:03.428599 <30>[ 20.046677] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
864 22:19:03.484010 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
865 22:19:03.527677 <30>[ 20.146825] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
866 22:19:03.591650 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
867 22:19:03.662578 <30>[ 20.282779] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
868 22:19:03.695439 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
869 22:19:03.702765 <30>[ 20.323891] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
870 22:19:03.746461 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
871 22:19:03.771712 <30>[ 20.390722] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
872 22:19:03.804785 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
873 22:19:03.943103 <30>[ 20.564005] systemd[1]: modprobe@configfs.service: Deactivated successfully.
874 22:19:03.973395 <30>[ 20.593178] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
875 22:19:03.999628 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
876 22:19:04.027764 <30>[ 20.648696] systemd[1]: Started systemd-journald.service - Journal Service.
877 22:19:04.041666 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
878 22:19:04.081829 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
879 22:19:04.112481 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
880 22:19:04.147390 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
881 22:19:04.183301 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
882 22:19:04.208308 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
883 22:19:04.241765 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
884 22:19:04.272739 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
885 22:19:04.293990 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
886 22:19:04.322650 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
887 22:19:04.382771 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
888 22:19:04.420372 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
889 22:19:04.502754 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
890 22:19:04.583747 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
891 22:19:04.667096 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
892 22:19:04.802556 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
893 22:19:04.819484 <46>[ 21.439652] systemd-journald[163]: Received client request to flush runtime journal.
894 22:19:04.903496 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
895 22:19:05.683735 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
896 22:19:06.107798 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
897 22:19:06.154575 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
898 22:19:06.661649 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
899 22:19:06.683290 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
900 22:19:06.702313 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
901 22:19:06.785356 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
902 22:19:07.404251 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
903 22:19:07.461483 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
904 22:19:07.807957 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
905 22:19:07.887614 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
906 22:19:10.149755 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
907 22:19:10.411432 <5>[ 27.031722] cfg80211: Loading compiled-in X.509 certificates for regulatory database
908 22:19:10.760813 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
909 22:19:11.753073 <5>[ 28.375896] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
910 22:19:11.815251 <5>[ 28.433557] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
911 22:19:11.820921 <4>[ 28.443219] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
912 22:19:11.827722 <6>[ 28.452308] cfg80211: failed to load regulatory.db
913 22:19:12.845268 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
914 22:19:13.100738 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
915 22:19:20.694094 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
916 22:19:20.723614 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
917 22:19:20.746787 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
918 22:19:20.822787 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
919 22:19:20.863883 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
920 22:19:20.923803 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
921 22:19:20.991548 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
922 22:19:21.074137 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
923 22:19:21.119059 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
924 22:19:21.172169 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
925 22:19:21.212196 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
926 22:19:21.232300 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
927 22:19:21.273133 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
928 22:19:21.454068 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
929 22:19:21.751799 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
930 22:19:21.773772 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
931 22:19:21.794330 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
932 22:19:21.813322 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
933 22:19:21.848377 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
934 22:19:21.888646 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
935 22:19:21.907372 <46>[ 38.516601] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
936 22:19:21.932493 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily<46>[ 38.538364] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
937 22:19:21.933100 dpkg database backup timer.
938 22:19:21.958356 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
939 22:19:21.999602 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
940 22:19:22.015480 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
941 22:19:22.355364 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
942 22:19:22.382470 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
943 22:19:22.483354 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
944 22:19:23.033963 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
945 22:19:23.173313 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
946 22:19:23.342023 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
947 22:19:23.812643 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
948 22:19:23.859469 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
949 22:19:23.928655 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
950 22:19:23.976649 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
951 22:19:24.522035 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
952 22:19:24.583199 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
953 22:19:24.643741 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
954 22:19:24.670392 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
955 22:19:24.760217 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
956 22:19:25.075730 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
957 22:19:25.321797 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
958 22:19:25.367356 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
959 22:19:25.397789 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
960 22:19:25.490891 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
961 22:19:25.660901 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
962 22:19:25.800378
963 22:19:25.800912 Debian GNU/Linux 12worm-armhf login: root (automatic login)
964 22:19:25.803571
965 22:19:26.127062 Linux debian-bookworm-armhf 6.12.0-rc3 #1 SMP Fri Nov 8 21:29:37 UTC 2024 armv7l
966 22:19:26.127495
967 22:19:26.132690 The programs included with the Debian GNU/Linux system are free software;
968 22:19:26.136060 the exact distribution terms for each program are described in the
969 22:19:26.141719 individual files in /usr/share/doc/*/copyright.
970 22:19:26.142022
971 22:19:26.147296 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
972 22:19:26.151853 permitted by applicable law.
973 22:19:30.867743 Unable to match end of the kernel message
975 22:19:30.868667 Setting prompt string to ['/ #']
976 22:19:30.868980 end: 2.4.4.1 login-action (duration 00:00:48) [common]
978 22:19:30.869715 end: 2.4.4 auto-login-action (duration 00:00:49) [common]
979 22:19:30.870074 start: 2.4.5 expect-shell-connection (timeout 00:03:11) [common]
980 22:19:30.870339 Setting prompt string to ['/ #']
981 22:19:30.870569 Forcing a shell prompt, looking for ['/ #']
983 22:19:30.921147 / #
984 22:19:30.921916 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
985 22:19:30.922239 Waiting using forced prompt support (timeout 00:02:30)
986 22:19:30.926381
987 22:19:30.933104 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
988 22:19:30.933541 start: 2.4.6 export-device-env (timeout 00:03:11) [common]
989 22:19:30.933874 Sending with 10 millisecond of delay
991 22:19:35.927990 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/962873/extract-nfsrootfs-7xjd04yq'
992 22:19:35.938699 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/962873/extract-nfsrootfs-7xjd04yq'
993 22:19:35.939724 Sending with 10 millisecond of delay
995 22:19:38.037748 / # export NFS_SERVER_IP='192.168.6.3'
996 22:19:38.048630 export NFS_SERVER_IP='192.168.6.3'
997 22:19:38.049517 end: 2.4.6 export-device-env (duration 00:00:07) [common]
998 22:19:38.049893 end: 2.4 uboot-commands (duration 00:01:56) [common]
999 22:19:38.050227 end: 2 uboot-action (duration 00:01:56) [common]
1000 22:19:38.050535 start: 3 lava-test-retry (timeout 00:06:53) [common]
1001 22:19:38.050845 start: 3.1 lava-test-shell (timeout 00:06:53) [common]
1002 22:19:38.051088 Using namespace: common
1004 22:19:38.151838 / # #
1005 22:19:38.152567 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1006 22:19:38.157305 #
1007 22:19:38.163617 Using /lava-962873
1009 22:19:38.264596 / # export SHELL=/bin/bash
1010 22:19:38.270079 export SHELL=/bin/bash
1012 22:19:38.377293 / # . /lava-962873/environment
1013 22:19:38.382688 . /lava-962873/environment
1015 22:19:38.495475 / # /lava-962873/bin/lava-test-runner /lava-962873/0
1016 22:19:38.496384 Test shell timeout: 10s (minimum of the action and connection timeout)
1017 22:19:38.500935 /lava-962873/bin/lava-test-runner /lava-962873/0
1018 22:19:38.881393 + export TESTRUN_ID=0_timesync-off
1019 22:19:38.889355 + TESTRUN_ID=0_timesync-off
1020 22:19:38.889773 + cd /lava-962873/0/tests/0_timesync-off
1021 22:19:38.890052 ++ cat uuid
1022 22:19:38.905261 + UUID=962873_1.6.2.4.1
1023 22:19:38.905564 + set +x
1024 22:19:38.913866 <LAVA_SIGNAL_STARTRUN 0_timesync-off 962873_1.6.2.4.1>
1025 22:19:38.914159 + systemctl stop systemd-timesyncd
1026 22:19:38.914626 Received signal: <STARTRUN> 0_timesync-off 962873_1.6.2.4.1
1027 22:19:38.914884 Starting test lava.0_timesync-off (962873_1.6.2.4.1)
1028 22:19:38.915172 Skipping test definition patterns.
1029 22:19:39.211405 + set +x
1030 22:19:39.211812 <LAVA_SIGNAL_ENDRUN 0_timesync-off 962873_1.6.2.4.1>
1031 22:19:39.212277 Received signal: <ENDRUN> 0_timesync-off 962873_1.6.2.4.1
1032 22:19:39.212567 Ending use of test pattern.
1033 22:19:39.212788 Ending test lava.0_timesync-off (962873_1.6.2.4.1), duration 0.30
1035 22:19:39.369691 + export TESTRUN_ID=1_kselftest-dt
1036 22:19:39.377591 + TESTRUN_ID=1_kselftest-dt
1037 22:19:39.377922 + cd /lava-962873/0/tests/1_kselftest-dt
1038 22:19:39.378142 ++ cat uuid
1039 22:19:39.392495 + UUID=962873_1.6.2.4.5
1040 22:19:39.392822 + set +x
1041 22:19:39.397952 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 962873_1.6.2.4.5>
1042 22:19:39.398251 + cd ./automated/linux/kselftest/
1043 22:19:39.398691 Received signal: <STARTRUN> 1_kselftest-dt 962873_1.6.2.4.5
1044 22:19:39.398925 Starting test lava.1_kselftest-dt (962873_1.6.2.4.5)
1045 22:19:39.399203 Skipping test definition patterns.
1046 22:19:39.427146 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-regmap/for-next/v6.12-rc3-8-gd1f4390dd28b/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g broonie-regmap -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1047 22:19:39.536031 INFO: install_deps skipped
1048 22:19:40.079772 --2024-11-08 22:19:40-- http://storage.kernelci.org/broonie-regmap/for-next/v6.12-rc3-8-gd1f4390dd28b/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1049 22:19:40.355654 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1050 22:19:40.497622 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1051 22:19:40.636359 HTTP request sent, awaiting response... 200 OK
1052 22:19:40.636751 Length: 4104532 (3.9M) [application/octet-stream]
1053 22:19:40.641884 Saving to: 'kselftest_armhf.tar.gz'
1054 22:19:40.642162
1055 22:19:42.216440
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 182KB/s
kselftest_armhf.tar 5%[> ] 213.48K 388KB/s
kselftest_armhf.tar 20%[===> ] 836.45K 1014KB/s
kselftest_armhf.tar 31%[=====> ] 1.24M 1.21MB/s
kselftest_armhf.tar 57%[==========> ] 2.26M 1.71MB/s
kselftest_armhf.tar 94%[=================> ] 3.69M 2.42MB/s
kselftest_armhf.tar 100%[===================>] 3.91M 2.49MB/s in 1.6s
1056 22:19:42.217079
1057 22:19:42.889471 2024-11-08 22:19:42 (2.49 MB/s) - 'kselftest_armhf.tar.gz' saved [4104532/4104532]
1058 22:19:42.889910
1059 22:19:57.118817 skiplist:
1060 22:19:57.119433 ========================================
1061 22:19:57.124454 ========================================
1062 22:19:57.227390 dt:test_unprobed_devices.sh
1063 22:19:57.268756 ============== Tests to run ===============
1064 22:19:57.276124 dt:test_unprobed_devices.sh
1065 22:19:57.280015 ===========End Tests to run ===============
1066 22:19:57.287792 shardfile-dt pass
1067 22:19:57.521699 <12>[ 74.147164] kselftest: Running tests in dt
1068 22:19:57.554321 TAP version 13
1069 22:19:57.577911 1..1
1070 22:19:57.631621 # timeout set to 45
1071 22:19:57.632252 # selftests: dt: test_unprobed_devices.sh
1072 22:19:58.461563 # TAP version 13
1073 22:20:23.791154 # 1..257
1074 22:20:23.963681 # ok 1 / # SKIP
1075 22:20:23.985794 # ok 2 /clk_mcasp0
1076 22:20:24.057053 # ok 3 /clk_mcasp0_fixed # SKIP
1077 22:20:24.126325 # ok 4 /cpus/cpu@0 # SKIP
1078 22:20:24.201308 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1079 22:20:24.220574 # ok 6 /fixedregulator0
1080 22:20:24.237745 # ok 7 /leds
1081 22:20:24.262675 # ok 8 /ocp
1082 22:20:24.281172 # ok 9 /ocp/interconnect@44c00000
1083 22:20:24.306707 # ok 10 /ocp/interconnect@44c00000/segment@0
1084 22:20:24.329570 # ok 11 /ocp/interconnect@44c00000/segment@100000
1085 22:20:24.353597 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1086 22:20:24.423943 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1087 22:20:24.445059 # ok 14 /ocp/interconnect@44c00000/segment@200000
1088 22:20:24.468826 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1089 22:20:24.573051 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1090 22:20:24.648159 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1091 22:20:24.716889 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1092 22:20:24.788733 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1093 22:20:24.864435 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1094 22:20:24.935729 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1095 22:20:25.005876 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1096 22:20:25.077744 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1097 22:20:25.148537 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1098 22:20:25.219136 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1099 22:20:25.286405 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1100 22:20:25.358009 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1101 22:20:25.429941 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1102 22:20:25.500649 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1103 22:20:25.574037 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1104 22:20:25.649099 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1105 22:20:25.717351 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1106 22:20:25.793567 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1107 22:20:25.861083 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1108 22:20:25.932363 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1109 22:20:26.002059 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1110 22:20:26.073045 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1111 22:20:26.144621 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1112 22:20:26.215104 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1113 22:20:26.286730 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1114 22:20:26.358171 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1115 22:20:26.435648 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1116 22:20:26.503508 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1117 22:20:26.574361 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1118 22:20:26.646177 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1119 22:20:26.717648 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1120 22:20:26.788774 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1121 22:20:26.862046 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1122 22:20:26.930862 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1123 22:20:27.002922 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1124 22:20:27.077764 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1125 22:20:27.144499 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1126 22:20:27.215965 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1127 22:20:27.288248 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1128 22:20:27.357993 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1129 22:20:27.434263 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1130 22:20:27.506759 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1131 22:20:27.576982 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1132 22:20:27.648441 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1133 22:20:27.719214 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1134 22:20:27.788563 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1135 22:20:27.858702 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1136 22:20:27.930314 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1137 22:20:28.001413 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1138 22:20:28.072643 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1139 22:20:28.144652 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1140 22:20:28.218842 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1141 22:20:28.289317 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1142 22:20:28.359500 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1143 22:20:28.430986 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1144 22:20:28.506243 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1145 22:20:28.576950 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1146 22:20:28.647265 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1147 22:20:28.717468 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1148 22:20:28.787959 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1149 22:20:28.858315 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1150 22:20:28.929112 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1151 22:20:28.999643 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1152 22:20:29.068710 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1153 22:20:29.139027 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1154 22:20:29.211443 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1155 22:20:29.286040 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1156 22:20:29.356879 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1157 22:20:29.427331 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1158 22:20:29.498326 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1159 22:20:29.568362 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1160 22:20:29.636449 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1161 22:20:29.706880 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1162 22:20:29.780061 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1163 22:20:29.851142 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1164 22:20:29.920425 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1165 22:20:29.993216 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1166 22:20:30.067910 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1167 22:20:30.139652 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1168 22:20:30.157536 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1169 22:20:30.179824 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1170 22:20:30.202908 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1171 22:20:30.226256 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1172 22:20:30.250253 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1173 22:20:30.273723 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1174 22:20:30.299184 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1175 22:20:30.319015 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1176 22:20:30.424474 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1177 22:20:30.449025 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1178 22:20:30.472455 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1179 22:20:30.496665 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1180 22:20:30.603198 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1181 22:20:30.676890 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1182 22:20:30.748200 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1183 22:20:30.819916 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1184 22:20:30.892708 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1185 22:20:30.961868 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1186 22:20:31.034715 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1187 22:20:31.104641 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1188 22:20:31.175752 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1189 22:20:31.247701 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1190 22:20:31.318527 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1191 22:20:31.389684 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1192 22:20:31.459245 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1193 22:20:31.539019 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1194 22:20:31.605785 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1195 22:20:31.676732 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1196 22:20:31.698623 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1197 22:20:31.768154 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1198 22:20:31.837260 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1199 22:20:31.908942 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1200 22:20:31.930872 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1201 22:20:32.002058 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1202 22:20:32.024239 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1203 22:20:32.094657 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1204 22:20:32.122425 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1205 22:20:32.146663 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1206 22:20:32.164985 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1207 22:20:32.189739 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1208 22:20:32.215007 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1209 22:20:32.236989 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1210 22:20:32.261768 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1211 22:20:32.335181 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1212 22:20:32.356157 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1213 22:20:32.379834 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1214 22:20:32.455384 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1215 22:20:32.520928 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1216 22:20:32.542417 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1217 22:20:32.643969 # not ok 144 /ocp/interconnect@47c00000
1218 22:20:32.714079 # not ok 145 /ocp/interconnect@47c00000/segment@0
1219 22:20:32.739214 # ok 146 /ocp/interconnect@48000000
1220 22:20:32.757861 # ok 147 /ocp/interconnect@48000000/segment@0
1221 22:20:32.786178 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1222 22:20:32.811072 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1223 22:20:32.834144 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1224 22:20:32.856171 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1225 22:20:32.882116 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1226 22:20:32.900462 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1227 22:20:32.923390 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1228 22:20:32.995324 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1229 22:20:33.072384 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1230 22:20:33.094342 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1231 22:20:33.116597 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1232 22:20:33.141784 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1233 22:20:33.166687 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1234 22:20:33.186144 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1235 22:20:33.208877 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1236 22:20:33.235426 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1237 22:20:33.256772 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1238 22:20:33.278087 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1239 22:20:33.302052 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1240 22:20:33.324330 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1241 22:20:33.352750 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1242 22:20:33.375187 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1243 22:20:33.396509 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1244 22:20:33.421222 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1245 22:20:33.446252 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1246 22:20:33.466051 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1247 22:20:33.493003 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1248 22:20:33.513574 # ok 175 /ocp/interconnect@48000000/segment@100000
1249 22:20:33.536448 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1250 22:20:33.559075 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1251 22:20:33.636287 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1252 22:20:33.710168 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1253 22:20:33.776347 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1254 22:20:33.852814 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1255 22:20:33.919572 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1256 22:20:33.997711 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1257 22:20:34.068124 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1258 22:20:34.140103 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1259 22:20:34.162297 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1260 22:20:34.185774 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1261 22:20:34.205691 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1262 22:20:34.232691 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1263 22:20:34.256204 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1264 22:20:34.275776 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1265 22:20:34.302960 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1266 22:20:34.326390 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1267 22:20:34.346347 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1268 22:20:34.368790 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1269 22:20:34.395868 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1270 22:20:34.417001 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1271 22:20:34.436852 # ok 198 /ocp/interconnect@48000000/segment@200000
1272 22:20:34.465260 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1273 22:20:34.537174 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1274 22:20:34.553890 # ok 201 /ocp/interconnect@48000000/segment@300000
1275 22:20:34.578602 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1276 22:20:34.606473 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1277 22:20:34.625692 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1278 22:20:34.653532 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1279 22:20:34.676261 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1280 22:20:34.698437 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1281 22:20:34.766230 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1282 22:20:34.785546 # ok 209 /ocp/interconnect@4a000000
1283 22:20:34.807979 # ok 210 /ocp/interconnect@4a000000/segment@0
1284 22:20:34.833317 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1285 22:20:34.858272 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1286 22:20:34.887691 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1287 22:20:34.909934 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1288 22:20:34.982398 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1289 22:20:35.088211 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1290 22:20:35.156564 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1291 22:20:35.259483 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1292 22:20:35.333737 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1293 22:20:35.398881 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1294 22:20:35.500764 # not ok 221 /ocp/interconnect@4b140000
1295 22:20:35.570524 # not ok 222 /ocp/interconnect@4b140000/segment@0
1296 22:20:35.641129 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1297 22:20:35.657473 # ok 224 /ocp/target-module@40300000
1298 22:20:35.684019 # ok 225 /ocp/target-module@40300000/sram@0
1299 22:20:35.755466 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1300 22:20:35.824952 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1301 22:20:35.849010 # ok 228 /ocp/target-module@47400000
1302 22:20:35.873532 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1303 22:20:35.890949 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1304 22:20:35.914545 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1305 22:20:35.935919 # ok 232 /ocp/target-module@47400000/usb@1400
1306 22:20:35.962099 # ok 233 /ocp/target-module@47400000/usb@1800
1307 22:20:35.983976 # ok 234 /ocp/target-module@47810000
1308 22:20:36.001553 # ok 235 /ocp/target-module@49000000
1309 22:20:36.024627 # ok 236 /ocp/target-module@49000000/dma@0
1310 22:20:36.050410 # ok 237 /ocp/target-module@49800000
1311 22:20:36.068750 # ok 238 /ocp/target-module@49800000/dma@0
1312 22:20:36.093411 # ok 239 /ocp/target-module@49900000
1313 22:20:36.121200 # ok 240 /ocp/target-module@49900000/dma@0
1314 22:20:36.136342 # ok 241 /ocp/target-module@49a00000
1315 22:20:36.158849 # ok 242 /ocp/target-module@49a00000/dma@0
1316 22:20:36.183443 # ok 243 /ocp/target-module@4c000000
1317 22:20:36.252464 # not ok 244 /ocp/target-module@4c000000/emif@0
1318 22:20:36.281462 # ok 245 /ocp/target-module@50000000
1319 22:20:36.302097 # ok 246 /ocp/target-module@53100000
1320 22:20:36.373498 # not ok 247 /ocp/target-module@53100000/sham@0
1321 22:20:36.390215 # ok 248 /ocp/target-module@53500000
1322 22:20:36.464340 # not ok 249 /ocp/target-module@53500000/aes@0
1323 22:20:36.482624 # ok 250 /ocp/target-module@56000000
1324 22:20:36.590521 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1325 22:20:36.659005 # ok 252 /opp-table # SKIP
1326 22:20:36.722485 # ok 253 /soc # SKIP
1327 22:20:36.748219 # ok 254 /sound
1328 22:20:36.766320 # ok 255 /target-module@4b000000
1329 22:20:36.791345 # ok 256 /target-module@4b000000/target-module@140000
1330 22:20:36.812196 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1331 22:20:36.820977 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1332 22:20:36.828668 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1333 22:20:39.045082 dt_test_unprobed_devices_sh_ skip
1334 22:20:39.050111 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1335 22:20:39.055828 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1336 22:20:39.056390 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1337 22:20:39.061177 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1338 22:20:39.066757 dt_test_unprobed_devices_sh_fixedregulator0 pass
1339 22:20:39.072354 dt_test_unprobed_devices_sh_leds pass
1340 22:20:39.072823 dt_test_unprobed_devices_sh_ocp pass
1341 22:20:39.077984 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1342 22:20:39.083663 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1343 22:20:39.089302 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1344 22:20:39.100574 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1345 22:20:39.106061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1346 22:20:39.111775 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1347 22:20:39.122715 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1348 22:20:39.128386 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1349 22:20:39.139610 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1350 22:20:39.150829 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1351 22:20:39.162050 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1352 22:20:39.167585 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1353 22:20:39.178788 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1354 22:20:39.190196 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1355 22:20:39.201288 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1356 22:20:39.212783 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1357 22:20:39.218122 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1358 22:20:39.229415 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1359 22:20:39.240496 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1360 22:20:39.251674 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1361 22:20:39.262898 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1362 22:20:39.268527 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1363 22:20:39.279694 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1364 22:20:39.290878 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1365 22:20:39.302089 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1366 22:20:39.307723 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1367 22:20:39.318829 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1368 22:20:39.330050 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1369 22:20:39.341252 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1370 22:20:39.352440 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1371 22:20:39.358125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1372 22:20:39.369232 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1373 22:20:39.380511 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1374 22:20:39.391672 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1375 22:20:39.402904 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1376 22:20:39.414254 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1377 22:20:39.425138 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1378 22:20:39.436356 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1379 22:20:39.447636 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1380 22:20:39.458746 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1381 22:20:39.469917 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1382 22:20:39.481136 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1383 22:20:39.492325 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1384 22:20:39.503658 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1385 22:20:39.514795 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1386 22:20:39.525806 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1387 22:20:39.537001 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1388 22:20:39.548271 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1389 22:20:39.559483 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1390 22:20:39.570664 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1391 22:20:39.581868 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1392 22:20:39.593038 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1393 22:20:39.604258 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1394 22:20:39.615405 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1395 22:20:39.626623 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1396 22:20:39.637783 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1397 22:20:39.643393 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1398 22:20:39.654635 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1399 22:20:39.665764 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1400 22:20:39.676950 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1401 22:20:39.688165 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1402 22:20:39.699334 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1403 22:20:39.710625 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1404 22:20:39.721703 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1405 22:20:39.732890 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1406 22:20:39.744112 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1407 22:20:39.755300 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1408 22:20:39.766503 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1409 22:20:39.777697 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1410 22:20:39.788882 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1411 22:20:39.800046 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1412 22:20:39.811245 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1413 22:20:39.822426 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1414 22:20:39.833623 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1415 22:20:39.839289 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1416 22:20:39.850462 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1417 22:20:39.861684 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1418 22:20:39.872843 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1419 22:20:39.884053 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1420 22:20:39.889760 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1421 22:20:39.906448 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1422 22:20:39.917734 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1423 22:20:39.923326 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1424 22:20:39.940010 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1425 22:20:39.951264 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1426 22:20:39.962557 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1427 22:20:39.968109 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1428 22:20:39.979232 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1429 22:20:39.990411 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1430 22:20:39.996118 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1431 22:20:40.007193 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1432 22:20:40.018427 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1433 22:20:40.024093 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1434 22:20:40.035238 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1435 22:20:40.040860 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1436 22:20:40.052107 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1437 22:20:40.063119 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1438 22:20:40.074312 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1439 22:20:40.085508 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1440 22:20:40.096710 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1441 22:20:40.107845 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1442 22:20:40.119070 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1443 22:20:40.130217 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1444 22:20:40.141437 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1445 22:20:40.152700 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1446 22:20:40.163830 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1447 22:20:40.175005 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1448 22:20:40.191788 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1449 22:20:40.202988 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1450 22:20:40.214181 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1451 22:20:40.225372 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1452 22:20:40.236619 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1453 22:20:40.253367 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1454 22:20:40.264594 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1455 22:20:40.275808 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1456 22:20:40.286930 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1457 22:20:40.292515 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1458 22:20:40.303721 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1459 22:20:40.314923 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1460 22:20:40.320521 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1461 22:20:40.331769 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1462 22:20:40.337283 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1463 22:20:40.348501 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1464 22:20:40.354094 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1465 22:20:40.365228 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1466 22:20:40.370912 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1467 22:20:40.382128 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1468 22:20:40.387771 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1469 22:20:40.398943 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1470 22:20:40.410157 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1471 22:20:40.421359 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1472 22:20:40.432484 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1473 22:20:40.443790 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1474 22:20:40.449282 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1475 22:20:40.460515 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1476 22:20:40.466068 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1477 22:20:40.471704 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1478 22:20:40.477221 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1479 22:20:40.482872 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1480 22:20:40.488474 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1481 22:20:40.499603 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1482 22:20:40.505222 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1483 22:20:40.510899 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1484 22:20:40.522198 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1485 22:20:40.527647 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1486 22:20:40.538822 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1487 22:20:40.544434 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1488 22:20:40.555645 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1489 22:20:40.561232 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1490 22:20:40.572428 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1491 22:20:40.578080 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1492 22:20:40.589227 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1493 22:20:40.594879 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1494 22:20:40.606044 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1495 22:20:40.611662 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1496 22:20:40.622773 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1497 22:20:40.628424 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1498 22:20:40.633986 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1499 22:20:40.645175 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1500 22:20:40.650767 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1501 22:20:40.661972 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1502 22:20:40.667563 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1503 22:20:40.678789 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1504 22:20:40.684276 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1505 22:20:40.695550 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1506 22:20:40.701118 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1507 22:20:40.706821 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1508 22:20:40.717950 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1509 22:20:40.723491 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1510 22:20:40.734788 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1511 22:20:40.745892 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1512 22:20:40.757064 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1513 22:20:40.768287 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1514 22:20:40.779476 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1515 22:20:40.790722 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1516 22:20:40.801986 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1517 22:20:40.813040 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1518 22:20:40.818719 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1519 22:20:40.829882 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1520 22:20:40.835439 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1521 22:20:40.846575 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1522 22:20:40.852168 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1523 22:20:40.863403 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1524 22:20:40.868948 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1525 22:20:40.880202 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1526 22:20:40.885769 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1527 22:20:40.896965 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1528 22:20:40.902747 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1529 22:20:40.914093 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1530 22:20:40.919459 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1531 22:20:40.930996 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1532 22:20:40.936357 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1533 22:20:40.941923 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1534 22:20:40.953181 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1535 22:20:40.959098 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1536 22:20:40.970055 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1537 22:20:40.975644 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1538 22:20:40.987002 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1539 22:20:40.992444 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1540 22:20:41.003656 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1541 22:20:41.009311 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1542 22:20:41.014933 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1543 22:20:41.020591 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1544 22:20:41.031748 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1545 22:20:41.042874 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1546 22:20:41.048387 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1547 22:20:41.054047 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1548 22:20:41.065200 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1549 22:20:41.076434 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1550 22:20:41.087714 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1551 22:20:41.098960 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1552 22:20:41.104567 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1553 22:20:41.110153 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1554 22:20:41.115762 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1555 22:20:41.121331 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1556 22:20:41.127006 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1557 22:20:41.132515 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1558 22:20:41.143720 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1559 22:20:41.149297 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1560 22:20:41.154847 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1561 22:20:41.160516 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1562 22:20:41.166133 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1563 22:20:41.177194 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1564 22:20:41.182877 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1565 22:20:41.188432 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1566 22:20:41.194116 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1567 22:20:41.199706 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1568 22:20:41.205346 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1569 22:20:41.211007 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1570 22:20:41.216535 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1571 22:20:41.222158 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1572 22:20:41.227735 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1573 22:20:41.233293 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1574 22:20:41.239056 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1575 22:20:41.244553 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1576 22:20:41.250224 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1577 22:20:41.255743 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1578 22:20:41.261378 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1579 22:20:41.267031 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1580 22:20:41.272669 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1581 22:20:41.278234 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1582 22:20:41.283831 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1583 22:20:41.289361 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1584 22:20:41.290004 dt_test_unprobed_devices_sh_opp-table skip
1585 22:20:41.295123 dt_test_unprobed_devices_sh_soc skip
1586 22:20:41.300545 dt_test_unprobed_devices_sh_sound pass
1587 22:20:41.306196 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1588 22:20:41.311779 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1589 22:20:41.317453 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1590 22:20:41.323040 dt_test_unprobed_devices_sh fail
1591 22:20:41.323620 + ../../utils/send-to-lava.sh ./output/result.txt
1592 22:20:41.330109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1593 22:20:41.331179 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1595 22:20:41.419865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1596 22:20:41.420845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1598 22:20:41.517686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1599 22:20:41.518646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1601 22:20:41.666898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1602 22:20:41.668119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1604 22:20:41.792562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1605 22:20:41.793498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1607 22:20:41.905668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1608 22:20:41.906650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1610 22:20:42.000915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1611 22:20:42.001680 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1613 22:20:42.097348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1614 22:20:42.098400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1616 22:20:42.196274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1617 22:20:42.197189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1619 22:20:42.290706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1620 22:20:42.291667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1622 22:20:42.382403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1623 22:20:42.383129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1625 22:20:42.476443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1626 22:20:42.477104 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1628 22:20:42.572235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1629 22:20:42.573022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1631 22:20:42.665165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1632 22:20:42.665845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1634 22:20:42.757449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1635 22:20:42.758154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1637 22:20:42.854146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1638 22:20:42.854818 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1640 22:20:42.948834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1641 22:20:42.949550 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1643 22:20:43.042591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1644 22:20:43.043568 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1646 22:20:43.133206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1647 22:20:43.134038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1649 22:20:43.224976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1650 22:20:43.225836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1652 22:20:43.318676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1653 22:20:43.319484 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1655 22:20:43.410961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1656 22:20:43.411822 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1658 22:20:43.501324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1659 22:20:43.502240 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1661 22:20:43.594310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1662 22:20:43.595176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1664 22:20:43.685776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1665 22:20:43.686609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1667 22:20:43.791794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1668 22:20:43.792359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1670 22:20:43.885436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1671 22:20:43.885946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1673 22:20:43.976928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1674 22:20:43.977555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1676 22:20:44.069160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1677 22:20:44.069733 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1679 22:20:44.171155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1680 22:20:44.171735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1682 22:20:44.261637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1683 22:20:44.262316 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1685 22:20:44.355566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1686 22:20:44.356148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1688 22:20:44.444962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1689 22:20:44.445637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1691 22:20:44.537742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1692 22:20:44.538326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1694 22:20:44.624754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1695 22:20:44.625685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1697 22:20:44.715928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1698 22:20:44.716891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1700 22:20:44.806807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1701 22:20:44.807362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1703 22:20:44.900983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1704 22:20:44.901899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1706 22:20:44.994488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1707 22:20:44.995286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1709 22:20:45.088314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1710 22:20:45.089116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1712 22:20:45.188112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1713 22:20:45.188915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1715 22:20:45.281087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1716 22:20:45.281908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1718 22:20:45.372829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1719 22:20:45.373649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1721 22:20:45.462763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1722 22:20:45.463427 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1724 22:20:45.553637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1725 22:20:45.554340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1727 22:20:45.644276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1728 22:20:45.645223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1730 22:20:45.736852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1731 22:20:45.737786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1733 22:20:45.828979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1734 22:20:45.829658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1736 22:20:45.919667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1737 22:20:45.920307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1739 22:20:46.011989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1740 22:20:46.012960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1742 22:20:46.102808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1743 22:20:46.103746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1745 22:20:46.193627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1746 22:20:46.194735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1748 22:20:46.285839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1749 22:20:46.286567 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1751 22:20:46.379324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1752 22:20:46.379966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1754 22:20:46.472260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1755 22:20:46.472929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1757 22:20:46.563782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1758 22:20:46.564430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1760 22:20:46.656306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1761 22:20:46.657002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1763 22:20:46.746869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1764 22:20:46.747519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1766 22:20:46.837269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1767 22:20:46.838332 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1769 22:20:46.928170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1770 22:20:46.928986 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1772 22:20:47.021199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1773 22:20:47.021850 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1775 22:20:47.113473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1776 22:20:47.114433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1778 22:20:47.206098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1779 22:20:47.207005 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1781 22:20:47.299274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1782 22:20:47.300196 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1784 22:20:47.400568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1785 22:20:47.401173 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1787 22:20:47.500926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1788 22:20:47.501874 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1790 22:20:47.594960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1791 22:20:47.595900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1793 22:20:47.688421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1794 22:20:47.689319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1796 22:20:47.778767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1797 22:20:47.779647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1799 22:20:47.871001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1800 22:20:47.871901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1802 22:20:47.963428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1803 22:20:47.964334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1805 22:20:48.054480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1806 22:20:48.055535 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1808 22:20:48.147830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1809 22:20:48.148836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1811 22:20:48.239222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1812 22:20:48.240122 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1814 22:20:48.330063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1815 22:20:48.331017 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1817 22:20:48.421838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1818 22:20:48.422889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1820 22:20:48.514923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1821 22:20:48.515926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1823 22:20:48.608422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1824 22:20:48.609342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1826 22:20:48.697864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1827 22:20:48.698721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1829 22:20:48.788125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1830 22:20:48.789067 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1832 22:20:48.880093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1833 22:20:48.881037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1835 22:20:48.972115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1836 22:20:48.972988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1838 22:20:49.063530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1839 22:20:49.064425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1841 22:20:49.154388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1842 22:20:49.155292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1844 22:20:49.245431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1845 22:20:49.246456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1847 22:20:49.336634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1848 22:20:49.337563 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1850 22:20:49.426538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1851 22:20:49.427441 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1853 22:20:49.518615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1854 22:20:49.519522 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1856 22:20:49.873135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1857 22:20:49.873780 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1859 22:20:49.874902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1860 22:20:49.875749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1862 22:20:49.877274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1863 22:20:49.878036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1865 22:20:49.886736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1866 22:20:49.887560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1868 22:20:49.979753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1869 22:20:49.982081 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1871 22:20:50.071310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1872 22:20:50.072256 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1874 22:20:50.166906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1875 22:20:50.167802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1877 22:20:50.254928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1878 22:20:50.257480 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1880 22:20:50.346846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1881 22:20:50.347442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1883 22:20:50.437642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1884 22:20:50.440146 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1886 22:20:50.530575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1887 22:20:50.532572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1889 22:20:50.622334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1890 22:20:50.623266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1892 22:20:50.715335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1893 22:20:50.716262 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1895 22:20:50.806235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1896 22:20:50.807151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1898 22:20:50.896637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1899 22:20:50.897764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1901 22:20:50.988714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1902 22:20:50.989651 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1904 22:20:51.091351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1905 22:20:51.092023 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1907 22:20:51.192797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1908 22:20:51.193655 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1910 22:20:51.286705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1911 22:20:51.287549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1913 22:20:51.376318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1914 22:20:51.377185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1916 22:20:51.468015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1917 22:20:51.468932 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1919 22:20:51.558621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1920 22:20:51.559539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1922 22:20:51.648532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1923 22:20:51.649380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1925 22:20:51.738098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1926 22:20:51.738923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1928 22:20:51.829020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1929 22:20:51.829916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1931 22:20:51.914520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1932 22:20:51.915354 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1934 22:20:52.007642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1935 22:20:52.008491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1937 22:20:52.100057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1938 22:20:52.100968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1940 22:20:52.192693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1941 22:20:52.193286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1943 22:20:52.284892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1944 22:20:52.285518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1946 22:20:52.375316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1947 22:20:52.375943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1949 22:20:52.465421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1950 22:20:52.466089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1952 22:20:52.557213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1954 22:20:52.560338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1955 22:20:52.649371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1957 22:20:52.652474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1958 22:20:52.741977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1960 22:20:52.745021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1961 22:20:52.835382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1962 22:20:52.835972 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1964 22:20:52.927083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1965 22:20:52.928022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1967 22:20:53.014431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1968 22:20:53.015314 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1970 22:20:53.106583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1971 22:20:53.107502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1973 22:20:53.196022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1974 22:20:53.196868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1976 22:20:53.290085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1977 22:20:53.290943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1979 22:20:53.383343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1980 22:20:53.384171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1982 22:20:53.475177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1983 22:20:53.475825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1985 22:20:53.568058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1986 22:20:53.570705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1988 22:20:53.660917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1989 22:20:53.661790 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1991 22:20:53.752993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1992 22:20:53.753883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1994 22:20:53.845673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1995 22:20:53.846582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1997 22:20:53.932453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1998 22:20:53.933310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2000 22:20:54.025109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2001 22:20:54.025972 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2003 22:20:54.116583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2004 22:20:54.117465 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2006 22:20:54.209437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2007 22:20:54.210111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2009 22:20:54.302640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2010 22:20:54.303574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2012 22:20:54.394023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2013 22:20:54.394935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2015 22:20:54.486382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2016 22:20:54.487216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2018 22:20:54.577121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2019 22:20:54.578052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2021 22:20:54.667234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2022 22:20:54.668097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2024 22:20:54.755987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2025 22:20:54.756835 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2027 22:20:54.848034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2028 22:20:54.848878 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2030 22:20:54.939790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2031 22:20:54.940643 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2033 22:20:55.041274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2034 22:20:55.042270 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2036 22:20:55.137064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2037 22:20:55.137942 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2039 22:20:55.229886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2040 22:20:55.230490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2042 22:20:55.323555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2043 22:20:55.324168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2045 22:20:55.634371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2046 22:20:55.634820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2047 22:20:55.635319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2049 22:20:55.636118 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2051 22:20:55.636964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2052 22:20:55.637515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2054 22:20:55.695420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2055 22:20:55.696318 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2057 22:20:55.789344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2058 22:20:55.790488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2060 22:20:55.882848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2061 22:20:55.884249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2063 22:20:55.974183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2064 22:20:55.975216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2066 22:20:56.067407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2067 22:20:56.068832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2069 22:20:56.160464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2070 22:20:56.161383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2072 22:20:56.254863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2073 22:20:56.255779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2075 22:20:56.345970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2076 22:20:56.346856 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2078 22:20:56.447120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2079 22:20:56.447795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2081 22:20:56.539019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2082 22:20:56.539642 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2084 22:20:56.632271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2085 22:20:56.633162 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2087 22:20:56.725280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2088 22:20:56.726170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2090 22:20:56.816787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2091 22:20:56.817510 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2093 22:20:56.907530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2094 22:20:56.908219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2096 22:20:57.002375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2097 22:20:57.003307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2099 22:20:57.094541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2100 22:20:57.095443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2102 22:20:57.185752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2103 22:20:57.186643 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2105 22:20:57.278753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2106 22:20:57.279596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2108 22:20:57.373958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2109 22:20:57.374835 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2111 22:20:57.463693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2112 22:20:57.464632 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2114 22:20:57.555932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2115 22:20:57.556528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2117 22:20:57.646703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2118 22:20:57.647330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2120 22:20:57.742684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2121 22:20:57.743322 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2123 22:20:57.833171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2124 22:20:57.834182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2126 22:20:57.926064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2127 22:20:57.927082 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2129 22:20:58.018590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2130 22:20:58.019525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2132 22:20:58.111701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2133 22:20:58.112579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2135 22:20:58.205870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2136 22:20:58.206735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2138 22:20:58.297110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2139 22:20:58.298145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2141 22:20:58.389404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2142 22:20:58.390314 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2144 22:20:58.481032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2145 22:20:58.481913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2147 22:20:58.576928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2148 22:20:58.577755 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2150 22:20:58.664897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2151 22:20:58.665721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2153 22:20:58.756393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2154 22:20:58.757219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2156 22:20:58.848647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2157 22:20:58.849478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2159 22:20:58.949680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2160 22:20:58.950629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2162 22:20:59.046241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2163 22:20:59.047136 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2165 22:20:59.136859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2166 22:20:59.137711 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2168 22:20:59.228207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2169 22:20:59.228803 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2171 22:20:59.321449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2172 22:20:59.322328 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2174 22:20:59.411877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2175 22:20:59.412504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2177 22:20:59.503571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2178 22:20:59.504184 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2180 22:20:59.596348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2181 22:20:59.596956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2183 22:20:59.690558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2184 22:20:59.691159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2186 22:20:59.780665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2187 22:20:59.781306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2189 22:20:59.875534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2190 22:20:59.876178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2192 22:20:59.968333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2193 22:20:59.968969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2195 22:21:00.058236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2196 22:21:00.058871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2198 22:21:00.152590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2199 22:21:00.153243 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2201 22:21:00.253708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2202 22:21:00.254385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2204 22:21:00.347615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2205 22:21:00.348234 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2207 22:21:00.448066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2208 22:21:00.448702 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2210 22:21:00.549781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2211 22:21:00.550428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2213 22:21:00.651420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2214 22:21:00.652036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2216 22:21:00.744945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2217 22:21:00.745567 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2219 22:21:00.843673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2220 22:21:00.844295 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2222 22:21:00.937882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2223 22:21:00.938538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2225 22:21:01.032373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2226 22:21:01.033024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2228 22:21:01.125511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2229 22:21:01.126191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2231 22:21:01.220243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2232 22:21:01.220885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2234 22:21:01.437515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2235 22:21:01.438510 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2237 22:21:01.560742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2238 22:21:01.561737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2240 22:21:01.654092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2241 22:21:01.654949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2243 22:21:01.749476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2244 22:21:01.750385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2246 22:21:01.844636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2247 22:21:01.845282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2249 22:21:01.975526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2250 22:21:01.976219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2252 22:21:02.066215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2253 22:21:02.066888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2255 22:21:02.159684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2256 22:21:02.160316 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2258 22:21:02.250325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2259 22:21:02.250935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2261 22:21:02.342193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2262 22:21:02.342787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2264 22:21:02.431948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2265 22:21:02.432623 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2267 22:21:02.517579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2268 22:21:02.518240 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2270 22:21:02.609649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2271 22:21:02.610261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2273 22:21:02.718766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2275 22:21:02.721883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2276 22:21:02.809746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2277 22:21:02.810353 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2279 22:21:02.903846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2280 22:21:02.904440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2282 22:21:02.993828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2283 22:21:02.994407 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2285 22:21:03.096747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2286 22:21:03.097363 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2288 22:21:03.237525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2289 22:21:03.238220 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2291 22:21:03.338507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2292 22:21:03.339093 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2294 22:21:03.432514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2295 22:21:03.433157 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2297 22:21:03.523848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2298 22:21:03.524470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2300 22:21:03.616344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2301 22:21:03.616955 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2303 22:21:03.707250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2304 22:21:03.707908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2306 22:21:03.798982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2307 22:21:03.799598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2309 22:21:03.888738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2310 22:21:03.889357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2312 22:21:03.982009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2313 22:21:03.982630 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2315 22:21:04.071720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2316 22:21:04.072346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2318 22:21:04.157632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2319 22:21:04.158274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2321 22:21:04.249948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2322 22:21:04.250554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2324 22:21:04.341508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2325 22:21:04.342213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2327 22:21:04.431551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2328 22:21:04.432164 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2330 22:21:04.516341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2331 22:21:04.517285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2333 22:21:04.607967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2334 22:21:04.608812 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2336 22:21:04.709507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2337 22:21:04.710386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2339 22:21:04.837143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2340 22:21:04.837970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2342 22:21:04.927890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2343 22:21:04.928710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2345 22:21:05.022568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2346 22:21:05.023484 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2348 22:21:05.113014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2349 22:21:05.114707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2351 22:21:05.251188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2352 22:21:05.252089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2354 22:21:05.343973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2355 22:21:05.344886 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2357 22:21:05.437119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2358 22:21:05.438015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2360 22:21:05.588551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2361 22:21:05.589845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2363 22:21:05.736564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2364 22:21:05.737478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2366 22:21:05.824608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2367 22:21:05.825208 + set +x
2368 22:21:05.825935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2370 22:21:05.828885 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 962873_1.6.2.4.5>
2371 22:21:05.829662 Received signal: <ENDRUN> 1_kselftest-dt 962873_1.6.2.4.5
2372 22:21:05.830188 Ending use of test pattern.
2373 22:21:05.830632 Ending test lava.1_kselftest-dt (962873_1.6.2.4.5), duration 86.43
2375 22:21:05.835950 <LAVA_TEST_RUNNER EXIT>
2376 22:21:05.836724 ok: lava_test_shell seems to have completed
2377 22:21:05.851040 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2378 22:21:05.853173 end: 3.1 lava-test-shell (duration 00:01:28) [common]
2379 22:21:05.853793 end: 3 lava-test-retry (duration 00:01:28) [common]
2380 22:21:05.854428 start: 4 finalize (timeout 00:05:25) [common]
2381 22:21:05.855031 start: 4.1 power-off (timeout 00:00:30) [common]
2382 22:21:05.856109 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-03'
2383 22:21:05.892262 >> OK - accepted request
2384 22:21:05.894128 Returned 0 in 0 seconds
2385 22:21:05.995469 end: 4.1 power-off (duration 00:00:00) [common]
2387 22:21:05.997339 start: 4.2 read-feedback (timeout 00:05:25) [common]
2388 22:21:05.998636 Listened to connection for namespace 'common' for up to 1s
2389 22:21:05.999587 Listened to connection for namespace 'common' for up to 1s
2390 22:21:06.999080 Finalising connection for namespace 'common'
2391 22:21:07.000875 Disconnecting from shell: Finalise
2392 22:21:07.001367 / #
2393 22:21:07.102226 end: 4.2 read-feedback (duration 00:00:01) [common]
2394 22:21:07.103046 end: 4 finalize (duration 00:00:01) [common]
2395 22:21:07.103728 Cleaning after the job
2396 22:21:07.104379 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962873/tftp-deploy-z5xrqvop/ramdisk
2397 22:21:07.107380 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962873/tftp-deploy-z5xrqvop/kernel
2398 22:21:07.109364 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962873/tftp-deploy-z5xrqvop/dtb
2399 22:21:07.110633 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962873/tftp-deploy-z5xrqvop/nfsrootfs
2400 22:21:07.156576 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962873/tftp-deploy-z5xrqvop/modules
2401 22:21:07.161628 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/962873
2402 22:21:10.083791 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/962873
2403 22:21:10.084335 Job finished correctly