Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 21:53:05.254111 lava-dispatcher, installed at version: 2024.01
2 21:53:05.254908 start: 0 validate
3 21:53:05.255392 Start time: 2024-11-08 21:53:05.255362+00:00 (UTC)
4 21:53:05.255934 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:53:05.256523 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 21:53:05.300471 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:53:05.301026 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-regmap%2Ffor-next%2Fv6.12-rc3-8-gd1f4390dd28b%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 21:53:05.335225 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:53:05.335890 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-regmap%2Ffor-next%2Fv6.12-rc3-8-gd1f4390dd28b%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 21:53:05.369360 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:53:05.369885 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-regmap%2Ffor-next%2Fv6.12-rc3-8-gd1f4390dd28b%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 21:53:05.411143 validate duration: 0.16
14 21:53:05.412304 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 21:53:05.412714 start: 1.1 download-retry (timeout 00:10:00) [common]
16 21:53:05.413044 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 21:53:05.413636 Not decompressing ramdisk as can be used compressed.
18 21:53:05.414104 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 21:53:05.414351 saving as /var/lib/lava/dispatcher/tmp/962997/tftp-deploy-hoi6utr4/ramdisk/rootfs.cpio.gz
20 21:53:05.414628 total size: 8181887 (7 MB)
21 21:53:05.451173 progress 0 % (0 MB)
22 21:53:05.457277 progress 5 % (0 MB)
23 21:53:05.462877 progress 10 % (0 MB)
24 21:53:05.468782 progress 15 % (1 MB)
25 21:53:05.474135 progress 20 % (1 MB)
26 21:53:05.479959 progress 25 % (1 MB)
27 21:53:05.485320 progress 30 % (2 MB)
28 21:53:05.491105 progress 35 % (2 MB)
29 21:53:05.496484 progress 40 % (3 MB)
30 21:53:05.502205 progress 45 % (3 MB)
31 21:53:05.507905 progress 50 % (3 MB)
32 21:53:05.513757 progress 55 % (4 MB)
33 21:53:05.519261 progress 60 % (4 MB)
34 21:53:05.524938 progress 65 % (5 MB)
35 21:53:05.530175 progress 70 % (5 MB)
36 21:53:05.535847 progress 75 % (5 MB)
37 21:53:05.541252 progress 80 % (6 MB)
38 21:53:05.547121 progress 85 % (6 MB)
39 21:53:05.552702 progress 90 % (7 MB)
40 21:53:05.558358 progress 95 % (7 MB)
41 21:53:05.563235 progress 100 % (7 MB)
42 21:53:05.563905 7 MB downloaded in 0.15 s (52.28 MB/s)
43 21:53:05.564633 end: 1.1.1 http-download (duration 00:00:00) [common]
45 21:53:05.565614 end: 1.1 download-retry (duration 00:00:00) [common]
46 21:53:05.565917 start: 1.2 download-retry (timeout 00:10:00) [common]
47 21:53:05.566190 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 21:53:05.566665 downloading http://storage.kernelci.org/broonie-regmap/for-next/v6.12-rc3-8-gd1f4390dd28b/arm64/defconfig/gcc-12/kernel/Image
49 21:53:05.566917 saving as /var/lib/lava/dispatcher/tmp/962997/tftp-deploy-hoi6utr4/kernel/Image
50 21:53:05.567125 total size: 45713920 (43 MB)
51 21:53:05.567335 No compression specified
52 21:53:05.602256 progress 0 % (0 MB)
53 21:53:05.631305 progress 5 % (2 MB)
54 21:53:05.659752 progress 10 % (4 MB)
55 21:53:05.688177 progress 15 % (6 MB)
56 21:53:05.718833 progress 20 % (8 MB)
57 21:53:05.747363 progress 25 % (10 MB)
58 21:53:05.776581 progress 30 % (13 MB)
59 21:53:05.805166 progress 35 % (15 MB)
60 21:53:05.834085 progress 40 % (17 MB)
61 21:53:05.862248 progress 45 % (19 MB)
62 21:53:05.891724 progress 50 % (21 MB)
63 21:53:05.920840 progress 55 % (24 MB)
64 21:53:05.949456 progress 60 % (26 MB)
65 21:53:05.977307 progress 65 % (28 MB)
66 21:53:06.005675 progress 70 % (30 MB)
67 21:53:06.035713 progress 75 % (32 MB)
68 21:53:06.065092 progress 80 % (34 MB)
69 21:53:06.093558 progress 85 % (37 MB)
70 21:53:06.122945 progress 90 % (39 MB)
71 21:53:06.151499 progress 95 % (41 MB)
72 21:53:06.179741 progress 100 % (43 MB)
73 21:53:06.180281 43 MB downloaded in 0.61 s (71.10 MB/s)
74 21:53:06.180767 end: 1.2.1 http-download (duration 00:00:01) [common]
76 21:53:06.181607 end: 1.2 download-retry (duration 00:00:01) [common]
77 21:53:06.181906 start: 1.3 download-retry (timeout 00:09:59) [common]
78 21:53:06.182193 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 21:53:06.182664 downloading http://storage.kernelci.org/broonie-regmap/for-next/v6.12-rc3-8-gd1f4390dd28b/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 21:53:06.182939 saving as /var/lib/lava/dispatcher/tmp/962997/tftp-deploy-hoi6utr4/dtb/meson-g12b-a311d-libretech-cc.dtb
81 21:53:06.183160 total size: 54703 (0 MB)
82 21:53:06.183375 No compression specified
83 21:53:06.225125 progress 59 % (0 MB)
84 21:53:06.225999 progress 100 % (0 MB)
85 21:53:06.226585 0 MB downloaded in 0.04 s (1.20 MB/s)
86 21:53:06.227069 end: 1.3.1 http-download (duration 00:00:00) [common]
88 21:53:06.227922 end: 1.3 download-retry (duration 00:00:00) [common]
89 21:53:06.228253 start: 1.4 download-retry (timeout 00:09:59) [common]
90 21:53:06.228537 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 21:53:06.229016 downloading http://storage.kernelci.org/broonie-regmap/for-next/v6.12-rc3-8-gd1f4390dd28b/arm64/defconfig/gcc-12/modules.tar.xz
92 21:53:06.229279 saving as /var/lib/lava/dispatcher/tmp/962997/tftp-deploy-hoi6utr4/modules/modules.tar
93 21:53:06.229493 total size: 11607860 (11 MB)
94 21:53:06.229709 Using unxz to decompress xz
95 21:53:06.270343 progress 0 % (0 MB)
96 21:53:06.337368 progress 5 % (0 MB)
97 21:53:06.411844 progress 10 % (1 MB)
98 21:53:06.509504 progress 15 % (1 MB)
99 21:53:06.605641 progress 20 % (2 MB)
100 21:53:06.685130 progress 25 % (2 MB)
101 21:53:06.760780 progress 30 % (3 MB)
102 21:53:06.834452 progress 35 % (3 MB)
103 21:53:06.911379 progress 40 % (4 MB)
104 21:53:06.987801 progress 45 % (5 MB)
105 21:53:07.072230 progress 50 % (5 MB)
106 21:53:07.149341 progress 55 % (6 MB)
107 21:53:07.236205 progress 60 % (6 MB)
108 21:53:07.316761 progress 65 % (7 MB)
109 21:53:07.393849 progress 70 % (7 MB)
110 21:53:07.479142 progress 75 % (8 MB)
111 21:53:07.563109 progress 80 % (8 MB)
112 21:53:07.643306 progress 85 % (9 MB)
113 21:53:07.721794 progress 90 % (9 MB)
114 21:53:07.799498 progress 95 % (10 MB)
115 21:53:07.876890 progress 100 % (11 MB)
116 21:53:07.887952 11 MB downloaded in 1.66 s (6.68 MB/s)
117 21:53:07.888871 end: 1.4.1 http-download (duration 00:00:02) [common]
119 21:53:07.890458 end: 1.4 download-retry (duration 00:00:02) [common]
120 21:53:07.890974 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 21:53:07.891486 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 21:53:07.891971 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 21:53:07.892510 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 21:53:07.893466 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p
125 21:53:07.894286 makedir: /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin
126 21:53:07.894906 makedir: /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/tests
127 21:53:07.895507 makedir: /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/results
128 21:53:07.896132 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-add-keys
129 21:53:07.897053 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-add-sources
130 21:53:07.897998 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-background-process-start
131 21:53:07.898947 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-background-process-stop
132 21:53:07.899934 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-common-functions
133 21:53:07.900939 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-echo-ipv4
134 21:53:07.901839 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-install-packages
135 21:53:07.902711 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-installed-packages
136 21:53:07.903574 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-os-build
137 21:53:07.904472 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-probe-channel
138 21:53:07.905388 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-probe-ip
139 21:53:07.906359 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-target-ip
140 21:53:07.907244 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-target-mac
141 21:53:07.908144 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-target-storage
142 21:53:07.909062 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-test-case
143 21:53:07.909940 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-test-event
144 21:53:07.910797 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-test-feedback
145 21:53:07.911654 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-test-raise
146 21:53:07.912655 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-test-reference
147 21:53:07.913578 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-test-runner
148 21:53:07.914463 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-test-set
149 21:53:07.915346 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-test-shell
150 21:53:07.916255 Updating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-install-packages (oe)
151 21:53:07.917201 Updating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/bin/lava-installed-packages (oe)
152 21:53:07.917996 Creating /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/environment
153 21:53:07.918684 LAVA metadata
154 21:53:07.919158 - LAVA_JOB_ID=962997
155 21:53:07.919583 - LAVA_DISPATCHER_IP=192.168.6.2
156 21:53:07.920272 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 21:53:07.922041 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 21:53:07.922615 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 21:53:07.923024 skipped lava-vland-overlay
160 21:53:07.923507 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 21:53:07.924039 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 21:53:07.924469 skipped lava-multinode-overlay
163 21:53:07.924949 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 21:53:07.925448 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 21:53:07.925913 Loading test definitions
166 21:53:07.926454 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 21:53:07.926890 Using /lava-962997 at stage 0
168 21:53:07.928672 uuid=962997_1.5.2.4.1 testdef=None
169 21:53:07.928988 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 21:53:07.929257 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 21:53:07.931011 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 21:53:07.931805 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 21:53:07.934048 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 21:53:07.934869 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 21:53:07.937229 runner path: /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/0/tests/0_dmesg test_uuid 962997_1.5.2.4.1
178 21:53:07.937816 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 21:53:07.938585 Creating lava-test-runner.conf files
181 21:53:07.938789 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/962997/lava-overlay-qke4fx4p/lava-962997/0 for stage 0
182 21:53:07.939126 - 0_dmesg
183 21:53:07.939468 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 21:53:07.939763 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 21:53:07.963356 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 21:53:07.963750 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 21:53:07.964032 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 21:53:07.964303 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 21:53:07.964568 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 21:53:08.966500 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 21:53:08.966976 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 21:53:08.967258 extracting modules file /var/lib/lava/dispatcher/tmp/962997/tftp-deploy-hoi6utr4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/962997/extract-overlay-ramdisk-esrr5oyf/ramdisk
193 21:53:10.383346 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 21:53:10.383812 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 21:53:10.384107 [common] Applying overlay /var/lib/lava/dispatcher/tmp/962997/compress-overlay-ewe1z2e9/overlay-1.5.2.5.tar.gz to ramdisk
196 21:53:10.384321 [common] Applying overlay /var/lib/lava/dispatcher/tmp/962997/compress-overlay-ewe1z2e9/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/962997/extract-overlay-ramdisk-esrr5oyf/ramdisk
197 21:53:10.414885 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 21:53:10.415318 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 21:53:10.415594 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 21:53:10.415823 Converting downloaded kernel to a uImage
201 21:53:10.416156 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/962997/tftp-deploy-hoi6utr4/kernel/Image /var/lib/lava/dispatcher/tmp/962997/tftp-deploy-hoi6utr4/kernel/uImage
202 21:53:11.048497 output: Image Name:
203 21:53:11.048915 output: Created: Fri Nov 8 21:53:10 2024
204 21:53:11.049123 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 21:53:11.049327 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 21:53:11.049528 output: Load Address: 01080000
207 21:53:11.049725 output: Entry Point: 01080000
208 21:53:11.049923 output:
209 21:53:11.050257 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 21:53:11.050519 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 21:53:11.050785 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 21:53:11.051035 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 21:53:11.051287 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 21:53:11.051539 Building ramdisk /var/lib/lava/dispatcher/tmp/962997/extract-overlay-ramdisk-esrr5oyf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/962997/extract-overlay-ramdisk-esrr5oyf/ramdisk
215 21:53:13.404487 >> 181562 blocks
216 21:53:21.916830 Adding RAMdisk u-boot header.
217 21:53:21.917724 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/962997/extract-overlay-ramdisk-esrr5oyf/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/962997/extract-overlay-ramdisk-esrr5oyf/ramdisk.cpio.gz.uboot
218 21:53:22.191153 output: Image Name:
219 21:53:22.191923 output: Created: Fri Nov 8 21:53:21 2024
220 21:53:22.192542 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 21:53:22.193084 output: Data Size: 26057901 Bytes = 25447.17 KiB = 24.85 MiB
222 21:53:22.193606 output: Load Address: 00000000
223 21:53:22.194134 output: Entry Point: 00000000
224 21:53:22.194646 output:
225 21:53:22.195886 rename /var/lib/lava/dispatcher/tmp/962997/extract-overlay-ramdisk-esrr5oyf/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/962997/tftp-deploy-hoi6utr4/ramdisk/ramdisk.cpio.gz.uboot
226 21:53:22.196872 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 21:53:22.197601 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 21:53:22.198359 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 21:53:22.198956 No LXC device requested
230 21:53:22.199616 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 21:53:22.200327 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 21:53:22.201002 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 21:53:22.201566 Checking files for TFTP limit of 4294967296 bytes.
234 21:53:22.205138 end: 1 tftp-deploy (duration 00:00:17) [common]
235 21:53:22.205944 start: 2 uboot-action (timeout 00:05:00) [common]
236 21:53:22.206656 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 21:53:22.207323 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 21:53:22.208012 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 21:53:22.208737 Using kernel file from prepare-kernel: 962997/tftp-deploy-hoi6utr4/kernel/uImage
240 21:53:22.209542 substitutions:
241 21:53:22.210081 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 21:53:22.210602 - {DTB_ADDR}: 0x01070000
243 21:53:22.211121 - {DTB}: 962997/tftp-deploy-hoi6utr4/dtb/meson-g12b-a311d-libretech-cc.dtb
244 21:53:22.211651 - {INITRD}: 962997/tftp-deploy-hoi6utr4/ramdisk/ramdisk.cpio.gz.uboot
245 21:53:22.212248 - {KERNEL_ADDR}: 0x01080000
246 21:53:22.212781 - {KERNEL}: 962997/tftp-deploy-hoi6utr4/kernel/uImage
247 21:53:22.213302 - {LAVA_MAC}: None
248 21:53:22.213904 - {PRESEED_CONFIG}: None
249 21:53:22.214442 - {PRESEED_LOCAL}: None
250 21:53:22.214952 - {RAMDISK_ADDR}: 0x08000000
251 21:53:22.215460 - {RAMDISK}: 962997/tftp-deploy-hoi6utr4/ramdisk/ramdisk.cpio.gz.uboot
252 21:53:22.215976 - {ROOT_PART}: None
253 21:53:22.216552 - {ROOT}: None
254 21:53:22.217063 - {SERVER_IP}: 192.168.6.2
255 21:53:22.217577 - {TEE_ADDR}: 0x83000000
256 21:53:22.218087 - {TEE}: None
257 21:53:22.218598 Parsed boot commands:
258 21:53:22.219099 - setenv autoload no
259 21:53:22.219605 - setenv initrd_high 0xffffffff
260 21:53:22.220148 - setenv fdt_high 0xffffffff
261 21:53:22.220661 - dhcp
262 21:53:22.221169 - setenv serverip 192.168.6.2
263 21:53:22.221673 - tftpboot 0x01080000 962997/tftp-deploy-hoi6utr4/kernel/uImage
264 21:53:22.222181 - tftpboot 0x08000000 962997/tftp-deploy-hoi6utr4/ramdisk/ramdisk.cpio.gz.uboot
265 21:53:22.222690 - tftpboot 0x01070000 962997/tftp-deploy-hoi6utr4/dtb/meson-g12b-a311d-libretech-cc.dtb
266 21:53:22.223196 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 21:53:22.223708 - bootm 0x01080000 0x08000000 0x01070000
268 21:53:22.224389 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 21:53:22.226384 start: 2.3 connect-device (timeout 00:05:00) [common]
271 21:53:22.226991 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 21:53:22.243881 Setting prompt string to ['lava-test: # ']
273 21:53:22.245807 end: 2.3 connect-device (duration 00:00:00) [common]
274 21:53:22.246618 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 21:53:22.247526 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 21:53:22.248292 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 21:53:22.249813 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 21:53:22.289140 >> OK - accepted request
279 21:53:22.291407 Returned 0 in 0 seconds
280 21:53:22.392907 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 21:53:22.395088 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 21:53:22.395826 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 21:53:22.396579 Setting prompt string to ['Hit any key to stop autoboot']
285 21:53:22.397182 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 21:53:22.399160 Trying 192.168.56.21...
287 21:53:22.399776 Connected to conserv1.
288 21:53:22.400367 Escape character is '^]'.
289 21:53:22.400936
290 21:53:22.401488 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 21:53:22.402056
292 21:53:34.203812 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
293 21:53:34.204390 bl2_stage_init 0x81
294 21:53:34.209257 hw id: 0x0000 - pwm id 0x01
295 21:53:34.209627 bl2_stage_init 0xc1
296 21:53:34.210029 bl2_stage_init 0x02
297 21:53:34.210303
298 21:53:34.214905 L0:00000000
299 21:53:34.215208 L1:20000703
300 21:53:34.215465 L2:00008067
301 21:53:34.215712 L3:14000000
302 21:53:34.215955 B2:00402000
303 21:53:34.217787 B1:e0f83180
304 21:53:34.218083
305 21:53:34.218344 TE: 58150
306 21:53:34.218591
307 21:53:34.228927 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
308 21:53:34.229228
309 21:53:34.229479 Board ID = 1
310 21:53:34.229718 Set A53 clk to 24M
311 21:53:34.229960 Set A73 clk to 24M
312 21:53:34.234531 Set clk81 to 24M
313 21:53:34.234835 A53 clk: 1200 MHz
314 21:53:34.235091 A73 clk: 1200 MHz
315 21:53:34.240129 CLK81: 166.6M
316 21:53:34.240432 smccc: 00012aab
317 21:53:34.245698 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
318 21:53:34.246008 board id: 1
319 21:53:34.254519 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
320 21:53:34.264940 fw parse done
321 21:53:34.270045 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
322 21:53:34.313522 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
323 21:53:34.324408 PIEI prepare done
324 21:53:34.324778 fastboot data load
325 21:53:34.325032 fastboot data verify
326 21:53:34.330138 verify result: 266
327 21:53:34.335531 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
328 21:53:34.335857 LPDDR4 probe
329 21:53:34.336144 ddr clk to 1584MHz
330 21:53:34.343543 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
331 21:53:34.380996
332 21:53:34.381379 dmc_version 0001
333 21:53:34.387587 Check phy result
334 21:53:34.393303 INFO : End of CA training
335 21:53:34.393659 INFO : End of initialization
336 21:53:34.399077 INFO : Training has run successfully!
337 21:53:34.399414 Check phy result
338 21:53:34.404561 INFO : End of initialization
339 21:53:34.404924 INFO : End of read enable training
340 21:53:34.410176 INFO : End of fine write leveling
341 21:53:34.415846 INFO : End of Write leveling coarse delay
342 21:53:34.416249 INFO : Training has run successfully!
343 21:53:34.416518 Check phy result
344 21:53:34.421406 INFO : End of initialization
345 21:53:34.421738 INFO : End of read dq deskew training
346 21:53:34.427076 INFO : End of MPR read delay center optimization
347 21:53:34.432565 INFO : End of write delay center optimization
348 21:53:34.438184 INFO : End of read delay center optimization
349 21:53:34.438511 INFO : End of max read latency training
350 21:53:34.443805 INFO : Training has run successfully!
351 21:53:34.444170 1D training succeed
352 21:53:34.453053 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
353 21:53:34.500684 Check phy result
354 21:53:34.501114 INFO : End of initialization
355 21:53:34.522419 INFO : End of 2D read delay Voltage center optimization
356 21:53:34.542655 INFO : End of 2D read delay Voltage center optimization
357 21:53:34.594725 INFO : End of 2D write delay Voltage center optimization
358 21:53:34.644022 INFO : End of 2D write delay Voltage center optimization
359 21:53:34.649512 INFO : Training has run successfully!
360 21:53:34.649803
361 21:53:34.650055 channel==0
362 21:53:34.655177 RxClkDly_Margin_A0==88 ps 9
363 21:53:34.655463 TxDqDly_Margin_A0==98 ps 10
364 21:53:34.658582 RxClkDly_Margin_A1==88 ps 9
365 21:53:34.658875 TxDqDly_Margin_A1==98 ps 10
366 21:53:34.664182 TrainedVREFDQ_A0==74
367 21:53:34.664481 TrainedVREFDQ_A1==74
368 21:53:34.664731 VrefDac_Margin_A0==25
369 21:53:34.669726 DeviceVref_Margin_A0==40
370 21:53:34.670026 VrefDac_Margin_A1==25
371 21:53:34.675320 DeviceVref_Margin_A1==40
372 21:53:34.675646
373 21:53:34.675913
374 21:53:34.676202 channel==1
375 21:53:34.676453 RxClkDly_Margin_A0==98 ps 10
376 21:53:34.680914 TxDqDly_Margin_A0==88 ps 9
377 21:53:34.681232 RxClkDly_Margin_A1==98 ps 10
378 21:53:34.686543 TxDqDly_Margin_A1==88 ps 9
379 21:53:34.686871 TrainedVREFDQ_A0==76
380 21:53:34.687129 TrainedVREFDQ_A1==77
381 21:53:34.692195 VrefDac_Margin_A0==22
382 21:53:34.692511 DeviceVref_Margin_A0==38
383 21:53:34.697764 VrefDac_Margin_A1==22
384 21:53:34.698085 DeviceVref_Margin_A1==37
385 21:53:34.698342
386 21:53:34.703383 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
387 21:53:34.703831
388 21:53:34.731436 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
389 21:53:34.737088 2D training succeed
390 21:53:34.742529 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
391 21:53:34.743001 auto size-- 65535DDR cs0 size: 2048MB
392 21:53:34.748224 DDR cs1 size: 2048MB
393 21:53:34.748689 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
394 21:53:34.753807 cs0 DataBus test pass
395 21:53:34.754297 cs1 DataBus test pass
396 21:53:34.754701 cs0 AddrBus test pass
397 21:53:34.759318 cs1 AddrBus test pass
398 21:53:34.759784
399 21:53:34.760236 100bdlr_step_size ps== 420
400 21:53:34.760642 result report
401 21:53:34.764964 boot times 0Enable ddr reg access
402 21:53:34.772549 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
403 21:53:34.786010 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
404 21:53:35.359716 0.0;M3 CHK:0;cm4_sp_mode 0
405 21:53:35.360404 MVN_1=0x00000000
406 21:53:35.365245 MVN_2=0x00000000
407 21:53:35.370964 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
408 21:53:35.371487 OPS=0x10
409 21:53:35.371918 ring efuse init
410 21:53:35.372394 chipver efuse init
411 21:53:35.376565 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
412 21:53:35.382347 [0.018961 Inits done]
413 21:53:35.382889 secure task start!
414 21:53:35.383346 high task start!
415 21:53:35.386747 low task start!
416 21:53:35.387236 run into bl31
417 21:53:35.393384 NOTICE: BL31: v1.3(release):4fc40b1
418 21:53:35.401166 NOTICE: BL31: Built : 15:58:17, May 22 2019
419 21:53:35.401659 NOTICE: BL31: G12A normal boot!
420 21:53:35.426610 NOTICE: BL31: BL33 decompress pass
421 21:53:35.432349 ERROR: Error initializing runtime service opteed_fast
422 21:53:36.665155
423 21:53:36.665795
424 21:53:36.673598 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
425 21:53:36.674101
426 21:53:36.674526 Model: Libre Computer AML-A311D-CC Alta
427 21:53:36.881952 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
428 21:53:36.905335 DRAM: 2 GiB (effective 3.8 GiB)
429 21:53:37.048389 Core: 408 devices, 31 uclasses, devicetree: separate
430 21:53:37.054139 WDT: Not starting watchdog@f0d0
431 21:53:37.086576 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
432 21:53:37.098820 Loading Environment from FAT... Card did not respond to voltage select! : -110
433 21:53:37.103844 ** Bad device specification mmc 0 **
434 21:53:37.114277 Card did not respond to voltage select! : -110
435 21:53:37.121829 ** Bad device specification mmc 0 **
436 21:53:37.122305 Couldn't find partition mmc 0
437 21:53:37.130251 Card did not respond to voltage select! : -110
438 21:53:37.135712 ** Bad device specification mmc 0 **
439 21:53:37.136217 Couldn't find partition mmc 0
440 21:53:37.140741 Error: could not access storage.
441 21:53:38.404162 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
442 21:53:38.404787 bl2_stage_init 0x01
443 21:53:38.405225 bl2_stage_init 0x81
444 21:53:38.409730 hw id: 0x0000 - pwm id 0x01
445 21:53:38.410207 bl2_stage_init 0xc1
446 21:53:38.410624 bl2_stage_init 0x02
447 21:53:38.411032
448 21:53:38.415243 L0:00000000
449 21:53:38.415738 L1:20000703
450 21:53:38.416198 L2:00008067
451 21:53:38.416605 L3:14000000
452 21:53:38.420857 B2:00402000
453 21:53:38.421324 B1:e0f83180
454 21:53:38.421730
455 21:53:38.422129 TE: 58124
456 21:53:38.422529
457 21:53:38.426463 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 21:53:38.426931
459 21:53:38.427349 Board ID = 1
460 21:53:38.432045 Set A53 clk to 24M
461 21:53:38.432508 Set A73 clk to 24M
462 21:53:38.432916 Set clk81 to 24M
463 21:53:38.437687 A53 clk: 1200 MHz
464 21:53:38.438151 A73 clk: 1200 MHz
465 21:53:38.438566 CLK81: 166.6M
466 21:53:38.438968 smccc: 00012a91
467 21:53:38.443201 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 21:53:38.448823 board id: 1
469 21:53:38.454733 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 21:53:38.465355 fw parse done
471 21:53:38.471345 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 21:53:38.513951 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 21:53:38.524871 PIEI prepare done
474 21:53:38.525355 fastboot data load
475 21:53:38.525769 fastboot data verify
476 21:53:38.530487 verify result: 266
477 21:53:38.536091 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 21:53:38.536579 LPDDR4 probe
479 21:53:38.536992 ddr clk to 1584MHz
480 21:53:38.544099 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 21:53:38.581342
482 21:53:38.581893 dmc_version 0001
483 21:53:38.587974 Check phy result
484 21:53:38.593851 INFO : End of CA training
485 21:53:38.594316 INFO : End of initialization
486 21:53:38.599475 INFO : Training has run successfully!
487 21:53:38.599937 Check phy result
488 21:53:38.605045 INFO : End of initialization
489 21:53:38.605503 INFO : End of read enable training
490 21:53:38.610714 INFO : End of fine write leveling
491 21:53:38.616268 INFO : End of Write leveling coarse delay
492 21:53:38.616732 INFO : Training has run successfully!
493 21:53:38.617141 Check phy result
494 21:53:38.621847 INFO : End of initialization
495 21:53:38.622303 INFO : End of read dq deskew training
496 21:53:38.627479 INFO : End of MPR read delay center optimization
497 21:53:38.633042 INFO : End of write delay center optimization
498 21:53:38.638744 INFO : End of read delay center optimization
499 21:53:38.639210 INFO : End of max read latency training
500 21:53:38.644284 INFO : Training has run successfully!
501 21:53:38.644770 1D training succeed
502 21:53:38.653392 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 21:53:38.701087 Check phy result
504 21:53:38.701632 INFO : End of initialization
505 21:53:38.722636 INFO : End of 2D read delay Voltage center optimization
506 21:53:38.742855 INFO : End of 2D read delay Voltage center optimization
507 21:53:38.794646 INFO : End of 2D write delay Voltage center optimization
508 21:53:38.843894 INFO : End of 2D write delay Voltage center optimization
509 21:53:38.849515 INFO : Training has run successfully!
510 21:53:38.849983
511 21:53:38.850398 channel==0
512 21:53:38.854999 RxClkDly_Margin_A0==88 ps 9
513 21:53:38.855464 TxDqDly_Margin_A0==98 ps 10
514 21:53:38.860754 RxClkDly_Margin_A1==88 ps 9
515 21:53:38.861215 TxDqDly_Margin_A1==98 ps 10
516 21:53:38.861624 TrainedVREFDQ_A0==74
517 21:53:38.866215 TrainedVREFDQ_A1==74
518 21:53:38.866674 VrefDac_Margin_A0==25
519 21:53:38.867081 DeviceVref_Margin_A0==40
520 21:53:38.871858 VrefDac_Margin_A1==26
521 21:53:38.872370 DeviceVref_Margin_A1==40
522 21:53:38.872787
523 21:53:38.873193
524 21:53:38.877423 channel==1
525 21:53:38.877897 RxClkDly_Margin_A0==98 ps 10
526 21:53:38.878305 TxDqDly_Margin_A0==98 ps 10
527 21:53:38.883040 RxClkDly_Margin_A1==98 ps 10
528 21:53:38.883498 TxDqDly_Margin_A1==88 ps 9
529 21:53:38.888625 TrainedVREFDQ_A0==77
530 21:53:38.889089 TrainedVREFDQ_A1==77
531 21:53:38.889503 VrefDac_Margin_A0==22
532 21:53:38.894226 DeviceVref_Margin_A0==37
533 21:53:38.894696 VrefDac_Margin_A1==23
534 21:53:38.899824 DeviceVref_Margin_A1==37
535 21:53:38.900305
536 21:53:38.900717 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 21:53:38.905425
538 21:53:38.933400 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
539 21:53:38.933924 2D training succeed
540 21:53:38.939006 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 21:53:38.944775 auto size-- 65535DDR cs0 size: 2048MB
542 21:53:38.945237 DDR cs1 size: 2048MB
543 21:53:38.950194 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 21:53:38.950653 cs0 DataBus test pass
545 21:53:38.955810 cs1 DataBus test pass
546 21:53:38.956308 cs0 AddrBus test pass
547 21:53:38.956713 cs1 AddrBus test pass
548 21:53:38.957109
549 21:53:38.961399 100bdlr_step_size ps== 420
550 21:53:38.961870 result report
551 21:53:38.967021 boot times 0Enable ddr reg access
552 21:53:38.972511 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 21:53:38.985888 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 21:53:39.558031 0.0;M3 CHK:0;cm4_sp_mode 0
555 21:53:39.558665 MVN_1=0x00000000
556 21:53:39.563547 MVN_2=0x00000000
557 21:53:39.569306 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 21:53:39.569846 OPS=0x10
559 21:53:39.570260 ring efuse init
560 21:53:39.570655 chipver efuse init
561 21:53:39.574849 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 21:53:39.580318 [0.018961 Inits done]
563 21:53:39.580787 secure task start!
564 21:53:39.581187 high task start!
565 21:53:39.584877 low task start!
566 21:53:39.585309 run into bl31
567 21:53:39.591545 NOTICE: BL31: v1.3(release):4fc40b1
568 21:53:39.599357 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 21:53:39.599834 NOTICE: BL31: G12A normal boot!
570 21:53:39.625286 NOTICE: BL31: BL33 decompress pass
571 21:53:39.630934 ERROR: Error initializing runtime service opteed_fast
572 21:53:40.864315
573 21:53:40.871474
574 21:53:40.878260 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 21:53:40.880160
576 21:53:40.880608 Model: Libre Computer AML-A311D-CC Alta
577 21:53:41.080867 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 21:53:41.104153 DRAM: 2 GiB (effective 3.8 GiB)
579 21:53:41.247176 Core: 408 devices, 31 uclasses, devicetree: separate
580 21:53:41.252983 WDT: Not starting watchdog@f0d0
581 21:53:41.285307 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 21:53:41.297733 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 21:53:41.302699 ** Bad device specification mmc 0 **
584 21:53:41.313099 Card did not respond to voltage select! : -110
585 21:53:41.320635 ** Bad device specification mmc 0 **
586 21:53:41.321079 Couldn't find partition mmc 0
587 21:53:41.329118 Card did not respond to voltage select! : -110
588 21:53:41.334486 ** Bad device specification mmc 0 **
589 21:53:41.334961 Couldn't find partition mmc 0
590 21:53:41.339567 Error: could not access storage.
591 21:53:41.682176 Net: eth0: ethernet@ff3f0000
592 21:53:41.682788 starting USB...
593 21:53:41.934048 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 21:53:41.934625 Starting the controller
595 21:53:41.940954 USB XHCI 1.10
596 21:53:43.654290 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 21:53:43.655019 bl2_stage_init 0x01
598 21:53:43.655539 bl2_stage_init 0x81
599 21:53:43.659736 hw id: 0x0000 - pwm id 0x01
600 21:53:43.660274 bl2_stage_init 0xc1
601 21:53:43.660750 bl2_stage_init 0x02
602 21:53:43.661172
603 21:53:43.665560 L0:00000000
604 21:53:43.666070 L1:20000703
605 21:53:43.666548 L2:00008067
606 21:53:43.667017 L3:14000000
607 21:53:43.668330 B2:00402000
608 21:53:43.668830 B1:e0f83180
609 21:53:43.669327
610 21:53:43.669805 TE: 58124
611 21:53:43.670280
612 21:53:43.679464 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 21:53:43.679977
614 21:53:43.680431 Board ID = 1
615 21:53:43.680838 Set A53 clk to 24M
616 21:53:43.681238 Set A73 clk to 24M
617 21:53:43.684927 Set clk81 to 24M
618 21:53:43.685429 A53 clk: 1200 MHz
619 21:53:43.685912 A73 clk: 1200 MHz
620 21:53:43.690602 CLK81: 166.6M
621 21:53:43.691110 smccc: 00012a92
622 21:53:43.696141 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 21:53:43.696638 board id: 1
624 21:53:43.701710 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 21:53:43.715468 fw parse done
626 21:53:43.721525 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 21:53:43.764086 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 21:53:43.774932 PIEI prepare done
629 21:53:43.775441 fastboot data load
630 21:53:43.775926 fastboot data verify
631 21:53:43.780512 verify result: 266
632 21:53:43.788650 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 21:53:43.789149 LPDDR4 probe
634 21:53:43.789636 ddr clk to 1584MHz
635 21:53:43.794240 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 21:53:43.831552
637 21:53:43.832095 dmc_version 0001
638 21:53:43.838091 Check phy result
639 21:53:43.843976 INFO : End of CA training
640 21:53:43.844500 INFO : End of initialization
641 21:53:43.849549 INFO : Training has run successfully!
642 21:53:43.850050 Check phy result
643 21:53:43.855185 INFO : End of initialization
644 21:53:43.855681 INFO : End of read enable training
645 21:53:43.860766 INFO : End of fine write leveling
646 21:53:43.866413 INFO : End of Write leveling coarse delay
647 21:53:43.866906 INFO : Training has run successfully!
648 21:53:43.867385 Check phy result
649 21:53:43.871905 INFO : End of initialization
650 21:53:43.872426 INFO : End of read dq deskew training
651 21:53:43.877525 INFO : End of MPR read delay center optimization
652 21:53:43.883125 INFO : End of write delay center optimization
653 21:53:43.888675 INFO : End of read delay center optimization
654 21:53:43.889171 INFO : End of max read latency training
655 21:53:43.894499 INFO : Training has run successfully!
656 21:53:43.894987 1D training succeed
657 21:53:43.903519 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 21:53:43.951137 Check phy result
659 21:53:43.951663 INFO : End of initialization
660 21:53:43.973676 INFO : End of 2D read delay Voltage center optimization
661 21:53:43.994027 INFO : End of 2D read delay Voltage center optimization
662 21:53:44.046076 INFO : End of 2D write delay Voltage center optimization
663 21:53:44.095484 INFO : End of 2D write delay Voltage center optimization
664 21:53:44.101005 INFO : Training has run successfully!
665 21:53:44.101518
666 21:53:44.102044 channel==0
667 21:53:44.106612 RxClkDly_Margin_A0==88 ps 9
668 21:53:44.107146 TxDqDly_Margin_A0==98 ps 10
669 21:53:44.112096 RxClkDly_Margin_A1==88 ps 9
670 21:53:44.112591 TxDqDly_Margin_A1==98 ps 10
671 21:53:44.113118 TrainedVREFDQ_A0==74
672 21:53:44.117750 TrainedVREFDQ_A1==74
673 21:53:44.118269 VrefDac_Margin_A0==24
674 21:53:44.118750 DeviceVref_Margin_A0==40
675 21:53:44.123497 VrefDac_Margin_A1==25
676 21:53:44.124084 DeviceVref_Margin_A1==40
677 21:53:44.124564
678 21:53:44.125041
679 21:53:44.128981 channel==1
680 21:53:44.129559 RxClkDly_Margin_A0==98 ps 10
681 21:53:44.130042 TxDqDly_Margin_A0==98 ps 10
682 21:53:44.134493 RxClkDly_Margin_A1==98 ps 10
683 21:53:44.134997 TxDqDly_Margin_A1==88 ps 9
684 21:53:44.140219 TrainedVREFDQ_A0==77
685 21:53:44.140712 TrainedVREFDQ_A1==77
686 21:53:44.141229 VrefDac_Margin_A0==22
687 21:53:44.145793 DeviceVref_Margin_A0==37
688 21:53:44.146283 VrefDac_Margin_A1==22
689 21:53:44.151584 DeviceVref_Margin_A1==37
690 21:53:44.152110
691 21:53:44.152586 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 21:53:44.156929
693 21:53:44.184926 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000016 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
694 21:53:44.185478 2D training succeed
695 21:53:44.190537 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 21:53:44.196156 auto size-- 65535DDR cs0 size: 2048MB
697 21:53:44.196659 DDR cs1 size: 2048MB
698 21:53:44.201688 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 21:53:44.202237 cs0 DataBus test pass
700 21:53:44.207426 cs1 DataBus test pass
701 21:53:44.207938 cs0 AddrBus test pass
702 21:53:44.208456 cs1 AddrBus test pass
703 21:53:44.208913
704 21:53:44.212841 100bdlr_step_size ps== 420
705 21:53:44.213352 result report
706 21:53:44.218501 boot times 0Enable ddr reg access
707 21:53:44.223876 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 21:53:44.237466 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 21:53:44.811037 0.0;M3 CHK:0;cm4_sp_mode 0
710 21:53:44.811522 MVN_1=0x00000000
711 21:53:44.816533 MVN_2=0x00000000
712 21:53:44.822283 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 21:53:44.822877 OPS=0x10
714 21:53:44.823343 ring efuse init
715 21:53:44.823796 chipver efuse init
716 21:53:44.827859 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 21:53:44.833484 [0.018961 Inits done]
718 21:53:44.833996 secure task start!
719 21:53:44.834490 high task start!
720 21:53:44.837984 low task start!
721 21:53:44.838527 run into bl31
722 21:53:44.844705 NOTICE: BL31: v1.3(release):4fc40b1
723 21:53:44.852543 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 21:53:44.853078 NOTICE: BL31: G12A normal boot!
725 21:53:44.877955 NOTICE: BL31: BL33 decompress pass
726 21:53:44.883608 ERROR: Error initializing runtime service opteed_fast
727 21:53:46.116452
728 21:53:46.116875
729 21:53:46.125107 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 21:53:46.125889
731 21:53:46.126573 Model: Libre Computer AML-A311D-CC Alta
732 21:53:46.333339 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 21:53:46.356833 DRAM: 2 GiB (effective 3.8 GiB)
734 21:53:46.499874 Core: 408 devices, 31 uclasses, devicetree: separate
735 21:53:46.505787 WDT: Not starting watchdog@f0d0
736 21:53:46.537923 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 21:53:46.550390 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 21:53:46.555348 ** Bad device specification mmc 0 **
739 21:53:46.565737 Card did not respond to voltage select! : -110
740 21:53:46.573353 ** Bad device specification mmc 0 **
741 21:53:46.573766 Couldn't find partition mmc 0
742 21:53:46.581740 Card did not respond to voltage select! : -110
743 21:53:46.587070 ** Bad device specification mmc 0 **
744 21:53:46.587545 Couldn't find partition mmc 0
745 21:53:46.592166 Error: could not access storage.
746 21:53:46.934724 Net: eth0: ethernet@ff3f0000
747 21:53:46.935149 starting USB...
748 21:53:47.186559 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 21:53:47.186966 Starting the controller
750 21:53:47.193447 USB XHCI 1.10
751 21:53:49.355764 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 21:53:49.356231 bl2_stage_init 0x01
753 21:53:49.356475 bl2_stage_init 0x81
754 21:53:49.361211 hw id: 0x0000 - pwm id 0x01
755 21:53:49.361639 bl2_stage_init 0xc1
756 21:53:49.361968 bl2_stage_init 0x02
757 21:53:49.362205
758 21:53:49.366746 L0:00000000
759 21:53:49.367056 L1:20000703
760 21:53:49.367266 L2:00008067
761 21:53:49.367469 L3:14000000
762 21:53:49.369808 B2:00402000
763 21:53:49.370121 B1:e0f83180
764 21:53:49.370337
765 21:53:49.370550 TE: 58124
766 21:53:49.370757
767 21:53:49.381289 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 21:53:49.381632
769 21:53:49.381843 Board ID = 1
770 21:53:49.382045 Set A53 clk to 24M
771 21:53:49.382251 Set A73 clk to 24M
772 21:53:49.386639 Set clk81 to 24M
773 21:53:49.386963 A53 clk: 1200 MHz
774 21:53:49.387174 A73 clk: 1200 MHz
775 21:53:49.392126 CLK81: 166.6M
776 21:53:49.392419 smccc: 00012a92
777 21:53:49.397678 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 21:53:49.397962 board id: 1
779 21:53:49.406252 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 21:53:49.416915 fw parse done
781 21:53:49.422874 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 21:53:49.465503 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 21:53:49.476464 PIEI prepare done
784 21:53:49.476831 fastboot data load
785 21:53:49.477058 fastboot data verify
786 21:53:49.481951 verify result: 266
787 21:53:49.487565 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 21:53:49.487869 LPDDR4 probe
789 21:53:49.488130 ddr clk to 1584MHz
790 21:53:49.495606 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 21:53:49.532860
792 21:53:49.533448 dmc_version 0001
793 21:53:49.539517 Check phy result
794 21:53:49.545380 INFO : End of CA training
795 21:53:49.545854 INFO : End of initialization
796 21:53:49.551002 INFO : Training has run successfully!
797 21:53:49.551359 Check phy result
798 21:53:49.556580 INFO : End of initialization
799 21:53:49.557061 INFO : End of read enable training
800 21:53:49.562182 INFO : End of fine write leveling
801 21:53:49.567825 INFO : End of Write leveling coarse delay
802 21:53:49.568219 INFO : Training has run successfully!
803 21:53:49.568447 Check phy result
804 21:53:49.573322 INFO : End of initialization
805 21:53:49.573661 INFO : End of read dq deskew training
806 21:53:49.578906 INFO : End of MPR read delay center optimization
807 21:53:49.584594 INFO : End of write delay center optimization
808 21:53:49.590660 INFO : End of read delay center optimization
809 21:53:49.590997 INFO : End of max read latency training
810 21:53:49.595748 INFO : Training has run successfully!
811 21:53:49.596096 1D training succeed
812 21:53:49.605028 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 21:53:49.652567 Check phy result
814 21:53:49.652993 INFO : End of initialization
815 21:53:49.674343 INFO : End of 2D read delay Voltage center optimization
816 21:53:49.694622 INFO : End of 2D read delay Voltage center optimization
817 21:53:49.746694 INFO : End of 2D write delay Voltage center optimization
818 21:53:49.796079 INFO : End of 2D write delay Voltage center optimization
819 21:53:49.801987 INFO : Training has run successfully!
820 21:53:49.802322
821 21:53:49.802556 channel==0
822 21:53:49.807080 RxClkDly_Margin_A0==88 ps 9
823 21:53:49.807386 TxDqDly_Margin_A0==98 ps 10
824 21:53:49.810531 RxClkDly_Margin_A1==88 ps 9
825 21:53:49.810817 TxDqDly_Margin_A1==98 ps 10
826 21:53:49.816220 TrainedVREFDQ_A0==74
827 21:53:49.816533 TrainedVREFDQ_A1==74
828 21:53:49.816752 VrefDac_Margin_A0==25
829 21:53:49.821802 DeviceVref_Margin_A0==40
830 21:53:49.822346 VrefDac_Margin_A1==25
831 21:53:49.827405 DeviceVref_Margin_A1==40
832 21:53:49.827920
833 21:53:49.828368
834 21:53:49.828808 channel==1
835 21:53:49.829225 RxClkDly_Margin_A0==98 ps 10
836 21:53:49.830883 TxDqDly_Margin_A0==88 ps 9
837 21:53:49.836359 RxClkDly_Margin_A1==98 ps 10
838 21:53:49.836891 TxDqDly_Margin_A1==88 ps 9
839 21:53:49.837303 TrainedVREFDQ_A0==74
840 21:53:49.842039 TrainedVREFDQ_A1==77
841 21:53:49.842588 VrefDac_Margin_A0==22
842 21:53:49.847695 DeviceVref_Margin_A0==40
843 21:53:49.848257 VrefDac_Margin_A1==24
844 21:53:49.848708 DeviceVref_Margin_A1==37
845 21:53:49.849113
846 21:53:49.853252 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 21:53:49.853783
848 21:53:49.886807 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
849 21:53:49.887433 2D training succeed
850 21:53:49.892380 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 21:53:49.897973 auto size-- 65535DDR cs0 size: 2048MB
852 21:53:49.898502 DDR cs1 size: 2048MB
853 21:53:49.903559 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 21:53:49.904129 cs0 DataBus test pass
855 21:53:49.904578 cs1 DataBus test pass
856 21:53:49.909207 cs0 AddrBus test pass
857 21:53:49.909751 cs1 AddrBus test pass
858 21:53:49.910144
859 21:53:49.914752 100bdlr_step_size ps== 432
860 21:53:49.915288 result report
861 21:53:49.915680 boot times 0Enable ddr reg access
862 21:53:49.924903 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 21:53:49.937888 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 21:53:50.511602 0.0;M3 CHK:0;cm4_sp_mode 0
865 21:53:50.512295 MVN_1=0x00000000
866 21:53:50.517095 MVN_2=0x00000000
867 21:53:50.522857 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 21:53:50.523390 OPS=0x10
869 21:53:50.523820 ring efuse init
870 21:53:50.524272 chipver efuse init
871 21:53:50.531300 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 21:53:50.531844 [0.018961 Inits done]
873 21:53:50.532303 secure task start!
874 21:53:50.538621 high task start!
875 21:53:50.539119 low task start!
876 21:53:50.539541 run into bl31
877 21:53:50.545290 NOTICE: BL31: v1.3(release):4fc40b1
878 21:53:50.553133 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 21:53:50.553652 NOTICE: BL31: G12A normal boot!
880 21:53:50.578419 NOTICE: BL31: BL33 decompress pass
881 21:53:50.584061 ERROR: Error initializing runtime service opteed_fast
882 21:53:51.816959
883 21:53:51.817396
884 21:53:51.825517 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 21:53:51.826031
886 21:53:51.826285 Model: Libre Computer AML-A311D-CC Alta
887 21:53:52.033982 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 21:53:52.057199 DRAM: 2 GiB (effective 3.8 GiB)
889 21:53:52.200210 Core: 408 devices, 31 uclasses, devicetree: separate
890 21:53:52.206493 WDT: Not starting watchdog@f0d0
891 21:53:52.238337 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 21:53:52.250780 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 21:53:52.255742 ** Bad device specification mmc 0 **
894 21:53:52.266112 Card did not respond to voltage select! : -110
895 21:53:52.273762 ** Bad device specification mmc 0 **
896 21:53:52.274147 Couldn't find partition mmc 0
897 21:53:52.282107 Card did not respond to voltage select! : -110
898 21:53:52.287611 ** Bad device specification mmc 0 **
899 21:53:52.288012 Couldn't find partition mmc 0
900 21:53:52.292685 Error: could not access storage.
901 21:53:52.635095 Net: eth0: ethernet@ff3f0000
902 21:53:52.635491 starting USB...
903 21:53:52.886917 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 21:53:52.887345 Starting the controller
905 21:53:52.893855 USB XHCI 1.10
906 21:53:54.755672 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
907 21:53:54.756542 bl2_stage_init 0x01
908 21:53:54.757124 bl2_stage_init 0x81
909 21:53:54.761182 hw id: 0x0000 - pwm id 0x01
910 21:53:54.761810 bl2_stage_init 0xc1
911 21:53:54.762361 bl2_stage_init 0x02
912 21:53:54.762901
913 21:53:54.766826 L0:00000000
914 21:53:54.767367 L1:20000703
915 21:53:54.767820 L2:00008067
916 21:53:54.768310 L3:14000000
917 21:53:54.772382 B2:00402000
918 21:53:54.772893 B1:e0f83180
919 21:53:54.773337
920 21:53:54.773768 TE: 58167
921 21:53:54.774203
922 21:53:54.777973 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
923 21:53:54.778490
924 21:53:54.778924 Board ID = 1
925 21:53:54.783559 Set A53 clk to 24M
926 21:53:54.784089 Set A73 clk to 24M
927 21:53:54.784531 Set clk81 to 24M
928 21:53:54.789180 A53 clk: 1200 MHz
929 21:53:54.789678 A73 clk: 1200 MHz
930 21:53:54.790128 CLK81: 166.6M
931 21:53:54.790553 smccc: 00012abd
932 21:53:54.794849 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
933 21:53:54.800413 board id: 1
934 21:53:54.806528 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
935 21:53:54.816960 fw parse done
936 21:53:54.822928 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
937 21:53:54.865519 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
938 21:53:54.876396 PIEI prepare done
939 21:53:54.876859 fastboot data load
940 21:53:54.877264 fastboot data verify
941 21:53:54.882058 verify result: 266
942 21:53:54.887663 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
943 21:53:54.888144 LPDDR4 probe
944 21:53:54.888542 ddr clk to 1584MHz
945 21:53:54.895913 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
946 21:53:54.933271
947 21:53:54.933868 dmc_version 0001
948 21:53:54.939824 Check phy result
949 21:53:54.945591 INFO : End of CA training
950 21:53:54.946045 INFO : End of initialization
951 21:53:54.951180 INFO : Training has run successfully!
952 21:53:54.951625 Check phy result
953 21:53:54.956714 INFO : End of initialization
954 21:53:54.957240 INFO : End of read enable training
955 21:53:54.962319 INFO : End of fine write leveling
956 21:53:54.968044 INFO : End of Write leveling coarse delay
957 21:53:54.968524 INFO : Training has run successfully!
958 21:53:54.968936 Check phy result
959 21:53:54.973545 INFO : End of initialization
960 21:53:54.974004 INFO : End of read dq deskew training
961 21:53:54.979180 INFO : End of MPR read delay center optimization
962 21:53:54.984759 INFO : End of write delay center optimization
963 21:53:54.990569 INFO : End of read delay center optimization
964 21:53:54.991082 INFO : End of max read latency training
965 21:53:54.996166 INFO : Training has run successfully!
966 21:53:54.996645 1D training succeed
967 21:53:55.005074 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
968 21:53:55.052793 Check phy result
969 21:53:55.053406 INFO : End of initialization
970 21:53:55.075191 INFO : End of 2D read delay Voltage center optimization
971 21:53:55.095319 INFO : End of 2D read delay Voltage center optimization
972 21:53:55.147312 INFO : End of 2D write delay Voltage center optimization
973 21:53:55.196461 INFO : End of 2D write delay Voltage center optimization
974 21:53:55.202083 INFO : Training has run successfully!
975 21:53:55.202566
976 21:53:55.202983 channel==0
977 21:53:55.207721 RxClkDly_Margin_A0==88 ps 9
978 21:53:55.208231 TxDqDly_Margin_A0==98 ps 10
979 21:53:55.213147 RxClkDly_Margin_A1==88 ps 9
980 21:53:55.213603 TxDqDly_Margin_A1==88 ps 9
981 21:53:55.214019 TrainedVREFDQ_A0==74
982 21:53:55.218763 TrainedVREFDQ_A1==74
983 21:53:55.219224 VrefDac_Margin_A0==25
984 21:53:55.219634 DeviceVref_Margin_A0==40
985 21:53:55.224431 VrefDac_Margin_A1==25
986 21:53:55.224949 DeviceVref_Margin_A1==40
987 21:53:55.225394
988 21:53:55.225827
989 21:53:55.226262 channel==1
990 21:53:55.230054 RxClkDly_Margin_A0==98 ps 10
991 21:53:55.230563 TxDqDly_Margin_A0==98 ps 10
992 21:53:55.235694 RxClkDly_Margin_A1==98 ps 10
993 21:53:55.236243 TxDqDly_Margin_A1==88 ps 9
994 21:53:55.241376 TrainedVREFDQ_A0==77
995 21:53:55.241897 TrainedVREFDQ_A1==77
996 21:53:55.242349 VrefDac_Margin_A0==22
997 21:53:55.246807 DeviceVref_Margin_A0==37
998 21:53:55.247327 VrefDac_Margin_A1==22
999 21:53:55.252442 DeviceVref_Margin_A1==37
1000 21:53:55.252955
1001 21:53:55.253404 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1002 21:53:55.253835
1003 21:53:55.286089 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000018 00000018 00000017 00000018 00000016 00000017 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000018 dram_vref_reg_value 0x 00000060
1004 21:53:55.286955 2D training succeed
1005 21:53:55.291705 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1006 21:53:55.297158 auto size-- 65535DDR cs0 size: 2048MB
1007 21:53:55.297824 DDR cs1 size: 2048MB
1008 21:53:55.302778 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1009 21:53:55.303461 cs0 DataBus test pass
1010 21:53:55.308376 cs1 DataBus test pass
1011 21:53:55.309068 cs0 AddrBus test pass
1012 21:53:55.309635 cs1 AddrBus test pass
1013 21:53:55.310200
1014 21:53:55.313926 100bdlr_step_size ps== 420
1015 21:53:55.314482 result report
1016 21:53:55.319541 boot times 0Enable ddr reg access
1017 21:53:55.324867 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1018 21:53:55.338343 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1019 21:53:55.910382 0.0;M3 CHK:0;cm4_sp_mode 0
1020 21:53:55.911035 MVN_1=0x00000000
1021 21:53:55.915915 MVN_2=0x00000000
1022 21:53:55.921631 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1023 21:53:55.922154 OPS=0x10
1024 21:53:55.922579 ring efuse init
1025 21:53:55.922990 chipver efuse init
1026 21:53:55.927246 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1027 21:53:55.932819 [0.018961 Inits done]
1028 21:53:55.933350 secure task start!
1029 21:53:55.933781 high task start!
1030 21:53:55.937479 low task start!
1031 21:53:55.937989 run into bl31
1032 21:53:55.944041 NOTICE: BL31: v1.3(release):4fc40b1
1033 21:53:55.951859 NOTICE: BL31: Built : 15:58:17, May 22 2019
1034 21:53:55.952443 NOTICE: BL31: G12A normal boot!
1035 21:53:55.977191 NOTICE: BL31: BL33 decompress pass
1036 21:53:55.982856 ERROR: Error initializing runtime service opteed_fast
1037 21:53:57.215569
1038 21:53:57.216011
1039 21:53:57.223125 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1040 21:53:57.223482
1041 21:53:57.223730 Model: Libre Computer AML-A311D-CC Alta
1042 21:53:57.432523 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1043 21:53:57.455930 DRAM: 2 GiB (effective 3.8 GiB)
1044 21:53:57.598852 Core: 408 devices, 31 uclasses, devicetree: separate
1045 21:53:57.604705 WDT: Not starting watchdog@f0d0
1046 21:53:57.637052 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1047 21:53:57.649497 Loading Environment from FAT... Card did not respond to voltage select! : -110
1048 21:53:57.654450 ** Bad device specification mmc 0 **
1049 21:53:57.664905 Card did not respond to voltage select! : -110
1050 21:53:57.672552 ** Bad device specification mmc 0 **
1051 21:53:57.673126 Couldn't find partition mmc 0
1052 21:53:57.680910 Card did not respond to voltage select! : -110
1053 21:53:57.686357 ** Bad device specification mmc 0 **
1054 21:53:57.686947 Couldn't find partition mmc 0
1055 21:53:57.691487 Error: could not access storage.
1056 21:53:58.033899 Net: eth0: ethernet@ff3f0000
1057 21:53:58.034554 starting USB...
1058 21:53:58.285667 Bus usb@ff500000: Register 3000140 NbrPorts 3
1059 21:53:58.286546 Starting the controller
1060 21:53:58.292597 USB XHCI 1.10
1061 21:53:59.848856 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1062 21:53:59.857126 scanning usb for storage devices... 0 Storage Device(s) found
1064 21:53:59.908248 Hit any key to stop autoboot: 1
1065 21:53:59.909136 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1066 21:53:59.909507 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1067 21:53:59.909772 Setting prompt string to ['=>']
1068 21:53:59.910026 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1069 21:53:59.914606 0
1070 21:53:59.915247 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1071 21:53:59.915533 Sending with 10 millisecond of delay
1073 21:54:01.050868 => setenv autoload no
1074 21:54:01.061682 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1075 21:54:01.066715 setenv autoload no
1076 21:54:01.067572 Sending with 10 millisecond of delay
1078 21:54:02.868738 => setenv initrd_high 0xffffffff
1079 21:54:02.879339 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1080 21:54:02.879954 setenv initrd_high 0xffffffff
1081 21:54:02.880460 Sending with 10 millisecond of delay
1083 21:54:04.498978 => setenv fdt_high 0xffffffff
1084 21:54:04.509712 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1085 21:54:04.510478 setenv fdt_high 0xffffffff
1086 21:54:04.511042 Sending with 10 millisecond of delay
1088 21:54:04.802827 => dhcp
1089 21:54:04.813615 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1090 21:54:04.814442 dhcp
1091 21:54:04.814874 Speed: 1000, full duplex
1092 21:54:04.815282 BOOTP broadcast 1
1093 21:54:04.817260 DHCP client bound to address 192.168.6.27 (3 ms)
1094 21:54:04.817967 Sending with 10 millisecond of delay
1096 21:54:06.496636 => setenv serverip 192.168.6.2
1097 21:54:06.507511 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1098 21:54:06.508815 setenv serverip 192.168.6.2
1099 21:54:06.509720 Sending with 10 millisecond of delay
1101 21:54:10.237540 => tftpboot 0x01080000 962997/tftp-deploy-hoi6utr4/kernel/uImage
1102 21:54:10.248413 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1103 21:54:10.249347 tftpboot 0x01080000 962997/tftp-deploy-hoi6utr4/kernel/uImage
1104 21:54:10.249801 Speed: 1000, full duplex
1105 21:54:10.250205 Using ethernet@ff3f0000 device
1106 21:54:10.251280 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1107 21:54:10.256632 Filename '962997/tftp-deploy-hoi6utr4/kernel/uImage'.
1108 21:54:10.260891 Load address: 0x1080000
1109 21:54:13.412697 Loading: *################################################## 43.6 MiB
1110 21:54:13.413125 13.8 MiB/s
1111 21:54:13.413352 done
1112 21:54:13.417187 Bytes transferred = 45713984 (2b98a40 hex)
1113 21:54:13.417761 Sending with 10 millisecond of delay
1115 21:54:18.106848 => tftpboot 0x08000000 962997/tftp-deploy-hoi6utr4/ramdisk/ramdisk.cpio.gz.uboot
1116 21:54:18.117715 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1117 21:54:18.118691 tftpboot 0x08000000 962997/tftp-deploy-hoi6utr4/ramdisk/ramdisk.cpio.gz.uboot
1118 21:54:18.119213 Speed: 1000, full duplex
1119 21:54:18.119712 Using ethernet@ff3f0000 device
1120 21:54:18.120626 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1121 21:54:18.132409 Filename '962997/tftp-deploy-hoi6utr4/ramdisk/ramdisk.cpio.gz.uboot'.
1122 21:54:18.132997 Load address: 0x8000000
1123 21:54:25.008515 Loading: *########T ######################################### UDP wrong checksum 00000005 00000fe4
1124 21:54:30.009797 T UDP wrong checksum 00000005 00000fe4
1125 21:54:40.011341 T UDP wrong checksum 00000005 00000fe4
1126 21:55:00.016913 T T T T UDP wrong checksum 00000005 00000fe4
1127 21:55:15.021873 T T T
1128 21:55:15.022497 Retry count exceeded; starting again
1130 21:55:15.023938 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1133 21:55:15.025894 end: 2.4 uboot-commands (duration 00:01:53) [common]
1135 21:55:15.027300 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1137 21:55:15.028449 end: 2 uboot-action (duration 00:01:53) [common]
1139 21:55:15.029950 Cleaning after the job
1140 21:55:15.030484 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962997/tftp-deploy-hoi6utr4/ramdisk
1141 21:55:15.031634 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962997/tftp-deploy-hoi6utr4/kernel
1142 21:55:15.038840 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962997/tftp-deploy-hoi6utr4/dtb
1143 21:55:15.039962 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962997/tftp-deploy-hoi6utr4/modules
1144 21:55:15.046073 start: 4.1 power-off (timeout 00:00:30) [common]
1145 21:55:15.047082 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1146 21:55:15.080547 >> OK - accepted request
1147 21:55:15.082333 Returned 0 in 0 seconds
1148 21:55:15.183454 end: 4.1 power-off (duration 00:00:00) [common]
1150 21:55:15.185174 start: 4.2 read-feedback (timeout 00:10:00) [common]
1151 21:55:15.186287 Listened to connection for namespace 'common' for up to 1s
1152 21:55:16.187120 Finalising connection for namespace 'common'
1153 21:55:16.187856 Disconnecting from shell: Finalise
1154 21:55:16.188439 =>
1155 21:55:16.289506 end: 4.2 read-feedback (duration 00:00:01) [common]
1156 21:55:16.290202 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/962997
1157 21:55:16.552216 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/962997
1158 21:55:16.552814 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.