Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 22:04:05.884046 lava-dispatcher, installed at version: 2024.01
2 22:04:05.884870 start: 0 validate
3 22:04:05.885337 Start time: 2024-11-08 22:04:05.885309+00:00 (UTC)
4 22:04:05.885872 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 22:04:05.886406 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 22:04:05.936567 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 22:04:05.937110 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-regmap%2Ffor-next%2Fv6.12-rc3-8-gd1f4390dd28b%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 22:04:05.968774 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 22:04:05.969396 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-regmap%2Ffor-next%2Fv6.12-rc3-8-gd1f4390dd28b%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 22:04:06.006868 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 22:04:06.007462 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-regmap%2Ffor-next%2Fv6.12-rc3-8-gd1f4390dd28b%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 22:04:06.051410 validate duration: 0.17
14 22:04:06.052537 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:04:06.052912 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:04:06.053270 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:04:06.053899 Not decompressing ramdisk as can be used compressed.
18 22:04:06.054408 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 22:04:06.054659 saving as /var/lib/lava/dispatcher/tmp/962944/tftp-deploy-0dmxqmca/ramdisk/rootfs.cpio.gz
20 22:04:06.054932 total size: 47897469 (45 MB)
21 22:04:06.089371 progress 0 % (0 MB)
22 22:04:06.121663 progress 5 % (2 MB)
23 22:04:06.154406 progress 10 % (4 MB)
24 22:04:06.186929 progress 15 % (6 MB)
25 22:04:06.219523 progress 20 % (9 MB)
26 22:04:06.251433 progress 25 % (11 MB)
27 22:04:06.283267 progress 30 % (13 MB)
28 22:04:06.316153 progress 35 % (16 MB)
29 22:04:06.348370 progress 40 % (18 MB)
30 22:04:06.380547 progress 45 % (20 MB)
31 22:04:06.412808 progress 50 % (22 MB)
32 22:04:06.445972 progress 55 % (25 MB)
33 22:04:06.478739 progress 60 % (27 MB)
34 22:04:06.510590 progress 65 % (29 MB)
35 22:04:06.542875 progress 70 % (32 MB)
36 22:04:06.574915 progress 75 % (34 MB)
37 22:04:06.608675 progress 80 % (36 MB)
38 22:04:06.640728 progress 85 % (38 MB)
39 22:04:06.672850 progress 90 % (41 MB)
40 22:04:06.704717 progress 95 % (43 MB)
41 22:04:06.735653 progress 100 % (45 MB)
42 22:04:06.736410 45 MB downloaded in 0.68 s (67.03 MB/s)
43 22:04:06.736963 end: 1.1.1 http-download (duration 00:00:01) [common]
45 22:04:06.737838 end: 1.1 download-retry (duration 00:00:01) [common]
46 22:04:06.738128 start: 1.2 download-retry (timeout 00:09:59) [common]
47 22:04:06.738395 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 22:04:06.738858 downloading http://storage.kernelci.org/broonie-regmap/for-next/v6.12-rc3-8-gd1f4390dd28b/arm64/defconfig/gcc-12/kernel/Image
49 22:04:06.739097 saving as /var/lib/lava/dispatcher/tmp/962944/tftp-deploy-0dmxqmca/kernel/Image
50 22:04:06.739305 total size: 45713920 (43 MB)
51 22:04:06.739514 No compression specified
52 22:04:06.778903 progress 0 % (0 MB)
53 22:04:06.808367 progress 5 % (2 MB)
54 22:04:06.838612 progress 10 % (4 MB)
55 22:04:06.868542 progress 15 % (6 MB)
56 22:04:06.898803 progress 20 % (8 MB)
57 22:04:06.928342 progress 25 % (10 MB)
58 22:04:06.958132 progress 30 % (13 MB)
59 22:04:06.987930 progress 35 % (15 MB)
60 22:04:07.018137 progress 40 % (17 MB)
61 22:04:07.047788 progress 45 % (19 MB)
62 22:04:07.078068 progress 50 % (21 MB)
63 22:04:07.108071 progress 55 % (24 MB)
64 22:04:07.138327 progress 60 % (26 MB)
65 22:04:07.167790 progress 65 % (28 MB)
66 22:04:07.197698 progress 70 % (30 MB)
67 22:04:07.228683 progress 75 % (32 MB)
68 22:04:07.259312 progress 80 % (34 MB)
69 22:04:07.289160 progress 85 % (37 MB)
70 22:04:07.319418 progress 90 % (39 MB)
71 22:04:07.351203 progress 95 % (41 MB)
72 22:04:07.381172 progress 100 % (43 MB)
73 22:04:07.381713 43 MB downloaded in 0.64 s (67.87 MB/s)
74 22:04:07.382192 end: 1.2.1 http-download (duration 00:00:01) [common]
76 22:04:07.383014 end: 1.2 download-retry (duration 00:00:01) [common]
77 22:04:07.383290 start: 1.3 download-retry (timeout 00:09:59) [common]
78 22:04:07.383556 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 22:04:07.384040 downloading http://storage.kernelci.org/broonie-regmap/for-next/v6.12-rc3-8-gd1f4390dd28b/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 22:04:07.384315 saving as /var/lib/lava/dispatcher/tmp/962944/tftp-deploy-0dmxqmca/dtb/meson-g12b-a311d-libretech-cc.dtb
81 22:04:07.384524 total size: 54703 (0 MB)
82 22:04:07.384734 No compression specified
83 22:04:07.430371 progress 59 % (0 MB)
84 22:04:07.431205 progress 100 % (0 MB)
85 22:04:07.431750 0 MB downloaded in 0.05 s (1.10 MB/s)
86 22:04:07.432256 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:04:07.433080 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:04:07.433344 start: 1.4 download-retry (timeout 00:09:59) [common]
90 22:04:07.433607 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 22:04:07.434064 downloading http://storage.kernelci.org/broonie-regmap/for-next/v6.12-rc3-8-gd1f4390dd28b/arm64/defconfig/gcc-12/modules.tar.xz
92 22:04:07.434302 saving as /var/lib/lava/dispatcher/tmp/962944/tftp-deploy-0dmxqmca/modules/modules.tar
93 22:04:07.434506 total size: 11607860 (11 MB)
94 22:04:07.434717 Using unxz to decompress xz
95 22:04:07.471789 progress 0 % (0 MB)
96 22:04:07.539797 progress 5 % (0 MB)
97 22:04:07.616678 progress 10 % (1 MB)
98 22:04:07.716267 progress 15 % (1 MB)
99 22:04:07.809338 progress 20 % (2 MB)
100 22:04:07.888942 progress 25 % (2 MB)
101 22:04:07.965120 progress 30 % (3 MB)
102 22:04:08.039673 progress 35 % (3 MB)
103 22:04:08.117283 progress 40 % (4 MB)
104 22:04:08.194306 progress 45 % (5 MB)
105 22:04:08.296739 progress 50 % (5 MB)
106 22:04:08.390684 progress 55 % (6 MB)
107 22:04:08.494907 progress 60 % (6 MB)
108 22:04:08.582700 progress 65 % (7 MB)
109 22:04:08.660166 progress 70 % (7 MB)
110 22:04:08.742653 progress 75 % (8 MB)
111 22:04:08.827900 progress 80 % (8 MB)
112 22:04:08.908949 progress 85 % (9 MB)
113 22:04:08.989024 progress 90 % (9 MB)
114 22:04:09.074429 progress 95 % (10 MB)
115 22:04:09.155938 progress 100 % (11 MB)
116 22:04:09.169541 11 MB downloaded in 1.74 s (6.38 MB/s)
117 22:04:09.170267 end: 1.4.1 http-download (duration 00:00:02) [common]
119 22:04:09.171224 end: 1.4 download-retry (duration 00:00:02) [common]
120 22:04:09.171791 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 22:04:09.172376 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 22:04:09.172912 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:04:09.173518 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 22:04:09.174511 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu
125 22:04:09.175583 makedir: /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin
126 22:04:09.176735 makedir: /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/tests
127 22:04:09.179333 makedir: /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/results
128 22:04:09.180243 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-add-keys
129 22:04:09.183149 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-add-sources
130 22:04:09.185183 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-background-process-start
131 22:04:09.186323 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-background-process-stop
132 22:04:09.187507 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-common-functions
133 22:04:09.188117 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-echo-ipv4
134 22:04:09.188723 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-install-packages
135 22:04:09.189489 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-installed-packages
136 22:04:09.190045 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-os-build
137 22:04:09.190586 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-probe-channel
138 22:04:09.191167 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-probe-ip
139 22:04:09.191765 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-target-ip
140 22:04:09.192470 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-target-mac
141 22:04:09.193280 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-target-storage
142 22:04:09.193859 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-test-case
143 22:04:09.194848 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-test-event
144 22:04:09.196139 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-test-feedback
145 22:04:09.196783 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-test-raise
146 22:04:09.197399 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-test-reference
147 22:04:09.198025 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-test-runner
148 22:04:09.198613 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-test-set
149 22:04:09.199175 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-test-shell
150 22:04:09.199764 Updating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-install-packages (oe)
151 22:04:09.200601 Updating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/bin/lava-installed-packages (oe)
152 22:04:09.202948 Creating /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/environment
153 22:04:09.204251 LAVA metadata
154 22:04:09.204621 - LAVA_JOB_ID=962944
155 22:04:09.204897 - LAVA_DISPATCHER_IP=192.168.6.2
156 22:04:09.205347 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 22:04:09.206877 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 22:04:09.207295 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 22:04:09.207760 skipped lava-vland-overlay
160 22:04:09.208108 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 22:04:09.208768 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 22:04:09.209044 skipped lava-multinode-overlay
163 22:04:09.209341 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 22:04:09.209937 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 22:04:09.210275 Loading test definitions
166 22:04:09.210615 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 22:04:09.210873 Using /lava-962944 at stage 0
168 22:04:09.213323 uuid=962944_1.5.2.4.1 testdef=None
169 22:04:09.213732 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 22:04:09.214060 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 22:04:09.216733 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 22:04:09.217798 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 22:04:09.222615 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 22:04:09.223652 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 22:04:09.226099 runner path: /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/0/tests/0_igt-gpu-panfrost test_uuid 962944_1.5.2.4.1
178 22:04:09.226853 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 22:04:09.227786 Creating lava-test-runner.conf files
181 22:04:09.228066 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/962944/lava-overlay-rgz83bvu/lava-962944/0 for stage 0
182 22:04:09.228484 - 0_igt-gpu-panfrost
183 22:04:09.228883 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 22:04:09.229200 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 22:04:09.257914 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 22:04:09.258396 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 22:04:09.258739 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 22:04:09.259061 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 22:04:09.259381 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 22:04:16.258773 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 22:04:16.259229 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 22:04:16.259478 extracting modules file /var/lib/lava/dispatcher/tmp/962944/tftp-deploy-0dmxqmca/modules/modules.tar to /var/lib/lava/dispatcher/tmp/962944/extract-overlay-ramdisk-26g4_u8f/ramdisk
193 22:04:17.672540 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 22:04:17.673036 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 22:04:17.673320 [common] Applying overlay /var/lib/lava/dispatcher/tmp/962944/compress-overlay-bxyda6ma/overlay-1.5.2.5.tar.gz to ramdisk
196 22:04:17.673535 [common] Applying overlay /var/lib/lava/dispatcher/tmp/962944/compress-overlay-bxyda6ma/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/962944/extract-overlay-ramdisk-26g4_u8f/ramdisk
197 22:04:17.703676 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 22:04:17.704148 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 22:04:17.704429 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 22:04:17.704660 Converting downloaded kernel to a uImage
201 22:04:17.704971 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/962944/tftp-deploy-0dmxqmca/kernel/Image /var/lib/lava/dispatcher/tmp/962944/tftp-deploy-0dmxqmca/kernel/uImage
202 22:04:18.262776 output: Image Name:
203 22:04:18.263210 output: Created: Fri Nov 8 22:04:17 2024
204 22:04:18.263420 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 22:04:18.263625 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 22:04:18.263828 output: Load Address: 01080000
207 22:04:18.264066 output: Entry Point: 01080000
208 22:04:18.264276 output:
209 22:04:18.264610 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 22:04:18.264880 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 22:04:18.265152 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 22:04:18.265410 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 22:04:18.265667 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 22:04:18.265923 Building ramdisk /var/lib/lava/dispatcher/tmp/962944/extract-overlay-ramdisk-26g4_u8f/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/962944/extract-overlay-ramdisk-26g4_u8f/ramdisk
215 22:04:25.028474 >> 502366 blocks
216 22:04:45.874106 Adding RAMdisk u-boot header.
217 22:04:45.874811 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/962944/extract-overlay-ramdisk-26g4_u8f/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/962944/extract-overlay-ramdisk-26g4_u8f/ramdisk.cpio.gz.uboot
218 22:04:46.550227 output: Image Name:
219 22:04:46.550647 output: Created: Fri Nov 8 22:04:45 2024
220 22:04:46.551079 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 22:04:46.551494 output: Data Size: 65712507 Bytes = 64172.37 KiB = 62.67 MiB
222 22:04:46.551897 output: Load Address: 00000000
223 22:04:46.552354 output: Entry Point: 00000000
224 22:04:46.552754 output:
225 22:04:46.553720 rename /var/lib/lava/dispatcher/tmp/962944/extract-overlay-ramdisk-26g4_u8f/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/962944/tftp-deploy-0dmxqmca/ramdisk/ramdisk.cpio.gz.uboot
226 22:04:46.554444 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 22:04:46.554993 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 22:04:46.555522 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:19) [common]
229 22:04:46.556003 No LXC device requested
230 22:04:46.556521 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 22:04:46.557041 start: 1.7 deploy-device-env (timeout 00:09:19) [common]
232 22:04:46.557542 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 22:04:46.557957 Checking files for TFTP limit of 4294967296 bytes.
234 22:04:46.560667 end: 1 tftp-deploy (duration 00:00:41) [common]
235 22:04:46.561292 start: 2 uboot-action (timeout 00:05:00) [common]
236 22:04:46.561831 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 22:04:46.562339 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 22:04:46.562847 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 22:04:46.563383 Using kernel file from prepare-kernel: 962944/tftp-deploy-0dmxqmca/kernel/uImage
240 22:04:46.564043 substitutions:
241 22:04:46.564477 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 22:04:46.564884 - {DTB_ADDR}: 0x01070000
243 22:04:46.565286 - {DTB}: 962944/tftp-deploy-0dmxqmca/dtb/meson-g12b-a311d-libretech-cc.dtb
244 22:04:46.565688 - {INITRD}: 962944/tftp-deploy-0dmxqmca/ramdisk/ramdisk.cpio.gz.uboot
245 22:04:46.566085 - {KERNEL_ADDR}: 0x01080000
246 22:04:46.566479 - {KERNEL}: 962944/tftp-deploy-0dmxqmca/kernel/uImage
247 22:04:46.566876 - {LAVA_MAC}: None
248 22:04:46.567310 - {PRESEED_CONFIG}: None
249 22:04:46.567715 - {PRESEED_LOCAL}: None
250 22:04:46.568141 - {RAMDISK_ADDR}: 0x08000000
251 22:04:46.568541 - {RAMDISK}: 962944/tftp-deploy-0dmxqmca/ramdisk/ramdisk.cpio.gz.uboot
252 22:04:46.568944 - {ROOT_PART}: None
253 22:04:46.569339 - {ROOT}: None
254 22:04:46.569739 - {SERVER_IP}: 192.168.6.2
255 22:04:46.570141 - {TEE_ADDR}: 0x83000000
256 22:04:46.570536 - {TEE}: None
257 22:04:46.570930 Parsed boot commands:
258 22:04:46.571312 - setenv autoload no
259 22:04:46.571703 - setenv initrd_high 0xffffffff
260 22:04:46.572125 - setenv fdt_high 0xffffffff
261 22:04:46.572520 - dhcp
262 22:04:46.572911 - setenv serverip 192.168.6.2
263 22:04:46.573299 - tftpboot 0x01080000 962944/tftp-deploy-0dmxqmca/kernel/uImage
264 22:04:46.573693 - tftpboot 0x08000000 962944/tftp-deploy-0dmxqmca/ramdisk/ramdisk.cpio.gz.uboot
265 22:04:46.574085 - tftpboot 0x01070000 962944/tftp-deploy-0dmxqmca/dtb/meson-g12b-a311d-libretech-cc.dtb
266 22:04:46.574475 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 22:04:46.574874 - bootm 0x01080000 0x08000000 0x01070000
268 22:04:46.575399 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 22:04:46.576957 start: 2.3 connect-device (timeout 00:05:00) [common]
271 22:04:46.577430 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 22:04:46.592513 Setting prompt string to ['lava-test: # ']
273 22:04:46.594004 end: 2.3 connect-device (duration 00:00:00) [common]
274 22:04:46.594620 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 22:04:46.595534 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 22:04:46.596165 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 22:04:46.597354 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 22:04:46.634261 >> OK - accepted request
279 22:04:46.636542 Returned 0 in 0 seconds
280 22:04:46.737731 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 22:04:46.739469 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 22:04:46.740132 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 22:04:46.740659 Setting prompt string to ['Hit any key to stop autoboot']
285 22:04:46.741128 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 22:04:46.742768 Trying 192.168.56.21...
287 22:04:46.743256 Connected to conserv1.
288 22:04:46.743684 Escape character is '^]'.
289 22:04:46.744136
290 22:04:46.744570 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 22:04:46.745010
292 22:04:57.959672 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 22:04:57.960338 bl2_stage_init 0x01
294 22:04:57.960809 bl2_stage_init 0x81
295 22:04:57.965218 hw id: 0x0000 - pwm id 0x01
296 22:04:57.965752 bl2_stage_init 0xc1
297 22:04:57.966158 bl2_stage_init 0x02
298 22:04:57.966559
299 22:04:57.970748 L0:00000000
300 22:04:57.971194 L1:20000703
301 22:04:57.971584 L2:00008067
302 22:04:57.971971 L3:14000000
303 22:04:57.973654 B2:00402000
304 22:04:57.974096 B1:e0f83180
305 22:04:57.974482
306 22:04:57.974869 TE: 58124
307 22:04:57.975254
308 22:04:57.984727 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 22:04:57.985185
310 22:04:57.985574 Board ID = 1
311 22:04:57.985957 Set A53 clk to 24M
312 22:04:57.986338 Set A73 clk to 24M
313 22:04:57.990475 Set clk81 to 24M
314 22:04:57.990920 A53 clk: 1200 MHz
315 22:04:57.991306 A73 clk: 1200 MHz
316 22:04:57.996513 CLK81: 166.6M
317 22:04:57.996953 smccc: 00012a91
318 22:04:58.001803 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 22:04:58.002255 board id: 1
320 22:04:58.007180 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 22:04:58.020950 fw parse done
322 22:04:58.026806 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 22:04:58.068479 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 22:04:58.080330 PIEI prepare done
325 22:04:58.080779 fastboot data load
326 22:04:58.081168 fastboot data verify
327 22:04:58.086005 verify result: 266
328 22:04:58.091603 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 22:04:58.092112 LPDDR4 probe
330 22:04:58.092499 ddr clk to 1584MHz
331 22:04:58.099625 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 22:04:58.135837
333 22:04:58.136373 dmc_version 0001
334 22:04:58.143400 Check phy result
335 22:04:58.149467 INFO : End of CA training
336 22:04:58.149922 INFO : End of initialization
337 22:04:58.155042 INFO : Training has run successfully!
338 22:04:58.155491 Check phy result
339 22:04:58.160581 INFO : End of initialization
340 22:04:58.161028 INFO : End of read enable training
341 22:04:58.166199 INFO : End of fine write leveling
342 22:04:58.171792 INFO : End of Write leveling coarse delay
343 22:04:58.172282 INFO : Training has run successfully!
344 22:04:58.172677 Check phy result
345 22:04:58.177414 INFO : End of initialization
346 22:04:58.177876 INFO : End of read dq deskew training
347 22:04:58.183320 INFO : End of MPR read delay center optimization
348 22:04:58.188637 INFO : End of write delay center optimization
349 22:04:58.194259 INFO : End of read delay center optimization
350 22:04:58.194780 INFO : End of max read latency training
351 22:04:58.199841 INFO : Training has run successfully!
352 22:04:58.200393 1D training succeed
353 22:04:58.209010 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 22:04:58.256612 Check phy result
355 22:04:58.257191 INFO : End of initialization
356 22:04:58.279140 INFO : End of 2D read delay Voltage center optimization
357 22:04:58.298549 INFO : End of 2D read delay Voltage center optimization
358 22:04:58.351448 INFO : End of 2D write delay Voltage center optimization
359 22:04:58.400918 INFO : End of 2D write delay Voltage center optimization
360 22:04:58.406455 INFO : Training has run successfully!
361 22:04:58.406936
362 22:04:58.407343 channel==0
363 22:04:58.412158 RxClkDly_Margin_A0==88 ps 9
364 22:04:58.412748 TxDqDly_Margin_A0==98 ps 10
365 22:04:58.415566 RxClkDly_Margin_A1==88 ps 9
366 22:04:58.416144 TxDqDly_Margin_A1==88 ps 9
367 22:04:58.421067 TrainedVREFDQ_A0==74
368 22:04:58.421528 TrainedVREFDQ_A1==74
369 22:04:58.421933 VrefDac_Margin_A0==25
370 22:04:58.426508 DeviceVref_Margin_A0==40
371 22:04:58.426963 VrefDac_Margin_A1==25
372 22:04:58.432166 DeviceVref_Margin_A1==40
373 22:04:58.432623
374 22:04:58.433025
375 22:04:58.433419 channel==1
376 22:04:58.433807 RxClkDly_Margin_A0==98 ps 10
377 22:04:58.437775 TxDqDly_Margin_A0==98 ps 10
378 22:04:58.438236 RxClkDly_Margin_A1==98 ps 10
379 22:04:58.443387 TxDqDly_Margin_A1==88 ps 9
380 22:04:58.443844 TrainedVREFDQ_A0==77
381 22:04:58.444280 TrainedVREFDQ_A1==77
382 22:04:58.448928 VrefDac_Margin_A0==22
383 22:04:58.449383 DeviceVref_Margin_A0==37
384 22:04:58.454529 VrefDac_Margin_A1==24
385 22:04:58.454984 DeviceVref_Margin_A1==37
386 22:04:58.455376
387 22:04:58.460335 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 22:04:58.460880
389 22:04:58.488098 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 22:04:58.493764 2D training succeed
391 22:04:58.499502 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 22:04:58.500061 auto size-- 65535DDR cs0 size: 2048MB
393 22:04:58.504991 DDR cs1 size: 2048MB
394 22:04:58.505504 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 22:04:58.510582 cs0 DataBus test pass
396 22:04:58.511092 cs1 DataBus test pass
397 22:04:58.511490 cs0 AddrBus test pass
398 22:04:58.516253 cs1 AddrBus test pass
399 22:04:58.516771
400 22:04:58.517179 100bdlr_step_size ps== 420
401 22:04:58.517583 result report
402 22:04:58.521844 boot times 0Enable ddr reg access
403 22:04:58.528537 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 22:04:58.542838 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 22:04:59.115800 0.0;M3 CHK:0;cm4_sp_mode 0
406 22:04:59.116450 MVN_1=0x00000000
407 22:04:59.121376 MVN_2=0x00000000
408 22:04:59.127050 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 22:04:59.127540 OPS=0x10
410 22:04:59.127960 ring efuse init
411 22:04:59.128402 chipver efuse init
412 22:04:59.132643 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 22:04:59.138218 [0.018960 Inits done]
414 22:04:59.138696 secure task start!
415 22:04:59.139109 high task start!
416 22:04:59.141858 low task start!
417 22:04:59.142339 run into bl31
418 22:04:59.149483 NOTICE: BL31: v1.3(release):4fc40b1
419 22:04:59.156343 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 22:04:59.156834 NOTICE: BL31: G12A normal boot!
421 22:04:59.182683 NOTICE: BL31: BL33 decompress pass
422 22:04:59.187559 ERROR: Error initializing runtime service opteed_fast
423 22:05:00.421238
424 22:05:00.421827
425 22:05:00.428637 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 22:05:00.429110
427 22:05:00.429529 Model: Libre Computer AML-A311D-CC Alta
428 22:05:00.638068 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 22:05:00.661538 DRAM: 2 GiB (effective 3.8 GiB)
430 22:05:00.804487 Core: 408 devices, 31 uclasses, devicetree: separate
431 22:05:00.810322 WDT: Not starting watchdog@f0d0
432 22:05:00.842592 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 22:05:00.855032 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 22:05:00.860168 ** Bad device specification mmc 0 **
435 22:05:00.870467 Card did not respond to voltage select! : -110
436 22:05:00.878032 ** Bad device specification mmc 0 **
437 22:05:00.878474 Couldn't find partition mmc 0
438 22:05:00.886422 Card did not respond to voltage select! : -110
439 22:05:00.892017 ** Bad device specification mmc 0 **
440 22:05:00.892454 Couldn't find partition mmc 0
441 22:05:00.897003 Error: could not access storage.
442 22:05:02.160127 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 22:05:02.160737 bl2_stage_init 0x01
444 22:05:02.161166 bl2_stage_init 0x81
445 22:05:02.165579 hw id: 0x0000 - pwm id 0x01
446 22:05:02.166023 bl2_stage_init 0xc1
447 22:05:02.166436 bl2_stage_init 0x02
448 22:05:02.166840
449 22:05:02.171170 L0:00000000
450 22:05:02.171601 L1:20000703
451 22:05:02.172031 L2:00008067
452 22:05:02.172434 L3:14000000
453 22:05:02.176823 B2:00402000
454 22:05:02.177250 B1:e0f83180
455 22:05:02.177649
456 22:05:02.178052 TE: 58124
457 22:05:02.178452
458 22:05:02.182355 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 22:05:02.182788
460 22:05:02.183216 Board ID = 1
461 22:05:02.187970 Set A53 clk to 24M
462 22:05:02.188469 Set A73 clk to 24M
463 22:05:02.188903 Set clk81 to 24M
464 22:05:02.193540 A53 clk: 1200 MHz
465 22:05:02.194024 A73 clk: 1200 MHz
466 22:05:02.194445 CLK81: 166.6M
467 22:05:02.194852 smccc: 00012a92
468 22:05:02.199110 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 22:05:02.204884 board id: 1
470 22:05:02.210657 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 22:05:02.221271 fw parse done
472 22:05:02.227227 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 22:05:02.269918 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 22:05:02.280872 PIEI prepare done
475 22:05:02.281332 fastboot data load
476 22:05:02.281751 fastboot data verify
477 22:05:02.286398 verify result: 266
478 22:05:02.291944 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 22:05:02.292422 LPDDR4 probe
480 22:05:02.292827 ddr clk to 1584MHz
481 22:05:02.300027 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 22:05:02.337312
483 22:05:02.337889 dmc_version 0001
484 22:05:02.343927 Check phy result
485 22:05:02.349849 INFO : End of CA training
486 22:05:02.350331 INFO : End of initialization
487 22:05:02.355397 INFO : Training has run successfully!
488 22:05:02.355912 Check phy result
489 22:05:02.360937 INFO : End of initialization
490 22:05:02.361384 INFO : End of read enable training
491 22:05:02.366563 INFO : End of fine write leveling
492 22:05:02.372191 INFO : End of Write leveling coarse delay
493 22:05:02.372631 INFO : Training has run successfully!
494 22:05:02.373041 Check phy result
495 22:05:02.377829 INFO : End of initialization
496 22:05:02.378281 INFO : End of read dq deskew training
497 22:05:02.383381 INFO : End of MPR read delay center optimization
498 22:05:02.388972 INFO : End of write delay center optimization
499 22:05:02.394607 INFO : End of read delay center optimization
500 22:05:02.395121 INFO : End of max read latency training
501 22:05:02.400168 INFO : Training has run successfully!
502 22:05:02.400653 1D training succeed
503 22:05:02.409358 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 22:05:02.457101 Check phy result
505 22:05:02.457667 INFO : End of initialization
506 22:05:02.478677 INFO : End of 2D read delay Voltage center optimization
507 22:05:02.498962 INFO : End of 2D read delay Voltage center optimization
508 22:05:02.551158 INFO : End of 2D write delay Voltage center optimization
509 22:05:02.600450 INFO : End of 2D write delay Voltage center optimization
510 22:05:02.605872 INFO : Training has run successfully!
511 22:05:02.606323
512 22:05:02.606742 channel==0
513 22:05:02.611499 RxClkDly_Margin_A0==88 ps 9
514 22:05:02.611962 TxDqDly_Margin_A0==98 ps 10
515 22:05:02.614829 RxClkDly_Margin_A1==88 ps 9
516 22:05:02.615253 TxDqDly_Margin_A1==98 ps 10
517 22:05:02.620564 TrainedVREFDQ_A0==74
518 22:05:02.621027 TrainedVREFDQ_A1==74
519 22:05:02.621436 VrefDac_Margin_A0==25
520 22:05:02.626057 DeviceVref_Margin_A0==40
521 22:05:02.626482 VrefDac_Margin_A1==25
522 22:05:02.631708 DeviceVref_Margin_A1==40
523 22:05:02.632173
524 22:05:02.632574
525 22:05:02.632971 channel==1
526 22:05:02.633360 RxClkDly_Margin_A0==98 ps 10
527 22:05:02.637340 TxDqDly_Margin_A0==88 ps 9
528 22:05:02.637773 RxClkDly_Margin_A1==98 ps 10
529 22:05:02.642884 TxDqDly_Margin_A1==88 ps 9
530 22:05:02.643315 TrainedVREFDQ_A0==74
531 22:05:02.643716 TrainedVREFDQ_A1==77
532 22:05:02.648513 VrefDac_Margin_A0==22
533 22:05:02.648935 DeviceVref_Margin_A0==40
534 22:05:02.654138 VrefDac_Margin_A1==22
535 22:05:02.654561 DeviceVref_Margin_A1==37
536 22:05:02.654956
537 22:05:02.659722 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 22:05:02.660224
539 22:05:02.687698 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
540 22:05:02.693308 2D training succeed
541 22:05:02.698878 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 22:05:02.699323 auto size-- 65535DDR cs0 size: 2048MB
543 22:05:02.704544 DDR cs1 size: 2048MB
544 22:05:02.704985 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 22:05:02.710094 cs0 DataBus test pass
546 22:05:02.710534 cs1 DataBus test pass
547 22:05:02.710937 cs0 AddrBus test pass
548 22:05:02.715659 cs1 AddrBus test pass
549 22:05:02.716125
550 22:05:02.716534 100bdlr_step_size ps== 420
551 22:05:02.716943 result report
552 22:05:02.721350 boot times 0Enable ddr reg access
553 22:05:02.728825 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 22:05:02.742333 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 22:05:03.316271 0.0;M3 CHK:0;cm4_sp_mode 0
556 22:05:03.316902 MVN_1=0x00000000
557 22:05:03.321822 MVN_2=0x00000000
558 22:05:03.327422 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 22:05:03.327912 OPS=0x10
560 22:05:03.329066 ring efuse init
561 22:05:03.329558 chipver efuse init
562 22:05:03.335754 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 22:05:03.336314 [0.018961 Inits done]
564 22:05:03.336724 secure task start!
565 22:05:03.343253 high task start!
566 22:05:03.343737 low task start!
567 22:05:03.344173 run into bl31
568 22:05:03.349865 NOTICE: BL31: v1.3(release):4fc40b1
569 22:05:03.357647 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 22:05:03.358130 NOTICE: BL31: G12A normal boot!
571 22:05:03.383144 NOTICE: BL31: BL33 decompress pass
572 22:05:03.388710 ERROR: Error initializing runtime service opteed_fast
573 22:05:04.621619
574 22:05:04.622260
575 22:05:04.630167 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 22:05:04.630728
577 22:05:04.631239 Model: Libre Computer AML-A311D-CC Alta
578 22:05:04.838610 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 22:05:04.861879 DRAM: 2 GiB (effective 3.8 GiB)
580 22:05:05.004801 Core: 408 devices, 31 uclasses, devicetree: separate
581 22:05:05.010683 WDT: Not starting watchdog@f0d0
582 22:05:05.042959 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 22:05:05.055335 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 22:05:05.060506 ** Bad device specification mmc 0 **
585 22:05:05.070723 Card did not respond to voltage select! : -110
586 22:05:05.078484 ** Bad device specification mmc 0 **
587 22:05:05.078959 Couldn't find partition mmc 0
588 22:05:05.086740 Card did not respond to voltage select! : -110
589 22:05:05.092192 ** Bad device specification mmc 0 **
590 22:05:05.092655 Couldn't find partition mmc 0
591 22:05:05.097315 Error: could not access storage.
592 22:05:05.439940 Net: eth0: ethernet@ff3f0000
593 22:05:05.440605 starting USB...
594 22:05:05.691687 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 22:05:05.692374 Starting the controller
596 22:05:05.698657 USB XHCI 1.10
597 22:05:07.409037 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 22:05:07.409745 bl2_stage_init 0x01
599 22:05:07.410223 bl2_stage_init 0x81
600 22:05:07.414803 hw id: 0x0000 - pwm id 0x01
601 22:05:07.415338 bl2_stage_init 0xc1
602 22:05:07.415801 bl2_stage_init 0x02
603 22:05:07.416298
604 22:05:07.420138 L0:00000000
605 22:05:07.420668 L1:20000703
606 22:05:07.421131 L2:00008067
607 22:05:07.421585 L3:14000000
608 22:05:07.425688 B2:00402000
609 22:05:07.426179 B1:e0f83180
610 22:05:07.426644
611 22:05:07.427093 TE: 58167
612 22:05:07.427541
613 22:05:07.431176 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 22:05:07.431653
615 22:05:07.432142 Board ID = 1
616 22:05:07.436784 Set A53 clk to 24M
617 22:05:07.437274 Set A73 clk to 24M
618 22:05:07.437726 Set clk81 to 24M
619 22:05:07.442351 A53 clk: 1200 MHz
620 22:05:07.442827 A73 clk: 1200 MHz
621 22:05:07.443324 CLK81: 166.6M
622 22:05:07.443796 smccc: 00012abe
623 22:05:07.448014 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 22:05:07.453588 board id: 1
625 22:05:07.459482 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 22:05:07.470328 fw parse done
627 22:05:07.476290 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 22:05:07.518805 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 22:05:07.529568 PIEI prepare done
630 22:05:07.530078 fastboot data load
631 22:05:07.530536 fastboot data verify
632 22:05:07.535353 verify result: 266
633 22:05:07.540898 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 22:05:07.541409 LPDDR4 probe
635 22:05:07.541870 ddr clk to 1584MHz
636 22:05:07.548858 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 22:05:07.586213
638 22:05:07.586827 dmc_version 0001
639 22:05:07.592747 Check phy result
640 22:05:07.598631 INFO : End of CA training
641 22:05:07.599122 INFO : End of initialization
642 22:05:07.604277 INFO : Training has run successfully!
643 22:05:07.604763 Check phy result
644 22:05:07.609839 INFO : End of initialization
645 22:05:07.610327 INFO : End of read enable training
646 22:05:07.615394 INFO : End of fine write leveling
647 22:05:07.621064 INFO : End of Write leveling coarse delay
648 22:05:07.621559 INFO : Training has run successfully!
649 22:05:07.622030 Check phy result
650 22:05:07.626620 INFO : End of initialization
651 22:05:07.627106 INFO : End of read dq deskew training
652 22:05:07.632245 INFO : End of MPR read delay center optimization
653 22:05:07.637879 INFO : End of write delay center optimization
654 22:05:07.644821 INFO : End of read delay center optimization
655 22:05:07.645213 INFO : End of max read latency training
656 22:05:07.649147 INFO : Training has run successfully!
657 22:05:07.649981 1D training succeed
658 22:05:07.658279 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 22:05:07.706008 Check phy result
660 22:05:07.706605 INFO : End of initialization
661 22:05:07.727720 INFO : End of 2D read delay Voltage center optimization
662 22:05:07.747937 INFO : End of 2D read delay Voltage center optimization
663 22:05:07.799926 INFO : End of 2D write delay Voltage center optimization
664 22:05:07.849375 INFO : End of 2D write delay Voltage center optimization
665 22:05:07.854858 INFO : Training has run successfully!
666 22:05:07.855332
667 22:05:07.855755 channel==0
668 22:05:07.860442 RxClkDly_Margin_A0==88 ps 9
669 22:05:07.860924 TxDqDly_Margin_A0==98 ps 10
670 22:05:07.866065 RxClkDly_Margin_A1==88 ps 9
671 22:05:07.866531 TxDqDly_Margin_A1==98 ps 10
672 22:05:07.866953 TrainedVREFDQ_A0==74
673 22:05:07.871743 TrainedVREFDQ_A1==76
674 22:05:07.872279 VrefDac_Margin_A0==25
675 22:05:07.872700 DeviceVref_Margin_A0==40
676 22:05:07.877262 VrefDac_Margin_A1==25
677 22:05:07.877738 DeviceVref_Margin_A1==38
678 22:05:07.878151
679 22:05:07.878555
680 22:05:07.882976 channel==1
681 22:05:07.883448 RxClkDly_Margin_A0==98 ps 10
682 22:05:07.883863 TxDqDly_Margin_A0==88 ps 9
683 22:05:07.888475 RxClkDly_Margin_A1==88 ps 9
684 22:05:07.888952 TxDqDly_Margin_A1==88 ps 9
685 22:05:07.894073 TrainedVREFDQ_A0==74
686 22:05:07.894542 TrainedVREFDQ_A1==77
687 22:05:07.894956 VrefDac_Margin_A0==22
688 22:05:07.899745 DeviceVref_Margin_A0==40
689 22:05:07.900239 VrefDac_Margin_A1==24
690 22:05:07.905266 DeviceVref_Margin_A1==37
691 22:05:07.905738
692 22:05:07.906149 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 22:05:07.906555
694 22:05:07.938846 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
695 22:05:07.939356 2D training succeed
696 22:05:07.944456 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 22:05:07.949969 auto size-- 65535DDR cs0 size: 2048MB
698 22:05:07.950454 DDR cs1 size: 2048MB
699 22:05:07.955683 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 22:05:07.956197 cs0 DataBus test pass
701 22:05:07.961149 cs1 DataBus test pass
702 22:05:07.961618 cs0 AddrBus test pass
703 22:05:07.962028 cs1 AddrBus test pass
704 22:05:07.962429
705 22:05:07.966759 100bdlr_step_size ps== 420
706 22:05:07.967237 result report
707 22:05:07.972358 boot times 0Enable ddr reg access
708 22:05:07.977726 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 22:05:07.991095 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 22:05:08.565303 0.0;M3 CHK:0;cm4_sp_mode 0
711 22:05:08.565931 MVN_1=0x00000000
712 22:05:08.570389 MVN_2=0x00000000
713 22:05:08.576112 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 22:05:08.576635 OPS=0x10
715 22:05:08.577034 ring efuse init
716 22:05:08.577420 chipver efuse init
717 22:05:08.584265 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 22:05:08.584740 [0.018961 Inits done]
719 22:05:08.591811 secure task start!
720 22:05:08.592310 high task start!
721 22:05:08.592697 low task start!
722 22:05:08.593077 run into bl31
723 22:05:08.598450 NOTICE: BL31: v1.3(release):4fc40b1
724 22:05:08.606277 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 22:05:08.606737 NOTICE: BL31: G12A normal boot!
726 22:05:08.631716 NOTICE: BL31: BL33 decompress pass
727 22:05:08.637297 ERROR: Error initializing runtime service opteed_fast
728 22:05:09.870156
729 22:05:09.870776
730 22:05:09.878609 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 22:05:09.879078
732 22:05:09.879492 Model: Libre Computer AML-A311D-CC Alta
733 22:05:10.087068 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 22:05:10.110319 DRAM: 2 GiB (effective 3.8 GiB)
735 22:05:10.253315 Core: 408 devices, 31 uclasses, devicetree: separate
736 22:05:10.259188 WDT: Not starting watchdog@f0d0
737 22:05:10.291464 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 22:05:10.303929 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 22:05:10.308874 ** Bad device specification mmc 0 **
740 22:05:10.319220 Card did not respond to voltage select! : -110
741 22:05:10.326868 ** Bad device specification mmc 0 **
742 22:05:10.327334 Couldn't find partition mmc 0
743 22:05:10.335213 Card did not respond to voltage select! : -110
744 22:05:10.340695 ** Bad device specification mmc 0 **
745 22:05:10.341153 Couldn't find partition mmc 0
746 22:05:10.345814 Error: could not access storage.
747 22:05:10.689603 Net: eth0: ethernet@ff3f0000
748 22:05:10.690197 starting USB...
749 22:05:10.941481 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 22:05:10.942034 Starting the controller
751 22:05:10.949385 USB XHCI 1.10
752 22:05:13.109041 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 22:05:13.109647 bl2_stage_init 0x01
754 22:05:13.110064 bl2_stage_init 0x81
755 22:05:13.114617 hw id: 0x0000 - pwm id 0x01
756 22:05:13.115084 bl2_stage_init 0xc1
757 22:05:13.115496 bl2_stage_init 0x02
758 22:05:13.115896
759 22:05:13.120203 L0:00000000
760 22:05:13.120660 L1:20000703
761 22:05:13.121067 L2:00008067
762 22:05:13.121463 L3:14000000
763 22:05:13.123210 B2:00402000
764 22:05:13.123659 B1:e0f83180
765 22:05:13.124099
766 22:05:13.124504 TE: 58124
767 22:05:13.124905
768 22:05:13.134312 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 22:05:13.134772
770 22:05:13.135183 Board ID = 1
771 22:05:13.135578 Set A53 clk to 24M
772 22:05:13.135969 Set A73 clk to 24M
773 22:05:13.139827 Set clk81 to 24M
774 22:05:13.140308 A53 clk: 1200 MHz
775 22:05:13.140720 A73 clk: 1200 MHz
776 22:05:13.143441 CLK81: 166.6M
777 22:05:13.143890 smccc: 00012a92
778 22:05:13.148843 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 22:05:13.154424 board id: 1
780 22:05:13.159519 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 22:05:13.170225 fw parse done
782 22:05:13.176147 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 22:05:13.218830 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 22:05:13.229809 PIEI prepare done
785 22:05:13.230262 fastboot data load
786 22:05:13.230670 fastboot data verify
787 22:05:13.235500 verify result: 266
788 22:05:13.241006 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 22:05:13.241467 LPDDR4 probe
790 22:05:13.241873 ddr clk to 1584MHz
791 22:05:13.248969 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 22:05:13.286292
793 22:05:13.286775 dmc_version 0001
794 22:05:13.292939 Check phy result
795 22:05:13.298777 INFO : End of CA training
796 22:05:13.299231 INFO : End of initialization
797 22:05:13.304338 INFO : Training has run successfully!
798 22:05:13.304792 Check phy result
799 22:05:13.310019 INFO : End of initialization
800 22:05:13.310472 INFO : End of read enable training
801 22:05:13.315515 INFO : End of fine write leveling
802 22:05:13.321171 INFO : End of Write leveling coarse delay
803 22:05:13.321624 INFO : Training has run successfully!
804 22:05:13.322030 Check phy result
805 22:05:13.326812 INFO : End of initialization
806 22:05:13.327263 INFO : End of read dq deskew training
807 22:05:13.332304 INFO : End of MPR read delay center optimization
808 22:05:13.338007 INFO : End of write delay center optimization
809 22:05:13.343511 INFO : End of read delay center optimization
810 22:05:13.344028 INFO : End of max read latency training
811 22:05:13.349109 INFO : Training has run successfully!
812 22:05:13.349565 1D training succeed
813 22:05:13.358338 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 22:05:13.405961 Check phy result
815 22:05:13.406468 INFO : End of initialization
816 22:05:13.427704 INFO : End of 2D read delay Voltage center optimization
817 22:05:13.447613 INFO : End of 2D read delay Voltage center optimization
818 22:05:13.499807 INFO : End of 2D write delay Voltage center optimization
819 22:05:13.548830 INFO : End of 2D write delay Voltage center optimization
820 22:05:13.554389 INFO : Training has run successfully!
821 22:05:13.554860
822 22:05:13.555275 channel==0
823 22:05:13.560014 RxClkDly_Margin_A0==88 ps 9
824 22:05:13.560489 TxDqDly_Margin_A0==98 ps 10
825 22:05:13.563294 RxClkDly_Margin_A1==88 ps 9
826 22:05:13.563757 TxDqDly_Margin_A1==98 ps 10
827 22:05:13.568863 TrainedVREFDQ_A0==74
828 22:05:13.569356 TrainedVREFDQ_A1==74
829 22:05:13.574454 VrefDac_Margin_A0==25
830 22:05:13.574938 DeviceVref_Margin_A0==40
831 22:05:13.575344 VrefDac_Margin_A1==25
832 22:05:13.579956 DeviceVref_Margin_A1==40
833 22:05:13.580455
834 22:05:13.580845
835 22:05:13.581228 channel==1
836 22:05:13.581610 RxClkDly_Margin_A0==98 ps 10
837 22:05:13.585575 TxDqDly_Margin_A0==98 ps 10
838 22:05:13.586025 RxClkDly_Margin_A1==98 ps 10
839 22:05:13.591169 TxDqDly_Margin_A1==88 ps 9
840 22:05:13.591615 TrainedVREFDQ_A0==77
841 22:05:13.592032 TrainedVREFDQ_A1==77
842 22:05:13.596817 VrefDac_Margin_A0==22
843 22:05:13.597255 DeviceVref_Margin_A0==37
844 22:05:13.602395 VrefDac_Margin_A1==22
845 22:05:13.602837 DeviceVref_Margin_A1==37
846 22:05:13.603220
847 22:05:13.607921 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 22:05:13.608391
849 22:05:13.635893 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
850 22:05:13.641493 2D training succeed
851 22:05:13.647123 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 22:05:13.647570 auto size-- 65535DDR cs0 size: 2048MB
853 22:05:13.652730 DDR cs1 size: 2048MB
854 22:05:13.653171 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 22:05:13.658337 cs0 DataBus test pass
856 22:05:13.658777 cs1 DataBus test pass
857 22:05:13.659162 cs0 AddrBus test pass
858 22:05:13.663924 cs1 AddrBus test pass
859 22:05:13.664405
860 22:05:13.664797 100bdlr_step_size ps== 420
861 22:05:13.665188 result report
862 22:05:13.669517 boot times 0Enable ddr reg access
863 22:05:13.677387 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 22:05:13.690764 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 22:05:14.262713 0.0;M3 CHK:0;cm4_sp_mode 0
866 22:05:14.263316 MVN_1=0x00000000
867 22:05:14.268297 MVN_2=0x00000000
868 22:05:14.274021 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 22:05:14.274477 OPS=0x10
870 22:05:14.274890 ring efuse init
871 22:05:14.275291 chipver efuse init
872 22:05:14.279554 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 22:05:14.285184 [0.018961 Inits done]
874 22:05:14.285634 secure task start!
875 22:05:14.286039 high task start!
876 22:05:14.289758 low task start!
877 22:05:14.290208 run into bl31
878 22:05:14.296461 NOTICE: BL31: v1.3(release):4fc40b1
879 22:05:14.303382 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 22:05:14.303889 NOTICE: BL31: G12A normal boot!
881 22:05:14.329683 NOTICE: BL31: BL33 decompress pass
882 22:05:14.335339 ERROR: Error initializing runtime service opteed_fast
883 22:05:15.568312
884 22:05:15.568940
885 22:05:15.576675 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 22:05:15.577170
887 22:05:15.577591 Model: Libre Computer AML-A311D-CC Alta
888 22:05:15.785069 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 22:05:15.808503 DRAM: 2 GiB (effective 3.8 GiB)
890 22:05:15.951476 Core: 408 devices, 31 uclasses, devicetree: separate
891 22:05:15.957289 WDT: Not starting watchdog@f0d0
892 22:05:15.989561 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 22:05:16.001974 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 22:05:16.006979 ** Bad device specification mmc 0 **
895 22:05:16.017349 Card did not respond to voltage select! : -110
896 22:05:16.025014 ** Bad device specification mmc 0 **
897 22:05:16.025508 Couldn't find partition mmc 0
898 22:05:16.033338 Card did not respond to voltage select! : -110
899 22:05:16.038850 ** Bad device specification mmc 0 **
900 22:05:16.039307 Couldn't find partition mmc 0
901 22:05:16.043181 Error: could not access storage.
902 22:05:16.386338 Net: eth0: ethernet@ff3f0000
903 22:05:16.386905 starting USB...
904 22:05:16.638103 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 22:05:16.638711 Starting the controller
906 22:05:16.645080 USB XHCI 1.10
907 22:05:18.508719 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 22:05:18.509414 bl2_stage_init 0x01
909 22:05:18.509924 bl2_stage_init 0x81
910 22:05:18.514145 hw id: 0x0000 - pwm id 0x01
911 22:05:18.514704 bl2_stage_init 0xc1
912 22:05:18.515188 bl2_stage_init 0x02
913 22:05:18.515660
914 22:05:18.519768 L0:00000000
915 22:05:18.520329 L1:20000703
916 22:05:18.520790 L2:00008067
917 22:05:18.521234 L3:14000000
918 22:05:18.522628 B2:00402000
919 22:05:18.523095 B1:e0f83180
920 22:05:18.523541
921 22:05:18.524011 TE: 58159
922 22:05:18.524466
923 22:05:18.533792 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 22:05:18.534296
925 22:05:18.534744 Board ID = 1
926 22:05:18.535184 Set A53 clk to 24M
927 22:05:18.535621 Set A73 clk to 24M
928 22:05:18.539377 Set clk81 to 24M
929 22:05:18.539862 A53 clk: 1200 MHz
930 22:05:18.540347 A73 clk: 1200 MHz
931 22:05:18.544961 CLK81: 166.6M
932 22:05:18.545434 smccc: 00012ab5
933 22:05:18.550576 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 22:05:18.551054 board id: 1
935 22:05:18.558321 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 22:05:18.569847 fw parse done
937 22:05:18.574873 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 22:05:18.618468 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 22:05:18.629348 PIEI prepare done
940 22:05:18.629825 fastboot data load
941 22:05:18.630258 fastboot data verify
942 22:05:18.635277 verify result: 266
943 22:05:18.640704 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 22:05:18.641252 LPDDR4 probe
945 22:05:18.641702 ddr clk to 1584MHz
946 22:05:18.648732 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 22:05:18.684900
948 22:05:18.685475 dmc_version 0001
949 22:05:18.691493 Check phy result
950 22:05:18.698301 INFO : End of CA training
951 22:05:18.698766 INFO : End of initialization
952 22:05:18.704022 INFO : Training has run successfully!
953 22:05:18.704485 Check phy result
954 22:05:18.709558 INFO : End of initialization
955 22:05:18.710076 INFO : End of read enable training
956 22:05:18.715347 INFO : End of fine write leveling
957 22:05:18.720883 INFO : End of Write leveling coarse delay
958 22:05:18.721396 INFO : Training has run successfully!
959 22:05:18.721845 Check phy result
960 22:05:18.726470 INFO : End of initialization
961 22:05:18.726979 INFO : End of read dq deskew training
962 22:05:18.732133 INFO : End of MPR read delay center optimization
963 22:05:18.737648 INFO : End of write delay center optimization
964 22:05:18.743267 INFO : End of read delay center optimization
965 22:05:18.743751 INFO : End of max read latency training
966 22:05:18.748894 INFO : Training has run successfully!
967 22:05:18.749369 1D training succeed
968 22:05:18.757415 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 22:05:18.805803 Check phy result
970 22:05:18.806339 INFO : End of initialization
971 22:05:18.827235 INFO : End of 2D read delay Voltage center optimization
972 22:05:18.847313 INFO : End of 2D read delay Voltage center optimization
973 22:05:18.899360 INFO : End of 2D write delay Voltage center optimization
974 22:05:18.948796 INFO : End of 2D write delay Voltage center optimization
975 22:05:18.954274 INFO : Training has run successfully!
976 22:05:18.954814
977 22:05:18.955279 channel==0
978 22:05:18.959790 RxClkDly_Margin_A0==88 ps 9
979 22:05:18.960361 TxDqDly_Margin_A0==98 ps 10
980 22:05:18.965342 RxClkDly_Margin_A1==88 ps 9
981 22:05:18.965841 TxDqDly_Margin_A1==98 ps 10
982 22:05:18.966297 TrainedVREFDQ_A0==74
983 22:05:18.970916 TrainedVREFDQ_A1==74
984 22:05:18.971414 VrefDac_Margin_A0==25
985 22:05:18.971857 DeviceVref_Margin_A0==40
986 22:05:18.976530 VrefDac_Margin_A1==25
987 22:05:18.977061 DeviceVref_Margin_A1==40
988 22:05:18.977509
989 22:05:18.977948
990 22:05:18.982632 channel==1
991 22:05:18.983160 RxClkDly_Margin_A0==98 ps 10
992 22:05:18.983613 TxDqDly_Margin_A0==98 ps 10
993 22:05:18.987897 RxClkDly_Margin_A1==88 ps 9
994 22:05:18.988423 TxDqDly_Margin_A1==88 ps 9
995 22:05:18.993335 TrainedVREFDQ_A0==77
996 22:05:18.993820 TrainedVREFDQ_A1==77
997 22:05:18.994262 VrefDac_Margin_A0==22
998 22:05:18.999016 DeviceVref_Margin_A0==37
999 22:05:18.999490 VrefDac_Margin_A1==24
1000 22:05:19.004574 DeviceVref_Margin_A1==37
1001 22:05:19.005054
1002 22:05:19.005501 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 22:05:19.005944
1004 22:05:19.038109 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
1005 22:05:19.038683 2D training succeed
1006 22:05:19.044037 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 22:05:19.049252 auto size-- 65535DDR cs0 size: 2048MB
1008 22:05:19.049743 DDR cs1 size: 2048MB
1009 22:05:19.054888 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 22:05:19.055380 cs0 DataBus test pass
1011 22:05:19.060452 cs1 DataBus test pass
1012 22:05:19.060931 cs0 AddrBus test pass
1013 22:05:19.061377 cs1 AddrBus test pass
1014 22:05:19.061815
1015 22:05:19.066193 100bdlr_step_size ps== 420
1016 22:05:19.066686 result report
1017 22:05:19.071676 boot times 0Enable ddr reg access
1018 22:05:19.076978 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 22:05:19.089432 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 22:05:19.662520 0.0;M3 CHK:0;cm4_sp_mode 0
1021 22:05:19.663179 MVN_1=0x00000000
1022 22:05:19.668034 MVN_2=0x00000000
1023 22:05:19.673721 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 22:05:19.674219 OPS=0x10
1025 22:05:19.674668 ring efuse init
1026 22:05:19.675109 chipver efuse init
1027 22:05:19.681944 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 22:05:19.682453 [0.018961 Inits done]
1029 22:05:19.689492 secure task start!
1030 22:05:19.689992 high task start!
1031 22:05:19.690441 low task start!
1032 22:05:19.690882 run into bl31
1033 22:05:19.696194 NOTICE: BL31: v1.3(release):4fc40b1
1034 22:05:19.703926 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 22:05:19.704509 NOTICE: BL31: G12A normal boot!
1036 22:05:19.729343 NOTICE: BL31: BL33 decompress pass
1037 22:05:19.735039 ERROR: Error initializing runtime service opteed_fast
1038 22:05:20.968013
1039 22:05:20.968659
1040 22:05:20.976304 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 22:05:20.976810
1042 22:05:20.977270 Model: Libre Computer AML-A311D-CC Alta
1043 22:05:21.183814 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 22:05:21.207150 DRAM: 2 GiB (effective 3.8 GiB)
1045 22:05:21.351188 Core: 408 devices, 31 uclasses, devicetree: separate
1046 22:05:21.356063 WDT: Not starting watchdog@f0d0
1047 22:05:21.389309 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 22:05:21.401706 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 22:05:21.405693 ** Bad device specification mmc 0 **
1050 22:05:21.417123 Card did not respond to voltage select! : -110
1051 22:05:21.423726 ** Bad device specification mmc 0 **
1052 22:05:21.424264 Couldn't find partition mmc 0
1053 22:05:21.433020 Card did not respond to voltage select! : -110
1054 22:05:21.438637 ** Bad device specification mmc 0 **
1055 22:05:21.439116 Couldn't find partition mmc 0
1056 22:05:21.442699 Error: could not access storage.
1057 22:05:21.786086 Net: eth0: ethernet@ff3f0000
1058 22:05:21.786677 starting USB...
1059 22:05:22.037919 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 22:05:22.038562 Starting the controller
1061 22:05:22.044782 USB XHCI 1.10
1062 22:05:23.599067 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 22:05:23.607291 scanning usb for storage devices... 0 Storage Device(s) found
1065 22:05:23.658952 Hit any key to stop autoboot: 1
1066 22:05:23.659787 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1067 22:05:23.660440 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1068 22:05:23.660936 Setting prompt string to ['=>']
1069 22:05:23.661444 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1070 22:05:23.674777 0
1071 22:05:23.675686 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 22:05:23.676233 Sending with 10 millisecond of delay
1074 22:05:24.811350 => setenv autoload no
1075 22:05:24.822199 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1076 22:05:24.827641 setenv autoload no
1077 22:05:24.828495 Sending with 10 millisecond of delay
1079 22:05:26.626067 => setenv initrd_high 0xffffffff
1080 22:05:26.636882 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1081 22:05:26.637753 setenv initrd_high 0xffffffff
1082 22:05:26.638503 Sending with 10 millisecond of delay
1084 22:05:28.254912 => setenv fdt_high 0xffffffff
1085 22:05:28.265752 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1086 22:05:28.266664 setenv fdt_high 0xffffffff
1087 22:05:28.267423 Sending with 10 millisecond of delay
1089 22:05:28.559426 => dhcp
1090 22:05:28.570284 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1091 22:05:28.571179 dhcp
1092 22:05:28.571689 Speed: 1000, full duplex
1093 22:05:28.572186 BOOTP broadcast 1
1094 22:05:28.580272 DHCP client bound to address 192.168.6.27 (10 ms)
1095 22:05:28.581035 Sending with 10 millisecond of delay
1097 22:05:30.258272 => setenv serverip 192.168.6.2
1098 22:05:30.269108 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1099 22:05:30.270001 setenv serverip 192.168.6.2
1100 22:05:30.270776 Sending with 10 millisecond of delay
1102 22:05:33.994198 => tftpboot 0x01080000 962944/tftp-deploy-0dmxqmca/kernel/uImage
1103 22:05:34.005062 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1104 22:05:34.005974 tftpboot 0x01080000 962944/tftp-deploy-0dmxqmca/kernel/uImage
1105 22:05:34.006479 Speed: 1000, full duplex
1106 22:05:34.006937 Using ethernet@ff3f0000 device
1107 22:05:34.007747 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1108 22:05:34.013331 Filename '962944/tftp-deploy-0dmxqmca/kernel/uImage'.
1109 22:05:34.017118 Load address: 0x1080000
1110 22:05:36.892493 Loading: *################################################## 43.6 MiB
1111 22:05:36.893140 15.1 MiB/s
1112 22:05:36.893770 done
1113 22:05:36.896946 Bytes transferred = 45713984 (2b98a40 hex)
1114 22:05:36.897788 Sending with 10 millisecond of delay
1116 22:05:41.584390 => tftpboot 0x08000000 962944/tftp-deploy-0dmxqmca/ramdisk/ramdisk.cpio.gz.uboot
1117 22:05:41.595224 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1118 22:05:41.596114 tftpboot 0x08000000 962944/tftp-deploy-0dmxqmca/ramdisk/ramdisk.cpio.gz.uboot
1119 22:05:41.596605 Speed: 1000, full duplex
1120 22:05:41.597062 Using ethernet@ff3f0000 device
1121 22:05:41.597839 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1122 22:05:41.609440 Filename '962944/tftp-deploy-0dmxqmca/ramdisk/ramdisk.cpio.gz.uboot'.
1123 22:05:41.610002 Load address: 0x8000000
1124 22:05:50.638076 Loading: *#######T ########################################## UDP wrong checksum 0000000f 0000e90f
1125 22:05:55.639080 T UDP wrong checksum 0000000f 0000e90f
1126 22:06:05.641903 T T UDP wrong checksum 0000000f 0000e90f
1127 22:06:25.645139 T T T UDP wrong checksum 0000000f 0000e90f
1128 22:06:30.763058 T T UDP wrong checksum 000000ff 00003a1a
1129 22:06:30.808207 UDP wrong checksum 000000ff 0000ca0c
1130 22:06:40.651082 T
1131 22:06:40.651471 Retry count exceeded; starting again
1133 22:06:40.652378 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
1136 22:06:40.653300 end: 2.4 uboot-commands (duration 00:01:54) [common]
1138 22:06:40.653988 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1140 22:06:40.654518 end: 2 uboot-action (duration 00:01:54) [common]
1142 22:06:40.655454 Cleaning after the job
1143 22:06:40.655813 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962944/tftp-deploy-0dmxqmca/ramdisk
1144 22:06:40.656781 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962944/tftp-deploy-0dmxqmca/kernel
1145 22:06:40.672745 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962944/tftp-deploy-0dmxqmca/dtb
1146 22:06:40.673553 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962944/tftp-deploy-0dmxqmca/modules
1147 22:06:40.678936 start: 4.1 power-off (timeout 00:00:30) [common]
1148 22:06:40.679538 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1149 22:06:40.712239 >> OK - accepted request
1150 22:06:40.714011 Returned 0 in 0 seconds
1151 22:06:40.814841 end: 4.1 power-off (duration 00:00:00) [common]
1153 22:06:40.816507 start: 4.2 read-feedback (timeout 00:10:00) [common]
1154 22:06:40.817603 Listened to connection for namespace 'common' for up to 1s
1155 22:06:41.818353 Finalising connection for namespace 'common'
1156 22:06:41.818865 Disconnecting from shell: Finalise
1157 22:06:41.819148 =>
1158 22:06:41.919871 end: 4.2 read-feedback (duration 00:00:01) [common]
1159 22:06:41.920376 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/962944
1160 22:06:42.517774 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/962944
1161 22:06:42.518383 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.