Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 22:00:05.923810 lava-dispatcher, installed at version: 2024.01
2 22:00:05.924645 start: 0 validate
3 22:00:05.925116 Start time: 2024-11-08 22:00:05.925086+00:00 (UTC)
4 22:00:05.925661 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 22:00:05.926217 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 22:00:05.972419 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 22:00:05.972957 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-regmap%2Ffor-next%2Fv6.12-rc3-8-gd1f4390dd28b%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 22:00:06.007599 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 22:00:06.008231 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-regmap%2Ffor-next%2Fv6.12-rc3-8-gd1f4390dd28b%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 22:00:06.046466 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 22:00:06.046956 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:00:06.092933 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 22:00:06.093422 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-regmap%2Ffor-next%2Fv6.12-rc3-8-gd1f4390dd28b%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 22:00:06.139363 validate duration: 0.21
16 22:00:06.141042 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:00:06.141703 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:00:06.142356 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:00:06.143394 Not decompressing ramdisk as can be used compressed.
20 22:00:06.144286 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 22:00:06.144856 saving as /var/lib/lava/dispatcher/tmp/962938/tftp-deploy-dzigv6gk/ramdisk/initrd.cpio.gz
22 22:00:06.145404 total size: 5628140 (5 MB)
23 22:00:06.190893 progress 0 % (0 MB)
24 22:00:06.198855 progress 5 % (0 MB)
25 22:00:06.207272 progress 10 % (0 MB)
26 22:00:06.214762 progress 15 % (0 MB)
27 22:00:06.223146 progress 20 % (1 MB)
28 22:00:06.227442 progress 25 % (1 MB)
29 22:00:06.231724 progress 30 % (1 MB)
30 22:00:06.236011 progress 35 % (1 MB)
31 22:00:06.239852 progress 40 % (2 MB)
32 22:00:06.244113 progress 45 % (2 MB)
33 22:00:06.247787 progress 50 % (2 MB)
34 22:00:06.252067 progress 55 % (2 MB)
35 22:00:06.256301 progress 60 % (3 MB)
36 22:00:06.260155 progress 65 % (3 MB)
37 22:00:06.264416 progress 70 % (3 MB)
38 22:00:06.268293 progress 75 % (4 MB)
39 22:00:06.272602 progress 80 % (4 MB)
40 22:00:06.276450 progress 85 % (4 MB)
41 22:00:06.280724 progress 90 % (4 MB)
42 22:00:06.284874 progress 95 % (5 MB)
43 22:00:06.288256 progress 100 % (5 MB)
44 22:00:06.288933 5 MB downloaded in 0.14 s (37.40 MB/s)
45 22:00:06.289525 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:00:06.290445 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:00:06.290762 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:00:06.291052 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:00:06.291550 downloading http://storage.kernelci.org/broonie-regmap/for-next/v6.12-rc3-8-gd1f4390dd28b/arm64/defconfig/gcc-12/kernel/Image
51 22:00:06.291808 saving as /var/lib/lava/dispatcher/tmp/962938/tftp-deploy-dzigv6gk/kernel/Image
52 22:00:06.292078 total size: 45713920 (43 MB)
53 22:00:06.292312 No compression specified
54 22:00:06.331005 progress 0 % (0 MB)
55 22:00:06.360511 progress 5 % (2 MB)
56 22:00:06.390596 progress 10 % (4 MB)
57 22:00:06.419862 progress 15 % (6 MB)
58 22:00:06.448299 progress 20 % (8 MB)
59 22:00:06.476018 progress 25 % (10 MB)
60 22:00:06.505237 progress 30 % (13 MB)
61 22:00:06.533578 progress 35 % (15 MB)
62 22:00:06.562647 progress 40 % (17 MB)
63 22:00:06.590677 progress 45 % (19 MB)
64 22:00:06.618941 progress 50 % (21 MB)
65 22:00:06.647049 progress 55 % (24 MB)
66 22:00:06.675409 progress 60 % (26 MB)
67 22:00:06.702906 progress 65 % (28 MB)
68 22:00:06.730725 progress 70 % (30 MB)
69 22:00:06.759161 progress 75 % (32 MB)
70 22:00:06.787202 progress 80 % (34 MB)
71 22:00:06.814861 progress 85 % (37 MB)
72 22:00:06.843196 progress 90 % (39 MB)
73 22:00:06.871572 progress 95 % (41 MB)
74 22:00:06.899012 progress 100 % (43 MB)
75 22:00:06.899550 43 MB downloaded in 0.61 s (71.77 MB/s)
76 22:00:06.900045 end: 1.2.1 http-download (duration 00:00:01) [common]
78 22:00:06.900870 end: 1.2 download-retry (duration 00:00:01) [common]
79 22:00:06.901142 start: 1.3 download-retry (timeout 00:09:59) [common]
80 22:00:06.901406 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 22:00:06.901878 downloading http://storage.kernelci.org/broonie-regmap/for-next/v6.12-rc3-8-gd1f4390dd28b/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 22:00:06.902147 saving as /var/lib/lava/dispatcher/tmp/962938/tftp-deploy-dzigv6gk/dtb/meson-g12b-a311d-libretech-cc.dtb
83 22:00:06.902354 total size: 54703 (0 MB)
84 22:00:06.902563 No compression specified
85 22:00:06.942917 progress 59 % (0 MB)
86 22:00:06.943778 progress 100 % (0 MB)
87 22:00:06.944359 0 MB downloaded in 0.04 s (1.24 MB/s)
88 22:00:06.944831 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:00:06.945641 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:00:06.945903 start: 1.4 download-retry (timeout 00:09:59) [common]
92 22:00:06.946167 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 22:00:06.946622 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 22:00:06.946860 saving as /var/lib/lava/dispatcher/tmp/962938/tftp-deploy-dzigv6gk/nfsrootfs/full.rootfs.tar
95 22:00:06.947064 total size: 474398908 (452 MB)
96 22:00:06.947272 Using unxz to decompress xz
97 22:00:06.979816 progress 0 % (0 MB)
98 22:00:08.103758 progress 5 % (22 MB)
99 22:00:09.562590 progress 10 % (45 MB)
100 22:00:10.011040 progress 15 % (67 MB)
101 22:00:10.815596 progress 20 % (90 MB)
102 22:00:11.361614 progress 25 % (113 MB)
103 22:00:11.714675 progress 30 % (135 MB)
104 22:00:12.329300 progress 35 % (158 MB)
105 22:00:13.223446 progress 40 % (181 MB)
106 22:00:14.087266 progress 45 % (203 MB)
107 22:00:14.755736 progress 50 % (226 MB)
108 22:00:15.432681 progress 55 % (248 MB)
109 22:00:16.655159 progress 60 % (271 MB)
110 22:00:18.079164 progress 65 % (294 MB)
111 22:00:19.669851 progress 70 % (316 MB)
112 22:00:23.024706 progress 75 % (339 MB)
113 22:00:25.926442 progress 80 % (361 MB)
114 22:00:28.881286 progress 85 % (384 MB)
115 22:00:32.081574 progress 90 % (407 MB)
116 22:00:35.311045 progress 95 % (429 MB)
117 22:00:38.596893 progress 100 % (452 MB)
118 22:00:38.611117 452 MB downloaded in 31.66 s (14.29 MB/s)
119 22:00:38.611721 end: 1.4.1 http-download (duration 00:00:32) [common]
121 22:00:38.612607 end: 1.4 download-retry (duration 00:00:32) [common]
122 22:00:38.612882 start: 1.5 download-retry (timeout 00:09:28) [common]
123 22:00:38.613151 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 22:00:38.613617 downloading http://storage.kernelci.org/broonie-regmap/for-next/v6.12-rc3-8-gd1f4390dd28b/arm64/defconfig/gcc-12/modules.tar.xz
125 22:00:38.613879 saving as /var/lib/lava/dispatcher/tmp/962938/tftp-deploy-dzigv6gk/modules/modules.tar
126 22:00:38.614100 total size: 11607860 (11 MB)
127 22:00:38.614318 Using unxz to decompress xz
128 22:00:38.657233 progress 0 % (0 MB)
129 22:00:38.725906 progress 5 % (0 MB)
130 22:00:38.801819 progress 10 % (1 MB)
131 22:00:38.902574 progress 15 % (1 MB)
132 22:00:38.996407 progress 20 % (2 MB)
133 22:00:39.077355 progress 25 % (2 MB)
134 22:00:39.157189 progress 30 % (3 MB)
135 22:00:39.238688 progress 35 % (3 MB)
136 22:00:39.317685 progress 40 % (4 MB)
137 22:00:39.395824 progress 45 % (5 MB)
138 22:00:39.481673 progress 50 % (5 MB)
139 22:00:39.561560 progress 55 % (6 MB)
140 22:00:39.648675 progress 60 % (6 MB)
141 22:00:39.730436 progress 65 % (7 MB)
142 22:00:39.808818 progress 70 % (7 MB)
143 22:00:39.891176 progress 75 % (8 MB)
144 22:00:39.976382 progress 80 % (8 MB)
145 22:00:40.058026 progress 85 % (9 MB)
146 22:00:40.138454 progress 90 % (9 MB)
147 22:00:40.217935 progress 95 % (10 MB)
148 22:00:40.297071 progress 100 % (11 MB)
149 22:00:40.309565 11 MB downloaded in 1.70 s (6.53 MB/s)
150 22:00:40.310163 end: 1.5.1 http-download (duration 00:00:02) [common]
152 22:00:40.310988 end: 1.5 download-retry (duration 00:00:02) [common]
153 22:00:40.311255 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
154 22:00:40.311520 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
155 22:00:56.233767 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/962938/extract-nfsrootfs-tkve1jhq
156 22:00:56.234342 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 22:00:56.234627 start: 1.6.2 lava-overlay (timeout 00:09:10) [common]
158 22:00:56.235313 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza
159 22:00:56.235752 makedir: /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin
160 22:00:56.236107 makedir: /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/tests
161 22:00:56.236431 makedir: /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/results
162 22:00:56.236762 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-add-keys
163 22:00:56.237281 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-add-sources
164 22:00:56.237777 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-background-process-start
165 22:00:56.238264 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-background-process-stop
166 22:00:56.238771 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-common-functions
167 22:00:56.239251 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-echo-ipv4
168 22:00:56.239718 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-install-packages
169 22:00:56.240249 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-installed-packages
170 22:00:56.240755 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-os-build
171 22:00:56.241230 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-probe-channel
172 22:00:56.241703 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-probe-ip
173 22:00:56.242175 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-target-ip
174 22:00:56.242639 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-target-mac
175 22:00:56.243107 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-target-storage
176 22:00:56.243580 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-test-case
177 22:00:56.244092 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-test-event
178 22:00:56.244598 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-test-feedback
179 22:00:56.245072 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-test-raise
180 22:00:56.245536 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-test-reference
181 22:00:56.246006 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-test-runner
182 22:00:56.246554 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-test-set
183 22:00:56.247033 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-test-shell
184 22:00:56.247507 Updating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-install-packages (oe)
185 22:00:56.248066 Updating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/bin/lava-installed-packages (oe)
186 22:00:56.248508 Creating /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/environment
187 22:00:56.248869 LAVA metadata
188 22:00:56.249127 - LAVA_JOB_ID=962938
189 22:00:56.249340 - LAVA_DISPATCHER_IP=192.168.6.2
190 22:00:56.249693 start: 1.6.2.1 ssh-authorize (timeout 00:09:10) [common]
191 22:00:56.250662 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 22:00:56.250978 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:10) [common]
193 22:00:56.251186 skipped lava-vland-overlay
194 22:00:56.251429 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 22:00:56.251684 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:10) [common]
196 22:00:56.251902 skipped lava-multinode-overlay
197 22:00:56.252171 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 22:00:56.252425 start: 1.6.2.4 test-definition (timeout 00:09:10) [common]
199 22:00:56.252672 Loading test definitions
200 22:00:56.252946 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:10) [common]
201 22:00:56.253164 Using /lava-962938 at stage 0
202 22:00:56.254285 uuid=962938_1.6.2.4.1 testdef=None
203 22:00:56.254582 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 22:00:56.254840 start: 1.6.2.4.2 test-overlay (timeout 00:09:10) [common]
205 22:00:56.256537 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 22:00:56.257317 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:10) [common]
208 22:00:56.259478 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 22:00:56.260328 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:10) [common]
211 22:00:56.262346 runner path: /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/0/tests/0_v4l2-decoder-conformance-h265 test_uuid 962938_1.6.2.4.1
212 22:00:56.262902 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 22:00:56.263654 Creating lava-test-runner.conf files
215 22:00:56.263853 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/962938/lava-overlay-_fv69hza/lava-962938/0 for stage 0
216 22:00:56.264240 - 0_v4l2-decoder-conformance-h265
217 22:00:56.264583 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 22:00:56.264853 start: 1.6.2.5 compress-overlay (timeout 00:09:10) [common]
219 22:00:56.286047 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 22:00:56.286411 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:10) [common]
221 22:00:56.286665 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 22:00:56.286929 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 22:00:56.287188 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:10) [common]
224 22:00:56.908909 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 22:00:56.909373 start: 1.6.4 extract-modules (timeout 00:09:09) [common]
226 22:00:56.909622 extracting modules file /var/lib/lava/dispatcher/tmp/962938/tftp-deploy-dzigv6gk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/962938/extract-nfsrootfs-tkve1jhq
227 22:00:58.285219 extracting modules file /var/lib/lava/dispatcher/tmp/962938/tftp-deploy-dzigv6gk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/962938/extract-overlay-ramdisk-jjnrxn27/ramdisk
228 22:00:59.689058 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 22:00:59.689516 start: 1.6.5 apply-overlay-tftp (timeout 00:09:06) [common]
230 22:00:59.689790 [common] Applying overlay to NFS
231 22:00:59.690002 [common] Applying overlay /var/lib/lava/dispatcher/tmp/962938/compress-overlay-abg6s5l7/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/962938/extract-nfsrootfs-tkve1jhq
232 22:00:59.719316 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 22:00:59.719721 start: 1.6.6 prepare-kernel (timeout 00:09:06) [common]
234 22:00:59.720012 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:06) [common]
235 22:00:59.720254 Converting downloaded kernel to a uImage
236 22:00:59.720561 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/962938/tftp-deploy-dzigv6gk/kernel/Image /var/lib/lava/dispatcher/tmp/962938/tftp-deploy-dzigv6gk/kernel/uImage
237 22:01:00.249851 output: Image Name:
238 22:01:00.250261 output: Created: Fri Nov 8 22:00:59 2024
239 22:01:00.250475 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 22:01:00.250680 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 22:01:00.250882 output: Load Address: 01080000
242 22:01:00.251084 output: Entry Point: 01080000
243 22:01:00.251281 output:
244 22:01:00.251617 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 22:01:00.251884 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 22:01:00.252212 start: 1.6.7 configure-preseed-file (timeout 00:09:06) [common]
247 22:01:00.252469 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 22:01:00.252727 start: 1.6.8 compress-ramdisk (timeout 00:09:06) [common]
249 22:01:00.252980 Building ramdisk /var/lib/lava/dispatcher/tmp/962938/extract-overlay-ramdisk-jjnrxn27/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/962938/extract-overlay-ramdisk-jjnrxn27/ramdisk
250 22:01:02.437965 >> 166779 blocks
251 22:01:10.293888 Adding RAMdisk u-boot header.
252 22:01:10.294299 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/962938/extract-overlay-ramdisk-jjnrxn27/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/962938/extract-overlay-ramdisk-jjnrxn27/ramdisk.cpio.gz.uboot
253 22:01:11.481372 output: Image Name:
254 22:01:11.482215 output: Created: Fri Nov 8 22:01:10 2024
255 22:01:11.482846 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 22:01:11.483435 output: Data Size: 23426233 Bytes = 22877.18 KiB = 22.34 MiB
257 22:01:11.484071 output: Load Address: 00000000
258 22:01:11.484660 output: Entry Point: 00000000
259 22:01:11.485293 output:
260 22:01:11.487122 rename /var/lib/lava/dispatcher/tmp/962938/extract-overlay-ramdisk-jjnrxn27/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/962938/tftp-deploy-dzigv6gk/ramdisk/ramdisk.cpio.gz.uboot
261 22:01:11.488180 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
262 22:01:11.489008 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
263 22:01:11.489845 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:55) [common]
264 22:01:11.490525 No LXC device requested
265 22:01:11.491325 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 22:01:11.492087 start: 1.8 deploy-device-env (timeout 00:08:55) [common]
267 22:01:11.492885 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 22:01:11.493522 Checking files for TFTP limit of 4294967296 bytes.
269 22:01:11.497492 end: 1 tftp-deploy (duration 00:01:05) [common]
270 22:01:11.498352 start: 2 uboot-action (timeout 00:05:00) [common]
271 22:01:11.499182 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 22:01:11.499916 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 22:01:11.500762 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 22:01:11.501496 Using kernel file from prepare-kernel: 962938/tftp-deploy-dzigv6gk/kernel/uImage
275 22:01:11.502420 substitutions:
276 22:01:11.503048 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 22:01:11.503661 - {DTB_ADDR}: 0x01070000
278 22:01:11.504340 - {DTB}: 962938/tftp-deploy-dzigv6gk/dtb/meson-g12b-a311d-libretech-cc.dtb
279 22:01:11.504977 - {INITRD}: 962938/tftp-deploy-dzigv6gk/ramdisk/ramdisk.cpio.gz.uboot
280 22:01:11.505546 - {KERNEL_ADDR}: 0x01080000
281 22:01:11.506173 - {KERNEL}: 962938/tftp-deploy-dzigv6gk/kernel/uImage
282 22:01:11.506757 - {LAVA_MAC}: None
283 22:01:11.507385 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/962938/extract-nfsrootfs-tkve1jhq
284 22:01:11.508043 - {NFS_SERVER_IP}: 192.168.6.2
285 22:01:11.508682 - {PRESEED_CONFIG}: None
286 22:01:11.509301 - {PRESEED_LOCAL}: None
287 22:01:11.509881 - {RAMDISK_ADDR}: 0x08000000
288 22:01:11.510438 - {RAMDISK}: 962938/tftp-deploy-dzigv6gk/ramdisk/ramdisk.cpio.gz.uboot
289 22:01:11.511062 - {ROOT_PART}: None
290 22:01:11.511674 - {ROOT}: None
291 22:01:11.512277 - {SERVER_IP}: 192.168.6.2
292 22:01:11.512869 - {TEE_ADDR}: 0x83000000
293 22:01:11.513446 - {TEE}: None
294 22:01:11.514052 Parsed boot commands:
295 22:01:11.514609 - setenv autoload no
296 22:01:11.515225 - setenv initrd_high 0xffffffff
297 22:01:11.515845 - setenv fdt_high 0xffffffff
298 22:01:11.516485 - dhcp
299 22:01:11.517050 - setenv serverip 192.168.6.2
300 22:01:11.517671 - tftpboot 0x01080000 962938/tftp-deploy-dzigv6gk/kernel/uImage
301 22:01:11.518242 - tftpboot 0x08000000 962938/tftp-deploy-dzigv6gk/ramdisk/ramdisk.cpio.gz.uboot
302 22:01:11.518758 - tftpboot 0x01070000 962938/tftp-deploy-dzigv6gk/dtb/meson-g12b-a311d-libretech-cc.dtb
303 22:01:11.519385 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/962938/extract-nfsrootfs-tkve1jhq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 22:01:11.519955 - bootm 0x01080000 0x08000000 0x01070000
305 22:01:11.520878 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 22:01:11.522275 start: 2.3 connect-device (timeout 00:05:00) [common]
308 22:01:11.522621 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 22:01:11.535748 Setting prompt string to ['lava-test: # ']
310 22:01:11.536955 end: 2.3 connect-device (duration 00:00:00) [common]
311 22:01:11.537503 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 22:01:11.537933 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 22:01:11.538396 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 22:01:11.539230 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 22:01:11.574412 >> OK - accepted request
316 22:01:11.576795 Returned 0 in 0 seconds
317 22:01:11.678437 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 22:01:11.680813 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 22:01:11.681661 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 22:01:11.682419 Setting prompt string to ['Hit any key to stop autoboot']
322 22:01:11.683125 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 22:01:11.685356 Trying 192.168.56.21...
324 22:01:11.686070 Connected to conserv1.
325 22:01:11.686685 Escape character is '^]'.
326 22:01:11.687293
327 22:01:11.687953 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 22:01:11.688593
329 22:01:22.776895 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
330 22:01:22.777484 bl2_stage_init 0x81
331 22:01:22.782709 hw id: 0x0000 - pwm id 0x01
332 22:01:22.783271 bl2_stage_init 0xc1
333 22:01:22.783731 bl2_stage_init 0x02
334 22:01:22.784232
335 22:01:22.788089 L0:00000000
336 22:01:22.788586 L1:20000703
337 22:01:22.789021 L2:00008067
338 22:01:22.789450 L3:14000000
339 22:01:22.789872 B2:00402000
340 22:01:22.793740 B1:e0f83180
341 22:01:22.794221
342 22:01:22.794659 TE: 58150
343 22:01:22.795088
344 22:01:22.799182 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
345 22:01:22.799705
346 22:01:22.800182 Board ID = 1
347 22:01:22.804716 Set A53 clk to 24M
348 22:01:22.805185 Set A73 clk to 24M
349 22:01:22.805614 Set clk81 to 24M
350 22:01:22.810239 A53 clk: 1200 MHz
351 22:01:22.810709 A73 clk: 1200 MHz
352 22:01:22.811133 CLK81: 166.6M
353 22:01:22.811554 smccc: 00012aac
354 22:01:22.815822 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
355 22:01:22.821559 board id: 1
356 22:01:22.827345 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
357 22:01:22.837828 fw parse done
358 22:01:22.843860 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
359 22:01:22.886502 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
360 22:01:22.897362 PIEI prepare done
361 22:01:22.897830 fastboot data load
362 22:01:22.898263 fastboot data verify
363 22:01:22.903090 verify result: 266
364 22:01:22.908656 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
365 22:01:22.909162 LPDDR4 probe
366 22:01:22.909595 ddr clk to 1584MHz
367 22:01:22.916761 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
368 22:01:22.953927
369 22:01:22.954429 dmc_version 0001
370 22:01:22.960576 Check phy result
371 22:01:22.966497 INFO : End of CA training
372 22:01:22.966992 INFO : End of initialization
373 22:01:22.972101 INFO : Training has run successfully!
374 22:01:22.972606 Check phy result
375 22:01:22.977647 INFO : End of initialization
376 22:01:22.978148 INFO : End of read enable training
377 22:01:22.983213 INFO : End of fine write leveling
378 22:01:22.988782 INFO : End of Write leveling coarse delay
379 22:01:22.989293 INFO : Training has run successfully!
380 22:01:22.989728 Check phy result
381 22:01:22.994453 INFO : End of initialization
382 22:01:22.994952 INFO : End of read dq deskew training
383 22:01:23.000094 INFO : End of MPR read delay center optimization
384 22:01:23.005699 INFO : End of write delay center optimization
385 22:01:23.011181 INFO : End of read delay center optimization
386 22:01:23.011692 INFO : End of max read latency training
387 22:01:23.016830 INFO : Training has run successfully!
388 22:01:23.017333 1D training succeed
389 22:01:23.026148 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 22:01:23.073717 Check phy result
391 22:01:23.074306 INFO : End of initialization
392 22:01:23.095368 INFO : End of 2D read delay Voltage center optimization
393 22:01:23.115641 INFO : End of 2D read delay Voltage center optimization
394 22:01:23.167696 INFO : End of 2D write delay Voltage center optimization
395 22:01:23.217167 INFO : End of 2D write delay Voltage center optimization
396 22:01:23.222666 INFO : Training has run successfully!
397 22:01:23.223326
398 22:01:23.223789 channel==0
399 22:01:23.228709 RxClkDly_Margin_A0==88 ps 9
400 22:01:23.229303 TxDqDly_Margin_A0==98 ps 10
401 22:01:23.233849 RxClkDly_Margin_A1==88 ps 9
402 22:01:23.234402 TxDqDly_Margin_A1==98 ps 10
403 22:01:23.234843 TrainedVREFDQ_A0==74
404 22:01:23.239554 TrainedVREFDQ_A1==74
405 22:01:23.240145 VrefDac_Margin_A0==25
406 22:01:23.240590 DeviceVref_Margin_A0==40
407 22:01:23.245094 VrefDac_Margin_A1==25
408 22:01:23.245646 DeviceVref_Margin_A1==40
409 22:01:23.246080
410 22:01:23.246513
411 22:01:23.251086 channel==1
412 22:01:23.251640 RxClkDly_Margin_A0==98 ps 10
413 22:01:23.253148 TxDqDly_Margin_A0==98 ps 10
414 22:01:23.256228 RxClkDly_Margin_A1==98 ps 10
415 22:01:23.256791 TxDqDly_Margin_A1==88 ps 9
416 22:01:23.261765 TrainedVREFDQ_A0==77
417 22:01:23.262315 TrainedVREFDQ_A1==77
418 22:01:23.262753 VrefDac_Margin_A0==22
419 22:01:23.267516 DeviceVref_Margin_A0==37
420 22:01:23.268089 VrefDac_Margin_A1==24
421 22:01:23.273127 DeviceVref_Margin_A1==37
422 22:01:23.274500
423 22:01:23.274945 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
424 22:01:23.278804
425 22:01:23.306601 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
426 22:01:23.307299 2D training succeed
427 22:01:23.312298 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
428 22:01:23.317746 auto size-- 65535DDR cs0 size: 2048MB
429 22:01:23.318325 DDR cs1 size: 2048MB
430 22:01:23.323367 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
431 22:01:23.323910 cs0 DataBus test pass
432 22:01:23.328996 cs1 DataBus test pass
433 22:01:23.329548 cs0 AddrBus test pass
434 22:01:23.329983 cs1 AddrBus test pass
435 22:01:23.330413
436 22:01:23.334559 100bdlr_step_size ps== 420
437 22:01:23.335122 result report
438 22:01:23.340172 boot times 0Enable ddr reg access
439 22:01:23.345595 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
440 22:01:23.359046 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
441 22:01:23.932761 0.0;M3 CHK:0;cm4_sp_mode 0
442 22:01:23.933413 MVN_1=0x00000000
443 22:01:23.938154 MVN_2=0x00000000
444 22:01:23.943900 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
445 22:01:23.944445 OPS=0x10
446 22:01:23.944891 ring efuse init
447 22:01:23.945324 chipver efuse init
448 22:01:23.952213 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
449 22:01:23.952715 [0.018960 Inits done]
450 22:01:23.953148 secure task start!
451 22:01:23.959706 high task start!
452 22:01:23.960222 low task start!
453 22:01:23.960656 run into bl31
454 22:01:23.966365 NOTICE: BL31: v1.3(release):4fc40b1
455 22:01:23.974113 NOTICE: BL31: Built : 15:58:17, May 22 2019
456 22:01:23.974604 NOTICE: BL31: G12A normal boot!
457 22:01:23.999681 NOTICE: BL31: BL33 decompress pass
458 22:01:24.005245 ERROR: Error initializing runtime service opteed_fast
459 22:01:25.238155
460 22:01:25.238827
461 22:01:25.246455 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
462 22:01:25.246973
463 22:01:25.247417 Model: Libre Computer AML-A311D-CC Alta
464 22:01:25.455070 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
465 22:01:25.478264 DRAM: 2 GiB (effective 3.8 GiB)
466 22:01:25.621299 Core: 408 devices, 31 uclasses, devicetree: separate
467 22:01:25.627080 WDT: Not starting watchdog@f0d0
468 22:01:26.886885 MMC: G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
469 22:01:26.887524 bl2_stage_init 0x01
470 22:01:26.888033 bl2_stage_init 0x81
471 22:01:26.892469 hw id: 0x0000 - pwm id 0x01
472 22:01:26.892954 bl2_stage_init 0xc1
473 22:01:26.893392 bl2_stage_init 0x02
474 22:01:26.893823
475 22:01:26.898064 L0:00000000
476 22:01:26.898537 L1:20000703
477 22:01:26.898970 L2:00008067
478 22:01:26.899399 L3:14000000
479 22:01:26.901042 B2:00402000
480 22:01:26.901511 B1:e0f83180
481 22:01:26.901945
482 22:01:26.902371 TE: 58124
483 22:01:26.902803
484 22:01:26.912232 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
485 22:01:26.912708
486 22:01:26.913142 Board ID = 1
487 22:01:26.913569 Set A53 clk to 24M
488 22:01:26.913992 Set A73 clk to 24M
489 22:01:26.917894 Set clk81 to 24M
490 22:01:26.918367 A53 clk: 1200 MHz
491 22:01:26.918800 A73 clk: 1200 MHz
492 22:01:26.923463 CLK81: 166.6M
493 22:01:26.923926 smccc: 00012a92
494 22:01:26.929025 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
495 22:01:26.929496 board id: 1
496 22:01:26.937538 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
497 22:01:26.948222 fw parse done
498 22:01:26.954165 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
499 22:01:26.996851 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
500 22:01:27.007733 PIEI prepare done
501 22:01:27.008298 fastboot data load
502 22:01:27.008738 fastboot data verify
503 22:01:27.013430 verify result: 266
504 22:01:27.019003 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
505 22:01:27.019503 LPDDR4 probe
506 22:01:27.019948 ddr clk to 1584MHz
507 22:01:27.027111 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
508 22:01:27.064322
509 22:01:27.064878 dmc_version 0001
510 22:01:27.070980 Check phy result
511 22:01:27.076808 INFO : End of CA training
512 22:01:27.077308 INFO : End of initialization
513 22:01:27.082408 INFO : Training has run successfully!
514 22:01:27.082903 Check phy result
515 22:01:27.088058 INFO : End of initialization
516 22:01:27.088553 INFO : End of read enable training
517 22:01:27.093585 INFO : End of fine write leveling
518 22:01:27.099188 INFO : End of Write leveling coarse delay
519 22:01:27.099675 INFO : Training has run successfully!
520 22:01:27.100147 Check phy result
521 22:01:27.104784 INFO : End of initialization
522 22:01:27.105265 INFO : End of read dq deskew training
523 22:01:27.110364 INFO : End of MPR read delay center optimization
524 22:01:27.115975 INFO : End of write delay center optimization
525 22:01:27.121618 INFO : End of read delay center optimization
526 22:01:27.122104 INFO : End of max read latency training
527 22:01:27.127195 INFO : Training has run successfully!
528 22:01:27.127680 1D training succeed
529 22:01:27.136345 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
530 22:01:27.184035 Check phy result
531 22:01:27.184532 INFO : End of initialization
532 22:01:27.206523 INFO : End of 2D read delay Voltage center optimization
533 22:01:27.226822 INFO : End of 2D read delay Voltage center optimization
534 22:01:27.279275 INFO : End of 2D write delay Voltage center optimization
535 22:01:27.329213 INFO : End of 2D write delay Voltage center optimization
536 22:01:27.333889 INFO : Training has run successfully!
537 22:01:27.334494
538 22:01:27.334951 channel==0
539 22:01:27.339411 RxClkDly_Margin_A0==88 ps 9
540 22:01:27.339965 TxDqDly_Margin_A0==98 ps 10
541 22:01:27.344998 RxClkDly_Margin_A1==88 ps 9
542 22:01:27.345537 TxDqDly_Margin_A1==98 ps 10
543 22:01:27.345984 TrainedVREFDQ_A0==74
544 22:01:27.350607 TrainedVREFDQ_A1==74
545 22:01:27.351154 VrefDac_Margin_A0==25
546 22:01:27.351596 DeviceVref_Margin_A0==40
547 22:01:27.356306 VrefDac_Margin_A1==24
548 22:01:27.356852 DeviceVref_Margin_A1==40
549 22:01:27.357292
550 22:01:27.357723
551 22:01:27.361798 channel==1
552 22:01:27.362336 RxClkDly_Margin_A0==98 ps 10
553 22:01:27.362782 TxDqDly_Margin_A0==98 ps 10
554 22:01:27.367438 RxClkDly_Margin_A1==88 ps 9
555 22:01:27.367911 TxDqDly_Margin_A1==88 ps 9
556 22:01:27.373009 TrainedVREFDQ_A0==77
557 22:01:27.373588 TrainedVREFDQ_A1==77
558 22:01:27.374052 VrefDac_Margin_A0==22
559 22:01:27.378813 DeviceVref_Margin_A0==37
560 22:01:27.379454 VrefDac_Margin_A1==24
561 22:01:27.384358 DeviceVref_Margin_A1==37
562 22:01:27.384988
563 22:01:27.385453 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
564 22:01:27.385921
565 22:01:27.417808 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
566 22:01:27.418249 2D training succeed
567 22:01:27.423360 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
568 22:01:27.429123 auto size-- 65535DDR cs0 size: 2048MB
569 22:01:27.429516 DDR cs1 size: 2048MB
570 22:01:27.434975 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
571 22:01:27.435400 cs0 DataBus test pass
572 22:01:27.440231 cs1 DataBus test pass
573 22:01:27.440590 cs0 AddrBus test pass
574 22:01:27.440808 cs1 AddrBus test pass
575 22:01:27.441115
576 22:01:27.445743 100bdlr_step_size ps== 420
577 22:01:27.446336 result report
578 22:01:27.451391 boot times 0Enable ddr reg access
579 22:01:27.456688 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
580 22:01:27.470149 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
581 22:01:28.043220 0.0;M3 CHK:0;cm4_sp_mode 0
582 22:01:28.043868 MVN_1=0x00000000
583 22:01:28.048655 MVN_2=0x00000000
584 22:01:28.054441 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
585 22:01:28.054932 OPS=0x10
586 22:01:28.055367 ring efuse init
587 22:01:28.055793 chipver efuse init
588 22:01:28.059954 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
589 22:01:28.065572 [0.018960 Inits done]
590 22:01:28.066037 secure task start!
591 22:01:28.066469 high task start!
592 22:01:28.070224 low task start!
593 22:01:28.070682 run into bl31
594 22:01:28.076779 NOTICE: BL31: v1.3(release):4fc40b1
595 22:01:28.084635 NOTICE: BL31: Built : 15:58:17, May 22 2019
596 22:01:28.085104 NOTICE: BL31: G12A normal boot!
597 22:01:28.109983 NOTICE: BL31: BL33 decompress pass
598 22:01:28.115697 ERROR: Error initializing runtime service opteed_fast
599 22:01:29.348688
600 22:01:29.349330
601 22:01:29.357132 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
602 22:01:29.357625
603 22:01:29.358079 Model: Libre Computer AML-A311D-CC Alta
604 22:01:29.565681 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
605 22:01:29.588877 DRAM: 2 GiB (effective 3.8 GiB)
606 22:01:29.732087 Core: 408 devices, 31 uclasses, devicetree: separate
607 22:01:29.737060 WDT: Not starting watchdog@f0d0
608 22:01:29.770083 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
609 22:01:29.782540 Loading Environment from FAT... Card did not respond to voltage select! : -110
610 22:01:29.787555 ** Bad device specification mmc 0 **
611 22:01:29.798009 Card did not respond to voltage select! : -110
612 22:01:29.805509 ** Bad device specification mmc 0 **
613 22:01:29.805987 Couldn't find partition mmc 0
614 22:01:29.813685 Card did not respond to voltage select! : -110
615 22:01:29.819281 ** Bad device specification mmc 0 **
616 22:01:29.819751 Couldn't find partition mmc 0
617 22:01:29.823458 Error: could not access storage.
618 22:01:30.166963 Net: eth0: ethernet@ff3f0000
619 22:01:30.167559 starting USB...
620 22:01:30.418878 Bus usb@ff500000: Register 3000140 NbrPorts 3
621 22:01:30.419513 Starting the controller
622 22:01:30.425773 USB XHCI 1.10
623 22:01:32.137126 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
624 22:01:32.137740 bl2_stage_init 0x01
625 22:01:32.138196 bl2_stage_init 0x81
626 22:01:32.142728 hw id: 0x0000 - pwm id 0x01
627 22:01:32.143205 bl2_stage_init 0xc1
628 22:01:32.143649 bl2_stage_init 0x02
629 22:01:32.144143
630 22:01:32.148328 L0:00000000
631 22:01:32.148795 L1:20000703
632 22:01:32.149237 L2:00008067
633 22:01:32.149670 L3:14000000
634 22:01:32.153896 B2:00402000
635 22:01:32.154367 B1:e0f83180
636 22:01:32.154809
637 22:01:32.155251 TE: 58124
638 22:01:32.155691
639 22:01:32.159533 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
640 22:01:32.160037
641 22:01:32.160485 Board ID = 1
642 22:01:32.165038 Set A53 clk to 24M
643 22:01:32.165506 Set A73 clk to 24M
644 22:01:32.165945 Set clk81 to 24M
645 22:01:32.170659 A53 clk: 1200 MHz
646 22:01:32.171119 A73 clk: 1200 MHz
647 22:01:32.171554 CLK81: 166.6M
648 22:01:32.172020 smccc: 00012a91
649 22:01:32.176328 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
650 22:01:32.181816 board id: 1
651 22:01:32.187688 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
652 22:01:32.198452 fw parse done
653 22:01:32.204309 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
654 22:01:32.246871 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
655 22:01:32.257834 PIEI prepare done
656 22:01:32.258301 fastboot data load
657 22:01:32.258745 fastboot data verify
658 22:01:32.263415 verify result: 266
659 22:01:32.269051 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
660 22:01:32.269519 LPDDR4 probe
661 22:01:32.269960 ddr clk to 1584MHz
662 22:01:32.277094 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
663 22:01:32.314291
664 22:01:32.314771 dmc_version 0001
665 22:01:32.320047 Check phy result
666 22:01:32.326928 INFO : End of CA training
667 22:01:32.327394 INFO : End of initialization
668 22:01:32.332556 INFO : Training has run successfully!
669 22:01:32.333016 Check phy result
670 22:01:32.338002 INFO : End of initialization
671 22:01:32.338466 INFO : End of read enable training
672 22:01:32.343727 INFO : End of fine write leveling
673 22:01:32.349416 INFO : End of Write leveling coarse delay
674 22:01:32.349889 INFO : Training has run successfully!
675 22:01:32.350331 Check phy result
676 22:01:32.354881 INFO : End of initialization
677 22:01:32.355349 INFO : End of read dq deskew training
678 22:01:32.360525 INFO : End of MPR read delay center optimization
679 22:01:32.366047 INFO : End of write delay center optimization
680 22:01:32.371741 INFO : End of read delay center optimization
681 22:01:32.372238 INFO : End of max read latency training
682 22:01:32.377287 INFO : Training has run successfully!
683 22:01:32.377761 1D training succeed
684 22:01:32.386475 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
685 22:01:32.433056 Check phy result
686 22:01:32.433632 INFO : End of initialization
687 22:01:32.455795 INFO : End of 2D read delay Voltage center optimization
688 22:01:32.476076 INFO : End of 2D read delay Voltage center optimization
689 22:01:32.528136 INFO : End of 2D write delay Voltage center optimization
690 22:01:32.577477 INFO : End of 2D write delay Voltage center optimization
691 22:01:32.582903 INFO : Training has run successfully!
692 22:01:32.583375
693 22:01:32.583828 channel==0
694 22:01:32.588513 RxClkDly_Margin_A0==88 ps 9
695 22:01:32.588986 TxDqDly_Margin_A0==98 ps 10
696 22:01:32.591864 RxClkDly_Margin_A1==88 ps 9
697 22:01:32.592364 TxDqDly_Margin_A1==98 ps 10
698 22:01:32.597570 TrainedVREFDQ_A0==74
699 22:01:32.598061 TrainedVREFDQ_A1==74
700 22:01:32.598509 VrefDac_Margin_A0==25
701 22:01:32.603039 DeviceVref_Margin_A0==40
702 22:01:32.603498 VrefDac_Margin_A1==24
703 22:01:32.608671 DeviceVref_Margin_A1==40
704 22:01:32.609136
705 22:01:32.609580
706 22:01:32.610020 channel==1
707 22:01:32.610456 RxClkDly_Margin_A0==98 ps 10
708 22:01:32.614342 TxDqDly_Margin_A0==98 ps 10
709 22:01:32.614813 RxClkDly_Margin_A1==98 ps 10
710 22:01:32.619849 TxDqDly_Margin_A1==88 ps 9
711 22:01:32.620359 TrainedVREFDQ_A0==77
712 22:01:32.620806 TrainedVREFDQ_A1==77
713 22:01:32.625440 VrefDac_Margin_A0==22
714 22:01:32.625910 DeviceVref_Margin_A0==37
715 22:01:32.631080 VrefDac_Margin_A1==22
716 22:01:32.631538 DeviceVref_Margin_A1==37
717 22:01:32.631974
718 22:01:32.636634 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
719 22:01:32.637103
720 22:01:32.664638 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
721 22:01:32.670343 2D training succeed
722 22:01:32.675852 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
723 22:01:32.676359 auto size-- 65535DDR cs0 size: 2048MB
724 22:01:32.681485 DDR cs1 size: 2048MB
725 22:01:32.681952 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
726 22:01:32.687031 cs0 DataBus test pass
727 22:01:32.687493 cs1 DataBus test pass
728 22:01:32.687934 cs0 AddrBus test pass
729 22:01:32.692658 cs1 AddrBus test pass
730 22:01:32.693123
731 22:01:32.693564 100bdlr_step_size ps== 420
732 22:01:32.694010 result report
733 22:01:32.698266 boot times 0Enable ddr reg access
734 22:01:32.705993 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
735 22:01:32.719484 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
736 22:01:33.293189 0.0;M3 CHK:0;cm4_sp_mode 0
737 22:01:33.293890 MVN_1=0x00000000
738 22:01:33.298691 MVN_2=0x00000000
739 22:01:33.304548 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
740 22:01:33.304942 OPS=0x10
741 22:01:33.305160 ring efuse init
742 22:01:33.305393 chipver efuse init
743 22:01:33.310555 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
744 22:01:33.316108 [0.018960 Inits done]
745 22:01:33.316758 secure task start!
746 22:01:33.317204 high task start!
747 22:01:33.320199 low task start!
748 22:01:33.320708 run into bl31
749 22:01:33.326934 NOTICE: BL31: v1.3(release):4fc40b1
750 22:01:33.334163 NOTICE: BL31: Built : 15:58:17, May 22 2019
751 22:01:33.334822 NOTICE: BL31: G12A normal boot!
752 22:01:33.360129 NOTICE: BL31: BL33 decompress pass
753 22:01:33.365823 ERROR: Error initializing runtime service opteed_fast
754 22:01:34.598672
755 22:01:34.599346
756 22:01:34.606687 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
757 22:01:34.607197
758 22:01:34.607656 Model: Libre Computer AML-A311D-CC Alta
759 22:01:34.815380 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
760 22:01:34.838733 DRAM: 2 GiB (effective 3.8 GiB)
761 22:01:34.981776 Core: 408 devices, 31 uclasses, devicetree: separate
762 22:01:34.987576 WDT: Not starting watchdog@f0d0
763 22:01:35.019955 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
764 22:01:35.032390 Loading Environment from FAT... Card did not respond to voltage select! : -110
765 22:01:35.037292 ** Bad device specification mmc 0 **
766 22:01:35.047633 Card did not respond to voltage select! : -110
767 22:01:35.055237 ** Bad device specification mmc 0 **
768 22:01:35.055713 Couldn't find partition mmc 0
769 22:01:35.063644 Card did not respond to voltage select! : -110
770 22:01:35.069072 ** Bad device specification mmc 0 **
771 22:01:35.069551 Couldn't find partition mmc 0
772 22:01:35.074175 Error: could not access storage.
773 22:01:35.416738 Net: eth0: ethernet@ff3f0000
774 22:01:35.417320 starting USB...
775 22:01:35.668538 Bus usb@ff500000: Register 3000140 NbrPorts 3
776 22:01:35.669180 Starting the controller
777 22:01:35.675449 USB XHCI 1.10
778 22:01:37.838696 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
779 22:01:37.839334 bl2_stage_init 0x01
780 22:01:37.839802 bl2_stage_init 0x81
781 22:01:37.844228 hw id: 0x0000 - pwm id 0x01
782 22:01:37.844719 bl2_stage_init 0xc1
783 22:01:37.845172 bl2_stage_init 0x02
784 22:01:37.845618
785 22:01:37.849765 L0:00000000
786 22:01:37.850243 L1:20000703
787 22:01:37.850689 L2:00008067
788 22:01:37.851124 L3:14000000
789 22:01:37.855272 B2:00402000
790 22:01:37.855748 B1:e0f83180
791 22:01:37.856249
792 22:01:37.856696 TE: 58159
793 22:01:37.857136
794 22:01:37.860958 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
795 22:01:37.861439
796 22:01:37.861887 Board ID = 1
797 22:01:37.866515 Set A53 clk to 24M
798 22:01:37.866991 Set A73 clk to 24M
799 22:01:37.867436 Set clk81 to 24M
800 22:01:37.872188 A53 clk: 1200 MHz
801 22:01:37.872662 A73 clk: 1200 MHz
802 22:01:37.873101 CLK81: 166.6M
803 22:01:37.873538 smccc: 00012ab4
804 22:01:37.877753 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
805 22:01:37.883347 board id: 1
806 22:01:37.889264 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
807 22:01:37.900028 fw parse done
808 22:01:37.905935 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
809 22:01:37.948709 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
810 22:01:37.959351 PIEI prepare done
811 22:01:37.959820 fastboot data load
812 22:01:37.960321 fastboot data verify
813 22:01:37.964995 verify result: 266
814 22:01:37.970570 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
815 22:01:37.971039 LPDDR4 probe
816 22:01:37.971481 ddr clk to 1584MHz
817 22:01:37.978680 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
818 22:01:38.015856
819 22:01:38.016368 dmc_version 0001
820 22:01:38.022150 Check phy result
821 22:01:38.028373 INFO : End of CA training
822 22:01:38.028853 INFO : End of initialization
823 22:01:38.034008 INFO : Training has run successfully!
824 22:01:38.034485 Check phy result
825 22:01:38.039591 INFO : End of initialization
826 22:01:38.040093 INFO : End of read enable training
827 22:01:38.045152 INFO : End of fine write leveling
828 22:01:38.050780 INFO : End of Write leveling coarse delay
829 22:01:38.051248 INFO : Training has run successfully!
830 22:01:38.051689 Check phy result
831 22:01:38.056317 INFO : End of initialization
832 22:01:38.056785 INFO : End of read dq deskew training
833 22:01:38.061963 INFO : End of MPR read delay center optimization
834 22:01:38.067539 INFO : End of write delay center optimization
835 22:01:38.073183 INFO : End of read delay center optimization
836 22:01:38.073651 INFO : End of max read latency training
837 22:01:38.078752 INFO : Training has run successfully!
838 22:01:38.079213 1D training succeed
839 22:01:38.087962 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
840 22:01:38.135604 Check phy result
841 22:01:38.136115 INFO : End of initialization
842 22:01:38.157419 INFO : End of 2D read delay Voltage center optimization
843 22:01:38.177705 INFO : End of 2D read delay Voltage center optimization
844 22:01:38.229766 INFO : End of 2D write delay Voltage center optimization
845 22:01:38.279205 INFO : End of 2D write delay Voltage center optimization
846 22:01:38.284672 INFO : Training has run successfully!
847 22:01:38.285158
848 22:01:38.285610 channel==0
849 22:01:38.290207 RxClkDly_Margin_A0==88 ps 9
850 22:01:38.290674 TxDqDly_Margin_A0==98 ps 10
851 22:01:38.295799 RxClkDly_Margin_A1==88 ps 9
852 22:01:38.296298 TxDqDly_Margin_A1==88 ps 9
853 22:01:38.296761 TrainedVREFDQ_A0==74
854 22:01:38.301478 TrainedVREFDQ_A1==74
855 22:01:38.302006 VrefDac_Margin_A0==25
856 22:01:38.302456 DeviceVref_Margin_A0==40
857 22:01:38.307017 VrefDac_Margin_A1==25
858 22:01:38.307517 DeviceVref_Margin_A1==40
859 22:01:38.307941
860 22:01:38.308413
861 22:01:38.308839 channel==1
862 22:01:38.312653 RxClkDly_Margin_A0==88 ps 9
863 22:01:38.313112 TxDqDly_Margin_A0==88 ps 9
864 22:01:38.318276 RxClkDly_Margin_A1==98 ps 10
865 22:01:38.318730 TxDqDly_Margin_A1==88 ps 9
866 22:01:38.323759 TrainedVREFDQ_A0==77
867 22:01:38.324251 TrainedVREFDQ_A1==77
868 22:01:38.324679 VrefDac_Margin_A0==22
869 22:01:38.329467 DeviceVref_Margin_A0==37
870 22:01:38.329916 VrefDac_Margin_A1==22
871 22:01:38.335005 DeviceVref_Margin_A1==37
872 22:01:38.335466
873 22:01:38.335889 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
874 22:01:38.336350
875 22:01:38.368588 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
876 22:01:38.369076 2D training succeed
877 22:01:38.374087 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
878 22:01:38.379709 auto size-- 65535DDR cs0 size: 2048MB
879 22:01:38.380225 DDR cs1 size: 2048MB
880 22:01:38.385320 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
881 22:01:38.385783 cs0 DataBus test pass
882 22:01:38.390887 cs1 DataBus test pass
883 22:01:38.391342 cs0 AddrBus test pass
884 22:01:38.391763 cs1 AddrBus test pass
885 22:01:38.392222
886 22:01:38.396552 100bdlr_step_size ps== 420
887 22:01:38.397028 result report
888 22:01:38.402158 boot times 0Enable ddr reg access
889 22:01:38.407300 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
890 22:01:38.420782 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
891 22:01:38.993763 0.0;M3 CHK:0;cm4_sp_mode 0
892 22:01:38.994419 MVN_1=0x00000000
893 22:01:38.999241 MVN_2=0x00000000
894 22:01:39.005020 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
895 22:01:39.005512 OPS=0x10
896 22:01:39.005967 ring efuse init
897 22:01:39.006414 chipver efuse init
898 22:01:39.010606 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
899 22:01:39.016203 [0.018960 Inits done]
900 22:01:39.016680 secure task start!
901 22:01:39.017126 high task start!
902 22:01:39.020802 low task start!
903 22:01:39.021279 run into bl31
904 22:01:39.027446 NOTICE: BL31: v1.3(release):4fc40b1
905 22:01:39.035301 NOTICE: BL31: Built : 15:58:17, May 22 2019
906 22:01:39.035807 NOTICE: BL31: G12A normal boot!
907 22:01:39.060675 NOTICE: BL31: BL33 decompress pass
908 22:01:39.066288 ERROR: Error initializing runtime service opteed_fast
909 22:01:40.299210
910 22:01:40.299854
911 22:01:40.306760 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
912 22:01:40.307256
913 22:01:40.307713 Model: Libre Computer AML-A311D-CC Alta
914 22:01:40.515838 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
915 22:01:40.539505 DRAM: 2 GiB (effective 3.8 GiB)
916 22:01:40.682483 Core: 408 devices, 31 uclasses, devicetree: separate
917 22:01:40.687464 WDT: Not starting watchdog@f0d0
918 22:01:40.720579 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
919 22:01:40.733031 Loading Environment from FAT... Card did not respond to voltage select! : -110
920 22:01:40.737891 ** Bad device specification mmc 0 **
921 22:01:40.748336 Card did not respond to voltage select! : -110
922 22:01:40.755301 ** Bad device specification mmc 0 **
923 22:01:40.755781 Couldn't find partition mmc 0
924 22:01:40.764404 Card did not respond to voltage select! : -110
925 22:01:40.769884 ** Bad device specification mmc 0 **
926 22:01:40.770357 Couldn't find partition mmc 0
927 22:01:40.774729 Error: could not access storage.
928 22:01:41.118507 Net: eth0: ethernet@ff3f0000
929 22:01:41.119131 starting USB...
930 22:01:41.370246 Bus usb@ff500000: Register 3000140 NbrPorts 3
931 22:01:41.370828 Starting the controller
932 22:01:41.377204 USB XHCI 1.10
933 22:01:43.238561 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
934 22:01:43.239212 bl2_stage_init 0x01
935 22:01:43.239683 bl2_stage_init 0x81
936 22:01:43.244242 hw id: 0x0000 - pwm id 0x01
937 22:01:43.244731 bl2_stage_init 0xc1
938 22:01:43.245183 bl2_stage_init 0x02
939 22:01:43.245627
940 22:01:43.249668 L0:00000000
941 22:01:43.250143 L1:20000703
942 22:01:43.250586 L2:00008067
943 22:01:43.251022 L3:14000000
944 22:01:43.255300 B2:00402000
945 22:01:43.255780 B1:e0f83180
946 22:01:43.256256
947 22:01:43.256701 TE: 58167
948 22:01:43.257144
949 22:01:43.260877 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
950 22:01:43.261345
951 22:01:43.261788 Board ID = 1
952 22:01:43.266486 Set A53 clk to 24M
953 22:01:43.266966 Set A73 clk to 24M
954 22:01:43.267406 Set clk81 to 24M
955 22:01:43.272602 A53 clk: 1200 MHz
956 22:01:43.273073 A73 clk: 1200 MHz
957 22:01:43.273512 CLK81: 166.6M
958 22:01:43.273946 smccc: 00012abd
959 22:01:43.277637 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
960 22:01:43.283271 board id: 1
961 22:01:43.288498 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
962 22:01:43.299884 fw parse done
963 22:01:43.305078 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
964 22:01:43.348480 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
965 22:01:43.359366 PIEI prepare done
966 22:01:43.359835 fastboot data load
967 22:01:43.360329 fastboot data verify
968 22:01:43.365370 verify result: 266
969 22:01:43.370992 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
970 22:01:43.371455 LPDDR4 probe
971 22:01:43.371891 ddr clk to 1584MHz
972 22:01:43.378083 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
973 22:01:43.415674
974 22:01:43.416320 dmc_version 0001
975 22:01:43.422795 Check phy result
976 22:01:43.428547 INFO : End of CA training
977 22:01:43.429049 INFO : End of initialization
978 22:01:43.434312 INFO : Training has run successfully!
979 22:01:43.434864 Check phy result
980 22:01:43.439958 INFO : End of initialization
981 22:01:43.440505 INFO : End of read enable training
982 22:01:43.443103 INFO : End of fine write leveling
983 22:01:43.448506 INFO : End of Write leveling coarse delay
984 22:01:43.453983 INFO : Training has run successfully!
985 22:01:43.454463 Check phy result
986 22:01:43.454912 INFO : End of initialization
987 22:01:43.459693 INFO : End of read dq deskew training
988 22:01:43.465063 INFO : End of MPR read delay center optimization
989 22:01:43.465590 INFO : End of write delay center optimization
990 22:01:43.470660 INFO : End of read delay center optimization
991 22:01:43.476252 INFO : End of max read latency training
992 22:01:43.476731 INFO : Training has run successfully!
993 22:01:43.481826 1D training succeed
994 22:01:43.487617 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
995 22:01:43.535088 Check phy result
996 22:01:43.535620 INFO : End of initialization
997 22:01:43.557371 INFO : End of 2D read delay Voltage center optimization
998 22:01:43.576917 INFO : End of 2D read delay Voltage center optimization
999 22:01:43.628852 INFO : End of 2D write delay Voltage center optimization
1000 22:01:43.678963 INFO : End of 2D write delay Voltage center optimization
1001 22:01:43.684543 INFO : Training has run successfully!
1002 22:01:43.685149
1003 22:01:43.685891 channel==0
1004 22:01:43.690120 RxClkDly_Margin_A0==88 ps 9
1005 22:01:43.690738 TxDqDly_Margin_A0==98 ps 10
1006 22:01:43.693531 RxClkDly_Margin_A1==88 ps 9
1007 22:01:43.694120 TxDqDly_Margin_A1==98 ps 10
1008 22:01:43.699038 TrainedVREFDQ_A0==74
1009 22:01:43.699592 TrainedVREFDQ_A1==74
1010 22:01:43.704609 VrefDac_Margin_A0==25
1011 22:01:43.705232 DeviceVref_Margin_A0==40
1012 22:01:43.705702 VrefDac_Margin_A1==25
1013 22:01:43.710263 DeviceVref_Margin_A1==40
1014 22:01:43.710813
1015 22:01:43.711288
1016 22:01:43.711743 channel==1
1017 22:01:43.712238 RxClkDly_Margin_A0==98 ps 10
1018 22:01:43.713811 TxDqDly_Margin_A0==88 ps 9
1019 22:01:43.719631 RxClkDly_Margin_A1==98 ps 10
1020 22:01:43.720217 TxDqDly_Margin_A1==88 ps 9
1021 22:01:43.720698 TrainedVREFDQ_A0==76
1022 22:01:43.724703 TrainedVREFDQ_A1==77
1023 22:01:43.725242 VrefDac_Margin_A0==22
1024 22:01:43.730417 DeviceVref_Margin_A0==38
1025 22:01:43.730943 VrefDac_Margin_A1==22
1026 22:01:43.731403 DeviceVref_Margin_A1==37
1027 22:01:43.731846
1028 22:01:43.739256 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1029 22:01:43.739884
1030 22:01:43.770494 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1031 22:01:43.771234 2D training succeed
1032 22:01:43.776153 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1033 22:01:43.781751 auto size-- 65535DDR cs0 size: 2048MB
1034 22:01:43.782503 DDR cs1 size: 2048MB
1035 22:01:43.787475 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1036 22:01:43.787915 cs0 DataBus test pass
1037 22:01:43.788185 cs1 DataBus test pass
1038 22:01:43.792903 cs0 AddrBus test pass
1039 22:01:43.793713 cs1 AddrBus test pass
1040 22:01:43.794159
1041 22:01:43.794523 100bdlr_step_size ps== 420
1042 22:01:43.798551 result report
1043 22:01:43.798968 boot times 0Enable ddr reg access
1044 22:01:43.806610 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1045 22:01:43.820300 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1046 22:01:44.394539 0.0;M3 CHK:0;cm4_sp_mode 0
1047 22:01:44.395123 MVN_1=0x00000000
1048 22:01:44.400212 MVN_2=0x00000000
1049 22:01:44.405807 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1050 22:01:44.406100 OPS=0x10
1051 22:01:44.406357 ring efuse init
1052 22:01:44.406599 chipver efuse init
1053 22:01:44.411364 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1054 22:01:44.417032 [0.018960 Inits done]
1055 22:01:44.417383 secure task start!
1056 22:01:44.417646 high task start!
1057 22:01:44.420844 low task start!
1058 22:01:44.421186 run into bl31
1059 22:01:44.428218 NOTICE: BL31: v1.3(release):4fc40b1
1060 22:01:44.436025 NOTICE: BL31: Built : 15:58:17, May 22 2019
1061 22:01:44.436356 NOTICE: BL31: G12A normal boot!
1062 22:01:44.461445 NOTICE: BL31: BL33 decompress pass
1063 22:01:44.466038 ERROR: Error initializing runtime service opteed_fast
1064 22:01:45.700050
1065 22:01:45.700496
1066 22:01:45.708437 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1067 22:01:45.708980
1068 22:01:45.709343 Model: Libre Computer AML-A311D-CC Alta
1069 22:01:45.916758 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1070 22:01:45.940296 DRAM: 2 GiB (effective 3.8 GiB)
1071 22:01:46.083256 Core: 408 devices, 31 uclasses, devicetree: separate
1072 22:01:46.089066 WDT: Not starting watchdog@f0d0
1073 22:01:46.121367 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1074 22:01:46.133758 Loading Environment from FAT... Card did not respond to voltage select! : -110
1075 22:01:46.138797 ** Bad device specification mmc 0 **
1076 22:01:46.149121 Card did not respond to voltage select! : -110
1077 22:01:46.156801 ** Bad device specification mmc 0 **
1078 22:01:46.157325 Couldn't find partition mmc 0
1079 22:01:46.165108 Card did not respond to voltage select! : -110
1080 22:01:46.170692 ** Bad device specification mmc 0 **
1081 22:01:46.171167 Couldn't find partition mmc 0
1082 22:01:46.175759 Error: could not access storage.
1083 22:01:46.518123 Net: eth0: ethernet@ff3f0000
1084 22:01:46.518724 starting USB...
1085 22:01:46.769975 Bus usb@ff500000: Register 3000140 NbrPorts 3
1086 22:01:46.770383 Starting the controller
1087 22:01:46.776901 USB XHCI 1.10
1088 22:01:48.331078 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1089 22:01:48.339319 scanning usb for storage devices... 0 Storage Device(s) found
1091 22:01:48.390402 Hit any key to stop autoboot: 1
1092 22:01:48.391181 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1093 22:01:48.391532 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1094 22:01:48.391783 Setting prompt string to ['=>']
1095 22:01:48.392067 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1096 22:01:48.396720 0
1097 22:01:48.397300 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1098 22:01:48.397566 Sending with 10 millisecond of delay
1100 22:01:49.532566 => setenv autoload no
1101 22:01:49.543165 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1102 22:01:49.545966 setenv autoload no
1103 22:01:49.546538 Sending with 10 millisecond of delay
1105 22:01:51.343002 => setenv initrd_high 0xffffffff
1106 22:01:51.353802 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1107 22:01:51.354720 setenv initrd_high 0xffffffff
1108 22:01:51.355470 Sending with 10 millisecond of delay
1110 22:01:52.972126 => setenv fdt_high 0xffffffff
1111 22:01:52.982897 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1112 22:01:52.983712 setenv fdt_high 0xffffffff
1113 22:01:52.984473 Sending with 10 millisecond of delay
1115 22:01:53.276304 => dhcp
1116 22:01:53.286888 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1117 22:01:53.287429 dhcp
1118 22:01:53.287673 Speed: 1000, full duplex
1119 22:01:53.287907 BOOTP broadcast 1
1120 22:01:53.461204 DHCP client bound to address 192.168.6.27 (175 ms)
1121 22:01:53.462389 Sending with 10 millisecond of delay
1123 22:01:55.139461 => setenv serverip 192.168.6.2
1124 22:01:55.150293 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1125 22:01:55.151167 setenv serverip 192.168.6.2
1126 22:01:55.151901 Sending with 10 millisecond of delay
1128 22:01:58.876526 => tftpboot 0x01080000 962938/tftp-deploy-dzigv6gk/kernel/uImage
1129 22:01:58.889313 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1130 22:01:58.890308 tftpboot 0x01080000 962938/tftp-deploy-dzigv6gk/kernel/uImage
1131 22:01:58.890800 Speed: 1000, full duplex
1132 22:01:58.891241 Using ethernet@ff3f0000 device
1133 22:01:58.891683 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1134 22:01:58.896060 Filename '962938/tftp-deploy-dzigv6gk/kernel/uImage'.
1135 22:01:58.898866 Load address: 0x1080000
1136 22:02:01.733686 Loading: *################################################## 43.6 MiB
1137 22:02:01.734341 15.4 MiB/s
1138 22:02:01.734812 done
1139 22:02:01.738006 Bytes transferred = 45713984 (2b98a40 hex)
1140 22:02:01.738790 Sending with 10 millisecond of delay
1142 22:02:06.425863 => tftpboot 0x08000000 962938/tftp-deploy-dzigv6gk/ramdisk/ramdisk.cpio.gz.uboot
1143 22:02:06.436665 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1144 22:02:06.437561 tftpboot 0x08000000 962938/tftp-deploy-dzigv6gk/ramdisk/ramdisk.cpio.gz.uboot
1145 22:02:06.437987 Speed: 1000, full duplex
1146 22:02:06.438383 Using ethernet@ff3f0000 device
1147 22:02:06.439720 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1148 22:02:06.451565 Filename '962938/tftp-deploy-dzigv6gk/ramdisk/ramdisk.cpio.gz.uboot'.
1149 22:02:06.452092 Load address: 0x8000000
1150 22:02:12.949923 Loading: *########################T ######################### UDP wrong checksum 00000005 0000da46
1151 22:02:13.123861 UDP wrong checksum 000000ff 0000fe88
1152 22:02:13.175249 UDP wrong checksum 000000ff 00008e7b
1153 22:02:14.434988 UDP wrong checksum 000000ff 00009cfa
1154 22:02:14.456569 UDP wrong checksum 000000ff 000032ed
1155 22:02:17.950947 T UDP wrong checksum 00000005 0000da46
1156 22:02:27.954119 T T UDP wrong checksum 00000005 0000da46
1157 22:02:46.220621 T T T UDP wrong checksum 000000ff 00005fac
1158 22:02:46.263660 UDP wrong checksum 000000ff 0000f69e
1159 22:02:47.957964 T UDP wrong checksum 00000005 0000da46
1160 22:03:02.962147 T T
1161 22:03:02.962829 Retry count exceeded; starting again
1163 22:03:02.964495 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1166 22:03:02.966602 end: 2.4 uboot-commands (duration 00:01:51) [common]
1168 22:03:02.968196 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1170 22:03:02.969393 end: 2 uboot-action (duration 00:01:51) [common]
1172 22:03:02.971039 Cleaning after the job
1173 22:03:02.971625 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962938/tftp-deploy-dzigv6gk/ramdisk
1174 22:03:02.973020 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962938/tftp-deploy-dzigv6gk/kernel
1175 22:03:03.005516 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962938/tftp-deploy-dzigv6gk/dtb
1176 22:03:03.007218 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962938/tftp-deploy-dzigv6gk/nfsrootfs
1177 22:03:03.055843 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962938/tftp-deploy-dzigv6gk/modules
1178 22:03:03.062316 start: 4.1 power-off (timeout 00:00:30) [common]
1179 22:03:03.062921 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1180 22:03:03.097904 >> OK - accepted request
1181 22:03:03.100173 Returned 0 in 0 seconds
1182 22:03:03.201215 end: 4.1 power-off (duration 00:00:00) [common]
1184 22:03:03.202214 start: 4.2 read-feedback (timeout 00:10:00) [common]
1185 22:03:03.202873 Listened to connection for namespace 'common' for up to 1s
1186 22:03:04.203858 Finalising connection for namespace 'common'
1187 22:03:04.204657 Disconnecting from shell: Finalise
1188 22:03:04.205036 =>
1189 22:03:04.305815 end: 4.2 read-feedback (duration 00:00:01) [common]
1190 22:03:04.306340 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/962938
1191 22:03:07.649974 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/962938
1192 22:03:07.650696 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.