Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 15:39:26.029035 lava-dispatcher, installed at version: 2024.01
2 15:39:26.029824 start: 0 validate
3 15:39:26.030308 Start time: 2024-11-04 15:39:26.030278+00:00 (UTC)
4 15:39:26.030868 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 15:39:26.031412 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 15:39:26.075773 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 15:39:26.076370 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-regulator%2Ffor-linus%2Fv6.12-rc3-2-g5e53e4a66bc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 15:39:26.107455 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 15:39:26.108159 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-regulator%2Ffor-linus%2Fv6.12-rc3-2-g5e53e4a66bc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 15:39:26.141144 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 15:39:26.141661 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 15:39:26.175654 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 15:39:26.176178 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-regulator%2Ffor-linus%2Fv6.12-rc3-2-g5e53e4a66bc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 15:39:26.220357 validate duration: 0.19
16 15:39:26.221829 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 15:39:26.222434 start: 1.1 download-retry (timeout 00:10:00) [common]
18 15:39:26.223033 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 15:39:26.224009 Not decompressing ramdisk as can be used compressed.
20 15:39:26.224798 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 15:39:26.225318 saving as /var/lib/lava/dispatcher/tmp/934537/tftp-deploy-4un9sz67/ramdisk/initrd.cpio.gz
22 15:39:26.225819 total size: 5628169 (5 MB)
23 15:39:26.270658 progress 0 % (0 MB)
24 15:39:26.276598 progress 5 % (0 MB)
25 15:39:26.284430 progress 10 % (0 MB)
26 15:39:26.291351 progress 15 % (0 MB)
27 15:39:26.298989 progress 20 % (1 MB)
28 15:39:26.305096 progress 25 % (1 MB)
29 15:39:26.309220 progress 30 % (1 MB)
30 15:39:26.313273 progress 35 % (1 MB)
31 15:39:26.316827 progress 40 % (2 MB)
32 15:39:26.320850 progress 45 % (2 MB)
33 15:39:26.324481 progress 50 % (2 MB)
34 15:39:26.328545 progress 55 % (2 MB)
35 15:39:26.332455 progress 60 % (3 MB)
36 15:39:26.336258 progress 65 % (3 MB)
37 15:39:26.340216 progress 70 % (3 MB)
38 15:39:26.343822 progress 75 % (4 MB)
39 15:39:26.347718 progress 80 % (4 MB)
40 15:39:26.351114 progress 85 % (4 MB)
41 15:39:26.354922 progress 90 % (4 MB)
42 15:39:26.358690 progress 95 % (5 MB)
43 15:39:26.362061 progress 100 % (5 MB)
44 15:39:26.362763 5 MB downloaded in 0.14 s (39.20 MB/s)
45 15:39:26.363323 end: 1.1.1 http-download (duration 00:00:00) [common]
47 15:39:26.364356 end: 1.1 download-retry (duration 00:00:00) [common]
48 15:39:26.364667 start: 1.2 download-retry (timeout 00:10:00) [common]
49 15:39:26.364942 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 15:39:26.365434 downloading http://storage.kernelci.org/broonie-regulator/for-linus/v6.12-rc3-2-g5e53e4a66bc7/arm64/defconfig/gcc-12/kernel/Image
51 15:39:26.365691 saving as /var/lib/lava/dispatcher/tmp/934537/tftp-deploy-4un9sz67/kernel/Image
52 15:39:26.365901 total size: 45713920 (43 MB)
53 15:39:26.366114 No compression specified
54 15:39:26.407267 progress 0 % (0 MB)
55 15:39:26.436130 progress 5 % (2 MB)
56 15:39:26.464291 progress 10 % (4 MB)
57 15:39:26.492867 progress 15 % (6 MB)
58 15:39:26.521532 progress 20 % (8 MB)
59 15:39:26.549184 progress 25 % (10 MB)
60 15:39:26.577798 progress 30 % (13 MB)
61 15:39:26.607637 progress 35 % (15 MB)
62 15:39:26.635357 progress 40 % (17 MB)
63 15:39:26.662619 progress 45 % (19 MB)
64 15:39:26.690377 progress 50 % (21 MB)
65 15:39:26.718607 progress 55 % (24 MB)
66 15:39:26.746790 progress 60 % (26 MB)
67 15:39:26.774531 progress 65 % (28 MB)
68 15:39:26.802031 progress 70 % (30 MB)
69 15:39:26.830359 progress 75 % (32 MB)
70 15:39:26.857805 progress 80 % (34 MB)
71 15:39:26.884745 progress 85 % (37 MB)
72 15:39:26.912229 progress 90 % (39 MB)
73 15:39:26.939823 progress 95 % (41 MB)
74 15:39:26.966420 progress 100 % (43 MB)
75 15:39:26.966942 43 MB downloaded in 0.60 s (72.54 MB/s)
76 15:39:26.967410 end: 1.2.1 http-download (duration 00:00:01) [common]
78 15:39:26.968254 end: 1.2 download-retry (duration 00:00:01) [common]
79 15:39:26.968531 start: 1.3 download-retry (timeout 00:09:59) [common]
80 15:39:26.968796 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 15:39:26.969266 downloading http://storage.kernelci.org/broonie-regulator/for-linus/v6.12-rc3-2-g5e53e4a66bc7/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 15:39:26.969532 saving as /var/lib/lava/dispatcher/tmp/934537/tftp-deploy-4un9sz67/dtb/meson-g12b-a311d-libretech-cc.dtb
83 15:39:26.969742 total size: 54703 (0 MB)
84 15:39:26.969949 No compression specified
85 15:39:27.009095 progress 59 % (0 MB)
86 15:39:27.009932 progress 100 % (0 MB)
87 15:39:27.010478 0 MB downloaded in 0.04 s (1.28 MB/s)
88 15:39:27.010945 end: 1.3.1 http-download (duration 00:00:00) [common]
90 15:39:27.011858 end: 1.3 download-retry (duration 00:00:00) [common]
91 15:39:27.012220 start: 1.4 download-retry (timeout 00:09:59) [common]
92 15:39:27.012514 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 15:39:27.013018 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 15:39:27.013271 saving as /var/lib/lava/dispatcher/tmp/934537/tftp-deploy-4un9sz67/nfsrootfs/full.rootfs.tar
95 15:39:27.013477 total size: 120894716 (115 MB)
96 15:39:27.013688 Using unxz to decompress xz
97 15:39:27.052609 progress 0 % (0 MB)
98 15:39:27.843820 progress 5 % (5 MB)
99 15:39:28.687221 progress 10 % (11 MB)
100 15:39:29.476902 progress 15 % (17 MB)
101 15:39:30.214949 progress 20 % (23 MB)
102 15:39:30.805740 progress 25 % (28 MB)
103 15:39:31.624448 progress 30 % (34 MB)
104 15:39:32.410859 progress 35 % (40 MB)
105 15:39:32.788130 progress 40 % (46 MB)
106 15:39:33.160349 progress 45 % (51 MB)
107 15:39:33.883202 progress 50 % (57 MB)
108 15:39:34.776908 progress 55 % (63 MB)
109 15:39:35.625098 progress 60 % (69 MB)
110 15:39:36.424257 progress 65 % (74 MB)
111 15:39:37.228109 progress 70 % (80 MB)
112 15:39:38.053895 progress 75 % (86 MB)
113 15:39:38.851360 progress 80 % (92 MB)
114 15:39:39.627347 progress 85 % (98 MB)
115 15:39:40.489905 progress 90 % (103 MB)
116 15:39:41.279141 progress 95 % (109 MB)
117 15:39:42.117574 progress 100 % (115 MB)
118 15:39:42.130070 115 MB downloaded in 15.12 s (7.63 MB/s)
119 15:39:42.130817 end: 1.4.1 http-download (duration 00:00:15) [common]
121 15:39:42.132680 end: 1.4 download-retry (duration 00:00:15) [common]
122 15:39:42.133271 start: 1.5 download-retry (timeout 00:09:44) [common]
123 15:39:42.133846 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 15:39:42.134822 downloading http://storage.kernelci.org/broonie-regulator/for-linus/v6.12-rc3-2-g5e53e4a66bc7/arm64/defconfig/gcc-12/modules.tar.xz
125 15:39:42.135344 saving as /var/lib/lava/dispatcher/tmp/934537/tftp-deploy-4un9sz67/modules/modules.tar
126 15:39:42.135801 total size: 11613116 (11 MB)
127 15:39:42.136306 Using unxz to decompress xz
128 15:39:42.183403 progress 0 % (0 MB)
129 15:39:42.250251 progress 5 % (0 MB)
130 15:39:42.324300 progress 10 % (1 MB)
131 15:39:42.421340 progress 15 % (1 MB)
132 15:39:42.514908 progress 20 % (2 MB)
133 15:39:42.594667 progress 25 % (2 MB)
134 15:39:42.670537 progress 30 % (3 MB)
135 15:39:42.749623 progress 35 % (3 MB)
136 15:39:42.822526 progress 40 % (4 MB)
137 15:39:42.899592 progress 45 % (5 MB)
138 15:39:42.983997 progress 50 % (5 MB)
139 15:39:43.061358 progress 55 % (6 MB)
140 15:39:43.146500 progress 60 % (6 MB)
141 15:39:43.228593 progress 65 % (7 MB)
142 15:39:43.309023 progress 70 % (7 MB)
143 15:39:43.386690 progress 75 % (8 MB)
144 15:39:43.471485 progress 80 % (8 MB)
145 15:39:43.552501 progress 85 % (9 MB)
146 15:39:43.631451 progress 90 % (9 MB)
147 15:39:43.709658 progress 95 % (10 MB)
148 15:39:43.787336 progress 100 % (11 MB)
149 15:39:43.799307 11 MB downloaded in 1.66 s (6.66 MB/s)
150 15:39:43.800418 end: 1.5.1 http-download (duration 00:00:02) [common]
152 15:39:43.802049 end: 1.5 download-retry (duration 00:00:02) [common]
153 15:39:43.802570 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 15:39:43.803082 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 15:40:01.313762 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/934537/extract-nfsrootfs-j6q_ke83
156 15:40:01.314393 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
157 15:40:01.314711 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 15:40:01.315423 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx
159 15:40:01.315934 makedir: /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin
160 15:40:01.316423 makedir: /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/tests
161 15:40:01.316769 makedir: /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/results
162 15:40:01.317124 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-add-keys
163 15:40:01.317690 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-add-sources
164 15:40:01.318261 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-background-process-start
165 15:40:01.318810 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-background-process-stop
166 15:40:01.319404 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-common-functions
167 15:40:01.319962 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-echo-ipv4
168 15:40:01.320646 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-install-packages
169 15:40:01.321229 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-installed-packages
170 15:40:01.321782 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-os-build
171 15:40:01.322362 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-probe-channel
172 15:40:01.322923 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-probe-ip
173 15:40:01.323441 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-target-ip
174 15:40:01.324061 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-target-mac
175 15:40:01.324631 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-target-storage
176 15:40:01.325237 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-test-case
177 15:40:01.325815 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-test-event
178 15:40:01.326453 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-test-feedback
179 15:40:01.326999 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-test-raise
180 15:40:01.327522 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-test-reference
181 15:40:01.328132 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-test-runner
182 15:40:01.328719 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-test-set
183 15:40:01.329268 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-test-shell
184 15:40:01.329816 Updating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-add-keys (debian)
185 15:40:01.330416 Updating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-add-sources (debian)
186 15:40:01.331064 Updating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-install-packages (debian)
187 15:40:01.331688 Updating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-installed-packages (debian)
188 15:40:01.332442 Updating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/bin/lava-os-build (debian)
189 15:40:01.333093 Creating /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/environment
190 15:40:01.333584 LAVA metadata
191 15:40:01.333909 - LAVA_JOB_ID=934537
192 15:40:01.334190 - LAVA_DISPATCHER_IP=192.168.6.2
193 15:40:01.334652 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 15:40:01.335857 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 15:40:01.336281 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 15:40:01.336533 skipped lava-vland-overlay
197 15:40:01.336811 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 15:40:01.337107 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 15:40:01.337400 skipped lava-multinode-overlay
200 15:40:01.337730 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 15:40:01.338042 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 15:40:01.338328 Loading test definitions
203 15:40:01.338622 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 15:40:01.338848 Using /lava-934537 at stage 0
205 15:40:01.340186 uuid=934537_1.6.2.4.1 testdef=None
206 15:40:01.340547 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 15:40:01.340821 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 15:40:01.342531 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 15:40:01.343450 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 15:40:01.345673 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 15:40:01.346555 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 15:40:01.348897 runner path: /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/0/tests/0_timesync-off test_uuid 934537_1.6.2.4.1
215 15:40:01.349642 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 15:40:01.350496 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 15:40:01.350730 Using /lava-934537 at stage 0
219 15:40:01.351109 Fetching tests from https://github.com/kernelci/test-definitions.git
220 15:40:01.351416 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/0/tests/1_kselftest-rtc'
221 15:40:05.012601 Running '/usr/bin/git checkout kernelci.org
222 15:40:05.035083 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
223 15:40:05.036595 uuid=934537_1.6.2.4.5 testdef=None
224 15:40:05.036953 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 15:40:05.037709 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 15:40:05.040615 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 15:40:05.041452 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 15:40:05.048095 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 15:40:05.049775 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 15:40:05.056982 runner path: /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/0/tests/1_kselftest-rtc test_uuid 934537_1.6.2.4.5
234 15:40:05.057530 BOARD='meson-g12b-a311d-libretech-cc'
235 15:40:05.057935 BRANCH='broonie-regulator'
236 15:40:05.058331 SKIPFILE='/dev/null'
237 15:40:05.058723 SKIP_INSTALL='True'
238 15:40:05.059112 TESTPROG_URL='http://storage.kernelci.org/broonie-regulator/for-linus/v6.12-rc3-2-g5e53e4a66bc7/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 15:40:05.059549 TST_CASENAME=''
240 15:40:05.059945 TST_CMDFILES='rtc'
241 15:40:05.060813 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 15:40:05.062134 Creating lava-test-runner.conf files
244 15:40:05.062553 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/934537/lava-overlay-km17vbfx/lava-934537/0 for stage 0
245 15:40:05.063237 - 0_timesync-off
246 15:40:05.063706 - 1_kselftest-rtc
247 15:40:05.064381 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 15:40:05.064927 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 15:40:28.843080 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
250 15:40:28.843544 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:57) [common]
251 15:40:28.843816 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 15:40:28.844140 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 15:40:28.844423 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:57) [common]
254 15:40:29.470528 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 15:40:29.471027 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 15:40:29.471282 extracting modules file /var/lib/lava/dispatcher/tmp/934537/tftp-deploy-4un9sz67/modules/modules.tar to /var/lib/lava/dispatcher/tmp/934537/extract-nfsrootfs-j6q_ke83
257 15:40:30.893968 extracting modules file /var/lib/lava/dispatcher/tmp/934537/tftp-deploy-4un9sz67/modules/modules.tar to /var/lib/lava/dispatcher/tmp/934537/extract-overlay-ramdisk-31swy96e/ramdisk
258 15:40:32.328890 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 15:40:32.329363 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 15:40:32.329645 [common] Applying overlay to NFS
261 15:40:32.329862 [common] Applying overlay /var/lib/lava/dispatcher/tmp/934537/compress-overlay-5mh64ddm/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/934537/extract-nfsrootfs-j6q_ke83
262 15:40:35.099813 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 15:40:35.100312 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 15:40:35.100587 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 15:40:35.100817 Converting downloaded kernel to a uImage
266 15:40:35.101143 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/934537/tftp-deploy-4un9sz67/kernel/Image /var/lib/lava/dispatcher/tmp/934537/tftp-deploy-4un9sz67/kernel/uImage
267 15:40:35.582432 output: Image Name:
268 15:40:35.582873 output: Created: Mon Nov 4 15:40:35 2024
269 15:40:35.583102 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 15:40:35.583319 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 15:40:35.583526 output: Load Address: 01080000
272 15:40:35.583731 output: Entry Point: 01080000
273 15:40:35.583935 output:
274 15:40:35.584314 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 15:40:35.584598 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 15:40:35.584888 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 15:40:35.585155 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 15:40:35.585430 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 15:40:35.585706 Building ramdisk /var/lib/lava/dispatcher/tmp/934537/extract-overlay-ramdisk-31swy96e/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/934537/extract-overlay-ramdisk-31swy96e/ramdisk
280 15:40:37.829841 >> 166779 blocks
281 15:40:45.565033 Adding RAMdisk u-boot header.
282 15:40:45.565711 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/934537/extract-overlay-ramdisk-31swy96e/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/934537/extract-overlay-ramdisk-31swy96e/ramdisk.cpio.gz.uboot
283 15:40:45.803574 output: Image Name:
284 15:40:45.804064 output: Created: Mon Nov 4 15:40:45 2024
285 15:40:45.804513 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 15:40:45.804928 output: Data Size: 23423963 Bytes = 22874.96 KiB = 22.34 MiB
287 15:40:45.805355 output: Load Address: 00000000
288 15:40:45.805755 output: Entry Point: 00000000
289 15:40:45.806155 output:
290 15:40:45.807284 rename /var/lib/lava/dispatcher/tmp/934537/extract-overlay-ramdisk-31swy96e/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/934537/tftp-deploy-4un9sz67/ramdisk/ramdisk.cpio.gz.uboot
291 15:40:45.808038 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 15:40:45.808602 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 15:40:45.809141 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:40) [common]
294 15:40:45.809621 No LXC device requested
295 15:40:45.810136 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 15:40:45.810654 start: 1.8 deploy-device-env (timeout 00:08:40) [common]
297 15:40:45.811156 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 15:40:45.811569 Checking files for TFTP limit of 4294967296 bytes.
299 15:40:45.814249 end: 1 tftp-deploy (duration 00:01:20) [common]
300 15:40:45.814826 start: 2 uboot-action (timeout 00:05:00) [common]
301 15:40:45.815358 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 15:40:45.815862 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 15:40:45.816412 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 15:40:45.816947 Using kernel file from prepare-kernel: 934537/tftp-deploy-4un9sz67/kernel/uImage
305 15:40:45.817581 substitutions:
306 15:40:45.817995 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 15:40:45.818407 - {DTB_ADDR}: 0x01070000
308 15:40:45.818811 - {DTB}: 934537/tftp-deploy-4un9sz67/dtb/meson-g12b-a311d-libretech-cc.dtb
309 15:40:45.819222 - {INITRD}: 934537/tftp-deploy-4un9sz67/ramdisk/ramdisk.cpio.gz.uboot
310 15:40:45.819624 - {KERNEL_ADDR}: 0x01080000
311 15:40:45.820076 - {KERNEL}: 934537/tftp-deploy-4un9sz67/kernel/uImage
312 15:40:45.820488 - {LAVA_MAC}: None
313 15:40:45.820930 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/934537/extract-nfsrootfs-j6q_ke83
314 15:40:45.821339 - {NFS_SERVER_IP}: 192.168.6.2
315 15:40:45.821739 - {PRESEED_CONFIG}: None
316 15:40:45.822136 - {PRESEED_LOCAL}: None
317 15:40:45.822532 - {RAMDISK_ADDR}: 0x08000000
318 15:40:45.822926 - {RAMDISK}: 934537/tftp-deploy-4un9sz67/ramdisk/ramdisk.cpio.gz.uboot
319 15:40:45.823322 - {ROOT_PART}: None
320 15:40:45.823716 - {ROOT}: None
321 15:40:45.824138 - {SERVER_IP}: 192.168.6.2
322 15:40:45.824535 - {TEE_ADDR}: 0x83000000
323 15:40:45.824925 - {TEE}: None
324 15:40:45.825320 Parsed boot commands:
325 15:40:45.825704 - setenv autoload no
326 15:40:45.826096 - setenv initrd_high 0xffffffff
327 15:40:45.826486 - setenv fdt_high 0xffffffff
328 15:40:45.826873 - dhcp
329 15:40:45.827261 - setenv serverip 192.168.6.2
330 15:40:45.827656 - tftpboot 0x01080000 934537/tftp-deploy-4un9sz67/kernel/uImage
331 15:40:45.828073 - tftpboot 0x08000000 934537/tftp-deploy-4un9sz67/ramdisk/ramdisk.cpio.gz.uboot
332 15:40:45.828471 - tftpboot 0x01070000 934537/tftp-deploy-4un9sz67/dtb/meson-g12b-a311d-libretech-cc.dtb
333 15:40:45.828869 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/934537/extract-nfsrootfs-j6q_ke83,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 15:40:45.829275 - bootm 0x01080000 0x08000000 0x01070000
335 15:40:45.829777 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 15:40:45.831277 start: 2.3 connect-device (timeout 00:05:00) [common]
338 15:40:45.831699 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 15:40:45.846698 Setting prompt string to ['lava-test: # ']
340 15:40:45.848227 end: 2.3 connect-device (duration 00:00:00) [common]
341 15:40:45.848858 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 15:40:45.849434 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 15:40:45.849975 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 15:40:45.851171 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 15:40:45.885380 >> OK - accepted request
346 15:40:45.887500 Returned 0 in 0 seconds
347 15:40:45.988648 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 15:40:45.990275 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 15:40:45.990855 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 15:40:45.991375 Setting prompt string to ['Hit any key to stop autoboot']
352 15:40:45.991842 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 15:40:45.993529 Trying 192.168.56.21...
354 15:40:45.994041 Connected to conserv1.
355 15:40:45.994468 Escape character is '^]'.
356 15:40:45.994895
357 15:40:45.995330 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 15:40:45.995761
359 15:40:56.717182 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 15:40:56.717828 bl2_stage_init 0x01
361 15:40:56.718266 bl2_stage_init 0x81
362 15:40:56.722787 hw id: 0x0000 - pwm id 0x01
363 15:40:56.723352 bl2_stage_init 0xc1
364 15:40:56.723863 bl2_stage_init 0x02
365 15:40:56.724451
366 15:40:56.728323 L0:00000000
367 15:40:56.728797 L1:20000703
368 15:40:56.729208 L2:00008067
369 15:40:56.729606 L3:14000000
370 15:40:56.733843 B2:00402000
371 15:40:56.734284 B1:e0f83180
372 15:40:56.734687
373 15:40:56.735077 TE: 58167
374 15:40:56.735467
375 15:40:56.739447 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 15:40:56.739865
377 15:40:56.740288 Board ID = 1
378 15:40:56.745062 Set A53 clk to 24M
379 15:40:56.745478 Set A73 clk to 24M
380 15:40:56.745863 Set clk81 to 24M
381 15:40:56.750659 A53 clk: 1200 MHz
382 15:40:56.751079 A73 clk: 1200 MHz
383 15:40:56.751464 CLK81: 166.6M
384 15:40:56.751845 smccc: 00012abd
385 15:40:56.756347 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 15:40:56.761872 board id: 1
387 15:40:56.767743 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 15:40:56.778451 fw parse done
389 15:40:56.784362 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 15:40:56.827038 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 15:40:56.837905 PIEI prepare done
392 15:40:56.838344 fastboot data load
393 15:40:56.838736 fastboot data verify
394 15:40:56.843580 verify result: 266
395 15:40:56.849233 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 15:40:56.849668 LPDDR4 probe
397 15:40:56.850078 ddr clk to 1584MHz
398 15:40:56.857165 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 15:40:56.894476
400 15:40:56.894948 dmc_version 0001
401 15:40:56.901116 Check phy result
402 15:40:56.906973 INFO : End of CA training
403 15:40:56.907406 INFO : End of initialization
404 15:40:56.912558 INFO : Training has run successfully!
405 15:40:56.912983 Check phy result
406 15:40:56.918128 INFO : End of initialization
407 15:40:56.918563 INFO : End of read enable training
408 15:40:56.923791 INFO : End of fine write leveling
409 15:40:56.929365 INFO : End of Write leveling coarse delay
410 15:40:56.929787 INFO : Training has run successfully!
411 15:40:56.930188 Check phy result
412 15:40:56.934971 INFO : End of initialization
413 15:40:56.935412 INFO : End of read dq deskew training
414 15:40:56.940531 INFO : End of MPR read delay center optimization
415 15:40:56.946147 INFO : End of write delay center optimization
416 15:40:56.951777 INFO : End of read delay center optimization
417 15:40:56.952247 INFO : End of max read latency training
418 15:40:56.957383 INFO : Training has run successfully!
419 15:40:56.957806 1D training succeed
420 15:40:56.966574 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 15:40:57.014171 Check phy result
422 15:40:57.014651 INFO : End of initialization
423 15:40:57.035883 INFO : End of 2D read delay Voltage center optimization
424 15:40:57.056124 INFO : End of 2D read delay Voltage center optimization
425 15:40:57.108154 INFO : End of 2D write delay Voltage center optimization
426 15:40:57.157583 INFO : End of 2D write delay Voltage center optimization
427 15:40:57.163071 INFO : Training has run successfully!
428 15:40:57.163510
429 15:40:57.163924 channel==0
430 15:40:57.168611 RxClkDly_Margin_A0==88 ps 9
431 15:40:57.169040 TxDqDly_Margin_A0==98 ps 10
432 15:40:57.174212 RxClkDly_Margin_A1==88 ps 9
433 15:40:57.174635 TxDqDly_Margin_A1==98 ps 10
434 15:40:57.175048 TrainedVREFDQ_A0==74
435 15:40:57.179834 TrainedVREFDQ_A1==74
436 15:40:57.180298 VrefDac_Margin_A0==25
437 15:40:57.180716 DeviceVref_Margin_A0==40
438 15:40:57.185478 VrefDac_Margin_A1==25
439 15:40:57.185909 DeviceVref_Margin_A1==40
440 15:40:57.186310
441 15:40:57.186710
442 15:40:57.191124 channel==1
443 15:40:57.191549 RxClkDly_Margin_A0==98 ps 10
444 15:40:57.191947 TxDqDly_Margin_A0==88 ps 9
445 15:40:57.196724 RxClkDly_Margin_A1==88 ps 9
446 15:40:57.197157 TxDqDly_Margin_A1==88 ps 9
447 15:40:57.202321 TrainedVREFDQ_A0==76
448 15:40:57.202781 TrainedVREFDQ_A1==77
449 15:40:57.203186 VrefDac_Margin_A0==22
450 15:40:57.207918 DeviceVref_Margin_A0==38
451 15:40:57.208391 VrefDac_Margin_A1==24
452 15:40:57.213431 DeviceVref_Margin_A1==37
453 15:40:57.213861
454 15:40:57.214263 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 15:40:57.214661
456 15:40:57.247100 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
457 15:40:57.247777 2D training succeed
458 15:40:57.252714 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 15:40:57.258300 auto size-- 65535DDR cs0 size: 2048MB
460 15:40:57.258831 DDR cs1 size: 2048MB
461 15:40:57.263883 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 15:40:57.264466 cs0 DataBus test pass
463 15:40:57.269508 cs1 DataBus test pass
464 15:40:57.270039 cs0 AddrBus test pass
465 15:40:57.270516 cs1 AddrBus test pass
466 15:40:57.270989
467 15:40:57.275122 100bdlr_step_size ps== 420
468 15:40:57.275657 result report
469 15:40:57.280720 boot times 0Enable ddr reg access
470 15:40:57.286013 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 15:40:57.299504 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 15:40:57.873082 0.0;M3 CHK:0;cm4_sp_mode 0
473 15:40:57.873772 MVN_1=0x00000000
474 15:40:57.878618 MVN_2=0x00000000
475 15:40:57.884443 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 15:40:57.884995 OPS=0x10
477 15:40:57.885519 ring efuse init
478 15:40:57.886394 chipver efuse init
479 15:40:57.892616 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 15:40:57.893192 [0.018961 Inits done]
481 15:40:57.900135 secure task start!
482 15:40:57.900673 high task start!
483 15:40:57.901140 low task start!
484 15:40:57.901597 run into bl31
485 15:40:57.906741 NOTICE: BL31: v1.3(release):4fc40b1
486 15:40:57.914590 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 15:40:57.915205 NOTICE: BL31: G12A normal boot!
488 15:40:57.942132 NOTICE: BL31: BL33 decompress pass
489 15:40:57.944842 ERROR: Error initializing runtime service opteed_fast
490 15:40:59.178507
491 15:40:59.179260
492 15:40:59.186989 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 15:40:59.187588
494 15:40:59.188116 Model: Libre Computer AML-A311D-CC Alta
495 15:40:59.395756 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 15:40:59.418778 DRAM: 2 GiB (effective 3.8 GiB)
497 15:40:59.562047 Core: 408 devices, 31 uclasses, devicetree: separate
498 15:40:59.567739 WDT: Not starting watchdog@f0d0
499 15:40:59.600083 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 15:40:59.612503 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 15:40:59.618812 ** Bad device specification mmc 0 **
502 15:40:59.627773 Card did not respond to voltage select! : -110
503 15:40:59.635626 ** Bad device specification mmc 0 **
504 15:40:59.636550 Couldn't find partition mmc 0
505 15:40:59.643893 Card did not respond to voltage select! : -110
506 15:40:59.649196 ** Bad device specification mmc 0 **
507 15:40:59.649762 Couldn't find partition mmc 0
508 15:40:59.654406 Error: could not access storage.
509 15:41:00.917566 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 15:41:00.918218 bl2_stage_init 0x01
511 15:41:00.918702 bl2_stage_init 0x81
512 15:41:00.923083 hw id: 0x0000 - pwm id 0x01
513 15:41:00.923572 bl2_stage_init 0xc1
514 15:41:00.924070 bl2_stage_init 0x02
515 15:41:00.924531
516 15:41:00.928813 L0:00000000
517 15:41:00.929727 L1:20000703
518 15:41:00.930508 L2:00008067
519 15:41:00.930974 L3:14000000
520 15:41:00.931742 B2:00402000
521 15:41:00.932244 B1:e0f83180
522 15:41:00.932692
523 15:41:00.933138 TE: 58159
524 15:41:00.933580
525 15:41:00.942705 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 15:41:00.943225
527 15:41:00.943685 Board ID = 1
528 15:41:00.944187 Set A53 clk to 24M
529 15:41:00.944775 Set A73 clk to 24M
530 15:41:00.948571 Set clk81 to 24M
531 15:41:00.949449 A53 clk: 1200 MHz
532 15:41:00.950333 A73 clk: 1200 MHz
533 15:41:00.951876 CLK81: 166.6M
534 15:41:00.952856 smccc: 00012ab5
535 15:41:00.957322 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 15:41:00.962936 board id: 1
537 15:41:00.967243 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 15:41:00.978919 fw parse done
539 15:41:00.984122 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 15:41:01.026644 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 15:41:01.038363 PIEI prepare done
542 15:41:01.038869 fastboot data load
543 15:41:01.039322 fastboot data verify
544 15:41:01.043944 verify result: 266
545 15:41:01.049584 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 15:41:01.050443 LPDDR4 probe
547 15:41:01.051275 ddr clk to 1584MHz
548 15:41:01.056690 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 15:41:01.094963
550 15:41:01.095587 dmc_version 0001
551 15:41:01.101446 Check phy result
552 15:41:01.107346 INFO : End of CA training
553 15:41:01.107817 INFO : End of initialization
554 15:41:01.113094 INFO : Training has run successfully!
555 15:41:01.113998 Check phy result
556 15:41:01.118525 INFO : End of initialization
557 15:41:01.119393 INFO : End of read enable training
558 15:41:01.124187 INFO : End of fine write leveling
559 15:41:01.129792 INFO : End of Write leveling coarse delay
560 15:41:01.130370 INFO : Training has run successfully!
561 15:41:01.130852 Check phy result
562 15:41:01.135377 INFO : End of initialization
563 15:41:01.135915 INFO : End of read dq deskew training
564 15:41:01.140953 INFO : End of MPR read delay center optimization
565 15:41:01.146522 INFO : End of write delay center optimization
566 15:41:01.152289 INFO : End of read delay center optimization
567 15:41:01.152955 INFO : End of max read latency training
568 15:41:01.157724 INFO : Training has run successfully!
569 15:41:01.158230 1D training succeed
570 15:41:01.166989 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 15:41:01.214819 Check phy result
572 15:41:01.215902 INFO : End of initialization
573 15:41:01.236307 INFO : End of 2D read delay Voltage center optimization
574 15:41:01.256251 INFO : End of 2D read delay Voltage center optimization
575 15:41:01.308126 INFO : End of 2D write delay Voltage center optimization
576 15:41:01.357369 INFO : End of 2D write delay Voltage center optimization
577 15:41:01.362992 INFO : Training has run successfully!
578 15:41:01.363484
579 15:41:01.363949 channel==0
580 15:41:01.368498 RxClkDly_Margin_A0==88 ps 9
581 15:41:01.368998 TxDqDly_Margin_A0==98 ps 10
582 15:41:01.374134 RxClkDly_Margin_A1==88 ps 9
583 15:41:01.374631 TxDqDly_Margin_A1==98 ps 10
584 15:41:01.375089 TrainedVREFDQ_A0==74
585 15:41:01.379728 TrainedVREFDQ_A1==74
586 15:41:01.380243 VrefDac_Margin_A0==25
587 15:41:01.380684 DeviceVref_Margin_A0==40
588 15:41:01.385319 VrefDac_Margin_A1==25
589 15:41:01.385789 DeviceVref_Margin_A1==40
590 15:41:01.386224
591 15:41:01.386658
592 15:41:01.390903 channel==1
593 15:41:01.391367 RxClkDly_Margin_A0==98 ps 10
594 15:41:01.391807 TxDqDly_Margin_A0==98 ps 10
595 15:41:01.396495 RxClkDly_Margin_A1==98 ps 10
596 15:41:01.396990 TxDqDly_Margin_A1==88 ps 9
597 15:41:01.402120 TrainedVREFDQ_A0==77
598 15:41:01.402604 TrainedVREFDQ_A1==77
599 15:41:01.403047 VrefDac_Margin_A0==22
600 15:41:01.407694 DeviceVref_Margin_A0==37
601 15:41:01.408194 VrefDac_Margin_A1==22
602 15:41:01.413291 DeviceVref_Margin_A1==37
603 15:41:01.413753
604 15:41:01.414189 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 15:41:01.418899
606 15:41:01.446953 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
607 15:41:01.447532 2D training succeed
608 15:41:01.452507 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 15:41:01.458147 auto size-- 65535DDR cs0 size: 2048MB
610 15:41:01.458663 DDR cs1 size: 2048MB
611 15:41:01.463809 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 15:41:01.464356 cs0 DataBus test pass
613 15:41:01.469350 cs1 DataBus test pass
614 15:41:01.469846 cs0 AddrBus test pass
615 15:41:01.470300 cs1 AddrBus test pass
616 15:41:01.470741
617 15:41:01.474929 100bdlr_step_size ps== 420
618 15:41:01.475442 result report
619 15:41:01.480532 boot times 0Enable ddr reg access
620 15:41:01.485981 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 15:41:01.499413 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 15:41:02.071580 0.0;M3 CHK:0;cm4_sp_mode 0
623 15:41:02.072271 MVN_1=0x00000000
624 15:41:02.076966 MVN_2=0x00000000
625 15:41:02.082782 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 15:41:02.083298 OPS=0x10
627 15:41:02.083766 ring efuse init
628 15:41:02.084271 chipver efuse init
629 15:41:02.088409 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 15:41:02.093958 [0.018960 Inits done]
631 15:41:02.094489 secure task start!
632 15:41:02.094932 high task start!
633 15:41:02.098505 low task start!
634 15:41:02.098993 run into bl31
635 15:41:02.105193 NOTICE: BL31: v1.3(release):4fc40b1
636 15:41:02.112940 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 15:41:02.113443 NOTICE: BL31: G12A normal boot!
638 15:41:02.138402 NOTICE: BL31: BL33 decompress pass
639 15:41:02.144027 ERROR: Error initializing runtime service opteed_fast
640 15:41:03.376985
641 15:41:03.377658
642 15:41:03.385271 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 15:41:03.385793
644 15:41:03.386256 Model: Libre Computer AML-A311D-CC Alta
645 15:41:03.593783 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 15:41:03.617100 DRAM: 2 GiB (effective 3.8 GiB)
647 15:41:03.760141 Core: 408 devices, 31 uclasses, devicetree: separate
648 15:41:03.765939 WDT: Not starting watchdog@f0d0
649 15:41:03.798259 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 15:41:03.810699 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 15:41:03.815717 ** Bad device specification mmc 0 **
652 15:41:03.826058 Card did not respond to voltage select! : -110
653 15:41:03.833688 ** Bad device specification mmc 0 **
654 15:41:03.834208 Couldn't find partition mmc 0
655 15:41:03.842054 Card did not respond to voltage select! : -110
656 15:41:03.847580 ** Bad device specification mmc 0 **
657 15:41:03.848157 Couldn't find partition mmc 0
658 15:41:03.852620 Error: could not access storage.
659 15:41:04.196122 Net: eth0: ethernet@ff3f0000
660 15:41:04.196739 starting USB...
661 15:41:04.448373 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 15:41:04.449075 Starting the controller
663 15:41:04.455064 USB XHCI 1.10
664 15:41:06.168511 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 15:41:06.168921 bl2_stage_init 0x01
666 15:41:06.169146 bl2_stage_init 0x81
667 15:41:06.174476 hw id: 0x0000 - pwm id 0x01
668 15:41:06.174893 bl2_stage_init 0xc1
669 15:41:06.175245 bl2_stage_init 0x02
670 15:41:06.175580
671 15:41:06.179757 L0:00000000
672 15:41:06.180349 L1:20000703
673 15:41:06.180817 L2:00008067
674 15:41:06.181264 L3:14000000
675 15:41:06.182553 B2:00402000
676 15:41:06.183056 B1:e0f83180
677 15:41:06.183514
678 15:41:06.183964 TE: 58167
679 15:41:06.184455
680 15:41:06.194364 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 15:41:06.194967
682 15:41:06.195440 Board ID = 1
683 15:41:06.195897 Set A53 clk to 24M
684 15:41:06.196395 Set A73 clk to 24M
685 15:41:06.199443 Set clk81 to 24M
686 15:41:06.199953 A53 clk: 1200 MHz
687 15:41:06.200477 A73 clk: 1200 MHz
688 15:41:06.205080 CLK81: 166.6M
689 15:41:06.205610 smccc: 00012abe
690 15:41:06.210815 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 15:41:06.211594 board id: 1
692 15:41:06.219250 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 15:41:06.230228 fw parse done
694 15:41:06.235920 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 15:41:06.278457 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 15:41:06.289400 PIEI prepare done
697 15:41:06.290028 fastboot data load
698 15:41:06.290527 fastboot data verify
699 15:41:06.294924 verify result: 266
700 15:41:06.300565 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 15:41:06.301105 LPDDR4 probe
702 15:41:06.301538 ddr clk to 1584MHz
703 15:41:06.308440 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 15:41:06.345823
705 15:41:06.346221 dmc_version 0001
706 15:41:06.352476 Check phy result
707 15:41:06.358331 INFO : End of CA training
708 15:41:06.358817 INFO : End of initialization
709 15:41:06.363915 INFO : Training has run successfully!
710 15:41:06.364250 Check phy result
711 15:41:06.369811 INFO : End of initialization
712 15:41:06.370104 INFO : End of read enable training
713 15:41:06.375136 INFO : End of fine write leveling
714 15:41:06.380678 INFO : End of Write leveling coarse delay
715 15:41:06.381010 INFO : Training has run successfully!
716 15:41:06.381224 Check phy result
717 15:41:06.386287 INFO : End of initialization
718 15:41:06.386557 INFO : End of read dq deskew training
719 15:41:06.391944 INFO : End of MPR read delay center optimization
720 15:41:06.397649 INFO : End of write delay center optimization
721 15:41:06.403170 INFO : End of read delay center optimization
722 15:41:06.403672 INFO : End of max read latency training
723 15:41:06.408858 INFO : Training has run successfully!
724 15:41:06.409362 1D training succeed
725 15:41:06.418000 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 15:41:06.465550 Check phy result
727 15:41:06.465948 INFO : End of initialization
728 15:41:06.487243 INFO : End of 2D read delay Voltage center optimization
729 15:41:06.507574 INFO : End of 2D read delay Voltage center optimization
730 15:41:06.559607 INFO : End of 2D write delay Voltage center optimization
731 15:41:06.608941 INFO : End of 2D write delay Voltage center optimization
732 15:41:06.614350 INFO : Training has run successfully!
733 15:41:06.614637
734 15:41:06.614855 channel==0
735 15:41:06.620010 RxClkDly_Margin_A0==88 ps 9
736 15:41:06.620331 TxDqDly_Margin_A0==98 ps 10
737 15:41:06.625557 RxClkDly_Margin_A1==88 ps 9
738 15:41:06.625850 TxDqDly_Margin_A1==98 ps 10
739 15:41:06.626080 TrainedVREFDQ_A0==74
740 15:41:06.631183 TrainedVREFDQ_A1==74
741 15:41:06.631516 VrefDac_Margin_A0==25
742 15:41:06.631755 DeviceVref_Margin_A0==40
743 15:41:06.636847 VrefDac_Margin_A1==25
744 15:41:06.637156 DeviceVref_Margin_A1==40
745 15:41:06.637374
746 15:41:06.637599
747 15:41:06.642385 channel==1
748 15:41:06.642680 RxClkDly_Margin_A0==98 ps 10
749 15:41:06.642896 TxDqDly_Margin_A0==88 ps 9
750 15:41:06.647955 RxClkDly_Margin_A1==98 ps 10
751 15:41:06.648303 TxDqDly_Margin_A1==88 ps 9
752 15:41:06.653571 TrainedVREFDQ_A0==77
753 15:41:06.653878 TrainedVREFDQ_A1==77
754 15:41:06.654102 VrefDac_Margin_A0==22
755 15:41:06.659175 DeviceVref_Margin_A0==37
756 15:41:06.659473 VrefDac_Margin_A1==22
757 15:41:06.664827 DeviceVref_Margin_A1==37
758 15:41:06.665122
759 15:41:06.665370 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 15:41:06.665583
761 15:41:06.698400 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
762 15:41:06.698948 2D training succeed
763 15:41:06.704002 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 15:41:06.709627 auto size-- 65535DDR cs0 size: 2048MB
765 15:41:06.709957 DDR cs1 size: 2048MB
766 15:41:06.715192 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 15:41:06.715700 cs0 DataBus test pass
768 15:41:06.720997 cs1 DataBus test pass
769 15:41:06.721577 cs0 AddrBus test pass
770 15:41:06.722001 cs1 AddrBus test pass
771 15:41:06.722413
772 15:41:06.726480 100bdlr_step_size ps== 420
773 15:41:06.726996 result report
774 15:41:06.732095 boot times 0Enable ddr reg access
775 15:41:06.737483 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 15:41:06.750946 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 15:41:07.324492 0.0;M3 CHK:0;cm4_sp_mode 0
778 15:41:07.325155 MVN_1=0x00000000
779 15:41:07.330017 MVN_2=0x00000000
780 15:41:07.335771 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 15:41:07.336423 OPS=0x10
782 15:41:07.336839 ring efuse init
783 15:41:07.337237 chipver efuse init
784 15:41:07.341301 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 15:41:07.346878 [0.018961 Inits done]
786 15:41:07.347359 secure task start!
787 15:41:07.347760 high task start!
788 15:41:07.351476 low task start!
789 15:41:07.351947 run into bl31
790 15:41:07.358157 NOTICE: BL31: v1.3(release):4fc40b1
791 15:41:07.365978 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 15:41:07.366452 NOTICE: BL31: G12A normal boot!
793 15:41:07.391331 NOTICE: BL31: BL33 decompress pass
794 15:41:07.396973 ERROR: Error initializing runtime service opteed_fast
795 15:41:08.629912
796 15:41:08.630341
797 15:41:08.640557 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 15:41:08.640869
799 15:41:08.641090 Model: Libre Computer AML-A311D-CC Alta
800 15:41:08.846721 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 15:41:08.870119 DRAM: 2 GiB (effective 3.8 GiB)
802 15:41:09.013090 Core: 408 devices, 31 uclasses, devicetree: separate
803 15:41:09.018859 WDT: Not starting watchdog@f0d0
804 15:41:09.051227 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 15:41:09.063605 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 15:41:09.068583 ** Bad device specification mmc 0 **
807 15:41:09.078996 Card did not respond to voltage select! : -110
808 15:41:09.086655 ** Bad device specification mmc 0 **
809 15:41:09.086963 Couldn't find partition mmc 0
810 15:41:09.094908 Card did not respond to voltage select! : -110
811 15:41:09.100488 ** Bad device specification mmc 0 **
812 15:41:09.100783 Couldn't find partition mmc 0
813 15:41:09.105508 Error: could not access storage.
814 15:41:09.448052 Net: eth0: ethernet@ff3f0000
815 15:41:09.448628 starting USB...
816 15:41:09.699806 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 15:41:09.700261 Starting the controller
818 15:41:09.706796 USB XHCI 1.10
819 15:41:11.867840 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 15:41:11.868319 bl2_stage_init 0x01
821 15:41:11.868539 bl2_stage_init 0x81
822 15:41:11.873389 hw id: 0x0000 - pwm id 0x01
823 15:41:11.873684 bl2_stage_init 0xc1
824 15:41:11.873897 bl2_stage_init 0x02
825 15:41:11.874110
826 15:41:11.878965 L0:00000000
827 15:41:11.879366 L1:20000703
828 15:41:11.879703 L2:00008067
829 15:41:11.880047 L3:14000000
830 15:41:11.881907 B2:00402000
831 15:41:11.882178 B1:e0f83180
832 15:41:11.882385
833 15:41:11.882584 TE: 58167
834 15:41:11.882787
835 15:41:11.893099 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 15:41:11.893436
837 15:41:11.893645 Board ID = 1
838 15:41:11.893850 Set A53 clk to 24M
839 15:41:11.894064 Set A73 clk to 24M
840 15:41:11.898662 Set clk81 to 24M
841 15:41:11.899088 A53 clk: 1200 MHz
842 15:41:11.899430 A73 clk: 1200 MHz
843 15:41:11.904265 CLK81: 166.6M
844 15:41:11.904570 smccc: 00012abe
845 15:41:11.909843 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 15:41:11.910153 board id: 1
847 15:41:11.918462 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 15:41:11.929036 fw parse done
849 15:41:11.935126 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 15:41:11.977762 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 15:41:11.988653 PIEI prepare done
852 15:41:11.988971 fastboot data load
853 15:41:11.989185 fastboot data verify
854 15:41:11.994213 verify result: 266
855 15:41:11.999768 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 15:41:12.000103 LPDDR4 probe
857 15:41:12.000322 ddr clk to 1584MHz
858 15:41:12.007838 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 15:41:12.044260
860 15:41:12.044683 dmc_version 0001
861 15:41:12.050791 Check phy result
862 15:41:12.057689 INFO : End of CA training
863 15:41:12.058037 INFO : End of initialization
864 15:41:12.063214 INFO : Training has run successfully!
865 15:41:12.063544 Check phy result
866 15:41:12.068808 INFO : End of initialization
867 15:41:12.069114 INFO : End of read enable training
868 15:41:12.074416 INFO : End of fine write leveling
869 15:41:12.080023 INFO : End of Write leveling coarse delay
870 15:41:12.080310 INFO : Training has run successfully!
871 15:41:12.080521 Check phy result
872 15:41:12.085643 INFO : End of initialization
873 15:41:12.085920 INFO : End of read dq deskew training
874 15:41:12.091162 INFO : End of MPR read delay center optimization
875 15:41:12.096778 INFO : End of write delay center optimization
876 15:41:12.102353 INFO : End of read delay center optimization
877 15:41:12.102627 INFO : End of max read latency training
878 15:41:12.108047 INFO : Training has run successfully!
879 15:41:12.108480 1D training succeed
880 15:41:12.117273 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 15:41:12.163931 Check phy result
882 15:41:12.164592 INFO : End of initialization
883 15:41:12.185732 INFO : End of 2D read delay Voltage center optimization
884 15:41:12.206114 INFO : End of 2D read delay Voltage center optimization
885 15:41:12.258014 INFO : End of 2D write delay Voltage center optimization
886 15:41:12.308465 INFO : End of 2D write delay Voltage center optimization
887 15:41:12.313819 INFO : Training has run successfully!
888 15:41:12.314385
889 15:41:12.314874 channel==0
890 15:41:12.319429 RxClkDly_Margin_A0==88 ps 9
891 15:41:12.320053 TxDqDly_Margin_A0==98 ps 10
892 15:41:12.325060 RxClkDly_Margin_A1==88 ps 9
893 15:41:12.325629 TxDqDly_Margin_A1==98 ps 10
894 15:41:12.326122 TrainedVREFDQ_A0==74
895 15:41:12.330701 TrainedVREFDQ_A1==74
896 15:41:12.331438 VrefDac_Margin_A0==25
897 15:41:12.332109 DeviceVref_Margin_A0==40
898 15:41:12.336364 VrefDac_Margin_A1==25
899 15:41:12.336920 DeviceVref_Margin_A1==40
900 15:41:12.337441
901 15:41:12.337944
902 15:41:12.341835 channel==1
903 15:41:12.342405 RxClkDly_Margin_A0==98 ps 10
904 15:41:12.342910 TxDqDly_Margin_A0==98 ps 10
905 15:41:12.347449 RxClkDly_Margin_A1==98 ps 10
906 15:41:12.347954 TxDqDly_Margin_A1==88 ps 9
907 15:41:12.353006 TrainedVREFDQ_A0==77
908 15:41:12.353508 TrainedVREFDQ_A1==77
909 15:41:12.353945 VrefDac_Margin_A0==22
910 15:41:12.358765 DeviceVref_Margin_A0==37
911 15:41:12.359255 VrefDac_Margin_A1==22
912 15:41:12.364320 DeviceVref_Margin_A1==37
913 15:41:12.364799
914 15:41:12.365237 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 15:41:12.369781
916 15:41:12.397829 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
917 15:41:12.398366 2D training succeed
918 15:41:12.403386 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 15:41:12.408984 auto size-- 65535DDR cs0 size: 2048MB
920 15:41:12.409486 DDR cs1 size: 2048MB
921 15:41:12.414583 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 15:41:12.415138 cs0 DataBus test pass
923 15:41:12.417674 cs1 DataBus test pass
924 15:41:12.421001 cs0 AddrBus test pass
925 15:41:12.421492 cs1 AddrBus test pass
926 15:41:12.421928
927 15:41:12.427311 100bdlr_step_size ps== 420
928 15:41:12.427804 result report
929 15:41:12.428286 boot times 0Enable ddr reg access
930 15:41:12.436092 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 15:41:12.449369 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 15:41:13.023973 0.0;M3 CHK:0;cm4_sp_mode 0
933 15:41:13.024651 MVN_1=0x00000000
934 15:41:13.029373 MVN_2=0x00000000
935 15:41:13.035161 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 15:41:13.035687 OPS=0x10
937 15:41:13.036194 ring efuse init
938 15:41:13.036645 chipver efuse init
939 15:41:13.040726 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 15:41:13.046367 [0.018960 Inits done]
941 15:41:13.046858 secure task start!
942 15:41:13.047309 high task start!
943 15:41:13.049987 low task start!
944 15:41:13.050486 run into bl31
945 15:41:13.057610 NOTICE: BL31: v1.3(release):4fc40b1
946 15:41:13.064454 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 15:41:13.064978 NOTICE: BL31: G12A normal boot!
948 15:41:13.091337 NOTICE: BL31: BL33 decompress pass
949 15:41:13.096052 ERROR: Error initializing runtime service opteed_fast
950 15:41:14.329914
951 15:41:14.330587
952 15:41:14.338268 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 15:41:14.338775
954 15:41:14.339254 Model: Libre Computer AML-A311D-CC Alta
955 15:41:14.546764 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 15:41:14.570117 DRAM: 2 GiB (effective 3.8 GiB)
957 15:41:14.713148 Core: 408 devices, 31 uclasses, devicetree: separate
958 15:41:14.719051 WDT: Not starting watchdog@f0d0
959 15:41:14.751202 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 15:41:14.763669 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 15:41:14.768596 ** Bad device specification mmc 0 **
962 15:41:14.778976 Card did not respond to voltage select! : -110
963 15:41:14.786599 ** Bad device specification mmc 0 **
964 15:41:14.787124 Couldn't find partition mmc 0
965 15:41:14.794957 Card did not respond to voltage select! : -110
966 15:41:14.800490 ** Bad device specification mmc 0 **
967 15:41:14.800979 Couldn't find partition mmc 0
968 15:41:14.805522 Error: could not access storage.
969 15:41:15.148196 Net: eth0: ethernet@ff3f0000
970 15:41:15.148861 starting USB...
971 15:41:15.399832 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 15:41:15.400475 Starting the controller
973 15:41:15.406803 USB XHCI 1.10
974 15:41:16.960701 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
975 15:41:16.969063 scanning usb for storage devices... 0 Storage Device(s) found
977 15:41:17.020724 Hit any key to stop autoboot: 1
978 15:41:17.021737 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
979 15:41:17.022389 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
980 15:41:17.022913 Setting prompt string to ['=>']
981 15:41:17.023455 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
982 15:41:17.035528 0
983 15:41:17.036513 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
984 15:41:17.037068 Sending with 10 millisecond of delay
986 15:41:18.172499 => setenv autoload no
987 15:41:18.183342 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:28)
988 15:41:18.188331 setenv autoload no
989 15:41:18.189061 Sending with 10 millisecond of delay
991 15:41:19.987049 => setenv initrd_high 0xffffffff
992 15:41:19.997884 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
993 15:41:19.998573 setenv initrd_high 0xffffffff
994 15:41:19.999071 Sending with 10 millisecond of delay
996 15:41:21.615340 => setenv fdt_high 0xffffffff
997 15:41:21.626289 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
998 15:41:21.627282 setenv fdt_high 0xffffffff
999 15:41:21.628260 Sending with 10 millisecond of delay
1001 15:41:21.921615 => dhcp
1002 15:41:21.932460 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
1003 15:41:21.933598 dhcp
1004 15:41:21.934125 Speed: 1000, full duplex
1005 15:41:21.934587 BOOTP broadcast 1
1006 15:41:21.945400 DHCP client bound to address 192.168.6.27 (12 ms)
1007 15:41:21.946183 Sending with 10 millisecond of delay
1009 15:41:23.623836 => setenv serverip 192.168.6.2
1010 15:41:23.634679 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1011 15:41:23.635639 setenv serverip 192.168.6.2
1012 15:41:23.636422 Sending with 10 millisecond of delay
1014 15:41:27.364842 => tftpboot 0x01080000 934537/tftp-deploy-4un9sz67/kernel/uImage
1015 15:41:27.375846 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1016 15:41:27.377087 tftpboot 0x01080000 934537/tftp-deploy-4un9sz67/kernel/uImage
1017 15:41:27.377674 Speed: 1000, full duplex
1018 15:41:27.378514 Using ethernet@ff3f0000 device
1019 15:41:27.379479 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1020 15:41:27.384073 Filename '934537/tftp-deploy-4un9sz67/kernel/uImage'.
1021 15:41:27.387205 Load address: 0x1080000
1022 15:41:30.283507 Loading: *################################################## 43.6 MiB
1023 15:41:30.283905 15 MiB/s
1024 15:41:30.284172 done
1025 15:41:30.287726 Bytes transferred = 45713984 (2b98a40 hex)
1026 15:41:30.288341 Sending with 10 millisecond of delay
1028 15:41:34.980543 => tftpboot 0x08000000 934537/tftp-deploy-4un9sz67/ramdisk/ramdisk.cpio.gz.uboot
1029 15:41:34.991137 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
1030 15:41:34.991758 tftpboot 0x08000000 934537/tftp-deploy-4un9sz67/ramdisk/ramdisk.cpio.gz.uboot
1031 15:41:34.992075 Speed: 1000, full duplex
1032 15:41:34.992325 Using ethernet@ff3f0000 device
1033 15:41:34.993832 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1034 15:41:35.004862 Filename '934537/tftp-deploy-4un9sz67/ramdisk/ramdisk.cpio.gz.uboot'.
1035 15:41:35.005270 Load address: 0x8000000
1036 15:41:35.008814 Loading: * UDP wrong checksum 000000ff 0000c168
1037 15:41:41.774081 #############T #################################### UDP wrong checksum 00000005 0000300c
1038 15:41:46.774732 T UDP wrong checksum 00000005 0000300c
1039 15:41:56.776548 T T UDP wrong checksum 00000005 0000300c
1040 15:42:16.781117 T T T UDP wrong checksum 00000005 0000300c
1041 15:42:28.441753 T T T UDP wrong checksum 000000ff 0000916e
1042 15:42:28.456669 UDP wrong checksum 000000ff 00002761
1043 15:42:31.786956
1044 15:42:31.787344 Retry count exceeded; starting again
1046 15:42:31.788386 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1049 15:42:31.789571 end: 2.4 uboot-commands (duration 00:01:46) [common]
1051 15:42:31.790290 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1053 15:42:31.790836 end: 2 uboot-action (duration 00:01:46) [common]
1055 15:42:31.791672 Cleaning after the job
1056 15:42:31.792005 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/934537/tftp-deploy-4un9sz67/ramdisk
1057 15:42:31.792810 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/934537/tftp-deploy-4un9sz67/kernel
1058 15:42:31.807826 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/934537/tftp-deploy-4un9sz67/dtb
1059 15:42:31.808954 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/934537/tftp-deploy-4un9sz67/nfsrootfs
1060 15:42:31.859819 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/934537/tftp-deploy-4un9sz67/modules
1061 15:42:31.881796 start: 4.1 power-off (timeout 00:00:30) [common]
1062 15:42:31.882485 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1063 15:42:31.916307 >> OK - accepted request
1064 15:42:31.918639 Returned 0 in 0 seconds
1065 15:42:32.019472 end: 4.1 power-off (duration 00:00:00) [common]
1067 15:42:32.020523 start: 4.2 read-feedback (timeout 00:10:00) [common]
1068 15:42:32.021186 Listened to connection for namespace 'common' for up to 1s
1069 15:42:33.021271 Finalising connection for namespace 'common'
1070 15:42:33.021964 Disconnecting from shell: Finalise
1071 15:42:33.022493 =>
1072 15:42:33.123479 end: 4.2 read-feedback (duration 00:00:01) [common]
1073 15:42:33.124190 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/934537
1074 15:42:36.245503 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/934537
1075 15:42:36.246125 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.