Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 15:50:46.505449 lava-dispatcher, installed at version: 2024.01
2 15:50:46.506238 start: 0 validate
3 15:50:46.506713 Start time: 2024-11-04 15:50:46.506682+00:00 (UTC)
4 15:50:46.507279 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 15:50:46.507832 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 15:50:46.547717 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 15:50:46.548324 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-regulator%2Ffor-linus%2Fv6.12-rc3-2-g5e53e4a66bc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 15:50:46.579084 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 15:50:46.579755 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-regulator%2Ffor-linus%2Fv6.12-rc3-2-g5e53e4a66bc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 15:50:46.609666 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 15:50:46.610194 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 15:50:46.645164 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 15:50:46.645681 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-regulator%2Ffor-linus%2Fv6.12-rc3-2-g5e53e4a66bc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 15:50:46.684492 validate duration: 0.18
16 15:50:46.685417 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 15:50:46.685760 start: 1.1 download-retry (timeout 00:10:00) [common]
18 15:50:46.686098 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 15:50:46.686705 Not decompressing ramdisk as can be used compressed.
20 15:50:46.687134 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 15:50:46.687430 saving as /var/lib/lava/dispatcher/tmp/934590/tftp-deploy-lokjrqhw/ramdisk/initrd.cpio.gz
22 15:50:46.687706 total size: 5628140 (5 MB)
23 15:50:46.725037 progress 0 % (0 MB)
24 15:50:46.732453 progress 5 % (0 MB)
25 15:50:46.740606 progress 10 % (0 MB)
26 15:50:46.744634 progress 15 % (0 MB)
27 15:50:46.749042 progress 20 % (1 MB)
28 15:50:46.753058 progress 25 % (1 MB)
29 15:50:46.757409 progress 30 % (1 MB)
30 15:50:46.761823 progress 35 % (1 MB)
31 15:50:46.765776 progress 40 % (2 MB)
32 15:50:46.770123 progress 45 % (2 MB)
33 15:50:46.774009 progress 50 % (2 MB)
34 15:50:46.778336 progress 55 % (2 MB)
35 15:50:46.782539 progress 60 % (3 MB)
36 15:50:46.786307 progress 65 % (3 MB)
37 15:50:46.790559 progress 70 % (3 MB)
38 15:50:46.794337 progress 75 % (4 MB)
39 15:50:46.798405 progress 80 % (4 MB)
40 15:50:46.802080 progress 85 % (4 MB)
41 15:50:46.806225 progress 90 % (4 MB)
42 15:50:46.810260 progress 95 % (5 MB)
43 15:50:46.813716 progress 100 % (5 MB)
44 15:50:46.814446 5 MB downloaded in 0.13 s (42.36 MB/s)
45 15:50:46.815036 end: 1.1.1 http-download (duration 00:00:00) [common]
47 15:50:46.815996 end: 1.1 download-retry (duration 00:00:00) [common]
48 15:50:46.816337 start: 1.2 download-retry (timeout 00:10:00) [common]
49 15:50:46.816635 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 15:50:46.817140 downloading http://storage.kernelci.org/broonie-regulator/for-linus/v6.12-rc3-2-g5e53e4a66bc7/arm64/defconfig/gcc-12/kernel/Image
51 15:50:46.817405 saving as /var/lib/lava/dispatcher/tmp/934590/tftp-deploy-lokjrqhw/kernel/Image
52 15:50:46.817632 total size: 45713920 (43 MB)
53 15:50:46.817864 No compression specified
54 15:50:46.852369 progress 0 % (0 MB)
55 15:50:46.889043 progress 5 % (2 MB)
56 15:50:46.921840 progress 10 % (4 MB)
57 15:50:46.951022 progress 15 % (6 MB)
58 15:50:46.980121 progress 20 % (8 MB)
59 15:50:47.009070 progress 25 % (10 MB)
60 15:50:47.038117 progress 30 % (13 MB)
61 15:50:47.067354 progress 35 % (15 MB)
62 15:50:47.096375 progress 40 % (17 MB)
63 15:50:47.125000 progress 45 % (19 MB)
64 15:50:47.154357 progress 50 % (21 MB)
65 15:50:47.183428 progress 55 % (24 MB)
66 15:50:47.213613 progress 60 % (26 MB)
67 15:50:47.242665 progress 65 % (28 MB)
68 15:50:47.271583 progress 70 % (30 MB)
69 15:50:47.300996 progress 75 % (32 MB)
70 15:50:47.330151 progress 80 % (34 MB)
71 15:50:47.359007 progress 85 % (37 MB)
72 15:50:47.387731 progress 90 % (39 MB)
73 15:50:47.416350 progress 95 % (41 MB)
74 15:50:47.445191 progress 100 % (43 MB)
75 15:50:47.445773 43 MB downloaded in 0.63 s (69.41 MB/s)
76 15:50:47.446275 end: 1.2.1 http-download (duration 00:00:01) [common]
78 15:50:47.447136 end: 1.2 download-retry (duration 00:00:01) [common]
79 15:50:47.447440 start: 1.3 download-retry (timeout 00:09:59) [common]
80 15:50:47.447726 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 15:50:47.448220 downloading http://storage.kernelci.org/broonie-regulator/for-linus/v6.12-rc3-2-g5e53e4a66bc7/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 15:50:47.448515 saving as /var/lib/lava/dispatcher/tmp/934590/tftp-deploy-lokjrqhw/dtb/meson-g12b-a311d-libretech-cc.dtb
83 15:50:47.448738 total size: 54703 (0 MB)
84 15:50:47.448957 No compression specified
85 15:50:47.488993 progress 59 % (0 MB)
86 15:50:47.489846 progress 100 % (0 MB)
87 15:50:47.490426 0 MB downloaded in 0.04 s (1.25 MB/s)
88 15:50:47.490908 end: 1.3.1 http-download (duration 00:00:00) [common]
90 15:50:47.491762 end: 1.3 download-retry (duration 00:00:00) [common]
91 15:50:47.492074 start: 1.4 download-retry (timeout 00:09:59) [common]
92 15:50:47.492370 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 15:50:47.492837 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 15:50:47.493090 saving as /var/lib/lava/dispatcher/tmp/934590/tftp-deploy-lokjrqhw/nfsrootfs/full.rootfs.tar
95 15:50:47.493307 total size: 474398908 (452 MB)
96 15:50:47.493527 Using unxz to decompress xz
97 15:50:47.531827 progress 0 % (0 MB)
98 15:50:48.673108 progress 5 % (22 MB)
99 15:50:50.146155 progress 10 % (45 MB)
100 15:50:50.582085 progress 15 % (67 MB)
101 15:50:51.350393 progress 20 % (90 MB)
102 15:50:51.874788 progress 25 % (113 MB)
103 15:50:52.234318 progress 30 % (135 MB)
104 15:50:52.845616 progress 35 % (158 MB)
105 15:50:53.710067 progress 40 % (181 MB)
106 15:50:54.433366 progress 45 % (203 MB)
107 15:50:54.977779 progress 50 % (226 MB)
108 15:50:55.608502 progress 55 % (248 MB)
109 15:50:56.828289 progress 60 % (271 MB)
110 15:50:58.313029 progress 65 % (294 MB)
111 15:50:59.939860 progress 70 % (316 MB)
112 15:51:03.021489 progress 75 % (339 MB)
113 15:51:05.454076 progress 80 % (361 MB)
114 15:51:08.314672 progress 85 % (384 MB)
115 15:51:11.440285 progress 90 % (407 MB)
116 15:51:14.621440 progress 95 % (429 MB)
117 15:51:17.778252 progress 100 % (452 MB)
118 15:51:17.791421 452 MB downloaded in 30.30 s (14.93 MB/s)
119 15:51:17.792334 end: 1.4.1 http-download (duration 00:00:30) [common]
121 15:51:17.793941 end: 1.4 download-retry (duration 00:00:30) [common]
122 15:51:17.794452 start: 1.5 download-retry (timeout 00:09:29) [common]
123 15:51:17.794958 start: 1.5.1 http-download (timeout 00:09:29) [common]
124 15:51:17.796886 downloading http://storage.kernelci.org/broonie-regulator/for-linus/v6.12-rc3-2-g5e53e4a66bc7/arm64/defconfig/gcc-12/modules.tar.xz
125 15:51:17.797410 saving as /var/lib/lava/dispatcher/tmp/934590/tftp-deploy-lokjrqhw/modules/modules.tar
126 15:51:17.797853 total size: 11613116 (11 MB)
127 15:51:17.798306 Using unxz to decompress xz
128 15:51:17.841462 progress 0 % (0 MB)
129 15:51:17.920022 progress 5 % (0 MB)
130 15:51:18.008275 progress 10 % (1 MB)
131 15:51:18.106191 progress 15 % (1 MB)
132 15:51:18.198154 progress 20 % (2 MB)
133 15:51:18.277466 progress 25 % (2 MB)
134 15:51:18.352549 progress 30 % (3 MB)
135 15:51:18.431925 progress 35 % (3 MB)
136 15:51:18.505588 progress 40 % (4 MB)
137 15:51:18.581659 progress 45 % (5 MB)
138 15:51:18.665315 progress 50 % (5 MB)
139 15:51:18.743152 progress 55 % (6 MB)
140 15:51:18.827792 progress 60 % (6 MB)
141 15:51:18.908370 progress 65 % (7 MB)
142 15:51:18.988534 progress 70 % (7 MB)
143 15:51:19.066897 progress 75 % (8 MB)
144 15:51:19.151189 progress 80 % (8 MB)
145 15:51:19.231013 progress 85 % (9 MB)
146 15:51:19.309326 progress 90 % (9 MB)
147 15:51:19.386786 progress 95 % (10 MB)
148 15:51:19.463210 progress 100 % (11 MB)
149 15:51:19.475563 11 MB downloaded in 1.68 s (6.60 MB/s)
150 15:51:19.476319 end: 1.5.1 http-download (duration 00:00:02) [common]
152 15:51:19.478020 end: 1.5 download-retry (duration 00:00:02) [common]
153 15:51:19.478550 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 15:51:19.479071 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 15:51:34.664827 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/934590/extract-nfsrootfs-61vtym74
156 15:51:34.665427 end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
157 15:51:34.665716 start: 1.6.2 lava-overlay (timeout 00:09:12) [common]
158 15:51:34.666490 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells
159 15:51:34.666969 makedir: /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin
160 15:51:34.667296 makedir: /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/tests
161 15:51:34.667615 makedir: /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/results
162 15:51:34.667952 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-add-keys
163 15:51:34.668524 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-add-sources
164 15:51:34.669031 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-background-process-start
165 15:51:34.669527 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-background-process-stop
166 15:51:34.670044 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-common-functions
167 15:51:34.670551 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-echo-ipv4
168 15:51:34.671065 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-install-packages
169 15:51:34.671605 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-installed-packages
170 15:51:34.672120 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-os-build
171 15:51:34.672606 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-probe-channel
172 15:51:34.673081 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-probe-ip
173 15:51:34.673548 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-target-ip
174 15:51:34.674009 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-target-mac
175 15:51:34.674560 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-target-storage
176 15:51:34.675079 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-test-case
177 15:51:34.675564 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-test-event
178 15:51:34.676054 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-test-feedback
179 15:51:34.676540 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-test-raise
180 15:51:34.677010 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-test-reference
181 15:51:34.677485 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-test-runner
182 15:51:34.677968 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-test-set
183 15:51:34.678456 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-test-shell
184 15:51:34.678954 Updating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-install-packages (oe)
185 15:51:34.679489 Updating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/bin/lava-installed-packages (oe)
186 15:51:34.679924 Creating /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/environment
187 15:51:34.680337 LAVA metadata
188 15:51:34.680602 - LAVA_JOB_ID=934590
189 15:51:34.680820 - LAVA_DISPATCHER_IP=192.168.6.2
190 15:51:34.681172 start: 1.6.2.1 ssh-authorize (timeout 00:09:12) [common]
191 15:51:34.682104 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 15:51:34.682411 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:12) [common]
193 15:51:34.682620 skipped lava-vland-overlay
194 15:51:34.682861 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 15:51:34.683137 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:12) [common]
196 15:51:34.683358 skipped lava-multinode-overlay
197 15:51:34.683599 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 15:51:34.683851 start: 1.6.2.4 test-definition (timeout 00:09:12) [common]
199 15:51:34.684147 Loading test definitions
200 15:51:34.684427 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:12) [common]
201 15:51:34.684650 Using /lava-934590 at stage 0
202 15:51:34.685797 uuid=934590_1.6.2.4.1 testdef=None
203 15:51:34.686094 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 15:51:34.686358 start: 1.6.2.4.2 test-overlay (timeout 00:09:12) [common]
205 15:51:34.688093 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 15:51:34.688938 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:12) [common]
208 15:51:34.691056 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 15:51:34.691884 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:12) [common]
211 15:51:34.693942 runner path: /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/0/tests/0_v4l2-decoder-conformance-h265 test_uuid 934590_1.6.2.4.1
212 15:51:34.694492 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 15:51:34.695256 Creating lava-test-runner.conf files
215 15:51:34.695457 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/934590/lava-overlay-v22uells/lava-934590/0 for stage 0
216 15:51:34.695786 - 0_v4l2-decoder-conformance-h265
217 15:51:34.696143 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 15:51:34.696419 start: 1.6.2.5 compress-overlay (timeout 00:09:12) [common]
219 15:51:34.717510 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 15:51:34.717850 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:12) [common]
221 15:51:34.718107 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 15:51:34.718368 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 15:51:34.718631 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:12) [common]
224 15:51:35.380358 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 15:51:35.380820 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
226 15:51:35.381071 extracting modules file /var/lib/lava/dispatcher/tmp/934590/tftp-deploy-lokjrqhw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/934590/extract-nfsrootfs-61vtym74
227 15:51:36.733911 extracting modules file /var/lib/lava/dispatcher/tmp/934590/tftp-deploy-lokjrqhw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/934590/extract-overlay-ramdisk-awyh88p0/ramdisk
228 15:51:38.165538 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 15:51:38.166022 start: 1.6.5 apply-overlay-tftp (timeout 00:09:09) [common]
230 15:51:38.166298 [common] Applying overlay to NFS
231 15:51:38.166514 [common] Applying overlay /var/lib/lava/dispatcher/tmp/934590/compress-overlay-sokq0c6o/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/934590/extract-nfsrootfs-61vtym74
232 15:51:38.196399 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 15:51:38.196810 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
234 15:51:38.197082 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
235 15:51:38.197311 Converting downloaded kernel to a uImage
236 15:51:38.197628 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/934590/tftp-deploy-lokjrqhw/kernel/Image /var/lib/lava/dispatcher/tmp/934590/tftp-deploy-lokjrqhw/kernel/uImage
237 15:51:38.662189 output: Image Name:
238 15:51:38.662603 output: Created: Mon Nov 4 15:51:38 2024
239 15:51:38.662815 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 15:51:38.663020 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 15:51:38.663221 output: Load Address: 01080000
242 15:51:38.663420 output: Entry Point: 01080000
243 15:51:38.663617 output:
244 15:51:38.663948 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 15:51:38.664260 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 15:51:38.664536 start: 1.6.7 configure-preseed-file (timeout 00:09:08) [common]
247 15:51:38.664790 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 15:51:38.665049 start: 1.6.8 compress-ramdisk (timeout 00:09:08) [common]
249 15:51:38.665315 Building ramdisk /var/lib/lava/dispatcher/tmp/934590/extract-overlay-ramdisk-awyh88p0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/934590/extract-overlay-ramdisk-awyh88p0/ramdisk
250 15:51:41.174143 >> 166779 blocks
251 15:51:48.876018 Adding RAMdisk u-boot header.
252 15:51:48.876657 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/934590/extract-overlay-ramdisk-awyh88p0/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/934590/extract-overlay-ramdisk-awyh88p0/ramdisk.cpio.gz.uboot
253 15:51:49.136027 output: Image Name:
254 15:51:49.136670 output: Created: Mon Nov 4 15:51:48 2024
255 15:51:49.137093 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 15:51:49.137500 output: Data Size: 23425915 Bytes = 22876.87 KiB = 22.34 MiB
257 15:51:49.137899 output: Load Address: 00000000
258 15:51:49.138293 output: Entry Point: 00000000
259 15:51:49.138683 output:
260 15:51:49.139741 rename /var/lib/lava/dispatcher/tmp/934590/extract-overlay-ramdisk-awyh88p0/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/934590/tftp-deploy-lokjrqhw/ramdisk/ramdisk.cpio.gz.uboot
261 15:51:49.140492 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 15:51:49.141040 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 15:51:49.141566 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:58) [common]
264 15:51:49.142035 No LXC device requested
265 15:51:49.142540 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 15:51:49.143050 start: 1.8 deploy-device-env (timeout 00:08:58) [common]
267 15:51:49.143542 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 15:51:49.143953 Checking files for TFTP limit of 4294967296 bytes.
269 15:51:49.146629 end: 1 tftp-deploy (duration 00:01:02) [common]
270 15:51:49.147211 start: 2 uboot-action (timeout 00:05:00) [common]
271 15:51:49.147733 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 15:51:49.148264 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 15:51:49.148768 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 15:51:49.149296 Using kernel file from prepare-kernel: 934590/tftp-deploy-lokjrqhw/kernel/uImage
275 15:51:49.149998 substitutions:
276 15:51:49.150435 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 15:51:49.150847 - {DTB_ADDR}: 0x01070000
278 15:51:49.151253 - {DTB}: 934590/tftp-deploy-lokjrqhw/dtb/meson-g12b-a311d-libretech-cc.dtb
279 15:51:49.151658 - {INITRD}: 934590/tftp-deploy-lokjrqhw/ramdisk/ramdisk.cpio.gz.uboot
280 15:51:49.152109 - {KERNEL_ADDR}: 0x01080000
281 15:51:49.152527 - {KERNEL}: 934590/tftp-deploy-lokjrqhw/kernel/uImage
282 15:51:49.152929 - {LAVA_MAC}: None
283 15:51:49.153375 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/934590/extract-nfsrootfs-61vtym74
284 15:51:49.153783 - {NFS_SERVER_IP}: 192.168.6.2
285 15:51:49.154178 - {PRESEED_CONFIG}: None
286 15:51:49.154574 - {PRESEED_LOCAL}: None
287 15:51:49.154970 - {RAMDISK_ADDR}: 0x08000000
288 15:51:49.155363 - {RAMDISK}: 934590/tftp-deploy-lokjrqhw/ramdisk/ramdisk.cpio.gz.uboot
289 15:51:49.155759 - {ROOT_PART}: None
290 15:51:49.156248 - {ROOT}: None
291 15:51:49.156676 - {SERVER_IP}: 192.168.6.2
292 15:51:49.157077 - {TEE_ADDR}: 0x83000000
293 15:51:49.157476 - {TEE}: None
294 15:51:49.157873 Parsed boot commands:
295 15:51:49.158263 - setenv autoload no
296 15:51:49.158657 - setenv initrd_high 0xffffffff
297 15:51:49.159048 - setenv fdt_high 0xffffffff
298 15:51:49.159442 - dhcp
299 15:51:49.159834 - setenv serverip 192.168.6.2
300 15:51:49.160263 - tftpboot 0x01080000 934590/tftp-deploy-lokjrqhw/kernel/uImage
301 15:51:49.160664 - tftpboot 0x08000000 934590/tftp-deploy-lokjrqhw/ramdisk/ramdisk.cpio.gz.uboot
302 15:51:49.161059 - tftpboot 0x01070000 934590/tftp-deploy-lokjrqhw/dtb/meson-g12b-a311d-libretech-cc.dtb
303 15:51:49.161455 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/934590/extract-nfsrootfs-61vtym74,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 15:51:49.161863 - bootm 0x01080000 0x08000000 0x01070000
305 15:51:49.162386 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 15:51:49.163900 start: 2.3 connect-device (timeout 00:05:00) [common]
308 15:51:49.164367 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 15:51:49.178231 Setting prompt string to ['lava-test: # ']
310 15:51:49.179830 end: 2.3 connect-device (duration 00:00:00) [common]
311 15:51:49.180498 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 15:51:49.181352 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 15:51:49.181973 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 15:51:49.183133 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 15:51:49.223663 >> OK - accepted request
316 15:51:49.225915 Returned 0 in 0 seconds
317 15:51:49.327003 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 15:51:49.328747 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 15:51:49.329352 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 15:51:49.329887 Setting prompt string to ['Hit any key to stop autoboot']
322 15:51:49.330363 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 15:51:49.331939 Trying 192.168.56.21...
324 15:51:49.332546 Connected to conserv1.
325 15:51:49.333008 Escape character is '^]'.
326 15:51:49.333438
327 15:51:49.333903 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 15:51:49.334367
329 15:52:01.441023 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 15:52:01.441657 bl2_stage_init 0x01
331 15:52:01.442148 bl2_stage_init 0x81
332 15:52:01.446692 hw id: 0x0000 - pwm id 0x01
333 15:52:01.447241 bl2_stage_init 0xc1
334 15:52:01.447697 bl2_stage_init 0x02
335 15:52:01.448185
336 15:52:01.452209 L0:00000000
337 15:52:01.452697 L1:20000703
338 15:52:01.453126 L2:00008067
339 15:52:01.453549 L3:14000000
340 15:52:01.457783 B2:00402000
341 15:52:01.458249 B1:e0f83180
342 15:52:01.458676
343 15:52:01.459102 TE: 58124
344 15:52:01.459527
345 15:52:01.463367 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 15:52:01.463841
347 15:52:01.464304 Board ID = 1
348 15:52:01.468956 Set A53 clk to 24M
349 15:52:01.469420 Set A73 clk to 24M
350 15:52:01.469844 Set clk81 to 24M
351 15:52:01.474477 A53 clk: 1200 MHz
352 15:52:01.474941 A73 clk: 1200 MHz
353 15:52:01.475365 CLK81: 166.6M
354 15:52:01.475789 smccc: 00012a92
355 15:52:01.480180 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 15:52:01.485725 board id: 1
357 15:52:01.491691 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 15:52:01.502359 fw parse done
359 15:52:01.508364 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 15:52:01.549901 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 15:52:01.561714 PIEI prepare done
362 15:52:01.562203 fastboot data load
363 15:52:01.562645 fastboot data verify
364 15:52:01.567379 verify result: 266
365 15:52:01.572922 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 15:52:01.573406 LPDDR4 probe
367 15:52:01.573855 ddr clk to 1584MHz
368 15:52:01.580867 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 15:52:01.618264
370 15:52:01.618801 dmc_version 0001
371 15:52:01.624861 Check phy result
372 15:52:01.630707 INFO : End of CA training
373 15:52:01.631178 INFO : End of initialization
374 15:52:01.636294 INFO : Training has run successfully!
375 15:52:01.636761 Check phy result
376 15:52:01.641924 INFO : End of initialization
377 15:52:01.642393 INFO : End of read enable training
378 15:52:01.645210 INFO : End of fine write leveling
379 15:52:01.650735 INFO : End of Write leveling coarse delay
380 15:52:01.656331 INFO : Training has run successfully!
381 15:52:01.656802 Check phy result
382 15:52:01.657244 INFO : End of initialization
383 15:52:01.661927 INFO : End of read dq deskew training
384 15:52:01.667532 INFO : End of MPR read delay center optimization
385 15:52:01.668060 INFO : End of write delay center optimization
386 15:52:01.673186 INFO : End of read delay center optimization
387 15:52:01.678737 INFO : End of max read latency training
388 15:52:01.679205 INFO : Training has run successfully!
389 15:52:01.684342 1D training succeed
390 15:52:01.690330 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 15:52:01.737903 Check phy result
392 15:52:01.738406 INFO : End of initialization
393 15:52:01.759689 INFO : End of 2D read delay Voltage center optimization
394 15:52:01.779923 INFO : End of 2D read delay Voltage center optimization
395 15:52:01.831912 INFO : End of 2D write delay Voltage center optimization
396 15:52:01.881414 INFO : End of 2D write delay Voltage center optimization
397 15:52:01.886861 INFO : Training has run successfully!
398 15:52:01.887335
399 15:52:01.887786 channel==0
400 15:52:01.892495 RxClkDly_Margin_A0==78 ps 8
401 15:52:01.892963 TxDqDly_Margin_A0==98 ps 10
402 15:52:01.898092 RxClkDly_Margin_A1==88 ps 9
403 15:52:01.898570 TxDqDly_Margin_A1==88 ps 9
404 15:52:01.899016 TrainedVREFDQ_A0==74
405 15:52:01.903687 TrainedVREFDQ_A1==74
406 15:52:01.904200 VrefDac_Margin_A0==25
407 15:52:01.904644 DeviceVref_Margin_A0==40
408 15:52:01.909260 VrefDac_Margin_A1==25
409 15:52:01.909719 DeviceVref_Margin_A1==40
410 15:52:01.910158
411 15:52:01.910591
412 15:52:01.911023 channel==1
413 15:52:01.914856 RxClkDly_Margin_A0==98 ps 10
414 15:52:01.915325 TxDqDly_Margin_A0==98 ps 10
415 15:52:01.920456 RxClkDly_Margin_A1==88 ps 9
416 15:52:01.920923 TxDqDly_Margin_A1==88 ps 9
417 15:52:01.926023 TrainedVREFDQ_A0==77
418 15:52:01.926489 TrainedVREFDQ_A1==77
419 15:52:01.926932 VrefDac_Margin_A0==22
420 15:52:01.931656 DeviceVref_Margin_A0==37
421 15:52:01.932148 VrefDac_Margin_A1==24
422 15:52:01.937248 DeviceVref_Margin_A1==37
423 15:52:01.937710
424 15:52:01.938152 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 15:52:01.938590
426 15:52:01.970863 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 15:52:01.971422 2D training succeed
428 15:52:01.976451 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 15:52:01.982032 auto size-- 65535DDR cs0 size: 2048MB
430 15:52:01.982503 DDR cs1 size: 2048MB
431 15:52:01.987616 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 15:52:01.988114 cs0 DataBus test pass
433 15:52:01.993256 cs1 DataBus test pass
434 15:52:01.993722 cs0 AddrBus test pass
435 15:52:01.994165 cs1 AddrBus test pass
436 15:52:01.994598
437 15:52:01.998870 100bdlr_step_size ps== 420
438 15:52:01.999343 result report
439 15:52:02.004426 boot times 0Enable ddr reg access
440 15:52:02.009707 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 15:52:02.023298 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 15:52:02.596878 0.0;M3 CHK:0;cm4_sp_mode 0
443 15:52:02.597507 MVN_1=0x00000000
444 15:52:02.602598 MVN_2=0x00000000
445 15:52:02.608273 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 15:52:02.608749 OPS=0x10
447 15:52:02.609194 ring efuse init
448 15:52:02.609630 chipver efuse init
449 15:52:02.616405 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 15:52:02.616963 [0.018961 Inits done]
451 15:52:02.623937 secure task start!
452 15:52:02.624463 high task start!
453 15:52:02.624918 low task start!
454 15:52:02.625363 run into bl31
455 15:52:02.630638 NOTICE: BL31: v1.3(release):4fc40b1
456 15:52:02.638377 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 15:52:02.638863 NOTICE: BL31: G12A normal boot!
458 15:52:02.663748 NOTICE: BL31: BL33 decompress pass
459 15:52:02.669417 ERROR: Error initializing runtime service opteed_fast
460 15:52:03.902440
461 15:52:03.903108
462 15:52:03.910733 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 15:52:03.911222
464 15:52:03.911675 Model: Libre Computer AML-A311D-CC Alta
465 15:52:04.119229 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 15:52:04.142617 DRAM: 2 GiB (effective 3.8 GiB)
467 15:52:04.285732 Core: 408 devices, 31 uclasses, devicetree: separate
468 15:52:04.291510 WDT: Not starting watchdog@f0d0
469 15:52:04.323747 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 15:52:04.336192 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 15:52:04.341157 ** Bad device specification mmc 0 **
472 15:52:04.351620 Card did not respond to voltage select! : -110
473 15:52:04.359160 ** Bad device specification mmc 0 **
474 15:52:04.359663 Couldn't find partition mmc 0
475 15:52:04.367630 Card did not respond to voltage select! : -110
476 15:52:04.372990 ** Bad device specification mmc 0 **
477 15:52:04.373497 Couldn't find partition mmc 0
478 15:52:04.378066 Error: could not access storage.
479 15:52:05.641341 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 15:52:05.641967 bl2_stage_init 0x01
481 15:52:05.642427 bl2_stage_init 0x81
482 15:52:05.646964 hw id: 0x0000 - pwm id 0x01
483 15:52:05.647483 bl2_stage_init 0xc1
484 15:52:05.647936 bl2_stage_init 0x02
485 15:52:05.648432
486 15:52:05.652538 L0:00000000
487 15:52:05.653033 L1:20000703
488 15:52:05.653478 L2:00008067
489 15:52:05.653917 L3:14000000
490 15:52:05.658156 B2:00402000
491 15:52:05.658657 B1:e0f83180
492 15:52:05.659101
493 15:52:05.659536 TE: 58167
494 15:52:05.659973
495 15:52:05.663798 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 15:52:05.664325
497 15:52:05.664777 Board ID = 1
498 15:52:05.669353 Set A53 clk to 24M
499 15:52:05.669849 Set A73 clk to 24M
500 15:52:05.670295 Set clk81 to 24M
501 15:52:05.674896 A53 clk: 1200 MHz
502 15:52:05.675447 A73 clk: 1200 MHz
503 15:52:05.675932 CLK81: 166.6M
504 15:52:05.676438 smccc: 00012abe
505 15:52:05.680499 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 15:52:05.686091 board id: 1
507 15:52:05.692015 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 15:52:05.702767 fw parse done
509 15:52:05.708613 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 15:52:05.751223 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 15:52:05.762166 PIEI prepare done
512 15:52:05.762703 fastboot data load
513 15:52:05.763157 fastboot data verify
514 15:52:05.767846 verify result: 266
515 15:52:05.773415 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 15:52:05.773932 LPDDR4 probe
517 15:52:05.774385 ddr clk to 1584MHz
518 15:52:05.781379 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 15:52:05.818735
520 15:52:05.819313 dmc_version 0001
521 15:52:05.825353 Check phy result
522 15:52:05.831172 INFO : End of CA training
523 15:52:05.831676 INFO : End of initialization
524 15:52:05.836809 INFO : Training has run successfully!
525 15:52:05.837318 Check phy result
526 15:52:05.842383 INFO : End of initialization
527 15:52:05.842888 INFO : End of read enable training
528 15:52:05.848026 INFO : End of fine write leveling
529 15:52:05.853626 INFO : End of Write leveling coarse delay
530 15:52:05.854166 INFO : Training has run successfully!
531 15:52:05.854615 Check phy result
532 15:52:05.859172 INFO : End of initialization
533 15:52:05.859687 INFO : End of read dq deskew training
534 15:52:05.864861 INFO : End of MPR read delay center optimization
535 15:52:05.870387 INFO : End of write delay center optimization
536 15:52:05.876018 INFO : End of read delay center optimization
537 15:52:05.876527 INFO : End of max read latency training
538 15:52:05.881592 INFO : Training has run successfully!
539 15:52:05.882084 1D training succeed
540 15:52:05.890661 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 15:52:05.938308 Check phy result
542 15:52:05.938882 INFO : End of initialization
543 15:52:05.959952 INFO : End of 2D read delay Voltage center optimization
544 15:52:05.980133 INFO : End of 2D read delay Voltage center optimization
545 15:52:06.031152 INFO : End of 2D write delay Voltage center optimization
546 15:52:06.081236 INFO : End of 2D write delay Voltage center optimization
547 15:52:06.086870 INFO : Training has run successfully!
548 15:52:06.087386
549 15:52:06.087836 channel==0
550 15:52:06.092392 RxClkDly_Margin_A0==88 ps 9
551 15:52:06.092896 TxDqDly_Margin_A0==98 ps 10
552 15:52:06.098018 RxClkDly_Margin_A1==88 ps 9
553 15:52:06.098525 TxDqDly_Margin_A1==98 ps 10
554 15:52:06.098979 TrainedVREFDQ_A0==74
555 15:52:06.103635 TrainedVREFDQ_A1==74
556 15:52:06.104181 VrefDac_Margin_A0==25
557 15:52:06.104630 DeviceVref_Margin_A0==40
558 15:52:06.109191 VrefDac_Margin_A1==25
559 15:52:06.109688 DeviceVref_Margin_A1==40
560 15:52:06.110124
561 15:52:06.110559
562 15:52:06.114846 channel==1
563 15:52:06.115340 RxClkDly_Margin_A0==98 ps 10
564 15:52:06.115802 TxDqDly_Margin_A0==98 ps 10
565 15:52:06.120424 RxClkDly_Margin_A1==98 ps 10
566 15:52:06.120934 TxDqDly_Margin_A1==88 ps 9
567 15:52:06.126011 TrainedVREFDQ_A0==77
568 15:52:06.126527 TrainedVREFDQ_A1==77
569 15:52:06.126975 VrefDac_Margin_A0==22
570 15:52:06.131618 DeviceVref_Margin_A0==37
571 15:52:06.132175 VrefDac_Margin_A1==22
572 15:52:06.137210 DeviceVref_Margin_A1==37
573 15:52:06.137713
574 15:52:06.138154 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 15:52:06.142870
576 15:52:06.170827 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000016 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
577 15:52:06.171396 2D training succeed
578 15:52:06.176388 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 15:52:06.181968 auto size-- 65535DDR cs0 size: 2048MB
580 15:52:06.182478 DDR cs1 size: 2048MB
581 15:52:06.187637 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 15:52:06.188166 cs0 DataBus test pass
583 15:52:06.193131 cs1 DataBus test pass
584 15:52:06.193628 cs0 AddrBus test pass
585 15:52:06.194071 cs1 AddrBus test pass
586 15:52:06.194507
587 15:52:06.198908 100bdlr_step_size ps== 420
588 15:52:06.199446 result report
589 15:52:06.204435 boot times 0Enable ddr reg access
590 15:52:06.209733 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 15:52:06.223257 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 15:52:06.795330 0.0;M3 CHK:0;cm4_sp_mode 0
593 15:52:06.795973 MVN_1=0x00000000
594 15:52:06.801003 MVN_2=0x00000000
595 15:52:06.806709 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 15:52:06.807249 OPS=0x10
597 15:52:06.807713 ring efuse init
598 15:52:06.808222 chipver efuse init
599 15:52:06.812213 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 15:52:06.817781 [0.018961 Inits done]
601 15:52:06.818283 secure task start!
602 15:52:06.818716 high task start!
603 15:52:06.822421 low task start!
604 15:52:06.822908 run into bl31
605 15:52:06.829037 NOTICE: BL31: v1.3(release):4fc40b1
606 15:52:06.836949 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 15:52:06.837448 NOTICE: BL31: G12A normal boot!
608 15:52:06.862725 NOTICE: BL31: BL33 decompress pass
609 15:52:06.868344 ERROR: Error initializing runtime service opteed_fast
610 15:52:08.101277
611 15:52:08.101891
612 15:52:08.109707 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 15:52:08.110244
614 15:52:08.110699 Model: Libre Computer AML-A311D-CC Alta
615 15:52:08.317679 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 15:52:08.341546 DRAM: 2 GiB (effective 3.8 GiB)
617 15:52:08.484470 Core: 408 devices, 31 uclasses, devicetree: separate
618 15:52:08.490421 WDT: Not starting watchdog@f0d0
619 15:52:08.522667 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 15:52:08.535025 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 15:52:08.540164 ** Bad device specification mmc 0 **
622 15:52:08.550335 Card did not respond to voltage select! : -110
623 15:52:08.557397 ** Bad device specification mmc 0 **
624 15:52:08.557912 Couldn't find partition mmc 0
625 15:52:08.566312 Card did not respond to voltage select! : -110
626 15:52:08.571818 ** Bad device specification mmc 0 **
627 15:52:08.572373 Couldn't find partition mmc 0
628 15:52:08.576888 Error: could not access storage.
629 15:52:08.918730 Net: eth0: ethernet@ff3f0000
630 15:52:08.919123 starting USB...
631 15:52:09.171110 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 15:52:09.171482 Starting the controller
633 15:52:09.178203 USB XHCI 1.10
634 15:52:10.771558 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 15:52:10.772176 bl2_stage_init 0x01
636 15:52:10.772457 bl2_stage_init 0x81
637 15:52:10.777189 hw id: 0x0000 - pwm id 0x01
638 15:52:10.777526 bl2_stage_init 0xc1
639 15:52:10.777765 bl2_stage_init 0x02
640 15:52:10.777989
641 15:52:10.782765 L0:00000000
642 15:52:10.783212 L1:20000703
643 15:52:10.783755 L2:00008067
644 15:52:10.784267 L3:14000000
645 15:52:10.785691 B2:00402000
646 15:52:10.786169 B1:e0f83180
647 15:52:10.786619
648 15:52:10.787067 TE: 58167
649 15:52:10.787513
650 15:52:10.796891 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 15:52:10.797416
652 15:52:10.797878 Board ID = 1
653 15:52:10.798329 Set A53 clk to 24M
654 15:52:10.798772 Set A73 clk to 24M
655 15:52:10.802470 Set clk81 to 24M
656 15:52:10.802962 A53 clk: 1200 MHz
657 15:52:10.803437 A73 clk: 1200 MHz
658 15:52:10.808066 CLK81: 166.6M
659 15:52:10.808583 smccc: 00012abd
660 15:52:10.813635 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 15:52:10.814147 board id: 1
662 15:52:10.822185 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 15:52:10.832869 fw parse done
664 15:52:10.838814 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 15:52:10.881492 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 15:52:10.892264 PIEI prepare done
667 15:52:10.892787 fastboot data load
668 15:52:10.893250 fastboot data verify
669 15:52:10.897954 verify result: 266
670 15:52:10.903603 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 15:52:10.904270 LPDDR4 probe
672 15:52:10.904760 ddr clk to 1584MHz
673 15:52:10.911601 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 15:52:10.949042
675 15:52:10.949591 dmc_version 0001
676 15:52:10.955684 Check phy result
677 15:52:10.961515 INFO : End of CA training
678 15:52:10.962091 INFO : End of initialization
679 15:52:10.967113 INFO : Training has run successfully!
680 15:52:10.967682 Check phy result
681 15:52:10.972707 INFO : End of initialization
682 15:52:10.973266 INFO : End of read enable training
683 15:52:10.978329 INFO : End of fine write leveling
684 15:52:10.983855 INFO : End of Write leveling coarse delay
685 15:52:10.984467 INFO : Training has run successfully!
686 15:52:10.984939 Check phy result
687 15:52:10.989467 INFO : End of initialization
688 15:52:10.990012 INFO : End of read dq deskew training
689 15:52:10.995015 INFO : End of MPR read delay center optimization
690 15:52:11.000592 INFO : End of write delay center optimization
691 15:52:11.007544 INFO : End of read delay center optimization
692 15:52:11.008177 INFO : End of max read latency training
693 15:52:11.011925 INFO : Training has run successfully!
694 15:52:11.012507 1D training succeed
695 15:52:11.021009 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 15:52:11.068835 Check phy result
697 15:52:11.069434 INFO : End of initialization
698 15:52:11.089607 INFO : End of 2D read delay Voltage center optimization
699 15:52:11.110648 INFO : End of 2D read delay Voltage center optimization
700 15:52:11.162943 INFO : End of 2D write delay Voltage center optimization
701 15:52:11.212090 INFO : End of 2D write delay Voltage center optimization
702 15:52:11.217732 INFO : Training has run successfully!
703 15:52:11.218312
704 15:52:11.218784 channel==0
705 15:52:11.223228 RxClkDly_Margin_A0==88 ps 9
706 15:52:11.223795 TxDqDly_Margin_A0==98 ps 10
707 15:52:11.226510 RxClkDly_Margin_A1==88 ps 9
708 15:52:11.227078 TxDqDly_Margin_A1==98 ps 10
709 15:52:11.232028 TrainedVREFDQ_A0==74
710 15:52:11.232608 TrainedVREFDQ_A1==74
711 15:52:11.237713 VrefDac_Margin_A0==25
712 15:52:11.238276 DeviceVref_Margin_A0==40
713 15:52:11.238733 VrefDac_Margin_A1==23
714 15:52:11.243265 DeviceVref_Margin_A1==40
715 15:52:11.243835
716 15:52:11.244339
717 15:52:11.244790 channel==1
718 15:52:11.245233 RxClkDly_Margin_A0==98 ps 10
719 15:52:11.248870 TxDqDly_Margin_A0==88 ps 9
720 15:52:11.249434 RxClkDly_Margin_A1==88 ps 9
721 15:52:11.254421 TxDqDly_Margin_A1==88 ps 9
722 15:52:11.254964 TrainedVREFDQ_A0==76
723 15:52:11.255423 TrainedVREFDQ_A1==77
724 15:52:11.260048 VrefDac_Margin_A0==22
725 15:52:11.260577 DeviceVref_Margin_A0==38
726 15:52:11.265674 VrefDac_Margin_A1==24
727 15:52:11.266194 DeviceVref_Margin_A1==37
728 15:52:11.266648
729 15:52:11.271156 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 15:52:11.271691
731 15:52:11.299119 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
732 15:52:11.304778 2D training succeed
733 15:52:11.310402 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 15:52:11.310942 auto size-- 65535DDR cs0 size: 2048MB
735 15:52:11.315953 DDR cs1 size: 2048MB
736 15:52:11.316526 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 15:52:11.321640 cs0 DataBus test pass
738 15:52:11.322189 cs1 DataBus test pass
739 15:52:11.322643 cs0 AddrBus test pass
740 15:52:11.327155 cs1 AddrBus test pass
741 15:52:11.327693
742 15:52:11.328188 100bdlr_step_size ps== 420
743 15:52:11.328651 result report
744 15:52:11.332772 boot times 0Enable ddr reg access
745 15:52:11.340502 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 15:52:11.353870 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 15:52:11.927436 0.0;M3 CHK:0;cm4_sp_mode 0
748 15:52:11.928137 MVN_1=0x00000000
749 15:52:11.932959 MVN_2=0x00000000
750 15:52:11.938735 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 15:52:11.939305 OPS=0x10
752 15:52:11.939741 ring efuse init
753 15:52:11.940209 chipver efuse init
754 15:52:11.944297 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 15:52:11.949886 [0.018961 Inits done]
756 15:52:11.950384 secure task start!
757 15:52:11.950815 high task start!
758 15:52:11.954489 low task start!
759 15:52:11.954975 run into bl31
760 15:52:11.961109 NOTICE: BL31: v1.3(release):4fc40b1
761 15:52:11.968918 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 15:52:11.969426 NOTICE: BL31: G12A normal boot!
763 15:52:11.994318 NOTICE: BL31: BL33 decompress pass
764 15:52:11.999929 ERROR: Error initializing runtime service opteed_fast
765 15:52:13.232832
766 15:52:13.233495
767 15:52:13.241220 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 15:52:13.241748
769 15:52:13.242213 Model: Libre Computer AML-A311D-CC Alta
770 15:52:13.449586 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 15:52:13.472926 DRAM: 2 GiB (effective 3.8 GiB)
772 15:52:13.615954 Core: 408 devices, 31 uclasses, devicetree: separate
773 15:52:13.621787 WDT: Not starting watchdog@f0d0
774 15:52:13.654087 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 15:52:13.666608 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 15:52:13.671523 ** Bad device specification mmc 0 **
777 15:52:13.681869 Card did not respond to voltage select! : -110
778 15:52:13.689529 ** Bad device specification mmc 0 **
779 15:52:13.689849 Couldn't find partition mmc 0
780 15:52:13.698002 Card did not respond to voltage select! : -110
781 15:52:13.703374 ** Bad device specification mmc 0 **
782 15:52:13.703697 Couldn't find partition mmc 0
783 15:52:13.707458 Error: could not access storage.
784 15:52:14.051417 Net: eth0: ethernet@ff3f0000
785 15:52:14.051878 starting USB...
786 15:52:14.303866 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 15:52:14.304579 Starting the controller
788 15:52:14.310765 USB XHCI 1.10
789 15:52:16.472541 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
790 15:52:16.473212 bl2_stage_init 0x81
791 15:52:16.477505 hw id: 0x0000 - pwm id 0x01
792 15:52:16.478027 bl2_stage_init 0xc1
793 15:52:16.478467 bl2_stage_init 0x02
794 15:52:16.478898
795 15:52:16.483003 L0:00000000
796 15:52:16.483514 L1:20000703
797 15:52:16.483951 L2:00008067
798 15:52:16.484439 L3:14000000
799 15:52:16.484871 B2:00402000
800 15:52:16.488847 B1:e0f83180
801 15:52:16.489357
802 15:52:16.489798 TE: 58150
803 15:52:16.490230
804 15:52:16.494472 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 15:52:16.494993
806 15:52:16.495431 Board ID = 1
807 15:52:16.500011 Set A53 clk to 24M
808 15:52:16.500532 Set A73 clk to 24M
809 15:52:16.500965 Set clk81 to 24M
810 15:52:16.505734 A53 clk: 1200 MHz
811 15:52:16.506247 A73 clk: 1200 MHz
812 15:52:16.506678 CLK81: 166.6M
813 15:52:16.507102 smccc: 00012aab
814 15:52:16.511746 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 15:52:16.516710 board id: 1
816 15:52:16.522374 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 15:52:16.533183 fw parse done
818 15:52:16.538968 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 15:52:16.581445 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 15:52:16.592389 PIEI prepare done
821 15:52:16.592916 fastboot data load
822 15:52:16.593354 fastboot data verify
823 15:52:16.598099 verify result: 266
824 15:52:16.603667 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 15:52:16.604240 LPDDR4 probe
826 15:52:16.604676 ddr clk to 1584MHz
827 15:52:16.611744 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 15:52:16.648940
829 15:52:16.649507 dmc_version 0001
830 15:52:16.655580 Check phy result
831 15:52:16.661445 INFO : End of CA training
832 15:52:16.661961 INFO : End of initialization
833 15:52:16.667109 INFO : Training has run successfully!
834 15:52:16.667630 Check phy result
835 15:52:16.672653 INFO : End of initialization
836 15:52:16.673170 INFO : End of read enable training
837 15:52:16.678236 INFO : End of fine write leveling
838 15:52:16.683836 INFO : End of Write leveling coarse delay
839 15:52:16.684382 INFO : Training has run successfully!
840 15:52:16.684821 Check phy result
841 15:52:16.689487 INFO : End of initialization
842 15:52:16.689993 INFO : End of read dq deskew training
843 15:52:16.695096 INFO : End of MPR read delay center optimization
844 15:52:16.700621 INFO : End of write delay center optimization
845 15:52:16.706195 INFO : End of read delay center optimization
846 15:52:16.706704 INFO : End of max read latency training
847 15:52:16.711822 INFO : Training has run successfully!
848 15:52:16.712368 1D training succeed
849 15:52:16.720986 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 15:52:16.768558 Check phy result
851 15:52:16.769110 INFO : End of initialization
852 15:52:16.790347 INFO : End of 2D read delay Voltage center optimization
853 15:52:16.809945 INFO : End of 2D read delay Voltage center optimization
854 15:52:16.862650 INFO : End of 2D write delay Voltage center optimization
855 15:52:16.912067 INFO : End of 2D write delay Voltage center optimization
856 15:52:16.917591 INFO : Training has run successfully!
857 15:52:16.918096
858 15:52:16.918533 channel==0
859 15:52:16.923257 RxClkDly_Margin_A0==88 ps 9
860 15:52:16.923773 TxDqDly_Margin_A0==98 ps 10
861 15:52:16.928809 RxClkDly_Margin_A1==88 ps 9
862 15:52:16.929323 TxDqDly_Margin_A1==98 ps 10
863 15:52:16.929753 TrainedVREFDQ_A0==74
864 15:52:16.934400 TrainedVREFDQ_A1==74
865 15:52:16.934908 VrefDac_Margin_A0==25
866 15:52:16.935332 DeviceVref_Margin_A0==40
867 15:52:16.940028 VrefDac_Margin_A1==24
868 15:52:16.940540 DeviceVref_Margin_A1==40
869 15:52:16.940966
870 15:52:16.941388
871 15:52:16.945624 channel==1
872 15:52:16.946140 RxClkDly_Margin_A0==98 ps 10
873 15:52:16.946565 TxDqDly_Margin_A0==88 ps 9
874 15:52:16.951336 RxClkDly_Margin_A1==98 ps 10
875 15:52:16.951901 TxDqDly_Margin_A1==88 ps 9
876 15:52:16.956816 TrainedVREFDQ_A0==77
877 15:52:16.957378 TrainedVREFDQ_A1==77
878 15:52:16.957812 VrefDac_Margin_A0==22
879 15:52:16.962391 DeviceVref_Margin_A0==37
880 15:52:16.962925 VrefDac_Margin_A1==22
881 15:52:16.968026 DeviceVref_Margin_A1==37
882 15:52:16.968580
883 15:52:16.969012 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 15:52:16.969439
885 15:52:17.001617 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
886 15:52:17.002285 2D training succeed
887 15:52:17.007292 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 15:52:17.012816 auto size-- 65535DDR cs0 size: 2048MB
889 15:52:17.013437 DDR cs1 size: 2048MB
890 15:52:17.018477 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 15:52:17.019115 cs0 DataBus test pass
892 15:52:17.024052 cs1 DataBus test pass
893 15:52:17.024594 cs0 AddrBus test pass
894 15:52:17.025024 cs1 AddrBus test pass
895 15:52:17.025443
896 15:52:17.029556 100bdlr_step_size ps== 420
897 15:52:17.030077 result report
898 15:52:17.035355 boot times 0Enable ddr reg access
899 15:52:17.040607 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 15:52:17.053109 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 15:52:17.627589 0.0;M3 CHK:0;cm4_sp_mode 0
902 15:52:17.628285 MVN_1=0x00000000
903 15:52:17.633074 MVN_2=0x00000000
904 15:52:17.638835 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 15:52:17.639375 OPS=0x10
906 15:52:17.639828 ring efuse init
907 15:52:17.640317 chipver efuse init
908 15:52:17.647235 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 15:52:17.647796 [0.018961 Inits done]
910 15:52:17.648279 secure task start!
911 15:52:17.654572 high task start!
912 15:52:17.655087 low task start!
913 15:52:17.655519 run into bl31
914 15:52:17.661372 NOTICE: BL31: v1.3(release):4fc40b1
915 15:52:17.669142 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 15:52:17.669719 NOTICE: BL31: G12A normal boot!
917 15:52:17.694401 NOTICE: BL31: BL33 decompress pass
918 15:52:17.700077 ERROR: Error initializing runtime service opteed_fast
919 15:52:18.933537
920 15:52:18.933941
921 15:52:18.940620 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 15:52:18.940944
923 15:52:18.941165 Model: Libre Computer AML-A311D-CC Alta
924 15:52:19.148881 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 15:52:19.172252 DRAM: 2 GiB (effective 3.8 GiB)
926 15:52:19.316231 Core: 408 devices, 31 uclasses, devicetree: separate
927 15:52:19.322106 WDT: Not starting watchdog@f0d0
928 15:52:19.354343 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 15:52:19.366661 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 15:52:19.370826 ** Bad device specification mmc 0 **
931 15:52:19.382107 Card did not respond to voltage select! : -110
932 15:52:19.388782 ** Bad device specification mmc 0 **
933 15:52:19.389559 Couldn't find partition mmc 0
934 15:52:19.398089 Card did not respond to voltage select! : -110
935 15:52:19.403611 ** Bad device specification mmc 0 **
936 15:52:19.403954 Couldn't find partition mmc 0
937 15:52:19.408626 Error: could not access storage.
938 15:52:19.752271 Net: eth0: ethernet@ff3f0000
939 15:52:19.752950 starting USB...
940 15:52:20.003852 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 15:52:20.004284 Starting the controller
942 15:52:20.011051 USB XHCI 1.10
943 15:52:21.565049 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
944 15:52:21.573474 scanning usb for storage devices... 0 Storage Device(s) found
946 15:52:21.625135 Hit any key to stop autoboot: 1
947 15:52:21.626022 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
948 15:52:21.626738 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
949 15:52:21.627264 Setting prompt string to ['=>']
950 15:52:21.627789 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
951 15:52:21.641045 0
952 15:52:21.642032 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
953 15:52:21.642583 Sending with 10 millisecond of delay
955 15:52:22.777493 => setenv autoload no
956 15:52:22.788337 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
957 15:52:22.793675 setenv autoload no
958 15:52:22.794460 Sending with 10 millisecond of delay
960 15:52:24.592699 => setenv initrd_high 0xffffffff
961 15:52:24.603603 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
962 15:52:24.604304 setenv initrd_high 0xffffffff
963 15:52:24.604877 Sending with 10 millisecond of delay
965 15:52:26.221424 => setenv fdt_high 0xffffffff
966 15:52:26.232330 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
967 15:52:26.232862 setenv fdt_high 0xffffffff
968 15:52:26.233323 Sending with 10 millisecond of delay
970 15:52:26.524765 => dhcp
971 15:52:26.535341 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
972 15:52:26.535917 dhcp
973 15:52:26.536224 Speed: 1000, full duplex
974 15:52:26.536442 BOOTP broadcast 1
975 15:52:26.543222 DHCP client bound to address 192.168.6.27 (8 ms)
976 15:52:26.543765 Sending with 10 millisecond of delay
978 15:52:28.219861 => setenv serverip 192.168.6.2
979 15:52:28.230466 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
980 15:52:28.231036 setenv serverip 192.168.6.2
981 15:52:28.231492 Sending with 10 millisecond of delay
983 15:52:31.954880 => tftpboot 0x01080000 934590/tftp-deploy-lokjrqhw/kernel/uImage
984 15:52:31.965876 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
985 15:52:31.966540 tftpboot 0x01080000 934590/tftp-deploy-lokjrqhw/kernel/uImage
986 15:52:31.966805 Speed: 1000, full duplex
987 15:52:31.967018 Using ethernet@ff3f0000 device
988 15:52:31.968292 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
989 15:52:31.973847 Filename '934590/tftp-deploy-lokjrqhw/kernel/uImage'.
990 15:52:31.977756 Load address: 0x1080000
991 15:52:34.784566 Loading: *################################################## 43.6 MiB
992 15:52:34.784959 15.5 MiB/s
993 15:52:34.785177 done
994 15:52:34.788975 Bytes transferred = 45713984 (2b98a40 hex)
995 15:52:34.789479 Sending with 10 millisecond of delay
997 15:52:39.475451 => tftpboot 0x08000000 934590/tftp-deploy-lokjrqhw/ramdisk/ramdisk.cpio.gz.uboot
998 15:52:39.486195 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
999 15:52:39.486743 tftpboot 0x08000000 934590/tftp-deploy-lokjrqhw/ramdisk/ramdisk.cpio.gz.uboot
1000 15:52:39.486991 Speed: 1000, full duplex
1001 15:52:39.487211 Using ethernet@ff3f0000 device
1002 15:52:39.488798 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1003 15:52:39.497591 Filename '934590/tftp-deploy-lokjrqhw/ramdisk/ramdisk.cpio.gz.uboot'.
1004 15:52:39.498068 Load address: 0x8000000
1005 15:52:46.092968 Loading: *####################T ############################# UDP wrong checksum 00000005 000012d7
1006 15:52:48.927049 UDP wrong checksum 000000ff 00005a2c
1007 15:52:48.939606 UDP wrong checksum 000000ff 0000f11e
1008 15:52:51.094918 T UDP wrong checksum 00000005 000012d7
1009 15:53:01.096968 T T UDP wrong checksum 00000005 000012d7
1010 15:53:18.674448 T T T UDP wrong checksum 000000ff 0000ccdf
1011 15:53:18.726079 UDP wrong checksum 000000ff 000056d2
1012 15:53:21.100977 T UDP wrong checksum 00000005 000012d7
1013 15:53:36.105102 T T
1014 15:53:36.105770 Retry count exceeded; starting again
1016 15:53:36.107351 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1019 15:53:36.109483 end: 2.4 uboot-commands (duration 00:01:47) [common]
1021 15:53:36.110994 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1023 15:53:36.112141 end: 2 uboot-action (duration 00:01:47) [common]
1025 15:53:36.113770 Cleaning after the job
1026 15:53:36.114350 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/934590/tftp-deploy-lokjrqhw/ramdisk
1027 15:53:36.115739 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/934590/tftp-deploy-lokjrqhw/kernel
1028 15:53:36.146654 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/934590/tftp-deploy-lokjrqhw/dtb
1029 15:53:36.148036 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/934590/tftp-deploy-lokjrqhw/nfsrootfs
1030 15:53:36.371125 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/934590/tftp-deploy-lokjrqhw/modules
1031 15:53:36.393120 start: 4.1 power-off (timeout 00:00:30) [common]
1032 15:53:36.393778 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1033 15:53:36.427337 >> OK - accepted request
1034 15:53:36.429443 Returned 0 in 0 seconds
1035 15:53:36.530326 end: 4.1 power-off (duration 00:00:00) [common]
1037 15:53:36.531402 start: 4.2 read-feedback (timeout 00:10:00) [common]
1038 15:53:36.532141 Listened to connection for namespace 'common' for up to 1s
1039 15:53:37.532219 Finalising connection for namespace 'common'
1040 15:53:37.532741 Disconnecting from shell: Finalise
1041 15:53:37.533024 =>
1042 15:53:37.633769 end: 4.2 read-feedback (duration 00:00:01) [common]
1043 15:53:37.634314 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/934590
1044 15:53:40.227123 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/934590
1045 15:53:40.227771 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.