Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 17:59:52.491359 lava-dispatcher, installed at version: 2024.01
2 17:59:52.492125 start: 0 validate
3 17:59:52.492601 Start time: 2024-11-05 17:59:52.492572+00:00 (UTC)
4 17:59:52.493131 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 17:59:52.493673 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 17:59:52.538327 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 17:59:52.538864 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-2-g08a3b241adfd9%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 17:59:52.566224 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 17:59:52.566794 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-2-g08a3b241adfd9%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 17:59:52.595791 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 17:59:52.596300 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 17:59:52.622088 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 17:59:52.622560 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-2-g08a3b241adfd9%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 17:59:52.662956 validate duration: 0.17
16 17:59:52.663872 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 17:59:52.664200 start: 1.1 download-retry (timeout 00:10:00) [common]
18 17:59:52.664495 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 17:59:52.665254 Not decompressing ramdisk as can be used compressed.
20 17:59:52.666049 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 17:59:52.666979 saving as /var/lib/lava/dispatcher/tmp/941318/tftp-deploy-qne4z7f2/ramdisk/initrd.cpio.gz
22 17:59:52.667536 total size: 4775763 (4 MB)
23 17:59:52.701402 progress 0 % (0 MB)
24 17:59:52.708956 progress 5 % (0 MB)
25 17:59:52.715070 progress 10 % (0 MB)
26 17:59:52.720901 progress 15 % (0 MB)
27 17:59:52.726744 progress 20 % (0 MB)
28 17:59:52.729767 progress 25 % (1 MB)
29 17:59:52.732784 progress 30 % (1 MB)
30 17:59:52.736250 progress 35 % (1 MB)
31 17:59:52.739341 progress 40 % (1 MB)
32 17:59:52.742296 progress 45 % (2 MB)
33 17:59:52.745222 progress 50 % (2 MB)
34 17:59:52.748469 progress 55 % (2 MB)
35 17:59:52.751361 progress 60 % (2 MB)
36 17:59:52.754300 progress 65 % (2 MB)
37 17:59:52.757530 progress 70 % (3 MB)
38 17:59:52.760440 progress 75 % (3 MB)
39 17:59:52.763502 progress 80 % (3 MB)
40 17:59:52.766397 progress 85 % (3 MB)
41 17:59:52.769614 progress 90 % (4 MB)
42 17:59:52.772503 progress 95 % (4 MB)
43 17:59:52.775430 progress 100 % (4 MB)
44 17:59:52.776072 4 MB downloaded in 0.11 s (41.97 MB/s)
45 17:59:52.776642 end: 1.1.1 http-download (duration 00:00:00) [common]
47 17:59:52.777547 end: 1.1 download-retry (duration 00:00:00) [common]
48 17:59:52.777884 start: 1.2 download-retry (timeout 00:10:00) [common]
49 17:59:52.778191 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 17:59:52.778673 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-2-g08a3b241adfd9/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 17:59:52.778955 saving as /var/lib/lava/dispatcher/tmp/941318/tftp-deploy-qne4z7f2/kernel/zImage
52 17:59:52.779192 total size: 11440640 (10 MB)
53 17:59:52.779415 No compression specified
54 17:59:52.813442 progress 0 % (0 MB)
55 17:59:52.820686 progress 5 % (0 MB)
56 17:59:52.827571 progress 10 % (1 MB)
57 17:59:52.834927 progress 15 % (1 MB)
58 17:59:52.841720 progress 20 % (2 MB)
59 17:59:52.848917 progress 25 % (2 MB)
60 17:59:52.856057 progress 30 % (3 MB)
61 17:59:52.863380 progress 35 % (3 MB)
62 17:59:52.870281 progress 40 % (4 MB)
63 17:59:52.877451 progress 45 % (4 MB)
64 17:59:52.884193 progress 50 % (5 MB)
65 17:59:52.891459 progress 55 % (6 MB)
66 17:59:52.898252 progress 60 % (6 MB)
67 17:59:52.905054 progress 65 % (7 MB)
68 17:59:52.912272 progress 70 % (7 MB)
69 17:59:52.919188 progress 75 % (8 MB)
70 17:59:52.926111 progress 80 % (8 MB)
71 17:59:52.932686 progress 85 % (9 MB)
72 17:59:52.939544 progress 90 % (9 MB)
73 17:59:52.946111 progress 95 % (10 MB)
74 17:59:52.953301 progress 100 % (10 MB)
75 17:59:52.953772 10 MB downloaded in 0.17 s (62.50 MB/s)
76 17:59:52.954324 end: 1.2.1 http-download (duration 00:00:00) [common]
78 17:59:52.955242 end: 1.2 download-retry (duration 00:00:00) [common]
79 17:59:52.955548 start: 1.3 download-retry (timeout 00:10:00) [common]
80 17:59:52.955829 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 17:59:52.956323 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-2-g08a3b241adfd9/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 17:59:52.956588 saving as /var/lib/lava/dispatcher/tmp/941318/tftp-deploy-qne4z7f2/dtb/am335x-boneblack.dtb
83 17:59:52.956807 total size: 70568 (0 MB)
84 17:59:52.957024 No compression specified
85 17:59:52.992938 progress 46 % (0 MB)
86 17:59:52.993730 progress 92 % (0 MB)
87 17:59:52.994435 progress 100 % (0 MB)
88 17:59:52.994810 0 MB downloaded in 0.04 s (1.77 MB/s)
89 17:59:52.995250 end: 1.3.1 http-download (duration 00:00:00) [common]
91 17:59:52.996043 end: 1.3 download-retry (duration 00:00:00) [common]
92 17:59:52.996306 start: 1.4 download-retry (timeout 00:10:00) [common]
93 17:59:52.996567 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 17:59:52.997026 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 17:59:52.997269 saving as /var/lib/lava/dispatcher/tmp/941318/tftp-deploy-qne4z7f2/nfsrootfs/full.rootfs.tar
96 17:59:52.997472 total size: 117747780 (112 MB)
97 17:59:52.997680 Using unxz to decompress xz
98 17:59:53.028903 progress 0 % (0 MB)
99 17:59:53.742771 progress 5 % (5 MB)
100 17:59:54.470743 progress 10 % (11 MB)
101 17:59:55.231433 progress 15 % (16 MB)
102 17:59:55.938857 progress 20 % (22 MB)
103 17:59:56.513686 progress 25 % (28 MB)
104 17:59:57.305644 progress 30 % (33 MB)
105 17:59:58.104501 progress 35 % (39 MB)
106 17:59:58.447556 progress 40 % (44 MB)
107 17:59:58.807641 progress 45 % (50 MB)
108 17:59:59.466109 progress 50 % (56 MB)
109 18:00:00.286219 progress 55 % (61 MB)
110 18:00:01.016391 progress 60 % (67 MB)
111 18:00:01.728658 progress 65 % (73 MB)
112 18:00:02.482251 progress 70 % (78 MB)
113 18:00:03.226924 progress 75 % (84 MB)
114 18:00:03.944206 progress 80 % (89 MB)
115 18:00:04.638971 progress 85 % (95 MB)
116 18:00:05.415324 progress 90 % (101 MB)
117 18:00:06.164978 progress 95 % (106 MB)
118 18:00:06.968821 progress 100 % (112 MB)
119 18:00:06.981526 112 MB downloaded in 13.98 s (8.03 MB/s)
120 18:00:06.983016 end: 1.4.1 http-download (duration 00:00:14) [common]
122 18:00:06.984979 end: 1.4 download-retry (duration 00:00:14) [common]
123 18:00:06.985541 start: 1.5 download-retry (timeout 00:09:46) [common]
124 18:00:06.986124 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 18:00:06.987031 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-2-g08a3b241adfd9/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 18:00:06.987611 saving as /var/lib/lava/dispatcher/tmp/941318/tftp-deploy-qne4z7f2/modules/modules.tar
127 18:00:06.988063 total size: 6609096 (6 MB)
128 18:00:06.988624 Using unxz to decompress xz
129 18:00:07.029617 progress 0 % (0 MB)
130 18:00:07.064685 progress 5 % (0 MB)
131 18:00:07.108113 progress 10 % (0 MB)
132 18:00:07.150723 progress 15 % (0 MB)
133 18:00:07.196805 progress 20 % (1 MB)
134 18:00:07.253476 progress 25 % (1 MB)
135 18:00:07.305712 progress 30 % (1 MB)
136 18:00:07.357184 progress 35 % (2 MB)
137 18:00:07.402043 progress 40 % (2 MB)
138 18:00:07.444581 progress 45 % (2 MB)
139 18:00:07.487391 progress 50 % (3 MB)
140 18:00:07.529199 progress 55 % (3 MB)
141 18:00:07.578659 progress 60 % (3 MB)
142 18:00:07.620973 progress 65 % (4 MB)
143 18:00:07.663938 progress 70 % (4 MB)
144 18:00:07.709108 progress 75 % (4 MB)
145 18:00:07.751220 progress 80 % (5 MB)
146 18:00:07.793083 progress 85 % (5 MB)
147 18:00:07.835444 progress 90 % (5 MB)
148 18:00:07.878207 progress 95 % (6 MB)
149 18:00:07.921572 progress 100 % (6 MB)
150 18:00:07.934445 6 MB downloaded in 0.95 s (6.66 MB/s)
151 18:00:07.935033 end: 1.5.1 http-download (duration 00:00:01) [common]
153 18:00:07.935866 end: 1.5 download-retry (duration 00:00:01) [common]
154 18:00:07.936136 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 18:00:07.936401 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 18:00:25.265266 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/941318/extract-nfsrootfs-4a67tz5m
157 18:00:25.265890 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 18:00:25.266182 start: 1.6.2 lava-overlay (timeout 00:09:27) [common]
159 18:00:25.266789 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_
160 18:00:25.267229 makedir: /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin
161 18:00:25.267563 makedir: /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/tests
162 18:00:25.267873 makedir: /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/results
163 18:00:25.268207 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-add-keys
164 18:00:25.268773 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-add-sources
165 18:00:25.269355 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-background-process-start
166 18:00:25.269890 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-background-process-stop
167 18:00:25.270452 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-common-functions
168 18:00:25.270955 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-echo-ipv4
169 18:00:25.271482 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-install-packages
170 18:00:25.271976 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-installed-packages
171 18:00:25.272475 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-os-build
172 18:00:25.272997 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-probe-channel
173 18:00:25.273480 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-probe-ip
174 18:00:25.273994 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-target-ip
175 18:00:25.274488 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-target-mac
176 18:00:25.274964 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-target-storage
177 18:00:25.275448 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-test-case
178 18:00:25.275943 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-test-event
179 18:00:25.276444 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-test-feedback
180 18:00:25.276974 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-test-raise
181 18:00:25.277459 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-test-reference
182 18:00:25.277989 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-test-runner
183 18:00:25.278557 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-test-set
184 18:00:25.279054 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-test-shell
185 18:00:25.279543 Updating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-add-keys (debian)
186 18:00:25.280075 Updating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-add-sources (debian)
187 18:00:25.280569 Updating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-install-packages (debian)
188 18:00:25.281077 Updating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-installed-packages (debian)
189 18:00:25.281578 Updating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/bin/lava-os-build (debian)
190 18:00:25.282043 Creating /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/environment
191 18:00:25.282424 LAVA metadata
192 18:00:25.282679 - LAVA_JOB_ID=941318
193 18:00:25.282889 - LAVA_DISPATCHER_IP=192.168.6.3
194 18:00:25.283250 start: 1.6.2.1 ssh-authorize (timeout 00:09:27) [common]
195 18:00:25.284183 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 18:00:25.284495 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:27) [common]
197 18:00:25.284697 skipped lava-vland-overlay
198 18:00:25.284933 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 18:00:25.285184 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:27) [common]
200 18:00:25.285382 skipped lava-multinode-overlay
201 18:00:25.285616 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 18:00:25.285880 start: 1.6.2.4 test-definition (timeout 00:09:27) [common]
203 18:00:25.286132 Loading test definitions
204 18:00:25.286405 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:27) [common]
205 18:00:25.286638 Using /lava-941318 at stage 0
206 18:00:25.287746 uuid=941318_1.6.2.4.1 testdef=None
207 18:00:25.288050 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 18:00:25.288311 start: 1.6.2.4.2 test-overlay (timeout 00:09:27) [common]
209 18:00:25.289859 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 18:00:25.290642 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:27) [common]
212 18:00:25.292574 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 18:00:25.293385 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:27) [common]
215 18:00:25.295198 runner path: /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/0/tests/0_timesync-off test_uuid 941318_1.6.2.4.1
216 18:00:25.295781 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 18:00:25.296597 start: 1.6.2.4.5 git-repo-action (timeout 00:09:27) [common]
219 18:00:25.296818 Using /lava-941318 at stage 0
220 18:00:25.297177 Fetching tests from https://github.com/kernelci/test-definitions.git
221 18:00:25.297468 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/0/tests/1_kselftest-dt'
222 18:00:28.656860 Running '/usr/bin/git checkout kernelci.org
223 18:00:29.100922 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 18:00:29.102372 uuid=941318_1.6.2.4.5 testdef=None
225 18:00:29.102715 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 18:00:29.103449 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 18:00:29.106270 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 18:00:29.107078 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 18:00:29.110736 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 18:00:29.111579 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 18:00:29.119418 runner path: /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/0/tests/1_kselftest-dt test_uuid 941318_1.6.2.4.5
235 18:00:29.120034 BOARD='beaglebone-black'
236 18:00:29.120479 BRANCH='broonie-sound'
237 18:00:29.120911 SKIPFILE='/dev/null'
238 18:00:29.121337 SKIP_INSTALL='True'
239 18:00:29.121761 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-2-g08a3b241adfd9/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 18:00:29.122226 TST_CASENAME=''
241 18:00:29.122659 TST_CMDFILES='dt'
242 18:00:29.123739 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 18:00:29.125398 Creating lava-test-runner.conf files
245 18:00:29.125890 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/941318/lava-overlay-8gk78xr_/lava-941318/0 for stage 0
246 18:00:29.126615 - 0_timesync-off
247 18:00:29.127111 - 1_kselftest-dt
248 18:00:29.127790 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 18:00:29.128379 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 18:00:53.029088 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 18:00:53.029518 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
252 18:00:53.029773 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 18:00:53.030072 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 18:00:53.030332 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
255 18:00:53.392922 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 18:00:53.393378 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
257 18:00:53.393624 extracting modules file /var/lib/lava/dispatcher/tmp/941318/tftp-deploy-qne4z7f2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/941318/extract-nfsrootfs-4a67tz5m
258 18:00:54.275118 extracting modules file /var/lib/lava/dispatcher/tmp/941318/tftp-deploy-qne4z7f2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/941318/extract-overlay-ramdisk-5b0ry2_1/ramdisk
259 18:00:55.173455 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 18:00:55.173951 start: 1.6.5 apply-overlay-tftp (timeout 00:08:57) [common]
261 18:00:55.174223 [common] Applying overlay to NFS
262 18:00:55.174433 [common] Applying overlay /var/lib/lava/dispatcher/tmp/941318/compress-overlay-woqvrd25/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/941318/extract-nfsrootfs-4a67tz5m
263 18:00:57.885146 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 18:00:57.885623 start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
265 18:00:57.885920 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
266 18:00:57.886240 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 18:00:57.886493 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 18:00:57.886743 start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
269 18:00:57.886985 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 18:00:57.887231 start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
271 18:00:57.887450 Building ramdisk /var/lib/lava/dispatcher/tmp/941318/extract-overlay-ramdisk-5b0ry2_1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/941318/extract-overlay-ramdisk-5b0ry2_1/ramdisk
272 18:00:58.900440 >> 74888 blocks
273 18:01:03.448878 Adding RAMdisk u-boot header.
274 18:01:03.449349 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/941318/extract-overlay-ramdisk-5b0ry2_1/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/941318/extract-overlay-ramdisk-5b0ry2_1/ramdisk.cpio.gz.uboot
275 18:01:03.606171 output: Image Name:
276 18:01:03.606594 output: Created: Tue Nov 5 18:01:03 2024
277 18:01:03.606812 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 18:01:03.607011 output: Data Size: 14791515 Bytes = 14444.84 KiB = 14.11 MiB
279 18:01:03.607207 output: Load Address: 00000000
280 18:01:03.607399 output: Entry Point: 00000000
281 18:01:03.607592 output:
282 18:01:03.608223 rename /var/lib/lava/dispatcher/tmp/941318/extract-overlay-ramdisk-5b0ry2_1/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/941318/tftp-deploy-qne4z7f2/ramdisk/ramdisk.cpio.gz.uboot
283 18:01:03.608669 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 18:01:03.608973 end: 1.6 prepare-tftp-overlay (duration 00:00:56) [common]
285 18:01:03.609254 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:49) [common]
286 18:01:03.609497 No LXC device requested
287 18:01:03.609750 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 18:01:03.610473 start: 1.8 deploy-device-env (timeout 00:08:49) [common]
289 18:01:03.610877 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 18:01:03.611209 Checking files for TFTP limit of 4294967296 bytes.
291 18:01:03.612791 end: 1 tftp-deploy (duration 00:01:11) [common]
292 18:01:03.613241 start: 2 uboot-action (timeout 00:05:00) [common]
293 18:01:03.613652 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 18:01:03.614062 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 18:01:03.614453 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 18:01:03.614988 substitutions:
297 18:01:03.615342 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 18:01:03.615654 - {DTB_ADDR}: 0x88000000
299 18:01:03.615955 - {DTB}: 941318/tftp-deploy-qne4z7f2/dtb/am335x-boneblack.dtb
300 18:01:03.616262 - {INITRD}: 941318/tftp-deploy-qne4z7f2/ramdisk/ramdisk.cpio.gz.uboot
301 18:01:03.616497 - {KERNEL_ADDR}: 0x82000000
302 18:01:03.616698 - {KERNEL}: 941318/tftp-deploy-qne4z7f2/kernel/zImage
303 18:01:03.616894 - {LAVA_MAC}: None
304 18:01:03.617402 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/941318/extract-nfsrootfs-4a67tz5m
305 18:01:03.617730 - {NFS_SERVER_IP}: 192.168.6.3
306 18:01:03.618062 - {PRESEED_CONFIG}: None
307 18:01:03.618385 - {PRESEED_LOCAL}: None
308 18:01:03.618688 - {RAMDISK_ADDR}: 0x83000000
309 18:01:03.618998 - {RAMDISK}: 941318/tftp-deploy-qne4z7f2/ramdisk/ramdisk.cpio.gz.uboot
310 18:01:03.619227 - {ROOT_PART}: None
311 18:01:03.619428 - {ROOT}: None
312 18:01:03.619622 - {SERVER_IP}: 192.168.6.3
313 18:01:03.619817 - {TEE_ADDR}: 0x83000000
314 18:01:03.620009 - {TEE}: None
315 18:01:03.620201 Parsed boot commands:
316 18:01:03.620386 - setenv autoload no
317 18:01:03.620575 - setenv initrd_high 0xffffffff
318 18:01:03.620765 - setenv fdt_high 0xffffffff
319 18:01:03.620955 - dhcp
320 18:01:03.621141 - setenv serverip 192.168.6.3
321 18:01:03.621329 - tftp 0x82000000 941318/tftp-deploy-qne4z7f2/kernel/zImage
322 18:01:03.621646 - tftp 0x83000000 941318/tftp-deploy-qne4z7f2/ramdisk/ramdisk.cpio.gz.uboot
323 18:01:03.621896 - setenv initrd_size ${filesize}
324 18:01:03.622101 - tftp 0x88000000 941318/tftp-deploy-qne4z7f2/dtb/am335x-boneblack.dtb
325 18:01:03.622296 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/941318/extract-nfsrootfs-4a67tz5m,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 18:01:03.622495 - bootz 0x82000000 0x83000000 0x88000000
327 18:01:03.622761 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 18:01:03.623541 start: 2.3 connect-device (timeout 00:05:00) [common]
330 18:01:03.623758 [common] connect-device Connecting to device using 'telnet conserv3 3002'
331 18:01:03.634747 Setting prompt string to ['lava-test: # ']
332 18:01:03.635959 end: 2.3 connect-device (duration 00:00:00) [common]
333 18:01:03.636400 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 18:01:03.636717 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 18:01:03.637020 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 18:01:03.637964 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
337 18:01:03.668711 >> OK - accepted request
338 18:01:03.670397 Returned 0 in 0 seconds
339 18:01:03.771348 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 18:01:03.772399 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 18:01:03.772764 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 18:01:03.773102 Setting prompt string to ['Hit any key to stop autoboot']
344 18:01:03.773358 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 18:01:03.774394 Trying 192.168.56.22...
346 18:01:03.774728 Connected to conserv3.
347 18:01:03.774954 Escape character is '^]'.
348 18:01:03.775179
349 18:01:03.775412 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 18:01:03.775646
351 18:01:12.190837
352 18:01:12.197733 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
353 18:01:12.198078 Trying to boot from MMC1
354 18:01:16.240876
355 18:01:16.247827 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
356 18:01:16.248449 Trying to boot from MMC1
357 18:01:18.930114
358 18:01:18.937841 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
359 18:01:18.938379 Trying to boot from MMC1
360 18:01:19.520231
361 18:01:19.520894
362 18:01:19.525712 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
363 18:01:19.526300
364 18:01:19.526787 CPU : AM335X-GP rev 2.0
365 18:01:19.530857 Model: TI AM335x BeagleBone Black
366 18:01:19.531389 DRAM: 512 MiB
367 18:01:19.610547 Core: 160 devices, 18 uclasses, devicetree: separate
368 18:01:19.624483 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
369 18:01:20.025152 NAND: 0 MiB
370 18:01:20.035435 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
371 18:01:20.157918 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
372 18:01:20.179243 <ethaddr> not set. Validating first E-fuse MAC
373 18:01:20.209612 Net: eth2: ethernet@4a100000, eth3: usb_ether
375 18:01:20.268334 Hit any key to stop autoboot: 2
376 18:01:20.269959 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
377 18:01:20.270713 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
378 18:01:20.271303 Setting prompt string to ['=>']
379 18:01:20.271920 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
380 18:01:20.278158 0
381 18:01:20.279044 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
382 18:01:20.279648 Sending with 10 millisecond of delay
384 18:01:21.414612 => setenv autoload no
385 18:01:21.425671 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
386 18:01:21.432420 setenv autoload no
387 18:01:21.433350 Sending with 10 millisecond of delay
389 18:01:23.234617 => setenv initrd_high 0xffffffff
390 18:01:23.245614 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
391 18:01:23.246478 setenv initrd_high 0xffffffff
392 18:01:23.247139 Sending with 10 millisecond of delay
394 18:01:24.864015 => setenv fdt_high 0xffffffff
395 18:01:24.875015 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
396 18:01:24.876115 setenv fdt_high 0xffffffff
397 18:01:24.877015 Sending with 10 millisecond of delay
399 18:01:25.170228 => dhcp
400 18:01:25.180734 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
401 18:01:25.182716 dhcp
402 18:01:25.183457 link up on port 0, speed 100, full duplex
403 18:01:25.183670 BOOTP broadcast 1
404 18:01:25.434435 BOOTP broadcast 2
405 18:01:25.937377 BOOTP broadcast 3
406 18:01:26.939346 BOOTP broadcast 4
407 18:01:27.027451 DHCP client bound to address 192.168.6.8 (1842 ms)
408 18:01:27.028252 Sending with 10 millisecond of delay
410 18:01:28.704643 => setenv serverip 192.168.6.3
411 18:01:28.715382 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
412 18:01:28.716179 setenv serverip 192.168.6.3
413 18:01:28.716894 Sending with 10 millisecond of delay
415 18:01:32.198736 => tftp 0x82000000 941318/tftp-deploy-qne4z7f2/kernel/zImage
416 18:01:32.209507 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:31)
417 18:01:32.210430 tftp 0x82000000 941318/tftp-deploy-qne4z7f2/kernel/zImage
418 18:01:32.210859 link up on port 0, speed 100, full duplex
419 18:01:32.214521 Using ethernet@4a100000 device
420 18:01:32.220851 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
421 18:01:32.221295 Filename '941318/tftp-deploy-qne4z7f2/kernel/zImage'.
422 18:01:32.223429 Load address: 0x82000000
423 18:01:34.339875 Loading: *################################################## 10.9 MiB
424 18:01:34.340705 5.2 MiB/s
425 18:01:34.341395 done
426 18:01:34.343323 Bytes transferred = 11440640 (ae9200 hex)
427 18:01:34.344345 Sending with 10 millisecond of delay
429 18:01:38.794665 => tftp 0x83000000 941318/tftp-deploy-qne4z7f2/ramdisk/ramdisk.cpio.gz.uboot
430 18:01:38.805470 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
431 18:01:38.806432 tftp 0x83000000 941318/tftp-deploy-qne4z7f2/ramdisk/ramdisk.cpio.gz.uboot
432 18:01:38.806902 link up on port 0, speed 100, full duplex
433 18:01:38.810251 Using ethernet@4a100000 device
434 18:01:38.815821 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
435 18:01:38.823289 Filename '941318/tftp-deploy-qne4z7f2/ramdisk/ramdisk.cpio.gz.uboot'.
436 18:01:38.823806 Load address: 0x83000000
437 18:01:41.576611 Loading: *################################################## 14.1 MiB
438 18:01:41.577358 5.1 MiB/s
439 18:01:41.577576 done
440 18:01:41.580870 Bytes transferred = 14791579 (e1b39b hex)
441 18:01:41.581750 Sending with 10 millisecond of delay
443 18:01:43.440913 => setenv initrd_size ${filesize}
444 18:01:43.451710 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
445 18:01:43.452561 setenv initrd_size ${filesize}
446 18:01:43.453316 Sending with 10 millisecond of delay
448 18:01:47.599385 => tftp 0x88000000 941318/tftp-deploy-qne4z7f2/dtb/am335x-boneblack.dtb
449 18:01:47.610162 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
450 18:01:47.611027 tftp 0x88000000 941318/tftp-deploy-qne4z7f2/dtb/am335x-boneblack.dtb
451 18:01:47.611444 link up on port 0, speed 100, full duplex
452 18:01:47.614734 Using ethernet@4a100000 device
453 18:01:47.620307 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
454 18:01:47.627612 Filename '941318/tftp-deploy-qne4z7f2/dtb/am335x-boneblack.dtb'.
455 18:01:47.628100 Load address: 0x88000000
456 18:01:47.639491 Loading: *################################################## 68.9 KiB
457 18:01:47.648299 5.2 MiB/s
458 18:01:47.648748 done
459 18:01:47.649139 Bytes transferred = 70568 (113a8 hex)
460 18:01:47.649795 Sending with 10 millisecond of delay
462 18:02:00.831010 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/941318/extract-nfsrootfs-4a67tz5m,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
463 18:02:00.841801 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
464 18:02:00.842681 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/941318/extract-nfsrootfs-4a67tz5m,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
465 18:02:00.843382 Sending with 10 millisecond of delay
467 18:02:03.182166 => bootz 0x82000000 0x83000000 0x88000000
468 18:02:03.193007 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
469 18:02:03.193643 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
470 18:02:03.194697 bootz 0x82000000 0x83000000 0x88000000
471 18:02:03.195181 Kernel image @ 0x82000000 [ 0x000000 - 0xae9200 ]
472 18:02:03.195675 ## Loading init Ramdisk from Legacy Image at 83000000 ...
473 18:02:03.200534 Image Name:
474 18:02:03.201047 Created: 2024-11-05 18:01:03 UTC
475 18:02:03.209330 Image Type: ARM Linux RAMDisk Image (uncompressed)
476 18:02:03.209923 Data Size: 14791515 Bytes = 14.1 MiB
477 18:02:03.216858 Load Address: 00000000
478 18:02:03.217417 Entry Point: 00000000
479 18:02:03.386073 Verifying Checksum ... OK
480 18:02:03.386626 ## Flattened Device Tree blob at 88000000
481 18:02:03.392617 Booting using the fdt blob at 0x88000000
482 18:02:03.393087 Working FDT set to 88000000
483 18:02:03.398175 Using Device Tree in place at 88000000, end 880143a7
484 18:02:03.402569 Working FDT set to 88000000
485 18:02:03.416149
486 18:02:03.416711 Starting kernel ...
487 18:02:03.417139
488 18:02:03.418097 end: 2.4.3 bootloader-commands (duration 00:00:43) [common]
489 18:02:03.418758 start: 2.4.4 auto-login-action (timeout 00:04:00) [common]
490 18:02:03.419251 Setting prompt string to ['Linux version [0-9]']
491 18:02:03.419724 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
492 18:02:03.420201 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
493 18:02:04.258985 [ 0.000000] Booting Linux on physical CPU 0x0
494 18:02:04.265236 start: 2.4.4.1 login-action (timeout 00:03:59) [common]
495 18:02:04.265863 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
496 18:02:04.266332 Setting prompt string to []
497 18:02:04.266615 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
498 18:02:04.266861 Using line separator: #'\n'#
499 18:02:04.267074 No login prompt set.
500 18:02:04.267390 Parsing kernel messages
501 18:02:04.267804 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
502 18:02:04.268625 [login-action] Waiting for messages, (timeout 00:03:59)
503 18:02:04.269068 Waiting using forced prompt support (timeout 00:02:00)
504 18:02:04.281803 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j363583-arm-gcc-12-multi-v7-defconfig-fl4l5) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Tue Nov 5 17:30:01 UTC 2024
505 18:02:04.287506 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
506 18:02:04.293257 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
507 18:02:04.304648 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
508 18:02:04.310422 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
509 18:02:04.316082 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
510 18:02:04.316401 [ 0.000000] Memory policy: Data cache writeback
511 18:02:04.322750 [ 0.000000] efi: UEFI not found.
512 18:02:04.328254 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
513 18:02:04.333949 [ 0.000000] Zone ranges:
514 18:02:04.339627 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
515 18:02:04.345367 [ 0.000000] Normal empty
516 18:02:04.345851 [ 0.000000] HighMem empty
517 18:02:04.348531 [ 0.000000] Movable zone start for each node
518 18:02:04.354174 [ 0.000000] Early memory node ranges
519 18:02:04.359951 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
520 18:02:04.368047 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
521 18:02:04.393360 [ 0.000000] CPU: All CPU(s) started in SVC mode.
522 18:02:04.399094 [ 0.000000] AM335X ES2.0 (sgx neon)
523 18:02:04.410603 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
524 18:02:04.428306 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/941318/extract-nfsrootfs-4a67tz5m,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
525 18:02:04.439865 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
526 18:02:04.445636 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
527 18:02:04.451362 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
528 18:02:04.461362 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
529 18:02:04.490516 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
530 18:02:04.496638 <6>[ 0.000000] trace event string verifier disabled
531 18:02:04.497130 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
532 18:02:04.504536 <6>[ 0.000000] rcu: RCU event tracing is enabled.
533 18:02:04.510191 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
534 18:02:04.521868 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
535 18:02:04.526653 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
536 18:02:04.540534 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
537 18:02:04.558476 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
538 18:02:04.565417 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
539 18:02:04.657106 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
540 18:02:04.665641 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
541 18:02:04.678266 <6>[ 0.008336] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
542 18:02:04.686692 <6>[ 0.019146] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
543 18:02:04.695961 <6>[ 0.033934] Console: colour dummy device 80x30
544 18:02:04.701872 Matched prompt #6: WARNING:
545 18:02:04.702435 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
546 18:02:04.707297 <3>[ 0.038832] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
547 18:02:04.713060 <3>[ 0.045900] This ensures that you still see kernel messages. Please
548 18:02:04.716872 <3>[ 0.052628] update your kernel commandline.
549 18:02:04.756998 <6>[ 0.057241] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
550 18:02:04.762781 <6>[ 0.096152] CPU: Testing write buffer coherency: ok
551 18:02:04.768931 <6>[ 0.101518] CPU0: Spectre v2: using BPIALL workaround
552 18:02:04.769773 <6>[ 0.106984] pid_max: default: 32768 minimum: 301
553 18:02:04.782303 <6>[ 0.112176] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
554 18:02:04.786937 <6>[ 0.119996] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
555 18:02:04.792992 <6>[ 0.129347] CPU0: thread -1, cpu 0, socket -1, mpidr 0
556 18:02:04.869583 <6>[ 0.199532] Setting up static identity map for 0x80300000 - 0x803000ac
557 18:02:04.875254 <6>[ 0.209151] rcu: Hierarchical SRCU implementation.
558 18:02:04.878959 <6>[ 0.214438] rcu: Max phase no-delay instances is 1000.
559 18:02:04.887562 <6>[ 0.225430] EFI services will not be available.
560 18:02:04.893283 <6>[ 0.230802] smp: Bringing up secondary CPUs ...
561 18:02:04.899090 <6>[ 0.235774] smp: Brought up 1 node, 1 CPU
562 18:02:04.907168 <6>[ 0.240247] SMP: Total of 1 processors activated (996.14 BogoMIPS).
563 18:02:04.913010 <6>[ 0.246968] CPU: All CPU(s) started in SVC mode.
564 18:02:04.925229 <6>[ 0.252162] Memory: 405996K/522240K available (16384K kernel code, 2542K rwdata, 6784K rodata, 2048K init, 431K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
565 18:02:04.931036 <6>[ 0.268433] devtmpfs: initialized
566 18:02:04.953178 <6>[ 0.285480] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
567 18:02:04.961602 <6>[ 0.294070] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
568 18:02:04.970640 <6>[ 0.304512] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
569 18:02:04.981273 <6>[ 0.316716] pinctrl core: initialized pinctrl subsystem
570 18:02:04.990609 <6>[ 0.327349] DMI not present or invalid.
571 18:02:04.998884 <6>[ 0.333199] NET: Registered PF_NETLINK/PF_ROUTE protocol family
572 18:02:05.008412 <6>[ 0.342162] DMA: preallocated 256 KiB pool for atomic coherent allocations
573 18:02:05.023465 <6>[ 0.353570] thermal_sys: Registered thermal governor 'step_wise'
574 18:02:05.024060 <6>[ 0.353745] cpuidle: using governor menu
575 18:02:05.051053 <6>[ 0.389366] No ATAGs?
576 18:02:05.057324 <6>[ 0.392101] hw-breakpoint: debug architecture 0x4 unsupported.
577 18:02:05.067432 <6>[ 0.404028] Serial: AMBA PL011 UART driver
578 18:02:05.097171 <6>[ 0.435234] iommu: Default domain type: Translated
579 18:02:05.106059 <6>[ 0.440585] iommu: DMA domain TLB invalidation policy: strict mode
580 18:02:05.133082 <5>[ 0.470591] SCSI subsystem initialized
581 18:02:05.138897 <6>[ 0.475468] usbcore: registered new interface driver usbfs
582 18:02:05.145019 <6>[ 0.481532] usbcore: registered new interface driver hub
583 18:02:05.151481 <6>[ 0.487315] usbcore: registered new device driver usb
584 18:02:05.159610 <6>[ 0.493819] pps_core: LinuxPPS API ver. 1 registered
585 18:02:05.168607 <6>[ 0.499205] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
586 18:02:05.175821 <6>[ 0.508944] PTP clock support registered
587 18:02:05.176255 <6>[ 0.513409] EDAC MC: Ver: 3.0.0
588 18:02:05.227565 <6>[ 0.563255] scmi_core: SCMI protocol bus registered
589 18:02:05.252139 <6>[ 0.589715] vgaarb: loaded
590 18:02:05.258136 <6>[ 0.593484] clocksource: Switched to clocksource dmtimer
591 18:02:05.282450 <6>[ 0.620390] NET: Registered PF_INET protocol family
592 18:02:05.295002 <6>[ 0.626088] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
593 18:02:05.302198 <6>[ 0.634919] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
594 18:02:05.313601 <6>[ 0.643848] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
595 18:02:05.319608 <6>[ 0.652090] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
596 18:02:05.325420 <6>[ 0.660382] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
597 18:02:05.331141 <6>[ 0.668104] TCP: Hash tables configured (established 4096 bind 4096)
598 18:02:05.342667 <6>[ 0.675023] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
599 18:02:05.348387 <6>[ 0.682034] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
600 18:02:05.354696 <6>[ 0.689650] NET: Registered PF_UNIX/PF_LOCAL protocol family
601 18:02:05.440718 <6>[ 0.773277] RPC: Registered named UNIX socket transport module.
602 18:02:05.441275 <6>[ 0.779714] RPC: Registered udp transport module.
603 18:02:05.449187 <6>[ 0.784838] RPC: Registered tcp transport module.
604 18:02:05.455010 <6>[ 0.789941] RPC: Registered tcp-with-tls transport module.
605 18:02:05.461090 <6>[ 0.795863] RPC: Registered tcp NFSv4.1 backchannel transport module.
606 18:02:05.468182 <6>[ 0.802769] PCI: CLS 0 bytes, default 64
607 18:02:05.470666 <5>[ 0.808553] Initialise system trusted keyrings
608 18:02:05.493446 <6>[ 0.828639] Trying to unpack rootfs image as initramfs...
609 18:02:05.572373 <6>[ 0.904443] workingset: timestamp_bits=30 max_order=17 bucket_order=0
610 18:02:05.577233 <6>[ 0.911951] squashfs: version 4.0 (2009/01/31) Phillip Lougher
611 18:02:05.616574 <5>[ 0.954230] NFS: Registering the id_resolver key type
612 18:02:05.622909 <5>[ 0.959895] Key type id_resolver registered
613 18:02:05.627689 <5>[ 0.964586] Key type id_legacy registered
614 18:02:05.633425 <6>[ 0.969027] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
615 18:02:05.643338 <6>[ 0.976238] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
616 18:02:05.711990 <5>[ 1.050306] Key type asymmetric registered
617 18:02:05.717751 <5>[ 1.054883] Asymmetric key parser 'x509' registered
618 18:02:05.726251 <6>[ 1.060308] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
619 18:02:05.731891 <6>[ 1.068226] io scheduler mq-deadline registered
620 18:02:05.739809 <6>[ 1.073155] io scheduler kyber registered
621 18:02:05.740290 <6>[ 1.077648] io scheduler bfq registered
622 18:02:05.860715 <6>[ 1.195502] ledtrig-cpu: registered to indicate activity on CPUs
623 18:02:06.160220 <6>[ 1.494627] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
624 18:02:06.190905 <6>[ 1.528898] msm_serial: driver initialized
625 18:02:06.196807 <6>[ 1.533931] SuperH (H)SCI(F) driver initialized
626 18:02:06.202724 <6>[ 1.539048] STMicroelectronics ASC driver initialized
627 18:02:06.207963 <6>[ 1.544731] STM32 USART driver initialized
628 18:02:06.312538 <6>[ 1.651133] brd: module loaded
629 18:02:06.356575 <6>[ 1.694231] loop: module loaded
630 18:02:06.393438 <6>[ 1.730925] CAN device driver interface
631 18:02:06.399945 <6>[ 1.736200] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
632 18:02:06.405763 <6>[ 1.743102] e1000e: Intel(R) PRO/1000 Network Driver
633 18:02:06.411681 <6>[ 1.748570] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
634 18:02:06.417301 <6>[ 1.755010] igb: Intel(R) Gigabit Ethernet Network Driver
635 18:02:06.425644 <6>[ 1.760833] igb: Copyright (c) 2007-2014 Intel Corporation.
636 18:02:06.437381 <6>[ 1.769972] pegasus: Pegasus/Pegasus II USB Ethernet driver
637 18:02:06.443076 <6>[ 1.776118] usbcore: registered new interface driver pegasus
638 18:02:06.448864 <6>[ 1.782246] usbcore: registered new interface driver asix
639 18:02:06.454703 <6>[ 1.788129] usbcore: registered new interface driver ax88179_178a
640 18:02:06.460395 <6>[ 1.794716] usbcore: registered new interface driver cdc_ether
641 18:02:06.466275 <6>[ 1.801015] usbcore: registered new interface driver smsc75xx
642 18:02:06.472125 <6>[ 1.807246] usbcore: registered new interface driver smsc95xx
643 18:02:06.477828 <6>[ 1.813486] usbcore: registered new interface driver net1080
644 18:02:06.483639 <6>[ 1.819610] usbcore: registered new interface driver cdc_subset
645 18:02:06.489438 <6>[ 1.826029] usbcore: registered new interface driver zaurus
646 18:02:06.497031 <6>[ 1.832070] usbcore: registered new interface driver cdc_ncm
647 18:02:06.506748 <6>[ 1.841415] usbcore: registered new interface driver usb-storage
648 18:02:06.782517 <6>[ 2.118886] i2c_dev: i2c /dev entries driver
649 18:02:06.839830 <5>[ 2.170124] cpuidle: enable-method property 'ti,am3352' found operations
650 18:02:06.845627 <6>[ 2.179730] sdhci: Secure Digital Host Controller Interface driver
651 18:02:06.852993 <6>[ 2.186518] sdhci: Copyright(c) Pierre Ossman
652 18:02:06.860332 <6>[ 2.192881] Synopsys Designware Multimedia Card Interface Driver
653 18:02:06.865893 <6>[ 2.200781] sdhci-pltfm: SDHCI platform and OF driver helper
654 18:02:06.993840 <6>[ 2.324691] usbcore: registered new interface driver usbhid
655 18:02:06.994216 <6>[ 2.330732] usbhid: USB HID core driver
656 18:02:07.024465 <6>[ 2.360229] NET: Registered PF_INET6 protocol family
657 18:02:07.056964 <6>[ 2.395325] Segment Routing with IPv6
658 18:02:07.062962 <6>[ 2.399469] In-situ OAM (IOAM) with IPv6
659 18:02:07.069577 <6>[ 2.404015] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
660 18:02:07.076948 <6>[ 2.411240] NET: Registered PF_PACKET protocol family
661 18:02:07.083246 <6>[ 2.416807] can: controller area network core
662 18:02:07.083504 <6>[ 2.421642] NET: Registered PF_CAN protocol family
663 18:02:07.088648 <6>[ 2.426874] can: raw protocol
664 18:02:07.094366 <6>[ 2.430200] can: broadcast manager protocol
665 18:02:07.101176 <6>[ 2.434796] can: netlink gateway - max_hops=1
666 18:02:07.101412 <5>[ 2.440280] Key type dns_resolver registered
667 18:02:07.106995 <6>[ 2.445352] ThumbEE CPU extension supported.
668 18:02:07.113269 <5>[ 2.450036] Registering SWP/SWPB emulation handler
669 18:02:07.121403 <3>[ 2.455743] omap_voltage_late_init: Voltage driver support not added
670 18:02:07.328299 <5>[ 2.664059] Loading compiled-in X.509 certificates
671 18:02:07.471123 <6>[ 2.796471] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
672 18:02:07.478271 <6>[ 2.813109] pinctrl-single 44e10800.pinmux: 142 pins, size 568
673 18:02:07.504050 <3>[ 2.836922] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
674 18:02:07.691143 <3>[ 3.023313] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
675 18:02:07.877982 <6>[ 3.214412] OMAP GPIO hardware version 0.1
676 18:02:07.897923 <6>[ 3.233056] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
677 18:02:08.011132 <4>[ 3.345339] at24 2-0054: supply vcc not found, using dummy regulator
678 18:02:08.047334 <4>[ 3.381599] at24 2-0055: supply vcc not found, using dummy regulator
679 18:02:08.085012 <4>[ 3.419259] at24 2-0056: supply vcc not found, using dummy regulator
680 18:02:08.133612 <4>[ 3.467709] at24 2-0057: supply vcc not found, using dummy regulator
681 18:02:08.172817 <6>[ 3.507852] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
682 18:02:08.248565 <3>[ 3.579534] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
683 18:02:08.272849 <6>[ 3.600379] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
684 18:02:08.295419 <4>[ 3.626584] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
685 18:02:08.302599 <4>[ 3.635798] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
686 18:02:08.439719 <6>[ 3.774144] omap_rng 48310000.rng: Random Number Generator ver. 20
687 18:02:08.463298 <5>[ 3.800390] random: crng init done
688 18:02:08.505045 <6>[ 3.842844] Freeing initrd memory: 14448K
689 18:02:08.513794 <6>[ 3.847589] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
690 18:02:08.564168 <6>[ 3.895973] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
691 18:02:08.569968 <6>[ 3.906343] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
692 18:02:08.581784 <6>[ 3.913690] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
693 18:02:08.587574 <6>[ 3.921122] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
694 18:02:08.598795 <6>[ 3.929254] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
695 18:02:08.606101 <6>[ 3.940886] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
696 18:02:08.618452 <5>[ 3.949898] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
697 18:02:08.647140 <3>[ 3.979665] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
698 18:02:08.651886 <6>[ 3.988261] edma 49000000.dma: TI EDMA DMA engine driver
699 18:02:08.722974 <3>[ 4.055853] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
700 18:02:08.737612 <6>[ 4.070216] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
701 18:02:08.751579 <3>[ 4.087328] l3-aon-clkctrl:0000:0: failed to disable
702 18:02:08.804701 <6>[ 4.137254] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
703 18:02:08.810363 <6>[ 4.146770] printk: legacy console [ttyS0] enabled
704 18:02:08.816187 <6>[ 4.146770] printk: legacy console [ttyS0] enabled
705 18:02:08.821763 <6>[ 4.157101] printk: legacy bootconsole [omap8250] disabled
706 18:02:08.826665 <6>[ 4.157101] printk: legacy bootconsole [omap8250] disabled
707 18:02:08.862645 <4>[ 4.194241] tps65217-pmic: Failed to locate of_node [id: -1]
708 18:02:08.865368 <4>[ 4.201638] tps65217-bl: Failed to locate of_node [id: -1]
709 18:02:08.882640 <6>[ 4.221259] tps65217 0-0024: TPS65217 ID 0xe version 1.2
710 18:02:08.901145 <6>[ 4.228213] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
711 18:02:08.912750 <6>[ 4.241895] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
712 18:02:08.917436 <6>[ 4.253771] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
713 18:02:08.940588 <6>[ 4.273410] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
714 18:02:08.946459 <6>[ 4.282675] sdhci-omap 48060000.mmc: Got CD GPIO
715 18:02:08.953613 <4>[ 4.287861] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
716 18:02:08.969348 <4>[ 4.301481] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
717 18:02:08.975644 <4>[ 4.310203] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
718 18:02:08.985111 <4>[ 4.318796] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
719 18:02:09.108901 <6>[ 4.442892] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
720 18:02:09.144948 <6>[ 4.479059] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
721 18:02:09.157841 <6>[ 4.489912] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
722 18:02:09.164194 <6>[ 4.498891] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
723 18:02:09.231648 <6>[ 4.560760] mmc1: new high speed MMC card at address 0001
724 18:02:09.232241 <6>[ 4.568041] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
725 18:02:09.245193 <6>[ 4.576719] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
726 18:02:09.253076 <6>[ 4.589103] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
727 18:02:09.261404 <6>[ 4.597373] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
728 18:02:09.270371 <6>[ 4.605879] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
729 18:02:09.291771 <6>[ 4.622092] mmc0: new high speed SDHC card at address aaaa
730 18:02:09.292355 <6>[ 4.629091] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
731 18:02:09.323835 <6>[ 4.660201] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
732 18:02:11.422040 <6>[ 6.754528] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
733 18:02:11.535289 <5>[ 6.793583] Sending DHCP requests ., OK
734 18:02:11.546624 <6>[ 6.878035] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.8
735 18:02:11.547201 <6>[ 6.886115] IP-Config: Complete:
736 18:02:11.557928 <6>[ 6.889654] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.6.8, mask=255.255.255.0, gw=192.168.6.1
737 18:02:11.563597 <6>[ 6.900086] host=192.168.6.8, domain=, nis-domain=(none)
738 18:02:11.569459 <6>[ 6.906212] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
739 18:02:11.576075 <6>[ 6.906245] nameserver0=10.255.253.1
740 18:02:11.582134 <6>[ 6.918874] clk: Disabling unused clocks
741 18:02:11.586730 <6>[ 6.923609] PM: genpd: Disabling unused power domains
742 18:02:11.606155 <6>[ 6.942113] Freeing unused kernel image (initmem) memory: 2048K
743 18:02:11.613690 <6>[ 6.951875] Run /init as init process
744 18:02:11.640578 Loading, please wait...
745 18:02:11.715744 Starting systemd-udevd version 252.22-1~deb12u1
746 18:02:14.770223 <4>[ 10.075491] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
747 18:02:14.983799 <4>[ 10.315067] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
748 18:02:15.144169 <6>[ 10.482762] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
749 18:02:15.154993 <6>[ 10.488667] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
750 18:02:15.397423 <6>[ 10.734544] hub 1-0:1.0: USB hub found
751 18:02:15.420156 <6>[ 10.756974] tda998x 0-0070: found TDA19988
752 18:02:15.444492 <6>[ 10.782243] hub 1-0:1.0: 1 port detected
753 18:02:18.767381 Begin: Loading essential drivers ... done.
754 18:02:18.768037 Begin: Running /scripts/init-premount ... done.
755 18:02:18.769482 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
756 18:02:18.770047 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
757 18:02:18.770304 Device /sys/class/net/eth0 found
758 18:02:18.770537 done.
759 18:02:18.770764 Begin: Waiting up to 180 secs for any network device to become available ... done.
760 18:02:18.771044 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
761 18:02:18.845077 IP-Config: eth0 guessed broadcast address 192.168.6.255
762 18:02:18.850596 IP-Config: eth0 complete (dhcp from 192.168.6.1):
763 18:02:18.856183 address: 192.168.6.8 broadcast: 192.168.6.255 netmask: 255.255.255.0
764 18:02:18.867276 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
765 18:02:18.867797 rootserver: 192.168.6.1 rootpath:
766 18:02:18.870711 filename :
767 18:02:18.980845 done.
768 18:02:18.991873 Begin: Running /scripts/nfs-bottom ... done.
769 18:02:19.055807 Begin: Running /scripts/init-bottom ... done.
770 18:02:20.572710 <30>[ 15.907273] systemd[1]: System time before build time, advancing clock.
771 18:02:20.746365 <30>[ 16.054728] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
772 18:02:20.755234 <30>[ 16.091640] systemd[1]: Detected architecture arm.
773 18:02:20.769580
774 18:02:20.770191 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
775 18:02:20.770670
776 18:02:20.798888 <30>[ 16.134031] systemd[1]: Hostname set to <debian-bookworm-armhf>.
777 18:02:22.977550 <30>[ 18.311273] systemd[1]: Queued start job for default target graphical.target.
778 18:02:22.994465 <30>[ 18.326285] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
779 18:02:23.002073 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
780 18:02:23.024712 <30>[ 18.356698] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
781 18:02:23.033102 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
782 18:02:23.054922 <30>[ 18.386944] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
783 18:02:23.063181 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
784 18:02:23.082998 <30>[ 18.415423] systemd[1]: Created slice user.slice - User and Session Slice.
785 18:02:23.089681 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
786 18:02:23.118268 <30>[ 18.444984] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
787 18:02:23.124340 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
788 18:02:23.142136 <30>[ 18.474597] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
789 18:02:23.153259 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
790 18:02:23.183181 <30>[ 18.504642] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
791 18:02:23.189614 <30>[ 18.525112] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
792 18:02:23.198160 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
793 18:02:23.221266 <30>[ 18.553967] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
794 18:02:23.229612 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
795 18:02:23.252022 <30>[ 18.584372] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
796 18:02:23.260433 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
797 18:02:23.282019 <30>[ 18.614555] systemd[1]: Reached target paths.target - Path Units.
798 18:02:23.287129 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
799 18:02:23.311528 <30>[ 18.644157] systemd[1]: Reached target remote-fs.target - Remote File Systems.
800 18:02:23.318987 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
801 18:02:23.341410 <30>[ 18.674035] systemd[1]: Reached target slices.target - Slice Units.
802 18:02:23.346959 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
803 18:02:23.371590 <30>[ 18.704238] systemd[1]: Reached target swap.target - Swaps.
804 18:02:23.375744 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
805 18:02:23.401793 <30>[ 18.734237] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
806 18:02:23.410760 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
807 18:02:23.433007 <30>[ 18.765249] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
808 18:02:23.441200 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
809 18:02:23.523192 <30>[ 18.850692] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
810 18:02:23.535792 <30>[ 18.868057] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
811 18:02:23.543732 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
812 18:02:23.573406 <30>[ 18.905228] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
813 18:02:23.580809 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
814 18:02:23.604971 <30>[ 18.937130] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
815 18:02:23.613153 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
816 18:02:23.636345 <30>[ 18.968541] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
817 18:02:23.642081 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
818 18:02:23.675603 <30>[ 19.006879] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
819 18:02:23.683112 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
820 18:02:23.708480 <30>[ 19.035065] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
821 18:02:23.725051 <30>[ 19.051478] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
822 18:02:23.771423 <30>[ 19.104046] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
823 18:02:23.779020 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
824 18:02:23.810176 <30>[ 19.143227] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
825 18:02:23.844375 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
826 18:02:23.914208 <30>[ 19.246385] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
827 18:02:23.959641 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
828 18:02:24.012180 <30>[ 19.345039] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
829 18:02:24.041541 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
830 18:02:24.092802 <30>[ 19.425423] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
831 18:02:24.112045 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
832 18:02:24.143369 <30>[ 19.477163] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
833 18:02:24.170098 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
834 18:02:24.224279 <30>[ 19.556808] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
835 18:02:24.250344 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
836 18:02:24.303180 <30>[ 19.636764] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
837 18:02:24.330300 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
838 18:02:24.381320 <30>[ 19.714878] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
839 18:02:24.403222 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
840 18:02:24.439278 <28>[ 19.765753] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
841 18:02:24.447752 <28>[ 19.780443] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
842 18:02:24.490878 <30>[ 19.824884] systemd[1]: Starting systemd-journald.service - Journal Service...
843 18:02:24.502131 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
844 18:02:24.581318 <30>[ 19.914494] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
845 18:02:24.594350 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
846 18:02:24.653101 <30>[ 19.986662] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
847 18:02:24.674911 Starting [0;1;39msystemd-network-g… units from Kernel command line...
848 18:02:24.741867 <30>[ 20.074926] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
849 18:02:24.763603 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
850 18:02:24.839920 <30>[ 20.172873] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
851 18:02:24.893801 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
852 18:02:24.948551 <30>[ 20.283265] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
853 18:02:25.021119 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
854 18:02:25.044255 <30>[ 20.377786] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
855 18:02:25.102894 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
856 18:02:25.132221 <30>[ 20.464563] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
857 18:02:25.159067 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
858 18:02:25.342275 <30>[ 20.676403] systemd[1]: modprobe@configfs.service: Deactivated successfully.
859 18:02:25.372249 <30>[ 20.705321] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
860 18:02:25.401249 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
861 18:02:25.422086 <30>[ 20.756331] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
862 18:02:25.462305 <30>[ 20.795670] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
863 18:02:25.491464 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
864 18:02:25.512760 <30>[ 20.845354] systemd[1]: Started systemd-journald.service - Journal Service.
865 18:02:25.519583 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
866 18:02:25.559202 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
867 18:02:25.591493 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
868 18:02:25.622498 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
869 18:02:25.646421 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
870 18:02:25.683783 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
871 18:02:25.705742 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
872 18:02:25.733832 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
873 18:02:25.755702 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
874 18:02:25.811650 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
875 18:02:25.854849 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
876 18:02:25.923176 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
877 18:02:26.033751 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
878 18:02:26.152757 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
879 18:02:26.190537 <46>[ 21.523876] systemd-journald[164]: Received client request to flush runtime journal.
880 18:02:26.287587 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
881 18:02:26.355948 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
882 18:02:27.166604 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
883 18:02:27.496183 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
884 18:02:27.553658 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
885 18:02:27.875805 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
886 18:02:28.105376 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
887 18:02:28.141061 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
888 18:02:28.161168 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
889 18:02:28.243671 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
890 18:02:28.290340 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
891 18:02:29.328602 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
892 18:02:29.381478 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
893 18:02:29.923408 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
894 18:02:30.041381 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
895 18:02:30.188247 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
896 18:02:31.967547 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
897 18:02:32.196143 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
898 18:02:32.584404 <5>[ 27.917991] cfg80211: Loading compiled-in X.509 certificates for regulatory database
899 18:02:32.965973 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
900 18:02:33.755655 <5>[ 29.091551] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
901 18:02:33.843550 <5>[ 29.178658] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
902 18:02:33.857290 <4>[ 29.190825] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
903 18:02:33.863240 <6>[ 29.199932] cfg80211: failed to load regulatory.db
904 18:02:34.965451 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
905 18:02:35.000171 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
906 18:02:35.018350 <46>[ 30.342081] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
907 18:02:35.147095 <46>[ 30.473866] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
908 18:02:43.859897 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
909 18:02:43.888075 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
910 18:02:43.913038 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
911 18:02:43.933247 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
912 18:02:44.000526 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
913 18:02:44.043291 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
914 18:02:44.103146 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
915 18:02:44.189970 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
916 18:02:44.237281 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
917 18:02:44.272161 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
918 18:02:44.296796 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
919 18:02:44.326713 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
920 18:02:44.367815 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
921 18:02:44.399069 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
922 18:02:44.432230 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
923 18:02:44.462032 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
924 18:02:44.490989 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
925 18:02:44.526318 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
926 18:02:44.552560 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
927 18:02:44.570844 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
928 18:02:44.601511 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
929 18:02:44.621947 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
930 18:02:44.648202 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
931 18:02:44.722115 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
932 18:02:44.773630 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
933 18:02:44.878352 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
934 18:02:44.972980 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
935 18:02:45.043618 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
936 18:02:45.096578 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
937 18:02:45.126494 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
938 18:02:45.310633 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
939 18:02:45.385328 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
940 18:02:45.442230 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
941 18:02:45.493304 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
942 18:02:45.512161 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
943 18:02:45.649150 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
944 18:02:45.977343 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
945 18:02:46.035053 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
946 18:02:46.078560 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
947 18:02:46.162419 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
948 18:02:46.332613 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
949 18:02:46.446267
950 18:02:46.450450 Debian GNU/Linux 12 debianrm-armhf login: root (automatic login)
951 18:02:46.451009
952 18:02:46.806441 Linux debian-bookworm-armhf 6.12.0-rc2 #1 SMP Tue Nov 5 17:30:01 UTC 2024 armv7l
953 18:02:46.807572
954 18:02:46.812111 The programs included with the Debian GNU/Linux system are free software;
955 18:02:46.817637 the exact distribution terms for each program are described in the
956 18:02:46.823446 individual files in /usr/share/doc/*/copyright.
957 18:02:46.824631
958 18:02:46.831429 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
959 18:02:46.832556 permitted by applicable law.
960 18:02:51.922089 Unable to match end of the kernel message
962 18:02:51.923043 Setting prompt string to ['/ #']
963 18:02:51.923385 end: 2.4.4.1 login-action (duration 00:00:48) [common]
965 18:02:51.924170 end: 2.4.4 auto-login-action (duration 00:00:49) [common]
966 18:02:51.924495 start: 2.4.5 expect-shell-connection (timeout 00:03:12) [common]
967 18:02:51.924765 Setting prompt string to ['/ #']
968 18:02:51.925006 Forcing a shell prompt, looking for ['/ #']
970 18:02:51.975607 / #
971 18:02:51.976267 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
972 18:02:51.976573 Waiting using forced prompt support (timeout 00:02:30)
973 18:02:51.981174
974 18:02:51.987369 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
975 18:02:51.987762 start: 2.4.6 export-device-env (timeout 00:03:12) [common]
976 18:02:51.988083 Sending with 10 millisecond of delay
978 18:02:56.980382 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/941318/extract-nfsrootfs-4a67tz5m'
979 18:02:56.991071 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/941318/extract-nfsrootfs-4a67tz5m'
980 18:02:56.992372 Sending with 10 millisecond of delay
982 18:02:59.090960 / # export NFS_SERVER_IP='192.168.6.3'
983 18:02:59.102280 export NFS_SERVER_IP='192.168.6.3'
984 18:02:59.104238 end: 2.4.6 export-device-env (duration 00:00:07) [common]
985 18:02:59.104649 end: 2.4 uboot-commands (duration 00:01:55) [common]
986 18:02:59.105007 end: 2 uboot-action (duration 00:01:55) [common]
987 18:02:59.105359 start: 3 lava-test-retry (timeout 00:06:54) [common]
988 18:02:59.105740 start: 3.1 lava-test-shell (timeout 00:06:54) [common]
989 18:02:59.106123 Using namespace: common
991 18:02:59.207266 / # #
992 18:02:59.208088 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
993 18:02:59.212924 #
994 18:02:59.218751 Using /lava-941318
996 18:02:59.319599 / # export SHELL=/bin/bash
997 18:02:59.325282 export SHELL=/bin/bash
999 18:02:59.432065 / # . /lava-941318/environment
1000 18:02:59.437267 . /lava-941318/environment
1002 18:02:59.551117 / # /lava-941318/bin/lava-test-runner /lava-941318/0
1003 18:02:59.551693 Test shell timeout: 10s (minimum of the action and connection timeout)
1004 18:02:59.556673 /lava-941318/bin/lava-test-runner /lava-941318/0
1005 18:02:59.972702 + export TESTRUN_ID=0_timesync-off
1006 18:02:59.980677 + TESTRUN_ID=0_timesync-off
1007 18:02:59.981221 + cd /lava-941318/0/tests/0_timesync-off
1008 18:02:59.981469 ++ cat uuid
1009 18:02:59.996775 + UUID=941318_1.6.2.4.1
1010 18:02:59.997474 + set +x
1011 18:03:00.005363 <LAVA_SIGNAL_STARTRUN 0_timesync-off 941318_1.6.2.4.1>
1012 18:03:00.005980 + systemctl stop systemd-timesyncd
1013 18:03:00.006792 Received signal: <STARTRUN> 0_timesync-off 941318_1.6.2.4.1
1014 18:03:00.007298 Starting test lava.0_timesync-off (941318_1.6.2.4.1)
1015 18:03:00.007912 Skipping test definition patterns.
1016 18:03:00.299350 + set +x
1017 18:03:00.300029 <LAVA_SIGNAL_ENDRUN 0_timesync-off 941318_1.6.2.4.1>
1018 18:03:00.300788 Received signal: <ENDRUN> 0_timesync-off 941318_1.6.2.4.1
1019 18:03:00.301345 Ending use of test pattern.
1020 18:03:00.301906 Ending test lava.0_timesync-off (941318_1.6.2.4.1), duration 0.29
1022 18:03:00.454283 + export TESTRUN_ID=1_kselftest-dt
1023 18:03:00.462210 + TESTRUN_ID=1_kselftest-dt
1024 18:03:00.462729 + cd /lava-941318/0/tests/1_kselftest-dt
1025 18:03:00.463180 ++ cat uuid
1026 18:03:00.478468 + UUID=941318_1.6.2.4.5
1027 18:03:00.479102 + set +x
1028 18:03:00.484028 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 941318_1.6.2.4.5>
1029 18:03:00.484613 + cd ./automated/linux/kselftest/
1030 18:03:00.485340 Received signal: <STARTRUN> 1_kselftest-dt 941318_1.6.2.4.5
1031 18:03:00.485804 Starting test lava.1_kselftest-dt (941318_1.6.2.4.5)
1032 18:03:00.486405 Skipping test definition patterns.
1033 18:03:00.514030 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-2-g08a3b241adfd9/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1034 18:03:00.622298 INFO: install_deps skipped
1035 18:03:01.248254 --2024-11-05 18:03:01-- http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-2-g08a3b241adfd9/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1036 18:03:01.287978 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1037 18:03:01.430423 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1038 18:03:01.573481 HTTP request sent, awaiting response... 200 OK
1039 18:03:01.574198 Length: 4097788 (3.9M) [application/octet-stream]
1040 18:03:01.578777 Saving to: 'kselftest_armhf.tar.gz'
1041 18:03:01.579275
1042 18:03:03.404200
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 180KB/s
kselftest_armhf.tar 4%[ ] 194.76K 346KB/s
kselftest_armhf.tar 19%[==> ] 768.95K 924KB/s
kselftest_armhf.tar 26%[====> ] 1.04M 1010KB/s
kselftest_armhf.tar 38%[======> ] 1.50M 1.19MB/s
kselftest_armhf.tar 67%[============> ] 2.63M 1.77MB/s
kselftest_armhf.tar 77%[==============> ] 3.04M 1.80MB/s
kselftest_armhf.tar 100%[===================>] 3.91M 2.14MB/s in 1.8s
1043 18:03:03.404642
1044 18:03:03.859253 2024-11-05 18:03:03 (2.14 MB/s) - 'kselftest_armhf.tar.gz' saved [4097788/4097788]
1045 18:03:03.859676
1046 18:03:18.333378 skiplist:
1047 18:03:18.333843 ========================================
1048 18:03:18.339053 ========================================
1049 18:03:18.455558 dt:test_unprobed_devices.sh
1050 18:03:18.493731 ============== Tests to run ===============
1051 18:03:18.500655 dt:test_unprobed_devices.sh
1052 18:03:18.504390 ===========End Tests to run ===============
1053 18:03:18.515542 shardfile-dt pass
1054 18:03:18.743400 <12>[ 74.082903] kselftest: Running tests in dt
1055 18:03:18.772402 TAP version 13
1056 18:03:18.795937 1..1
1057 18:03:18.849686 # timeout set to 45
1058 18:03:18.850305 # selftests: dt: test_unprobed_devices.sh
1059 18:03:19.681898 # TAP version 13
1060 18:03:44.545048 # 1..257
1061 18:03:44.721942 # ok 1 / # SKIP
1062 18:03:44.739832 # ok 2 /clk_mcasp0
1063 18:03:44.811872 # ok 3 /clk_mcasp0_fixed # SKIP
1064 18:03:44.882237 # ok 4 /cpus/cpu@0 # SKIP
1065 18:03:44.953585 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1066 18:03:44.976943 # ok 6 /fixedregulator0
1067 18:03:44.997935 # ok 7 /leds
1068 18:03:45.018786 # ok 8 /ocp
1069 18:03:45.042769 # ok 9 /ocp/interconnect@44c00000
1070 18:03:45.063303 # ok 10 /ocp/interconnect@44c00000/segment@0
1071 18:03:45.089989 # ok 11 /ocp/interconnect@44c00000/segment@100000
1072 18:03:45.114626 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1073 18:03:45.184831 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1074 18:03:45.205942 # ok 14 /ocp/interconnect@44c00000/segment@200000
1075 18:03:45.223967 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1076 18:03:45.332946 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1077 18:03:45.401132 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1078 18:03:45.476334 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1079 18:03:45.546688 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1080 18:03:45.617455 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1081 18:03:45.686934 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1082 18:03:45.758563 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1083 18:03:45.825625 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1084 18:03:45.897324 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1085 18:03:45.974137 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1086 18:03:46.038774 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1087 18:03:46.109933 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1088 18:03:46.179795 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1089 18:03:46.254620 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1090 18:03:46.324132 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1091 18:03:46.394850 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1092 18:03:46.464180 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1093 18:03:46.535071 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1094 18:03:46.604190 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1095 18:03:46.675715 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1096 18:03:46.744726 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1097 18:03:46.816170 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1098 18:03:46.888867 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1099 18:03:46.955470 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1100 18:03:47.025386 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1101 18:03:47.095604 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1102 18:03:47.166577 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1103 18:03:47.237006 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1104 18:03:47.308592 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1105 18:03:47.380061 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1106 18:03:47.452964 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1107 18:03:47.525952 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1108 18:03:47.590881 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1109 18:03:47.665967 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1110 18:03:47.731916 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1111 18:03:47.806994 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1112 18:03:47.873177 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1113 18:03:47.943659 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1114 18:03:48.014820 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1115 18:03:48.084258 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1116 18:03:48.154204 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1117 18:03:48.224847 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1118 18:03:48.294483 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1119 18:03:48.364843 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1120 18:03:48.437350 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1121 18:03:48.508196 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1122 18:03:48.581048 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1123 18:03:48.648625 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1124 18:03:48.721185 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1125 18:03:48.794538 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1126 18:03:48.866412 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1127 18:03:48.937769 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1128 18:03:49.007571 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1129 18:03:49.077780 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1130 18:03:49.149439 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1131 18:03:49.216626 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1132 18:03:49.287781 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1133 18:03:49.359115 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1134 18:03:49.431803 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1135 18:03:49.503063 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1136 18:03:49.573990 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1137 18:03:49.644548 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1138 18:03:49.714586 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1139 18:03:49.785231 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1140 18:03:49.855721 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1141 18:03:49.926438 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1142 18:03:49.997469 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1143 18:03:50.067510 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1144 18:03:50.141115 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1145 18:03:50.213596 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1146 18:03:50.284744 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1147 18:03:50.354954 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1148 18:03:50.425236 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1149 18:03:50.497592 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1150 18:03:50.569650 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1151 18:03:50.638290 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1152 18:03:50.709893 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1153 18:03:50.775756 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1154 18:03:50.846671 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1155 18:03:50.870000 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1156 18:03:50.889677 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1157 18:03:50.913076 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1158 18:03:50.942518 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1159 18:03:50.959729 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1160 18:03:50.986935 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1161 18:03:51.009444 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1162 18:03:51.030879 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1163 18:03:51.136787 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1164 18:03:51.165790 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1165 18:03:51.182590 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1166 18:03:51.206827 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1167 18:03:51.309099 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1168 18:03:51.381616 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1169 18:03:51.456642 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1170 18:03:51.523435 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1171 18:03:51.593514 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1172 18:03:51.663710 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1173 18:03:51.734393 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1174 18:03:51.805142 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1175 18:03:51.876523 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1176 18:03:51.956807 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1177 18:03:52.024118 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1178 18:03:52.095170 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1179 18:03:52.165623 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1180 18:03:52.238076 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1181 18:03:52.309035 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1182 18:03:52.380066 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1183 18:03:52.405346 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1184 18:03:52.472070 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1185 18:03:52.539518 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1186 18:03:52.611491 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1187 18:03:52.635764 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1188 18:03:52.702938 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1189 18:03:52.732987 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1190 18:03:52.795958 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1191 18:03:52.817918 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1192 18:03:52.841477 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1193 18:03:52.865801 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1194 18:03:52.892565 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1195 18:03:52.915376 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1196 18:03:52.936259 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1197 18:03:52.965415 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1198 18:03:53.038074 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1199 18:03:53.055472 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1200 18:03:53.078996 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1201 18:03:53.154222 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1202 18:03:53.225170 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1203 18:03:53.245740 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1204 18:03:53.349717 # not ok 144 /ocp/interconnect@47c00000
1205 18:03:53.418084 # not ok 145 /ocp/interconnect@47c00000/segment@0
1206 18:03:53.439708 # ok 146 /ocp/interconnect@48000000
1207 18:03:53.462480 # ok 147 /ocp/interconnect@48000000/segment@0
1208 18:03:53.482890 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1209 18:03:53.506212 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1210 18:03:53.533449 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1211 18:03:53.554660 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1212 18:03:53.575410 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1213 18:03:53.603409 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1214 18:03:53.625529 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1215 18:03:53.695639 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1216 18:03:53.769700 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1217 18:03:53.787727 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1218 18:03:53.812083 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1219 18:03:53.834311 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1220 18:03:53.858512 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1221 18:03:53.880625 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1222 18:03:53.906212 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1223 18:03:53.927279 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1224 18:03:53.951133 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1225 18:03:53.975537 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1226 18:03:54.002148 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1227 18:03:54.024432 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1228 18:03:54.046066 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1229 18:03:54.071223 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1230 18:03:54.091365 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1231 18:03:54.115689 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1232 18:03:54.138458 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1233 18:03:54.160557 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1234 18:03:54.186560 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1235 18:03:54.205746 # ok 175 /ocp/interconnect@48000000/segment@100000
1236 18:03:54.234808 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1237 18:03:54.256446 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1238 18:03:54.329137 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1239 18:03:54.405905 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1240 18:03:54.478534 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1241 18:03:54.548917 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1242 18:03:54.618222 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1243 18:03:54.687147 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1244 18:03:54.756511 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1245 18:03:54.830183 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1246 18:03:54.854117 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1247 18:03:54.876103 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1248 18:03:54.897857 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1249 18:03:54.925235 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1250 18:03:54.945951 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1251 18:03:54.970270 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1252 18:03:55.005307 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1253 18:03:55.032426 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1254 18:03:55.055600 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1255 18:03:55.075942 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1256 18:03:55.102434 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1257 18:03:55.126394 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1258 18:03:55.144110 # ok 198 /ocp/interconnect@48000000/segment@200000
1259 18:03:55.166427 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1260 18:03:55.241782 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1261 18:03:55.261585 # ok 201 /ocp/interconnect@48000000/segment@300000
1262 18:03:55.285508 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1263 18:03:55.310007 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1264 18:03:55.334341 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1265 18:03:55.357395 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1266 18:03:55.374998 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1267 18:03:55.398831 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1268 18:03:55.470146 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1269 18:03:55.487912 # ok 209 /ocp/interconnect@4a000000
1270 18:03:55.510856 # ok 210 /ocp/interconnect@4a000000/segment@0
1271 18:03:55.535291 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1272 18:03:55.563235 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1273 18:03:55.587116 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1274 18:03:55.605428 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1275 18:03:55.675476 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1276 18:03:55.781909 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1277 18:03:55.853303 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1278 18:03:55.966457 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1279 18:03:56.036135 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1280 18:03:56.110621 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1281 18:03:56.208867 # not ok 221 /ocp/interconnect@4b140000
1282 18:03:56.283300 # not ok 222 /ocp/interconnect@4b140000/segment@0
1283 18:03:56.354431 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1284 18:03:56.375059 # ok 224 /ocp/target-module@40300000
1285 18:03:56.401746 # ok 225 /ocp/target-module@40300000/sram@0
1286 18:03:56.485595 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1287 18:03:56.560611 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1288 18:03:56.575414 # ok 228 /ocp/target-module@47400000
1289 18:03:56.603606 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1290 18:03:56.624075 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1291 18:03:56.644082 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1292 18:03:56.664887 # ok 232 /ocp/target-module@47400000/usb@1400
1293 18:03:56.691842 # ok 233 /ocp/target-module@47400000/usb@1800
1294 18:03:56.709020 # ok 234 /ocp/target-module@47810000
1295 18:03:56.732928 # ok 235 /ocp/target-module@49000000
1296 18:03:56.759206 # ok 236 /ocp/target-module@49000000/dma@0
1297 18:03:56.780317 # ok 237 /ocp/target-module@49800000
1298 18:03:56.798786 # ok 238 /ocp/target-module@49800000/dma@0
1299 18:03:56.822912 # ok 239 /ocp/target-module@49900000
1300 18:03:56.850625 # ok 240 /ocp/target-module@49900000/dma@0
1301 18:03:56.865702 # ok 241 /ocp/target-module@49a00000
1302 18:03:56.893282 # ok 242 /ocp/target-module@49a00000/dma@0
1303 18:03:56.911588 # ok 243 /ocp/target-module@4c000000
1304 18:03:56.982987 # not ok 244 /ocp/target-module@4c000000/emif@0
1305 18:03:57.008433 # ok 245 /ocp/target-module@50000000
1306 18:03:57.025980 # ok 246 /ocp/target-module@53100000
1307 18:03:57.102034 # not ok 247 /ocp/target-module@53100000/sham@0
1308 18:03:57.122905 # ok 248 /ocp/target-module@53500000
1309 18:03:57.190129 # not ok 249 /ocp/target-module@53500000/aes@0
1310 18:03:57.211417 # ok 250 /ocp/target-module@56000000
1311 18:03:57.315687 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1312 18:03:57.382126 # ok 252 /opp-table # SKIP
1313 18:03:57.451684 # ok 253 /soc # SKIP
1314 18:03:57.471441 # ok 254 /sound
1315 18:03:57.499878 # ok 255 /target-module@4b000000
1316 18:03:57.524612 # ok 256 /target-module@4b000000/target-module@140000
1317 18:03:57.540463 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1318 18:03:57.549024 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1319 18:03:57.555993 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1320 18:03:59.731951 dt_test_unprobed_devices_sh_ skip
1321 18:03:59.737176 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1322 18:03:59.742777 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1323 18:03:59.743168 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1324 18:03:59.751809 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1325 18:03:59.752394 dt_test_unprobed_devices_sh_fixedregulator0 pass
1326 18:03:59.757481 dt_test_unprobed_devices_sh_leds pass
1327 18:03:59.762977 dt_test_unprobed_devices_sh_ocp pass
1328 18:03:59.763395 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1329 18:03:59.774238 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1330 18:03:59.779816 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1331 18:03:59.785547 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1332 18:03:59.796674 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1333 18:03:59.802286 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1334 18:03:59.807878 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1335 18:03:59.819251 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1336 18:03:59.824774 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1337 18:03:59.836066 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1338 18:03:59.847162 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1339 18:03:59.858420 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1340 18:03:59.869605 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1341 18:03:59.875189 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1342 18:03:59.886532 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1343 18:03:59.897592 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1344 18:03:59.908788 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1345 18:03:59.920014 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1346 18:03:59.925586 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1347 18:03:59.936795 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1348 18:03:59.948078 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1349 18:03:59.959198 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1350 18:03:59.970437 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1351 18:03:59.976098 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1352 18:03:59.987157 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1353 18:03:59.998358 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1354 18:04:00.009600 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1355 18:04:00.015195 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1356 18:04:00.026367 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1357 18:04:00.037602 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1358 18:04:00.048793 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1359 18:04:00.060035 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1360 18:04:00.071184 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1361 18:04:00.082411 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1362 18:04:00.093583 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1363 18:04:00.104733 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1364 18:04:00.115956 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1365 18:04:00.127125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1366 18:04:00.138326 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1367 18:04:00.149561 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1368 18:04:00.160688 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1369 18:04:00.171946 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1370 18:04:00.183127 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1371 18:04:00.194285 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1372 18:04:00.205548 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1373 18:04:00.216704 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1374 18:04:00.227926 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1375 18:04:00.239175 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1376 18:04:00.250401 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1377 18:04:00.261611 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1378 18:04:00.267232 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1379 18:04:00.278548 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1380 18:04:00.289673 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1381 18:04:00.300799 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1382 18:04:00.312129 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1383 18:04:00.323369 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1384 18:04:00.334552 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1385 18:04:00.345767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1386 18:04:00.357022 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1387 18:04:00.368198 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1388 18:04:00.373892 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1389 18:04:00.385113 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1390 18:04:00.396320 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1391 18:04:00.407516 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1392 18:04:00.418910 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1393 18:04:00.429937 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1394 18:04:00.441154 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1395 18:04:00.452380 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1396 18:04:00.463523 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1397 18:04:00.474654 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1398 18:04:00.485903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1399 18:04:00.497121 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1400 18:04:00.508260 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1401 18:04:00.522177 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1402 18:04:00.532408 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1403 18:04:00.541849 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1404 18:04:00.547538 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1405 18:04:00.558569 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1406 18:04:00.569801 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1407 18:04:00.581021 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1408 18:04:00.592156 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1409 18:04:00.603408 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1410 18:04:00.614552 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1411 18:04:00.625736 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1412 18:04:00.636972 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1413 18:04:00.648120 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1414 18:04:00.659325 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1415 18:04:00.664963 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1416 18:04:00.676653 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1417 18:04:00.687344 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1418 18:04:00.693027 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1419 18:04:00.704154 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1420 18:04:00.715313 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1421 18:04:00.720955 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1422 18:04:00.732129 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1423 18:04:00.743343 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1424 18:04:00.748975 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1425 18:04:00.760402 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1426 18:04:00.771362 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1427 18:04:00.782565 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1428 18:04:00.793716 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1429 18:04:00.804954 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1430 18:04:00.816167 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1431 18:04:00.832996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1432 18:04:00.844241 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1433 18:04:00.855670 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1434 18:04:00.866742 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1435 18:04:00.878015 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1436 18:04:00.889167 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1437 18:04:00.900388 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1438 18:04:00.911617 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1439 18:04:00.928353 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1440 18:04:00.939614 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1441 18:04:00.956374 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1442 18:04:00.962072 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1443 18:04:00.973150 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1444 18:04:00.984333 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1445 18:04:00.989996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1446 18:04:01.001151 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1447 18:04:01.006833 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1448 18:04:01.017921 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1449 18:04:01.029128 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1450 18:04:01.034787 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1451 18:04:01.045931 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1452 18:04:01.051579 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1453 18:04:01.062669 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1454 18:04:01.068390 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1455 18:04:01.079478 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1456 18:04:01.090681 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1457 18:04:01.101924 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1458 18:04:01.107589 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1459 18:04:01.118691 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1460 18:04:01.129937 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1461 18:04:01.141077 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1462 18:04:01.146764 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1463 18:04:01.152374 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1464 18:04:01.157964 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1465 18:04:01.163631 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1466 18:04:01.169165 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1467 18:04:01.180260 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1468 18:04:01.185966 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1469 18:04:01.191553 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1470 18:04:01.202706 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1471 18:04:01.208316 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1472 18:04:01.219420 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1473 18:04:01.225069 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1474 18:04:01.236216 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1475 18:04:01.241884 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1476 18:04:01.252960 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1477 18:04:01.258686 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1478 18:04:01.264188 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1479 18:04:01.275354 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1480 18:04:01.281015 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1481 18:04:01.292130 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1482 18:04:01.297752 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1483 18:04:01.308924 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1484 18:04:01.314594 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1485 18:04:01.325680 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1486 18:04:01.331360 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1487 18:04:01.342533 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1488 18:04:01.348149 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1489 18:04:01.359288 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1490 18:04:01.364932 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1491 18:04:01.376045 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1492 18:04:01.381746 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1493 18:04:01.392804 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1494 18:04:01.398528 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1495 18:04:01.404132 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1496 18:04:01.415206 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1497 18:04:01.426381 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1498 18:04:01.437694 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1499 18:04:01.448843 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1500 18:04:01.460008 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1501 18:04:01.465766 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1502 18:04:01.476794 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1503 18:04:01.487996 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1504 18:04:01.499161 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1505 18:04:01.510383 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1506 18:04:01.516080 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1507 18:04:01.527180 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1508 18:04:01.532848 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1509 18:04:01.543962 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1510 18:04:01.549666 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1511 18:04:01.560795 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1512 18:04:01.566398 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1513 18:04:01.577607 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1514 18:04:01.583217 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1515 18:04:01.594341 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1516 18:04:01.600044 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1517 18:04:01.611025 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1518 18:04:01.616627 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1519 18:04:01.628000 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1520 18:04:01.633602 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1521 18:04:01.639190 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1522 18:04:01.650372 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1523 18:04:01.655950 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1524 18:04:01.667148 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1525 18:04:01.672869 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1526 18:04:01.683867 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1527 18:04:01.689564 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1528 18:04:01.695143 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1529 18:04:01.700808 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1530 18:04:01.714161 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1531 18:04:01.717404 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1532 18:04:01.729158 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1533 18:04:01.734337 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1534 18:04:01.745422 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1535 18:04:01.757508 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1536 18:04:01.767897 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1537 18:04:01.773497 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1538 18:04:01.784552 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1539 18:04:01.796047 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1540 18:04:01.802107 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1541 18:04:01.807400 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1542 18:04:01.812786 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1543 18:04:01.818249 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1544 18:04:01.823876 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1545 18:04:01.829545 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1546 18:04:01.835258 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1547 18:04:01.840729 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1548 18:04:01.851844 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1549 18:04:01.857596 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1550 18:04:01.863180 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1551 18:04:01.868815 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1552 18:04:01.874416 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1553 18:04:01.880981 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1554 18:04:01.885612 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1555 18:04:01.891200 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1556 18:04:01.897240 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1557 18:04:01.902465 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1558 18:04:01.908049 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1559 18:04:01.913608 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1560 18:04:01.920447 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1561 18:04:01.927489 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1562 18:04:01.930171 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1563 18:04:01.935767 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1564 18:04:01.941386 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1565 18:04:01.947021 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1566 18:04:01.952587 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1567 18:04:01.958235 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1568 18:04:01.963841 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1569 18:04:01.969500 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1570 18:04:01.975037 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1571 18:04:01.980642 dt_test_unprobed_devices_sh_opp-table skip
1572 18:04:01.980925 dt_test_unprobed_devices_sh_soc skip
1573 18:04:01.986253 dt_test_unprobed_devices_sh_sound pass
1574 18:04:01.991832 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1575 18:04:01.997680 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1576 18:04:02.003182 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1577 18:04:02.008769 dt_test_unprobed_devices_sh fail
1578 18:04:02.014502 + ../../utils/send-to-lava.sh ./output/result.txt
1579 18:04:02.020041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1580 18:04:02.021217 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1582 18:04:02.025743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1583 18:04:02.026292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1585 18:04:02.117723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1586 18:04:02.118367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1588 18:04:02.209927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1589 18:04:02.210856 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1591 18:04:02.304050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1592 18:04:02.304960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1594 18:04:02.399722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1595 18:04:02.400618 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1597 18:04:02.489406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1598 18:04:02.490330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1600 18:04:02.579259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1601 18:04:02.580149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1603 18:04:02.670555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1604 18:04:02.671476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1606 18:04:02.765054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1607 18:04:02.765963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1609 18:04:02.857393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1610 18:04:02.858402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1612 18:04:02.950334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1613 18:04:02.951241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1615 18:04:03.043806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1616 18:04:03.044726 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1618 18:04:03.136481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1619 18:04:03.137376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1621 18:04:03.226910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1622 18:04:03.227800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1624 18:04:03.319743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1625 18:04:03.320675 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1627 18:04:03.413024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1628 18:04:03.414069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1630 18:04:03.504463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1631 18:04:03.505379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1633 18:04:03.594595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1634 18:04:03.595487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1636 18:04:03.678959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1637 18:04:03.679968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1639 18:04:03.774503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1640 18:04:03.776181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1642 18:04:03.867562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1643 18:04:03.868202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1645 18:04:03.964131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1646 18:04:03.965045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1648 18:04:04.055527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1649 18:04:04.056444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1651 18:04:04.154958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1652 18:04:04.155883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1654 18:04:04.247808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1655 18:04:04.248715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1657 18:04:04.339122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1658 18:04:04.339993 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1660 18:04:04.434855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1661 18:04:04.435790 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1663 18:04:04.526253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1664 18:04:04.527338 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1666 18:04:04.618105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1667 18:04:04.619024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1669 18:04:04.710386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1670 18:04:04.711259 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1672 18:04:04.812704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1673 18:04:04.813601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1675 18:04:04.905552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1676 18:04:04.906451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1678 18:04:04.997488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1679 18:04:04.998341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1681 18:04:05.101529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1682 18:04:05.102445 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1684 18:04:05.190945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1685 18:04:05.191558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1687 18:04:05.285929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1688 18:04:05.286792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1690 18:04:05.377430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1691 18:04:05.378216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1693 18:04:05.469617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1694 18:04:05.470411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1696 18:04:05.559937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1697 18:04:05.560713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1699 18:04:05.651746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1700 18:04:05.652356 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1702 18:04:05.745248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1703 18:04:05.745858 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1705 18:04:05.846893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1706 18:04:05.847792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1708 18:04:05.941047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1709 18:04:05.941926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1711 18:04:06.036502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1712 18:04:06.037514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1714 18:04:06.126541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1715 18:04:06.127416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1717 18:04:06.218150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1718 18:04:06.219046 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1720 18:04:06.311029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1721 18:04:06.311903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1723 18:04:06.411435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1724 18:04:06.412317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1726 18:04:06.503971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1727 18:04:06.504875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1729 18:04:06.606008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1730 18:04:06.606915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1732 18:04:06.706718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1733 18:04:06.707766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1735 18:04:06.808935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1736 18:04:06.809938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1738 18:04:06.910312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1739 18:04:06.911371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1741 18:04:07.006999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1742 18:04:07.007995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1744 18:04:07.101165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1745 18:04:07.101830 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1747 18:04:07.208510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1748 18:04:07.209206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1750 18:04:07.304740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1751 18:04:07.305514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1753 18:04:07.398485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1754 18:04:07.399143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1756 18:04:07.491564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1757 18:04:07.492156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1759 18:04:07.588784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1760 18:04:07.589781 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1762 18:04:07.682462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1763 18:04:07.683419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1765 18:04:07.777244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1766 18:04:07.778216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1768 18:04:07.876616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1769 18:04:07.877298 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1771 18:04:07.973996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1772 18:04:07.974903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1774 18:04:08.087181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1775 18:04:08.088123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1777 18:04:08.187475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1778 18:04:08.188089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1780 18:04:08.280397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1781 18:04:08.280987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1783 18:04:08.380840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1784 18:04:08.381462 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1786 18:04:08.482254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1787 18:04:08.482876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1789 18:04:08.584558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1790 18:04:08.585430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1792 18:04:08.687082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1793 18:04:08.687888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1795 18:04:08.777874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1796 18:04:08.778656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1798 18:04:08.870127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1799 18:04:08.870886 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1801 18:04:08.961925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1802 18:04:08.962748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1804 18:04:09.056706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1805 18:04:09.057620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1807 18:04:09.147528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1808 18:04:09.148397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1810 18:04:09.240370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1811 18:04:09.241200 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1813 18:04:09.334941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1814 18:04:09.335720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1816 18:04:09.427388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1817 18:04:09.428258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1819 18:04:09.517606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1820 18:04:09.518491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1822 18:04:09.609353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1823 18:04:09.610224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1825 18:04:09.702691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1826 18:04:09.703538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1828 18:04:09.795974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1829 18:04:09.796829 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1831 18:04:09.886624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1832 18:04:09.887470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1834 18:04:09.977331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1835 18:04:09.978230 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1837 18:04:10.068590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1838 18:04:10.069435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1840 18:04:10.160151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1841 18:04:10.160990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1843 18:04:10.251706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1844 18:04:10.252488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1846 18:04:10.344530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1847 18:04:10.345330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1849 18:04:10.436931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1850 18:04:10.437837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1852 18:04:10.524780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1853 18:04:10.525466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1855 18:04:10.618548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1856 18:04:10.619111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1858 18:04:10.708669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1859 18:04:10.709545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1861 18:04:10.803377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1862 18:04:10.804273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1864 18:04:10.891641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1865 18:04:10.892570 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1867 18:04:10.983428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1868 18:04:10.984305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1870 18:04:11.074917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1871 18:04:11.075807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1873 18:04:11.166480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1874 18:04:11.167368 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1876 18:04:11.267386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1877 18:04:11.268291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1879 18:04:11.360842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1880 18:04:11.361764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1882 18:04:11.451966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1883 18:04:11.452837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1885 18:04:11.542913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1886 18:04:11.544025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1888 18:04:11.635369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1889 18:04:11.636270 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1891 18:04:11.726956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1892 18:04:11.727904 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1894 18:04:11.820185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1895 18:04:11.821072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1897 18:04:11.910725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1898 18:04:11.911631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1900 18:04:12.012601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1901 18:04:12.013707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1903 18:04:12.115882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1904 18:04:12.116756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1906 18:04:12.208367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1907 18:04:12.209266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1909 18:04:12.300604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1910 18:04:12.301535 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1912 18:04:12.392409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1913 18:04:12.393325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1915 18:04:12.483823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1916 18:04:12.484747 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1918 18:04:12.575934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1919 18:04:12.577110 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1921 18:04:12.665995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1922 18:04:12.666908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1924 18:04:12.756571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1925 18:04:12.757493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1927 18:04:12.842623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1928 18:04:12.844191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1930 18:04:12.934191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1931 18:04:12.935002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1933 18:04:13.027536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1934 18:04:13.028186 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1936 18:04:13.117509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1937 18:04:13.118160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1939 18:04:13.209541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1941 18:04:13.212603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1942 18:04:13.310398 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1944 18:04:13.313511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1945 18:04:13.411419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1947 18:04:13.414637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1948 18:04:13.514178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1949 18:04:13.514842 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1951 18:04:13.606579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1952 18:04:13.607169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1954 18:04:13.696947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1955 18:04:13.697617 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1957 18:04:13.789659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1958 18:04:13.790319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1960 18:04:13.880825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1961 18:04:13.881417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1963 18:04:13.973586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1964 18:04:13.974376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1966 18:04:14.065486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1967 18:04:14.066439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1969 18:04:14.158189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1970 18:04:14.159085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1972 18:04:14.250639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1973 18:04:14.251511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1975 18:04:14.343650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1976 18:04:14.344551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1978 18:04:14.434793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1979 18:04:14.435688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1981 18:04:14.527036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1982 18:04:14.527931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1984 18:04:14.619620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1985 18:04:14.620516 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1987 18:04:14.714256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1988 18:04:14.715204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1990 18:04:14.807940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1991 18:04:14.808810 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1993 18:04:14.901625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
1994 18:04:14.902258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
1996 18:04:15.001060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
1997 18:04:15.001692 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
1999 18:04:15.102236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2000 18:04:15.103021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2002 18:04:15.197646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2003 18:04:15.198281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2005 18:04:15.298683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2006 18:04:15.299274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2008 18:04:15.398063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2009 18:04:15.398681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2011 18:04:15.490039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2012 18:04:15.490675 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2014 18:04:15.583291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2015 18:04:15.584157 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2017 18:04:15.681111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2018 18:04:15.682018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2020 18:04:15.774939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2021 18:04:15.775834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2023 18:04:15.869953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2024 18:04:15.870834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2026 18:04:15.963070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2027 18:04:15.963952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2029 18:04:16.053948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2030 18:04:16.054787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2032 18:04:16.145740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2033 18:04:16.146615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2035 18:04:16.237238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2036 18:04:16.238126 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2038 18:04:16.330569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2039 18:04:16.331391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2041 18:04:16.422397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2042 18:04:16.423232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2044 18:04:16.514718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2045 18:04:16.515544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2047 18:04:16.606299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2048 18:04:16.607115 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2050 18:04:16.697565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2051 18:04:16.698434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2053 18:04:16.793581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2054 18:04:16.794453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2056 18:04:16.885322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2057 18:04:16.886188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2059 18:04:16.977008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2060 18:04:16.977892 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2062 18:04:17.078326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2063 18:04:17.079176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2065 18:04:17.176207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2066 18:04:17.177040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2068 18:04:17.269536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2069 18:04:17.270406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2071 18:04:17.374775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2072 18:04:17.375643 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2074 18:04:17.472884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2075 18:04:17.473786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2077 18:04:17.574475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2078 18:04:17.575372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2080 18:04:17.675105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2081 18:04:17.676004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2083 18:04:17.766926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2084 18:04:17.767831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2086 18:04:17.868640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2087 18:04:17.869683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2089 18:04:17.962756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2090 18:04:17.963663 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2092 18:04:18.055731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2093 18:04:18.056625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2095 18:04:18.150085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2096 18:04:18.150964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2098 18:04:18.241398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2099 18:04:18.242322 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2101 18:04:18.336211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2102 18:04:18.336970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2104 18:04:18.423121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2105 18:04:18.423763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2107 18:04:18.519685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2108 18:04:18.520326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2110 18:04:18.614279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2111 18:04:18.614883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2113 18:04:18.706188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2114 18:04:18.706807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2116 18:04:18.800074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2117 18:04:18.800666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2119 18:04:18.900173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2120 18:04:18.900760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2122 18:04:19.002280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2123 18:04:19.002919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2125 18:04:19.102473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2126 18:04:19.103396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2128 18:04:19.196480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2129 18:04:19.197382 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2131 18:04:19.287038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2132 18:04:19.287901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2134 18:04:19.388180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2135 18:04:19.389056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2137 18:04:19.482967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2138 18:04:19.483863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2140 18:04:19.575343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2141 18:04:19.576222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2143 18:04:19.667028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2144 18:04:19.667884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2146 18:04:19.761749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2147 18:04:19.762706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2149 18:04:19.855281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2150 18:04:19.856195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2152 18:04:19.948135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2153 18:04:19.951056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2155 18:04:20.039710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2156 18:04:20.040721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2158 18:04:20.133194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2159 18:04:20.133908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2161 18:04:20.223851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2162 18:04:20.224923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2164 18:04:20.314771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2165 18:04:20.315599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2167 18:04:20.407855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2168 18:04:20.408671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2170 18:04:20.503428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2171 18:04:20.504337 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2173 18:04:20.592118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2174 18:04:20.592802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2176 18:04:20.685225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2177 18:04:20.685913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2179 18:04:20.786890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2180 18:04:20.787538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2182 18:04:20.886287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2183 18:04:20.886973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2185 18:04:20.989094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2186 18:04:20.989804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2188 18:04:21.082818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2189 18:04:21.083719 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2191 18:04:21.174333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2192 18:04:21.175348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2194 18:04:21.265622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2195 18:04:21.266736 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2197 18:04:21.358040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2198 18:04:21.358938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2200 18:04:21.451628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2201 18:04:21.452542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2203 18:04:21.544323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2204 18:04:21.545249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2206 18:04:21.632614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2207 18:04:21.633715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2209 18:04:21.726317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2210 18:04:21.727244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2212 18:04:21.822310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2213 18:04:21.823249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2215 18:04:21.923820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2216 18:04:21.924710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2218 18:04:22.020909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2219 18:04:22.021787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2221 18:04:22.113325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2222 18:04:22.114247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2224 18:04:22.204151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2225 18:04:22.205030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2227 18:04:22.297699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2228 18:04:22.298645 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2230 18:04:22.391726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2231 18:04:22.392609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2233 18:04:22.483309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2234 18:04:22.484198 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2236 18:04:22.574712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2237 18:04:22.575584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2239 18:04:22.668383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2240 18:04:22.669229 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2242 18:04:22.755355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2243 18:04:22.756186 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2245 18:04:22.848423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2246 18:04:22.849313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2248 18:04:22.940856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2249 18:04:22.941729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2251 18:04:23.030645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2252 18:04:23.031509 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2254 18:04:23.123245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2255 18:04:23.124162 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2257 18:04:23.216970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2258 18:04:23.217935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2260 18:04:23.306167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2262 18:04:23.309181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2263 18:04:23.399299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2264 18:04:23.400199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2266 18:04:23.495081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2267 18:04:23.496007 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2269 18:04:23.584260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2270 18:04:23.585128 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2272 18:04:23.677441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2273 18:04:23.678339 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2275 18:04:23.766692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2276 18:04:23.767317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2278 18:04:23.858917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2279 18:04:23.859525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2281 18:04:23.949756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2282 18:04:23.950376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2284 18:04:24.040115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2285 18:04:24.040754 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2287 18:04:24.134113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2288 18:04:24.134724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2290 18:04:24.228372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2291 18:04:24.228979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2293 18:04:24.320315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2294 18:04:24.320907 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2296 18:04:24.412258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2297 18:04:24.413129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2299 18:04:24.503435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2300 18:04:24.504286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2302 18:04:24.594877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2303 18:04:24.595555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2305 18:04:24.687336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2306 18:04:24.688249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2308 18:04:24.778482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2309 18:04:24.779346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2311 18:04:24.872701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2312 18:04:24.873521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2314 18:04:24.966914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2315 18:04:24.967732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2317 18:04:25.059502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2318 18:04:25.060118 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2320 18:04:25.151588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2321 18:04:25.152474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2323 18:04:25.240752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2324 18:04:25.241605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2326 18:04:25.335564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2327 18:04:25.336470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2329 18:04:25.430304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2330 18:04:25.431177 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2332 18:04:25.521557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2333 18:04:25.522447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2335 18:04:25.610635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2336 18:04:25.611475 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2338 18:04:25.702635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2339 18:04:25.703235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2341 18:04:25.825488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2342 18:04:25.826353 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2344 18:04:25.928872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2345 18:04:25.929795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2347 18:04:26.034314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2348 18:04:26.035227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2350 18:04:26.135971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2351 18:04:26.136870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2353 18:04:26.235955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2354 18:04:26.236609 + set +x
2355 18:04:26.237344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2357 18:04:26.240290 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 941318_1.6.2.4.5>
2358 18:04:26.241076 Received signal: <ENDRUN> 1_kselftest-dt 941318_1.6.2.4.5
2359 18:04:26.241572 Ending use of test pattern.
2360 18:04:26.242059 Ending test lava.1_kselftest-dt (941318_1.6.2.4.5), duration 85.76
2362 18:04:26.248423 <LAVA_TEST_RUNNER EXIT>
2363 18:04:26.249198 ok: lava_test_shell seems to have completed
2364 18:04:26.263851 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2365 18:04:26.265989 end: 3.1 lava-test-shell (duration 00:01:27) [common]
2366 18:04:26.266654 end: 3 lava-test-retry (duration 00:01:27) [common]
2367 18:04:26.267299 start: 4 finalize (timeout 00:05:26) [common]
2368 18:04:26.267948 start: 4.1 power-off (timeout 00:00:30) [common]
2369 18:04:26.269026 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2370 18:04:26.306645 >> OK - accepted request
2371 18:04:26.308593 Returned 0 in 0 seconds
2372 18:04:26.409675 end: 4.1 power-off (duration 00:00:00) [common]
2374 18:04:26.410763 start: 4.2 read-feedback (timeout 00:05:26) [common]
2375 18:04:26.411478 Listened to connection for namespace 'common' for up to 1s
2376 18:04:26.412085 Listened to connection for namespace 'common' for up to 1s
2377 18:04:27.412360 Finalising connection for namespace 'common'
2378 18:04:27.412874 Disconnecting from shell: Finalise
2379 18:04:27.413160 / #
2380 18:04:27.514011 end: 4.2 read-feedback (duration 00:00:01) [common]
2381 18:04:27.514888 end: 4 finalize (duration 00:00:01) [common]
2382 18:04:27.515668 Cleaning after the job
2383 18:04:27.516369 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/941318/tftp-deploy-qne4z7f2/ramdisk
2384 18:04:27.518191 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/941318/tftp-deploy-qne4z7f2/kernel
2385 18:04:27.519478 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/941318/tftp-deploy-qne4z7f2/dtb
2386 18:04:27.520414 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/941318/tftp-deploy-qne4z7f2/nfsrootfs
2387 18:04:27.553131 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/941318/tftp-deploy-qne4z7f2/modules
2388 18:04:27.558072 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/941318
2389 18:04:30.499792 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/941318
2390 18:04:30.500362 Job finished correctly