Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 22:53:50.282764 lava-dispatcher, installed at version: 2024.01
2 22:53:50.283767 start: 0 validate
3 22:53:50.284382 Start time: 2024-11-06 22:53:50.284345+00:00 (UTC)
4 22:53:50.285072 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 22:53:50.285763 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 22:53:50.328554 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 22:53:50.329218 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-4-gde156f3cf70e1%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 22:53:50.356027 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 22:53:50.356649 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-4-gde156f3cf70e1%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 22:53:50.383667 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 22:53:50.384170 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 22:53:50.409905 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 22:53:50.410368 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-4-gde156f3cf70e1%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 22:53:50.437614 validate duration: 0.15
16 22:53:50.438563 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:53:50.438900 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:53:50.439202 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:53:50.439807 Not decompressing ramdisk as can be used compressed.
20 22:53:50.440237 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 22:53:50.440520 saving as /var/lib/lava/dispatcher/tmp/949684/tftp-deploy-3gh0c2ah/ramdisk/initrd.cpio.gz
22 22:53:50.440788 total size: 4775763 (4 MB)
23 22:53:50.469240 progress 0 % (0 MB)
24 22:53:50.472850 progress 5 % (0 MB)
25 22:53:50.476301 progress 10 % (0 MB)
26 22:53:50.479580 progress 15 % (0 MB)
27 22:53:50.483391 progress 20 % (0 MB)
28 22:53:50.486628 progress 25 % (1 MB)
29 22:53:50.489990 progress 30 % (1 MB)
30 22:53:50.493693 progress 35 % (1 MB)
31 22:53:50.496919 progress 40 % (1 MB)
32 22:53:50.500301 progress 45 % (2 MB)
33 22:53:50.503574 progress 50 % (2 MB)
34 22:53:50.507278 progress 55 % (2 MB)
35 22:53:50.510600 progress 60 % (2 MB)
36 22:53:50.513749 progress 65 % (2 MB)
37 22:53:50.517461 progress 70 % (3 MB)
38 22:53:50.520757 progress 75 % (3 MB)
39 22:53:50.524003 progress 80 % (3 MB)
40 22:53:50.527358 progress 85 % (3 MB)
41 22:53:50.530985 progress 90 % (4 MB)
42 22:53:50.534120 progress 95 % (4 MB)
43 22:53:50.537035 progress 100 % (4 MB)
44 22:53:50.537660 4 MB downloaded in 0.10 s (47.02 MB/s)
45 22:53:50.538221 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:53:50.539066 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:53:50.539357 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:53:50.539625 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:53:50.540157 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-4-gde156f3cf70e1/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 22:53:50.540439 saving as /var/lib/lava/dispatcher/tmp/949684/tftp-deploy-3gh0c2ah/kernel/zImage
52 22:53:50.540659 total size: 11440640 (10 MB)
53 22:53:50.540870 No compression specified
54 22:53:50.572593 progress 0 % (0 MB)
55 22:53:50.579887 progress 5 % (0 MB)
56 22:53:50.587164 progress 10 % (1 MB)
57 22:53:50.594677 progress 15 % (1 MB)
58 22:53:50.601706 progress 20 % (2 MB)
59 22:53:50.609356 progress 25 % (2 MB)
60 22:53:50.616409 progress 30 % (3 MB)
61 22:53:50.623835 progress 35 % (3 MB)
62 22:53:50.631022 progress 40 % (4 MB)
63 22:53:50.638528 progress 45 % (4 MB)
64 22:53:50.645659 progress 50 % (5 MB)
65 22:53:50.653225 progress 55 % (6 MB)
66 22:53:50.660300 progress 60 % (6 MB)
67 22:53:50.667369 progress 65 % (7 MB)
68 22:53:50.674990 progress 70 % (7 MB)
69 22:53:50.682004 progress 75 % (8 MB)
70 22:53:50.689394 progress 80 % (8 MB)
71 22:53:50.696517 progress 85 % (9 MB)
72 22:53:50.704168 progress 90 % (9 MB)
73 22:53:50.711232 progress 95 % (10 MB)
74 22:53:50.718372 progress 100 % (10 MB)
75 22:53:50.718846 10 MB downloaded in 0.18 s (61.24 MB/s)
76 22:53:50.719338 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:53:50.720168 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:53:50.720441 start: 1.3 download-retry (timeout 00:10:00) [common]
80 22:53:50.720701 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 22:53:50.721166 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-4-gde156f3cf70e1/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 22:53:50.721403 saving as /var/lib/lava/dispatcher/tmp/949684/tftp-deploy-3gh0c2ah/dtb/am335x-boneblack.dtb
83 22:53:50.721607 total size: 70568 (0 MB)
84 22:53:50.721833 No compression specified
85 22:53:50.753877 progress 46 % (0 MB)
86 22:53:50.754690 progress 92 % (0 MB)
87 22:53:50.755362 progress 100 % (0 MB)
88 22:53:50.755729 0 MB downloaded in 0.03 s (1.97 MB/s)
89 22:53:50.756168 end: 1.3.1 http-download (duration 00:00:00) [common]
91 22:53:50.756958 end: 1.3 download-retry (duration 00:00:00) [common]
92 22:53:50.757216 start: 1.4 download-retry (timeout 00:10:00) [common]
93 22:53:50.757491 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 22:53:50.758004 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 22:53:50.758273 saving as /var/lib/lava/dispatcher/tmp/949684/tftp-deploy-3gh0c2ah/nfsrootfs/full.rootfs.tar
96 22:53:50.758490 total size: 117747780 (112 MB)
97 22:53:50.758698 Using unxz to decompress xz
98 22:53:50.793031 progress 0 % (0 MB)
99 22:53:51.520077 progress 5 % (5 MB)
100 22:53:52.262307 progress 10 % (11 MB)
101 22:53:53.034247 progress 15 % (16 MB)
102 22:53:53.748859 progress 20 % (22 MB)
103 22:53:54.324557 progress 25 % (28 MB)
104 22:53:55.152654 progress 30 % (33 MB)
105 22:53:56.128185 progress 35 % (39 MB)
106 22:53:56.522340 progress 40 % (44 MB)
107 22:53:56.918940 progress 45 % (50 MB)
108 22:53:57.575878 progress 50 % (56 MB)
109 22:53:58.397352 progress 55 % (61 MB)
110 22:53:59.140879 progress 60 % (67 MB)
111 22:53:59.855148 progress 65 % (73 MB)
112 22:54:00.613119 progress 70 % (78 MB)
113 22:54:01.365090 progress 75 % (84 MB)
114 22:54:02.087384 progress 80 % (89 MB)
115 22:54:02.787205 progress 85 % (95 MB)
116 22:54:03.562421 progress 90 % (101 MB)
117 22:54:04.313670 progress 95 % (106 MB)
118 22:54:05.124388 progress 100 % (112 MB)
119 22:54:05.137430 112 MB downloaded in 14.38 s (7.81 MB/s)
120 22:54:05.138410 end: 1.4.1 http-download (duration 00:00:14) [common]
122 22:54:05.140167 end: 1.4 download-retry (duration 00:00:14) [common]
123 22:54:05.140727 start: 1.5 download-retry (timeout 00:09:45) [common]
124 22:54:05.141281 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 22:54:05.142176 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-4-gde156f3cf70e1/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 22:54:05.142709 saving as /var/lib/lava/dispatcher/tmp/949684/tftp-deploy-3gh0c2ah/modules/modules.tar
127 22:54:05.143213 total size: 6607624 (6 MB)
128 22:54:05.143680 Using unxz to decompress xz
129 22:54:05.178183 progress 0 % (0 MB)
130 22:54:05.214668 progress 5 % (0 MB)
131 22:54:05.257069 progress 10 % (0 MB)
132 22:54:05.299912 progress 15 % (0 MB)
133 22:54:05.343316 progress 20 % (1 MB)
134 22:54:05.389192 progress 25 % (1 MB)
135 22:54:05.432483 progress 30 % (1 MB)
136 22:54:05.474040 progress 35 % (2 MB)
137 22:54:05.516785 progress 40 % (2 MB)
138 22:54:05.559297 progress 45 % (2 MB)
139 22:54:05.601528 progress 50 % (3 MB)
140 22:54:05.643453 progress 55 % (3 MB)
141 22:54:05.687911 progress 60 % (3 MB)
142 22:54:05.735218 progress 65 % (4 MB)
143 22:54:05.777930 progress 70 % (4 MB)
144 22:54:05.824999 progress 75 % (4 MB)
145 22:54:05.866983 progress 80 % (5 MB)
146 22:54:05.908820 progress 85 % (5 MB)
147 22:54:05.951020 progress 90 % (5 MB)
148 22:54:05.993646 progress 95 % (6 MB)
149 22:54:06.036706 progress 100 % (6 MB)
150 22:54:06.049594 6 MB downloaded in 0.91 s (6.95 MB/s)
151 22:54:06.050442 end: 1.5.1 http-download (duration 00:00:01) [common]
153 22:54:06.052203 end: 1.5 download-retry (duration 00:00:01) [common]
154 22:54:06.052772 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 22:54:06.053339 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 22:54:22.724228 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/949684/extract-nfsrootfs-ohwjovwi
157 22:54:22.724836 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 22:54:22.725164 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 22:54:22.725976 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k
160 22:54:22.726488 makedir: /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin
161 22:54:22.726900 makedir: /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/tests
162 22:54:22.727272 makedir: /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/results
163 22:54:22.727646 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-add-keys
164 22:54:22.728187 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-add-sources
165 22:54:22.728696 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-background-process-start
166 22:54:22.729276 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-background-process-stop
167 22:54:22.729837 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-common-functions
168 22:54:22.730357 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-echo-ipv4
169 22:54:22.730857 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-install-packages
170 22:54:22.731352 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-installed-packages
171 22:54:22.731825 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-os-build
172 22:54:22.732298 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-probe-channel
173 22:54:22.732767 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-probe-ip
174 22:54:22.733236 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-target-ip
175 22:54:22.733699 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-target-mac
176 22:54:22.734209 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-target-storage
177 22:54:22.734730 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-test-case
178 22:54:22.735320 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-test-event
179 22:54:22.735809 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-test-feedback
180 22:54:22.736282 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-test-raise
181 22:54:22.736748 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-test-reference
182 22:54:22.737215 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-test-runner
183 22:54:22.737690 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-test-set
184 22:54:22.738213 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-test-shell
185 22:54:22.738721 Updating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-add-keys (debian)
186 22:54:22.739266 Updating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-add-sources (debian)
187 22:54:22.739766 Updating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-install-packages (debian)
188 22:54:22.740271 Updating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-installed-packages (debian)
189 22:54:22.740765 Updating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/bin/lava-os-build (debian)
190 22:54:22.741191 Creating /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/environment
191 22:54:22.741556 LAVA metadata
192 22:54:22.741825 - LAVA_JOB_ID=949684
193 22:54:22.742044 - LAVA_DISPATCHER_IP=192.168.6.3
194 22:54:22.742398 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 22:54:22.743331 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 22:54:22.743635 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 22:54:22.743838 skipped lava-vland-overlay
198 22:54:22.744074 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 22:54:22.744322 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 22:54:22.744519 skipped lava-multinode-overlay
201 22:54:22.744755 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 22:54:22.744999 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 22:54:22.745243 Loading test definitions
204 22:54:22.745510 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 22:54:22.745742 Using /lava-949684 at stage 0
206 22:54:22.746806 uuid=949684_1.6.2.4.1 testdef=None
207 22:54:22.747100 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 22:54:22.747357 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 22:54:22.748866 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 22:54:22.749636 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 22:54:22.751606 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 22:54:22.752414 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 22:54:22.754287 runner path: /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/0/tests/0_timesync-off test_uuid 949684_1.6.2.4.1
216 22:54:22.754882 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 22:54:22.755692 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 22:54:22.755911 Using /lava-949684 at stage 0
220 22:54:22.756262 Fetching tests from https://github.com/kernelci/test-definitions.git
221 22:54:22.756553 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/0/tests/1_kselftest-dt'
222 22:54:26.188919 Running '/usr/bin/git checkout kernelci.org
223 22:54:26.447792 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 22:54:26.449208 uuid=949684_1.6.2.4.5 testdef=None
225 22:54:26.449547 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 22:54:26.450755 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 22:54:26.456099 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 22:54:26.457641 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 22:54:26.464671 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 22:54:26.466334 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 22:54:26.473148 runner path: /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/0/tests/1_kselftest-dt test_uuid 949684_1.6.2.4.5
235 22:54:26.473693 BOARD='beaglebone-black'
236 22:54:26.474126 BRANCH='broonie-sound'
237 22:54:26.474514 SKIPFILE='/dev/null'
238 22:54:26.474900 SKIP_INSTALL='True'
239 22:54:26.475284 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-4-gde156f3cf70e1/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 22:54:26.475677 TST_CASENAME=''
241 22:54:26.476059 TST_CMDFILES='dt'
242 22:54:26.477038 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 22:54:26.478562 Creating lava-test-runner.conf files
245 22:54:26.478958 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/949684/lava-overlay-3rqxc_4k/lava-949684/0 for stage 0
246 22:54:26.479583 - 0_timesync-off
247 22:54:26.480023 - 1_kselftest-dt
248 22:54:26.480622 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 22:54:26.481148 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 22:54:50.235740 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 22:54:50.236298 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
252 22:54:50.236634 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 22:54:50.237003 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 22:54:50.237356 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
255 22:54:50.593237 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 22:54:50.593846 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 22:54:50.594192 extracting modules file /var/lib/lava/dispatcher/tmp/949684/tftp-deploy-3gh0c2ah/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949684/extract-nfsrootfs-ohwjovwi
258 22:54:51.734458 extracting modules file /var/lib/lava/dispatcher/tmp/949684/tftp-deploy-3gh0c2ah/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949684/extract-overlay-ramdisk-olinim0y/ramdisk
259 22:54:52.729638 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 22:54:52.730121 start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
261 22:54:52.730397 [common] Applying overlay to NFS
262 22:54:52.730612 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949684/compress-overlay-fl2_2379/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/949684/extract-nfsrootfs-ohwjovwi
263 22:54:55.473310 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 22:54:55.473828 start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
265 22:54:55.474120 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
266 22:54:55.474430 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 22:54:55.474689 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 22:54:55.474947 start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
269 22:54:55.475195 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 22:54:55.475449 start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
271 22:54:55.475674 Building ramdisk /var/lib/lava/dispatcher/tmp/949684/extract-overlay-ramdisk-olinim0y/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/949684/extract-overlay-ramdisk-olinim0y/ramdisk
272 22:54:56.473621 >> 74888 blocks
273 22:55:01.081749 Adding RAMdisk u-boot header.
274 22:55:01.082544 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/949684/extract-overlay-ramdisk-olinim0y/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/949684/extract-overlay-ramdisk-olinim0y/ramdisk.cpio.gz.uboot
275 22:55:01.243345 output: Image Name:
276 22:55:01.243755 output: Created: Wed Nov 6 22:55:01 2024
277 22:55:01.243964 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 22:55:01.244167 output: Data Size: 14791675 Bytes = 14445.00 KiB = 14.11 MiB
279 22:55:01.244368 output: Load Address: 00000000
280 22:55:01.244565 output: Entry Point: 00000000
281 22:55:01.244760 output:
282 22:55:01.245367 rename /var/lib/lava/dispatcher/tmp/949684/extract-overlay-ramdisk-olinim0y/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/949684/tftp-deploy-3gh0c2ah/ramdisk/ramdisk.cpio.gz.uboot
283 22:55:01.245797 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 22:55:01.246425 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 22:55:01.247006 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:49) [common]
286 22:55:01.247499 No LXC device requested
287 22:55:01.248044 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 22:55:01.248601 start: 1.8 deploy-device-env (timeout 00:08:49) [common]
289 22:55:01.249140 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 22:55:01.249587 Checking files for TFTP limit of 4294967296 bytes.
291 22:55:01.252545 end: 1 tftp-deploy (duration 00:01:11) [common]
292 22:55:01.253173 start: 2 uboot-action (timeout 00:05:00) [common]
293 22:55:01.253744 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 22:55:01.254329 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 22:55:01.254876 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 22:55:01.255696 substitutions:
297 22:55:01.256154 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 22:55:01.256594 - {DTB_ADDR}: 0x88000000
299 22:55:01.257030 - {DTB}: 949684/tftp-deploy-3gh0c2ah/dtb/am335x-boneblack.dtb
300 22:55:01.257464 - {INITRD}: 949684/tftp-deploy-3gh0c2ah/ramdisk/ramdisk.cpio.gz.uboot
301 22:55:01.257936 - {KERNEL_ADDR}: 0x82000000
302 22:55:01.258370 - {KERNEL}: 949684/tftp-deploy-3gh0c2ah/kernel/zImage
303 22:55:01.258801 - {LAVA_MAC}: None
304 22:55:01.259270 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/949684/extract-nfsrootfs-ohwjovwi
305 22:55:01.259708 - {NFS_SERVER_IP}: 192.168.6.3
306 22:55:01.260134 - {PRESEED_CONFIG}: None
307 22:55:01.260561 - {PRESEED_LOCAL}: None
308 22:55:01.261330 - {RAMDISK_ADDR}: 0x83000000
309 22:55:01.261799 - {RAMDISK}: 949684/tftp-deploy-3gh0c2ah/ramdisk/ramdisk.cpio.gz.uboot
310 22:55:01.262268 - {ROOT_PART}: None
311 22:55:01.262699 - {ROOT}: None
312 22:55:01.263128 - {SERVER_IP}: 192.168.6.3
313 22:55:01.263557 - {TEE_ADDR}: 0x83000000
314 22:55:01.263979 - {TEE}: None
315 22:55:01.264405 Parsed boot commands:
316 22:55:01.264819 - setenv autoload no
317 22:55:01.265244 - setenv initrd_high 0xffffffff
318 22:55:01.265670 - setenv fdt_high 0xffffffff
319 22:55:01.266121 - dhcp
320 22:55:01.266548 - setenv serverip 192.168.6.3
321 22:55:01.266974 - tftp 0x82000000 949684/tftp-deploy-3gh0c2ah/kernel/zImage
322 22:55:01.267398 - tftp 0x83000000 949684/tftp-deploy-3gh0c2ah/ramdisk/ramdisk.cpio.gz.uboot
323 22:55:01.267825 - setenv initrd_size ${filesize}
324 22:55:01.268244 - tftp 0x88000000 949684/tftp-deploy-3gh0c2ah/dtb/am335x-boneblack.dtb
325 22:55:01.268666 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/949684/extract-nfsrootfs-ohwjovwi,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 22:55:01.269100 - bootz 0x82000000 0x83000000 0x88000000
327 22:55:01.269654 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 22:55:01.271312 start: 2.3 connect-device (timeout 00:05:00) [common]
330 22:55:01.271768 [common] connect-device Connecting to device using 'telnet conserv3 3000'
331 22:55:01.287094 Setting prompt string to ['lava-test: # ']
332 22:55:01.288665 end: 2.3 connect-device (duration 00:00:00) [common]
333 22:55:01.289319 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 22:55:01.290034 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 22:55:01.290729 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 22:55:01.292108 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-03'
337 22:55:01.330389 >> OK - accepted request
338 22:55:01.332609 Returned 0 in 0 seconds
339 22:55:01.433792 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 22:55:01.435609 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 22:55:01.436231 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 22:55:01.436859 Setting prompt string to ['Hit any key to stop autoboot']
344 22:55:01.437406 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 22:55:01.439115 Trying 192.168.56.22...
346 22:55:01.439654 Connected to conserv3.
347 22:55:01.440117 Escape character is '^]'.
348 22:55:01.440574
349 22:55:01.441033 ser2net port telnet,3000 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 22:55:01.441485
351 22:55:09.565417
352 22:55:09.572911 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
353 22:55:09.573446 Trying to boot from MMC1
354 22:55:10.158148
355 22:55:10.158762
356 22:55:10.163525 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
357 22:55:10.164024
358 22:55:10.164470 CPU : AM335X-GP rev 2.0
359 22:55:10.168704 Model: TI AM335x BeagleBone Black
360 22:55:10.169185 DRAM: 512 MiB
361 22:55:13.613891
362 22:55:13.620848 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
363 22:55:13.621429 Trying to boot from MMC1
364 22:55:14.207021
365 22:55:14.207701
366 22:55:14.212361 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
367 22:55:14.212909
368 22:55:14.213560 CPU : AM335X-GP rev 2.0
369 22:55:14.217530 Model: TI AM335x BeagleBone Black
370 22:55:14.218141 DRAM: 512 MiB
371 22:55:16.314252
372 22:55:16.320096 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
373 22:55:16.320672 Trying to boot from MMC1
374 22:55:16.907918
375 22:55:16.908523
376 22:55:16.913393 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
377 22:55:16.913925
378 22:55:16.914387 CPU : AM335X-GP rev 2.0
379 22:55:16.918561 Model: TI AM335x BeagleBone Black
380 22:55:16.919035 DRAM: 512 MiB
381 22:55:17.003242 Core: 160 devices, 18 uclasses, devicetree: separate
382 22:55:17.017087 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
383 22:55:17.417617 NAND: 0 MiB
384 22:55:17.427894 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
385 22:55:17.502543 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
386 22:55:17.523877 <ethaddr> not set. Validating first E-fuse MAC
387 22:55:17.553600 Net: eth2: ethernet@4a100000, eth3: usb_ether
389 22:55:17.612107 Hit any key to stop autoboot: 2
390 22:55:17.612961 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
391 22:55:17.613612 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
392 22:55:17.614176 Setting prompt string to ['=>']
393 22:55:17.614705 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
394 22:55:17.621142 0
395 22:55:17.622087 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
396 22:55:17.622638 Sending with 10 millisecond of delay
398 22:55:18.757579 => setenv autoload no
399 22:55:18.768435 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
400 22:55:18.773858 setenv autoload no
401 22:55:18.774627 Sending with 10 millisecond of delay
403 22:55:20.572815 => setenv initrd_high 0xffffffff
404 22:55:20.583659 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
405 22:55:20.584508 setenv initrd_high 0xffffffff
406 22:55:20.585310 Sending with 10 millisecond of delay
408 22:55:22.201753 => setenv fdt_high 0xffffffff
409 22:55:22.212623 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
410 22:55:22.213550 setenv fdt_high 0xffffffff
411 22:55:22.214331 Sending with 10 millisecond of delay
413 22:55:22.506186 => dhcp
414 22:55:22.516923 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
415 22:55:22.517741 dhcp
416 22:55:22.518226 link up on port 0, speed 100, full duplex
417 22:55:22.518647 BOOTP broadcast 1
418 22:55:22.770870 BOOTP broadcast 2
419 22:55:23.272839 BOOTP broadcast 3
420 22:55:24.274909 BOOTP broadcast 4
421 22:55:24.376375 DHCP client bound to address 192.168.6.23 (1854 ms)
422 22:55:24.377357 Sending with 10 millisecond of delay
424 22:55:26.056114 => setenv serverip 192.168.6.3
425 22:55:26.067112 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
426 22:55:26.068264 setenv serverip 192.168.6.3
427 22:55:26.069200 Sending with 10 millisecond of delay
429 22:55:29.556759 => tftp 0x82000000 949684/tftp-deploy-3gh0c2ah/kernel/zImage
430 22:55:29.567928 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
431 22:55:29.569243 tftp 0x82000000 949684/tftp-deploy-3gh0c2ah/kernel/zImage
432 22:55:29.570014 link up on port 0, speed 100, full duplex
433 22:55:29.573059 Using ethernet@4a100000 device
434 22:55:29.578314 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
435 22:55:29.584754 Filename '949684/tftp-deploy-3gh0c2ah/kernel/zImage'.
436 22:55:29.585496 Load address: 0x82000000
437 22:55:31.673358 Loading: *################################################## 10.9 MiB
438 22:55:31.673986 5.2 MiB/s
439 22:55:31.674414 done
440 22:55:31.677647 Bytes transferred = 11440640 (ae9200 hex)
441 22:55:31.678429 Sending with 10 millisecond of delay
443 22:55:36.126266 => tftp 0x83000000 949684/tftp-deploy-3gh0c2ah/ramdisk/ramdisk.cpio.gz.uboot
444 22:55:36.137392 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
445 22:55:36.138283 tftp 0x83000000 949684/tftp-deploy-3gh0c2ah/ramdisk/ramdisk.cpio.gz.uboot
446 22:55:36.138626 link up on port 0, speed 100, full duplex
447 22:55:36.142051 Using ethernet@4a100000 device
448 22:55:36.147645 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
449 22:55:36.156417 Filename '949684/tftp-deploy-3gh0c2ah/ramdisk/ramdisk.cpio.gz.uboot'.
450 22:55:36.157117 Load address: 0x83000000
451 22:55:39.089320 Loading: *################################################## 14.1 MiB
452 22:55:39.089727 5.3 MiB/s
453 22:55:39.089971 done
454 22:55:39.092174 Bytes transferred = 14791739 (e1b43b hex)
455 22:55:39.092942 Sending with 10 millisecond of delay
457 22:55:40.950619 => setenv initrd_size ${filesize}
458 22:55:40.961404 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
459 22:55:40.962303 setenv initrd_size ${filesize}
460 22:55:40.963019 Sending with 10 millisecond of delay
462 22:55:45.108911 => tftp 0x88000000 949684/tftp-deploy-3gh0c2ah/dtb/am335x-boneblack.dtb
463 22:55:45.119500 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
464 22:55:45.120175 tftp 0x88000000 949684/tftp-deploy-3gh0c2ah/dtb/am335x-boneblack.dtb
465 22:55:45.120415 link up on port 0, speed 100, full duplex
466 22:55:45.124514 Using ethernet@4a100000 device
467 22:55:45.130300 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
468 22:55:45.137931 Filename '949684/tftp-deploy-3gh0c2ah/dtb/am335x-boneblack.dtb'.
469 22:55:45.138301 Load address: 0x88000000
470 22:55:45.150317 Loading: *################################################## 68.9 KiB
471 22:55:45.159161 4.5 MiB/s
472 22:55:45.159686 done
473 22:55:45.160084 Bytes transferred = 70568 (113a8 hex)
474 22:55:45.160760 Sending with 10 millisecond of delay
476 22:55:58.338962 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/949684/extract-nfsrootfs-ohwjovwi,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
477 22:55:58.349853 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
478 22:55:58.350782 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/949684/extract-nfsrootfs-ohwjovwi,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
479 22:55:58.351559 Sending with 10 millisecond of delay
481 22:56:00.691474 => bootz 0x82000000 0x83000000 0x88000000
482 22:56:00.702472 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
483 22:56:00.702901 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:01)
484 22:56:00.703479 bootz 0x82000000 0x83000000 0x88000000
485 22:56:00.703732 Kernel image @ 0x82000000 [ 0x000000 - 0xae9200 ]
486 22:56:00.704447 ## Loading init Ramdisk from Legacy Image at 83000000 ...
487 22:56:00.709973 Image Name:
488 22:56:00.710279 Created: 2024-11-06 22:55:01 UTC
489 22:56:00.713316 Image Type: ARM Linux RAMDisk Image (uncompressed)
490 22:56:00.718974 Data Size: 14791675 Bytes = 14.1 MiB
491 22:56:00.726399 Load Address: 00000000
492 22:56:00.726723 Entry Point: 00000000
493 22:56:00.895468 Verifying Checksum ... OK
494 22:56:00.895848 ## Flattened Device Tree blob at 88000000
495 22:56:00.902120 Booting using the fdt blob at 0x88000000
496 22:56:00.902416 Working FDT set to 88000000
497 22:56:00.907607 Using Device Tree in place at 88000000, end 880143a7
498 22:56:00.912073 Working FDT set to 88000000
499 22:56:00.925226
500 22:56:00.925554 Starting kernel ...
501 22:56:00.925765
502 22:56:00.926388 end: 2.4.3 bootloader-commands (duration 00:00:43) [common]
503 22:56:00.926722 start: 2.4.4 auto-login-action (timeout 00:04:00) [common]
504 22:56:00.926973 Setting prompt string to ['Linux version [0-9]']
505 22:56:00.927215 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
506 22:56:00.927454 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
507 22:56:01.769550 [ 0.000000] Booting Linux on physical CPU 0x0
508 22:56:01.775425 start: 2.4.4.1 login-action (timeout 00:03:59) [common]
509 22:56:01.775927 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
510 22:56:01.776204 Setting prompt string to []
511 22:56:01.776475 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
512 22:56:01.776718 Using line separator: #'\n'#
513 22:56:01.776922 No login prompt set.
514 22:56:01.777157 Parsing kernel messages
515 22:56:01.777363 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
516 22:56:01.777786 [login-action] Waiting for messages, (timeout 00:03:59)
517 22:56:01.778045 Waiting using forced prompt support (timeout 00:02:00)
518 22:56:01.789421 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j365798-arm-gcc-12-multi-v7-defconfig-rk9d7) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Wed Nov 6 22:21:17 UTC 2024
519 22:56:01.800812 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
520 22:56:01.804081 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
521 22:56:01.809603 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
522 22:56:01.821109 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
523 22:56:01.826945 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
524 22:56:01.827295 [ 0.000000] Memory policy: Data cache writeback
525 22:56:01.834271 [ 0.000000] efi: UEFI not found.
526 22:56:01.838911 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
527 22:56:01.844576 [ 0.000000] Zone ranges:
528 22:56:01.850356 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
529 22:56:01.856223 [ 0.000000] Normal empty
530 22:56:01.856647 [ 0.000000] HighMem empty
531 22:56:01.858978 [ 0.000000] Movable zone start for each node
532 22:56:01.864540 [ 0.000000] Early memory node ranges
533 22:56:01.870364 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
534 22:56:01.878523 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
535 22:56:01.903748 [ 0.000000] CPU: All CPU(s) started in SVC mode.
536 22:56:01.909435 [ 0.000000] AM335X ES2.0 (sgx neon)
537 22:56:01.921165 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
538 22:56:01.939550 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/949684/extract-nfsrootfs-ohwjovwi,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
539 22:56:01.950378 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
540 22:56:01.956117 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
541 22:56:01.961743 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
542 22:56:01.971455 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
543 22:56:02.000788 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
544 22:56:02.006749 <6>[ 0.000000] trace event string verifier disabled
545 22:56:02.007147 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
546 22:56:02.014741 <6>[ 0.000000] rcu: RCU event tracing is enabled.
547 22:56:02.020490 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
548 22:56:02.029218 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
549 22:56:02.036852 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
550 22:56:02.051751 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
551 22:56:02.068882 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
552 22:56:02.075608 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
553 22:56:02.167321 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
554 22:56:02.178751 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
555 22:56:02.185476 <6>[ 0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
556 22:56:02.198563 <6>[ 0.019144] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
557 22:56:02.205853 <6>[ 0.033929] Console: colour dummy device 80x30
558 22:56:02.211890 Matched prompt #6: WARNING:
559 22:56:02.212248 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
560 22:56:02.217382 <3>[ 0.038827] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
561 22:56:02.223156 <3>[ 0.045900] This ensures that you still see kernel messages. Please
562 22:56:02.225507 <3>[ 0.052633] update your kernel commandline.
563 22:56:02.267091 <6>[ 0.057244] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
564 22:56:02.272837 <6>[ 0.096150] CPU: Testing write buffer coherency: ok
565 22:56:02.278751 <6>[ 0.101517] CPU0: Spectre v2: using BPIALL workaround
566 22:56:02.279088 <6>[ 0.106985] pid_max: default: 32768 minimum: 301
567 22:56:02.290230 <6>[ 0.112176] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 22:56:02.297179 <6>[ 0.120002] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
569 22:56:02.304279 <6>[ 0.129351] CPU0: thread -1, cpu 0, socket -1, mpidr 0
570 22:56:02.312674 <6>[ 0.136351] Setting up static identity map for 0x80300000 - 0x803000ac
571 22:56:02.318460 <6>[ 0.145977] rcu: Hierarchical SRCU implementation.
572 22:56:02.326095 <6>[ 0.151261] rcu: Max phase no-delay instances is 1000.
573 22:56:02.334602 <6>[ 0.162372] EFI services will not be available.
574 22:56:02.340444 <6>[ 0.167645] smp: Bringing up secondary CPUs ...
575 22:56:02.346165 <6>[ 0.172694] smp: Brought up 1 node, 1 CPU
576 22:56:02.351944 <6>[ 0.177095] SMP: Total of 1 processors activated (996.14 BogoMIPS).
577 22:56:02.357897 <6>[ 0.183864] CPU: All CPU(s) started in SVC mode.
578 22:56:02.378289 <6>[ 0.189045] Memory: 405996K/522240K available (16384K kernel code, 2542K rwdata, 6784K rodata, 2048K init, 431K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
579 22:56:02.378718 <6>[ 0.205334] devtmpfs: initialized
580 22:56:02.400416 <6>[ 0.222384] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
581 22:56:02.411927 <6>[ 0.230954] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
582 22:56:02.417907 <6>[ 0.241404] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
583 22:56:02.428662 <6>[ 0.253754] pinctrl core: initialized pinctrl subsystem
584 22:56:02.437904 <6>[ 0.264358] DMI not present or invalid.
585 22:56:02.446182 <6>[ 0.270216] NET: Registered PF_NETLINK/PF_ROUTE protocol family
586 22:56:02.455650 <6>[ 0.279101] DMA: preallocated 256 KiB pool for atomic coherent allocations
587 22:56:02.470769 <6>[ 0.290645] thermal_sys: Registered thermal governor 'step_wise'
588 22:56:02.471144 <6>[ 0.290810] cpuidle: using governor menu
589 22:56:02.498324 <6>[ 0.326389] No ATAGs?
590 22:56:02.503723 <6>[ 0.329034] hw-breakpoint: debug architecture 0x4 unsupported.
591 22:56:02.514807 <6>[ 0.341090] Serial: AMBA PL011 UART driver
592 22:56:02.547324 <6>[ 0.375227] iommu: Default domain type: Translated
593 22:56:02.556374 <6>[ 0.380576] iommu: DMA domain TLB invalidation policy: strict mode
594 22:56:02.583509 <5>[ 0.410628] SCSI subsystem initialized
595 22:56:02.589156 <6>[ 0.415515] usbcore: registered new interface driver usbfs
596 22:56:02.595061 <6>[ 0.421577] usbcore: registered new interface driver hub
597 22:56:02.601771 <6>[ 0.427358] usbcore: registered new device driver usb
598 22:56:02.607441 <6>[ 0.433880] pps_core: LinuxPPS API ver. 1 registered
599 22:56:02.619024 <6>[ 0.439271] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
600 22:56:02.626145 <6>[ 0.448999] PTP clock support registered
601 22:56:02.626501 <6>[ 0.453462] EDAC MC: Ver: 3.0.0
602 22:56:02.674939 <6>[ 0.500371] scmi_core: SCMI protocol bus registered
603 22:56:02.690076 <6>[ 0.517697] vgaarb: loaded
604 22:56:02.702604 <6>[ 0.530706] clocksource: Switched to clocksource dmtimer
605 22:56:02.739262 <6>[ 0.566849] NET: Registered PF_INET protocol family
606 22:56:02.751711 <6>[ 0.572543] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
607 22:56:02.757472 <6>[ 0.581353] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
608 22:56:02.768892 <6>[ 0.590282] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
609 22:56:02.774679 <6>[ 0.598544] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
610 22:56:02.786300 <6>[ 0.606828] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
611 22:56:02.792159 <6>[ 0.614553] TCP: Hash tables configured (established 4096 bind 4096)
612 22:56:02.798359 <6>[ 0.621456] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
613 22:56:02.804323 <6>[ 0.628494] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
614 22:56:02.811673 <6>[ 0.636097] NET: Registered PF_UNIX/PF_LOCAL protocol family
615 22:56:02.888196 <6>[ 0.710557] RPC: Registered named UNIX socket transport module.
616 22:56:02.888842 <6>[ 0.717000] RPC: Registered udp transport module.
617 22:56:02.893923 <6>[ 0.722130] RPC: Registered tcp transport module.
618 22:56:02.899660 <6>[ 0.727234] RPC: Registered tcp-with-tls transport module.
619 22:56:02.912661 <6>[ 0.733159] RPC: Registered tcp NFSv4.1 backchannel transport module.
620 22:56:02.913276 <6>[ 0.740063] PCI: CLS 0 bytes, default 64
621 22:56:02.919848 <5>[ 0.745851] Initialise system trusted keyrings
622 22:56:02.940882 <6>[ 0.765898] Trying to unpack rootfs image as initramfs...
623 22:56:03.019957 <6>[ 0.841791] workingset: timestamp_bits=30 max_order=17 bucket_order=0
624 22:56:03.024589 <6>[ 0.849303] squashfs: version 4.0 (2009/01/31) Phillip Lougher
625 22:56:03.064733 <5>[ 0.892687] NFS: Registering the id_resolver key type
626 22:56:03.070474 <5>[ 0.898280] Key type id_resolver registered
627 22:56:03.076248 <5>[ 0.902974] Key type id_legacy registered
628 22:56:03.082023 <6>[ 0.907411] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
629 22:56:03.091605 <6>[ 0.914612] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
630 22:56:03.164196 <5>[ 0.992215] Key type asymmetric registered
631 22:56:03.170044 <5>[ 0.996741] Asymmetric key parser 'x509' registered
632 22:56:03.178388 <6>[ 1.002220] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
633 22:56:03.184237 <6>[ 1.010109] io scheduler mq-deadline registered
634 22:56:03.192934 <6>[ 1.015092] io scheduler kyber registered
635 22:56:03.193506 <6>[ 1.019543] io scheduler bfq registered
636 22:56:03.293108 <6>[ 1.117500] ledtrig-cpu: registered to indicate activity on CPUs
637 22:56:03.588711 <6>[ 1.413653] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
638 22:56:03.618833 <6>[ 1.446608] msm_serial: driver initialized
639 22:56:03.624812 <6>[ 1.451386] SuperH (H)SCI(F) driver initialized
640 22:56:03.630751 <6>[ 1.456730] STMicroelectronics ASC driver initialized
641 22:56:03.636073 <6>[ 1.462412] STM32 USART driver initialized
642 22:56:03.780466 <6>[ 1.607906] brd: module loaded
643 22:56:03.798738 <6>[ 1.626052] loop: module loaded
644 22:56:03.842110 <6>[ 1.669280] CAN device driver interface
645 22:56:03.848614 <6>[ 1.674503] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
646 22:56:03.854393 <6>[ 1.681396] e1000e: Intel(R) PRO/1000 Network Driver
647 22:56:03.860316 <6>[ 1.686850] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
648 22:56:03.865928 <6>[ 1.693284] igb: Intel(R) Gigabit Ethernet Network Driver
649 22:56:03.874177 <6>[ 1.699107] igb: Copyright (c) 2007-2014 Intel Corporation.
650 22:56:03.885902 <6>[ 1.708291] pegasus: Pegasus/Pegasus II USB Ethernet driver
651 22:56:03.891739 <6>[ 1.714444] usbcore: registered new interface driver pegasus
652 22:56:03.897557 <6>[ 1.720568] usbcore: registered new interface driver asix
653 22:56:03.903348 <6>[ 1.726463] usbcore: registered new interface driver ax88179_178a
654 22:56:03.909105 <6>[ 1.733055] usbcore: registered new interface driver cdc_ether
655 22:56:03.914856 <6>[ 1.739352] usbcore: registered new interface driver smsc75xx
656 22:56:03.920667 <6>[ 1.745583] usbcore: registered new interface driver smsc95xx
657 22:56:03.926411 <6>[ 1.751822] usbcore: registered new interface driver net1080
658 22:56:03.932178 <6>[ 1.757948] usbcore: registered new interface driver cdc_subset
659 22:56:03.938001 <6>[ 1.764357] usbcore: registered new interface driver zaurus
660 22:56:03.945634 <6>[ 1.770405] usbcore: registered new interface driver cdc_ncm
661 22:56:03.955429 <6>[ 1.779772] usbcore: registered new interface driver usb-storage
662 22:56:04.237780 <6>[ 2.063916] i2c_dev: i2c /dev entries driver
663 22:56:04.288236 <5>[ 2.108245] cpuidle: enable-method property 'ti,am3352' found operations
664 22:56:04.294396 <6>[ 2.117884] sdhci: Secure Digital Host Controller Interface driver
665 22:56:04.301886 <6>[ 2.124711] sdhci: Copyright(c) Pierre Ossman
666 22:56:04.309006 <6>[ 2.131128] Synopsys Designware Multimedia Card Interface Driver
667 22:56:04.314237 <6>[ 2.139045] sdhci-pltfm: SDHCI platform and OF driver helper
668 22:56:04.442443 <6>[ 2.263046] usbcore: registered new interface driver usbhid
669 22:56:04.442866 <6>[ 2.269087] usbhid: USB HID core driver
670 22:56:04.482525 <6>[ 2.307881] NET: Registered PF_INET6 protocol family
671 22:56:04.529929 <6>[ 2.357810] Segment Routing with IPv6
672 22:56:04.535604 <6>[ 2.362054] In-situ OAM (IOAM) with IPv6
673 22:56:04.542281 <6>[ 2.366462] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
674 22:56:04.547995 <6>[ 2.373757] NET: Registered PF_PACKET protocol family
675 22:56:04.553883 <6>[ 2.379250] can: controller area network core
676 22:56:04.559820 <6>[ 2.384135] NET: Registered PF_CAN protocol family
677 22:56:04.560401 <6>[ 2.389335] can: raw protocol
678 22:56:04.565505 <6>[ 2.392685] can: broadcast manager protocol
679 22:56:04.572003 <6>[ 2.397265] can: netlink gateway - max_hops=1
680 22:56:04.578101 <5>[ 2.402796] Key type dns_resolver registered
681 22:56:04.584470 <6>[ 2.407789] ThumbEE CPU extension supported.
682 22:56:04.585060 <5>[ 2.412575] Registering SWP/SWPB emulation handler
683 22:56:04.594136 <3>[ 2.418227] omap_voltage_late_init: Voltage driver support not added
684 22:56:04.776410 <5>[ 2.601923] Loading compiled-in X.509 certificates
685 22:56:04.925189 <6>[ 2.740267] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
686 22:56:04.932438 <6>[ 2.756949] pinctrl-single 44e10800.pinmux: 142 pins, size 568
687 22:56:04.958711 <3>[ 2.780692] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
688 22:56:05.169378 <3>[ 2.991361] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
689 22:56:05.356881 <6>[ 3.183111] OMAP GPIO hardware version 0.1
690 22:56:05.377695 <6>[ 3.201963] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
691 22:56:05.479708 <4>[ 3.303734] at24 2-0054: supply vcc not found, using dummy regulator
692 22:56:05.517875 <4>[ 3.341945] at24 2-0055: supply vcc not found, using dummy regulator
693 22:56:05.554401 <4>[ 3.378330] at24 2-0056: supply vcc not found, using dummy regulator
694 22:56:05.598911 <4>[ 3.422970] at24 2-0057: supply vcc not found, using dummy regulator
695 22:56:05.631570 <6>[ 3.456409] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
696 22:56:05.703189 <3>[ 3.524020] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
697 22:56:05.728483 <6>[ 3.545088] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
698 22:56:05.750049 <4>[ 3.571930] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
699 22:56:05.756835 <4>[ 3.580471] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
700 22:56:05.888118 <6>[ 3.712363] omap_rng 48310000.rng: Random Number Generator ver. 20
701 22:56:05.911631 <5>[ 3.738684] random: crng init done
702 22:56:05.953206 <6>[ 3.781033] Freeing initrd memory: 14448K
703 22:56:05.962977 <6>[ 3.785779] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
704 22:56:06.012171 <6>[ 3.834023] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
705 22:56:06.018046 <6>[ 3.844371] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
706 22:56:06.029731 <6>[ 3.851746] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
707 22:56:06.035636 <6>[ 3.859196] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
708 22:56:06.047114 <6>[ 3.867331] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
709 22:56:06.054453 <6>[ 3.878969] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5c:d5:d8
710 22:56:06.067785 <5>[ 3.887989] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
711 22:56:06.095410 <3>[ 3.917758] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
712 22:56:06.101222 <6>[ 3.926351] edma 49000000.dma: TI EDMA DMA engine driver
713 22:56:06.172464 <3>[ 3.994070] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
714 22:56:06.187170 <6>[ 4.008435] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
715 22:56:06.200177 <3>[ 4.025586] l3-aon-clkctrl:0000:0: failed to disable
716 22:56:06.250362 <6>[ 4.072701] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
717 22:56:06.256033 <6>[ 4.082167] printk: legacy console [ttyS0] enabled
718 22:56:06.261724 <6>[ 4.082167] printk: legacy console [ttyS0] enabled
719 22:56:06.267362 <6>[ 4.092502] printk: legacy bootconsole [omap8250] disabled
720 22:56:06.273355 <6>[ 4.092502] printk: legacy bootconsole [omap8250] disabled
721 22:56:06.311089 <4>[ 4.132364] tps65217-pmic: Failed to locate of_node [id: -1]
722 22:56:06.314767 <4>[ 4.139741] tps65217-bl: Failed to locate of_node [id: -1]
723 22:56:06.331171 <6>[ 4.159378] tps65217 0-0024: TPS65217 ID 0xe version 1.2
724 22:56:06.349470 <6>[ 4.166331] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
725 22:56:06.361237 <6>[ 4.180026] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
726 22:56:06.366983 <6>[ 4.191906] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
727 22:56:06.389086 <6>[ 4.211780] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
728 22:56:06.395092 <6>[ 4.220838] sdhci-omap 48060000.mmc: Got CD GPIO
729 22:56:06.403128 <4>[ 4.226034] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
730 22:56:06.417913 <4>[ 4.239607] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
731 22:56:06.424110 <4>[ 4.248325] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
732 22:56:06.433894 <4>[ 4.256892] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
733 22:56:06.557157 <6>[ 4.380962] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
734 22:56:06.607230 <6>[ 4.427938] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
735 22:56:06.613720 <6>[ 4.438081] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
736 22:56:06.622877 <6>[ 4.447077] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
737 22:56:06.684615 <6>[ 4.502218] mmc0: new high speed SDHC card at address 0001
738 22:56:06.685276 <6>[ 4.510781] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
739 22:56:06.697623 <6>[ 4.523705] mmc1: new high speed MMC card at address 0001
740 22:56:06.706763 <6>[ 4.532834] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
741 22:56:06.718894 <6>[ 4.541029] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
742 22:56:06.725294 <6>[ 4.552493] mmcblk1:
743 22:56:06.728126 <6>[ 4.555830] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
744 22:56:06.734082 <6>[ 4.562068] mmcblk0: p1
745 22:56:06.746914 <6>[ 4.573470] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
746 22:56:06.755095 <6>[ 4.580398] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
747 22:56:08.860419 <6>[ 6.682599] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
748 22:56:08.973633 <5>[ 6.721639] Sending DHCP requests ., OK
749 22:56:08.985109 <6>[ 6.806112] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.23
750 22:56:08.985668 <6>[ 6.814279] IP-Config: Complete:
751 22:56:08.999115 <6>[ 6.817817] device=eth0, hwaddr=90:59:af:5c:d5:d8, ipaddr=192.168.6.23, mask=255.255.255.0, gw=192.168.6.1
752 22:56:09.004866 <6>[ 6.828335] host=192.168.6.23, domain=, nis-domain=(none)
753 22:56:09.008273 <6>[ 6.834560] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
754 22:56:09.014720 <6>[ 6.834594] nameserver0=10.255.253.1
755 22:56:09.020756 <6>[ 6.847208] clk: Disabling unused clocks
756 22:56:09.026319 <6>[ 6.851912] PM: genpd: Disabling unused power domains
757 22:56:09.045989 <6>[ 6.870791] Freeing unused kernel image (initmem) memory: 2048K
758 22:56:09.053432 <6>[ 6.880501] Run /init as init process
759 22:56:09.078443 Loading, please wait...
760 22:56:09.153787 Starting systemd-udevd version 252.22-1~deb12u1
761 22:56:12.183634 <4>[ 10.004493] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
762 22:56:12.343266 <4>[ 10.164188] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
763 22:56:12.585461 <6>[ 10.413860] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
764 22:56:12.596061 <6>[ 10.419546] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
765 22:56:12.804224 <6>[ 10.631118] hub 1-0:1.0: USB hub found
766 22:56:12.855157 <6>[ 10.681855] hub 1-0:1.0: 1 port detected
767 22:56:12.927832 <6>[ 10.754392] tda998x 0-0070: found TDA19988
768 22:56:15.790123 Begin: Loading essential drivers ... done.
769 22:56:15.795565 Begin: Running /scripts/init-premount ... done.
770 22:56:15.801125 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
771 22:56:15.810388 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
772 22:56:15.817572 Device /sys/class/net/eth0 found
773 22:56:15.817956 done.
774 22:56:15.891992 Begin: Waiting up to 180 secs for any network device to become available ... done.
775 22:56:15.965238 IP-Config: eth0 hardware address 90:59:af:5c:d5:d8 mtu 1500 DHCP
776 22:56:16.063432 IP-Config: eth0 guessed broadcast address 192.168.6.255
777 22:56:16.068974 IP-Config: eth0 complete (dhcp from 192.168.6.1):
778 22:56:16.074579 address: 192.168.6.23 broadcast: 192.168.6.255 netmask: 255.255.255.0
779 22:56:16.086027 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
780 22:56:16.086591 rootserver: 192.168.6.1 rootpath:
781 22:56:16.088339 filename :
782 22:56:16.153317 done.
783 22:56:16.160880 Begin: Running /scripts/nfs-bottom ... done.
784 22:56:16.243524 Begin: Running /scripts/init-bottom ... done.
785 22:56:17.514093 <30>[ 15.338487] systemd[1]: System time before build time, advancing clock.
786 22:56:17.690466 <30>[ 15.488693] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
787 22:56:17.698611 <30>[ 15.525497] systemd[1]: Detected architecture arm.
788 22:56:17.711200
789 22:56:17.711835 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
790 22:56:17.712310
791 22:56:17.736324 <30>[ 15.561326] systemd[1]: Hostname set to <debian-bookworm-armhf>.
792 22:56:19.899849 <30>[ 17.724619] systemd[1]: Queued start job for default target graphical.target.
793 22:56:19.917330 <30>[ 17.739169] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
794 22:56:19.924953 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
795 22:56:19.950141 <30>[ 17.774333] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
796 22:56:19.961727 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
797 22:56:19.982854 <30>[ 17.804912] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
798 22:56:19.990548 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
799 22:56:20.013866 <30>[ 17.835318] systemd[1]: Created slice user.slice - User and Session Slice.
800 22:56:20.020606 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
801 22:56:20.046217 <30>[ 17.862828] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
802 22:56:20.052337 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
803 22:56:20.070319 <30>[ 17.892630] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
804 22:56:20.079309 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
805 22:56:20.111467 <30>[ 17.922632] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
806 22:56:20.117799 <30>[ 17.943136] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
807 22:56:20.126313 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
808 22:56:20.149594 <30>[ 17.972074] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
809 22:56:20.158100 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
810 22:56:20.180196 <30>[ 18.002368] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
811 22:56:20.188797 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
812 22:56:20.211050 <30>[ 18.032559] systemd[1]: Reached target paths.target - Path Units.
813 22:56:20.215269 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
814 22:56:20.239639 <30>[ 18.062154] systemd[1]: Reached target remote-fs.target - Remote File Systems.
815 22:56:20.247258 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
816 22:56:20.269755 <30>[ 18.092084] systemd[1]: Reached target slices.target - Slice Units.
817 22:56:20.275134 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
818 22:56:20.300322 <30>[ 18.122654] systemd[1]: Reached target swap.target - Swaps.
819 22:56:20.304321 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
820 22:56:20.330144 <30>[ 18.152300] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
821 22:56:20.339098 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
822 22:56:20.361107 <30>[ 18.183181] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
823 22:56:20.369322 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
824 22:56:20.452604 <30>[ 18.270047] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
825 22:56:20.465412 <30>[ 18.287612] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
826 22:56:20.473845 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
827 22:56:20.501651 <30>[ 18.323297] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
828 22:56:20.509187 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
829 22:56:20.533135 <30>[ 18.355180] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
830 22:56:20.541658 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
831 22:56:20.569092 <30>[ 18.392626] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
832 22:56:20.581203 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
833 22:56:20.601320 <30>[ 18.422979] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
834 22:56:20.609048 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
835 22:56:20.638885 <30>[ 18.454992] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
836 22:56:20.659387 <30>[ 18.475579] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
837 22:56:20.699610 <30>[ 18.522725] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
838 22:56:20.715279 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
839 22:56:20.750801 <30>[ 18.574740] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
840 22:56:20.776495 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
841 22:56:20.844564 <30>[ 18.666668] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
842 22:56:20.878523 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
843 22:56:20.930237 <30>[ 18.753007] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
844 22:56:20.952666 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
845 22:56:21.010305 <30>[ 18.833339] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
846 22:56:21.031907 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
847 22:56:21.090296 <30>[ 18.913833] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
848 22:56:21.113063 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
849 22:56:21.182169 <30>[ 19.004434] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
850 22:56:21.207291 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
851 22:56:21.260352 <30>[ 19.083715] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
852 22:56:21.279494 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
853 22:56:21.314636 <30>[ 19.137226] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
854 22:56:21.338335 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
855 22:56:21.368931 <28>[ 19.183822] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
856 22:56:21.375756 <28>[ 19.197839] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
857 22:56:21.419190 <30>[ 19.243005] systemd[1]: Starting systemd-journald.service - Journal Service...
858 22:56:21.438058 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
859 22:56:21.511417 <30>[ 19.334314] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
860 22:56:21.523650 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
861 22:56:21.589978 <30>[ 19.413236] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
862 22:56:21.641548 Starting [0;1;39msystemd-network-g… units from Kernel command line...
863 22:56:21.712909 <30>[ 19.535014] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
864 22:56:21.768969 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
865 22:56:21.815904 <30>[ 19.638462] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
866 22:56:21.880134 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
867 22:56:21.931439 <30>[ 19.754979] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
868 22:56:21.982147 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
869 22:56:21.988455 <30>[ 19.813776] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
870 22:56:22.028124 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
871 22:56:22.055753 <30>[ 19.878073] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
872 22:56:22.089700 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
873 22:56:22.239183 <30>[ 20.063134] systemd[1]: modprobe@configfs.service: Deactivated successfully.
874 22:56:22.269381 <30>[ 20.092077] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
875 22:56:22.278286 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
876 22:56:22.290434 <30>[ 20.114495] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
877 22:56:22.320295 <30>[ 20.143475] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
878 22:56:22.349524 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
879 22:56:22.370831 <30>[ 20.193385] systemd[1]: Started systemd-journald.service - Journal Service.
880 22:56:22.376964 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
881 22:56:22.410850 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
882 22:56:22.444621 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
883 22:56:22.480759 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
884 22:56:22.505173 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
885 22:56:22.539750 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
886 22:56:22.563009 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
887 22:56:22.592048 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
888 22:56:22.613777 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
889 22:56:22.682597 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
890 22:56:22.738458 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
891 22:56:22.790673 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
892 22:56:22.851887 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
893 22:56:22.924211 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
894 22:56:23.080025 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
895 22:56:23.179784 <46>[ 21.003172] systemd-journald[163]: Received client request to flush runtime journal.
896 22:56:23.252623 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
897 22:56:23.302225 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
898 22:56:24.134622 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
899 22:56:24.185977 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
900 22:56:24.850756 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
901 22:56:24.993154 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
902 22:56:25.028177 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
903 22:56:25.048829 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
904 22:56:25.119869 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
905 22:56:25.171177 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
906 22:56:26.097510 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
907 22:56:26.161371 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
908 22:56:26.289444 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
909 22:56:26.408773 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
910 22:56:26.433031 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
911 22:56:28.391971 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
912 22:56:29.088431 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
913 22:56:29.096622 <5>[ 26.918875] cfg80211: Loading compiled-in X.509 certificates for regulatory database
914 22:56:30.079339 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
915 22:56:30.522010 <5>[ 28.343317] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
916 22:56:30.527343 <5>[ 28.351434] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
917 22:56:30.548954 <4>[ 28.372214] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
918 22:56:30.554749 <6>[ 28.381311] cfg80211: failed to load regulatory.db
919 22:56:31.621750 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
920 22:56:31.646305 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
921 22:56:31.670510 <46>[ 29.485185] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
922 22:56:31.748264 <46>[ 29.565004] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
923 22:56:40.348973 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
924 22:56:40.375971 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
925 22:56:40.401058 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
926 22:56:40.421185 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
927 22:56:40.493699 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
928 22:56:40.570914 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
929 22:56:40.622641 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
930 22:56:40.660533 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
931 22:56:40.721806 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
932 22:56:40.753778 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
933 22:56:40.783489 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
934 22:56:40.826457 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
935 22:56:40.852942 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
936 22:56:40.900011 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
937 22:56:40.938181 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
938 22:56:40.960132 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
939 22:56:40.983970 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
940 22:56:41.024092 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
941 22:56:41.050353 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
942 22:56:41.069527 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
943 22:56:41.099754 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
944 22:56:41.119572 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
945 22:56:41.146510 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
946 22:56:41.220041 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
947 22:56:41.278285 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
948 22:56:41.373314 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
949 22:56:41.440767 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
950 22:56:41.489284 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
951 22:56:41.524696 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
952 22:56:41.557761 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
953 22:56:41.763519 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
954 22:56:41.828941 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
955 22:56:41.901011 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
956 22:56:41.919225 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
957 22:56:41.950214 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
958 22:56:42.185867 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
959 22:56:42.482318 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
960 22:56:42.534756 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
961 22:56:42.568767 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
962 22:56:42.623153 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
963 22:56:42.811248 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
964 22:56:42.941571
965 22:56:42.946107 Debian GNU/Linux 12 debian-bookwworm-armhf login: root (automatic login)
966 22:56:42.946699
967 22:56:43.255464 Linux debian-bookworm-armhf 6.12.0-rc2 #1 SMP Wed Nov 6 22:21:17 UTC 2024 armv7l
968 22:56:43.256045
969 22:56:43.261040 The programs included with the Debian GNU/Linux system are free software;
970 22:56:43.266615 the exact distribution terms for each program are described in the
971 22:56:43.272189 individual files in /usr/share/doc/*/copyright.
972 22:56:43.272909
973 22:56:43.280074 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
974 22:56:43.280591 permitted by applicable law.
975 22:56:47.933733 Unable to match end of the kernel message
977 22:56:47.935902 Setting prompt string to ['/ #']
978 22:56:47.936465 end: 2.4.4.1 login-action (duration 00:00:46) [common]
980 22:56:47.937777 end: 2.4.4 auto-login-action (duration 00:00:47) [common]
981 22:56:47.938354 start: 2.4.5 expect-shell-connection (timeout 00:03:13) [common]
982 22:56:47.938790 Setting prompt string to ['/ #']
983 22:56:47.939187 Forcing a shell prompt, looking for ['/ #']
985 22:56:47.990110 / #
986 22:56:47.990794 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
987 22:56:47.991239 Waiting using forced prompt support (timeout 00:02:30)
988 22:56:47.994671
989 22:56:48.003683 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
990 22:56:48.004271 start: 2.4.6 export-device-env (timeout 00:03:13) [common]
991 22:56:48.004719 Sending with 10 millisecond of delay
993 22:56:52.997859 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/949684/extract-nfsrootfs-ohwjovwi'
994 22:56:53.008674 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/949684/extract-nfsrootfs-ohwjovwi'
995 22:56:53.009692 Sending with 10 millisecond of delay
997 22:56:55.109769 / # export NFS_SERVER_IP='192.168.6.3'
998 22:56:55.120561 export NFS_SERVER_IP='192.168.6.3'
999 22:56:55.121470 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1000 22:56:55.121837 end: 2.4 uboot-commands (duration 00:01:54) [common]
1001 22:56:55.122339 end: 2 uboot-action (duration 00:01:54) [common]
1002 22:56:55.122765 start: 3 lava-test-retry (timeout 00:06:55) [common]
1003 22:56:55.123195 start: 3.1 lava-test-shell (timeout 00:06:55) [common]
1004 22:56:55.123558 Using namespace: common
1006 22:56:55.224402 / # #
1007 22:56:55.225038 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1008 22:56:55.228352 #
1009 22:56:55.235064 Using /lava-949684
1011 22:56:55.335783 / # export SHELL=/bin/bash
1012 22:56:55.340589 export SHELL=/bin/bash
1014 22:56:55.445739 / # . /lava-949684/environment
1015 22:56:55.450537 . /lava-949684/environment
1017 22:56:55.562418 / # /lava-949684/bin/lava-test-runner /lava-949684/0
1018 22:56:55.562908 Test shell timeout: 10s (minimum of the action and connection timeout)
1019 22:56:55.566735 /lava-949684/bin/lava-test-runner /lava-949684/0
1020 22:56:55.947884 + export TESTRUN_ID=0_timesync-off
1021 22:56:55.955803 + TESTRUN_ID=0_timesync-off
1022 22:56:55.956134 + cd /lava-949684/0/tests/0_timesync-off
1023 22:56:55.956376 ++ cat uuid
1024 22:56:55.971397 + UUID=949684_1.6.2.4.1
1025 22:56:55.971800 + set +x
1026 22:56:55.980025 <LAVA_SIGNAL_STARTRUN 0_timesync-off 949684_1.6.2.4.1>
1027 22:56:55.980344 + systemctl stop systemd-timesyncd
1028 22:56:55.980897 Received signal: <STARTRUN> 0_timesync-off 949684_1.6.2.4.1
1029 22:56:55.981181 Starting test lava.0_timesync-off (949684_1.6.2.4.1)
1030 22:56:55.981551 Skipping test definition patterns.
1031 22:56:56.273458 + set +x
1032 22:56:56.273919 <LAVA_SIGNAL_ENDRUN 0_timesync-off 949684_1.6.2.4.1>
1033 22:56:56.274417 Received signal: <ENDRUN> 0_timesync-off 949684_1.6.2.4.1
1034 22:56:56.274732 Ending use of test pattern.
1035 22:56:56.274975 Ending test lava.0_timesync-off (949684_1.6.2.4.1), duration 0.29
1037 22:56:56.487004 + export TESTRUN_ID=1_kselftest-dt
1038 22:56:56.494551 + TESTRUN_ID=1_kselftest-dt
1039 22:56:56.494881 + cd /lava-949684/0/tests/1_kselftest-dt
1040 22:56:56.495157 ++ cat uuid
1041 22:56:56.510544 + UUID=949684_1.6.2.4.5
1042 22:56:56.510923 + set +x
1043 22:56:56.516177 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 949684_1.6.2.4.5>
1044 22:56:56.516493 + cd ./automated/linux/kselftest/
1045 22:56:56.516946 Received signal: <STARTRUN> 1_kselftest-dt 949684_1.6.2.4.5
1046 22:56:56.517194 Starting test lava.1_kselftest-dt (949684_1.6.2.4.5)
1047 22:56:56.517464 Skipping test definition patterns.
1048 22:56:56.545157 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-4-gde156f3cf70e1/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1049 22:56:56.660869 INFO: install_deps skipped
1050 22:56:57.202005 --2024-11-06 22:56:57-- http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-4-gde156f3cf70e1/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1051 22:56:57.238157 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1052 22:56:57.379890 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1053 22:56:57.522244 HTTP request sent, awaiting response... 200 OK
1054 22:56:57.522586 Length: 4096476 (3.9M) [application/octet-stream]
1055 22:56:57.527799 Saving to: 'kselftest_armhf.tar.gz'
1056 22:56:57.528046
1057 22:56:58.933762
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 47.54K 173KB/s
kselftest_armhf.tar 5%[> ] 218.67K 394KB/s
kselftest_armhf.tar 17%[==> ] 695.39K 860KB/s
kselftest_armhf.tar 31%[=====> ] 1.22M 1.15MB/s
kselftest_armhf.tar 70%[=============> ] 2.77M 2.17MB/s
kselftest_armhf.tar 100%[===================>] 3.91M 2.78MB/s in 1.4s
1058 22:56:58.934367
1059 22:56:59.656421 2024-11-06 22:56:58 (2.78 MB/s) - 'kselftest_armhf.tar.gz' saved [4096476/4096476]
1060 22:56:59.656835
1061 22:57:13.868334 skiplist:
1062 22:57:13.868798 ========================================
1063 22:57:13.874076 ========================================
1064 22:57:13.983926 dt:test_unprobed_devices.sh
1065 22:57:14.016737 ============== Tests to run ===============
1066 22:57:14.023759 dt:test_unprobed_devices.sh
1067 22:57:14.027738 ===========End Tests to run ===============
1068 22:57:14.035454 shardfile-dt pass
1069 22:57:14.269540 <12>[ 72.098053] kselftest: Running tests in dt
1070 22:57:14.298978 TAP version 13
1071 22:57:14.321364 1..1
1072 22:57:14.375660 # timeout set to 45
1073 22:57:14.376196 # selftests: dt: test_unprobed_devices.sh
1074 22:57:15.185722 # TAP version 13
1075 22:57:40.079370 # 1..257
1076 22:57:40.241100 # ok 1 / # SKIP
1077 22:57:40.262358 # ok 2 /clk_mcasp0
1078 22:57:40.335462 # ok 3 /clk_mcasp0_fixed # SKIP
1079 22:57:40.406464 # ok 4 /cpus/cpu@0 # SKIP
1080 22:57:40.481087 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1081 22:57:40.497598 # ok 6 /fixedregulator0
1082 22:57:40.518246 # ok 7 /leds
1083 22:57:40.539041 # ok 8 /ocp
1084 22:57:40.566979 # ok 9 /ocp/interconnect@44c00000
1085 22:57:40.589954 # ok 10 /ocp/interconnect@44c00000/segment@0
1086 22:57:40.608359 # ok 11 /ocp/interconnect@44c00000/segment@100000
1087 22:57:40.633372 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1088 22:57:40.703744 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1089 22:57:40.728348 # ok 14 /ocp/interconnect@44c00000/segment@200000
1090 22:57:40.748066 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1091 22:57:40.854294 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1092 22:57:40.923878 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1093 22:57:40.995446 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1094 22:57:41.070323 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1095 22:57:41.135816 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1096 22:57:41.211571 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1097 22:57:41.278312 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1098 22:57:41.349200 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1099 22:57:41.420239 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1100 22:57:41.492271 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1101 22:57:41.563791 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1102 22:57:41.640257 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1103 22:57:41.706263 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1104 22:57:41.781433 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1105 22:57:41.852356 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1106 22:57:41.924300 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1107 22:57:41.994018 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1108 22:57:42.065957 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1109 22:57:42.132959 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1110 22:57:42.205124 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1111 22:57:42.278559 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1112 22:57:42.348375 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1113 22:57:42.420304 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1114 22:57:42.491501 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1115 22:57:42.562566 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1116 22:57:42.634023 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1117 22:57:42.706582 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1118 22:57:42.778424 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1119 22:57:42.850244 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1120 22:57:42.921094 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1121 22:57:42.993802 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1122 22:57:43.066374 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1123 22:57:43.139104 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1124 22:57:43.211403 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1125 22:57:43.282809 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1126 22:57:43.354304 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1127 22:57:43.427039 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1128 22:57:43.505723 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1129 22:57:43.573106 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1130 22:57:43.644085 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1131 22:57:43.716420 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1132 22:57:43.788027 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1133 22:57:43.858787 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1134 22:57:43.932505 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1135 22:57:44.005048 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1136 22:57:44.083049 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1137 22:57:44.149451 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1138 22:57:44.221007 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1139 22:57:44.292945 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1140 22:57:44.363984 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1141 22:57:44.436319 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1142 22:57:44.508582 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1143 22:57:44.580451 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1144 22:57:44.650847 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1145 22:57:44.723719 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1146 22:57:44.798037 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1147 22:57:44.870930 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1148 22:57:44.943184 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1149 22:57:45.014832 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1150 22:57:45.089750 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1151 22:57:45.162683 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1152 22:57:45.237017 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1153 22:57:45.306809 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1154 22:57:45.376021 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1155 22:57:45.448018 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1156 22:57:45.520532 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1157 22:57:45.592690 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1158 22:57:45.663605 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1159 22:57:45.735808 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1160 22:57:45.810257 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1161 22:57:45.883005 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1162 22:57:45.955227 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1163 22:57:46.025707 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1164 22:57:46.097776 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1165 22:57:46.172671 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1166 22:57:46.243337 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1167 22:57:46.316678 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1168 22:57:46.386976 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1169 22:57:46.455714 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1170 22:57:46.484362 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1171 22:57:46.504601 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1172 22:57:46.532809 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1173 22:57:46.550454 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1174 22:57:46.575258 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1175 22:57:46.598168 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1176 22:57:46.624377 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1177 22:57:46.649444 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1178 22:57:46.754311 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1179 22:57:46.779090 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1180 22:57:46.798888 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1181 22:57:46.822822 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1182 22:57:46.927604 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1183 22:57:47.001467 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1184 22:57:47.072164 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1185 22:57:47.143298 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1186 22:57:47.213523 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1187 22:57:47.285928 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1188 22:57:47.357286 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1189 22:57:47.432919 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1190 22:57:47.500004 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1191 22:57:47.571717 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1192 22:57:47.643034 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1193 22:57:47.714290 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1194 22:57:47.784365 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1195 22:57:47.858107 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1196 22:57:47.935365 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1197 22:57:48.002791 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1198 22:57:48.024011 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1199 22:57:48.094262 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1200 22:57:48.163663 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1201 22:57:48.240007 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1202 22:57:48.262038 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1203 22:57:48.343626 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1204 22:57:48.363383 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1205 22:57:48.432509 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1206 22:57:48.455242 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1207 22:57:48.478664 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1208 22:57:48.501940 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1209 22:57:48.526303 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1210 22:57:48.553432 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1211 22:57:48.572869 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1212 22:57:48.598141 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1213 22:57:48.671681 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1214 22:57:48.693056 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1215 22:57:48.716583 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1216 22:57:48.787885 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1217 22:57:48.861141 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1218 22:57:48.881967 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1219 22:57:48.980356 # not ok 144 /ocp/interconnect@47c00000
1220 22:57:49.055882 # not ok 145 /ocp/interconnect@47c00000/segment@0
1221 22:57:49.076396 # ok 146 /ocp/interconnect@48000000
1222 22:57:49.096156 # ok 147 /ocp/interconnect@48000000/segment@0
1223 22:57:49.122997 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1224 22:57:49.143886 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1225 22:57:49.171880 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1226 22:57:49.193143 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1227 22:57:49.218613 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1228 22:57:49.243654 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1229 22:57:49.266268 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1230 22:57:49.334232 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1231 22:57:49.404561 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1232 22:57:49.427403 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1233 22:57:49.453797 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1234 22:57:49.478679 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1235 22:57:49.503655 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1236 22:57:49.523126 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1237 22:57:49.545704 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1238 22:57:49.571200 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1239 22:57:49.593724 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1240 22:57:49.614043 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1241 22:57:49.642303 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1242 22:57:49.663016 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1243 22:57:49.688897 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1244 22:57:49.711215 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1245 22:57:49.733659 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1246 22:57:49.758851 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1247 22:57:49.782327 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1248 22:57:49.802949 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1249 22:57:49.825936 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1250 22:57:49.846156 # ok 175 /ocp/interconnect@48000000/segment@100000
1251 22:57:49.872338 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1252 22:57:49.896504 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1253 22:57:49.972664 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1254 22:57:50.045384 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1255 22:57:50.115200 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1256 22:57:50.187018 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1257 22:57:50.253408 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1258 22:57:50.326027 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1259 22:57:50.399587 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1260 22:57:50.473669 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1261 22:57:50.493336 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1262 22:57:50.515331 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1263 22:57:50.536150 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1264 22:57:50.559772 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1265 22:57:50.582997 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1266 22:57:50.611602 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1267 22:57:50.633345 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1268 22:57:50.658711 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1269 22:57:50.681520 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1270 22:57:50.703307 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1271 22:57:50.729216 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1272 22:57:50.753023 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1273 22:57:50.771739 # ok 198 /ocp/interconnect@48000000/segment@200000
1274 22:57:50.794651 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1275 22:57:50.870394 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1276 22:57:50.890490 # ok 201 /ocp/interconnect@48000000/segment@300000
1277 22:57:50.912959 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1278 22:57:50.938599 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1279 22:57:50.964026 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1280 22:57:50.981636 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1281 22:57:51.005925 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1282 22:57:51.028810 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1283 22:57:51.100016 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1284 22:57:51.120377 # ok 209 /ocp/interconnect@4a000000
1285 22:57:51.141926 # ok 210 /ocp/interconnect@4a000000/segment@0
1286 22:57:51.166019 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1287 22:57:51.191123 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1288 22:57:51.215751 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1289 22:57:51.237205 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1290 22:57:51.312824 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1291 22:57:51.415397 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1292 22:57:51.485316 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1293 22:57:51.587866 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1294 22:57:51.657165 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1295 22:57:51.731452 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1296 22:57:51.829416 # not ok 221 /ocp/interconnect@4b140000
1297 22:57:51.900651 # not ok 222 /ocp/interconnect@4b140000/segment@0
1298 22:57:51.967013 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1299 22:57:51.990461 # ok 224 /ocp/target-module@40300000
1300 22:57:52.011029 # ok 225 /ocp/target-module@40300000/sram@0
1301 22:57:52.084541 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1302 22:57:52.154238 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1303 22:57:52.177789 # ok 228 /ocp/target-module@47400000
1304 22:57:52.202279 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1305 22:57:52.221658 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1306 22:57:52.246914 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1307 22:57:52.270432 # ok 232 /ocp/target-module@47400000/usb@1400
1308 22:57:52.288564 # ok 233 /ocp/target-module@47400000/usb@1800
1309 22:57:52.315839 # ok 234 /ocp/target-module@47810000
1310 22:57:52.332428 # ok 235 /ocp/target-module@49000000
1311 22:57:52.355083 # ok 236 /ocp/target-module@49000000/dma@0
1312 22:57:52.380408 # ok 237 /ocp/target-module@49800000
1313 22:57:52.404547 # ok 238 /ocp/target-module@49800000/dma@0
1314 22:57:52.422819 # ok 239 /ocp/target-module@49900000
1315 22:57:52.449565 # ok 240 /ocp/target-module@49900000/dma@0
1316 22:57:52.466726 # ok 241 /ocp/target-module@49a00000
1317 22:57:52.491063 # ok 242 /ocp/target-module@49a00000/dma@0
1318 22:57:52.516332 # ok 243 /ocp/target-module@4c000000
1319 22:57:52.583218 # not ok 244 /ocp/target-module@4c000000/emif@0
1320 22:57:52.608450 # ok 245 /ocp/target-module@50000000
1321 22:57:52.630514 # ok 246 /ocp/target-module@53100000
1322 22:57:52.700429 # not ok 247 /ocp/target-module@53100000/sham@0
1323 22:57:52.727002 # ok 248 /ocp/target-module@53500000
1324 22:57:52.790452 # not ok 249 /ocp/target-module@53500000/aes@0
1325 22:57:52.812813 # ok 250 /ocp/target-module@56000000
1326 22:57:52.914407 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1327 22:57:52.987087 # ok 252 /opp-table # SKIP
1328 22:57:53.056403 # ok 253 /soc # SKIP
1329 22:57:53.073140 # ok 254 /sound
1330 22:57:53.100121 # ok 255 /target-module@4b000000
1331 22:57:53.125558 # ok 256 /target-module@4b000000/target-module@140000
1332 22:57:53.142981 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1333 22:57:53.151141 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1334 22:57:53.159097 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1335 22:57:55.200650 dt_test_unprobed_devices_sh_ skip
1336 22:57:55.206147 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1337 22:57:55.211581 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1338 22:57:55.212112 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1339 22:57:55.220471 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1340 22:57:55.220966 dt_test_unprobed_devices_sh_fixedregulator0 pass
1341 22:57:55.226156 dt_test_unprobed_devices_sh_leds pass
1342 22:57:55.231711 dt_test_unprobed_devices_sh_ocp pass
1343 22:57:55.237363 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1344 22:57:55.242975 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1345 22:57:55.248525 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1346 22:57:55.254199 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1347 22:57:55.265368 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1348 22:57:55.271030 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1349 22:57:55.276668 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1350 22:57:55.287802 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1351 22:57:55.299095 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1352 22:57:55.304613 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1353 22:57:55.315745 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1354 22:57:55.327000 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1355 22:57:55.338238 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1356 22:57:55.349438 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1357 22:57:55.355052 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1358 22:57:55.366222 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1359 22:57:55.377385 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1360 22:57:55.388638 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1361 22:57:55.394291 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1362 22:57:55.405392 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1363 22:57:55.416586 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1364 22:57:55.427828 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1365 22:57:55.439019 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1366 22:57:55.444655 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1367 22:57:55.455801 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1368 22:57:55.466983 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1369 22:57:55.478207 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1370 22:57:55.483867 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1371 22:57:55.495091 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1372 22:57:55.506146 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1373 22:57:55.517352 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1374 22:57:55.528554 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1375 22:57:55.539747 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1376 22:57:55.550965 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1377 22:57:55.562132 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1378 22:57:55.573350 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1379 22:57:55.584557 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1380 22:57:55.595702 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1381 22:57:55.606987 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1382 22:57:55.618098 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1383 22:57:55.629290 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1384 22:57:55.640489 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1385 22:57:55.651664 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1386 22:57:55.662874 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1387 22:57:55.674114 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1388 22:57:55.685278 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1389 22:57:55.696491 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1390 22:57:55.707638 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1391 22:57:55.718839 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1392 22:57:55.730106 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1393 22:57:55.735710 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1394 22:57:55.746825 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1395 22:57:55.758049 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1396 22:57:55.769199 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1397 22:57:55.780382 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1398 22:57:55.791583 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1399 22:57:55.802789 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1400 22:57:55.814064 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1401 22:57:55.825163 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1402 22:57:55.836315 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1403 22:57:55.847542 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1404 22:57:55.853217 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1405 22:57:55.864317 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1406 22:57:55.875553 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1407 22:57:55.886718 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1408 22:57:55.897928 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1409 22:57:55.909118 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1410 22:57:55.920323 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1411 22:57:55.931484 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1412 22:57:55.942716 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1413 22:57:55.953898 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1414 22:57:55.965050 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1415 22:57:55.976380 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1416 22:57:55.987619 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1417 22:57:55.998667 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1418 22:57:56.009990 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1419 22:57:56.015551 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1420 22:57:56.026722 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1421 22:57:56.037652 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1422 22:57:56.048963 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1423 22:57:56.060249 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1424 22:57:56.071452 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1425 22:57:56.082675 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1426 22:57:56.093855 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1427 22:57:56.105103 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1428 22:57:56.116205 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1429 22:57:56.127377 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1430 22:57:56.138595 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1431 22:57:56.144100 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1432 22:57:56.155353 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1433 22:57:56.166562 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1434 22:57:56.172170 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1435 22:57:56.183340 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1436 22:57:56.188996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1437 22:57:56.200104 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1438 22:57:56.211330 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1439 22:57:56.217029 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1440 22:57:56.228129 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1441 22:57:56.239316 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1442 22:57:56.250469 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1443 22:57:56.261668 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1444 22:57:56.272881 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1445 22:57:56.284081 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1446 22:57:56.300821 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1447 22:57:56.312063 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1448 22:57:56.323215 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1449 22:57:56.334447 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1450 22:57:56.345631 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1451 22:57:56.356847 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1452 22:57:56.368100 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1453 22:57:56.384809 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1454 22:57:56.396094 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1455 22:57:56.407166 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1456 22:57:56.423954 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1457 22:57:56.435181 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1458 22:57:56.440825 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1459 22:57:56.451959 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1460 22:57:56.457577 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1461 22:57:56.468729 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1462 22:57:56.479907 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1463 22:57:56.485557 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1464 22:57:56.496713 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1465 22:57:56.502345 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1466 22:57:56.513488 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1467 22:57:56.519145 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1468 22:57:56.530264 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1469 22:57:56.535889 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1470 22:57:56.547154 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1471 22:57:56.558251 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1472 22:57:56.569476 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1473 22:57:56.575168 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1474 22:57:56.586263 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1475 22:57:56.597437 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1476 22:57:56.608625 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1477 22:57:56.614298 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1478 22:57:56.619845 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1479 22:57:56.625461 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1480 22:57:56.631010 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1481 22:57:56.636639 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1482 22:57:56.647808 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1483 22:57:56.653412 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1484 22:57:56.664605 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1485 22:57:56.670209 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1486 22:57:56.675847 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1487 22:57:56.687018 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1488 22:57:56.692623 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1489 22:57:56.703761 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1490 22:57:56.709438 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1491 22:57:56.720582 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1492 22:57:56.726232 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1493 22:57:56.737349 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1494 22:57:56.742978 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1495 22:57:56.748593 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1496 22:57:56.759742 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1497 22:57:56.765369 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1498 22:57:56.776522 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1499 22:57:56.782168 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1500 22:57:56.793317 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1501 22:57:56.798957 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1502 22:57:56.810173 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1503 22:57:56.815738 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1504 22:57:56.827238 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1505 22:57:56.832597 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1506 22:57:56.843718 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1507 22:57:56.849333 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1508 22:57:56.860617 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1509 22:57:56.866152 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1510 22:57:56.871558 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1511 22:57:56.882783 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1512 22:57:56.894076 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1513 22:57:56.905224 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1514 22:57:56.916315 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1515 22:57:56.927532 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1516 22:57:56.933127 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1517 22:57:56.944312 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1518 22:57:56.955581 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1519 22:57:56.966760 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1520 22:57:56.978024 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1521 22:57:56.983560 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1522 22:57:56.994748 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1523 22:57:57.000412 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1524 22:57:57.011643 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1525 22:57:57.017349 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1526 22:57:57.029235 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1527 22:57:57.034112 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1528 22:57:57.045345 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1529 22:57:57.050857 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1530 22:57:57.062053 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1531 22:57:57.067690 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1532 22:57:57.078839 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1533 22:57:57.084508 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1534 22:57:57.095641 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1535 22:57:57.101253 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1536 22:57:57.106869 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1537 22:57:57.118009 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1538 22:57:57.123576 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1539 22:57:57.134800 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1540 22:57:57.140381 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1541 22:57:57.151532 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1542 22:57:57.157099 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1543 22:57:57.162694 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1544 22:57:57.168288 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1545 22:57:57.179498 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1546 22:57:57.185130 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1547 22:57:57.196241 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1548 22:57:57.201907 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1549 22:57:57.213130 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1550 22:57:57.224286 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1551 22:57:57.235436 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1552 22:57:57.241047 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1553 22:57:57.252420 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1554 22:57:57.263445 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1555 22:57:57.269153 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1556 22:57:57.274712 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1557 22:57:57.280278 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1558 22:57:57.285958 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1559 22:57:57.291536 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1560 22:57:57.297172 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1561 22:57:57.302812 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1562 22:57:57.308506 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1563 22:57:57.319591 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1564 22:57:57.325203 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1565 22:57:57.330811 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1566 22:57:57.336426 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1567 22:57:57.342276 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1568 22:57:57.347577 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1569 22:57:57.353199 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1570 22:57:57.358871 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1571 22:57:57.364382 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1572 22:57:57.370020 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1573 22:57:57.375588 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1574 22:57:57.381193 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1575 22:57:57.386854 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1576 22:57:57.392442 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1577 22:57:57.398267 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1578 22:57:57.403598 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1579 22:57:57.409177 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1580 22:57:57.414887 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1581 22:57:57.420404 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1582 22:57:57.425918 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1583 22:57:57.431509 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1584 22:57:57.437099 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1585 22:57:57.442736 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1586 22:57:57.448316 dt_test_unprobed_devices_sh_opp-table skip
1587 22:57:57.448802 dt_test_unprobed_devices_sh_soc skip
1588 22:57:57.453913 dt_test_unprobed_devices_sh_sound pass
1589 22:57:57.459506 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1590 22:57:57.465097 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1591 22:57:57.470749 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1592 22:57:57.476326 dt_test_unprobed_devices_sh fail
1593 22:57:57.481905 + ../../utils/send-to-lava.sh ./output/result.txt
1594 22:57:57.486570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1595 22:57:57.487462 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1597 22:57:57.538305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1598 22:57:57.539060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1600 22:57:57.629017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1601 22:57:57.629781 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1603 22:57:57.723616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1604 22:57:57.724364 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1606 22:57:57.814122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1607 22:57:57.814921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1609 22:57:57.906739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1610 22:57:57.907500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1612 22:57:57.999555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1613 22:57:58.000340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1615 22:57:58.089507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1616 22:57:58.090297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1618 22:57:58.182701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1619 22:57:58.183544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1621 22:57:58.277013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1622 22:57:58.277764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1624 22:57:58.370461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1625 22:57:58.371226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1627 22:57:58.462044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1628 22:57:58.462845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1630 22:57:58.556020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1631 22:57:58.556853 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1633 22:57:58.650036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1634 22:57:58.650865 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1636 22:57:58.739647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1637 22:57:58.740477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1639 22:57:58.833779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1640 22:57:58.834669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1642 22:57:58.926912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1643 22:57:58.927740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1645 22:57:59.018750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1646 22:57:59.019573 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1648 22:57:59.111758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1649 22:57:59.112529 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1651 22:57:59.204593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1652 22:57:59.205448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1654 22:57:59.295568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1655 22:57:59.296392 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1657 22:57:59.389690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1658 22:57:59.390555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1660 22:57:59.482640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1661 22:57:59.483484 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1663 22:57:59.574587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1664 22:57:59.575428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1666 22:57:59.666459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1667 22:57:59.667285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1669 22:57:59.759458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1670 22:57:59.760294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1672 22:57:59.851451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1673 22:57:59.852271 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1675 22:57:59.944379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1676 22:57:59.945200 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1678 22:58:00.036445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1679 22:58:00.037286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1681 22:58:00.129947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1682 22:58:00.130751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1684 22:58:00.222022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1685 22:58:00.222859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1687 22:58:00.315276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1688 22:58:00.316160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1690 22:58:00.408489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1691 22:58:00.409355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1693 22:58:00.501039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1694 22:58:00.501909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1696 22:58:00.594193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1697 22:58:00.595039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1699 22:58:00.685330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1700 22:58:00.686202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1702 22:58:00.779175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1703 22:58:00.780030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1705 22:58:00.872266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1706 22:58:00.873086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1708 22:58:00.965002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1709 22:58:00.965854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1711 22:58:01.057462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1712 22:58:01.058333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1714 22:58:01.153376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1715 22:58:01.154491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1717 22:58:01.244767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1718 22:58:01.245548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1720 22:58:01.338847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1721 22:58:01.339719 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1723 22:58:01.432118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1724 22:58:01.432951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1726 22:58:01.525498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1727 22:58:01.526387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1729 22:58:01.616246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1730 22:58:01.617072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1732 22:58:01.709014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1733 22:58:01.709868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1735 22:58:01.803587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1736 22:58:01.804430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1738 22:58:01.895725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1739 22:58:01.896381 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1741 22:58:01.997018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1742 22:58:01.997696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1744 22:58:02.097934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1745 22:58:02.098967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1747 22:58:02.192521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1748 22:58:02.193591 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1750 22:58:02.285233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1751 22:58:02.286258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1753 22:58:02.377350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1754 22:58:02.378221 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1756 22:58:02.471093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1757 22:58:02.471901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1759 22:58:02.563144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1760 22:58:02.563948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1762 22:58:02.656784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1763 22:58:02.657557 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1765 22:58:02.747931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1766 22:58:02.748728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1768 22:58:02.839042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1769 22:58:02.839876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1771 22:58:02.930232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1772 22:58:02.931053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1774 22:58:03.022493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1775 22:58:03.023360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1777 22:58:03.114292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1778 22:58:03.115159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1780 22:58:03.205571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1781 22:58:03.206158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1783 22:58:03.296752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1784 22:58:03.297357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1786 22:58:03.389692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1787 22:58:03.390297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1789 22:58:03.483313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1790 22:58:03.483897 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1792 22:58:03.576797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1793 22:58:03.577367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1795 22:58:03.670391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1796 22:58:03.670974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1798 22:58:03.762062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1799 22:58:03.762645 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1801 22:58:03.854168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1802 22:58:03.854738 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1804 22:58:03.945831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1805 22:58:03.946398 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1807 22:58:04.039310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1808 22:58:04.039876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1810 22:58:04.131681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1811 22:58:04.132239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1813 22:58:04.224613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1814 22:58:04.225179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1816 22:58:04.317244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1817 22:58:04.317838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1819 22:58:04.409998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1820 22:58:04.410565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1822 22:58:04.503823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1823 22:58:04.504365 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1825 22:58:04.596591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1826 22:58:04.597144 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1828 22:58:04.689301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1829 22:58:04.689884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1831 22:58:04.782402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1832 22:58:04.782988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1834 22:58:04.874687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1835 22:58:04.875259 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1837 22:58:04.972718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1838 22:58:04.973364 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1840 22:58:05.066502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1841 22:58:05.067072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1843 22:58:05.160836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1844 22:58:05.161376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1846 22:58:05.254196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1847 22:58:05.254756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1849 22:58:05.356147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1850 22:58:05.356703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1852 22:58:05.452883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1853 22:58:05.453464 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1855 22:58:05.544125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1856 22:58:05.544695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1858 22:58:05.636896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1859 22:58:05.637490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1861 22:58:05.732512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1862 22:58:05.733274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1864 22:58:05.823602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1865 22:58:05.824216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1867 22:58:05.913933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1868 22:58:05.914527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1870 22:58:06.002604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1871 22:58:06.003170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1873 22:58:06.094701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1874 22:58:06.095271 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1876 22:58:06.196659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1877 22:58:06.197202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1879 22:58:06.295471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1880 22:58:06.296040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1882 22:58:06.396353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1883 22:58:06.396953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1885 22:58:06.491292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1886 22:58:06.491891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1888 22:58:06.582992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1889 22:58:06.583584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1891 22:58:06.674653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1892 22:58:06.675248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1894 22:58:06.768156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1895 22:58:06.768766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1897 22:58:06.862494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1898 22:58:06.863111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1900 22:58:06.951584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1901 22:58:06.952185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1903 22:58:07.044180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1904 22:58:07.044775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1906 22:58:07.137709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1907 22:58:07.138334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1909 22:58:07.232303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1910 22:58:07.232927 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1912 22:58:07.325323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1913 22:58:07.325930 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1915 22:58:07.427028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1916 22:58:07.427662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1918 22:58:07.521839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1919 22:58:07.522450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1921 22:58:07.613345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1922 22:58:07.613986 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1924 22:58:07.706391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1925 22:58:07.706979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1927 22:58:07.798523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1928 22:58:07.799223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1930 22:58:07.897503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1931 22:58:07.898192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1933 22:58:07.989278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1934 22:58:07.989898 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1936 22:58:08.081163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1937 22:58:08.081745 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1939 22:58:08.183201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1940 22:58:08.183827 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1942 22:58:08.284784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1943 22:58:08.285409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1945 22:58:08.386084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1946 22:58:08.386759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1948 22:58:08.478824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1949 22:58:08.479431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1951 22:58:08.569148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1952 22:58:08.569713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1954 22:58:08.665713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1956 22:58:08.667885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1957 22:58:08.758771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1959 22:58:08.761885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1960 22:58:08.852302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1962 22:58:08.854445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1963 22:58:08.944427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1964 22:58:08.944990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1966 22:58:09.034262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1967 22:58:09.034831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1969 22:58:09.117655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1970 22:58:09.118256 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1972 22:58:09.210912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1973 22:58:09.211476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1975 22:58:09.301612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1976 22:58:09.302207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1978 22:58:09.392541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1979 22:58:09.393153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1981 22:58:09.482990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1982 22:58:09.483609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1984 22:58:09.578511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1985 22:58:09.579081 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1987 22:58:09.671799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1988 22:58:09.672403 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1990 22:58:09.763044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1991 22:58:09.763665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1993 22:58:09.857107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1994 22:58:09.857723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1996 22:58:09.950503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1997 22:58:09.951123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1999 22:58:10.050863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2000 22:58:10.051500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2002 22:58:10.146937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2003 22:58:10.147567 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2005 22:58:10.242463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2006 22:58:10.243098 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2008 22:58:10.337174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2009 22:58:10.337910 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2011 22:58:10.428975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2012 22:58:10.429557 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2014 22:58:10.522853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2015 22:58:10.523455 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2017 22:58:10.615145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2018 22:58:10.615758 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2020 22:58:10.710809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2021 22:58:10.711458 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2023 22:58:10.801590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2024 22:58:10.802197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2026 22:58:10.894258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2027 22:58:10.894844 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2029 22:58:10.993299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2030 22:58:10.993944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2032 22:58:11.086007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2033 22:58:11.086625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2035 22:58:11.182768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2036 22:58:11.183354 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2038 22:58:11.277608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2039 22:58:11.278254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2041 22:58:11.372188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2042 22:58:11.372809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2044 22:58:11.465185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2045 22:58:11.465833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2047 22:58:11.561243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2048 22:58:11.561873 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2050 22:58:11.651725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2051 22:58:11.652297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2053 22:58:11.747922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2054 22:58:11.748530 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2056 22:58:11.841150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2057 22:58:11.841774 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2059 22:58:11.936397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2060 22:58:11.936984 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2062 22:58:12.030953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2063 22:58:12.031569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2065 22:58:12.123017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2066 22:58:12.123623 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2068 22:58:12.216551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2069 22:58:12.217120 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2071 22:58:12.310415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2072 22:58:12.310993 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2074 22:58:12.403651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2075 22:58:12.404246 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2077 22:58:12.495629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2078 22:58:12.496230 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2080 22:58:12.589056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2081 22:58:12.589662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2083 22:58:12.681346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2084 22:58:12.681935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2086 22:58:12.775842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2087 22:58:12.776453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2089 22:58:12.866549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2090 22:58:12.867171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2092 22:58:12.958246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2093 22:58:12.958853 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2095 22:58:13.049751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2096 22:58:13.050355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2098 22:58:13.143668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2099 22:58:13.144246 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2101 22:58:13.239349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2102 22:58:13.240022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2104 22:58:13.333601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2105 22:58:13.334193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2107 22:58:13.425421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2108 22:58:13.426030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2110 22:58:13.520687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2111 22:58:13.521287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2113 22:58:13.613607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2114 22:58:13.614212 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2116 22:58:13.706829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2117 22:58:13.707419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2119 22:58:13.796700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2120 22:58:13.797297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2122 22:58:13.894381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2123 22:58:13.894991 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2125 22:58:13.990123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2126 22:58:13.990698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2128 22:58:14.083940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2129 22:58:14.084518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2131 22:58:14.178720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2132 22:58:14.179352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2134 22:58:14.270806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2135 22:58:14.271401 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2137 22:58:14.366297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2138 22:58:14.366916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2140 22:58:14.458782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2141 22:58:14.459380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2143 22:58:14.552720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2144 22:58:14.553341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2146 22:58:14.647154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2147 22:58:14.647756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2149 22:58:14.742298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2150 22:58:14.742921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2152 22:58:14.834270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2153 22:58:14.834881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2155 22:58:14.929929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2156 22:58:14.930535 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2158 22:58:15.023443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2159 22:58:15.024032 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2161 22:58:15.120342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2162 22:58:15.120954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2164 22:58:15.212896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2165 22:58:15.213483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2167 22:58:15.310632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2168 22:58:15.311217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2170 22:58:15.405484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2171 22:58:15.406580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2173 22:58:15.502850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2174 22:58:15.503743 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2176 22:58:15.599567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2177 22:58:15.600485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2179 22:58:15.695095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2180 22:58:15.695988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2182 22:58:15.792627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2183 22:58:15.793624 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2185 22:58:15.887326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2186 22:58:15.888491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2188 22:58:15.977423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2189 22:58:15.978334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2191 22:58:16.074610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2192 22:58:16.075241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2194 22:58:16.170084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2195 22:58:16.170958 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2197 22:58:16.261509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2198 22:58:16.262505 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2200 22:58:16.362804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2201 22:58:16.363843 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2203 22:58:16.455810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2204 22:58:16.456757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2206 22:58:16.554258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2207 22:58:16.555565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2209 22:58:16.646040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2210 22:58:16.646924 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2212 22:58:16.740795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2213 22:58:16.741594 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2215 22:58:16.832848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2216 22:58:16.833674 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2218 22:58:16.926529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2219 22:58:16.927313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2221 22:58:17.019069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2222 22:58:17.019923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2224 22:58:17.111406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2225 22:58:17.112215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2227 22:58:17.205945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2228 22:58:17.206746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2230 22:58:17.301558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2231 22:58:17.302639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2233 22:58:17.394499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2234 22:58:17.395430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2236 22:58:17.486195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2237 22:58:17.487129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2239 22:58:17.582025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2240 22:58:17.583032 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2242 22:58:17.674698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2243 22:58:17.675537 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2245 22:58:17.769206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2246 22:58:17.770173 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2248 22:58:17.863115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2249 22:58:17.864055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2251 22:58:17.956697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2252 22:58:17.957645 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2254 22:58:18.051119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2255 22:58:18.052191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2257 22:58:18.141262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2258 22:58:18.142070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2260 22:58:18.238913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2261 22:58:18.239865 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2263 22:58:18.333368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2264 22:58:18.334668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2266 22:58:18.427978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2267 22:58:18.428878 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2269 22:58:18.521314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2270 22:58:18.522260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2272 22:58:18.616070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2273 22:58:18.617008 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2275 22:58:18.709498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2277 22:58:18.712368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2278 22:58:18.804916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2279 22:58:18.805881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2281 22:58:18.903739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2282 22:58:18.904712 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2284 22:58:18.997298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2285 22:58:18.998072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2287 22:58:19.089676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2288 22:58:19.090327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2290 22:58:19.182776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2291 22:58:19.183359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2293 22:58:19.276588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2294 22:58:19.277191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2296 22:58:19.368640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2297 22:58:19.369250 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2299 22:58:19.461692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2300 22:58:19.462319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2302 22:58:19.554935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2303 22:58:19.555544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2305 22:58:19.647642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2306 22:58:19.648213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2308 22:58:19.742291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2309 22:58:19.742897 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2311 22:58:19.838528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2312 22:58:19.839097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2314 22:58:19.932866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2315 22:58:19.933469 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2317 22:58:20.028475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2318 22:58:20.029344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2320 22:58:20.122793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2321 22:58:20.123614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2323 22:58:20.214115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2324 22:58:20.214943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2326 22:58:20.307314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2327 22:58:20.308156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2329 22:58:20.398524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2330 22:58:20.399334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2332 22:58:20.492827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2333 22:58:20.495879 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2335 22:58:20.586619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2336 22:58:20.587464 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2338 22:58:20.679963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2339 22:58:20.680754 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2341 22:58:20.771231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2342 22:58:20.772066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2344 22:58:20.862529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2345 22:58:20.863357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2347 22:58:20.959592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2348 22:58:20.960418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2350 22:58:21.052192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2351 22:58:21.053010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2353 22:58:21.145055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2354 22:58:21.145875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2356 22:58:21.237254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2357 22:58:21.238045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2359 22:58:21.328388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2360 22:58:21.329179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2362 22:58:21.426620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2363 22:58:21.428800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2365 22:58:21.521534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2366 22:58:21.523888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2368 22:58:21.610108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2369 22:58:21.610632 + set +x
2370 22:58:21.611297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2372 22:58:21.613333 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 949684_1.6.2.4.5>
2373 22:58:21.614027 Received signal: <ENDRUN> 1_kselftest-dt 949684_1.6.2.4.5
2374 22:58:21.614473 Ending use of test pattern.
2375 22:58:21.614876 Ending test lava.1_kselftest-dt (949684_1.6.2.4.5), duration 85.10
2377 22:58:21.623615 <LAVA_TEST_RUNNER EXIT>
2378 22:58:21.624312 ok: lava_test_shell seems to have completed
2379 22:58:21.637220 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2380 22:58:21.639134 end: 3.1 lava-test-shell (duration 00:01:27) [common]
2381 22:58:21.639699 end: 3 lava-test-retry (duration 00:01:27) [common]
2382 22:58:21.640251 start: 4 finalize (timeout 00:05:29) [common]
2383 22:58:21.640794 start: 4.1 power-off (timeout 00:00:30) [common]
2384 22:58:21.641743 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-03'
2385 22:58:21.674344 >> OK - accepted request
2386 22:58:21.676345 Returned 0 in 0 seconds
2387 22:58:21.777513 end: 4.1 power-off (duration 00:00:00) [common]
2389 22:58:21.779292 start: 4.2 read-feedback (timeout 00:05:29) [common]
2390 22:58:21.780720 Listened to connection for namespace 'common' for up to 1s
2391 22:58:21.781599 Listened to connection for namespace 'common' for up to 1s
2392 22:58:22.780770 Finalising connection for namespace 'common'
2393 22:58:22.781339 Disconnecting from shell: Finalise
2394 22:58:22.781629 / #
2395 22:58:22.882279 end: 4.2 read-feedback (duration 00:00:01) [common]
2396 22:58:22.882766 end: 4 finalize (duration 00:00:01) [common]
2397 22:58:22.883129 Cleaning after the job
2398 22:58:22.883471 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949684/tftp-deploy-3gh0c2ah/ramdisk
2399 22:58:22.885111 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949684/tftp-deploy-3gh0c2ah/kernel
2400 22:58:22.886178 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949684/tftp-deploy-3gh0c2ah/dtb
2401 22:58:22.886905 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949684/tftp-deploy-3gh0c2ah/nfsrootfs
2402 22:58:22.937539 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949684/tftp-deploy-3gh0c2ah/modules
2403 22:58:22.941887 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/949684
2404 22:58:25.943683 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/949684
2405 22:58:25.944225 Job finished correctly