Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 14:56:40.335316 lava-dispatcher, installed at version: 2024.01
2 14:56:40.336111 start: 0 validate
3 14:56:40.336597 Start time: 2024-11-07 14:56:40.336569+00:00 (UTC)
4 14:56:40.337161 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 14:56:40.337692 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 14:56:40.372121 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 14:56:40.372675 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-5-g94debe5eaa0ad%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 14:56:40.396492 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 14:56:40.397093 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-5-g94debe5eaa0ad%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 14:56:40.423156 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 14:56:40.423977 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 14:56:40.446881 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 14:56:40.447362 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-5-g94debe5eaa0ad%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 14:56:40.477829 validate duration: 0.14
16 14:56:40.478772 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 14:56:40.479102 start: 1.1 download-retry (timeout 00:10:00) [common]
18 14:56:40.479389 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 14:56:40.479994 Not decompressing ramdisk as can be used compressed.
20 14:56:40.480413 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 14:56:40.480686 saving as /var/lib/lava/dispatcher/tmp/953176/tftp-deploy-iqhle6r4/ramdisk/initrd.cpio.gz
22 14:56:40.480953 total size: 4775763 (4 MB)
23 14:56:40.508458 progress 0 % (0 MB)
24 14:56:40.512179 progress 5 % (0 MB)
25 14:56:40.515482 progress 10 % (0 MB)
26 14:56:40.518704 progress 15 % (0 MB)
27 14:56:40.522291 progress 20 % (0 MB)
28 14:56:40.525380 progress 25 % (1 MB)
29 14:56:40.528498 progress 30 % (1 MB)
30 14:56:40.532027 progress 35 % (1 MB)
31 14:56:40.535187 progress 40 % (1 MB)
32 14:56:40.538339 progress 45 % (2 MB)
33 14:56:40.541483 progress 50 % (2 MB)
34 14:56:40.545070 progress 55 % (2 MB)
35 14:56:40.548244 progress 60 % (2 MB)
36 14:56:40.551384 progress 65 % (2 MB)
37 14:56:40.554921 progress 70 % (3 MB)
38 14:56:40.558050 progress 75 % (3 MB)
39 14:56:40.561171 progress 80 % (3 MB)
40 14:56:40.564319 progress 85 % (3 MB)
41 14:56:40.567585 progress 90 % (4 MB)
42 14:56:40.570485 progress 95 % (4 MB)
43 14:56:40.573370 progress 100 % (4 MB)
44 14:56:40.574034 4 MB downloaded in 0.09 s (48.94 MB/s)
45 14:56:40.574592 end: 1.1.1 http-download (duration 00:00:00) [common]
47 14:56:40.575474 end: 1.1 download-retry (duration 00:00:00) [common]
48 14:56:40.575780 start: 1.2 download-retry (timeout 00:10:00) [common]
49 14:56:40.576060 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 14:56:40.576543 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-5-g94debe5eaa0ad/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 14:56:40.576819 saving as /var/lib/lava/dispatcher/tmp/953176/tftp-deploy-iqhle6r4/kernel/zImage
52 14:56:40.577049 total size: 11440640 (10 MB)
53 14:56:40.577267 No compression specified
54 14:56:40.607142 progress 0 % (0 MB)
55 14:56:40.614794 progress 5 % (0 MB)
56 14:56:40.621886 progress 10 % (1 MB)
57 14:56:40.629774 progress 15 % (1 MB)
58 14:56:40.637606 progress 20 % (2 MB)
59 14:56:40.645269 progress 25 % (2 MB)
60 14:56:40.652695 progress 30 % (3 MB)
61 14:56:40.660903 progress 35 % (3 MB)
62 14:56:40.667954 progress 40 % (4 MB)
63 14:56:40.675420 progress 45 % (4 MB)
64 14:56:40.682460 progress 50 % (5 MB)
65 14:56:40.689905 progress 55 % (6 MB)
66 14:56:40.696891 progress 60 % (6 MB)
67 14:56:40.703925 progress 65 % (7 MB)
68 14:56:40.711718 progress 70 % (7 MB)
69 14:56:40.718730 progress 75 % (8 MB)
70 14:56:40.726120 progress 80 % (8 MB)
71 14:56:40.733071 progress 85 % (9 MB)
72 14:56:40.740441 progress 90 % (9 MB)
73 14:56:40.747346 progress 95 % (10 MB)
74 14:56:40.754148 progress 100 % (10 MB)
75 14:56:40.754584 10 MB downloaded in 0.18 s (61.46 MB/s)
76 14:56:40.755038 end: 1.2.1 http-download (duration 00:00:00) [common]
78 14:56:40.755838 end: 1.2 download-retry (duration 00:00:00) [common]
79 14:56:40.756105 start: 1.3 download-retry (timeout 00:10:00) [common]
80 14:56:40.756364 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 14:56:40.756839 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-5-g94debe5eaa0ad/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 14:56:40.757082 saving as /var/lib/lava/dispatcher/tmp/953176/tftp-deploy-iqhle6r4/dtb/am335x-boneblack.dtb
83 14:56:40.757286 total size: 70568 (0 MB)
84 14:56:40.757493 No compression specified
85 14:56:40.796581 progress 46 % (0 MB)
86 14:56:40.797398 progress 92 % (0 MB)
87 14:56:40.798104 progress 100 % (0 MB)
88 14:56:40.798498 0 MB downloaded in 0.04 s (1.63 MB/s)
89 14:56:40.798943 end: 1.3.1 http-download (duration 00:00:00) [common]
91 14:56:40.799744 end: 1.3 download-retry (duration 00:00:00) [common]
92 14:56:40.800024 start: 1.4 download-retry (timeout 00:10:00) [common]
93 14:56:40.800288 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 14:56:40.800750 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 14:56:40.800988 saving as /var/lib/lava/dispatcher/tmp/953176/tftp-deploy-iqhle6r4/nfsrootfs/full.rootfs.tar
96 14:56:40.801192 total size: 117747780 (112 MB)
97 14:56:40.801402 Using unxz to decompress xz
98 14:56:40.827987 progress 0 % (0 MB)
99 14:56:41.551975 progress 5 % (5 MB)
100 14:56:42.292174 progress 10 % (11 MB)
101 14:56:43.055110 progress 15 % (16 MB)
102 14:56:43.767156 progress 20 % (22 MB)
103 14:56:44.343379 progress 25 % (28 MB)
104 14:56:45.145551 progress 30 % (33 MB)
105 14:56:45.944571 progress 35 % (39 MB)
106 14:56:46.279667 progress 40 % (44 MB)
107 14:56:46.632498 progress 45 % (50 MB)
108 14:56:47.283517 progress 50 % (56 MB)
109 14:56:48.081603 progress 55 % (61 MB)
110 14:56:48.804397 progress 60 % (67 MB)
111 14:56:49.515235 progress 65 % (73 MB)
112 14:56:50.370559 progress 70 % (78 MB)
113 14:56:51.136169 progress 75 % (84 MB)
114 14:56:51.863498 progress 80 % (89 MB)
115 14:56:52.563681 progress 85 % (95 MB)
116 14:56:53.338194 progress 90 % (101 MB)
117 14:56:54.094762 progress 95 % (106 MB)
118 14:56:54.904442 progress 100 % (112 MB)
119 14:56:54.916706 112 MB downloaded in 14.12 s (7.96 MB/s)
120 14:56:54.917285 end: 1.4.1 http-download (duration 00:00:14) [common]
122 14:56:54.918484 end: 1.4 download-retry (duration 00:00:14) [common]
123 14:56:54.919056 start: 1.5 download-retry (timeout 00:09:46) [common]
124 14:56:54.919614 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 14:56:54.920738 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-5-g94debe5eaa0ad/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 14:56:54.921268 saving as /var/lib/lava/dispatcher/tmp/953176/tftp-deploy-iqhle6r4/modules/modules.tar
127 14:56:54.921858 total size: 6605760 (6 MB)
128 14:56:54.922331 Using unxz to decompress xz
129 14:56:54.956070 progress 0 % (0 MB)
130 14:56:54.990938 progress 5 % (0 MB)
131 14:56:55.033850 progress 10 % (0 MB)
132 14:56:55.076992 progress 15 % (0 MB)
133 14:56:55.120969 progress 20 % (1 MB)
134 14:56:55.167046 progress 25 % (1 MB)
135 14:56:55.209547 progress 30 % (1 MB)
136 14:56:55.251856 progress 35 % (2 MB)
137 14:56:55.295390 progress 40 % (2 MB)
138 14:56:55.338413 progress 45 % (2 MB)
139 14:56:55.381699 progress 50 % (3 MB)
140 14:56:55.425450 progress 55 % (3 MB)
141 14:56:55.474114 progress 60 % (3 MB)
142 14:56:55.521293 progress 65 % (4 MB)
143 14:56:55.564509 progress 70 % (4 MB)
144 14:56:55.611226 progress 75 % (4 MB)
145 14:56:55.653691 progress 80 % (5 MB)
146 14:56:55.696007 progress 85 % (5 MB)
147 14:56:55.738886 progress 90 % (5 MB)
148 14:56:55.781965 progress 95 % (6 MB)
149 14:56:55.825748 progress 100 % (6 MB)
150 14:56:55.838452 6 MB downloaded in 0.92 s (6.87 MB/s)
151 14:56:55.839139 end: 1.5.1 http-download (duration 00:00:01) [common]
153 14:56:55.840007 end: 1.5 download-retry (duration 00:00:01) [common]
154 14:56:55.840280 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 14:56:55.840551 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 14:57:12.406393 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/953176/extract-nfsrootfs-d7zdt34x
157 14:57:12.406992 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 14:57:12.407278 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 14:57:12.407881 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp
160 14:57:12.408335 makedir: /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin
161 14:57:12.408707 makedir: /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/tests
162 14:57:12.409032 makedir: /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/results
163 14:57:12.409386 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-add-keys
164 14:57:12.410061 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-add-sources
165 14:57:12.410684 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-background-process-start
166 14:57:12.411217 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-background-process-stop
167 14:57:12.411766 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-common-functions
168 14:57:12.412304 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-echo-ipv4
169 14:57:12.412853 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-install-packages
170 14:57:12.413369 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-installed-packages
171 14:57:12.413919 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-os-build
172 14:57:12.414462 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-probe-channel
173 14:57:12.415052 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-probe-ip
174 14:57:12.415580 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-target-ip
175 14:57:12.416122 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-target-mac
176 14:57:12.416627 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-target-storage
177 14:57:12.417154 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-test-case
178 14:57:12.417659 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-test-event
179 14:57:12.418195 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-test-feedback
180 14:57:12.418703 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-test-raise
181 14:57:12.419196 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-test-reference
182 14:57:12.419692 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-test-runner
183 14:57:12.420198 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-test-set
184 14:57:12.420700 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-test-shell
185 14:57:12.421254 Updating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-add-keys (debian)
186 14:57:12.421914 Updating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-add-sources (debian)
187 14:57:12.422549 Updating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-install-packages (debian)
188 14:57:12.423130 Updating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-installed-packages (debian)
189 14:57:12.423662 Updating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/bin/lava-os-build (debian)
190 14:57:12.424140 Creating /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/environment
191 14:57:12.424564 LAVA metadata
192 14:57:12.424830 - LAVA_JOB_ID=953176
193 14:57:12.425046 - LAVA_DISPATCHER_IP=192.168.6.3
194 14:57:12.425428 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 14:57:12.426435 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 14:57:12.426771 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 14:57:12.426978 skipped lava-vland-overlay
198 14:57:12.427218 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 14:57:12.427471 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 14:57:12.427692 skipped lava-multinode-overlay
201 14:57:12.427933 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 14:57:12.428183 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 14:57:12.428433 Loading test definitions
204 14:57:12.428712 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 14:57:12.428950 Using /lava-953176 at stage 0
206 14:57:12.430228 uuid=953176_1.6.2.4.1 testdef=None
207 14:57:12.430558 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 14:57:12.430822 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 14:57:12.432492 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 14:57:12.433305 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 14:57:12.435340 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 14:57:12.436181 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 14:57:12.438258 runner path: /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/0/tests/0_timesync-off test_uuid 953176_1.6.2.4.1
216 14:57:12.438878 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 14:57:12.439699 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 14:57:12.439947 Using /lava-953176 at stage 0
220 14:57:12.440319 Fetching tests from https://github.com/kernelci/test-definitions.git
221 14:57:12.440618 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/0/tests/1_kselftest-dt'
222 14:57:16.125138 Running '/usr/bin/git checkout kernelci.org
223 14:57:16.288395 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 14:57:16.289957 uuid=953176_1.6.2.4.5 testdef=None
225 14:57:16.290354 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 14:57:16.291188 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 14:57:16.294309 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 14:57:16.295242 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 14:57:16.299352 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 14:57:16.300328 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 14:57:16.304225 runner path: /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/0/tests/1_kselftest-dt test_uuid 953176_1.6.2.4.5
235 14:57:16.304545 BOARD='beaglebone-black'
236 14:57:16.304789 BRANCH='broonie-sound'
237 14:57:16.305022 SKIPFILE='/dev/null'
238 14:57:16.305347 SKIP_INSTALL='True'
239 14:57:16.305598 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-5-g94debe5eaa0ad/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 14:57:16.305853 TST_CASENAME=''
241 14:57:16.306097 TST_CMDFILES='dt'
242 14:57:16.306765 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 14:57:16.307614 Creating lava-test-runner.conf files
245 14:57:16.307827 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/953176/lava-overlay-7zxsucxp/lava-953176/0 for stage 0
246 14:57:16.308205 - 0_timesync-off
247 14:57:16.308469 - 1_kselftest-dt
248 14:57:16.308834 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 14:57:16.309125 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 14:57:40.231304 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 14:57:40.231759 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
252 14:57:40.232056 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 14:57:40.232366 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 14:57:40.232664 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
255 14:57:40.583240 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 14:57:40.583720 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 14:57:40.583972 extracting modules file /var/lib/lava/dispatcher/tmp/953176/tftp-deploy-iqhle6r4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/953176/extract-nfsrootfs-d7zdt34x
258 14:57:41.470566 extracting modules file /var/lib/lava/dispatcher/tmp/953176/tftp-deploy-iqhle6r4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/953176/extract-overlay-ramdisk-_v20d1z2/ramdisk
259 14:57:42.393752 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 14:57:42.394228 start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
261 14:57:42.394505 [common] Applying overlay to NFS
262 14:57:42.394719 [common] Applying overlay /var/lib/lava/dispatcher/tmp/953176/compress-overlay-q89vop5j/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/953176/extract-nfsrootfs-d7zdt34x
263 14:57:45.106953 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 14:57:45.107429 start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
265 14:57:45.107704 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
266 14:57:45.107982 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 14:57:45.108237 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 14:57:45.108494 start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
269 14:57:45.108740 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 14:57:45.108997 start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
271 14:57:45.109248 Building ramdisk /var/lib/lava/dispatcher/tmp/953176/extract-overlay-ramdisk-_v20d1z2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/953176/extract-overlay-ramdisk-_v20d1z2/ramdisk
272 14:57:46.088051 >> 74888 blocks
273 14:57:50.818167 Adding RAMdisk u-boot header.
274 14:57:50.818628 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/953176/extract-overlay-ramdisk-_v20d1z2/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/953176/extract-overlay-ramdisk-_v20d1z2/ramdisk.cpio.gz.uboot
275 14:57:50.971225 output: Image Name:
276 14:57:50.971631 output: Created: Thu Nov 7 14:57:50 2024
277 14:57:50.971840 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 14:57:50.972044 output: Data Size: 14791512 Bytes = 14444.84 KiB = 14.11 MiB
279 14:57:50.972247 output: Load Address: 00000000
280 14:57:50.972447 output: Entry Point: 00000000
281 14:57:50.972644 output:
282 14:57:50.973273 rename /var/lib/lava/dispatcher/tmp/953176/extract-overlay-ramdisk-_v20d1z2/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/953176/tftp-deploy-iqhle6r4/ramdisk/ramdisk.cpio.gz.uboot
283 14:57:50.973687 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 14:57:50.974248 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 14:57:50.974931 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:50) [common]
286 14:57:50.975443 No LXC device requested
287 14:57:50.975994 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 14:57:50.976553 start: 1.8 deploy-device-env (timeout 00:08:50) [common]
289 14:57:50.977091 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 14:57:50.977546 Checking files for TFTP limit of 4294967296 bytes.
291 14:57:50.980544 end: 1 tftp-deploy (duration 00:01:11) [common]
292 14:57:50.981175 start: 2 uboot-action (timeout 00:05:00) [common]
293 14:57:50.981749 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 14:57:50.982335 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 14:57:50.982888 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 14:57:50.983700 substitutions:
297 14:57:50.984163 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 14:57:50.984613 - {DTB_ADDR}: 0x88000000
299 14:57:50.985051 - {DTB}: 953176/tftp-deploy-iqhle6r4/dtb/am335x-boneblack.dtb
300 14:57:50.985488 - {INITRD}: 953176/tftp-deploy-iqhle6r4/ramdisk/ramdisk.cpio.gz.uboot
301 14:57:50.985952 - {KERNEL_ADDR}: 0x82000000
302 14:57:50.986389 - {KERNEL}: 953176/tftp-deploy-iqhle6r4/kernel/zImage
303 14:57:50.986823 - {LAVA_MAC}: None
304 14:57:50.987296 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/953176/extract-nfsrootfs-d7zdt34x
305 14:57:50.987733 - {NFS_SERVER_IP}: 192.168.6.3
306 14:57:50.988164 - {PRESEED_CONFIG}: None
307 14:57:50.988594 - {PRESEED_LOCAL}: None
308 14:57:50.989023 - {RAMDISK_ADDR}: 0x83000000
309 14:57:50.989449 - {RAMDISK}: 953176/tftp-deploy-iqhle6r4/ramdisk/ramdisk.cpio.gz.uboot
310 14:57:50.989903 - {ROOT_PART}: None
311 14:57:50.990329 - {ROOT}: None
312 14:57:50.990757 - {SERVER_IP}: 192.168.6.3
313 14:57:50.991181 - {TEE_ADDR}: 0x83000000
314 14:57:50.991605 - {TEE}: None
315 14:57:50.992028 Parsed boot commands:
316 14:57:50.992441 - setenv autoload no
317 14:57:50.992861 - setenv initrd_high 0xffffffff
318 14:57:50.993284 - setenv fdt_high 0xffffffff
319 14:57:50.993703 - dhcp
320 14:57:50.994202 - setenv serverip 192.168.6.3
321 14:57:50.994638 - tftp 0x82000000 953176/tftp-deploy-iqhle6r4/kernel/zImage
322 14:57:50.995064 - tftp 0x83000000 953176/tftp-deploy-iqhle6r4/ramdisk/ramdisk.cpio.gz.uboot
323 14:57:50.995489 - setenv initrd_size ${filesize}
324 14:57:50.995911 - tftp 0x88000000 953176/tftp-deploy-iqhle6r4/dtb/am335x-boneblack.dtb
325 14:57:50.996334 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/953176/extract-nfsrootfs-d7zdt34x,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 14:57:50.996771 - bootz 0x82000000 0x83000000 0x88000000
327 14:57:50.997309 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 14:57:50.998970 start: 2.3 connect-device (timeout 00:05:00) [common]
330 14:57:50.999434 [common] connect-device Connecting to device using 'telnet conserv3 3000'
331 14:57:51.014951 Setting prompt string to ['lava-test: # ']
332 14:57:51.016554 end: 2.3 connect-device (duration 00:00:00) [common]
333 14:57:51.017201 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 14:57:51.017845 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 14:57:51.018438 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 14:57:51.019742 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-03'
337 14:57:51.054186 >> OK - accepted request
338 14:57:51.056011 Returned 0 in 0 seconds
339 14:57:51.157166 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 14:57:51.158959 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 14:57:51.159560 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 14:57:51.160108 Setting prompt string to ['Hit any key to stop autoboot']
344 14:57:51.160606 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 14:57:51.162294 Trying 192.168.56.22...
346 14:57:51.162825 Connected to conserv3.
347 14:57:51.163282 Escape character is '^]'.
348 14:57:51.163734
349 14:57:51.164193 ser2net port telnet,3000 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 14:57:51.164646
351 14:57:59.734213
352 14:57:59.741066 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
353 14:57:59.741606 Trying to boot from MMC1
354 14:58:00.329041
355 14:58:00.329464
356 14:58:00.334622 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
357 14:58:00.335074
358 14:58:00.335576 CPU : AM335X-GP rev 2.0
359 14:58:00.339724 Model: TI AM335x BeagleBone Black
360 14:58:00.340044 DRAM: 512 MiB
361 14:58:03.894295
362 14:58:03.901223 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
363 14:58:03.901538 Trying to boot from MMC1
364 14:58:04.488148
365 14:58:04.488584
366 14:58:04.493529 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
367 14:58:04.493993
368 14:58:04.494488 CPU : AM335X-GP rev 2.0
369 14:58:04.498699 Model: TI AM335x BeagleBone Black
370 14:58:04.498992 DRAM: 512 MiB
371 14:58:06.593705
372 14:58:06.600640 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
373 14:58:06.601147 Trying to boot from MMC1
374 14:58:07.186664
375 14:58:07.187314
376 14:58:07.191919 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
377 14:58:07.192453
378 14:58:07.192916 CPU : AM335X-GP rev 2.0
379 14:58:07.197219 Model: TI AM335x BeagleBone Black
380 14:58:07.197742 DRAM: 512 MiB
381 14:58:07.281625 Core: 160 devices, 18 uclasses, devicetree: separate
382 14:58:07.295584 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
383 14:58:07.695562 NAND: 0 MiB
384 14:58:07.706357 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
385 14:58:07.780958 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
386 14:58:07.802339 <ethaddr> not set. Validating first E-fuse MAC
387 14:58:07.832048 Net: eth2: ethernet@4a100000, eth3: usb_ether
389 14:58:07.890726 Hit any key to stop autoboot: 2
390 14:58:07.891641 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
391 14:58:07.892342 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
392 14:58:07.892911 Setting prompt string to ['=>']
393 14:58:07.893457 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
394 14:58:07.900427 0
395 14:58:07.901470 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
396 14:58:07.902101 Sending with 10 millisecond of delay
398 14:58:09.037366 => setenv autoload no
399 14:58:09.048421 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
400 14:58:09.054959 setenv autoload no
401 14:58:09.056009 Sending with 10 millisecond of delay
403 14:58:10.857780 => setenv initrd_high 0xffffffff
404 14:58:10.868829 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
405 14:58:10.870015 setenv initrd_high 0xffffffff
406 14:58:10.870922 Sending with 10 millisecond of delay
408 14:58:12.488434 => setenv fdt_high 0xffffffff
409 14:58:12.499247 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
410 14:58:12.500169 setenv fdt_high 0xffffffff
411 14:58:12.500917 Sending with 10 millisecond of delay
413 14:58:12.792908 => dhcp
414 14:58:12.803882 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
415 14:58:12.804980 dhcp
416 14:58:12.805650 link up on port 0, speed 100, full duplex
417 14:58:12.806248 BOOTP broadcast 1
418 14:58:13.057281 BOOTP broadcast 2
419 14:58:13.560238 BOOTP broadcast 3
420 14:58:13.641969 DHCP client bound to address 192.168.6.23 (833 ms)
421 14:58:13.642841 Sending with 10 millisecond of delay
423 14:58:15.320243 => setenv serverip 192.168.6.3
424 14:58:15.330993 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
425 14:58:15.331824 setenv serverip 192.168.6.3
426 14:58:15.332530 Sending with 10 millisecond of delay
428 14:58:18.815639 => tftp 0x82000000 953176/tftp-deploy-iqhle6r4/kernel/zImage
429 14:58:18.826508 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
430 14:58:18.827463 tftp 0x82000000 953176/tftp-deploy-iqhle6r4/kernel/zImage
431 14:58:18.827954 link up on port 0, speed 100, full duplex
432 14:58:18.831497 Using ethernet@4a100000 device
433 14:58:18.837041 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
434 14:58:18.843678 Filename '953176/tftp-deploy-iqhle6r4/kernel/zImage'.
435 14:58:18.844077 Load address: 0x82000000
436 14:58:20.993539 Loading: *################################################## 10.9 MiB
437 14:58:20.994191 5.1 MiB/s
438 14:58:20.994604 done
439 14:58:20.997797 Bytes transferred = 11440640 (ae9200 hex)
440 14:58:20.998624 Sending with 10 millisecond of delay
442 14:58:25.447151 => tftp 0x83000000 953176/tftp-deploy-iqhle6r4/ramdisk/ramdisk.cpio.gz.uboot
443 14:58:25.457702 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
444 14:58:25.458283 tftp 0x83000000 953176/tftp-deploy-iqhle6r4/ramdisk/ramdisk.cpio.gz.uboot
445 14:58:25.458526 link up on port 0, speed 100, full duplex
446 14:58:25.463125 Using ethernet@4a100000 device
447 14:58:25.468249 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
448 14:58:25.476754 Filename '953176/tftp-deploy-iqhle6r4/ramdisk/ramdisk.cpio.gz.uboot'.
449 14:58:25.477100 Load address: 0x83000000
450 14:58:28.267524 Loading: *################################################## 14.1 MiB
451 14:58:28.268142 5.1 MiB/s
452 14:58:28.268599 done
453 14:58:28.271652 Bytes transferred = 14791576 (e1b398 hex)
454 14:58:28.272466 Sending with 10 millisecond of delay
456 14:58:30.132495 => setenv initrd_size ${filesize}
457 14:58:30.143495 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
458 14:58:30.144707 setenv initrd_size ${filesize}
459 14:58:30.145643 Sending with 10 millisecond of delay
461 14:58:34.294013 => tftp 0x88000000 953176/tftp-deploy-iqhle6r4/dtb/am335x-boneblack.dtb
462 14:58:34.304854 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
463 14:58:34.305784 tftp 0x88000000 953176/tftp-deploy-iqhle6r4/dtb/am335x-boneblack.dtb
464 14:58:34.306327 link up on port 0, speed 100, full duplex
465 14:58:34.309296 Using ethernet@4a100000 device
466 14:58:34.314874 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
467 14:58:34.322446 Filename '953176/tftp-deploy-iqhle6r4/dtb/am335x-boneblack.dtb'.
468 14:58:34.323017 Load address: 0x88000000
469 14:58:34.335875 Loading: *################################################## 68.9 KiB
470 14:58:34.345687 4.5 MiB/s
471 14:58:34.346196 done
472 14:58:34.346631 Bytes transferred = 70568 (113a8 hex)
473 14:58:34.347345 Sending with 10 millisecond of delay
475 14:58:47.543033 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/953176/extract-nfsrootfs-d7zdt34x,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
476 14:58:47.553909 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
477 14:58:47.554872 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/953176/extract-nfsrootfs-d7zdt34x,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 14:58:47.555636 Sending with 10 millisecond of delay
480 14:58:49.895970 => bootz 0x82000000 0x83000000 0x88000000
481 14:58:49.906726 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
482 14:58:49.907095 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:01)
483 14:58:49.907684 bootz 0x82000000 0x83000000 0x88000000
484 14:58:49.907942 Kernel image @ 0x82000000 [ 0x000000 - 0xae9200 ]
485 14:58:49.908758 ## Loading init Ramdisk from Legacy Image at 83000000 ...
486 14:58:49.914613 Image Name:
487 14:58:49.914942 Created: 2024-11-07 14:57:50 UTC
488 14:58:49.923274 Image Type: ARM Linux RAMDisk Image (uncompressed)
489 14:58:49.923627 Data Size: 14791512 Bytes = 14.1 MiB
490 14:58:49.931746 Load Address: 00000000
491 14:58:49.932117 Entry Point: 00000000
492 14:58:50.100155 Verifying Checksum ... OK
493 14:58:50.100590 ## Flattened Device Tree blob at 88000000
494 14:58:50.106505 Booting using the fdt blob at 0x88000000
495 14:58:50.106876 Working FDT set to 88000000
496 14:58:50.112148 Using Device Tree in place at 88000000, end 880143a7
497 14:58:50.116636 Working FDT set to 88000000
498 14:58:50.129896
499 14:58:50.130674 Starting kernel ...
500 14:58:50.131361
501 14:58:50.132582 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 14:58:50.133454 start: 2.4.4 auto-login-action (timeout 00:04:01) [common]
503 14:58:50.134127 Setting prompt string to ['Linux version [0-9]']
504 14:58:50.134660 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
505 14:58:50.135188 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
506 14:58:50.972741 [ 0.000000] Booting Linux on physical CPU 0x0
507 14:58:50.978862 start: 2.4.4.1 login-action (timeout 00:04:00) [common]
508 14:58:50.979507 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 14:58:50.980008 Setting prompt string to []
510 14:58:50.980531 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 14:58:50.981023 Using line separator: #'\n'#
512 14:58:50.981463 No login prompt set.
513 14:58:50.981985 Parsing kernel messages
514 14:58:50.982424 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 14:58:50.983318 [login-action] Waiting for messages, (timeout 00:04:00)
516 14:58:50.983834 Waiting using forced prompt support (timeout 00:02:00)
517 14:58:50.995380 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j366895-arm-gcc-12-multi-v7-defconfig-6xnvh) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Thu Nov 7 13:40:45 UTC 2024
518 14:58:51.001061 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 14:58:51.006976 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 14:58:51.018519 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 14:58:51.024127 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 14:58:51.029834 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 14:58:51.030367 [ 0.000000] Memory policy: Data cache writeback
524 14:58:51.036480 [ 0.000000] efi: UEFI not found.
525 14:58:51.045359 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 14:58:51.045730 [ 0.000000] Zone ranges:
527 14:58:51.051142 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 14:58:51.056776 [ 0.000000] Normal empty
529 14:58:51.062491 [ 0.000000] HighMem empty
530 14:58:51.063092 [ 0.000000] Movable zone start for each node
531 14:58:51.068069 [ 0.000000] Early memory node ranges
532 14:58:51.073897 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 14:58:51.081626 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 14:58:51.107012 [ 0.000000] CPU: All CPU(s) started in SVC mode.
535 14:58:51.112543 [ 0.000000] AM335X ES2.0 (sgx neon)
536 14:58:51.124200 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
537 14:58:51.141907 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/953176/extract-nfsrootfs-d7zdt34x,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
538 14:58:51.153411 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
539 14:58:51.159226 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
540 14:58:51.164892 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
541 14:58:51.174077 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
542 14:58:51.204013 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
543 14:58:51.209951 <6>[ 0.000000] trace event string verifier disabled
544 14:58:51.210530 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
545 14:58:51.215827 <6>[ 0.000000] rcu: RCU event tracing is enabled.
546 14:58:51.227131 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
547 14:58:51.232884 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
548 14:58:51.239179 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
549 14:58:51.255084 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
550 14:58:51.272363 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
551 14:58:51.278930 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
552 14:58:51.370865 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
553 14:58:51.382102 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
554 14:58:51.388793 <6>[ 0.008334] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
555 14:58:51.400955 <6>[ 0.019141] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
556 14:58:51.409109 <6>[ 0.033925] Console: colour dummy device 80x30
557 14:58:51.415224 Matched prompt #6: WARNING:
558 14:58:51.415785 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
559 14:58:51.420607 <3>[ 0.038824] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
560 14:58:51.426344 <3>[ 0.045893] This ensures that you still see kernel messages. Please
561 14:58:51.429580 <3>[ 0.052621] update your kernel commandline.
562 14:58:51.470423 <6>[ 0.057232] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
563 14:58:51.476175 <6>[ 0.096146] CPU: Testing write buffer coherency: ok
564 14:58:51.482010 <6>[ 0.101513] CPU0: Spectre v2: using BPIALL workaround
565 14:58:51.482578 <6>[ 0.106978] pid_max: default: 32768 minimum: 301
566 14:58:51.493475 <6>[ 0.112172] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 14:58:51.500446 <6>[ 0.119996] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 14:58:51.507528 <6>[ 0.129355] CPU0: thread -1, cpu 0, socket -1, mpidr 0
569 14:58:51.515956 <6>[ 0.136350] Setting up static identity map for 0x80300000 - 0x803000ac
570 14:58:51.521708 <6>[ 0.145997] rcu: Hierarchical SRCU implementation.
571 14:58:51.528568 <6>[ 0.151280] rcu: Max phase no-delay instances is 1000.
572 14:58:51.537892 <6>[ 0.162390] EFI services will not be available.
573 14:58:51.543668 <6>[ 0.167673] smp: Bringing up secondary CPUs ...
574 14:58:51.549413 <6>[ 0.172716] smp: Brought up 1 node, 1 CPU
575 14:58:51.555225 <6>[ 0.177119] SMP: Total of 1 processors activated (996.14 BogoMIPS).
576 14:58:51.561187 <6>[ 0.183888] CPU: All CPU(s) started in SVC mode.
577 14:58:51.581529 <6>[ 0.189069] Memory: 405996K/522240K available (16384K kernel code, 2542K rwdata, 6784K rodata, 2048K init, 431K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
578 14:58:51.582205 <6>[ 0.205346] devtmpfs: initialized
579 14:58:51.603621 <6>[ 0.222375] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
580 14:58:51.615178 <6>[ 0.230954] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
581 14:58:51.620220 <6>[ 0.241415] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
582 14:58:51.631058 <6>[ 0.253752] pinctrl core: initialized pinctrl subsystem
583 14:58:51.641234 <6>[ 0.264381] DMI not present or invalid.
584 14:58:51.649439 <6>[ 0.270228] NET: Registered PF_NETLINK/PF_ROUTE protocol family
585 14:58:51.658555 <6>[ 0.279111] DMA: preallocated 256 KiB pool for atomic coherent allocations
586 14:58:51.674215 <6>[ 0.290645] thermal_sys: Registered thermal governor 'step_wise'
587 14:58:51.674674 <6>[ 0.290809] cpuidle: using governor menu
588 14:58:51.701717 <6>[ 0.326358] No ATAGs?
589 14:58:51.707843 <6>[ 0.328998] hw-breakpoint: debug architecture 0x4 unsupported.
590 14:58:51.718234 <6>[ 0.341040] Serial: AMBA PL011 UART driver
591 14:58:51.750879 <6>[ 0.375355] iommu: Default domain type: Translated
592 14:58:51.759821 <6>[ 0.380702] iommu: DMA domain TLB invalidation policy: strict mode
593 14:58:51.786618 <5>[ 0.410616] SCSI subsystem initialized
594 14:58:51.792440 <6>[ 0.415507] usbcore: registered new interface driver usbfs
595 14:58:51.798134 <6>[ 0.421569] usbcore: registered new interface driver hub
596 14:58:51.804929 <6>[ 0.427349] usbcore: registered new device driver usb
597 14:58:51.810617 <6>[ 0.433865] pps_core: LinuxPPS API ver. 1 registered
598 14:58:51.822207 <6>[ 0.439252] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
599 14:58:51.829417 <6>[ 0.448983] PTP clock support registered
600 14:58:51.829974 <6>[ 0.453441] EDAC MC: Ver: 3.0.0
601 14:58:51.878250 <6>[ 0.500362] scmi_core: SCMI protocol bus registered
602 14:58:51.892737 <6>[ 0.517710] vgaarb: loaded
603 14:58:51.906023 <6>[ 0.530731] clocksource: Switched to clocksource dmtimer
604 14:58:51.942636 <6>[ 0.566883] NET: Registered PF_INET protocol family
605 14:58:51.954994 <6>[ 0.572573] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
606 14:58:51.962233 <6>[ 0.581392] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
607 14:58:51.967952 <6>[ 0.590320] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
608 14:58:51.976781 <6>[ 0.598577] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
609 14:58:51.988206 <6>[ 0.606866] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
610 14:58:51.994155 <6>[ 0.614589] TCP: Hash tables configured (established 4096 bind 4096)
611 14:58:52.002761 <6>[ 0.621494] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
612 14:58:52.008649 <6>[ 0.628533] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
613 14:58:52.014520 <6>[ 0.636138] NET: Registered PF_UNIX/PF_LOCAL protocol family
614 14:58:52.105785 <6>[ 0.724890] RPC: Registered named UNIX socket transport module.
615 14:58:52.106446 <6>[ 0.731280] RPC: Registered udp transport module.
616 14:58:52.111613 <6>[ 0.736432] RPC: Registered tcp transport module.
617 14:58:52.120159 <6>[ 0.741557] RPC: Registered tcp-with-tls transport module.
618 14:58:52.125991 <6>[ 0.747465] RPC: Registered tcp NFSv4.1 backchannel transport module.
619 14:58:52.133180 <6>[ 0.754389] PCI: CLS 0 bytes, default 64
620 14:58:52.135662 <5>[ 0.760166] Initialise system trusted keyrings
621 14:58:52.157018 <6>[ 0.778733] Trying to unpack rootfs image as initramfs...
622 14:58:52.242522 <6>[ 0.861070] workingset: timestamp_bits=30 max_order=17 bucket_order=0
623 14:58:52.247355 <6>[ 0.868617] squashfs: version 4.0 (2009/01/31) Phillip Lougher
624 14:58:52.267792 <5>[ 0.892562] NFS: Registering the id_resolver key type
625 14:58:52.273679 <5>[ 0.898165] Key type id_resolver registered
626 14:58:52.279425 <5>[ 0.902847] Key type id_legacy registered
627 14:58:52.285164 <6>[ 0.907287] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
628 14:58:52.294871 <6>[ 0.914483] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
629 14:58:52.363646 <5>[ 0.988336] Key type asymmetric registered
630 14:58:52.369740 <5>[ 0.992919] Asymmetric key parser 'x509' registered
631 14:58:52.380980 <6>[ 0.998346] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
632 14:58:52.381485 <6>[ 1.006268] io scheduler mq-deadline registered
633 14:58:52.386947 <6>[ 1.011198] io scheduler kyber registered
634 14:58:52.391526 <6>[ 1.015683] io scheduler bfq registered
635 14:58:52.515151 <6>[ 1.137274] ledtrig-cpu: registered to indicate activity on CPUs
636 14:58:52.797092 <6>[ 1.418230] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
637 14:58:52.832745 <6>[ 1.457043] msm_serial: driver initialized
638 14:58:52.838502 <6>[ 1.462081] SuperH (H)SCI(F) driver initialized
639 14:58:52.844586 <6>[ 1.467191] STMicroelectronics ASC driver initialized
640 14:58:52.849672 <6>[ 1.472853] STM32 USART driver initialized
641 14:58:52.969372 <6>[ 1.593529] brd: module loaded
642 14:58:53.001622 <6>[ 1.625574] loop: module loaded
643 14:58:53.055383 <6>[ 1.679197] CAN device driver interface
644 14:58:53.061939 <6>[ 1.684437] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
645 14:58:53.067657 <6>[ 1.691398] e1000e: Intel(R) PRO/1000 Network Driver
646 14:58:53.073573 <6>[ 1.696854] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
647 14:58:53.079228 <6>[ 1.703293] igb: Intel(R) Gigabit Ethernet Network Driver
648 14:58:53.087555 <6>[ 1.709115] igb: Copyright (c) 2007-2014 Intel Corporation.
649 14:58:53.099223 <6>[ 1.718316] pegasus: Pegasus/Pegasus II USB Ethernet driver
650 14:58:53.105088 <6>[ 1.724470] usbcore: registered new interface driver pegasus
651 14:58:53.110870 <6>[ 1.730598] usbcore: registered new interface driver asix
652 14:58:53.116690 <6>[ 1.736479] usbcore: registered new interface driver ax88179_178a
653 14:58:53.122405 <6>[ 1.743065] usbcore: registered new interface driver cdc_ether
654 14:58:53.128207 <6>[ 1.749363] usbcore: registered new interface driver smsc75xx
655 14:58:53.133977 <6>[ 1.755588] usbcore: registered new interface driver smsc95xx
656 14:58:53.139738 <6>[ 1.761818] usbcore: registered new interface driver net1080
657 14:58:53.145553 <6>[ 1.767947] usbcore: registered new interface driver cdc_subset
658 14:58:53.151312 <6>[ 1.774364] usbcore: registered new interface driver zaurus
659 14:58:53.158984 <6>[ 1.780407] usbcore: registered new interface driver cdc_ncm
660 14:58:53.167794 <6>[ 1.789834] usbcore: registered new interface driver usb-storage
661 14:58:53.440984 <6>[ 2.063818] i2c_dev: i2c /dev entries driver
662 14:58:53.501427 <5>[ 2.118200] cpuidle: enable-method property 'ti,am3352' found operations
663 14:58:53.507237 <6>[ 2.127782] sdhci: Secure Digital Host Controller Interface driver
664 14:58:53.514727 <6>[ 2.134552] sdhci: Copyright(c) Pierre Ossman
665 14:58:53.521778 <6>[ 2.140947] Synopsys Designware Multimedia Card Interface Driver
666 14:58:53.527005 <6>[ 2.148855] sdhci-pltfm: SDHCI platform and OF driver helper
667 14:58:53.644240 <6>[ 2.262590] usbcore: registered new interface driver usbhid
668 14:58:53.644621 <6>[ 2.268633] usbhid: USB HID core driver
669 14:58:53.696080 <6>[ 2.318233] NET: Registered PF_INET6 protocol family
670 14:58:53.728368 <6>[ 2.353148] Segment Routing with IPv6
671 14:58:53.734260 <6>[ 2.357294] In-situ OAM (IOAM) with IPv6
672 14:58:53.740883 <6>[ 2.361836] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
673 14:58:53.748270 <6>[ 2.369077] NET: Registered PF_PACKET protocol family
674 14:58:53.754223 <6>[ 2.374649] can: controller area network core
675 14:58:53.754764 <6>[ 2.379476] NET: Registered PF_CAN protocol family
676 14:58:53.760004 <6>[ 2.384705] can: raw protocol
677 14:58:53.762829 <6>[ 2.388030] can: broadcast manager protocol
678 14:58:53.769253 <6>[ 2.392626] can: netlink gateway - max_hops=1
679 14:58:53.775372 <5>[ 2.398137] Key type dns_resolver registered
680 14:58:53.781118 <6>[ 2.403221] ThumbEE CPU extension supported.
681 14:58:53.787383 <5>[ 2.407905] Registering SWP/SWPB emulation handler
682 14:58:53.792759 <3>[ 2.413607] omap_voltage_late_init: Voltage driver support not added
683 14:58:53.990127 <5>[ 2.612285] Loading compiled-in X.509 certificates
684 14:58:54.116260 <6>[ 2.728070] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
685 14:58:54.123397 <6>[ 2.744747] pinctrl-single 44e10800.pinmux: 142 pins, size 568
686 14:58:54.148961 <3>[ 2.768455] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
687 14:58:54.356260 <3>[ 2.974979] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
688 14:58:54.549645 <6>[ 3.172573] OMAP GPIO hardware version 0.1
689 14:58:54.570105 <6>[ 3.191199] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
690 14:58:54.673388 <4>[ 3.294122] at24 2-0054: supply vcc not found, using dummy regulator
691 14:58:54.705289 <4>[ 3.326069] at24 2-0055: supply vcc not found, using dummy regulator
692 14:58:54.754671 <4>[ 3.375437] at24 2-0056: supply vcc not found, using dummy regulator
693 14:58:54.795342 <4>[ 3.416157] at24 2-0057: supply vcc not found, using dummy regulator
694 14:58:54.836537 <6>[ 3.458119] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
695 14:58:54.907460 <3>[ 3.525011] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
696 14:58:54.932099 <6>[ 3.546032] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
697 14:58:54.954051 <4>[ 3.572813] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
698 14:58:54.961778 <4>[ 3.581339] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
699 14:58:55.070641 <6>[ 3.692590] omap_rng 48310000.rng: Random Number Generator ver. 20
700 14:58:55.094240 <5>[ 3.719034] random: crng init done
701 14:58:55.142401 <6>[ 3.761908] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
702 14:58:55.166921 <6>[ 3.790870] Freeing initrd memory: 14448K
703 14:58:55.215523 <6>[ 3.834017] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
704 14:58:55.221363 <6>[ 3.844358] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
705 14:58:55.233060 <6>[ 3.851733] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
706 14:58:55.238961 <6>[ 3.859200] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
707 14:58:55.250381 <6>[ 3.867333] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
708 14:58:55.257796 <6>[ 3.878973] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5c:d5:d8
709 14:58:55.270124 <5>[ 3.887986] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
710 14:58:55.298637 <3>[ 3.917737] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
711 14:58:55.303600 <6>[ 3.926327] edma 49000000.dma: TI EDMA DMA engine driver
712 14:58:55.375474 <3>[ 3.993855] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
713 14:58:55.390169 <6>[ 4.008208] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
714 14:58:55.403203 <3>[ 4.025330] l3-aon-clkctrl:0000:0: failed to disable
715 14:58:55.456278 <6>[ 4.075349] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
716 14:58:55.461924 <6>[ 4.084850] printk: legacy console [ttyS0] enabled
717 14:58:55.464729 <6>[ 4.084850] printk: legacy console [ttyS0] enabled
718 14:58:55.470285 <6>[ 4.095185] printk: legacy bootconsole [omap8250] disabled
719 14:58:55.479249 <6>[ 4.095185] printk: legacy bootconsole [omap8250] disabled
720 14:58:55.514419 <4>[ 4.132360] tps65217-pmic: Failed to locate of_node [id: -1]
721 14:58:55.517191 <4>[ 4.139760] tps65217-bl: Failed to locate of_node [id: -1]
722 14:58:55.534417 <6>[ 4.159368] tps65217 0-0024: TPS65217 ID 0xe version 1.2
723 14:58:55.553051 <6>[ 4.166313] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
724 14:58:55.564403 <6>[ 4.180000] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
725 14:58:55.570129 <6>[ 4.191885] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
726 14:58:55.592341 <6>[ 4.211855] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
727 14:58:55.598251 <6>[ 4.220912] sdhci-omap 48060000.mmc: Got CD GPIO
728 14:58:55.606277 <4>[ 4.226104] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
729 14:58:55.622487 <4>[ 4.239660] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
730 14:58:55.629318 <4>[ 4.249753] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
731 14:58:55.638132 <4>[ 4.258877] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
732 14:58:55.760799 <6>[ 4.381383] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
733 14:58:55.810157 <6>[ 4.428691] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
734 14:58:55.816577 <6>[ 4.437384] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
735 14:58:55.824609 <6>[ 4.446293] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
736 14:58:55.875479 <6>[ 4.491040] mmc0: new high speed SDHC card at address 0001
737 14:58:55.876046 <6>[ 4.498455] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
738 14:58:55.882189 <6>[ 4.506857] mmcblk0: p1
739 14:58:55.904313 <6>[ 4.521101] mmc1: new high speed MMC card at address 0001
740 14:58:55.904850 <6>[ 4.528194] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
741 14:58:55.916969 <6>[ 4.536016] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
742 14:58:55.923383 <6>[ 4.547297] mmcblk1:
743 14:58:55.925458 <6>[ 4.550650] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
744 14:58:55.934726 <6>[ 4.558104] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
745 14:58:55.950269 <6>[ 4.571411] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
746 14:58:58.063448 <6>[ 6.682605] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
747 14:58:58.176828 <5>[ 6.721658] Sending DHCP requests ., OK
748 14:58:58.188258 <6>[ 6.806141] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.23
749 14:58:58.188584 <6>[ 6.814327] IP-Config: Complete:
750 14:58:58.199483 <6>[ 6.817866] device=eth0, hwaddr=90:59:af:5c:d5:d8, ipaddr=192.168.6.23, mask=255.255.255.0, gw=192.168.6.1
751 14:58:58.205388 <6>[ 6.828383] host=192.168.6.23, domain=, nis-domain=(none)
752 14:58:58.217752 <6>[ 6.834594] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
753 14:58:58.218467 <6>[ 6.834627] nameserver0=10.255.253.1
754 14:58:58.223790 <6>[ 6.847238] clk: Disabling unused clocks
755 14:58:58.228677 <6>[ 6.851951] PM: genpd: Disabling unused power domains
756 14:58:58.248571 <6>[ 6.870866] Freeing unused kernel image (initmem) memory: 2048K
757 14:58:58.256001 <6>[ 6.880623] Run /init as init process
758 14:58:58.281991 Loading, please wait...
759 14:58:58.357131 Starting systemd-udevd version 252.22-1~deb12u1
760 14:59:01.425537 <4>[ 10.043275] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
761 14:59:01.595448 <4>[ 10.213169] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
762 14:59:01.765623 <6>[ 10.390683] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
763 14:59:01.776462 <6>[ 10.396510] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
764 14:59:01.972281 <6>[ 10.595846] hub 1-0:1.0: USB hub found
765 14:59:02.061657 <6>[ 10.685212] hub 1-0:1.0: 1 port detected
766 14:59:02.086495 <6>[ 10.709909] tda998x 0-0070: found TDA19988
767 14:59:04.980393 Begin: Loading essential drivers ... done.
768 14:59:04.985862 Begin: Running /scripts/init-premount ... done.
769 14:59:04.991631 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
770 14:59:05.005403 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
771 14:59:05.005683 Device /sys/class/net/eth0 found
772 14:59:05.005926 done.
773 14:59:05.075360 Begin: Waiting up to 180 secs for any network device to become available ... done.
774 14:59:05.149454 IP-Config: eth0 hardware address 90:59:af:5c:d5:d8 mtu 1500 DHCP
775 14:59:05.289360 IP-Config: eth0 guessed broadcast address 192.168.6.255
776 14:59:05.294972 IP-Config: eth0 complete (dhcp from 192.168.6.1):
777 14:59:05.300477 address: 192.168.6.23 broadcast: 192.168.6.255 netmask: 255.255.255.0
778 14:59:05.311793 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
779 14:59:05.312711 rootserver: 192.168.6.1 rootpath:
780 14:59:05.315302 filename :
781 14:59:05.373543 done.
782 14:59:05.389734 Begin: Running /scripts/nfs-bottom ... done.
783 14:59:05.459995 Begin: Running /scripts/init-bottom ... done.
784 14:59:06.803498 <30>[ 15.424385] systemd[1]: System time before build time, advancing clock.
785 14:59:07.032559 <30>[ 15.627358] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
786 14:59:07.046110 <30>[ 15.668895] systemd[1]: Detected architecture arm.
787 14:59:07.058199
788 14:59:07.058787 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
789 14:59:07.059261
790 14:59:07.079357 <30>[ 15.701189] systemd[1]: Hostname set to <debian-bookworm-armhf>.
791 14:59:09.193585 <30>[ 17.813943] systemd[1]: Queued start job for default target graphical.target.
792 14:59:09.210181 <30>[ 17.828439] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
793 14:59:09.217749 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
794 14:59:09.247649 <30>[ 17.867459] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
795 14:59:09.261216 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
796 14:59:09.286324 <30>[ 17.904971] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
797 14:59:09.294733 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
798 14:59:09.314733 <30>[ 17.933589] systemd[1]: Created slice user.slice - User and Session Slice.
799 14:59:09.321461 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
800 14:59:09.349837 <30>[ 17.962934] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
801 14:59:09.355919 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
802 14:59:09.374117 <30>[ 17.992733] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
803 14:59:09.385080 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
804 14:59:09.414534 <30>[ 18.022645] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
805 14:59:09.421039 <30>[ 18.043049] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
806 14:59:09.429313 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
807 14:59:09.453013 <30>[ 18.072121] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
808 14:59:09.461134 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
809 14:59:09.483561 <30>[ 18.102442] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
810 14:59:09.491732 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
811 14:59:09.516730 <30>[ 18.134011] systemd[1]: Reached target paths.target - Path Units.
812 14:59:09.521948 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
813 14:59:09.543014 <30>[ 18.162176] systemd[1]: Reached target remote-fs.target - Remote File Systems.
814 14:59:09.550067 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
815 14:59:09.572859 <30>[ 18.192075] systemd[1]: Reached target slices.target - Slice Units.
816 14:59:09.578373 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
817 14:59:09.603318 <30>[ 18.222452] systemd[1]: Reached target swap.target - Swaps.
818 14:59:09.607446 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
819 14:59:09.633660 <30>[ 18.252355] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
820 14:59:09.641595 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
821 14:59:09.666040 <30>[ 18.284892] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
822 14:59:09.678686 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
823 14:59:09.759635 <30>[ 18.374664] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
824 14:59:09.773337 <30>[ 18.392398] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
825 14:59:09.781847 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
826 14:59:09.805139 <30>[ 18.423476] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
827 14:59:09.812511 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
828 14:59:09.842342 <30>[ 18.460404] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
829 14:59:09.850176 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
830 14:59:09.875011 <30>[ 18.495534] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
831 14:59:09.886458 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
832 14:59:09.917099 <30>[ 18.534946] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
833 14:59:09.924664 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
834 14:59:09.950189 <30>[ 18.563261] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
835 14:59:09.966786 <30>[ 18.579695] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
836 14:59:10.012927 <30>[ 18.632112] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
837 14:59:10.020580 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
838 14:59:10.051365 <30>[ 18.671027] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
839 14:59:10.082565 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
840 14:59:10.136167 <30>[ 18.754904] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
841 14:59:10.158553 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
842 14:59:10.203555 <30>[ 18.822908] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
843 14:59:10.213386 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
844 14:59:10.240965 <30>[ 18.860671] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
845 14:59:10.273919 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
846 14:59:10.324787 <30>[ 18.944939] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
847 14:59:10.351674 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
848 14:59:10.403854 <30>[ 19.022944] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
849 14:59:10.423387 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
850 14:59:10.456520 <30>[ 19.076693] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
851 14:59:10.490960 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
852 14:59:10.544124 <30>[ 19.164271] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
853 14:59:10.569567 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
854 14:59:10.600589 <28>[ 19.214037] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
855 14:59:10.609118 <28>[ 19.228384] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
856 14:59:10.654364 <30>[ 19.274968] systemd[1]: Starting systemd-journald.service - Journal Service...
857 14:59:10.671583 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
858 14:59:10.733140 <30>[ 19.352865] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
859 14:59:10.752423 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
860 14:59:10.784305 <30>[ 19.404300] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
861 14:59:10.833389 Starting [0;1;39msystemd-network-g… units from Kernel command line...
862 14:59:10.877026 <30>[ 19.496184] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
863 14:59:10.931833 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
864 14:59:11.005794 <30>[ 19.625067] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
865 14:59:11.048309 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
866 14:59:11.138332 <30>[ 19.758531] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
867 14:59:11.195983 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
868 14:59:11.223912 <30>[ 19.843896] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
869 14:59:11.242820 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
870 14:59:11.264514 <30>[ 19.884405] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
871 14:59:11.296201 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
872 14:59:11.455253 <30>[ 20.076089] systemd[1]: modprobe@configfs.service: Deactivated successfully.
873 14:59:11.493887 <30>[ 20.113537] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
874 14:59:11.522751 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
875 14:59:11.543815 <30>[ 20.163291] systemd[1]: Started systemd-journald.service - Journal Service.
876 14:59:11.550716 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
877 14:59:11.590349 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
878 14:59:11.621124 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
879 14:59:11.648818 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
880 14:59:11.683960 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
881 14:59:11.713950 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
882 14:59:11.735564 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
883 14:59:11.763244 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
884 14:59:11.786143 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
885 14:59:11.817573 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
886 14:59:11.882472 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
887 14:59:11.927729 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
888 14:59:11.974570 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
889 14:59:12.064492 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
890 14:59:12.123302 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
891 14:59:12.262065 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
892 14:59:12.352617 <46>[ 20.972524] systemd-journald[163]: Received client request to flush runtime journal.
893 14:59:12.433141 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
894 14:59:13.009652 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
895 14:59:13.320075 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
896 14:59:13.380174 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
897 14:59:13.972081 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
898 14:59:14.073756 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
899 14:59:14.094064 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
900 14:59:14.112630 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
901 14:59:14.172888 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
902 14:59:14.214202 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
903 14:59:15.178441 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
904 14:59:15.247970 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
905 14:59:15.332878 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
906 14:59:15.472535 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
907 14:59:15.503802 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
908 14:59:16.020103 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
909 14:59:16.658052 <5>[ 25.278153] cfg80211: Loading compiled-in X.509 certificates for regulatory database
910 14:59:18.127490 [[0m[0;31m* [0m] (1 of 4) Job dev-ttyS0.device/start running (8s / 1min 30s)
911 14:59:18.335012 <5>[ 26.953181] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
912 14:59:18.343180 <5>[ 26.961284] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
913 14:59:18.348733 <4>[ 26.971395] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
914 14:59:18.357058 <6>[ 26.980508] cfg80211: failed to load regulatory.db
915 14:59:18.601503 M
[K[[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
916 14:59:19.139180 [K[[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
917 14:59:19.566954 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
918 14:59:19.587848 <46>[ 28.199058] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
919 14:59:19.639698 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
920 14:59:19.778491 <46>[ 28.391959] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
921 14:59:29.530172 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
922 14:59:29.553610 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
923 14:59:29.574801 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
924 14:59:29.594822 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
925 14:59:29.652845 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
926 14:59:29.695000 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
927 14:59:29.725612 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
928 14:59:29.780626 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
929 14:59:29.830400 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
930 14:59:29.874197 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
931 14:59:29.898747 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
932 14:59:29.927940 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
933 14:59:29.968758 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
934 14:59:30.000205 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
935 14:59:30.036151 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
936 14:59:30.070355 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
937 14:59:30.114118 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
938 14:59:30.135934 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
939 14:59:30.164507 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
940 14:59:30.183233 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
941 14:59:30.220298 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
942 14:59:30.243181 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
943 14:59:30.265342 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
944 14:59:30.343589 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
945 14:59:30.383313 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
946 14:59:30.477090 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
947 14:59:30.566562 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
948 14:59:30.634078 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
949 14:59:30.688042 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
950 14:59:30.713710 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
951 14:59:30.899118 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
952 14:59:30.963533 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
953 14:59:31.008021 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
954 14:59:31.032729 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
955 14:59:31.043221 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
956 14:59:31.271759 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
957 14:59:31.646818 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
958 14:59:31.706266 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
959 14:59:31.749867 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
960 14:59:31.841617 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
961 14:59:32.017370 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
962 14:59:32.168039
963 14:59:32.171588 Debian GNU/Linux 12 debirm-armhf login: root (automatic login)
964 14:59:32.172045
965 14:59:32.501924 Linux debian-bookworm-armhf 6.12.0-rc2 #1 SMP Thu Nov 7 13:40:45 UTC 2024 armv7l
966 14:59:32.502542
967 14:59:32.507572 The programs included with the Debian GNU/Linux system are free software;
968 14:59:32.513270 the exact distribution terms for each program are described in the
969 14:59:32.518818 individual files in /usr/share/doc/*/copyright.
970 14:59:32.519332
971 14:59:32.525769 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
972 14:59:32.526252 permitted by applicable law.
973 14:59:37.142197 Unable to match end of the kernel message
975 14:59:37.143776 Setting prompt string to ['/ #']
976 14:59:37.144353 end: 2.4.4.1 login-action (duration 00:00:46) [common]
978 14:59:37.145749 end: 2.4.4 auto-login-action (duration 00:00:47) [common]
979 14:59:37.146333 start: 2.4.5 expect-shell-connection (timeout 00:03:14) [common]
980 14:59:37.146798 Setting prompt string to ['/ #']
981 14:59:37.147233 Forcing a shell prompt, looking for ['/ #']
983 14:59:37.198225 / #
984 14:59:37.198908 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
985 14:59:37.199412 Waiting using forced prompt support (timeout 00:02:30)
986 14:59:37.203353
987 14:59:37.243783 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
988 14:59:37.244398 start: 2.4.6 export-device-env (timeout 00:03:14) [common]
989 14:59:37.244877 Sending with 10 millisecond of delay
991 14:59:42.233844 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/953176/extract-nfsrootfs-d7zdt34x'
992 14:59:42.244782 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/953176/extract-nfsrootfs-d7zdt34x'
993 14:59:42.245885 Sending with 10 millisecond of delay
995 14:59:44.344214 / # export NFS_SERVER_IP='192.168.6.3'
996 14:59:44.355002 export NFS_SERVER_IP='192.168.6.3'
997 14:59:44.355729 end: 2.4.6 export-device-env (duration 00:00:07) [common]
998 14:59:44.356106 end: 2.4 uboot-commands (duration 00:01:53) [common]
999 14:59:44.356461 end: 2 uboot-action (duration 00:01:53) [common]
1000 14:59:44.356800 start: 3 lava-test-retry (timeout 00:06:56) [common]
1001 14:59:44.357132 start: 3.1 lava-test-shell (timeout 00:06:56) [common]
1002 14:59:44.357389 Using namespace: common
1004 14:59:44.458222 / # #
1005 14:59:44.458763 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1006 14:59:44.463379 #
1007 14:59:44.468175 Using /lava-953176
1009 14:59:44.569012 / # export SHELL=/bin/bash
1010 14:59:44.574342 export SHELL=/bin/bash
1012 14:59:44.680606 / # . /lava-953176/environment
1013 14:59:44.685929 . /lava-953176/environment
1015 14:59:44.798775 / # /lava-953176/bin/lava-test-runner /lava-953176/0
1016 14:59:44.799314 Test shell timeout: 10s (minimum of the action and connection timeout)
1017 14:59:44.804087 /lava-953176/bin/lava-test-runner /lava-953176/0
1018 14:59:45.181379 + export TESTRUN_ID=0_timesync-off
1019 14:59:45.188488 + TESTRUN_ID=0_timesync-off
1020 14:59:45.188816 + cd /lava-953176/0/tests/0_timesync-off
1021 14:59:45.189072 ++ cat uuid
1022 14:59:45.204850 + UUID=953176_1.6.2.4.1
1023 14:59:45.205199 + set +x
1024 14:59:45.213383 <LAVA_SIGNAL_STARTRUN 0_timesync-off 953176_1.6.2.4.1>
1025 14:59:45.213686 + systemctl stop systemd-timesyncd
1026 14:59:45.214181 Received signal: <STARTRUN> 0_timesync-off 953176_1.6.2.4.1
1027 14:59:45.214445 Starting test lava.0_timesync-off (953176_1.6.2.4.1)
1028 14:59:45.214767 Skipping test definition patterns.
1029 14:59:45.498837 + set +x
1030 14:59:45.499286 <LAVA_SIGNAL_ENDRUN 0_timesync-off 953176_1.6.2.4.1>
1031 14:59:45.499776 Received signal: <ENDRUN> 0_timesync-off 953176_1.6.2.4.1
1032 14:59:45.500081 Ending use of test pattern.
1033 14:59:45.500310 Ending test lava.0_timesync-off (953176_1.6.2.4.1), duration 0.29
1035 14:59:45.652703 + export TESTRUN_ID=1_kselftest-dt
1036 14:59:45.660579 + TESTRUN_ID=1_kselftest-dt
1037 14:59:45.660887 + cd /lava-953176/0/tests/1_kselftest-dt
1038 14:59:45.661124 ++ cat uuid
1039 14:59:45.676186 + UUID=953176_1.6.2.4.5
1040 14:59:45.676500 + set +x
1041 14:59:45.681618 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 953176_1.6.2.4.5>
1042 14:59:45.681944 + cd ./automated/linux/kselftest/
1043 14:59:45.682407 Received signal: <STARTRUN> 1_kselftest-dt 953176_1.6.2.4.5
1044 14:59:45.682659 Starting test lava.1_kselftest-dt (953176_1.6.2.4.5)
1045 14:59:45.682944 Skipping test definition patterns.
1046 14:59:45.711543 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-5-g94debe5eaa0ad/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1047 14:59:45.821886 INFO: install_deps skipped
1048 14:59:46.376602 --2024-11-07 14:59:46-- http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-5-g94debe5eaa0ad/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1049 14:59:46.402655 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1050 14:59:46.545912 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1051 14:59:46.684754 HTTP request sent, awaiting response... 200 OK
1052 14:59:46.685258 Length: 4098284 (3.9M) [application/octet-stream]
1053 14:59:46.690319 Saving to: 'kselftest_armhf.tar.gz'
1054 14:59:46.690745
1055 14:59:48.371196
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 180KB/s
kselftest_armhf.tar 4%[ ] 194.76K 346KB/s
kselftest_armhf.tar 19%[==> ] 771.76K 928KB/s
kselftest_armhf.tar 26%[====> ] 1.05M 1006KB/s
kselftest_armhf.tar 56%[==========> ] 2.20M 1.59MB/s
kselftest_armhf.tar 88%[================> ] 3.47M 2.19MB/s
kselftest_armhf.tar 100%[===================>] 3.91M 2.33MB/s in 1.7s
1056 14:59:48.371855
1057 14:59:49.055132 2024-11-07 14:59:48 (2.33 MB/s) - 'kselftest_armhf.tar.gz' saved [4098284/4098284]
1058 14:59:49.055759
1059 15:00:03.668060 skiplist:
1060 15:00:03.668687 ========================================
1061 15:00:03.673700 ========================================
1062 15:00:03.775810 dt:test_unprobed_devices.sh
1063 15:00:03.809774 ============== Tests to run ===============
1064 15:00:03.817898 dt:test_unprobed_devices.sh
1065 15:00:03.821781 ===========End Tests to run ===============
1066 15:00:03.831011 shardfile-dt pass
1067 15:00:04.061457 <12>[ 72.687685] kselftest: Running tests in dt
1068 15:00:04.094784 TAP version 13
1069 15:00:04.118341 1..1
1070 15:00:04.171258 # timeout set to 45
1071 15:00:04.171897 # selftests: dt: test_unprobed_devices.sh
1072 15:00:04.979096 # TAP version 13
1073 15:00:29.663868 # 1..257
1074 15:00:29.835432 # ok 1 / # SKIP
1075 15:00:29.862118 # ok 2 /clk_mcasp0
1076 15:00:29.926916 # ok 3 /clk_mcasp0_fixed # SKIP
1077 15:00:30.001594 # ok 4 /cpus/cpu@0 # SKIP
1078 15:00:30.083998 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1079 15:00:30.103146 # ok 6 /fixedregulator0
1080 15:00:30.120971 # ok 7 /leds
1081 15:00:30.142198 # ok 8 /ocp
1082 15:00:30.170267 # ok 9 /ocp/interconnect@44c00000
1083 15:00:30.194271 # ok 10 /ocp/interconnect@44c00000/segment@0
1084 15:00:30.215134 # ok 11 /ocp/interconnect@44c00000/segment@100000
1085 15:00:30.237407 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1086 15:00:30.317369 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1087 15:00:30.344507 # ok 14 /ocp/interconnect@44c00000/segment@200000
1088 15:00:30.365734 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1089 15:00:30.472174 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1090 15:00:30.548641 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1091 15:00:30.615852 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1092 15:00:30.686604 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1093 15:00:30.757804 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1094 15:00:30.831256 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1095 15:00:30.899047 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1096 15:00:30.975557 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1097 15:00:31.047261 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1098 15:00:31.118158 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1099 15:00:31.188754 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1100 15:00:31.256421 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1101 15:00:31.326927 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1102 15:00:31.397347 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1103 15:00:31.467697 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1104 15:00:31.538252 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1105 15:00:31.608022 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1106 15:00:31.678642 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1107 15:00:31.748355 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1108 15:00:31.823572 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1109 15:00:31.888443 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1110 15:00:31.966341 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1111 15:00:32.038854 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1112 15:00:32.108086 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1113 15:00:32.179024 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1114 15:00:32.250123 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1115 15:00:32.317662 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1116 15:00:32.388906 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1117 15:00:32.458858 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1118 15:00:32.529312 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1119 15:00:32.599752 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1120 15:00:32.669680 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1121 15:00:32.739830 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1122 15:00:32.811664 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1123 15:00:32.881697 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1124 15:00:32.953128 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1125 15:00:33.027742 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1126 15:00:33.100658 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1127 15:00:33.171191 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1128 15:00:33.239315 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1129 15:00:33.310979 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1130 15:00:33.380810 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1131 15:00:33.456663 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1132 15:00:33.527764 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1133 15:00:33.598750 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1134 15:00:33.670109 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1135 15:00:33.740140 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1136 15:00:33.807668 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1137 15:00:33.879066 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1138 15:00:33.952226 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1139 15:00:34.021131 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1140 15:00:34.093512 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1141 15:00:34.170075 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1142 15:00:34.238976 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1143 15:00:34.315759 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1144 15:00:34.382567 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1145 15:00:34.454099 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1146 15:00:34.526179 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1147 15:00:34.597589 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1148 15:00:34.673739 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1149 15:00:34.741662 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1150 15:00:34.818030 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1151 15:00:34.890078 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1152 15:00:34.956478 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1153 15:00:35.028801 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1154 15:00:35.118754 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1155 15:00:35.196264 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1156 15:00:35.268630 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1157 15:00:35.341680 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1158 15:00:35.413739 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1159 15:00:35.495679 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1160 15:00:35.566751 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1161 15:00:35.644522 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1162 15:00:35.722908 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1163 15:00:35.795853 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1164 15:00:35.862349 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1165 15:00:35.935483 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1166 15:00:36.006861 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1167 15:00:36.083485 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1168 15:00:36.103557 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1169 15:00:36.126821 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1170 15:00:36.150537 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1171 15:00:36.173595 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1172 15:00:36.197407 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1173 15:00:36.221229 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1174 15:00:36.244650 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1175 15:00:36.271184 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1176 15:00:36.378342 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1177 15:00:36.408501 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1178 15:00:36.430486 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1179 15:00:36.458371 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1180 15:00:36.574952 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1181 15:00:36.650720 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1182 15:00:36.720899 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1183 15:00:36.798628 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1184 15:00:36.866086 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1185 15:00:36.938703 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1186 15:00:37.023875 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1187 15:00:37.104552 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1188 15:00:37.176955 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1189 15:00:37.255865 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1190 15:00:37.331715 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1191 15:00:37.403306 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1192 15:00:37.474089 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1193 15:00:37.558703 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1194 15:00:37.641318 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1195 15:00:37.706596 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1196 15:00:37.727292 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1197 15:00:37.798555 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1198 15:00:37.873196 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1199 15:00:37.944454 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1200 15:00:37.966257 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1201 15:00:38.037983 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1202 15:00:38.056198 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1203 15:00:38.133880 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1204 15:00:38.156612 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1205 15:00:38.177622 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1206 15:00:38.203243 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1207 15:00:38.227273 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1208 15:00:38.246801 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1209 15:00:38.273555 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1210 15:00:38.294792 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1211 15:00:38.370821 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1212 15:00:38.391496 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1213 15:00:38.415614 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1214 15:00:38.488474 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1215 15:00:38.559506 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1216 15:00:38.584035 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1217 15:00:38.682600 # not ok 144 /ocp/interconnect@47c00000
1218 15:00:38.754981 # not ok 145 /ocp/interconnect@47c00000/segment@0
1219 15:00:38.772782 # ok 146 /ocp/interconnect@48000000
1220 15:00:38.795671 # ok 147 /ocp/interconnect@48000000/segment@0
1221 15:00:38.824790 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1222 15:00:38.846580 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1223 15:00:38.871317 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1224 15:00:38.893948 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1225 15:00:38.916818 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1226 15:00:38.938323 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1227 15:00:38.958641 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1228 15:00:39.031170 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1229 15:00:39.102908 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1230 15:00:39.124971 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1231 15:00:39.149359 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1232 15:00:39.171394 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1233 15:00:39.195117 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1234 15:00:39.222321 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1235 15:00:39.246622 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1236 15:00:39.264574 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1237 15:00:39.293107 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1238 15:00:39.315789 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1239 15:00:39.337156 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1240 15:00:39.362265 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1241 15:00:39.386289 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1242 15:00:39.406836 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1243 15:00:39.432839 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1244 15:00:39.455149 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1245 15:00:39.477365 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1246 15:00:39.502091 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1247 15:00:39.527173 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1248 15:00:39.545147 # ok 175 /ocp/interconnect@48000000/segment@100000
1249 15:00:39.572696 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1250 15:00:39.597129 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1251 15:00:39.665111 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1252 15:00:39.740518 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1253 15:00:39.805734 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1254 15:00:39.877860 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1255 15:00:39.947353 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1256 15:00:40.020401 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1257 15:00:40.088786 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1258 15:00:40.161701 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1259 15:00:40.181116 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1260 15:00:40.206800 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1261 15:00:40.227574 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1262 15:00:40.250854 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1263 15:00:40.276681 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1264 15:00:40.302469 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1265 15:00:40.321095 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1266 15:00:40.347502 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1267 15:00:40.372324 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1268 15:00:40.396289 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1269 15:00:40.416807 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1270 15:00:40.443402 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1271 15:00:40.464382 # ok 198 /ocp/interconnect@48000000/segment@200000
1272 15:00:40.486484 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1273 15:00:40.556103 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1274 15:00:40.580899 # ok 201 /ocp/interconnect@48000000/segment@300000
1275 15:00:40.605379 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1276 15:00:40.626824 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1277 15:00:40.653211 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1278 15:00:40.675457 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1279 15:00:40.696688 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1280 15:00:40.722101 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1281 15:00:40.794040 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1282 15:00:40.812262 # ok 209 /ocp/interconnect@4a000000
1283 15:00:40.830110 # ok 210 /ocp/interconnect@4a000000/segment@0
1284 15:00:40.855794 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1285 15:00:40.884350 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1286 15:00:40.907995 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1287 15:00:40.933885 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1288 15:00:41.002552 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1289 15:00:41.102900 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1290 15:00:41.174022 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1291 15:00:41.275363 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1292 15:00:41.344068 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1293 15:00:41.413632 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1294 15:00:41.514605 # not ok 221 /ocp/interconnect@4b140000
1295 15:00:41.582217 # not ok 222 /ocp/interconnect@4b140000/segment@0
1296 15:00:41.652130 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1297 15:00:41.673077 # ok 224 /ocp/target-module@40300000
1298 15:00:41.696302 # ok 225 /ocp/target-module@40300000/sram@0
1299 15:00:41.767956 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1300 15:00:41.842442 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1301 15:00:41.861795 # ok 228 /ocp/target-module@47400000
1302 15:00:41.882261 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1303 15:00:41.905164 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1304 15:00:41.926769 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1305 15:00:41.952345 # ok 232 /ocp/target-module@47400000/usb@1400
1306 15:00:41.974639 # ok 233 /ocp/target-module@47400000/usb@1800
1307 15:00:41.991221 # ok 234 /ocp/target-module@47810000
1308 15:00:42.013797 # ok 235 /ocp/target-module@49000000
1309 15:00:42.040359 # ok 236 /ocp/target-module@49000000/dma@0
1310 15:00:42.061874 # ok 237 /ocp/target-module@49800000
1311 15:00:42.080189 # ok 238 /ocp/target-module@49800000/dma@0
1312 15:00:42.104051 # ok 239 /ocp/target-module@49900000
1313 15:00:42.129784 # ok 240 /ocp/target-module@49900000/dma@0
1314 15:00:42.151696 # ok 241 /ocp/target-module@49a00000
1315 15:00:42.170050 # ok 242 /ocp/target-module@49a00000/dma@0
1316 15:00:42.193955 # ok 243 /ocp/target-module@4c000000
1317 15:00:42.262933 # not ok 244 /ocp/target-module@4c000000/emif@0
1318 15:00:42.284072 # ok 245 /ocp/target-module@50000000
1319 15:00:42.304882 # ok 246 /ocp/target-module@53100000
1320 15:00:42.380534 # not ok 247 /ocp/target-module@53100000/sham@0
1321 15:00:42.401159 # ok 248 /ocp/target-module@53500000
1322 15:00:42.467539 # not ok 249 /ocp/target-module@53500000/aes@0
1323 15:00:42.492247 # ok 250 /ocp/target-module@56000000
1324 15:00:42.594799 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1325 15:00:42.658346 # ok 252 /opp-table # SKIP
1326 15:00:42.730906 # ok 253 /soc # SKIP
1327 15:00:42.751830 # ok 254 /sound
1328 15:00:42.770041 # ok 255 /target-module@4b000000
1329 15:00:42.799183 # ok 256 /target-module@4b000000/target-module@140000
1330 15:00:42.816165 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1331 15:00:42.824651 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1332 15:00:42.831601 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1333 15:00:44.906139 dt_test_unprobed_devices_sh_ skip
1334 15:00:44.911663 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1335 15:00:44.917363 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1336 15:00:44.917648 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1337 15:00:44.922842 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1338 15:00:44.928438 dt_test_unprobed_devices_sh_fixedregulator0 pass
1339 15:00:44.934226 dt_test_unprobed_devices_sh_leds pass
1340 15:00:44.934520 dt_test_unprobed_devices_sh_ocp pass
1341 15:00:44.939664 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1342 15:00:44.945271 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1343 15:00:44.951076 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1344 15:00:44.962091 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1345 15:00:44.967691 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1346 15:00:44.973351 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1347 15:00:44.984494 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1348 15:00:44.990104 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1349 15:00:45.001422 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1350 15:00:45.012650 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1351 15:00:45.023907 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1352 15:00:45.029547 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1353 15:00:45.040729 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1354 15:00:45.051944 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1355 15:00:45.063166 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1356 15:00:45.074375 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1357 15:00:45.079927 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1358 15:00:45.091183 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1359 15:00:45.102318 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1360 15:00:45.113528 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1361 15:00:45.124728 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1362 15:00:45.130322 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1363 15:00:45.141488 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1364 15:00:45.152667 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1365 15:00:45.163877 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1366 15:00:45.169474 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1367 15:00:45.180680 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1368 15:00:45.191943 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1369 15:00:45.203021 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1370 15:00:45.214172 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1371 15:00:45.219790 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1372 15:00:45.230964 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1373 15:00:45.242167 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1374 15:00:45.253372 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1375 15:00:45.264545 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1376 15:00:45.275771 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1377 15:00:45.286969 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1378 15:00:45.298137 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1379 15:00:45.309312 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1380 15:00:45.320534 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1381 15:00:45.331678 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1382 15:00:45.342893 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1383 15:00:45.354163 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1384 15:00:45.365280 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1385 15:00:45.376477 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1386 15:00:45.387697 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1387 15:00:45.398893 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1388 15:00:45.410067 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1389 15:00:45.421258 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1390 15:00:45.432468 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1391 15:00:45.443668 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1392 15:00:45.454812 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1393 15:00:45.466015 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1394 15:00:45.477234 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1395 15:00:45.488521 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1396 15:00:45.499593 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1397 15:00:45.505228 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1398 15:00:45.516402 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1399 15:00:45.527585 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1400 15:00:45.538761 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1401 15:00:45.549965 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1402 15:00:45.561152 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1403 15:00:45.572340 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1404 15:00:45.583508 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1405 15:00:45.594742 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1406 15:00:45.605917 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1407 15:00:45.617208 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1408 15:00:45.629184 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1409 15:00:45.639480 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1410 15:00:45.650696 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1411 15:00:45.661874 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1412 15:00:45.673085 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1413 15:00:45.684264 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1414 15:00:45.695443 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1415 15:00:45.701010 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1416 15:00:45.712249 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1417 15:00:45.723660 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1418 15:00:45.734602 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1419 15:00:45.745793 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1420 15:00:45.751378 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1421 15:00:45.768205 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1422 15:00:45.779353 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1423 15:00:45.784916 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1424 15:00:45.801749 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1425 15:00:45.813028 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1426 15:00:45.824208 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1427 15:00:45.829824 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1428 15:00:45.840999 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1429 15:00:45.852175 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1430 15:00:45.857769 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1431 15:00:45.868961 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1432 15:00:45.880133 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1433 15:00:45.885735 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1434 15:00:45.896937 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1435 15:00:45.902559 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1436 15:00:45.913732 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1437 15:00:45.924932 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1438 15:00:45.936147 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1439 15:00:45.947279 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1440 15:00:45.958505 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1441 15:00:45.969838 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1442 15:00:45.980863 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1443 15:00:45.992041 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1444 15:00:46.003342 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1445 15:00:46.014456 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1446 15:00:46.025651 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1447 15:00:46.036913 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1448 15:00:46.053611 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1449 15:00:46.064844 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1450 15:00:46.075983 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1451 15:00:46.087208 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1452 15:00:46.098345 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1453 15:00:46.115202 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1454 15:00:46.126337 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1455 15:00:46.137548 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1456 15:00:46.148714 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1457 15:00:46.154288 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1458 15:00:46.165487 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1459 15:00:46.176681 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1460 15:00:46.182334 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1461 15:00:46.193499 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1462 15:00:46.199111 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1463 15:00:46.210301 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1464 15:00:46.215906 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1465 15:00:46.227076 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1466 15:00:46.232718 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1467 15:00:46.243862 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1468 15:00:46.249504 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1469 15:00:46.260642 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1470 15:00:46.271864 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1471 15:00:46.283064 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1472 15:00:46.294222 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1473 15:00:46.305427 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1474 15:00:46.311041 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1475 15:00:46.322231 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1476 15:00:46.327781 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1477 15:00:46.333407 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1478 15:00:46.339023 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1479 15:00:46.344639 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1480 15:00:46.350219 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1481 15:00:46.361400 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1482 15:00:46.367011 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1483 15:00:46.372608 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1484 15:00:46.383790 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1485 15:00:46.389421 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1486 15:00:46.400560 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1487 15:00:46.406169 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1488 15:00:46.417337 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1489 15:00:46.422968 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1490 15:00:46.434155 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1491 15:00:46.439752 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1492 15:00:46.451118 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1493 15:00:46.456555 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1494 15:00:46.467777 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1495 15:00:46.473432 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1496 15:00:46.484570 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1497 15:00:46.490196 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1498 15:00:46.495745 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1499 15:00:46.506950 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1500 15:00:46.512587 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1501 15:00:46.523712 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1502 15:00:46.529322 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1503 15:00:46.540572 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1504 15:00:46.546117 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1505 15:00:46.557297 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1506 15:00:46.562939 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1507 15:00:46.568490 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1508 15:00:46.579612 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1509 15:00:46.585229 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1510 15:00:46.596384 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1511 15:00:46.607576 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1512 15:00:46.618692 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1513 15:00:46.630019 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1514 15:00:46.641234 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1515 15:00:46.652404 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1516 15:00:46.663599 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1517 15:00:46.674787 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1518 15:00:46.680361 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1519 15:00:46.691577 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1520 15:00:46.697183 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1521 15:00:46.708440 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1522 15:00:46.714003 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1523 15:00:46.725162 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1524 15:00:46.730725 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1525 15:00:46.742010 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1526 15:00:46.747722 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1527 15:00:46.758818 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1528 15:00:46.764562 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1529 15:00:46.775612 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1530 15:00:46.781392 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1531 15:00:46.794671 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1532 15:00:46.798307 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1533 15:00:46.803646 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1534 15:00:46.814844 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1535 15:00:46.820331 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1536 15:00:46.831656 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1537 15:00:46.837269 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1538 15:00:46.848709 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1539 15:00:46.854005 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1540 15:00:46.865170 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1541 15:00:46.870691 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1542 15:00:46.876485 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1543 15:00:46.882071 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1544 15:00:46.893025 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1545 15:00:46.904146 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1546 15:00:46.909832 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1547 15:00:46.915459 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1548 15:00:46.926667 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1549 15:00:46.937932 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1550 15:00:46.949110 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1551 15:00:46.960362 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1552 15:00:46.965983 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1553 15:00:46.971618 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1554 15:00:46.977211 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1555 15:00:46.982804 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1556 15:00:46.988469 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1557 15:00:46.994012 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1558 15:00:47.005120 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1559 15:00:47.010839 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1560 15:00:47.016428 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1561 15:00:47.022164 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1562 15:00:47.027768 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1563 15:00:47.038816 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1564 15:00:47.044441 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1565 15:00:47.050306 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1566 15:00:47.055664 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1567 15:00:47.061185 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1568 15:00:47.066720 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1569 15:00:47.072353 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1570 15:00:47.078211 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1571 15:00:47.083732 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1572 15:00:47.089238 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1573 15:00:47.094799 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1574 15:00:47.100423 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1575 15:00:47.106074 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1576 15:00:47.111658 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1577 15:00:47.117234 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1578 15:00:47.122830 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1579 15:00:47.128563 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1580 15:00:47.134033 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1581 15:00:47.139685 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1582 15:00:47.145276 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1583 15:00:47.150856 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1584 15:00:47.151371 dt_test_unprobed_devices_sh_opp-table skip
1585 15:00:47.156511 dt_test_unprobed_devices_sh_soc skip
1586 15:00:47.162155 dt_test_unprobed_devices_sh_sound pass
1587 15:00:47.167734 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1588 15:00:47.173312 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1589 15:00:47.178971 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1590 15:00:47.184566 dt_test_unprobed_devices_sh fail
1591 15:00:47.185138 + ../../utils/send-to-lava.sh ./output/result.txt
1592 15:00:47.190072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1593 15:00:47.190770 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1595 15:00:47.199471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1596 15:00:47.200162 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1598 15:00:47.296141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1599 15:00:47.296847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1601 15:00:47.387910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1602 15:00:47.388559 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1604 15:00:47.477648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1605 15:00:47.478319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1607 15:00:47.568921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1608 15:00:47.569564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1610 15:00:47.658737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1611 15:00:47.659383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1613 15:00:47.747103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1614 15:00:47.747835 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1616 15:00:47.839840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1617 15:00:47.840605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1619 15:00:47.940789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1620 15:00:47.941646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1622 15:00:48.034740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1623 15:00:48.035770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1625 15:00:48.126462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1626 15:00:48.127344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1628 15:00:48.218631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1629 15:00:48.219505 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1631 15:00:48.313106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1632 15:00:48.314198 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1634 15:00:48.404447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1635 15:00:48.405148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1637 15:00:48.497902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1638 15:00:48.498578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1640 15:00:48.591565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1641 15:00:48.592245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1643 15:00:48.681402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1644 15:00:48.682088 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1646 15:00:48.772328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1647 15:00:48.772981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1649 15:00:48.865630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1650 15:00:48.866323 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1652 15:00:48.957202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1653 15:00:48.957879 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1655 15:00:49.050551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1656 15:00:49.051225 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1658 15:00:49.143522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1659 15:00:49.144690 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1661 15:00:49.235036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1662 15:00:49.236102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1664 15:00:49.328346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1665 15:00:49.329031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1667 15:00:49.419505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1668 15:00:49.420168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1670 15:00:49.510101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1671 15:00:49.511045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1673 15:00:49.600357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1674 15:00:49.601267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1676 15:00:49.690737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1677 15:00:49.691645 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1679 15:00:49.780502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1680 15:00:49.781409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1682 15:00:49.871956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1683 15:00:49.872639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1685 15:00:49.965917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1686 15:00:49.966576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1688 15:00:50.056858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1689 15:00:50.057489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1691 15:00:50.144642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1692 15:00:50.145261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1694 15:00:50.231799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1695 15:00:50.232433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1697 15:00:50.320622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1698 15:00:50.321259 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1700 15:00:50.412374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1701 15:00:50.412998 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1703 15:00:50.502365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1704 15:00:50.503006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1706 15:00:50.591765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1707 15:00:50.592382 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1709 15:00:50.681106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1710 15:00:50.681732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1712 15:00:50.771199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1713 15:00:50.771816 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1715 15:00:50.863355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1716 15:00:50.864152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1718 15:00:50.953424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1719 15:00:50.954137 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1721 15:00:51.044623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1722 15:00:51.045261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1724 15:00:51.134573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1725 15:00:51.135264 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1727 15:00:51.226368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1728 15:00:51.227001 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1730 15:00:51.316449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1731 15:00:51.317089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1733 15:00:51.406639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1734 15:00:51.407268 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1736 15:00:51.497778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1737 15:00:51.498525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1739 15:00:51.586881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1740 15:00:51.587504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1742 15:00:51.676250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1743 15:00:51.676963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1745 15:00:51.769604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1746 15:00:51.770379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1748 15:00:51.868286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1749 15:00:51.869265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1751 15:00:51.980424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1752 15:00:51.981264 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1754 15:00:52.076910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1755 15:00:52.079255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1757 15:00:52.167160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1758 15:00:52.168061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1760 15:00:52.258363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1761 15:00:52.259236 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1763 15:00:52.342488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1764 15:00:52.343331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1766 15:00:52.440398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1767 15:00:52.441279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1769 15:00:52.529390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1770 15:00:52.530263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1772 15:00:52.621924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1773 15:00:52.622766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1775 15:00:52.715409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1776 15:00:52.716280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1778 15:00:52.804529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1779 15:00:52.805170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1781 15:00:52.895638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1782 15:00:52.896254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1784 15:00:52.986617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1785 15:00:52.987245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1787 15:00:53.076429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1788 15:00:53.077049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1790 15:00:53.167431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1791 15:00:53.168081 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1793 15:00:53.257943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1794 15:00:53.258581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1796 15:00:53.347886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1797 15:00:53.348505 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1799 15:00:53.437586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1800 15:00:53.438241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1802 15:00:53.524191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1803 15:00:53.524825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1805 15:00:53.614965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1806 15:00:53.615552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1808 15:00:53.706287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1809 15:00:53.706917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1811 15:00:53.796531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1812 15:00:53.797139 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1814 15:00:53.886301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1815 15:00:53.886884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1817 15:00:53.977352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1818 15:00:53.977939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1820 15:00:54.067767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1821 15:00:54.068385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1823 15:00:54.156655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1824 15:00:54.157269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1826 15:00:54.247175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1827 15:00:54.247829 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1829 15:00:54.338078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1830 15:00:54.338715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1832 15:00:54.430438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1833 15:00:54.431082 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1835 15:00:54.522709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1836 15:00:54.523340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1838 15:00:54.616073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1839 15:00:54.616688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1841 15:00:54.708884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1842 15:00:54.709528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1844 15:00:54.802577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1845 15:00:54.803621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1847 15:00:54.895818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1848 15:00:54.896786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1850 15:00:54.986780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1851 15:00:54.987736 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1853 15:00:55.078158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1854 15:00:55.079153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1856 15:00:55.168013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1857 15:00:55.168920 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1859 15:00:55.254009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1860 15:00:55.255303 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1862 15:00:55.348360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1863 15:00:55.349147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1865 15:00:55.437707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1866 15:00:55.438356 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1868 15:00:55.531995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1869 15:00:55.532651 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1871 15:00:55.631613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1872 15:00:55.632279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1874 15:00:55.732829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1875 15:00:55.733494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1877 15:00:55.822004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1878 15:00:55.822648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1880 15:00:55.916313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1881 15:00:55.916965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1883 15:00:56.005491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1884 15:00:56.007054 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1886 15:00:56.097090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1887 15:00:56.097742 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1889 15:00:56.186964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1890 15:00:56.187629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1892 15:00:56.280433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1893 15:00:56.281093 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1895 15:00:56.375638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1896 15:00:56.376577 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1898 15:00:56.463571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1899 15:00:56.464482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1901 15:00:56.556296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1902 15:00:56.557401 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1904 15:00:56.645229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1905 15:00:56.646284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1907 15:00:56.738451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1908 15:00:56.740289 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1910 15:00:56.834191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1911 15:00:56.834846 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1913 15:00:56.924909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1914 15:00:56.925640 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1916 15:00:57.017641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1917 15:00:57.018628 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1919 15:00:57.113481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1920 15:00:57.114159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1922 15:00:57.206458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1923 15:00:57.207111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1925 15:00:57.295499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1926 15:00:57.296167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1928 15:00:57.387088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1929 15:00:57.387696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1931 15:00:57.477323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1932 15:00:57.478289 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1934 15:00:57.568049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1935 15:00:57.568981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1937 15:00:57.658881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1938 15:00:57.659836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1940 15:00:57.750619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1941 15:00:57.751522 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1943 15:00:57.843534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1944 15:00:57.844449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1946 15:00:57.934799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1947 15:00:57.935489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1949 15:00:58.025451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1950 15:00:58.026207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1952 15:00:58.116688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1954 15:00:58.119868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1955 15:00:58.206417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1957 15:00:58.209422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1958 15:00:58.299159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1960 15:00:58.302193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1961 15:00:58.387678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1962 15:00:58.388473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1964 15:00:58.476233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1965 15:00:58.477171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1967 15:00:58.564246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1968 15:00:58.564968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1970 15:00:58.655695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1971 15:00:58.656414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1973 15:00:58.740168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1974 15:00:58.740903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1976 15:00:58.831286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1977 15:00:58.832057 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1979 15:00:58.923798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1980 15:00:58.924763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1982 15:00:59.014032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1983 15:00:59.015030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1985 15:00:59.105709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1986 15:00:59.106633 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1988 15:00:59.198194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1989 15:00:59.199094 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1991 15:00:59.289746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1992 15:00:59.290700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1994 15:00:59.384886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1995 15:00:59.385857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1997 15:00:59.475731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1998 15:00:59.476673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2000 15:00:59.567296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2001 15:00:59.568237 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2003 15:00:59.660725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2004 15:00:59.661652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2006 15:00:59.753573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2007 15:00:59.754668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2009 15:00:59.844355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2010 15:00:59.845284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2012 15:00:59.935750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2013 15:00:59.936680 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2015 15:01:00.030221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2016 15:01:00.031797 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2018 15:01:00.134611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2019 15:01:00.135474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2021 15:01:00.225875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2022 15:01:00.226799 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2024 15:01:00.316434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2025 15:01:00.317364 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2027 15:01:00.412299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2028 15:01:00.413217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2030 15:01:00.508178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2031 15:01:00.508970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2033 15:01:00.611558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2034 15:01:00.612531 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2036 15:01:00.706737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2037 15:01:00.707685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2039 15:01:00.799024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2040 15:01:00.799749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2042 15:01:00.893151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2043 15:01:00.894233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2045 15:01:01.012709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2046 15:01:01.013614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2048 15:01:01.117395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2049 15:01:01.118433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2051 15:01:01.234203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2052 15:01:01.235180 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2054 15:01:01.325000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2055 15:01:01.325925 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2057 15:01:01.414783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2058 15:01:01.415716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2060 15:01:01.516486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2061 15:01:01.517146 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2063 15:01:01.604816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2064 15:01:01.605723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2066 15:01:01.696561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2067 15:01:01.697134 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2069 15:01:01.787157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2070 15:01:01.788041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2072 15:01:01.879105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2073 15:01:01.879841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2075 15:01:01.970753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2076 15:01:01.971825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2078 15:01:02.064141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2079 15:01:02.065092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2081 15:01:02.154785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2082 15:01:02.155647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2084 15:01:02.244433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2085 15:01:02.245287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2087 15:01:02.332950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2088 15:01:02.333975 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2090 15:01:02.425027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2091 15:01:02.425946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2093 15:01:02.515552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2094 15:01:02.516372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2096 15:01:02.599611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2097 15:01:02.600233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2099 15:01:02.689901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2100 15:01:02.690494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2102 15:01:02.780191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2103 15:01:02.780947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2105 15:01:02.868993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2106 15:01:02.869841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2108 15:01:02.963069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2109 15:01:02.963836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2111 15:01:03.056570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2112 15:01:03.057438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2114 15:01:03.147661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2115 15:01:03.148350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2117 15:01:03.236443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2118 15:01:03.237210 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2120 15:01:03.327603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2121 15:01:03.328455 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2123 15:01:03.418239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2124 15:01:03.419075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2126 15:01:03.511475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2127 15:01:03.512129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2129 15:01:03.603896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2130 15:01:03.604512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2132 15:01:03.692818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2133 15:01:03.693424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2135 15:01:03.784536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2136 15:01:03.785164 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2138 15:01:03.875119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2139 15:01:03.875744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2141 15:01:03.979410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2142 15:01:03.980028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2144 15:01:04.067517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2145 15:01:04.068102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2147 15:01:04.159022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2148 15:01:04.159621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2150 15:01:04.243985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2151 15:01:04.244551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2153 15:01:04.334856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2154 15:01:04.335426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2156 15:01:04.425523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2157 15:01:04.426132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2159 15:01:04.514403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2160 15:01:04.515043 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2162 15:01:04.604971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2163 15:01:04.605579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2165 15:01:04.695610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2166 15:01:04.696238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2168 15:01:04.779522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2169 15:01:04.780177 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2171 15:01:04.870582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2172 15:01:04.871456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2174 15:01:04.961375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2175 15:01:04.962289 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2177 15:01:05.052365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2178 15:01:05.053600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2180 15:01:05.141251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2181 15:01:05.142117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2183 15:01:05.231317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2184 15:01:05.232107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2186 15:01:05.318495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2187 15:01:05.319360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2189 15:01:05.409402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2190 15:01:05.410223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2192 15:01:05.500502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2193 15:01:05.501773 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2195 15:01:05.590708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2196 15:01:05.591575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2198 15:01:05.680618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2199 15:01:05.681513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2201 15:01:05.770533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2202 15:01:05.771410 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2204 15:01:05.861338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2205 15:01:05.862234 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2207 15:01:05.951700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2208 15:01:05.952581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2210 15:01:06.043494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2211 15:01:06.044392 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2213 15:01:06.135805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2214 15:01:06.136648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2216 15:01:06.226014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2217 15:01:06.226891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2219 15:01:06.306097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2220 15:01:06.306953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2222 15:01:06.398935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2223 15:01:06.399806 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2225 15:01:06.490553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2226 15:01:06.491446 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2228 15:01:06.583594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2229 15:01:06.584456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2231 15:01:06.674397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2232 15:01:06.675283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2234 15:01:06.764245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2235 15:01:06.765101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2237 15:01:06.855901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2238 15:01:06.856753 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2240 15:01:06.941964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2241 15:01:06.942771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2243 15:01:07.035647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2244 15:01:07.036527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2246 15:01:07.127356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2247 15:01:07.128210 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2249 15:01:07.220396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2250 15:01:07.221227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2252 15:01:07.311127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2253 15:01:07.311936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2255 15:01:07.397597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2256 15:01:07.398437 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2258 15:01:07.490850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2259 15:01:07.491704 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2261 15:01:07.582846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2262 15:01:07.583702 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2264 15:01:07.674817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2265 15:01:07.675682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2267 15:01:07.767373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2268 15:01:07.768219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2270 15:01:07.861462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2271 15:01:07.862368 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2273 15:01:07.950506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2275 15:01:07.953273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2276 15:01:08.040008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2277 15:01:08.040899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2279 15:01:08.261253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2280 15:01:08.262518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2282 15:01:08.368975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2283 15:01:08.370494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2285 15:01:08.464394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2286 15:01:08.465630 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2288 15:01:08.554283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2289 15:01:08.555443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2291 15:01:08.646691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2292 15:01:08.647844 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2294 15:01:08.737179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2295 15:01:08.738393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2297 15:01:08.829888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2298 15:01:08.830938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2300 15:01:08.922185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2301 15:01:08.923312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2303 15:01:09.012943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2304 15:01:09.013975 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2306 15:01:09.105180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2307 15:01:09.106325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2309 15:01:09.196729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2310 15:01:09.197660 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2312 15:01:09.290163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2313 15:01:09.291100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2315 15:01:09.380803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2316 15:01:09.381540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2318 15:01:09.470687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2319 15:01:09.471463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2321 15:01:09.560512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2322 15:01:09.561267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2324 15:01:09.651556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2325 15:01:09.652304 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2327 15:01:09.741086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2328 15:01:09.741804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2330 15:01:09.826922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2331 15:01:09.827658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2333 15:01:09.918772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2334 15:01:09.919524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2336 15:01:10.009038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2337 15:01:10.009762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2339 15:01:10.100828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2340 15:01:10.101523 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2342 15:01:10.190953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2343 15:01:10.191746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2345 15:01:10.279868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2346 15:01:10.280497 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2348 15:01:10.361160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2349 15:01:10.361970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2351 15:01:10.451089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2352 15:01:10.451940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2354 15:01:10.539794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2355 15:01:10.540756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2357 15:01:10.625857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2358 15:01:10.626664 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2360 15:01:10.717365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2361 15:01:10.718186 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2363 15:01:10.809727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2364 15:01:10.810665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2366 15:01:10.898142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2367 15:01:10.898794 + set +x
2368 15:01:10.899516 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2370 15:01:10.902253 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 953176_1.6.2.4.5>
2371 15:01:10.903046 Received signal: <ENDRUN> 1_kselftest-dt 953176_1.6.2.4.5
2372 15:01:10.903553 Ending use of test pattern.
2373 15:01:10.903998 Ending test lava.1_kselftest-dt (953176_1.6.2.4.5), duration 85.22
2375 15:01:10.908577 <LAVA_TEST_RUNNER EXIT>
2376 15:01:10.909362 ok: lava_test_shell seems to have completed
2377 15:01:10.923611 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2378 15:01:10.925879 end: 3.1 lava-test-shell (duration 00:01:27) [common]
2379 15:01:10.926551 end: 3 lava-test-retry (duration 00:01:27) [common]
2380 15:01:10.927194 start: 4 finalize (timeout 00:05:30) [common]
2381 15:01:10.927841 start: 4.1 power-off (timeout 00:00:30) [common]
2382 15:01:10.928973 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-03'
2383 15:01:10.963730 >> OK - accepted request
2384 15:01:10.965711 Returned 0 in 0 seconds
2385 15:01:11.067096 end: 4.1 power-off (duration 00:00:00) [common]
2387 15:01:11.068980 start: 4.2 read-feedback (timeout 00:05:29) [common]
2388 15:01:11.070240 Listened to connection for namespace 'common' for up to 1s
2389 15:01:11.071163 Listened to connection for namespace 'common' for up to 1s
2390 15:01:12.070703 Finalising connection for namespace 'common'
2391 15:01:12.071802 Disconnecting from shell: Finalise
2392 15:01:12.072077 / #
2393 15:01:12.172934 end: 4.2 read-feedback (duration 00:00:01) [common]
2394 15:01:12.173400 end: 4 finalize (duration 00:00:01) [common]
2395 15:01:12.173874 Cleaning after the job
2396 15:01:12.174230 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953176/tftp-deploy-iqhle6r4/ramdisk
2397 15:01:12.178830 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953176/tftp-deploy-iqhle6r4/kernel
2398 15:01:12.180490 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953176/tftp-deploy-iqhle6r4/dtb
2399 15:01:12.181236 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953176/tftp-deploy-iqhle6r4/nfsrootfs
2400 15:01:12.235861 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953176/tftp-deploy-iqhle6r4/modules
2401 15:01:12.245193 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/953176
2402 15:01:15.212263 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/953176
2403 15:01:15.212841 Job finished correctly