Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 14:46:14.627020 lava-dispatcher, installed at version: 2024.01
2 14:46:14.627810 start: 0 validate
3 14:46:14.628355 Start time: 2024-11-07 14:46:14.628325+00:00 (UTC)
4 14:46:14.628922 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 14:46:14.629464 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 14:46:14.674442 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 14:46:14.674988 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-5-g94debe5eaa0ad%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 14:46:14.707828 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 14:46:14.708509 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-5-g94debe5eaa0ad%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 14:46:16.767640 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 14:46:16.768355 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-5-g94debe5eaa0ad%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 14:46:16.813090 validate duration: 2.18
14 14:46:16.813915 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 14:46:16.814223 start: 1.1 download-retry (timeout 00:10:00) [common]
16 14:46:16.814509 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 14:46:16.815099 Not decompressing ramdisk as can be used compressed.
18 14:46:16.815461 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 14:46:16.815714 saving as /var/lib/lava/dispatcher/tmp/953341/tftp-deploy-7jhxdu8e/ramdisk/rootfs.cpio.gz
20 14:46:16.815970 total size: 8181887 (7 MB)
21 14:46:16.857273 progress 0 % (0 MB)
22 14:46:16.871132 progress 5 % (0 MB)
23 14:46:16.884031 progress 10 % (0 MB)
24 14:46:16.892870 progress 15 % (1 MB)
25 14:46:16.899086 progress 20 % (1 MB)
26 14:46:16.905879 progress 25 % (1 MB)
27 14:46:16.912152 progress 30 % (2 MB)
28 14:46:16.918845 progress 35 % (2 MB)
29 14:46:16.925094 progress 40 % (3 MB)
30 14:46:16.931683 progress 45 % (3 MB)
31 14:46:16.937897 progress 50 % (3 MB)
32 14:46:16.944640 progress 55 % (4 MB)
33 14:46:16.950815 progress 60 % (4 MB)
34 14:46:16.957473 progress 65 % (5 MB)
35 14:46:16.963518 progress 70 % (5 MB)
36 14:46:16.970182 progress 75 % (5 MB)
37 14:46:16.976396 progress 80 % (6 MB)
38 14:46:16.982841 progress 85 % (6 MB)
39 14:46:16.988583 progress 90 % (7 MB)
40 14:46:16.994597 progress 95 % (7 MB)
41 14:46:17.000460 progress 100 % (7 MB)
42 14:46:17.001262 7 MB downloaded in 0.19 s (42.12 MB/s)
43 14:46:17.001910 end: 1.1.1 http-download (duration 00:00:00) [common]
45 14:46:17.002980 end: 1.1 download-retry (duration 00:00:00) [common]
46 14:46:17.003332 start: 1.2 download-retry (timeout 00:10:00) [common]
47 14:46:17.003661 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 14:46:17.004280 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-5-g94debe5eaa0ad/arm64/defconfig/gcc-12/kernel/Image
49 14:46:17.004607 saving as /var/lib/lava/dispatcher/tmp/953341/tftp-deploy-7jhxdu8e/kernel/Image
50 14:46:17.004861 total size: 45713920 (43 MB)
51 14:46:17.005116 No compression specified
52 14:46:17.046597 progress 0 % (0 MB)
53 14:46:17.079779 progress 5 % (2 MB)
54 14:46:17.112942 progress 10 % (4 MB)
55 14:46:17.145848 progress 15 % (6 MB)
56 14:46:17.178846 progress 20 % (8 MB)
57 14:46:17.211889 progress 25 % (10 MB)
58 14:46:17.244719 progress 30 % (13 MB)
59 14:46:17.278532 progress 35 % (15 MB)
60 14:46:17.306918 progress 40 % (17 MB)
61 14:46:17.334797 progress 45 % (19 MB)
62 14:46:17.362731 progress 50 % (21 MB)
63 14:46:17.391555 progress 55 % (24 MB)
64 14:46:17.419494 progress 60 % (26 MB)
65 14:46:17.447238 progress 65 % (28 MB)
66 14:46:17.475108 progress 70 % (30 MB)
67 14:46:17.502815 progress 75 % (32 MB)
68 14:46:17.530439 progress 80 % (34 MB)
69 14:46:17.557925 progress 85 % (37 MB)
70 14:46:17.586028 progress 90 % (39 MB)
71 14:46:17.613468 progress 95 % (41 MB)
72 14:46:17.640000 progress 100 % (43 MB)
73 14:46:17.640517 43 MB downloaded in 0.64 s (68.59 MB/s)
74 14:46:17.641001 end: 1.2.1 http-download (duration 00:00:01) [common]
76 14:46:17.641841 end: 1.2 download-retry (duration 00:00:01) [common]
77 14:46:17.642167 start: 1.3 download-retry (timeout 00:09:59) [common]
78 14:46:17.642443 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 14:46:17.642934 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-5-g94debe5eaa0ad/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 14:46:17.643223 saving as /var/lib/lava/dispatcher/tmp/953341/tftp-deploy-7jhxdu8e/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 14:46:17.643437 total size: 53209 (0 MB)
82 14:46:17.643648 No compression specified
83 14:46:17.681792 progress 61 % (0 MB)
84 14:46:17.682636 progress 100 % (0 MB)
85 14:46:17.683163 0 MB downloaded in 0.04 s (1.28 MB/s)
86 14:46:17.683623 end: 1.3.1 http-download (duration 00:00:00) [common]
88 14:46:17.684479 end: 1.3 download-retry (duration 00:00:00) [common]
89 14:46:17.684741 start: 1.4 download-retry (timeout 00:09:59) [common]
90 14:46:17.685001 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 14:46:17.685468 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-5-g94debe5eaa0ad/arm64/defconfig/gcc-12/modules.tar.xz
92 14:46:17.685730 saving as /var/lib/lava/dispatcher/tmp/953341/tftp-deploy-7jhxdu8e/modules/modules.tar
93 14:46:17.685934 total size: 11609576 (11 MB)
94 14:46:17.686144 Using unxz to decompress xz
95 14:46:17.726576 progress 0 % (0 MB)
96 14:46:17.792518 progress 5 % (0 MB)
97 14:46:17.866727 progress 10 % (1 MB)
98 14:46:17.962510 progress 15 % (1 MB)
99 14:46:18.054877 progress 20 % (2 MB)
100 14:46:18.133681 progress 25 % (2 MB)
101 14:46:18.208925 progress 30 % (3 MB)
102 14:46:18.286733 progress 35 % (3 MB)
103 14:46:18.360546 progress 40 % (4 MB)
104 14:46:18.436865 progress 45 % (5 MB)
105 14:46:18.521340 progress 50 % (5 MB)
106 14:46:18.598843 progress 55 % (6 MB)
107 14:46:18.683879 progress 60 % (6 MB)
108 14:46:18.763741 progress 65 % (7 MB)
109 14:46:18.844511 progress 70 % (7 MB)
110 14:46:18.922835 progress 75 % (8 MB)
111 14:46:19.006102 progress 80 % (8 MB)
112 14:46:19.086078 progress 85 % (9 MB)
113 14:46:19.165575 progress 90 % (9 MB)
114 14:46:19.243019 progress 95 % (10 MB)
115 14:46:19.320593 progress 100 % (11 MB)
116 14:46:19.331974 11 MB downloaded in 1.65 s (6.73 MB/s)
117 14:46:19.333017 end: 1.4.1 http-download (duration 00:00:02) [common]
119 14:46:19.334625 end: 1.4 download-retry (duration 00:00:02) [common]
120 14:46:19.335146 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 14:46:19.335665 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 14:46:19.336197 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 14:46:19.336708 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 14:46:19.337719 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8
125 14:46:19.338595 makedir: /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin
126 14:46:19.339237 makedir: /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/tests
127 14:46:19.339848 makedir: /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/results
128 14:46:19.340519 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-add-keys
129 14:46:19.341492 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-add-sources
130 14:46:19.342444 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-background-process-start
131 14:46:19.343414 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-background-process-stop
132 14:46:19.344454 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-common-functions
133 14:46:19.345387 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-echo-ipv4
134 14:46:19.346292 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-install-packages
135 14:46:19.347178 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-installed-packages
136 14:46:19.348095 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-os-build
137 14:46:19.349007 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-probe-channel
138 14:46:19.349894 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-probe-ip
139 14:46:19.350802 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-target-ip
140 14:46:19.351710 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-target-mac
141 14:46:19.352670 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-target-storage
142 14:46:19.353595 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-test-case
143 14:46:19.354569 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-test-event
144 14:46:19.355481 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-test-feedback
145 14:46:19.356442 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-test-raise
146 14:46:19.357362 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-test-reference
147 14:46:19.358302 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-test-runner
148 14:46:19.359237 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-test-set
149 14:46:19.360251 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-test-shell
150 14:46:19.361239 Updating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-install-packages (oe)
151 14:46:19.362244 Updating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/bin/lava-installed-packages (oe)
152 14:46:19.363110 Creating /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/environment
153 14:46:19.363839 LAVA metadata
154 14:46:19.364391 - LAVA_JOB_ID=953341
155 14:46:19.364822 - LAVA_DISPATCHER_IP=192.168.6.2
156 14:46:19.365501 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 14:46:19.367305 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 14:46:19.367926 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 14:46:19.368377 skipped lava-vland-overlay
160 14:46:19.368862 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 14:46:19.369364 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 14:46:19.369785 skipped lava-multinode-overlay
163 14:46:19.370258 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 14:46:19.370753 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 14:46:19.371225 Loading test definitions
166 14:46:19.371769 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 14:46:19.372176 Using /lava-953341 at stage 0
168 14:46:19.373509 uuid=953341_1.5.2.4.1 testdef=None
169 14:46:19.373864 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 14:46:19.374138 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 14:46:19.375971 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 14:46:19.376844 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 14:46:19.379126 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 14:46:19.380005 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 14:46:19.382207 runner path: /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/0/tests/0_dmesg test_uuid 953341_1.5.2.4.1
178 14:46:19.382799 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 14:46:19.383595 Creating lava-test-runner.conf files
181 14:46:19.383799 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/953341/lava-overlay-1ou7d1_8/lava-953341/0 for stage 0
182 14:46:19.384161 - 0_dmesg
183 14:46:19.384530 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 14:46:19.384818 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 14:46:19.408432 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 14:46:19.408878 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 14:46:19.409189 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 14:46:19.409508 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 14:46:19.409808 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 14:46:20.355375 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 14:46:20.356138 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 14:46:20.356645 extracting modules file /var/lib/lava/dispatcher/tmp/953341/tftp-deploy-7jhxdu8e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/953341/extract-overlay-ramdisk-q3jtwc8r/ramdisk
193 14:46:21.695789 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 14:46:21.696273 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 14:46:21.696550 [common] Applying overlay /var/lib/lava/dispatcher/tmp/953341/compress-overlay-n_45_afd/overlay-1.5.2.5.tar.gz to ramdisk
196 14:46:21.696767 [common] Applying overlay /var/lib/lava/dispatcher/tmp/953341/compress-overlay-n_45_afd/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/953341/extract-overlay-ramdisk-q3jtwc8r/ramdisk
197 14:46:21.726674 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 14:46:21.727066 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 14:46:21.727336 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 14:46:21.727562 Converting downloaded kernel to a uImage
201 14:46:21.727868 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/953341/tftp-deploy-7jhxdu8e/kernel/Image /var/lib/lava/dispatcher/tmp/953341/tftp-deploy-7jhxdu8e/kernel/uImage
202 14:46:22.222315 output: Image Name:
203 14:46:22.222717 output: Created: Thu Nov 7 14:46:21 2024
204 14:46:22.222924 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 14:46:22.223126 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 14:46:22.223326 output: Load Address: 01080000
207 14:46:22.223521 output: Entry Point: 01080000
208 14:46:22.223717 output:
209 14:46:22.224078 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 14:46:22.224351 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 14:46:22.224622 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 14:46:22.224874 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 14:46:22.225129 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 14:46:22.225382 Building ramdisk /var/lib/lava/dispatcher/tmp/953341/extract-overlay-ramdisk-q3jtwc8r/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/953341/extract-overlay-ramdisk-q3jtwc8r/ramdisk
215 14:46:24.941091 >> 181566 blocks
216 14:46:33.348406 Adding RAMdisk u-boot header.
217 14:46:33.349264 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/953341/extract-overlay-ramdisk-q3jtwc8r/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/953341/extract-overlay-ramdisk-q3jtwc8r/ramdisk.cpio.gz.uboot
218 14:46:33.616241 output: Image Name:
219 14:46:33.616860 output: Created: Thu Nov 7 14:46:33 2024
220 14:46:33.617282 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 14:46:33.617685 output: Data Size: 26051097 Bytes = 25440.52 KiB = 24.84 MiB
222 14:46:33.618085 output: Load Address: 00000000
223 14:46:33.618481 output: Entry Point: 00000000
224 14:46:33.618867 output:
225 14:46:33.619905 rename /var/lib/lava/dispatcher/tmp/953341/extract-overlay-ramdisk-q3jtwc8r/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/953341/tftp-deploy-7jhxdu8e/ramdisk/ramdisk.cpio.gz.uboot
226 14:46:33.620699 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 14:46:33.621253 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 14:46:33.621781 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 14:46:33.622242 No LXC device requested
230 14:46:33.622744 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 14:46:33.623254 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 14:46:33.623750 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 14:46:33.624202 Checking files for TFTP limit of 4294967296 bytes.
234 14:46:33.627044 end: 1 tftp-deploy (duration 00:00:17) [common]
235 14:46:33.627634 start: 2 uboot-action (timeout 00:05:00) [common]
236 14:46:33.628188 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 14:46:33.628690 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 14:46:33.629202 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 14:46:33.629719 Using kernel file from prepare-kernel: 953341/tftp-deploy-7jhxdu8e/kernel/uImage
240 14:46:33.630317 substitutions:
241 14:46:33.630746 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 14:46:33.631150 - {DTB_ADDR}: 0x01070000
243 14:46:33.631545 - {DTB}: 953341/tftp-deploy-7jhxdu8e/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 14:46:33.631942 - {INITRD}: 953341/tftp-deploy-7jhxdu8e/ramdisk/ramdisk.cpio.gz.uboot
245 14:46:33.632372 - {KERNEL_ADDR}: 0x01080000
246 14:46:33.632764 - {KERNEL}: 953341/tftp-deploy-7jhxdu8e/kernel/uImage
247 14:46:33.633155 - {LAVA_MAC}: None
248 14:46:33.633590 - {PRESEED_CONFIG}: None
249 14:46:33.634032 - {PRESEED_LOCAL}: None
250 14:46:33.634435 - {RAMDISK_ADDR}: 0x08000000
251 14:46:33.634823 - {RAMDISK}: 953341/tftp-deploy-7jhxdu8e/ramdisk/ramdisk.cpio.gz.uboot
252 14:46:33.635215 - {ROOT_PART}: None
253 14:46:33.635604 - {ROOT}: None
254 14:46:33.636014 - {SERVER_IP}: 192.168.6.2
255 14:46:33.636416 - {TEE_ADDR}: 0x83000000
256 14:46:33.636805 - {TEE}: None
257 14:46:33.637192 Parsed boot commands:
258 14:46:33.637567 - setenv autoload no
259 14:46:33.637955 - setenv initrd_high 0xffffffff
260 14:46:33.638394 - setenv fdt_high 0xffffffff
261 14:46:33.638799 - dhcp
262 14:46:33.639182 - setenv serverip 192.168.6.2
263 14:46:33.639564 - tftpboot 0x01080000 953341/tftp-deploy-7jhxdu8e/kernel/uImage
264 14:46:33.639951 - tftpboot 0x08000000 953341/tftp-deploy-7jhxdu8e/ramdisk/ramdisk.cpio.gz.uboot
265 14:46:33.640378 - tftpboot 0x01070000 953341/tftp-deploy-7jhxdu8e/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 14:46:33.640766 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 14:46:33.641160 - bootm 0x01080000 0x08000000 0x01070000
268 14:46:33.641662 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 14:46:33.643215 start: 2.3 connect-device (timeout 00:05:00) [common]
271 14:46:33.643685 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 14:46:33.658715 Setting prompt string to ['lava-test: # ']
273 14:46:33.660210 end: 2.3 connect-device (duration 00:00:00) [common]
274 14:46:33.660574 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 14:46:33.660861 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 14:46:33.661128 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 14:46:33.661765 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 14:46:33.698456 >> OK - accepted request
279 14:46:33.700654 Returned 0 in 0 seconds
280 14:46:33.801898 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 14:46:33.803648 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 14:46:33.804331 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 14:46:33.804900 Setting prompt string to ['Hit any key to stop autoboot']
285 14:46:33.805385 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 14:46:33.807057 Trying 192.168.56.21...
287 14:46:33.807577 Connected to conserv1.
288 14:46:33.808069 Escape character is '^]'.
289 14:46:33.833623
290 14:46:33.834156 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 14:46:33.834632
292 14:46:40.916200 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 14:46:40.916883 bl2_stage_init 0x01
294 14:46:40.917381 bl2_stage_init 0x81
295 14:46:40.921761 hw id: 0x0000 - pwm id 0x01
296 14:46:40.922289 bl2_stage_init 0xc1
297 14:46:40.927294 bl2_stage_init 0x02
298 14:46:40.927804
299 14:46:40.928340 L0:00000000
300 14:46:40.928809 L1:00000703
301 14:46:40.929265 L2:00008067
302 14:46:40.929703 L3:15000000
303 14:46:40.932799 S1:00000000
304 14:46:40.933300 B2:20282000
305 14:46:40.933754 B1:a0f83180
306 14:46:40.934198
307 14:46:40.934637 TE: 67212
308 14:46:40.935078
309 14:46:40.938421 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 14:46:40.938908
311 14:46:40.944079 Board ID = 1
312 14:46:40.944562 Set cpu clk to 24M
313 14:46:40.945010 Set clk81 to 24M
314 14:46:40.949750 Use GP1_pll as DSU clk.
315 14:46:40.950228 DSU clk: 1200 Mhz
316 14:46:40.950675 CPU clk: 1200 MHz
317 14:46:40.955350 Set clk81 to 166.6M
318 14:46:40.960889 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 14:46:40.961403 board id: 1
320 14:46:40.968055 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 14:46:40.978632 fw parse done
322 14:46:40.984648 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 14:46:41.027337 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 14:46:41.038171 PIEI prepare done
325 14:46:41.038757 fastboot data load
326 14:46:41.039169 fastboot data verify
327 14:46:41.043780 verify result: 266
328 14:46:41.049385 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 14:46:41.049825 LPDDR4 probe
330 14:46:41.050224 ddr clk to 1584MHz
331 14:46:41.057359 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 14:46:41.094825
333 14:46:41.095376 dmc_version 0001
334 14:46:41.101459 Check phy result
335 14:46:41.107281 INFO : End of CA training
336 14:46:41.107728 INFO : End of initialization
337 14:46:41.112860 INFO : Training has run successfully!
338 14:46:41.113326 Check phy result
339 14:46:41.118398 INFO : End of initialization
340 14:46:41.118904 INFO : End of read enable training
341 14:46:41.124287 INFO : End of fine write leveling
342 14:46:41.129668 INFO : End of Write leveling coarse delay
343 14:46:41.130110 INFO : Training has run successfully!
344 14:46:41.130524 Check phy result
345 14:46:41.135277 INFO : End of initialization
346 14:46:41.135712 INFO : End of read dq deskew training
347 14:46:41.140851 INFO : End of MPR read delay center optimization
348 14:46:41.146401 INFO : End of write delay center optimization
349 14:46:41.152078 INFO : End of read delay center optimization
350 14:46:41.152521 INFO : End of max read latency training
351 14:46:41.157706 INFO : Training has run successfully!
352 14:46:41.158195 1D training succeed
353 14:46:41.166870 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 14:46:41.214415 Check phy result
355 14:46:41.214878 INFO : End of initialization
356 14:46:41.236773 INFO : End of 2D read delay Voltage center optimization
357 14:46:41.255902 INFO : End of 2D read delay Voltage center optimization
358 14:46:41.307890 INFO : End of 2D write delay Voltage center optimization
359 14:46:41.357027 INFO : End of 2D write delay Voltage center optimization
360 14:46:41.362816 INFO : Training has run successfully!
361 14:46:41.363240
362 14:46:41.363636 channel==0
363 14:46:41.368225 RxClkDly_Margin_A0==78 ps 8
364 14:46:41.368670 TxDqDly_Margin_A0==98 ps 10
365 14:46:41.371513 RxClkDly_Margin_A1==88 ps 9
366 14:46:41.371940 TxDqDly_Margin_A1==88 ps 9
367 14:46:41.376952 TrainedVREFDQ_A0==74
368 14:46:41.377396 TrainedVREFDQ_A1==74
369 14:46:41.382611 VrefDac_Margin_A0==23
370 14:46:41.383038 DeviceVref_Margin_A0==40
371 14:46:41.383429 VrefDac_Margin_A1==23
372 14:46:41.388180 DeviceVref_Margin_A1==40
373 14:46:41.388604
374 14:46:41.388995
375 14:46:41.389385 channel==1
376 14:46:41.389772 RxClkDly_Margin_A0==78 ps 8
377 14:46:41.393754 TxDqDly_Margin_A0==98 ps 10
378 14:46:41.394182 RxClkDly_Margin_A1==78 ps 8
379 14:46:41.399425 TxDqDly_Margin_A1==78 ps 8
380 14:46:41.399862 TrainedVREFDQ_A0==76
381 14:46:41.400287 TrainedVREFDQ_A1==76
382 14:46:41.404855 VrefDac_Margin_A0==22
383 14:46:41.405285 DeviceVref_Margin_A0==38
384 14:46:41.410540 VrefDac_Margin_A1==22
385 14:46:41.410967 DeviceVref_Margin_A1==38
386 14:46:41.411353
387 14:46:41.416145 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 14:46:41.416588
389 14:46:41.444087 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
390 14:46:41.449798 2D training succeed
391 14:46:41.455286 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 14:46:41.455722 auto size-- 65535DDR cs0 size: 2048MB
393 14:46:41.460877 DDR cs1 size: 2048MB
394 14:46:41.461300 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 14:46:41.466464 cs0 DataBus test pass
396 14:46:41.466884 cs1 DataBus test pass
397 14:46:41.467270 cs0 AddrBus test pass
398 14:46:41.472067 cs1 AddrBus test pass
399 14:46:41.472493
400 14:46:41.472885 100bdlr_step_size ps== 478
401 14:46:41.473279 result report
402 14:46:41.477669 boot times 0Enable ddr reg access
403 14:46:41.485307 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 14:46:41.499173 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 14:46:42.154338 bl2z: ptr: 05129330, size: 00001e40
406 14:46:42.160397 0.0;M3 CHK:0;cm4_sp_mode 0
407 14:46:42.160855 MVN_1=0x00000000
408 14:46:42.161249 MVN_2=0x00000000
409 14:46:42.171859 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 14:46:42.172355 OPS=0x04
411 14:46:42.172750 ring efuse init
412 14:46:42.177493 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 14:46:42.177934 [0.017320 Inits done]
414 14:46:42.178323 secure task start!
415 14:46:42.185336 high task start!
416 14:46:42.185760 low task start!
417 14:46:42.186147 run into bl31
418 14:46:42.193901 NOTICE: BL31: v1.3(release):4fc40b1
419 14:46:42.201803 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 14:46:42.202246 NOTICE: BL31: G12A normal boot!
421 14:46:42.217263 NOTICE: BL31: BL33 decompress pass
422 14:46:42.222944 ERROR: Error initializing runtime service opteed_fast
423 14:46:44.972525 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 14:46:44.972966 bl2_stage_init 0x01
425 14:46:44.973185 bl2_stage_init 0x81
426 14:46:44.978122 hw id: 0x0000 - pwm id 0x01
427 14:46:44.978430 bl2_stage_init 0xc1
428 14:46:44.978640 bl2_stage_init 0x02
429 14:46:44.978844
430 14:46:44.983782 L0:00000000
431 14:46:44.984087 L1:00000703
432 14:46:44.984299 L2:00008067
433 14:46:44.984503 L3:15000000
434 14:46:44.984705 S1:00000000
435 14:46:44.989306 B2:20282000
436 14:46:44.989581 B1:a0f83180
437 14:46:44.989783
438 14:46:44.989982 TE: 71782
439 14:46:44.990182
440 14:46:44.995054 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 14:46:44.995346
442 14:46:45.000619 Board ID = 1
443 14:46:45.001133 Set cpu clk to 24M
444 14:46:45.001537 Set clk81 to 24M
445 14:46:45.006108 Use GP1_pll as DSU clk.
446 14:46:45.006564 DSU clk: 1200 Mhz
447 14:46:45.006963 CPU clk: 1200 MHz
448 14:46:45.007354 Set clk81 to 166.6M
449 14:46:45.017364 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 14:46:45.017875 board id: 1
451 14:46:45.023694 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 14:46:45.034410 fw parse done
453 14:46:45.040322 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 14:46:45.083177 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 14:46:45.093940 PIEI prepare done
456 14:46:45.094404 fastboot data load
457 14:46:45.094801 fastboot data verify
458 14:46:45.099500 verify result: 266
459 14:46:45.105109 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 14:46:45.105552 LPDDR4 probe
461 14:46:45.105943 ddr clk to 1584MHz
462 14:46:45.113221 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 14:46:45.150380
464 14:46:45.150897 dmc_version 0001
465 14:46:45.157034 Check phy result
466 14:46:45.162961 INFO : End of CA training
467 14:46:45.163433 INFO : End of initialization
468 14:46:45.168528 INFO : Training has run successfully!
469 14:46:45.168978 Check phy result
470 14:46:45.174175 INFO : End of initialization
471 14:46:45.174630 INFO : End of read enable training
472 14:46:45.179745 INFO : End of fine write leveling
473 14:46:45.185349 INFO : End of Write leveling coarse delay
474 14:46:45.185795 INFO : Training has run successfully!
475 14:46:45.186207 Check phy result
476 14:46:45.190938 INFO : End of initialization
477 14:46:45.191377 INFO : End of read dq deskew training
478 14:46:45.196548 INFO : End of MPR read delay center optimization
479 14:46:45.202191 INFO : End of write delay center optimization
480 14:46:45.207726 INFO : End of read delay center optimization
481 14:46:45.208218 INFO : End of max read latency training
482 14:46:45.213340 INFO : Training has run successfully!
483 14:46:45.213784 1D training succeed
484 14:46:45.222529 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 14:46:45.270288 Check phy result
486 14:46:45.270833 INFO : End of initialization
487 14:46:45.292472 INFO : End of 2D read delay Voltage center optimization
488 14:46:45.311657 INFO : End of 2D read delay Voltage center optimization
489 14:46:45.363597 INFO : End of 2D write delay Voltage center optimization
490 14:46:45.412784 INFO : End of 2D write delay Voltage center optimization
491 14:46:45.418381 INFO : Training has run successfully!
492 14:46:45.418880
493 14:46:45.419158 channel==0
494 14:46:45.423922 RxClkDly_Margin_A0==78 ps 8
495 14:46:45.424297 TxDqDly_Margin_A0==98 ps 10
496 14:46:45.427209 RxClkDly_Margin_A1==88 ps 9
497 14:46:45.427660 TxDqDly_Margin_A1==88 ps 9
498 14:46:45.435927 TrainedVREFDQ_A0==74
499 14:46:45.437408 TrainedVREFDQ_A1==74
500 14:46:45.437744 VrefDac_Margin_A0==23
501 14:46:45.438516 DeviceVref_Margin_A0==40
502 14:46:45.438945 VrefDac_Margin_A1==23
503 14:46:45.444069 DeviceVref_Margin_A1==40
504 14:46:45.444453
505 14:46:45.444673
506 14:46:45.444893 channel==1
507 14:46:45.445101 RxClkDly_Margin_A0==78 ps 8
508 14:46:45.449598 TxDqDly_Margin_A0==98 ps 10
509 14:46:45.449957 RxClkDly_Margin_A1==88 ps 9
510 14:46:45.455230 TxDqDly_Margin_A1==88 ps 9
511 14:46:45.455732 TrainedVREFDQ_A0==78
512 14:46:45.456133 TrainedVREFDQ_A1==78
513 14:46:45.460798 VrefDac_Margin_A0==22
514 14:46:45.461280 DeviceVref_Margin_A0==36
515 14:46:45.466316 VrefDac_Margin_A1==22
516 14:46:45.466799 DeviceVref_Margin_A1==36
517 14:46:45.467219
518 14:46:45.471948 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 14:46:45.472450
520 14:46:45.499894 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000019 00000017 00000019 00000015 00000018 00000014 00000016 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
521 14:46:45.505493 2D training succeed
522 14:46:45.511110 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 14:46:45.511585 auto size-- 65535DDR cs0 size: 2048MB
524 14:46:45.516657 DDR cs1 size: 2048MB
525 14:46:45.517117 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 14:46:45.522279 cs0 DataBus test pass
527 14:46:45.522749 cs1 DataBus test pass
528 14:46:45.523159 cs0 AddrBus test pass
529 14:46:45.528012 cs1 AddrBus test pass
530 14:46:45.528498
531 14:46:45.528921 100bdlr_step_size ps== 478
532 14:46:45.529343 result report
533 14:46:45.533572 boot times 0Enable ddr reg access
534 14:46:45.541061 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 14:46:45.554841 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 14:46:46.208838 bl2z: ptr: 05129330, size: 00001e40
537 14:46:46.216949 0.0;M3 CHK:0;cm4_sp_mode 0
538 14:46:46.217439 MVN_1=0x00000000
539 14:46:46.217860 MVN_2=0x00000000
540 14:46:46.228432 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 14:46:46.228953 OPS=0x04
542 14:46:46.229383 ring efuse init
543 14:46:46.234251 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 14:46:46.234724 [0.017320 Inits done]
545 14:46:46.235133 secure task start!
546 14:46:46.242016 high task start!
547 14:46:46.242467 low task start!
548 14:46:46.242876 run into bl31
549 14:46:46.250588 NOTICE: BL31: v1.3(release):4fc40b1
550 14:46:46.258385 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 14:46:46.258840 NOTICE: BL31: G12A normal boot!
552 14:46:46.273877 NOTICE: BL31: BL33 decompress pass
553 14:46:46.279569 ERROR: Error initializing runtime service opteed_fast
554 14:46:47.669849 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 14:46:47.670282 bl2_stage_init 0x01
556 14:46:47.670493 bl2_stage_init 0x81
557 14:46:47.675539 hw id: 0x0000 - pwm id 0x01
558 14:46:47.675842 bl2_stage_init 0xc1
559 14:46:47.680968 bl2_stage_init 0x02
560 14:46:47.681468
561 14:46:47.681892 L0:00000000
562 14:46:47.682304 L1:00000703
563 14:46:47.682706 L2:00008067
564 14:46:47.683108 L3:15000000
565 14:46:47.686606 S1:00000000
566 14:46:47.687057 B2:20282000
567 14:46:47.687484 B1:a0f83180
568 14:46:47.687922
569 14:46:47.688385 TE: 70823
570 14:46:47.688794
571 14:46:47.692295 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 14:46:47.692768
573 14:46:47.697762 Board ID = 1
574 14:46:47.698220 Set cpu clk to 24M
575 14:46:47.698628 Set clk81 to 24M
576 14:46:47.703454 Use GP1_pll as DSU clk.
577 14:46:47.703910 DSU clk: 1200 Mhz
578 14:46:47.704359 CPU clk: 1200 MHz
579 14:46:47.708945 Set clk81 to 166.6M
580 14:46:47.714568 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 14:46:47.715106 board id: 1
582 14:46:47.721746 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 14:46:47.732681 fw parse done
584 14:46:47.738655 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 14:46:47.781768 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 14:46:47.792849 PIEI prepare done
587 14:46:47.793333 fastboot data load
588 14:46:47.793766 fastboot data verify
589 14:46:47.798496 verify result: 266
590 14:46:47.804053 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 14:46:47.804535 LPDDR4 probe
592 14:46:47.804957 ddr clk to 1584MHz
593 14:46:47.812075 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 14:46:47.849875
595 14:46:47.850444 dmc_version 0001
596 14:46:47.856809 Check phy result
597 14:46:47.862758 INFO : End of CA training
598 14:46:47.863223 INFO : End of initialization
599 14:46:47.868357 INFO : Training has run successfully!
600 14:46:47.868819 Check phy result
601 14:46:47.873964 INFO : End of initialization
602 14:46:47.874416 INFO : End of read enable training
603 14:46:47.877252 INFO : End of fine write leveling
604 14:46:47.882766 INFO : End of Write leveling coarse delay
605 14:46:47.888471 INFO : Training has run successfully!
606 14:46:47.888930 Check phy result
607 14:46:47.889350 INFO : End of initialization
608 14:46:47.894013 INFO : End of read dq deskew training
609 14:46:47.899565 INFO : End of MPR read delay center optimization
610 14:46:47.900093 INFO : End of write delay center optimization
611 14:46:47.905227 INFO : End of read delay center optimization
612 14:46:47.910834 INFO : End of max read latency training
613 14:46:47.911305 INFO : Training has run successfully!
614 14:46:47.916510 1D training succeed
615 14:46:47.922405 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 14:46:47.970782 Check phy result
617 14:46:47.971354 INFO : End of initialization
618 14:46:47.998163 INFO : End of 2D read delay Voltage center optimization
619 14:46:48.022323 INFO : End of 2D read delay Voltage center optimization
620 14:46:48.078941 INFO : End of 2D write delay Voltage center optimization
621 14:46:48.132993 INFO : End of 2D write delay Voltage center optimization
622 14:46:48.138511 INFO : Training has run successfully!
623 14:46:48.139019
624 14:46:48.139450 channel==0
625 14:46:48.143968 RxClkDly_Margin_A0==78 ps 8
626 14:46:48.144475 TxDqDly_Margin_A0==98 ps 10
627 14:46:48.149602 RxClkDly_Margin_A1==88 ps 9
628 14:46:48.150057 TxDqDly_Margin_A1==88 ps 9
629 14:46:48.150470 TrainedVREFDQ_A0==74
630 14:46:48.155222 TrainedVREFDQ_A1==75
631 14:46:48.155677 VrefDac_Margin_A0==24
632 14:46:48.156116 DeviceVref_Margin_A0==40
633 14:46:48.160838 VrefDac_Margin_A1==23
634 14:46:48.161292 DeviceVref_Margin_A1==39
635 14:46:48.161700
636 14:46:48.162108
637 14:46:48.162510 channel==1
638 14:46:48.166488 RxClkDly_Margin_A0==78 ps 8
639 14:46:48.166948 TxDqDly_Margin_A0==98 ps 10
640 14:46:48.172051 RxClkDly_Margin_A1==78 ps 8
641 14:46:48.172512 TxDqDly_Margin_A1==88 ps 9
642 14:46:48.177568 TrainedVREFDQ_A0==78
643 14:46:48.178030 TrainedVREFDQ_A1==77
644 14:46:48.178447 VrefDac_Margin_A0==22
645 14:46:48.183200 DeviceVref_Margin_A0==36
646 14:46:48.183659 VrefDac_Margin_A1==22
647 14:46:48.188862 DeviceVref_Margin_A1==37
648 14:46:48.189312
649 14:46:48.189720 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 14:46:48.190122
651 14:46:48.222334 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000060
652 14:46:48.222908 2D training succeed
653 14:46:48.227933 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 14:46:48.233537 auto size-- 65535DDR cs0 size: 2048MB
655 14:46:48.233995 DDR cs1 size: 2048MB
656 14:46:48.239103 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 14:46:48.239559 cs0 DataBus test pass
658 14:46:48.244736 cs1 DataBus test pass
659 14:46:48.245198 cs0 AddrBus test pass
660 14:46:48.245613 cs1 AddrBus test pass
661 14:46:48.246014
662 14:46:48.250318 100bdlr_step_size ps== 478
663 14:46:48.250799 result report
664 14:46:48.255940 boot times 0Enable ddr reg access
665 14:46:48.261092 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 14:46:48.274974 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 14:46:48.933979 bl2z: ptr: 05129330, size: 00001e40
668 14:46:48.942605 0.0;M3 CHK:0;cm4_sp_mode 0
669 14:46:48.943074 MVN_1=0x00000000
670 14:46:48.943335 MVN_2=0x00000000
671 14:46:48.954052 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 14:46:48.954401 OPS=0x04
673 14:46:48.954626 ring efuse init
674 14:46:48.959746 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 14:46:48.960240 [0.017354 Inits done]
676 14:46:48.960587 secure task start!
677 14:46:48.967208 high task start!
678 14:46:48.967645 low task start!
679 14:46:48.967970 run into bl31
680 14:46:48.975852 NOTICE: BL31: v1.3(release):4fc40b1
681 14:46:48.983685 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 14:46:48.984042 NOTICE: BL31: G12A normal boot!
683 14:46:48.999206 NOTICE: BL31: BL33 decompress pass
684 14:46:49.004877 ERROR: Error initializing runtime service opteed_fast
685 14:46:49.800190
686 14:46:49.800606
687 14:46:49.805690 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 14:46:49.806120
689 14:46:49.809092 Model: Libre Computer AML-S905D3-CC Solitude
690 14:46:49.956164 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 14:46:49.971566 DRAM: 2 GiB (effective 3.8 GiB)
692 14:46:50.072554 Core: 406 devices, 33 uclasses, devicetree: separate
693 14:46:50.078878 WDT: Not starting watchdog@f0d0
694 14:46:50.103609 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 14:46:50.115774 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 14:46:50.120210 ** Bad device specification mmc 0 **
697 14:46:50.130721 Card did not respond to voltage select! : -110
698 14:46:50.138361 ** Bad device specification mmc 0 **
699 14:46:50.138705 Couldn't find partition mmc 0
700 14:46:50.146765 Card did not respond to voltage select! : -110
701 14:46:50.152212 ** Bad device specification mmc 0 **
702 14:46:50.152556 Couldn't find partition mmc 0
703 14:46:50.157301 Error: could not access storage.
704 14:46:50.454759 Net: eth0: ethernet@ff3f0000
705 14:46:50.455190 starting USB...
706 14:46:50.699457 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 14:46:50.700066 Starting the controller
708 14:46:50.706439 USB XHCI 1.10
709 14:46:52.260632 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 14:46:52.269003 scanning usb for storage devices... 0 Storage Device(s) found
712 14:46:52.320618 Hit any key to stop autoboot: 1
713 14:46:52.321666 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 14:46:52.322388 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 14:46:52.322935 Setting prompt string to ['=>']
716 14:46:52.323473 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 14:46:52.335095 0
718 14:46:52.336119 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 14:46:52.437479 => setenv autoload no
721 14:46:52.438283 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 14:46:52.443596 setenv autoload no
724 14:46:52.545242 => setenv initrd_high 0xffffffff
725 14:46:52.546023 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 14:46:52.550338 setenv initrd_high 0xffffffff
728 14:46:52.651907 => setenv fdt_high 0xffffffff
729 14:46:52.652678 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 14:46:52.656988 setenv fdt_high 0xffffffff
732 14:46:52.758559 => dhcp
733 14:46:52.759276 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 14:46:52.763280 dhcp
735 14:46:53.618390 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 14:46:53.619054 Speed: 1000, full duplex
737 14:46:53.619533 BOOTP broadcast 1
738 14:46:53.867331 BOOTP broadcast 2
739 14:46:53.879025 DHCP client bound to address 192.168.6.21 (259 ms)
741 14:46:53.981314 => setenv serverip 192.168.6.2
742 14:46:53.982306 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
743 14:46:53.986656 setenv serverip 192.168.6.2
745 14:46:54.088450 => tftpboot 0x01080000 953341/tftp-deploy-7jhxdu8e/kernel/uImage
746 14:46:54.089744 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
747 14:46:54.096408 tftpboot 0x01080000 953341/tftp-deploy-7jhxdu8e/kernel/uImage
748 14:46:54.097140 Speed: 1000, full duplex
749 14:46:54.097776 Using ethernet@ff3f0000 device
750 14:46:54.101775 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
751 14:46:54.107338 Filename '953341/tftp-deploy-7jhxdu8e/kernel/uImage'.
752 14:46:54.111273 Load address: 0x1080000
753 14:46:56.950697 Loading: *################################################## 43.6 MiB
754 14:46:56.951315 15.3 MiB/s
755 14:46:56.951723 done
756 14:46:56.955322 Bytes transferred = 45713984 (2b98a40 hex)
758 14:46:57.056797 => tftpboot 0x08000000 953341/tftp-deploy-7jhxdu8e/ramdisk/ramdisk.cpio.gz.uboot
759 14:46:57.057543 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
760 14:46:57.064328 tftpboot 0x08000000 953341/tftp-deploy-7jhxdu8e/ramdisk/ramdisk.cpio.gz.uboot
761 14:46:57.064776 Speed: 1000, full duplex
762 14:46:57.065176 Using ethernet@ff3f0000 device
763 14:46:57.069882 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
764 14:46:57.079688 Filename '953341/tftp-deploy-7jhxdu8e/ramdisk/ramdisk.cpio.gz.uboot'.
765 14:46:57.080175 Load address: 0x8000000
766 14:46:58.708046 Loading: *################################################# UDP wrong checksum 00000005 00004c43
767 14:47:03.708870 T UDP wrong checksum 00000005 00004c43
768 14:47:06.117984 UDP wrong checksum 000000ff 0000bcde
769 14:47:06.169825 UDP wrong checksum 000000ff 00004cd1
770 14:47:13.711068 T T UDP wrong checksum 00000005 00004c43
771 14:47:33.506709 T T T UDP wrong checksum 000000ff 00004561
772 14:47:33.529130 UDP wrong checksum 000000ff 0000dc53
773 14:47:33.715458 T UDP wrong checksum 00000005 00004c43
774 14:47:53.719918 T T T
775 14:47:53.720381 Retry count exceeded; starting again
777 14:47:53.721778 end: 2.4.3 bootloader-commands (duration 00:01:01) [common]
780 14:47:53.722755 end: 2.4 uboot-commands (duration 00:01:20) [common]
782 14:47:53.723509 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
784 14:47:53.724123 end: 2 uboot-action (duration 00:01:20) [common]
786 14:47:53.725012 Cleaning after the job
787 14:47:53.725354 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953341/tftp-deploy-7jhxdu8e/ramdisk
788 14:47:53.726237 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953341/tftp-deploy-7jhxdu8e/kernel
789 14:47:53.730183 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953341/tftp-deploy-7jhxdu8e/dtb
790 14:47:53.730905 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953341/tftp-deploy-7jhxdu8e/modules
791 14:47:53.734148 start: 4.1 power-off (timeout 00:00:30) [common]
792 14:47:53.734761 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
793 14:47:53.795520 >> OK - accepted request
794 14:47:53.797845 Returned 0 in 0 seconds
795 14:47:53.898680 end: 4.1 power-off (duration 00:00:00) [common]
797 14:47:53.899726 start: 4.2 read-feedback (timeout 00:10:00) [common]
798 14:47:53.900485 Listened to connection for namespace 'common' for up to 1s
799 14:47:54.901471 Finalising connection for namespace 'common'
800 14:47:54.902312 Disconnecting from shell: Finalise
801 14:47:54.902951 =>
802 14:47:55.004001 end: 4.2 read-feedback (duration 00:00:01) [common]
803 14:47:55.004480 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/953341
804 14:47:55.294326 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/953341
805 14:47:55.294925 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.