Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 17:50:41.385949 lava-dispatcher, installed at version: 2024.01
2 17:50:41.386751 start: 0 validate
3 17:50:41.387239 Start time: 2024-11-07 17:50:41.387210+00:00 (UTC)
4 17:50:41.387787 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 17:50:41.388374 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 17:50:41.433100 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 17:50:41.433703 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-5-g94debe5eaa0ad%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 17:50:41.462653 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 17:50:41.463364 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-5-g94debe5eaa0ad%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 17:50:41.492811 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 17:50:41.493335 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 17:50:41.526616 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 17:50:41.527133 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-5-g94debe5eaa0ad%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 17:50:41.566942 validate duration: 0.18
16 17:50:41.568050 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 17:50:41.568471 start: 1.1 download-retry (timeout 00:10:00) [common]
18 17:50:41.568853 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 17:50:41.569703 Not decompressing ramdisk as can be used compressed.
20 17:50:41.570283 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 17:50:41.570657 saving as /var/lib/lava/dispatcher/tmp/953294/tftp-deploy-1dgoogz1/ramdisk/initrd.cpio.gz
22 17:50:41.571021 total size: 5628140 (5 MB)
23 17:50:41.603251 progress 0 % (0 MB)
24 17:50:41.607285 progress 5 % (0 MB)
25 17:50:41.611609 progress 10 % (0 MB)
26 17:50:41.615530 progress 15 % (0 MB)
27 17:50:41.619787 progress 20 % (1 MB)
28 17:50:41.623618 progress 25 % (1 MB)
29 17:50:41.627814 progress 30 % (1 MB)
30 17:50:41.632077 progress 35 % (1 MB)
31 17:50:41.635843 progress 40 % (2 MB)
32 17:50:41.639908 progress 45 % (2 MB)
33 17:50:41.643623 progress 50 % (2 MB)
34 17:50:41.647868 progress 55 % (2 MB)
35 17:50:41.652012 progress 60 % (3 MB)
36 17:50:41.655740 progress 65 % (3 MB)
37 17:50:41.659909 progress 70 % (3 MB)
38 17:50:41.663701 progress 75 % (4 MB)
39 17:50:41.667859 progress 80 % (4 MB)
40 17:50:41.671631 progress 85 % (4 MB)
41 17:50:41.676024 progress 90 % (4 MB)
42 17:50:41.680169 progress 95 % (5 MB)
43 17:50:41.683518 progress 100 % (5 MB)
44 17:50:41.684180 5 MB downloaded in 0.11 s (47.44 MB/s)
45 17:50:41.684731 end: 1.1.1 http-download (duration 00:00:00) [common]
47 17:50:41.685621 end: 1.1 download-retry (duration 00:00:00) [common]
48 17:50:41.685916 start: 1.2 download-retry (timeout 00:10:00) [common]
49 17:50:41.686188 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 17:50:41.686654 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-5-g94debe5eaa0ad/arm64/defconfig/gcc-12/kernel/Image
51 17:50:41.686900 saving as /var/lib/lava/dispatcher/tmp/953294/tftp-deploy-1dgoogz1/kernel/Image
52 17:50:41.687112 total size: 45713920 (43 MB)
53 17:50:41.687324 No compression specified
54 17:50:41.719501 progress 0 % (0 MB)
55 17:50:41.749442 progress 5 % (2 MB)
56 17:50:41.779273 progress 10 % (4 MB)
57 17:50:41.808908 progress 15 % (6 MB)
58 17:50:41.838271 progress 20 % (8 MB)
59 17:50:41.868532 progress 25 % (10 MB)
60 17:50:41.898089 progress 30 % (13 MB)
61 17:50:41.928119 progress 35 % (15 MB)
62 17:50:41.958403 progress 40 % (17 MB)
63 17:50:41.987883 progress 45 % (19 MB)
64 17:50:42.018092 progress 50 % (21 MB)
65 17:50:42.048143 progress 55 % (24 MB)
66 17:50:42.078375 progress 60 % (26 MB)
67 17:50:42.108129 progress 65 % (28 MB)
68 17:50:42.137841 progress 70 % (30 MB)
69 17:50:42.168938 progress 75 % (32 MB)
70 17:50:42.199106 progress 80 % (34 MB)
71 17:50:42.228313 progress 85 % (37 MB)
72 17:50:42.258037 progress 90 % (39 MB)
73 17:50:42.288300 progress 95 % (41 MB)
74 17:50:42.318472 progress 100 % (43 MB)
75 17:50:42.319005 43 MB downloaded in 0.63 s (68.99 MB/s)
76 17:50:42.319482 end: 1.2.1 http-download (duration 00:00:01) [common]
78 17:50:42.320337 end: 1.2 download-retry (duration 00:00:01) [common]
79 17:50:42.320618 start: 1.3 download-retry (timeout 00:09:59) [common]
80 17:50:42.320887 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 17:50:42.321456 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-5-g94debe5eaa0ad/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 17:50:42.321741 saving as /var/lib/lava/dispatcher/tmp/953294/tftp-deploy-1dgoogz1/dtb/meson-g12b-a311d-libretech-cc.dtb
83 17:50:42.321953 total size: 54703 (0 MB)
84 17:50:42.322164 No compression specified
85 17:50:42.363182 progress 59 % (0 MB)
86 17:50:42.364068 progress 100 % (0 MB)
87 17:50:42.364642 0 MB downloaded in 0.04 s (1.22 MB/s)
88 17:50:42.365131 end: 1.3.1 http-download (duration 00:00:00) [common]
90 17:50:42.365959 end: 1.3 download-retry (duration 00:00:00) [common]
91 17:50:42.366228 start: 1.4 download-retry (timeout 00:09:59) [common]
92 17:50:42.366495 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 17:50:42.366952 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 17:50:42.367200 saving as /var/lib/lava/dispatcher/tmp/953294/tftp-deploy-1dgoogz1/nfsrootfs/full.rootfs.tar
95 17:50:42.367405 total size: 474398908 (452 MB)
96 17:50:42.367617 Using unxz to decompress xz
97 17:50:42.408795 progress 0 % (0 MB)
98 17:50:43.512536 progress 5 % (22 MB)
99 17:50:45.014606 progress 10 % (45 MB)
100 17:50:45.495828 progress 15 % (67 MB)
101 17:50:46.301543 progress 20 % (90 MB)
102 17:50:46.855537 progress 25 % (113 MB)
103 17:50:47.227605 progress 30 % (135 MB)
104 17:50:47.841443 progress 35 % (158 MB)
105 17:50:48.766293 progress 40 % (181 MB)
106 17:50:49.612978 progress 45 % (203 MB)
107 17:50:50.171636 progress 50 % (226 MB)
108 17:50:50.821934 progress 55 % (248 MB)
109 17:50:52.046942 progress 60 % (271 MB)
110 17:50:53.541548 progress 65 % (294 MB)
111 17:50:55.388195 progress 70 % (316 MB)
112 17:50:58.766049 progress 75 % (339 MB)
113 17:51:01.222461 progress 80 % (361 MB)
114 17:51:04.146128 progress 85 % (384 MB)
115 17:51:07.482253 progress 90 % (407 MB)
116 17:51:10.700294 progress 95 % (429 MB)
117 17:51:13.893317 progress 100 % (452 MB)
118 17:51:13.907310 452 MB downloaded in 31.54 s (14.34 MB/s)
119 17:51:13.907898 end: 1.4.1 http-download (duration 00:00:32) [common]
121 17:51:13.909697 end: 1.4 download-retry (duration 00:00:32) [common]
122 17:51:13.910271 start: 1.5 download-retry (timeout 00:09:28) [common]
123 17:51:13.910839 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 17:51:13.912053 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-5-g94debe5eaa0ad/arm64/defconfig/gcc-12/modules.tar.xz
125 17:51:13.912623 saving as /var/lib/lava/dispatcher/tmp/953294/tftp-deploy-1dgoogz1/modules/modules.tar
126 17:51:13.913074 total size: 11609576 (11 MB)
127 17:51:13.913534 Using unxz to decompress xz
128 17:51:13.960896 progress 0 % (0 MB)
129 17:51:14.029603 progress 5 % (0 MB)
130 17:51:14.105627 progress 10 % (1 MB)
131 17:51:14.204787 progress 15 % (1 MB)
132 17:51:14.297598 progress 20 % (2 MB)
133 17:51:14.376977 progress 25 % (2 MB)
134 17:51:14.452994 progress 30 % (3 MB)
135 17:51:14.531313 progress 35 % (3 MB)
136 17:51:14.604288 progress 40 % (4 MB)
137 17:51:14.679320 progress 45 % (5 MB)
138 17:51:14.763124 progress 50 % (5 MB)
139 17:51:14.839608 progress 55 % (6 MB)
140 17:51:14.924065 progress 60 % (6 MB)
141 17:51:15.003923 progress 65 % (7 MB)
142 17:51:15.084294 progress 70 % (7 MB)
143 17:51:15.163008 progress 75 % (8 MB)
144 17:51:15.246634 progress 80 % (8 MB)
145 17:51:15.326626 progress 85 % (9 MB)
146 17:51:15.405299 progress 90 % (9 MB)
147 17:51:15.483220 progress 95 % (10 MB)
148 17:51:15.560559 progress 100 % (11 MB)
149 17:51:15.573445 11 MB downloaded in 1.66 s (6.67 MB/s)
150 17:51:15.574341 end: 1.5.1 http-download (duration 00:00:02) [common]
152 17:51:15.575942 end: 1.5 download-retry (duration 00:00:02) [common]
153 17:51:15.576528 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
154 17:51:15.577054 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
155 17:51:31.043755 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/953294/extract-nfsrootfs-vw5dnzfj
156 17:51:31.044392 end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
157 17:51:31.044682 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 17:51:31.045384 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y
159 17:51:31.045829 makedir: /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin
160 17:51:31.046156 makedir: /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/tests
161 17:51:31.046479 makedir: /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/results
162 17:51:31.046823 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-add-keys
163 17:51:31.047350 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-add-sources
164 17:51:31.047848 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-background-process-start
165 17:51:31.048396 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-background-process-stop
166 17:51:31.048923 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-common-functions
167 17:51:31.049417 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-echo-ipv4
168 17:51:31.049893 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-install-packages
169 17:51:31.050373 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-installed-packages
170 17:51:31.050871 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-os-build
171 17:51:31.051395 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-probe-channel
172 17:51:31.051868 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-probe-ip
173 17:51:31.052376 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-target-ip
174 17:51:31.052853 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-target-mac
175 17:51:31.053324 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-target-storage
176 17:51:31.053803 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-test-case
177 17:51:31.054275 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-test-event
178 17:51:31.054764 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-test-feedback
179 17:51:31.055263 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-test-raise
180 17:51:31.055734 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-test-reference
181 17:51:31.056294 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-test-runner
182 17:51:31.056789 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-test-set
183 17:51:31.057253 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-test-shell
184 17:51:31.057723 Updating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-install-packages (oe)
185 17:51:31.058246 Updating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/bin/lava-installed-packages (oe)
186 17:51:31.058673 Creating /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/environment
187 17:51:31.059031 LAVA metadata
188 17:51:31.059286 - LAVA_JOB_ID=953294
189 17:51:31.059499 - LAVA_DISPATCHER_IP=192.168.6.2
190 17:51:31.059849 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 17:51:31.060835 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 17:51:31.061146 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 17:51:31.061353 skipped lava-vland-overlay
194 17:51:31.061595 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 17:51:31.061847 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 17:51:31.062065 skipped lava-multinode-overlay
197 17:51:31.062306 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 17:51:31.062557 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 17:51:31.062803 Loading test definitions
200 17:51:31.063079 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 17:51:31.063298 Using /lava-953294 at stage 0
202 17:51:31.064447 uuid=953294_1.6.2.4.1 testdef=None
203 17:51:31.064748 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 17:51:31.065006 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 17:51:31.066706 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 17:51:31.067485 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 17:51:31.069662 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 17:51:31.070489 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:10) [common]
211 17:51:31.072569 runner path: /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 953294_1.6.2.4.1
212 17:51:31.073106 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 17:51:31.073875 Creating lava-test-runner.conf files
215 17:51:31.074078 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/953294/lava-overlay-lnzovz9y/lava-953294/0 for stage 0
216 17:51:31.074410 - 0_v4l2-decoder-conformance-vp9
217 17:51:31.074744 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 17:51:31.075012 start: 1.6.2.5 compress-overlay (timeout 00:09:10) [common]
219 17:51:31.096283 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 17:51:31.096633 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:10) [common]
221 17:51:31.096898 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 17:51:31.097160 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 17:51:31.097421 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:10) [common]
224 17:51:31.718821 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 17:51:31.719300 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 17:51:31.719570 extracting modules file /var/lib/lava/dispatcher/tmp/953294/tftp-deploy-1dgoogz1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/953294/extract-nfsrootfs-vw5dnzfj
227 17:51:33.076315 extracting modules file /var/lib/lava/dispatcher/tmp/953294/tftp-deploy-1dgoogz1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/953294/extract-overlay-ramdisk-t2tn91sk/ramdisk
228 17:51:34.461379 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 17:51:34.461863 start: 1.6.5 apply-overlay-tftp (timeout 00:09:07) [common]
230 17:51:34.462157 [common] Applying overlay to NFS
231 17:51:34.462381 [common] Applying overlay /var/lib/lava/dispatcher/tmp/953294/compress-overlay-bp1zfr2a/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/953294/extract-nfsrootfs-vw5dnzfj
232 17:51:34.491210 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 17:51:34.491585 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 17:51:34.491876 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 17:51:34.492149 Converting downloaded kernel to a uImage
236 17:51:34.492466 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/953294/tftp-deploy-1dgoogz1/kernel/Image /var/lib/lava/dispatcher/tmp/953294/tftp-deploy-1dgoogz1/kernel/uImage
237 17:51:34.983164 output: Image Name:
238 17:51:34.983590 output: Created: Thu Nov 7 17:51:34 2024
239 17:51:34.983815 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 17:51:34.984071 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 17:51:34.984287 output: Load Address: 01080000
242 17:51:34.984495 output: Entry Point: 01080000
243 17:51:34.984697 output:
244 17:51:34.985040 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 17:51:34.985316 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 17:51:34.985593 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 17:51:34.985858 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 17:51:34.986125 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 17:51:34.986391 Building ramdisk /var/lib/lava/dispatcher/tmp/953294/extract-overlay-ramdisk-t2tn91sk/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/953294/extract-overlay-ramdisk-t2tn91sk/ramdisk
250 17:51:37.152418 >> 166783 blocks
251 17:51:44.927844 Adding RAMdisk u-boot header.
252 17:51:44.928564 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/953294/extract-overlay-ramdisk-t2tn91sk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/953294/extract-overlay-ramdisk-t2tn91sk/ramdisk.cpio.gz.uboot
253 17:51:45.177669 output: Image Name:
254 17:51:45.178076 output: Created: Thu Nov 7 17:51:44 2024
255 17:51:45.178292 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 17:51:45.178499 output: Data Size: 23429727 Bytes = 22880.59 KiB = 22.34 MiB
257 17:51:45.178702 output: Load Address: 00000000
258 17:51:45.178900 output: Entry Point: 00000000
259 17:51:45.179099 output:
260 17:51:45.179678 rename /var/lib/lava/dispatcher/tmp/953294/extract-overlay-ramdisk-t2tn91sk/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/953294/tftp-deploy-1dgoogz1/ramdisk/ramdisk.cpio.gz.uboot
261 17:51:45.180181 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 17:51:45.180744 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 17:51:45.181271 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
264 17:51:45.181721 No LXC device requested
265 17:51:45.182218 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 17:51:45.182723 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
267 17:51:45.183211 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 17:51:45.183622 Checking files for TFTP limit of 4294967296 bytes.
269 17:51:45.186307 end: 1 tftp-deploy (duration 00:01:04) [common]
270 17:51:45.186876 start: 2 uboot-action (timeout 00:05:00) [common]
271 17:51:45.187399 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 17:51:45.187892 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 17:51:45.188429 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 17:51:45.188956 Using kernel file from prepare-kernel: 953294/tftp-deploy-1dgoogz1/kernel/uImage
275 17:51:45.189583 substitutions:
276 17:51:45.189989 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 17:51:45.190387 - {DTB_ADDR}: 0x01070000
278 17:51:45.190784 - {DTB}: 953294/tftp-deploy-1dgoogz1/dtb/meson-g12b-a311d-libretech-cc.dtb
279 17:51:45.191179 - {INITRD}: 953294/tftp-deploy-1dgoogz1/ramdisk/ramdisk.cpio.gz.uboot
280 17:51:45.191575 - {KERNEL_ADDR}: 0x01080000
281 17:51:45.191965 - {KERNEL}: 953294/tftp-deploy-1dgoogz1/kernel/uImage
282 17:51:45.192387 - {LAVA_MAC}: None
283 17:51:45.192818 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/953294/extract-nfsrootfs-vw5dnzfj
284 17:51:45.193216 - {NFS_SERVER_IP}: 192.168.6.2
285 17:51:45.193605 - {PRESEED_CONFIG}: None
286 17:51:45.193992 - {PRESEED_LOCAL}: None
287 17:51:45.194379 - {RAMDISK_ADDR}: 0x08000000
288 17:51:45.194762 - {RAMDISK}: 953294/tftp-deploy-1dgoogz1/ramdisk/ramdisk.cpio.gz.uboot
289 17:51:45.195149 - {ROOT_PART}: None
290 17:51:45.195534 - {ROOT}: None
291 17:51:45.195917 - {SERVER_IP}: 192.168.6.2
292 17:51:45.196375 - {TEE_ADDR}: 0x83000000
293 17:51:45.196765 - {TEE}: None
294 17:51:45.197151 Parsed boot commands:
295 17:51:45.197530 - setenv autoload no
296 17:51:45.197913 - setenv initrd_high 0xffffffff
297 17:51:45.198298 - setenv fdt_high 0xffffffff
298 17:51:45.198683 - dhcp
299 17:51:45.199067 - setenv serverip 192.168.6.2
300 17:51:45.199450 - tftpboot 0x01080000 953294/tftp-deploy-1dgoogz1/kernel/uImage
301 17:51:45.199837 - tftpboot 0x08000000 953294/tftp-deploy-1dgoogz1/ramdisk/ramdisk.cpio.gz.uboot
302 17:51:45.200253 - tftpboot 0x01070000 953294/tftp-deploy-1dgoogz1/dtb/meson-g12b-a311d-libretech-cc.dtb
303 17:51:45.200641 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/953294/extract-nfsrootfs-vw5dnzfj,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 17:51:45.201041 - bootm 0x01080000 0x08000000 0x01070000
305 17:51:45.201532 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 17:51:45.202997 start: 2.3 connect-device (timeout 00:05:00) [common]
308 17:51:45.203413 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 17:51:45.218471 Setting prompt string to ['lava-test: # ']
310 17:51:45.219914 end: 2.3 connect-device (duration 00:00:00) [common]
311 17:51:45.220554 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 17:51:45.221092 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 17:51:45.221605 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 17:51:45.222716 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 17:51:45.260219 >> OK - accepted request
316 17:51:45.262291 Returned 0 in 0 seconds
317 17:51:45.363149 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 17:51:45.364735 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 17:51:45.365283 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 17:51:45.365804 Setting prompt string to ['Hit any key to stop autoboot']
322 17:51:45.366266 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 17:51:45.367810 Trying 192.168.56.21...
324 17:51:45.368315 Connected to conserv1.
325 17:51:45.368732 Escape character is '^]'.
326 17:51:45.369147
327 17:51:45.369565 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 17:51:45.369979
329 17:51:56.509405 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 17:51:56.510037 bl2_stage_init 0x01
331 17:51:56.510478 bl2_stage_init 0x81
332 17:51:56.514850 hw id: 0x0000 - pwm id 0x01
333 17:51:56.515375 bl2_stage_init 0xc1
334 17:51:56.515772 bl2_stage_init 0x02
335 17:51:56.516215
336 17:51:56.520423 L0:00000000
337 17:51:56.520856 L1:20000703
338 17:51:56.521243 L2:00008067
339 17:51:56.521627 L3:14000000
340 17:51:56.523327 B2:00402000
341 17:51:56.523757 B1:e0f83180
342 17:51:56.524188
343 17:51:56.524580 TE: 58124
344 17:51:56.524967
345 17:51:56.534517 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 17:51:56.534957
347 17:51:56.535350 Board ID = 1
348 17:51:56.535735 Set A53 clk to 24M
349 17:51:56.536159 Set A73 clk to 24M
350 17:51:56.540106 Set clk81 to 24M
351 17:51:56.540523 A53 clk: 1200 MHz
352 17:51:56.540910 A73 clk: 1200 MHz
353 17:51:56.543571 CLK81: 166.6M
354 17:51:56.544013 smccc: 00012a92
355 17:51:56.549176 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 17:51:56.554720 board id: 1
357 17:51:56.560113 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 17:51:56.570412 fw parse done
359 17:51:56.576381 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 17:51:56.619013 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 17:51:56.629986 PIEI prepare done
362 17:51:56.630400 fastboot data load
363 17:51:56.630790 fastboot data verify
364 17:51:56.635583 verify result: 266
365 17:51:56.641281 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 17:51:56.641703 LPDDR4 probe
367 17:51:56.642093 ddr clk to 1584MHz
368 17:51:56.647189 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 17:51:56.686395
370 17:51:56.686807 dmc_version 0001
371 17:51:56.693067 Check phy result
372 17:51:56.698952 INFO : End of CA training
373 17:51:56.699357 INFO : End of initialization
374 17:51:56.704586 INFO : Training has run successfully!
375 17:51:56.705016 Check phy result
376 17:51:56.710203 INFO : End of initialization
377 17:51:56.710618 INFO : End of read enable training
378 17:51:56.715753 INFO : End of fine write leveling
379 17:51:56.721358 INFO : End of Write leveling coarse delay
380 17:51:56.721767 INFO : Training has run successfully!
381 17:51:56.722152 Check phy result
382 17:51:56.726969 INFO : End of initialization
383 17:51:56.727382 INFO : End of read dq deskew training
384 17:51:56.732512 INFO : End of MPR read delay center optimization
385 17:51:56.738229 INFO : End of write delay center optimization
386 17:51:56.743740 INFO : End of read delay center optimization
387 17:51:56.744181 INFO : End of max read latency training
388 17:51:56.749368 INFO : Training has run successfully!
389 17:51:56.749808 1D training succeed
390 17:51:56.758539 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 17:51:56.806107 Check phy result
392 17:51:56.806553 INFO : End of initialization
393 17:51:56.827787 INFO : End of 2D read delay Voltage center optimization
394 17:51:56.847060 INFO : End of 2D read delay Voltage center optimization
395 17:51:56.898936 INFO : End of 2D write delay Voltage center optimization
396 17:51:56.948183 INFO : End of 2D write delay Voltage center optimization
397 17:51:56.953884 INFO : Training has run successfully!
398 17:51:56.954295
399 17:51:56.954699 channel==0
400 17:51:56.959388 RxClkDly_Margin_A0==88 ps 9
401 17:51:56.959796 TxDqDly_Margin_A0==98 ps 10
402 17:51:56.964944 RxClkDly_Margin_A1==88 ps 9
403 17:51:56.965367 TxDqDly_Margin_A1==98 ps 10
404 17:51:56.965757 TrainedVREFDQ_A0==74
405 17:51:56.970535 TrainedVREFDQ_A1==74
406 17:51:56.970949 VrefDac_Margin_A0==25
407 17:51:56.971335 DeviceVref_Margin_A0==40
408 17:51:56.976240 VrefDac_Margin_A1==25
409 17:51:56.976660 DeviceVref_Margin_A1==40
410 17:51:56.977045
411 17:51:56.977428
412 17:51:56.981746 channel==1
413 17:51:56.982157 RxClkDly_Margin_A0==88 ps 9
414 17:51:56.982542 TxDqDly_Margin_A0==88 ps 9
415 17:51:56.987322 RxClkDly_Margin_A1==88 ps 9
416 17:51:56.987729 TxDqDly_Margin_A1==88 ps 9
417 17:51:56.992940 TrainedVREFDQ_A0==76
418 17:51:56.993351 TrainedVREFDQ_A1==77
419 17:51:56.993737 VrefDac_Margin_A0==23
420 17:51:56.998539 DeviceVref_Margin_A0==38
421 17:51:56.998949 VrefDac_Margin_A1==24
422 17:51:57.004193 DeviceVref_Margin_A1==37
423 17:51:57.004599
424 17:51:57.004985 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 17:51:57.005369
426 17:51:57.037740 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 17:51:57.038248 2D training succeed
428 17:51:57.043324 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 17:51:57.048924 auto size-- 65535DDR cs0 size: 2048MB
430 17:51:57.049339 DDR cs1 size: 2048MB
431 17:51:57.054529 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 17:51:57.054938 cs0 DataBus test pass
433 17:51:57.060202 cs1 DataBus test pass
434 17:51:57.060607 cs0 AddrBus test pass
435 17:51:57.060992 cs1 AddrBus test pass
436 17:51:57.061374
437 17:51:57.065707 100bdlr_step_size ps== 420
438 17:51:57.066129 result report
439 17:51:57.071307 boot times 0Enable ddr reg access
440 17:51:57.076510 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 17:51:57.089962 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 17:51:57.662104 0.0;M3 CHK:0;cm4_sp_mode 0
443 17:51:57.662647 MVN_1=0x00000000
444 17:51:57.667507 MVN_2=0x00000000
445 17:51:57.673257 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 17:51:57.673693 OPS=0x10
447 17:51:57.674100 ring efuse init
448 17:51:57.674496 chipver efuse init
449 17:51:57.678839 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 17:51:57.684432 [0.018961 Inits done]
451 17:51:57.684848 secure task start!
452 17:51:57.685248 high task start!
453 17:51:57.689031 low task start!
454 17:51:57.689451 run into bl31
455 17:51:57.695684 NOTICE: BL31: v1.3(release):4fc40b1
456 17:51:57.703503 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 17:51:57.703959 NOTICE: BL31: G12A normal boot!
458 17:51:57.728844 NOTICE: BL31: BL33 decompress pass
459 17:51:57.734521 ERROR: Error initializing runtime service opteed_fast
460 17:51:58.967577
461 17:51:58.968213
462 17:51:58.975878 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 17:51:58.976347
464 17:51:58.976750 Model: Libre Computer AML-A311D-CC Alta
465 17:51:59.184385 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 17:51:59.207672 DRAM: 2 GiB (effective 3.8 GiB)
467 17:51:59.350694 Core: 408 devices, 31 uclasses, devicetree: separate
468 17:51:59.356527 WDT: Not starting watchdog@f0d0
469 17:51:59.388805 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 17:51:59.401267 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 17:51:59.406240 ** Bad device specification mmc 0 **
472 17:51:59.416571 Card did not respond to voltage select! : -110
473 17:51:59.424210 ** Bad device specification mmc 0 **
474 17:51:59.424645 Couldn't find partition mmc 0
475 17:51:59.432553 Card did not respond to voltage select! : -110
476 17:51:59.438061 ** Bad device specification mmc 0 **
477 17:51:59.438481 Couldn't find partition mmc 0
478 17:51:59.443131 Error: could not access storage.
479 17:52:00.709747 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 17:52:00.710389 bl2_stage_init 0x01
481 17:52:00.710831 bl2_stage_init 0x81
482 17:52:00.715273 hw id: 0x0000 - pwm id 0x01
483 17:52:00.715764 bl2_stage_init 0xc1
484 17:52:00.716240 bl2_stage_init 0x02
485 17:52:00.716654
486 17:52:00.720881 L0:00000000
487 17:52:00.721352 L1:20000703
488 17:52:00.721763 L2:00008067
489 17:52:00.722166 L3:14000000
490 17:52:00.723763 B2:00402000
491 17:52:00.724247 B1:e0f83180
492 17:52:00.724654
493 17:52:00.725053 TE: 58167
494 17:52:00.725450
495 17:52:00.734937 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 17:52:00.735473
497 17:52:00.735892 Board ID = 1
498 17:52:00.736346 Set A53 clk to 24M
499 17:52:00.736752 Set A73 clk to 24M
500 17:52:00.740621 Set clk81 to 24M
501 17:52:00.741221 A53 clk: 1200 MHz
502 17:52:00.741664 A73 clk: 1200 MHz
503 17:52:00.746279 CLK81: 166.6M
504 17:52:00.746898 smccc: 00012abe
505 17:52:00.751827 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 17:52:00.752565 board id: 1
507 17:52:00.760411 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 17:52:00.771114 fw parse done
509 17:52:00.778093 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 17:52:00.819577 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 17:52:00.830538 PIEI prepare done
512 17:52:00.831056 fastboot data load
513 17:52:00.831478 fastboot data verify
514 17:52:00.836248 verify result: 266
515 17:52:00.841790 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 17:52:00.842287 LPDDR4 probe
517 17:52:00.842703 ddr clk to 1584MHz
518 17:52:00.849778 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 17:52:00.887049
520 17:52:00.887570 dmc_version 0001
521 17:52:00.893707 Check phy result
522 17:52:00.899577 INFO : End of CA training
523 17:52:00.900104 INFO : End of initialization
524 17:52:00.905183 INFO : Training has run successfully!
525 17:52:00.905678 Check phy result
526 17:52:00.910805 INFO : End of initialization
527 17:52:00.911301 INFO : End of read enable training
528 17:52:00.916403 INFO : End of fine write leveling
529 17:52:00.922010 INFO : End of Write leveling coarse delay
530 17:52:00.922518 INFO : Training has run successfully!
531 17:52:00.922935 Check phy result
532 17:52:00.927598 INFO : End of initialization
533 17:52:00.928160 INFO : End of read dq deskew training
534 17:52:00.933183 INFO : End of MPR read delay center optimization
535 17:52:00.938787 INFO : End of write delay center optimization
536 17:52:00.944363 INFO : End of read delay center optimization
537 17:52:00.944851 INFO : End of max read latency training
538 17:52:00.949998 INFO : Training has run successfully!
539 17:52:00.950495 1D training succeed
540 17:52:00.959061 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 17:52:01.006854 Check phy result
542 17:52:01.007421 INFO : End of initialization
543 17:52:01.029323 INFO : End of 2D read delay Voltage center optimization
544 17:52:01.049581 INFO : End of 2D read delay Voltage center optimization
545 17:52:01.101639 INFO : End of 2D write delay Voltage center optimization
546 17:52:01.150974 INFO : End of 2D write delay Voltage center optimization
547 17:52:01.156532 INFO : Training has run successfully!
548 17:52:01.157011
549 17:52:01.157423 channel==0
550 17:52:01.162129 RxClkDly_Margin_A0==88 ps 9
551 17:52:01.162629 TxDqDly_Margin_A0==98 ps 10
552 17:52:01.167726 RxClkDly_Margin_A1==88 ps 9
553 17:52:01.168268 TxDqDly_Margin_A1==98 ps 10
554 17:52:01.168692 TrainedVREFDQ_A0==74
555 17:52:01.173304 TrainedVREFDQ_A1==74
556 17:52:01.173800 VrefDac_Margin_A0==25
557 17:52:01.174212 DeviceVref_Margin_A0==40
558 17:52:01.178925 VrefDac_Margin_A1==25
559 17:52:01.179403 DeviceVref_Margin_A1==40
560 17:52:01.179813
561 17:52:01.180257
562 17:52:01.184554 channel==1
563 17:52:01.185031 RxClkDly_Margin_A0==98 ps 10
564 17:52:01.185444 TxDqDly_Margin_A0==88 ps 9
565 17:52:01.190092 RxClkDly_Margin_A1==88 ps 9
566 17:52:01.190570 TxDqDly_Margin_A1==88 ps 9
567 17:52:01.195765 TrainedVREFDQ_A0==76
568 17:52:01.196288 TrainedVREFDQ_A1==77
569 17:52:01.196709 VrefDac_Margin_A0==22
570 17:52:01.201358 DeviceVref_Margin_A0==38
571 17:52:01.201851 VrefDac_Margin_A1==24
572 17:52:01.206940 DeviceVref_Margin_A1==37
573 17:52:01.207440
574 17:52:01.207858 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 17:52:01.208300
576 17:52:01.240506 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000018 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
577 17:52:01.241051 2D training succeed
578 17:52:01.246149 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 17:52:01.251717 auto size-- 65535DDR cs0 size: 2048MB
580 17:52:01.252226 DDR cs1 size: 2048MB
581 17:52:01.257319 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 17:52:01.257797 cs0 DataBus test pass
583 17:52:01.262939 cs1 DataBus test pass
584 17:52:01.263413 cs0 AddrBus test pass
585 17:52:01.263826 cs1 AddrBus test pass
586 17:52:01.264268
587 17:52:01.268522 100bdlr_step_size ps== 420
588 17:52:01.269012 result report
589 17:52:01.274127 boot times 0Enable ddr reg access
590 17:52:01.279377 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 17:52:01.292845 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 17:52:01.866587 0.0;M3 CHK:0;cm4_sp_mode 0
593 17:52:01.867202 MVN_1=0x00000000
594 17:52:01.872130 MVN_2=0x00000000
595 17:52:01.877831 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 17:52:01.878347 OPS=0x10
597 17:52:01.878804 ring efuse init
598 17:52:01.879238 chipver efuse init
599 17:52:01.886078 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 17:52:01.886606 [0.018961 Inits done]
601 17:52:01.893702 secure task start!
602 17:52:01.894176 high task start!
603 17:52:01.894574 low task start!
604 17:52:01.894962 run into bl31
605 17:52:01.900364 NOTICE: BL31: v1.3(release):4fc40b1
606 17:52:01.908207 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 17:52:01.908680 NOTICE: BL31: G12A normal boot!
608 17:52:01.933521 NOTICE: BL31: BL33 decompress pass
609 17:52:01.939201 ERROR: Error initializing runtime service opteed_fast
610 17:52:03.172051
611 17:52:03.172465
612 17:52:03.180639 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 17:52:03.181047
614 17:52:03.181385 Model: Libre Computer AML-A311D-CC Alta
615 17:52:03.389037 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 17:52:03.412380 DRAM: 2 GiB (effective 3.8 GiB)
617 17:52:03.555118 Core: 408 devices, 31 uclasses, devicetree: separate
618 17:52:03.561103 WDT: Not starting watchdog@f0d0
619 17:52:03.593317 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 17:52:03.605865 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 17:52:03.610691 ** Bad device specification mmc 0 **
622 17:52:03.621406 Card did not respond to voltage select! : -110
623 17:52:03.628737 ** Bad device specification mmc 0 **
624 17:52:03.629040 Couldn't find partition mmc 0
625 17:52:03.637165 Card did not respond to voltage select! : -110
626 17:52:03.642496 ** Bad device specification mmc 0 **
627 17:52:03.642780 Couldn't find partition mmc 0
628 17:52:03.647934 Error: could not access storage.
629 17:52:03.990135 Net: eth0: ethernet@ff3f0000
630 17:52:03.990742 starting USB...
631 17:52:04.241899 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 17:52:04.242471 Starting the controller
633 17:52:04.248830 USB XHCI 1.10
634 17:52:05.960128 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 17:52:05.960760 bl2_stage_init 0x01
636 17:52:05.961003 bl2_stage_init 0x81
637 17:52:05.965608 hw id: 0x0000 - pwm id 0x01
638 17:52:05.965911 bl2_stage_init 0xc1
639 17:52:05.966129 bl2_stage_init 0x02
640 17:52:05.966339
641 17:52:05.971091 L0:00000000
642 17:52:05.971363 L1:20000703
643 17:52:05.971578 L2:00008067
644 17:52:05.971782 L3:14000000
645 17:52:05.976750 B2:00402000
646 17:52:05.977012 B1:e0f83180
647 17:52:05.977222
648 17:52:05.977425 TE: 58124
649 17:52:05.977624
650 17:52:05.982312 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 17:52:05.982577
652 17:52:05.982790 Board ID = 1
653 17:52:05.987943 Set A53 clk to 24M
654 17:52:05.988292 Set A73 clk to 24M
655 17:52:05.988529 Set clk81 to 24M
656 17:52:05.993640 A53 clk: 1200 MHz
657 17:52:05.993947 A73 clk: 1200 MHz
658 17:52:05.994164 CLK81: 166.6M
659 17:52:05.994407 smccc: 00012a92
660 17:52:05.999245 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 17:52:06.004884 board id: 1
662 17:52:06.010931 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 17:52:06.021180 fw parse done
664 17:52:06.027128 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 17:52:06.069845 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 17:52:06.080761 PIEI prepare done
667 17:52:06.081225 fastboot data load
668 17:52:06.081638 fastboot data verify
669 17:52:06.086485 verify result: 266
670 17:52:06.092060 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 17:52:06.092527 LPDDR4 probe
672 17:52:06.092941 ddr clk to 1584MHz
673 17:52:06.100060 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 17:52:06.137307
675 17:52:06.137805 dmc_version 0001
676 17:52:06.143958 Check phy result
677 17:52:06.149855 INFO : End of CA training
678 17:52:06.150320 INFO : End of initialization
679 17:52:06.155463 INFO : Training has run successfully!
680 17:52:06.155927 Check phy result
681 17:52:06.161036 INFO : End of initialization
682 17:52:06.161498 INFO : End of read enable training
683 17:52:06.166653 INFO : End of fine write leveling
684 17:52:06.172257 INFO : End of Write leveling coarse delay
685 17:52:06.172719 INFO : Training has run successfully!
686 17:52:06.173131 Check phy result
687 17:52:06.177839 INFO : End of initialization
688 17:52:06.178300 INFO : End of read dq deskew training
689 17:52:06.183433 INFO : End of MPR read delay center optimization
690 17:52:06.189020 INFO : End of write delay center optimization
691 17:52:06.194653 INFO : End of read delay center optimization
692 17:52:06.195113 INFO : End of max read latency training
693 17:52:06.200244 INFO : Training has run successfully!
694 17:52:06.200704 1D training succeed
695 17:52:06.209396 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 17:52:06.257009 Check phy result
697 17:52:06.257492 INFO : End of initialization
698 17:52:06.278720 INFO : End of 2D read delay Voltage center optimization
699 17:52:06.298949 INFO : End of 2D read delay Voltage center optimization
700 17:52:06.350980 INFO : End of 2D write delay Voltage center optimization
701 17:52:06.400379 INFO : End of 2D write delay Voltage center optimization
702 17:52:06.405909 INFO : Training has run successfully!
703 17:52:06.406375
704 17:52:06.406804 channel==0
705 17:52:06.411521 RxClkDly_Margin_A0==88 ps 9
706 17:52:06.412033 TxDqDly_Margin_A0==108 ps 11
707 17:52:06.417126 RxClkDly_Margin_A1==88 ps 9
708 17:52:06.417616 TxDqDly_Margin_A1==98 ps 10
709 17:52:06.418028 TrainedVREFDQ_A0==74
710 17:52:06.422691 TrainedVREFDQ_A1==74
711 17:52:06.423157 VrefDac_Margin_A0==25
712 17:52:06.428372 DeviceVref_Margin_A0==40
713 17:52:06.428858 VrefDac_Margin_A1==25
714 17:52:06.429268 DeviceVref_Margin_A1==40
715 17:52:06.429666
716 17:52:06.430063
717 17:52:06.433928 channel==1
718 17:52:06.434389 RxClkDly_Margin_A0==98 ps 10
719 17:52:06.434795 TxDqDly_Margin_A0==88 ps 9
720 17:52:06.439518 RxClkDly_Margin_A1==98 ps 10
721 17:52:06.440016 TxDqDly_Margin_A1==88 ps 9
722 17:52:06.445124 TrainedVREFDQ_A0==77
723 17:52:06.445589 TrainedVREFDQ_A1==77
724 17:52:06.445998 VrefDac_Margin_A0==22
725 17:52:06.450711 DeviceVref_Margin_A0==37
726 17:52:06.451175 VrefDac_Margin_A1==22
727 17:52:06.456326 DeviceVref_Margin_A1==37
728 17:52:06.456783
729 17:52:06.457192 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 17:52:06.461919
731 17:52:06.489839 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
732 17:52:06.490405 2D training succeed
733 17:52:06.495534 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 17:52:06.501119 auto size-- 65535DDR cs0 size: 2048MB
735 17:52:06.501668 DDR cs1 size: 2048MB
736 17:52:06.506631 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 17:52:06.507100 cs0 DataBus test pass
738 17:52:06.512231 cs1 DataBus test pass
739 17:52:06.512688 cs0 AddrBus test pass
740 17:52:06.513098 cs1 AddrBus test pass
741 17:52:06.513510
742 17:52:06.517829 100bdlr_step_size ps== 420
743 17:52:06.518321 result report
744 17:52:06.523437 boot times 0Enable ddr reg access
745 17:52:06.528879 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 17:52:06.542381 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 17:52:07.116149 0.0;M3 CHK:0;cm4_sp_mode 0
748 17:52:07.116778 MVN_1=0x00000000
749 17:52:07.121724 MVN_2=0x00000000
750 17:52:07.127372 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 17:52:07.127910 OPS=0x10
752 17:52:07.128356 ring efuse init
753 17:52:07.128741 chipver efuse init
754 17:52:07.132942 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 17:52:07.138545 [0.018961 Inits done]
756 17:52:07.139031 secure task start!
757 17:52:07.139420 high task start!
758 17:52:07.143110 low task start!
759 17:52:07.143587 run into bl31
760 17:52:07.149790 NOTICE: BL31: v1.3(release):4fc40b1
761 17:52:07.157592 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 17:52:07.158082 NOTICE: BL31: G12A normal boot!
763 17:52:07.182994 NOTICE: BL31: BL33 decompress pass
764 17:52:07.188737 ERROR: Error initializing runtime service opteed_fast
765 17:52:08.421528
766 17:52:08.422138
767 17:52:08.429911 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 17:52:08.430449
769 17:52:08.430895 Model: Libre Computer AML-A311D-CC Alta
770 17:52:08.638332 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 17:52:08.661650 DRAM: 2 GiB (effective 3.8 GiB)
772 17:52:08.804720 Core: 408 devices, 31 uclasses, devicetree: separate
773 17:52:08.810598 WDT: Not starting watchdog@f0d0
774 17:52:08.842918 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 17:52:08.855276 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 17:52:08.860285 ** Bad device specification mmc 0 **
777 17:52:08.870605 Card did not respond to voltage select! : -110
778 17:52:08.878247 ** Bad device specification mmc 0 **
779 17:52:08.878722 Couldn't find partition mmc 0
780 17:52:08.886608 Card did not respond to voltage select! : -110
781 17:52:08.892170 ** Bad device specification mmc 0 **
782 17:52:08.892647 Couldn't find partition mmc 0
783 17:52:08.897198 Error: could not access storage.
784 17:52:09.239731 Net: eth0: ethernet@ff3f0000
785 17:52:09.240384 starting USB...
786 17:52:09.491487 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 17:52:09.492115 Starting the controller
788 17:52:09.498366 USB XHCI 1.10
789 17:52:11.661462 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 17:52:11.662081 bl2_stage_init 0x01
791 17:52:11.662510 bl2_stage_init 0x81
792 17:52:11.667104 hw id: 0x0000 - pwm id 0x01
793 17:52:11.667578 bl2_stage_init 0xc1
794 17:52:11.668031 bl2_stage_init 0x02
795 17:52:11.668444
796 17:52:11.672670 L0:00000000
797 17:52:11.673132 L1:20000703
798 17:52:11.673537 L2:00008067
799 17:52:11.673938 L3:14000000
800 17:52:11.675616 B2:00402000
801 17:52:11.676099 B1:e0f83180
802 17:52:11.676512
803 17:52:11.676912 TE: 58167
804 17:52:11.677307
805 17:52:11.686622 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 17:52:11.687094
807 17:52:11.687502 Board ID = 1
808 17:52:11.687898 Set A53 clk to 24M
809 17:52:11.688332 Set A73 clk to 24M
810 17:52:11.692313 Set clk81 to 24M
811 17:52:11.692776 A53 clk: 1200 MHz
812 17:52:11.693178 A73 clk: 1200 MHz
813 17:52:11.697828 CLK81: 166.6M
814 17:52:11.698290 smccc: 00012abd
815 17:52:11.703540 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 17:52:11.704029 board id: 1
817 17:52:11.712205 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 17:52:11.722619 fw parse done
819 17:52:11.728590 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 17:52:11.771199 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 17:52:11.782139 PIEI prepare done
822 17:52:11.782601 fastboot data load
823 17:52:11.783019 fastboot data verify
824 17:52:11.787805 verify result: 266
825 17:52:11.793431 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 17:52:11.793897 LPDDR4 probe
827 17:52:11.794304 ddr clk to 1584MHz
828 17:52:11.801475 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 17:52:11.838630
830 17:52:11.839097 dmc_version 0001
831 17:52:11.845318 Check phy result
832 17:52:11.851187 INFO : End of CA training
833 17:52:11.851644 INFO : End of initialization
834 17:52:11.856781 INFO : Training has run successfully!
835 17:52:11.857239 Check phy result
836 17:52:11.862374 INFO : End of initialization
837 17:52:11.862831 INFO : End of read enable training
838 17:52:11.867977 INFO : End of fine write leveling
839 17:52:11.873569 INFO : End of Write leveling coarse delay
840 17:52:11.874030 INFO : Training has run successfully!
841 17:52:11.874435 Check phy result
842 17:52:11.879173 INFO : End of initialization
843 17:52:11.879625 INFO : End of read dq deskew training
844 17:52:11.884767 INFO : End of MPR read delay center optimization
845 17:52:11.890376 INFO : End of write delay center optimization
846 17:52:11.896012 INFO : End of read delay center optimization
847 17:52:11.896472 INFO : End of max read latency training
848 17:52:11.901599 INFO : Training has run successfully!
849 17:52:11.902059 1D training succeed
850 17:52:11.910741 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 17:52:11.958364 Check phy result
852 17:52:11.958840 INFO : End of initialization
853 17:52:11.980128 INFO : End of 2D read delay Voltage center optimization
854 17:52:12.000748 INFO : End of 2D read delay Voltage center optimization
855 17:52:12.052388 INFO : End of 2D write delay Voltage center optimization
856 17:52:12.101741 INFO : End of 2D write delay Voltage center optimization
857 17:52:12.107284 INFO : Training has run successfully!
858 17:52:12.107735
859 17:52:12.108197 channel==0
860 17:52:12.112897 RxClkDly_Margin_A0==88 ps 9
861 17:52:12.113356 TxDqDly_Margin_A0==98 ps 10
862 17:52:12.118498 RxClkDly_Margin_A1==88 ps 9
863 17:52:12.118944 TxDqDly_Margin_A1==98 ps 10
864 17:52:12.119365 TrainedVREFDQ_A0==74
865 17:52:12.124257 TrainedVREFDQ_A1==74
866 17:52:12.124736 VrefDac_Margin_A0==25
867 17:52:12.125143 DeviceVref_Margin_A0==40
868 17:52:12.129733 VrefDac_Margin_A1==23
869 17:52:12.130196 DeviceVref_Margin_A1==40
870 17:52:12.130579
871 17:52:12.130959
872 17:52:12.135312 channel==1
873 17:52:12.135759 RxClkDly_Margin_A0==98 ps 10
874 17:52:12.136179 TxDqDly_Margin_A0==88 ps 9
875 17:52:12.140904 RxClkDly_Margin_A1==98 ps 10
876 17:52:12.141348 TxDqDly_Margin_A1==88 ps 9
877 17:52:12.146500 TrainedVREFDQ_A0==77
878 17:52:12.146949 TrainedVREFDQ_A1==77
879 17:52:12.147335 VrefDac_Margin_A0==22
880 17:52:12.152113 DeviceVref_Margin_A0==37
881 17:52:12.152563 VrefDac_Margin_A1==22
882 17:52:12.157708 DeviceVref_Margin_A1==37
883 17:52:12.158151
884 17:52:12.158535 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 17:52:12.158914
886 17:52:12.191262 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
887 17:52:12.191775 2D training succeed
888 17:52:12.196928 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 17:52:12.202486 auto size-- 65535DDR cs0 size: 2048MB
890 17:52:12.202941 DDR cs1 size: 2048MB
891 17:52:12.208120 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 17:52:12.208573 cs0 DataBus test pass
893 17:52:12.213692 cs1 DataBus test pass
894 17:52:12.214135 cs0 AddrBus test pass
895 17:52:12.214519 cs1 AddrBus test pass
896 17:52:12.214896
897 17:52:12.219317 100bdlr_step_size ps== 420
898 17:52:12.219777 result report
899 17:52:12.224895 boot times 0Enable ddr reg access
900 17:52:12.230222 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 17:52:12.243713 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 17:52:12.817297 0.0;M3 CHK:0;cm4_sp_mode 0
903 17:52:12.817724 MVN_1=0x00000000
904 17:52:12.822780 MVN_2=0x00000000
905 17:52:12.828546 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 17:52:12.828843 OPS=0x10
907 17:52:12.829055 ring efuse init
908 17:52:12.829260 chipver efuse init
909 17:52:12.834152 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 17:52:12.839758 [0.018960 Inits done]
911 17:52:12.840174 secure task start!
912 17:52:12.840499 high task start!
913 17:52:12.844419 low task start!
914 17:52:12.844700 run into bl31
915 17:52:12.850966 NOTICE: BL31: v1.3(release):4fc40b1
916 17:52:12.858779 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 17:52:12.859074 NOTICE: BL31: G12A normal boot!
918 17:52:12.884148 NOTICE: BL31: BL33 decompress pass
919 17:52:12.889809 ERROR: Error initializing runtime service opteed_fast
920 17:52:14.122858
921 17:52:14.123473
922 17:52:14.132008 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 17:52:14.132500
924 17:52:14.132921 Model: Libre Computer AML-A311D-CC Alta
925 17:52:14.339602 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 17:52:14.362998 DRAM: 2 GiB (effective 3.8 GiB)
927 17:52:14.505904 Core: 408 devices, 31 uclasses, devicetree: separate
928 17:52:14.511804 WDT: Not starting watchdog@f0d0
929 17:52:14.544226 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 17:52:14.556609 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 17:52:14.561467 ** Bad device specification mmc 0 **
932 17:52:14.571897 Card did not respond to voltage select! : -110
933 17:52:14.579422 ** Bad device specification mmc 0 **
934 17:52:14.579882 Couldn't find partition mmc 0
935 17:52:14.587757 Card did not respond to voltage select! : -110
936 17:52:14.593283 ** Bad device specification mmc 0 **
937 17:52:14.593731 Couldn't find partition mmc 0
938 17:52:14.598342 Error: could not access storage.
939 17:52:14.941921 Net: eth0: ethernet@ff3f0000
940 17:52:14.942522 starting USB...
941 17:52:15.193872 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 17:52:15.194452 Starting the controller
943 17:52:15.200682 USB XHCI 1.10
944 17:52:17.061845 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
945 17:52:17.062479 bl2_stage_init 0x81
946 17:52:17.067374 hw id: 0x0000 - pwm id 0x01
947 17:52:17.067829 bl2_stage_init 0xc1
948 17:52:17.068293 bl2_stage_init 0x02
949 17:52:17.068703
950 17:52:17.072949 L0:00000000
951 17:52:17.073389 L1:20000703
952 17:52:17.073798 L2:00008067
953 17:52:17.074199 L3:14000000
954 17:52:17.074593 B2:00402000
955 17:52:17.075834 B1:e0f83180
956 17:52:17.076299
957 17:52:17.076706 TE: 58150
958 17:52:17.077108
959 17:52:17.086870 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
960 17:52:17.087322
961 17:52:17.087728 Board ID = 1
962 17:52:17.088172 Set A53 clk to 24M
963 17:52:17.088574 Set A73 clk to 24M
964 17:52:17.092474 Set clk81 to 24M
965 17:52:17.092907 A53 clk: 1200 MHz
966 17:52:17.093312 A73 clk: 1200 MHz
967 17:52:17.098089 CLK81: 166.6M
968 17:52:17.098525 smccc: 00012aac
969 17:52:17.103766 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
970 17:52:17.104237 board id: 1
971 17:52:17.112503 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
972 17:52:17.122896 fw parse done
973 17:52:17.128896 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
974 17:52:17.171512 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
975 17:52:17.182369 PIEI prepare done
976 17:52:17.182799 fastboot data load
977 17:52:17.183189 fastboot data verify
978 17:52:17.188094 verify result: 266
979 17:52:17.193629 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
980 17:52:17.194043 LPDDR4 probe
981 17:52:17.194426 ddr clk to 1584MHz
982 17:52:17.201636 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
983 17:52:17.238900
984 17:52:17.239329 dmc_version 0001
985 17:52:17.245659 Check phy result
986 17:52:17.251456 INFO : End of CA training
987 17:52:17.251873 INFO : End of initialization
988 17:52:17.257121 INFO : Training has run successfully!
989 17:52:17.257610 Check phy result
990 17:52:17.262677 INFO : End of initialization
991 17:52:17.263112 INFO : End of read enable training
992 17:52:17.268269 INFO : End of fine write leveling
993 17:52:17.273858 INFO : End of Write leveling coarse delay
994 17:52:17.274292 INFO : Training has run successfully!
995 17:52:17.274695 Check phy result
996 17:52:17.279511 INFO : End of initialization
997 17:52:17.279951 INFO : End of read dq deskew training
998 17:52:17.285102 INFO : End of MPR read delay center optimization
999 17:52:17.290654 INFO : End of write delay center optimization
1000 17:52:17.296328 INFO : End of read delay center optimization
1001 17:52:17.296766 INFO : End of max read latency training
1002 17:52:17.301925 INFO : Training has run successfully!
1003 17:52:17.302353 1D training succeed
1004 17:52:17.311070 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 17:52:17.358583 Check phy result
1006 17:52:17.359086 INFO : End of initialization
1007 17:52:17.380375 INFO : End of 2D read delay Voltage center optimization
1008 17:52:17.400700 INFO : End of 2D read delay Voltage center optimization
1009 17:52:17.452778 INFO : End of 2D write delay Voltage center optimization
1010 17:52:17.502046 INFO : End of 2D write delay Voltage center optimization
1011 17:52:17.507571 INFO : Training has run successfully!
1012 17:52:17.507921
1013 17:52:17.508210 channel==0
1014 17:52:17.513152 RxClkDly_Margin_A0==88 ps 9
1015 17:52:17.513498 TxDqDly_Margin_A0==98 ps 10
1016 17:52:17.518745 RxClkDly_Margin_A1==88 ps 9
1017 17:52:17.519203 TxDqDly_Margin_A1==98 ps 10
1018 17:52:17.519584 TrainedVREFDQ_A0==74
1019 17:52:17.524346 TrainedVREFDQ_A1==75
1020 17:52:17.524683 VrefDac_Margin_A0==25
1021 17:52:17.524922 DeviceVref_Margin_A0==40
1022 17:52:17.529963 VrefDac_Margin_A1==25
1023 17:52:17.530295 DeviceVref_Margin_A1==39
1024 17:52:17.530526
1025 17:52:17.530744
1026 17:52:17.535599 channel==1
1027 17:52:17.536131 RxClkDly_Margin_A0==98 ps 10
1028 17:52:17.536544 TxDqDly_Margin_A0==98 ps 10
1029 17:52:17.541172 RxClkDly_Margin_A1==98 ps 10
1030 17:52:17.541667 TxDqDly_Margin_A1==88 ps 9
1031 17:52:17.546780 TrainedVREFDQ_A0==77
1032 17:52:17.547137 TrainedVREFDQ_A1==77
1033 17:52:17.547374 VrefDac_Margin_A0==22
1034 17:52:17.552347 DeviceVref_Margin_A0==37
1035 17:52:17.552682 VrefDac_Margin_A1==22
1036 17:52:17.557951 DeviceVref_Margin_A1==37
1037 17:52:17.558419
1038 17:52:17.558809 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1039 17:52:17.563547
1040 17:52:17.591451 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
1041 17:52:17.591840 2D training succeed
1042 17:52:17.597103 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1043 17:52:17.602711 auto size-- 65535DDR cs0 size: 2048MB
1044 17:52:17.603002 DDR cs1 size: 2048MB
1045 17:52:17.608307 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1046 17:52:17.608591 cs0 DataBus test pass
1047 17:52:17.613929 cs1 DataBus test pass
1048 17:52:17.614213 cs0 AddrBus test pass
1049 17:52:17.614433 cs1 AddrBus test pass
1050 17:52:17.614645
1051 17:52:17.619486 100bdlr_step_size ps== 420
1052 17:52:17.619773 result report
1053 17:52:17.625138 boot times 0Enable ddr reg access
1054 17:52:17.630685 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1055 17:52:17.644117 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1056 17:52:18.217828 0.0;M3 CHK:0;cm4_sp_mode 0
1057 17:52:18.218409 MVN_1=0x00000000
1058 17:52:18.223314 MVN_2=0x00000000
1059 17:52:18.229055 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1060 17:52:18.229538 OPS=0x10
1061 17:52:18.229953 ring efuse init
1062 17:52:18.230352 chipver efuse init
1063 17:52:18.234656 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1064 17:52:18.240262 [0.018961 Inits done]
1065 17:52:18.240739 secure task start!
1066 17:52:18.241148 high task start!
1067 17:52:18.244861 low task start!
1068 17:52:18.245335 run into bl31
1069 17:52:18.251505 NOTICE: BL31: v1.3(release):4fc40b1
1070 17:52:18.259331 NOTICE: BL31: Built : 15:58:17, May 22 2019
1071 17:52:18.259823 NOTICE: BL31: G12A normal boot!
1072 17:52:18.284666 NOTICE: BL31: BL33 decompress pass
1073 17:52:18.290363 ERROR: Error initializing runtime service opteed_fast
1074 17:52:19.523096
1075 17:52:19.523531
1076 17:52:19.531490 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1077 17:52:19.531964
1078 17:52:19.532390 Model: Libre Computer AML-A311D-CC Alta
1079 17:52:19.740034 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1080 17:52:19.763371 DRAM: 2 GiB (effective 3.8 GiB)
1081 17:52:19.906309 Core: 408 devices, 31 uclasses, devicetree: separate
1082 17:52:19.912293 WDT: Not starting watchdog@f0d0
1083 17:52:19.944435 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1084 17:52:19.956913 Loading Environment from FAT... Card did not respond to voltage select! : -110
1085 17:52:19.961916 ** Bad device specification mmc 0 **
1086 17:52:19.972259 Card did not respond to voltage select! : -110
1087 17:52:19.979891 ** Bad device specification mmc 0 **
1088 17:52:19.980399 Couldn't find partition mmc 0
1089 17:52:19.988222 Card did not respond to voltage select! : -110
1090 17:52:19.993752 ** Bad device specification mmc 0 **
1091 17:52:19.994217 Couldn't find partition mmc 0
1092 17:52:19.998805 Error: could not access storage.
1093 17:52:20.342286 Net: eth0: ethernet@ff3f0000
1094 17:52:20.342875 starting USB...
1095 17:52:20.594132 Bus usb@ff500000: Register 3000140 NbrPorts 3
1096 17:52:20.594540 Starting the controller
1097 17:52:20.601087 USB XHCI 1.10
1098 17:52:22.155176 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1099 17:52:22.163471 scanning usb for storage devices... 0 Storage Device(s) found
1101 17:52:22.215040 Hit any key to stop autoboot: 1
1102 17:52:22.215864 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1103 17:52:22.216528 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1104 17:52:22.216999 Setting prompt string to ['=>']
1105 17:52:22.217473 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1106 17:52:22.230952 0
1107 17:52:22.231814 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1108 17:52:22.232320 Sending with 10 millisecond of delay
1110 17:52:23.366930 => setenv autoload no
1111 17:52:23.377712 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1112 17:52:23.382619 setenv autoload no
1113 17:52:23.383353 Sending with 10 millisecond of delay
1115 17:52:25.180070 => setenv initrd_high 0xffffffff
1116 17:52:25.190831 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1117 17:52:25.191661 setenv initrd_high 0xffffffff
1118 17:52:25.192412 Sending with 10 millisecond of delay
1120 17:52:26.808499 => setenv fdt_high 0xffffffff
1121 17:52:26.819268 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1122 17:52:26.820123 setenv fdt_high 0xffffffff
1123 17:52:26.820828 Sending with 10 millisecond of delay
1125 17:52:27.112584 => dhcp
1126 17:52:27.123290 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1127 17:52:27.124133 dhcp
1128 17:52:27.124566 Speed: 1000, full duplex
1129 17:52:27.124971 BOOTP broadcast 1
1130 17:52:27.131612 DHCP client bound to address 192.168.6.27 (8 ms)
1131 17:52:27.132351 Sending with 10 millisecond of delay
1133 17:52:28.808636 => setenv serverip 192.168.6.2
1134 17:52:28.819439 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1135 17:52:28.820394 setenv serverip 192.168.6.2
1136 17:52:28.821081 Sending with 10 millisecond of delay
1138 17:52:32.544380 => tftpboot 0x01080000 953294/tftp-deploy-1dgoogz1/kernel/uImage
1139 17:52:32.555183 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1140 17:52:32.556087 tftpboot 0x01080000 953294/tftp-deploy-1dgoogz1/kernel/uImage
1141 17:52:32.556561 Speed: 1000, full duplex
1142 17:52:32.556975 Using ethernet@ff3f0000 device
1143 17:52:32.558079 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1144 17:52:32.563637 Filename '953294/tftp-deploy-1dgoogz1/kernel/uImage'.
1145 17:52:32.567698 Load address: 0x1080000
1146 17:52:35.442496 Loading: *################################################## 43.6 MiB
1147 17:52:35.443172 15.2 MiB/s
1148 17:52:35.443640 done
1149 17:52:35.446925 Bytes transferred = 45713984 (2b98a40 hex)
1150 17:52:35.447767 Sending with 10 millisecond of delay
1152 17:52:40.139145 => tftpboot 0x08000000 953294/tftp-deploy-1dgoogz1/ramdisk/ramdisk.cpio.gz.uboot
1153 17:52:40.149993 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1154 17:52:40.150850 tftpboot 0x08000000 953294/tftp-deploy-1dgoogz1/ramdisk/ramdisk.cpio.gz.uboot
1155 17:52:40.151336 Speed: 1000, full duplex
1156 17:52:40.151789 Using ethernet@ff3f0000 device
1157 17:52:40.152639 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1158 17:52:40.161340 Filename '953294/tftp-deploy-1dgoogz1/ramdisk/ramdisk.cpio.gz.uboot'.
1159 17:52:40.161834 Load address: 0x8000000
1160 17:52:46.997559 Loading: *########################T ######################### UDP wrong checksum 00000005 00002159
1161 17:52:51.998171 T UDP wrong checksum 00000005 00002159
1162 17:53:02.001455 T T UDP wrong checksum 00000005 00002159
1163 17:53:22.005423 T T T T UDP wrong checksum 00000005 00002159
1164 17:53:37.008994 T T
1165 17:53:37.009401 Retry count exceeded; starting again
1167 17:53:37.012356 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1170 17:53:37.013337 end: 2.4 uboot-commands (duration 00:01:52) [common]
1172 17:53:37.014046 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1174 17:53:37.014590 end: 2 uboot-action (duration 00:01:52) [common]
1176 17:53:37.015414 Cleaning after the job
1177 17:53:37.015727 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953294/tftp-deploy-1dgoogz1/ramdisk
1178 17:53:37.016545 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953294/tftp-deploy-1dgoogz1/kernel
1179 17:53:37.031461 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953294/tftp-deploy-1dgoogz1/dtb
1180 17:53:37.032238 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953294/tftp-deploy-1dgoogz1/nfsrootfs
1181 17:53:37.231720 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953294/tftp-deploy-1dgoogz1/modules
1182 17:53:37.253078 start: 4.1 power-off (timeout 00:00:30) [common]
1183 17:53:37.253731 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1184 17:53:37.288870 >> OK - accepted request
1185 17:53:37.290995 Returned 0 in 0 seconds
1186 17:53:37.391695 end: 4.1 power-off (duration 00:00:00) [common]
1188 17:53:37.392611 start: 4.2 read-feedback (timeout 00:10:00) [common]
1189 17:53:37.393250 Listened to connection for namespace 'common' for up to 1s
1190 17:53:38.394153 Finalising connection for namespace 'common'
1191 17:53:38.394606 Disconnecting from shell: Finalise
1192 17:53:38.394888 =>
1193 17:53:38.495520 end: 4.2 read-feedback (duration 00:00:01) [common]
1194 17:53:38.495867 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/953294
1195 17:53:41.368538 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/953294
1196 17:53:41.369167 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.