Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 17:14:25.521557 lava-dispatcher, installed at version: 2024.01
2 17:14:25.522406 start: 0 validate
3 17:14:25.522904 Start time: 2024-11-07 17:14:25.522874+00:00 (UTC)
4 17:14:25.523468 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 17:14:25.524004 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 17:14:25.557467 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 17:14:25.558071 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-8-g23569c8b31492%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 17:14:25.581868 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 17:14:25.582475 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-8-g23569c8b31492%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 17:14:25.605759 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 17:14:25.606317 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 17:14:25.630778 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 17:14:25.631264 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-8-g23569c8b31492%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 17:14:25.662457 validate duration: 0.14
16 17:14:25.663377 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 17:14:25.663721 start: 1.1 download-retry (timeout 00:10:00) [common]
18 17:14:25.664007 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 17:14:25.664607 Not decompressing ramdisk as can be used compressed.
20 17:14:25.665035 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 17:14:25.665319 saving as /var/lib/lava/dispatcher/tmp/954361/tftp-deploy-bj4alk9r/ramdisk/initrd.cpio.gz
22 17:14:25.665582 total size: 4775763 (4 MB)
23 17:14:25.696464 progress 0 % (0 MB)
24 17:14:25.700274 progress 5 % (0 MB)
25 17:14:25.703448 progress 10 % (0 MB)
26 17:14:25.706563 progress 15 % (0 MB)
27 17:14:25.710182 progress 20 % (0 MB)
28 17:14:25.713251 progress 25 % (1 MB)
29 17:14:25.716474 progress 30 % (1 MB)
30 17:14:25.720010 progress 35 % (1 MB)
31 17:14:25.723314 progress 40 % (1 MB)
32 17:14:25.726353 progress 45 % (2 MB)
33 17:14:25.729570 progress 50 % (2 MB)
34 17:14:25.732946 progress 55 % (2 MB)
35 17:14:25.735953 progress 60 % (2 MB)
36 17:14:25.738875 progress 65 % (2 MB)
37 17:14:25.742153 progress 70 % (3 MB)
38 17:14:25.745032 progress 75 % (3 MB)
39 17:14:25.748144 progress 80 % (3 MB)
40 17:14:25.751205 progress 85 % (3 MB)
41 17:14:25.754483 progress 90 % (4 MB)
42 17:14:25.757354 progress 95 % (4 MB)
43 17:14:25.760338 progress 100 % (4 MB)
44 17:14:25.761018 4 MB downloaded in 0.10 s (47.73 MB/s)
45 17:14:25.761575 end: 1.1.1 http-download (duration 00:00:00) [common]
47 17:14:25.762501 end: 1.1 download-retry (duration 00:00:00) [common]
48 17:14:25.762807 start: 1.2 download-retry (timeout 00:10:00) [common]
49 17:14:25.763087 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 17:14:25.763566 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-8-g23569c8b31492/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 17:14:25.763848 saving as /var/lib/lava/dispatcher/tmp/954361/tftp-deploy-bj4alk9r/kernel/zImage
52 17:14:25.764081 total size: 11440640 (10 MB)
53 17:14:25.764302 No compression specified
54 17:14:25.789963 progress 0 % (0 MB)
55 17:14:25.796922 progress 5 % (0 MB)
56 17:14:25.803708 progress 10 % (1 MB)
57 17:14:25.810868 progress 15 % (1 MB)
58 17:14:25.817645 progress 20 % (2 MB)
59 17:14:25.825013 progress 25 % (2 MB)
60 17:14:25.832114 progress 30 % (3 MB)
61 17:14:25.839337 progress 35 % (3 MB)
62 17:14:25.846197 progress 40 % (4 MB)
63 17:14:25.853273 progress 45 % (4 MB)
64 17:14:25.860056 progress 50 % (5 MB)
65 17:14:25.867207 progress 55 % (6 MB)
66 17:14:25.873979 progress 60 % (6 MB)
67 17:14:25.880773 progress 65 % (7 MB)
68 17:14:25.887928 progress 70 % (7 MB)
69 17:14:25.894762 progress 75 % (8 MB)
70 17:14:25.901579 progress 80 % (8 MB)
71 17:14:25.908028 progress 85 % (9 MB)
72 17:14:25.914987 progress 90 % (9 MB)
73 17:14:25.921543 progress 95 % (10 MB)
74 17:14:25.928663 progress 100 % (10 MB)
75 17:14:25.929176 10 MB downloaded in 0.17 s (66.09 MB/s)
76 17:14:25.929660 end: 1.2.1 http-download (duration 00:00:00) [common]
78 17:14:25.930539 end: 1.2 download-retry (duration 00:00:00) [common]
79 17:14:25.930876 start: 1.3 download-retry (timeout 00:10:00) [common]
80 17:14:25.931190 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 17:14:25.931706 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-8-g23569c8b31492/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 17:14:25.931970 saving as /var/lib/lava/dispatcher/tmp/954361/tftp-deploy-bj4alk9r/dtb/am335x-boneblack.dtb
83 17:14:25.932186 total size: 70568 (0 MB)
84 17:14:25.932405 No compression specified
85 17:14:25.967305 progress 46 % (0 MB)
86 17:14:25.968097 progress 92 % (0 MB)
87 17:14:25.968817 progress 100 % (0 MB)
88 17:14:25.969249 0 MB downloaded in 0.04 s (1.82 MB/s)
89 17:14:25.969743 end: 1.3.1 http-download (duration 00:00:00) [common]
91 17:14:25.970626 end: 1.3 download-retry (duration 00:00:00) [common]
92 17:14:25.970906 start: 1.4 download-retry (timeout 00:10:00) [common]
93 17:14:25.971179 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 17:14:25.971678 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 17:14:25.971964 saving as /var/lib/lava/dispatcher/tmp/954361/tftp-deploy-bj4alk9r/nfsrootfs/full.rootfs.tar
96 17:14:25.972185 total size: 117747780 (112 MB)
97 17:14:25.972408 Using unxz to decompress xz
98 17:14:26.000051 progress 0 % (0 MB)
99 17:14:26.728425 progress 5 % (5 MB)
100 17:14:27.491649 progress 10 % (11 MB)
101 17:14:28.276770 progress 15 % (16 MB)
102 17:14:29.004966 progress 20 % (22 MB)
103 17:14:29.585164 progress 25 % (28 MB)
104 17:14:30.383764 progress 30 % (33 MB)
105 17:14:31.181275 progress 35 % (39 MB)
106 17:14:31.505640 progress 40 % (44 MB)
107 17:14:31.860497 progress 45 % (50 MB)
108 17:14:32.530274 progress 50 % (56 MB)
109 17:14:33.340531 progress 55 % (61 MB)
110 17:14:34.101341 progress 60 % (67 MB)
111 17:14:34.818913 progress 65 % (73 MB)
112 17:14:35.664581 progress 70 % (78 MB)
113 17:14:36.415602 progress 75 % (84 MB)
114 17:14:37.167452 progress 80 % (89 MB)
115 17:14:37.870753 progress 85 % (95 MB)
116 17:14:38.652637 progress 90 % (101 MB)
117 17:14:39.412997 progress 95 % (106 MB)
118 17:14:40.244348 progress 100 % (112 MB)
119 17:14:40.256720 112 MB downloaded in 14.28 s (7.86 MB/s)
120 17:14:40.258325 end: 1.4.1 http-download (duration 00:00:14) [common]
122 17:14:40.260844 end: 1.4 download-retry (duration 00:00:14) [common]
123 17:14:40.261564 start: 1.5 download-retry (timeout 00:09:45) [common]
124 17:14:40.262334 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 17:14:40.263662 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-8-g23569c8b31492/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 17:14:40.264495 saving as /var/lib/lava/dispatcher/tmp/954361/tftp-deploy-bj4alk9r/modules/modules.tar
127 17:14:40.265203 total size: 6608080 (6 MB)
128 17:14:40.265854 Using unxz to decompress xz
129 17:14:40.307651 progress 0 % (0 MB)
130 17:14:40.343104 progress 5 % (0 MB)
131 17:14:40.386075 progress 10 % (0 MB)
132 17:14:40.429337 progress 15 % (0 MB)
133 17:14:40.473995 progress 20 % (1 MB)
134 17:14:40.521030 progress 25 % (1 MB)
135 17:14:40.564748 progress 30 % (1 MB)
136 17:14:40.608733 progress 35 % (2 MB)
137 17:14:40.652798 progress 40 % (2 MB)
138 17:14:40.696226 progress 45 % (2 MB)
139 17:14:40.739921 progress 50 % (3 MB)
140 17:14:40.782582 progress 55 % (3 MB)
141 17:14:40.828109 progress 60 % (3 MB)
142 17:14:40.874576 progress 65 % (4 MB)
143 17:14:40.917908 progress 70 % (4 MB)
144 17:14:40.963859 progress 75 % (4 MB)
145 17:14:41.006655 progress 80 % (5 MB)
146 17:14:41.049632 progress 85 % (5 MB)
147 17:14:41.092624 progress 90 % (5 MB)
148 17:14:41.136182 progress 95 % (6 MB)
149 17:14:41.179874 progress 100 % (6 MB)
150 17:14:41.192655 6 MB downloaded in 0.93 s (6.80 MB/s)
151 17:14:41.193416 end: 1.5.1 http-download (duration 00:00:01) [common]
153 17:14:41.195311 end: 1.5 download-retry (duration 00:00:01) [common]
154 17:14:41.196031 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 17:14:41.196910 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 17:14:57.973161 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/954361/extract-nfsrootfs-91b6uxt9
157 17:14:57.973769 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 17:14:57.974089 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 17:14:57.974710 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua
160 17:14:57.975135 makedir: /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin
161 17:14:57.975458 makedir: /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/tests
162 17:14:57.975769 makedir: /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/results
163 17:14:57.976105 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-add-keys
164 17:14:57.976634 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-add-sources
165 17:14:57.977142 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-background-process-start
166 17:14:57.977639 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-background-process-stop
167 17:14:57.978212 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-common-functions
168 17:14:57.978729 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-echo-ipv4
169 17:14:57.979249 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-install-packages
170 17:14:57.979761 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-installed-packages
171 17:14:57.980247 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-os-build
172 17:14:57.980725 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-probe-channel
173 17:14:57.981200 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-probe-ip
174 17:14:57.981676 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-target-ip
175 17:14:57.982204 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-target-mac
176 17:14:57.982693 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-target-storage
177 17:14:57.983208 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-test-case
178 17:14:57.983712 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-test-event
179 17:14:57.984197 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-test-feedback
180 17:14:57.984676 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-test-raise
181 17:14:57.985150 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-test-reference
182 17:14:57.985632 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-test-runner
183 17:14:57.986160 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-test-set
184 17:14:57.986743 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-test-shell
185 17:14:57.987274 Updating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-add-keys (debian)
186 17:14:57.987843 Updating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-add-sources (debian)
187 17:14:57.988368 Updating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-install-packages (debian)
188 17:14:57.988894 Updating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-installed-packages (debian)
189 17:14:57.989401 Updating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/bin/lava-os-build (debian)
190 17:14:57.989857 Creating /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/environment
191 17:14:57.990258 LAVA metadata
192 17:14:57.990518 - LAVA_JOB_ID=954361
193 17:14:57.990734 - LAVA_DISPATCHER_IP=192.168.6.3
194 17:14:57.991101 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 17:14:57.992040 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 17:14:57.992354 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 17:14:57.992561 skipped lava-vland-overlay
198 17:14:57.992800 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 17:14:57.993055 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 17:14:57.993273 skipped lava-multinode-overlay
201 17:14:57.993516 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 17:14:57.993768 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 17:14:57.994061 Loading test definitions
204 17:14:57.994347 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 17:14:57.994589 Using /lava-954361 at stage 0
206 17:14:57.995677 uuid=954361_1.6.2.4.1 testdef=None
207 17:14:57.995982 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 17:14:57.996246 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 17:14:57.997794 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 17:14:57.998617 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 17:14:58.000595 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 17:14:58.001429 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 17:14:58.003285 runner path: /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/0/tests/0_timesync-off test_uuid 954361_1.6.2.4.1
216 17:14:58.003845 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 17:14:58.004661 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 17:14:58.004885 Using /lava-954361 at stage 0
220 17:14:58.005239 Fetching tests from https://github.com/kernelci/test-definitions.git
221 17:14:58.005532 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/0/tests/1_kselftest-dt'
222 17:15:01.984850 Running '/usr/bin/git checkout kernelci.org
223 17:15:02.436372 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 17:15:02.437799 uuid=954361_1.6.2.4.5 testdef=None
225 17:15:02.438525 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 17:15:02.440079 start: 1.6.2.4.6 test-overlay (timeout 00:09:23) [common]
228 17:15:02.445756 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 17:15:02.447665 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:23) [common]
231 17:15:02.454477 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 17:15:02.456304 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:23) [common]
234 17:15:02.463769 runner path: /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/0/tests/1_kselftest-dt test_uuid 954361_1.6.2.4.5
235 17:15:02.464321 BOARD='beaglebone-black'
236 17:15:02.464777 BRANCH='broonie-sound'
237 17:15:02.465182 SKIPFILE='/dev/null'
238 17:15:02.465573 SKIP_INSTALL='True'
239 17:15:02.465994 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-8-g23569c8b31492/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 17:15:02.466463 TST_CASENAME=''
241 17:15:02.466858 TST_CMDFILES='dt'
242 17:15:02.467960 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 17:15:02.469594 Creating lava-test-runner.conf files
245 17:15:02.470036 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/954361/lava-overlay-rl_qc8ua/lava-954361/0 for stage 0
246 17:15:02.470781 - 0_timesync-off
247 17:15:02.471243 - 1_kselftest-dt
248 17:15:02.471947 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 17:15:02.472506 start: 1.6.2.5 compress-overlay (timeout 00:09:23) [common]
250 17:15:27.515536 end: 1.6.2.5 compress-overlay (duration 00:00:25) [common]
251 17:15:27.515998 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
252 17:15:27.516264 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 17:15:27.516536 end: 1.6.2 lava-overlay (duration 00:00:30) [common]
254 17:15:27.516804 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
255 17:15:27.901942 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 17:15:27.902433 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
257 17:15:27.902724 extracting modules file /var/lib/lava/dispatcher/tmp/954361/tftp-deploy-bj4alk9r/modules/modules.tar to /var/lib/lava/dispatcher/tmp/954361/extract-nfsrootfs-91b6uxt9
258 17:15:28.863528 extracting modules file /var/lib/lava/dispatcher/tmp/954361/tftp-deploy-bj4alk9r/modules/modules.tar to /var/lib/lava/dispatcher/tmp/954361/extract-overlay-ramdisk-f7rc4wkq/ramdisk
259 17:15:29.789014 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 17:15:29.789478 start: 1.6.5 apply-overlay-tftp (timeout 00:08:56) [common]
261 17:15:29.789728 [common] Applying overlay to NFS
262 17:15:29.789971 [common] Applying overlay /var/lib/lava/dispatcher/tmp/954361/compress-overlay-wu81afzi/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/954361/extract-nfsrootfs-91b6uxt9
263 17:15:32.727126 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 17:15:32.727589 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
265 17:15:32.727866 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
266 17:15:32.728174 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 17:15:32.728431 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 17:15:32.728690 start: 1.6.7 configure-preseed-file (timeout 00:08:53) [common]
269 17:15:32.728937 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 17:15:32.729192 start: 1.6.8 compress-ramdisk (timeout 00:08:53) [common]
271 17:15:32.729417 Building ramdisk /var/lib/lava/dispatcher/tmp/954361/extract-overlay-ramdisk-f7rc4wkq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/954361/extract-overlay-ramdisk-f7rc4wkq/ramdisk
272 17:15:33.774109 >> 74888 blocks
273 17:15:38.354305 Adding RAMdisk u-boot header.
274 17:15:38.354778 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/954361/extract-overlay-ramdisk-f7rc4wkq/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/954361/extract-overlay-ramdisk-f7rc4wkq/ramdisk.cpio.gz.uboot
275 17:15:38.517870 output: Image Name:
276 17:15:38.518518 output: Created: Thu Nov 7 17:15:38 2024
277 17:15:38.518936 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 17:15:38.519341 output: Data Size: 14791323 Bytes = 14444.65 KiB = 14.11 MiB
279 17:15:38.519745 output: Load Address: 00000000
280 17:15:38.520141 output: Entry Point: 00000000
281 17:15:38.520531 output:
282 17:15:38.521616 rename /var/lib/lava/dispatcher/tmp/954361/extract-overlay-ramdisk-f7rc4wkq/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/954361/tftp-deploy-bj4alk9r/ramdisk/ramdisk.cpio.gz.uboot
283 17:15:38.522383 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 17:15:38.522946 end: 1.6 prepare-tftp-overlay (duration 00:00:57) [common]
285 17:15:38.523482 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:47) [common]
286 17:15:38.523939 No LXC device requested
287 17:15:38.524437 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 17:15:38.524950 start: 1.8 deploy-device-env (timeout 00:08:47) [common]
289 17:15:38.525442 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 17:15:38.525884 Checking files for TFTP limit of 4294967296 bytes.
291 17:15:38.528559 end: 1 tftp-deploy (duration 00:01:13) [common]
292 17:15:38.529130 start: 2 uboot-action (timeout 00:05:00) [common]
293 17:15:38.529651 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 17:15:38.530182 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 17:15:38.530684 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 17:15:38.531433 substitutions:
297 17:15:38.531849 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 17:15:38.532253 - {DTB_ADDR}: 0x88000000
299 17:15:38.532651 - {DTB}: 954361/tftp-deploy-bj4alk9r/dtb/am335x-boneblack.dtb
300 17:15:38.533043 - {INITRD}: 954361/tftp-deploy-bj4alk9r/ramdisk/ramdisk.cpio.gz.uboot
301 17:15:38.533437 - {KERNEL_ADDR}: 0x82000000
302 17:15:38.533844 - {KERNEL}: 954361/tftp-deploy-bj4alk9r/kernel/zImage
303 17:15:38.534241 - {LAVA_MAC}: None
304 17:15:38.534671 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/954361/extract-nfsrootfs-91b6uxt9
305 17:15:38.535069 - {NFS_SERVER_IP}: 192.168.6.3
306 17:15:38.535460 - {PRESEED_CONFIG}: None
307 17:15:38.535852 - {PRESEED_LOCAL}: None
308 17:15:38.536241 - {RAMDISK_ADDR}: 0x83000000
309 17:15:38.536627 - {RAMDISK}: 954361/tftp-deploy-bj4alk9r/ramdisk/ramdisk.cpio.gz.uboot
310 17:15:38.537015 - {ROOT_PART}: None
311 17:15:38.537399 - {ROOT}: None
312 17:15:38.537785 - {SERVER_IP}: 192.168.6.3
313 17:15:38.538194 - {TEE_ADDR}: 0x83000000
314 17:15:38.538579 - {TEE}: None
315 17:15:38.538961 Parsed boot commands:
316 17:15:38.539333 - setenv autoload no
317 17:15:38.539713 - setenv initrd_high 0xffffffff
318 17:15:38.540096 - setenv fdt_high 0xffffffff
319 17:15:38.540477 - dhcp
320 17:15:38.540859 - setenv serverip 192.168.6.3
321 17:15:38.541237 - tftp 0x82000000 954361/tftp-deploy-bj4alk9r/kernel/zImage
322 17:15:38.541617 - tftp 0x83000000 954361/tftp-deploy-bj4alk9r/ramdisk/ramdisk.cpio.gz.uboot
323 17:15:38.542026 - setenv initrd_size ${filesize}
324 17:15:38.542408 - tftp 0x88000000 954361/tftp-deploy-bj4alk9r/dtb/am335x-boneblack.dtb
325 17:15:38.542796 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/954361/extract-nfsrootfs-91b6uxt9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 17:15:38.543192 - bootz 0x82000000 0x83000000 0x88000000
327 17:15:38.543681 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 17:15:38.545152 start: 2.3 connect-device (timeout 00:05:00) [common]
330 17:15:38.545563 [common] connect-device Connecting to device using 'telnet conserv3 3002'
331 17:15:38.560256 Setting prompt string to ['lava-test: # ']
332 17:15:38.561766 end: 2.3 connect-device (duration 00:00:00) [common]
333 17:15:38.562408 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 17:15:38.562975 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 17:15:38.563550 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 17:15:38.564826 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
337 17:15:38.602033 >> OK - accepted request
338 17:15:38.604232 Returned 0 in 0 seconds
339 17:15:38.705107 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 17:15:38.706764 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 17:15:38.707322 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 17:15:38.707832 Setting prompt string to ['Hit any key to stop autoboot']
344 17:15:38.708299 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 17:15:38.709884 Trying 192.168.56.22...
346 17:15:38.710380 Connected to conserv3.
347 17:15:38.710804 Escape character is '^]'.
348 17:15:38.711219
349 17:15:38.711640 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 17:15:38.712059
351 17:15:47.483122
352 17:15:47.489899 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
353 17:15:47.490258 Trying to boot from MMC1
354 17:15:51.545592
355 17:15:51.552531 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
356 17:15:51.552870 Trying to boot from MMC1
357 17:15:54.238716
358 17:15:54.245561 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
359 17:15:54.245976 Trying to boot from MMC1
360 17:15:54.828762
361 17:15:54.829167
362 17:15:54.834363 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
363 17:15:54.834739
364 17:15:54.835055 CPU : AM335X-GP rev 2.0
365 17:15:54.839352 Model: TI AM335x BeagleBone Black
366 17:15:54.839599 DRAM: 512 MiB
367 17:15:54.919119 Core: 160 devices, 18 uclasses, devicetree: separate
368 17:15:54.933113 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
369 17:15:55.333906 NAND: 0 MiB
370 17:15:55.344113 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
371 17:15:55.459390 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
372 17:15:55.479742 <ethaddr> not set. Validating first E-fuse MAC
373 17:15:55.511639 Net: eth2: ethernet@4a100000, eth3: usb_ether
375 17:15:55.569910 Hit any key to stop autoboot: 2
376 17:15:55.570525 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
377 17:15:55.570952 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
378 17:15:55.571224 Setting prompt string to ['=>']
379 17:15:55.571483 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
380 17:15:55.580059 0
381 17:15:55.580662 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
382 17:15:55.580961 Sending with 10 millisecond of delay
384 17:15:56.715447 => setenv autoload no
385 17:15:56.726213 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
386 17:15:56.731108 setenv autoload no
387 17:15:56.731819 Sending with 10 millisecond of delay
389 17:15:58.528293 => setenv initrd_high 0xffffffff
390 17:15:58.539130 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
391 17:15:58.540089 setenv initrd_high 0xffffffff
392 17:15:58.540845 Sending with 10 millisecond of delay
394 17:16:00.157173 => setenv fdt_high 0xffffffff
395 17:16:00.167717 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
396 17:16:00.168234 setenv fdt_high 0xffffffff
397 17:16:00.168774 Sending with 10 millisecond of delay
399 17:16:00.460756 => dhcp
400 17:16:00.471498 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
401 17:16:00.472264 dhcp
402 17:16:00.472616 link up on port 0, speed 100, full duplex
403 17:16:00.472951 BOOTP broadcast 1
404 17:16:00.726364 BOOTP broadcast 2
405 17:16:01.228378 BOOTP broadcast 3
406 17:16:02.230249 BOOTP broadcast 4
407 17:16:02.299214 DHCP client bound to address 192.168.6.8 (1823 ms)
408 17:16:02.300032 Sending with 10 millisecond of delay
410 17:16:03.978247 => setenv serverip 192.168.6.3
411 17:16:03.989018 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
412 17:16:03.989863 setenv serverip 192.168.6.3
413 17:16:03.990593 Sending with 10 millisecond of delay
415 17:16:07.473259 => tftp 0x82000000 954361/tftp-deploy-bj4alk9r/kernel/zImage
416 17:16:07.484119 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:31)
417 17:16:07.485082 tftp 0x82000000 954361/tftp-deploy-bj4alk9r/kernel/zImage
418 17:16:07.485517 link up on port 0, speed 100, full duplex
419 17:16:07.489024 Using ethernet@4a100000 device
420 17:16:07.495392 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
421 17:16:07.495839 Filename '954361/tftp-deploy-bj4alk9r/kernel/zImage'.
422 17:16:07.501602 Load address: 0x82000000
423 17:16:09.555843 Loading: *################################################## 10.9 MiB
424 17:16:09.556516 5.3 MiB/s
425 17:16:09.556994 done
426 17:16:09.560119 Bytes transferred = 11440640 (ae9200 hex)
427 17:16:09.560968 Sending with 10 millisecond of delay
429 17:16:14.010725 => tftp 0x83000000 954361/tftp-deploy-bj4alk9r/ramdisk/ramdisk.cpio.gz.uboot
430 17:16:14.022072 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
431 17:16:14.023030 tftp 0x83000000 954361/tftp-deploy-bj4alk9r/ramdisk/ramdisk.cpio.gz.uboot
432 17:16:14.023516 link up on port 0, speed 100, full duplex
433 17:16:14.026974 Using ethernet@4a100000 device
434 17:16:14.032524 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
435 17:16:14.040664 Filename '954361/tftp-deploy-bj4alk9r/ramdisk/ramdisk.cpio.gz.uboot'.
436 17:16:14.041219 Load address: 0x83000000
437 17:16:16.696938 Loading: *################################################## 14.1 MiB
438 17:16:16.697622 5.3 MiB/s
439 17:16:16.698202 done
440 17:16:16.700768 Bytes transferred = 14791387 (e1b2db hex)
441 17:16:16.701882 Sending with 10 millisecond of delay
443 17:16:18.560169 => setenv initrd_size ${filesize}
444 17:16:18.570943 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
445 17:16:18.571445 setenv initrd_size ${filesize}
446 17:16:18.571925 Sending with 10 millisecond of delay
448 17:16:22.718570 => tftp 0x88000000 954361/tftp-deploy-bj4alk9r/dtb/am335x-boneblack.dtb
449 17:16:22.729359 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
450 17:16:22.730254 tftp 0x88000000 954361/tftp-deploy-bj4alk9r/dtb/am335x-boneblack.dtb
451 17:16:22.730682 link up on port 0, speed 100, full duplex
452 17:16:22.734619 Using ethernet@4a100000 device
453 17:16:22.739946 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
454 17:16:22.743331 Filename '954361/tftp-deploy-bj4alk9r/dtb/am335x-boneblack.dtb'.
455 17:16:22.757971 Load address: 0x88000000
456 17:16:22.763810 Loading: *################################################## 68.9 KiB
457 17:16:22.764303 4.5 MiB/s
458 17:16:22.764708 done
459 17:16:22.769886 Bytes transferred = 70568 (113a8 hex)
460 17:16:22.770576 Sending with 10 millisecond of delay
462 17:16:35.953975 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/954361/extract-nfsrootfs-91b6uxt9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
463 17:16:35.964735 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
464 17:16:35.965596 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/954361/extract-nfsrootfs-91b6uxt9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
465 17:16:35.966358 Sending with 10 millisecond of delay
467 17:16:38.306001 => bootz 0x82000000 0x83000000 0x88000000
468 17:16:38.316819 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
469 17:16:38.317464 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
470 17:16:38.318549 bootz 0x82000000 0x83000000 0x88000000
471 17:16:38.319038 Kernel image @ 0x82000000 [ 0x000000 - 0xae9200 ]
472 17:16:38.319554 ## Loading init Ramdisk from Legacy Image at 83000000 ...
473 17:16:38.324377 Image Name:
474 17:16:38.324890 Created: 2024-11-07 17:15:38 UTC
475 17:16:38.329974 Image Type: ARM Linux RAMDisk Image (uncompressed)
476 17:16:38.335468 Data Size: 14791323 Bytes = 14.1 MiB
477 17:16:38.335970 Load Address: 00000000
478 17:16:38.341273 Entry Point: 00000000
479 17:16:38.510360 Verifying Checksum ... OK
480 17:16:38.510963 ## Flattened Device Tree blob at 88000000
481 17:16:38.516681 Booting using the fdt blob at 0x88000000
482 17:16:38.517201 Working FDT set to 88000000
483 17:16:38.522315 Using Device Tree in place at 88000000, end 880143a7
484 17:16:38.526245 Working FDT set to 88000000
485 17:16:38.540209
486 17:16:38.540762 Starting kernel ...
487 17:16:38.541183
488 17:16:38.542080 end: 2.4.3 bootloader-commands (duration 00:00:43) [common]
489 17:16:38.542667 start: 2.4.4 auto-login-action (timeout 00:04:00) [common]
490 17:16:38.543121 Setting prompt string to ['Linux version [0-9]']
491 17:16:38.543570 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
492 17:16:38.544039 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
493 17:16:39.383166 [ 0.000000] Booting Linux on physical CPU 0x0
494 17:16:39.389142 start: 2.4.4.1 login-action (timeout 00:03:59) [common]
495 17:16:39.389663 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
496 17:16:39.390163 Setting prompt string to []
497 17:16:39.390650 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
498 17:16:39.391109 Using line separator: #'\n'#
499 17:16:39.391513 No login prompt set.
500 17:16:39.391929 Parsing kernel messages
501 17:16:39.392317 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
502 17:16:39.393079 [login-action] Waiting for messages, (timeout 00:03:59)
503 17:16:39.393497 Waiting using forced prompt support (timeout 00:02:00)
504 17:16:39.405995 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j366958-arm-gcc-12-multi-v7-defconfig-46j22) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Thu Nov 7 16:46:23 UTC 2024
505 17:16:39.411738 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
506 17:16:39.417471 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
507 17:16:39.428739 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
508 17:16:39.434536 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
509 17:16:39.440250 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
510 17:16:39.440548 [ 0.000000] Memory policy: Data cache writeback
511 17:16:39.446929 [ 0.000000] efi: UEFI not found.
512 17:16:39.452405 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
513 17:16:39.458076 [ 0.000000] Zone ranges:
514 17:16:39.463796 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
515 17:16:39.469507 [ 0.000000] Normal empty
516 17:16:39.469898 [ 0.000000] HighMem empty
517 17:16:39.472606 [ 0.000000] Movable zone start for each node
518 17:16:39.478362 [ 0.000000] Early memory node ranges
519 17:16:39.484027 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
520 17:16:39.491713 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
521 17:16:39.517480 [ 0.000000] CPU: All CPU(s) started in SVC mode.
522 17:16:39.523043 [ 0.000000] AM335X ES2.0 (sgx neon)
523 17:16:39.534721 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
524 17:16:39.552372 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/954361/extract-nfsrootfs-91b6uxt9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
525 17:16:39.564049 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
526 17:16:39.569715 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
527 17:16:39.575470 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
528 17:16:39.584546 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
529 17:16:39.614645 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
530 17:16:39.620677 <6>[ 0.000000] trace event string verifier disabled
531 17:16:39.621190 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
532 17:16:39.628648 <6>[ 0.000000] rcu: RCU event tracing is enabled.
533 17:16:39.634406 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
534 17:16:39.645769 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
535 17:16:39.650722 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
536 17:16:39.665712 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
537 17:16:39.682766 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
538 17:16:39.689450 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
539 17:16:39.781306 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
540 17:16:39.789917 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
541 17:16:39.802299 <6>[ 0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
542 17:16:39.810522 <6>[ 0.019144] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
543 17:16:39.819889 <6>[ 0.033936] Console: colour dummy device 80x30
544 17:16:39.826070 Matched prompt #6: WARNING:
545 17:16:39.826655 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
546 17:16:39.831448 <3>[ 0.038836] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
547 17:16:39.837119 <3>[ 0.045904] This ensures that you still see kernel messages. Please
548 17:16:39.840399 <3>[ 0.052632] update your kernel commandline.
549 17:16:39.881009 <6>[ 0.057241] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
550 17:16:39.886855 <6>[ 0.096152] CPU: Testing write buffer coherency: ok
551 17:16:39.892783 <6>[ 0.101518] CPU0: Spectre v2: using BPIALL workaround
552 17:16:39.893316 <6>[ 0.106984] pid_max: default: 32768 minimum: 301
553 17:16:39.904168 <6>[ 0.112177] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
554 17:16:39.911182 <6>[ 0.119999] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
555 17:16:39.918296 <6>[ 0.129355] CPU0: thread -1, cpu 0, socket -1, mpidr 0
556 17:16:39.926792 <6>[ 0.136367] Setting up static identity map for 0x80300000 - 0x803000ac
557 17:16:39.932536 <6>[ 0.146005] rcu: Hierarchical SRCU implementation.
558 17:16:39.939183 <6>[ 0.151289] rcu: Max phase no-delay instances is 1000.
559 17:16:39.948638 <6>[ 0.162401] EFI services will not be available.
560 17:16:39.954457 <6>[ 0.167683] smp: Bringing up secondary CPUs ...
561 17:16:39.960232 <6>[ 0.172730] smp: Brought up 1 node, 1 CPU
562 17:16:39.965987 <6>[ 0.177130] SMP: Total of 1 processors activated (996.14 BogoMIPS).
563 17:16:39.971849 <6>[ 0.183897] CPU: All CPU(s) started in SVC mode.
564 17:16:39.992231 <6>[ 0.189074] Memory: 405996K/522240K available (16384K kernel code, 2542K rwdata, 6784K rodata, 2048K init, 431K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
565 17:16:39.992832 <6>[ 0.205360] devtmpfs: initialized
566 17:16:40.014482 <6>[ 0.222403] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
567 17:16:40.023651 <6>[ 0.230986] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
568 17:16:40.030989 <6>[ 0.241441] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
569 17:16:40.042674 <6>[ 0.253790] pinctrl core: initialized pinctrl subsystem
570 17:16:40.051911 <6>[ 0.264396] DMI not present or invalid.
571 17:16:40.060226 <6>[ 0.270249] NET: Registered PF_NETLINK/PF_ROUTE protocol family
572 17:16:40.069600 <6>[ 0.279128] DMA: preallocated 256 KiB pool for atomic coherent allocations
573 17:16:40.084807 <6>[ 0.290658] thermal_sys: Registered thermal governor 'step_wise'
574 17:16:40.085168 <6>[ 0.290819] cpuidle: using governor menu
575 17:16:40.112191 <6>[ 0.326369] No ATAGs?
576 17:16:40.117439 <6>[ 0.329013] hw-breakpoint: debug architecture 0x4 unsupported.
577 17:16:40.128715 <6>[ 0.341061] Serial: AMBA PL011 UART driver
578 17:16:40.161351 <6>[ 0.375246] iommu: Default domain type: Translated
579 17:16:40.170429 <6>[ 0.380591] iommu: DMA domain TLB invalidation policy: strict mode
580 17:16:40.197369 <5>[ 0.410638] SCSI subsystem initialized
581 17:16:40.203207 <6>[ 0.415527] usbcore: registered new interface driver usbfs
582 17:16:40.208822 <6>[ 0.421582] usbcore: registered new interface driver hub
583 17:16:40.217416 <6>[ 0.427364] usbcore: registered new device driver usb
584 17:16:40.223200 <6>[ 0.433879] pps_core: LinuxPPS API ver. 1 registered
585 17:16:40.228859 <6>[ 0.439263] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
586 17:16:40.234847 <6>[ 0.448996] PTP clock support registered
587 17:16:40.239976 <6>[ 0.453457] EDAC MC: Ver: 3.0.0
588 17:16:40.288970 <6>[ 0.500384] scmi_core: SCMI protocol bus registered
589 17:16:40.302966 <6>[ 0.517727] vgaarb: loaded
590 17:16:40.316468 <6>[ 0.530746] clocksource: Switched to clocksource dmtimer
591 17:16:40.353259 <6>[ 0.566877] NET: Registered PF_INET protocol family
592 17:16:40.365627 <6>[ 0.572566] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
593 17:16:40.371463 <6>[ 0.581365] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
594 17:16:40.382907 <6>[ 0.590295] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
595 17:16:40.388778 <6>[ 0.598558] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
596 17:16:40.400530 <6>[ 0.606842] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
597 17:16:40.406168 <6>[ 0.614567] TCP: Hash tables configured (established 4096 bind 4096)
598 17:16:40.411866 <6>[ 0.621473] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
599 17:16:40.417766 <6>[ 0.628513] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
600 17:16:40.425315 <6>[ 0.636121] NET: Registered PF_UNIX/PF_LOCAL protocol family
601 17:16:40.502141 <6>[ 0.710608] RPC: Registered named UNIX socket transport module.
602 17:16:40.502557 <6>[ 0.717045] RPC: Registered udp transport module.
603 17:16:40.507887 <6>[ 0.722175] RPC: Registered tcp transport module.
604 17:16:40.516483 <6>[ 0.727281] RPC: Registered tcp-with-tls transport module.
605 17:16:40.522519 <6>[ 0.733205] RPC: Registered tcp NFSv4.1 backchannel transport module.
606 17:16:40.529469 <6>[ 0.740113] PCI: CLS 0 bytes, default 64
607 17:16:40.531811 <5>[ 0.745898] Initialise system trusted keyrings
608 17:16:40.554785 <6>[ 0.765964] Trying to unpack rootfs image as initramfs...
609 17:16:40.633988 <6>[ 0.841840] workingset: timestamp_bits=30 max_order=17 bucket_order=0
610 17:16:40.638702 <6>[ 0.849357] squashfs: version 4.0 (2009/01/31) Phillip Lougher
611 17:16:40.678703 <5>[ 0.892706] NFS: Registering the id_resolver key type
612 17:16:40.684659 <5>[ 0.898331] Key type id_resolver registered
613 17:16:40.690351 <5>[ 0.903025] Key type id_legacy registered
614 17:16:40.696143 <6>[ 0.907464] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
615 17:16:40.705665 <6>[ 0.914667] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
616 17:16:40.778192 <5>[ 0.992276] Key type asymmetric registered
617 17:16:40.784053 <5>[ 0.996802] Asymmetric key parser 'x509' registered
618 17:16:40.795636 <6>[ 1.002282] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
619 17:16:40.796212 <6>[ 1.010171] io scheduler mq-deadline registered
620 17:16:40.801440 <6>[ 1.015150] io scheduler kyber registered
621 17:16:40.806986 <6>[ 1.019603] io scheduler bfq registered
622 17:16:40.907098 <6>[ 1.117469] ledtrig-cpu: registered to indicate activity on CPUs
623 17:16:41.184725 <6>[ 1.394933] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
624 17:16:41.222076 <6>[ 1.435962] msm_serial: driver initialized
625 17:16:41.228107 <6>[ 1.440740] SuperH (H)SCI(F) driver initialized
626 17:16:41.234062 <6>[ 1.446078] STMicroelectronics ASC driver initialized
627 17:16:41.239262 <6>[ 1.451760] STM32 USART driver initialized
628 17:16:41.362124 <6>[ 1.575428] brd: module loaded
629 17:16:41.395283 <6>[ 1.608683] loop: module loaded
630 17:16:41.435918 <6>[ 1.648971] CAN device driver interface
631 17:16:41.442333 <6>[ 1.654224] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
632 17:16:41.448169 <6>[ 1.661140] e1000e: Intel(R) PRO/1000 Network Driver
633 17:16:41.453972 <6>[ 1.666608] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
634 17:16:41.459690 <6>[ 1.673066] igb: Intel(R) Gigabit Ethernet Network Driver
635 17:16:41.468006 <6>[ 1.678889] igb: Copyright (c) 2007-2014 Intel Corporation.
636 17:16:41.479688 <6>[ 1.688085] pegasus: Pegasus/Pegasus II USB Ethernet driver
637 17:16:41.485573 <6>[ 1.694237] usbcore: registered new interface driver pegasus
638 17:16:41.491348 <6>[ 1.700365] usbcore: registered new interface driver asix
639 17:16:41.497177 <6>[ 1.706248] usbcore: registered new interface driver ax88179_178a
640 17:16:41.502901 <6>[ 1.712833] usbcore: registered new interface driver cdc_ether
641 17:16:41.508691 <6>[ 1.719128] usbcore: registered new interface driver smsc75xx
642 17:16:41.514453 <6>[ 1.725367] usbcore: registered new interface driver smsc95xx
643 17:16:41.520226 <6>[ 1.731598] usbcore: registered new interface driver net1080
644 17:16:41.526061 <6>[ 1.737724] usbcore: registered new interface driver cdc_subset
645 17:16:41.531781 <6>[ 1.744134] usbcore: registered new interface driver zaurus
646 17:16:41.538598 <6>[ 1.750183] usbcore: registered new interface driver cdc_ncm
647 17:16:41.549160 <6>[ 1.759562] usbcore: registered new interface driver usb-storage
648 17:16:41.833974 <6>[ 2.043666] i2c_dev: i2c /dev entries driver
649 17:16:41.895113 <5>[ 2.101439] cpuidle: enable-method property 'ti,am3352' found operations
650 17:16:41.900978 <6>[ 2.110989] sdhci: Secure Digital Host Controller Interface driver
651 17:16:41.908460 <6>[ 2.117777] sdhci: Copyright(c) Pierre Ossman
652 17:16:41.915811 <6>[ 2.124282] Synopsys Designware Multimedia Card Interface Driver
653 17:16:41.921221 <6>[ 2.132262] sdhci-pltfm: SDHCI platform and OF driver helper
654 17:16:42.046259 <6>[ 2.253103] usbcore: registered new interface driver usbhid
655 17:16:42.046668 <6>[ 2.259144] usbhid: USB HID core driver
656 17:16:42.086569 <6>[ 2.298211] NET: Registered PF_INET6 protocol family
657 17:16:42.118369 <6>[ 2.332655] Segment Routing with IPv6
658 17:16:42.124130 <6>[ 2.336799] In-situ OAM (IOAM) with IPv6
659 17:16:42.130922 <6>[ 2.341202] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
660 17:16:42.138434 <6>[ 2.348564] NET: Registered PF_PACKET protocol family
661 17:16:42.144269 <6>[ 2.354124] can: controller area network core
662 17:16:42.144588 <6>[ 2.358954] NET: Registered PF_CAN protocol family
663 17:16:42.150145 <6>[ 2.364185] can: raw protocol
664 17:16:42.155975 <6>[ 2.367514] can: broadcast manager protocol
665 17:16:42.162816 <6>[ 2.372120] can: netlink gateway - max_hops=1
666 17:16:42.163132 <5>[ 2.377607] Key type dns_resolver registered
667 17:16:42.168544 <6>[ 2.382688] ThumbEE CPU extension supported.
668 17:16:42.174786 <5>[ 2.387374] Registering SWP/SWPB emulation handler
669 17:16:42.182846 <3>[ 2.393069] omap_voltage_late_init: Voltage driver support not added
670 17:16:42.380522 <5>[ 2.592308] Loading compiled-in X.509 certificates
671 17:16:42.519783 <6>[ 2.721015] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
672 17:16:42.527157 <6>[ 2.737681] pinctrl-single 44e10800.pinmux: 142 pins, size 568
673 17:16:42.553303 <3>[ 2.761413] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
674 17:16:42.752744 <3>[ 2.960830] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
675 17:16:42.952486 <6>[ 3.164862] OMAP GPIO hardware version 0.1
676 17:16:42.973229 <6>[ 3.183710] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
677 17:16:43.054061 <4>[ 3.264213] at24 2-0054: supply vcc not found, using dummy regulator
678 17:16:43.087368 <4>[ 3.297573] at24 2-0055: supply vcc not found, using dummy regulator
679 17:16:43.409010 <4>[ 3.350525] at24 2-0056: supply vcc not found, using dummy regulator
680 17:16:43.409781 <4>[ 3.388996] at24 2-0057: supply vcc not found, using dummy regulator
681 17:16:43.410231 <6>[ 3.426962] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
682 17:16:43.410580 <3>[ 3.494493] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
683 17:16:43.410924 <6>[ 3.515510] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
684 17:16:43.411257 <4>[ 3.542136] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
685 17:16:43.412737 <4>[ 3.550956] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
686 17:16:43.482375 <6>[ 3.693776] omap_rng 48310000.rng: Random Number Generator ver. 20
687 17:16:43.506754 <5>[ 3.720066] random: crng init done
688 17:16:43.565081 <6>[ 3.779184] Freeing initrd memory: 14448K
689 17:16:43.574949 <6>[ 3.783882] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
690 17:16:43.626593 <6>[ 3.834009] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
691 17:16:43.631845 <6>[ 3.844327] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
692 17:16:43.643585 <6>[ 3.851661] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
693 17:16:43.649383 <6>[ 3.859120] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
694 17:16:43.660930 <6>[ 3.867248] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
695 17:16:43.668221 <6>[ 3.878889] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
696 17:16:43.681389 <5>[ 3.887897] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
697 17:16:43.709164 <3>[ 3.917674] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
698 17:16:43.714954 <6>[ 3.926259] edma 49000000.dma: TI EDMA DMA engine driver
699 17:16:43.786160 <3>[ 3.993818] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
700 17:16:43.800876 <6>[ 4.008156] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
701 17:16:43.813707 <3>[ 4.025296] l3-aon-clkctrl:0000:0: failed to disable
702 17:16:43.866803 <6>[ 4.075261] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
703 17:16:43.872460 <6>[ 4.084767] printk: legacy console [ttyS0] enabled
704 17:16:43.878174 <6>[ 4.084767] printk: legacy console [ttyS0] enabled
705 17:16:43.883849 <6>[ 4.095104] printk: legacy bootconsole [omap8250] disabled
706 17:16:43.888984 <6>[ 4.095104] printk: legacy bootconsole [omap8250] disabled
707 17:16:43.924930 <4>[ 4.132378] tps65217-pmic: Failed to locate of_node [id: -1]
708 17:16:43.928534 <4>[ 4.139769] tps65217-bl: Failed to locate of_node [id: -1]
709 17:16:43.944847 <6>[ 4.159356] tps65217 0-0024: TPS65217 ID 0xe version 1.2
710 17:16:43.963336 <6>[ 4.166316] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
711 17:16:43.975080 <6>[ 4.180001] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
712 17:16:43.980771 <6>[ 4.191874] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
713 17:16:44.003139 <6>[ 4.211891] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
714 17:16:44.008911 <6>[ 4.220948] sdhci-omap 48060000.mmc: Got CD GPIO
715 17:16:44.017010 <4>[ 4.226141] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
716 17:16:44.031670 <4>[ 4.239686] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
717 17:16:44.038091 <4>[ 4.248465] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
718 17:16:44.047883 <4>[ 4.257061] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
719 17:16:44.121359 <6>[ 4.331045] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
720 17:16:44.157725 <6>[ 4.366557] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
721 17:16:44.180794 <6>[ 4.388719] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
722 17:16:44.187589 <6>[ 4.397655] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
723 17:16:44.244474 <6>[ 4.448503] mmc1: new high speed MMC card at address 0001
724 17:16:44.244816 <6>[ 4.455810] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
725 17:16:44.252416 <6>[ 4.464969] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
726 17:16:44.261210 <6>[ 4.472950] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
727 17:16:44.273620 <6>[ 4.481266] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
728 17:16:44.281743 <6>[ 4.488916] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
729 17:16:44.307198 <6>[ 4.512551] mmc0: new high speed SDHC card at address aaaa
730 17:16:44.307526 <6>[ 4.519441] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
731 17:16:44.337476 <6>[ 4.549645] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
732 17:16:46.394301 <6>[ 6.602642] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
733 17:16:46.567691 <5>[ 6.641586] Sending DHCP requests ., OK
734 17:16:46.578924 <6>[ 6.786030] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.8
735 17:16:46.579301 <6>[ 6.794107] IP-Config: Complete:
736 17:16:46.590100 <6>[ 6.797646] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.6.8, mask=255.255.255.0, gw=192.168.6.1
737 17:16:46.595785 <6>[ 6.808075] host=192.168.6.8, domain=, nis-domain=(none)
738 17:16:46.601428 <6>[ 6.814200] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
739 17:16:46.608150 <6>[ 6.814233] nameserver0=10.255.253.1
740 17:16:46.614115 <6>[ 6.826795] clk: Disabling unused clocks
741 17:16:46.619610 <6>[ 6.831395] PM: genpd: Disabling unused power domains
742 17:16:46.638732 <6>[ 6.849511] Freeing unused kernel image (initmem) memory: 2048K
743 17:16:46.646403 <6>[ 6.859519] Run /init as init process
744 17:16:46.671913 Loading, please wait...
745 17:16:46.747506 Starting systemd-udevd version 252.22-1~deb12u1
746 17:16:49.756118 <4>[ 9.963302] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
747 17:16:49.983718 <4>[ 10.189739] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
748 17:16:50.132101 <6>[ 10.346691] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
749 17:16:50.142951 <6>[ 10.352498] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
750 17:16:50.340252 <6>[ 10.553940] hub 1-0:1.0: USB hub found
751 17:16:50.346029 <6>[ 10.558883] tda998x 0-0070: found TDA19988
752 17:16:50.408266 <6>[ 10.621279] hub 1-0:1.0: 1 port detected
753 17:16:53.563955 Begin: Loading essential drivers ... done.
754 17:16:53.569399 Begin: Running /scripts/init-premount ... done.
755 17:16:53.574898 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
756 17:16:53.588756 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
757 17:16:53.589167 Device /sys/class/net/eth0 found
758 17:16:53.589402 done.
759 17:16:53.656325 Begin: Waiting up to 180 secs for any network device to become available ... done.
760 17:16:53.740767 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
761 17:16:53.864151 IP-Config: eth0 guessed broadcast address 192.168.6.255
762 17:16:53.865519 IP-Config: eth0 complete (dhcp from 192.168.6.1):
763 17:16:53.870294 address: 192.168.6.8 broadcast: 192.168.6.255 netmask: 255.255.255.0
764 17:16:53.881456 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
765 17:16:53.882072 rootserver: 192.168.6.1 rootpath:
766 17:16:53.884847 filename :
767 17:16:53.942434 done.
768 17:16:53.956409 Begin: Running /scripts/nfs-bottom ... done.
769 17:16:54.031328 Begin: Running /scripts/init-bottom ... done.
770 17:16:55.445396 <30>[ 15.656457] systemd[1]: System time before build time, advancing clock.
771 17:16:55.643977 <30>[ 15.829089] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
772 17:16:55.653976 <30>[ 15.866250] systemd[1]: Detected architecture arm.
773 17:16:55.666550
774 17:16:55.666895 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
775 17:16:55.667118
776 17:16:55.689051 <30>[ 15.901008] systemd[1]: Hostname set to <debian-bookworm-armhf>.
777 17:16:57.888212 <30>[ 18.097928] systemd[1]: Queued start job for default target graphical.target.
778 17:16:57.905378 <30>[ 18.112980] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
779 17:16:57.912898 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
780 17:16:57.936521 <30>[ 18.144626] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
781 17:16:57.944020 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
782 17:16:57.967114 <30>[ 18.174991] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
783 17:16:57.975373 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
784 17:16:57.995770 <30>[ 18.203564] systemd[1]: Created slice user.slice - User and Session Slice.
785 17:16:58.002557 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
786 17:16:58.031564 <30>[ 18.232988] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
787 17:16:58.037498 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
788 17:16:58.066148 <30>[ 18.273655] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
789 17:16:58.077165 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
790 17:16:58.115129 <30>[ 18.312529] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
791 17:16:58.121521 <30>[ 18.332940] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
792 17:16:58.130062 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
793 17:16:58.153708 <30>[ 18.362044] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
794 17:16:58.161843 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
795 17:16:58.184132 <30>[ 18.392341] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
796 17:16:58.192664 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
797 17:16:58.214254 <30>[ 18.422574] systemd[1]: Reached target paths.target - Path Units.
798 17:16:58.219229 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
799 17:16:58.246785 <30>[ 18.453295] systemd[1]: Reached target remote-fs.target - Remote File Systems.
800 17:16:58.253021 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
801 17:16:58.273579 <30>[ 18.482105] systemd[1]: Reached target slices.target - Slice Units.
802 17:16:58.279031 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
803 17:16:58.303769 <30>[ 18.512318] systemd[1]: Reached target swap.target - Swaps.
804 17:16:58.307769 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
805 17:16:58.334147 <30>[ 18.542408] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
806 17:16:58.343081 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
807 17:16:58.365198 <30>[ 18.573242] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
808 17:16:58.373361 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
809 17:16:58.454776 <30>[ 18.658149] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
810 17:16:58.467339 <30>[ 18.675478] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
811 17:16:58.475272 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
812 17:16:58.505675 <30>[ 18.713304] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
813 17:16:58.512947 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
814 17:16:58.537393 <30>[ 18.745205] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
815 17:16:58.545543 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
816 17:16:58.568815 <30>[ 18.776833] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
817 17:16:58.574450 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
818 17:16:58.607894 <30>[ 18.815029] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
819 17:16:58.615545 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
820 17:16:58.640913 <30>[ 18.843234] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
821 17:16:58.657475 <30>[ 18.859716] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
822 17:16:58.703853 <30>[ 18.912176] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
823 17:16:58.710770 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
824 17:16:58.750637 <30>[ 18.959697] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
825 17:16:58.778765 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
826 17:16:58.846435 <30>[ 19.054345] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
827 17:16:58.871400 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
828 17:16:58.891405 <30>[ 19.100669] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
829 17:16:58.931430 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
830 17:16:58.985359 <30>[ 19.194389] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
831 17:16:59.003709 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
832 17:16:59.042762 <30>[ 19.253084] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
833 17:16:59.071864 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
834 17:16:59.113976 <30>[ 19.322876] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
835 17:16:59.132539 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
836 17:16:59.165709 <30>[ 19.375144] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
837 17:16:59.194315 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
838 17:16:59.244067 <30>[ 19.452662] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
839 17:16:59.251578 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
840 17:16:59.282605 <28>[ 19.485936] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
841 17:16:59.302354 <28>[ 19.510584] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
842 17:16:59.355349 <30>[ 19.562899] systemd[1]: Starting systemd-journald.service - Journal Service...
843 17:16:59.361176 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
844 17:16:59.403990 <30>[ 19.613054] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
845 17:16:59.424533 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
846 17:16:59.460434 <30>[ 19.669780] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
847 17:16:59.514684 Starting [0;1;39msystemd-network-g… units from Kernel command line...
848 17:16:59.568634 <30>[ 19.776350] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
849 17:16:59.632807 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
850 17:16:59.698564 <30>[ 19.907183] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
851 17:16:59.758743 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
852 17:16:59.792225 <30>[ 20.001491] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
853 17:16:59.845335 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
854 17:16:59.884617 <30>[ 20.093908] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
855 17:16:59.905425 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
856 17:16:59.926168 <30>[ 20.134358] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
857 17:16:59.951257 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
858 17:17:00.114447 <30>[ 20.324179] systemd[1]: modprobe@configfs.service: Deactivated successfully.
859 17:17:00.144593 <30>[ 20.353374] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
860 17:17:00.173750 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
861 17:17:00.204466 <30>[ 20.414464] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
862 17:17:00.234261 <30>[ 20.443087] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
863 17:17:00.263046 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
864 17:17:00.284147 <30>[ 20.494560] systemd[1]: modprobe@drm.service: Deactivated successfully.
865 17:17:00.303662 <30>[ 20.513344] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
866 17:17:00.331962 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
867 17:17:00.344657 <30>[ 20.553293] systemd[1]: Started systemd-journald.service - Journal Service.
868 17:17:00.351557 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
869 17:17:00.395209 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
870 17:17:00.418268 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
871 17:17:00.454805 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
872 17:17:00.476430 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
873 17:17:00.496885 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
874 17:17:00.526151 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
875 17:17:00.548041 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
876 17:17:00.616140 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
877 17:17:00.662589 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
878 17:17:00.725709 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
879 17:17:00.823135 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
880 17:17:00.908607 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
881 17:17:01.039263 <46>[ 21.247199] systemd-journald[164]: Received client request to flush runtime journal.
882 17:17:01.052158 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
883 17:17:01.087262 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
884 17:17:01.284248 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
885 17:17:02.058774 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
886 17:17:02.125967 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
887 17:17:02.766409 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
888 17:17:02.896564 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
889 17:17:02.923608 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
890 17:17:02.943540 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
891 17:17:03.008513 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
892 17:17:03.058846 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
893 17:17:03.967734 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
894 17:17:04.044785 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
895 17:17:04.323939 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
896 17:17:04.375930 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
897 17:17:04.416787 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
898 17:17:06.012258 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
899 17:17:06.118820 <5>[ 26.328108] cfg80211: Loading compiled-in X.509 certificates for regulatory database
900 17:17:06.882771 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
901 17:17:07.496802 <5>[ 27.708128] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
902 17:17:07.549171 <5>[ 27.759059] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
903 17:17:07.581367 <4>[ 27.790599] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
904 17:17:07.587352 <6>[ 27.799729] cfg80211: failed to load regulatory.db
905 17:17:07.964778 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
906 17:17:08.498113 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
907 17:17:08.513356 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
908 17:17:08.798475 <46>[ 28.998741] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
909 17:17:08.955419 <46>[ 29.158019] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
910 17:17:18.587630 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
911 17:17:18.619923 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
912 17:17:18.644758 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
913 17:17:18.664732 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
914 17:17:18.722770 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
915 17:17:18.773359 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
916 17:17:18.821680 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
917 17:17:18.883802 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
918 17:17:18.936322 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
919 17:17:18.969643 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
920 17:17:18.997398 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
921 17:17:19.039647 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
922 17:17:19.066199 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
923 17:17:19.113250 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
924 17:17:19.136858 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
925 17:17:19.176270 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
926 17:17:19.213259 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
927 17:17:19.237906 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
928 17:17:19.264232 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
929 17:17:19.285248 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
930 17:17:19.334392 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
931 17:17:19.351005 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
932 17:17:19.375674 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
933 17:17:19.454046 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
934 17:17:19.500191 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
935 17:17:19.620630 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
936 17:17:19.702511 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
937 17:17:19.766319 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
938 17:17:19.816332 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
939 17:17:19.845084 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
940 17:17:20.044008 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
941 17:17:20.114008 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
942 17:17:20.175747 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
943 17:17:20.193582 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
944 17:17:20.215764 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
945 17:17:20.448472 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
946 17:17:20.826002 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
947 17:17:20.879001 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
948 17:17:20.908442 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
949 17:17:20.998592 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
950 17:17:21.171210 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
951 17:17:21.306449
952 17:17:21.307035 Debian GNU/Linux 12 debian-bookworm
953 17:17:21.307601
954 17:17:21.312502 debian-bookworm-armhf login: root (automatic login)
955 17:17:21.313036
956 17:17:21.617684 Linux debian-bookworm-armhf 6.12.0-rc2 #1 SMP Thu Nov 7 16:46:23 UTC 2024 armv7l
957 17:17:21.618391
958 17:17:21.623281 The programs included with the Debian GNU/Linux system are free software;
959 17:17:21.628872 the exact distribution terms for each program are described in the
960 17:17:21.634527 individual files in /usr/share/doc/*/copyright.
961 17:17:21.635087
962 17:17:21.642485 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
963 17:17:21.643066 permitted by applicable law.
964 17:17:26.685916 Unable to match end of the kernel message
966 17:17:26.686849 Setting prompt string to ['/ #']
967 17:17:26.687194 end: 2.4.4.1 login-action (duration 00:00:47) [common]
969 17:17:26.688008 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
970 17:17:26.688365 start: 2.4.5 expect-shell-connection (timeout 00:03:12) [common]
971 17:17:26.688628 Setting prompt string to ['/ #']
972 17:17:26.688853 Forcing a shell prompt, looking for ['/ #']
974 17:17:26.739448 / #
975 17:17:26.740186 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
976 17:17:26.740483 Waiting using forced prompt support (timeout 00:02:30)
977 17:17:26.744891
978 17:17:26.769152 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
979 17:17:26.769628 start: 2.4.6 export-device-env (timeout 00:03:12) [common]
980 17:17:26.769924 Sending with 10 millisecond of delay
982 17:17:31.761779 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/954361/extract-nfsrootfs-91b6uxt9'
983 17:17:31.772657 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/954361/extract-nfsrootfs-91b6uxt9'
984 17:17:31.773560 Sending with 10 millisecond of delay
986 17:17:33.873906 / # export NFS_SERVER_IP='192.168.6.3'
987 17:17:33.884821 export NFS_SERVER_IP='192.168.6.3'
988 17:17:33.888960 end: 2.4.6 export-device-env (duration 00:00:07) [common]
989 17:17:33.889570 end: 2.4 uboot-commands (duration 00:01:55) [common]
990 17:17:33.890183 end: 2 uboot-action (duration 00:01:55) [common]
991 17:17:33.890757 start: 3 lava-test-retry (timeout 00:06:52) [common]
992 17:17:33.891366 start: 3.1 lava-test-shell (timeout 00:06:52) [common]
993 17:17:33.891815 Using namespace: common
995 17:17:33.992970 / # #
996 17:17:33.993938 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
997 17:17:33.998635 #
998 17:17:34.004803 Using /lava-954361
1000 17:17:34.105989 / # export SHELL=/bin/bash
1001 17:17:34.110497 export SHELL=/bin/bash
1003 17:17:34.218527 / # . /lava-954361/environment
1004 17:17:34.223553 . /lava-954361/environment
1006 17:17:34.337732 / # /lava-954361/bin/lava-test-runner /lava-954361/0
1007 17:17:34.338338 Test shell timeout: 10s (minimum of the action and connection timeout)
1008 17:17:34.343331 /lava-954361/bin/lava-test-runner /lava-954361/0
1009 17:17:34.728494 + export TESTRUN_ID=0_timesync-off
1010 17:17:34.736310 + TESTRUN_ID=0_timesync-off
1011 17:17:34.736770 + cd /lava-954361/0/tests/0_timesync-off
1012 17:17:34.737179 ++ cat uuid
1013 17:17:34.751291 + UUID=954361_1.6.2.4.1
1014 17:17:34.751754 + set +x
1015 17:17:34.760014 <LAVA_SIGNAL_STARTRUN 0_timesync-off 954361_1.6.2.4.1>
1016 17:17:34.760450 + systemctl stop systemd-timesyncd
1017 17:17:34.761162 Received signal: <STARTRUN> 0_timesync-off 954361_1.6.2.4.1
1018 17:17:34.761628 Starting test lava.0_timesync-off (954361_1.6.2.4.1)
1019 17:17:34.762187 Skipping test definition patterns.
1020 17:17:35.039137 + set +x
1021 17:17:35.039754 <LAVA_SIGNAL_ENDRUN 0_timesync-off 954361_1.6.2.4.1>
1022 17:17:35.040446 Received signal: <ENDRUN> 0_timesync-off 954361_1.6.2.4.1
1023 17:17:35.040943 Ending use of test pattern.
1024 17:17:35.041343 Ending test lava.0_timesync-off (954361_1.6.2.4.1), duration 0.28
1026 17:17:35.211643 + export TESTRUN_ID=1_kselftest-dt
1027 17:17:35.219510 + TESTRUN_ID=1_kselftest-dt
1028 17:17:35.220017 + cd /lava-954361/0/tests/1_kselftest-dt
1029 17:17:35.220453 ++ cat uuid
1030 17:17:35.243925 + UUID=954361_1.6.2.4.5
1031 17:17:35.244495 + set +x
1032 17:17:35.249634 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 954361_1.6.2.4.5>
1033 17:17:35.250153 + cd ./automated/linux/kselftest/
1034 17:17:35.250819 Received signal: <STARTRUN> 1_kselftest-dt 954361_1.6.2.4.5
1035 17:17:35.251237 Starting test lava.1_kselftest-dt (954361_1.6.2.4.5)
1036 17:17:35.251714 Skipping test definition patterns.
1037 17:17:35.279570 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-8-g23569c8b31492/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1038 17:17:35.379133 INFO: install_deps skipped
1039 17:17:35.949569 --2024-11-07 17:17:35-- http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-8-g23569c8b31492/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1040 17:17:35.988470 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1041 17:17:36.135385 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1042 17:17:36.280079 HTTP request sent, awaiting response... 200 OK
1043 17:17:36.280677 Length: 4099116 (3.9M) [application/octet-stream]
1044 17:17:36.285491 Saving to: 'kselftest_armhf.tar.gz'
1045 17:17:36.286040
1046 17:17:38.052260
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 174KB/s
kselftest_armhf.tar 4%[ ] 194.76K 335KB/s
kselftest_armhf.tar 18%[==> ] 726.76K 790KB/s
kselftest_armhf.tar 41%[=======> ] 1.64M 1.44MB/s
kselftest_armhf.tar 58%[==========> ] 2.28M 1.70MB/s
kselftest_armhf.tar 81%[===============> ] 3.18M 2.03MB/s
kselftest_armhf.tar 100%[===================>] 3.91M 2.21MB/s in 1.8s
1047 17:17:38.052959
1048 17:17:38.593698 2024-11-07 17:17:38 (2.21 MB/s) - 'kselftest_armhf.tar.gz' saved [4099116/4099116]
1049 17:17:38.594508
1050 17:17:53.467053 skiplist:
1051 17:17:53.467470 ========================================
1052 17:17:53.472635 ========================================
1053 17:17:53.572488 dt:test_unprobed_devices.sh
1054 17:17:53.606516 ============== Tests to run ===============
1055 17:17:53.614492 dt:test_unprobed_devices.sh
1056 17:17:53.618274 ===========End Tests to run ===============
1057 17:17:53.629314 shardfile-dt pass
1058 17:17:53.862287 <12>[ 74.076629] kselftest: Running tests in dt
1059 17:17:53.891781 TAP version 13
1060 17:17:53.912977 1..1
1061 17:17:53.966088 # timeout set to 45
1062 17:17:53.966553 # selftests: dt: test_unprobed_devices.sh
1063 17:17:54.795305 # TAP version 13
1064 17:18:19.463802 # 1..257
1065 17:18:19.627457 # ok 1 / # SKIP
1066 17:18:19.648392 # ok 2 /clk_mcasp0
1067 17:18:19.718918 # ok 3 /clk_mcasp0_fixed # SKIP
1068 17:18:19.792993 # ok 4 /cpus/cpu@0 # SKIP
1069 17:18:19.862741 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1070 17:18:19.890170 # ok 6 /fixedregulator0
1071 17:18:19.904423 # ok 7 /leds
1072 17:18:19.924805 # ok 8 /ocp
1073 17:18:19.949289 # ok 9 /ocp/interconnect@44c00000
1074 17:18:19.975956 # ok 10 /ocp/interconnect@44c00000/segment@0
1075 17:18:20.000591 # ok 11 /ocp/interconnect@44c00000/segment@100000
1076 17:18:20.020023 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1077 17:18:20.091321 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1078 17:18:20.111623 # ok 14 /ocp/interconnect@44c00000/segment@200000
1079 17:18:20.137718 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1080 17:18:20.241252 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1081 17:18:20.313568 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1082 17:18:20.385845 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1083 17:18:20.457151 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1084 17:18:20.527710 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1085 17:18:20.598613 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1086 17:18:20.670066 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1087 17:18:20.740843 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1088 17:18:20.811679 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1089 17:18:20.887167 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1090 17:18:20.958256 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1091 17:18:21.030273 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1092 17:18:21.099835 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1093 17:18:21.168948 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1094 17:18:21.239948 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1095 17:18:21.310737 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1096 17:18:21.383494 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1097 17:18:21.458012 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1098 17:18:21.529397 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1099 17:18:21.600513 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1100 17:18:21.667377 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1101 17:18:21.742994 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1102 17:18:21.815227 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1103 17:18:21.886956 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1104 17:18:21.958946 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1105 17:18:22.030459 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1106 17:18:22.104885 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1107 17:18:22.180999 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1108 17:18:22.251801 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1109 17:18:22.320598 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1110 17:18:22.394184 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1111 17:18:22.461782 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1112 17:18:22.532418 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1113 17:18:22.602925 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1114 17:18:22.674008 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1115 17:18:22.745087 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1116 17:18:22.814712 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1117 17:18:22.886637 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1118 17:18:22.957654 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1119 17:18:23.028165 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1120 17:18:23.100855 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1121 17:18:23.172519 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1122 17:18:23.242945 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1123 17:18:23.315464 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1124 17:18:23.387663 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1125 17:18:23.457984 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1126 17:18:23.530919 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1127 17:18:23.603028 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1128 17:18:23.678935 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1129 17:18:23.748691 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1130 17:18:23.819953 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1131 17:18:23.891629 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1132 17:18:23.958271 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1133 17:18:24.027903 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1134 17:18:24.100343 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1135 17:18:24.175142 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1136 17:18:24.245742 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1137 17:18:24.317246 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1138 17:18:24.389456 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1139 17:18:24.463976 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1140 17:18:24.535638 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1141 17:18:24.606869 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1142 17:18:24.677645 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1143 17:18:24.748558 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1144 17:18:24.819981 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1145 17:18:24.893849 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1146 17:18:24.967323 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1147 17:18:25.038872 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1148 17:18:25.110751 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1149 17:18:25.177279 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1150 17:18:25.248546 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1151 17:18:25.321550 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1152 17:18:25.390506 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1153 17:18:25.464466 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1154 17:18:25.535369 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1155 17:18:25.604584 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1156 17:18:25.676908 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1157 17:18:25.746618 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1158 17:18:25.819145 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1159 17:18:25.842465 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1160 17:18:25.866918 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1161 17:18:25.888991 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1162 17:18:25.911081 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1163 17:18:25.934156 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1164 17:18:25.957888 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1165 17:18:25.981629 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1166 17:18:26.002492 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1167 17:18:26.106991 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1168 17:18:26.137083 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1169 17:18:26.159872 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1170 17:18:26.180612 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1171 17:18:26.284791 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1172 17:18:26.358732 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1173 17:18:26.431376 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1174 17:18:26.505714 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1175 17:18:26.574754 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1176 17:18:26.645840 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1177 17:18:26.720029 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1178 17:18:26.790186 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1179 17:18:26.861917 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1180 17:18:26.938234 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1181 17:18:27.008620 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1182 17:18:27.075811 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1183 17:18:27.145921 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1184 17:18:27.219341 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1185 17:18:27.290736 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1186 17:18:27.362552 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1187 17:18:27.384246 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1188 17:18:27.454040 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1189 17:18:27.522349 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1190 17:18:27.593877 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1191 17:18:27.615328 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1192 17:18:27.686377 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1193 17:18:27.708711 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1194 17:18:27.778708 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1195 17:18:27.805248 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1196 17:18:27.828399 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1197 17:18:27.847343 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1198 17:18:27.871865 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1199 17:18:27.894041 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1200 17:18:27.917729 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1201 17:18:27.943558 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1202 17:18:28.021285 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1203 17:18:28.038298 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1204 17:18:28.061552 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1205 17:18:28.136426 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1206 17:18:28.201617 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1207 17:18:28.222143 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1208 17:18:28.325418 # not ok 144 /ocp/interconnect@47c00000
1209 17:18:28.391879 # not ok 145 /ocp/interconnect@47c00000/segment@0
1210 17:18:28.412857 # ok 146 /ocp/interconnect@48000000
1211 17:18:28.436501 # ok 147 /ocp/interconnect@48000000/segment@0
1212 17:18:28.460884 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1213 17:18:28.487826 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1214 17:18:28.509327 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1215 17:18:28.529916 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1216 17:18:28.553462 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1217 17:18:28.576369 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1218 17:18:28.599209 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1219 17:18:28.670436 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1220 17:18:28.742036 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1221 17:18:28.763631 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1222 17:18:28.787735 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1223 17:18:28.810317 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1224 17:18:28.834230 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1225 17:18:28.856499 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1226 17:18:28.885262 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1227 17:18:28.907764 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1228 17:18:28.928425 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1229 17:18:28.950067 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1230 17:18:28.977598 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1231 17:18:28.996919 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1232 17:18:29.020053 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1233 17:18:29.046588 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1234 17:18:29.068287 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1235 17:18:29.093446 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1236 17:18:29.117648 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1237 17:18:29.135726 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1238 17:18:29.164866 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1239 17:18:29.185172 # ok 175 /ocp/interconnect@48000000/segment@100000
1240 17:18:29.208239 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1241 17:18:29.234779 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1242 17:18:29.302892 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1243 17:18:29.375144 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1244 17:18:29.444323 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1245 17:18:29.517638 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1246 17:18:29.588182 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1247 17:18:29.659891 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1248 17:18:29.734124 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1249 17:18:29.803193 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1250 17:18:29.823032 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1251 17:18:29.846080 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1252 17:18:29.869641 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1253 17:18:29.897383 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1254 17:18:29.918103 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1255 17:18:29.940804 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1256 17:18:29.967053 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1257 17:18:29.988752 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1258 17:18:30.010039 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1259 17:18:30.035973 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1260 17:18:30.057162 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1261 17:18:30.083973 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1262 17:18:30.104114 # ok 198 /ocp/interconnect@48000000/segment@200000
1263 17:18:30.126892 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1264 17:18:30.198316 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1265 17:18:30.218569 # ok 201 /ocp/interconnect@48000000/segment@300000
1266 17:18:30.242590 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1267 17:18:30.267912 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1268 17:18:30.290505 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1269 17:18:30.313036 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1270 17:18:30.336250 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1271 17:18:30.364039 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1272 17:18:30.436455 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1273 17:18:30.454626 # ok 209 /ocp/interconnect@4a000000
1274 17:18:30.475757 # ok 210 /ocp/interconnect@4a000000/segment@0
1275 17:18:30.498127 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1276 17:18:30.522808 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1277 17:18:30.547467 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1278 17:18:30.573384 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1279 17:18:30.640471 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1280 17:18:30.749741 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1281 17:18:30.820939 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1282 17:18:30.919960 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1283 17:18:30.987533 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1284 17:18:31.064349 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1285 17:18:31.157438 # not ok 221 /ocp/interconnect@4b140000
1286 17:18:31.229071 # not ok 222 /ocp/interconnect@4b140000/segment@0
1287 17:18:31.304281 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1288 17:18:31.324814 # ok 224 /ocp/target-module@40300000
1289 17:18:31.344684 # ok 225 /ocp/target-module@40300000/sram@0
1290 17:18:31.423437 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1291 17:18:31.491132 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1292 17:18:31.514382 # ok 228 /ocp/target-module@47400000
1293 17:18:31.538378 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1294 17:18:31.555648 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1295 17:18:31.583546 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1296 17:18:31.605769 # ok 232 /ocp/target-module@47400000/usb@1400
1297 17:18:31.623338 # ok 233 /ocp/target-module@47400000/usb@1800
1298 17:18:31.644951 # ok 234 /ocp/target-module@47810000
1299 17:18:31.670888 # ok 235 /ocp/target-module@49000000
1300 17:18:31.692929 # ok 236 /ocp/target-module@49000000/dma@0
1301 17:18:31.709144 # ok 237 /ocp/target-module@49800000
1302 17:18:31.735587 # ok 238 /ocp/target-module@49800000/dma@0
1303 17:18:31.756134 # ok 239 /ocp/target-module@49900000
1304 17:18:31.779369 # ok 240 /ocp/target-module@49900000/dma@0
1305 17:18:31.805128 # ok 241 /ocp/target-module@49a00000
1306 17:18:31.825497 # ok 242 /ocp/target-module@49a00000/dma@0
1307 17:18:31.849356 # ok 243 /ocp/target-module@4c000000
1308 17:18:31.920655 # not ok 244 /ocp/target-module@4c000000/emif@0
1309 17:18:31.941781 # ok 245 /ocp/target-module@50000000
1310 17:18:31.959567 # ok 246 /ocp/target-module@53100000
1311 17:18:32.034708 # not ok 247 /ocp/target-module@53100000/sham@0
1312 17:18:32.054005 # ok 248 /ocp/target-module@53500000
1313 17:18:32.122824 # not ok 249 /ocp/target-module@53500000/aes@0
1314 17:18:32.144298 # ok 250 /ocp/target-module@56000000
1315 17:18:32.251296 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1316 17:18:32.323497 # ok 252 /opp-table # SKIP
1317 17:18:32.393525 # ok 253 /soc # SKIP
1318 17:18:32.410238 # ok 254 /sound
1319 17:18:32.433912 # ok 255 /target-module@4b000000
1320 17:18:32.457934 # ok 256 /target-module@4b000000/target-module@140000
1321 17:18:32.479392 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1322 17:18:32.487661 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1323 17:18:32.496276 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1324 17:18:34.687789 dt_test_unprobed_devices_sh_ skip
1325 17:18:34.693246 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1326 17:18:34.698840 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1327 17:18:34.699374 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1328 17:18:34.704382 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1329 17:18:34.709983 dt_test_unprobed_devices_sh_fixedregulator0 pass
1330 17:18:34.715612 dt_test_unprobed_devices_sh_leds pass
1331 17:18:34.716152 dt_test_unprobed_devices_sh_ocp pass
1332 17:18:34.721198 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1333 17:18:34.726878 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1334 17:18:34.732433 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1335 17:18:34.743627 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1336 17:18:34.749247 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1337 17:18:34.754852 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1338 17:18:34.766063 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1339 17:18:34.771685 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1340 17:18:34.782976 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1341 17:18:34.794341 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1342 17:18:34.805442 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1343 17:18:34.811066 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1344 17:18:34.822202 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1345 17:18:34.833574 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1346 17:18:34.844609 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1347 17:18:34.855840 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1348 17:18:34.861577 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1349 17:18:34.872754 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1350 17:18:34.883903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1351 17:18:34.895221 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1352 17:18:34.906339 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1353 17:18:34.911935 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1354 17:18:34.923129 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1355 17:18:34.934312 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1356 17:18:34.945497 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1357 17:18:34.951071 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1358 17:18:34.962187 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1359 17:18:34.973365 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1360 17:18:34.984710 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1361 17:18:34.995766 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1362 17:18:35.001352 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1363 17:18:35.012524 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1364 17:18:35.023738 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1365 17:18:35.035017 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1366 17:18:35.046192 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1367 17:18:35.057436 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1368 17:18:35.068562 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1369 17:18:35.079632 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1370 17:18:35.091053 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1371 17:18:35.102172 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1372 17:18:35.113372 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1373 17:18:35.124683 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1374 17:18:35.135808 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1375 17:18:35.146988 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1376 17:18:35.158194 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1377 17:18:35.169317 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1378 17:18:35.180611 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1379 17:18:35.191607 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1380 17:18:35.202805 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1381 17:18:35.214012 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1382 17:18:35.225202 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1383 17:18:35.236400 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1384 17:18:35.247582 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1385 17:18:35.258767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1386 17:18:35.269954 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1387 17:18:35.281301 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1388 17:18:35.286798 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1389 17:18:35.298050 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1390 17:18:35.309095 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1391 17:18:35.320326 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1392 17:18:35.331565 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1393 17:18:35.342665 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1394 17:18:35.353949 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1395 17:18:35.365031 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1396 17:18:35.376332 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1397 17:18:35.387511 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1398 17:18:35.398760 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1399 17:18:35.410351 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1400 17:18:35.421019 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1401 17:18:35.432213 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1402 17:18:35.443408 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1403 17:18:35.454561 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1404 17:18:35.465747 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1405 17:18:35.476948 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1406 17:18:35.482622 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1407 17:18:35.493736 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1408 17:18:35.504988 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1409 17:18:35.516230 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1410 17:18:35.527177 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1411 17:18:35.532866 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1412 17:18:35.549590 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1413 17:18:35.560950 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1414 17:18:35.566541 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1415 17:18:35.583249 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1416 17:18:35.594468 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1417 17:18:35.605754 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1418 17:18:35.611295 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1419 17:18:35.622474 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1420 17:18:35.633648 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1421 17:18:35.639305 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1422 17:18:35.650433 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1423 17:18:35.661625 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1424 17:18:35.667239 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1425 17:18:35.678441 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1426 17:18:35.684085 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1427 17:18:35.695215 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1428 17:18:35.706365 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1429 17:18:35.717636 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1430 17:18:35.728755 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1431 17:18:35.740777 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1432 17:18:35.751266 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1433 17:18:35.762393 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1434 17:18:35.773675 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1435 17:18:35.784752 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1436 17:18:35.796707 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1437 17:18:35.807650 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1438 17:18:35.818473 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1439 17:18:35.835306 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1440 17:18:35.846297 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1441 17:18:35.857398 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1442 17:18:35.868835 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1443 17:18:35.879948 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1444 17:18:35.896690 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1445 17:18:35.908014 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1446 17:18:35.919214 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1447 17:18:35.930370 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1448 17:18:35.935918 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1449 17:18:35.949029 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1450 17:18:35.958546 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1451 17:18:35.963996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1452 17:18:35.975153 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1453 17:18:35.980696 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1454 17:18:35.991976 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1455 17:18:35.997480 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1456 17:18:36.008663 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1457 17:18:36.014292 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1458 17:18:36.025437 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1459 17:18:36.031029 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1460 17:18:36.042268 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1461 17:18:36.053328 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1462 17:18:36.064620 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1463 17:18:36.076251 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1464 17:18:36.087063 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1465 17:18:36.092586 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1466 17:18:36.103742 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1467 17:18:36.109324 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1468 17:18:36.114989 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1469 17:18:36.120579 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1470 17:18:36.126172 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1471 17:18:36.131740 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1472 17:18:36.142921 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1473 17:18:36.148485 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1474 17:18:36.154088 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1475 17:18:36.165233 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1476 17:18:36.170932 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1477 17:18:36.182098 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1478 17:18:36.187654 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1479 17:18:36.199283 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1480 17:18:36.204379 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1481 17:18:36.215594 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1482 17:18:36.221161 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1483 17:18:36.232457 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1484 17:18:36.238073 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1485 17:18:36.249244 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1486 17:18:36.254835 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1487 17:18:36.266064 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1488 17:18:36.271693 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1489 17:18:36.277219 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1490 17:18:36.288391 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1491 17:18:36.294038 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1492 17:18:36.305172 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1493 17:18:36.310785 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1494 17:18:36.322040 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1495 17:18:36.327574 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1496 17:18:36.338697 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1497 17:18:36.344319 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1498 17:18:36.349929 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1499 17:18:36.361199 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1500 17:18:36.366805 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1501 17:18:36.378016 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1502 17:18:36.389145 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1503 17:18:36.400318 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1504 17:18:36.411543 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1505 17:18:36.422721 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1506 17:18:36.433936 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1507 17:18:36.445101 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1508 17:18:36.456258 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1509 17:18:36.461911 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1510 17:18:36.473106 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1511 17:18:36.478774 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1512 17:18:36.489860 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1513 17:18:36.495469 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1514 17:18:36.506788 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1515 17:18:36.512245 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1516 17:18:36.523439 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1517 17:18:36.529070 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1518 17:18:36.540215 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1519 17:18:36.545893 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1520 17:18:36.557052 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1521 17:18:36.562657 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1522 17:18:36.573877 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1523 17:18:36.579536 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1524 17:18:36.585141 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1525 17:18:36.596240 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1526 17:18:36.601902 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1527 17:18:36.612997 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1528 17:18:36.618631 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1529 17:18:36.629894 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1530 17:18:36.635434 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1531 17:18:36.646646 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1532 17:18:36.652265 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1533 17:18:36.657895 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1534 17:18:36.663437 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1535 17:18:36.674656 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1536 17:18:36.685960 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1537 17:18:36.691479 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1538 17:18:36.697043 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1539 17:18:36.708253 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1540 17:18:36.719360 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1541 17:18:36.732718 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1542 17:18:36.741787 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1543 17:18:36.747356 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1544 17:18:36.752960 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1545 17:18:36.758618 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1546 17:18:36.764202 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1547 17:18:36.769774 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1548 17:18:36.775379 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1549 17:18:36.786606 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1550 17:18:36.792203 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1551 17:18:36.797717 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1552 17:18:36.803357 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1553 17:18:36.809025 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1554 17:18:36.820198 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1555 17:18:36.825746 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1556 17:18:36.831383 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1557 17:18:36.837029 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1558 17:18:36.842604 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1559 17:18:36.848193 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1560 17:18:36.853838 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1561 17:18:36.859458 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1562 17:18:36.865069 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1563 17:18:36.870656 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1564 17:18:36.876327 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1565 17:18:36.881879 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1566 17:18:36.887446 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1567 17:18:36.893063 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1568 17:18:36.898726 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1569 17:18:36.904354 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1570 17:18:36.909920 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1571 17:18:36.915480 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1572 17:18:36.921092 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1573 17:18:36.926700 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1574 17:18:36.932277 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1575 17:18:36.932847 dt_test_unprobed_devices_sh_opp-table skip
1576 17:18:36.937864 dt_test_unprobed_devices_sh_soc skip
1577 17:18:36.943488 dt_test_unprobed_devices_sh_sound pass
1578 17:18:36.949150 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1579 17:18:36.954708 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1580 17:18:36.960505 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1581 17:18:36.966059 dt_test_unprobed_devices_sh fail
1582 17:18:36.966861 + ../../utils/send-to-lava.sh ./output/result.txt
1583 17:18:36.972492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1584 17:18:36.973263 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1586 17:18:36.981535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1587 17:18:36.982245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1589 17:18:37.071553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1590 17:18:37.072308 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1592 17:18:37.163217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1593 17:18:37.164484 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1595 17:18:37.255417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1596 17:18:37.256701 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1598 17:18:37.347634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1599 17:18:37.348415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1601 17:18:37.438153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1602 17:18:37.438987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1604 17:18:37.529968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1605 17:18:37.530552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1607 17:18:37.620664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1608 17:18:37.621252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1610 17:18:37.724280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1611 17:18:37.724919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1613 17:18:37.826450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1614 17:18:37.827095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1616 17:18:37.925782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1617 17:18:37.926550 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1619 17:18:38.027951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1620 17:18:38.029178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1622 17:18:38.121491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1623 17:18:38.122418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1625 17:18:38.216156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1626 17:18:38.217014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1628 17:18:38.311767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1629 17:18:38.312646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1631 17:18:38.417289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1632 17:18:38.418495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1634 17:18:38.511096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1635 17:18:38.511922 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1637 17:18:38.606067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1638 17:18:38.606894 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1640 17:18:38.705222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1641 17:18:38.706045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1643 17:18:38.807091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1644 17:18:38.807929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1646 17:18:38.907104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1647 17:18:38.908016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1649 17:18:39.009302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1650 17:18:39.010086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1652 17:18:39.101319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1653 17:18:39.101895 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1655 17:18:39.194222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1656 17:18:39.194957 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1658 17:18:39.286499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1659 17:18:39.287143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1661 17:18:39.387317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1662 17:18:39.388084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1664 17:18:39.488966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1665 17:18:39.489891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1667 17:18:39.582003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1668 17:18:39.582902 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1670 17:18:39.680363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1671 17:18:39.680931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1673 17:18:39.771779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1674 17:18:39.772748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1676 17:18:39.873619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1677 17:18:39.874644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1679 17:18:39.973579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1680 17:18:39.974487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1682 17:18:40.077552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1683 17:18:40.078431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1685 17:18:40.168549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1686 17:18:40.169150 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1688 17:18:40.264211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1689 17:18:40.265159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1691 17:18:40.366395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1692 17:18:40.367266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1694 17:18:40.466915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1695 17:18:40.467840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1697 17:18:40.568487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1698 17:18:40.569261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1700 17:18:40.669769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1701 17:18:40.671019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1703 17:18:40.764274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1704 17:18:40.765165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1706 17:18:40.867632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1707 17:18:40.868519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1709 17:18:40.966596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1710 17:18:40.967244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1712 17:18:41.060672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1713 17:18:41.062033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1715 17:18:41.149643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1716 17:18:41.151357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1718 17:18:41.235612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1719 17:18:41.236962 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1721 17:18:41.326527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1722 17:18:41.327826 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1724 17:18:41.418957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1725 17:18:41.420346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1727 17:18:41.509716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1728 17:18:41.511206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1730 17:18:41.612585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1731 17:18:41.613277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1733 17:18:41.713915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1734 17:18:41.714557 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1736 17:18:41.814696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1737 17:18:41.815345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1739 17:18:41.917475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1740 17:18:41.918123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1742 17:18:42.009880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1743 17:18:42.010490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1745 17:18:42.098118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1746 17:18:42.098729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1748 17:18:42.197866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1749 17:18:42.198474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1751 17:18:42.289224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1752 17:18:42.289840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1754 17:18:42.375218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1755 17:18:42.375822 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1757 17:18:42.466479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1758 17:18:42.467082 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1760 17:18:42.558305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1761 17:18:42.558892 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1763 17:18:42.651753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1764 17:18:42.652330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1766 17:18:42.753489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1767 17:18:42.754344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1769 17:18:42.848145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1770 17:18:42.849077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1772 17:18:42.947025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1773 17:18:42.947864 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1775 17:18:43.049681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1776 17:18:43.050585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1778 17:18:43.149357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1779 17:18:43.150263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1781 17:18:43.251535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1782 17:18:43.252391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1784 17:18:43.353276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1785 17:18:43.354541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1787 17:18:43.446368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1788 17:18:43.447282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1790 17:18:43.537411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1791 17:18:43.538331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1793 17:18:43.628750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1794 17:18:43.629763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1796 17:18:43.730478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1797 17:18:43.731091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1799 17:18:43.831873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1800 17:18:43.832477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1802 17:18:43.921347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1803 17:18:43.922018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1805 17:18:44.013181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1806 17:18:44.014161 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1808 17:18:44.106874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1809 17:18:44.107710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1811 17:18:44.200590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1812 17:18:44.201427 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1814 17:18:44.293064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1815 17:18:44.293906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1817 17:18:44.387966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1818 17:18:44.388912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1820 17:18:44.479337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1821 17:18:44.480231 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1823 17:18:44.571693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1824 17:18:44.572305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1826 17:18:44.663826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1827 17:18:44.664427 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1829 17:18:44.754212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1830 17:18:44.755093 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1832 17:18:44.846421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1833 17:18:44.847296 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1835 17:18:44.947244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1836 17:18:44.948215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1838 17:18:45.040668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1839 17:18:45.041301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1841 17:18:45.133012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1842 17:18:45.134125 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1844 17:18:45.224244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1845 17:18:45.224858 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1847 17:18:45.314600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1848 17:18:45.315463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1850 17:18:45.407977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1851 17:18:45.409035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1853 17:18:45.501316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1854 17:18:45.501909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1856 17:18:45.594194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1857 17:18:45.595033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1859 17:18:45.689339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1860 17:18:45.690200 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1862 17:18:45.778631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1863 17:18:45.779453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1865 17:18:45.873106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1866 17:18:45.873961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1868 17:18:45.961972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1869 17:18:45.962801 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1871 17:18:46.065456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1872 17:18:46.066371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1874 17:18:46.166193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1875 17:18:46.166996 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1877 17:18:46.266193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1878 17:18:46.266998 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1880 17:18:46.367742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1881 17:18:46.368553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1883 17:18:46.459349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1884 17:18:46.460165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1886 17:18:46.550216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1887 17:18:46.551060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1889 17:18:46.642511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1890 17:18:46.643205 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1892 17:18:46.733024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1893 17:18:46.733669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1895 17:18:46.827040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1896 17:18:46.827956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1898 17:18:46.917479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1899 17:18:46.918173 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1901 17:18:47.001873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1902 17:18:47.002396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1904 17:18:47.092560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1905 17:18:47.093348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1907 17:18:47.198103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1908 17:18:47.198930 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1910 17:18:47.289739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1911 17:18:47.290333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1913 17:18:47.381738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1914 17:18:47.382349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1916 17:18:47.475350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1917 17:18:47.475960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1919 17:18:47.567612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1920 17:18:47.568200 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1922 17:18:47.659690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1923 17:18:47.660281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1925 17:18:47.752463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1926 17:18:47.753062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1928 17:18:47.853614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1929 17:18:47.854200 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1931 17:18:47.956920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1932 17:18:47.957499 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1934 17:18:48.049860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1935 17:18:48.050445 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1937 17:18:48.140542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1938 17:18:48.141100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1940 17:18:48.231650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1941 17:18:48.232243 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1943 17:18:48.324286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1945 17:18:48.326649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1946 17:18:48.418383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1948 17:18:48.420818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1949 17:18:48.509868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1951 17:18:48.512065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1952 17:18:48.602326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1953 17:18:48.602911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1955 17:18:48.702268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1956 17:18:48.702875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1958 17:18:48.794075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1959 17:18:48.794681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1961 17:18:48.886359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1962 17:18:48.886996 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1964 17:18:48.976750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1965 17:18:48.977350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1967 17:18:49.069891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1968 17:18:49.070536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1970 17:18:49.160225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1971 17:18:49.160812 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1973 17:18:49.252983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1974 17:18:49.253609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1976 17:18:49.345684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1977 17:18:49.346306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1979 17:18:49.439496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1980 17:18:49.440098 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1982 17:18:49.530818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1983 17:18:49.531433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1985 17:18:49.632566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1986 17:18:49.633190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1988 17:18:49.732990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1989 17:18:49.733624 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1991 17:18:49.834649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1992 17:18:49.835242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1994 17:18:49.937074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1995 17:18:49.938313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1997 17:18:50.039571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
1998 17:18:50.040666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2000 17:18:50.138791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2001 17:18:50.139871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2003 17:18:50.236157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2004 17:18:50.237018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2006 17:18:50.326948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2007 17:18:50.327620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2009 17:18:50.420673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2010 17:18:50.421365 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2012 17:18:50.512937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2013 17:18:50.513942 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2015 17:18:50.602907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2016 17:18:50.603797 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2018 17:18:50.695919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2019 17:18:50.696800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2021 17:18:50.788805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2022 17:18:50.789716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2024 17:18:50.881591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2025 17:18:50.882566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2027 17:18:50.976404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2028 17:18:50.977006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2030 17:18:51.068000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2031 17:18:51.068680 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2033 17:18:51.162028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2034 17:18:51.162588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2036 17:18:51.253541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2037 17:18:51.254539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2039 17:18:51.354290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2040 17:18:51.355457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2042 17:18:51.456764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2043 17:18:51.457656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2045 17:18:51.558093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2046 17:18:51.558989 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2048 17:18:51.650134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2049 17:18:51.651036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2051 17:18:51.744261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2052 17:18:51.745132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2054 17:18:51.836173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2055 17:18:51.837056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2057 17:18:51.929601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2058 17:18:51.930544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2060 17:18:52.030611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2061 17:18:52.031543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2063 17:18:52.123160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2064 17:18:52.124064 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2066 17:18:52.214590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2067 17:18:52.215491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2069 17:18:52.305457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2070 17:18:52.306333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2072 17:18:52.396309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2073 17:18:52.397220 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2075 17:18:52.489772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2076 17:18:52.490421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2078 17:18:52.590398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2079 17:18:52.590995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2081 17:18:52.691653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2082 17:18:52.692232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2084 17:18:52.785897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2085 17:18:52.786489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2087 17:18:52.877979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2088 17:18:52.878593 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2090 17:18:52.970206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2091 17:18:52.971133 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2093 17:18:53.062211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2094 17:18:53.062938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2096 17:18:53.151332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2097 17:18:53.151934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2099 17:18:53.244265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2100 17:18:53.244861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2102 17:18:53.335711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2103 17:18:53.336597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2105 17:18:53.429121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2106 17:18:53.430015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2108 17:18:53.520248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2109 17:18:53.521156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2111 17:18:53.615139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2112 17:18:53.616000 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2114 17:18:53.707679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2115 17:18:53.708532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2117 17:18:53.801637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2118 17:18:53.802278 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2120 17:18:53.897140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2121 17:18:53.898053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2123 17:18:53.988775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2124 17:18:53.989613 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2126 17:18:54.084449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2127 17:18:54.085346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2129 17:18:54.176356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2130 17:18:54.177184 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2132 17:18:54.270122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2133 17:18:54.270980 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2135 17:18:54.361414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2136 17:18:54.362324 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2138 17:18:54.467062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2139 17:18:54.468037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2141 17:18:54.561057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2142 17:18:54.561929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2144 17:18:54.657768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2145 17:18:54.658740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2147 17:18:54.761558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2148 17:18:54.762457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2150 17:18:54.859547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2151 17:18:54.860427 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2153 17:18:54.954932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2154 17:18:54.955908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2156 17:18:55.057096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2157 17:18:55.057965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2159 17:18:55.155919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2160 17:18:55.156901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2162 17:18:55.250455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2163 17:18:55.251383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2165 17:18:55.343922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2166 17:18:55.345040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2168 17:18:55.439325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2169 17:18:55.439965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2171 17:18:55.536298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2172 17:18:55.536947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2174 17:18:55.635954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2175 17:18:55.636691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2177 17:18:55.728167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2178 17:18:55.728885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2180 17:18:55.823425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2181 17:18:55.824031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2183 17:18:55.939623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2184 17:18:55.940314 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2186 17:18:56.034430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2187 17:18:56.035054 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2189 17:18:56.126815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2190 17:18:56.127405 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2192 17:18:56.227941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2193 17:18:56.228532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2195 17:18:56.319901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2196 17:18:56.320498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2198 17:18:56.411262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2199 17:18:56.412122 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2201 17:18:56.502016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2202 17:18:56.503599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2204 17:18:56.591725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2205 17:18:56.593299 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2207 17:18:56.685765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2208 17:18:56.687069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2210 17:18:56.776832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2211 17:18:56.777413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2213 17:18:56.867027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2214 17:18:56.867620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2216 17:18:56.969249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2217 17:18:56.969877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2219 17:18:57.074724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2220 17:18:57.075325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2222 17:18:57.166262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2223 17:18:57.166860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2225 17:18:57.254692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2226 17:18:57.255599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2228 17:18:57.345907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2229 17:18:57.346437 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2231 17:18:57.438332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2232 17:18:57.439215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2234 17:18:57.527851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2235 17:18:57.528769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2237 17:18:57.618544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2238 17:18:57.619420 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2240 17:18:57.710945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2241 17:18:57.711773 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2243 17:18:57.805051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2244 17:18:57.805890 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2246 17:18:57.902062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2247 17:18:57.902842 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2249 17:18:58.003376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2250 17:18:58.004263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2252 17:18:58.095091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2253 17:18:58.095965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2255 17:18:58.188100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2256 17:18:58.188974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2258 17:18:58.280857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2259 17:18:58.281717 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2261 17:18:58.375325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2262 17:18:58.376211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2264 17:18:58.465636 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2266 17:18:58.467708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2267 17:18:58.567467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2268 17:18:58.568350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2270 17:18:58.670039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2271 17:18:58.670968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2273 17:18:58.770176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2274 17:18:58.771044 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2276 17:18:58.871922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2277 17:18:58.872833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2279 17:18:58.968971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2280 17:18:58.969839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2282 17:18:59.061941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2283 17:18:59.062832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2285 17:18:59.153907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2286 17:18:59.154795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2288 17:18:59.243960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2289 17:18:59.244861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2291 17:18:59.346342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2292 17:18:59.347231 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2294 17:18:59.447322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2295 17:18:59.448207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2297 17:18:59.541910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2298 17:18:59.542811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2300 17:18:59.633471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2301 17:18:59.634290 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2303 17:18:59.726207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2304 17:18:59.727024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2306 17:18:59.818387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2307 17:18:59.819206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2309 17:18:59.909865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2310 17:18:59.910738 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2312 17:19:00.000250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2313 17:19:00.001010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2315 17:19:00.102659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2316 17:19:00.103566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2318 17:19:00.204275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2319 17:19:00.204906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2321 17:19:00.297947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2322 17:19:00.298570 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2324 17:19:00.392614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2325 17:19:00.393216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2327 17:19:00.484142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2328 17:19:00.484765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2330 17:19:00.573170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2331 17:19:00.573780 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2333 17:19:00.661988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2334 17:19:00.662582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2336 17:19:00.754490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2337 17:19:00.755157 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2339 17:19:00.841502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2340 17:19:00.842172 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2342 17:19:00.942976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2343 17:19:00.943632 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2345 17:19:01.033501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2346 17:19:01.034195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2348 17:19:01.124758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2349 17:19:01.125421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2351 17:19:01.223084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2352 17:19:01.223794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2354 17:19:01.314890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2355 17:19:01.316281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2357 17:19:01.402510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2358 17:19:01.403156 + set +x
2359 17:19:01.403878 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2361 17:19:01.406667 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 954361_1.6.2.4.5>
2362 17:19:01.407422 Received signal: <ENDRUN> 1_kselftest-dt 954361_1.6.2.4.5
2363 17:19:01.407908 Ending use of test pattern.
2364 17:19:01.408343 Ending test lava.1_kselftest-dt (954361_1.6.2.4.5), duration 86.16
2366 17:19:01.413373 <LAVA_TEST_RUNNER EXIT>
2367 17:19:01.414133 ok: lava_test_shell seems to have completed
2368 17:19:01.428099 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2369 17:19:01.430054 end: 3.1 lava-test-shell (duration 00:01:28) [common]
2370 17:19:01.430615 end: 3 lava-test-retry (duration 00:01:28) [common]
2371 17:19:01.431152 start: 4 finalize (timeout 00:05:24) [common]
2372 17:19:01.431671 start: 4.1 power-off (timeout 00:00:30) [common]
2373 17:19:01.432577 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2374 17:19:01.465580 >> OK - accepted request
2375 17:19:01.469439 Returned 0 in 0 seconds
2376 17:19:01.571371 end: 4.1 power-off (duration 00:00:00) [common]
2378 17:19:01.572400 start: 4.2 read-feedback (timeout 00:05:24) [common]
2379 17:19:01.573329 Listened to connection for namespace 'common' for up to 1s
2380 17:19:01.573912 Listened to connection for namespace 'common' for up to 1s
2381 17:19:02.573995 Finalising connection for namespace 'common'
2382 17:19:02.574537 Disconnecting from shell: Finalise
2383 17:19:02.574817 / #
2384 17:19:02.675509 end: 4.2 read-feedback (duration 00:00:01) [common]
2385 17:19:02.676077 end: 4 finalize (duration 00:00:01) [common]
2386 17:19:02.676504 Cleaning after the job
2387 17:19:02.676870 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954361/tftp-deploy-bj4alk9r/ramdisk
2388 17:19:02.678593 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954361/tftp-deploy-bj4alk9r/kernel
2389 17:19:02.680084 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954361/tftp-deploy-bj4alk9r/dtb
2390 17:19:02.680782 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954361/tftp-deploy-bj4alk9r/nfsrootfs
2391 17:19:02.740570 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954361/tftp-deploy-bj4alk9r/modules
2392 17:19:02.748498 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/954361
2393 17:19:05.803593 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/954361
2394 17:19:05.804229 Job finished correctly