Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:52:08.431368 lava-dispatcher, installed at version: 2024.01
2 20:52:08.432248 start: 0 validate
3 20:52:08.432735 Start time: 2024-11-07 20:52:08.432705+00:00 (UTC)
4 20:52:08.433311 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:52:08.433869 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 20:52:08.480058 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:52:08.480641 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-8-g23569c8b31492%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 20:52:08.512904 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:52:08.513593 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-8-g23569c8b31492%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 20:52:08.550965 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:52:08.551552 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 20:52:08.584699 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 20:52:08.585216 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-8-g23569c8b31492%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 20:52:08.622282 validate duration: 0.19
16 20:52:08.623105 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 20:52:08.623445 start: 1.1 download-retry (timeout 00:10:00) [common]
18 20:52:08.623764 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 20:52:08.624362 Not decompressing ramdisk as can be used compressed.
20 20:52:08.624820 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 20:52:08.625106 saving as /var/lib/lava/dispatcher/tmp/954555/tftp-deploy-gw9n9f0u/ramdisk/initrd.cpio.gz
22 20:52:08.625379 total size: 5628169 (5 MB)
23 20:52:08.659831 progress 0 % (0 MB)
24 20:52:08.664185 progress 5 % (0 MB)
25 20:52:08.668599 progress 10 % (0 MB)
26 20:52:08.672561 progress 15 % (0 MB)
27 20:52:08.677295 progress 20 % (1 MB)
28 20:52:08.681131 progress 25 % (1 MB)
29 20:52:08.685287 progress 30 % (1 MB)
30 20:52:08.689499 progress 35 % (1 MB)
31 20:52:08.693272 progress 40 % (2 MB)
32 20:52:08.697486 progress 45 % (2 MB)
33 20:52:08.701305 progress 50 % (2 MB)
34 20:52:08.705486 progress 55 % (2 MB)
35 20:52:08.709744 progress 60 % (3 MB)
36 20:52:08.713556 progress 65 % (3 MB)
37 20:52:08.717696 progress 70 % (3 MB)
38 20:52:08.721382 progress 75 % (4 MB)
39 20:52:08.725450 progress 80 % (4 MB)
40 20:52:08.729123 progress 85 % (4 MB)
41 20:52:08.733144 progress 90 % (4 MB)
42 20:52:08.737138 progress 95 % (5 MB)
43 20:52:08.740473 progress 100 % (5 MB)
44 20:52:08.741113 5 MB downloaded in 0.12 s (46.39 MB/s)
45 20:52:08.741648 end: 1.1.1 http-download (duration 00:00:00) [common]
47 20:52:08.742532 end: 1.1 download-retry (duration 00:00:00) [common]
48 20:52:08.742820 start: 1.2 download-retry (timeout 00:10:00) [common]
49 20:52:08.743089 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 20:52:08.743564 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-8-g23569c8b31492/arm64/defconfig/gcc-12/kernel/Image
51 20:52:08.743828 saving as /var/lib/lava/dispatcher/tmp/954555/tftp-deploy-gw9n9f0u/kernel/Image
52 20:52:08.744068 total size: 45713920 (43 MB)
53 20:52:08.744281 No compression specified
54 20:52:08.785735 progress 0 % (0 MB)
55 20:52:08.816690 progress 5 % (2 MB)
56 20:52:08.845399 progress 10 % (4 MB)
57 20:52:08.873817 progress 15 % (6 MB)
58 20:52:08.901741 progress 20 % (8 MB)
59 20:52:08.929488 progress 25 % (10 MB)
60 20:52:08.957508 progress 30 % (13 MB)
61 20:52:08.985169 progress 35 % (15 MB)
62 20:52:09.012790 progress 40 % (17 MB)
63 20:52:09.040861 progress 45 % (19 MB)
64 20:52:09.068876 progress 50 % (21 MB)
65 20:52:09.096999 progress 55 % (24 MB)
66 20:52:09.125215 progress 60 % (26 MB)
67 20:52:09.152687 progress 65 % (28 MB)
68 20:52:09.180432 progress 70 % (30 MB)
69 20:52:09.208566 progress 75 % (32 MB)
70 20:52:09.236430 progress 80 % (34 MB)
71 20:52:09.263632 progress 85 % (37 MB)
72 20:52:09.291346 progress 90 % (39 MB)
73 20:52:09.319432 progress 95 % (41 MB)
74 20:52:09.346536 progress 100 % (43 MB)
75 20:52:09.347041 43 MB downloaded in 0.60 s (72.30 MB/s)
76 20:52:09.347515 end: 1.2.1 http-download (duration 00:00:01) [common]
78 20:52:09.348366 end: 1.2 download-retry (duration 00:00:01) [common]
79 20:52:09.348645 start: 1.3 download-retry (timeout 00:09:59) [common]
80 20:52:09.348908 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 20:52:09.349376 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-8-g23569c8b31492/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 20:52:09.349648 saving as /var/lib/lava/dispatcher/tmp/954555/tftp-deploy-gw9n9f0u/dtb/meson-g12b-a311d-libretech-cc.dtb
83 20:52:09.349857 total size: 54703 (0 MB)
84 20:52:09.350066 No compression specified
85 20:52:09.391230 progress 59 % (0 MB)
86 20:52:09.392114 progress 100 % (0 MB)
87 20:52:09.392665 0 MB downloaded in 0.04 s (1.22 MB/s)
88 20:52:09.393123 end: 1.3.1 http-download (duration 00:00:00) [common]
90 20:52:09.393936 end: 1.3 download-retry (duration 00:00:00) [common]
91 20:52:09.394196 start: 1.4 download-retry (timeout 00:09:59) [common]
92 20:52:09.394459 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 20:52:09.394911 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 20:52:09.395150 saving as /var/lib/lava/dispatcher/tmp/954555/tftp-deploy-gw9n9f0u/nfsrootfs/full.rootfs.tar
95 20:52:09.395353 total size: 120894716 (115 MB)
96 20:52:09.395560 Using unxz to decompress xz
97 20:52:09.432486 progress 0 % (0 MB)
98 20:52:10.228388 progress 5 % (5 MB)
99 20:52:11.080873 progress 10 % (11 MB)
100 20:52:11.878548 progress 15 % (17 MB)
101 20:52:12.615486 progress 20 % (23 MB)
102 20:52:13.208208 progress 25 % (28 MB)
103 20:52:14.040844 progress 30 % (34 MB)
104 20:52:14.841412 progress 35 % (40 MB)
105 20:52:15.187245 progress 40 % (46 MB)
106 20:52:15.572160 progress 45 % (51 MB)
107 20:52:16.439684 progress 50 % (57 MB)
108 20:52:17.491658 progress 55 % (63 MB)
109 20:52:18.416304 progress 60 % (69 MB)
110 20:52:19.314630 progress 65 % (74 MB)
111 20:52:20.237517 progress 70 % (80 MB)
112 20:52:21.130807 progress 75 % (86 MB)
113 20:52:21.918835 progress 80 % (92 MB)
114 20:52:22.690529 progress 85 % (98 MB)
115 20:52:23.560095 progress 90 % (103 MB)
116 20:52:24.365883 progress 95 % (109 MB)
117 20:52:25.199484 progress 100 % (115 MB)
118 20:52:25.212153 115 MB downloaded in 15.82 s (7.29 MB/s)
119 20:52:25.213098 end: 1.4.1 http-download (duration 00:00:16) [common]
121 20:52:25.214842 end: 1.4 download-retry (duration 00:00:16) [common]
122 20:52:25.215407 start: 1.5 download-retry (timeout 00:09:43) [common]
123 20:52:25.215968 start: 1.5.1 http-download (timeout 00:09:43) [common]
124 20:52:25.216852 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-8-g23569c8b31492/arm64/defconfig/gcc-12/modules.tar.xz
125 20:52:25.217390 saving as /var/lib/lava/dispatcher/tmp/954555/tftp-deploy-gw9n9f0u/modules/modules.tar
126 20:52:25.217835 total size: 11608504 (11 MB)
127 20:52:25.218292 Using unxz to decompress xz
128 20:52:25.261551 progress 0 % (0 MB)
129 20:52:25.328527 progress 5 % (0 MB)
130 20:52:25.402680 progress 10 % (1 MB)
131 20:52:25.498658 progress 15 % (1 MB)
132 20:52:25.598983 progress 20 % (2 MB)
133 20:52:25.677800 progress 25 % (2 MB)
134 20:52:25.753317 progress 30 % (3 MB)
135 20:52:25.827480 progress 35 % (3 MB)
136 20:52:25.904580 progress 40 % (4 MB)
137 20:52:25.983346 progress 45 % (5 MB)
138 20:52:26.067861 progress 50 % (5 MB)
139 20:52:26.144905 progress 55 % (6 MB)
140 20:52:26.229628 progress 60 % (6 MB)
141 20:52:26.309630 progress 65 % (7 MB)
142 20:52:26.386489 progress 70 % (7 MB)
143 20:52:26.468007 progress 75 % (8 MB)
144 20:52:26.552798 progress 80 % (8 MB)
145 20:52:26.634995 progress 85 % (9 MB)
146 20:52:26.713037 progress 90 % (9 MB)
147 20:52:26.792765 progress 95 % (10 MB)
148 20:52:26.869909 progress 100 % (11 MB)
149 20:52:26.881007 11 MB downloaded in 1.66 s (6.66 MB/s)
150 20:52:26.881613 end: 1.5.1 http-download (duration 00:00:02) [common]
152 20:52:26.882455 end: 1.5 download-retry (duration 00:00:02) [common]
153 20:52:26.882724 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 20:52:26.882993 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 20:52:43.951342 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/954555/extract-nfsrootfs-azqr57d2
156 20:52:43.951976 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 20:52:43.952302 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 20:52:43.952914 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce
159 20:52:43.953348 makedir: /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin
160 20:52:43.953683 makedir: /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/tests
161 20:52:43.953998 makedir: /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/results
162 20:52:43.954331 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-add-keys
163 20:52:43.954870 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-add-sources
164 20:52:43.955391 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-background-process-start
165 20:52:43.955897 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-background-process-stop
166 20:52:43.956470 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-common-functions
167 20:52:43.956974 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-echo-ipv4
168 20:52:43.957487 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-install-packages
169 20:52:43.957972 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-installed-packages
170 20:52:43.958443 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-os-build
171 20:52:43.958917 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-probe-channel
172 20:52:43.959399 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-probe-ip
173 20:52:43.959876 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-target-ip
174 20:52:43.960400 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-target-mac
175 20:52:43.960887 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-target-storage
176 20:52:43.961377 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-test-case
177 20:52:43.961906 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-test-event
178 20:52:43.962424 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-test-feedback
179 20:52:43.962912 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-test-raise
180 20:52:43.963394 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-test-reference
181 20:52:43.963875 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-test-runner
182 20:52:43.964409 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-test-set
183 20:52:43.964895 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-test-shell
184 20:52:43.965394 Updating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-add-keys (debian)
185 20:52:43.965961 Updating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-add-sources (debian)
186 20:52:43.966568 Updating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-install-packages (debian)
187 20:52:43.967099 Updating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-installed-packages (debian)
188 20:52:43.967597 Updating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/bin/lava-os-build (debian)
189 20:52:43.968053 Creating /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/environment
190 20:52:43.968439 LAVA metadata
191 20:52:43.968698 - LAVA_JOB_ID=954555
192 20:52:43.968913 - LAVA_DISPATCHER_IP=192.168.6.2
193 20:52:43.969283 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 20:52:43.970225 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 20:52:43.970533 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 20:52:43.970740 skipped lava-vland-overlay
197 20:52:43.970980 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 20:52:43.971232 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 20:52:43.971449 skipped lava-multinode-overlay
200 20:52:43.971689 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 20:52:43.971939 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 20:52:43.972259 Loading test definitions
203 20:52:43.972538 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 20:52:43.972760 Using /lava-954555 at stage 0
205 20:52:43.973838 uuid=954555_1.6.2.4.1 testdef=None
206 20:52:43.974139 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 20:52:43.974402 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 20:52:43.975927 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 20:52:43.976740 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 20:52:43.978658 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 20:52:43.979479 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 20:52:43.981322 runner path: /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/0/tests/0_timesync-off test_uuid 954555_1.6.2.4.1
215 20:52:43.981869 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 20:52:43.982675 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 20:52:43.982900 Using /lava-954555 at stage 0
219 20:52:43.983250 Fetching tests from https://github.com/kernelci/test-definitions.git
220 20:52:43.983543 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/0/tests/1_kselftest-dt'
221 20:52:47.467103 Running '/usr/bin/git checkout kernelci.org
222 20:52:47.842313 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
223 20:52:47.843748 uuid=954555_1.6.2.4.5 testdef=None
224 20:52:47.844227 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 20:52:47.845889 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 20:52:47.851853 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 20:52:47.853670 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 20:52:47.861685 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 20:52:47.863531 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 20:52:47.871310 runner path: /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/0/tests/1_kselftest-dt test_uuid 954555_1.6.2.4.5
234 20:52:47.871901 BOARD='meson-g12b-a311d-libretech-cc'
235 20:52:47.872384 BRANCH='broonie-sound'
236 20:52:47.872819 SKIPFILE='/dev/null'
237 20:52:47.873254 SKIP_INSTALL='True'
238 20:52:47.873684 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-8-g23569c8b31492/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 20:52:47.874125 TST_CASENAME=''
240 20:52:47.874558 TST_CMDFILES='dt'
241 20:52:47.875671 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 20:52:47.877419 Creating lava-test-runner.conf files
244 20:52:47.877868 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/954555/lava-overlay-m3xu7jce/lava-954555/0 for stage 0
245 20:52:47.878583 - 0_timesync-off
246 20:52:47.879096 - 1_kselftest-dt
247 20:52:47.879886 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 20:52:47.880549 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 20:53:11.171653 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 20:53:11.172165 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:57) [common]
251 20:53:11.172481 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 20:53:11.172810 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 20:53:11.173121 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:57) [common]
254 20:53:11.849507 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 20:53:11.849987 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 20:53:11.850259 extracting modules file /var/lib/lava/dispatcher/tmp/954555/tftp-deploy-gw9n9f0u/modules/modules.tar to /var/lib/lava/dispatcher/tmp/954555/extract-nfsrootfs-azqr57d2
257 20:53:13.420197 extracting modules file /var/lib/lava/dispatcher/tmp/954555/tftp-deploy-gw9n9f0u/modules/modules.tar to /var/lib/lava/dispatcher/tmp/954555/extract-overlay-ramdisk-i82heuad/ramdisk
258 20:53:14.878318 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 20:53:14.878803 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 20:53:14.879101 [common] Applying overlay to NFS
261 20:53:14.879330 [common] Applying overlay /var/lib/lava/dispatcher/tmp/954555/compress-overlay-mmkbhgav/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/954555/extract-nfsrootfs-azqr57d2
262 20:53:17.658539 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 20:53:17.658992 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 20:53:17.659295 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 20:53:17.659558 Converting downloaded kernel to a uImage
266 20:53:17.659887 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/954555/tftp-deploy-gw9n9f0u/kernel/Image /var/lib/lava/dispatcher/tmp/954555/tftp-deploy-gw9n9f0u/kernel/uImage
267 20:53:18.282083 output: Image Name:
268 20:53:18.282530 output: Created: Thu Nov 7 20:53:17 2024
269 20:53:18.282785 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 20:53:18.283021 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 20:53:18.283260 output: Load Address: 01080000
272 20:53:18.283502 output: Entry Point: 01080000
273 20:53:18.283730 output:
274 20:53:18.284137 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 20:53:18.284472 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 20:53:18.284812 start: 1.6.7 configure-preseed-file (timeout 00:08:50) [common]
277 20:53:18.285122 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 20:53:18.285438 start: 1.6.8 compress-ramdisk (timeout 00:08:50) [common]
279 20:53:18.285744 Building ramdisk /var/lib/lava/dispatcher/tmp/954555/extract-overlay-ramdisk-i82heuad/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/954555/extract-overlay-ramdisk-i82heuad/ramdisk
280 20:53:21.200739 >> 166783 blocks
281 20:53:28.936603 Adding RAMdisk u-boot header.
282 20:53:28.937055 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/954555/extract-overlay-ramdisk-i82heuad/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/954555/extract-overlay-ramdisk-i82heuad/ramdisk.cpio.gz.uboot
283 20:53:29.222109 output: Image Name:
284 20:53:29.222535 output: Created: Thu Nov 7 20:53:28 2024
285 20:53:29.222749 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 20:53:29.222953 output: Data Size: 23430095 Bytes = 22880.95 KiB = 22.34 MiB
287 20:53:29.223157 output: Load Address: 00000000
288 20:53:29.223356 output: Entry Point: 00000000
289 20:53:29.223556 output:
290 20:53:29.224223 rename /var/lib/lava/dispatcher/tmp/954555/extract-overlay-ramdisk-i82heuad/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/954555/tftp-deploy-gw9n9f0u/ramdisk/ramdisk.cpio.gz.uboot
291 20:53:29.224944 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
292 20:53:29.225490 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 20:53:29.226063 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:39) [common]
294 20:53:29.226507 No LXC device requested
295 20:53:29.227001 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 20:53:29.227502 start: 1.8 deploy-device-env (timeout 00:08:39) [common]
297 20:53:29.228018 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 20:53:29.228443 Checking files for TFTP limit of 4294967296 bytes.
299 20:53:29.231190 end: 1 tftp-deploy (duration 00:01:21) [common]
300 20:53:29.231762 start: 2 uboot-action (timeout 00:05:00) [common]
301 20:53:29.232319 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 20:53:29.232816 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 20:53:29.233314 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 20:53:29.233834 Using kernel file from prepare-kernel: 954555/tftp-deploy-gw9n9f0u/kernel/uImage
305 20:53:29.234459 substitutions:
306 20:53:29.234862 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 20:53:29.235263 - {DTB_ADDR}: 0x01070000
308 20:53:29.235659 - {DTB}: 954555/tftp-deploy-gw9n9f0u/dtb/meson-g12b-a311d-libretech-cc.dtb
309 20:53:29.236090 - {INITRD}: 954555/tftp-deploy-gw9n9f0u/ramdisk/ramdisk.cpio.gz.uboot
310 20:53:29.236489 - {KERNEL_ADDR}: 0x01080000
311 20:53:29.236878 - {KERNEL}: 954555/tftp-deploy-gw9n9f0u/kernel/uImage
312 20:53:29.237268 - {LAVA_MAC}: None
313 20:53:29.237693 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/954555/extract-nfsrootfs-azqr57d2
314 20:53:29.238087 - {NFS_SERVER_IP}: 192.168.6.2
315 20:53:29.238472 - {PRESEED_CONFIG}: None
316 20:53:29.238856 - {PRESEED_LOCAL}: None
317 20:53:29.239242 - {RAMDISK_ADDR}: 0x08000000
318 20:53:29.239624 - {RAMDISK}: 954555/tftp-deploy-gw9n9f0u/ramdisk/ramdisk.cpio.gz.uboot
319 20:53:29.240037 - {ROOT_PART}: None
320 20:53:29.240431 - {ROOT}: None
321 20:53:29.240815 - {SERVER_IP}: 192.168.6.2
322 20:53:29.241195 - {TEE_ADDR}: 0x83000000
323 20:53:29.241574 - {TEE}: None
324 20:53:29.241958 Parsed boot commands:
325 20:53:29.242332 - setenv autoload no
326 20:53:29.242714 - setenv initrd_high 0xffffffff
327 20:53:29.243097 - setenv fdt_high 0xffffffff
328 20:53:29.243476 - dhcp
329 20:53:29.243857 - setenv serverip 192.168.6.2
330 20:53:29.244268 - tftpboot 0x01080000 954555/tftp-deploy-gw9n9f0u/kernel/uImage
331 20:53:29.244659 - tftpboot 0x08000000 954555/tftp-deploy-gw9n9f0u/ramdisk/ramdisk.cpio.gz.uboot
332 20:53:29.245047 - tftpboot 0x01070000 954555/tftp-deploy-gw9n9f0u/dtb/meson-g12b-a311d-libretech-cc.dtb
333 20:53:29.245436 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/954555/extract-nfsrootfs-azqr57d2,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 20:53:29.245837 - bootm 0x01080000 0x08000000 0x01070000
335 20:53:29.246331 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 20:53:29.247797 start: 2.3 connect-device (timeout 00:05:00) [common]
338 20:53:29.248239 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 20:53:29.263454 Setting prompt string to ['lava-test: # ']
340 20:53:29.264981 end: 2.3 connect-device (duration 00:00:00) [common]
341 20:53:29.265592 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 20:53:29.266180 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 20:53:29.266930 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 20:53:29.268136 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 20:53:29.302857 >> OK - accepted request
346 20:53:29.304707 Returned 0 in 0 seconds
347 20:53:29.405851 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 20:53:29.407546 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 20:53:29.408135 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 20:53:29.408661 Setting prompt string to ['Hit any key to stop autoboot']
352 20:53:29.409112 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 20:53:29.410688 Trying 192.168.56.21...
354 20:53:29.411187 Connected to conserv1.
355 20:53:29.411595 Escape character is '^]'.
356 20:53:29.412043
357 20:53:29.412463 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 20:53:29.412885
359 20:53:41.006992 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 20:53:41.007663 bl2_stage_init 0x01
361 20:53:41.008151 bl2_stage_init 0x81
362 20:53:41.012636 hw id: 0x0000 - pwm id 0x01
363 20:53:41.013386 bl2_stage_init 0xc1
364 20:53:41.013947 bl2_stage_init 0x02
365 20:53:41.014512
366 20:53:41.018159 L0:00000000
367 20:53:41.018841 L1:20000703
368 20:53:41.019438 L2:00008067
369 20:53:41.020178 L3:14000000
370 20:53:41.023864 B2:00402000
371 20:53:41.024476 B1:e0f83180
372 20:53:41.024894
373 20:53:41.025298 TE: 58159
374 20:53:41.025701
375 20:53:41.029329 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 20:53:41.029900
377 20:53:41.030303 Board ID = 1
378 20:53:41.034856 Set A53 clk to 24M
379 20:53:41.035304 Set A73 clk to 24M
380 20:53:41.035703 Set clk81 to 24M
381 20:53:41.040409 A53 clk: 1200 MHz
382 20:53:41.040849 A73 clk: 1200 MHz
383 20:53:41.041242 CLK81: 166.6M
384 20:53:41.041631 smccc: 00012ab5
385 20:53:41.046040 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 20:53:41.051759 board id: 1
387 20:53:41.056861 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 20:53:41.068237 fw parse done
389 20:53:41.074395 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 20:53:41.116840 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 20:53:41.127868 PIEI prepare done
392 20:53:41.128480 fastboot data load
393 20:53:41.128894 fastboot data verify
394 20:53:41.133374 verify result: 266
395 20:53:41.138933 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 20:53:41.139395 LPDDR4 probe
397 20:53:41.139824 ddr clk to 1584MHz
398 20:53:41.146286 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 20:53:41.184256
400 20:53:41.184814 dmc_version 0001
401 20:53:41.190966 Check phy result
402 20:53:41.196818 INFO : End of CA training
403 20:53:41.197160 INFO : End of initialization
404 20:53:41.202364 INFO : Training has run successfully!
405 20:53:41.202864 Check phy result
406 20:53:41.207866 INFO : End of initialization
407 20:53:41.208370 INFO : End of read enable training
408 20:53:41.213517 INFO : End of fine write leveling
409 20:53:41.219142 INFO : End of Write leveling coarse delay
410 20:53:41.219623 INFO : Training has run successfully!
411 20:53:41.220071 Check phy result
412 20:53:41.224816 INFO : End of initialization
413 20:53:41.225329 INFO : End of read dq deskew training
414 20:53:41.230217 INFO : End of MPR read delay center optimization
415 20:53:41.235800 INFO : End of write delay center optimization
416 20:53:41.241524 INFO : End of read delay center optimization
417 20:53:41.242002 INFO : End of max read latency training
418 20:53:41.246993 INFO : Training has run successfully!
419 20:53:41.247448 1D training succeed
420 20:53:41.256250 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 20:53:41.304065 Check phy result
422 20:53:41.304794 INFO : End of initialization
423 20:53:41.326627 INFO : End of 2D read delay Voltage center optimization
424 20:53:41.346741 INFO : End of 2D read delay Voltage center optimization
425 20:53:41.398934 INFO : End of 2D write delay Voltage center optimization
426 20:53:41.448303 INFO : End of 2D write delay Voltage center optimization
427 20:53:41.453838 INFO : Training has run successfully!
428 20:53:41.454456
429 20:53:41.455035 channel==0
430 20:53:41.459311 RxClkDly_Margin_A0==88 ps 9
431 20:53:41.459896 TxDqDly_Margin_A0==98 ps 10
432 20:53:41.465030 RxClkDly_Margin_A1==88 ps 9
433 20:53:41.465760 TxDqDly_Margin_A1==98 ps 10
434 20:53:41.466371 TrainedVREFDQ_A0==74
435 20:53:41.470586 TrainedVREFDQ_A1==74
436 20:53:41.471224 VrefDac_Margin_A0==25
437 20:53:41.471747 DeviceVref_Margin_A0==40
438 20:53:41.476150 VrefDac_Margin_A1==25
439 20:53:41.476713 DeviceVref_Margin_A1==40
440 20:53:41.477231
441 20:53:41.477744
442 20:53:41.481831 channel==1
443 20:53:41.482382 RxClkDly_Margin_A0==98 ps 10
444 20:53:41.482899 TxDqDly_Margin_A0==98 ps 10
445 20:53:41.487295 RxClkDly_Margin_A1==98 ps 10
446 20:53:41.487855 TxDqDly_Margin_A1==88 ps 9
447 20:53:41.492908 TrainedVREFDQ_A0==77
448 20:53:41.493388 TrainedVREFDQ_A1==77
449 20:53:41.493801 VrefDac_Margin_A0==22
450 20:53:41.498681 DeviceVref_Margin_A0==37
451 20:53:41.499171 VrefDac_Margin_A1==22
452 20:53:41.504171 DeviceVref_Margin_A1==37
453 20:53:41.504620
454 20:53:41.505029 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 20:53:41.509855
456 20:53:41.537988 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
457 20:53:41.538802 2D training succeed
458 20:53:41.543414 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 20:53:41.549006 auto size-- 65535DDR cs0 size: 2048MB
460 20:53:41.549610 DDR cs1 size: 2048MB
461 20:53:41.554630 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 20:53:41.555200 cs0 DataBus test pass
463 20:53:41.560194 cs1 DataBus test pass
464 20:53:41.560763 cs0 AddrBus test pass
465 20:53:41.561286 cs1 AddrBus test pass
466 20:53:41.561798
467 20:53:41.565868 100bdlr_step_size ps== 420
468 20:53:41.566447 result report
469 20:53:41.571492 boot times 0Enable ddr reg access
470 20:53:41.576743 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 20:53:41.590191 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 20:53:42.164262 0.0;M3 CHK:0;cm4_sp_mode 0
473 20:53:42.164940 MVN_1=0x00000000
474 20:53:42.169530 MVN_2=0x00000000
475 20:53:42.175296 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 20:53:42.175822 OPS=0x10
477 20:53:42.176322 ring efuse init
478 20:53:42.176768 chipver efuse init
479 20:53:42.180864 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 20:53:42.186510 [0.018961 Inits done]
481 20:53:42.187047 secure task start!
482 20:53:42.187513 high task start!
483 20:53:42.190909 low task start!
484 20:53:42.191425 run into bl31
485 20:53:42.197849 NOTICE: BL31: v1.3(release):4fc40b1
486 20:53:42.205556 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 20:53:42.206098 NOTICE: BL31: G12A normal boot!
488 20:53:42.230901 NOTICE: BL31: BL33 decompress pass
489 20:53:42.236400 ERROR: Error initializing runtime service opteed_fast
490 20:53:43.469659
491 20:53:43.470342
492 20:53:43.477980 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 20:53:43.478540
494 20:53:43.479043 Model: Libre Computer AML-A311D-CC Alta
495 20:53:43.686731 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 20:53:43.709935 DRAM: 2 GiB (effective 3.8 GiB)
497 20:53:43.852778 Core: 408 devices, 31 uclasses, devicetree: separate
498 20:53:43.858761 WDT: Not starting watchdog@f0d0
499 20:53:43.890944 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 20:53:43.903407 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 20:53:43.908478 ** Bad device specification mmc 0 **
502 20:53:43.918709 Card did not respond to voltage select! : -110
503 20:53:43.926385 ** Bad device specification mmc 0 **
504 20:53:43.926906 Couldn't find partition mmc 0
505 20:53:43.934789 Card did not respond to voltage select! : -110
506 20:53:43.940244 ** Bad device specification mmc 0 **
507 20:53:43.940765 Couldn't find partition mmc 0
508 20:53:43.945322 Error: could not access storage.
509 20:53:45.207644 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 20:53:45.208385 bl2_stage_init 0x01
511 20:53:45.208875 bl2_stage_init 0x81
512 20:53:45.213286 hw id: 0x0000 - pwm id 0x01
513 20:53:45.213807 bl2_stage_init 0xc1
514 20:53:45.214272 bl2_stage_init 0x02
515 20:53:45.214722
516 20:53:45.218874 L0:00000000
517 20:53:45.219408 L1:20000703
518 20:53:45.219866 L2:00008067
519 20:53:45.220366 L3:14000000
520 20:53:45.224405 B2:00402000
521 20:53:45.224940 B1:e0f83180
522 20:53:45.225403
523 20:53:45.225860 TE: 58159
524 20:53:45.226312
525 20:53:45.230002 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 20:53:45.230512
527 20:53:45.230972 Board ID = 1
528 20:53:45.235633 Set A53 clk to 24M
529 20:53:45.236220 Set A73 clk to 24M
530 20:53:45.236702 Set clk81 to 24M
531 20:53:45.241203 A53 clk: 1200 MHz
532 20:53:45.241725 A73 clk: 1200 MHz
533 20:53:45.242189 CLK81: 166.6M
534 20:53:45.242644 smccc: 00012ab5
535 20:53:45.246741 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 20:53:45.252427 board id: 1
537 20:53:45.258292 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 20:53:45.268986 fw parse done
539 20:53:45.274991 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 20:53:45.317408 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 20:53:45.328271 PIEI prepare done
542 20:53:45.328789 fastboot data load
543 20:53:45.329254 fastboot data verify
544 20:53:45.333936 verify result: 266
545 20:53:45.339522 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 20:53:45.340078 LPDDR4 probe
547 20:53:45.340550 ddr clk to 1584MHz
548 20:53:45.347538 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 20:53:45.384770
550 20:53:45.385315 dmc_version 0001
551 20:53:45.391430 Check phy result
552 20:53:45.397294 INFO : End of CA training
553 20:53:45.397802 INFO : End of initialization
554 20:53:45.402922 INFO : Training has run successfully!
555 20:53:45.403458 Check phy result
556 20:53:45.408551 INFO : End of initialization
557 20:53:45.409064 INFO : End of read enable training
558 20:53:45.414145 INFO : End of fine write leveling
559 20:53:45.419709 INFO : End of Write leveling coarse delay
560 20:53:45.420256 INFO : Training has run successfully!
561 20:53:45.420716 Check phy result
562 20:53:45.425332 INFO : End of initialization
563 20:53:45.425839 INFO : End of read dq deskew training
564 20:53:45.430897 INFO : End of MPR read delay center optimization
565 20:53:45.436517 INFO : End of write delay center optimization
566 20:53:45.442104 INFO : End of read delay center optimization
567 20:53:45.442611 INFO : End of max read latency training
568 20:53:45.447711 INFO : Training has run successfully!
569 20:53:45.448263 1D training succeed
570 20:53:45.456857 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 20:53:45.504436 Check phy result
572 20:53:45.504827 INFO : End of initialization
573 20:53:45.526836 INFO : End of 2D read delay Voltage center optimization
574 20:53:45.547009 INFO : End of 2D read delay Voltage center optimization
575 20:53:45.598941 INFO : End of 2D write delay Voltage center optimization
576 20:53:45.648338 INFO : End of 2D write delay Voltage center optimization
577 20:53:45.653758 INFO : Training has run successfully!
578 20:53:45.654276
579 20:53:45.654757 channel==0
580 20:53:45.659360 RxClkDly_Margin_A0==88 ps 9
581 20:53:45.659869 TxDqDly_Margin_A0==98 ps 10
582 20:53:45.664984 RxClkDly_Margin_A1==88 ps 9
583 20:53:45.665504 TxDqDly_Margin_A1==98 ps 10
584 20:53:45.665972 TrainedVREFDQ_A0==74
585 20:53:45.670585 TrainedVREFDQ_A1==74
586 20:53:45.671113 VrefDac_Margin_A0==24
587 20:53:45.671582 DeviceVref_Margin_A0==40
588 20:53:45.676167 VrefDac_Margin_A1==25
589 20:53:45.676692 DeviceVref_Margin_A1==40
590 20:53:45.677152
591 20:53:45.677604
592 20:53:45.681770 channel==1
593 20:53:45.682284 RxClkDly_Margin_A0==98 ps 10
594 20:53:45.682743 TxDqDly_Margin_A0==98 ps 10
595 20:53:45.687373 RxClkDly_Margin_A1==98 ps 10
596 20:53:45.687880 TxDqDly_Margin_A1==88 ps 9
597 20:53:45.692951 TrainedVREFDQ_A0==77
598 20:53:45.693460 TrainedVREFDQ_A1==77
599 20:53:45.693919 VrefDac_Margin_A0==22
600 20:53:45.698581 DeviceVref_Margin_A0==37
601 20:53:45.699080 VrefDac_Margin_A1==22
602 20:53:45.704189 DeviceVref_Margin_A1==37
603 20:53:45.704711
604 20:53:45.705166 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 20:53:45.709773
606 20:53:45.737691 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
607 20:53:45.738258 2D training succeed
608 20:53:45.743447 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 20:53:45.748993 auto size-- 65535DDR cs0 size: 2048MB
610 20:53:45.749504 DDR cs1 size: 2048MB
611 20:53:45.754565 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 20:53:45.755072 cs0 DataBus test pass
613 20:53:45.760184 cs1 DataBus test pass
614 20:53:45.760695 cs0 AddrBus test pass
615 20:53:45.761151 cs1 AddrBus test pass
616 20:53:45.761596
617 20:53:45.765732 100bdlr_step_size ps== 420
618 20:53:45.766248 result report
619 20:53:45.771363 boot times 0Enable ddr reg access
620 20:53:45.775888 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 20:53:45.790241 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 20:53:46.362219 0.0;M3 CHK:0;cm4_sp_mode 0
623 20:53:46.362917 MVN_1=0x00000000
624 20:53:46.367735 MVN_2=0x00000000
625 20:53:46.373602 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 20:53:46.374142 OPS=0x10
627 20:53:46.374606 ring efuse init
628 20:53:46.375086 chipver efuse init
629 20:53:46.379037 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 20:53:46.384624 [0.018961 Inits done]
631 20:53:46.385131 secure task start!
632 20:53:46.385568 high task start!
633 20:53:46.389168 low task start!
634 20:53:46.389686 run into bl31
635 20:53:46.395865 NOTICE: BL31: v1.3(release):4fc40b1
636 20:53:46.403644 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 20:53:46.404186 NOTICE: BL31: G12A normal boot!
638 20:53:46.429017 NOTICE: BL31: BL33 decompress pass
639 20:53:46.434720 ERROR: Error initializing runtime service opteed_fast
640 20:53:47.667685
641 20:53:47.668411
642 20:53:47.676068 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 20:53:47.676601
644 20:53:47.677071 Model: Libre Computer AML-A311D-CC Alta
645 20:53:47.884431 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 20:53:47.907897 DRAM: 2 GiB (effective 3.8 GiB)
647 20:53:48.050898 Core: 408 devices, 31 uclasses, devicetree: separate
648 20:53:48.056731 WDT: Not starting watchdog@f0d0
649 20:53:48.088964 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 20:53:48.101403 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 20:53:48.106403 ** Bad device specification mmc 0 **
652 20:53:48.116803 Card did not respond to voltage select! : -110
653 20:53:48.124376 ** Bad device specification mmc 0 **
654 20:53:48.124885 Couldn't find partition mmc 0
655 20:53:48.132813 Card did not respond to voltage select! : -110
656 20:53:48.139119 ** Bad device specification mmc 0 **
657 20:53:48.139627 Couldn't find partition mmc 0
658 20:53:48.143144 Error: could not access storage.
659 20:53:48.486989 Net: eth0: ethernet@ff3f0000
660 20:53:48.487653 starting USB...
661 20:53:48.738672 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 20:53:48.739304 Starting the controller
663 20:53:48.745612 USB XHCI 1.10
664 20:53:50.456237 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 20:53:50.456952 bl2_stage_init 0x01
666 20:53:50.457445 bl2_stage_init 0x81
667 20:53:50.461648 hw id: 0x0000 - pwm id 0x01
668 20:53:50.462233 bl2_stage_init 0xc1
669 20:53:50.462715 bl2_stage_init 0x02
670 20:53:50.463172
671 20:53:50.467181 L0:00000000
672 20:53:50.467665 L1:20000703
673 20:53:50.468180 L2:00008067
674 20:53:50.468638 L3:14000000
675 20:53:50.470069 B2:00402000
676 20:53:50.470542 B1:e0f83180
677 20:53:50.470992
678 20:53:50.471439 TE: 58124
679 20:53:50.471883
680 20:53:50.481205 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 20:53:50.481711
682 20:53:50.482174 Board ID = 1
683 20:53:50.482623 Set A53 clk to 24M
684 20:53:50.483066 Set A73 clk to 24M
685 20:53:50.486879 Set clk81 to 24M
686 20:53:50.487361 A53 clk: 1200 MHz
687 20:53:50.487815 A73 clk: 1200 MHz
688 20:53:50.490292 CLK81: 166.6M
689 20:53:50.490781 smccc: 00012a92
690 20:53:50.495976 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 20:53:50.504104 board id: 1
692 20:53:50.507490 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 20:53:50.517949 fw parse done
694 20:53:50.523471 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 20:53:50.565973 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 20:53:50.576846 PIEI prepare done
697 20:53:50.577390 fastboot data load
698 20:53:50.577866 fastboot data verify
699 20:53:50.583136 verify result: 266
700 20:53:50.588088 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 20:53:50.588632 LPDDR4 probe
702 20:53:50.589258 ddr clk to 1584MHz
703 20:53:50.596107 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 20:53:50.633289
705 20:53:50.633836 dmc_version 0001
706 20:53:50.639887 Check phy result
707 20:53:50.645757 INFO : End of CA training
708 20:53:50.646250 INFO : End of initialization
709 20:53:50.651299 INFO : Training has run successfully!
710 20:53:50.651786 Check phy result
711 20:53:50.656952 INFO : End of initialization
712 20:53:50.657461 INFO : End of read enable training
713 20:53:50.662623 INFO : End of fine write leveling
714 20:53:50.668236 INFO : End of Write leveling coarse delay
715 20:53:50.668739 INFO : Training has run successfully!
716 20:53:50.669192 Check phy result
717 20:53:50.673761 INFO : End of initialization
718 20:53:50.674252 INFO : End of read dq deskew training
719 20:53:50.679496 INFO : End of MPR read delay center optimization
720 20:53:50.685029 INFO : End of write delay center optimization
721 20:53:50.690616 INFO : End of read delay center optimization
722 20:53:50.691110 INFO : End of max read latency training
723 20:53:50.696221 INFO : Training has run successfully!
724 20:53:50.696726 1D training succeed
725 20:53:50.705423 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 20:53:50.752998 Check phy result
727 20:53:50.753575 INFO : End of initialization
728 20:53:50.774633 INFO : End of 2D read delay Voltage center optimization
729 20:53:50.794386 INFO : End of 2D read delay Voltage center optimization
730 20:53:50.846944 INFO : End of 2D write delay Voltage center optimization
731 20:53:50.896261 INFO : End of 2D write delay Voltage center optimization
732 20:53:50.901900 INFO : Training has run successfully!
733 20:53:50.902390
734 20:53:50.902849 channel==0
735 20:53:50.907664 RxClkDly_Margin_A0==88 ps 9
736 20:53:50.908198 TxDqDly_Margin_A0==98 ps 10
737 20:53:50.911396 RxClkDly_Margin_A1==88 ps 9
738 20:53:50.911703 TxDqDly_Margin_A1==98 ps 10
739 20:53:50.916499 TrainedVREFDQ_A0==74
740 20:53:50.916829 TrainedVREFDQ_A1==74
741 20:53:50.917174 VrefDac_Margin_A0==25
742 20:53:50.921926 DeviceVref_Margin_A0==40
743 20:53:50.922250 VrefDac_Margin_A1==25
744 20:53:50.927553 DeviceVref_Margin_A1==40
745 20:53:50.927866
746 20:53:50.928143
747 20:53:50.928396 channel==1
748 20:53:50.928640 RxClkDly_Margin_A0==98 ps 10
749 20:53:50.933202 TxDqDly_Margin_A0==88 ps 9
750 20:53:50.933521 RxClkDly_Margin_A1==98 ps 10
751 20:53:50.938703 TxDqDly_Margin_A1==88 ps 9
752 20:53:50.939015 TrainedVREFDQ_A0==77
753 20:53:50.939263 TrainedVREFDQ_A1==77
754 20:53:50.944393 VrefDac_Margin_A0==22
755 20:53:50.944704 DeviceVref_Margin_A0==37
756 20:53:50.949916 VrefDac_Margin_A1==22
757 20:53:50.950242 DeviceVref_Margin_A1==37
758 20:53:50.950491
759 20:53:50.955554 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 20:53:50.955861
761 20:53:50.983576 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
762 20:53:50.989222 2D training succeed
763 20:53:50.994809 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 20:53:50.995207 auto size-- 65535DDR cs0 size: 2048MB
765 20:53:51.000422 DDR cs1 size: 2048MB
766 20:53:51.000826 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 20:53:51.006159 cs0 DataBus test pass
768 20:53:51.006573 cs1 DataBus test pass
769 20:53:51.006806 cs0 AddrBus test pass
770 20:53:51.011612 cs1 AddrBus test pass
771 20:53:51.012011
772 20:53:51.012257 100bdlr_step_size ps== 420
773 20:53:51.012487 result report
774 20:53:51.017340 boot times 0Enable ddr reg access
775 20:53:51.024895 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 20:53:51.038347 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 20:53:51.611835 0.0;M3 CHK:0;cm4_sp_mode 0
778 20:53:51.612283 MVN_1=0x00000000
779 20:53:51.617380 MVN_2=0x00000000
780 20:53:51.623277 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 20:53:51.623668 OPS=0x10
782 20:53:51.623915 ring efuse init
783 20:53:51.624186 chipver efuse init
784 20:53:51.631352 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 20:53:51.631679 [0.018961 Inits done]
786 20:53:51.638082 secure task start!
787 20:53:51.638452 high task start!
788 20:53:51.638687 low task start!
789 20:53:51.638915 run into bl31
790 20:53:51.645658 NOTICE: BL31: v1.3(release):4fc40b1
791 20:53:51.653406 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 20:53:51.653782 NOTICE: BL31: G12A normal boot!
793 20:53:51.678763 NOTICE: BL31: BL33 decompress pass
794 20:53:51.683506 ERROR: Error initializing runtime service opteed_fast
795 20:53:52.917335
796 20:53:52.917778
797 20:53:52.925811 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 20:53:52.926174
799 20:53:52.926432 Model: Libre Computer AML-A311D-CC Alta
800 20:53:53.133783 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 20:53:53.157692 DRAM: 2 GiB (effective 3.8 GiB)
802 20:53:53.300633 Core: 408 devices, 31 uclasses, devicetree: separate
803 20:53:53.306690 WDT: Not starting watchdog@f0d0
804 20:53:53.338907 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 20:53:53.351378 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 20:53:53.356254 ** Bad device specification mmc 0 **
807 20:53:53.366571 Card did not respond to voltage select! : -110
808 20:53:53.374130 ** Bad device specification mmc 0 **
809 20:53:53.374619 Couldn't find partition mmc 0
810 20:53:53.382470 Card did not respond to voltage select! : -110
811 20:53:53.387969 ** Bad device specification mmc 0 **
812 20:53:53.388450 Couldn't find partition mmc 0
813 20:53:53.393028 Error: could not access storage.
814 20:53:53.735794 Net: eth0: ethernet@ff3f0000
815 20:53:53.736483 starting USB...
816 20:53:53.987430 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 20:53:53.988109 Starting the controller
818 20:53:53.994278 USB XHCI 1.10
819 20:53:56.156407 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 20:53:56.157056 bl2_stage_init 0x01
821 20:53:56.157475 bl2_stage_init 0x81
822 20:53:56.162247 hw id: 0x0000 - pwm id 0x01
823 20:53:56.162769 bl2_stage_init 0xc1
824 20:53:56.163195 bl2_stage_init 0x02
825 20:53:56.163608
826 20:53:56.167378 L0:00000000
827 20:53:56.167831 L1:20000703
828 20:53:56.168272 L2:00008067
829 20:53:56.168677 L3:14000000
830 20:53:56.170379 B2:00402000
831 20:53:56.170806 B1:e0f83180
832 20:53:56.171211
833 20:53:56.171614 TE: 58124
834 20:53:56.172050
835 20:53:56.181592 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 20:53:56.182162
837 20:53:56.182588 Board ID = 1
838 20:53:56.182998 Set A53 clk to 24M
839 20:53:56.183399 Set A73 clk to 24M
840 20:53:56.187147 Set clk81 to 24M
841 20:53:56.187612 A53 clk: 1200 MHz
842 20:53:56.188049 A73 clk: 1200 MHz
843 20:53:56.192559 CLK81: 166.6M
844 20:53:56.193007 smccc: 00012a92
845 20:53:56.198188 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 20:53:56.198658 board id: 1
847 20:53:56.205802 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 20:53:56.217414 fw parse done
849 20:53:56.223335 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 20:53:56.266008 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 20:53:56.276919 PIEI prepare done
852 20:53:56.277409 fastboot data load
853 20:53:56.277917 fastboot data verify
854 20:53:56.284470 verify result: 266
855 20:53:56.288316 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 20:53:56.288834 LPDDR4 probe
857 20:53:56.289253 ddr clk to 1584MHz
858 20:53:56.296236 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 20:53:56.333479
860 20:53:56.334024 dmc_version 0001
861 20:53:56.340137 Check phy result
862 20:53:56.345954 INFO : End of CA training
863 20:53:56.346444 INFO : End of initialization
864 20:53:56.351591 INFO : Training has run successfully!
865 20:53:56.352105 Check phy result
866 20:53:56.357208 INFO : End of initialization
867 20:53:56.357695 INFO : End of read enable training
868 20:53:56.362758 INFO : End of fine write leveling
869 20:53:56.368339 INFO : End of Write leveling coarse delay
870 20:53:56.368841 INFO : Training has run successfully!
871 20:53:56.369264 Check phy result
872 20:53:56.373955 INFO : End of initialization
873 20:53:56.374428 INFO : End of read dq deskew training
874 20:53:56.379632 INFO : End of MPR read delay center optimization
875 20:53:56.385200 INFO : End of write delay center optimization
876 20:53:56.390766 INFO : End of read delay center optimization
877 20:53:56.391252 INFO : End of max read latency training
878 20:53:56.396392 INFO : Training has run successfully!
879 20:53:56.396885 1D training succeed
880 20:53:56.404581 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 20:53:56.452251 Check phy result
882 20:53:56.452783 INFO : End of initialization
883 20:53:56.474214 INFO : End of 2D read delay Voltage center optimization
884 20:53:56.494301 INFO : End of 2D read delay Voltage center optimization
885 20:53:56.546398 INFO : End of 2D write delay Voltage center optimization
886 20:53:56.597113 INFO : End of 2D write delay Voltage center optimization
887 20:53:56.602264 INFO : Training has run successfully!
888 20:53:56.602891
889 20:53:56.603340 channel==0
890 20:53:56.607830 RxClkDly_Margin_A0==88 ps 9
891 20:53:56.608380 TxDqDly_Margin_A0==98 ps 10
892 20:53:56.613354 RxClkDly_Margin_A1==88 ps 9
893 20:53:56.613849 TxDqDly_Margin_A1==98 ps 10
894 20:53:56.614294 TrainedVREFDQ_A0==74
895 20:53:56.619044 TrainedVREFDQ_A1==74
896 20:53:56.619623 VrefDac_Margin_A0==25
897 20:53:56.620100 DeviceVref_Margin_A0==40
898 20:53:56.624570 VrefDac_Margin_A1==25
899 20:53:56.625112 DeviceVref_Margin_A1==40
900 20:53:56.625510
901 20:53:56.625907
902 20:53:56.630221 channel==1
903 20:53:56.630684 RxClkDly_Margin_A0==98 ps 10
904 20:53:56.631083 TxDqDly_Margin_A0==88 ps 9
905 20:53:56.635815 RxClkDly_Margin_A1==98 ps 10
906 20:53:56.636303 TxDqDly_Margin_A1==98 ps 10
907 20:53:56.641365 TrainedVREFDQ_A0==77
908 20:53:56.641841 TrainedVREFDQ_A1==77
909 20:53:56.642240 VrefDac_Margin_A0==22
910 20:53:56.647006 DeviceVref_Margin_A0==37
911 20:53:56.647443 VrefDac_Margin_A1==22
912 20:53:56.652529 DeviceVref_Margin_A1==37
913 20:53:56.652967
914 20:53:56.653362 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 20:53:56.658215
916 20:53:56.686288 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 0000005f
917 20:53:56.686785 2D training succeed
918 20:53:56.691708 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 20:53:56.697343 auto size-- 65535DDR cs0 size: 2048MB
920 20:53:56.697708 DDR cs1 size: 2048MB
921 20:53:56.703004 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 20:53:56.703324 cs0 DataBus test pass
923 20:53:56.708474 cs1 DataBus test pass
924 20:53:56.708767 cs0 AddrBus test pass
925 20:53:56.708990 cs1 AddrBus test pass
926 20:53:56.709215
927 20:53:56.714153 100bdlr_step_size ps== 420
928 20:53:56.714465 result report
929 20:53:56.719837 boot times 0Enable ddr reg access
930 20:53:56.724325 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 20:53:56.737825 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 20:53:57.312353 0.0;M3 CHK:0;cm4_sp_mode 0
933 20:53:57.312980 MVN_1=0x00000000
934 20:53:57.317849 MVN_2=0x00000000
935 20:53:57.323630 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 20:53:57.324236 OPS=0x10
937 20:53:57.324672 ring efuse init
938 20:53:57.325083 chipver efuse init
939 20:53:57.329319 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 20:53:57.334822 [0.018960 Inits done]
941 20:53:57.335179 secure task start!
942 20:53:57.335617 high task start!
943 20:53:57.338411 low task start!
944 20:53:57.338895 run into bl31
945 20:53:57.346061 NOTICE: BL31: v1.3(release):4fc40b1
946 20:53:57.352966 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 20:53:57.353551 NOTICE: BL31: G12A normal boot!
948 20:53:57.379458 NOTICE: BL31: BL33 decompress pass
949 20:53:57.384057 ERROR: Error initializing runtime service opteed_fast
950 20:53:58.617763
951 20:53:58.618354
952 20:53:58.626287 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 20:53:58.626758
954 20:53:58.627197 Model: Libre Computer AML-A311D-CC Alta
955 20:53:58.834677 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 20:53:58.857985 DRAM: 2 GiB (effective 3.8 GiB)
957 20:53:59.001144 Core: 408 devices, 31 uclasses, devicetree: separate
958 20:53:59.006809 WDT: Not starting watchdog@f0d0
959 20:53:59.039226 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 20:53:59.051569 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 20:53:59.056566 ** Bad device specification mmc 0 **
962 20:53:59.066872 Card did not respond to voltage select! : -110
963 20:53:59.074508 ** Bad device specification mmc 0 **
964 20:53:59.074972 Couldn't find partition mmc 0
965 20:53:59.082860 Card did not respond to voltage select! : -110
966 20:53:59.088346 ** Bad device specification mmc 0 **
967 20:53:59.088802 Couldn't find partition mmc 0
968 20:53:59.093423 Error: could not access storage.
969 20:53:59.437078 Net: eth0: ethernet@ff3f0000
970 20:53:59.437707 starting USB...
971 20:53:59.688751 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 20:53:59.689367 Starting the controller
973 20:53:59.695743 USB XHCI 1.10
974 20:54:01.556295 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 20:54:01.556740 bl2_stage_init 0x01
976 20:54:01.556981 bl2_stage_init 0x81
977 20:54:01.561800 hw id: 0x0000 - pwm id 0x01
978 20:54:01.562136 bl2_stage_init 0xc1
979 20:54:01.562366 bl2_stage_init 0x02
980 20:54:01.562583
981 20:54:01.567443 L0:00000000
982 20:54:01.567876 L1:20000703
983 20:54:01.568262 L2:00008067
984 20:54:01.568588 L3:14000000
985 20:54:01.573021 B2:00402000
986 20:54:01.573473 B1:e0f83180
987 20:54:01.573831
988 20:54:01.574183 TE: 58124
989 20:54:01.574440
990 20:54:01.578590 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 20:54:01.579093
992 20:54:01.579456 Board ID = 1
993 20:54:01.584153 Set A53 clk to 24M
994 20:54:01.584464 Set A73 clk to 24M
995 20:54:01.584686 Set clk81 to 24M
996 20:54:01.589768 A53 clk: 1200 MHz
997 20:54:01.590200 A73 clk: 1200 MHz
998 20:54:01.590552 CLK81: 166.6M
999 20:54:01.590899 smccc: 00012a92
1000 20:54:01.595387 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 20:54:01.600901 board id: 1
1002 20:54:01.607014 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 20:54:01.617405 fw parse done
1004 20:54:01.623442 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 20:54:01.666046 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 20:54:01.676916 PIEI prepare done
1007 20:54:01.677369 fastboot data load
1008 20:54:01.677775 fastboot data verify
1009 20:54:01.682524 verify result: 266
1010 20:54:01.688155 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 20:54:01.688628 LPDDR4 probe
1012 20:54:01.689030 ddr clk to 1584MHz
1013 20:54:01.696125 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 20:54:01.733447
1015 20:54:01.734021 dmc_version 0001
1016 20:54:01.740136 Check phy result
1017 20:54:01.745936 INFO : End of CA training
1018 20:54:01.746425 INFO : End of initialization
1019 20:54:01.751487 INFO : Training has run successfully!
1020 20:54:01.751950 Check phy result
1021 20:54:01.757199 INFO : End of initialization
1022 20:54:01.757697 INFO : End of read enable training
1023 20:54:01.762735 INFO : End of fine write leveling
1024 20:54:01.768371 INFO : End of Write leveling coarse delay
1025 20:54:01.768834 INFO : Training has run successfully!
1026 20:54:01.769260 Check phy result
1027 20:54:01.773944 INFO : End of initialization
1028 20:54:01.774408 INFO : End of read dq deskew training
1029 20:54:01.779551 INFO : End of MPR read delay center optimization
1030 20:54:01.785146 INFO : End of write delay center optimization
1031 20:54:01.790802 INFO : End of read delay center optimization
1032 20:54:01.791262 INFO : End of max read latency training
1033 20:54:01.796332 INFO : Training has run successfully!
1034 20:54:01.796800 1D training succeed
1035 20:54:01.805609 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 20:54:01.853205 Check phy result
1037 20:54:01.853784 INFO : End of initialization
1038 20:54:01.874880 INFO : End of 2D read delay Voltage center optimization
1039 20:54:01.894306 INFO : End of 2D read delay Voltage center optimization
1040 20:54:01.946408 INFO : End of 2D write delay Voltage center optimization
1041 20:54:01.995601 INFO : End of 2D write delay Voltage center optimization
1042 20:54:02.001257 INFO : Training has run successfully!
1043 20:54:02.001731
1044 20:54:02.002156 channel==0
1045 20:54:02.006859 RxClkDly_Margin_A0==88 ps 9
1046 20:54:02.007333 TxDqDly_Margin_A0==98 ps 10
1047 20:54:02.010127 RxClkDly_Margin_A1==88 ps 9
1048 20:54:02.010583 TxDqDly_Margin_A1==98 ps 10
1049 20:54:02.015855 TrainedVREFDQ_A0==74
1050 20:54:02.016418 TrainedVREFDQ_A1==75
1051 20:54:02.016846 VrefDac_Margin_A0==25
1052 20:54:02.021446 DeviceVref_Margin_A0==40
1053 20:54:02.021940 VrefDac_Margin_A1==25
1054 20:54:02.027102 DeviceVref_Margin_A1==39
1055 20:54:02.027575
1056 20:54:02.028023
1057 20:54:02.028443 channel==1
1058 20:54:02.028850 RxClkDly_Margin_A0==88 ps 9
1059 20:54:02.032609 TxDqDly_Margin_A0==98 ps 10
1060 20:54:02.033084 RxClkDly_Margin_A1==88 ps 9
1061 20:54:02.038063 TxDqDly_Margin_A1==88 ps 9
1062 20:54:02.038519 TrainedVREFDQ_A0==77
1063 20:54:02.038934 TrainedVREFDQ_A1==77
1064 20:54:02.043919 VrefDac_Margin_A0==23
1065 20:54:02.044400 DeviceVref_Margin_A0==37
1066 20:54:02.049286 VrefDac_Margin_A1==24
1067 20:54:02.049738 DeviceVref_Margin_A1==37
1068 20:54:02.050146
1069 20:54:02.054876 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 20:54:02.055325
1071 20:54:02.091029 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000019 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 00000019 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
1072 20:54:02.091557 2D training succeed
1073 20:54:02.092019 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 20:54:02.096561 auto size-- 65535DDR cs0 size: 2048MB
1075 20:54:02.097015 DDR cs1 size: 2048MB
1076 20:54:02.102196 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 20:54:02.102651 cs0 DataBus test pass
1078 20:54:02.107799 cs1 DataBus test pass
1079 20:54:02.108316 cs0 AddrBus test pass
1080 20:54:02.108737 cs1 AddrBus test pass
1081 20:54:02.109146
1082 20:54:02.111217 100bdlr_step_size ps== 420
1083 20:54:02.111565 result report
1084 20:54:02.116816 boot times 0Enable ddr reg access
1085 20:54:02.124034 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 20:54:02.137528 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 20:54:02.711548 0.0;M3 CHK:0;cm4_sp_mode 0
1088 20:54:02.712228 MVN_1=0x00000000
1089 20:54:02.716902 MVN_2=0x00000000
1090 20:54:02.722535 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 20:54:02.722990 OPS=0x10
1092 20:54:02.723410 ring efuse init
1093 20:54:02.723823 chipver efuse init
1094 20:54:02.731000 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 20:54:02.731472 [0.018960 Inits done]
1096 20:54:02.731886 secure task start!
1097 20:54:02.738398 high task start!
1098 20:54:02.738840 low task start!
1099 20:54:02.739255 run into bl31
1100 20:54:02.744914 NOTICE: BL31: v1.3(release):4fc40b1
1101 20:54:02.752900 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 20:54:02.753375 NOTICE: BL31: G12A normal boot!
1103 20:54:02.778327 NOTICE: BL31: BL33 decompress pass
1104 20:54:02.784066 ERROR: Error initializing runtime service opteed_fast
1105 20:54:04.016894
1106 20:54:04.017338
1107 20:54:04.025291 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 20:54:04.025790
1109 20:54:04.026169 Model: Libre Computer AML-A311D-CC Alta
1110 20:54:04.232795 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 20:54:04.257091 DRAM: 2 GiB (effective 3.8 GiB)
1112 20:54:04.400218 Core: 408 devices, 31 uclasses, devicetree: separate
1113 20:54:04.405978 WDT: Not starting watchdog@f0d0
1114 20:54:04.438232 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 20:54:04.450649 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 20:54:04.455665 ** Bad device specification mmc 0 **
1117 20:54:04.465867 Card did not respond to voltage select! : -110
1118 20:54:04.473625 ** Bad device specification mmc 0 **
1119 20:54:04.473932 Couldn't find partition mmc 0
1120 20:54:04.481935 Card did not respond to voltage select! : -110
1121 20:54:04.487380 ** Bad device specification mmc 0 **
1122 20:54:04.487776 Couldn't find partition mmc 0
1123 20:54:04.492544 Error: could not access storage.
1124 20:54:04.835150 Net: eth0: ethernet@ff3f0000
1125 20:54:04.835578 starting USB...
1126 20:54:05.086859 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 20:54:05.087459 Starting the controller
1128 20:54:05.092930 USB XHCI 1.10
1129 20:54:06.647864 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 20:54:06.655968 scanning usb for storage devices... 0 Storage Device(s) found
1132 20:54:06.707121 Hit any key to stop autoboot: 1
1133 20:54:06.707785 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 20:54:06.708185 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 20:54:06.708472 Setting prompt string to ['=>']
1136 20:54:06.708748 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 20:54:06.713577 0
1138 20:54:06.714196 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 20:54:06.714488 Sending with 10 millisecond of delay
1141 20:54:07.849347 => setenv autoload no
1142 20:54:07.860180 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1143 20:54:07.865064 setenv autoload no
1144 20:54:07.865820 Sending with 10 millisecond of delay
1146 20:54:09.663142 => setenv initrd_high 0xffffffff
1147 20:54:09.673929 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 20:54:09.674859 setenv initrd_high 0xffffffff
1149 20:54:09.675584 Sending with 10 millisecond of delay
1151 20:54:11.292079 => setenv fdt_high 0xffffffff
1152 20:54:11.302833 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 20:54:11.303437 setenv fdt_high 0xffffffff
1154 20:54:11.304006 Sending with 10 millisecond of delay
1156 20:54:11.596522 => dhcp
1157 20:54:11.607294 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 20:54:11.608144 dhcp
1159 20:54:11.608598 Speed: 1000, full duplex
1160 20:54:11.609018 BOOTP broadcast 1
1161 20:54:11.615054 DHCP client bound to address 192.168.6.27 (8 ms)
1162 20:54:11.615752 Sending with 10 millisecond of delay
1164 20:54:13.292582 => setenv serverip 192.168.6.2
1165 20:54:13.304596 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1166 20:54:13.305183 setenv serverip 192.168.6.2
1167 20:54:13.305677 Sending with 10 millisecond of delay
1169 20:54:17.029864 => tftpboot 0x01080000 954555/tftp-deploy-gw9n9f0u/kernel/uImage
1170 20:54:17.040463 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1171 20:54:17.041022 tftpboot 0x01080000 954555/tftp-deploy-gw9n9f0u/kernel/uImage
1172 20:54:17.041357 Speed: 1000, full duplex
1173 20:54:17.041679 Using ethernet@ff3f0000 device
1174 20:54:17.043077 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 20:54:17.048708 Filename '954555/tftp-deploy-gw9n9f0u/kernel/uImage'.
1176 20:54:17.051968 Load address: 0x1080000
1177 20:54:20.054233 Loading: *################################################## 43.6 MiB
1178 20:54:20.054896 14.5 MiB/s
1179 20:54:20.055359 done
1180 20:54:20.058281 Bytes transferred = 45713984 (2b98a40 hex)
1181 20:54:20.059058 Sending with 10 millisecond of delay
1183 20:54:24.749253 => tftpboot 0x08000000 954555/tftp-deploy-gw9n9f0u/ramdisk/ramdisk.cpio.gz.uboot
1184 20:54:24.760114 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1185 20:54:24.761010 tftpboot 0x08000000 954555/tftp-deploy-gw9n9f0u/ramdisk/ramdisk.cpio.gz.uboot
1186 20:54:24.761497 Speed: 1000, full duplex
1187 20:54:24.761952 Using ethernet@ff3f0000 device
1188 20:54:24.763114 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 20:54:24.771651 Filename '954555/tftp-deploy-gw9n9f0u/ramdisk/ramdisk.cpio.gz.uboot'.
1190 20:54:24.772263 Load address: 0x8000000
1191 20:54:31.965684 Loading: *#############T #################################### UDP wrong checksum 00000005 000017a0
1192 20:54:36.966519 T UDP wrong checksum 00000005 000017a0
1193 20:54:38.855728 UDP wrong checksum 000000ff 00002735
1194 20:54:38.865329 UDP wrong checksum 000000ff 0000bc27
1195 20:54:46.969619 T T UDP wrong checksum 00000005 000017a0
1196 20:54:58.095347 T T UDP wrong checksum 000000ff 00002ce9
1197 20:54:58.108217 UDP wrong checksum 000000ff 0000c2db
1198 20:55:03.579621 T UDP wrong checksum 000000ff 0000e37a
1199 20:55:03.629557 UDP wrong checksum 000000ff 00007f6d
1200 20:55:06.973118 UDP wrong checksum 00000005 000017a0
1201 20:55:12.030603 T T UDP wrong checksum 000000ff 000021e4
1202 20:55:12.046509 UDP wrong checksum 000000ff 0000aad6
1203 20:55:21.979221 T
1204 20:55:21.979918 Retry count exceeded; starting again
1206 20:55:21.981555 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1209 20:55:21.983589 end: 2.4 uboot-commands (duration 00:01:53) [common]
1211 20:55:21.985261 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1213 20:55:21.986504 end: 2 uboot-action (duration 00:01:53) [common]
1215 20:55:21.988247 Cleaning after the job
1216 20:55:21.988893 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954555/tftp-deploy-gw9n9f0u/ramdisk
1217 20:55:21.990363 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954555/tftp-deploy-gw9n9f0u/kernel
1218 20:55:22.039936 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954555/tftp-deploy-gw9n9f0u/dtb
1219 20:55:22.040874 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954555/tftp-deploy-gw9n9f0u/nfsrootfs
1220 20:55:22.080616 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954555/tftp-deploy-gw9n9f0u/modules
1221 20:55:22.084439 start: 4.1 power-off (timeout 00:00:30) [common]
1222 20:55:22.085002 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1223 20:55:22.119932 >> OK - accepted request
1224 20:55:22.122146 Returned 0 in 0 seconds
1225 20:55:22.222940 end: 4.1 power-off (duration 00:00:00) [common]
1227 20:55:22.223886 start: 4.2 read-feedback (timeout 00:10:00) [common]
1228 20:55:22.224566 Listened to connection for namespace 'common' for up to 1s
1229 20:55:23.225544 Finalising connection for namespace 'common'
1230 20:55:23.226298 Disconnecting from shell: Finalise
1231 20:55:23.226828 =>
1232 20:55:23.327910 end: 4.2 read-feedback (duration 00:00:01) [common]
1233 20:55:23.328643 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/954555
1234 20:55:26.288639 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/954555
1235 20:55:26.289249 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.