Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:48:28.311195 lava-dispatcher, installed at version: 2024.01
2 20:48:28.312016 start: 0 validate
3 20:48:28.312504 Start time: 2024-11-07 20:48:28.312474+00:00 (UTC)
4 20:48:28.313045 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:48:28.313606 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 20:48:28.353260 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:48:28.353814 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-8-g23569c8b31492%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 20:48:28.386532 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:48:28.387161 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-8-g23569c8b31492%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 20:48:28.420651 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:48:28.421150 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 20:48:28.454256 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 20:48:28.454759 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-linus%2Fasoc-fix-v6.12-rc5-8-g23569c8b31492%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 20:48:28.491593 validate duration: 0.18
16 20:48:28.492469 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 20:48:28.492795 start: 1.1 download-retry (timeout 00:10:00) [common]
18 20:48:28.493118 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 20:48:28.493711 Not decompressing ramdisk as can be used compressed.
20 20:48:28.494161 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 20:48:28.494446 saving as /var/lib/lava/dispatcher/tmp/954544/tftp-deploy-dz0qxhzx/ramdisk/initrd.cpio.gz
22 20:48:28.494719 total size: 5628140 (5 MB)
23 20:48:28.534983 progress 0 % (0 MB)
24 20:48:28.541271 progress 5 % (0 MB)
25 20:48:28.548957 progress 10 % (0 MB)
26 20:48:28.555862 progress 15 % (0 MB)
27 20:48:28.561822 progress 20 % (1 MB)
28 20:48:28.565373 progress 25 % (1 MB)
29 20:48:28.569424 progress 30 % (1 MB)
30 20:48:28.573550 progress 35 % (1 MB)
31 20:48:28.577096 progress 40 % (2 MB)
32 20:48:28.581045 progress 45 % (2 MB)
33 20:48:28.584549 progress 50 % (2 MB)
34 20:48:28.588488 progress 55 % (2 MB)
35 20:48:28.592416 progress 60 % (3 MB)
36 20:48:28.595974 progress 65 % (3 MB)
37 20:48:28.599902 progress 70 % (3 MB)
38 20:48:28.603607 progress 75 % (4 MB)
39 20:48:28.607539 progress 80 % (4 MB)
40 20:48:28.611083 progress 85 % (4 MB)
41 20:48:28.615051 progress 90 % (4 MB)
42 20:48:28.618735 progress 95 % (5 MB)
43 20:48:28.622096 progress 100 % (5 MB)
44 20:48:28.622848 5 MB downloaded in 0.13 s (41.90 MB/s)
45 20:48:28.623470 end: 1.1.1 http-download (duration 00:00:00) [common]
47 20:48:28.624517 end: 1.1 download-retry (duration 00:00:00) [common]
48 20:48:28.624888 start: 1.2 download-retry (timeout 00:10:00) [common]
49 20:48:28.625223 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 20:48:28.625710 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-8-g23569c8b31492/arm64/defconfig/gcc-12/kernel/Image
51 20:48:28.625954 saving as /var/lib/lava/dispatcher/tmp/954544/tftp-deploy-dz0qxhzx/kernel/Image
52 20:48:28.626169 total size: 45713920 (43 MB)
53 20:48:28.626381 No compression specified
54 20:48:28.664092 progress 0 % (0 MB)
55 20:48:28.693619 progress 5 % (2 MB)
56 20:48:28.723076 progress 10 % (4 MB)
57 20:48:28.753143 progress 15 % (6 MB)
58 20:48:28.782365 progress 20 % (8 MB)
59 20:48:28.812075 progress 25 % (10 MB)
60 20:48:28.841812 progress 30 % (13 MB)
61 20:48:28.870904 progress 35 % (15 MB)
62 20:48:28.899665 progress 40 % (17 MB)
63 20:48:28.928403 progress 45 % (19 MB)
64 20:48:28.957408 progress 50 % (21 MB)
65 20:48:28.986598 progress 55 % (24 MB)
66 20:48:29.016388 progress 60 % (26 MB)
67 20:48:29.045362 progress 65 % (28 MB)
68 20:48:29.074521 progress 70 % (30 MB)
69 20:48:29.103816 progress 75 % (32 MB)
70 20:48:29.134050 progress 80 % (34 MB)
71 20:48:29.162858 progress 85 % (37 MB)
72 20:48:29.191858 progress 90 % (39 MB)
73 20:48:29.220763 progress 95 % (41 MB)
74 20:48:29.249462 progress 100 % (43 MB)
75 20:48:29.250006 43 MB downloaded in 0.62 s (69.89 MB/s)
76 20:48:29.250483 end: 1.2.1 http-download (duration 00:00:01) [common]
78 20:48:29.251294 end: 1.2 download-retry (duration 00:00:01) [common]
79 20:48:29.251567 start: 1.3 download-retry (timeout 00:09:59) [common]
80 20:48:29.251835 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 20:48:29.252331 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-8-g23569c8b31492/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 20:48:29.252664 saving as /var/lib/lava/dispatcher/tmp/954544/tftp-deploy-dz0qxhzx/dtb/meson-g12b-a311d-libretech-cc.dtb
83 20:48:29.252881 total size: 54703 (0 MB)
84 20:48:29.253088 No compression specified
85 20:48:29.290311 progress 59 % (0 MB)
86 20:48:29.292158 progress 100 % (0 MB)
87 20:48:29.292852 0 MB downloaded in 0.04 s (1.31 MB/s)
88 20:48:29.293433 end: 1.3.1 http-download (duration 00:00:00) [common]
90 20:48:29.294428 end: 1.3 download-retry (duration 00:00:00) [common]
91 20:48:29.294746 start: 1.4 download-retry (timeout 00:09:59) [common]
92 20:48:29.295070 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 20:48:29.295627 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 20:48:29.295924 saving as /var/lib/lava/dispatcher/tmp/954544/tftp-deploy-dz0qxhzx/nfsrootfs/full.rootfs.tar
95 20:48:29.296311 total size: 474398908 (452 MB)
96 20:48:29.296575 Using unxz to decompress xz
97 20:48:29.337437 progress 0 % (0 MB)
98 20:48:30.444666 progress 5 % (22 MB)
99 20:48:31.884810 progress 10 % (45 MB)
100 20:48:32.320660 progress 15 % (67 MB)
101 20:48:33.090621 progress 20 % (90 MB)
102 20:48:33.630295 progress 25 % (113 MB)
103 20:48:33.984220 progress 30 % (135 MB)
104 20:48:34.602532 progress 35 % (158 MB)
105 20:48:35.527701 progress 40 % (181 MB)
106 20:48:36.397999 progress 45 % (203 MB)
107 20:48:36.949828 progress 50 % (226 MB)
108 20:48:37.594544 progress 55 % (248 MB)
109 20:48:38.813770 progress 60 % (271 MB)
110 20:48:40.303394 progress 65 % (294 MB)
111 20:48:41.969432 progress 70 % (316 MB)
112 20:48:45.090829 progress 75 % (339 MB)
113 20:48:47.524810 progress 80 % (361 MB)
114 20:48:50.439770 progress 85 % (384 MB)
115 20:48:53.634917 progress 90 % (407 MB)
116 20:48:56.953593 progress 95 % (429 MB)
117 20:49:00.233667 progress 100 % (452 MB)
118 20:49:00.246696 452 MB downloaded in 30.95 s (14.62 MB/s)
119 20:49:00.247347 end: 1.4.1 http-download (duration 00:00:31) [common]
121 20:49:00.248262 end: 1.4 download-retry (duration 00:00:31) [common]
122 20:49:00.248557 start: 1.5 download-retry (timeout 00:09:28) [common]
123 20:49:00.248846 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 20:49:00.249487 downloading http://storage.kernelci.org/broonie-sound/for-linus/asoc-fix-v6.12-rc5-8-g23569c8b31492/arm64/defconfig/gcc-12/modules.tar.xz
125 20:49:00.249799 saving as /var/lib/lava/dispatcher/tmp/954544/tftp-deploy-dz0qxhzx/modules/modules.tar
126 20:49:00.250013 total size: 11608504 (11 MB)
127 20:49:00.250234 Using unxz to decompress xz
128 20:49:00.297230 progress 0 % (0 MB)
129 20:49:00.365857 progress 5 % (0 MB)
130 20:49:00.443997 progress 10 % (1 MB)
131 20:49:00.545074 progress 15 % (1 MB)
132 20:49:00.639293 progress 20 % (2 MB)
133 20:49:00.719612 progress 25 % (2 MB)
134 20:49:00.796857 progress 30 % (3 MB)
135 20:49:00.872829 progress 35 % (3 MB)
136 20:49:00.951796 progress 40 % (4 MB)
137 20:49:01.029766 progress 45 % (5 MB)
138 20:49:01.116115 progress 50 % (5 MB)
139 20:49:01.195169 progress 55 % (6 MB)
140 20:49:01.286609 progress 60 % (6 MB)
141 20:49:01.381502 progress 65 % (7 MB)
142 20:49:01.459881 progress 70 % (7 MB)
143 20:49:01.543150 progress 75 % (8 MB)
144 20:49:01.628732 progress 80 % (8 MB)
145 20:49:01.710972 progress 85 % (9 MB)
146 20:49:01.791350 progress 90 % (9 MB)
147 20:49:01.870949 progress 95 % (10 MB)
148 20:49:01.949298 progress 100 % (11 MB)
149 20:49:01.960784 11 MB downloaded in 1.71 s (6.47 MB/s)
150 20:49:01.961399 end: 1.5.1 http-download (duration 00:00:02) [common]
152 20:49:01.962224 end: 1.5 download-retry (duration 00:00:02) [common]
153 20:49:01.962489 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 20:49:01.962753 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 20:49:20.661904 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/954544/extract-nfsrootfs-e3r6ic07
156 20:49:20.662503 end: 1.6.1 extract-nfsrootfs (duration 00:00:19) [common]
157 20:49:20.662797 start: 1.6.2 lava-overlay (timeout 00:09:08) [common]
158 20:49:20.663620 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg
159 20:49:20.664141 makedir: /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin
160 20:49:20.664509 makedir: /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/tests
161 20:49:20.664871 makedir: /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/results
162 20:49:20.665262 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-add-keys
163 20:49:20.665964 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-add-sources
164 20:49:20.666532 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-background-process-start
165 20:49:20.667066 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-background-process-stop
166 20:49:20.667627 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-common-functions
167 20:49:20.668234 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-echo-ipv4
168 20:49:20.668813 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-install-packages
169 20:49:20.669399 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-installed-packages
170 20:49:20.669927 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-os-build
171 20:49:20.670430 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-probe-channel
172 20:49:20.670917 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-probe-ip
173 20:49:20.671403 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-target-ip
174 20:49:20.671945 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-target-mac
175 20:49:20.672487 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-target-storage
176 20:49:20.673029 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-test-case
177 20:49:20.673576 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-test-event
178 20:49:20.674073 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-test-feedback
179 20:49:20.674585 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-test-raise
180 20:49:20.675155 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-test-reference
181 20:49:20.675699 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-test-runner
182 20:49:20.676248 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-test-set
183 20:49:20.676816 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-test-shell
184 20:49:20.677394 Updating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-install-packages (oe)
185 20:49:20.677969 Updating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/bin/lava-installed-packages (oe)
186 20:49:20.678441 Creating /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/environment
187 20:49:20.678855 LAVA metadata
188 20:49:20.679124 - LAVA_JOB_ID=954544
189 20:49:20.679343 - LAVA_DISPATCHER_IP=192.168.6.2
190 20:49:20.679718 start: 1.6.2.1 ssh-authorize (timeout 00:09:08) [common]
191 20:49:20.680763 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 20:49:20.681092 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:08) [common]
193 20:49:20.681305 skipped lava-vland-overlay
194 20:49:20.681550 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 20:49:20.681808 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:08) [common]
196 20:49:20.682028 skipped lava-multinode-overlay
197 20:49:20.682270 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 20:49:20.682523 start: 1.6.2.4 test-definition (timeout 00:09:08) [common]
199 20:49:20.682772 Loading test definitions
200 20:49:20.683053 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:08) [common]
201 20:49:20.683276 Using /lava-954544 at stage 0
202 20:49:20.684616 uuid=954544_1.6.2.4.1 testdef=None
203 20:49:20.684941 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 20:49:20.685207 start: 1.6.2.4.2 test-overlay (timeout 00:09:08) [common]
205 20:49:20.687135 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 20:49:20.687941 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:08) [common]
208 20:49:20.690370 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 20:49:20.691216 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:08) [common]
211 20:49:20.693500 runner path: /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/0/tests/0_v4l2-decoder-conformance-h264 test_uuid 954544_1.6.2.4.1
212 20:49:20.694105 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 20:49:20.694876 Creating lava-test-runner.conf files
215 20:49:20.695083 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/954544/lava-overlay-mvh4yizg/lava-954544/0 for stage 0
216 20:49:20.695440 - 0_v4l2-decoder-conformance-h264
217 20:49:20.695812 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 20:49:20.696132 start: 1.6.2.5 compress-overlay (timeout 00:09:08) [common]
219 20:49:20.718504 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 20:49:20.718944 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:08) [common]
221 20:49:20.719205 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 20:49:20.719475 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 20:49:20.719737 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:08) [common]
224 20:49:21.411366 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 20:49:21.412025 start: 1.6.4 extract-modules (timeout 00:09:07) [common]
226 20:49:21.412422 extracting modules file /var/lib/lava/dispatcher/tmp/954544/tftp-deploy-dz0qxhzx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/954544/extract-nfsrootfs-e3r6ic07
227 20:49:23.223057 extracting modules file /var/lib/lava/dispatcher/tmp/954544/tftp-deploy-dz0qxhzx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/954544/extract-overlay-ramdisk-f9n43i3e/ramdisk
228 20:49:24.704137 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 20:49:24.704624 start: 1.6.5 apply-overlay-tftp (timeout 00:09:04) [common]
230 20:49:24.704908 [common] Applying overlay to NFS
231 20:49:24.705126 [common] Applying overlay /var/lib/lava/dispatcher/tmp/954544/compress-overlay-wx_3e6av/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/954544/extract-nfsrootfs-e3r6ic07
232 20:49:24.737527 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 20:49:24.738003 start: 1.6.6 prepare-kernel (timeout 00:09:04) [common]
234 20:49:24.738285 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:04) [common]
235 20:49:24.738520 Converting downloaded kernel to a uImage
236 20:49:24.741500 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/954544/tftp-deploy-dz0qxhzx/kernel/Image /var/lib/lava/dispatcher/tmp/954544/tftp-deploy-dz0qxhzx/kernel/uImage
237 20:49:25.459512 output: Image Name:
238 20:49:25.459962 output: Created: Thu Nov 7 20:49:24 2024
239 20:49:25.460241 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 20:49:25.460454 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 20:49:25.460661 output: Load Address: 01080000
242 20:49:25.460862 output: Entry Point: 01080000
243 20:49:25.461062 output:
244 20:49:25.461418 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 20:49:25.461714 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 20:49:25.462008 start: 1.6.7 configure-preseed-file (timeout 00:09:03) [common]
247 20:49:25.462278 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 20:49:25.462545 start: 1.6.8 compress-ramdisk (timeout 00:09:03) [common]
249 20:49:25.462822 Building ramdisk /var/lib/lava/dispatcher/tmp/954544/extract-overlay-ramdisk-f9n43i3e/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/954544/extract-overlay-ramdisk-f9n43i3e/ramdisk
250 20:49:27.663790 >> 166783 blocks
251 20:49:35.474687 Adding RAMdisk u-boot header.
252 20:49:35.475346 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/954544/extract-overlay-ramdisk-f9n43i3e/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/954544/extract-overlay-ramdisk-f9n43i3e/ramdisk.cpio.gz.uboot
253 20:49:35.720617 output: Image Name:
254 20:49:35.721040 output: Created: Thu Nov 7 20:49:35 2024
255 20:49:35.721251 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 20:49:35.721455 output: Data Size: 23429505 Bytes = 22880.38 KiB = 22.34 MiB
257 20:49:35.721654 output: Load Address: 00000000
258 20:49:35.721851 output: Entry Point: 00000000
259 20:49:35.722048 output:
260 20:49:35.722702 rename /var/lib/lava/dispatcher/tmp/954544/extract-overlay-ramdisk-f9n43i3e/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/954544/tftp-deploy-dz0qxhzx/ramdisk/ramdisk.cpio.gz.uboot
261 20:49:35.723139 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 20:49:35.723425 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
263 20:49:35.723699 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:53) [common]
264 20:49:35.723946 No LXC device requested
265 20:49:35.724514 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 20:49:35.725032 start: 1.8 deploy-device-env (timeout 00:08:53) [common]
267 20:49:35.725527 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 20:49:35.725938 Checking files for TFTP limit of 4294967296 bytes.
269 20:49:35.728713 end: 1 tftp-deploy (duration 00:01:07) [common]
270 20:49:35.729305 start: 2 uboot-action (timeout 00:05:00) [common]
271 20:49:35.729826 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 20:49:35.730319 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 20:49:35.730823 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 20:49:35.731347 Using kernel file from prepare-kernel: 954544/tftp-deploy-dz0qxhzx/kernel/uImage
275 20:49:35.731968 substitutions:
276 20:49:35.732419 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 20:49:35.732821 - {DTB_ADDR}: 0x01070000
278 20:49:35.733217 - {DTB}: 954544/tftp-deploy-dz0qxhzx/dtb/meson-g12b-a311d-libretech-cc.dtb
279 20:49:35.733615 - {INITRD}: 954544/tftp-deploy-dz0qxhzx/ramdisk/ramdisk.cpio.gz.uboot
280 20:49:35.734007 - {KERNEL_ADDR}: 0x01080000
281 20:49:35.734396 - {KERNEL}: 954544/tftp-deploy-dz0qxhzx/kernel/uImage
282 20:49:35.734786 - {LAVA_MAC}: None
283 20:49:35.735216 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/954544/extract-nfsrootfs-e3r6ic07
284 20:49:35.735613 - {NFS_SERVER_IP}: 192.168.6.2
285 20:49:35.736024 - {PRESEED_CONFIG}: None
286 20:49:35.736420 - {PRESEED_LOCAL}: None
287 20:49:35.736809 - {RAMDISK_ADDR}: 0x08000000
288 20:49:35.737193 - {RAMDISK}: 954544/tftp-deploy-dz0qxhzx/ramdisk/ramdisk.cpio.gz.uboot
289 20:49:35.737581 - {ROOT_PART}: None
290 20:49:35.737966 - {ROOT}: None
291 20:49:35.738347 - {SERVER_IP}: 192.168.6.2
292 20:49:35.738733 - {TEE_ADDR}: 0x83000000
293 20:49:35.739116 - {TEE}: None
294 20:49:35.739503 Parsed boot commands:
295 20:49:35.739877 - setenv autoload no
296 20:49:35.740295 - setenv initrd_high 0xffffffff
297 20:49:35.740681 - setenv fdt_high 0xffffffff
298 20:49:35.741064 - dhcp
299 20:49:35.741446 - setenv serverip 192.168.6.2
300 20:49:35.741828 - tftpboot 0x01080000 954544/tftp-deploy-dz0qxhzx/kernel/uImage
301 20:49:35.742210 - tftpboot 0x08000000 954544/tftp-deploy-dz0qxhzx/ramdisk/ramdisk.cpio.gz.uboot
302 20:49:35.742596 - tftpboot 0x01070000 954544/tftp-deploy-dz0qxhzx/dtb/meson-g12b-a311d-libretech-cc.dtb
303 20:49:35.742979 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/954544/extract-nfsrootfs-e3r6ic07,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 20:49:35.743375 - bootm 0x01080000 0x08000000 0x01070000
305 20:49:35.743871 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 20:49:35.745453 start: 2.3 connect-device (timeout 00:05:00) [common]
308 20:49:35.745872 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 20:49:35.760744 Setting prompt string to ['lava-test: # ']
310 20:49:35.762205 end: 2.3 connect-device (duration 00:00:00) [common]
311 20:49:35.762798 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 20:49:35.763329 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 20:49:35.763853 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 20:49:35.765042 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 20:49:35.799368 >> OK - accepted request
316 20:49:35.801461 Returned 0 in 0 seconds
317 20:49:35.902378 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 20:49:35.904064 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 20:49:35.904665 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 20:49:35.905180 Setting prompt string to ['Hit any key to stop autoboot']
322 20:49:35.905643 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 20:49:35.907235 Trying 192.168.56.21...
324 20:49:35.907726 Connected to conserv1.
325 20:49:35.908201 Escape character is '^]'.
326 20:49:35.908639
327 20:49:35.909070 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 20:49:35.909486
329 20:49:46.494517 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 20:49:46.494921 bl2_stage_init 0x01
331 20:49:46.495160 bl2_stage_init 0x81
332 20:49:46.499931 hw id: 0x0000 - pwm id 0x01
333 20:49:46.500298 bl2_stage_init 0xc1
334 20:49:46.500543 bl2_stage_init 0x02
335 20:49:46.500772
336 20:49:46.505544 L0:00000000
337 20:49:46.505854 L1:20000703
338 20:49:46.506086 L2:00008067
339 20:49:46.506308 L3:14000000
340 20:49:46.508438 B2:00402000
341 20:49:46.508718 B1:e0f83180
342 20:49:46.508953
343 20:49:46.509182 TE: 58167
344 20:49:46.509401
345 20:49:46.519634 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 20:49:46.519962
347 20:49:46.520279 Board ID = 1
348 20:49:46.520521 Set A53 clk to 24M
349 20:49:46.520747 Set A73 clk to 24M
350 20:49:46.525241 Set clk81 to 24M
351 20:49:46.525565 A53 clk: 1200 MHz
352 20:49:46.525797 A73 clk: 1200 MHz
353 20:49:46.530783 CLK81: 166.6M
354 20:49:46.531095 smccc: 00012abd
355 20:49:46.536406 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 20:49:46.536729 board id: 1
357 20:49:46.545003 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 20:49:46.555622 fw parse done
359 20:49:46.561423 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 20:49:46.603637 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 20:49:46.614976 PIEI prepare done
362 20:49:46.615281 fastboot data load
363 20:49:46.615513 fastboot data verify
364 20:49:46.620610 verify result: 266
365 20:49:46.626213 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 20:49:46.626530 LPDDR4 probe
367 20:49:46.626769 ddr clk to 1584MHz
368 20:49:46.634159 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 20:49:46.671415
370 20:49:46.671774 dmc_version 0001
371 20:49:46.677109 Check phy result
372 20:49:46.683936 INFO : End of CA training
373 20:49:46.684251 INFO : End of initialization
374 20:49:46.689574 INFO : Training has run successfully!
375 20:49:46.689862 Check phy result
376 20:49:46.695226 INFO : End of initialization
377 20:49:46.695506 INFO : End of read enable training
378 20:49:46.700707 INFO : End of fine write leveling
379 20:49:46.706320 INFO : End of Write leveling coarse delay
380 20:49:46.706612 INFO : Training has run successfully!
381 20:49:46.706849 Check phy result
382 20:49:46.711937 INFO : End of initialization
383 20:49:46.712268 INFO : End of read dq deskew training
384 20:49:46.717490 INFO : End of MPR read delay center optimization
385 20:49:46.723194 INFO : End of write delay center optimization
386 20:49:46.728723 INFO : End of read delay center optimization
387 20:49:46.729013 INFO : End of max read latency training
388 20:49:46.734342 INFO : Training has run successfully!
389 20:49:46.734638 1D training succeed
390 20:49:46.743519 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 20:49:46.790284 Check phy result
392 20:49:46.790648 INFO : End of initialization
393 20:49:46.812897 INFO : End of 2D read delay Voltage center optimization
394 20:49:46.833063 INFO : End of 2D read delay Voltage center optimization
395 20:49:46.885227 INFO : End of 2D write delay Voltage center optimization
396 20:49:46.934596 INFO : End of 2D write delay Voltage center optimization
397 20:49:46.940171 INFO : Training has run successfully!
398 20:49:46.940605
399 20:49:46.940880 channel==0
400 20:49:46.945720 RxClkDly_Margin_A0==88 ps 9
401 20:49:46.946121 TxDqDly_Margin_A0==98 ps 10
402 20:49:46.951315 RxClkDly_Margin_A1==88 ps 9
403 20:49:46.951708 TxDqDly_Margin_A1==98 ps 10
404 20:49:46.951968 TrainedVREFDQ_A0==74
405 20:49:46.956904 TrainedVREFDQ_A1==74
406 20:49:46.957297 VrefDac_Margin_A0==25
407 20:49:46.957581 DeviceVref_Margin_A0==40
408 20:49:46.962494 VrefDac_Margin_A1==25
409 20:49:46.962897 DeviceVref_Margin_A1==40
410 20:49:46.963147
411 20:49:46.963394
412 20:49:46.968262 channel==1
413 20:49:46.968670 RxClkDly_Margin_A0==98 ps 10
414 20:49:46.968927 TxDqDly_Margin_A0==98 ps 10
415 20:49:46.973807 RxClkDly_Margin_A1==98 ps 10
416 20:49:46.974198 TxDqDly_Margin_A1==88 ps 9
417 20:49:46.979487 TrainedVREFDQ_A0==77
418 20:49:46.979890 TrainedVREFDQ_A1==77
419 20:49:46.980281 VrefDac_Margin_A0==22
420 20:49:46.984978 DeviceVref_Margin_A0==37
421 20:49:46.985402 VrefDac_Margin_A1==22
422 20:49:46.990577 DeviceVref_Margin_A1==37
423 20:49:46.990962
424 20:49:46.991224 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 20:49:46.996215
426 20:49:47.024324 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 20:49:47.024764 2D training succeed
428 20:49:47.029771 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 20:49:47.035321 auto size-- 65535DDR cs0 size: 2048MB
430 20:49:47.035610 DDR cs1 size: 2048MB
431 20:49:47.040904 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 20:49:47.041181 cs0 DataBus test pass
433 20:49:47.046522 cs1 DataBus test pass
434 20:49:47.046827 cs0 AddrBus test pass
435 20:49:47.047062 cs1 AddrBus test pass
436 20:49:47.047285
437 20:49:47.052346 100bdlr_step_size ps== 420
438 20:49:47.052942 result report
439 20:49:47.057743 boot times 0Enable ddr reg access
440 20:49:47.063187 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 20:49:47.076727 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 20:49:47.649630 0.0;M3 CHK:0;cm4_sp_mode 0
443 20:49:47.650039 MVN_1=0x00000000
444 20:49:47.655112 MVN_2=0x00000000
445 20:49:47.660859 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 20:49:47.661173 OPS=0x10
447 20:49:47.661392 ring efuse init
448 20:49:47.661601 chipver efuse init
449 20:49:47.666462 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 20:49:47.672243 [0.018960 Inits done]
451 20:49:47.672815 secure task start!
452 20:49:47.673274 high task start!
453 20:49:47.676050 low task start!
454 20:49:47.676551 run into bl31
455 20:49:47.683355 NOTICE: BL31: v1.3(release):4fc40b1
456 20:49:47.691130 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 20:49:47.691628 NOTICE: BL31: G12A normal boot!
458 20:49:47.716527 NOTICE: BL31: BL33 decompress pass
459 20:49:47.722174 ERROR: Error initializing runtime service opteed_fast
460 20:49:48.955170
461 20:49:48.955806
462 20:49:48.963625 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 20:49:48.964151
464 20:49:48.964599 Model: Libre Computer AML-A311D-CC Alta
465 20:49:49.172102 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 20:49:49.195358 DRAM: 2 GiB (effective 3.8 GiB)
467 20:49:49.338417 Core: 408 devices, 31 uclasses, devicetree: separate
468 20:49:49.344210 WDT: Not starting watchdog@f0d0
469 20:49:49.376495 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 20:49:49.388918 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 20:49:49.393846 ** Bad device specification mmc 0 **
472 20:49:49.404222 Card did not respond to voltage select! : -110
473 20:49:49.411838 ** Bad device specification mmc 0 **
474 20:49:49.412361 Couldn't find partition mmc 0
475 20:49:49.420215 Card did not respond to voltage select! : -110
476 20:49:49.425706 ** Bad device specification mmc 0 **
477 20:49:49.426180 Couldn't find partition mmc 0
478 20:49:49.430787 Error: could not access storage.
479 20:49:50.694459 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 20:49:50.695099 bl2_stage_init 0x01
481 20:49:50.695556 bl2_stage_init 0x81
482 20:49:50.700075 hw id: 0x0000 - pwm id 0x01
483 20:49:50.700586 bl2_stage_init 0xc1
484 20:49:50.701034 bl2_stage_init 0x02
485 20:49:50.701472
486 20:49:50.705653 L0:00000000
487 20:49:50.706131 L1:20000703
488 20:49:50.706571 L2:00008067
489 20:49:50.707005 L3:14000000
490 20:49:50.711240 B2:00402000
491 20:49:50.711714 B1:e0f83180
492 20:49:50.712186
493 20:49:50.712622 TE: 58159
494 20:49:50.713057
495 20:49:50.716937 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 20:49:50.717411
497 20:49:50.717852 Board ID = 1
498 20:49:50.722499 Set A53 clk to 24M
499 20:49:50.722969 Set A73 clk to 24M
500 20:49:50.723404 Set clk81 to 24M
501 20:49:50.728070 A53 clk: 1200 MHz
502 20:49:50.728548 A73 clk: 1200 MHz
503 20:49:50.728988 CLK81: 166.6M
504 20:49:50.729422 smccc: 00012ab5
505 20:49:50.733642 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 20:49:50.739209 board id: 1
507 20:49:50.744305 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 20:49:50.755806 fw parse done
509 20:49:50.761727 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 20:49:50.804367 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 20:49:50.815306 PIEI prepare done
512 20:49:50.815780 fastboot data load
513 20:49:50.816258 fastboot data verify
514 20:49:50.820972 verify result: 266
515 20:49:50.826512 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 20:49:50.826983 LPDDR4 probe
517 20:49:50.827421 ddr clk to 1584MHz
518 20:49:50.834512 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 20:49:50.871901
520 20:49:50.872557 dmc_version 0001
521 20:49:50.878478 Check phy result
522 20:49:50.884294 INFO : End of CA training
523 20:49:50.884766 INFO : End of initialization
524 20:49:50.889972 INFO : Training has run successfully!
525 20:49:50.890441 Check phy result
526 20:49:50.895505 INFO : End of initialization
527 20:49:50.895968 INFO : End of read enable training
528 20:49:50.898930 INFO : End of fine write leveling
529 20:49:50.904432 INFO : End of Write leveling coarse delay
530 20:49:50.910041 INFO : Training has run successfully!
531 20:49:50.910507 Check phy result
532 20:49:50.910939 INFO : End of initialization
533 20:49:50.915594 INFO : End of read dq deskew training
534 20:49:50.918964 INFO : End of MPR read delay center optimization
535 20:49:50.924523 INFO : End of write delay center optimization
536 20:49:50.930161 INFO : End of read delay center optimization
537 20:49:50.930625 INFO : End of max read latency training
538 20:49:50.935729 INFO : Training has run successfully!
539 20:49:50.936240 1D training succeed
540 20:49:50.943139 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 20:49:50.990695 Check phy result
542 20:49:50.991277 INFO : End of initialization
543 20:49:51.013186 INFO : End of 2D read delay Voltage center optimization
544 20:49:51.033227 INFO : End of 2D read delay Voltage center optimization
545 20:49:51.085066 INFO : End of 2D write delay Voltage center optimization
546 20:49:51.135282 INFO : End of 2D write delay Voltage center optimization
547 20:49:51.140890 INFO : Training has run successfully!
548 20:49:51.141496
549 20:49:51.141955 channel==0
550 20:49:51.146419 RxClkDly_Margin_A0==88 ps 9
551 20:49:51.147181 TxDqDly_Margin_A0==98 ps 10
552 20:49:51.152045 RxClkDly_Margin_A1==88 ps 9
553 20:49:51.152786 TxDqDly_Margin_A1==98 ps 10
554 20:49:51.153441 TrainedVREFDQ_A0==74
555 20:49:51.157630 TrainedVREFDQ_A1==74
556 20:49:51.158198 VrefDac_Margin_A0==24
557 20:49:51.158648 DeviceVref_Margin_A0==40
558 20:49:51.163284 VrefDac_Margin_A1==24
559 20:49:51.164054 DeviceVref_Margin_A1==40
560 20:49:51.164734
561 20:49:51.165376
562 20:49:51.168858 channel==1
563 20:49:51.169640 RxClkDly_Margin_A0==98 ps 10
564 20:49:51.170158 TxDqDly_Margin_A0==98 ps 10
565 20:49:51.174365 RxClkDly_Margin_A1==98 ps 10
566 20:49:51.174856 TxDqDly_Margin_A1==88 ps 9
567 20:49:51.180019 TrainedVREFDQ_A0==77
568 20:49:51.180530 TrainedVREFDQ_A1==77
569 20:49:51.180982 VrefDac_Margin_A0==22
570 20:49:51.185568 DeviceVref_Margin_A0==37
571 20:49:51.186039 VrefDac_Margin_A1==24
572 20:49:51.191138 DeviceVref_Margin_A1==37
573 20:49:51.191607
574 20:49:51.192081 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 20:49:51.196789
576 20:49:51.224809 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
577 20:49:51.225417 2D training succeed
578 20:49:51.230379 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 20:49:51.235912 auto size-- 65535DDR cs0 size: 2048MB
580 20:49:51.236470 DDR cs1 size: 2048MB
581 20:49:51.241520 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 20:49:51.242005 cs0 DataBus test pass
583 20:49:51.247150 cs1 DataBus test pass
584 20:49:51.247650 cs0 AddrBus test pass
585 20:49:51.248131 cs1 AddrBus test pass
586 20:49:51.248579
587 20:49:51.252853 100bdlr_step_size ps== 420
588 20:49:51.253347 result report
589 20:49:51.258380 boot times 0Enable ddr reg access
590 20:49:51.263732 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 20:49:51.277304 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 20:49:51.849438 0.0;M3 CHK:0;cm4_sp_mode 0
593 20:49:51.850114 MVN_1=0x00000000
594 20:49:51.854966 MVN_2=0x00000000
595 20:49:51.860723 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 20:49:51.861261 OPS=0x10
597 20:49:51.861726 ring efuse init
598 20:49:51.862195 chipver efuse init
599 20:49:51.868908 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 20:49:51.869485 [0.018961 Inits done]
601 20:49:51.876510 secure task start!
602 20:49:51.877083 high task start!
603 20:49:51.877546 low task start!
604 20:49:51.877997 run into bl31
605 20:49:51.883172 NOTICE: BL31: v1.3(release):4fc40b1
606 20:49:51.890894 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 20:49:51.891440 NOTICE: BL31: G12A normal boot!
608 20:49:51.916254 NOTICE: BL31: BL33 decompress pass
609 20:49:51.921864 ERROR: Error initializing runtime service opteed_fast
610 20:49:53.155007
611 20:49:53.155401
612 20:49:53.163411 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 20:49:53.163786
614 20:49:53.164147 Model: Libre Computer AML-A311D-CC Alta
615 20:49:53.662120 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 20:49:53.662790 DRAM: 2 GiB (effective 3.8 GiB)
617 20:49:53.663262 Core: 408 devices, 31 uclasses, devicetree: separate
618 20:49:53.663719 WDT: Not starting watchdog@f0d0
619 20:49:53.664629 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 20:49:53.665111 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 20:49:53.665567 ** Bad device specification mmc 0 **
622 20:49:53.666019 Card did not respond to voltage select! : -110
623 20:49:53.666466 ** Bad device specification mmc 0 **
624 20:49:53.666910 Couldn't find partition mmc 0
625 20:49:53.667351 Card did not respond to voltage select! : -110
626 20:49:53.667789 ** Bad device specification mmc 0 **
627 20:49:53.668278 Couldn't find partition mmc 0
628 20:49:53.668811 Error: could not access storage.
629 20:49:53.973038 Net: eth0: ethernet@ff3f0000
630 20:49:53.973640 starting USB...
631 20:49:54.224975 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 20:49:54.225606 Starting the controller
633 20:49:54.231790 USB XHCI 1.10
634 20:49:55.886667 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
635 20:49:55.887181 bl2_stage_init 0x81
636 20:49:55.892261 hw id: 0x0000 - pwm id 0x01
637 20:49:55.892910 bl2_stage_init 0xc1
638 20:49:55.893422 bl2_stage_init 0x02
639 20:49:55.893933
640 20:49:55.897726 L0:00000000
641 20:49:55.898321 L1:20000703
642 20:49:55.898809 L2:00008067
643 20:49:55.899509 L3:14000000
644 20:49:55.900091 B2:00402000
645 20:49:55.904269 B1:e0f83180
646 20:49:55.904825
647 20:49:55.905298 TE: 58150
648 20:49:55.905757
649 20:49:55.908924 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
650 20:49:55.909495
651 20:49:55.909970 Board ID = 1
652 20:49:55.914583 Set A53 clk to 24M
653 20:49:55.915162 Set A73 clk to 24M
654 20:49:55.915702 Set clk81 to 24M
655 20:49:55.920150 A53 clk: 1200 MHz
656 20:49:55.920696 A73 clk: 1200 MHz
657 20:49:55.921165 CLK81: 166.6M
658 20:49:55.921618 smccc: 00012aac
659 20:49:55.925645 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
660 20:49:55.931422 board id: 1
661 20:49:55.936079 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
662 20:49:55.947672 fw parse done
663 20:49:55.952616 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
664 20:49:55.996210 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
665 20:49:56.007074 PIEI prepare done
666 20:49:56.007474 fastboot data load
667 20:49:56.008454 fastboot data verify
668 20:49:56.012876 verify result: 266
669 20:49:56.018359 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
670 20:49:56.018820 LPDDR4 probe
671 20:49:56.019050 ddr clk to 1584MHz
672 20:49:56.026358 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
673 20:49:56.063632
674 20:49:56.064102 dmc_version 0001
675 20:49:56.069288 Check phy result
676 20:49:56.076433 INFO : End of CA training
677 20:49:56.076867 INFO : End of initialization
678 20:49:56.081860 INFO : Training has run successfully!
679 20:49:56.082370 Check phy result
680 20:49:56.087384 INFO : End of initialization
681 20:49:56.087799 INFO : End of read enable training
682 20:49:56.093081 INFO : End of fine write leveling
683 20:49:56.105630 INFO : End of Write leveling coarse delay
684 20:49:56.106033 INFO : Training has run successfully!
685 20:49:56.106245 Check phy result
686 20:49:56.106452 INFO : End of initialization
687 20:49:56.106658 INFO : End of read dq deskew training
688 20:49:56.109792 INFO : End of MPR read delay center optimization
689 20:49:56.115424 INFO : End of write delay center optimization
690 20:49:56.120961 INFO : End of read delay center optimization
691 20:49:56.121323 INFO : End of max read latency training
692 20:49:56.126806 INFO : Training has run successfully!
693 20:49:56.127194 1D training succeed
694 20:49:56.135818 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 20:49:56.182463 Check phy result
696 20:49:56.182895 INFO : End of initialization
697 20:49:56.205168 INFO : End of 2D read delay Voltage center optimization
698 20:49:56.225381 INFO : End of 2D read delay Voltage center optimization
699 20:49:56.277593 INFO : End of 2D write delay Voltage center optimization
700 20:49:56.328153 INFO : End of 2D write delay Voltage center optimization
701 20:49:56.333153 INFO : Training has run successfully!
702 20:49:56.333528
703 20:49:56.333775 channel==0
704 20:49:56.338737 RxClkDly_Margin_A0==88 ps 9
705 20:49:56.339071 TxDqDly_Margin_A0==98 ps 10
706 20:49:56.344412 RxClkDly_Margin_A1==88 ps 9
707 20:49:56.344693 TxDqDly_Margin_A1==98 ps 10
708 20:49:56.344913 TrainedVREFDQ_A0==74
709 20:49:56.349863 TrainedVREFDQ_A1==74
710 20:49:56.350134 VrefDac_Margin_A0==24
711 20:49:56.350375 DeviceVref_Margin_A0==40
712 20:49:56.355621 VrefDac_Margin_A1==24
713 20:49:56.355898 DeviceVref_Margin_A1==40
714 20:49:56.356145
715 20:49:56.356388
716 20:49:56.361570 channel==1
717 20:49:56.362085 RxClkDly_Margin_A0==98 ps 10
718 20:49:56.362536 TxDqDly_Margin_A0==88 ps 9
719 20:49:56.366663 RxClkDly_Margin_A1==88 ps 9
720 20:49:56.366959 TxDqDly_Margin_A1==88 ps 9
721 20:49:56.372360 TrainedVREFDQ_A0==76
722 20:49:56.372787 TrainedVREFDQ_A1==77
723 20:49:56.373043 VrefDac_Margin_A0==22
724 20:49:56.377843 DeviceVref_Margin_A0==38
725 20:49:56.378228 VrefDac_Margin_A1==24
726 20:49:56.383639 DeviceVref_Margin_A1==37
727 20:49:56.384007
728 20:49:56.384245 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
729 20:49:56.384469
730 20:49:56.417127 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000017 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
731 20:49:56.417585 2D training succeed
732 20:49:56.422716 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
733 20:49:56.428318 auto size-- 65535DDR cs0 size: 2048MB
734 20:49:56.428769 DDR cs1 size: 2048MB
735 20:49:56.433881 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
736 20:49:56.434648 cs0 DataBus test pass
737 20:49:56.439603 cs1 DataBus test pass
738 20:49:56.440064 cs0 AddrBus test pass
739 20:49:56.440331 cs1 AddrBus test pass
740 20:49:56.440583
741 20:49:56.445322 100bdlr_step_size ps== 420
742 20:49:56.446098 result report
743 20:49:56.450734 boot times 0Enable ddr reg access
744 20:49:56.456017 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
745 20:49:56.469497 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
746 20:49:57.043753 0.0;M3 CHK:0;cm4_sp_mode 0
747 20:49:57.044503 MVN_1=0x00000000
748 20:49:57.048642 MVN_2=0x00000000
749 20:49:57.054434 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
750 20:49:57.055216 OPS=0x10
751 20:49:57.055710 ring efuse init
752 20:49:57.056197 chipver efuse init
753 20:49:57.060022 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
754 20:49:57.066321 [0.018961 Inits done]
755 20:49:57.066822 secure task start!
756 20:49:57.067267 high task start!
757 20:49:57.070142 low task start!
758 20:49:57.070622 run into bl31
759 20:49:57.076861 NOTICE: BL31: v1.3(release):4fc40b1
760 20:49:57.084755 NOTICE: BL31: Built : 15:58:17, May 22 2019
761 20:49:57.085273 NOTICE: BL31: G12A normal boot!
762 20:49:57.109983 NOTICE: BL31: BL33 decompress pass
763 20:49:57.115712 ERROR: Error initializing runtime service opteed_fast
764 20:49:58.348489
765 20:49:58.348896
766 20:49:58.356845 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
767 20:49:58.357137
768 20:49:58.357349 Model: Libre Computer AML-A311D-CC Alta
769 20:49:58.565370 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
770 20:49:58.588709 DRAM: 2 GiB (effective 3.8 GiB)
771 20:49:58.731713 Core: 408 devices, 31 uclasses, devicetree: separate
772 20:49:58.737507 WDT: Not starting watchdog@f0d0
773 20:49:58.769848 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
774 20:49:58.782272 Loading Environment from FAT... Card did not respond to voltage select! : -110
775 20:49:58.787198 ** Bad device specification mmc 0 **
776 20:49:58.797588 Card did not respond to voltage select! : -110
777 20:49:58.805216 ** Bad device specification mmc 0 **
778 20:49:58.805572 Couldn't find partition mmc 0
779 20:49:58.813542 Card did not respond to voltage select! : -110
780 20:49:58.819123 ** Bad device specification mmc 0 **
781 20:49:58.819588 Couldn't find partition mmc 0
782 20:49:58.824174 Error: could not access storage.
783 20:49:59.170308 Net: eth0: ethernet@ff3f0000
784 20:49:59.170739 starting USB...
785 20:49:59.419554 Bus usb@ff500000: Register 3000140 NbrPorts 3
786 20:49:59.420185 Starting the controller
787 20:49:59.426456 USB XHCI 1.10
788 20:50:01.585087 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
789 20:50:01.585543 bl2_stage_init 0x01
790 20:50:01.585767 bl2_stage_init 0x81
791 20:50:01.590515 hw id: 0x0000 - pwm id 0x01
792 20:50:01.590952 bl2_stage_init 0xc1
793 20:50:01.591267 bl2_stage_init 0x02
794 20:50:01.591580
795 20:50:01.596100 L0:00000000
796 20:50:01.596526 L1:20000703
797 20:50:01.596762 L2:00008067
798 20:50:01.596970 L3:14000000
799 20:50:01.601716 B2:00402000
800 20:50:01.602134 B1:e0f83180
801 20:50:01.602446
802 20:50:01.602752 TE: 58167
803 20:50:01.603054
804 20:50:01.608211 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 20:50:01.608566
806 20:50:01.608785 Board ID = 1
807 20:50:01.613109 Set A53 clk to 24M
808 20:50:01.613498 Set A73 clk to 24M
809 20:50:01.613806 Set clk81 to 24M
810 20:50:01.618684 A53 clk: 1200 MHz
811 20:50:01.619099 A73 clk: 1200 MHz
812 20:50:01.619334 CLK81: 166.6M
813 20:50:01.619542 smccc: 00012abe
814 20:50:01.624199 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 20:50:01.629637 board id: 1
816 20:50:01.635488 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 20:50:01.646162 fw parse done
818 20:50:01.652137 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 20:50:01.694836 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 20:50:01.705663 PIEI prepare done
821 20:50:01.705978 fastboot data load
822 20:50:01.706197 fastboot data verify
823 20:50:01.711361 verify result: 266
824 20:50:01.716945 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 20:50:01.717608 LPDDR4 probe
826 20:50:01.717974 ddr clk to 1584MHz
827 20:50:01.724950 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 20:50:01.762288
829 20:50:01.762687 dmc_version 0001
830 20:50:01.768900 Check phy result
831 20:50:01.774670 INFO : End of CA training
832 20:50:01.775152 INFO : End of initialization
833 20:50:01.780419 INFO : Training has run successfully!
834 20:50:01.780771 Check phy result
835 20:50:01.785983 INFO : End of initialization
836 20:50:01.786428 INFO : End of read enable training
837 20:50:01.791622 INFO : End of fine write leveling
838 20:50:01.797188 INFO : End of Write leveling coarse delay
839 20:50:01.797558 INFO : Training has run successfully!
840 20:50:01.797785 Check phy result
841 20:50:01.802829 INFO : End of initialization
842 20:50:01.803338 INFO : End of read dq deskew training
843 20:50:01.808462 INFO : End of MPR read delay center optimization
844 20:50:01.813894 INFO : End of write delay center optimization
845 20:50:01.819518 INFO : End of read delay center optimization
846 20:50:01.819842 INFO : End of max read latency training
847 20:50:01.825173 INFO : Training has run successfully!
848 20:50:01.825477 1D training succeed
849 20:50:01.834345 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 20:50:01.881975 Check phy result
851 20:50:01.882381 INFO : End of initialization
852 20:50:01.904590 INFO : End of 2D read delay Voltage center optimization
853 20:50:01.924877 INFO : End of 2D read delay Voltage center optimization
854 20:50:01.976927 INFO : End of 2D write delay Voltage center optimization
855 20:50:02.026170 INFO : End of 2D write delay Voltage center optimization
856 20:50:02.031621 INFO : Training has run successfully!
857 20:50:02.031933
858 20:50:02.032190 channel==0
859 20:50:02.037256 RxClkDly_Margin_A0==88 ps 9
860 20:50:02.037579 TxDqDly_Margin_A0==98 ps 10
861 20:50:02.042842 RxClkDly_Margin_A1==88 ps 9
862 20:50:02.043134 TxDqDly_Margin_A1==98 ps 10
863 20:50:02.043347 TrainedVREFDQ_A0==74
864 20:50:02.048424 TrainedVREFDQ_A1==74
865 20:50:02.048719 VrefDac_Margin_A0==25
866 20:50:02.048923 DeviceVref_Margin_A0==40
867 20:50:02.054018 VrefDac_Margin_A1==24
868 20:50:02.054301 DeviceVref_Margin_A1==40
869 20:50:02.054507
870 20:50:02.054715
871 20:50:02.059657 channel==1
872 20:50:02.059925 RxClkDly_Margin_A0==98 ps 10
873 20:50:02.060153 TxDqDly_Margin_A0==98 ps 10
874 20:50:02.065203 RxClkDly_Margin_A1==88 ps 9
875 20:50:02.065491 TxDqDly_Margin_A1==88 ps 9
876 20:50:02.070823 TrainedVREFDQ_A0==77
877 20:50:02.071110 TrainedVREFDQ_A1==77
878 20:50:02.071320 VrefDac_Margin_A0==22
879 20:50:02.076443 DeviceVref_Margin_A0==37
880 20:50:02.076756 VrefDac_Margin_A1==24
881 20:50:02.082025 DeviceVref_Margin_A1==37
882 20:50:02.082322
883 20:50:02.082535 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 20:50:02.082737
885 20:50:02.115663 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
886 20:50:02.116085 2D training succeed
887 20:50:02.121212 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 20:50:02.126823 auto size-- 65535DDR cs0 size: 2048MB
889 20:50:02.127158 DDR cs1 size: 2048MB
890 20:50:02.132455 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 20:50:02.132743 cs0 DataBus test pass
892 20:50:02.138071 cs1 DataBus test pass
893 20:50:02.138393 cs0 AddrBus test pass
894 20:50:02.138606 cs1 AddrBus test pass
895 20:50:02.138809
896 20:50:02.143603 100bdlr_step_size ps== 420
897 20:50:02.144035 result report
898 20:50:02.149197 boot times 0Enable ddr reg access
899 20:50:02.154564 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 20:50:02.168116 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 20:50:02.741715 0.0;M3 CHK:0;cm4_sp_mode 0
902 20:50:02.742124 MVN_1=0x00000000
903 20:50:02.747311 MVN_2=0x00000000
904 20:50:02.753040 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 20:50:02.753328 OPS=0x10
906 20:50:02.753539 ring efuse init
907 20:50:02.753741 chipver efuse init
908 20:50:02.758583 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 20:50:02.764164 [0.018961 Inits done]
910 20:50:02.764451 secure task start!
911 20:50:02.764659 high task start!
912 20:50:02.768754 low task start!
913 20:50:02.769025 run into bl31
914 20:50:02.775452 NOTICE: BL31: v1.3(release):4fc40b1
915 20:50:02.782491 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 20:50:02.782853 NOTICE: BL31: G12A normal boot!
917 20:50:02.808910 NOTICE: BL31: BL33 decompress pass
918 20:50:02.813443 ERROR: Error initializing runtime service opteed_fast
919 20:50:04.047314
920 20:50:04.047926
921 20:50:04.055666 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 20:50:04.056208
923 20:50:04.056638 Model: Libre Computer AML-A311D-CC Alta
924 20:50:04.264134 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 20:50:04.287520 DRAM: 2 GiB (effective 3.8 GiB)
926 20:50:04.430486 Core: 408 devices, 31 uclasses, devicetree: separate
927 20:50:04.436367 WDT: Not starting watchdog@f0d0
928 20:50:04.468598 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 20:50:04.481049 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 20:50:04.486033 ** Bad device specification mmc 0 **
931 20:50:04.496422 Card did not respond to voltage select! : -110
932 20:50:04.504110 ** Bad device specification mmc 0 **
933 20:50:04.504646 Couldn't find partition mmc 0
934 20:50:04.512363 Card did not respond to voltage select! : -110
935 20:50:04.517868 ** Bad device specification mmc 0 **
936 20:50:04.518380 Couldn't find partition mmc 0
937 20:50:04.522923 Error: could not access storage.
938 20:50:04.865457 Net: eth0: ethernet@ff3f0000
939 20:50:04.866067 starting USB...
940 20:50:05.117432 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 20:50:05.118427 Starting the controller
942 20:50:05.124287 USB XHCI 1.10
943 20:50:06.681406 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
944 20:50:06.689799 scanning usb for storage devices... 0 Storage Device(s) found
946 20:50:06.741627 Hit any key to stop autoboot: 1
947 20:50:06.742750 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
948 20:50:06.743394 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
949 20:50:06.743881 Setting prompt string to ['=>']
950 20:50:06.744425 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
951 20:50:06.757246 0
952 20:50:06.758223 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
953 20:50:06.758733 Sending with 10 millisecond of delay
955 20:50:07.893725 => setenv autoload no
956 20:50:07.904963 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:28)
957 20:50:07.910033 setenv autoload no
958 20:50:07.910838 Sending with 10 millisecond of delay
960 20:50:09.709912 => setenv initrd_high 0xffffffff
961 20:50:09.720868 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
962 20:50:09.721964 setenv initrd_high 0xffffffff
963 20:50:09.722768 Sending with 10 millisecond of delay
965 20:50:11.341163 => setenv fdt_high 0xffffffff
966 20:50:11.351877 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
967 20:50:11.352649 setenv fdt_high 0xffffffff
968 20:50:11.353316 Sending with 10 millisecond of delay
970 20:50:11.645561 => dhcp
971 20:50:11.656226 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
972 20:50:11.657207 dhcp
973 20:50:11.657666 Speed: 1000, full duplex
974 20:50:11.658087 BOOTP broadcast 1
975 20:50:11.673366 DHCP client bound to address 192.168.6.27 (18 ms)
976 20:50:11.674218 Sending with 10 millisecond of delay
978 20:50:13.351417 => setenv serverip 192.168.6.2
979 20:50:13.362008 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
980 20:50:13.362624 setenv serverip 192.168.6.2
981 20:50:13.363071 Sending with 10 millisecond of delay
983 20:50:17.090733 => tftpboot 0x01080000 954544/tftp-deploy-dz0qxhzx/kernel/uImage
984 20:50:17.101548 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
985 20:50:17.102420 tftpboot 0x01080000 954544/tftp-deploy-dz0qxhzx/kernel/uImage
986 20:50:17.102891 Speed: 1000, full duplex
987 20:50:17.103312 Using ethernet@ff3f0000 device
988 20:50:17.104194 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
989 20:50:17.109665 Filename '954544/tftp-deploy-dz0qxhzx/kernel/uImage'.
990 20:50:17.113516 Load address: 0x1080000
991 20:50:20.275380 Loading: *################################################## 43.6 MiB
992 20:50:20.276073 13.8 MiB/s
993 20:50:20.276497 done
994 20:50:20.279571 Bytes transferred = 45713984 (2b98a40 hex)
995 20:50:20.280325 Sending with 10 millisecond of delay
997 20:50:24.974155 => tftpboot 0x08000000 954544/tftp-deploy-dz0qxhzx/ramdisk/ramdisk.cpio.gz.uboot
998 20:50:24.984746 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
999 20:50:24.985327 tftpboot 0x08000000 954544/tftp-deploy-dz0qxhzx/ramdisk/ramdisk.cpio.gz.uboot
1000 20:50:24.985603 Speed: 1000, full duplex
1001 20:50:24.985836 Using ethernet@ff3f0000 device
1002 20:50:24.988247 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1003 20:50:25.000154 Filename '954544/tftp-deploy-dz0qxhzx/ramdisk/ramdisk.cpio.gz.uboot'.
1004 20:50:25.000591 Load address: 0x8000000
1005 20:50:31.575883 Loading: *###########T ###################################### UDP wrong checksum 00000005 00005a98
1006 20:50:36.575831 T UDP wrong checksum 00000005 00005a98
1007 20:50:38.329833 UDP wrong checksum 000000ff 000055f1
1008 20:50:38.338095 UDP wrong checksum 000000ff 0000e3e3
1009 20:50:41.424418 UDP wrong checksum 000000ff 00007d99
1010 20:50:41.463779 UDP wrong checksum 000000ff 0000198c
1011 20:50:46.580155 T T UDP wrong checksum 00000005 00005a98
1012 20:50:55.249761 T UDP wrong checksum 000000ff 0000bd1e
1013 20:50:55.263339 UDP wrong checksum 000000ff 00004611
1014 20:50:57.869787 T UDP wrong checksum 000000ff 00005962
1015 20:50:57.879846 UDP wrong checksum 000000ff 0000ee54
1016 20:51:00.490573 UDP wrong checksum 000000ff 00001dc4
1017 20:51:00.504713 UDP wrong checksum 000000ff 0000b3b6
1018 20:51:06.584199 T T UDP wrong checksum 00000005 00005a98
1019 20:51:21.588394 T T
1020 20:51:21.588859 Retry count exceeded; starting again
1022 20:51:21.589844 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1025 20:51:21.590928 end: 2.4 uboot-commands (duration 00:01:46) [common]
1027 20:51:21.591727 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1029 20:51:21.592444 end: 2 uboot-action (duration 00:01:46) [common]
1031 20:51:21.593500 Cleaning after the job
1032 20:51:21.593888 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954544/tftp-deploy-dz0qxhzx/ramdisk
1033 20:51:21.594874 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954544/tftp-deploy-dz0qxhzx/kernel
1034 20:51:21.612943 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954544/tftp-deploy-dz0qxhzx/dtb
1035 20:51:21.613945 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954544/tftp-deploy-dz0qxhzx/nfsrootfs
1036 20:51:21.671330 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954544/tftp-deploy-dz0qxhzx/modules
1037 20:51:21.688212 start: 4.1 power-off (timeout 00:00:30) [common]
1038 20:51:21.688976 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1039 20:51:21.725253 >> OK - accepted request
1040 20:51:21.727789 Returned 0 in 0 seconds
1041 20:51:21.829093 end: 4.1 power-off (duration 00:00:00) [common]
1043 20:51:21.830406 start: 4.2 read-feedback (timeout 00:10:00) [common]
1044 20:51:21.831498 Listened to connection for namespace 'common' for up to 1s
1045 20:51:22.832171 Finalising connection for namespace 'common'
1046 20:51:22.832781 Disconnecting from shell: Finalise
1047 20:51:22.833220 =>
1048 20:51:22.934038 end: 4.2 read-feedback (duration 00:00:01) [common]
1049 20:51:22.934550 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/954544
1050 20:51:25.728327 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/954544
1051 20:51:25.728956 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.