Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 27
- Errors: 0
- Boot result: PASS
- Kernel Errors: 59
1 21:36:19.495148 lava-dispatcher, installed at version: 2024.01
2 21:36:19.495961 start: 0 validate
3 21:36:19.496492 Start time: 2024-11-04 21:36:19.496461+00:00 (UTC)
4 21:36:19.497068 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:36:19.497632 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 21:36:19.538078 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:36:19.538702 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-194-g71c9d5bcfa2c%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 21:36:20.593070 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:36:20.593989 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-194-g71c9d5bcfa2c%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 21:36:22.653133 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:36:22.653635 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 21:36:22.695155 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 21:36:22.695946 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-194-g71c9d5bcfa2c%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 21:36:23.758182 validate duration: 4.26
16 21:36:23.759808 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 21:36:23.760524 start: 1.1 download-retry (timeout 00:10:00) [common]
18 21:36:23.761162 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 21:36:23.762213 Not decompressing ramdisk as can be used compressed.
20 21:36:23.762986 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 21:36:23.763517 saving as /var/lib/lava/dispatcher/tmp/936947/tftp-deploy-kz_c3zm3/ramdisk/initrd.cpio.gz
22 21:36:23.764104 total size: 4775763 (4 MB)
23 21:36:23.805500 progress 0 % (0 MB)
24 21:36:23.813196 progress 5 % (0 MB)
25 21:36:23.820256 progress 10 % (0 MB)
26 21:36:23.826973 progress 15 % (0 MB)
27 21:36:23.834727 progress 20 % (0 MB)
28 21:36:23.841454 progress 25 % (1 MB)
29 21:36:23.847773 progress 30 % (1 MB)
30 21:36:23.851920 progress 35 % (1 MB)
31 21:36:23.855260 progress 40 % (1 MB)
32 21:36:23.858841 progress 45 % (2 MB)
33 21:36:23.862095 progress 50 % (2 MB)
34 21:36:23.865798 progress 55 % (2 MB)
35 21:36:23.869086 progress 60 % (2 MB)
36 21:36:23.872344 progress 65 % (2 MB)
37 21:36:23.875900 progress 70 % (3 MB)
38 21:36:23.879123 progress 75 % (3 MB)
39 21:36:23.882541 progress 80 % (3 MB)
40 21:36:23.886059 progress 85 % (3 MB)
41 21:36:23.890191 progress 90 % (4 MB)
42 21:36:23.893300 progress 95 % (4 MB)
43 21:36:23.896252 progress 100 % (4 MB)
44 21:36:23.896916 4 MB downloaded in 0.13 s (34.29 MB/s)
45 21:36:23.897475 end: 1.1.1 http-download (duration 00:00:00) [common]
47 21:36:23.898410 end: 1.1 download-retry (duration 00:00:00) [common]
48 21:36:23.898765 start: 1.2 download-retry (timeout 00:10:00) [common]
49 21:36:23.899071 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 21:36:23.899574 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-194-g71c9d5bcfa2c/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 21:36:23.900025 saving as /var/lib/lava/dispatcher/tmp/936947/tftp-deploy-kz_c3zm3/kernel/zImage
52 21:36:23.900299 total size: 11440640 (10 MB)
53 21:36:23.900544 No compression specified
54 21:36:23.940338 progress 0 % (0 MB)
55 21:36:23.947433 progress 5 % (0 MB)
56 21:36:23.954514 progress 10 % (1 MB)
57 21:36:23.961897 progress 15 % (1 MB)
58 21:36:23.968882 progress 20 % (2 MB)
59 21:36:23.976294 progress 25 % (2 MB)
60 21:36:23.983302 progress 30 % (3 MB)
61 21:36:23.990668 progress 35 % (3 MB)
62 21:36:23.997678 progress 40 % (4 MB)
63 21:36:24.005166 progress 45 % (4 MB)
64 21:36:24.012149 progress 50 % (5 MB)
65 21:36:24.019455 progress 55 % (6 MB)
66 21:36:24.026442 progress 60 % (6 MB)
67 21:36:24.033546 progress 65 % (7 MB)
68 21:36:24.040900 progress 70 % (7 MB)
69 21:36:24.047838 progress 75 % (8 MB)
70 21:36:24.055354 progress 80 % (8 MB)
71 21:36:24.062448 progress 85 % (9 MB)
72 21:36:24.069898 progress 90 % (9 MB)
73 21:36:24.076900 progress 95 % (10 MB)
74 21:36:24.083948 progress 100 % (10 MB)
75 21:36:24.084523 10 MB downloaded in 0.18 s (59.23 MB/s)
76 21:36:24.085035 end: 1.2.1 http-download (duration 00:00:00) [common]
78 21:36:24.085902 end: 1.2 download-retry (duration 00:00:00) [common]
79 21:36:24.086210 start: 1.3 download-retry (timeout 00:10:00) [common]
80 21:36:24.086498 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 21:36:24.086986 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-194-g71c9d5bcfa2c/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 21:36:24.087288 saving as /var/lib/lava/dispatcher/tmp/936947/tftp-deploy-kz_c3zm3/dtb/am335x-boneblack.dtb
83 21:36:24.087513 total size: 70568 (0 MB)
84 21:36:24.087738 No compression specified
85 21:36:24.128237 progress 46 % (0 MB)
86 21:36:24.129065 progress 92 % (0 MB)
87 21:36:24.129811 progress 100 % (0 MB)
88 21:36:24.130270 0 MB downloaded in 0.04 s (1.57 MB/s)
89 21:36:24.130804 end: 1.3.1 http-download (duration 00:00:00) [common]
91 21:36:24.131764 end: 1.3 download-retry (duration 00:00:00) [common]
92 21:36:24.132132 start: 1.4 download-retry (timeout 00:10:00) [common]
93 21:36:24.132460 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 21:36:24.132984 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 21:36:24.133286 saving as /var/lib/lava/dispatcher/tmp/936947/tftp-deploy-kz_c3zm3/nfsrootfs/full.rootfs.tar
96 21:36:24.133530 total size: 117747780 (112 MB)
97 21:36:24.133783 Using unxz to decompress xz
98 21:36:24.175886 progress 0 % (0 MB)
99 21:36:24.902999 progress 5 % (5 MB)
100 21:36:25.653831 progress 10 % (11 MB)
101 21:36:26.428980 progress 15 % (16 MB)
102 21:36:27.143501 progress 20 % (22 MB)
103 21:36:27.718853 progress 25 % (28 MB)
104 21:36:28.521205 progress 30 % (33 MB)
105 21:36:29.321132 progress 35 % (39 MB)
106 21:36:29.653689 progress 40 % (44 MB)
107 21:36:30.029175 progress 45 % (50 MB)
108 21:36:30.682375 progress 50 % (56 MB)
109 21:36:31.489685 progress 55 % (61 MB)
110 21:36:32.216755 progress 60 % (67 MB)
111 21:36:32.922714 progress 65 % (73 MB)
112 21:36:33.676732 progress 70 % (78 MB)
113 21:36:34.428832 progress 75 % (84 MB)
114 21:36:35.202511 progress 80 % (89 MB)
115 21:36:36.028428 progress 85 % (95 MB)
116 21:36:36.893567 progress 90 % (101 MB)
117 21:36:37.680773 progress 95 % (106 MB)
118 21:36:38.515135 progress 100 % (112 MB)
119 21:36:38.527962 112 MB downloaded in 14.39 s (7.80 MB/s)
120 21:36:38.529058 end: 1.4.1 http-download (duration 00:00:14) [common]
122 21:36:38.530825 end: 1.4 download-retry (duration 00:00:14) [common]
123 21:36:38.531384 start: 1.5 download-retry (timeout 00:09:45) [common]
124 21:36:38.532055 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 21:36:38.532952 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-194-g71c9d5bcfa2c/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 21:36:38.533450 saving as /var/lib/lava/dispatcher/tmp/936947/tftp-deploy-kz_c3zm3/modules/modules.tar
127 21:36:38.533885 total size: 6607836 (6 MB)
128 21:36:38.534327 Using unxz to decompress xz
129 21:36:38.582388 progress 0 % (0 MB)
130 21:36:38.618642 progress 5 % (0 MB)
131 21:36:38.664329 progress 10 % (0 MB)
132 21:36:38.710005 progress 15 % (0 MB)
133 21:36:38.754130 progress 20 % (1 MB)
134 21:36:38.801289 progress 25 % (1 MB)
135 21:36:38.844371 progress 30 % (1 MB)
136 21:36:38.887246 progress 35 % (2 MB)
137 21:36:38.931051 progress 40 % (2 MB)
138 21:36:38.974502 progress 45 % (2 MB)
139 21:36:39.018083 progress 50 % (3 MB)
140 21:36:39.061071 progress 55 % (3 MB)
141 21:36:39.106470 progress 60 % (3 MB)
142 21:36:39.152898 progress 65 % (4 MB)
143 21:36:39.196419 progress 70 % (4 MB)
144 21:36:39.242160 progress 75 % (4 MB)
145 21:36:39.284969 progress 80 % (5 MB)
146 21:36:39.327311 progress 85 % (5 MB)
147 21:36:39.370453 progress 90 % (5 MB)
148 21:36:39.414486 progress 95 % (6 MB)
149 21:36:39.459280 progress 100 % (6 MB)
150 21:36:39.472216 6 MB downloaded in 0.94 s (6.72 MB/s)
151 21:36:39.472871 end: 1.5.1 http-download (duration 00:00:01) [common]
153 21:36:39.473747 end: 1.5 download-retry (duration 00:00:01) [common]
154 21:36:39.474030 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 21:36:39.474308 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 21:36:56.178666 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/936947/extract-nfsrootfs-q3xx0mjv
157 21:36:56.179268 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 21:36:56.179604 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 21:36:56.180332 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom
160 21:36:56.180859 makedir: /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin
161 21:36:56.181276 makedir: /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/tests
162 21:36:56.181664 makedir: /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/results
163 21:36:56.182048 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-add-keys
164 21:36:56.182684 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-add-sources
165 21:36:56.183265 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-background-process-start
166 21:36:56.183805 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-background-process-stop
167 21:36:56.184454 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-common-functions
168 21:36:56.184998 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-echo-ipv4
169 21:36:56.185509 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-install-packages
170 21:36:56.186002 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-installed-packages
171 21:36:56.186502 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-os-build
172 21:36:56.186996 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-probe-channel
173 21:36:56.187586 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-probe-ip
174 21:36:56.188147 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-target-ip
175 21:36:56.188688 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-target-mac
176 21:36:56.189202 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-target-storage
177 21:36:56.189717 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-test-case
178 21:36:56.190228 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-test-event
179 21:36:56.190731 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-test-feedback
180 21:36:56.191237 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-test-raise
181 21:36:56.191761 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-test-reference
182 21:36:56.192333 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-test-runner
183 21:36:56.192862 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-test-set
184 21:36:56.193372 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-test-shell
185 21:36:56.193892 Updating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-add-keys (debian)
186 21:36:56.194452 Updating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-add-sources (debian)
187 21:36:56.195003 Updating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-install-packages (debian)
188 21:36:56.195542 Updating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-installed-packages (debian)
189 21:36:56.196097 Updating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/bin/lava-os-build (debian)
190 21:36:56.196572 Creating /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/environment
191 21:36:56.196961 LAVA metadata
192 21:36:56.197233 - LAVA_JOB_ID=936947
193 21:36:56.197456 - LAVA_DISPATCHER_IP=192.168.6.2
194 21:36:56.197832 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 21:36:56.198831 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 21:36:56.199153 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 21:36:56.199367 skipped lava-vland-overlay
198 21:36:56.199610 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 21:36:56.199868 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 21:36:56.200131 skipped lava-multinode-overlay
201 21:36:56.200390 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 21:36:56.200648 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 21:36:56.200904 Loading test definitions
204 21:36:56.201186 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 21:36:56.201411 Using /lava-936947 at stage 0
206 21:36:56.202558 uuid=936947_1.6.2.4.1 testdef=None
207 21:36:56.202869 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 21:36:56.203140 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 21:36:56.204776 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 21:36:56.205588 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 21:36:56.207574 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 21:36:56.208442 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 21:36:56.210347 runner path: /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/0/tests/0_timesync-off test_uuid 936947_1.6.2.4.1
216 21:36:56.210917 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 21:36:56.211748 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 21:36:56.211976 Using /lava-936947 at stage 0
220 21:36:56.212366 Fetching tests from https://github.com/kernelci/test-definitions.git
221 21:36:56.212671 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/0/tests/1_kselftest-dt'
222 21:36:59.641481 Running '/usr/bin/git checkout kernelci.org
223 21:37:00.087282 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 21:37:00.090180 uuid=936947_1.6.2.4.5 testdef=None
225 21:37:00.090981 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 21:37:00.092903 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 21:37:00.099965 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 21:37:00.102099 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 21:37:00.111582 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 21:37:00.113802 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 21:37:00.122978 runner path: /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/0/tests/1_kselftest-dt test_uuid 936947_1.6.2.4.5
235 21:37:00.123662 BOARD='beaglebone-black'
236 21:37:00.124257 BRANCH='broonie-sound'
237 21:37:00.124782 SKIPFILE='/dev/null'
238 21:37:00.125291 SKIP_INSTALL='True'
239 21:37:00.125784 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-194-g71c9d5bcfa2c/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 21:37:00.126306 TST_CASENAME=''
241 21:37:00.126811 TST_CMDFILES='dt'
242 21:37:00.128186 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 21:37:00.130203 Creating lava-test-runner.conf files
245 21:37:00.130720 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/936947/lava-overlay-z6pktaom/lava-936947/0 for stage 0
246 21:37:00.131617 - 0_timesync-off
247 21:37:00.132265 - 1_kselftest-dt
248 21:37:00.133100 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 21:37:00.133805 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 21:37:24.757465 end: 1.6.2.5 compress-overlay (duration 00:00:25) [common]
251 21:37:24.757939 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
252 21:37:24.758222 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 21:37:24.758503 end: 1.6.2 lava-overlay (duration 00:00:29) [common]
254 21:37:24.758777 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
255 21:37:25.146970 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 21:37:25.147446 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
257 21:37:25.147702 extracting modules file /var/lib/lava/dispatcher/tmp/936947/tftp-deploy-kz_c3zm3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/936947/extract-nfsrootfs-q3xx0mjv
258 21:37:26.041454 extracting modules file /var/lib/lava/dispatcher/tmp/936947/tftp-deploy-kz_c3zm3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/936947/extract-overlay-ramdisk-bojgz7kz/ramdisk
259 21:37:26.968729 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 21:37:26.969206 start: 1.6.5 apply-overlay-tftp (timeout 00:08:57) [common]
261 21:37:26.969489 [common] Applying overlay to NFS
262 21:37:26.969706 [common] Applying overlay /var/lib/lava/dispatcher/tmp/936947/compress-overlay-odpnw2ic/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/936947/extract-nfsrootfs-q3xx0mjv
263 21:37:29.729078 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 21:37:29.729549 start: 1.6.6 prepare-kernel (timeout 00:08:54) [common]
265 21:37:29.729823 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:54) [common]
266 21:37:29.730101 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 21:37:29.730354 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 21:37:29.730611 start: 1.6.7 configure-preseed-file (timeout 00:08:54) [common]
269 21:37:29.730863 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 21:37:29.731118 start: 1.6.8 compress-ramdisk (timeout 00:08:54) [common]
271 21:37:29.731369 Building ramdisk /var/lib/lava/dispatcher/tmp/936947/extract-overlay-ramdisk-bojgz7kz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/936947/extract-overlay-ramdisk-bojgz7kz/ramdisk
272 21:37:30.885099 >> 74896 blocks
273 21:37:35.532415 Adding RAMdisk u-boot header.
274 21:37:35.533140 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/936947/extract-overlay-ramdisk-bojgz7kz/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/936947/extract-overlay-ramdisk-bojgz7kz/ramdisk.cpio.gz.uboot
275 21:37:35.697696 output: Image Name:
276 21:37:35.698314 output: Created: Mon Nov 4 21:37:35 2024
277 21:37:35.698749 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 21:37:35.699171 output: Data Size: 14790404 Bytes = 14443.75 KiB = 14.11 MiB
279 21:37:35.699580 output: Load Address: 00000000
280 21:37:35.700016 output: Entry Point: 00000000
281 21:37:35.700433 output:
282 21:37:35.701519 rename /var/lib/lava/dispatcher/tmp/936947/extract-overlay-ramdisk-bojgz7kz/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/936947/tftp-deploy-kz_c3zm3/ramdisk/ramdisk.cpio.gz.uboot
283 21:37:35.702252 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 21:37:35.702812 end: 1.6 prepare-tftp-overlay (duration 00:00:56) [common]
285 21:37:35.703401 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:48) [common]
286 21:37:35.703882 No LXC device requested
287 21:37:35.704433 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 21:37:35.704957 start: 1.8 deploy-device-env (timeout 00:08:48) [common]
289 21:37:35.705464 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 21:37:35.705883 Checking files for TFTP limit of 4294967296 bytes.
291 21:37:35.708553 end: 1 tftp-deploy (duration 00:01:12) [common]
292 21:37:35.709132 start: 2 uboot-action (timeout 00:05:00) [common]
293 21:37:35.709671 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 21:37:35.710179 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 21:37:35.710693 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 21:37:35.711449 substitutions:
297 21:37:35.711877 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 21:37:35.712327 - {DTB_ADDR}: 0x88000000
299 21:37:35.712738 - {DTB}: 936947/tftp-deploy-kz_c3zm3/dtb/am335x-boneblack.dtb
300 21:37:35.713144 - {INITRD}: 936947/tftp-deploy-kz_c3zm3/ramdisk/ramdisk.cpio.gz.uboot
301 21:37:35.713547 - {KERNEL_ADDR}: 0x82000000
302 21:37:35.713949 - {KERNEL}: 936947/tftp-deploy-kz_c3zm3/kernel/zImage
303 21:37:35.714349 - {LAVA_MAC}: None
304 21:37:35.714790 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/936947/extract-nfsrootfs-q3xx0mjv
305 21:37:35.715198 - {NFS_SERVER_IP}: 192.168.6.2
306 21:37:35.715600 - {PRESEED_CONFIG}: None
307 21:37:35.716014 - {PRESEED_LOCAL}: None
308 21:37:35.716416 - {RAMDISK_ADDR}: 0x83000000
309 21:37:35.716815 - {RAMDISK}: 936947/tftp-deploy-kz_c3zm3/ramdisk/ramdisk.cpio.gz.uboot
310 21:37:35.717216 - {ROOT_PART}: None
311 21:37:35.717611 - {ROOT}: None
312 21:37:35.718004 - {SERVER_IP}: 192.168.6.2
313 21:37:35.718397 - {TEE_ADDR}: 0x83000000
314 21:37:35.718787 - {TEE}: None
315 21:37:35.719178 Parsed boot commands:
316 21:37:35.719559 - setenv autoload no
317 21:37:35.719953 - setenv initrd_high 0xffffffff
318 21:37:35.720373 - setenv fdt_high 0xffffffff
319 21:37:35.720768 - dhcp
320 21:37:35.721160 - setenv serverip 192.168.6.2
321 21:37:35.721554 - tftp 0x82000000 936947/tftp-deploy-kz_c3zm3/kernel/zImage
322 21:37:35.721948 - tftp 0x83000000 936947/tftp-deploy-kz_c3zm3/ramdisk/ramdisk.cpio.gz.uboot
323 21:37:35.722343 - setenv initrd_size ${filesize}
324 21:37:35.722732 - tftp 0x88000000 936947/tftp-deploy-kz_c3zm3/dtb/am335x-boneblack.dtb
325 21:37:35.723125 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/936947/extract-nfsrootfs-q3xx0mjv,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 21:37:35.723529 - bootz 0x82000000 0x83000000 0x88000000
327 21:37:35.724054 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 21:37:35.725569 start: 2.3 connect-device (timeout 00:05:00) [common]
330 21:37:35.725993 [common] connect-device Connecting to device using 'telnet conserv3 3001'
331 21:37:35.740547 Setting prompt string to ['lava-test: # ']
332 21:37:35.742018 end: 2.3 connect-device (duration 00:00:00) [common]
333 21:37:35.742639 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 21:37:35.743193 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 21:37:35.743733 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 21:37:35.744938 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-04'
337 21:37:35.780416 >> OK - accepted request
338 21:37:35.782513 Returned 0 in 0 seconds
339 21:37:35.883682 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 21:37:35.885389 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 21:37:35.885965 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 21:37:35.886520 Setting prompt string to ['Hit any key to stop autoboot']
344 21:37:35.887023 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 21:37:35.888671 Trying 192.168.56.22...
346 21:37:35.889174 Connected to conserv3.
347 21:37:35.889589 Escape character is '^]'.
348 21:37:35.890002
349 21:37:35.890411 ser2net port telnet,3001 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 21:37:35.890826
351 21:38:12.567444
352 21:38:12.574389 U-Boot SPL 2023.01-rc4-00047-g3089d12a02 (Jan 01 2023 - 22:23:32 +0000)
353 21:38:12.574988 Trying to boot from MMC1
354 21:38:13.152889
355 21:38:13.153549
356 21:38:13.158283 U-Boot 2023.01-rc4-00047-g3089d12a02 (Jan 01 2023 - 22:23:32 +0000)
357 21:38:13.158866
358 21:38:13.159374 CPU : AM335X-GP rev 2.0
359 21:38:13.163356 Model: TI AM335x BeagleBone Black
360 21:38:13.163937 DRAM: 512 MiB
361 21:38:13.248233 Core: 160 devices, 18 uclasses, devicetree: separate
362 21:38:13.262003 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
363 21:38:13.662869 NAND: 0 MiB
364 21:38:13.672974 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
365 21:38:13.747691 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
366 21:38:13.769106 <ethaddr> not set. Validating first E-fuse MAC
367 21:38:13.798748 Net: eth2: ethernet@4a100000, eth3: usb_ether
369 21:38:13.857224 Hit any key to stop autoboot: 2
370 21:38:13.858279 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
371 21:38:13.858925 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
372 21:38:13.859441 Setting prompt string to ['=>']
373 21:38:13.859958 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
374 21:38:13.867088 0
375 21:38:13.867961 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
376 21:38:13.868488 Sending with 10 millisecond of delay
378 21:38:15.003884 => setenv autoload no
379 21:38:15.014692 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
380 21:38:15.019562 setenv autoload no
381 21:38:15.020336 Sending with 10 millisecond of delay
383 21:38:16.818106 => setenv initrd_high 0xffffffff
384 21:38:16.828897 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
385 21:38:16.829767 setenv initrd_high 0xffffffff
386 21:38:16.830543 Sending with 10 millisecond of delay
388 21:38:18.448072 => setenv fdt_high 0xffffffff
389 21:38:18.458880 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
390 21:38:18.459769 setenv fdt_high 0xffffffff
391 21:38:18.460506 Sending with 10 millisecond of delay
393 21:38:18.752437 => dhcp
394 21:38:18.763210 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
395 21:38:18.764090 dhcp
396 21:38:18.765931 link up on port 0, speed 100, full duplex
397 21:38:18.766430 BOOTP broadcast 1
398 21:38:18.835232 DHCP client bound to address 192.168.6.16 (66 ms)
399 21:38:18.836096 Sending with 10 millisecond of delay
401 21:38:20.513124 => setenv serverip 192.168.6.2
402 21:38:20.523972 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
403 21:38:20.525035 setenv serverip 192.168.6.2
404 21:38:20.525800 Sending with 10 millisecond of delay
406 21:38:24.011581 => tftp 0x82000000 936947/tftp-deploy-kz_c3zm3/kernel/zImage
407 21:38:24.022527 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
408 21:38:24.023483 tftp 0x82000000 936947/tftp-deploy-kz_c3zm3/kernel/zImage
409 21:38:24.024023 link up on port 0, speed 100, full duplex
410 21:38:24.027512 Using ethernet@4a100000 device
411 21:38:24.033129 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
412 21:38:24.034126 Filename '936947/tftp-deploy-kz_c3zm3/kernel/zImage'.
413 21:38:24.040403 Load address: 0x82000000
414 21:38:26.225509 Loading: *################################################## 10.9 MiB
415 21:38:26.225925 5 MiB/s
416 21:38:26.226168 done
417 21:38:26.229511 Bytes transferred = 11440640 (ae9200 hex)
418 21:38:26.230038 Sending with 10 millisecond of delay
420 21:38:30.677796 => tftp 0x83000000 936947/tftp-deploy-kz_c3zm3/ramdisk/ramdisk.cpio.gz.uboot
421 21:38:30.688609 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
422 21:38:30.689490 tftp 0x83000000 936947/tftp-deploy-kz_c3zm3/ramdisk/ramdisk.cpio.gz.uboot
423 21:38:30.689934 link up on port 0, speed 100, full duplex
424 21:38:30.693248 Using ethernet@4a100000 device
425 21:38:30.698826 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
426 21:38:30.707487 Filename '936947/tftp-deploy-kz_c3zm3/ramdisk/ramdisk.cpio.gz.uboot'.
427 21:38:30.707952 Load address: 0x83000000
428 21:38:33.464142 Loading: *################################################## 14.1 MiB
429 21:38:33.464785 5.1 MiB/s
430 21:38:33.465216 done
431 21:38:33.468352 Bytes transferred = 14790468 (e1af44 hex)
432 21:38:33.469213 Sending with 10 millisecond of delay
434 21:38:35.326578 => setenv initrd_size ${filesize}
435 21:38:35.337327 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
436 21:38:35.337856 setenv initrd_size ${filesize}
437 21:38:35.338367 Sending with 10 millisecond of delay
439 21:38:39.488580 => tftp 0x88000000 936947/tftp-deploy-kz_c3zm3/dtb/am335x-boneblack.dtb
440 21:38:39.499436 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:56)
441 21:38:39.500480 tftp 0x88000000 936947/tftp-deploy-kz_c3zm3/dtb/am335x-boneblack.dtb
442 21:38:39.500975 link up on port 0, speed 100, full duplex
443 21:38:39.504080 Using ethernet@4a100000 device
444 21:38:39.509756 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
445 21:38:39.520629 Filename '936947/tftp-deploy-kz_c3zm3/dtb/am335x-boneblack.dtb'.
446 21:38:39.521236 Load address: 0x88000000
447 21:38:39.531571 Loading: *################################################## 68.9 KiB
448 21:38:39.532201 4.5 MiB/s
449 21:38:39.539306 done
450 21:38:39.539820 Bytes transferred = 70568 (113a8 hex)
451 21:38:39.540579 Sending with 10 millisecond of delay
453 21:38:52.724263 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/936947/extract-nfsrootfs-q3xx0mjv,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
454 21:38:52.735029 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:43)
455 21:38:52.735898 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/936947/extract-nfsrootfs-q3xx0mjv,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
456 21:38:52.736658 Sending with 10 millisecond of delay
458 21:38:55.076158 => bootz 0x82000000 0x83000000 0x88000000
459 21:38:55.086965 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
460 21:38:55.087574 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:41)
461 21:38:55.088645 bootz 0x82000000 0x83000000 0x88000000
462 21:38:55.089162 Kernel image @ 0x82000000 [ 0x000000 - 0xae9200 ]
463 21:38:55.089687 ## Loading init Ramdisk from Legacy Image at 83000000 ...
464 21:38:55.094890 Image Name:
465 21:38:55.095339 Created: 2024-11-04 21:37:35 UTC
466 21:38:55.098306 Image Type: ARM Linux RAMDisk Image (uncompressed)
467 21:38:55.103769 Data Size: 14790404 Bytes = 14.1 MiB
468 21:38:55.111940 Load Address: 00000000
469 21:38:55.112402 Entry Point: 00000000
470 21:38:55.280457 Verifying Checksum ... OK
471 21:38:55.281040 ## Flattened Device Tree blob at 88000000
472 21:38:55.287073 Booting using the fdt blob at 0x88000000
473 21:38:55.287522 Working FDT set to 88000000
474 21:38:55.292598 Using Device Tree in place at 88000000, end 880143a7
475 21:38:55.296410 Working FDT set to 88000000
476 21:38:55.309888
477 21:38:55.310353 Starting kernel ...
478 21:38:55.310749
479 21:38:55.311605 end: 2.4.3 bootloader-commands (duration 00:00:41) [common]
480 21:38:55.312234 start: 2.4.4 auto-login-action (timeout 00:03:40) [common]
481 21:38:55.312690 Setting prompt string to ['Linux version [0-9]']
482 21:38:55.313139 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
483 21:38:55.313591 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
484 21:38:56.156995 [ 0.000000] Booting Linux on physical CPU 0x0
485 21:38:56.162830 start: 2.4.4.1 login-action (timeout 00:03:40) [common]
486 21:38:56.163333 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
487 21:38:56.163620 Setting prompt string to []
488 21:38:56.163883 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
489 21:38:56.164171 Using line separator: #'\n'#
490 21:38:56.164403 No login prompt set.
491 21:38:56.164648 Parsing kernel messages
492 21:38:56.164866 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
493 21:38:56.165275 [login-action] Waiting for messages, (timeout 00:03:40)
494 21:38:56.165513 Waiting using forced prompt support (timeout 00:01:50)
495 21:38:56.179759 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j362256-arm-gcc-12-multi-v7-defconfig-6tgvj) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Mon Nov 4 21:15:50 UTC 2024
496 21:38:56.185353 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
497 21:38:56.191063 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
498 21:38:56.202472 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
499 21:38:56.208230 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
500 21:38:56.214013 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
501 21:38:56.214454 [ 0.000000] Memory policy: Data cache writeback
502 21:38:56.220608 [ 0.000000] efi: UEFI not found.
503 21:38:56.229471 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
504 21:38:56.229913 [ 0.000000] Zone ranges:
505 21:38:56.235126 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
506 21:38:56.240871 [ 0.000000] Normal empty
507 21:38:56.246621 [ 0.000000] HighMem empty
508 21:38:56.247058 [ 0.000000] Movable zone start for each node
509 21:38:56.252439 [ 0.000000] Early memory node ranges
510 21:38:56.258113 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
511 21:38:56.265051 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
512 21:38:56.291182 [ 0.000000] CPU: All CPU(s) started in SVC mode.
513 21:38:56.296742 [ 0.000000] AM335X ES2.0 (sgx neon)
514 21:38:56.308515 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
515 21:38:56.328872 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/936947/extract-nfsrootfs-q3xx0mjv,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
516 21:38:56.334742 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
517 21:38:56.346164 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
518 21:38:56.351887 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
519 21:38:56.359214 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
520 21:38:56.388380 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
521 21:38:56.394240 <6>[ 0.000000] trace event string verifier disabled
522 21:38:56.394679 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
523 21:38:56.400003 <6>[ 0.000000] rcu: RCU event tracing is enabled.
524 21:38:56.411476 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
525 21:38:56.417163 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
526 21:38:56.424462 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
527 21:38:56.439370 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
528 21:38:56.456469 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
529 21:38:56.463256 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
530 21:38:56.554920 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
531 21:38:56.566401 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
532 21:38:56.573140 <6>[ 0.008338] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
533 21:38:56.586291 <6>[ 0.019146] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
534 21:38:56.593543 <6>[ 0.033938] Console: colour dummy device 80x30
535 21:38:56.599617 Matched prompt #6: WARNING:
536 21:38:56.600145 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
537 21:38:56.605087 <3>[ 0.038838] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
538 21:38:56.610766 <3>[ 0.045905] This ensures that you still see kernel messages. Please
539 21:38:56.614018 <3>[ 0.052632] update your kernel commandline.
540 21:38:56.654734 <6>[ 0.057245] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
541 21:38:56.660625 <6>[ 0.096153] CPU: Testing write buffer coherency: ok
542 21:38:56.663281 <6>[ 0.101521] CPU0: Spectre v2: using BPIALL workaround
543 21:38:56.669178 <6>[ 0.106982] pid_max: default: 32768 minimum: 301
544 21:38:56.674918 <6>[ 0.112177] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
545 21:38:56.687615 <6>[ 0.119998] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
546 21:38:56.691776 <6>[ 0.129349] CPU0: thread -1, cpu 0, socket -1, mpidr 0
547 21:38:56.752416 <6>[ 0.189536] Setting up static identity map for 0x80300000 - 0x803000ac
548 21:38:56.758827 <6>[ 0.199134] rcu: Hierarchical SRCU implementation.
549 21:38:56.766959 <6>[ 0.204427] rcu: Max phase no-delay instances is 1000.
550 21:38:56.775384 <6>[ 0.215446] EFI services will not be available.
551 21:38:56.781124 <6>[ 0.220807] smp: Bringing up secondary CPUs ...
552 21:38:56.787064 <6>[ 0.225777] smp: Brought up 1 node, 1 CPU
553 21:38:56.792705 <6>[ 0.230267] SMP: Total of 1 processors activated (996.14 BogoMIPS).
554 21:38:56.798623 <6>[ 0.236990] CPU: All CPU(s) started in SVC mode.
555 21:38:56.818979 <6>[ 0.242191] Memory: 406000K/522240K available (16384K kernel code, 2542K rwdata, 6784K rodata, 2048K init, 431K bss, 49048K reserved, 65536K cma-reserved, 0K highmem)
556 21:38:56.819432 <6>[ 0.258470] devtmpfs: initialized
557 21:38:56.841218 <6>[ 0.275540] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
558 21:38:56.849560 <6>[ 0.284150] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
559 21:38:56.857802 <6>[ 0.294591] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
560 21:38:56.869454 <6>[ 0.306898] pinctrl core: initialized pinctrl subsystem
561 21:38:56.878701 <6>[ 0.317555] DMI not present or invalid.
562 21:38:56.887132 <6>[ 0.323414] NET: Registered PF_NETLINK/PF_ROUTE protocol family
563 21:38:56.896582 <6>[ 0.332377] DMA: preallocated 256 KiB pool for atomic coherent allocations
564 21:38:56.911680 <6>[ 0.343820] thermal_sys: Registered thermal governor 'step_wise'
565 21:38:56.912155 <6>[ 0.343998] cpuidle: using governor menu
566 21:38:56.939338 <6>[ 0.379785] No ATAGs?
567 21:38:56.945524 <6>[ 0.382428] hw-breakpoint: debug architecture 0x4 unsupported.
568 21:38:56.955768 <6>[ 0.394362] Serial: AMBA PL011 UART driver
569 21:38:56.985522 <6>[ 0.425635] iommu: Default domain type: Translated
570 21:38:56.994510 <6>[ 0.430986] iommu: DMA domain TLB invalidation policy: strict mode
571 21:38:57.021420 <5>[ 0.460341] SCSI subsystem initialized
572 21:38:57.035814 <6>[ 0.470481] usbcore: registered new interface driver usbfs
573 21:38:57.042665 <6>[ 0.476443] usbcore: registered new interface driver hub
574 21:38:57.042953 <6>[ 0.482269] usbcore: registered new device driver usb
575 21:38:57.050150 <6>[ 0.488754] pps_core: LinuxPPS API ver. 1 registered
576 21:38:57.061693 <6>[ 0.494190] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
577 21:38:57.068742 <6>[ 0.503907] PTP clock support registered
578 21:38:57.069005 <6>[ 0.508355] EDAC MC: Ver: 3.0.0
579 21:38:57.116095 <6>[ 0.553821] scmi_core: SCMI protocol bus registered
580 21:38:57.140717 <6>[ 0.580336] vgaarb: loaded
581 21:38:57.146818 <6>[ 0.584119] clocksource: Switched to clocksource dmtimer
582 21:38:57.171066 <6>[ 0.611069] NET: Registered PF_INET protocol family
583 21:38:57.183743 <6>[ 0.616772] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
584 21:38:57.190764 <6>[ 0.625615] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
585 21:38:57.202246 <6>[ 0.634543] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
586 21:38:57.208016 <6>[ 0.642785] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
587 21:38:57.213863 <6>[ 0.651071] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
588 21:38:57.219703 <6>[ 0.658790] TCP: Hash tables configured (established 4096 bind 4096)
589 21:38:57.231181 <6>[ 0.665721] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
590 21:38:57.237098 <6>[ 0.672735] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
591 21:38:57.243341 <6>[ 0.680352] NET: Registered PF_UNIX/PF_LOCAL protocol family
592 21:38:57.329308 <6>[ 0.763971] RPC: Registered named UNIX socket transport module.
593 21:38:57.329693 <6>[ 0.770414] RPC: Registered udp transport module.
594 21:38:57.335076 <6>[ 0.775544] RPC: Registered tcp transport module.
595 21:38:57.340824 <6>[ 0.780650] RPC: Registered tcp-with-tls transport module.
596 21:38:57.353823 <6>[ 0.786573] RPC: Registered tcp NFSv4.1 backchannel transport module.
597 21:38:57.354122 <6>[ 0.793480] PCI: CLS 0 bytes, default 64
598 21:38:57.361011 <5>[ 0.799286] Initialise system trusted keyrings
599 21:38:57.382073 <6>[ 0.819371] Trying to unpack rootfs image as initramfs...
600 21:38:57.461127 <6>[ 0.895220] workingset: timestamp_bits=30 max_order=17 bucket_order=0
601 21:38:57.465739 <6>[ 0.902739] squashfs: version 4.0 (2009/01/31) Phillip Lougher
602 21:38:57.504811 <5>[ 0.944989] NFS: Registering the id_resolver key type
603 21:38:57.510503 <5>[ 0.950581] Key type id_resolver registered
604 21:38:57.516303 <5>[ 0.955276] Key type id_legacy registered
605 21:38:57.522056 <6>[ 0.959714] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
606 21:38:57.531642 <6>[ 0.966911] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
607 21:38:57.604479 <5>[ 1.044730] Key type asymmetric registered
608 21:38:57.610259 <5>[ 1.049258] Asymmetric key parser 'x509' registered
609 21:38:57.621755 <6>[ 1.054741] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
610 21:38:57.622034 <6>[ 1.062630] io scheduler mq-deadline registered
611 21:38:57.627557 <6>[ 1.067615] io scheduler kyber registered
612 21:38:57.633156 <6>[ 1.072073] io scheduler bfq registered
613 21:38:57.733577 <6>[ 1.170232] ledtrig-cpu: registered to indicate activity on CPUs
614 21:38:58.014266 <6>[ 1.450684] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
615 21:38:58.048884 <6>[ 1.489034] msm_serial: driver initialized
616 21:38:58.054989 <6>[ 1.493817] SuperH (H)SCI(F) driver initialized
617 21:38:58.060933 <6>[ 1.499151] STMicroelectronics ASC driver initialized
618 21:38:58.066143 <6>[ 1.504845] STM32 USART driver initialized
619 21:38:58.207325 <6>[ 1.647036] brd: module loaded
620 21:38:58.242137 <6>[ 1.681793] loop: module loaded
621 21:38:58.282767 <6>[ 1.722219] CAN device driver interface
622 21:38:58.289452 <6>[ 1.727468] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
623 21:38:58.295146 <6>[ 1.734512] e1000e: Intel(R) PRO/1000 Network Driver
624 21:38:58.300984 <6>[ 1.739901] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
625 21:38:58.306738 <6>[ 1.746352] igb: Intel(R) Gigabit Ethernet Network Driver
626 21:38:58.314980 <6>[ 1.752176] igb: Copyright (c) 2007-2014 Intel Corporation.
627 21:38:58.326843 <6>[ 1.761325] pegasus: Pegasus/Pegasus II USB Ethernet driver
628 21:38:58.332518 <6>[ 1.767491] usbcore: registered new interface driver pegasus
629 21:38:58.338359 <6>[ 1.773620] usbcore: registered new interface driver asix
630 21:38:58.344103 <6>[ 1.779507] usbcore: registered new interface driver ax88179_178a
631 21:38:58.349876 <6>[ 1.786102] usbcore: registered new interface driver cdc_ether
632 21:38:58.355634 <6>[ 1.792400] usbcore: registered new interface driver smsc75xx
633 21:38:58.361418 <6>[ 1.798631] usbcore: registered new interface driver smsc95xx
634 21:38:58.367192 <6>[ 1.804868] usbcore: registered new interface driver net1080
635 21:38:58.372995 <6>[ 1.810993] usbcore: registered new interface driver cdc_subset
636 21:38:58.378820 <6>[ 1.817404] usbcore: registered new interface driver zaurus
637 21:38:58.386409 <6>[ 1.823451] usbcore: registered new interface driver cdc_ncm
638 21:38:58.396186 <6>[ 1.832812] usbcore: registered new interface driver usb-storage
639 21:38:58.678078 <6>[ 2.116429] i2c_dev: i2c /dev entries driver
640 21:38:58.741131 <5>[ 2.173423] cpuidle: enable-method property 'ti,am3352' found operations
641 21:38:58.746965 <6>[ 2.183060] sdhci: Secure Digital Host Controller Interface driver
642 21:38:58.754393 <6>[ 2.189838] sdhci: Copyright(c) Pierre Ossman
643 21:38:58.761460 <6>[ 2.196281] Synopsys Designware Multimedia Card Interface Driver
644 21:38:58.766136 <6>[ 2.204007] sdhci-pltfm: SDHCI platform and OF driver helper
645 21:38:58.882377 <6>[ 2.315191] usbcore: registered new interface driver usbhid
646 21:38:58.882999 <6>[ 2.321233] usbhid: USB HID core driver
647 21:38:58.933132 <6>[ 2.370792] NET: Registered PF_INET6 protocol family
648 21:38:58.965073 <6>[ 2.405335] Segment Routing with IPv6
649 21:38:58.970806 <6>[ 2.409485] In-situ OAM (IOAM) with IPv6
650 21:38:58.977550 <6>[ 2.413886] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
651 21:38:58.983303 <6>[ 2.421245] NET: Registered PF_PACKET protocol family
652 21:38:58.989128 <6>[ 2.426811] can: controller area network core
653 21:38:58.994980 <6>[ 2.431638] NET: Registered PF_CAN protocol family
654 21:38:58.995460 <6>[ 2.436867] can: raw protocol
655 21:38:59.000767 <6>[ 2.440194] can: broadcast manager protocol
656 21:38:59.007278 <6>[ 2.444791] can: netlink gateway - max_hops=1
657 21:38:59.013357 <5>[ 2.450293] Key type dns_resolver registered
658 21:38:59.019650 <6>[ 2.455398] ThumbEE CPU extension supported.
659 21:38:59.020210 <5>[ 2.460087] Registering SWP/SWPB emulation handler
660 21:38:59.029413 <3>[ 2.465791] omap_voltage_late_init: Voltage driver support not added
661 21:38:59.215911 <5>[ 2.654642] Loading compiled-in X.509 certificates
662 21:38:59.345921 <6>[ 2.773347] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
663 21:38:59.353132 <6>[ 2.790027] pinctrl-single 44e10800.pinmux: 142 pins, size 568
664 21:38:59.379606 <3>[ 2.813853] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
665 21:38:59.580572 <3>[ 3.014839] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
666 21:38:59.787492 <6>[ 3.226019] OMAP GPIO hardware version 0.1
667 21:38:59.807283 <6>[ 3.244926] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
668 21:38:59.899753 <4>[ 3.336137] at24 2-0054: supply vcc not found, using dummy regulator
669 21:38:59.938964 <4>[ 3.376348] at24 2-0055: supply vcc not found, using dummy regulator
670 21:38:59.974411 <4>[ 3.410810] at24 2-0056: supply vcc not found, using dummy regulator
671 21:39:00.012515 <4>[ 3.448916] at24 2-0057: supply vcc not found, using dummy regulator
672 21:39:00.050120 <6>[ 3.487302] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
673 21:39:00.126943 <3>[ 3.560124] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
674 21:39:00.151523 <6>[ 3.581052] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
675 21:39:00.172682 <4>[ 3.607854] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
676 21:39:00.199780 <4>[ 3.634968] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
677 21:39:00.318233 <6>[ 3.754605] omap_rng 48310000.rng: Random Number Generator ver. 20
678 21:39:00.341653 <5>[ 3.781025] random: crng init done
679 21:39:00.397028 <6>[ 3.837198] Freeing initrd memory: 14444K
680 21:39:00.406736 <6>[ 3.841838] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
681 21:39:00.462827 <6>[ 3.896555] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
682 21:39:00.468421 <6>[ 3.906890] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
683 21:39:00.480117 <6>[ 3.914232] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
684 21:39:00.485924 <6>[ 3.921681] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
685 21:39:00.497434 <6>[ 3.929819] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
686 21:39:00.504801 <6>[ 3.941454] cpsw-switch 4a100000.switch: Detected MACID = c8:a0:30:c2:c5:7d
687 21:39:00.517895 <5>[ 3.950469] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
688 21:39:00.545784 <3>[ 3.980389] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
689 21:39:00.551621 <6>[ 3.988980] edma 49000000.dma: TI EDMA DMA engine driver
690 21:39:00.623204 <3>[ 4.057044] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
691 21:39:00.637822 <6>[ 4.071442] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
692 21:39:00.650777 <3>[ 4.088566] l3-aon-clkctrl:0000:0: failed to disable
693 21:39:00.700780 <6>[ 4.135261] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
694 21:39:00.706372 <6>[ 4.144729] printk: legacy console [ttyS0] enabled
695 21:39:00.709221 <6>[ 4.144729] printk: legacy console [ttyS0] enabled
696 21:39:00.714789 <6>[ 4.155059] printk: legacy bootconsole [omap8250] disabled
697 21:39:00.720481 <6>[ 4.155059] printk: legacy bootconsole [omap8250] disabled
698 21:39:00.761390 <4>[ 4.194879] tps65217-pmic: Failed to locate of_node [id: -1]
699 21:39:00.764895 <4>[ 4.202276] tps65217-bl: Failed to locate of_node [id: -1]
700 21:39:00.781403 <6>[ 4.222012] tps65217 0-0024: TPS65217 ID 0xe version 1.2
701 21:39:00.799831 <6>[ 4.228976] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
702 21:39:00.811518 <6>[ 4.242659] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
703 21:39:00.817253 <6>[ 4.254533] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
704 21:39:00.839610 <6>[ 4.274701] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
705 21:39:00.845563 <6>[ 4.283755] sdhci-omap 48060000.mmc: Got CD GPIO
706 21:39:00.853632 <4>[ 4.288988] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
707 21:39:00.868388 <4>[ 4.302450] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
708 21:39:00.875585 <4>[ 4.311181] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
709 21:39:00.884391 <4>[ 4.319756] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
710 21:39:00.984116 <6>[ 4.419214] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
711 21:39:01.030329 <6>[ 4.464394] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
712 21:39:01.036939 <6>[ 4.473435] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
713 21:39:01.046007 <6>[ 4.482420] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
714 21:39:01.097951 <6>[ 4.535355] mmc0: new high speed SDHC card at address 0001
715 21:39:01.106061 <6>[ 4.544545] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
716 21:39:01.115863 <6>[ 4.556241] mmcblk0: p1
717 21:39:01.133624 <6>[ 4.565976] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
718 21:39:01.143457 <4>[ 4.581737] mmc1: unexpected status 0x2000980 after switch
719 21:39:01.160780 <4>[ 4.595490] mmc1: unexpected status 0x2000900 after switch
720 21:39:01.167058 <4>[ 4.601646] mmc1: unexpected status 0x2000900 after switch
721 21:39:01.169301 <4>[ 4.608120] mmc1: unexpected status 0x2000900 after switch
722 21:39:01.176244 <6>[ 4.613948] mmc1: new high speed MMC card at address 0001
723 21:39:01.182384 <6>[ 4.620962] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
724 21:39:02.784514 <4>[ 6.217558] mmc1: unexpected status 0x2000980 after switch
725 21:39:02.790517 <4>[ 6.225234] mmc1: unexpected status 0x2000900 after switch
726 21:39:02.792205 <4>[ 6.231522] mmc1: unexpected status 0x2000900 after switch
727 21:39:02.801112 <4>[ 6.238424] mmc1: unexpected status 0x2000900 after switch
728 21:39:03.240669 <6>[ 6.675181] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
729 21:39:03.353972 <5>[ 6.714122] Sending DHCP requests ., OK
730 21:39:03.365259 <6>[ 6.798687] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.16
731 21:39:03.365720 <6>[ 6.806855] IP-Config: Complete:
732 21:39:03.376490 <6>[ 6.810393] device=eth0, hwaddr=c8:a0:30:c2:c5:7d, ipaddr=192.168.6.16, mask=255.255.255.0, gw=192.168.6.1
733 21:39:03.382283 <6>[ 6.820913] host=192.168.6.16, domain=, nis-domain=(none)
734 21:39:03.394580 <6>[ 6.827124] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
735 21:39:03.395023 <6>[ 6.827158] nameserver0=10.255.253.1
736 21:39:03.400693 <6>[ 6.839735] clk: Disabling unused clocks
737 21:39:03.406411 <6>[ 6.844448] PM: genpd: Disabling unused power domains
738 21:39:03.425726 <6>[ 6.862832] Freeing unused kernel image (initmem) memory: 2048K
739 21:39:03.432425 <6>[ 6.872596] Run /init as init process
740 21:39:03.458577 Loading, please wait...
741 21:39:03.559690 <3>[ 6.994226] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
742 21:39:03.593556 Starting systemd-udevd version 252.22-1~deb12u1
743 21:39:04.346297 <3>[ 7.780756] I/O error, dev mmcblk1, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
744 21:39:05.135381 <3>[ 8.569752] I/O error, dev mmcblk1, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
745 21:39:05.892804 <3>[ 9.328206] I/O error, dev mmcblk1, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
746 21:39:06.720169 <3>[ 10.154768] I/O error, dev mmcblk1, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
747 21:39:06.823316 <4>[ 10.256628] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
748 21:39:07.002400 <4>[ 10.435767] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
749 21:39:07.212292 <6>[ 10.653107] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
750 21:39:07.223153 <6>[ 10.658944] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
751 21:39:07.491758 <6>[ 10.930881] hub 1-0:1.0: USB hub found
752 21:39:07.497424 <6>[ 10.936598] tda998x 0-0070: found TDA19988
753 21:39:07.505652 <3>[ 10.941148] I/O error, dev mmcblk1, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
754 21:39:07.515322 <6>[ 10.954345] hub 1-0:1.0: 1 port detected
755 21:39:08.310277 <3>[ 11.745833] I/O error, dev mmcblk1, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
756 21:39:08.446870 <6>[ 11.884359] usb 1-1: new low-speed USB device number 2 using musb-hdrc
757 21:39:08.586698 <3>[ 12.024365] usb 1-1: device descriptor read/64, error -71
758 21:39:08.876699 <3>[ 12.314418] usb 1-1: device descriptor read/64, error -71
759 21:39:09.103519 <3>[ 12.538605] I/O error, dev mmcblk1, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
760 21:39:09.111555 <3>[ 12.547554] Buffer I/O error on dev mmcblk1, logical block 0, async page read
761 21:39:09.190457 <6>[ 12.627024] usb 1-1: new low-speed USB device number 3 using musb-hdrc
762 21:39:09.366596 <3>[ 12.804418] usb 1-1: device descriptor read/64, error -71
763 21:39:09.635714 <3>[ 13.074387] usb 1-1: device descriptor read/64, error -71
764 21:39:09.754474 <6>[ 13.193935] usb usb1-port1: attempt power cycle
765 21:39:10.087643 <6>[ 13.524411] usb 1-1: new low-speed USB device number 4 using musb-hdrc
766 21:39:10.646379 <6>[ 14.082866] usb 1-1: new low-speed USB device number 5 using musb-hdrc
767 21:39:11.165997 Begin: Loading essential drivers ... done.
768 21:39:11.171365 Begin: Running /scripts/init-premount ... done.
769 21:39:11.176787 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
770 21:39:11.190472 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
771 21:39:11.191055 Device /sys/class/net/eth0 found
772 21:39:11.191521 done.
773 21:39:11.246524 Begin: Waiting up to 180 secs for any network device to become available ... done.
774 21:39:11.316703 IP-Config: eth0 hardware address c8:a0:30:c2:c5:7d mtu 1500 DHCP
775 21:39:11.530695 IP-Config: eth0 guessed broadcast address 192.168.6.255
776 21:39:11.536401 IP-Config: eth0 complete (dhcp from 192.168.6.1):
777 21:39:11.541791 address: 192.168.6.16 broadcast: 192.168.6.255 netmask: 255.255.255.0
778 21:39:11.552967 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
779 21:39:11.553616 rootserver: 192.168.6.1 rootpath:
780 21:39:11.555939 filename :
781 21:39:11.662405 done.
782 21:39:11.677913 Begin: Running /scripts/nfs-bottom ... done.
783 21:39:11.739773 Begin: Running /scripts/init-bottom ... done.
784 21:39:12.295929 <3>[ 15.731349] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
785 21:39:13.067784 <3>[ 16.503471] I/O error, dev mmcblk1, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
786 21:39:13.531153 <30>[ 16.968270] systemd[1]: System time before build time, advancing clock.
787 21:39:13.839192 <3>[ 17.272993] I/O error, dev mmcblk1, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
788 21:39:13.969699 <30>[ 17.380725] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
789 21:39:13.978359 <30>[ 17.417480] systemd[1]: Detected architecture arm.
790 21:39:13.990772
791 21:39:13.991104 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
792 21:39:13.991348
793 21:39:14.016670 <30>[ 17.454574] systemd[1]: Hostname set to <debian-bookworm-armhf>.
794 21:39:14.679027 <3>[ 18.114480] I/O error, dev mmcblk1, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
795 21:39:15.438252 <3>[ 18.873792] I/O error, dev mmcblk1, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
796 21:39:16.196592 <3>[ 19.632211] I/O error, dev mmcblk1, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
797 21:39:16.380100 <30>[ 19.816377] systemd[1]: Queued start job for default target graphical.target.
798 21:39:16.397500 <30>[ 19.830997] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
799 21:39:16.403953 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
800 21:39:16.433758 <30>[ 19.866947] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
801 21:39:16.441307 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
802 21:39:16.465858 <30>[ 19.900191] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
803 21:39:16.478927 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
804 21:39:16.501144 <30>[ 19.935928] systemd[1]: Created slice user.slice - User and Session Slice.
805 21:39:16.507810 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
806 21:39:16.537788 <30>[ 19.965293] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
807 21:39:16.543667 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
808 21:39:16.572447 <30>[ 20.006235] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
809 21:39:16.583401 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
810 21:39:16.621446 <30>[ 20.045112] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
811 21:39:16.627848 <30>[ 20.065522] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
812 21:39:16.636353 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
813 21:39:16.659553 <30>[ 20.094532] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
814 21:39:16.667960 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
815 21:39:16.691712 <30>[ 20.126094] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
816 21:39:16.703950 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
817 21:39:16.730225 <30>[ 20.164965] systemd[1]: Reached target paths.target - Path Units.
818 21:39:16.735367 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
819 21:39:16.760178 <30>[ 20.194842] systemd[1]: Reached target remote-fs.target - Remote File Systems.
820 21:39:16.767611 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
821 21:39:16.790264 <30>[ 20.224689] systemd[1]: Reached target slices.target - Slice Units.
822 21:39:16.796196 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
823 21:39:16.820086 <30>[ 20.254933] systemd[1]: Reached target swap.target - Swaps.
824 21:39:16.824133 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
825 21:39:16.850264 <30>[ 20.284919] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
826 21:39:16.859207 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
827 21:39:16.881196 <30>[ 20.315664] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
828 21:39:16.889535 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
829 21:39:16.958339 <3>[ 20.393285] I/O error, dev mmcblk1, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
830 21:39:17.042755 <30>[ 20.472492] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
831 21:39:17.055558 <30>[ 20.490019] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
832 21:39:17.064015 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
833 21:39:17.091780 <30>[ 20.525823] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
834 21:39:17.099210 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
835 21:39:17.123372 <30>[ 20.557641] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
836 21:39:17.131564 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
837 21:39:17.161683 <30>[ 20.595373] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
838 21:39:17.167293 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
839 21:39:17.191361 <30>[ 20.625813] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
840 21:39:17.199909 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
841 21:39:17.227551 <30>[ 20.655977] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
842 21:39:17.244245 <30>[ 20.672715] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
843 21:39:17.295730 <30>[ 20.731184] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
844 21:39:17.320223 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
845 21:39:17.370495 <30>[ 20.805824] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
846 21:39:17.400646 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
847 21:39:17.461043 <30>[ 20.895448] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
848 21:39:17.471598 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
849 21:39:17.511765 <30>[ 20.946783] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
850 21:39:17.538116 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
851 21:39:17.589976 <30>[ 21.025334] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
852 21:39:17.608999 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
853 21:39:17.640749 <30>[ 21.076514] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
854 21:39:17.722747 Starting [0;1;39mmodprobe@drm.service[0m - Load Kerne<3>[ 21.152908] I/O error, dev mmcblk1, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
855 21:39:17.723427 l Module drm...
856 21:39:17.733973 <3>[ 21.167157] Buffer I/O error on dev mmcblk1, logical block 0, async page read
857 21:39:17.740283 <6>[ 21.176190] mmcblk1: unable to read partition table
858 21:39:17.743483 <6>[ 21.182033] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
859 21:39:17.769324 <6>[ 21.207671] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
860 21:39:17.785438 <6>[ 21.218441] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
861 21:39:17.791890 <30>[ 21.227449] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
862 21:39:17.830862 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
863 21:39:17.879729 <30>[ 21.315346] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
864 21:39:17.899440 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
865 21:39:17.930798 <30>[ 21.366411] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
866 21:39:17.958893 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
867 21:39:17.986732 <28>[ 21.416445] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
868 21:39:17.995243 <28>[ 21.430052] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
869 21:39:18.039483 <30>[ 21.475592] systemd[1]: Starting systemd-journald.service - Journal Service...
870 21:39:18.059008 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
871 21:39:18.131801 <30>[ 21.567235] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
872 21:39:18.148462 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
873 21:39:18.175633 <30>[ 21.611283] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
874 21:39:18.220726 Starting [0;1;39msystemd-network-g… units from Kernel command line...
875 21:39:18.273316 <30>[ 21.707442] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
876 21:39:18.320247 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
877 21:39:18.375010 <30>[ 21.809949] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
878 21:39:18.439968 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
879 21:39:18.507124 <30>[ 21.942939] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
880 21:39:18.567834 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
881 21:39:18.610709 <30>[ 22.046417] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
882 21:39:18.635130 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
883 21:39:18.664246 <30>[ 22.098838] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
884 21:39:18.692884 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
885 21:39:18.890395 <30>[ 22.326734] systemd[1]: modprobe@configfs.service: Deactivated successfully.
886 21:39:18.915135 <30>[ 22.350163] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
887 21:39:18.949490 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
888 21:39:18.970830 <30>[ 22.405886] systemd[1]: Started systemd-journald.service - Journal Service.
889 21:39:18.977795 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
890 21:39:19.012175 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
891 21:39:19.035235 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
892 21:39:19.066150 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
893 21:39:19.104554 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
894 21:39:19.140990 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
895 21:39:19.163530 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
896 21:39:19.199820 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
897 21:39:19.229844 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
898 21:39:19.254562 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
899 21:39:19.319121 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
900 21:39:19.390554 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
901 21:39:19.450639 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
902 21:39:19.539894 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
903 21:39:19.638636 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
904 21:39:19.717480 <46>[ 23.153185] systemd-journald[164]: Received client request to flush runtime journal.
905 21:39:19.755130 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
906 21:39:19.803591 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
907 21:39:20.678395 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
908 21:39:21.051589 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
909 21:39:21.122017 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
910 21:39:21.479733 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
911 21:39:21.751135 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
912 21:39:21.779240 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
913 21:39:21.798924 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
914 21:39:21.879136 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
915 21:39:21.928073 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
916 21:39:22.839834 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
917 21:39:22.910538 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
918 21:39:23.032684 <4>[ 26.470855] mmc1: unexpected status 0x2000980 after switch
919 21:39:23.055523 <4>[ 26.494441] mmc1: unexpected status 0x2000900 after switch
920 21:39:23.067135 <4>[ 26.506065] mmc1: unexpected status 0x2000900 after switch
921 21:39:23.097583 <4>[ 26.536268] mmc1: unexpected status 0x2000900 after switch
922 21:39:23.401958 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
923 21:39:23.526436 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
924 21:39:23.598403 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
925 21:39:25.612445 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
926 21:39:25.619863 <5>[ 29.056713] cfg80211: Loading compiled-in X.509 certificates for regulatory database
927 21:39:25.631861 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
928 21:39:26.389007 <3>[ 29.824440] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
929 21:39:26.863485 <5>[ 30.301757] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
930 21:39:26.940736 <5>[ 30.377448] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
931 21:39:26.959608 <4>[ 30.395498] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
932 21:39:26.964617 <6>[ 30.404596] cfg80211: failed to load regulatory.db
933 21:39:27.182591 <3>[ 30.617773] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
934 21:39:27.574179 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
935 21:39:27.709031 <46>[ 31.136043] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
936 21:39:27.831176 <46>[ 31.260597] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
937 21:39:27.952629 <3>[ 31.387675] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
938 21:39:27.976218 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
939 21:39:28.715163 <3>[ 32.150568] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
940 21:39:29.480077 <3>[ 32.915196] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
941 21:39:30.272694 <3>[ 33.706886] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
942 21:39:30.302021 [[0m[0;31m* [0m] Job dev-ttyS0.device/start running (13s / 1min 30s)
943 21:39:30.707879 M
[K[[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (14s / 1min 30s)
944 21:39:31.050425 <3>[ 34.484917] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
945 21:39:31.064833 M
[K[[0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (14s / 1min 30s)
946 21:39:31.457275 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (15s / 1min 30s)
947 21:39:31.815531 <3>[ 35.250050] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
948 21:39:31.874333 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (15s / 1min 30s)
949 21:39:32.296376 M
[K[ [0;31m*[0;1;31m*[0m[0;31m*[0m] Job dev-ttyS0.device/start running (15s / 1min 30s)
950 21:39:32.726110 M
[K[ [0;31m*[0;1;31m*[0m] Job dev-ttyS0.device/start running (16s / 1min 30s)
951 21:39:33.217313 M
[K[ [0;31m*[0m] Job dev-ttyS0.device/start running (16s / 1min 30s)
952 21:39:33.626220 M
[K[ [0;31m*[0;1;31m*[0m] Job dev-ttyS0.device/start running (17s / 1min 30s)
953 21:39:34.020900 M
[K[ [0;31m*[0;1;31m*[0m[0;31m*[0m] Job dev-ttyS0.device/start running (17s / 1min 30s)
954 21:39:34.362319 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (17s / 1min 30s)
955 21:39:34.707974 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (18s / 1min 30s)
956 21:39:35.039377 <3>[ 38.474518] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
957 21:39:35.062135 M
[K[[0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (18s / 1min 30s)
958 21:39:35.327539 M
[K[[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
959 21:39:35.350053 [K[[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
960 21:39:35.372095 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
961 21:39:35.431616 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
962 21:39:35.480210 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
963 21:39:35.543585 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
964 21:39:35.619181 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
965 21:39:35.669715 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
966 21:39:35.695489 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
967 21:39:35.725233 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
968 21:39:35.801166 <3>[ 39.236224] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
969 21:39:35.822393 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
970 21:39:35.870164 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
971 21:39:35.916954 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
972 21:39:35.944656 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
973 21:39:35.971451 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
974 21:39:36.005047 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
975 21:39:36.036381 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
976 21:39:36.061265 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
977 21:39:36.082360 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
978 21:39:36.130462 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
979 21:39:36.148411 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
980 21:39:36.172282 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
981 21:39:36.284062 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
982 21:39:36.342955 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
983 21:39:36.468142 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
984 21:39:36.560312 <3>[ 39.995498] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
985 21:39:36.600459 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
986 21:39:36.638817 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
987 21:39:36.677527 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
988 21:39:36.704825 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
989 21:39:36.909162 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
990 21:39:36.959559 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
991 21:39:37.071768 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
992 21:39:37.319967 <3>[ 40.754609] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
993 21:39:37.436968 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
994 21:39:37.732993 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
995 21:39:38.079191 <3>[ 41.514243] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
996 21:39:38.848160 <3>[ 42.283202] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
997 21:39:39.617284 <3>[ 43.052277] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
998 21:39:40.024100 [[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (23s / 1min 30s)
999 21:39:40.385341 <3>[ 43.821374] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1000 21:39:40.394482 <3>[ 43.830892] Buffer I/O error on dev mmcblk1, logical block 468976, async page read
1001 21:39:40.827900 M
[K[[0m[0;31m* [0m] Job dev-ttyS0.device/start running (24s / 1min 30s)
1002 21:39:41.925253 M
[K[[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (25s / 1min 30s)
1003 21:39:42.369137 M
[K[[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
1004 21:39:43.623242 [K[[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1005 21:39:43.735661 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
1006 21:39:43.888651 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1007 21:39:43.908292 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1008 21:39:43.933394 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1009 21:39:44.031382 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1010 21:39:44.296013
1011 21:39:44.296449 Debian GNU/Linux 12worm-armhf login: root (automatic login)
1012 21:39:44.298270
1013 21:39:44.622950 <3>[ 48.057963] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1014 21:39:44.738422 Linux debian-bookworm-armhf 6.12.0-rc2 #1 SMP Mon Nov 4 21:15:50 UTC 2024 armv7l
1015 21:39:44.738859
1016 21:39:44.744067 The programs included with the Debian GNU/Linux system are free software;
1017 21:39:44.747368 the exact distribution terms for each program are described in the
1018 21:39:44.752928 individual files in /usr/share/doc/*/copyright.
1019 21:39:44.753305
1020 21:39:44.758558 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1021 21:39:44.763234 permitted by applicable law.
1022 21:39:45.382387 <3>[ 48.817369] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1023 21:39:46.141642 <3>[ 49.576468] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1024 21:39:46.900031 <3>[ 50.335540] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1025 21:39:47.659509 <3>[ 51.094629] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1026 21:39:48.418596 <3>[ 51.853743] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1027 21:39:49.177735 <3>[ 52.613199] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1028 21:39:49.797596 Unable to match end of the kernel message
1030 21:39:49.798573 Setting prompt string to ['/ #']
1031 21:39:49.798894 end: 2.4.4.1 login-action (duration 00:00:54) [common]
1033 21:39:49.799658 end: 2.4.4 auto-login-action (duration 00:00:54) [common]
1034 21:39:49.799952 start: 2.4.5 expect-shell-connection (timeout 00:02:46) [common]
1035 21:39:49.800239 Setting prompt string to ['/ #']
1036 21:39:49.800457 Forcing a shell prompt, looking for ['/ #']
1038 21:39:49.851035 / #
1039 21:39:49.851758 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1040 21:39:49.852116 Waiting using forced prompt support (timeout 00:02:30)
1041 21:39:49.856279
1042 21:39:49.865786 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1043 21:39:49.866345 start: 2.4.6 export-device-env (timeout 00:02:46) [common]
1044 21:39:49.866646 Sending with 10 millisecond of delay
1046 21:39:54.867865 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/936947/extract-nfsrootfs-q3xx0mjv'
1047 21:39:54.878993 <3>[ 53.375238] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1048 21:39:54.879588 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/9369<3>[ 56.514018] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1049 21:39:54.880081 47/extract-n<3>[ 57.283105] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1050 21:39:54.880544 fsrootfs-q3xx<3>[ 58.052177] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1051 21:39:54.880991 0mjv'
1052 21:39:54.881773 Sending with 10 millisecond of delay
1054 21:39:56.982851 / # export NFS_SERVER_IP='192.168.6.2'
1055 21:39:56.994316 export <3>[ 58.821323] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1056 21:39:56.994681 NFS_SERVER_IP<3>[ 59.590425] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1057 21:39:56.994903 ='192.168.6.<3>[ 60.359522] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1058 21:39:56.995114 2'
1059 21:39:56.995640 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1060 21:39:56.995957 end: 2.4 uboot-commands (duration 00:02:21) [common]
1061 21:39:56.996320 end: 2 uboot-action (duration 00:02:21) [common]
1062 21:39:56.996631 start: 3 lava-test-retry (timeout 00:06:27) [common]
1063 21:39:56.996942 start: 3.1 lava-test-shell (timeout 00:06:27) [common]
1064 21:39:56.997192 Using namespace: common
1066 21:39:57.097950 / # #
1067 21:39:57.098524 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1068 21:39:57.103567 #
1069 21:39:57.109353 Using /lava-936947
1071 21:39:57.210215 / # export SHELL=/bin/bash
1072 21:39:57.215533 export SHELL=/bin/bash
1074 21:39:57.321440 / # . /lava-936947/environment
1075 21:39:57.326823 . /lava-936947/environment
1077 21:39:57.439122 / # /lava-936947/bin/lava-test-runner /lava-936947/0
1078 21:39:57.439656 Test shell timeout: 10s (minimum of the action and connection timeout)
1079 21:39:57.444260 /lava-936947/bin/lava-test-runner /lava-936947/0
1080 21:39:57.693643 <3>[ 61.129412] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1081 21:39:57.906552 + export TESTRUN_ID=0_timesync-off
1082 21:39:57.914403 + TESTRUN_ID=0_timesync-off
1083 21:39:57.914734 + cd /lava-936947/0/tests/0_timesync-off
1084 21:39:57.914960 ++ cat uuid
1085 21:39:57.930204 + UUID=936947_1.6.2.4.1
1086 21:39:57.930514 + set +x
1087 21:39:57.938871 <LAVA_SIGNAL_STARTRUN 0_timesync-off 936947_1.6.2.4.1>
1088 21:39:57.939149 + systemctl stop systemd-timesyncd
1089 21:39:57.939608 Received signal: <STARTRUN> 0_timesync-off 936947_1.6.2.4.1
1090 21:39:57.939857 Starting test lava.0_timesync-off (936947_1.6.2.4.1)
1091 21:39:57.940189 Skipping test definition patterns.
1092 21:39:58.207383 + set +x
1093 21:39:58.207781 <LAVA_SIGNAL_ENDRUN 0_timesync-off 936947_1.6.2.4.1>
1094 21:39:58.208356 Received signal: <ENDRUN> 0_timesync-off 936947_1.6.2.4.1
1095 21:39:58.208937 Ending use of test pattern.
1096 21:39:58.209386 Ending test lava.0_timesync-off (936947_1.6.2.4.1), duration 0.27
1098 21:39:58.390884 + export TESTRUN_ID=1_kselftest-dt
1099 21:39:58.396863 + TESTRUN_ID=1_kselftest-dt
1100 21:39:58.445520 + cd /lava-936947/0/tests/1_kselftest-dt
1101 21:39:58.446182 ++ cat uuid
1102 21:39:58.451003 <3>[ 61.888457] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1103 21:39:58.460080 <3>[ 61.899231] Buffer I/O error on dev mmcblk1, logical block 468976, async page read
1104 21:39:58.555593 + UUID=936947_1.6.2.4.5
1105 21:39:58.556261 + set +x
1106 21:39:58.561021 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 936947_1.6.2.4.5>
1107 21:39:58.561543 + cd ./automated/linux/kselftest/
1108 21:39:58.562313 Received signal: <STARTRUN> 1_kselftest-dt 936947_1.6.2.4.5
1109 21:39:58.562785 Starting test lava.1_kselftest-dt (936947_1.6.2.4.5)
1110 21:39:58.563327 Skipping test definition patterns.
1111 21:39:58.591039 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-194-g71c9d5bcfa2c/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1112 21:39:58.696572 INFO: install_deps skipped
1113 21:39:59.273870 --2024-11-04 21:39:59-- http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-194-g71c9d5bcfa2c/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1114 21:39:59.297969 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1115 21:39:59.435469 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1116 21:39:59.572340 HTTP request sent, awaiting response... 200 OK
1117 21:39:59.572998 Length: 4096156 (3.9M) [application/octet-stream]
1118 21:39:59.577837 Saving to: 'kselftest_armhf.tar.gz'
1119 21:39:59.578382
1120 21:40:01.432124
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 186KB/s
kselftest_armhf.tar 4%[ ] 194.76K 360KB/s
kselftest_armhf.tar 17%[==> ] 712.70K 886KB/s
kselftest_armhf.tar 20%[===> ] 837.42K 765KB/s
kselftest_armhf.tar 51%[=========> ] 2.02M 1.47MB/s
kselftest_armhf.tar 80%[===============> ] 3.16M 1.96MB/s
kselftest_armhf.tar 97%[==================> ] 3.82M 2.11MB/s
kselftest_armhf.tar 100%[===================>] 3.91M 2.11MB/s in 1.9s
1121 21:40:01.432861
1122 21:40:02.082020 2024-11-04 21:40:01 (2.11 MB/s) - 'kselftest_armhf.tar.gz' saved [4096156/4096156]
1123 21:40:02.082458
1124 21:40:15.313585 skiplist:
1125 21:40:15.314000 ========================================
1126 21:40:15.319218 ========================================
1127 21:40:15.433133 dt:test_unprobed_devices.sh
1128 21:40:15.463549 ============== Tests to run ===============
1129 21:40:15.471856 dt:test_unprobed_devices.sh
1130 21:40:15.475809 ===========End Tests to run ===============
1131 21:40:15.484747 shardfile-dt pass
1132 21:40:15.721180 <12>[ 79.162190] kselftest: Running tests in dt
1133 21:40:15.749213 TAP version 13
1134 21:40:15.775081 1..1
1135 21:40:15.832699 # timeout set to 45
1136 21:40:15.833351 # selftests: dt: test_unprobed_devices.sh
1137 21:40:16.620373 # TAP version 13
1138 21:40:41.666803 # 1..257
1139 21:40:41.869285 # ok 1 / # SKIP
1140 21:40:41.893564 # ok 2 /clk_mcasp0
1141 21:40:41.960086 # ok 3 /clk_mcasp0_fixed # SKIP
1142 21:40:42.029927 # ok 4 /cpus/cpu@0 # SKIP
1143 21:40:42.101426 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1144 21:40:42.125490 # ok 6 /fixedregulator0
1145 21:40:42.140755 # ok 7 /leds
1146 21:40:42.167130 # ok 8 /ocp
1147 21:40:42.185837 # ok 9 /ocp/interconnect@44c00000
1148 21:40:42.209760 # ok 10 /ocp/interconnect@44c00000/segment@0
1149 21:40:42.232817 # ok 11 /ocp/interconnect@44c00000/segment@100000
1150 21:40:42.261028 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1151 21:40:42.328573 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1152 21:40:42.352241 # ok 14 /ocp/interconnect@44c00000/segment@200000
1153 21:40:42.377733 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1154 21:40:42.483834 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1155 21:40:42.555756 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1156 21:40:42.624423 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1157 21:40:42.696207 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1158 21:40:42.768654 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1159 21:40:42.846523 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1160 21:40:42.920521 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1161 21:40:42.991826 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1162 21:40:43.064497 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1163 21:40:43.136446 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1164 21:40:43.203498 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1165 21:40:43.277615 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1166 21:40:43.346540 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1167 21:40:43.424142 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1168 21:40:43.496122 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1169 21:40:43.563564 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1170 21:40:43.635765 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1171 21:40:43.708880 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1172 21:40:43.779633 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1173 21:40:43.853427 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1174 21:40:43.924534 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1175 21:40:43.997453 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1176 21:40:44.069533 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1177 21:40:44.142233 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1178 21:40:44.214273 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1179 21:40:44.287335 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1180 21:40:44.359095 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1181 21:40:44.432780 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1182 21:40:44.515417 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1183 21:40:44.596140 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1184 21:40:44.669409 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1185 21:40:44.746026 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1186 21:40:44.819768 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1187 21:40:44.889238 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1188 21:40:44.961469 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1189 21:40:45.036651 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1190 21:40:45.105660 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1191 21:40:45.177677 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1192 21:40:45.248334 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1193 21:40:45.320759 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1194 21:40:45.392978 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1195 21:40:45.464786 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1196 21:40:45.537517 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1197 21:40:45.609473 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1198 21:40:45.682622 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1199 21:40:45.754701 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1200 21:40:45.826916 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1201 21:40:45.903554 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1202 21:40:45.976995 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1203 21:40:46.043479 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1204 21:40:46.116921 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1205 21:40:46.187921 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1206 21:40:46.261101 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1207 21:40:46.333112 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1208 21:40:46.408178 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1209 21:40:46.480329 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1210 21:40:46.553087 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1211 21:40:46.624248 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1212 21:40:46.703309 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1213 21:40:46.769567 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1214 21:40:46.847066 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1215 21:40:46.915586 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1216 21:40:46.992667 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1217 21:40:47.059201 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1218 21:40:47.131591 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1219 21:40:47.203273 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1220 21:40:47.275091 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1221 21:40:47.350838 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1222 21:40:47.422700 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1223 21:40:47.494379 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1224 21:40:47.575964 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1225 21:40:47.676476 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1226 21:40:47.752540 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1227 21:40:47.826572 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1228 21:40:47.898123 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1229 21:40:47.964682 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1230 21:40:48.040498 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1231 21:40:48.108692 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1232 21:40:48.185935 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1233 21:40:48.204643 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1234 21:40:48.230552 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1235 21:40:48.254672 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1236 21:40:48.278380 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1237 21:40:48.299646 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1238 21:40:48.323119 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1239 21:40:48.346287 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1240 21:40:48.369131 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1241 21:40:48.474609 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1242 21:40:48.498719 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1243 21:40:48.525474 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1244 21:40:48.553765 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1245 21:40:48.653221 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1246 21:40:48.734012 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1247 21:40:48.805708 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1248 21:40:48.873255 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1249 21:40:48.944928 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1250 21:40:49.016665 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1251 21:40:49.094275 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1252 21:40:49.160538 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1253 21:40:49.231497 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1254 21:40:49.304114 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1255 21:40:49.375687 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1256 21:40:49.451761 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1257 21:40:49.525573 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1258 21:40:49.600053 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1259 21:40:49.698857 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1260 21:40:49.778958 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1261 21:40:49.804273 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1262 21:40:49.874960 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1263 21:40:49.948640 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1264 21:40:50.017504 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1265 21:40:50.039686 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1266 21:40:50.111182 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1267 21:40:50.138179 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1268 21:40:50.208800 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1269 21:40:50.232144 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1270 21:40:50.254111 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1271 21:40:50.279628 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1272 21:40:50.304342 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1273 21:40:50.320520 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1274 21:40:50.347301 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1275 21:40:50.375762 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1276 21:40:50.446611 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1277 21:40:50.468226 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1278 21:40:50.491416 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1279 21:40:50.566050 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1280 21:40:50.635344 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1281 21:40:50.657351 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1282 21:40:50.756960 # not ok 144 /ocp/interconnect@47c00000
1283 21:40:50.828311 # not ok 145 /ocp/interconnect@47c00000/segment@0
1284 21:40:50.849292 # ok 146 /ocp/interconnect@48000000
1285 21:40:50.877381 # ok 147 /ocp/interconnect@48000000/segment@0
1286 21:40:50.902210 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1287 21:40:50.922638 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1288 21:40:50.949180 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1289 21:40:50.972750 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1290 21:40:50.991250 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1291 21:40:51.020164 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1292 21:40:51.041598 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1293 21:40:51.113711 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1294 21:40:51.183585 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1295 21:40:51.208941 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1296 21:40:51.233988 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1297 21:40:51.256890 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1298 21:40:51.276724 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1299 21:40:51.299607 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1300 21:40:51.328324 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1301 21:40:51.346466 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1302 21:40:51.370376 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1303 21:40:51.392838 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1304 21:40:51.421205 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1305 21:40:51.443224 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1306 21:40:51.462386 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1307 21:40:51.485884 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1308 21:40:51.509411 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1309 21:40:51.531634 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1310 21:40:51.560521 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1311 21:40:51.582044 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1312 21:40:51.604140 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1313 21:40:51.627475 # ok 175 /ocp/interconnect@48000000/segment@100000
1314 21:40:51.648440 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1315 21:40:51.674116 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1316 21:40:51.745967 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1317 21:40:51.819053 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1318 21:40:51.888377 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1319 21:40:51.962071 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1320 21:40:52.030510 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1321 21:40:52.103726 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1322 21:40:52.172614 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1323 21:40:52.245993 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1324 21:40:52.266367 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1325 21:40:52.293917 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1326 21:40:52.319540 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1327 21:40:52.342894 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1328 21:40:52.363556 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1329 21:40:52.386661 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1330 21:40:52.413547 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1331 21:40:52.433203 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1332 21:40:52.456158 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1333 21:40:52.482657 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1334 21:40:52.503477 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1335 21:40:52.531189 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1336 21:40:52.551484 # ok 198 /ocp/interconnect@48000000/segment@200000
1337 21:40:52.570670 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1338 21:40:52.644446 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1339 21:40:52.668891 # ok 201 /ocp/interconnect@48000000/segment@300000
1340 21:40:52.693106 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1341 21:40:52.713126 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1342 21:40:52.741920 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1343 21:40:52.763490 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1344 21:40:52.784273 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1345 21:40:52.806531 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1346 21:40:52.880625 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1347 21:40:52.899145 # ok 209 /ocp/interconnect@4a000000
1348 21:40:52.927287 # ok 210 /ocp/interconnect@4a000000/segment@0
1349 21:40:52.952382 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1350 21:40:52.974117 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1351 21:40:52.997164 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1352 21:40:53.023227 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1353 21:40:53.090077 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1354 21:40:53.203136 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1355 21:40:53.272681 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1356 21:40:53.374755 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1357 21:40:53.444076 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1358 21:40:53.515155 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1359 21:40:53.609968 # not ok 221 /ocp/interconnect@4b140000
1360 21:40:53.683190 # not ok 222 /ocp/interconnect@4b140000/segment@0
1361 21:40:53.758056 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1362 21:40:53.779057 # ok 224 /ocp/target-module@40300000
1363 21:40:53.797912 # ok 225 /ocp/target-module@40300000/sram@0
1364 21:40:53.872695 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1365 21:40:53.945450 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1366 21:40:53.962430 # ok 228 /ocp/target-module@47400000
1367 21:40:53.991940 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1368 21:40:54.011756 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1369 21:40:54.032233 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1370 21:40:54.058929 # ok 232 /ocp/target-module@47400000/usb@1400
1371 21:40:54.081341 # ok 233 /ocp/target-module@47400000/usb@1800
1372 21:40:54.099875 # ok 234 /ocp/target-module@47810000
1373 21:40:54.121175 # ok 235 /ocp/target-module@49000000
1374 21:40:54.144262 # ok 236 /ocp/target-module@49000000/dma@0
1375 21:40:54.165922 # ok 237 /ocp/target-module@49800000
1376 21:40:54.191184 # ok 238 /ocp/target-module@49800000/dma@0
1377 21:40:54.215494 # ok 239 /ocp/target-module@49900000
1378 21:40:54.233892 # ok 240 /ocp/target-module@49900000/dma@0
1379 21:40:54.255272 # ok 241 /ocp/target-module@49a00000
1380 21:40:54.277696 # ok 242 /ocp/target-module@49a00000/dma@0
1381 21:40:54.300739 # ok 243 /ocp/target-module@4c000000
1382 21:40:54.372249 # not ok 244 /ocp/target-module@4c000000/emif@0
1383 21:40:54.397714 # ok 245 /ocp/target-module@50000000
1384 21:40:54.422627 # ok 246 /ocp/target-module@53100000
1385 21:40:54.487187 # not ok 247 /ocp/target-module@53100000/sham@0
1386 21:40:54.510724 # ok 248 /ocp/target-module@53500000
1387 21:40:54.579049 # not ok 249 /ocp/target-module@53500000/aes@0
1388 21:40:54.605173 # ok 250 /ocp/target-module@56000000
1389 21:40:54.706893 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1390 21:40:54.779700 # ok 252 /opp-table # SKIP
1391 21:40:54.844789 # ok 253 /soc # SKIP
1392 21:40:54.868693 # ok 254 /sound
1393 21:40:54.889253 # ok 255 /target-module@4b000000
1394 21:40:54.914583 # ok 256 /target-module@4b000000/target-module@140000
1395 21:40:54.935092 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1396 21:40:54.942637 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1397 21:40:54.952682 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1398 21:40:57.222629 dt_test_unprobed_devices_sh_ skip
1399 21:40:57.228085 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1400 21:40:57.233624 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1401 21:40:57.234065 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1402 21:40:57.242561 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1403 21:40:57.243023 dt_test_unprobed_devices_sh_fixedregulator0 pass
1404 21:40:57.248095 dt_test_unprobed_devices_sh_leds pass
1405 21:40:57.253810 dt_test_unprobed_devices_sh_ocp pass
1406 21:40:57.259355 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1407 21:40:57.264846 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1408 21:40:57.270518 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1409 21:40:57.275967 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1410 21:40:57.287206 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1411 21:40:57.292811 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1412 21:40:57.298389 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1413 21:40:57.309804 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1414 21:40:57.315401 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1415 21:40:57.326505 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1416 21:40:57.337702 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1417 21:40:57.348912 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1418 21:40:57.360251 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1419 21:40:57.365779 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1420 21:40:57.377001 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1421 21:40:57.388241 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1422 21:40:57.399450 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1423 21:40:57.410637 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1424 21:40:57.416169 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1425 21:40:57.427441 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1426 21:40:57.438599 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1427 21:40:57.449782 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1428 21:40:57.460974 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1429 21:40:57.466604 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1430 21:40:57.477727 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1431 21:40:57.488951 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1432 21:40:57.500150 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1433 21:40:57.505784 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1434 21:40:57.516947 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1435 21:40:57.528147 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1436 21:40:57.539321 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1437 21:40:57.550584 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1438 21:40:57.561703 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1439 21:40:57.572839 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1440 21:40:57.584132 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1441 21:40:57.595256 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1442 21:40:57.606466 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1443 21:40:57.617644 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1444 21:40:57.628824 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1445 21:40:57.640072 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1446 21:40:57.651230 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1447 21:40:57.662408 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1448 21:40:57.673658 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1449 21:40:57.684860 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1450 21:40:57.696038 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1451 21:40:57.707230 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1452 21:40:57.718403 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1453 21:40:57.729596 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1454 21:40:57.740788 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1455 21:40:57.752057 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1456 21:40:57.757658 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1457 21:40:57.768842 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1458 21:40:57.780090 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1459 21:40:57.791296 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1460 21:40:57.802524 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1461 21:40:57.813755 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1462 21:40:57.825009 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1463 21:40:57.836227 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1464 21:40:57.847425 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1465 21:40:57.858628 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1466 21:40:57.864272 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1467 21:40:57.875447 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1468 21:40:57.886686 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1469 21:40:57.897882 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1470 21:40:57.909090 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1471 21:40:57.920375 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1472 21:40:57.931435 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1473 21:40:57.942575 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1474 21:40:57.953851 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1475 21:40:57.964999 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1476 21:40:57.976239 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1477 21:40:57.987372 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1478 21:40:57.998585 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1479 21:40:58.009765 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1480 21:40:58.021005 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1481 21:40:58.032117 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1482 21:40:58.037872 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1483 21:40:58.048930 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1484 21:40:58.060167 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1485 21:40:58.071388 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1486 21:40:58.082617 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1487 21:40:58.093864 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1488 21:40:58.105059 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1489 21:40:58.116248 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1490 21:40:58.127470 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1491 21:40:58.138648 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1492 21:40:58.149843 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1493 21:40:58.161066 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1494 21:40:58.166636 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1495 21:40:58.177882 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1496 21:40:58.189053 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1497 21:40:58.194648 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1498 21:40:58.205821 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1499 21:40:58.211442 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1500 21:40:58.222640 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1501 21:40:58.233881 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1502 21:40:58.239449 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1503 21:40:58.250605 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1504 21:40:58.261761 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1505 21:40:58.272948 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1506 21:40:58.284163 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1507 21:40:58.295340 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1508 21:40:58.306602 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1509 21:40:58.323355 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1510 21:40:58.334582 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1511 21:40:58.345723 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1512 21:40:58.356950 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1513 21:40:58.368265 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1514 21:40:58.379355 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1515 21:40:58.390608 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1516 21:40:58.401753 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1517 21:40:58.418559 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1518 21:40:58.429740 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1519 21:40:58.446539 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1520 21:40:58.457715 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1521 21:40:58.463346 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1522 21:40:58.474480 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1523 21:40:58.480124 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1524 21:40:58.491261 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1525 21:40:58.502528 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1526 21:40:58.508143 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1527 21:40:58.519284 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1528 21:40:58.524899 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1529 21:40:58.536105 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1530 21:40:58.541714 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1531 21:40:58.552799 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1532 21:40:58.558484 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1533 21:40:58.569654 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1534 21:40:58.580781 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1535 21:40:58.592018 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1536 21:40:58.597791 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1537 21:40:58.608802 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1538 21:40:58.620037 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1539 21:40:58.631209 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1540 21:40:58.636836 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1541 21:40:58.642417 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1542 21:40:58.648034 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1543 21:40:58.653586 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1544 21:40:58.659192 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1545 21:40:58.670352 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1546 21:40:58.676014 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1547 21:40:58.681542 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1548 21:40:58.692765 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1549 21:40:58.698391 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1550 21:40:58.709531 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1551 21:40:58.715142 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1552 21:40:58.726340 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1553 21:40:58.731932 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1554 21:40:58.743130 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1555 21:40:58.748732 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1556 21:40:58.759880 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1557 21:40:58.765512 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1558 21:40:58.771074 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1559 21:40:58.782314 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1560 21:40:58.787946 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1561 21:40:58.799175 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1562 21:40:58.804817 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1563 21:40:58.815888 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1564 21:40:58.821497 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1565 21:40:58.832745 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1566 21:40:58.838305 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1567 21:40:58.849448 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1568 21:40:58.855048 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1569 21:40:58.866254 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1570 21:40:58.871836 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1571 21:40:58.882971 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1572 21:40:58.888637 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1573 21:40:58.894224 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1574 21:40:58.905394 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1575 21:40:58.916596 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1576 21:40:58.927770 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1577 21:40:58.939021 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1578 21:40:58.950130 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1579 21:40:58.955800 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1580 21:40:58.966934 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1581 21:40:58.978124 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1582 21:40:58.989285 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1583 21:40:59.000572 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1584 21:40:59.006195 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1585 21:40:59.017321 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1586 21:40:59.022938 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1587 21:40:59.034113 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1588 21:40:59.039804 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1589 21:40:59.050885 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1590 21:40:59.056535 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1591 21:40:59.067746 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1592 21:40:59.073286 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1593 21:40:59.084511 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1594 21:40:59.090064 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1595 21:40:59.101302 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1596 21:40:59.106886 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1597 21:40:59.118039 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1598 21:40:59.123652 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1599 21:40:59.129275 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1600 21:40:59.140482 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1601 21:40:59.146059 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1602 21:40:59.157219 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1603 21:40:59.162831 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1604 21:40:59.174016 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1605 21:40:59.179607 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1606 21:40:59.185202 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1607 21:40:59.190802 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1608 21:40:59.201971 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1609 21:40:59.207627 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1610 21:40:59.218771 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1611 21:40:59.224421 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1612 21:40:59.235594 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1613 21:40:59.246787 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1614 21:40:59.258026 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1615 21:40:59.263610 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1616 21:40:59.274925 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1617 21:40:59.286008 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1618 21:40:59.291559 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1619 21:40:59.297246 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1620 21:40:59.302883 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1621 21:40:59.308473 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1622 21:40:59.314058 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1623 21:40:59.319688 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1624 21:40:59.325295 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1625 21:40:59.330872 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1626 21:40:59.342055 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1627 21:40:59.347711 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1628 21:40:59.353276 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1629 21:40:59.358859 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1630 21:40:59.364468 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1631 21:40:59.370105 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1632 21:40:59.375713 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1633 21:40:59.381320 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1634 21:40:59.386975 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1635 21:40:59.392444 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1636 21:40:59.398081 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1637 21:40:59.403668 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1638 21:40:59.409282 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1639 21:40:59.414848 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1640 21:40:59.420445 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1641 21:40:59.426106 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1642 21:40:59.431725 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1643 21:40:59.437362 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1644 21:40:59.442912 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1645 21:40:59.448526 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1646 21:40:59.454077 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1647 21:40:59.459743 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1648 21:40:59.465301 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1649 21:40:59.470917 dt_test_unprobed_devices_sh_opp-table skip
1650 21:40:59.471515 dt_test_unprobed_devices_sh_soc skip
1651 21:40:59.476530 dt_test_unprobed_devices_sh_sound pass
1652 21:40:59.482089 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1653 21:40:59.487711 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1654 21:40:59.493332 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1655 21:40:59.499011 dt_test_unprobed_devices_sh fail
1656 21:40:59.504538 + ../../utils/send-to-lava.sh ./output/result.txt
1657 21:40:59.508255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1658 21:40:59.509322 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1660 21:40:59.527887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1661 21:40:59.528723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1663 21:40:59.619437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1664 21:40:59.620338 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1666 21:40:59.706029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1667 21:40:59.706880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1669 21:40:59.797202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1670 21:40:59.798136 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1672 21:40:59.889870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1673 21:40:59.890776 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1675 21:40:59.974673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1676 21:40:59.975513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1678 21:41:00.064729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1679 21:41:00.065573 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1681 21:41:00.150025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1682 21:41:00.150963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1684 21:41:00.245193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1685 21:41:00.246107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1687 21:41:00.339799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1688 21:41:00.340683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1690 21:41:00.431607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1691 21:41:00.432587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1693 21:41:00.520034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1694 21:41:00.520950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1696 21:41:00.613506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1697 21:41:00.614355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1699 21:41:00.703753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1700 21:41:00.704750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1702 21:41:00.791497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1703 21:41:00.792527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1705 21:41:00.879720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1706 21:41:00.880703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1708 21:41:00.972298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1709 21:41:00.973266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1711 21:41:01.063923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1712 21:41:01.064909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1714 21:41:01.154931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1715 21:41:01.155840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1717 21:41:01.244349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1718 21:41:01.245416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1720 21:41:01.335081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1721 21:41:01.336142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1723 21:41:01.428393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1724 21:41:01.429246 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1726 21:41:01.521487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1727 21:41:01.522449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1729 21:41:01.613621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1730 21:41:01.614581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1732 21:41:01.704322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1733 21:41:01.705340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1735 21:41:01.790896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1736 21:41:01.791937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1738 21:41:01.883136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1739 21:41:01.884087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1741 21:41:01.974980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1742 21:41:01.975669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1744 21:41:02.066635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1745 21:41:02.067614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1747 21:41:02.154088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1748 21:41:02.154934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1750 21:41:02.242947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1751 21:41:02.243861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1753 21:41:02.334938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1754 21:41:02.335738 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1756 21:41:02.427270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1757 21:41:02.428140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1759 21:41:02.513111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1760 21:41:02.513956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1762 21:41:02.599031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1763 21:41:02.599956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1765 21:41:02.685631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1766 21:41:02.686499 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1768 21:41:02.778364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1769 21:41:02.779183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1771 21:41:02.865688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1772 21:41:02.866551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1774 21:41:02.951163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1775 21:41:02.952062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1777 21:41:03.044572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1778 21:41:03.045491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1780 21:41:03.134318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1781 21:41:03.135233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1783 21:41:03.225963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1784 21:41:03.226860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1786 21:41:03.317565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1787 21:41:03.318487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1789 21:41:03.405022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1790 21:41:03.405926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1792 21:41:03.491439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1793 21:41:03.492370 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1795 21:41:03.586313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1796 21:41:03.587179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1798 21:41:03.677453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1799 21:41:03.678347 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1801 21:41:03.774007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1802 21:41:03.774882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1804 21:41:03.865140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1805 21:41:03.866038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1807 21:41:03.956632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1808 21:41:03.957454 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1810 21:41:04.044717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1811 21:41:04.045546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1813 21:41:04.134951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1814 21:41:04.135789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1816 21:41:04.226432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1817 21:41:04.227324 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1819 21:41:04.314649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1820 21:41:04.315518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1822 21:41:04.405140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1823 21:41:04.406015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1825 21:41:04.498826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1826 21:41:04.499678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1828 21:41:04.590531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1829 21:41:04.591392 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1831 21:41:04.682613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1832 21:41:04.683481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1834 21:41:04.775037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1835 21:41:04.775910 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1837 21:41:04.861927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1838 21:41:04.862780 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1840 21:41:04.954209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1841 21:41:04.955063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1843 21:41:05.045157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1844 21:41:05.046015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1846 21:41:05.137407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1847 21:41:05.138272 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1849 21:41:05.224358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1850 21:41:05.225229 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1852 21:41:05.310362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1853 21:41:05.311223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1855 21:41:05.403892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1856 21:41:05.404780 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1858 21:41:05.495932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1859 21:41:05.496811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1861 21:41:05.584983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1862 21:41:05.585840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1864 21:41:05.671669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1865 21:41:05.672578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1867 21:41:05.764730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1868 21:41:05.765600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1870 21:41:05.855871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1871 21:41:05.856786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1873 21:41:05.943172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1874 21:41:05.944059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1876 21:41:06.034646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1877 21:41:06.035520 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1879 21:41:06.127382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1880 21:41:06.128331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1882 21:41:06.214025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1883 21:41:06.214904 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1885 21:41:06.305634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1886 21:41:06.306513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1888 21:41:06.398114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1889 21:41:06.398992 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1891 21:41:06.485593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1892 21:41:06.486488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1894 21:41:06.573015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1895 21:41:06.573936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1897 21:41:06.664301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1898 21:41:06.665178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1900 21:41:06.754330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1901 21:41:06.755193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1903 21:41:06.842308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1904 21:41:06.843182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1906 21:41:06.933124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1907 21:41:06.933999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1909 21:41:07.024975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1910 21:41:07.025863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1912 21:41:07.116266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1913 21:41:07.117124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1915 21:41:07.203329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1916 21:41:07.204171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1918 21:41:07.288606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1919 21:41:07.289441 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1921 21:41:07.376685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1922 21:41:07.377610 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1924 21:41:07.470812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1925 21:41:07.471681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1927 21:41:07.558235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1928 21:41:07.559077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1930 21:41:07.641940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1931 21:41:07.642935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1933 21:41:07.736371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1934 21:41:07.737299 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1936 21:41:07.824647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1937 21:41:07.825478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1939 21:41:07.915594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1940 21:41:07.916502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1942 21:41:08.003936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1943 21:41:08.004816 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1945 21:41:08.092504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1946 21:41:08.093375 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1948 21:41:08.181992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1949 21:41:08.182819 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1951 21:41:08.274953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1952 21:41:08.275769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1954 21:41:08.362773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1955 21:41:08.363601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1957 21:41:08.452860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1958 21:41:08.453712 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1960 21:41:08.543518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1961 21:41:08.544377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1963 21:41:08.631799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1964 21:41:08.632652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1966 21:41:08.721558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1967 21:41:08.722377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1969 21:41:08.815050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1970 21:41:08.815867 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1972 21:41:08.903630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1973 21:41:08.904487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1975 21:41:08.993765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1976 21:41:08.994605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1978 21:41:09.084972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1979 21:41:09.085818 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1981 21:41:09.174837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1982 21:41:09.175651 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1984 21:41:09.265564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1985 21:41:09.266388 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1987 21:41:09.358455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1988 21:41:09.359433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1990 21:41:09.445237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1991 21:41:09.446105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1993 21:41:09.531216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1994 21:41:09.532090 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1996 21:41:09.617517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1997 21:41:09.618518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1999 21:41:09.708448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
2000 21:41:09.709282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
2002 21:41:09.795856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
2003 21:41:09.796738 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
2005 21:41:09.882627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
2006 21:41:09.883456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
2008 21:41:09.974694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
2009 21:41:09.975515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
2011 21:41:10.060352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
2012 21:41:10.061169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
2014 21:41:10.150320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
2015 21:41:10.151188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
2017 21:41:10.235617 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
2019 21:41:10.238765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
2020 21:41:10.321575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
2022 21:41:10.324787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
2023 21:41:10.413074 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
2025 21:41:10.416250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
2026 21:41:10.504629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
2027 21:41:10.505502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
2029 21:41:10.594997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
2030 21:41:10.595839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
2032 21:41:10.681792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
2033 21:41:10.682649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
2035 21:41:10.770812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
2036 21:41:10.771665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
2038 21:41:10.861642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
2039 21:41:10.862494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
2041 21:41:10.947042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
2042 21:41:10.947890 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
2044 21:41:11.039597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
2045 21:41:11.040500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
2047 21:41:11.130680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
2048 21:41:11.131514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
2050 21:41:11.221797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2051 21:41:11.222645 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2053 21:41:11.306992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2054 21:41:11.307836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2056 21:41:11.392583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2057 21:41:11.393433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2059 21:41:11.486063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2060 21:41:11.486909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2062 21:41:11.572681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2063 21:41:11.573544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2065 21:41:11.659835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2066 21:41:11.660787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2068 21:41:11.753455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2069 21:41:11.754341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2071 21:41:11.845463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2072 21:41:11.846375 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2074 21:41:11.935622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2075 21:41:11.936553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2077 21:41:12.021326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2078 21:41:12.022162 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2080 21:41:12.113396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2081 21:41:12.114226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2083 21:41:12.204998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2084 21:41:12.205825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2086 21:41:12.291473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2087 21:41:12.292386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2089 21:41:12.377905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2090 21:41:12.378759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2092 21:41:12.470441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2093 21:41:12.471258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2095 21:41:12.555232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2096 21:41:12.556079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2098 21:41:12.647633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2099 21:41:12.648509 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2101 21:41:12.741785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2102 21:41:12.742609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2104 21:41:12.828069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2105 21:41:12.828967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2107 21:41:12.920286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2108 21:41:12.921116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2110 21:41:13.011465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2111 21:41:13.012348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2113 21:41:13.097695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2114 21:41:13.098557 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2116 21:41:13.190635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2117 21:41:13.191471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2119 21:41:13.282743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2120 21:41:13.283601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2122 21:41:13.375309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2123 21:41:13.376141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2125 21:41:13.462815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2126 21:41:13.463628 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2128 21:41:13.553104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2129 21:41:13.553906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2131 21:41:13.640889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2132 21:41:13.641709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2134 21:41:13.731155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2135 21:41:13.732027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2137 21:41:13.823860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2138 21:41:13.824704 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2140 21:41:13.910944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2141 21:41:13.911767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2143 21:41:14.003500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2144 21:41:14.004376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2146 21:41:14.094096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2147 21:41:14.094983 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2149 21:41:14.186248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2150 21:41:14.187130 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2152 21:41:14.273111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2153 21:41:14.273931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2155 21:41:14.364741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2156 21:41:14.365605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2158 21:41:14.451275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2159 21:41:14.452111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2161 21:41:14.537608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2162 21:41:14.538494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2164 21:41:14.623410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2165 21:41:14.624284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2167 21:41:14.715016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2168 21:41:14.715841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2170 21:41:14.800943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2171 21:41:14.801788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2173 21:41:14.886797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2174 21:41:14.887665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2176 21:41:14.977417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2177 21:41:14.978289 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2179 21:41:15.064501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2180 21:41:15.065396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2182 21:41:15.153757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2183 21:41:15.154597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2185 21:41:15.241022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2186 21:41:15.241897 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2188 21:41:15.327240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2189 21:41:15.328146 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2191 21:41:15.416102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2192 21:41:15.416989 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2194 21:41:15.510396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2195 21:41:15.511250 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2197 21:41:15.602760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2198 21:41:15.603613 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2200 21:41:15.695782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2201 21:41:15.696659 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2203 21:41:15.781675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2204 21:41:15.782492 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2206 21:41:15.876278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2207 21:41:15.877154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2209 21:41:15.967252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2210 21:41:15.968093 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2212 21:41:16.054227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2213 21:41:16.055066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2215 21:41:16.137606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2216 21:41:16.138461 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2218 21:41:16.229894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2219 21:41:16.230745 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2221 21:41:16.320944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2222 21:41:16.321860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2224 21:41:16.411436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2225 21:41:16.412388 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2227 21:41:16.497214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2228 21:41:16.498198 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2230 21:41:16.583528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2231 21:41:16.584502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2233 21:41:16.673886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2234 21:41:16.674770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2236 21:41:16.761709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2237 21:41:16.762609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2239 21:41:16.851480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2240 21:41:16.852439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2242 21:41:16.937041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2243 21:41:16.938055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2245 21:41:17.029019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2246 21:41:17.029870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2248 21:41:17.122751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2249 21:41:17.123654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2251 21:41:17.211594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2252 21:41:17.212568 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2254 21:41:17.301041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2255 21:41:17.302017 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2257 21:41:17.391044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2258 21:41:17.392033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2260 21:41:17.479585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2261 21:41:17.480597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2263 21:41:17.566969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2264 21:41:17.567884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2266 21:41:17.659382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2267 21:41:17.660304 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2269 21:41:17.751578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2270 21:41:17.752596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2272 21:41:17.842611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2273 21:41:17.843489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2275 21:41:17.939604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2276 21:41:17.941923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2278 21:41:18.041999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2279 21:41:18.043002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2281 21:41:18.135700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2282 21:41:18.136702 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2284 21:41:18.223405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2285 21:41:18.224413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2287 21:41:18.314242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2288 21:41:18.315137 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2290 21:41:18.400238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2291 21:41:18.401103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2293 21:41:18.485374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2294 21:41:18.485992 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2296 21:41:18.571087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2297 21:41:18.572020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2299 21:41:18.661351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2300 21:41:18.662224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2302 21:41:18.748204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2303 21:41:18.749028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2305 21:41:18.840137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2306 21:41:18.840925 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2308 21:41:18.933905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2309 21:41:18.934735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2311 21:41:19.018544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2312 21:41:19.019171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2314 21:41:19.104075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2315 21:41:19.104996 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2317 21:41:19.190250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2318 21:41:19.191176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2320 21:41:19.276805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2321 21:41:19.277698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2323 21:41:19.370390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2324 21:41:19.371292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2326 21:41:19.461267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2327 21:41:19.462086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2329 21:41:19.546241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2330 21:41:19.547022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2332 21:41:19.641403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2333 21:41:19.642206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2335 21:41:19.736937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2336 21:41:19.737708 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2338 21:41:19.827538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2340 21:41:19.830508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2341 21:41:19.919666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2342 21:41:19.920620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2344 21:41:20.010078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2345 21:41:20.010870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2347 21:41:20.099358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2348 21:41:20.099931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2350 21:41:20.190559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2351 21:41:20.191450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2353 21:41:20.274925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2354 21:41:20.275718 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2356 21:41:20.365441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2357 21:41:20.366191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2359 21:41:20.450317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2360 21:41:20.451113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2362 21:41:20.535786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2363 21:41:20.536578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2365 21:41:20.627956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2366 21:41:20.628788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2368 21:41:20.718707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2369 21:41:20.719485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2371 21:41:20.805639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2372 21:41:20.806536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2374 21:41:20.898495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2375 21:41:20.899318 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2377 21:41:20.988881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2378 21:41:20.989677 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2380 21:41:21.073703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2381 21:41:21.074379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2383 21:41:21.159893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2384 21:41:21.160686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2386 21:41:21.251396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2387 21:41:21.252147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2389 21:41:21.335913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2390 21:41:21.336638 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2392 21:41:21.426426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2393 21:41:21.427344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2395 21:41:21.516890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2396 21:41:21.517633 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2398 21:41:21.608822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2399 21:41:21.609606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2401 21:41:21.693568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2402 21:41:21.694321 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2404 21:41:21.778640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2405 21:41:21.779587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2407 21:41:21.863637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2408 21:41:21.864597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2410 21:41:21.949281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2411 21:41:21.950195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2413 21:41:22.036272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2414 21:41:22.037170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2416 21:41:22.120828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2417 21:41:22.121756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2419 21:41:22.213111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2420 21:41:22.214010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2422 21:41:22.305505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2423 21:41:22.306413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2425 21:41:22.392556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2426 21:41:22.393461 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2428 21:41:22.484948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2429 21:41:22.485857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2431 21:41:22.567029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2432 21:41:22.567670 + set +x
2433 21:41:22.568455 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2435 21:41:22.575326 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 936947_1.6.2.4.5>
2436 21:41:22.575873 <LAVA_TEST_RUNNER EXIT>
2437 21:41:22.576618 Received signal: <ENDRUN> 1_kselftest-dt 936947_1.6.2.4.5
2438 21:41:22.577111 Ending use of test pattern.
2439 21:41:22.577549 Ending test lava.1_kselftest-dt (936947_1.6.2.4.5), duration 84.01
2441 21:41:22.579224 ok: lava_test_shell seems to have completed
2442 21:41:22.593358 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2443 21:41:22.595454 end: 3.1 lava-test-shell (duration 00:01:26) [common]
2444 21:41:22.596073 end: 3 lava-test-retry (duration 00:01:26) [common]
2445 21:41:22.596685 start: 4 finalize (timeout 00:05:01) [common]
2446 21:41:22.597284 start: 4.1 power-off (timeout 00:00:30) [common]
2447 21:41:22.598359 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-04'
2448 21:41:22.634246 >> OK - accepted request
2449 21:41:22.636310 Returned 0 in 0 seconds
2450 21:41:22.737231 end: 4.1 power-off (duration 00:00:00) [common]
2452 21:41:22.739022 start: 4.2 read-feedback (timeout 00:05:01) [common]
2453 21:41:22.740277 Listened to connection for namespace 'common' for up to 1s
2454 21:41:22.741204 Listened to connection for namespace 'common' for up to 1s
2455 21:41:23.411758 Listened to connection for namespace 'common' for up to 1s
2456 21:41:23.740195 Finalising connection for namespace 'common'
2457 21:41:23.740734 Disconnecting from shell: Finalise
2458 21:41:23.741032 / # <3>[ 14
2459 21:41:23.841743 end: 4.2 read-feedback (duration 00:00:01) [common]
2460 21:41:23.842302 end: 4 finalize (duration 00:00:01) [common]
2461 21:41:23.842735 Cleaning after the job
2462 21:41:23.843179 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936947/tftp-deploy-kz_c3zm3/ramdisk
2463 21:41:23.844803 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936947/tftp-deploy-kz_c3zm3/kernel
2464 21:41:23.846199 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936947/tftp-deploy-kz_c3zm3/dtb
2465 21:41:23.847015 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936947/tftp-deploy-kz_c3zm3/nfsrootfs
2466 21:41:23.880899 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936947/tftp-deploy-kz_c3zm3/modules
2467 21:41:23.885234 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/936947
2468 21:41:26.719457 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/936947
2469 21:41:26.720002 Job finished correctly