Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 21:54:20.759756 lava-dispatcher, installed at version: 2024.01
2 21:54:20.760722 start: 0 validate
3 21:54:20.761259 Start time: 2024-11-04 21:54:20.761225+00:00 (UTC)
4 21:54:20.761895 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:54:20.762488 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 21:54:20.800685 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:54:20.801316 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-194-g71c9d5bcfa2c%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 21:54:20.837637 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:54:20.838282 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-194-g71c9d5bcfa2c%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 21:54:21.893505 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:54:21.894018 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-194-g71c9d5bcfa2c%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 21:54:21.942143 validate duration: 1.18
14 21:54:21.943674 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 21:54:21.944348 start: 1.1 download-retry (timeout 00:10:00) [common]
16 21:54:21.944927 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 21:54:21.945870 Not decompressing ramdisk as can be used compressed.
18 21:54:21.946619 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 21:54:21.947070 saving as /var/lib/lava/dispatcher/tmp/937037/tftp-deploy-w6kt60fr/ramdisk/rootfs.cpio.gz
20 21:54:21.947546 total size: 8181887 (7 MB)
21 21:54:21.992254 progress 0 % (0 MB)
22 21:54:22.004673 progress 5 % (0 MB)
23 21:54:22.016668 progress 10 % (0 MB)
24 21:54:22.027139 progress 15 % (1 MB)
25 21:54:22.032745 progress 20 % (1 MB)
26 21:54:22.038666 progress 25 % (1 MB)
27 21:54:22.044187 progress 30 % (2 MB)
28 21:54:22.050070 progress 35 % (2 MB)
29 21:54:22.057599 progress 40 % (3 MB)
30 21:54:22.063392 progress 45 % (3 MB)
31 21:54:22.068778 progress 50 % (3 MB)
32 21:54:22.074495 progress 55 % (4 MB)
33 21:54:22.079878 progress 60 % (4 MB)
34 21:54:22.085699 progress 65 % (5 MB)
35 21:54:22.091216 progress 70 % (5 MB)
36 21:54:22.097001 progress 75 % (5 MB)
37 21:54:22.102341 progress 80 % (6 MB)
38 21:54:22.108065 progress 85 % (6 MB)
39 21:54:22.113524 progress 90 % (7 MB)
40 21:54:22.119277 progress 95 % (7 MB)
41 21:54:22.124264 progress 100 % (7 MB)
42 21:54:22.124953 7 MB downloaded in 0.18 s (43.99 MB/s)
43 21:54:22.125515 end: 1.1.1 http-download (duration 00:00:00) [common]
45 21:54:22.126412 end: 1.1 download-retry (duration 00:00:00) [common]
46 21:54:22.126707 start: 1.2 download-retry (timeout 00:10:00) [common]
47 21:54:22.126978 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 21:54:22.127465 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-194-g71c9d5bcfa2c/arm64/defconfig/gcc-12/kernel/Image
49 21:54:22.127743 saving as /var/lib/lava/dispatcher/tmp/937037/tftp-deploy-w6kt60fr/kernel/Image
50 21:54:22.127957 total size: 45713920 (43 MB)
51 21:54:22.128202 No compression specified
52 21:54:22.168880 progress 0 % (0 MB)
53 21:54:22.197716 progress 5 % (2 MB)
54 21:54:22.226441 progress 10 % (4 MB)
55 21:54:22.255367 progress 15 % (6 MB)
56 21:54:22.284024 progress 20 % (8 MB)
57 21:54:22.312630 progress 25 % (10 MB)
58 21:54:22.340960 progress 30 % (13 MB)
59 21:54:22.369722 progress 35 % (15 MB)
60 21:54:22.398336 progress 40 % (17 MB)
61 21:54:22.426744 progress 45 % (19 MB)
62 21:54:22.456089 progress 50 % (21 MB)
63 21:54:22.484899 progress 55 % (24 MB)
64 21:54:22.514190 progress 60 % (26 MB)
65 21:54:22.542379 progress 65 % (28 MB)
66 21:54:22.570756 progress 70 % (30 MB)
67 21:54:22.599596 progress 75 % (32 MB)
68 21:54:22.628214 progress 80 % (34 MB)
69 21:54:22.656661 progress 85 % (37 MB)
70 21:54:22.685394 progress 90 % (39 MB)
71 21:54:22.714240 progress 95 % (41 MB)
72 21:54:22.743581 progress 100 % (43 MB)
73 21:54:22.744172 43 MB downloaded in 0.62 s (70.75 MB/s)
74 21:54:22.744719 end: 1.2.1 http-download (duration 00:00:01) [common]
76 21:54:22.745620 end: 1.2 download-retry (duration 00:00:01) [common]
77 21:54:22.745937 start: 1.3 download-retry (timeout 00:09:59) [common]
78 21:54:22.746243 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 21:54:22.746749 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-194-g71c9d5bcfa2c/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 21:54:22.747061 saving as /var/lib/lava/dispatcher/tmp/937037/tftp-deploy-w6kt60fr/dtb/meson-g12b-a311d-libretech-cc.dtb
81 21:54:22.747278 total size: 54703 (0 MB)
82 21:54:22.747487 No compression specified
83 21:54:22.796483 progress 59 % (0 MB)
84 21:54:22.797393 progress 100 % (0 MB)
85 21:54:22.797973 0 MB downloaded in 0.05 s (1.03 MB/s)
86 21:54:22.798469 end: 1.3.1 http-download (duration 00:00:00) [common]
88 21:54:22.799313 end: 1.3 download-retry (duration 00:00:00) [common]
89 21:54:22.799580 start: 1.4 download-retry (timeout 00:09:59) [common]
90 21:54:22.799852 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 21:54:22.800357 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-194-g71c9d5bcfa2c/arm64/defconfig/gcc-12/modules.tar.xz
92 21:54:22.800651 saving as /var/lib/lava/dispatcher/tmp/937037/tftp-deploy-w6kt60fr/modules/modules.tar
93 21:54:22.800862 total size: 11607844 (11 MB)
94 21:54:22.801079 Using unxz to decompress xz
95 21:54:22.840708 progress 0 % (0 MB)
96 21:54:22.924343 progress 5 % (0 MB)
97 21:54:23.006471 progress 10 % (1 MB)
98 21:54:23.109992 progress 15 % (1 MB)
99 21:54:23.220544 progress 20 % (2 MB)
100 21:54:23.317308 progress 25 % (2 MB)
101 21:54:23.408832 progress 30 % (3 MB)
102 21:54:23.498412 progress 35 % (3 MB)
103 21:54:23.592592 progress 40 % (4 MB)
104 21:54:23.684819 progress 45 % (5 MB)
105 21:54:23.786841 progress 50 % (5 MB)
106 21:54:23.880896 progress 55 % (6 MB)
107 21:54:23.984338 progress 60 % (6 MB)
108 21:54:24.082199 progress 65 % (7 MB)
109 21:54:24.174491 progress 70 % (7 MB)
110 21:54:24.272621 progress 75 % (8 MB)
111 21:54:24.365380 progress 80 % (8 MB)
112 21:54:24.448375 progress 85 % (9 MB)
113 21:54:24.542456 progress 90 % (9 MB)
114 21:54:24.621142 progress 95 % (10 MB)
115 21:54:24.698186 progress 100 % (11 MB)
116 21:54:24.709280 11 MB downloaded in 1.91 s (5.80 MB/s)
117 21:54:24.710162 end: 1.4.1 http-download (duration 00:00:02) [common]
119 21:54:24.711747 end: 1.4 download-retry (duration 00:00:02) [common]
120 21:54:24.712312 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 21:54:24.712825 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 21:54:24.713314 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 21:54:24.713807 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 21:54:24.714813 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs
125 21:54:24.715654 makedir: /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin
126 21:54:24.716357 makedir: /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/tests
127 21:54:24.716978 makedir: /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/results
128 21:54:24.717586 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-add-keys
129 21:54:24.718522 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-add-sources
130 21:54:24.719446 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-background-process-start
131 21:54:24.720429 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-background-process-stop
132 21:54:24.721424 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-common-functions
133 21:54:24.722336 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-echo-ipv4
134 21:54:24.723245 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-install-packages
135 21:54:24.724173 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-installed-packages
136 21:54:24.725090 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-os-build
137 21:54:24.726007 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-probe-channel
138 21:54:24.726945 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-probe-ip
139 21:54:24.727891 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-target-ip
140 21:54:24.728853 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-target-mac
141 21:54:24.729751 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-target-storage
142 21:54:24.730660 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-test-case
143 21:54:24.731559 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-test-event
144 21:54:24.732497 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-test-feedback
145 21:54:24.733402 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-test-raise
146 21:54:24.734354 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-test-reference
147 21:54:24.735280 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-test-runner
148 21:54:24.736225 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-test-set
149 21:54:24.737183 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-test-shell
150 21:54:24.738184 Updating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-install-packages (oe)
151 21:54:24.739199 Updating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/bin/lava-installed-packages (oe)
152 21:54:24.740072 Creating /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/environment
153 21:54:24.740817 LAVA metadata
154 21:54:24.741298 - LAVA_JOB_ID=937037
155 21:54:24.741724 - LAVA_DISPATCHER_IP=192.168.6.2
156 21:54:24.742405 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 21:54:24.744466 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 21:54:24.745084 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 21:54:24.745493 skipped lava-vland-overlay
160 21:54:24.745979 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 21:54:24.746483 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 21:54:24.746908 skipped lava-multinode-overlay
163 21:54:24.747385 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 21:54:24.747880 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 21:54:24.748398 Loading test definitions
166 21:54:24.748952 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 21:54:24.749389 Using /lava-937037 at stage 0
168 21:54:24.751630 uuid=937037_1.5.2.4.1 testdef=None
169 21:54:24.752174 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 21:54:24.752461 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 21:54:24.754358 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 21:54:24.755169 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 21:54:24.757611 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 21:54:24.758453 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 21:54:24.760765 runner path: /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/0/tests/0_dmesg test_uuid 937037_1.5.2.4.1
178 21:54:24.761379 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 21:54:24.762159 Creating lava-test-runner.conf files
181 21:54:24.762364 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/937037/lava-overlay-4m4h0gfs/lava-937037/0 for stage 0
182 21:54:24.762722 - 0_dmesg
183 21:54:24.763078 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 21:54:24.763358 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 21:54:24.787762 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 21:54:24.788241 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 21:54:24.788522 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 21:54:24.788790 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 21:54:24.789053 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 21:54:25.715291 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 21:54:25.715758 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 21:54:25.716049 extracting modules file /var/lib/lava/dispatcher/tmp/937037/tftp-deploy-w6kt60fr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/937037/extract-overlay-ramdisk-7saw3944/ramdisk
193 21:54:27.045989 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 21:54:27.046476 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 21:54:27.046754 [common] Applying overlay /var/lib/lava/dispatcher/tmp/937037/compress-overlay-s3j6p7xe/overlay-1.5.2.5.tar.gz to ramdisk
196 21:54:27.046968 [common] Applying overlay /var/lib/lava/dispatcher/tmp/937037/compress-overlay-s3j6p7xe/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/937037/extract-overlay-ramdisk-7saw3944/ramdisk
197 21:54:27.077079 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 21:54:27.077504 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 21:54:27.077773 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 21:54:27.078002 Converting downloaded kernel to a uImage
201 21:54:27.078305 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/937037/tftp-deploy-w6kt60fr/kernel/Image /var/lib/lava/dispatcher/tmp/937037/tftp-deploy-w6kt60fr/kernel/uImage
202 21:54:27.621849 output: Image Name:
203 21:54:27.622260 output: Created: Mon Nov 4 21:54:27 2024
204 21:54:27.622471 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 21:54:27.622675 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 21:54:27.622877 output: Load Address: 01080000
207 21:54:27.623073 output: Entry Point: 01080000
208 21:54:27.623269 output:
209 21:54:27.623599 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 21:54:27.623861 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 21:54:27.624183 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 21:54:27.624443 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 21:54:27.624699 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 21:54:27.624953 Building ramdisk /var/lib/lava/dispatcher/tmp/937037/extract-overlay-ramdisk-7saw3944/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/937037/extract-overlay-ramdisk-7saw3944/ramdisk
215 21:54:30.498691 >> 181573 blocks
216 21:54:38.952855 Adding RAMdisk u-boot header.
217 21:54:38.953715 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/937037/extract-overlay-ramdisk-7saw3944/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/937037/extract-overlay-ramdisk-7saw3944/ramdisk.cpio.gz.uboot
218 21:54:39.218226 output: Image Name:
219 21:54:39.218612 output: Created: Mon Nov 4 21:54:38 2024
220 21:54:39.218820 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 21:54:39.219023 output: Data Size: 26054567 Bytes = 25443.91 KiB = 24.85 MiB
222 21:54:39.219223 output: Load Address: 00000000
223 21:54:39.219420 output: Entry Point: 00000000
224 21:54:39.219614 output:
225 21:54:39.220784 rename /var/lib/lava/dispatcher/tmp/937037/extract-overlay-ramdisk-7saw3944/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/937037/tftp-deploy-w6kt60fr/ramdisk/ramdisk.cpio.gz.uboot
226 21:54:39.221596 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 21:54:39.222190 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 21:54:39.222760 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 21:54:39.223266 No LXC device requested
230 21:54:39.223813 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 21:54:39.224399 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 21:54:39.224934 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 21:54:39.225395 Checking files for TFTP limit of 4294967296 bytes.
234 21:54:39.228308 end: 1 tftp-deploy (duration 00:00:17) [common]
235 21:54:39.228928 start: 2 uboot-action (timeout 00:05:00) [common]
236 21:54:39.229497 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 21:54:39.230038 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 21:54:39.230585 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 21:54:39.231163 Using kernel file from prepare-kernel: 937037/tftp-deploy-w6kt60fr/kernel/uImage
240 21:54:39.231822 substitutions:
241 21:54:39.232307 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 21:54:39.232750 - {DTB_ADDR}: 0x01070000
243 21:54:39.233183 - {DTB}: 937037/tftp-deploy-w6kt60fr/dtb/meson-g12b-a311d-libretech-cc.dtb
244 21:54:39.233619 - {INITRD}: 937037/tftp-deploy-w6kt60fr/ramdisk/ramdisk.cpio.gz.uboot
245 21:54:39.234054 - {KERNEL_ADDR}: 0x01080000
246 21:54:39.234485 - {KERNEL}: 937037/tftp-deploy-w6kt60fr/kernel/uImage
247 21:54:39.234915 - {LAVA_MAC}: None
248 21:54:39.235387 - {PRESEED_CONFIG}: None
249 21:54:39.235818 - {PRESEED_LOCAL}: None
250 21:54:39.236277 - {RAMDISK_ADDR}: 0x08000000
251 21:54:39.236705 - {RAMDISK}: 937037/tftp-deploy-w6kt60fr/ramdisk/ramdisk.cpio.gz.uboot
252 21:54:39.237137 - {ROOT_PART}: None
253 21:54:39.237564 - {ROOT}: None
254 21:54:39.237991 - {SERVER_IP}: 192.168.6.2
255 21:54:39.238421 - {TEE_ADDR}: 0x83000000
256 21:54:39.238849 - {TEE}: None
257 21:54:39.239275 Parsed boot commands:
258 21:54:39.239688 - setenv autoload no
259 21:54:39.240165 - setenv initrd_high 0xffffffff
260 21:54:39.240594 - setenv fdt_high 0xffffffff
261 21:54:39.241017 - dhcp
262 21:54:39.241440 - setenv serverip 192.168.6.2
263 21:54:39.241867 - tftpboot 0x01080000 937037/tftp-deploy-w6kt60fr/kernel/uImage
264 21:54:39.242292 - tftpboot 0x08000000 937037/tftp-deploy-w6kt60fr/ramdisk/ramdisk.cpio.gz.uboot
265 21:54:39.242720 - tftpboot 0x01070000 937037/tftp-deploy-w6kt60fr/dtb/meson-g12b-a311d-libretech-cc.dtb
266 21:54:39.243145 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 21:54:39.243575 - bootm 0x01080000 0x08000000 0x01070000
268 21:54:39.244132 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 21:54:39.245755 start: 2.3 connect-device (timeout 00:05:00) [common]
271 21:54:39.246238 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 21:54:39.261727 Setting prompt string to ['lava-test: # ']
273 21:54:39.263334 end: 2.3 connect-device (duration 00:00:00) [common]
274 21:54:39.264019 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 21:54:39.264635 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 21:54:39.265218 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 21:54:39.266464 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 21:54:39.301116 >> OK - accepted request
279 21:54:39.302961 Returned 0 in 0 seconds
280 21:54:39.404150 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 21:54:39.405873 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 21:54:39.406479 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 21:54:39.407033 Setting prompt string to ['Hit any key to stop autoboot']
285 21:54:39.407520 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 21:54:39.409233 Trying 192.168.56.21...
287 21:54:39.409752 Connected to conserv1.
288 21:54:39.410196 Escape character is '^]'.
289 21:54:39.410649
290 21:54:39.411113 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 21:54:39.411590
292 21:54:51.223413 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 21:54:51.224126 bl2_stage_init 0x01
294 21:54:51.224613 bl2_stage_init 0x81
295 21:54:51.228902 hw id: 0x0000 - pwm id 0x01
296 21:54:51.229409 bl2_stage_init 0xc1
297 21:54:51.229857 bl2_stage_init 0x02
298 21:54:51.230309
299 21:54:51.234559 L0:00000000
300 21:54:51.235036 L1:20000703
301 21:54:51.235469 L2:00008067
302 21:54:51.235894 L3:14000000
303 21:54:51.240070 B2:00402000
304 21:54:51.240575 B1:e0f83180
305 21:54:51.241005
306 21:54:51.241435 TE: 58124
307 21:54:51.241866
308 21:54:51.245791 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 21:54:51.246298
310 21:54:51.246736 Board ID = 1
311 21:54:51.251199 Set A53 clk to 24M
312 21:54:51.251663 Set A73 clk to 24M
313 21:54:51.252124 Set clk81 to 24M
314 21:54:51.256754 A53 clk: 1200 MHz
315 21:54:51.257254 A73 clk: 1200 MHz
316 21:54:51.257696 CLK81: 166.6M
317 21:54:51.258148 smccc: 00012a92
318 21:54:51.262359 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 21:54:51.267955 board id: 1
320 21:54:51.273823 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 21:54:51.284497 fw parse done
322 21:54:51.290049 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 21:54:51.333192 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 21:54:51.343972 PIEI prepare done
325 21:54:51.344505 fastboot data load
326 21:54:51.344941 fastboot data verify
327 21:54:51.349707 verify result: 266
328 21:54:51.355232 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 21:54:51.355740 LPDDR4 probe
330 21:54:51.356233 ddr clk to 1584MHz
331 21:54:51.362311 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 21:54:51.400548
333 21:54:51.401075 dmc_version 0001
334 21:54:51.407209 Check phy result
335 21:54:51.413015 INFO : End of CA training
336 21:54:51.413502 INFO : End of initialization
337 21:54:51.418655 INFO : Training has run successfully!
338 21:54:51.419118 Check phy result
339 21:54:51.424234 INFO : End of initialization
340 21:54:51.424691 INFO : End of read enable training
341 21:54:51.429808 INFO : End of fine write leveling
342 21:54:51.435424 INFO : End of Write leveling coarse delay
343 21:54:51.435880 INFO : Training has run successfully!
344 21:54:51.436346 Check phy result
345 21:54:51.441007 INFO : End of initialization
346 21:54:51.441473 INFO : End of read dq deskew training
347 21:54:51.446612 INFO : End of MPR read delay center optimization
348 21:54:51.452219 INFO : End of write delay center optimization
349 21:54:51.457791 INFO : End of read delay center optimization
350 21:54:51.458255 INFO : End of max read latency training
351 21:54:51.463386 INFO : Training has run successfully!
352 21:54:51.463875 1D training succeed
353 21:54:51.472589 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 21:54:51.520360 Check phy result
355 21:54:51.520880 INFO : End of initialization
356 21:54:51.541913 INFO : End of 2D read delay Voltage center optimization
357 21:54:51.562300 INFO : End of 2D read delay Voltage center optimization
358 21:54:51.614315 INFO : End of 2D write delay Voltage center optimization
359 21:54:51.663600 INFO : End of 2D write delay Voltage center optimization
360 21:54:51.669307 INFO : Training has run successfully!
361 21:54:51.669766
362 21:54:51.670202 channel==0
363 21:54:51.674809 RxClkDly_Margin_A0==88 ps 9
364 21:54:51.675277 TxDqDly_Margin_A0==98 ps 10
365 21:54:51.680452 RxClkDly_Margin_A1==88 ps 9
366 21:54:51.680925 TxDqDly_Margin_A1==98 ps 10
367 21:54:51.681362 TrainedVREFDQ_A0==74
368 21:54:51.686027 TrainedVREFDQ_A1==74
369 21:54:51.686484 VrefDac_Margin_A0==25
370 21:54:51.686913 DeviceVref_Margin_A0==40
371 21:54:51.691630 VrefDac_Margin_A1==25
372 21:54:51.692124 DeviceVref_Margin_A1==40
373 21:54:51.692563
374 21:54:51.692991
375 21:54:51.697323 channel==1
376 21:54:51.697777 RxClkDly_Margin_A0==98 ps 10
377 21:54:51.698209 TxDqDly_Margin_A0==98 ps 10
378 21:54:51.702811 RxClkDly_Margin_A1==88 ps 9
379 21:54:51.703267 TxDqDly_Margin_A1==98 ps 10
380 21:54:51.708370 TrainedVREFDQ_A0==77
381 21:54:51.708827 TrainedVREFDQ_A1==77
382 21:54:51.709259 VrefDac_Margin_A0==22
383 21:54:51.713982 DeviceVref_Margin_A0==37
384 21:54:51.714434 VrefDac_Margin_A1==24
385 21:54:51.719614 DeviceVref_Margin_A1==37
386 21:54:51.720086
387 21:54:51.720521 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 21:54:51.725306
389 21:54:51.753332 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
390 21:54:51.753879 2D training succeed
391 21:54:51.758804 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 21:54:51.764278 auto size-- 65535DDR cs0 size: 2048MB
393 21:54:51.764732 DDR cs1 size: 2048MB
394 21:54:51.769893 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 21:54:51.770343 cs0 DataBus test pass
396 21:54:51.775481 cs1 DataBus test pass
397 21:54:51.775932 cs0 AddrBus test pass
398 21:54:51.776410 cs1 AddrBus test pass
399 21:54:51.776835
400 21:54:51.781163 100bdlr_step_size ps== 420
401 21:54:51.781637 result report
402 21:54:51.786683 boot times 0Enable ddr reg access
403 21:54:51.792251 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 21:54:51.805572 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 21:54:52.378716 0.0;M3 CHK:0;cm4_sp_mode 0
406 21:54:52.379355 MVN_1=0x00000000
407 21:54:52.384213 MVN_2=0x00000000
408 21:54:52.389944 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 21:54:52.390432 OPS=0x10
410 21:54:52.390854 ring efuse init
411 21:54:52.391260 chipver efuse init
412 21:54:52.395538 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 21:54:52.401206 [0.018961 Inits done]
414 21:54:52.401676 secure task start!
415 21:54:52.402089 high task start!
416 21:54:52.405716 low task start!
417 21:54:52.406184 run into bl31
418 21:54:52.412315 NOTICE: BL31: v1.3(release):4fc40b1
419 21:54:52.420191 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 21:54:52.420684 NOTICE: BL31: G12A normal boot!
421 21:54:52.445519 NOTICE: BL31: BL33 decompress pass
422 21:54:52.451171 ERROR: Error initializing runtime service opteed_fast
423 21:54:53.684066
424 21:54:53.684657
425 21:54:53.692506 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 21:54:53.692996
427 21:54:53.693410 Model: Libre Computer AML-A311D-CC Alta
428 21:54:53.900109 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 21:54:53.924216 DRAM: 2 GiB (effective 3.8 GiB)
430 21:54:54.067255 Core: 408 devices, 31 uclasses, devicetree: separate
431 21:54:54.073067 WDT: Not starting watchdog@f0d0
432 21:54:54.105353 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 21:54:54.117753 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 21:54:54.122759 ** Bad device specification mmc 0 **
435 21:54:54.133083 Card did not respond to voltage select! : -110
436 21:54:54.140751 ** Bad device specification mmc 0 **
437 21:54:54.141239 Couldn't find partition mmc 0
438 21:54:54.149098 Card did not respond to voltage select! : -110
439 21:54:54.154613 ** Bad device specification mmc 0 **
440 21:54:54.155097 Couldn't find partition mmc 0
441 21:54:54.159689 Error: could not access storage.
442 21:54:55.424493 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
443 21:54:55.425114 bl2_stage_init 0x81
444 21:54:55.430043 hw id: 0x0000 - pwm id 0x01
445 21:54:55.430520 bl2_stage_init 0xc1
446 21:54:55.430927 bl2_stage_init 0x02
447 21:54:55.431324
448 21:54:55.435597 L0:00000000
449 21:54:55.436093 L1:20000703
450 21:54:55.436498 L2:00008067
451 21:54:55.436895 L3:14000000
452 21:54:55.437286 B2:00402000
453 21:54:55.441192 B1:e0f83180
454 21:54:55.441641
455 21:54:55.442044 TE: 58150
456 21:54:55.442441
457 21:54:55.446808 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 21:54:55.447266
459 21:54:55.447667 Board ID = 1
460 21:54:55.452482 Set A53 clk to 24M
461 21:54:55.452922 Set A73 clk to 24M
462 21:54:55.453325 Set clk81 to 24M
463 21:54:55.457982 A53 clk: 1200 MHz
464 21:54:55.458422 A73 clk: 1200 MHz
465 21:54:55.458822 CLK81: 166.6M
466 21:54:55.459219 smccc: 00012aac
467 21:54:55.463617 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 21:54:55.469221 board id: 1
469 21:54:55.474062 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 21:54:55.485650 fw parse done
471 21:54:55.491691 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 21:54:55.534234 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 21:54:55.545125 PIEI prepare done
474 21:54:55.545575 fastboot data load
475 21:54:55.545985 fastboot data verify
476 21:54:55.550806 verify result: 266
477 21:54:55.556402 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 21:54:55.556841 LPDDR4 probe
479 21:54:55.557238 ddr clk to 1584MHz
480 21:54:55.564364 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 21:54:55.600864
482 21:54:55.601329 dmc_version 0001
483 21:54:55.608396 Check phy result
484 21:54:55.614179 INFO : End of CA training
485 21:54:55.614621 INFO : End of initialization
486 21:54:55.619791 INFO : Training has run successfully!
487 21:54:55.620275 Check phy result
488 21:54:55.625381 INFO : End of initialization
489 21:54:55.625820 INFO : End of read enable training
490 21:54:55.628690 INFO : End of fine write leveling
491 21:54:55.634215 INFO : End of Write leveling coarse delay
492 21:54:55.639803 INFO : Training has run successfully!
493 21:54:55.640275 Check phy result
494 21:54:55.640677 INFO : End of initialization
495 21:54:55.645431 INFO : End of read dq deskew training
496 21:54:55.651023 INFO : End of MPR read delay center optimization
497 21:54:55.651455 INFO : End of write delay center optimization
498 21:54:55.656697 INFO : End of read delay center optimization
499 21:54:55.662227 INFO : End of max read latency training
500 21:54:55.662692 INFO : Training has run successfully!
501 21:54:55.667805 1D training succeed
502 21:54:55.673814 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 21:54:55.721324 Check phy result
504 21:54:55.721796 INFO : End of initialization
505 21:54:55.742803 INFO : End of 2D read delay Voltage center optimization
506 21:54:55.762431 INFO : End of 2D read delay Voltage center optimization
507 21:54:55.815342 INFO : End of 2D write delay Voltage center optimization
508 21:54:55.864803 INFO : End of 2D write delay Voltage center optimization
509 21:54:55.870434 INFO : Training has run successfully!
510 21:54:55.870875
511 21:54:55.871282 channel==0
512 21:54:55.876014 RxClkDly_Margin_A0==88 ps 9
513 21:54:55.876455 TxDqDly_Margin_A0==98 ps 10
514 21:54:55.881538 RxClkDly_Margin_A1==88 ps 9
515 21:54:55.881972 TxDqDly_Margin_A1==98 ps 10
516 21:54:55.882374 TrainedVREFDQ_A0==74
517 21:54:55.887072 TrainedVREFDQ_A1==74
518 21:54:55.887501 VrefDac_Margin_A0==25
519 21:54:55.887899 DeviceVref_Margin_A0==40
520 21:54:55.892711 VrefDac_Margin_A1==25
521 21:54:55.893138 DeviceVref_Margin_A1==40
522 21:54:55.893533
523 21:54:55.893926
524 21:54:55.898304 channel==1
525 21:54:55.898743 RxClkDly_Margin_A0==98 ps 10
526 21:54:55.899144 TxDqDly_Margin_A0==98 ps 10
527 21:54:55.903862 RxClkDly_Margin_A1==98 ps 10
528 21:54:55.904319 TxDqDly_Margin_A1==88 ps 9
529 21:54:55.909455 TrainedVREFDQ_A0==77
530 21:54:55.909891 TrainedVREFDQ_A1==77
531 21:54:55.910291 VrefDac_Margin_A0==22
532 21:54:55.915128 DeviceVref_Margin_A0==37
533 21:54:55.915564 VrefDac_Margin_A1==22
534 21:54:55.920747 DeviceVref_Margin_A1==37
535 21:54:55.921183
536 21:54:55.921583 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 21:54:55.926377
538 21:54:55.954315 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
539 21:54:55.954801 2D training succeed
540 21:54:55.959894 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 21:54:55.965472 auto size-- 65535DDR cs0 size: 2048MB
542 21:54:55.965910 DDR cs1 size: 2048MB
543 21:54:55.971097 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 21:54:55.971530 cs0 DataBus test pass
545 21:54:55.976736 cs1 DataBus test pass
546 21:54:55.977171 cs0 AddrBus test pass
547 21:54:55.977568 cs1 AddrBus test pass
548 21:54:55.977959
549 21:54:55.982280 100bdlr_step_size ps== 420
550 21:54:55.982722 result report
551 21:54:55.987854 boot times 0Enable ddr reg access
552 21:54:55.992405 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 21:54:56.005850 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 21:54:56.580742 0.0;M3 CHK:0;cm4_sp_mode 0
555 21:54:56.581372 MVN_1=0x00000000
556 21:54:56.586224 MVN_2=0x00000000
557 21:54:56.591812 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 21:54:56.592342 OPS=0x10
559 21:54:56.592755 ring efuse init
560 21:54:56.593157 chipver efuse init
561 21:54:56.600122 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 21:54:56.600717 [0.018960 Inits done]
563 21:54:56.606568 secure task start!
564 21:54:56.607191 high task start!
565 21:54:56.607706 low task start!
566 21:54:56.608269 run into bl31
567 21:54:56.614204 NOTICE: BL31: v1.3(release):4fc40b1
568 21:54:56.620995 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 21:54:56.621601 NOTICE: BL31: G12A normal boot!
570 21:54:56.647379 NOTICE: BL31: BL33 decompress pass
571 21:54:56.652164 ERROR: Error initializing runtime service opteed_fast
572 21:54:57.886118
573 21:54:57.886882
574 21:54:57.894338 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 21:54:57.894943
576 21:54:57.895493 Model: Libre Computer AML-A311D-CC Alta
577 21:54:58.102797 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 21:54:58.126237 DRAM: 2 GiB (effective 3.8 GiB)
579 21:54:58.269201 Core: 408 devices, 31 uclasses, devicetree: separate
580 21:54:58.275041 WDT: Not starting watchdog@f0d0
581 21:54:58.307405 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 21:54:58.319816 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 21:54:58.324796 ** Bad device specification mmc 0 **
584 21:54:58.335140 Card did not respond to voltage select! : -110
585 21:54:58.343251 ** Bad device specification mmc 0 **
586 21:54:58.343695 Couldn't find partition mmc 0
587 21:54:58.351111 Card did not respond to voltage select! : -110
588 21:54:58.356638 ** Bad device specification mmc 0 **
589 21:54:58.357092 Couldn't find partition mmc 0
590 21:54:58.361681 Error: could not access storage.
591 21:54:58.704207 Net: eth0: ethernet@ff3f0000
592 21:54:58.704766 starting USB...
593 21:54:58.956063 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 21:54:58.956602 Starting the controller
595 21:54:58.962975 USB XHCI 1.10
596 21:55:00.675465 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 21:55:00.676112 bl2_stage_init 0x01
598 21:55:00.676540 bl2_stage_init 0x81
599 21:55:00.681046 hw id: 0x0000 - pwm id 0x01
600 21:55:00.681499 bl2_stage_init 0xc1
601 21:55:00.681908 bl2_stage_init 0x02
602 21:55:00.682306
603 21:55:00.686637 L0:00000000
604 21:55:00.687080 L1:20000703
605 21:55:00.687485 L2:00008067
606 21:55:00.687883 L3:14000000
607 21:55:00.692222 B2:00402000
608 21:55:00.692676 B1:e0f83180
609 21:55:00.693074
610 21:55:00.693471 TE: 58159
611 21:55:00.693868
612 21:55:00.697836 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 21:55:00.698291
614 21:55:00.698694 Board ID = 1
615 21:55:00.703436 Set A53 clk to 24M
616 21:55:00.703871 Set A73 clk to 24M
617 21:55:00.704306 Set clk81 to 24M
618 21:55:00.709032 A53 clk: 1200 MHz
619 21:55:00.709468 A73 clk: 1200 MHz
620 21:55:00.709868 CLK81: 166.6M
621 21:55:00.710257 smccc: 00012ab5
622 21:55:00.714633 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 21:55:00.720266 board id: 1
624 21:55:00.726118 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 21:55:00.736811 fw parse done
626 21:55:00.742747 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 21:55:00.785458 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 21:55:00.796252 PIEI prepare done
629 21:55:00.796696 fastboot data load
630 21:55:00.797101 fastboot data verify
631 21:55:00.801874 verify result: 266
632 21:55:00.807478 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 21:55:00.807915 LPDDR4 probe
634 21:55:00.808363 ddr clk to 1584MHz
635 21:55:00.815591 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 21:55:00.852692
637 21:55:00.853151 dmc_version 0001
638 21:55:00.859463 Check phy result
639 21:55:00.865237 INFO : End of CA training
640 21:55:00.865671 INFO : End of initialization
641 21:55:00.870892 INFO : Training has run successfully!
642 21:55:00.871320 Check phy result
643 21:55:00.876443 INFO : End of initialization
644 21:55:00.876874 INFO : End of read enable training
645 21:55:00.882026 INFO : End of fine write leveling
646 21:55:00.887643 INFO : End of Write leveling coarse delay
647 21:55:00.888107 INFO : Training has run successfully!
648 21:55:00.888513 Check phy result
649 21:55:00.893259 INFO : End of initialization
650 21:55:00.893712 INFO : End of read dq deskew training
651 21:55:00.898840 INFO : End of MPR read delay center optimization
652 21:55:00.904423 INFO : End of write delay center optimization
653 21:55:00.910033 INFO : End of read delay center optimization
654 21:55:00.910488 INFO : End of max read latency training
655 21:55:00.915692 INFO : Training has run successfully!
656 21:55:00.916171 1D training succeed
657 21:55:00.924871 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 21:55:00.972527 Check phy result
659 21:55:00.973013 INFO : End of initialization
660 21:55:00.994183 INFO : End of 2D read delay Voltage center optimization
661 21:55:01.014505 INFO : End of 2D read delay Voltage center optimization
662 21:55:01.066537 INFO : End of 2D write delay Voltage center optimization
663 21:55:01.115863 INFO : End of 2D write delay Voltage center optimization
664 21:55:01.121424 INFO : Training has run successfully!
665 21:55:01.121870
666 21:55:01.122271 channel==0
667 21:55:01.127019 RxClkDly_Margin_A0==88 ps 9
668 21:55:01.127456 TxDqDly_Margin_A0==98 ps 10
669 21:55:01.130444 RxClkDly_Margin_A1==88 ps 9
670 21:55:01.130872 TxDqDly_Margin_A1==98 ps 10
671 21:55:01.136066 TrainedVREFDQ_A0==74
672 21:55:01.136520 TrainedVREFDQ_A1==74
673 21:55:01.136924 VrefDac_Margin_A0==25
674 21:55:01.141641 DeviceVref_Margin_A0==40
675 21:55:01.142082 VrefDac_Margin_A1==25
676 21:55:01.147362 DeviceVref_Margin_A1==40
677 21:55:01.147830
678 21:55:01.148278
679 21:55:01.148683 channel==1
680 21:55:01.149074 RxClkDly_Margin_A0==98 ps 10
681 21:55:01.152844 TxDqDly_Margin_A0==88 ps 9
682 21:55:01.153294 RxClkDly_Margin_A1==98 ps 10
683 21:55:01.158427 TxDqDly_Margin_A1==88 ps 9
684 21:55:01.158868 TrainedVREFDQ_A0==77
685 21:55:01.159276 TrainedVREFDQ_A1==77
686 21:55:01.164043 VrefDac_Margin_A0==22
687 21:55:01.164487 DeviceVref_Margin_A0==37
688 21:55:01.169628 VrefDac_Margin_A1==22
689 21:55:01.170072 DeviceVref_Margin_A1==37
690 21:55:01.170472
691 21:55:01.175207 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 21:55:01.175654
693 21:55:01.203332 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 0000005f
694 21:55:01.208828 2D training succeed
695 21:55:01.214441 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 21:55:01.214890 auto size-- 65535DDR cs0 size: 2048MB
697 21:55:01.220054 DDR cs1 size: 2048MB
698 21:55:01.220500 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 21:55:01.225635 cs0 DataBus test pass
700 21:55:01.226073 cs1 DataBus test pass
701 21:55:01.226475 cs0 AddrBus test pass
702 21:55:01.231313 cs1 AddrBus test pass
703 21:55:01.231754
704 21:55:01.232191 100bdlr_step_size ps== 420
705 21:55:01.232596 result report
706 21:55:01.236834 boot times 0Enable ddr reg access
707 21:55:01.244402 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 21:55:01.257862 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 21:55:01.831026 0.0;M3 CHK:0;cm4_sp_mode 0
710 21:55:01.831637 MVN_1=0x00000000
711 21:55:01.836633 MVN_2=0x00000000
712 21:55:01.842224 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 21:55:01.842781 OPS=0x10
714 21:55:01.843185 ring efuse init
715 21:55:01.843574 chipver efuse init
716 21:55:01.847790 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 21:55:01.853397 [0.018961 Inits done]
718 21:55:01.853854 secure task start!
719 21:55:01.854244 high task start!
720 21:55:01.857952 low task start!
721 21:55:01.858315 run into bl31
722 21:55:01.864765 NOTICE: BL31: v1.3(release):4fc40b1
723 21:55:01.872742 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 21:55:01.873361 NOTICE: BL31: G12A normal boot!
725 21:55:01.897965 NOTICE: BL31: BL33 decompress pass
726 21:55:01.903818 ERROR: Error initializing runtime service opteed_fast
727 21:55:03.136398
728 21:55:03.136829
729 21:55:03.144899 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 21:55:03.145398
731 21:55:03.145759 Model: Libre Computer AML-A311D-CC Alta
732 21:55:03.353287 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 21:55:03.376770 DRAM: 2 GiB (effective 3.8 GiB)
734 21:55:03.519662 Core: 408 devices, 31 uclasses, devicetree: separate
735 21:55:03.524629 WDT: Not starting watchdog@f0d0
736 21:55:03.557963 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 21:55:03.570225 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 21:55:03.574550 ** Bad device specification mmc 0 **
739 21:55:03.585594 Card did not respond to voltage select! : -110
740 21:55:03.593320 ** Bad device specification mmc 0 **
741 21:55:03.593694 Couldn't find partition mmc 0
742 21:55:03.601621 Card did not respond to voltage select! : -110
743 21:55:03.607041 ** Bad device specification mmc 0 **
744 21:55:03.607526 Couldn't find partition mmc 0
745 21:55:03.612160 Error: could not access storage.
746 21:55:03.954602 Net: eth0: ethernet@ff3f0000
747 21:55:03.955199 starting USB...
748 21:55:04.206446 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 21:55:04.207024 Starting the controller
750 21:55:04.213489 USB XHCI 1.10
751 21:55:06.373968 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 21:55:06.374586 bl2_stage_init 0x01
753 21:55:06.375005 bl2_stage_init 0x81
754 21:55:06.379643 hw id: 0x0000 - pwm id 0x01
755 21:55:06.380190 bl2_stage_init 0xc1
756 21:55:06.380615 bl2_stage_init 0x02
757 21:55:06.381019
758 21:55:06.385231 L0:00000000
759 21:55:06.385730 L1:20000703
760 21:55:06.386136 L2:00008067
761 21:55:06.386532 L3:14000000
762 21:55:06.390694 B2:00402000
763 21:55:06.391171 B1:e0f83180
764 21:55:06.391573
765 21:55:06.391972 TE: 58124
766 21:55:06.392417
767 21:55:06.396349 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 21:55:06.396834
769 21:55:06.397243 Board ID = 1
770 21:55:06.401959 Set A53 clk to 24M
771 21:55:06.402431 Set A73 clk to 24M
772 21:55:06.402841 Set clk81 to 24M
773 21:55:06.407539 A53 clk: 1200 MHz
774 21:55:06.408032 A73 clk: 1200 MHz
775 21:55:06.408444 CLK81: 166.6M
776 21:55:06.408837 smccc: 00012a92
777 21:55:06.413148 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 21:55:06.418730 board id: 1
779 21:55:06.424631 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 21:55:06.435351 fw parse done
781 21:55:06.441320 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 21:55:06.483808 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 21:55:06.494707 PIEI prepare done
784 21:55:06.495193 fastboot data load
785 21:55:06.495605 fastboot data verify
786 21:55:06.500339 verify result: 266
787 21:55:06.505939 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 21:55:06.506412 LPDDR4 probe
789 21:55:06.506817 ddr clk to 1584MHz
790 21:55:06.513934 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 21:55:06.551130
792 21:55:06.551653 dmc_version 0001
793 21:55:06.557858 Check phy result
794 21:55:06.563726 INFO : End of CA training
795 21:55:06.564215 INFO : End of initialization
796 21:55:06.569332 INFO : Training has run successfully!
797 21:55:06.569795 Check phy result
798 21:55:06.574878 INFO : End of initialization
799 21:55:06.575334 INFO : End of read enable training
800 21:55:06.580480 INFO : End of fine write leveling
801 21:55:06.586099 INFO : End of Write leveling coarse delay
802 21:55:06.586562 INFO : Training has run successfully!
803 21:55:06.586965 Check phy result
804 21:55:06.591692 INFO : End of initialization
805 21:55:06.592190 INFO : End of read dq deskew training
806 21:55:06.597326 INFO : End of MPR read delay center optimization
807 21:55:06.602879 INFO : End of write delay center optimization
808 21:55:06.608923 INFO : End of read delay center optimization
809 21:55:06.609378 INFO : End of max read latency training
810 21:55:06.614111 INFO : Training has run successfully!
811 21:55:06.614564 1D training succeed
812 21:55:06.622558 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 21:55:06.670822 Check phy result
814 21:55:06.671301 INFO : End of initialization
815 21:55:06.692696 INFO : End of 2D read delay Voltage center optimization
816 21:55:06.712122 INFO : End of 2D read delay Voltage center optimization
817 21:55:06.764129 INFO : End of 2D write delay Voltage center optimization
818 21:55:06.813572 INFO : End of 2D write delay Voltage center optimization
819 21:55:06.819123 INFO : Training has run successfully!
820 21:55:06.819606
821 21:55:06.820064 channel==0
822 21:55:06.824612 RxClkDly_Margin_A0==88 ps 9
823 21:55:06.825076 TxDqDly_Margin_A0==98 ps 10
824 21:55:06.830342 RxClkDly_Margin_A1==88 ps 9
825 21:55:06.830825 TxDqDly_Margin_A1==98 ps 10
826 21:55:06.831236 TrainedVREFDQ_A0==74
827 21:55:06.835899 TrainedVREFDQ_A1==75
828 21:55:06.836411 VrefDac_Margin_A0==25
829 21:55:06.836832 DeviceVref_Margin_A0==40
830 21:55:06.841556 VrefDac_Margin_A1==25
831 21:55:06.842049 DeviceVref_Margin_A1==39
832 21:55:06.842453
833 21:55:06.842857
834 21:55:06.847104 channel==1
835 21:55:06.847586 RxClkDly_Margin_A0==98 ps 10
836 21:55:06.847974 TxDqDly_Margin_A0==88 ps 9
837 21:55:06.852690 RxClkDly_Margin_A1==88 ps 9
838 21:55:06.853147 TxDqDly_Margin_A1==88 ps 9
839 21:55:06.858292 TrainedVREFDQ_A0==77
840 21:55:06.858747 TrainedVREFDQ_A1==77
841 21:55:06.859135 VrefDac_Margin_A0==23
842 21:55:06.863847 DeviceVref_Margin_A0==37
843 21:55:06.864325 VrefDac_Margin_A1==24
844 21:55:06.869430 DeviceVref_Margin_A1==37
845 21:55:06.869872
846 21:55:06.870258 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 21:55:06.870642
848 21:55:06.903044 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
849 21:55:06.903601 2D training succeed
850 21:55:06.908613 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 21:55:06.914201 auto size-- 65535DDR cs0 size: 2048MB
852 21:55:06.914653 DDR cs1 size: 2048MB
853 21:55:06.919731 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 21:55:06.920228 cs0 DataBus test pass
855 21:55:06.925329 cs1 DataBus test pass
856 21:55:06.925782 cs0 AddrBus test pass
857 21:55:06.926165 cs1 AddrBus test pass
858 21:55:06.926543
859 21:55:06.930928 100bdlr_step_size ps== 420
860 21:55:06.931386 result report
861 21:55:06.936533 boot times 0Enable ddr reg access
862 21:55:06.941800 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 21:55:06.955339 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 21:55:07.528843 0.0;M3 CHK:0;cm4_sp_mode 0
865 21:55:07.529272 MVN_1=0x00000000
866 21:55:07.534354 MVN_2=0x00000000
867 21:55:07.540147 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 21:55:07.540635 OPS=0x10
869 21:55:07.541034 ring efuse init
870 21:55:07.541424 chipver efuse init
871 21:55:07.545791 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 21:55:07.551380 [0.018960 Inits done]
873 21:55:07.551832 secure task start!
874 21:55:07.552269 high task start!
875 21:55:07.555970 low task start!
876 21:55:07.556469 run into bl31
877 21:55:07.562647 NOTICE: BL31: v1.3(release):4fc40b1
878 21:55:07.570461 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 21:55:07.570937 NOTICE: BL31: G12A normal boot!
880 21:55:07.595827 NOTICE: BL31: BL33 decompress pass
881 21:55:07.601548 ERROR: Error initializing runtime service opteed_fast
882 21:55:08.834395
883 21:55:08.834968
884 21:55:08.842824 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 21:55:08.843306
886 21:55:08.843715 Model: Libre Computer AML-A311D-CC Alta
887 21:55:09.051193 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 21:55:09.074578 DRAM: 2 GiB (effective 3.8 GiB)
889 21:55:09.217541 Core: 408 devices, 31 uclasses, devicetree: separate
890 21:55:09.223321 WDT: Not starting watchdog@f0d0
891 21:55:09.255667 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 21:55:09.268100 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 21:55:09.273053 ** Bad device specification mmc 0 **
894 21:55:09.283489 Card did not respond to voltage select! : -110
895 21:55:09.291037 ** Bad device specification mmc 0 **
896 21:55:09.291595 Couldn't find partition mmc 0
897 21:55:09.299495 Card did not respond to voltage select! : -110
898 21:55:09.305024 ** Bad device specification mmc 0 **
899 21:55:09.305417 Couldn't find partition mmc 0
900 21:55:09.309956 Error: could not access storage.
901 21:55:09.653602 Net: eth0: ethernet@ff3f0000
902 21:55:09.654205 starting USB...
903 21:55:09.905375 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 21:55:09.905948 Starting the controller
905 21:55:09.912303 USB XHCI 1.10
906 21:55:11.773762 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
907 21:55:11.774176 bl2_stage_init 0x01
908 21:55:11.774413 bl2_stage_init 0x81
909 21:55:11.779384 hw id: 0x0000 - pwm id 0x01
910 21:55:11.779756 bl2_stage_init 0xc1
911 21:55:11.780025 bl2_stage_init 0x02
912 21:55:11.780268
913 21:55:11.785009 L0:00000000
914 21:55:11.785391 L1:20000703
915 21:55:11.785626 L2:00008067
916 21:55:11.785859 L3:14000000
917 21:55:11.790579 B2:00402000
918 21:55:11.791116 B1:e0f83180
919 21:55:11.791510
920 21:55:11.791888 TE: 58124
921 21:55:11.792311
922 21:55:11.796156 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
923 21:55:11.796505
924 21:55:11.796739 Board ID = 1
925 21:55:11.801786 Set A53 clk to 24M
926 21:55:11.802293 Set A73 clk to 24M
927 21:55:11.802674 Set clk81 to 24M
928 21:55:11.807345 A53 clk: 1200 MHz
929 21:55:11.807802 A73 clk: 1200 MHz
930 21:55:11.808090 CLK81: 166.6M
931 21:55:11.808321 smccc: 00012a92
932 21:55:11.812964 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
933 21:55:11.818548 board id: 1
934 21:55:11.823448 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
935 21:55:11.835058 fw parse done
936 21:55:11.841017 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
937 21:55:11.883630 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
938 21:55:11.894646 PIEI prepare done
939 21:55:11.895035 fastboot data load
940 21:55:11.895276 fastboot data verify
941 21:55:11.900356 verify result: 266
942 21:55:11.905930 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
943 21:55:11.906263 LPDDR4 probe
944 21:55:11.906491 ddr clk to 1584MHz
945 21:55:11.913952 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
946 21:55:11.950781
947 21:55:11.951409 dmc_version 0001
948 21:55:11.958185 Check phy result
949 21:55:11.964447 INFO : End of CA training
950 21:55:11.964952 INFO : End of initialization
951 21:55:11.969982 INFO : Training has run successfully!
952 21:55:11.970584 Check phy result
953 21:55:11.975109 INFO : End of initialization
954 21:55:11.975636 INFO : End of read enable training
955 21:55:11.978320 INFO : End of fine write leveling
956 21:55:11.984082 INFO : End of Write leveling coarse delay
957 21:55:11.989355 INFO : Training has run successfully!
958 21:55:11.989888 Check phy result
959 21:55:11.990342 INFO : End of initialization
960 21:55:11.995072 INFO : End of read dq deskew training
961 21:55:11.998460 INFO : End of MPR read delay center optimization
962 21:55:12.004179 INFO : End of write delay center optimization
963 21:55:12.009559 INFO : End of read delay center optimization
964 21:55:12.010086 INFO : End of max read latency training
965 21:55:12.015181 INFO : Training has run successfully!
966 21:55:12.015772 1D training succeed
967 21:55:12.022282 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
968 21:55:12.071008 Check phy result
969 21:55:12.071677 INFO : End of initialization
970 21:55:12.092429 INFO : End of 2D read delay Voltage center optimization
971 21:55:12.113107 INFO : End of 2D read delay Voltage center optimization
972 21:55:12.164671 INFO : End of 2D write delay Voltage center optimization
973 21:55:12.214988 INFO : End of 2D write delay Voltage center optimization
974 21:55:12.220569 INFO : Training has run successfully!
975 21:55:12.221056
976 21:55:12.221622 channel==0
977 21:55:12.226177 RxClkDly_Margin_A0==88 ps 9
978 21:55:12.226660 TxDqDly_Margin_A0==98 ps 10
979 21:55:12.231880 RxClkDly_Margin_A1==88 ps 9
980 21:55:12.232395 TxDqDly_Margin_A1==88 ps 9
981 21:55:12.232853 TrainedVREFDQ_A0==74
982 21:55:12.237363 TrainedVREFDQ_A1==74
983 21:55:12.237842 VrefDac_Margin_A0==25
984 21:55:12.238288 DeviceVref_Margin_A0==40
985 21:55:12.242975 VrefDac_Margin_A1==24
986 21:55:12.243445 DeviceVref_Margin_A1==40
987 21:55:12.243888
988 21:55:12.244369
989 21:55:12.244814 channel==1
990 21:55:12.248585 RxClkDly_Margin_A0==98 ps 10
991 21:55:12.249059 TxDqDly_Margin_A0==88 ps 9
992 21:55:12.254171 RxClkDly_Margin_A1==98 ps 10
993 21:55:12.254646 TxDqDly_Margin_A1==88 ps 9
994 21:55:12.259744 TrainedVREFDQ_A0==77
995 21:55:12.260265 TrainedVREFDQ_A1==77
996 21:55:12.260721 VrefDac_Margin_A0==22
997 21:55:12.265347 DeviceVref_Margin_A0==37
998 21:55:12.265815 VrefDac_Margin_A1==22
999 21:55:12.270992 DeviceVref_Margin_A1==37
1000 21:55:12.271467
1001 21:55:12.271914 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1002 21:55:12.272389
1003 21:55:12.304576 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1004 21:55:12.305092 2D training succeed
1005 21:55:12.310174 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1006 21:55:12.315784 auto size-- 65535DDR cs0 size: 2048MB
1007 21:55:12.316293 DDR cs1 size: 2048MB
1008 21:55:12.321354 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1009 21:55:12.321828 cs0 DataBus test pass
1010 21:55:12.326974 cs1 DataBus test pass
1011 21:55:12.327445 cs0 AddrBus test pass
1012 21:55:12.327891 cs1 AddrBus test pass
1013 21:55:12.328375
1014 21:55:12.332567 100bdlr_step_size ps== 420
1015 21:55:12.333055 result report
1016 21:55:12.338177 boot times 0Enable ddr reg access
1017 21:55:12.343435 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1018 21:55:12.356935 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1019 21:55:12.930541 0.0;M3 CHK:0;cm4_sp_mode 0
1020 21:55:12.931121 MVN_1=0x00000000
1021 21:55:12.936092 MVN_2=0x00000000
1022 21:55:12.941826 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1023 21:55:12.942306 OPS=0x10
1024 21:55:12.942755 ring efuse init
1025 21:55:12.943194 chipver efuse init
1026 21:55:12.947438 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1027 21:55:12.953026 [0.018961 Inits done]
1028 21:55:12.953496 secure task start!
1029 21:55:12.953934 high task start!
1030 21:55:12.956660 low task start!
1031 21:55:12.957131 run into bl31
1032 21:55:12.964314 NOTICE: BL31: v1.3(release):4fc40b1
1033 21:55:12.971251 NOTICE: BL31: Built : 15:58:17, May 22 2019
1034 21:55:12.971725 NOTICE: BL31: G12A normal boot!
1035 21:55:12.997562 NOTICE: BL31: BL33 decompress pass
1036 21:55:13.002154 ERROR: Error initializing runtime service opteed_fast
1037 21:55:14.236006
1038 21:55:14.236419
1039 21:55:14.243493 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1040 21:55:14.243997
1041 21:55:14.244268 Model: Libre Computer AML-A311D-CC Alta
1042 21:55:14.451874 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1043 21:55:14.475480 DRAM: 2 GiB (effective 3.8 GiB)
1044 21:55:14.619267 Core: 408 devices, 31 uclasses, devicetree: separate
1045 21:55:14.624216 WDT: Not starting watchdog@f0d0
1046 21:55:14.663210 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1047 21:55:14.669948 Loading Environment from FAT... Card did not respond to voltage select! : -110
1048 21:55:14.673923 ** Bad device specification mmc 0 **
1049 21:55:14.685087 Card did not respond to voltage select! : -110
1050 21:55:14.691761 ** Bad device specification mmc 0 **
1051 21:55:14.692210 Couldn't find partition mmc 0
1052 21:55:14.701090 Card did not respond to voltage select! : -110
1053 21:55:14.706631 ** Bad device specification mmc 0 **
1054 21:55:14.707006 Couldn't find partition mmc 0
1055 21:55:14.710710 Error: could not access storage.
1056 21:55:15.053478 Net: eth0: ethernet@ff3f0000
1057 21:55:15.053935 starting USB...
1058 21:55:15.305950 Bus usb@ff500000: Register 3000140 NbrPorts 3
1059 21:55:15.306425 Starting the controller
1060 21:55:15.313100 USB XHCI 1.10
1061 21:55:16.867026 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1062 21:55:16.875358 scanning usb for storage devices... 0 Storage Device(s) found
1064 21:55:16.927027 Hit any key to stop autoboot: 1
1065 21:55:16.927945 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1066 21:55:16.928618 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1067 21:55:16.929089 Setting prompt string to ['=>']
1068 21:55:16.929553 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1069 21:55:16.942825 0
1070 21:55:16.943705 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1071 21:55:16.944269 Sending with 10 millisecond of delay
1073 21:55:18.079073 => setenv autoload no
1074 21:55:18.089909 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1075 21:55:18.094952 setenv autoload no
1076 21:55:18.095757 Sending with 10 millisecond of delay
1078 21:55:19.892591 => setenv initrd_high 0xffffffff
1079 21:55:19.903379 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1080 21:55:19.904260 setenv initrd_high 0xffffffff
1081 21:55:19.904975 Sending with 10 millisecond of delay
1083 21:55:21.520972 => setenv fdt_high 0xffffffff
1084 21:55:21.531702 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1085 21:55:21.532548 setenv fdt_high 0xffffffff
1086 21:55:21.533251 Sending with 10 millisecond of delay
1088 21:55:21.825010 => dhcp
1089 21:55:21.835698 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1090 21:55:21.836528 dhcp
1091 21:55:21.836962 Speed: 1000, full duplex
1092 21:55:21.837375 BOOTP broadcast 1
1093 21:55:21.844270 DHCP client bound to address 192.168.6.27 (8 ms)
1094 21:55:21.844995 Sending with 10 millisecond of delay
1096 21:55:23.521153 => setenv serverip 192.168.6.2
1097 21:55:23.531947 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1098 21:55:23.532857 setenv serverip 192.168.6.2
1099 21:55:23.533540 Sending with 10 millisecond of delay
1101 21:55:27.256113 => tftpboot 0x01080000 937037/tftp-deploy-w6kt60fr/kernel/uImage
1102 21:55:27.266913 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1103 21:55:27.267787 tftpboot 0x01080000 937037/tftp-deploy-w6kt60fr/kernel/uImage
1104 21:55:27.268290 Speed: 1000, full duplex
1105 21:55:27.268709 Using ethernet@ff3f0000 device
1106 21:55:27.269789 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1107 21:55:27.275282 Filename '937037/tftp-deploy-w6kt60fr/kernel/uImage'.
1108 21:55:27.279210 Load address: 0x1080000
1109 21:55:30.060260 Loading: *################################################## 43.6 MiB
1110 21:55:30.060878 15.7 MiB/s
1111 21:55:30.061311 done
1112 21:55:30.064882 Bytes transferred = 45713984 (2b98a40 hex)
1113 21:55:30.065725 Sending with 10 millisecond of delay
1115 21:55:34.751694 => tftpboot 0x08000000 937037/tftp-deploy-w6kt60fr/ramdisk/ramdisk.cpio.gz.uboot
1116 21:55:34.762512 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1117 21:55:34.763334 tftpboot 0x08000000 937037/tftp-deploy-w6kt60fr/ramdisk/ramdisk.cpio.gz.uboot
1118 21:55:34.763778 Speed: 1000, full duplex
1119 21:55:34.764235 Using ethernet@ff3f0000 device
1120 21:55:34.765305 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1121 21:55:34.777166 Filename '937037/tftp-deploy-w6kt60fr/ramdisk/ramdisk.cpio.gz.uboot'.
1122 21:55:34.777660 Load address: 0x8000000
1123 21:55:41.678888 Loading: *####################T ############################# UDP wrong checksum 00000005 00002111
1124 21:55:46.680116 T UDP wrong checksum 00000005 00002111
1125 21:55:56.682999 T T UDP wrong checksum 00000005 00002111
1126 21:56:16.685141 T T T UDP wrong checksum 00000005 00002111
1127 21:56:31.691301 T T T
1128 21:56:31.691958 Retry count exceeded; starting again
1130 21:56:31.693567 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1133 21:56:31.695616 end: 2.4 uboot-commands (duration 00:01:52) [common]
1135 21:56:31.697155 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1137 21:56:31.698274 end: 2 uboot-action (duration 00:01:52) [common]
1139 21:56:31.699919 Cleaning after the job
1140 21:56:31.700549 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/937037/tftp-deploy-w6kt60fr/ramdisk
1141 21:56:31.701921 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/937037/tftp-deploy-w6kt60fr/kernel
1142 21:56:31.750103 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/937037/tftp-deploy-w6kt60fr/dtb
1143 21:56:31.750863 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/937037/tftp-deploy-w6kt60fr/modules
1144 21:56:31.769462 start: 4.1 power-off (timeout 00:00:30) [common]
1145 21:56:31.770098 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1146 21:56:31.806315 >> OK - accepted request
1147 21:56:31.808527 Returned 0 in 0 seconds
1148 21:56:31.909545 end: 4.1 power-off (duration 00:00:00) [common]
1150 21:56:31.910424 start: 4.2 read-feedback (timeout 00:10:00) [common]
1151 21:56:31.911078 Listened to connection for namespace 'common' for up to 1s
1152 21:56:32.911548 Finalising connection for namespace 'common'
1153 21:56:32.912076 Disconnecting from shell: Finalise
1154 21:56:32.912464 =>
1155 21:56:33.013359 end: 4.2 read-feedback (duration 00:00:01) [common]
1156 21:56:33.014072 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/937037
1157 21:56:33.307472 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/937037
1158 21:56:33.308084 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.