Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 20:59:19.265265 lava-dispatcher, installed at version: 2024.01
2 20:59:19.266064 start: 0 validate
3 20:59:19.266519 Start time: 2024-11-05 20:59:19.266490+00:00 (UTC)
4 20:59:19.267007 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 20:59:19.267509 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 20:59:19.298996 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 20:59:19.299552 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-228-ga18dadd1209ac%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 20:59:19.322436 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 20:59:19.323019 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-228-ga18dadd1209ac%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 20:59:19.350760 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 20:59:19.351257 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 20:59:19.372876 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 20:59:19.373341 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-228-ga18dadd1209ac%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 20:59:19.402591 validate duration: 0.14
16 20:59:19.403499 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 20:59:19.403825 start: 1.1 download-retry (timeout 00:10:00) [common]
18 20:59:19.404119 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 20:59:19.404708 Not decompressing ramdisk as can be used compressed.
20 20:59:19.405132 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 20:59:19.405408 saving as /var/lib/lava/dispatcher/tmp/942676/tftp-deploy-eaamaxf6/ramdisk/initrd.cpio.gz
22 20:59:19.405673 total size: 4775763 (4 MB)
23 20:59:19.439862 progress 0 % (0 MB)
24 20:59:19.443527 progress 5 % (0 MB)
25 20:59:19.446790 progress 10 % (0 MB)
26 20:59:19.449990 progress 15 % (0 MB)
27 20:59:19.453538 progress 20 % (0 MB)
28 20:59:19.456723 progress 25 % (1 MB)
29 20:59:19.459829 progress 30 % (1 MB)
30 20:59:19.463338 progress 35 % (1 MB)
31 20:59:19.466464 progress 40 % (1 MB)
32 20:59:19.469587 progress 45 % (2 MB)
33 20:59:19.472706 progress 50 % (2 MB)
34 20:59:19.476248 progress 55 % (2 MB)
35 20:59:19.479386 progress 60 % (2 MB)
36 20:59:19.482525 progress 65 % (2 MB)
37 20:59:19.486017 progress 70 % (3 MB)
38 20:59:19.489096 progress 75 % (3 MB)
39 20:59:19.492272 progress 80 % (3 MB)
40 20:59:19.495401 progress 85 % (3 MB)
41 20:59:19.498928 progress 90 % (4 MB)
42 20:59:19.501876 progress 95 % (4 MB)
43 20:59:19.504727 progress 100 % (4 MB)
44 20:59:19.505343 4 MB downloaded in 0.10 s (45.71 MB/s)
45 20:59:19.505905 end: 1.1.1 http-download (duration 00:00:00) [common]
47 20:59:19.506789 end: 1.1 download-retry (duration 00:00:00) [common]
48 20:59:19.507099 start: 1.2 download-retry (timeout 00:10:00) [common]
49 20:59:19.507382 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 20:59:19.507861 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-228-ga18dadd1209ac/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 20:59:19.508146 saving as /var/lib/lava/dispatcher/tmp/942676/tftp-deploy-eaamaxf6/kernel/zImage
52 20:59:19.508378 total size: 11440640 (10 MB)
53 20:59:19.508620 No compression specified
54 20:59:19.544944 progress 0 % (0 MB)
55 20:59:19.554305 progress 5 % (0 MB)
56 20:59:19.563113 progress 10 % (1 MB)
57 20:59:19.572648 progress 15 % (1 MB)
58 20:59:19.581710 progress 20 % (2 MB)
59 20:59:19.590339 progress 25 % (2 MB)
60 20:59:19.597663 progress 30 % (3 MB)
61 20:59:19.607051 progress 35 % (3 MB)
62 20:59:19.614428 progress 40 % (4 MB)
63 20:59:19.622228 progress 45 % (4 MB)
64 20:59:19.629367 progress 50 % (5 MB)
65 20:59:19.637182 progress 55 % (6 MB)
66 20:59:19.644498 progress 60 % (6 MB)
67 20:59:19.652041 progress 65 % (7 MB)
68 20:59:19.660112 progress 70 % (7 MB)
69 20:59:19.667563 progress 75 % (8 MB)
70 20:59:19.675569 progress 80 % (8 MB)
71 20:59:19.683035 progress 85 % (9 MB)
72 20:59:19.691012 progress 90 % (9 MB)
73 20:59:19.698611 progress 95 % (10 MB)
74 20:59:19.706215 progress 100 % (10 MB)
75 20:59:19.706758 10 MB downloaded in 0.20 s (55.00 MB/s)
76 20:59:19.707233 end: 1.2.1 http-download (duration 00:00:00) [common]
78 20:59:19.708052 end: 1.2 download-retry (duration 00:00:00) [common]
79 20:59:19.708351 start: 1.3 download-retry (timeout 00:10:00) [common]
80 20:59:19.708626 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 20:59:19.709097 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-228-ga18dadd1209ac/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 20:59:19.709337 saving as /var/lib/lava/dispatcher/tmp/942676/tftp-deploy-eaamaxf6/dtb/am335x-boneblack.dtb
83 20:59:19.709542 total size: 70568 (0 MB)
84 20:59:19.709750 No compression specified
85 20:59:19.739263 progress 46 % (0 MB)
86 20:59:19.740110 progress 92 % (0 MB)
87 20:59:19.740810 progress 100 % (0 MB)
88 20:59:19.741189 0 MB downloaded in 0.03 s (2.13 MB/s)
89 20:59:19.741640 end: 1.3.1 http-download (duration 00:00:00) [common]
91 20:59:19.742489 end: 1.3 download-retry (duration 00:00:00) [common]
92 20:59:19.742753 start: 1.4 download-retry (timeout 00:10:00) [common]
93 20:59:19.743017 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 20:59:19.743484 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 20:59:19.743723 saving as /var/lib/lava/dispatcher/tmp/942676/tftp-deploy-eaamaxf6/nfsrootfs/full.rootfs.tar
96 20:59:19.743927 total size: 117747780 (112 MB)
97 20:59:19.744135 Using unxz to decompress xz
98 20:59:19.775398 progress 0 % (0 MB)
99 20:59:20.489937 progress 5 % (5 MB)
100 20:59:21.228767 progress 10 % (11 MB)
101 20:59:21.996165 progress 15 % (16 MB)
102 20:59:22.699751 progress 20 % (22 MB)
103 20:59:23.275925 progress 25 % (28 MB)
104 20:59:24.070748 progress 30 % (33 MB)
105 20:59:24.863120 progress 35 % (39 MB)
106 20:59:25.198642 progress 40 % (44 MB)
107 20:59:25.550437 progress 45 % (50 MB)
108 20:59:26.203459 progress 50 % (56 MB)
109 20:59:27.004485 progress 55 % (61 MB)
110 20:59:27.727074 progress 60 % (67 MB)
111 20:59:28.438654 progress 65 % (73 MB)
112 20:59:29.196738 progress 70 % (78 MB)
113 20:59:29.951869 progress 75 % (84 MB)
114 20:59:30.684231 progress 80 % (89 MB)
115 20:59:31.390345 progress 85 % (95 MB)
116 20:59:32.181061 progress 90 % (101 MB)
117 20:59:32.958652 progress 95 % (106 MB)
118 20:59:33.875435 progress 100 % (112 MB)
119 20:59:33.890960 112 MB downloaded in 14.15 s (7.94 MB/s)
120 20:59:33.891619 end: 1.4.1 http-download (duration 00:00:14) [common]
122 20:59:33.892543 end: 1.4 download-retry (duration 00:00:14) [common]
123 20:59:33.892854 start: 1.5 download-retry (timeout 00:09:46) [common]
124 20:59:33.893157 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 20:59:33.893858 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-228-ga18dadd1209ac/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 20:59:33.894158 saving as /var/lib/lava/dispatcher/tmp/942676/tftp-deploy-eaamaxf6/modules/modules.tar
127 20:59:33.894394 total size: 6608664 (6 MB)
128 20:59:33.894626 Using unxz to decompress xz
129 20:59:33.933415 progress 0 % (0 MB)
130 20:59:33.967742 progress 5 % (0 MB)
131 20:59:34.011046 progress 10 % (0 MB)
132 20:59:34.054441 progress 15 % (0 MB)
133 20:59:34.098815 progress 20 % (1 MB)
134 20:59:34.146536 progress 25 % (1 MB)
135 20:59:34.189718 progress 30 % (1 MB)
136 20:59:34.232597 progress 35 % (2 MB)
137 20:59:34.276424 progress 40 % (2 MB)
138 20:59:34.319733 progress 45 % (2 MB)
139 20:59:34.363931 progress 50 % (3 MB)
140 20:59:34.407875 progress 55 % (3 MB)
141 20:59:34.456879 progress 60 % (3 MB)
142 20:59:34.499371 progress 65 % (4 MB)
143 20:59:34.544558 progress 70 % (4 MB)
144 20:59:34.589124 progress 75 % (4 MB)
145 20:59:34.635035 progress 80 % (5 MB)
146 20:59:34.675470 progress 85 % (5 MB)
147 20:59:34.719760 progress 90 % (5 MB)
148 20:59:34.765171 progress 95 % (6 MB)
149 20:59:34.808919 progress 100 % (6 MB)
150 20:59:34.821358 6 MB downloaded in 0.93 s (6.80 MB/s)
151 20:59:34.822610 end: 1.5.1 http-download (duration 00:00:01) [common]
153 20:59:34.824492 end: 1.5 download-retry (duration 00:00:01) [common]
154 20:59:34.824773 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 20:59:34.825038 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 20:59:51.605792 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/942676/extract-nfsrootfs-ao5id5gi
157 20:59:51.606415 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 20:59:51.606702 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 20:59:51.607466 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi
160 20:59:51.607923 makedir: /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin
161 20:59:51.608247 makedir: /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/tests
162 20:59:51.608563 makedir: /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/results
163 20:59:51.608895 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-add-keys
164 20:59:51.609456 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-add-sources
165 20:59:51.610028 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-background-process-start
166 20:59:51.610552 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-background-process-stop
167 20:59:51.611092 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-common-functions
168 20:59:51.611594 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-echo-ipv4
169 20:59:51.612086 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-install-packages
170 20:59:51.612634 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-installed-packages
171 20:59:51.613148 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-os-build
172 20:59:51.613689 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-probe-channel
173 20:59:51.614214 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-probe-ip
174 20:59:51.614689 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-target-ip
175 20:59:51.615164 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-target-mac
176 20:59:51.615638 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-target-storage
177 20:59:51.616126 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-test-case
178 20:59:51.616606 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-test-event
179 20:59:51.617101 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-test-feedback
180 20:59:51.617610 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-test-raise
181 20:59:51.618120 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-test-reference
182 20:59:51.618606 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-test-runner
183 20:59:51.619094 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-test-set
184 20:59:51.619568 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-test-shell
185 20:59:51.620054 Updating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-add-keys (debian)
186 20:59:51.620587 Updating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-add-sources (debian)
187 20:59:51.621092 Updating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-install-packages (debian)
188 20:59:51.621587 Updating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-installed-packages (debian)
189 20:59:51.622105 Updating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/bin/lava-os-build (debian)
190 20:59:51.622542 Creating /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/environment
191 20:59:51.622911 LAVA metadata
192 20:59:51.623166 - LAVA_JOB_ID=942676
193 20:59:51.623378 - LAVA_DISPATCHER_IP=192.168.6.3
194 20:59:51.623725 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 20:59:51.624636 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 20:59:51.624941 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 20:59:51.625145 skipped lava-vland-overlay
198 20:59:51.625382 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 20:59:51.625632 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 20:59:51.625849 skipped lava-multinode-overlay
201 20:59:51.626089 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 20:59:51.626336 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 20:59:51.626577 Loading test definitions
204 20:59:51.626845 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 20:59:51.627079 Using /lava-942676 at stage 0
206 20:59:51.628158 uuid=942676_1.6.2.4.1 testdef=None
207 20:59:51.628451 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 20:59:51.628711 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 20:59:51.630262 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 20:59:51.631048 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 20:59:51.632941 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 20:59:51.633756 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 20:59:51.635592 runner path: /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/0/tests/0_timesync-off test_uuid 942676_1.6.2.4.1
216 20:59:51.636148 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 20:59:51.636967 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 20:59:51.637189 Using /lava-942676 at stage 0
220 20:59:51.637537 Fetching tests from https://github.com/kernelci/test-definitions.git
221 20:59:51.637842 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/0/tests/1_kselftest-dt'
222 20:59:54.916290 Running '/usr/bin/git checkout kernelci.org
223 20:59:55.360259 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 20:59:55.362563 uuid=942676_1.6.2.4.5 testdef=None
225 20:59:55.363177 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 20:59:55.364655 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 20:59:55.370101 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 20:59:55.371697 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 20:59:55.378892 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 20:59:55.380551 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 20:59:55.387554 runner path: /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/0/tests/1_kselftest-dt test_uuid 942676_1.6.2.4.5
235 20:59:55.388108 BOARD='beaglebone-black'
236 20:59:55.388521 BRANCH='broonie-sound'
237 20:59:55.388920 SKIPFILE='/dev/null'
238 20:59:55.389319 SKIP_INSTALL='True'
239 20:59:55.389708 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-228-ga18dadd1209ac/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 20:59:55.390190 TST_CASENAME=''
241 20:59:55.390637 TST_CMDFILES='dt'
242 20:59:55.391728 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 20:59:55.393292 Creating lava-test-runner.conf files
245 20:59:55.393706 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/942676/lava-overlay-0p5wdfyi/lava-942676/0 for stage 0
246 20:59:55.394393 - 0_timesync-off
247 20:59:55.394656 - 1_kselftest-dt
248 20:59:55.395010 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 20:59:55.395303 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 21:00:18.735533 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 21:00:18.736012 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 21:00:18.736317 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 21:00:18.736642 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 21:00:18.736952 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 21:00:19.152785 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 21:00:19.153296 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 21:00:19.153572 extracting modules file /var/lib/lava/dispatcher/tmp/942676/tftp-deploy-eaamaxf6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/942676/extract-nfsrootfs-ao5id5gi
258 21:00:20.139920 extracting modules file /var/lib/lava/dispatcher/tmp/942676/tftp-deploy-eaamaxf6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/942676/extract-overlay-ramdisk-k3w78z1k/ramdisk
259 21:00:21.087459 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 21:00:21.087928 start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
261 21:00:21.088222 [common] Applying overlay to NFS
262 21:00:21.088449 [common] Applying overlay /var/lib/lava/dispatcher/tmp/942676/compress-overlay-q5bfdorv/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/942676/extract-nfsrootfs-ao5id5gi
263 21:00:23.846572 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 21:00:23.847061 start: 1.6.6 prepare-kernel (timeout 00:08:56) [common]
265 21:00:23.847370 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:56) [common]
266 21:00:23.847718 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 21:00:23.848010 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 21:00:23.848287 start: 1.6.7 configure-preseed-file (timeout 00:08:56) [common]
269 21:00:23.848563 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 21:00:23.848855 start: 1.6.8 compress-ramdisk (timeout 00:08:56) [common]
271 21:00:23.849106 Building ramdisk /var/lib/lava/dispatcher/tmp/942676/extract-overlay-ramdisk-k3w78z1k/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/942676/extract-overlay-ramdisk-k3w78z1k/ramdisk
272 21:00:25.000015 >> 74896 blocks
273 21:00:29.565155 Adding RAMdisk u-boot header.
274 21:00:29.565637 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/942676/extract-overlay-ramdisk-k3w78z1k/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/942676/extract-overlay-ramdisk-k3w78z1k/ramdisk.cpio.gz.uboot
275 21:00:29.780094 output: Image Name:
276 21:00:29.780539 output: Created: Tue Nov 5 21:00:29 2024
277 21:00:29.780770 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 21:00:29.780989 output: Data Size: 14789176 Bytes = 14442.55 KiB = 14.10 MiB
279 21:00:29.781201 output: Load Address: 00000000
280 21:00:29.781416 output: Entry Point: 00000000
281 21:00:29.781703 output:
282 21:00:29.782508 rename /var/lib/lava/dispatcher/tmp/942676/extract-overlay-ramdisk-k3w78z1k/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/942676/tftp-deploy-eaamaxf6/ramdisk/ramdisk.cpio.gz.uboot
283 21:00:29.782974 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 21:00:29.783286 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 21:00:29.783585 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:50) [common]
286 21:00:29.783834 No LXC device requested
287 21:00:29.784094 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 21:00:29.784355 start: 1.8 deploy-device-env (timeout 00:08:50) [common]
289 21:00:29.784608 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 21:00:29.784817 Checking files for TFTP limit of 4294967296 bytes.
291 21:00:29.786504 end: 1 tftp-deploy (duration 00:01:10) [common]
292 21:00:29.786908 start: 2 uboot-action (timeout 00:05:00) [common]
293 21:00:29.787199 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 21:00:29.787472 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 21:00:29.787762 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 21:00:29.788227 substitutions:
297 21:00:29.788463 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 21:00:29.788694 - {DTB_ADDR}: 0x88000000
299 21:00:29.788935 - {DTB}: 942676/tftp-deploy-eaamaxf6/dtb/am335x-boneblack.dtb
300 21:00:29.789159 - {INITRD}: 942676/tftp-deploy-eaamaxf6/ramdisk/ramdisk.cpio.gz.uboot
301 21:00:29.789363 - {KERNEL_ADDR}: 0x82000000
302 21:00:29.789561 - {KERNEL}: 942676/tftp-deploy-eaamaxf6/kernel/zImage
303 21:00:29.789771 - {LAVA_MAC}: None
304 21:00:29.790056 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/942676/extract-nfsrootfs-ao5id5gi
305 21:00:29.790289 - {NFS_SERVER_IP}: 192.168.6.3
306 21:00:29.790510 - {PRESEED_CONFIG}: None
307 21:00:29.790726 - {PRESEED_LOCAL}: None
308 21:00:29.790939 - {RAMDISK_ADDR}: 0x83000000
309 21:00:29.791151 - {RAMDISK}: 942676/tftp-deploy-eaamaxf6/ramdisk/ramdisk.cpio.gz.uboot
310 21:00:29.791368 - {ROOT_PART}: None
311 21:00:29.791583 - {ROOT}: None
312 21:00:29.791803 - {SERVER_IP}: 192.168.6.3
313 21:00:29.792021 - {TEE_ADDR}: 0x83000000
314 21:00:29.792236 - {TEE}: None
315 21:00:29.792459 Parsed boot commands:
316 21:00:29.792661 - setenv autoload no
317 21:00:29.792860 - setenv initrd_high 0xffffffff
318 21:00:29.793678 - setenv fdt_high 0xffffffff
319 21:00:29.793928 - dhcp
320 21:00:29.794140 - setenv serverip 192.168.6.3
321 21:00:29.794344 - tftp 0x82000000 942676/tftp-deploy-eaamaxf6/kernel/zImage
322 21:00:29.795468 - tftp 0x83000000 942676/tftp-deploy-eaamaxf6/ramdisk/ramdisk.cpio.gz.uboot
323 21:00:29.795790 - setenv initrd_size ${filesize}
324 21:00:29.795995 - tftp 0x88000000 942676/tftp-deploy-eaamaxf6/dtb/am335x-boneblack.dtb
325 21:00:29.796200 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/942676/extract-nfsrootfs-ao5id5gi,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 21:00:29.796409 - bootz 0x82000000 0x83000000 0x88000000
327 21:00:29.799187 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 21:00:29.800989 start: 2.3 connect-device (timeout 00:05:00) [common]
330 21:00:29.801311 [common] connect-device Connecting to device using 'telnet conserv3 3002'
331 21:00:29.827035 Setting prompt string to ['lava-test: # ']
332 21:00:29.828139 end: 2.3 connect-device (duration 00:00:00) [common]
333 21:00:29.828619 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 21:00:29.829079 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 21:00:29.829514 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 21:00:29.830345 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
337 21:00:29.869475 >> OK - accepted request
338 21:00:29.871200 Returned 0 in 0 seconds
339 21:00:29.972389 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 21:00:29.973896 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 21:00:29.974469 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 21:00:29.974776 Setting prompt string to ['Hit any key to stop autoboot']
344 21:00:29.975019 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 21:00:29.975934 Trying 192.168.56.22...
346 21:00:29.976210 Connected to conserv3.
347 21:00:29.976425 Escape character is '^]'.
348 21:00:29.976793
349 21:00:29.977259 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 21:00:29.977691
351 21:00:37.962133
352 21:00:37.968925 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
353 21:00:37.969435 Trying to boot from MMC1
354 21:00:42.013542
355 21:00:42.020351 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
356 21:00:42.020858 Trying to boot from MMC1
357 21:00:44.708214
358 21:00:44.714707 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
359 21:00:44.715140 Trying to boot from MMC1
360 21:00:45.302496
361 21:00:45.302932
362 21:00:45.308049 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
363 21:00:45.308362
364 21:00:45.308621 CPU : AM335X-GP rev 2.0
365 21:00:45.313190 Model: TI AM335x BeagleBone Black
366 21:00:45.313483 DRAM: 512 MiB
367 21:00:45.393122 Core: 160 devices, 18 uclasses, devicetree: separate
368 21:00:45.407186 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
369 21:00:45.807983 NAND: 0 MiB
370 21:00:45.818214 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
371 21:00:45.946120 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
372 21:00:45.967469 <ethaddr> not set. Validating first E-fuse MAC
373 21:00:45.997924 Net: eth2: ethernet@4a100000, eth3: usb_ether
375 21:00:46.056341 Hit any key to stop autoboot: 2
376 21:00:46.057130 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
377 21:00:46.057725 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
378 21:00:46.058252 Setting prompt string to ['=>']
379 21:00:46.058743 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
380 21:00:46.066297 0
381 21:00:46.067207 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
382 21:00:46.067706 Sending with 10 millisecond of delay
384 21:00:47.202602 => setenv autoload no
385 21:00:47.213451 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
386 21:00:47.218569 setenv autoload no
387 21:00:47.219334 Sending with 10 millisecond of delay
389 21:00:49.016610 => setenv initrd_high 0xffffffff
390 21:00:49.027372 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
391 21:00:49.028168 setenv initrd_high 0xffffffff
392 21:00:49.028869 Sending with 10 millisecond of delay
394 21:00:50.645257 => setenv fdt_high 0xffffffff
395 21:00:50.656063 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
396 21:00:50.656861 setenv fdt_high 0xffffffff
397 21:00:50.657559 Sending with 10 millisecond of delay
399 21:00:50.949432 => dhcp
400 21:00:50.960021 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
401 21:00:50.960610 dhcp
402 21:00:50.962186 link up on port 0, speed 100, full duplex
403 21:00:50.963350 BOOTP broadcast 1
404 21:00:51.214567 BOOTP broadcast 2
405 21:00:51.717386 BOOTP broadcast 3
406 21:00:52.719338 BOOTP broadcast 4
407 21:00:52.818769 DHCP client bound to address 192.168.6.8 (1854 ms)
408 21:00:52.819615 Sending with 10 millisecond of delay
410 21:00:54.497695 => setenv serverip 192.168.6.3
411 21:00:54.508563 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
412 21:00:54.509532 setenv serverip 192.168.6.3
413 21:00:54.510359 Sending with 10 millisecond of delay
415 21:00:57.995168 => tftp 0x82000000 942676/tftp-deploy-eaamaxf6/kernel/zImage
416 21:00:58.005753 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
417 21:00:58.006409 tftp 0x82000000 942676/tftp-deploy-eaamaxf6/kernel/zImage
418 21:00:58.006656 link up on port 0, speed 100, full duplex
419 21:00:58.011270 Using ethernet@4a100000 device
420 21:00:58.017879 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
421 21:00:58.023367 Filename '942676/tftp-deploy-eaamaxf6/kernel/zImage'.
422 21:00:58.023754 Load address: 0x82000000
423 21:01:00.049891 Loading: *################################################## 10.9 MiB
424 21:01:00.050477 5.4 MiB/s
425 21:01:00.050910 done
426 21:01:00.053521 Bytes transferred = 11440640 (ae9200 hex)
427 21:01:00.054321 Sending with 10 millisecond of delay
429 21:01:04.500042 => tftp 0x83000000 942676/tftp-deploy-eaamaxf6/ramdisk/ramdisk.cpio.gz.uboot
430 21:01:04.510822 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
431 21:01:04.511677 tftp 0x83000000 942676/tftp-deploy-eaamaxf6/ramdisk/ramdisk.cpio.gz.uboot
432 21:01:04.512101 link up on port 0, speed 100, full duplex
433 21:01:04.516103 Using ethernet@4a100000 device
434 21:01:04.521304 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
435 21:01:04.524726 Filename '942676/tftp-deploy-eaamaxf6/ramdisk/ramdisk.cpio.gz.uboot'.
436 21:01:04.529999 Load address: 0x83000000
437 21:01:07.174898 Loading: *################################################## 14.1 MiB
438 21:01:07.175330 5.3 MiB/s
439 21:01:07.175540 done
440 21:01:07.179124 Bytes transferred = 14789240 (e1aa78 hex)
441 21:01:07.179725 Sending with 10 millisecond of delay
443 21:01:09.036419 => setenv initrd_size ${filesize}
444 21:01:09.047122 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
445 21:01:09.047611 setenv initrd_size ${filesize}
446 21:01:09.048060 Sending with 10 millisecond of delay
448 21:01:13.192506 => tftp 0x88000000 942676/tftp-deploy-eaamaxf6/dtb/am335x-boneblack.dtb
449 21:01:13.203270 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
450 21:01:13.204081 tftp 0x88000000 942676/tftp-deploy-eaamaxf6/dtb/am335x-boneblack.dtb
451 21:01:13.204500 link up on port 0, speed 100, full duplex
452 21:01:13.207843 Using ethernet@4a100000 device
453 21:01:13.213407 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
454 21:01:13.216836 Filename '942676/tftp-deploy-eaamaxf6/dtb/am335x-boneblack.dtb'.
455 21:01:13.220572 Load address: 0x88000000
456 21:01:13.232944 Loading: *################################################## 68.9 KiB
457 21:01:13.241798 4.8 MiB/s
458 21:01:13.242264 done
459 21:01:13.242654 Bytes transferred = 70568 (113a8 hex)
460 21:01:13.243305 Sending with 10 millisecond of delay
462 21:01:26.425215 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/942676/extract-nfsrootfs-ao5id5gi,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
463 21:01:26.435731 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
464 21:01:26.436184 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/942676/extract-nfsrootfs-ao5id5gi,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
465 21:01:26.436632 Sending with 10 millisecond of delay
467 21:01:28.775710 => bootz 0x82000000 0x83000000 0x88000000
468 21:01:28.786552 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
469 21:01:28.787107 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:01)
470 21:01:28.788307 bootz 0x82000000 0x83000000 0x88000000
471 21:01:28.788774 Kernel image @ 0x82000000 [ 0x000000 - 0xae9200 ]
472 21:01:28.789194 ## Loading init Ramdisk from Legacy Image at 83000000 ...
473 21:01:28.793877 Image Name:
474 21:01:28.794312 Created: 2024-11-05 21:00:29 UTC
475 21:01:28.799435 Image Type: ARM Linux RAMDisk Image (uncompressed)
476 21:01:28.804993 Data Size: 14789176 Bytes = 14.1 MiB
477 21:01:28.805416 Load Address: 00000000
478 21:01:28.811134 Entry Point: 00000000
479 21:01:28.979694 Verifying Checksum ... OK
480 21:01:28.980258 ## Flattened Device Tree blob at 88000000
481 21:01:28.986090 Booting using the fdt blob at 0x88000000
482 21:01:28.986575 Working FDT set to 88000000
483 21:01:28.991628 Using Device Tree in place at 88000000, end 880143a7
484 21:01:28.996136 Working FDT set to 88000000
485 21:01:29.009721
486 21:01:29.010181 Starting kernel ...
487 21:01:29.010399
488 21:01:29.010990 end: 2.4.3 bootloader-commands (duration 00:00:43) [common]
489 21:01:29.011365 start: 2.4.4 auto-login-action (timeout 00:04:01) [common]
490 21:01:29.011619 Setting prompt string to ['Linux version [0-9]']
491 21:01:29.011860 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
492 21:01:29.012096 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
493 21:01:29.856367 [ 0.000000] Booting Linux on physical CPU 0x0
494 21:01:29.862530 start: 2.4.4.1 login-action (timeout 00:04:00) [common]
495 21:01:29.863162 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
496 21:01:29.863690 Setting prompt string to []
497 21:01:29.864237 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
498 21:01:29.864750 Using line separator: #'\n'#
499 21:01:29.865205 No login prompt set.
500 21:01:29.865924 Parsing kernel messages
501 21:01:29.866446 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
502 21:01:29.867345 [login-action] Waiting for messages, (timeout 00:04:00)
503 21:01:29.867861 Waiting using forced prompt support (timeout 00:02:00)
504 21:01:29.876218 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j363793-arm-gcc-12-multi-v7-defconfig-zpgq5) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Tue Nov 5 20:23:39 UTC 2024
505 21:01:29.887669 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
506 21:01:29.890709 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
507 21:01:29.902164 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
508 21:01:29.907910 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
509 21:01:29.913806 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
510 21:01:29.914390 [ 0.000000] Memory policy: Data cache writeback
511 21:01:29.920327 [ 0.000000] efi: UEFI not found.
512 21:01:29.925637 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
513 21:01:29.931312 [ 0.000000] Zone ranges:
514 21:01:29.937063 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
515 21:01:29.942889 [ 0.000000] Normal empty
516 21:01:29.943419 [ 0.000000] HighMem empty
517 21:01:29.948651 [ 0.000000] Movable zone start for each node
518 21:01:29.949188 [ 0.000000] Early memory node ranges
519 21:01:29.960217 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
520 21:01:29.965421 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
521 21:01:29.990757 [ 0.000000] CPU: All CPU(s) started in SVC mode.
522 21:01:29.996399 [ 0.000000] AM335X ES2.0 (sgx neon)
523 21:01:30.008021 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
524 21:01:30.025695 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/942676/extract-nfsrootfs-ao5id5gi,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
525 21:01:30.037224 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
526 21:01:30.043093 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
527 21:01:30.048700 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
528 21:01:30.058757 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
529 21:01:30.087821 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
530 21:01:30.093896 <6>[ 0.000000] trace event string verifier disabled
531 21:01:30.094430 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
532 21:01:30.099578 <6>[ 0.000000] rcu: RCU event tracing is enabled.
533 21:01:30.110986 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
534 21:01:30.116778 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
535 21:01:30.123082 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
536 21:01:30.138864 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
537 21:01:30.156074 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
538 21:01:30.162810 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
539 21:01:30.254468 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
540 21:01:30.263312 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
541 21:01:30.275627 <6>[ 0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
542 21:01:30.283734 <6>[ 0.019149] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
543 21:01:30.293106 <6>[ 0.033933] Console: colour dummy device 80x30
544 21:01:30.299233 Matched prompt #6: WARNING:
545 21:01:30.299793 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
546 21:01:30.304574 <3>[ 0.038827] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
547 21:01:30.307371 <3>[ 0.045896] This ensures that you still see kernel messages. Please
548 21:01:30.313590 <3>[ 0.052624] update your kernel commandline.
549 21:01:30.354338 <6>[ 0.057237] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
550 21:01:30.360082 <6>[ 0.096155] CPU: Testing write buffer coherency: ok
551 21:01:30.362913 <6>[ 0.101521] CPU0: Spectre v2: using BPIALL workaround
552 21:01:30.368789 <6>[ 0.106989] pid_max: default: 32768 minimum: 301
553 21:01:30.374488 <6>[ 0.112184] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
554 21:01:30.387191 <6>[ 0.120005] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
555 21:01:30.394363 <6>[ 0.129362] CPU0: thread -1, cpu 0, socket -1, mpidr 0
556 21:01:30.398819 <6>[ 0.136367] Setting up static identity map for 0x80300000 - 0x803000ac
557 21:01:30.405238 <6>[ 0.146006] rcu: Hierarchical SRCU implementation.
558 21:01:30.412478 <6>[ 0.151289] rcu: Max phase no-delay instances is 1000.
559 21:01:30.421868 <6>[ 0.162404] EFI services will not be available.
560 21:01:30.427677 <6>[ 0.167689] smp: Bringing up secondary CPUs ...
561 21:01:30.433397 <6>[ 0.172733] smp: Brought up 1 node, 1 CPU
562 21:01:30.439314 <6>[ 0.177135] SMP: Total of 1 processors activated (996.14 BogoMIPS).
563 21:01:30.445093 <6>[ 0.183903] CPU: All CPU(s) started in SVC mode.
564 21:01:30.464516 <6>[ 0.189085] Memory: 406000K/522240K available (16384K kernel code, 2542K rwdata, 6784K rodata, 2048K init, 431K bss, 49048K reserved, 65536K cma-reserved, 0K highmem)
565 21:01:30.465096 <6>[ 0.205368] devtmpfs: initialized
566 21:01:30.487591 <6>[ 0.222443] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
567 21:01:30.499223 <6>[ 0.231026] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
568 21:01:30.505064 <6>[ 0.241485] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
569 21:01:30.515874 <6>[ 0.253834] pinctrl core: initialized pinctrl subsystem
570 21:01:30.525233 <6>[ 0.264478] DMI not present or invalid.
571 21:01:30.532224 <6>[ 0.270328] NET: Registered PF_NETLINK/PF_ROUTE protocol family
572 21:01:30.542911 <6>[ 0.279212] DMA: preallocated 256 KiB pool for atomic coherent allocations
573 21:01:30.558062 <6>[ 0.290773] thermal_sys: Registered thermal governor 'step_wise'
574 21:01:30.558570 <6>[ 0.290938] cpuidle: using governor menu
575 21:01:30.585694 <6>[ 0.326544] No ATAGs?
576 21:01:30.591834 <6>[ 0.329186] hw-breakpoint: debug architecture 0x4 unsupported.
577 21:01:30.602074 <6>[ 0.341241] Serial: AMBA PL011 UART driver
578 21:01:30.634587 <6>[ 0.375450] iommu: Default domain type: Translated
579 21:01:30.642810 <6>[ 0.380799] iommu: DMA domain TLB invalidation policy: strict mode
580 21:01:30.670743 <5>[ 0.410866] SCSI subsystem initialized
581 21:01:30.676494 <6>[ 0.415752] usbcore: registered new interface driver usbfs
582 21:01:30.682278 <6>[ 0.421813] usbcore: registered new interface driver hub
583 21:01:30.689125 <6>[ 0.427594] usbcore: registered new device driver usb
584 21:01:30.694837 <6>[ 0.434103] pps_core: LinuxPPS API ver. 1 registered
585 21:01:30.706325 <6>[ 0.439542] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
586 21:01:30.712680 <6>[ 0.449230] PTP clock support registered
587 21:01:30.713192 <6>[ 0.453692] EDAC MC: Ver: 3.0.0
588 21:01:30.762429 <6>[ 0.500615] scmi_core: SCMI protocol bus registered
589 21:01:30.777441 <6>[ 0.517957] vgaarb: loaded
590 21:01:30.790012 <6>[ 0.530973] clocksource: Switched to clocksource dmtimer
591 21:01:30.817491 <6>[ 0.557978] NET: Registered PF_INET protocol family
592 21:01:30.830090 <6>[ 0.563691] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
593 21:01:30.837100 <6>[ 0.572524] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
594 21:01:30.848559 <6>[ 0.581452] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
595 21:01:30.854327 <6>[ 0.589693] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
596 21:01:30.860218 <6>[ 0.597978] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
597 21:01:30.866133 <6>[ 0.605699] TCP: Hash tables configured (established 4096 bind 4096)
598 21:01:30.877421 <6>[ 0.612620] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
599 21:01:30.883521 <6>[ 0.619629] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
600 21:01:30.888682 <6>[ 0.627250] NET: Registered PF_UNIX/PF_LOCAL protocol family
601 21:01:30.975601 <6>[ 0.710871] RPC: Registered named UNIX socket transport module.
602 21:01:30.976164 <6>[ 0.717306] RPC: Registered udp transport module.
603 21:01:30.981332 <6>[ 0.722431] RPC: Registered tcp transport module.
604 21:01:30.989930 <6>[ 0.727535] RPC: Registered tcp-with-tls transport module.
605 21:01:30.995654 <6>[ 0.733464] RPC: Registered tcp NFSv4.1 backchannel transport module.
606 21:01:31.002984 <6>[ 0.740373] PCI: CLS 0 bytes, default 64
607 21:01:31.004273 <5>[ 0.746179] Initialise system trusted keyrings
608 21:01:31.028316 <6>[ 0.766254] Trying to unpack rootfs image as initramfs...
609 21:01:31.106705 <6>[ 0.841190] workingset: timestamp_bits=30 max_order=17 bucket_order=0
610 21:01:31.111348 <6>[ 0.848705] squashfs: version 4.0 (2009/01/31) Phillip Lougher
611 21:01:31.150490 <5>[ 0.891349] NFS: Registering the id_resolver key type
612 21:01:31.156276 <5>[ 0.896933] Key type id_resolver registered
613 21:01:31.162107 <5>[ 0.901585] Key type id_legacy registered
614 21:01:31.170411 <6>[ 0.906021] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
615 21:01:31.177432 <6>[ 0.913213] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
616 21:01:31.246312 <5>[ 0.987070] Key type asymmetric registered
617 21:01:31.252041 <5>[ 0.991658] Asymmetric key parser 'x509' registered
618 21:01:31.263554 <6>[ 0.997086] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
619 21:01:31.264059 <6>[ 1.005003] io scheduler mq-deadline registered
620 21:01:31.269350 <6>[ 1.009932] io scheduler kyber registered
621 21:01:31.274893 <6>[ 1.014415] io scheduler bfq registered
622 21:01:31.382242 <6>[ 1.119495] ledtrig-cpu: registered to indicate activity on CPUs
623 21:01:31.671946 <6>[ 1.409887] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
624 21:01:31.705736 <6>[ 1.446223] msm_serial: driver initialized
625 21:01:31.711544 <6>[ 1.451215] SuperH (H)SCI(F) driver initialized
626 21:01:31.717489 <6>[ 1.456372] STMicroelectronics ASC driver initialized
627 21:01:31.722653 <6>[ 1.462039] STM32 USART driver initialized
628 21:01:31.875299 <6>[ 1.615326] brd: module loaded
629 21:01:31.904332 <6>[ 1.644351] loop: module loaded
630 21:01:31.938375 <6>[ 1.678253] CAN device driver interface
631 21:01:31.944649 <6>[ 1.683438] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
632 21:01:31.950508 <6>[ 1.690340] e1000e: Intel(R) PRO/1000 Network Driver
633 21:01:31.957248 <6>[ 1.695790] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
634 21:01:31.963124 <6>[ 1.702225] igb: Intel(R) Gigabit Ethernet Network Driver
635 21:01:31.970004 <6>[ 1.708050] igb: Copyright (c) 2007-2014 Intel Corporation.
636 21:01:31.982049 <6>[ 1.717222] pegasus: Pegasus/Pegasus II USB Ethernet driver
637 21:01:31.987756 <6>[ 1.723378] usbcore: registered new interface driver pegasus
638 21:01:31.993673 <6>[ 1.729503] usbcore: registered new interface driver asix
639 21:01:31.999404 <6>[ 1.735398] usbcore: registered new interface driver ax88179_178a
640 21:01:32.005178 <6>[ 1.741987] usbcore: registered new interface driver cdc_ether
641 21:01:32.010970 <6>[ 1.748286] usbcore: registered new interface driver smsc75xx
642 21:01:32.016670 <6>[ 1.754519] usbcore: registered new interface driver smsc95xx
643 21:01:32.022498 <6>[ 1.760727] usbcore: registered new interface driver net1080
644 21:01:32.028306 <6>[ 1.766877] usbcore: registered new interface driver cdc_subset
645 21:01:32.034070 <6>[ 1.773285] usbcore: registered new interface driver zaurus
646 21:01:32.041656 <6>[ 1.779327] usbcore: registered new interface driver cdc_ncm
647 21:01:32.051442 <6>[ 1.788733] usbcore: registered new interface driver usb-storage
648 21:01:32.334730 <6>[ 2.073782] i2c_dev: i2c /dev entries driver
649 21:01:32.394416 <5>[ 2.127413] cpuidle: enable-method property 'ti,am3352' found operations
650 21:01:32.400279 <6>[ 2.136971] sdhci: Secure Digital Host Controller Interface driver
651 21:01:32.407587 <6>[ 2.143744] sdhci: Copyright(c) Pierre Ossman
652 21:01:32.414832 <6>[ 2.150061] Synopsys Designware Multimedia Card Interface Driver
653 21:01:32.420223 <6>[ 2.157963] sdhci-pltfm: SDHCI platform and OF driver helper
654 21:01:32.542437 <6>[ 2.275868] usbcore: registered new interface driver usbhid
655 21:01:32.542838 <6>[ 2.282047] usbhid: USB HID core driver
656 21:01:32.578177 <6>[ 2.317518] NET: Registered PF_INET6 protocol family
657 21:01:32.631132 <6>[ 2.372057] Segment Routing with IPv6
658 21:01:32.636820 <6>[ 2.376208] In-situ OAM (IOAM) with IPv6
659 21:01:32.643723 <6>[ 2.380612] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
660 21:01:32.649498 <6>[ 2.387983] NET: Registered PF_PACKET protocol family
661 21:01:32.655263 <6>[ 2.393549] can: controller area network core
662 21:01:32.660972 <6>[ 2.398382] NET: Registered PF_CAN protocol family
663 21:01:32.661260 <6>[ 2.403612] can: raw protocol
664 21:01:32.666912 <6>[ 2.406939] can: broadcast manager protocol
665 21:01:32.673283 <6>[ 2.411535] can: netlink gateway - max_hops=1
666 21:01:32.679510 <5>[ 2.417039] Key type dns_resolver registered
667 21:01:32.685804 <6>[ 2.422119] ThumbEE CPU extension supported.
668 21:01:32.686297 <5>[ 2.426806] Registering SWP/SWPB emulation handler
669 21:01:32.695530 <3>[ 2.432508] omap_voltage_late_init: Voltage driver support not added
670 21:01:32.882501 <5>[ 2.621723] Loading compiled-in X.509 certificates
671 21:01:33.026773 <6>[ 2.754703] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
672 21:01:33.033917 <6>[ 2.771482] pinctrl-single 44e10800.pinmux: 142 pins, size 568
673 21:01:33.059956 <3>[ 2.795317] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
674 21:01:33.267231 <3>[ 3.001878] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
675 21:01:33.462779 <6>[ 3.201725] OMAP GPIO hardware version 0.1
676 21:01:33.482524 <6>[ 3.220452] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
677 21:01:33.566529 <4>[ 3.303397] at24 2-0054: supply vcc not found, using dummy regulator
678 21:01:33.604312 <4>[ 3.341913] at24 2-0055: supply vcc not found, using dummy regulator
679 21:01:33.639967 <4>[ 3.376850] at24 2-0056: supply vcc not found, using dummy regulator
680 21:01:33.680769 <4>[ 3.417687] at24 2-0057: supply vcc not found, using dummy regulator
681 21:01:33.718269 <6>[ 3.455924] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
682 21:01:33.793530 <3>[ 3.527097] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
683 21:01:33.818123 <6>[ 3.548041] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
684 21:01:33.840207 <4>[ 3.574341] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
685 21:01:33.847063 <4>[ 3.583538] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
686 21:01:33.954936 <6>[ 3.692019] omap_rng 48310000.rng: Random Number Generator ver. 20
687 21:01:33.977638 <5>[ 3.718386] random: crng init done
688 21:01:34.026050 <6>[ 3.761648] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
689 21:01:34.053885 <6>[ 3.792933] Freeing initrd memory: 14444K
690 21:01:34.108763 <6>[ 3.843424] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
691 21:01:34.114606 <6>[ 3.853749] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
692 21:01:34.122870 <6>[ 3.861090] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
693 21:01:34.134320 <6>[ 3.868536] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
694 21:01:34.142714 <6>[ 3.876676] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
695 21:01:34.155843 <6>[ 3.888318] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
696 21:01:34.164240 <5>[ 3.897345] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
697 21:01:34.191981 <3>[ 3.927218] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
698 21:01:34.197731 <6>[ 3.935816] edma 49000000.dma: TI EDMA DMA engine driver
699 21:01:34.269517 <3>[ 4.004072] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
700 21:01:34.284263 <6>[ 4.018485] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
701 21:01:34.297213 <3>[ 4.035625] l3-aon-clkctrl:0000:0: failed to disable
702 21:01:34.346853 <6>[ 4.082112] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
703 21:01:34.352509 <6>[ 4.091587] printk: legacy console [ttyS0] enabled
704 21:01:34.358220 <6>[ 4.091587] printk: legacy console [ttyS0] enabled
705 21:01:34.363868 <6>[ 4.101919] printk: legacy bootconsole [omap8250] disabled
706 21:01:34.369722 <6>[ 4.101919] printk: legacy bootconsole [omap8250] disabled
707 21:01:34.407581 <4>[ 4.141733] tps65217-pmic: Failed to locate of_node [id: -1]
708 21:01:34.411066 <4>[ 4.149120] tps65217-bl: Failed to locate of_node [id: -1]
709 21:01:34.427677 <6>[ 4.168858] tps65217 0-0024: TPS65217 ID 0xe version 1.2
710 21:01:34.447943 <6>[ 4.175827] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
711 21:01:34.459700 <6>[ 4.189513] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
712 21:01:34.462404 <6>[ 4.201396] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
713 21:01:34.485540 <6>[ 4.221229] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
714 21:01:34.491435 <6>[ 4.230285] sdhci-omap 48060000.mmc: Got CD GPIO
715 21:01:34.499463 <4>[ 4.235463] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
716 21:01:34.514012 <4>[ 4.248959] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
717 21:01:34.520408 <4>[ 4.257594] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
718 21:01:34.530272 <4>[ 4.266252] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
719 21:01:34.654563 <6>[ 4.390447] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
720 21:01:34.693962 <6>[ 4.426682] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
721 21:01:34.700501 <6>[ 4.437553] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
722 21:01:34.709422 <6>[ 4.446500] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
723 21:01:34.776547 <6>[ 4.508229] mmc1: new high speed MMC card at address 0001
724 21:01:34.777128 <6>[ 4.515521] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
725 21:01:34.790207 <6>[ 4.524211] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
726 21:01:34.798052 <6>[ 4.536657] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
727 21:01:34.806404 <6>[ 4.545004] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
728 21:01:34.816322 <6>[ 4.553645] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
729 21:01:34.837654 <6>[ 4.569723] mmc0: new high speed SDHC card at address aaaa
730 21:01:34.838230 <6>[ 4.576782] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
731 21:01:34.868163 <6>[ 4.607125] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
732 21:01:36.946736 <6>[ 6.682031] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
733 21:01:37.060148 <5>[ 6.721065] Sending DHCP requests ., OK
734 21:01:37.071471 <6>[ 6.805539] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.8
735 21:01:37.072028 <6>[ 6.813620] IP-Config: Complete:
736 21:01:37.082805 <6>[ 6.817158] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.6.8, mask=255.255.255.0, gw=192.168.6.1
737 21:01:37.088478 <6>[ 6.827591] host=192.168.6.8, domain=, nis-domain=(none)
738 21:01:37.094234 <6>[ 6.833727] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
739 21:01:37.100851 <6>[ 6.833761] nameserver0=10.255.253.1
740 21:01:37.107002 <6>[ 6.846392] clk: Disabling unused clocks
741 21:01:37.112479 <6>[ 6.851121] PM: genpd: Disabling unused power domains
742 21:01:37.132085 <6>[ 6.869740] Freeing unused kernel image (initmem) memory: 2048K
743 21:01:37.139499 <6>[ 6.879480] Run /init as init process
744 21:01:37.164629 Loading, please wait...
745 21:01:37.240175 Starting systemd-udevd version 252.22-1~deb12u1
746 21:01:40.691981 <4>[ 10.424736] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
747 21:01:40.697513 <6>[ 10.437896] tda998x 0-0070: found TDA19988
748 21:01:40.900453 <4>[ 10.634040] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
749 21:01:41.039580 <6>[ 10.780812] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
750 21:01:41.049850 <6>[ 10.786742] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
751 21:01:41.383445 <6>[ 11.123175] hub 1-0:1.0: USB hub found
752 21:01:41.410218 <6>[ 11.149671] hub 1-0:1.0: 1 port detected
753 21:01:44.084666 Begin: Loading essential drivers ... done.
754 21:01:44.090187 Begin: Running /scripts/init-premount ... done.
755 21:01:44.095874 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
756 21:01:44.109712 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
757 21:01:44.110541 Device /sys/class/net/eth0 found
758 21:01:44.110750 done.
759 21:01:44.170435 Begin: Waiting up to 180 secs for any network device to become available ... done.
760 21:01:44.252965 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
761 21:01:44.377900 IP-Config: eth0 guessed broadcast address 192.168.6.255
762 21:01:44.383432 IP-Config: eth0 complete (dhcp from 192.168.6.1):
763 21:01:44.389041 address: 192.168.6.8 broadcast: 192.168.6.255 netmask: 255.255.255.0
764 21:01:44.400189 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
765 21:01:44.400699 rootserver: 192.168.6.1 rootpath:
766 21:01:44.403631 filename :
767 21:01:44.495570 done.
768 21:01:44.516250 Begin: Running /scripts/nfs-bottom ... done.
769 21:01:44.593164 Begin: Running /scripts/init-bottom ... done.
770 21:01:46.186299 <30>[ 15.923375] systemd[1]: System time before build time, advancing clock.
771 21:01:46.365137 <30>[ 16.076004] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
772 21:01:46.374603 <30>[ 16.113606] systemd[1]: Detected architecture arm.
773 21:01:46.387125
774 21:01:46.387641 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
775 21:01:46.388062
776 21:01:46.412762 <30>[ 16.150528] systemd[1]: Hostname set to <debian-bookworm-armhf>.
777 21:01:48.581866 <30>[ 18.318346] systemd[1]: Queued start job for default target graphical.target.
778 21:01:48.599007 <30>[ 18.333405] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
779 21:01:48.605635 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
780 21:01:48.631435 <30>[ 18.367293] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
781 21:01:48.643618 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
782 21:01:48.667648 <30>[ 18.403356] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
783 21:01:48.678883 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
784 21:01:48.698402 <30>[ 18.433190] systemd[1]: Created slice user.slice - User and Session Slice.
785 21:01:48.704158 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
786 21:01:48.730047 <30>[ 18.463661] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
787 21:01:48.743774 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
788 21:01:48.767837 <30>[ 18.501921] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
789 21:01:48.778863 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
790 21:01:48.805659 <30>[ 18.532065] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
791 21:01:48.819263 <30>[ 18.554172] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
792 21:01:48.823852 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
793 21:01:48.846177 <30>[ 18.581516] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
794 21:01:48.854483 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
795 21:01:48.876863 <30>[ 18.611896] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
796 21:01:48.885305 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
797 21:01:48.906721 <30>[ 18.641964] systemd[1]: Reached target paths.target - Path Units.
798 21:01:48.911857 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
799 21:01:48.936418 <30>[ 18.671669] systemd[1]: Reached target remote-fs.target - Remote File Systems.
800 21:01:48.942977 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
801 21:01:48.966247 <30>[ 18.701554] systemd[1]: Reached target slices.target - Slice Units.
802 21:01:48.971866 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
803 21:01:48.996433 <30>[ 18.731716] systemd[1]: Reached target swap.target - Swaps.
804 21:01:48.999571 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
805 21:01:49.026826 <30>[ 18.761749] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
806 21:01:49.035101 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
807 21:01:49.057765 <30>[ 18.792671] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
808 21:01:49.066029 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
809 21:01:49.144741 <30>[ 18.875810] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
810 21:01:49.158404 <30>[ 18.893496] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
811 21:01:49.167008 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
812 21:01:49.189587 <30>[ 18.923768] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
813 21:01:49.196966 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
814 21:01:49.219062 <30>[ 18.954066] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
815 21:01:49.227297 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
816 21:01:49.249561 <30>[ 18.986046] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
817 21:01:49.260901 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
818 21:01:49.288943 <30>[ 19.022682] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
819 21:01:49.296473 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
820 21:01:49.323705 <30>[ 19.052750] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
821 21:01:49.342315 <30>[ 19.071330] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
822 21:01:49.390273 <30>[ 19.126177] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
823 21:01:49.416510 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
824 21:01:49.466079 <30>[ 19.201748] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
825 21:01:49.480952 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
826 21:01:49.528084 <30>[ 19.262920] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
827 21:01:49.545252 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
828 21:01:49.591600 <30>[ 19.327057] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
829 21:01:49.624473 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
830 21:01:49.678057 <30>[ 19.414650] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
831 21:01:49.706545 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
832 21:01:49.756466 <30>[ 19.493724] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
833 21:01:49.782977 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
834 21:01:49.838349 <30>[ 19.574310] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
835 21:01:49.875279 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
836 21:01:49.926310 <30>[ 19.662541] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
837 21:01:49.942900 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
838 21:01:49.966184 <30>[ 19.702472] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
839 21:01:49.992022 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
840 21:01:50.022413 <28>[ 19.753438] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
841 21:01:50.036704 <28>[ 19.772926] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
842 21:01:50.086645 <30>[ 19.822101] systemd[1]: Starting systemd-journald.service - Journal Service...
843 21:01:50.093172 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
844 21:01:50.158128 <30>[ 19.894040] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
845 21:01:50.184464 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
846 21:01:50.238001 <30>[ 19.973970] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
847 21:01:50.282380 Starting [0;1;39msystemd-network-g… units from Kernel command line...
848 21:01:50.339716 <30>[ 20.074328] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
849 21:01:50.395863 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
850 21:01:50.469878 <30>[ 20.205917] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
851 21:01:50.528750 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
852 21:01:50.607403 <30>[ 20.343637] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
853 21:01:50.656221 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
854 21:01:50.677710 <30>[ 20.413877] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
855 21:01:50.711656 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
856 21:01:50.741681 <30>[ 20.477661] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
857 21:01:50.796004 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
858 21:01:50.908389 <30>[ 20.645301] systemd[1]: modprobe@configfs.service: Deactivated successfully.
859 21:01:50.937184 <30>[ 20.672821] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
860 21:01:50.966071 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
861 21:01:50.995954 <30>[ 20.730876] systemd[1]: Started systemd-journald.service - Journal Service.
862 21:01:51.002995 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
863 21:01:51.047999 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
864 21:01:51.077321 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
865 21:01:51.107637 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
866 21:01:51.132133 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
867 21:01:51.169561 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
868 21:01:51.197974 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
869 21:01:51.228601 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
870 21:01:51.249517 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
871 21:01:51.280507 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
872 21:01:51.348148 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
873 21:01:51.418016 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
874 21:01:51.507412 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
875 21:01:51.585957 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
876 21:01:51.676795 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
877 21:01:51.740483 <46>[ 21.476571] systemd-journald[164]: Received client request to flush runtime journal.
878 21:01:51.808647 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
879 21:01:51.978695 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
880 21:01:52.767834 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
881 21:01:53.078108 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
882 21:01:53.138408 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
883 21:01:53.473159 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
884 21:01:53.680749 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
885 21:01:53.708750 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
886 21:01:53.740635 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
887 21:01:53.835114 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
888 21:01:53.865924 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
889 21:01:54.743986 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
890 21:01:54.808294 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
891 21:01:55.359128 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
892 21:01:55.478528 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
893 21:01:55.566268 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
894 21:01:57.416532 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
895 21:01:57.686812 <5>[ 27.423345] cfg80211: Loading compiled-in X.509 certificates for regulatory database
896 21:01:57.814547 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
897 21:01:58.399197 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
898 21:01:58.687321 <5>[ 28.425667] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
899 21:01:58.748551 <5>[ 28.482975] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
900 21:01:58.754311 <4>[ 28.492301] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
901 21:01:58.762050 <6>[ 28.501402] cfg80211: failed to load regulatory.db
902 21:01:59.991488 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
903 21:02:00.332418 <46>[ 30.058808] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
904 21:02:00.388026 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - N<46>[ 30.115046] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
905 21:02:00.391885 etwork Time Synchronization.
906 21:02:09.445939 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
907 21:02:09.472428 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
908 21:02:09.497990 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
909 21:02:09.517449 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
910 21:02:09.576189 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
911 21:02:09.617112 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
912 21:02:09.668221 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
913 21:02:09.755501 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
914 21:02:09.800846 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
915 21:02:09.836884 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
916 21:02:09.861767 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
917 21:02:09.891507 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
918 21:02:09.932831 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
919 21:02:09.963803 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
920 21:02:09.998950 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
921 21:02:10.028316 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
922 21:02:10.068815 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
923 21:02:10.106620 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
924 21:02:10.127564 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
925 21:02:10.146898 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
926 21:02:10.176436 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
927 21:02:10.196499 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
928 21:02:10.223291 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
929 21:02:10.296957 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
930 21:02:10.354662 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
931 21:02:10.462567 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
932 21:02:10.541299 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
933 21:02:10.584460 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
934 21:02:10.617103 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
935 21:02:10.645958 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
936 21:02:10.842706 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
937 21:02:10.896238 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
938 21:02:10.965391 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
939 21:02:10.975401 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
940 21:02:10.994406 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
941 21:02:11.265704 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
942 21:02:11.614474 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
943 21:02:11.658104 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
944 21:02:11.680344 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
945 21:02:11.760824 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
946 21:02:11.924877 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
947 21:02:12.059056
948 21:02:12.062513 Debian GNU/Linux 12 dworm-armhf login: root (automatic login)
949 21:02:12.062825
950 21:02:12.371166 Linux debian-bookworm-armhf 6.12.0-rc2 #1 SMP Tue Nov 5 20:23:39 UTC 2024 armv7l
951 21:02:12.371823
952 21:02:12.376774 The programs included with the Debian GNU/Linux system are free software;
953 21:02:12.382329 the exact distribution terms for each program are described in the
954 21:02:12.388004 individual files in /usr/share/doc/*/copyright.
955 21:02:12.388577
956 21:02:12.395073 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
957 21:02:12.395651 permitted by applicable law.
958 21:02:17.432334 Unable to match end of the kernel message
960 21:02:17.433639 Setting prompt string to ['/ #']
961 21:02:17.434000 end: 2.4.4.1 login-action (duration 00:00:48) [common]
963 21:02:17.434747 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
964 21:02:17.435053 start: 2.4.5 expect-shell-connection (timeout 00:03:12) [common]
965 21:02:17.435286 Setting prompt string to ['/ #']
966 21:02:17.435488 Forcing a shell prompt, looking for ['/ #']
968 21:02:17.486077 / #
969 21:02:17.486568 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
970 21:02:17.486826 Waiting using forced prompt support (timeout 00:02:30)
971 21:02:17.490419
972 21:02:17.500607 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
973 21:02:17.501051 start: 2.4.6 export-device-env (timeout 00:03:12) [common]
974 21:02:17.501350 Sending with 10 millisecond of delay
976 21:02:22.492552 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/942676/extract-nfsrootfs-ao5id5gi'
977 21:02:22.503999 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/942676/extract-nfsrootfs-ao5id5gi'
978 21:02:22.505060 Sending with 10 millisecond of delay
980 21:02:24.604155 / # export NFS_SERVER_IP='192.168.6.3'
981 21:02:24.614817 export NFS_SERVER_IP='192.168.6.3'
982 21:02:24.616257 end: 2.4.6 export-device-env (duration 00:00:07) [common]
983 21:02:24.617579 end: 2.4 uboot-commands (duration 00:01:55) [common]
984 21:02:24.619048 end: 2 uboot-action (duration 00:01:55) [common]
985 21:02:24.620344 start: 3 lava-test-retry (timeout 00:06:55) [common]
986 21:02:24.620877 start: 3.1 lava-test-shell (timeout 00:06:55) [common]
987 21:02:24.621119 Using namespace: common
989 21:02:24.723572 / # #
990 21:02:24.724060 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
991 21:02:24.728242 #
992 21:02:24.734230 Using /lava-942676
994 21:02:24.835368 / # export SHELL=/bin/bash
995 21:02:24.840312 export SHELL=/bin/bash
997 21:02:24.950559 / # . /lava-942676/environment
998 21:02:24.955115 . /lava-942676/environment
1000 21:02:25.068523 / # /lava-942676/bin/lava-test-runner /lava-942676/0
1001 21:02:25.069229 Test shell timeout: 10s (minimum of the action and connection timeout)
1002 21:02:25.072697 /lava-942676/bin/lava-test-runner /lava-942676/0
1003 21:02:25.466590 + export TESTRUN_ID=0_timesync-off
1004 21:02:25.474522 + TESTRUN_ID=0_timesync-off
1005 21:02:25.474857 + cd /lava-942676/0/tests/0_timesync-off
1006 21:02:25.475127 ++ cat uuid
1007 21:02:25.490758 + UUID=942676_1.6.2.4.1
1008 21:02:25.491167 + set +x
1009 21:02:25.499396 <LAVA_SIGNAL_STARTRUN 0_timesync-off 942676_1.6.2.4.1>
1010 21:02:25.499800 + systemctl stop systemd-timesyncd
1011 21:02:25.500331 Received signal: <STARTRUN> 0_timesync-off 942676_1.6.2.4.1
1012 21:02:25.500638 Starting test lava.0_timesync-off (942676_1.6.2.4.1)
1013 21:02:25.500989 Skipping test definition patterns.
1014 21:02:25.793909 + set +x
1015 21:02:25.794333 <LAVA_SIGNAL_ENDRUN 0_timesync-off 942676_1.6.2.4.1>
1016 21:02:25.794793 Received signal: <ENDRUN> 0_timesync-off 942676_1.6.2.4.1
1017 21:02:25.795098 Ending use of test pattern.
1018 21:02:25.795320 Ending test lava.0_timesync-off (942676_1.6.2.4.1), duration 0.29
1020 21:02:25.983715 + export TESTRUN_ID=1_kselftest-dt
1021 21:02:25.984148 + TESTRUN_ID=1_kselftest-dt
1022 21:02:25.984366 + cd /lava-942676/0/tests/1_kselftest-dt
1023 21:02:25.984574 ++ cat uuid
1024 21:02:25.984999 + UUID=942676_1.6.2.4.5
1025 21:02:25.985494 + set +x
1026 21:02:25.988169 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 942676_1.6.2.4.5>
1027 21:02:25.989144 + cd ./automated/linux/kselftest/
1028 21:02:25.990705 Received signal: <STARTRUN> 1_kselftest-dt 942676_1.6.2.4.5
1029 21:02:25.991308 Starting test lava.1_kselftest-dt (942676_1.6.2.4.5)
1030 21:02:25.991896 Skipping test definition patterns.
1031 21:02:26.035563 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-228-ga18dadd1209ac/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1032 21:02:26.148029 INFO: install_deps skipped
1033 21:02:26.698710 --2024-11-05 21:02:26-- http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-228-ga18dadd1209ac/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1034 21:02:26.965793 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1035 21:02:27.107916 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1036 21:02:27.249050 HTTP request sent, awaiting response... 200 OK
1037 21:02:27.249649 Length: 4098196 (3.9M) [application/octet-stream]
1038 21:02:27.254503 Saving to: 'kselftest_armhf.tar.gz'
1039 21:02:27.255040
1040 21:02:29.078895
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 179KB/s
kselftest_armhf.tar 4%[ ] 194.76K 347KB/s
kselftest_armhf.tar 16%[==> ] 671.92K 807KB/s
kselftest_armhf.tar 23%[===> ] 947.54K 889KB/s
kselftest_armhf.tar 50%[=========> ] 1.96M 1.43MB/s
kselftest_armhf.tar 79%[==============> ] 3.10M 1.95MB/s
kselftest_armhf.tar 95%[==================> ] 3.74M 2.09MB/s
kselftest_armhf.tar 100%[===================>] 3.91M 2.14MB/s in 1.8s
1041 21:02:29.079625
1042 21:02:29.622406 2024-11-05 21:02:29 (2.14 MB/s) - 'kselftest_armhf.tar.gz' saved [4098196/4098196]
1043 21:02:29.623033
1044 21:02:44.464543 skiplist:
1045 21:02:44.465173 ========================================
1046 21:02:44.482643 ========================================
1047 21:02:44.575101 dt:test_unprobed_devices.sh
1048 21:02:44.611023 ============== Tests to run ===============
1049 21:02:44.619347 dt:test_unprobed_devices.sh
1050 21:02:44.623156 ===========End Tests to run ===============
1051 21:02:44.632426 shardfile-dt pass
1052 21:02:44.881349 <12>[ 74.622411] kselftest: Running tests in dt
1053 21:02:44.908929 TAP version 13
1054 21:02:44.932329 1..1
1055 21:02:44.985281 # timeout set to 45
1056 21:02:44.985863 # selftests: dt: test_unprobed_devices.sh
1057 21:02:45.827353 # TAP version 13
1058 21:03:10.835780 # 1..257
1059 21:03:11.008836 # ok 1 / # SKIP
1060 21:03:11.032388 # ok 2 /clk_mcasp0
1061 21:03:11.103614 # ok 3 /clk_mcasp0_fixed # SKIP
1062 21:03:11.176562 # ok 4 /cpus/cpu@0 # SKIP
1063 21:03:11.244548 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1064 21:03:11.264899 # ok 6 /fixedregulator0
1065 21:03:11.289947 # ok 7 /leds
1066 21:03:11.306172 # ok 8 /ocp
1067 21:03:11.334626 # ok 9 /ocp/interconnect@44c00000
1068 21:03:11.352777 # ok 10 /ocp/interconnect@44c00000/segment@0
1069 21:03:11.376491 # ok 11 /ocp/interconnect@44c00000/segment@100000
1070 21:03:11.400902 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1071 21:03:11.472042 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1072 21:03:11.496582 # ok 14 /ocp/interconnect@44c00000/segment@200000
1073 21:03:11.522157 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1074 21:03:11.620692 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1075 21:03:11.693947 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1076 21:03:11.765983 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1077 21:03:11.837136 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1078 21:03:11.908629 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1079 21:03:11.979965 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1080 21:03:12.051733 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1081 21:03:12.122654 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1082 21:03:12.195594 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1083 21:03:12.267003 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1084 21:03:12.338219 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1085 21:03:12.411148 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1086 21:03:12.485605 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1087 21:03:12.557281 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1088 21:03:12.628528 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1089 21:03:12.701101 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1090 21:03:12.778289 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1091 21:03:12.845724 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1092 21:03:12.916438 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1093 21:03:12.988662 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1094 21:03:13.059457 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1095 21:03:13.131718 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1096 21:03:13.204450 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1097 21:03:13.279741 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1098 21:03:13.351074 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1099 21:03:13.422833 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1100 21:03:13.493846 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1101 21:03:13.562667 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1102 21:03:13.635334 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1103 21:03:13.706700 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1104 21:03:13.778384 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1105 21:03:13.850186 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1106 21:03:13.921953 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1107 21:03:13.994411 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1108 21:03:14.069037 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1109 21:03:14.142731 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1110 21:03:14.213854 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1111 21:03:14.282390 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1112 21:03:14.358796 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1113 21:03:14.427343 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1114 21:03:14.500280 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1115 21:03:14.571769 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1116 21:03:14.644522 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1117 21:03:14.714792 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1118 21:03:14.788097 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1119 21:03:14.858960 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1120 21:03:14.931376 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1121 21:03:15.004773 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1122 21:03:15.080291 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1123 21:03:15.152820 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1124 21:03:15.221729 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1125 21:03:15.296720 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1126 21:03:15.370098 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1127 21:03:15.437737 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1128 21:03:15.513378 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1129 21:03:15.585263 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1130 21:03:15.661626 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1131 21:03:15.733928 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1132 21:03:15.801758 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1133 21:03:15.879855 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1134 21:03:15.947485 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1135 21:03:16.019666 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1136 21:03:16.090691 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1137 21:03:16.162406 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1138 21:03:16.237343 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1139 21:03:16.306444 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1140 21:03:16.377918 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1141 21:03:16.449424 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1142 21:03:16.521010 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1143 21:03:16.597640 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1144 21:03:16.671339 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1145 21:03:16.742917 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1146 21:03:16.811172 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1147 21:03:16.886380 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1148 21:03:16.963632 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1149 21:03:17.032808 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1150 21:03:17.102606 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1151 21:03:17.174245 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1152 21:03:17.246177 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1153 21:03:17.267438 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1154 21:03:17.291007 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1155 21:03:17.318934 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1156 21:03:17.343127 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1157 21:03:17.359896 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1158 21:03:17.391465 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1159 21:03:17.416453 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1160 21:03:17.434549 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1161 21:03:17.542394 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1162 21:03:17.567127 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1163 21:03:17.592511 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1164 21:03:17.618721 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1165 21:03:17.722107 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1166 21:03:17.798930 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1167 21:03:17.868381 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1168 21:03:17.941597 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1169 21:03:18.014171 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1170 21:03:18.086587 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1171 21:03:18.158424 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1172 21:03:18.231219 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1173 21:03:18.303945 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1174 21:03:18.377915 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1175 21:03:18.450128 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1176 21:03:18.521199 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1177 21:03:18.593399 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1178 21:03:18.668605 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1179 21:03:18.741672 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1180 21:03:18.814728 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1181 21:03:18.840758 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1182 21:03:18.908260 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1183 21:03:18.978408 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1184 21:03:19.051998 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1185 21:03:19.074067 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1186 21:03:19.150489 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1187 21:03:19.170514 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1188 21:03:19.240226 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1189 21:03:19.263354 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1190 21:03:19.287462 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1191 21:03:19.314603 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1192 21:03:19.334271 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1193 21:03:19.357471 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1194 21:03:19.381747 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1195 21:03:19.407593 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1196 21:03:19.482070 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1197 21:03:19.508342 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1198 21:03:19.531643 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1199 21:03:19.600511 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1200 21:03:19.671968 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1201 21:03:19.693078 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1202 21:03:19.795029 # not ok 144 /ocp/interconnect@47c00000
1203 21:03:19.866629 # not ok 145 /ocp/interconnect@47c00000/segment@0
1204 21:03:19.888360 # ok 146 /ocp/interconnect@48000000
1205 21:03:19.915885 # ok 147 /ocp/interconnect@48000000/segment@0
1206 21:03:19.940295 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1207 21:03:19.962911 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1208 21:03:19.984471 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1209 21:03:20.006746 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1210 21:03:20.034495 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1211 21:03:20.059446 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1212 21:03:20.079268 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1213 21:03:20.166220 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1214 21:03:20.255651 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1215 21:03:20.278438 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1216 21:03:20.300820 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1217 21:03:20.320552 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1218 21:03:20.349476 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1219 21:03:20.370278 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1220 21:03:20.394843 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1221 21:03:20.415276 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1222 21:03:20.440864 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1223 21:03:20.462730 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1224 21:03:20.486660 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1225 21:03:20.509166 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1226 21:03:20.538044 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1227 21:03:20.560010 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1228 21:03:20.583828 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1229 21:03:20.604030 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1230 21:03:20.631070 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1231 21:03:20.655763 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1232 21:03:20.680970 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1233 21:03:20.697672 # ok 175 /ocp/interconnect@48000000/segment@100000
1234 21:03:20.723398 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1235 21:03:20.747790 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1236 21:03:20.822081 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1237 21:03:20.896076 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1238 21:03:20.971436 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1239 21:03:21.044183 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1240 21:03:21.111928 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1241 21:03:21.190789 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1242 21:03:21.261038 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1243 21:03:21.334192 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1244 21:03:21.356941 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1245 21:03:21.374017 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1246 21:03:21.398100 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1247 21:03:21.426543 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1248 21:03:21.450413 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1249 21:03:21.471072 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1250 21:03:21.492696 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1251 21:03:21.517615 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1252 21:03:21.544565 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1253 21:03:21.568572 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1254 21:03:21.590410 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1255 21:03:21.612977 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1256 21:03:21.633218 # ok 198 /ocp/interconnect@48000000/segment@200000
1257 21:03:21.657763 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1258 21:03:21.736474 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1259 21:03:21.756742 # ok 201 /ocp/interconnect@48000000/segment@300000
1260 21:03:21.780353 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1261 21:03:21.805777 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1262 21:03:21.831181 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1263 21:03:21.855503 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1264 21:03:21.879612 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1265 21:03:21.900408 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1266 21:03:21.971373 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1267 21:03:21.995093 # ok 209 /ocp/interconnect@4a000000
1268 21:03:22.018516 # ok 210 /ocp/interconnect@4a000000/segment@0
1269 21:03:22.041293 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1270 21:03:22.065477 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1271 21:03:22.090393 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1272 21:03:22.112639 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1273 21:03:22.183740 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1274 21:03:22.290497 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1275 21:03:22.363196 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1276 21:03:22.470685 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1277 21:03:22.541066 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1278 21:03:22.610069 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1279 21:03:22.714225 # not ok 221 /ocp/interconnect@4b140000
1280 21:03:22.786202 # not ok 222 /ocp/interconnect@4b140000/segment@0
1281 21:03:22.858152 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1282 21:03:22.874560 # ok 224 /ocp/target-module@40300000
1283 21:03:22.897727 # ok 225 /ocp/target-module@40300000/sram@0
1284 21:03:22.977128 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1285 21:03:23.049241 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1286 21:03:23.064239 # ok 228 /ocp/target-module@47400000
1287 21:03:23.089641 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1288 21:03:23.115793 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1289 21:03:23.134148 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1290 21:03:23.157535 # ok 232 /ocp/target-module@47400000/usb@1400
1291 21:03:23.184301 # ok 233 /ocp/target-module@47400000/usb@1800
1292 21:03:23.201533 # ok 234 /ocp/target-module@47810000
1293 21:03:23.227383 # ok 235 /ocp/target-module@49000000
1294 21:03:23.247879 # ok 236 /ocp/target-module@49000000/dma@0
1295 21:03:23.269424 # ok 237 /ocp/target-module@49800000
1296 21:03:23.292561 # ok 238 /ocp/target-module@49800000/dma@0
1297 21:03:23.316891 # ok 239 /ocp/target-module@49900000
1298 21:03:23.343725 # ok 240 /ocp/target-module@49900000/dma@0
1299 21:03:23.366894 # ok 241 /ocp/target-module@49a00000
1300 21:03:23.384600 # ok 242 /ocp/target-module@49a00000/dma@0
1301 21:03:23.407390 # ok 243 /ocp/target-module@4c000000
1302 21:03:23.484692 # not ok 244 /ocp/target-module@4c000000/emif@0
1303 21:03:23.507039 # ok 245 /ocp/target-module@50000000
1304 21:03:23.524453 # ok 246 /ocp/target-module@53100000
1305 21:03:23.602528 # not ok 247 /ocp/target-module@53100000/sham@0
1306 21:03:23.623845 # ok 248 /ocp/target-module@53500000
1307 21:03:23.692217 # not ok 249 /ocp/target-module@53500000/aes@0
1308 21:03:23.716679 # ok 250 /ocp/target-module@56000000
1309 21:03:23.824301 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1310 21:03:23.894378 # ok 252 /opp-table # SKIP
1311 21:03:23.965641 # ok 253 /soc # SKIP
1312 21:03:23.982968 # ok 254 /sound
1313 21:03:24.007146 # ok 255 /target-module@4b000000
1314 21:03:24.036187 # ok 256 /target-module@4b000000/target-module@140000
1315 21:03:24.054349 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1316 21:03:24.062093 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1317 21:03:24.070088 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1318 21:03:26.161362 dt_test_unprobed_devices_sh_ skip
1319 21:03:26.166920 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1320 21:03:26.172698 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1321 21:03:26.173233 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1322 21:03:26.178086 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1323 21:03:26.184202 dt_test_unprobed_devices_sh_fixedregulator0 pass
1324 21:03:26.189283 dt_test_unprobed_devices_sh_leds pass
1325 21:03:26.189856 dt_test_unprobed_devices_sh_ocp pass
1326 21:03:26.195104 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1327 21:03:26.200583 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1328 21:03:26.206315 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1329 21:03:26.217467 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1330 21:03:26.223060 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1331 21:03:26.228792 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1332 21:03:26.239899 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1333 21:03:26.245526 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1334 21:03:26.256828 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1335 21:03:26.267976 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1336 21:03:26.279281 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1337 21:03:26.284954 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1338 21:03:26.296019 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1339 21:03:26.307255 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1340 21:03:26.318464 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1341 21:03:26.329757 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1342 21:03:26.335304 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1343 21:03:26.346492 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1344 21:03:26.357909 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1345 21:03:26.368876 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1346 21:03:26.380055 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1347 21:03:26.385666 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1348 21:03:26.396833 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1349 21:03:26.407998 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1350 21:03:26.419178 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1351 21:03:26.424838 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1352 21:03:26.435980 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1353 21:03:26.447144 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1354 21:03:26.458362 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1355 21:03:26.469531 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1356 21:03:26.475166 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1357 21:03:26.486358 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1358 21:03:26.497574 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1359 21:03:26.508798 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1360 21:03:26.519948 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1361 21:03:26.531138 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1362 21:03:26.542365 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1363 21:03:26.553549 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1364 21:03:26.564675 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1365 21:03:26.575923 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1366 21:03:26.587185 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1367 21:03:26.598271 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1368 21:03:26.609470 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1369 21:03:26.620652 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1370 21:03:26.631855 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1371 21:03:26.643072 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1372 21:03:26.654227 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1373 21:03:26.665410 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1374 21:03:26.676643 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1375 21:03:26.687830 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1376 21:03:26.699052 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1377 21:03:26.710195 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1378 21:03:26.721443 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1379 21:03:26.732587 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1380 21:03:26.743791 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1381 21:03:26.755072 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1382 21:03:26.760608 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1383 21:03:26.771769 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1384 21:03:26.782976 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1385 21:03:26.794191 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1386 21:03:26.805341 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1387 21:03:26.816561 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1388 21:03:26.827746 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1389 21:03:26.839028 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1390 21:03:26.850231 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1391 21:03:26.861316 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1392 21:03:26.872660 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1393 21:03:26.883726 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1394 21:03:26.894833 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1395 21:03:26.906107 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1396 21:03:26.917237 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1397 21:03:26.928371 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1398 21:03:26.939555 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1399 21:03:26.950823 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1400 21:03:26.956390 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1401 21:03:26.967562 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1402 21:03:26.978740 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1403 21:03:26.990030 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1404 21:03:27.001202 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1405 21:03:27.006750 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1406 21:03:27.023946 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1407 21:03:27.034741 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1408 21:03:27.040328 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1409 21:03:27.057120 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1410 21:03:27.068285 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1411 21:03:27.079626 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1412 21:03:27.085088 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1413 21:03:27.096391 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1414 21:03:27.107498 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1415 21:03:27.113113 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1416 21:03:27.124286 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1417 21:03:27.135491 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1418 21:03:27.141041 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1419 21:03:27.152276 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1420 21:03:27.157960 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1421 21:03:27.169162 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1422 21:03:27.180406 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1423 21:03:27.191622 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1424 21:03:27.202679 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1425 21:03:27.213960 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1426 21:03:27.225213 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1427 21:03:27.236606 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1428 21:03:27.247535 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1429 21:03:27.258684 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1430 21:03:27.269990 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1431 21:03:27.281071 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1432 21:03:27.292352 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1433 21:03:27.309163 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1434 21:03:27.320272 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1435 21:03:27.331542 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1436 21:03:27.342742 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1437 21:03:27.353956 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1438 21:03:27.370567 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1439 21:03:27.381902 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1440 21:03:27.393081 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1441 21:03:27.404331 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1442 21:03:27.409935 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1443 21:03:27.421081 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1444 21:03:27.432452 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1445 21:03:27.437885 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1446 21:03:27.448933 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1447 21:03:27.454544 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1448 21:03:27.465735 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1449 21:03:27.471350 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1450 21:03:27.482511 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1451 21:03:27.488201 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1452 21:03:27.499280 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1453 21:03:27.504916 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1454 21:03:27.516161 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1455 21:03:27.527324 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1456 21:03:27.538505 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1457 21:03:27.549706 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1458 21:03:27.561034 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1459 21:03:27.566627 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1460 21:03:27.577733 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1461 21:03:27.583425 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1462 21:03:27.589035 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1463 21:03:27.594673 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1464 21:03:27.600208 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1465 21:03:27.605928 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1466 21:03:27.616920 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1467 21:03:27.622603 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1468 21:03:27.628207 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1469 21:03:27.639259 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1470 21:03:27.644968 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1471 21:03:27.656429 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1472 21:03:27.661754 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1473 21:03:27.672843 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1474 21:03:27.678513 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1475 21:03:27.689647 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1476 21:03:27.695254 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1477 21:03:27.706443 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1478 21:03:27.712043 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1479 21:03:27.723155 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1480 21:03:27.728860 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1481 21:03:27.739960 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1482 21:03:27.745602 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1483 21:03:27.751229 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1484 21:03:27.762347 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1485 21:03:27.767987 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1486 21:03:27.779184 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1487 21:03:27.784779 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1488 21:03:27.795964 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1489 21:03:27.801556 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1490 21:03:27.812707 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1491 21:03:27.818375 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1492 21:03:27.824004 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1493 21:03:27.835067 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1494 21:03:27.840651 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1495 21:03:27.851824 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1496 21:03:27.863073 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1497 21:03:27.874161 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1498 21:03:27.885314 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1499 21:03:27.896518 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1500 21:03:27.907738 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1501 21:03:27.918927 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1502 21:03:27.930104 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1503 21:03:27.935713 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1504 21:03:27.946889 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1505 21:03:27.952492 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1506 21:03:27.963665 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1507 21:03:27.969242 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1508 21:03:27.980473 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1509 21:03:27.986061 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1510 21:03:27.997258 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1511 21:03:28.002859 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1512 21:03:28.014067 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1513 21:03:28.019622 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1514 21:03:28.030796 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1515 21:03:28.036414 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1516 21:03:28.047619 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1517 21:03:28.053222 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1518 21:03:28.058803 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1519 21:03:28.070086 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1520 21:03:28.075592 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1521 21:03:28.086750 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1522 21:03:28.092390 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1523 21:03:28.103563 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1524 21:03:28.109149 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1525 21:03:28.120341 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1526 21:03:28.125989 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1527 21:03:28.131548 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1528 21:03:28.137114 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1529 21:03:28.148342 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1530 21:03:28.159520 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1531 21:03:28.165136 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1532 21:03:28.170734 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1533 21:03:28.181919 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1534 21:03:28.193180 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1535 21:03:28.204462 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1536 21:03:28.215630 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1537 21:03:28.221259 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1538 21:03:28.226914 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1539 21:03:28.232495 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1540 21:03:28.238164 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1541 21:03:28.243743 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1542 21:03:28.249333 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1543 21:03:28.260495 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1544 21:03:28.266333 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1545 21:03:28.271797 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1546 21:03:28.277379 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1547 21:03:28.282991 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1548 21:03:28.294241 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1549 21:03:28.299868 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1550 21:03:28.305472 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1551 21:03:28.311010 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1552 21:03:28.316657 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1553 21:03:28.322248 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1554 21:03:28.327848 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1555 21:03:28.333448 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1556 21:03:28.339067 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1557 21:03:28.344665 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1558 21:03:28.350394 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1559 21:03:28.355929 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1560 21:03:28.361535 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1561 21:03:28.367123 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1562 21:03:28.372744 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1563 21:03:28.378360 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1564 21:03:28.383990 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1565 21:03:28.389532 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1566 21:03:28.395145 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1567 21:03:28.400735 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1568 21:03:28.406383 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1569 21:03:28.406931 dt_test_unprobed_devices_sh_opp-table skip
1570 21:03:28.411958 dt_test_unprobed_devices_sh_soc skip
1571 21:03:28.417619 dt_test_unprobed_devices_sh_sound pass
1572 21:03:28.423173 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1573 21:03:28.428787 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1574 21:03:28.434354 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1575 21:03:28.439991 dt_test_unprobed_devices_sh fail
1576 21:03:28.440488 + ../../utils/send-to-lava.sh ./output/result.txt
1577 21:03:28.445569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1578 21:03:28.446539 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1580 21:03:28.454382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1581 21:03:28.455154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1583 21:03:28.548640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1584 21:03:28.549423 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1586 21:03:28.642423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1587 21:03:28.643274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1589 21:03:28.742708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1590 21:03:28.743593 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1592 21:03:28.844866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1593 21:03:28.846090 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1595 21:03:28.937688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1596 21:03:28.938841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1598 21:03:29.037338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1599 21:03:29.038460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1601 21:03:29.138069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1602 21:03:29.139438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1604 21:03:29.233954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1605 21:03:29.235326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1607 21:03:29.327962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1608 21:03:29.329060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1610 21:03:29.422119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1611 21:03:29.423211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1613 21:03:29.517101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1614 21:03:29.518369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1616 21:03:29.612394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1617 21:03:29.613714 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1619 21:03:29.712033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1620 21:03:29.712950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1622 21:03:29.814330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1623 21:03:29.815505 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1625 21:03:29.908167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1626 21:03:29.909342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1628 21:03:30.009755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1629 21:03:30.010742 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1631 21:03:30.110940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1632 21:03:30.111783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1634 21:03:30.212360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1635 21:03:30.213192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1637 21:03:30.314036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1638 21:03:30.314908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1640 21:03:30.416711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1641 21:03:30.417547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1643 21:03:30.516896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1644 21:03:30.517698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1646 21:03:30.618115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1647 21:03:30.618903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1649 21:03:30.710740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1650 21:03:30.711536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1652 21:03:30.803069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1653 21:03:30.803879 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1655 21:03:30.895681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1656 21:03:30.896596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1658 21:03:30.989748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1659 21:03:30.990676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1661 21:03:31.081843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1662 21:03:31.082509 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1664 21:03:31.175601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1665 21:03:31.176469 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1667 21:03:31.269021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1668 21:03:31.269903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1670 21:03:31.368779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1671 21:03:31.369632 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1673 21:03:31.462076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1674 21:03:31.462921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1676 21:03:31.564519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1677 21:03:31.565392 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1679 21:03:31.664443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1680 21:03:31.665276 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1682 21:03:31.765696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1683 21:03:31.766927 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1685 21:03:31.858562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1686 21:03:31.859402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1688 21:03:31.960118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1689 21:03:31.960968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1691 21:03:32.062316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1692 21:03:32.063177 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1694 21:03:32.164114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1695 21:03:32.165053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1697 21:03:32.265362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1698 21:03:32.266282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1700 21:03:32.365505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1701 21:03:32.366785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1703 21:03:32.467672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1704 21:03:32.468538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1706 21:03:32.569158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1707 21:03:32.570019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1709 21:03:32.669521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1710 21:03:32.670434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1712 21:03:32.771202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1713 21:03:32.772045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1715 21:03:32.871258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1716 21:03:32.872141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1718 21:03:32.973411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1719 21:03:32.974307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1721 21:03:33.073462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1722 21:03:33.074341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1724 21:03:33.175555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1725 21:03:33.176392 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1727 21:03:33.270256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1728 21:03:33.271414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1730 21:03:33.364691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1731 21:03:33.365518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1733 21:03:33.459196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1734 21:03:33.460016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1736 21:03:33.560819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1737 21:03:33.561654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1739 21:03:33.660739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1740 21:03:33.661550 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1742 21:03:33.754317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1743 21:03:33.755158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1745 21:03:33.855065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1746 21:03:33.856238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1748 21:03:33.956805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1749 21:03:33.957675 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1751 21:03:34.057545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1752 21:03:34.058472 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1754 21:03:34.150845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1755 21:03:34.151692 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1757 21:03:34.251745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1758 21:03:34.252612 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1760 21:03:34.352533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1761 21:03:34.353372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1763 21:03:34.454057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1764 21:03:34.454874 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1766 21:03:34.555557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1767 21:03:34.556374 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1769 21:03:34.655992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1770 21:03:34.656845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1772 21:03:34.749300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1773 21:03:34.750151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1775 21:03:34.841377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1776 21:03:34.842250 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1778 21:03:34.935075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1779 21:03:34.935905 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1781 21:03:35.026490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1782 21:03:35.027308 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1784 21:03:35.118958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1785 21:03:35.119765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1787 21:03:35.214619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1788 21:03:35.224391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1790 21:03:35.312887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1791 21:03:35.313641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1793 21:03:35.413438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1794 21:03:35.414299 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1796 21:03:35.514955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1797 21:03:35.515769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1799 21:03:35.610003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1800 21:03:35.610813 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1802 21:03:35.701546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1803 21:03:35.702470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1805 21:03:35.794240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1806 21:03:35.795039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1808 21:03:35.895788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1809 21:03:35.896564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1811 21:03:35.996212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1812 21:03:35.997032 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1814 21:03:36.097193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1815 21:03:36.098209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1817 21:03:36.198585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1818 21:03:36.199430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1820 21:03:36.299617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1821 21:03:36.300442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1823 21:03:36.401640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1824 21:03:36.402500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1826 21:03:36.492699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1827 21:03:36.493534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1829 21:03:36.594020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1830 21:03:36.594858 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1832 21:03:36.688785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1833 21:03:36.689609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1835 21:03:36.789488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1836 21:03:36.790359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1838 21:03:36.882369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1839 21:03:36.883179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1841 21:03:36.976974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1842 21:03:36.977775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1844 21:03:37.079477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1845 21:03:37.080295 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1847 21:03:37.175657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1848 21:03:37.176574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1850 21:03:37.280055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1851 21:03:37.281320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1853 21:03:37.376939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1854 21:03:37.377847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1856 21:03:37.572573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1857 21:03:37.573170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1859 21:03:37.711392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1860 21:03:37.712222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1862 21:03:37.809633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1863 21:03:37.810427 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1865 21:03:37.910901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1866 21:03:37.911693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1868 21:03:38.004162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1869 21:03:38.005187 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1871 21:03:38.161165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1872 21:03:38.162140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1874 21:03:38.260847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1875 21:03:38.261710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1877 21:03:38.361892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1878 21:03:38.363005 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1880 21:03:38.486089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1881 21:03:38.487284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1883 21:03:38.577660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1884 21:03:38.578792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1886 21:03:38.671206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1887 21:03:38.672277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1889 21:03:38.786274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1890 21:03:38.786885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1892 21:03:38.880586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1893 21:03:38.881180 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1895 21:03:38.973138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1896 21:03:38.973785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1898 21:03:39.117500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1899 21:03:39.118123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1901 21:03:39.261613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1902 21:03:39.262477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1904 21:03:39.364530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1905 21:03:39.365414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1907 21:03:39.478972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1908 21:03:39.480232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1910 21:03:39.615355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1911 21:03:39.616551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1913 21:03:39.718194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1914 21:03:39.719359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1916 21:03:39.819698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1917 21:03:39.820757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1919 21:03:40.008273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1920 21:03:40.009515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1922 21:03:40.108747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1923 21:03:40.109962 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1925 21:03:40.202640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1926 21:03:40.203560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1928 21:03:40.295519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1929 21:03:40.296436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1931 21:03:40.389127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1932 21:03:40.390050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1934 21:03:40.480895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1935 21:03:40.481804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1937 21:03:40.571743 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1939 21:03:40.574906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1940 21:03:40.664668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1942 21:03:40.666776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1943 21:03:40.758850 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1945 21:03:40.761898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1946 21:03:40.851793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1947 21:03:40.852476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1949 21:03:40.943021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1950 21:03:40.943921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1952 21:03:41.032690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1953 21:03:41.033650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1955 21:03:41.125255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1956 21:03:41.126284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1958 21:03:41.216388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1959 21:03:41.216994 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1961 21:03:41.311990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1962 21:03:41.312583 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1964 21:03:41.406039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1965 21:03:41.406969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1967 21:03:41.509929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1968 21:03:41.510876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1970 21:03:41.607974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1971 21:03:41.608853 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1973 21:03:41.710672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1974 21:03:41.711582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1976 21:03:41.802959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1977 21:03:41.803804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1979 21:03:41.897154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1980 21:03:41.897985 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1982 21:03:41.988847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1983 21:03:41.989981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1985 21:03:42.090074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1986 21:03:42.091051 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1988 21:03:42.213191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1989 21:03:42.214048 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1991 21:03:42.308439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
1992 21:03:42.309317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
1994 21:03:42.399339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
1995 21:03:42.399921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
1997 21:03:42.491558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
1998 21:03:42.492195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2000 21:03:42.586099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2001 21:03:42.586738 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2003 21:03:42.682018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2004 21:03:42.683142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2006 21:03:42.778544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2007 21:03:42.779491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2009 21:03:42.877051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2010 21:03:42.877943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2012 21:03:42.979105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2013 21:03:42.980175 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2015 21:03:43.079370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2016 21:03:43.080388 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2018 21:03:43.180190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2019 21:03:43.180803 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2021 21:03:43.277780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2022 21:03:43.278703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2024 21:03:43.370719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2025 21:03:43.371605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2027 21:03:43.464507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2028 21:03:43.465397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2030 21:03:43.557066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2031 21:03:43.557932 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2033 21:03:43.650074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2034 21:03:43.650935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2036 21:03:43.743598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2037 21:03:43.744579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2039 21:03:43.835235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2040 21:03:43.836560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2042 21:03:43.928691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2043 21:03:43.929595 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2045 21:03:44.019237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2046 21:03:44.020128 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2048 21:03:44.111391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2049 21:03:44.112305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2051 21:03:44.208450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2052 21:03:44.209377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2054 21:03:44.303094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2055 21:03:44.304002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2057 21:03:44.398920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2058 21:03:44.399558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2060 21:03:44.491127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2061 21:03:44.491750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2063 21:03:44.588935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2064 21:03:44.589550 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2066 21:03:44.680799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2067 21:03:44.681414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2069 21:03:44.776797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2070 21:03:44.777419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2072 21:03:44.869053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2073 21:03:44.869650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2075 21:03:44.963308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2076 21:03:44.963919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2078 21:03:45.056745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2079 21:03:45.057352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2081 21:03:45.150817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2082 21:03:45.151705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2084 21:03:45.243081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2085 21:03:45.244244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2087 21:03:45.339884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2088 21:03:45.340976 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2090 21:03:45.432748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2091 21:03:45.433796 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2093 21:03:45.526360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2094 21:03:45.527524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2096 21:03:45.617918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2097 21:03:45.618979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2099 21:03:45.709243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2100 21:03:45.710362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2102 21:03:45.792937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2103 21:03:45.793984 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2105 21:03:45.888960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2106 21:03:45.889934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2108 21:03:45.982072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2109 21:03:45.983102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2111 21:03:46.076904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2112 21:03:46.077982 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2114 21:03:46.182034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2115 21:03:46.183138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2117 21:03:46.278478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2118 21:03:46.279420 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2120 21:03:46.381697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2121 21:03:46.382666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2123 21:03:46.482645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2124 21:03:46.483524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2126 21:03:46.574498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2127 21:03:46.575439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2129 21:03:46.665478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2130 21:03:46.666476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2132 21:03:46.773160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2133 21:03:46.773797 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2135 21:03:46.865296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2136 21:03:46.866232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2138 21:03:46.958745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2139 21:03:46.959390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2141 21:03:47.316290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2142 21:03:47.316699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2143 21:03:47.317171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2145 21:03:47.317934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2147 21:03:47.318651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2148 21:03:47.319106 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2150 21:03:47.329513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2151 21:03:47.330069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2153 21:03:47.417541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2154 21:03:47.418486 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2156 21:03:47.511854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2157 21:03:47.512460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2159 21:03:47.606135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2160 21:03:47.606767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2162 21:03:47.701474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2163 21:03:47.702175 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2165 21:03:47.794889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2166 21:03:47.795547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2168 21:03:47.898809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2169 21:03:47.899528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2171 21:03:47.995085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2172 21:03:47.995746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2174 21:03:48.097599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2175 21:03:48.098313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2177 21:03:48.199128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2178 21:03:48.200020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2180 21:03:48.287227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2181 21:03:48.288095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2183 21:03:48.382690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2184 21:03:48.383578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2186 21:03:48.476173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2187 21:03:48.477057 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2189 21:03:48.568927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2190 21:03:48.569787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2192 21:03:48.659714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2193 21:03:48.660600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2195 21:03:48.761561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2196 21:03:48.762218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2198 21:03:48.863739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2199 21:03:48.864373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2201 21:03:48.965591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2202 21:03:48.966307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2204 21:03:49.055980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2205 21:03:49.056899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2207 21:03:49.147123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2208 21:03:49.148008 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2210 21:03:49.240384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2211 21:03:49.241021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2213 21:03:49.343375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2214 21:03:49.344015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2216 21:03:49.444893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2217 21:03:49.445720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2219 21:03:49.532719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2220 21:03:49.533376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2222 21:03:49.628710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2223 21:03:49.629568 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2225 21:03:49.722071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2226 21:03:49.722938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2228 21:03:49.824755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2229 21:03:49.825597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2231 21:03:49.924523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2232 21:03:49.925359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2234 21:03:50.025460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2235 21:03:50.026330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2237 21:03:50.127817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2238 21:03:50.128901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2240 21:03:50.216213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2241 21:03:50.216920 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2243 21:03:50.309024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2244 21:03:50.309956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2246 21:03:50.402028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2247 21:03:50.402891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2249 21:03:50.493908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2250 21:03:50.494494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2252 21:03:50.588338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2253 21:03:50.590790 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2255 21:03:50.683380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2256 21:03:50.684981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2258 21:03:50.784871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2260 21:03:50.787939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2261 21:03:50.885032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2262 21:03:50.885940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2264 21:03:50.980066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2265 21:03:50.981012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2267 21:03:51.072534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2268 21:03:51.073433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2270 21:03:51.175366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2271 21:03:51.176257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2273 21:03:51.276544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2274 21:03:51.277440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2276 21:03:51.369760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2277 21:03:51.370383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2279 21:03:51.462198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2280 21:03:51.463085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2282 21:03:51.564552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2283 21:03:51.565453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2285 21:03:51.666121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2286 21:03:51.667014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2288 21:03:51.766636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2289 21:03:51.767163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2291 21:03:51.860145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2292 21:03:51.860829 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2294 21:03:51.951064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2295 21:03:51.951738 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2297 21:03:52.043805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2298 21:03:52.044349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2300 21:03:52.148678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2301 21:03:52.149239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2303 21:03:52.260316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2304 21:03:52.261101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2306 21:03:52.366994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2307 21:03:52.367577 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2309 21:03:52.466642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2310 21:03:52.467274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2312 21:03:52.570555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2313 21:03:52.571306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2315 21:03:52.672888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2316 21:03:52.673512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2318 21:03:52.770898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2319 21:03:52.771593 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2321 21:03:52.864897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2322 21:03:52.865580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2324 21:03:52.967035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2325 21:03:52.967697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2327 21:03:53.067887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2328 21:03:53.068883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2330 21:03:53.161233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2331 21:03:53.161973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2333 21:03:53.252951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2334 21:03:53.253689 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2336 21:03:53.345163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2337 21:03:53.345832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2339 21:03:53.438583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2340 21:03:53.439270 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2342 21:03:53.532929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2343 21:03:53.533583 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2345 21:03:53.628287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2346 21:03:53.628964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2348 21:03:53.720940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2349 21:03:53.721934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2351 21:03:53.813306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2352 21:03:53.813973 + set +x
2353 21:03:53.814747 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2355 21:03:53.817586 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 942676_1.6.2.4.5>
2356 21:03:53.818543 Received signal: <ENDRUN> 1_kselftest-dt 942676_1.6.2.4.5
2357 21:03:53.819076 Ending use of test pattern.
2358 21:03:53.819530 Ending test lava.1_kselftest-dt (942676_1.6.2.4.5), duration 87.83
2360 21:03:53.826436 <LAVA_TEST_RUNNER EXIT>
2361 21:03:53.827206 ok: lava_test_shell seems to have completed
2362 21:03:53.840055 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2363 21:03:53.842135 end: 3.1 lava-test-shell (duration 00:01:29) [common]
2364 21:03:53.842766 end: 3 lava-test-retry (duration 00:01:29) [common]
2365 21:03:53.843404 start: 4 finalize (timeout 00:05:26) [common]
2366 21:03:53.844011 start: 4.1 power-off (timeout 00:00:30) [common]
2367 21:03:53.845002 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2368 21:03:53.878968 >> OK - accepted request
2369 21:03:53.881229 Returned 0 in 0 seconds
2370 21:03:53.982890 end: 4.1 power-off (duration 00:00:00) [common]
2372 21:03:53.985298 start: 4.2 read-feedback (timeout 00:05:25) [common]
2373 21:03:53.986950 Listened to connection for namespace 'common' for up to 1s
2374 21:03:53.988123 Listened to connection for namespace 'common' for up to 1s
2375 21:03:54.986664 Finalising connection for namespace 'common'
2376 21:03:54.987410 Disconnecting from shell: Finalise
2377 21:03:54.987903 / #
2378 21:03:55.089179 end: 4.2 read-feedback (duration 00:00:01) [common]
2379 21:03:55.090689 end: 4 finalize (duration 00:00:01) [common]
2380 21:03:55.091927 Cleaning after the job
2381 21:03:55.093085 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/942676/tftp-deploy-eaamaxf6/ramdisk
2382 21:03:55.107713 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/942676/tftp-deploy-eaamaxf6/kernel
2383 21:03:55.111120 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/942676/tftp-deploy-eaamaxf6/dtb
2384 21:03:55.113242 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/942676/tftp-deploy-eaamaxf6/nfsrootfs
2385 21:03:55.225185 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/942676/tftp-deploy-eaamaxf6/modules
2386 21:03:55.232300 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/942676
2387 21:03:58.822452 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/942676
2388 21:03:58.823038 Job finished correctly