Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 21:53:07.521900 lava-dispatcher, installed at version: 2024.01
2 21:53:07.522648 start: 0 validate
3 21:53:07.523143 Start time: 2024-11-05 21:53:07.523114+00:00 (UTC)
4 21:53:07.523673 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:53:07.524222 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 21:53:07.569993 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:53:07.570642 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-228-ga18dadd1209ac%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 21:53:07.604248 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:53:07.604879 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-228-ga18dadd1209ac%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 21:53:07.637348 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:53:07.637844 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-228-ga18dadd1209ac%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 21:53:07.681049 validate duration: 0.16
14 21:53:07.681909 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 21:53:07.682263 start: 1.1 download-retry (timeout 00:10:00) [common]
16 21:53:07.682581 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 21:53:07.683160 Not decompressing ramdisk as can be used compressed.
18 21:53:07.683609 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 21:53:07.683865 saving as /var/lib/lava/dispatcher/tmp/942710/tftp-deploy-si6n787q/ramdisk/rootfs.cpio.gz
20 21:53:07.684163 total size: 47897469 (45 MB)
21 21:53:07.721830 progress 0 % (0 MB)
22 21:53:07.751809 progress 5 % (2 MB)
23 21:53:07.781137 progress 10 % (4 MB)
24 21:53:07.810457 progress 15 % (6 MB)
25 21:53:07.839779 progress 20 % (9 MB)
26 21:53:07.869001 progress 25 % (11 MB)
27 21:53:07.898400 progress 30 % (13 MB)
28 21:53:07.927846 progress 35 % (16 MB)
29 21:53:07.956987 progress 40 % (18 MB)
30 21:53:07.986192 progress 45 % (20 MB)
31 21:53:08.015639 progress 50 % (22 MB)
32 21:53:08.044913 progress 55 % (25 MB)
33 21:53:08.074360 progress 60 % (27 MB)
34 21:53:08.104021 progress 65 % (29 MB)
35 21:53:08.133118 progress 70 % (32 MB)
36 21:53:08.162359 progress 75 % (34 MB)
37 21:53:08.191407 progress 80 % (36 MB)
38 21:53:08.220962 progress 85 % (38 MB)
39 21:53:08.250247 progress 90 % (41 MB)
40 21:53:08.279238 progress 95 % (43 MB)
41 21:53:08.308365 progress 100 % (45 MB)
42 21:53:08.309093 45 MB downloaded in 0.62 s (73.10 MB/s)
43 21:53:08.309673 end: 1.1.1 http-download (duration 00:00:01) [common]
45 21:53:08.310616 end: 1.1 download-retry (duration 00:00:01) [common]
46 21:53:08.310935 start: 1.2 download-retry (timeout 00:09:59) [common]
47 21:53:08.311225 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 21:53:08.311727 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-228-ga18dadd1209ac/arm64/defconfig/gcc-12/kernel/Image
49 21:53:08.312038 saving as /var/lib/lava/dispatcher/tmp/942710/tftp-deploy-si6n787q/kernel/Image
50 21:53:08.312272 total size: 45713920 (43 MB)
51 21:53:08.312502 No compression specified
52 21:53:08.354384 progress 0 % (0 MB)
53 21:53:08.384860 progress 5 % (2 MB)
54 21:53:08.414610 progress 10 % (4 MB)
55 21:53:08.444522 progress 15 % (6 MB)
56 21:53:08.473717 progress 20 % (8 MB)
57 21:53:08.502805 progress 25 % (10 MB)
58 21:53:08.532928 progress 30 % (13 MB)
59 21:53:08.564372 progress 35 % (15 MB)
60 21:53:08.595688 progress 40 % (17 MB)
61 21:53:08.626425 progress 45 % (19 MB)
62 21:53:08.657612 progress 50 % (21 MB)
63 21:53:08.688670 progress 55 % (24 MB)
64 21:53:08.720124 progress 60 % (26 MB)
65 21:53:08.751220 progress 65 % (28 MB)
66 21:53:08.782713 progress 70 % (30 MB)
67 21:53:08.813295 progress 75 % (32 MB)
68 21:53:08.842760 progress 80 % (34 MB)
69 21:53:08.872371 progress 85 % (37 MB)
70 21:53:08.901829 progress 90 % (39 MB)
71 21:53:08.931343 progress 95 % (41 MB)
72 21:53:08.960805 progress 100 % (43 MB)
73 21:53:08.961415 43 MB downloaded in 0.65 s (67.16 MB/s)
74 21:53:08.961923 end: 1.2.1 http-download (duration 00:00:01) [common]
76 21:53:08.962751 end: 1.2 download-retry (duration 00:00:01) [common]
77 21:53:08.963029 start: 1.3 download-retry (timeout 00:09:59) [common]
78 21:53:08.963298 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 21:53:08.963804 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-228-ga18dadd1209ac/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 21:53:08.964110 saving as /var/lib/lava/dispatcher/tmp/942710/tftp-deploy-si6n787q/dtb/meson-g12b-a311d-libretech-cc.dtb
81 21:53:08.964323 total size: 54703 (0 MB)
82 21:53:08.964538 No compression specified
83 21:53:09.006855 progress 59 % (0 MB)
84 21:53:09.007741 progress 100 % (0 MB)
85 21:53:09.008363 0 MB downloaded in 0.04 s (1.18 MB/s)
86 21:53:09.008865 end: 1.3.1 http-download (duration 00:00:00) [common]
88 21:53:09.009704 end: 1.3 download-retry (duration 00:00:00) [common]
89 21:53:09.009971 start: 1.4 download-retry (timeout 00:09:59) [common]
90 21:53:09.010235 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 21:53:09.010731 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-228-ga18dadd1209ac/arm64/defconfig/gcc-12/modules.tar.xz
92 21:53:09.011001 saving as /var/lib/lava/dispatcher/tmp/942710/tftp-deploy-si6n787q/modules/modules.tar
93 21:53:09.011210 total size: 11607644 (11 MB)
94 21:53:09.011425 Using unxz to decompress xz
95 21:53:09.050474 progress 0 % (0 MB)
96 21:53:09.117183 progress 5 % (0 MB)
97 21:53:09.193706 progress 10 % (1 MB)
98 21:53:09.291488 progress 15 % (1 MB)
99 21:53:09.384908 progress 20 % (2 MB)
100 21:53:09.466749 progress 25 % (2 MB)
101 21:53:09.544556 progress 30 % (3 MB)
102 21:53:09.620473 progress 35 % (3 MB)
103 21:53:09.699512 progress 40 % (4 MB)
104 21:53:09.778084 progress 45 % (5 MB)
105 21:53:09.864389 progress 50 % (5 MB)
106 21:53:09.943598 progress 55 % (6 MB)
107 21:53:10.030674 progress 60 % (6 MB)
108 21:53:10.113083 progress 65 % (7 MB)
109 21:53:10.191622 progress 70 % (7 MB)
110 21:53:10.276700 progress 75 % (8 MB)
111 21:53:10.363654 progress 80 % (8 MB)
112 21:53:10.445934 progress 85 % (9 MB)
113 21:53:10.528707 progress 90 % (9 MB)
114 21:53:10.608625 progress 95 % (10 MB)
115 21:53:10.687418 progress 100 % (11 MB)
116 21:53:10.698647 11 MB downloaded in 1.69 s (6.56 MB/s)
117 21:53:10.699343 end: 1.4.1 http-download (duration 00:00:02) [common]
119 21:53:10.700447 end: 1.4 download-retry (duration 00:00:02) [common]
120 21:53:10.700996 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 21:53:10.701526 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 21:53:10.702019 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 21:53:10.702523 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 21:53:10.703571 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4
125 21:53:10.704548 makedir: /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin
126 21:53:10.705230 makedir: /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/tests
127 21:53:10.705862 makedir: /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/results
128 21:53:10.706504 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-add-keys
129 21:53:10.707483 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-add-sources
130 21:53:10.708512 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-background-process-start
131 21:53:10.709517 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-background-process-stop
132 21:53:10.710575 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-common-functions
133 21:53:10.711543 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-echo-ipv4
134 21:53:10.712582 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-install-packages
135 21:53:10.713548 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-installed-packages
136 21:53:10.714483 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-os-build
137 21:53:10.715401 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-probe-channel
138 21:53:10.716373 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-probe-ip
139 21:53:10.717323 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-target-ip
140 21:53:10.718263 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-target-mac
141 21:53:10.719194 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-target-storage
142 21:53:10.720180 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-test-case
143 21:53:10.721141 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-test-event
144 21:53:10.722081 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-test-feedback
145 21:53:10.723016 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-test-raise
146 21:53:10.723950 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-test-reference
147 21:53:10.724939 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-test-runner
148 21:53:10.725891 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-test-set
149 21:53:10.726816 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-test-shell
150 21:53:10.727760 Updating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-install-packages (oe)
151 21:53:10.728837 Updating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/bin/lava-installed-packages (oe)
152 21:53:10.729824 Creating /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/environment
153 21:53:10.730628 LAVA metadata
154 21:53:10.731147 - LAVA_JOB_ID=942710
155 21:53:10.731583 - LAVA_DISPATCHER_IP=192.168.6.2
156 21:53:10.732316 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 21:53:10.734232 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 21:53:10.734882 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 21:53:10.735300 skipped lava-vland-overlay
160 21:53:10.735787 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 21:53:10.736232 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 21:53:10.736477 skipped lava-multinode-overlay
163 21:53:10.736731 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 21:53:10.736994 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 21:53:10.737267 Loading test definitions
166 21:53:10.737567 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 21:53:10.737801 Using /lava-942710 at stage 0
168 21:53:10.739196 uuid=942710_1.5.2.4.1 testdef=None
169 21:53:10.739572 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 21:53:10.739855 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 21:53:10.741781 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 21:53:10.742649 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 21:53:10.745060 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 21:53:10.745970 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 21:53:10.748296 runner path: /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/0/tests/0_igt-gpu-panfrost test_uuid 942710_1.5.2.4.1
178 21:53:10.748998 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 21:53:10.749874 Creating lava-test-runner.conf files
181 21:53:10.750088 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/942710/lava-overlay-covarlr4/lava-942710/0 for stage 0
182 21:53:10.750463 - 0_igt-gpu-panfrost
183 21:53:10.750873 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 21:53:10.751187 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 21:53:10.776075 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 21:53:10.776556 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 21:53:10.776829 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 21:53:10.777105 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 21:53:10.777374 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 21:53:17.696736 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 21:53:17.697314 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 21:53:17.697619 extracting modules file /var/lib/lava/dispatcher/tmp/942710/tftp-deploy-si6n787q/modules/modules.tar to /var/lib/lava/dispatcher/tmp/942710/extract-overlay-ramdisk-9e3ky6er/ramdisk
193 21:53:19.355406 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 21:53:19.355889 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 21:53:19.356193 [common] Applying overlay /var/lib/lava/dispatcher/tmp/942710/compress-overlay-eq5evz_h/overlay-1.5.2.5.tar.gz to ramdisk
196 21:53:19.356414 [common] Applying overlay /var/lib/lava/dispatcher/tmp/942710/compress-overlay-eq5evz_h/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/942710/extract-overlay-ramdisk-9e3ky6er/ramdisk
197 21:53:19.386433 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 21:53:19.386803 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 21:53:19.387074 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 21:53:19.387305 Converting downloaded kernel to a uImage
201 21:53:19.387609 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/942710/tftp-deploy-si6n787q/kernel/Image /var/lib/lava/dispatcher/tmp/942710/tftp-deploy-si6n787q/kernel/uImage
202 21:53:19.888885 output: Image Name:
203 21:53:19.889300 output: Created: Tue Nov 5 21:53:19 2024
204 21:53:19.889514 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 21:53:19.889719 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 21:53:19.889923 output: Load Address: 01080000
207 21:53:19.890124 output: Entry Point: 01080000
208 21:53:19.890325 output:
209 21:53:19.890657 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 21:53:19.890926 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 21:53:19.891196 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 21:53:19.891453 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 21:53:19.891712 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 21:53:19.891968 Building ramdisk /var/lib/lava/dispatcher/tmp/942710/extract-overlay-ramdisk-9e3ky6er/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/942710/extract-overlay-ramdisk-9e3ky6er/ramdisk
215 21:53:26.411957 >> 502379 blocks
216 21:53:48.989678 Adding RAMdisk u-boot header.
217 21:53:48.990537 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/942710/extract-overlay-ramdisk-9e3ky6er/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/942710/extract-overlay-ramdisk-9e3ky6er/ramdisk.cpio.gz.uboot
218 21:53:49.655814 output: Image Name:
219 21:53:49.656636 output: Created: Tue Nov 5 21:53:48 2024
220 21:53:49.657165 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 21:53:49.657691 output: Data Size: 65713051 Bytes = 64172.90 KiB = 62.67 MiB
222 21:53:49.658204 output: Load Address: 00000000
223 21:53:49.658712 output: Entry Point: 00000000
224 21:53:49.659217 output:
225 21:53:49.660582 rename /var/lib/lava/dispatcher/tmp/942710/extract-overlay-ramdisk-9e3ky6er/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/942710/tftp-deploy-si6n787q/ramdisk/ramdisk.cpio.gz.uboot
226 21:53:49.661508 end: 1.5.8 compress-ramdisk (duration 00:00:30) [common]
227 21:53:49.662213 end: 1.5 prepare-tftp-overlay (duration 00:00:39) [common]
228 21:53:49.662896 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:18) [common]
229 21:53:49.663483 No LXC device requested
230 21:53:49.664162 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 21:53:49.664826 start: 1.7 deploy-device-env (timeout 00:09:18) [common]
232 21:53:49.665465 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 21:53:49.665988 Checking files for TFTP limit of 4294967296 bytes.
234 21:53:49.669469 end: 1 tftp-deploy (duration 00:00:42) [common]
235 21:53:49.670212 start: 2 uboot-action (timeout 00:05:00) [common]
236 21:53:49.670875 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 21:53:49.671522 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 21:53:49.672225 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 21:53:49.672921 Using kernel file from prepare-kernel: 942710/tftp-deploy-si6n787q/kernel/uImage
240 21:53:49.673711 substitutions:
241 21:53:49.674251 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 21:53:49.674774 - {DTB_ADDR}: 0x01070000
243 21:53:49.675290 - {DTB}: 942710/tftp-deploy-si6n787q/dtb/meson-g12b-a311d-libretech-cc.dtb
244 21:53:49.675813 - {INITRD}: 942710/tftp-deploy-si6n787q/ramdisk/ramdisk.cpio.gz.uboot
245 21:53:49.676360 - {KERNEL_ADDR}: 0x01080000
246 21:53:49.676868 - {KERNEL}: 942710/tftp-deploy-si6n787q/kernel/uImage
247 21:53:49.677375 - {LAVA_MAC}: None
248 21:53:49.677932 - {PRESEED_CONFIG}: None
249 21:53:49.678444 - {PRESEED_LOCAL}: None
250 21:53:49.678947 - {RAMDISK_ADDR}: 0x08000000
251 21:53:49.679450 - {RAMDISK}: 942710/tftp-deploy-si6n787q/ramdisk/ramdisk.cpio.gz.uboot
252 21:53:49.679960 - {ROOT_PART}: None
253 21:53:49.680498 - {ROOT}: None
254 21:53:49.681018 - {SERVER_IP}: 192.168.6.2
255 21:53:49.681542 - {TEE_ADDR}: 0x83000000
256 21:53:49.682055 - {TEE}: None
257 21:53:49.682570 Parsed boot commands:
258 21:53:49.683065 - setenv autoload no
259 21:53:49.683578 - setenv initrd_high 0xffffffff
260 21:53:49.684105 - setenv fdt_high 0xffffffff
261 21:53:49.684613 - dhcp
262 21:53:49.685122 - setenv serverip 192.168.6.2
263 21:53:49.685628 - tftpboot 0x01080000 942710/tftp-deploy-si6n787q/kernel/uImage
264 21:53:49.686144 - tftpboot 0x08000000 942710/tftp-deploy-si6n787q/ramdisk/ramdisk.cpio.gz.uboot
265 21:53:49.686653 - tftpboot 0x01070000 942710/tftp-deploy-si6n787q/dtb/meson-g12b-a311d-libretech-cc.dtb
266 21:53:49.687164 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 21:53:49.687674 - bootm 0x01080000 0x08000000 0x01070000
268 21:53:49.688403 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 21:53:49.690372 start: 2.3 connect-device (timeout 00:05:00) [common]
271 21:53:49.690959 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 21:53:49.707637 Setting prompt string to ['lava-test: # ']
273 21:53:49.709522 end: 2.3 connect-device (duration 00:00:00) [common]
274 21:53:49.710296 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 21:53:49.710982 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 21:53:49.711654 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 21:53:49.713243 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 21:53:49.751858 >> OK - accepted request
279 21:53:49.754043 Returned 0 in 0 seconds
280 21:53:49.855456 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 21:53:49.857563 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 21:53:49.858296 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 21:53:49.858938 Setting prompt string to ['Hit any key to stop autoboot']
285 21:53:49.859526 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 21:53:49.861591 Trying 192.168.56.21...
287 21:53:49.862205 Connected to conserv1.
288 21:53:49.862739 Escape character is '^]'.
289 21:53:49.863271
290 21:53:49.863818 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 21:53:49.864415
292 21:54:01.075719 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 21:54:01.076580 bl2_stage_init 0x01
294 21:54:01.077199 bl2_stage_init 0x81
295 21:54:01.081303 hw id: 0x0000 - pwm id 0x01
296 21:54:01.082018 bl2_stage_init 0xc1
297 21:54:01.082587 bl2_stage_init 0x02
298 21:54:01.083110
299 21:54:01.086713 L0:00000000
300 21:54:01.087296 L1:20000703
301 21:54:01.087815 L2:00008067
302 21:54:01.088355 L3:14000000
303 21:54:01.089630 B2:00402000
304 21:54:01.090185 B1:e0f83180
305 21:54:01.090688
306 21:54:01.091192 TE: 58124
307 21:54:01.091693
308 21:54:01.100855 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 21:54:01.101453
310 21:54:01.101962 Board ID = 1
311 21:54:01.102462 Set A53 clk to 24M
312 21:54:01.102959 Set A73 clk to 24M
313 21:54:01.106405 Set clk81 to 24M
314 21:54:01.106981 A53 clk: 1200 MHz
315 21:54:01.107492 A73 clk: 1200 MHz
316 21:54:01.109854 CLK81: 166.6M
317 21:54:01.110411 smccc: 00012a92
318 21:54:01.115425 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 21:54:01.120993 board id: 1
320 21:54:01.126290 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 21:54:01.136807 fw parse done
322 21:54:01.142865 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 21:54:01.185388 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 21:54:01.196399 PIEI prepare done
325 21:54:01.196981 fastboot data load
326 21:54:01.197499 fastboot data verify
327 21:54:01.201908 verify result: 266
328 21:54:01.207664 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 21:54:01.208330 LPDDR4 probe
330 21:54:01.208867 ddr clk to 1584MHz
331 21:54:01.215530 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 21:54:01.251885
333 21:54:01.252550 dmc_version 0001
334 21:54:01.259487 Check phy result
335 21:54:01.265299 INFO : End of CA training
336 21:54:01.265881 INFO : End of initialization
337 21:54:01.270908 INFO : Training has run successfully!
338 21:54:01.271480 Check phy result
339 21:54:01.276511 INFO : End of initialization
340 21:54:01.277088 INFO : End of read enable training
341 21:54:01.282266 INFO : End of fine write leveling
342 21:54:01.287701 INFO : End of Write leveling coarse delay
343 21:54:01.288278 INFO : Training has run successfully!
344 21:54:01.288806 Check phy result
345 21:54:01.293297 INFO : End of initialization
346 21:54:01.293864 INFO : End of read dq deskew training
347 21:54:01.298917 INFO : End of MPR read delay center optimization
348 21:54:01.304523 INFO : End of write delay center optimization
349 21:54:01.310214 INFO : End of read delay center optimization
350 21:54:01.310793 INFO : End of max read latency training
351 21:54:01.315709 INFO : Training has run successfully!
352 21:54:01.316322 1D training succeed
353 21:54:01.324901 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 21:54:01.372507 Check phy result
355 21:54:01.373120 INFO : End of initialization
356 21:54:01.394252 INFO : End of 2D read delay Voltage center optimization
357 21:54:01.413631 INFO : End of 2D read delay Voltage center optimization
358 21:54:01.465669 INFO : End of 2D write delay Voltage center optimization
359 21:54:01.515033 INFO : End of 2D write delay Voltage center optimization
360 21:54:01.520636 INFO : Training has run successfully!
361 21:54:01.521205
362 21:54:01.521742 channel==0
363 21:54:01.526354 RxClkDly_Margin_A0==88 ps 9
364 21:54:01.526936 TxDqDly_Margin_A0==98 ps 10
365 21:54:01.531859 RxClkDly_Margin_A1==88 ps 9
366 21:54:01.532465 TxDqDly_Margin_A1==98 ps 10
367 21:54:01.532998 TrainedVREFDQ_A0==74
368 21:54:01.537435 TrainedVREFDQ_A1==74
369 21:54:01.538013 VrefDac_Margin_A0==25
370 21:54:01.538541 DeviceVref_Margin_A0==40
371 21:54:01.543005 VrefDac_Margin_A1==25
372 21:54:01.543573 DeviceVref_Margin_A1==40
373 21:54:01.544130
374 21:54:01.544664
375 21:54:01.548669 channel==1
376 21:54:01.549233 RxClkDly_Margin_A0==88 ps 9
377 21:54:01.549763 TxDqDly_Margin_A0==98 ps 10
378 21:54:01.554333 RxClkDly_Margin_A1==88 ps 9
379 21:54:01.554904 TxDqDly_Margin_A1==88 ps 9
380 21:54:01.559835 TrainedVREFDQ_A0==77
381 21:54:01.560431 TrainedVREFDQ_A1==77
382 21:54:01.560953 VrefDac_Margin_A0==23
383 21:54:01.565430 DeviceVref_Margin_A0==37
384 21:54:01.565996 VrefDac_Margin_A1==24
385 21:54:01.570964 DeviceVref_Margin_A1==37
386 21:54:01.571539
387 21:54:01.572096 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 21:54:01.572621
389 21:54:01.604649 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000019 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 21:54:01.605329 2D training succeed
391 21:54:01.610437 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 21:54:01.615730 auto size-- 65535DDR cs0 size: 2048MB
393 21:54:01.616339 DDR cs1 size: 2048MB
394 21:54:01.621298 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 21:54:01.621859 cs0 DataBus test pass
396 21:54:01.626915 cs1 DataBus test pass
397 21:54:01.627489 cs0 AddrBus test pass
398 21:54:01.628042 cs1 AddrBus test pass
399 21:54:01.628566
400 21:54:01.632503 100bdlr_step_size ps== 420
401 21:54:01.633067 result report
402 21:54:01.638104 boot times 0Enable ddr reg access
403 21:54:01.643350 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 21:54:01.656831 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 21:54:02.230569 0.0;M3 CHK:0;cm4_sp_mode 0
406 21:54:02.231310 MVN_1=0x00000000
407 21:54:02.236063 MVN_2=0x00000000
408 21:54:02.241789 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 21:54:02.242380 OPS=0x10
410 21:54:02.242919 ring efuse init
411 21:54:02.243437 chipver efuse init
412 21:54:02.247370 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 21:54:02.252999 [0.018961 Inits done]
414 21:54:02.253576 secure task start!
415 21:54:02.254113 high task start!
416 21:54:02.257574 low task start!
417 21:54:02.258150 run into bl31
418 21:54:02.264262 NOTICE: BL31: v1.3(release):4fc40b1
419 21:54:02.272021 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 21:54:02.272609 NOTICE: BL31: G12A normal boot!
421 21:54:02.297394 NOTICE: BL31: BL33 decompress pass
422 21:54:02.303078 ERROR: Error initializing runtime service opteed_fast
423 21:54:03.536074
424 21:54:03.536919
425 21:54:03.544463 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 21:54:03.545145
427 21:54:03.545703 Model: Libre Computer AML-A311D-CC Alta
428 21:54:03.752925 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 21:54:03.776261 DRAM: 2 GiB (effective 3.8 GiB)
430 21:54:03.919213 Core: 408 devices, 31 uclasses, devicetree: separate
431 21:54:03.924991 WDT: Not starting watchdog@f0d0
432 21:54:03.957264 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 21:54:03.969676 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 21:54:03.974674 ** Bad device specification mmc 0 **
435 21:54:03.985022 Card did not respond to voltage select! : -110
436 21:54:03.992667 ** Bad device specification mmc 0 **
437 21:54:03.993268 Couldn't find partition mmc 0
438 21:54:04.000996 Card did not respond to voltage select! : -110
439 21:54:04.006529 ** Bad device specification mmc 0 **
440 21:54:04.007122 Couldn't find partition mmc 0
441 21:54:04.011600 Error: could not access storage.
442 21:54:05.274916 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
443 21:54:05.275728 bl2_stage_init 0x81
444 21:54:05.280568 hw id: 0x0000 - pwm id 0x01
445 21:54:05.281167 bl2_stage_init 0xc1
446 21:54:05.281705 bl2_stage_init 0x02
447 21:54:05.282223
448 21:54:05.286091 L0:00000000
449 21:54:05.286677 L1:20000703
450 21:54:05.287211 L2:00008067
451 21:54:05.287725 L3:14000000
452 21:54:05.288274 B2:00402000
453 21:54:05.291661 B1:e0f83180
454 21:54:05.292255
455 21:54:05.292790 TE: 58150
456 21:54:05.293305
457 21:54:05.297302 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 21:54:05.297895
459 21:54:05.298435 Board ID = 1
460 21:54:05.302880 Set A53 clk to 24M
461 21:54:05.303442 Set A73 clk to 24M
462 21:54:05.303973 Set clk81 to 24M
463 21:54:05.308546 A53 clk: 1200 MHz
464 21:54:05.309132 A73 clk: 1200 MHz
465 21:54:05.309656 CLK81: 166.6M
466 21:54:05.310177 smccc: 00012aab
467 21:54:05.314035 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 21:54:05.319634 board id: 1
469 21:54:05.325457 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 21:54:05.336115 fw parse done
471 21:54:05.342083 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 21:54:05.384737 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 21:54:05.395680 PIEI prepare done
474 21:54:05.396312 fastboot data load
475 21:54:05.396851 fastboot data verify
476 21:54:05.401332 verify result: 266
477 21:54:05.406883 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 21:54:05.407464 LPDDR4 probe
479 21:54:05.408013 ddr clk to 1584MHz
480 21:54:05.414875 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 21:54:05.452099
482 21:54:05.452557 dmc_version 0001
483 21:54:05.458791 Check phy result
484 21:54:05.464722 INFO : End of CA training
485 21:54:05.465185 INFO : End of initialization
486 21:54:05.470233 INFO : Training has run successfully!
487 21:54:05.470670 Check phy result
488 21:54:05.475828 INFO : End of initialization
489 21:54:05.476294 INFO : End of read enable training
490 21:54:05.481429 INFO : End of fine write leveling
491 21:54:05.487034 INFO : End of Write leveling coarse delay
492 21:54:05.487470 INFO : Training has run successfully!
493 21:54:05.487878 Check phy result
494 21:54:05.492704 INFO : End of initialization
495 21:54:05.493145 INFO : End of read dq deskew training
496 21:54:05.498233 INFO : End of MPR read delay center optimization
497 21:54:05.503840 INFO : End of write delay center optimization
498 21:54:05.509419 INFO : End of read delay center optimization
499 21:54:05.509855 INFO : End of max read latency training
500 21:54:05.515030 INFO : Training has run successfully!
501 21:54:05.515470 1D training succeed
502 21:54:05.524221 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 21:54:05.571829 Check phy result
504 21:54:05.572313 INFO : End of initialization
505 21:54:05.593506 INFO : End of 2D read delay Voltage center optimization
506 21:54:05.613841 INFO : End of 2D read delay Voltage center optimization
507 21:54:05.665851 INFO : End of 2D write delay Voltage center optimization
508 21:54:05.715168 INFO : End of 2D write delay Voltage center optimization
509 21:54:05.720744 INFO : Training has run successfully!
510 21:54:05.721215
511 21:54:05.721643 channel==0
512 21:54:05.726356 RxClkDly_Margin_A0==88 ps 9
513 21:54:05.726845 TxDqDly_Margin_A0==98 ps 10
514 21:54:05.731972 RxClkDly_Margin_A1==88 ps 9
515 21:54:05.732468 TxDqDly_Margin_A1==98 ps 10
516 21:54:05.732887 TrainedVREFDQ_A0==74
517 21:54:05.737554 TrainedVREFDQ_A1==74
518 21:54:05.738024 VrefDac_Margin_A0==25
519 21:54:05.738435 DeviceVref_Margin_A0==40
520 21:54:05.743170 VrefDac_Margin_A1==25
521 21:54:05.743622 DeviceVref_Margin_A1==40
522 21:54:05.744059
523 21:54:05.744482
524 21:54:05.748756 channel==1
525 21:54:05.749203 RxClkDly_Margin_A0==98 ps 10
526 21:54:05.749614 TxDqDly_Margin_A0==98 ps 10
527 21:54:05.754349 RxClkDly_Margin_A1==88 ps 9
528 21:54:05.754799 TxDqDly_Margin_A1==88 ps 9
529 21:54:05.759933 TrainedVREFDQ_A0==77
530 21:54:05.760421 TrainedVREFDQ_A1==77
531 21:54:05.760837 VrefDac_Margin_A0==22
532 21:54:05.765547 DeviceVref_Margin_A0==37
533 21:54:05.765989 VrefDac_Margin_A1==24
534 21:54:05.771159 DeviceVref_Margin_A1==37
535 21:54:05.771599
536 21:54:05.772038 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 21:54:05.772457
538 21:54:05.804777 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
539 21:54:05.805290 2D training succeed
540 21:54:05.810354 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 21:54:05.815967 auto size-- 65535DDR cs0 size: 2048MB
542 21:54:05.816459 DDR cs1 size: 2048MB
543 21:54:05.821553 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 21:54:05.822008 cs0 DataBus test pass
545 21:54:05.827165 cs1 DataBus test pass
546 21:54:05.827617 cs0 AddrBus test pass
547 21:54:05.828054 cs1 AddrBus test pass
548 21:54:05.828470
549 21:54:05.832778 100bdlr_step_size ps== 420
550 21:54:05.833257 result report
551 21:54:05.838364 boot times 0Enable ddr reg access
552 21:54:05.843701 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 21:54:05.857221 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 21:54:06.430883 0.0;M3 CHK:0;cm4_sp_mode 0
555 21:54:06.431418 MVN_1=0x00000000
556 21:54:06.436368 MVN_2=0x00000000
557 21:54:06.442162 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 21:54:06.442716 OPS=0x10
559 21:54:06.443159 ring efuse init
560 21:54:06.443547 chipver efuse init
561 21:54:06.447808 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 21:54:06.453306 [0.018960 Inits done]
563 21:54:06.453757 secure task start!
564 21:54:06.454144 high task start!
565 21:54:06.457910 low task start!
566 21:54:06.458351 run into bl31
567 21:54:06.464539 NOTICE: BL31: v1.3(release):4fc40b1
568 21:54:06.472328 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 21:54:06.472771 NOTICE: BL31: G12A normal boot!
570 21:54:06.498289 NOTICE: BL31: BL33 decompress pass
571 21:54:06.503953 ERROR: Error initializing runtime service opteed_fast
572 21:54:07.737102
573 21:54:07.737688
574 21:54:07.745428 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 21:54:07.745904
576 21:54:07.746320 Model: Libre Computer AML-A311D-CC Alta
577 21:54:07.953778 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 21:54:07.977361 DRAM: 2 GiB (effective 3.8 GiB)
579 21:54:08.120170 Core: 408 devices, 31 uclasses, devicetree: separate
580 21:54:08.126148 WDT: Not starting watchdog@f0d0
581 21:54:08.158276 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 21:54:08.170791 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 21:54:08.175795 ** Bad device specification mmc 0 **
584 21:54:08.186177 Card did not respond to voltage select! : -110
585 21:54:08.193784 ** Bad device specification mmc 0 **
586 21:54:08.194236 Couldn't find partition mmc 0
587 21:54:08.202170 Card did not respond to voltage select! : -110
588 21:54:08.207575 ** Bad device specification mmc 0 **
589 21:54:08.208053 Couldn't find partition mmc 0
590 21:54:08.212702 Error: could not access storage.
591 21:54:08.556301 Net: eth0: ethernet@ff3f0000
592 21:54:08.556824 starting USB...
593 21:54:08.807941 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 21:54:08.808557 Starting the controller
595 21:54:08.814934 USB XHCI 1.10
596 21:54:10.526495 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 21:54:10.527090 bl2_stage_init 0x01
598 21:54:10.527519 bl2_stage_init 0x81
599 21:54:10.532079 hw id: 0x0000 - pwm id 0x01
600 21:54:10.532542 bl2_stage_init 0xc1
601 21:54:10.532951 bl2_stage_init 0x02
602 21:54:10.533355
603 21:54:10.537915 L0:00000000
604 21:54:10.538365 L1:20000703
605 21:54:10.538772 L2:00008067
606 21:54:10.539170 L3:14000000
607 21:54:10.540627 B2:00402000
608 21:54:10.541076 B1:e0f83180
609 21:54:10.541483
610 21:54:10.541883 TE: 58124
611 21:54:10.542276
612 21:54:10.551700 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 21:54:10.552208
614 21:54:10.552629 Board ID = 1
615 21:54:10.553031 Set A53 clk to 24M
616 21:54:10.553429 Set A73 clk to 24M
617 21:54:10.557376 Set clk81 to 24M
618 21:54:10.557832 A53 clk: 1200 MHz
619 21:54:10.558241 A73 clk: 1200 MHz
620 21:54:10.560988 CLK81: 166.6M
621 21:54:10.561480 smccc: 00012a92
622 21:54:10.566505 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 21:54:10.572270 board id: 1
624 21:54:10.576623 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 21:54:10.587872 fw parse done
626 21:54:10.593661 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 21:54:10.635406 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 21:54:10.647356 PIEI prepare done
629 21:54:10.647823 fastboot data load
630 21:54:10.648273 fastboot data verify
631 21:54:10.652869 verify result: 266
632 21:54:10.658546 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 21:54:10.659000 LPDDR4 probe
634 21:54:10.659409 ddr clk to 1584MHz
635 21:54:10.665663 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 21:54:10.703015
637 21:54:10.703471 dmc_version 0001
638 21:54:10.710032 Check phy result
639 21:54:10.716335 INFO : End of CA training
640 21:54:10.716795 INFO : End of initialization
641 21:54:10.721845 INFO : Training has run successfully!
642 21:54:10.722299 Check phy result
643 21:54:10.727427 INFO : End of initialization
644 21:54:10.727875 INFO : End of read enable training
645 21:54:10.733068 INFO : End of fine write leveling
646 21:54:10.738671 INFO : End of Write leveling coarse delay
647 21:54:10.739123 INFO : Training has run successfully!
648 21:54:10.739527 Check phy result
649 21:54:10.744365 INFO : End of initialization
650 21:54:10.744822 INFO : End of read dq deskew training
651 21:54:10.749856 INFO : End of MPR read delay center optimization
652 21:54:10.755455 INFO : End of write delay center optimization
653 21:54:10.761053 INFO : End of read delay center optimization
654 21:54:10.761503 INFO : End of max read latency training
655 21:54:10.766694 INFO : Training has run successfully!
656 21:54:10.767180 1D training succeed
657 21:54:10.775410 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 21:54:10.822809 Check phy result
659 21:54:10.823278 INFO : End of initialization
660 21:54:10.844176 INFO : End of 2D read delay Voltage center optimization
661 21:54:10.864455 INFO : End of 2D read delay Voltage center optimization
662 21:54:10.916785 INFO : End of 2D write delay Voltage center optimization
663 21:54:10.966261 INFO : End of 2D write delay Voltage center optimization
664 21:54:10.971829 INFO : Training has run successfully!
665 21:54:10.972322
666 21:54:10.972735 channel==0
667 21:54:10.977490 RxClkDly_Margin_A0==88 ps 9
668 21:54:10.977933 TxDqDly_Margin_A0==98 ps 10
669 21:54:10.983008 RxClkDly_Margin_A1==88 ps 9
670 21:54:10.983454 TxDqDly_Margin_A1==88 ps 9
671 21:54:10.983865 TrainedVREFDQ_A0==74
672 21:54:10.988596 TrainedVREFDQ_A1==74
673 21:54:10.989059 VrefDac_Margin_A0==25
674 21:54:10.989471 DeviceVref_Margin_A0==40
675 21:54:10.994192 VrefDac_Margin_A1==25
676 21:54:10.994636 DeviceVref_Margin_A1==40
677 21:54:10.995040
678 21:54:10.995438
679 21:54:10.995830 channel==1
680 21:54:11.000239 RxClkDly_Margin_A0==98 ps 10
681 21:54:11.000690 TxDqDly_Margin_A0==88 ps 9
682 21:54:11.005461 RxClkDly_Margin_A1==88 ps 9
683 21:54:11.005913 TxDqDly_Margin_A1==88 ps 9
684 21:54:11.010990 TrainedVREFDQ_A0==75
685 21:54:11.011440 TrainedVREFDQ_A1==77
686 21:54:11.011848 VrefDac_Margin_A0==22
687 21:54:11.016627 DeviceVref_Margin_A0==38
688 21:54:11.017129 VrefDac_Margin_A1==24
689 21:54:11.022205 DeviceVref_Margin_A1==37
690 21:54:11.022712
691 21:54:11.023134 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 21:54:11.023543
693 21:54:11.055778 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
694 21:54:11.056371 2D training succeed
695 21:54:11.061486 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 21:54:11.066972 auto size-- 65535DDR cs0 size: 2048MB
697 21:54:11.067469 DDR cs1 size: 2048MB
698 21:54:11.072596 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 21:54:11.073092 cs0 DataBus test pass
700 21:54:11.078187 cs1 DataBus test pass
701 21:54:11.078711 cs0 AddrBus test pass
702 21:54:11.079403 cs1 AddrBus test pass
703 21:54:11.079816
704 21:54:11.083762 100bdlr_step_size ps== 420
705 21:54:11.084312 result report
706 21:54:11.089487 boot times 0Enable ddr reg access
707 21:54:11.094412 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 21:54:11.107285 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 21:54:11.680113 0.0;M3 CHK:0;cm4_sp_mode 0
710 21:54:11.680736 MVN_1=0x00000000
711 21:54:11.685745 MVN_2=0x00000000
712 21:54:11.692045 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 21:54:11.692617 OPS=0x10
714 21:54:11.693046 ring efuse init
715 21:54:11.693468 chipver efuse init
716 21:54:11.696936 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 21:54:11.702545 [0.018961 Inits done]
718 21:54:11.702995 secure task start!
719 21:54:11.703396 high task start!
720 21:54:11.706096 low task start!
721 21:54:11.706558 run into bl31
722 21:54:11.713677 NOTICE: BL31: v1.3(release):4fc40b1
723 21:54:11.721537 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 21:54:11.722011 NOTICE: BL31: G12A normal boot!
725 21:54:11.746888 NOTICE: BL31: BL33 decompress pass
726 21:54:11.752037 ERROR: Error initializing runtime service opteed_fast
727 21:54:12.985513
728 21:54:12.986119
729 21:54:12.993639 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 21:54:12.994142
731 21:54:12.994576 Model: Libre Computer AML-A311D-CC Alta
732 21:54:13.201592 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 21:54:13.224923 DRAM: 2 GiB (effective 3.8 GiB)
734 21:54:13.368750 Core: 408 devices, 31 uclasses, devicetree: separate
735 21:54:13.373769 WDT: Not starting watchdog@f0d0
736 21:54:13.406799 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 21:54:13.419244 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 21:54:13.423387 ** Bad device specification mmc 0 **
739 21:54:13.434591 Card did not respond to voltage select! : -110
740 21:54:13.441387 ** Bad device specification mmc 0 **
741 21:54:13.441896 Couldn't find partition mmc 0
742 21:54:13.450571 Card did not respond to voltage select! : -110
743 21:54:13.456077 ** Bad device specification mmc 0 **
744 21:54:13.456585 Couldn't find partition mmc 0
745 21:54:13.460451 Error: could not access storage.
746 21:54:13.802681 Net: eth0: ethernet@ff3f0000
747 21:54:13.803256 starting USB...
748 21:54:14.055380 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 21:54:14.055947 Starting the controller
750 21:54:14.061925 USB XHCI 1.10
751 21:54:16.225392 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
752 21:54:16.226029 bl2_stage_init 0x81
753 21:54:16.230919 hw id: 0x0000 - pwm id 0x01
754 21:54:16.231386 bl2_stage_init 0xc1
755 21:54:16.231801 bl2_stage_init 0x02
756 21:54:16.232279
757 21:54:16.236514 L0:00000000
758 21:54:16.236969 L1:20000703
759 21:54:16.237380 L2:00008067
760 21:54:16.237781 L3:14000000
761 21:54:16.238178 B2:00402000
762 21:54:16.239426 B1:e0f83180
763 21:54:16.239875
764 21:54:16.240328 TE: 58150
765 21:54:16.240737
766 21:54:16.250606 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
767 21:54:16.251084
768 21:54:16.251507 Board ID = 1
769 21:54:16.251915 Set A53 clk to 24M
770 21:54:16.252364 Set A73 clk to 24M
771 21:54:16.256201 Set clk81 to 24M
772 21:54:16.256664 A53 clk: 1200 MHz
773 21:54:16.257077 A73 clk: 1200 MHz
774 21:54:16.259747 CLK81: 166.6M
775 21:54:16.260237 smccc: 00012aab
776 21:54:16.265321 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
777 21:54:16.270900 board id: 1
778 21:54:16.275890 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
779 21:54:16.286570 fw parse done
780 21:54:16.292597 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
781 21:54:16.335023 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
782 21:54:16.345935 PIEI prepare done
783 21:54:16.346410 fastboot data load
784 21:54:16.346828 fastboot data verify
785 21:54:16.351503 verify result: 266
786 21:54:16.357215 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
787 21:54:16.357696 LPDDR4 probe
788 21:54:16.358105 ddr clk to 1584MHz
789 21:54:16.365083 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
790 21:54:16.402412
791 21:54:16.402903 dmc_version 0001
792 21:54:16.409000 Check phy result
793 21:54:16.414875 INFO : End of CA training
794 21:54:16.415331 INFO : End of initialization
795 21:54:16.420476 INFO : Training has run successfully!
796 21:54:16.420953 Check phy result
797 21:54:16.426088 INFO : End of initialization
798 21:54:16.426545 INFO : End of read enable training
799 21:54:16.431685 INFO : End of fine write leveling
800 21:54:16.437274 INFO : End of Write leveling coarse delay
801 21:54:16.437741 INFO : Training has run successfully!
802 21:54:16.438148 Check phy result
803 21:54:16.442852 INFO : End of initialization
804 21:54:16.443309 INFO : End of read dq deskew training
805 21:54:16.448460 INFO : End of MPR read delay center optimization
806 21:54:16.454117 INFO : End of write delay center optimization
807 21:54:16.459670 INFO : End of read delay center optimization
808 21:54:16.460150 INFO : End of max read latency training
809 21:54:16.465275 INFO : Training has run successfully!
810 21:54:16.465732 1D training succeed
811 21:54:16.474468 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
812 21:54:16.522017 Check phy result
813 21:54:16.522479 INFO : End of initialization
814 21:54:16.544609 INFO : End of 2D read delay Voltage center optimization
815 21:54:16.564035 INFO : End of 2D read delay Voltage center optimization
816 21:54:16.616083 INFO : End of 2D write delay Voltage center optimization
817 21:54:16.665439 INFO : End of 2D write delay Voltage center optimization
818 21:54:16.671005 INFO : Training has run successfully!
819 21:54:16.671456
820 21:54:16.671864 channel==0
821 21:54:16.676613 RxClkDly_Margin_A0==88 ps 9
822 21:54:16.677064 TxDqDly_Margin_A0==98 ps 10
823 21:54:16.682264 RxClkDly_Margin_A1==88 ps 9
824 21:54:16.682711 TxDqDly_Margin_A1==88 ps 9
825 21:54:16.683149 TrainedVREFDQ_A0==74
826 21:54:16.687830 TrainedVREFDQ_A1==74
827 21:54:16.688385 VrefDac_Margin_A0==24
828 21:54:16.688799 DeviceVref_Margin_A0==40
829 21:54:16.693420 VrefDac_Margin_A1==24
830 21:54:16.693917 DeviceVref_Margin_A1==40
831 21:54:16.694307
832 21:54:16.694693
833 21:54:16.695073 channel==1
834 21:54:16.698999 RxClkDly_Margin_A0==88 ps 9
835 21:54:16.699434 TxDqDly_Margin_A0==98 ps 10
836 21:54:16.704572 RxClkDly_Margin_A1==88 ps 9
837 21:54:16.705019 TxDqDly_Margin_A1==88 ps 9
838 21:54:16.710265 TrainedVREFDQ_A0==77
839 21:54:16.710705 TrainedVREFDQ_A1==77
840 21:54:16.711097 VrefDac_Margin_A0==23
841 21:54:16.715793 DeviceVref_Margin_A0==37
842 21:54:16.716255 VrefDac_Margin_A1==24
843 21:54:16.721410 DeviceVref_Margin_A1==37
844 21:54:16.721836
845 21:54:16.722223 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
846 21:54:16.722607
847 21:54:16.755034 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000019 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
848 21:54:16.755512 2D training succeed
849 21:54:16.760611 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
850 21:54:16.766254 auto size-- 65535DDR cs0 size: 2048MB
851 21:54:16.766689 DDR cs1 size: 2048MB
852 21:54:16.771794 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
853 21:54:16.772257 cs0 DataBus test pass
854 21:54:16.777409 cs1 DataBus test pass
855 21:54:16.777837 cs0 AddrBus test pass
856 21:54:16.778224 cs1 AddrBus test pass
857 21:54:16.778605
858 21:54:16.783001 100bdlr_step_size ps== 420
859 21:54:16.783436 result report
860 21:54:16.788582 boot times 0Enable ddr reg access
861 21:54:16.793759 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
862 21:54:16.807323 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
863 21:54:17.380995 0.0;M3 CHK:0;cm4_sp_mode 0
864 21:54:17.381524 MVN_1=0x00000000
865 21:54:17.386425 MVN_2=0x00000000
866 21:54:17.392238 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
867 21:54:17.392694 OPS=0x10
868 21:54:17.393106 ring efuse init
869 21:54:17.393507 chipver efuse init
870 21:54:17.397804 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
871 21:54:17.403392 [0.018961 Inits done]
872 21:54:17.403836 secure task start!
873 21:54:17.404291 high task start!
874 21:54:17.408017 low task start!
875 21:54:17.408456 run into bl31
876 21:54:17.414637 NOTICE: BL31: v1.3(release):4fc40b1
877 21:54:17.422447 NOTICE: BL31: Built : 15:58:17, May 22 2019
878 21:54:17.422901 NOTICE: BL31: G12A normal boot!
879 21:54:17.447797 NOTICE: BL31: BL33 decompress pass
880 21:54:17.453519 ERROR: Error initializing runtime service opteed_fast
881 21:54:18.686567
882 21:54:18.687026
883 21:54:18.694848 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
884 21:54:18.695399
885 21:54:18.695789 Model: Libre Computer AML-A311D-CC Alta
886 21:54:18.903310 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
887 21:54:18.926659 DRAM: 2 GiB (effective 3.8 GiB)
888 21:54:19.069701 Core: 408 devices, 31 uclasses, devicetree: separate
889 21:54:19.075523 WDT: Not starting watchdog@f0d0
890 21:54:19.107785 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
891 21:54:19.120242 Loading Environment from FAT... Card did not respond to voltage select! : -110
892 21:54:19.125204 ** Bad device specification mmc 0 **
893 21:54:19.135583 Card did not respond to voltage select! : -110
894 21:54:19.143215 ** Bad device specification mmc 0 **
895 21:54:19.143679 Couldn't find partition mmc 0
896 21:54:19.151602 Card did not respond to voltage select! : -110
897 21:54:19.157078 ** Bad device specification mmc 0 **
898 21:54:19.157536 Couldn't find partition mmc 0
899 21:54:19.162122 Error: could not access storage.
900 21:54:19.504753 Net: eth0: ethernet@ff3f0000
901 21:54:19.505300 starting USB...
902 21:54:19.756538 Bus usb@ff500000: Register 3000140 NbrPorts 3
903 21:54:19.756951 Starting the controller
904 21:54:19.763380 USB XHCI 1.10
905 21:54:21.317526 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
906 21:54:21.325350 scanning usb for storage devices... 0 Storage Device(s) found
908 21:54:21.376960 Hit any key to stop autoboot: 1
909 21:54:21.377859 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
910 21:54:21.378472 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
911 21:54:21.378959 Setting prompt string to ['=>']
912 21:54:21.379454 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
913 21:54:21.392672 0
914 21:54:21.393663 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
915 21:54:21.394183 Sending with 10 millisecond of delay
917 21:54:22.528623 => setenv autoload no
918 21:54:22.539372 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
919 21:54:22.544293 setenv autoload no
920 21:54:22.545024 Sending with 10 millisecond of delay
922 21:54:24.341357 => setenv initrd_high 0xffffffff
923 21:54:24.351968 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
924 21:54:24.352558 setenv initrd_high 0xffffffff
925 21:54:24.353033 Sending with 10 millisecond of delay
927 21:54:25.968493 => setenv fdt_high 0xffffffff
928 21:54:25.979210 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
929 21:54:25.979739 setenv fdt_high 0xffffffff
930 21:54:25.980229 Sending with 10 millisecond of delay
932 21:54:26.271604 => dhcp
933 21:54:26.282179 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
934 21:54:26.282669 dhcp
935 21:54:26.282896 Speed: 1000, full duplex
936 21:54:26.283101 BOOTP broadcast 1
937 21:54:26.292595 DHCP client bound to address 192.168.6.27 (11 ms)
938 21:54:26.293086 Sending with 10 millisecond of delay
940 21:54:27.969047 => setenv serverip 192.168.6.2
941 21:54:27.980247 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
942 21:54:27.981300 setenv serverip 192.168.6.2
943 21:54:27.982126 Sending with 10 millisecond of delay
945 21:54:31.706653 => tftpboot 0x01080000 942710/tftp-deploy-si6n787q/kernel/uImage
946 21:54:31.717437 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
947 21:54:31.718242 tftpboot 0x01080000 942710/tftp-deploy-si6n787q/kernel/uImage
948 21:54:31.718690 Speed: 1000, full duplex
949 21:54:31.719109 Using ethernet@ff3f0000 device
950 21:54:31.719833 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
951 21:54:31.725421 Filename '942710/tftp-deploy-si6n787q/kernel/uImage'.
952 21:54:31.729249 Load address: 0x1080000
953 21:54:34.645865 Loading: *################################################## 43.6 MiB
954 21:54:34.646489 14.9 MiB/s
955 21:54:34.646917 done
956 21:54:34.649869 Bytes transferred = 45713984 (2b98a40 hex)
957 21:54:34.650659 Sending with 10 millisecond of delay
959 21:54:39.338722 => tftpboot 0x08000000 942710/tftp-deploy-si6n787q/ramdisk/ramdisk.cpio.gz.uboot
960 21:54:39.349490 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
961 21:54:39.350346 tftpboot 0x08000000 942710/tftp-deploy-si6n787q/ramdisk/ramdisk.cpio.gz.uboot
962 21:54:39.350807 Speed: 1000, full duplex
963 21:54:39.351222 Using ethernet@ff3f0000 device
964 21:54:39.352072 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
965 21:54:39.363970 Filename '942710/tftp-deploy-si6n787q/ramdisk/ramdisk.cpio.gz.uboot'.
966 21:54:39.364871 Load address: 0x8000000
967 21:54:48.726030 Loading: *#####T ############################################ UDP wrong checksum 0000000f 0000b8e5
968 21:54:53.727572 T UDP wrong checksum 0000000f 0000b8e5
969 21:55:03.731660 T T UDP wrong checksum 0000000f 0000b8e5
970 21:55:23.733266 T T T UDP wrong checksum 0000000f 0000b8e5
971 21:55:25.133136 T UDP wrong checksum 000000ff 0000317f
972 21:55:25.184763 UDP wrong checksum 000000ff 0000c271
973 21:55:38.739696 T T
974 21:55:38.740590 Retry count exceeded; starting again
976 21:55:38.742379 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
979 21:55:38.744829 end: 2.4 uboot-commands (duration 00:01:49) [common]
981 21:55:38.747219 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
983 21:55:38.748512 end: 2 uboot-action (duration 00:01:49) [common]
985 21:55:38.750241 Cleaning after the job
986 21:55:38.750851 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/942710/tftp-deploy-si6n787q/ramdisk
987 21:55:38.752292 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/942710/tftp-deploy-si6n787q/kernel
988 21:55:38.800783 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/942710/tftp-deploy-si6n787q/dtb
989 21:55:38.801652 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/942710/tftp-deploy-si6n787q/modules
990 21:55:38.824156 start: 4.1 power-off (timeout 00:00:30) [common]
991 21:55:38.824850 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
992 21:55:38.859825 >> OK - accepted request
993 21:55:38.861903 Returned 0 in 0 seconds
994 21:55:38.962707 end: 4.1 power-off (duration 00:00:00) [common]
996 21:55:38.963734 start: 4.2 read-feedback (timeout 00:10:00) [common]
997 21:55:38.964908 Listened to connection for namespace 'common' for up to 1s
998 21:55:39.965340 Finalising connection for namespace 'common'
999 21:55:39.966122 Disconnecting from shell: Finalise
1000 21:55:39.966701 =>
1001 21:55:40.067775 end: 4.2 read-feedback (duration 00:00:01) [common]
1002 21:55:40.068584 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/942710
1003 21:55:40.772797 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/942710
1004 21:55:40.773446 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.