Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 23:50:52.365713 lava-dispatcher, installed at version: 2024.01
2 23:50:52.366485 start: 0 validate
3 23:50:52.366936 Start time: 2024-11-06 23:50:52.366908+00:00 (UTC)
4 23:50:52.367461 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 23:50:52.367996 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 23:50:52.400029 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 23:50:52.400552 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-230-g1aed5b247ee28%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 23:50:52.421157 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 23:50:52.421779 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-230-g1aed5b247ee28%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 23:50:52.442887 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 23:50:52.443403 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 23:50:52.464098 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 23:50:52.464575 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-230-g1aed5b247ee28%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 23:50:52.491330 validate duration: 0.12
16 23:50:52.492288 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:50:52.492634 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:50:52.492934 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:50:52.493532 Not decompressing ramdisk as can be used compressed.
20 23:50:52.494006 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 23:50:52.494302 saving as /var/lib/lava/dispatcher/tmp/949962/tftp-deploy-xrgbj320/ramdisk/initrd.cpio.gz
22 23:50:52.494579 total size: 4775763 (4 MB)
23 23:50:52.524552 progress 0 % (0 MB)
24 23:50:52.528355 progress 5 % (0 MB)
25 23:50:52.531689 progress 10 % (0 MB)
26 23:50:52.535074 progress 15 % (0 MB)
27 23:50:52.538797 progress 20 % (0 MB)
28 23:50:52.542094 progress 25 % (1 MB)
29 23:50:52.545335 progress 30 % (1 MB)
30 23:50:52.549028 progress 35 % (1 MB)
31 23:50:52.552352 progress 40 % (1 MB)
32 23:50:52.555581 progress 45 % (2 MB)
33 23:50:52.558926 progress 50 % (2 MB)
34 23:50:52.562616 progress 55 % (2 MB)
35 23:50:52.565878 progress 60 % (2 MB)
36 23:50:52.569052 progress 65 % (2 MB)
37 23:50:52.572680 progress 70 % (3 MB)
38 23:50:52.575937 progress 75 % (3 MB)
39 23:50:52.579281 progress 80 % (3 MB)
40 23:50:52.582585 progress 85 % (3 MB)
41 23:50:52.586409 progress 90 % (4 MB)
42 23:50:52.589341 progress 95 % (4 MB)
43 23:50:52.592248 progress 100 % (4 MB)
44 23:50:52.592885 4 MB downloaded in 0.10 s (46.34 MB/s)
45 23:50:52.593441 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:50:52.594358 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:50:52.594676 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:50:52.594964 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:50:52.595454 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-230-g1aed5b247ee28/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 23:50:52.595738 saving as /var/lib/lava/dispatcher/tmp/949962/tftp-deploy-xrgbj320/kernel/zImage
52 23:50:52.595958 total size: 11440640 (10 MB)
53 23:50:52.596178 No compression specified
54 23:50:52.625166 progress 0 % (0 MB)
55 23:50:52.633183 progress 5 % (0 MB)
56 23:50:52.640741 progress 10 % (1 MB)
57 23:50:52.648672 progress 15 % (1 MB)
58 23:50:52.656342 progress 20 % (2 MB)
59 23:50:52.664240 progress 25 % (2 MB)
60 23:50:52.671723 progress 30 % (3 MB)
61 23:50:52.679605 progress 35 % (3 MB)
62 23:50:52.687092 progress 40 % (4 MB)
63 23:50:52.695116 progress 45 % (4 MB)
64 23:50:52.702565 progress 50 % (5 MB)
65 23:50:52.710369 progress 55 % (6 MB)
66 23:50:52.717876 progress 60 % (6 MB)
67 23:50:52.725328 progress 65 % (7 MB)
68 23:50:52.733243 progress 70 % (7 MB)
69 23:50:52.740636 progress 75 % (8 MB)
70 23:50:52.748938 progress 80 % (8 MB)
71 23:50:52.756468 progress 85 % (9 MB)
72 23:50:52.764313 progress 90 % (9 MB)
73 23:50:52.771936 progress 95 % (10 MB)
74 23:50:52.779264 progress 100 % (10 MB)
75 23:50:52.779775 10 MB downloaded in 0.18 s (59.36 MB/s)
76 23:50:52.780255 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:50:52.781069 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:50:52.781344 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:50:52.781610 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:50:52.782095 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-230-g1aed5b247ee28/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 23:50:52.782357 saving as /var/lib/lava/dispatcher/tmp/949962/tftp-deploy-xrgbj320/dtb/am335x-boneblack.dtb
83 23:50:52.782564 total size: 70568 (0 MB)
84 23:50:52.782771 No compression specified
85 23:50:52.814667 progress 46 % (0 MB)
86 23:50:52.815519 progress 92 % (0 MB)
87 23:50:52.816179 progress 100 % (0 MB)
88 23:50:52.816566 0 MB downloaded in 0.03 s (1.98 MB/s)
89 23:50:52.817034 end: 1.3.1 http-download (duration 00:00:00) [common]
91 23:50:52.817863 end: 1.3 download-retry (duration 00:00:00) [common]
92 23:50:52.818140 start: 1.4 download-retry (timeout 00:10:00) [common]
93 23:50:52.818405 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 23:50:52.818864 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 23:50:52.819116 saving as /var/lib/lava/dispatcher/tmp/949962/tftp-deploy-xrgbj320/nfsrootfs/full.rootfs.tar
96 23:50:52.819332 total size: 117747780 (112 MB)
97 23:50:52.819548 Using unxz to decompress xz
98 23:50:52.850171 progress 0 % (0 MB)
99 23:50:53.579398 progress 5 % (5 MB)
100 23:50:54.329071 progress 10 % (11 MB)
101 23:50:55.098778 progress 15 % (16 MB)
102 23:50:55.809324 progress 20 % (22 MB)
103 23:50:56.383051 progress 25 % (28 MB)
104 23:50:57.174596 progress 30 % (33 MB)
105 23:50:57.964712 progress 35 % (39 MB)
106 23:50:58.314975 progress 40 % (44 MB)
107 23:50:58.681145 progress 45 % (50 MB)
108 23:50:59.328887 progress 50 % (56 MB)
109 23:51:00.133943 progress 55 % (61 MB)
110 23:51:00.852702 progress 60 % (67 MB)
111 23:51:01.557623 progress 65 % (73 MB)
112 23:51:02.310756 progress 70 % (78 MB)
113 23:51:03.064473 progress 75 % (84 MB)
114 23:51:03.799771 progress 80 % (89 MB)
115 23:51:04.507760 progress 85 % (95 MB)
116 23:51:05.293307 progress 90 % (101 MB)
117 23:51:06.066929 progress 95 % (106 MB)
118 23:51:06.893729 progress 100 % (112 MB)
119 23:51:06.906069 112 MB downloaded in 14.09 s (7.97 MB/s)
120 23:51:06.907327 end: 1.4.1 http-download (duration 00:00:14) [common]
122 23:51:06.909579 end: 1.4 download-retry (duration 00:00:14) [common]
123 23:51:06.910343 start: 1.5 download-retry (timeout 00:09:46) [common]
124 23:51:06.911061 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 23:51:06.912101 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-230-g1aed5b247ee28/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 23:51:06.912713 saving as /var/lib/lava/dispatcher/tmp/949962/tftp-deploy-xrgbj320/modules/modules.tar
127 23:51:06.913281 total size: 6609904 (6 MB)
128 23:51:06.913882 Using unxz to decompress xz
129 23:51:06.950638 progress 0 % (0 MB)
130 23:51:06.988275 progress 5 % (0 MB)
131 23:51:07.032292 progress 10 % (0 MB)
132 23:51:07.079629 progress 15 % (0 MB)
133 23:51:07.124977 progress 20 % (1 MB)
134 23:51:07.174351 progress 25 % (1 MB)
135 23:51:07.218621 progress 30 % (1 MB)
136 23:51:07.260709 progress 35 % (2 MB)
137 23:51:07.304101 progress 40 % (2 MB)
138 23:51:07.346952 progress 45 % (2 MB)
139 23:51:07.390020 progress 50 % (3 MB)
140 23:51:07.432344 progress 55 % (3 MB)
141 23:51:07.482158 progress 60 % (3 MB)
142 23:51:07.524417 progress 65 % (4 MB)
143 23:51:07.567492 progress 70 % (4 MB)
144 23:51:07.613448 progress 75 % (4 MB)
145 23:51:07.656426 progress 80 % (5 MB)
146 23:51:07.700219 progress 85 % (5 MB)
147 23:51:07.743940 progress 90 % (5 MB)
148 23:51:07.786844 progress 95 % (6 MB)
149 23:51:07.830118 progress 100 % (6 MB)
150 23:51:07.843583 6 MB downloaded in 0.93 s (6.78 MB/s)
151 23:51:07.844266 end: 1.5.1 http-download (duration 00:00:01) [common]
153 23:51:07.845305 end: 1.5 download-retry (duration 00:00:01) [common]
154 23:51:07.845645 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 23:51:07.846314 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 23:51:26.931782 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/949962/extract-nfsrootfs-9ry9sv6z
157 23:51:26.932413 end: 1.6.1 extract-nfsrootfs (duration 00:00:19) [common]
158 23:51:26.932737 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
159 23:51:26.933333 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3
160 23:51:26.933766 makedir: /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin
161 23:51:26.934144 makedir: /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/tests
162 23:51:26.934471 makedir: /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/results
163 23:51:26.934825 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-add-keys
164 23:51:26.935410 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-add-sources
165 23:51:26.936014 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-background-process-start
166 23:51:26.937382 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-background-process-stop
167 23:51:26.938344 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-common-functions
168 23:51:26.938985 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-echo-ipv4
169 23:51:26.939557 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-install-packages
170 23:51:26.940073 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-installed-packages
171 23:51:26.940687 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-os-build
172 23:51:26.941193 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-probe-channel
173 23:51:26.941765 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-probe-ip
174 23:51:26.942307 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-target-ip
175 23:51:26.942802 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-target-mac
176 23:51:26.943474 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-target-storage
177 23:51:26.944022 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-test-case
178 23:51:26.944530 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-test-event
179 23:51:26.945014 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-test-feedback
180 23:51:26.945501 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-test-raise
181 23:51:26.946016 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-test-reference
182 23:51:26.946618 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-test-runner
183 23:51:26.947151 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-test-set
184 23:51:26.947645 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-test-shell
185 23:51:26.948183 Updating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-add-keys (debian)
186 23:51:26.948823 Updating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-add-sources (debian)
187 23:51:26.949549 Updating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-install-packages (debian)
188 23:51:26.950258 Updating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-installed-packages (debian)
189 23:51:26.950853 Updating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/bin/lava-os-build (debian)
190 23:51:26.951370 Creating /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/environment
191 23:51:26.951771 LAVA metadata
192 23:51:26.952092 - LAVA_JOB_ID=949962
193 23:51:26.952387 - LAVA_DISPATCHER_IP=192.168.6.3
194 23:51:26.952786 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
195 23:51:26.953823 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 23:51:26.954166 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
197 23:51:26.954378 skipped lava-vland-overlay
198 23:51:26.954622 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 23:51:26.954879 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
200 23:51:26.955079 skipped lava-multinode-overlay
201 23:51:26.955318 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 23:51:26.955567 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
203 23:51:26.955824 Loading test definitions
204 23:51:26.956103 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
205 23:51:26.956351 Using /lava-949962 at stage 0
206 23:51:26.957503 uuid=949962_1.6.2.4.1 testdef=None
207 23:51:26.957931 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 23:51:26.958215 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
209 23:51:26.960056 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 23:51:26.960918 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
212 23:51:26.963165 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 23:51:26.964044 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
215 23:51:26.965979 runner path: /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/0/tests/0_timesync-off test_uuid 949962_1.6.2.4.1
216 23:51:26.966738 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 23:51:26.967594 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
219 23:51:26.967825 Using /lava-949962 at stage 0
220 23:51:26.968200 Fetching tests from https://github.com/kernelci/test-definitions.git
221 23:51:26.968587 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/0/tests/1_kselftest-dt'
222 23:51:30.464793 Running '/usr/bin/git checkout kernelci.org
223 23:51:30.840990 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 23:51:30.842470 uuid=949962_1.6.2.4.5 testdef=None
225 23:51:30.842822 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 23:51:30.843592 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
228 23:51:30.846461 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 23:51:30.847280 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
231 23:51:30.851033 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 23:51:30.851902 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
234 23:51:30.855529 runner path: /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/0/tests/1_kselftest-dt test_uuid 949962_1.6.2.4.5
235 23:51:30.855839 BOARD='beaglebone-black'
236 23:51:30.856057 BRANCH='broonie-sound'
237 23:51:30.856261 SKIPFILE='/dev/null'
238 23:51:30.856463 SKIP_INSTALL='True'
239 23:51:30.856661 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-230-g1aed5b247ee28/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 23:51:30.856863 TST_CASENAME=''
241 23:51:30.857061 TST_CMDFILES='dt'
242 23:51:30.857649 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 23:51:30.858476 Creating lava-test-runner.conf files
245 23:51:30.858689 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/949962/lava-overlay-1kwpe4r3/lava-949962/0 for stage 0
246 23:51:30.859065 - 0_timesync-off
247 23:51:30.859309 - 1_kselftest-dt
248 23:51:30.859654 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 23:51:30.859951 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
250 23:51:54.225432 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 23:51:54.225891 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
252 23:51:54.226192 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 23:51:54.226502 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 23:51:54.226794 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
255 23:51:54.578107 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 23:51:54.578580 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
257 23:51:54.578856 extracting modules file /var/lib/lava/dispatcher/tmp/949962/tftp-deploy-xrgbj320/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949962/extract-nfsrootfs-9ry9sv6z
258 23:51:55.463282 extracting modules file /var/lib/lava/dispatcher/tmp/949962/tftp-deploy-xrgbj320/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949962/extract-overlay-ramdisk-q3wnhvpu/ramdisk
259 23:51:56.375760 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 23:51:56.376231 start: 1.6.5 apply-overlay-tftp (timeout 00:08:56) [common]
261 23:51:56.376526 [common] Applying overlay to NFS
262 23:51:56.376757 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949962/compress-overlay-guuwuxqd/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/949962/extract-nfsrootfs-9ry9sv6z
263 23:51:59.150314 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 23:51:59.150800 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
265 23:51:59.151096 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
266 23:51:59.151418 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 23:51:59.151687 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 23:51:59.151955 start: 1.6.7 configure-preseed-file (timeout 00:08:53) [common]
269 23:51:59.152215 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 23:51:59.152483 start: 1.6.8 compress-ramdisk (timeout 00:08:53) [common]
271 23:51:59.152722 Building ramdisk /var/lib/lava/dispatcher/tmp/949962/extract-overlay-ramdisk-q3wnhvpu/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/949962/extract-overlay-ramdisk-q3wnhvpu/ramdisk
272 23:52:00.147123 >> 74896 blocks
273 23:52:04.717496 Adding RAMdisk u-boot header.
274 23:52:04.718272 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/949962/extract-overlay-ramdisk-q3wnhvpu/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/949962/extract-overlay-ramdisk-q3wnhvpu/ramdisk.cpio.gz.uboot
275 23:52:04.874017 output: Image Name:
276 23:52:04.874432 output: Created: Wed Nov 6 23:52:04 2024
277 23:52:04.874643 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 23:52:04.874847 output: Data Size: 14789181 Bytes = 14442.56 KiB = 14.10 MiB
279 23:52:04.875047 output: Load Address: 00000000
280 23:52:04.875245 output: Entry Point: 00000000
281 23:52:04.875441 output:
282 23:52:04.876052 rename /var/lib/lava/dispatcher/tmp/949962/extract-overlay-ramdisk-q3wnhvpu/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/949962/tftp-deploy-xrgbj320/ramdisk/ramdisk.cpio.gz.uboot
283 23:52:04.876477 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 23:52:04.876765 end: 1.6 prepare-tftp-overlay (duration 00:00:57) [common]
285 23:52:04.877044 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:48) [common]
286 23:52:04.877288 No LXC device requested
287 23:52:04.877545 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 23:52:04.877806 start: 1.8 deploy-device-env (timeout 00:08:48) [common]
289 23:52:04.878357 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 23:52:04.878773 Checking files for TFTP limit of 4294967296 bytes.
291 23:52:04.881421 end: 1 tftp-deploy (duration 00:01:12) [common]
292 23:52:04.882025 start: 2 uboot-action (timeout 00:05:00) [common]
293 23:52:04.882553 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 23:52:04.883046 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 23:52:04.883543 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 23:52:04.884293 substitutions:
297 23:52:04.884711 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 23:52:04.885113 - {DTB_ADDR}: 0x88000000
299 23:52:04.885508 - {DTB}: 949962/tftp-deploy-xrgbj320/dtb/am335x-boneblack.dtb
300 23:52:04.885932 - {INITRD}: 949962/tftp-deploy-xrgbj320/ramdisk/ramdisk.cpio.gz.uboot
301 23:52:04.886332 - {KERNEL_ADDR}: 0x82000000
302 23:52:04.886725 - {KERNEL}: 949962/tftp-deploy-xrgbj320/kernel/zImage
303 23:52:04.887113 - {LAVA_MAC}: None
304 23:52:04.887540 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/949962/extract-nfsrootfs-9ry9sv6z
305 23:52:04.887938 - {NFS_SERVER_IP}: 192.168.6.3
306 23:52:04.888325 - {PRESEED_CONFIG}: None
307 23:52:04.888712 - {PRESEED_LOCAL}: None
308 23:52:04.889098 - {RAMDISK_ADDR}: 0x83000000
309 23:52:04.889482 - {RAMDISK}: 949962/tftp-deploy-xrgbj320/ramdisk/ramdisk.cpio.gz.uboot
310 23:52:04.889890 - {ROOT_PART}: None
311 23:52:04.890281 - {ROOT}: None
312 23:52:04.890663 - {SERVER_IP}: 192.168.6.3
313 23:52:04.891045 - {TEE_ADDR}: 0x83000000
314 23:52:04.891425 - {TEE}: None
315 23:52:04.891804 Parsed boot commands:
316 23:52:04.892172 - setenv autoload no
317 23:52:04.892552 - setenv initrd_high 0xffffffff
318 23:52:04.892932 - setenv fdt_high 0xffffffff
319 23:52:04.893311 - dhcp
320 23:52:04.893689 - setenv serverip 192.168.6.3
321 23:52:04.894095 - tftp 0x82000000 949962/tftp-deploy-xrgbj320/kernel/zImage
322 23:52:04.894481 - tftp 0x83000000 949962/tftp-deploy-xrgbj320/ramdisk/ramdisk.cpio.gz.uboot
323 23:52:04.894862 - setenv initrd_size ${filesize}
324 23:52:04.895238 - tftp 0x88000000 949962/tftp-deploy-xrgbj320/dtb/am335x-boneblack.dtb
325 23:52:04.895618 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/949962/extract-nfsrootfs-9ry9sv6z,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 23:52:04.896018 - bootz 0x82000000 0x83000000 0x88000000
327 23:52:04.896506 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 23:52:04.897980 start: 2.3 connect-device (timeout 00:05:00) [common]
330 23:52:04.898396 [common] connect-device Connecting to device using 'telnet conserv3 3000'
331 23:52:04.913370 Setting prompt string to ['lava-test: # ']
332 23:52:04.914858 end: 2.3 connect-device (duration 00:00:00) [common]
333 23:52:04.915465 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 23:52:04.916153 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 23:52:04.916820 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 23:52:04.918089 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-03'
337 23:52:04.954478 >> OK - accepted request
338 23:52:04.956590 Returned 0 in 0 seconds
339 23:52:05.057667 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 23:52:05.059301 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 23:52:05.059862 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 23:52:05.060363 Setting prompt string to ['Hit any key to stop autoboot']
344 23:52:05.060812 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 23:52:05.062379 Trying 192.168.56.22...
346 23:52:05.062868 Connected to conserv3.
347 23:52:05.063280 Escape character is '^]'.
348 23:52:05.063697
349 23:52:05.064115 ser2net port telnet,3000 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 23:52:05.064537
351 23:52:12.875843
352 23:52:12.882829 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
353 23:52:12.883387 Trying to boot from MMC1
354 23:52:13.469288
355 23:52:13.469955
356 23:52:13.474410 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
357 23:52:13.474857
358 23:52:13.475266 CPU : AM335X-GP rev 2.0
359 23:52:13.479619 Model: TI AM335x BeagleBone Black
360 23:52:13.480042 DRAM: 512 MiB
361 23:52:16.930566
362 23:52:16.937475 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
363 23:52:16.937736 Trying to boot from MMC1
364 23:52:17.523425
365 23:52:17.524011
366 23:52:17.528673 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
367 23:52:17.529108
368 23:52:17.529510 CPU : AM335X-GP rev 2.0
369 23:52:17.533963 Model: TI AM335x BeagleBone Black
370 23:52:17.534395 DRAM: 512 MiB
371 23:52:19.625241
372 23:52:19.632176 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
373 23:52:19.632707 Trying to boot from MMC1
374 23:52:20.219428
375 23:52:20.220028
376 23:52:20.224594 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
377 23:52:20.225089
378 23:52:20.225514 CPU : AM335X-GP rev 2.0
379 23:52:20.229851 Model: TI AM335x BeagleBone Black
380 23:52:20.230337 DRAM: 512 MiB
381 23:52:20.314198 Core: 160 devices, 18 uclasses, devicetree: separate
382 23:52:20.328093 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
383 23:52:20.728966 NAND: 0 MiB
384 23:52:20.738862 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
385 23:52:20.813781 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
386 23:52:20.834957 <ethaddr> not set. Validating first E-fuse MAC
387 23:52:20.863856 Net: eth2: ethernet@4a100000, eth3: usb_ether
389 23:52:20.922400 Hit any key to stop autoboot: 2
390 23:52:20.923258 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
391 23:52:20.923852 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
392 23:52:20.924334 Setting prompt string to ['=>']
393 23:52:20.924820 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
394 23:52:20.932999 0
395 23:52:20.933908 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
396 23:52:20.934415 Sending with 10 millisecond of delay
398 23:52:22.070310 => setenv autoload no
399 23:52:22.080994 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
400 23:52:22.088757 setenv autoload no
401 23:52:22.089244 Sending with 10 millisecond of delay
403 23:52:23.885955 => setenv initrd_high 0xffffffff
404 23:52:23.896570 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
405 23:52:23.897066 setenv initrd_high 0xffffffff
406 23:52:23.897507 Sending with 10 millisecond of delay
408 23:52:25.513300 => setenv fdt_high 0xffffffff
409 23:52:25.524136 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
410 23:52:25.525029 setenv fdt_high 0xffffffff
411 23:52:25.525736 Sending with 10 millisecond of delay
413 23:52:25.817538 => dhcp
414 23:52:25.828130 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
415 23:52:25.828811 dhcp
416 23:52:25.829034 link up on port 0, speed 100, full duplex
417 23:52:25.829276 BOOTP broadcast 1
418 23:52:26.083151 BOOTP broadcast 2
419 23:52:26.585208 BOOTP broadcast 3
420 23:52:27.587158 BOOTP broadcast 4
421 23:52:29.588610 BOOTP broadcast 5
422 23:52:29.691243 DHCP client bound to address 192.168.6.23 (3858 ms)
423 23:52:29.692066 Sending with 10 millisecond of delay
425 23:52:31.369673 => setenv serverip 192.168.6.3
426 23:52:31.380441 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
427 23:52:31.381283 setenv serverip 192.168.6.3
428 23:52:31.382009 Sending with 10 millisecond of delay
430 23:52:34.867043 => tftp 0x82000000 949962/tftp-deploy-xrgbj320/kernel/zImage
431 23:52:34.877910 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:30)
432 23:52:34.878844 tftp 0x82000000 949962/tftp-deploy-xrgbj320/kernel/zImage
433 23:52:34.879271 link up on port 0, speed 100, full duplex
434 23:52:34.882668 Using ethernet@4a100000 device
435 23:52:34.888098 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
436 23:52:34.895501 Filename '949962/tftp-deploy-xrgbj320/kernel/zImage'.
437 23:52:34.895971 Load address: 0x82000000
438 23:52:37.264081 Loading: *################################################## 10.9 MiB
439 23:52:37.264720 4.6 MiB/s
440 23:52:37.265139 done
441 23:52:37.268299 Bytes transferred = 11440640 (ae9200 hex)
442 23:52:37.269072 Sending with 10 millisecond of delay
444 23:52:41.718426 => tftp 0x83000000 949962/tftp-deploy-xrgbj320/ramdisk/ramdisk.cpio.gz.uboot
445 23:52:41.729233 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
446 23:52:41.730148 tftp 0x83000000 949962/tftp-deploy-xrgbj320/ramdisk/ramdisk.cpio.gz.uboot
447 23:52:41.730676 link up on port 0, speed 100, full duplex
448 23:52:41.734211 Using ethernet@4a100000 device
449 23:52:41.739972 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
450 23:52:41.747601 Filename '949962/tftp-deploy-xrgbj320/ramdisk/ramdisk.cpio.gz.uboot'.
451 23:52:41.748170 Load address: 0x83000000
452 23:52:44.370415 Loading: *################################################## 14.1 MiB
453 23:52:44.370809 5.4 MiB/s
454 23:52:44.371054 done
455 23:52:44.373832 Bytes transferred = 14789245 (e1aa7d hex)
456 23:52:44.374384 Sending with 10 millisecond of delay
458 23:52:46.231887 => setenv initrd_size ${filesize}
459 23:52:46.242679 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
460 23:52:46.243537 setenv initrd_size ${filesize}
461 23:52:46.244227 Sending with 10 millisecond of delay
463 23:52:50.393837 => tftp 0x88000000 949962/tftp-deploy-xrgbj320/dtb/am335x-boneblack.dtb
464 23:52:50.404622 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:14)
465 23:52:50.405499 tftp 0x88000000 949962/tftp-deploy-xrgbj320/dtb/am335x-boneblack.dtb
466 23:52:50.405965 link up on port 0, speed 100, full duplex
467 23:52:50.409312 Using ethernet@4a100000 device
468 23:52:50.414817 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
469 23:52:50.425755 Filename '949962/tftp-deploy-xrgbj320/dtb/am335x-boneblack.dtb'.
470 23:52:50.426389 Load address: 0x88000000
471 23:52:50.436406 Loading: *################################################## 68.9 KiB
472 23:52:50.436877 4.5 MiB/s
473 23:52:50.444983 done
474 23:52:50.445445 Bytes transferred = 70568 (113a8 hex)
475 23:52:50.446134 Sending with 10 millisecond of delay
477 23:53:03.629367 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/949962/extract-nfsrootfs-9ry9sv6z,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 23:53:03.640188 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:01)
479 23:53:03.641078 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/949962/extract-nfsrootfs-9ry9sv6z,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 23:53:03.641859 Sending with 10 millisecond of delay
482 23:53:05.982634 => bootz 0x82000000 0x83000000 0x88000000
483 23:53:05.993414 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 23:53:05.994031 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:59)
485 23:53:05.995064 bootz 0x82000000 0x83000000 0x88000000
486 23:53:05.995532 Kernel image @ 0x82000000 [ 0x000000 - 0xae9200 ]
487 23:53:05.996031 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 23:53:06.001569 Image Name:
489 23:53:06.002328 Created: 2024-11-06 23:52:04 UTC
490 23:53:06.006641 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 23:53:06.012164 Data Size: 14789181 Bytes = 14.1 MiB
492 23:53:06.012863 Load Address: 00000000
493 23:53:06.018284 Entry Point: 00000000
494 23:53:06.186519 Verifying Checksum ... OK
495 23:53:06.187128 ## Flattened Device Tree blob at 88000000
496 23:53:06.192955 Booting using the fdt blob at 0x88000000
497 23:53:06.193465 Working FDT set to 88000000
498 23:53:06.198528 Using Device Tree in place at 88000000, end 880143a7
499 23:53:06.202888 Working FDT set to 88000000
500 23:53:06.216120
501 23:53:06.216622 Starting kernel ...
502 23:53:06.217075
503 23:53:06.218055 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
504 23:53:06.218713 start: 2.4.4 auto-login-action (timeout 00:03:59) [common]
505 23:53:06.219231 Setting prompt string to ['Linux version [0-9]']
506 23:53:06.219750 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
507 23:53:06.220268 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
508 23:53:07.060021 [ 0.000000] Booting Linux on physical CPU 0x0
509 23:53:07.065911 start: 2.4.4.1 login-action (timeout 00:03:58) [common]
510 23:53:07.066534 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
511 23:53:07.067065 Setting prompt string to []
512 23:53:07.067609 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
513 23:53:07.068113 Using line separator: #'\n'#
514 23:53:07.068564 No login prompt set.
515 23:53:07.069035 Parsing kernel messages
516 23:53:07.069472 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
517 23:53:07.070364 [login-action] Waiting for messages, (timeout 00:03:58)
518 23:53:07.070866 Waiting using forced prompt support (timeout 00:01:59)
519 23:53:07.079794 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j365807-arm-gcc-12-multi-v7-defconfig-2rbjx) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Wed Nov 6 23:15:22 UTC 2024
520 23:53:07.091413 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
521 23:53:07.094299 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
522 23:53:07.105681 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
523 23:53:07.111369 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
524 23:53:07.117177 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
525 23:53:07.117678 [ 0.000000] Memory policy: Data cache writeback
526 23:53:07.123848 [ 0.000000] efi: UEFI not found.
527 23:53:07.129149 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
528 23:53:07.134876 [ 0.000000] Zone ranges:
529 23:53:07.140613 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
530 23:53:07.146345 [ 0.000000] Normal empty
531 23:53:07.146826 [ 0.000000] HighMem empty
532 23:53:07.152041 [ 0.000000] Movable zone start for each node
533 23:53:07.152526 [ 0.000000] Early memory node ranges
534 23:53:07.163475 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
535 23:53:07.168820 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
536 23:53:07.194322 [ 0.000000] CPU: All CPU(s) started in SVC mode.
537 23:53:07.199788 [ 0.000000] AM335X ES2.0 (sgx neon)
538 23:53:07.211426 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
539 23:53:07.229144 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/949962/extract-nfsrootfs-9ry9sv6z,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
540 23:53:07.240993 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
541 23:53:07.246392 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
542 23:53:07.252076 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
543 23:53:07.262155 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
544 23:53:07.291130 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
545 23:53:07.297182 <6>[ 0.000000] trace event string verifier disabled
546 23:53:07.297756 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
547 23:53:07.305124 <6>[ 0.000000] rcu: RCU event tracing is enabled.
548 23:53:07.310923 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
549 23:53:07.322260 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
550 23:53:07.327263 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
551 23:53:07.342121 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
552 23:53:07.359258 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
553 23:53:07.366053 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
554 23:53:07.457842 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
555 23:53:07.469226 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
556 23:53:07.475890 <6>[ 0.008335] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
557 23:53:07.489001 <6>[ 0.019140] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
558 23:53:07.496281 <6>[ 0.033920] Console: colour dummy device 80x30
559 23:53:07.502559 Matched prompt #6: WARNING:
560 23:53:07.502903 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
561 23:53:07.507871 <3>[ 0.038818] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
562 23:53:07.510613 <3>[ 0.045890] This ensures that you still see kernel messages. Please
563 23:53:07.516814 <3>[ 0.052619] update your kernel commandline.
564 23:53:07.557647 <6>[ 0.057230] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
565 23:53:07.563364 <6>[ 0.096149] CPU: Testing write buffer coherency: ok
566 23:53:07.569299 <6>[ 0.101515] CPU0: Spectre v2: using BPIALL workaround
567 23:53:07.569860 <6>[ 0.106979] pid_max: default: 32768 minimum: 301
568 23:53:07.580773 <6>[ 0.112169] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
569 23:53:07.587761 <6>[ 0.119990] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
570 23:53:07.594917 <6>[ 0.129351] CPU0: thread -1, cpu 0, socket -1, mpidr 0
571 23:53:07.602265 <6>[ 0.136342] Setting up static identity map for 0x80300000 - 0x803000ac
572 23:53:07.608496 <6>[ 0.145984] rcu: Hierarchical SRCU implementation.
573 23:53:07.616621 <6>[ 0.151272] rcu: Max phase no-delay instances is 1000.
574 23:53:07.627073 <6>[ 0.162373] EFI services will not be available.
575 23:53:07.638442 <6>[ 0.167652] smp: Bringing up secondary CPUs ...
576 23:53:07.653518 <6>[ 0.172696] smp: Brought up 1 node, 1 CPU
577 23:53:07.656365 <6>[ 0.177097] SMP: Total of 1 processors activated (996.14 BogoMIPS).
578 23:53:07.657017 <6>[ 0.183865] CPU: All CPU(s) started in SVC mode.
579 23:53:07.667780 <6>[ 0.189047] Memory: 406000K/522240K available (16384K kernel code, 2542K rwdata, 6784K rodata, 2048K init, 431K bss, 49048K reserved, 65536K cma-reserved, 0K highmem)
580 23:53:07.668405 <6>[ 0.205341] devtmpfs: initialized
581 23:53:07.691004 <6>[ 0.222374] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
582 23:53:07.702400 <6>[ 0.230961] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
583 23:53:07.708446 <6>[ 0.241417] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
584 23:53:07.720844 <6>[ 0.253752] pinctrl core: initialized pinctrl subsystem
585 23:53:07.728840 <6>[ 0.264366] DMI not present or invalid.
586 23:53:07.737007 <6>[ 0.270241] NET: Registered PF_NETLINK/PF_ROUTE protocol family
587 23:53:07.746470 <6>[ 0.279128] DMA: preallocated 256 KiB pool for atomic coherent allocations
588 23:53:07.761425 <6>[ 0.290656] thermal_sys: Registered thermal governor 'step_wise'
589 23:53:07.761989 <6>[ 0.290818] cpuidle: using governor menu
590 23:53:07.789022 <6>[ 0.326379] No ATAGs?
591 23:53:07.795102 <6>[ 0.329023] hw-breakpoint: debug architecture 0x4 unsupported.
592 23:53:07.806112 <6>[ 0.341090] Serial: AMBA PL011 UART driver
593 23:53:07.841982 <6>[ 0.375261] iommu: Default domain type: Translated
594 23:53:07.846875 <6>[ 0.380611] iommu: DMA domain TLB invalidation policy: strict mode
595 23:53:07.873840 <5>[ 0.410658] SCSI subsystem initialized
596 23:53:07.879645 <6>[ 0.415545] usbcore: registered new interface driver usbfs
597 23:53:07.885428 <6>[ 0.421607] usbcore: registered new interface driver hub
598 23:53:07.892234 <6>[ 0.427388] usbcore: registered new device driver usb
599 23:53:07.897982 <6>[ 0.433910] pps_core: LinuxPPS API ver. 1 registered
600 23:53:07.909486 <6>[ 0.439294] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
601 23:53:07.915806 <6>[ 0.449022] PTP clock support registered
602 23:53:07.916191 <6>[ 0.453480] EDAC MC: Ver: 3.0.0
603 23:53:07.965444 <6>[ 0.500396] scmi_core: SCMI protocol bus registered
604 23:53:07.980492 <6>[ 0.517746] vgaarb: loaded
605 23:53:07.993632 <6>[ 0.530750] clocksource: Switched to clocksource dmtimer
606 23:53:08.029679 <6>[ 0.566861] NET: Registered PF_INET protocol family
607 23:53:08.042108 <6>[ 0.572561] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
608 23:53:08.047976 <6>[ 0.581375] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
609 23:53:08.059398 <6>[ 0.590309] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
610 23:53:08.065188 <6>[ 0.598570] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
611 23:53:08.076757 <6>[ 0.606857] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
612 23:53:08.082603 <6>[ 0.614583] TCP: Hash tables configured (established 4096 bind 4096)
613 23:53:08.088362 <6>[ 0.621489] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
614 23:53:08.094262 <6>[ 0.628527] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
615 23:53:08.101910 <6>[ 0.636131] NET: Registered PF_UNIX/PF_LOCAL protocol family
616 23:53:08.192999 <6>[ 0.724859] RPC: Registered named UNIX socket transport module.
617 23:53:08.193400 <6>[ 0.731248] RPC: Registered udp transport module.
618 23:53:08.198748 <6>[ 0.736400] RPC: Registered tcp transport module.
619 23:53:08.207257 <6>[ 0.741506] RPC: Registered tcp-with-tls transport module.
620 23:53:08.213017 <6>[ 0.747431] RPC: Registered tcp NFSv4.1 backchannel transport module.
621 23:53:08.220269 <6>[ 0.754354] PCI: CLS 0 bytes, default 64
622 23:53:08.222622 <5>[ 0.760122] Initialise system trusted keyrings
623 23:53:08.244411 <6>[ 0.778687] Trying to unpack rootfs image as initramfs...
624 23:53:08.329784 <6>[ 0.861093] workingset: timestamp_bits=30 max_order=17 bucket_order=0
625 23:53:08.334642 <6>[ 0.868640] squashfs: version 4.0 (2009/01/31) Phillip Lougher
626 23:53:08.355207 <5>[ 0.892552] NFS: Registering the id_resolver key type
627 23:53:08.360949 <5>[ 0.898154] Key type id_resolver registered
628 23:53:08.366633 <5>[ 0.902833] Key type id_legacy registered
629 23:53:08.375175 <6>[ 0.907277] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
630 23:53:08.382150 <6>[ 0.914478] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
631 23:53:08.450893 <5>[ 0.988356] Key type asymmetric registered
632 23:53:08.456660 <5>[ 0.992941] Asymmetric key parser 'x509' registered
633 23:53:08.465381 <6>[ 0.998369] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
634 23:53:08.470839 <6>[ 1.006287] io scheduler mq-deadline registered
635 23:53:08.479637 <6>[ 1.011218] io scheduler kyber registered
636 23:53:08.479987 <6>[ 1.015703] io scheduler bfq registered
637 23:53:08.602598 <6>[ 1.137165] ledtrig-cpu: registered to indicate activity on CPUs
638 23:53:08.873533 <6>[ 1.407057] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
639 23:53:08.907273 <6>[ 1.444446] msm_serial: driver initialized
640 23:53:08.913188 <6>[ 1.449233] SuperH (H)SCI(F) driver initialized
641 23:53:08.919220 <6>[ 1.454538] STMicroelectronics ASC driver initialized
642 23:53:08.922294 <6>[ 1.460133] STM32 USART driver initialized
643 23:53:09.045865 <6>[ 1.582582] brd: module loaded
644 23:53:09.087267 <6>[ 1.623924] loop: module loaded
645 23:53:09.122867 <6>[ 1.659481] CAN device driver interface
646 23:53:09.129705 <6>[ 1.664721] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
647 23:53:09.135386 <6>[ 1.671836] e1000e: Intel(R) PRO/1000 Network Driver
648 23:53:09.141183 <6>[ 1.677229] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
649 23:53:09.146891 <6>[ 1.683686] igb: Intel(R) Gigabit Ethernet Network Driver
650 23:53:09.155272 <6>[ 1.689507] igb: Copyright (c) 2007-2014 Intel Corporation.
651 23:53:09.166879 <6>[ 1.698685] pegasus: Pegasus/Pegasus II USB Ethernet driver
652 23:53:09.172792 <6>[ 1.704831] usbcore: registered new interface driver pegasus
653 23:53:09.175683 <6>[ 1.710953] usbcore: registered new interface driver asix
654 23:53:09.181382 <6>[ 1.716837] usbcore: registered new interface driver ax88179_178a
655 23:53:09.187102 <6>[ 1.723427] usbcore: registered new interface driver cdc_ether
656 23:53:09.192939 <6>[ 1.729726] usbcore: registered new interface driver smsc75xx
657 23:53:09.204353 <6>[ 1.735966] usbcore: registered new interface driver smsc95xx
658 23:53:09.210261 <6>[ 1.742194] usbcore: registered new interface driver net1080
659 23:53:09.216104 <6>[ 1.748325] usbcore: registered new interface driver cdc_subset
660 23:53:09.221731 <6>[ 1.754735] usbcore: registered new interface driver zaurus
661 23:53:09.226585 <6>[ 1.760780] usbcore: registered new interface driver cdc_ncm
662 23:53:09.236313 <6>[ 1.770162] usbcore: registered new interface driver usb-storage
663 23:53:09.532117 <6>[ 2.067681] i2c_dev: i2c /dev entries driver
664 23:53:09.588344 <5>[ 2.117970] cpuidle: enable-method property 'ti,am3352' found operations
665 23:53:09.594211 <6>[ 2.127551] sdhci: Secure Digital Host Controller Interface driver
666 23:53:09.601526 <6>[ 2.134330] sdhci: Copyright(c) Pierre Ossman
667 23:53:09.608697 <6>[ 2.140710] Synopsys Designware Multimedia Card Interface Driver
668 23:53:09.614231 <6>[ 2.148597] sdhci-pltfm: SDHCI platform and OF driver helper
669 23:53:09.733029 <6>[ 2.263252] usbcore: registered new interface driver usbhid
670 23:53:09.733658 <6>[ 2.269294] usbhid: USB HID core driver
671 23:53:09.773243 <6>[ 2.308253] NET: Registered PF_INET6 protocol family
672 23:53:09.815817 <6>[ 2.353428] Segment Routing with IPv6
673 23:53:09.821672 <6>[ 2.357576] In-situ OAM (IOAM) with IPv6
674 23:53:09.828324 <6>[ 2.362108] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
675 23:53:09.835765 <6>[ 2.369337] NET: Registered PF_PACKET protocol family
676 23:53:09.841678 <6>[ 2.374899] can: controller area network core
677 23:53:09.842241 <6>[ 2.379726] NET: Registered PF_CAN protocol family
678 23:53:09.847567 <6>[ 2.384967] can: raw protocol
679 23:53:09.853287 <6>[ 2.388292] can: broadcast manager protocol
680 23:53:09.860293 <6>[ 2.392888] can: netlink gateway - max_hops=1
681 23:53:09.860850 <5>[ 2.398380] Key type dns_resolver registered
682 23:53:09.865955 <6>[ 2.403460] ThumbEE CPU extension supported.
683 23:53:09.872288 <5>[ 2.408144] Registering SWP/SWPB emulation handler
684 23:53:09.880359 <3>[ 2.413843] omap_voltage_late_init: Voltage driver support not added
685 23:53:10.077154 <5>[ 2.612256] Loading compiled-in X.509 certificates
686 23:53:10.213203 <6>[ 2.737784] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
687 23:53:10.220410 <6>[ 2.754460] pinctrl-single 44e10800.pinmux: 142 pins, size 568
688 23:53:10.246695 <3>[ 2.778237] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
689 23:53:10.455279 <3>[ 2.986896] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
690 23:53:10.665465 <6>[ 3.202299] OMAP GPIO hardware version 0.1
691 23:53:10.686023 <6>[ 3.220938] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
692 23:53:10.770474 <4>[ 3.305200] at24 2-0054: supply vcc not found, using dummy regulator
693 23:53:10.818526 <4>[ 3.353200] at24 2-0055: supply vcc not found, using dummy regulator
694 23:53:10.853747 <4>[ 3.388522] at24 2-0056: supply vcc not found, using dummy regulator
695 23:53:10.894622 <4>[ 3.428404] at24 2-0057: supply vcc not found, using dummy regulator
696 23:53:10.929798 <6>[ 3.465173] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
697 23:53:11.008262 <3>[ 3.539092] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
698 23:53:11.032255 <6>[ 3.559911] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
699 23:53:11.055149 <4>[ 3.586091] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
700 23:53:11.062051 <4>[ 3.595267] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
701 23:53:11.177550 <6>[ 3.712264] omap_rng 48310000.rng: Random Number Generator ver. 20
702 23:53:11.201273 <5>[ 3.738558] random: crng init done
703 23:53:11.243761 <6>[ 3.781099] Freeing initrd memory: 14444K
704 23:53:11.252604 <6>[ 3.785855] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
705 23:53:11.302716 <6>[ 3.834065] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
706 23:53:11.308600 <6>[ 3.844412] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
707 23:53:11.316681 <6>[ 3.851779] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
708 23:53:11.328231 <6>[ 3.859227] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
709 23:53:11.336551 <6>[ 3.867360] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
710 23:53:11.349555 <6>[ 3.878997] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5c:d5:d8
711 23:53:11.357191 <5>[ 3.888012] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
712 23:53:11.385880 <3>[ 3.917806] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
713 23:53:11.391682 <6>[ 3.926401] edma 49000000.dma: TI EDMA DMA engine driver
714 23:53:11.461984 <3>[ 3.994023] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
715 23:53:11.476525 <6>[ 4.008385] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
716 23:53:11.489668 <3>[ 4.025507] l3-aon-clkctrl:0000:0: failed to disable
717 23:53:11.543688 <6>[ 4.075557] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
718 23:53:11.549524 <6>[ 4.085055] printk: legacy console [ttyS0] enabled
719 23:53:11.552204 <6>[ 4.085055] printk: legacy console [ttyS0] enabled
720 23:53:11.557654 <6>[ 4.095394] printk: legacy bootconsole [omap8250] disabled
721 23:53:11.567420 <6>[ 4.095394] printk: legacy bootconsole [omap8250] disabled
722 23:53:11.601586 <4>[ 4.132381] tps65217-pmic: Failed to locate of_node [id: -1]
723 23:53:11.604069 <4>[ 4.139783] tps65217-bl: Failed to locate of_node [id: -1]
724 23:53:11.621758 <6>[ 4.159345] tps65217 0-0024: TPS65217 ID 0xe version 1.2
725 23:53:11.641727 <6>[ 4.166296] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
726 23:53:11.653515 <6>[ 4.179970] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
727 23:53:11.656101 <6>[ 4.191838] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
728 23:53:11.679451 <6>[ 4.211523] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
729 23:53:11.685222 <6>[ 4.220776] sdhci-omap 48060000.mmc: Got CD GPIO
730 23:53:11.692403 <4>[ 4.225969] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
731 23:53:11.708052 <4>[ 4.239549] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
732 23:53:11.714466 <4>[ 4.248266] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
733 23:53:11.723398 <4>[ 4.256854] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
734 23:53:11.846653 <6>[ 4.380948] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
735 23:53:11.883837 <6>[ 4.417188] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
736 23:53:11.896690 <6>[ 4.428072] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
737 23:53:11.902354 <6>[ 4.437040] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
738 23:53:11.951923 <6>[ 4.480753] mmc0: new high speed SDHC card at address 0001
739 23:53:11.952494 <6>[ 4.488684] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
740 23:53:11.959080 <6>[ 4.497769] mmcblk0: p1
741 23:53:11.982689 <6>[ 4.513089] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
742 23:53:12.005202 <6>[ 4.534155] mmc1: new high speed MMC card at address 0001
743 23:53:12.005748 <6>[ 4.541122] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
744 23:53:12.013685 <6>[ 4.550968] mmcblk1:
745 23:53:12.021007 <6>[ 4.554186] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
746 23:53:12.027454 <6>[ 4.561120] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
747 23:53:12.034048 <6>[ 4.568116] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
748 23:53:14.070699 <6>[ 6.602636] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
749 23:53:14.203920 <5>[ 6.641591] Sending DHCP requests ., OK
750 23:53:14.215280 <6>[ 6.746037] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.23
751 23:53:14.215818 <6>[ 6.754208] IP-Config: Complete:
752 23:53:14.226565 <6>[ 6.757746] device=eth0, hwaddr=90:59:af:5c:d5:d8, ipaddr=192.168.6.23, mask=255.255.255.0, gw=192.168.6.1
753 23:53:14.232284 <6>[ 6.768264] host=192.168.6.23, domain=, nis-domain=(none)
754 23:53:14.244589 <6>[ 6.774476] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
755 23:53:14.245093 <6>[ 6.774510] nameserver0=10.255.253.1
756 23:53:14.250731 <6>[ 6.787071] clk: Disabling unused clocks
757 23:53:14.256453 <6>[ 6.791790] PM: genpd: Disabling unused power domains
758 23:53:14.275593 <6>[ 6.809930] Freeing unused kernel image (initmem) memory: 2048K
759 23:53:14.283027 <6>[ 6.819694] Run /init as init process
760 23:53:14.309072 Loading, please wait...
761 23:53:14.384306 Starting systemd-udevd version 252.22-1~deb12u1
762 23:53:17.453425 <4>[ 9.983806] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
763 23:53:17.602696 <4>[ 10.133139] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
764 23:53:17.735496 <6>[ 10.273380] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
765 23:53:17.746154 <6>[ 10.279056] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
766 23:53:17.919337 <6>[ 10.455749] hub 1-0:1.0: USB hub found
767 23:53:17.995522 <6>[ 10.531746] hub 1-0:1.0: 1 port detected
768 23:53:18.118009 <6>[ 10.654031] tda998x 0-0070: found TDA19988
769 23:53:20.966195 Begin: Loading essential drivers ... done.
770 23:53:20.971669 Begin: Running /scripts/init-premount ... done.
771 23:53:20.977207 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
772 23:53:20.985471 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
773 23:53:20.991146 Device /sys/class/net/eth0 found
774 23:53:20.991588 done.
775 23:53:21.065686 Begin: Waiting up to 180 secs for any network device to become available ... done.
776 23:53:21.136799 IP-Config: eth0 hardware address 90:59:af:5c:d5:d8 mtu 1500 DHCP
777 23:53:21.238825 IP-Config: eth0 guessed broadcast address 192.168.6.255
778 23:53:21.244335 IP-Config: eth0 complete (dhcp from 192.168.6.1):
779 23:53:21.249881 address: 192.168.6.23 broadcast: 192.168.6.255 netmask: 255.255.255.0
780 23:53:21.261254 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
781 23:53:21.262200 rootserver: 192.168.6.1 rootpath:
782 23:53:21.264792 filename :
783 23:53:21.324634 done.
784 23:53:21.332138 Begin: Running /scripts/nfs-bottom ... done.
785 23:53:21.407333 Begin: Running /scripts/init-bottom ... done.
786 23:53:22.852108 <30>[ 15.385859] systemd[1]: System time before build time, advancing clock.
787 23:53:23.034859 <30>[ 15.542543] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
788 23:53:23.043460 <30>[ 15.579207] systemd[1]: Detected architecture arm.
789 23:53:23.055911
790 23:53:23.056491 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
791 23:53:23.056913
792 23:53:23.087239 <30>[ 15.621799] systemd[1]: Hostname set to <debian-bookworm-armhf>.
793 23:53:25.484401 <30>[ 18.018258] systemd[1]: Queued start job for default target graphical.target.
794 23:53:25.501889 <30>[ 18.033366] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
795 23:53:25.509383 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
796 23:53:25.532924 <30>[ 18.064617] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
797 23:53:25.541436 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
798 23:53:25.563298 <30>[ 18.095003] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
799 23:53:25.571715 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
800 23:53:25.591817 <30>[ 18.123571] systemd[1]: Created slice user.slice - User and Session Slice.
801 23:53:25.598506 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
802 23:53:25.626907 <30>[ 18.152991] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
803 23:53:25.633094 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
804 23:53:25.650849 <30>[ 18.182724] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
805 23:53:25.659885 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
806 23:53:25.692016 <30>[ 18.212807] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
807 23:53:25.698596 <30>[ 18.233330] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
808 23:53:25.705897 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
809 23:53:25.730074 <30>[ 18.262138] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
810 23:53:25.738314 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
811 23:53:25.760803 <30>[ 18.292547] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
812 23:53:25.769362 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
813 23:53:25.790728 <30>[ 18.322755] systemd[1]: Reached target paths.target - Path Units.
814 23:53:25.795829 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
815 23:53:25.820267 <30>[ 18.352317] systemd[1]: Reached target remote-fs.target - Remote File Systems.
816 23:53:25.827671 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
817 23:53:25.850224 <30>[ 18.382197] systemd[1]: Reached target slices.target - Slice Units.
818 23:53:25.855628 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
819 23:53:25.880523 <30>[ 18.412439] systemd[1]: Reached target swap.target - Swaps.
820 23:53:25.884558 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
821 23:53:25.910659 <30>[ 18.442376] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
822 23:53:25.918525 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
823 23:53:25.941666 <30>[ 18.473262] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
824 23:53:25.950828 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
825 23:53:26.030684 <30>[ 18.557582] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
826 23:53:26.043314 <30>[ 18.574976] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
827 23:53:26.051601 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
828 23:53:26.072609 <30>[ 18.605892] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
829 23:53:26.084655 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
830 23:53:26.113797 <30>[ 18.644443] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
831 23:53:26.120960 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
832 23:53:26.151632 <30>[ 18.682393] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
833 23:53:26.156984 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
834 23:53:26.181592 <30>[ 18.713255] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
835 23:53:26.190242 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
836 23:53:26.217729 <30>[ 18.743434] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
837 23:53:26.234275 <30>[ 18.760061] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
838 23:53:26.284389 <30>[ 18.816988] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
839 23:53:26.315226 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
840 23:53:26.370337 <30>[ 18.902841] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
841 23:53:26.432978 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
842 23:53:26.501180 <30>[ 19.032848] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
843 23:53:26.538788 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
844 23:53:26.590295 <30>[ 19.123060] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
845 23:53:26.613350 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
846 23:53:26.672264 <30>[ 19.204876] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
847 23:53:26.699115 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
848 23:53:26.751170 <30>[ 19.284366] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
849 23:53:26.776759 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
850 23:53:26.830718 <30>[ 19.363611] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
851 23:53:26.860229 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
852 23:53:26.909848 <30>[ 19.443448] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
853 23:53:26.929877 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
854 23:53:26.952958 <30>[ 19.485853] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
855 23:53:26.975419 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
856 23:53:27.006549 <28>[ 19.534234] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
857 23:53:27.021545 <28>[ 19.553501] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
858 23:53:27.070633 <30>[ 19.602726] systemd[1]: Starting systemd-journald.service - Journal Service...
859 23:53:27.077114 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
860 23:53:27.151615 <30>[ 19.685154] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
861 23:53:27.179880 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
862 23:53:27.224599 <30>[ 19.757423] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
863 23:53:27.271046 Starting [0;1;39msystemd-network-g… units from Kernel command line...
864 23:53:27.323834 <30>[ 19.855143] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
865 23:53:27.379268 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
866 23:53:27.443931 <30>[ 19.976000] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
867 23:53:27.490066 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
868 23:53:27.571050 <30>[ 20.103995] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
869 23:53:27.620023 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
870 23:53:27.641029 <30>[ 20.173807] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
871 23:53:27.664567 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
872 23:53:27.684697 <30>[ 20.216393] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
873 23:53:27.716776 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
874 23:53:27.873022 <30>[ 20.406423] systemd[1]: modprobe@configfs.service: Deactivated successfully.
875 23:53:27.910889 <30>[ 20.443355] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
876 23:53:27.939980 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
877 23:53:27.959821 <30>[ 20.494358] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
878 23:53:27.992986 <30>[ 20.525736] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
879 23:53:28.019453 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
880 23:53:28.041210 <30>[ 20.573373] systemd[1]: Started systemd-journald.service - Journal Service.
881 23:53:28.048053 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
882 23:53:28.081090 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
883 23:53:28.109435 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
884 23:53:28.140420 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
885 23:53:28.173709 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
886 23:53:28.203728 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
887 23:53:28.222416 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
888 23:53:28.241921 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
889 23:53:28.270206 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
890 23:53:28.329720 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
891 23:53:28.371066 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
892 23:53:28.444799 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
893 23:53:28.521637 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
894 23:53:28.570607 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
895 23:53:28.732479 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
896 23:53:28.769804 <46>[ 21.302470] systemd-journald[163]: Received client request to flush runtime journal.
897 23:53:28.874715 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
898 23:53:28.972258 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
899 23:53:29.882980 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
900 23:53:29.955895 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
901 23:53:30.448631 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
902 23:53:30.603446 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
903 23:53:30.631859 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
904 23:53:30.649556 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
905 23:53:30.738774 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
906 23:53:30.811440 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
907 23:53:31.722443 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
908 23:53:31.791294 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
909 23:53:31.890228 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
910 23:53:31.951176 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
911 23:53:31.990137 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
912 23:53:33.093076 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
913 23:53:34.445468 <5>[ 26.979280] cfg80211: Loading compiled-in X.509 certificates for regulatory database
914 23:53:34.745671 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
915 23:53:35.701116 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
916 23:53:36.021495 <5>[ 28.552430] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
917 23:53:36.026891 <5>[ 28.560562] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
918 23:53:36.039076 <4>[ 28.572120] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
919 23:53:36.045077 <6>[ 28.581097] cfg80211: failed to load regulatory.db
920 23:53:36.523875 <46>[ 29.048219] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
921 23:53:36.666477 <46>[ 29.192943] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
922 23:53:36.781999 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
923 23:53:37.245500 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
924 23:53:45.862090 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
925 23:53:45.890804 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
926 23:53:45.910794 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
927 23:53:45.933292 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
928 23:53:45.999786 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
929 23:53:46.044175 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
930 23:53:46.081563 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
931 23:53:46.124035 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
932 23:53:46.201398 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
933 23:53:46.238191 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
934 23:53:46.267113 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
935 23:53:46.294609 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
936 23:53:46.336531 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
937 23:53:46.367727 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
938 23:53:46.403504 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
939 23:53:46.431555 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
940 23:53:46.467987 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
941 23:53:46.495127 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
942 23:53:46.521539 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
943 23:53:46.542900 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
944 23:53:46.589989 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
945 23:53:46.608290 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
946 23:53:46.632600 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
947 23:53:46.710341 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
948 23:53:46.755913 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
949 23:53:46.859043 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
950 23:53:46.922560 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
951 23:53:47.001077 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
952 23:53:47.043237 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
953 23:53:47.084639 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
954 23:53:47.263116 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
955 23:53:47.339783 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
956 23:53:47.409884 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
957 23:53:47.428040 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
958 23:53:47.451202 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
959 23:53:47.648872 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
960 23:53:47.969334 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
961 23:53:48.011647 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
962 23:53:48.044540 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
963 23:53:48.134765 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
964 23:53:48.303625 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
965 23:53:48.465284
966 23:53:48.468283 Debian GNU/Linux 12 debian-brm-armhf login: root (automatic login)
967 23:53:48.468588
968 23:53:48.760672 Linux debian-bookworm-armhf 6.12.0-rc2 #1 SMP Wed Nov 6 23:15:22 UTC 2024 armv7l
969 23:53:48.761257
970 23:53:48.766398 The programs included with the Debian GNU/Linux system are free software;
971 23:53:48.769590 the exact distribution terms for each program are described in the
972 23:53:48.775234 individual files in /usr/share/doc/*/copyright.
973 23:53:48.775735
974 23:53:48.780847 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
975 23:53:48.785537 permitted by applicable law.
976 23:53:53.403102 Unable to match end of the kernel message
978 23:53:53.404643 Setting prompt string to ['/ #']
979 23:53:53.405222 end: 2.4.4.1 login-action (duration 00:00:46) [common]
981 23:53:53.406695 end: 2.4.4 auto-login-action (duration 00:00:47) [common]
982 23:53:53.407244 start: 2.4.5 expect-shell-connection (timeout 00:03:11) [common]
983 23:53:53.407710 Setting prompt string to ['/ #']
984 23:53:53.408128 Forcing a shell prompt, looking for ['/ #']
986 23:53:53.459107 / #
987 23:53:53.459858 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
988 23:53:53.460546 Waiting using forced prompt support (timeout 00:02:30)
989 23:53:53.464380
990 23:53:53.470655 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
991 23:53:53.471252 start: 2.4.6 export-device-env (timeout 00:03:11) [common]
992 23:53:53.471746 Sending with 10 millisecond of delay
994 23:53:58.460742 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/949962/extract-nfsrootfs-9ry9sv6z'
995 23:53:58.471659 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/949962/extract-nfsrootfs-9ry9sv6z'
996 23:53:58.473063 Sending with 10 millisecond of delay
998 23:54:00.572529 / # export NFS_SERVER_IP='192.168.6.3'
999 23:54:00.583477 export NFS_SERVER_IP='192.168.6.3'
1000 23:54:00.584903 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1001 23:54:00.585509 end: 2.4 uboot-commands (duration 00:01:56) [common]
1002 23:54:00.586125 end: 2 uboot-action (duration 00:01:56) [common]
1003 23:54:00.586698 start: 3 lava-test-retry (timeout 00:06:52) [common]
1004 23:54:00.587280 start: 3.1 lava-test-shell (timeout 00:06:52) [common]
1005 23:54:00.587774 Using namespace: common
1007 23:54:00.688963 / # #
1008 23:54:00.689805 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1009 23:54:00.694586 #
1010 23:54:00.699759 Using /lava-949962
1012 23:54:00.800890 / # export SHELL=/bin/bash
1013 23:54:00.805455 export SHELL=/bin/bash
1015 23:54:00.913655 / # . /lava-949962/environment
1016 23:54:00.919230 . /lava-949962/environment
1018 23:54:01.032208 / # /lava-949962/bin/lava-test-runner /lava-949962/0
1019 23:54:01.033051 Test shell timeout: 10s (minimum of the action and connection timeout)
1020 23:54:01.037620 /lava-949962/bin/lava-test-runner /lava-949962/0
1021 23:54:01.426592 + export TESTRUN_ID=0_timesync-off
1022 23:54:01.434717 + TESTRUN_ID=0_timesync-off
1023 23:54:01.435212 + cd /lava-949962/0/tests/0_timesync-off
1024 23:54:01.435642 ++ cat uuid
1025 23:54:01.450573 + UUID=949962_1.6.2.4.1
1026 23:54:01.451062 + set +x
1027 23:54:01.459169 <LAVA_SIGNAL_STARTRUN 0_timesync-off 949962_1.6.2.4.1>
1028 23:54:01.459630 + systemctl stop systemd-timesyncd
1029 23:54:01.460328 Received signal: <STARTRUN> 0_timesync-off 949962_1.6.2.4.1
1030 23:54:01.460768 Starting test lava.0_timesync-off (949962_1.6.2.4.1)
1031 23:54:01.461290 Skipping test definition patterns.
1032 23:54:01.748386 + set +x
1033 23:54:01.748940 <LAVA_SIGNAL_ENDRUN 0_timesync-off 949962_1.6.2.4.1>
1034 23:54:01.749616 Received signal: <ENDRUN> 0_timesync-off 949962_1.6.2.4.1
1035 23:54:01.750154 Ending use of test pattern.
1036 23:54:01.750571 Ending test lava.0_timesync-off (949962_1.6.2.4.1), duration 0.29
1038 23:54:01.960999 + export TESTRUN_ID=1_kselftest-dt
1039 23:54:01.968278 + TESTRUN_ID=1_kselftest-dt
1040 23:54:01.968769 + cd /lava-949962/0/tests/1_kselftest-dt
1041 23:54:01.969193 ++ cat uuid
1042 23:54:01.984757 + UUID=949962_1.6.2.4.5
1043 23:54:01.985233 + set +x
1044 23:54:01.990320 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 949962_1.6.2.4.5>
1045 23:54:01.990785 + cd ./automated/linux/kselftest/
1046 23:54:01.991461 Received signal: <STARTRUN> 1_kselftest-dt 949962_1.6.2.4.5
1047 23:54:01.991891 Starting test lava.1_kselftest-dt (949962_1.6.2.4.5)
1048 23:54:01.992397 Skipping test definition patterns.
1049 23:54:02.020254 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-230-g1aed5b247ee28/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1050 23:54:02.128027 INFO: install_deps skipped
1051 23:54:02.671032 --2024-11-06 23:54:02-- http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-230-g1aed5b247ee28/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1052 23:54:02.931010 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1053 23:54:03.072151 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1054 23:54:03.212713 HTTP request sent, awaiting response... 200 OK
1055 23:54:03.213244 Length: 4097908 (3.9M) [application/octet-stream]
1056 23:54:03.218287 Saving to: 'kselftest_armhf.tar.gz'
1057 23:54:03.218751
1058 23:54:04.828090
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 180KB/s
kselftest_armhf.tar 4%[ ] 194.76K 341KB/s
kselftest_armhf.tar 18%[==> ] 750.23K 902KB/s
kselftest_armhf.tar 25%[====> ] 1.01M 979KB/s
kselftest_armhf.tar 59%[==========> ] 2.31M 1.83MB/s
kselftest_armhf.tar 81%[===============> ] 3.17M 2.02MB/s
kselftest_armhf.tar 100%[===================>] 3.91M 2.43MB/s in 1.6s
1059 23:54:04.828707
1060 23:54:05.393320 2024-11-06 23:54:04 (2.43 MB/s) - 'kselftest_armhf.tar.gz' saved [4097908/4097908]
1061 23:54:05.393975
1062 23:54:20.495160 skiplist:
1063 23:54:20.495584 ========================================
1064 23:54:20.500768 ========================================
1065 23:54:20.612523 dt:test_unprobed_devices.sh
1066 23:54:20.646953 ============== Tests to run ===============
1067 23:54:20.654883 dt:test_unprobed_devices.sh
1068 23:54:20.658716 ===========End Tests to run ===============
1069 23:54:20.667782 shardfile-dt pass
1070 23:54:20.892953 <12>[ 73.431318] kselftest: Running tests in dt
1071 23:54:20.920608 TAP version 13
1072 23:54:20.943940 1..1
1073 23:54:20.996553 # timeout set to 45
1074 23:54:20.997138 # selftests: dt: test_unprobed_devices.sh
1075 23:54:21.944492 # TAP version 13
1076 23:54:46.678048 # 1..257
1077 23:54:46.856799 # ok 1 / # SKIP
1078 23:54:46.878268 # ok 2 /clk_mcasp0
1079 23:54:46.944772 # ok 3 /clk_mcasp0_fixed # SKIP
1080 23:54:47.019187 # ok 4 /cpus/cpu@0 # SKIP
1081 23:54:47.086648 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1082 23:54:47.110139 # ok 6 /fixedregulator0
1083 23:54:47.126992 # ok 7 /leds
1084 23:54:47.148215 # ok 8 /ocp
1085 23:54:47.176843 # ok 9 /ocp/interconnect@44c00000
1086 23:54:47.200261 # ok 10 /ocp/interconnect@44c00000/segment@0
1087 23:54:47.219370 # ok 11 /ocp/interconnect@44c00000/segment@100000
1088 23:54:47.247925 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1089 23:54:47.318876 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1090 23:54:47.339029 # ok 14 /ocp/interconnect@44c00000/segment@200000
1091 23:54:47.362097 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1092 23:54:47.464881 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1093 23:54:47.540985 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1094 23:54:47.612895 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1095 23:54:47.684295 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1096 23:54:47.756411 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1097 23:54:47.826443 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1098 23:54:47.894164 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1099 23:54:47.967630 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1100 23:54:48.036869 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1101 23:54:48.110332 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1102 23:54:48.181312 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1103 23:54:48.256421 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1104 23:54:48.326121 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1105 23:54:48.398917 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1106 23:54:48.466287 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1107 23:54:48.537976 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1108 23:54:48.608066 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1109 23:54:48.683974 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1110 23:54:48.754159 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1111 23:54:48.826591 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1112 23:54:48.893522 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1113 23:54:48.965071 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1114 23:54:49.039429 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1115 23:54:49.107330 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1116 23:54:49.183805 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1117 23:54:49.255195 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1118 23:54:49.327358 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1119 23:54:49.397667 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1120 23:54:49.466868 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1121 23:54:49.540654 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1122 23:54:49.617161 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1123 23:54:49.696233 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1124 23:54:49.769839 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1125 23:54:49.843018 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1126 23:54:49.915848 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1127 23:54:49.987783 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1128 23:54:50.054877 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1129 23:54:50.126903 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1130 23:54:50.202872 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1131 23:54:50.270038 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1132 23:54:50.342056 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1133 23:54:50.413714 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1134 23:54:50.484522 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1135 23:54:50.556803 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1136 23:54:50.634338 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1137 23:54:50.701211 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1138 23:54:50.772333 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1139 23:54:50.842348 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1140 23:54:50.915259 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1141 23:54:50.986444 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1142 23:54:51.057508 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1143 23:54:51.134317 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1144 23:54:51.205418 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1145 23:54:51.276687 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1146 23:54:51.344561 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1147 23:54:51.416484 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1148 23:54:51.489565 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1149 23:54:51.563257 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1150 23:54:51.636054 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1151 23:54:51.712120 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1152 23:54:51.779865 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1153 23:54:51.851817 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1154 23:54:51.923012 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1155 23:54:51.993348 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1156 23:54:52.065665 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1157 23:54:52.139694 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1158 23:54:52.208009 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1159 23:54:52.280087 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1160 23:54:52.351832 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1161 23:54:52.423417 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1162 23:54:52.495237 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1163 23:54:52.570638 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1164 23:54:52.642777 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1165 23:54:52.716769 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1166 23:54:52.784447 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1167 23:54:52.853200 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1168 23:54:52.926486 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1169 23:54:52.999048 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1170 23:54:53.070754 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1171 23:54:53.092063 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1172 23:54:53.120687 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1173 23:54:53.145010 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1174 23:54:53.173007 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1175 23:54:53.194073 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1176 23:54:53.222031 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1177 23:54:53.239066 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1178 23:54:53.262209 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1179 23:54:53.368087 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1180 23:54:53.393200 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1181 23:54:53.422268 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1182 23:54:53.445573 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1183 23:54:53.551692 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1184 23:54:53.627220 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1185 23:54:53.698304 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1186 23:54:53.767478 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1187 23:54:53.840473 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1188 23:54:53.911250 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1189 23:54:53.982506 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1190 23:54:54.053581 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1191 23:54:54.124721 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1192 23:54:54.198064 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1193 23:54:54.270138 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1194 23:54:54.342243 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1195 23:54:54.412015 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1196 23:54:54.485888 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1197 23:54:54.564357 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1198 23:54:54.637354 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1199 23:54:54.655072 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1200 23:54:54.724894 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1201 23:54:54.799454 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1202 23:54:54.866223 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1203 23:54:54.888554 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1204 23:54:54.960090 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1205 23:54:54.982486 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1206 23:54:55.054980 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1207 23:54:55.079953 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1208 23:54:55.104135 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1209 23:54:55.123978 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1210 23:54:55.146955 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1211 23:54:55.173459 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1212 23:54:55.194392 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1213 23:54:55.223563 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1214 23:54:55.297016 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1215 23:54:55.314050 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1216 23:54:55.337503 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1217 23:54:55.408898 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1218 23:54:55.479512 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1219 23:54:55.500401 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1220 23:54:55.600796 # not ok 144 /ocp/interconnect@47c00000
1221 23:54:55.677071 # not ok 145 /ocp/interconnect@47c00000/segment@0
1222 23:54:55.697956 # ok 146 /ocp/interconnect@48000000
1223 23:54:55.720915 # ok 147 /ocp/interconnect@48000000/segment@0
1224 23:54:55.741412 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1225 23:54:55.769525 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1226 23:54:55.792855 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1227 23:54:55.813546 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1228 23:54:55.839549 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1229 23:54:55.863595 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1230 23:54:55.883627 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1231 23:54:55.953909 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1232 23:54:56.025828 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1233 23:54:56.052052 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1234 23:54:56.074193 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1235 23:54:56.095052 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1236 23:54:56.123855 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1237 23:54:56.143765 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1238 23:54:56.170534 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1239 23:54:56.193097 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1240 23:54:56.212689 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1241 23:54:56.234553 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1242 23:54:56.263290 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1243 23:54:56.283618 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1244 23:54:56.310743 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1245 23:54:56.333029 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1246 23:54:56.354208 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1247 23:54:56.375732 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1248 23:54:56.403853 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1249 23:54:56.423827 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1250 23:54:56.446961 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1251 23:54:56.467260 # ok 175 /ocp/interconnect@48000000/segment@100000
1252 23:54:56.492158 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1253 23:54:56.520849 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1254 23:54:56.594193 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1255 23:54:56.667674 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1256 23:54:56.736286 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1257 23:54:56.806329 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1258 23:54:56.877028 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1259 23:54:56.949015 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1260 23:54:57.019965 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1261 23:54:57.092402 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1262 23:54:57.111763 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1263 23:54:57.139640 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1264 23:54:57.163913 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1265 23:54:57.183553 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1266 23:54:57.207098 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1267 23:54:57.231063 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1268 23:54:57.255351 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1269 23:54:57.282805 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1270 23:54:57.303979 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1271 23:54:57.328915 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1272 23:54:57.352487 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1273 23:54:57.374618 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1274 23:54:57.393141 # ok 198 /ocp/interconnect@48000000/segment@200000
1275 23:54:57.417995 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1276 23:54:57.494686 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1277 23:54:57.510173 # ok 201 /ocp/interconnect@48000000/segment@300000
1278 23:54:57.534404 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1279 23:54:57.562507 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1280 23:54:57.584584 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1281 23:54:57.609924 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1282 23:54:57.633200 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1283 23:54:57.654116 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1284 23:54:57.723757 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1285 23:54:57.741410 # ok 209 /ocp/interconnect@4a000000
1286 23:54:57.769603 # ok 210 /ocp/interconnect@4a000000/segment@0
1287 23:54:57.790069 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1288 23:54:57.819457 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1289 23:54:57.844283 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1290 23:54:57.863618 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1291 23:54:57.933734 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1292 23:54:58.039603 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1293 23:54:58.111721 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1294 23:54:58.215706 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1295 23:54:58.285609 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1296 23:54:58.356534 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1297 23:54:58.459623 # not ok 221 /ocp/interconnect@4b140000
1298 23:54:58.531684 # not ok 222 /ocp/interconnect@4b140000/segment@0
1299 23:54:58.598045 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1300 23:54:58.621122 # ok 224 /ocp/target-module@40300000
1301 23:54:58.644215 # ok 225 /ocp/target-module@40300000/sram@0
1302 23:54:58.719693 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1303 23:54:58.790731 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1304 23:54:58.810119 # ok 228 /ocp/target-module@47400000
1305 23:54:58.830144 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1306 23:54:58.856865 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1307 23:54:58.879223 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1308 23:54:58.897349 # ok 232 /ocp/target-module@47400000/usb@1400
1309 23:54:58.921833 # ok 233 /ocp/target-module@47400000/usb@1800
1310 23:54:58.945886 # ok 234 /ocp/target-module@47810000
1311 23:54:58.963901 # ok 235 /ocp/target-module@49000000
1312 23:54:58.990697 # ok 236 /ocp/target-module@49000000/dma@0
1313 23:54:59.012227 # ok 237 /ocp/target-module@49800000
1314 23:54:59.030143 # ok 238 /ocp/target-module@49800000/dma@0
1315 23:54:59.052952 # ok 239 /ocp/target-module@49900000
1316 23:54:59.079946 # ok 240 /ocp/target-module@49900000/dma@0
1317 23:54:59.100821 # ok 241 /ocp/target-module@49a00000
1318 23:54:59.121314 # ok 242 /ocp/target-module@49a00000/dma@0
1319 23:54:59.146739 # ok 243 /ocp/target-module@4c000000
1320 23:54:59.219388 # not ok 244 /ocp/target-module@4c000000/emif@0
1321 23:54:59.236177 # ok 245 /ocp/target-module@50000000
1322 23:54:59.260849 # ok 246 /ocp/target-module@53100000
1323 23:54:59.332057 # not ok 247 /ocp/target-module@53100000/sham@0
1324 23:54:59.357068 # ok 248 /ocp/target-module@53500000
1325 23:54:59.422350 # not ok 249 /ocp/target-module@53500000/aes@0
1326 23:54:59.448521 # ok 250 /ocp/target-module@56000000
1327 23:54:59.548421 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1328 23:54:59.620196 # ok 252 /opp-table # SKIP
1329 23:54:59.695944 # ok 253 /soc # SKIP
1330 23:54:59.711526 # ok 254 /sound
1331 23:54:59.734766 # ok 255 /target-module@4b000000
1332 23:54:59.762612 # ok 256 /target-module@4b000000/target-module@140000
1333 23:54:59.782146 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1334 23:54:59.790570 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1335 23:54:59.798423 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1336 23:55:01.936564 dt_test_unprobed_devices_sh_ skip
1337 23:55:01.942238 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1338 23:55:01.947717 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1339 23:55:01.948235 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1340 23:55:01.953312 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1341 23:55:01.958886 dt_test_unprobed_devices_sh_fixedregulator0 pass
1342 23:55:01.964556 dt_test_unprobed_devices_sh_leds pass
1343 23:55:01.965002 dt_test_unprobed_devices_sh_ocp pass
1344 23:55:01.970146 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1345 23:55:01.975891 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1346 23:55:01.981309 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1347 23:55:01.992604 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1348 23:55:01.998211 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1349 23:55:02.003757 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1350 23:55:02.014958 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1351 23:55:02.020494 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1352 23:55:02.031993 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1353 23:55:02.042944 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1354 23:55:02.054272 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1355 23:55:02.059992 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1356 23:55:02.070982 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1357 23:55:02.082273 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1358 23:55:02.093580 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1359 23:55:02.104741 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1360 23:55:02.110221 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1361 23:55:02.121455 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1362 23:55:02.132808 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1363 23:55:02.143975 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1364 23:55:02.155132 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1365 23:55:02.160775 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1366 23:55:02.171905 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1367 23:55:02.183117 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1368 23:55:02.194324 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1369 23:55:02.199888 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1370 23:55:02.211051 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1371 23:55:02.222238 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1372 23:55:02.233430 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1373 23:55:02.244655 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1374 23:55:02.250231 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1375 23:55:02.261385 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1376 23:55:02.272627 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1377 23:55:02.283863 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1378 23:55:02.294957 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1379 23:55:02.306244 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1380 23:55:02.317399 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1381 23:55:02.328528 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1382 23:55:02.339760 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1383 23:55:02.350913 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1384 23:55:02.362245 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1385 23:55:02.373345 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1386 23:55:02.384548 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1387 23:55:02.395765 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1388 23:55:02.406884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1389 23:55:02.418043 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1390 23:55:02.429359 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1391 23:55:02.440406 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1392 23:55:02.451777 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1393 23:55:02.462869 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1394 23:55:02.474092 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1395 23:55:02.485261 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1396 23:55:02.496517 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1397 23:55:02.507818 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1398 23:55:02.518907 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1399 23:55:02.530085 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1400 23:55:02.535746 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1401 23:55:02.546898 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1402 23:55:02.558073 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1403 23:55:02.569282 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1404 23:55:02.580511 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1405 23:55:02.591688 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1406 23:55:02.602995 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1407 23:55:02.614120 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1408 23:55:02.625352 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1409 23:55:02.636530 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1410 23:55:02.647613 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1411 23:55:02.659034 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1412 23:55:02.670158 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1413 23:55:02.681298 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1414 23:55:02.692395 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1415 23:55:02.703664 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1416 23:55:02.714813 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1417 23:55:02.726065 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1418 23:55:02.731652 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1419 23:55:02.742931 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1420 23:55:02.754047 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1421 23:55:02.765207 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1422 23:55:02.776487 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1423 23:55:02.782098 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1424 23:55:02.798839 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1425 23:55:02.809854 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1426 23:55:02.815595 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1427 23:55:02.832319 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1428 23:55:02.843514 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1429 23:55:02.854790 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1430 23:55:02.860465 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1431 23:55:02.871545 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1432 23:55:02.882778 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1433 23:55:02.888332 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1434 23:55:02.899554 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1435 23:55:02.910769 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1436 23:55:02.916350 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1437 23:55:02.927585 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1438 23:55:02.933027 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1439 23:55:02.944269 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1440 23:55:02.955533 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1441 23:55:02.966758 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1442 23:55:02.977954 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1443 23:55:02.989390 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1444 23:55:03.000179 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1445 23:55:03.011477 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1446 23:55:03.022605 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1447 23:55:03.033913 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1448 23:55:03.044996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1449 23:55:03.056141 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1450 23:55:03.067368 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1451 23:55:03.084182 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1452 23:55:03.095388 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1453 23:55:03.106545 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1454 23:55:03.117852 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1455 23:55:03.128957 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1456 23:55:03.145755 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1457 23:55:03.156931 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1458 23:55:03.168165 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1459 23:55:03.179418 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1460 23:55:03.185051 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1461 23:55:03.196301 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1462 23:55:03.207570 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1463 23:55:03.213148 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1464 23:55:03.224315 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1465 23:55:03.230077 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1466 23:55:03.241258 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1467 23:55:03.246988 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1468 23:55:03.258155 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1469 23:55:03.263658 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1470 23:55:03.274972 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1471 23:55:03.280497 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1472 23:55:03.291574 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1473 23:55:03.302844 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1474 23:55:03.314058 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1475 23:55:03.325212 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1476 23:55:03.336482 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1477 23:55:03.341946 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1478 23:55:03.353219 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1479 23:55:03.358758 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1480 23:55:03.364436 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1481 23:55:03.369931 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1482 23:55:03.375518 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1483 23:55:03.381201 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1484 23:55:03.392391 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1485 23:55:03.398170 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1486 23:55:03.403656 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1487 23:55:03.414896 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1488 23:55:03.420309 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1489 23:55:03.431509 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1490 23:55:03.437111 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1491 23:55:03.448322 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1492 23:55:03.453882 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1493 23:55:03.465209 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1494 23:55:03.470807 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1495 23:55:03.482115 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1496 23:55:03.487622 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1497 23:55:03.498835 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1498 23:55:03.504432 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1499 23:55:03.515615 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1500 23:55:03.521252 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1501 23:55:03.526799 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1502 23:55:03.538194 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1503 23:55:03.543583 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1504 23:55:03.554702 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1505 23:55:03.560352 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1506 23:55:03.571550 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1507 23:55:03.577083 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1508 23:55:03.588351 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1509 23:55:03.593938 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1510 23:55:03.599546 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1511 23:55:03.610788 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1512 23:55:03.616396 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1513 23:55:03.627602 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1514 23:55:03.638759 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1515 23:55:03.649981 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1516 23:55:03.661200 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1517 23:55:03.672334 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1518 23:55:03.683765 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1519 23:55:03.694752 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1520 23:55:03.706092 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1521 23:55:03.711672 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1522 23:55:03.722771 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1523 23:55:03.728601 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1524 23:55:03.739733 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1525 23:55:03.745221 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1526 23:55:03.756372 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1527 23:55:03.761896 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1528 23:55:03.773029 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1529 23:55:03.778735 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1530 23:55:03.789865 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1531 23:55:03.795584 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1532 23:55:03.806704 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1533 23:55:03.812369 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1534 23:55:03.823507 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1535 23:55:03.829079 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1536 23:55:03.834673 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1537 23:55:03.845999 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1538 23:55:03.851528 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1539 23:55:03.862582 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1540 23:55:03.868206 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1541 23:55:03.879491 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1542 23:55:03.885118 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1543 23:55:03.896240 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1544 23:55:03.901788 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1545 23:55:03.907364 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1546 23:55:03.912988 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1547 23:55:03.924231 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1548 23:55:03.935348 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1549 23:55:03.941063 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1550 23:55:03.946645 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1551 23:55:03.957649 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1552 23:55:03.969001 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1553 23:55:03.980208 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1554 23:55:03.991387 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1555 23:55:03.997076 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1556 23:55:04.002608 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1557 23:55:04.008310 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1558 23:55:04.013954 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1559 23:55:04.019525 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1560 23:55:04.025220 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1561 23:55:04.036386 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1562 23:55:04.041953 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1563 23:55:04.047576 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1564 23:55:04.053063 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1565 23:55:04.058713 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1566 23:55:04.070034 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1567 23:55:04.075601 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1568 23:55:04.081163 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1569 23:55:04.086696 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1570 23:55:04.092285 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1571 23:55:04.097929 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1572 23:55:04.103556 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1573 23:55:04.109153 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1574 23:55:04.114715 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1575 23:55:04.120402 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1576 23:55:04.125942 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1577 23:55:04.131535 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1578 23:55:04.137185 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1579 23:55:04.142790 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1580 23:55:04.148363 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1581 23:55:04.154108 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1582 23:55:04.159709 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1583 23:55:04.165253 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1584 23:55:04.170960 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1585 23:55:04.176426 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1586 23:55:04.182062 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1587 23:55:04.182695 dt_test_unprobed_devices_sh_opp-table skip
1588 23:55:04.187701 dt_test_unprobed_devices_sh_soc skip
1589 23:55:04.193270 dt_test_unprobed_devices_sh_sound pass
1590 23:55:04.199009 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1591 23:55:04.204827 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1592 23:55:04.210189 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1593 23:55:04.215725 dt_test_unprobed_devices_sh fail
1594 23:55:04.216260 + ../../utils/send-to-lava.sh ./output/result.txt
1595 23:55:04.221376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1596 23:55:04.222387 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1598 23:55:04.229563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1599 23:55:04.230437 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1601 23:55:04.318622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1602 23:55:04.319590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1604 23:55:04.414916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1605 23:55:04.415834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1607 23:55:04.505437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1608 23:55:04.506200 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1610 23:55:04.600680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1611 23:55:04.601576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1613 23:55:04.690422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1614 23:55:04.691336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1616 23:55:04.781961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1617 23:55:04.782806 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1619 23:55:04.873617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1620 23:55:04.874496 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1622 23:55:04.968872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1623 23:55:04.969708 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1625 23:55:05.060659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1626 23:55:05.061502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1628 23:55:05.158696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1629 23:55:05.159589 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1631 23:55:05.335687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1632 23:55:05.336732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1634 23:55:05.431911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1635 23:55:05.432792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1637 23:55:05.525090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1638 23:55:05.525991 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1640 23:55:05.621762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1641 23:55:05.622691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1643 23:55:05.713947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1644 23:55:05.714823 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1646 23:55:05.809998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1647 23:55:05.811116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1649 23:55:05.904635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1650 23:55:05.905774 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1652 23:55:05.994820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1653 23:55:05.995692 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1655 23:55:06.086094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1656 23:55:06.086964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1658 23:55:06.177000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1659 23:55:06.177933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1661 23:55:06.267806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1662 23:55:06.268753 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1664 23:55:06.359888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1665 23:55:06.360880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1667 23:55:06.450444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1668 23:55:06.451361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1670 23:55:06.540507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1671 23:55:06.541416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1673 23:55:06.632888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1674 23:55:06.633897 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1676 23:55:06.724065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1677 23:55:06.724970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1679 23:55:06.816784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1680 23:55:06.817704 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1682 23:55:06.908077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1683 23:55:06.908990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1685 23:55:07.001788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1686 23:55:07.002462 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1688 23:55:07.094716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1689 23:55:07.095352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1691 23:55:07.186334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1692 23:55:07.186986 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1694 23:55:07.281947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1695 23:55:07.283079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1697 23:55:07.373776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1698 23:55:07.374988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1700 23:55:07.465568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1701 23:55:07.466817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1703 23:55:07.555304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1704 23:55:07.556416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1706 23:55:07.656997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1707 23:55:07.658158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1709 23:55:07.763415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1710 23:55:07.764541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1712 23:55:07.856017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1713 23:55:07.857086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1715 23:55:07.945784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1716 23:55:07.946896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1718 23:55:08.037967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1719 23:55:08.039039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1721 23:55:08.130982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1722 23:55:08.132105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1724 23:55:08.222789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1725 23:55:08.223443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1727 23:55:08.314802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1728 23:55:08.315469 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1730 23:55:08.408361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1731 23:55:08.409209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1733 23:55:08.510027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1734 23:55:08.510977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1736 23:55:08.606941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1737 23:55:08.607888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1739 23:55:08.707293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1740 23:55:08.708227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1742 23:55:08.808498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1743 23:55:08.809461 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1745 23:55:08.904072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1746 23:55:08.904719 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1748 23:55:08.996072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1749 23:55:08.996718 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1751 23:55:09.090680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1752 23:55:09.091724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1754 23:55:09.184024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1755 23:55:09.185254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1757 23:55:09.277369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1758 23:55:09.278569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1760 23:55:09.367467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1761 23:55:09.368095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1763 23:55:09.461028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1764 23:55:09.461698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1766 23:55:09.554527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1767 23:55:09.555167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1769 23:55:09.647565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1770 23:55:09.648210 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1772 23:55:09.740795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1773 23:55:09.741749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1775 23:55:09.834052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1776 23:55:09.835006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1778 23:55:09.927337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1779 23:55:09.928247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1781 23:55:10.018832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1782 23:55:10.019770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1784 23:55:10.119121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1785 23:55:10.120031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1787 23:55:10.221212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1788 23:55:10.222452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1790 23:55:10.322255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1791 23:55:10.323204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1793 23:55:10.423650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1794 23:55:10.424602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1796 23:55:10.530810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1797 23:55:10.531761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1799 23:55:10.643021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1800 23:55:10.643938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1802 23:55:10.734374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1803 23:55:10.735307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1805 23:55:10.826160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1806 23:55:10.827100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1808 23:55:10.911336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1809 23:55:10.912490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1811 23:55:11.004129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1812 23:55:11.005018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1814 23:55:11.096330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1815 23:55:11.096952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1817 23:55:11.187059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1818 23:55:11.187685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1820 23:55:11.275862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1821 23:55:11.276489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1823 23:55:11.361135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1824 23:55:11.362031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1826 23:55:11.454235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1827 23:55:11.455619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1829 23:55:11.545777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1830 23:55:11.546482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1832 23:55:11.638949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1833 23:55:11.639815 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1835 23:55:11.739565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1836 23:55:11.740425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1838 23:55:11.840407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1839 23:55:11.841264 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1841 23:55:11.934427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1842 23:55:11.935363 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1844 23:55:12.026302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1845 23:55:12.027489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1847 23:55:12.118688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1848 23:55:12.119487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1850 23:55:12.210577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1851 23:55:12.211309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1853 23:55:12.301711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1854 23:55:12.302932 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1856 23:55:12.392898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1857 23:55:12.393525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1859 23:55:12.486501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1860 23:55:12.487319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1862 23:55:12.580445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1863 23:55:12.581390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1865 23:55:12.675353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1866 23:55:12.676314 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1868 23:55:12.765201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1869 23:55:12.766176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1871 23:55:12.858237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1872 23:55:12.859157 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1874 23:55:12.948832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1875 23:55:12.949780 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1877 23:55:13.044422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1878 23:55:13.045330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1880 23:55:13.132338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1881 23:55:13.133269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1883 23:55:13.223108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1884 23:55:13.224013 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1886 23:55:13.316524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1887 23:55:13.317460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1889 23:55:13.409090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1890 23:55:13.409990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1892 23:55:13.500771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1893 23:55:13.501398 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1895 23:55:13.592653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1896 23:55:13.593300 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1898 23:55:13.683582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1899 23:55:13.684494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1901 23:55:13.773522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1902 23:55:13.774442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1904 23:55:13.864099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1905 23:55:13.864973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1907 23:55:13.955319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1908 23:55:13.956196 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1910 23:55:14.050259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1911 23:55:14.050882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1913 23:55:14.141863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1914 23:55:14.142478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1916 23:55:14.234281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1917 23:55:14.234895 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1919 23:55:14.329056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1920 23:55:14.329672 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1922 23:55:14.422021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1923 23:55:14.422639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1925 23:55:14.516120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1926 23:55:14.516756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1928 23:55:14.605782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1929 23:55:14.606418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1931 23:55:14.691582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1932 23:55:14.692178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1934 23:55:14.841983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1935 23:55:14.842636 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1937 23:55:14.935256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1938 23:55:14.936259 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1940 23:55:15.026624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1941 23:55:15.027274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1943 23:55:15.120507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1944 23:55:15.121117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1946 23:55:15.214463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1947 23:55:15.215369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1949 23:55:15.307548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1950 23:55:15.308408 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1952 23:55:15.399125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1953 23:55:15.399977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1955 23:55:15.493426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1957 23:55:15.496551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1958 23:55:15.584271 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1960 23:55:15.587357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1961 23:55:15.675693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1963 23:55:15.678774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1964 23:55:15.767706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1965 23:55:15.768466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1967 23:55:15.859095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1968 23:55:15.859882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1970 23:55:15.949571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1971 23:55:15.950364 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1973 23:55:16.042614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1974 23:55:16.043385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1976 23:55:16.133306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1977 23:55:16.134142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1979 23:55:16.228481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1980 23:55:16.229118 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1982 23:55:16.321504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1983 23:55:16.322346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1985 23:55:16.412932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1986 23:55:16.413728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1988 23:55:16.513999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1989 23:55:16.514785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1991 23:55:16.617096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1992 23:55:16.617952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1994 23:55:16.711653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1995 23:55:16.712584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1997 23:55:16.803059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1998 23:55:16.803865 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2000 23:55:16.895730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2001 23:55:16.896690 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2003 23:55:16.988004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2004 23:55:16.988928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2006 23:55:17.082459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2007 23:55:17.083333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2009 23:55:17.177085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2010 23:55:17.177932 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2012 23:55:17.268228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2013 23:55:17.269106 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2015 23:55:17.655215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2016 23:55:17.656254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2018 23:55:17.657345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2019 23:55:17.657971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2020 23:55:17.658532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2022 23:55:17.659725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2024 23:55:17.660717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2025 23:55:17.661305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2027 23:55:17.718999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2028 23:55:17.719770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2030 23:55:17.810131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2031 23:55:17.811269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2033 23:55:17.898980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2034 23:55:17.899992 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2036 23:55:17.992521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2037 23:55:17.993394 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2039 23:55:18.084373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2040 23:55:18.085305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2042 23:55:18.175421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2043 23:55:18.176337 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2045 23:55:18.269800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2046 23:55:18.270831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2048 23:55:18.360811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2049 23:55:18.361804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2051 23:55:18.453117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2052 23:55:18.454147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2054 23:55:18.555451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2055 23:55:18.556471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2057 23:55:18.647806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2058 23:55:18.648731 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2060 23:55:18.739978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2061 23:55:18.740850 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2063 23:55:18.829804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2064 23:55:18.830702 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2066 23:55:18.920929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2067 23:55:18.921932 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2069 23:55:19.010859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2070 23:55:19.011778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2072 23:55:19.095299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2073 23:55:19.096409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2075 23:55:19.186572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2076 23:55:19.187468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2078 23:55:19.279558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2079 23:55:19.280489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2081 23:55:19.373019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2082 23:55:19.373937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2084 23:55:19.466564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2085 23:55:19.467492 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2087 23:55:19.583020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2088 23:55:19.584051 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2090 23:55:19.673632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2091 23:55:19.674575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2093 23:55:19.768922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2094 23:55:19.769912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2096 23:55:19.861453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2097 23:55:19.862500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2099 23:55:19.954989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2100 23:55:19.956014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2102 23:55:20.049146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2103 23:55:20.049923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2105 23:55:20.153345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2106 23:55:20.154213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2108 23:55:20.244023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2109 23:55:20.244721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2111 23:55:20.337359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2112 23:55:20.338114 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2114 23:55:20.428479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2115 23:55:20.429566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2117 23:55:20.536132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2118 23:55:20.536797 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2120 23:55:20.626576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2121 23:55:20.627528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2123 23:55:20.722303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2124 23:55:20.722952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2126 23:55:20.813876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2127 23:55:20.814578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2129 23:55:20.907553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2130 23:55:20.908239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2132 23:55:21.010512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2133 23:55:21.011200 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2135 23:55:21.102263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2136 23:55:21.102916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2138 23:55:21.394988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2139 23:55:21.395648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2141 23:55:21.506722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2142 23:55:21.507591 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2144 23:55:21.601370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2145 23:55:21.602280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2147 23:55:21.693107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2148 23:55:21.693996 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2150 23:55:21.789373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2151 23:55:21.790296 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2153 23:55:21.878364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2154 23:55:21.879248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2156 23:55:21.970887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2157 23:55:21.971738 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2159 23:55:22.064677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2160 23:55:22.065548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2162 23:55:22.160784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2163 23:55:22.161641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2165 23:55:22.254365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2166 23:55:22.255185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2168 23:55:22.343167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2169 23:55:22.343983 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2171 23:55:22.433800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2172 23:55:22.434587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2174 23:55:22.525172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2175 23:55:22.525946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2177 23:55:22.619782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2178 23:55:22.620524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2180 23:55:22.710355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2181 23:55:22.711095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2183 23:55:22.803240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2184 23:55:22.803970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2186 23:55:22.897141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2187 23:55:22.897995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2189 23:55:22.989494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2190 23:55:22.990502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2192 23:55:23.081522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2193 23:55:23.082455 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2195 23:55:23.173341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2196 23:55:23.174242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2198 23:55:23.263639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2199 23:55:23.264499 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2201 23:55:23.357382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2202 23:55:23.358306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2204 23:55:23.452912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2205 23:55:23.453775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2207 23:55:23.546030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2208 23:55:23.546895 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2210 23:55:23.640152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2211 23:55:23.640996 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2213 23:55:23.735106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2214 23:55:23.735967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2216 23:55:23.828172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2217 23:55:23.829050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2219 23:55:23.922078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2220 23:55:23.922942 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2222 23:55:24.009290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2223 23:55:24.010196 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2225 23:55:24.096077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2226 23:55:24.096923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2228 23:55:24.204227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2229 23:55:24.205186 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2231 23:55:24.333270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2232 23:55:24.334228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2234 23:55:24.436112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2235 23:55:24.437004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2237 23:55:24.526605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2238 23:55:24.527681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2240 23:55:24.620903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2241 23:55:24.621771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2243 23:55:24.714110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2244 23:55:24.714987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2246 23:55:24.808879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2247 23:55:24.809767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2249 23:55:24.901294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2250 23:55:24.902208 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2252 23:55:24.993903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2253 23:55:24.994737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2255 23:55:25.085603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2256 23:55:25.087125 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2258 23:55:25.193986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2259 23:55:25.194916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2261 23:55:25.294554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2262 23:55:25.295317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2264 23:55:25.397502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2265 23:55:25.398460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2267 23:55:25.491700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2268 23:55:25.492363 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2270 23:55:25.588121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2271 23:55:25.589025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2273 23:55:25.684365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2274 23:55:25.685379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2276 23:55:25.789734 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2278 23:55:25.792945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2279 23:55:25.883688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2280 23:55:25.884384 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2282 23:55:25.980457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2283 23:55:25.981155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2285 23:55:26.073206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2286 23:55:26.074185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2288 23:55:26.170162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2289 23:55:26.171105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2291 23:55:26.262479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2292 23:55:26.263433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2294 23:55:26.361196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2295 23:55:26.362163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2297 23:55:26.462438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2298 23:55:26.463365 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2300 23:55:26.557031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2301 23:55:26.557942 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2303 23:55:26.737349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2304 23:55:26.738043 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2306 23:55:26.829577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2307 23:55:26.830500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2309 23:55:26.921920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2310 23:55:26.922888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2312 23:55:27.014267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2313 23:55:27.015217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2315 23:55:27.105207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2316 23:55:27.106201 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2318 23:55:27.196767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2319 23:55:27.197919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2321 23:55:27.288377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2322 23:55:27.289340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2324 23:55:27.378389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2325 23:55:27.379483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2327 23:55:27.469215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2328 23:55:27.470264 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2330 23:55:27.554744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2331 23:55:27.555720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2333 23:55:27.645509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2334 23:55:27.646523 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2336 23:55:27.739966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2337 23:55:27.741046 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2339 23:55:27.825763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2340 23:55:27.826872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2342 23:55:27.918705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2343 23:55:27.920282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2345 23:55:28.007965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2346 23:55:28.008667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2348 23:55:28.098391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2349 23:55:28.099515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2351 23:55:28.187756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2352 23:55:28.188418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2354 23:55:28.278609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2355 23:55:28.279278 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2357 23:55:28.379496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2358 23:55:28.380203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2360 23:55:28.472818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2361 23:55:28.473572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2363 23:55:28.564615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2364 23:55:28.565250 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2366 23:55:28.659030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2367 23:55:28.659642 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2369 23:55:28.748835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2370 23:55:28.749269 + set +x
2371 23:55:28.749736 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2373 23:55:28.753326 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 949962_1.6.2.4.5>
2374 23:55:28.753882 Received signal: <ENDRUN> 1_kselftest-dt 949962_1.6.2.4.5
2375 23:55:28.754167 Ending use of test pattern.
2376 23:55:28.754397 Ending test lava.1_kselftest-dt (949962_1.6.2.4.5), duration 86.76
2378 23:55:28.760425 <LAVA_TEST_RUNNER EXIT>
2379 23:55:28.760978 ok: lava_test_shell seems to have completed
2380 23:55:28.768006 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2381 23:55:28.769179 end: 3.1 lava-test-shell (duration 00:01:28) [common]
2382 23:55:28.769556 end: 3 lava-test-retry (duration 00:01:28) [common]
2383 23:55:28.769940 start: 4 finalize (timeout 00:05:24) [common]
2384 23:55:28.770315 start: 4.1 power-off (timeout 00:00:30) [common]
2385 23:55:28.770901 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-03'
2386 23:55:28.805464 >> OK - accepted request
2387 23:55:28.807509 Returned 0 in 0 seconds
2388 23:55:28.908530 end: 4.1 power-off (duration 00:00:00) [common]
2390 23:55:28.909581 start: 4.2 read-feedback (timeout 00:05:24) [common]
2391 23:55:28.910358 Listened to connection for namespace 'common' for up to 1s
2392 23:55:28.910992 Listened to connection for namespace 'common' for up to 1s
2393 23:55:29.910415 Finalising connection for namespace 'common'
2394 23:55:29.911469 Disconnecting from shell: Finalise
2395 23:55:29.912207 / #
2396 23:55:30.013645 end: 4.2 read-feedback (duration 00:00:01) [common]
2397 23:55:30.014826 end: 4 finalize (duration 00:00:01) [common]
2398 23:55:30.015781 Cleaning after the job
2399 23:55:30.016728 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949962/tftp-deploy-xrgbj320/ramdisk
2400 23:55:30.028363 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949962/tftp-deploy-xrgbj320/kernel
2401 23:55:30.030944 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949962/tftp-deploy-xrgbj320/dtb
2402 23:55:30.032656 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949962/tftp-deploy-xrgbj320/nfsrootfs
2403 23:55:30.070383 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949962/tftp-deploy-xrgbj320/modules
2404 23:55:30.074806 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/949962
2405 23:55:33.467645 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/949962
2406 23:55:33.468244 Job finished correctly