Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 23:38:19.251266 lava-dispatcher, installed at version: 2024.01
2 23:38:19.252126 start: 0 validate
3 23:38:19.252609 Start time: 2024-11-06 23:38:19.252581+00:00 (UTC)
4 23:38:19.253147 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 23:38:19.253685 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 23:38:19.293709 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 23:38:19.294254 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-230-g1aed5b247ee28%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 23:38:19.322910 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 23:38:19.323560 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-230-g1aed5b247ee28%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 23:38:20.377228 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 23:38:20.377757 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-230-g1aed5b247ee28%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 23:38:20.417163 validate duration: 1.16
14 23:38:20.418018 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:38:20.418364 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:38:20.418672 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:38:20.419250 Not decompressing ramdisk as can be used compressed.
18 23:38:20.419683 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 23:38:20.419926 saving as /var/lib/lava/dispatcher/tmp/950054/tftp-deploy-hplxcz2q/ramdisk/rootfs.cpio.gz
20 23:38:20.420213 total size: 8181887 (7 MB)
21 23:38:20.460598 progress 0 % (0 MB)
22 23:38:20.473401 progress 5 % (0 MB)
23 23:38:20.485336 progress 10 % (0 MB)
24 23:38:20.497224 progress 15 % (1 MB)
25 23:38:20.504052 progress 20 % (1 MB)
26 23:38:20.510043 progress 25 % (1 MB)
27 23:38:20.515538 progress 30 % (2 MB)
28 23:38:20.521465 progress 35 % (2 MB)
29 23:38:20.526884 progress 40 % (3 MB)
30 23:38:20.532657 progress 45 % (3 MB)
31 23:38:20.538026 progress 50 % (3 MB)
32 23:38:20.543871 progress 55 % (4 MB)
33 23:38:20.549185 progress 60 % (4 MB)
34 23:38:20.555036 progress 65 % (5 MB)
35 23:38:20.560271 progress 70 % (5 MB)
36 23:38:20.566172 progress 75 % (5 MB)
37 23:38:20.571379 progress 80 % (6 MB)
38 23:38:20.577189 progress 85 % (6 MB)
39 23:38:20.582566 progress 90 % (7 MB)
40 23:38:20.588215 progress 95 % (7 MB)
41 23:38:20.593080 progress 100 % (7 MB)
42 23:38:20.593750 7 MB downloaded in 0.17 s (44.97 MB/s)
43 23:38:20.594289 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:38:20.595170 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:38:20.595463 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:38:20.595951 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:38:20.596464 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-230-g1aed5b247ee28/arm64/defconfig/gcc-12/kernel/Image
49 23:38:20.596729 saving as /var/lib/lava/dispatcher/tmp/950054/tftp-deploy-hplxcz2q/kernel/Image
50 23:38:20.596942 total size: 45713920 (43 MB)
51 23:38:20.597153 No compression specified
52 23:38:20.632299 progress 0 % (0 MB)
53 23:38:20.661665 progress 5 % (2 MB)
54 23:38:20.691072 progress 10 % (4 MB)
55 23:38:20.720548 progress 15 % (6 MB)
56 23:38:20.750195 progress 20 % (8 MB)
57 23:38:20.779229 progress 25 % (10 MB)
58 23:38:20.808704 progress 30 % (13 MB)
59 23:38:20.837921 progress 35 % (15 MB)
60 23:38:20.867542 progress 40 % (17 MB)
61 23:38:20.896498 progress 45 % (19 MB)
62 23:38:20.925710 progress 50 % (21 MB)
63 23:38:20.955152 progress 55 % (24 MB)
64 23:38:20.984595 progress 60 % (26 MB)
65 23:38:21.013504 progress 65 % (28 MB)
66 23:38:21.043444 progress 70 % (30 MB)
67 23:38:21.072901 progress 75 % (32 MB)
68 23:38:21.102312 progress 80 % (34 MB)
69 23:38:21.131278 progress 85 % (37 MB)
70 23:38:21.160717 progress 90 % (39 MB)
71 23:38:21.190453 progress 95 % (41 MB)
72 23:38:21.219063 progress 100 % (43 MB)
73 23:38:21.219596 43 MB downloaded in 0.62 s (70.02 MB/s)
74 23:38:21.220095 end: 1.2.1 http-download (duration 00:00:01) [common]
76 23:38:21.220923 end: 1.2 download-retry (duration 00:00:01) [common]
77 23:38:21.221197 start: 1.3 download-retry (timeout 00:09:59) [common]
78 23:38:21.221460 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 23:38:21.221924 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-230-g1aed5b247ee28/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 23:38:21.222195 saving as /var/lib/lava/dispatcher/tmp/950054/tftp-deploy-hplxcz2q/dtb/meson-g12b-a311d-libretech-cc.dtb
81 23:38:21.222406 total size: 54703 (0 MB)
82 23:38:21.222615 No compression specified
83 23:38:21.258289 progress 59 % (0 MB)
84 23:38:21.259108 progress 100 % (0 MB)
85 23:38:21.259645 0 MB downloaded in 0.04 s (1.40 MB/s)
86 23:38:21.260130 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:38:21.260946 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:38:21.261205 start: 1.4 download-retry (timeout 00:09:59) [common]
90 23:38:21.261469 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 23:38:21.261926 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-230-g1aed5b247ee28/arm64/defconfig/gcc-12/modules.tar.xz
92 23:38:21.262166 saving as /var/lib/lava/dispatcher/tmp/950054/tftp-deploy-hplxcz2q/modules/modules.tar
93 23:38:21.262373 total size: 11613904 (11 MB)
94 23:38:21.262583 Using unxz to decompress xz
95 23:38:21.298593 progress 0 % (0 MB)
96 23:38:21.364554 progress 5 % (0 MB)
97 23:38:21.440620 progress 10 % (1 MB)
98 23:38:21.536848 progress 15 % (1 MB)
99 23:38:21.629061 progress 20 % (2 MB)
100 23:38:21.710223 progress 25 % (2 MB)
101 23:38:21.786366 progress 30 % (3 MB)
102 23:38:21.865136 progress 35 % (3 MB)
103 23:38:21.937989 progress 40 % (4 MB)
104 23:38:22.013677 progress 45 % (5 MB)
105 23:38:22.098147 progress 50 % (5 MB)
106 23:38:22.175605 progress 55 % (6 MB)
107 23:38:22.261532 progress 60 % (6 MB)
108 23:38:22.343382 progress 65 % (7 MB)
109 23:38:22.424874 progress 70 % (7 MB)
110 23:38:22.504143 progress 75 % (8 MB)
111 23:38:22.588613 progress 80 % (8 MB)
112 23:38:22.669261 progress 85 % (9 MB)
113 23:38:22.748162 progress 90 % (9 MB)
114 23:38:22.826262 progress 95 % (10 MB)
115 23:38:22.903355 progress 100 % (11 MB)
116 23:38:22.915245 11 MB downloaded in 1.65 s (6.70 MB/s)
117 23:38:22.916222 end: 1.4.1 http-download (duration 00:00:02) [common]
119 23:38:22.917970 end: 1.4 download-retry (duration 00:00:02) [common]
120 23:38:22.918542 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 23:38:22.919111 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 23:38:22.919655 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:38:22.920237 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 23:38:22.921272 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz
125 23:38:22.922234 makedir: /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin
126 23:38:22.922937 makedir: /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/tests
127 23:38:22.923603 makedir: /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/results
128 23:38:22.924280 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-add-keys
129 23:38:22.925292 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-add-sources
130 23:38:22.926296 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-background-process-start
131 23:38:22.927543 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-background-process-stop
132 23:38:22.928672 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-common-functions
133 23:38:22.929672 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-echo-ipv4
134 23:38:22.930650 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-install-packages
135 23:38:22.931623 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-installed-packages
136 23:38:22.932638 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-os-build
137 23:38:22.933726 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-probe-channel
138 23:38:22.934714 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-probe-ip
139 23:38:22.935689 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-target-ip
140 23:38:22.936706 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-target-mac
141 23:38:22.937675 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-target-storage
142 23:38:22.938670 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-test-case
143 23:38:22.939650 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-test-event
144 23:38:22.940671 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-test-feedback
145 23:38:22.941578 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-test-raise
146 23:38:22.942109 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-test-reference
147 23:38:22.942947 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-test-runner
148 23:38:22.944031 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-test-set
149 23:38:22.945038 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-test-shell
150 23:38:22.946087 Updating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-install-packages (oe)
151 23:38:22.947191 Updating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/bin/lava-installed-packages (oe)
152 23:38:22.948151 Creating /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/environment
153 23:38:22.948955 LAVA metadata
154 23:38:22.949482 - LAVA_JOB_ID=950054
155 23:38:22.949954 - LAVA_DISPATCHER_IP=192.168.6.2
156 23:38:22.950684 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 23:38:22.952699 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 23:38:22.953343 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 23:38:22.953793 skipped lava-vland-overlay
160 23:38:22.954327 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 23:38:22.954883 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 23:38:22.955351 skipped lava-multinode-overlay
163 23:38:22.955876 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 23:38:22.956488 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 23:38:22.956971 Loading test definitions
166 23:38:22.957539 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 23:38:22.957977 Using /lava-950054 at stage 0
168 23:38:22.960277 uuid=950054_1.5.2.4.1 testdef=None
169 23:38:22.960858 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 23:38:22.961372 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 23:38:22.964764 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 23:38:22.966311 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 23:38:22.970692 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 23:38:22.972404 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 23:38:22.976628 runner path: /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/0/tests/0_dmesg test_uuid 950054_1.5.2.4.1
178 23:38:22.977629 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 23:38:22.979116 Creating lava-test-runner.conf files
181 23:38:22.979517 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/950054/lava-overlay-dk1xu0lz/lava-950054/0 for stage 0
182 23:38:22.980156 - 0_dmesg
183 23:38:22.980526 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 23:38:22.980804 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 23:38:23.005227 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 23:38:23.005641 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 23:38:23.005905 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 23:38:23.006176 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 23:38:23.006441 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 23:38:23.920116 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 23:38:23.920563 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 23:38:23.920811 extracting modules file /var/lib/lava/dispatcher/tmp/950054/tftp-deploy-hplxcz2q/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950054/extract-overlay-ramdisk-i94j7lru/ramdisk
193 23:38:25.246019 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 23:38:25.246483 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 23:38:25.246759 [common] Applying overlay /var/lib/lava/dispatcher/tmp/950054/compress-overlay-f9ncy95m/overlay-1.5.2.5.tar.gz to ramdisk
196 23:38:25.246973 [common] Applying overlay /var/lib/lava/dispatcher/tmp/950054/compress-overlay-f9ncy95m/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/950054/extract-overlay-ramdisk-i94j7lru/ramdisk
197 23:38:25.277054 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 23:38:25.277473 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 23:38:25.277738 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 23:38:25.277961 Converting downloaded kernel to a uImage
201 23:38:25.278263 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/950054/tftp-deploy-hplxcz2q/kernel/Image /var/lib/lava/dispatcher/tmp/950054/tftp-deploy-hplxcz2q/kernel/uImage
202 23:38:25.728257 output: Image Name:
203 23:38:25.728660 output: Created: Wed Nov 6 23:38:25 2024
204 23:38:25.728870 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 23:38:25.729074 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 23:38:25.729275 output: Load Address: 01080000
207 23:38:25.729473 output: Entry Point: 01080000
208 23:38:25.729671 output:
209 23:38:25.730003 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 23:38:25.730269 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 23:38:25.730538 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 23:38:25.730791 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 23:38:25.731051 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 23:38:25.731306 Building ramdisk /var/lib/lava/dispatcher/tmp/950054/extract-overlay-ramdisk-i94j7lru/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/950054/extract-overlay-ramdisk-i94j7lru/ramdisk
215 23:38:28.181752 >> 181575 blocks
216 23:38:36.679032 Adding RAMdisk u-boot header.
217 23:38:36.679488 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/950054/extract-overlay-ramdisk-i94j7lru/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/950054/extract-overlay-ramdisk-i94j7lru/ramdisk.cpio.gz.uboot
218 23:38:36.952925 output: Image Name:
219 23:38:36.953336 output: Created: Wed Nov 6 23:38:36 2024
220 23:38:36.953555 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 23:38:36.953758 output: Data Size: 26054951 Bytes = 25444.29 KiB = 24.85 MiB
222 23:38:36.953957 output: Load Address: 00000000
223 23:38:36.954156 output: Entry Point: 00000000
224 23:38:36.954351 output:
225 23:38:36.954973 rename /var/lib/lava/dispatcher/tmp/950054/extract-overlay-ramdisk-i94j7lru/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/950054/tftp-deploy-hplxcz2q/ramdisk/ramdisk.cpio.gz.uboot
226 23:38:36.955391 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 23:38:36.955675 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 23:38:36.955977 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 23:38:36.956512 No LXC device requested
230 23:38:36.957068 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 23:38:36.957628 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 23:38:36.958168 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 23:38:36.958619 Checking files for TFTP limit of 4294967296 bytes.
234 23:38:36.961564 end: 1 tftp-deploy (duration 00:00:17) [common]
235 23:38:36.962204 start: 2 uboot-action (timeout 00:05:00) [common]
236 23:38:36.962778 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 23:38:36.963324 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 23:38:36.963873 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 23:38:36.964491 Using kernel file from prepare-kernel: 950054/tftp-deploy-hplxcz2q/kernel/uImage
240 23:38:36.965160 substitutions:
241 23:38:36.965610 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 23:38:36.966054 - {DTB_ADDR}: 0x01070000
243 23:38:36.966493 - {DTB}: 950054/tftp-deploy-hplxcz2q/dtb/meson-g12b-a311d-libretech-cc.dtb
244 23:38:36.966933 - {INITRD}: 950054/tftp-deploy-hplxcz2q/ramdisk/ramdisk.cpio.gz.uboot
245 23:38:36.967370 - {KERNEL_ADDR}: 0x01080000
246 23:38:36.967803 - {KERNEL}: 950054/tftp-deploy-hplxcz2q/kernel/uImage
247 23:38:36.968275 - {LAVA_MAC}: None
248 23:38:36.968755 - {PRESEED_CONFIG}: None
249 23:38:36.969190 - {PRESEED_LOCAL}: None
250 23:38:36.969618 - {RAMDISK_ADDR}: 0x08000000
251 23:38:36.970047 - {RAMDISK}: 950054/tftp-deploy-hplxcz2q/ramdisk/ramdisk.cpio.gz.uboot
252 23:38:36.970478 - {ROOT_PART}: None
253 23:38:36.970904 - {ROOT}: None
254 23:38:36.971332 - {SERVER_IP}: 192.168.6.2
255 23:38:36.971765 - {TEE_ADDR}: 0x83000000
256 23:38:36.972225 - {TEE}: None
257 23:38:36.972657 Parsed boot commands:
258 23:38:36.973074 - setenv autoload no
259 23:38:36.973499 - setenv initrd_high 0xffffffff
260 23:38:36.973925 - setenv fdt_high 0xffffffff
261 23:38:36.974348 - dhcp
262 23:38:36.974775 - setenv serverip 192.168.6.2
263 23:38:36.975200 - tftpboot 0x01080000 950054/tftp-deploy-hplxcz2q/kernel/uImage
264 23:38:36.975627 - tftpboot 0x08000000 950054/tftp-deploy-hplxcz2q/ramdisk/ramdisk.cpio.gz.uboot
265 23:38:36.976078 - tftpboot 0x01070000 950054/tftp-deploy-hplxcz2q/dtb/meson-g12b-a311d-libretech-cc.dtb
266 23:38:36.976509 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 23:38:36.976944 - bootm 0x01080000 0x08000000 0x01070000
268 23:38:36.977492 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 23:38:36.979122 start: 2.3 connect-device (timeout 00:05:00) [common]
271 23:38:36.979608 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 23:38:36.995351 Setting prompt string to ['lava-test: # ']
273 23:38:36.997049 end: 2.3 connect-device (duration 00:00:00) [common]
274 23:38:36.997709 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 23:38:36.998302 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 23:38:36.998879 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 23:38:37.000186 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 23:38:37.040055 >> OK - accepted request
279 23:38:37.042608 Returned 0 in 0 seconds
280 23:38:37.143784 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 23:38:37.145564 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 23:38:37.146165 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 23:38:37.146719 Setting prompt string to ['Hit any key to stop autoboot']
285 23:38:37.147214 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 23:38:37.148952 Trying 192.168.56.21...
287 23:38:37.149470 Connected to conserv1.
288 23:38:37.149913 Escape character is '^]'.
289 23:38:37.150376
290 23:38:37.150835 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 23:38:37.151302
292 23:38:49.070789 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 23:38:49.071567 bl2_stage_init 0x01
294 23:38:49.071976 bl2_stage_init 0x81
295 23:38:49.075918 hw id: 0x0000 - pwm id 0x01
296 23:38:49.076314 bl2_stage_init 0xc1
297 23:38:49.076575 bl2_stage_init 0x02
298 23:38:49.076784
299 23:38:49.081556 L0:00000000
300 23:38:49.082267 L1:20000703
301 23:38:49.082680 L2:00008067
302 23:38:49.083070 L3:14000000
303 23:38:49.087180 B2:00402000
304 23:38:49.087703 B1:e0f83180
305 23:38:49.088144
306 23:38:49.088557 TE: 58124
307 23:38:49.088955
308 23:38:49.092608 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 23:38:49.093139
310 23:38:49.093554 Board ID = 1
311 23:38:49.098309 Set A53 clk to 24M
312 23:38:49.098874 Set A73 clk to 24M
313 23:38:49.099287 Set clk81 to 24M
314 23:38:49.104035 A53 clk: 1200 MHz
315 23:38:49.104640 A73 clk: 1200 MHz
316 23:38:49.105065 CLK81: 166.6M
317 23:38:49.105508 smccc: 00012a92
318 23:38:49.109408 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 23:38:49.115151 board id: 1
320 23:38:49.121013 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 23:38:49.131677 fw parse done
322 23:38:49.137615 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 23:38:49.180282 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 23:38:49.191194 PIEI prepare done
325 23:38:49.191597 fastboot data load
326 23:38:49.191818 fastboot data verify
327 23:38:49.196750 verify result: 266
328 23:38:49.202406 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 23:38:49.202787 LPDDR4 probe
330 23:38:49.203022 ddr clk to 1584MHz
331 23:38:49.210359 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 23:38:49.247599
333 23:38:49.248061 dmc_version 0001
334 23:38:49.254176 Check phy result
335 23:38:49.260180 INFO : End of CA training
336 23:38:49.260635 INFO : End of initialization
337 23:38:49.265696 INFO : Training has run successfully!
338 23:38:49.266960 Check phy result
339 23:38:49.271382 INFO : End of initialization
340 23:38:49.272159 INFO : End of read enable training
341 23:38:49.276849 INFO : End of fine write leveling
342 23:38:49.282519 INFO : End of Write leveling coarse delay
343 23:38:49.282903 INFO : Training has run successfully!
344 23:38:49.283131 Check phy result
345 23:38:49.288311 INFO : End of initialization
346 23:38:49.288734 INFO : End of read dq deskew training
347 23:38:49.293705 INFO : End of MPR read delay center optimization
348 23:38:49.299474 INFO : End of write delay center optimization
349 23:38:49.304930 INFO : End of read delay center optimization
350 23:38:49.305303 INFO : End of max read latency training
351 23:38:49.310425 INFO : Training has run successfully!
352 23:38:49.310810 1D training succeed
353 23:38:49.319743 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 23:38:49.367328 Check phy result
355 23:38:49.367752 INFO : End of initialization
356 23:38:49.389648 INFO : End of 2D read delay Voltage center optimization
357 23:38:49.410152 INFO : End of 2D read delay Voltage center optimization
358 23:38:49.462166 INFO : End of 2D write delay Voltage center optimization
359 23:38:49.511571 INFO : End of 2D write delay Voltage center optimization
360 23:38:49.517115 INFO : Training has run successfully!
361 23:38:49.517486
362 23:38:49.517711 channel==0
363 23:38:49.522696 RxClkDly_Margin_A0==88 ps 9
364 23:38:49.523038 TxDqDly_Margin_A0==98 ps 10
365 23:38:49.528337 RxClkDly_Margin_A1==88 ps 9
366 23:38:49.528728 TxDqDly_Margin_A1==88 ps 9
367 23:38:49.528952 TrainedVREFDQ_A0==74
368 23:38:49.533892 TrainedVREFDQ_A1==74
369 23:38:49.534251 VrefDac_Margin_A0==24
370 23:38:49.534467 DeviceVref_Margin_A0==40
371 23:38:49.539535 VrefDac_Margin_A1==25
372 23:38:49.539899 DeviceVref_Margin_A1==40
373 23:38:49.540156
374 23:38:49.540374
375 23:38:49.540582 channel==1
376 23:38:49.545157 RxClkDly_Margin_A0==88 ps 9
377 23:38:49.545571 TxDqDly_Margin_A0==98 ps 10
378 23:38:49.550754 RxClkDly_Margin_A1==88 ps 9
379 23:38:49.551140 TxDqDly_Margin_A1==88 ps 9
380 23:38:49.556315 TrainedVREFDQ_A0==77
381 23:38:49.556713 TrainedVREFDQ_A1==77
382 23:38:49.556935 VrefDac_Margin_A0==22
383 23:38:49.561791 DeviceVref_Margin_A0==37
384 23:38:49.562186 VrefDac_Margin_A1==24
385 23:38:49.567500 DeviceVref_Margin_A1==37
386 23:38:49.567859
387 23:38:49.568134 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 23:38:49.568352
389 23:38:49.601176 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 23:38:49.601652 2D training succeed
391 23:38:49.606772 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 23:38:49.612349 auto size-- 65535DDR cs0 size: 2048MB
393 23:38:49.612747 DDR cs1 size: 2048MB
394 23:38:49.617952 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 23:38:49.618335 cs0 DataBus test pass
396 23:38:49.623497 cs1 DataBus test pass
397 23:38:49.623885 cs0 AddrBus test pass
398 23:38:49.624168 cs1 AddrBus test pass
399 23:38:49.624390
400 23:38:49.629135 100bdlr_step_size ps== 420
401 23:38:49.629532 result report
402 23:38:49.634751 boot times 0Enable ddr reg access
403 23:38:49.639925 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 23:38:49.653321 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 23:38:50.227023 0.0;M3 CHK:0;cm4_sp_mode 0
406 23:38:50.227419 MVN_1=0x00000000
407 23:38:50.232553 MVN_2=0x00000000
408 23:38:50.238424 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 23:38:50.238804 OPS=0x10
410 23:38:50.239022 ring efuse init
411 23:38:50.239224 chipver efuse init
412 23:38:50.246473 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 23:38:50.246814 [0.018961 Inits done]
414 23:38:50.254105 secure task start!
415 23:38:50.254496 high task start!
416 23:38:50.254722 low task start!
417 23:38:50.254927 run into bl31
418 23:38:50.260691 NOTICE: BL31: v1.3(release):4fc40b1
419 23:38:50.268475 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 23:38:50.268849 NOTICE: BL31: G12A normal boot!
421 23:38:50.293872 NOTICE: BL31: BL33 decompress pass
422 23:38:50.298705 ERROR: Error initializing runtime service opteed_fast
423 23:38:51.532344
424 23:38:51.532761
425 23:38:51.540763 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 23:38:51.541179
427 23:38:51.541495 Model: Libre Computer AML-A311D-CC Alta
428 23:38:51.749537 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 23:38:51.772801 DRAM: 2 GiB (effective 3.8 GiB)
430 23:38:51.915720 Core: 408 devices, 31 uclasses, devicetree: separate
431 23:38:51.921617 WDT: Not starting watchdog@f0d0
432 23:38:51.953893 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 23:38:51.966226 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 23:38:51.971224 ** Bad device specification mmc 0 **
435 23:38:51.981565 Card did not respond to voltage select! : -110
436 23:38:51.989202 ** Bad device specification mmc 0 **
437 23:38:51.989481 Couldn't find partition mmc 0
438 23:38:51.997535 Card did not respond to voltage select! : -110
439 23:38:52.003138 ** Bad device specification mmc 0 **
440 23:38:52.003715 Couldn't find partition mmc 0
441 23:38:52.008252 Error: could not access storage.
442 23:38:53.271066 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
443 23:38:53.271727 bl2_stage_init 0x81
444 23:38:53.276681 hw id: 0x0000 - pwm id 0x01
445 23:38:53.277204 bl2_stage_init 0xc1
446 23:38:53.277668 bl2_stage_init 0x02
447 23:38:53.278121
448 23:38:53.282210 L0:00000000
449 23:38:53.282720 L1:20000703
450 23:38:53.283171 L2:00008067
451 23:38:53.283616 L3:14000000
452 23:38:53.284090 B2:00402000
453 23:38:53.285293 B1:e0f83180
454 23:38:53.285828
455 23:38:53.286290 TE: 58150
456 23:38:53.286744
457 23:38:53.296574 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 23:38:53.297082
459 23:38:53.297539 Board ID = 1
460 23:38:53.297984 Set A53 clk to 24M
461 23:38:53.298426 Set A73 clk to 24M
462 23:38:53.302083 Set clk81 to 24M
463 23:38:53.302571 A53 clk: 1200 MHz
464 23:38:53.303020 A73 clk: 1200 MHz
465 23:38:53.307546 CLK81: 166.6M
466 23:38:53.308078 smccc: 00012aac
467 23:38:53.313052 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 23:38:53.313540 board id: 1
469 23:38:53.320461 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 23:38:53.332096 fw parse done
471 23:38:53.337079 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 23:38:53.380193 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 23:38:53.391497 PIEI prepare done
474 23:38:53.392047 fastboot data load
475 23:38:53.392516 fastboot data verify
476 23:38:53.397190 verify result: 266
477 23:38:53.402825 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 23:38:53.403344 LPDDR4 probe
479 23:38:53.403798 ddr clk to 1584MHz
480 23:38:53.410890 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 23:38:53.447245
482 23:38:53.447787 dmc_version 0001
483 23:38:53.454781 Check phy result
484 23:38:53.460639 INFO : End of CA training
485 23:38:53.461147 INFO : End of initialization
486 23:38:53.466221 INFO : Training has run successfully!
487 23:38:53.466722 Check phy result
488 23:38:53.471831 INFO : End of initialization
489 23:38:53.472368 INFO : End of read enable training
490 23:38:53.477442 INFO : End of fine write leveling
491 23:38:53.483031 INFO : End of Write leveling coarse delay
492 23:38:53.483531 INFO : Training has run successfully!
493 23:38:53.484005 Check phy result
494 23:38:53.488617 INFO : End of initialization
495 23:38:53.489112 INFO : End of read dq deskew training
496 23:38:53.494242 INFO : End of MPR read delay center optimization
497 23:38:53.499818 INFO : End of write delay center optimization
498 23:38:53.505418 INFO : End of read delay center optimization
499 23:38:53.505934 INFO : End of max read latency training
500 23:38:53.511039 INFO : Training has run successfully!
501 23:38:53.511569 1D training succeed
502 23:38:53.520228 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 23:38:53.567795 Check phy result
504 23:38:53.568379 INFO : End of initialization
505 23:38:53.590214 INFO : End of 2D read delay Voltage center optimization
506 23:38:53.610365 INFO : End of 2D read delay Voltage center optimization
507 23:38:53.662184 INFO : End of 2D write delay Voltage center optimization
508 23:38:53.711412 INFO : End of 2D write delay Voltage center optimization
509 23:38:53.717102 INFO : Training has run successfully!
510 23:38:53.717618
511 23:38:53.718073 channel==0
512 23:38:53.722612 RxClkDly_Margin_A0==88 ps 9
513 23:38:53.723117 TxDqDly_Margin_A0==98 ps 10
514 23:38:53.728271 RxClkDly_Margin_A1==88 ps 9
515 23:38:53.728788 TxDqDly_Margin_A1==98 ps 10
516 23:38:53.729244 TrainedVREFDQ_A0==74
517 23:38:53.733785 TrainedVREFDQ_A1==75
518 23:38:53.734297 VrefDac_Margin_A0==24
519 23:38:53.734751 DeviceVref_Margin_A0==40
520 23:38:53.739461 VrefDac_Margin_A1==24
521 23:38:53.739964 DeviceVref_Margin_A1==39
522 23:38:53.740463
523 23:38:53.740909
524 23:38:53.745110 channel==1
525 23:38:53.745606 RxClkDly_Margin_A0==98 ps 10
526 23:38:53.746053 TxDqDly_Margin_A0==98 ps 10
527 23:38:53.750651 RxClkDly_Margin_A1==98 ps 10
528 23:38:53.751152 TxDqDly_Margin_A1==88 ps 9
529 23:38:53.756271 TrainedVREFDQ_A0==77
530 23:38:53.756773 TrainedVREFDQ_A1==77
531 23:38:53.757221 VrefDac_Margin_A0==22
532 23:38:53.761851 DeviceVref_Margin_A0==37
533 23:38:53.762346 VrefDac_Margin_A1==24
534 23:38:53.767408 DeviceVref_Margin_A1==37
535 23:38:53.767905
536 23:38:53.768399 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 23:38:53.773085
538 23:38:53.801067 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000017 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
539 23:38:53.801635 2D training succeed
540 23:38:53.806642 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 23:38:53.812288 auto size-- 65535DDR cs0 size: 2048MB
542 23:38:53.812794 DDR cs1 size: 2048MB
543 23:38:53.817875 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 23:38:53.818387 cs0 DataBus test pass
545 23:38:53.823442 cs1 DataBus test pass
546 23:38:53.823944 cs0 AddrBus test pass
547 23:38:53.824434 cs1 AddrBus test pass
548 23:38:53.824878
549 23:38:53.829116 100bdlr_step_size ps== 420
550 23:38:53.829633 result report
551 23:38:53.834632 boot times 0Enable ddr reg access
552 23:38:53.840233 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 23:38:53.853486 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 23:38:54.425467 0.0;M3 CHK:0;cm4_sp_mode 0
555 23:38:54.426115 MVN_1=0x00000000
556 23:38:54.431020 MVN_2=0x00000000
557 23:38:54.436748 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 23:38:54.437221 OPS=0x10
559 23:38:54.437623 ring efuse init
560 23:38:54.438014 chipver efuse init
561 23:38:54.444935 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 23:38:54.445434 [0.018961 Inits done]
563 23:38:54.452503 secure task start!
564 23:38:54.452976 high task start!
565 23:38:54.453366 low task start!
566 23:38:54.453750 run into bl31
567 23:38:54.459101 NOTICE: BL31: v1.3(release):4fc40b1
568 23:38:54.466912 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 23:38:54.467405 NOTICE: BL31: G12A normal boot!
570 23:38:54.492363 NOTICE: BL31: BL33 decompress pass
571 23:38:54.498024 ERROR: Error initializing runtime service opteed_fast
572 23:38:55.999382
573 23:38:55.999939
574 23:38:56.000415 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 23:38:56.000867
576 23:38:56.001313 Model: Libre Computer AML-A311D-CC Alta
577 23:38:56.001749 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 23:38:56.002521 DRAM: 2 GiB (effective 3.8 GiB)
579 23:38:56.114085 Core: 408 devices, 31 uclasses, devicetree: separate
580 23:38:56.119908 WDT: Not starting watchdog@f0d0
581 23:38:56.152245 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 23:38:56.164611 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 23:38:56.169580 ** Bad device specification mmc 0 **
584 23:38:56.179959 Card did not respond to voltage select! : -110
585 23:38:56.187582 ** Bad device specification mmc 0 **
586 23:38:56.188066 Couldn't find partition mmc 0
587 23:38:56.195908 Card did not respond to voltage select! : -110
588 23:38:56.201494 ** Bad device specification mmc 0 **
589 23:38:56.201992 Couldn't find partition mmc 0
590 23:38:56.206569 Error: could not access storage.
591 23:38:56.550141 Net: eth0: ethernet@ff3f0000
592 23:38:56.550711 starting USB...
593 23:38:56.801880 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 23:38:56.802426 Starting the controller
595 23:38:56.808830 USB XHCI 1.10
596 23:38:58.522663 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 23:38:58.523283 bl2_stage_init 0x01
598 23:38:58.523708 bl2_stage_init 0x81
599 23:38:58.528162 hw id: 0x0000 - pwm id 0x01
600 23:38:58.528640 bl2_stage_init 0xc1
601 23:38:58.529060 bl2_stage_init 0x02
602 23:38:58.529461
603 23:38:58.533789 L0:00000000
604 23:38:58.534266 L1:20000703
605 23:38:58.534682 L2:00008067
606 23:38:58.535083 L3:14000000
607 23:38:58.539319 B2:00402000
608 23:38:58.539762 B1:e0f83180
609 23:38:58.540210
610 23:38:58.540618 TE: 58159
611 23:38:58.541019
612 23:38:58.544970 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 23:38:58.545428
614 23:38:58.545840 Board ID = 1
615 23:38:58.550473 Set A53 clk to 24M
616 23:38:58.550917 Set A73 clk to 24M
617 23:38:58.551318 Set clk81 to 24M
618 23:38:58.556019 A53 clk: 1200 MHz
619 23:38:58.556469 A73 clk: 1200 MHz
620 23:38:58.556876 CLK81: 166.6M
621 23:38:58.557274 smccc: 00012ab5
622 23:38:58.561463 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 23:38:58.567096 board id: 1
624 23:38:58.573040 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 23:38:58.583650 fw parse done
626 23:38:58.589821 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 23:38:58.632214 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 23:38:58.643086 PIEI prepare done
629 23:38:58.643547 fastboot data load
630 23:38:58.643958 fastboot data verify
631 23:38:58.648712 verify result: 266
632 23:38:58.654303 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 23:38:58.654750 LPDDR4 probe
634 23:38:58.655152 ddr clk to 1584MHz
635 23:38:58.662295 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 23:38:58.699570
637 23:38:58.700074 dmc_version 0001
638 23:38:58.706250 Check phy result
639 23:38:58.712142 INFO : End of CA training
640 23:38:58.712612 INFO : End of initialization
641 23:38:58.717684 INFO : Training has run successfully!
642 23:38:58.718138 Check phy result
643 23:38:58.723318 INFO : End of initialization
644 23:38:58.723796 INFO : End of read enable training
645 23:38:58.728901 INFO : End of fine write leveling
646 23:38:58.734513 INFO : End of Write leveling coarse delay
647 23:38:58.734960 INFO : Training has run successfully!
648 23:38:58.735369 Check phy result
649 23:38:58.740088 INFO : End of initialization
650 23:38:58.740532 INFO : End of read dq deskew training
651 23:38:58.745770 INFO : End of MPR read delay center optimization
652 23:38:58.751311 INFO : End of write delay center optimization
653 23:38:58.756908 INFO : End of read delay center optimization
654 23:38:58.757368 INFO : End of max read latency training
655 23:38:58.762516 INFO : Training has run successfully!
656 23:38:58.762961 1D training succeed
657 23:38:58.771700 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 23:38:58.819379 Check phy result
659 23:38:58.819884 INFO : End of initialization
660 23:38:58.841821 INFO : End of 2D read delay Voltage center optimization
661 23:38:58.862042 INFO : End of 2D read delay Voltage center optimization
662 23:38:58.914200 INFO : End of 2D write delay Voltage center optimization
663 23:38:58.963521 INFO : End of 2D write delay Voltage center optimization
664 23:38:58.968978 INFO : Training has run successfully!
665 23:38:58.969306
666 23:38:58.969521 channel==0
667 23:38:58.974679 RxClkDly_Margin_A0==88 ps 9
668 23:38:58.975133 TxDqDly_Margin_A0==98 ps 10
669 23:38:58.980239 RxClkDly_Margin_A1==88 ps 9
670 23:38:58.980703 TxDqDly_Margin_A1==98 ps 10
671 23:38:58.981058 TrainedVREFDQ_A0==74
672 23:38:58.985779 TrainedVREFDQ_A1==74
673 23:38:58.986158 VrefDac_Margin_A0==24
674 23:38:58.986429 DeviceVref_Margin_A0==40
675 23:38:58.991405 VrefDac_Margin_A1==24
676 23:38:58.991697 DeviceVref_Margin_A1==40
677 23:38:58.991922
678 23:38:58.992186
679 23:38:58.997028 channel==1
680 23:38:58.997336 RxClkDly_Margin_A0==98 ps 10
681 23:38:58.997551 TxDqDly_Margin_A0==98 ps 10
682 23:38:59.003630 RxClkDly_Margin_A1==98 ps 10
683 23:38:59.003922 TxDqDly_Margin_A1==88 ps 9
684 23:38:59.008229 TrainedVREFDQ_A0==77
685 23:38:59.008532 TrainedVREFDQ_A1==77
686 23:38:59.008759 VrefDac_Margin_A0==22
687 23:38:59.013856 DeviceVref_Margin_A0==37
688 23:38:59.014162 VrefDac_Margin_A1==24
689 23:38:59.019466 DeviceVref_Margin_A1==37
690 23:38:59.019774
691 23:38:59.020027 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 23:38:59.024902
693 23:38:59.052931 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
694 23:38:59.053467 2D training succeed
695 23:38:59.058589 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 23:38:59.064155 auto size-- 65535DDR cs0 size: 2048MB
697 23:38:59.064614 DDR cs1 size: 2048MB
698 23:38:59.069724 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 23:38:59.070154 cs0 DataBus test pass
700 23:38:59.075355 cs1 DataBus test pass
701 23:38:59.075787 cs0 AddrBus test pass
702 23:38:59.076213 cs1 AddrBus test pass
703 23:38:59.076604
704 23:38:59.080937 100bdlr_step_size ps== 420
705 23:38:59.081381 result report
706 23:38:59.086565 boot times 0Enable ddr reg access
707 23:38:59.091964 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 23:38:59.105526 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 23:38:59.679285 0.0;M3 CHK:0;cm4_sp_mode 0
710 23:38:59.679921 MVN_1=0x00000000
711 23:38:59.684720 MVN_2=0x00000000
712 23:38:59.690492 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 23:38:59.691000 OPS=0x10
714 23:38:59.691405 ring efuse init
715 23:38:59.691797 chipver efuse init
716 23:38:59.696078 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 23:38:59.701692 [0.018961 Inits done]
718 23:38:59.702130 secure task start!
719 23:38:59.702520 high task start!
720 23:38:59.706215 low task start!
721 23:38:59.706661 run into bl31
722 23:38:59.713008 NOTICE: BL31: v1.3(release):4fc40b1
723 23:38:59.720770 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 23:38:59.721237 NOTICE: BL31: G12A normal boot!
725 23:38:59.746182 NOTICE: BL31: BL33 decompress pass
726 23:38:59.750945 ERROR: Error initializing runtime service opteed_fast
727 23:39:00.984718
728 23:39:00.985168
729 23:39:00.993083 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 23:39:00.993499
731 23:39:00.993788 Model: Libre Computer AML-A311D-CC Alta
732 23:39:01.201585 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 23:39:01.224918 DRAM: 2 GiB (effective 3.8 GiB)
734 23:39:01.367836 Core: 408 devices, 31 uclasses, devicetree: separate
735 23:39:01.373870 WDT: Not starting watchdog@f0d0
736 23:39:01.406101 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 23:39:01.418507 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 23:39:01.423557 ** Bad device specification mmc 0 **
739 23:39:01.433924 Card did not respond to voltage select! : -110
740 23:39:01.441519 ** Bad device specification mmc 0 **
741 23:39:01.442076 Couldn't find partition mmc 0
742 23:39:01.449856 Card did not respond to voltage select! : -110
743 23:39:01.455337 ** Bad device specification mmc 0 **
744 23:39:01.455885 Couldn't find partition mmc 0
745 23:39:01.460404 Error: could not access storage.
746 23:39:01.804050 Net: eth0: ethernet@ff3f0000
747 23:39:01.804699 starting USB...
748 23:39:02.055748 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 23:39:02.056413 Starting the controller
750 23:39:02.062733 USB XHCI 1.10
751 23:39:04.221984 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 23:39:04.222622 bl2_stage_init 0x01
753 23:39:04.223088 bl2_stage_init 0x81
754 23:39:04.226721 hw id: 0x0000 - pwm id 0x01
755 23:39:04.227280 bl2_stage_init 0xc1
756 23:39:04.227770 bl2_stage_init 0x02
757 23:39:04.228330
758 23:39:04.232361 L0:00000000
759 23:39:04.232886 L1:20000703
760 23:39:04.233339 L2:00008067
761 23:39:04.233782 L3:14000000
762 23:39:04.235231 B2:00402000
763 23:39:04.235740 B1:e0f83180
764 23:39:04.236232
765 23:39:04.236682 TE: 58167
766 23:39:04.237122
767 23:39:04.246427 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 23:39:04.247000
769 23:39:04.247460 Board ID = 1
770 23:39:04.247904 Set A53 clk to 24M
771 23:39:04.248395 Set A73 clk to 24M
772 23:39:04.252187 Set clk81 to 24M
773 23:39:04.252754 A53 clk: 1200 MHz
774 23:39:04.253265 A73 clk: 1200 MHz
775 23:39:04.257441 CLK81: 166.6M
776 23:39:04.258000 smccc: 00012abe
777 23:39:04.263085 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 23:39:04.263673 board id: 1
779 23:39:04.271737 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 23:39:04.282418 fw parse done
781 23:39:04.288233 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 23:39:04.330932 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 23:39:04.341821 PIEI prepare done
784 23:39:04.342499 fastboot data load
785 23:39:04.343094 fastboot data verify
786 23:39:04.347465 verify result: 266
787 23:39:04.353093 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 23:39:04.353674 LPDDR4 probe
789 23:39:04.354123 ddr clk to 1584MHz
790 23:39:04.360712 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 23:39:04.397383
792 23:39:04.398019 dmc_version 0001
793 23:39:04.405063 Check phy result
794 23:39:04.410908 INFO : End of CA training
795 23:39:04.411501 INFO : End of initialization
796 23:39:04.416456 INFO : Training has run successfully!
797 23:39:04.417191 Check phy result
798 23:39:04.421954 INFO : End of initialization
799 23:39:04.422308 INFO : End of read enable training
800 23:39:04.425484 INFO : End of fine write leveling
801 23:39:04.430823 INFO : End of Write leveling coarse delay
802 23:39:04.436394 INFO : Training has run successfully!
803 23:39:04.436749 Check phy result
804 23:39:04.436984 INFO : End of initialization
805 23:39:04.441941 INFO : End of read dq deskew training
806 23:39:04.447720 INFO : End of MPR read delay center optimization
807 23:39:04.448249 INFO : End of write delay center optimization
808 23:39:04.453245 INFO : End of read delay center optimization
809 23:39:04.458840 INFO : End of max read latency training
810 23:39:04.459238 INFO : Training has run successfully!
811 23:39:04.464475 1D training succeed
812 23:39:04.470316 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 23:39:04.518034 Check phy result
814 23:39:04.518576 INFO : End of initialization
815 23:39:04.539619 INFO : End of 2D read delay Voltage center optimization
816 23:39:04.559770 INFO : End of 2D read delay Voltage center optimization
817 23:39:04.611798 INFO : End of 2D write delay Voltage center optimization
818 23:39:04.661020 INFO : End of 2D write delay Voltage center optimization
819 23:39:04.666500 INFO : Training has run successfully!
820 23:39:04.666991
821 23:39:04.667410 channel==0
822 23:39:04.672060 RxClkDly_Margin_A0==88 ps 9
823 23:39:04.672545 TxDqDly_Margin_A0==98 ps 10
824 23:39:04.677629 RxClkDly_Margin_A1==88 ps 9
825 23:39:04.678102 TxDqDly_Margin_A1==98 ps 10
826 23:39:04.678512 TrainedVREFDQ_A0==74
827 23:39:04.683216 TrainedVREFDQ_A1==74
828 23:39:04.683681 VrefDac_Margin_A0==25
829 23:39:04.684110 DeviceVref_Margin_A0==40
830 23:39:04.688881 VrefDac_Margin_A1==25
831 23:39:04.689367 DeviceVref_Margin_A1==40
832 23:39:04.689767
833 23:39:04.690156
834 23:39:04.694542 channel==1
835 23:39:04.695009 RxClkDly_Margin_A0==98 ps 10
836 23:39:04.695407 TxDqDly_Margin_A0==98 ps 10
837 23:39:04.700135 RxClkDly_Margin_A1==88 ps 9
838 23:39:04.700675 TxDqDly_Margin_A1==88 ps 9
839 23:39:04.705660 TrainedVREFDQ_A0==77
840 23:39:04.706131 TrainedVREFDQ_A1==77
841 23:39:04.706534 VrefDac_Margin_A0==22
842 23:39:04.711317 DeviceVref_Margin_A0==37
843 23:39:04.711784 VrefDac_Margin_A1==24
844 23:39:04.716915 DeviceVref_Margin_A1==37
845 23:39:04.717388
846 23:39:04.717794 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 23:39:04.718186
848 23:39:04.750539 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
849 23:39:04.751086 2D training succeed
850 23:39:04.756083 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 23:39:04.761724 auto size-- 65535DDR cs0 size: 2048MB
852 23:39:04.762199 DDR cs1 size: 2048MB
853 23:39:04.767208 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 23:39:04.767677 cs0 DataBus test pass
855 23:39:04.772786 cs1 DataBus test pass
856 23:39:04.773256 cs0 AddrBus test pass
857 23:39:04.773654 cs1 AddrBus test pass
858 23:39:04.774048
859 23:39:04.778508 100bdlr_step_size ps== 432
860 23:39:04.778978 result report
861 23:39:04.783974 boot times 0Enable ddr reg access
862 23:39:04.789418 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 23:39:04.801850 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 23:39:05.374809 0.0;M3 CHK:0;cm4_sp_mode 0
865 23:39:05.375442 MVN_1=0x00000000
866 23:39:05.380396 MVN_2=0x00000000
867 23:39:05.386072 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 23:39:05.386705 OPS=0x10
869 23:39:05.387264 ring efuse init
870 23:39:05.387919 chipver efuse init
871 23:39:05.391627 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 23:39:05.397285 [0.018960 Inits done]
873 23:39:05.397842 secure task start!
874 23:39:05.398323 high task start!
875 23:39:05.401876 low task start!
876 23:39:05.402482 run into bl31
877 23:39:05.408545 NOTICE: BL31: v1.3(release):4fc40b1
878 23:39:05.415427 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 23:39:05.416048 NOTICE: BL31: G12A normal boot!
880 23:39:05.441729 NOTICE: BL31: BL33 decompress pass
881 23:39:05.446512 ERROR: Error initializing runtime service opteed_fast
882 23:39:06.680279
883 23:39:06.680912
884 23:39:06.687888 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 23:39:06.688456
886 23:39:06.688900 Model: Libre Computer AML-A311D-CC Alta
887 23:39:06.897188 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 23:39:06.920552 DRAM: 2 GiB (effective 3.8 GiB)
889 23:39:07.063666 Core: 408 devices, 31 uclasses, devicetree: separate
890 23:39:07.068880 WDT: Not starting watchdog@f0d0
891 23:39:07.101727 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 23:39:07.114163 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 23:39:07.118247 ** Bad device specification mmc 0 **
894 23:39:07.129450 Card did not respond to voltage select! : -110
895 23:39:07.137067 ** Bad device specification mmc 0 **
896 23:39:07.137597 Couldn't find partition mmc 0
897 23:39:07.145386 Card did not respond to voltage select! : -110
898 23:39:07.150899 ** Bad device specification mmc 0 **
899 23:39:07.151414 Couldn't find partition mmc 0
900 23:39:07.155974 Error: could not access storage.
901 23:39:07.498455 Net: eth0: ethernet@ff3f0000
902 23:39:07.499107 starting USB...
903 23:39:07.750308 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 23:39:07.750945 Starting the controller
905 23:39:07.757180 USB XHCI 1.10
906 23:39:09.620804 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
907 23:39:09.621488 bl2_stage_init 0x01
908 23:39:09.621997 bl2_stage_init 0x81
909 23:39:09.626232 hw id: 0x0000 - pwm id 0x01
910 23:39:09.626766 bl2_stage_init 0xc1
911 23:39:09.627224 bl2_stage_init 0x02
912 23:39:09.627670
913 23:39:09.631780 L0:00000000
914 23:39:09.632402 L1:20000703
915 23:39:09.632860 L2:00008067
916 23:39:09.633671 L3:14000000
917 23:39:09.637382 B2:00402000
918 23:39:09.637959 B1:e0f83180
919 23:39:09.638440
920 23:39:09.638915 TE: 58124
921 23:39:09.639385
922 23:39:09.643139 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
923 23:39:09.643666
924 23:39:09.644138 Board ID = 1
925 23:39:09.648646 Set A53 clk to 24M
926 23:39:09.649105 Set A73 clk to 24M
927 23:39:09.649523 Set clk81 to 24M
928 23:39:09.654217 A53 clk: 1200 MHz
929 23:39:09.654666 A73 clk: 1200 MHz
930 23:39:09.655077 CLK81: 166.6M
931 23:39:09.655482 smccc: 00012a92
932 23:39:09.659827 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
933 23:39:09.665436 board id: 1
934 23:39:09.671236 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
935 23:39:09.682015 fw parse done
936 23:39:09.687861 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
937 23:39:09.730483 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
938 23:39:09.741354 PIEI prepare done
939 23:39:09.741810 fastboot data load
940 23:39:09.742204 fastboot data verify
941 23:39:09.747074 verify result: 266
942 23:39:09.752656 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
943 23:39:09.753099 LPDDR4 probe
944 23:39:09.753486 ddr clk to 1584MHz
945 23:39:09.760799 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
946 23:39:09.798067
947 23:39:09.798631 dmc_version 0001
948 23:39:09.804765 Check phy result
949 23:39:09.810542 INFO : End of CA training
950 23:39:09.810995 INFO : End of initialization
951 23:39:09.816238 INFO : Training has run successfully!
952 23:39:09.816767 Check phy result
953 23:39:09.821855 INFO : End of initialization
954 23:39:09.822331 INFO : End of read enable training
955 23:39:09.827294 INFO : End of fine write leveling
956 23:39:09.832907 INFO : End of Write leveling coarse delay
957 23:39:09.833567 INFO : Training has run successfully!
958 23:39:09.834031 Check phy result
959 23:39:09.838534 INFO : End of initialization
960 23:39:09.839063 INFO : End of read dq deskew training
961 23:39:09.844098 INFO : End of MPR read delay center optimization
962 23:39:09.849693 INFO : End of write delay center optimization
963 23:39:09.855331 INFO : End of read delay center optimization
964 23:39:09.855861 INFO : End of max read latency training
965 23:39:09.860835 INFO : Training has run successfully!
966 23:39:09.861314 1D training succeed
967 23:39:09.870099 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
968 23:39:09.917817 Check phy result
969 23:39:09.918388 INFO : End of initialization
970 23:39:09.939370 INFO : End of 2D read delay Voltage center optimization
971 23:39:09.957843 INFO : End of 2D read delay Voltage center optimization
972 23:39:10.010545 INFO : End of 2D write delay Voltage center optimization
973 23:39:10.059803 INFO : End of 2D write delay Voltage center optimization
974 23:39:10.065290 INFO : Training has run successfully!
975 23:39:10.065772
976 23:39:10.066188 channel==0
977 23:39:10.070818 RxClkDly_Margin_A0==88 ps 9
978 23:39:10.071278 TxDqDly_Margin_A0==98 ps 10
979 23:39:10.076452 RxClkDly_Margin_A1==88 ps 9
980 23:39:10.076911 TxDqDly_Margin_A1==98 ps 10
981 23:39:10.077329 TrainedVREFDQ_A0==74
982 23:39:10.082094 TrainedVREFDQ_A1==74
983 23:39:10.082616 VrefDac_Margin_A0==25
984 23:39:10.083033 DeviceVref_Margin_A0==40
985 23:39:10.087720 VrefDac_Margin_A1==25
986 23:39:10.088235 DeviceVref_Margin_A1==40
987 23:39:10.088645
988 23:39:10.089048
989 23:39:10.093248 channel==1
990 23:39:10.093709 RxClkDly_Margin_A0==98 ps 10
991 23:39:10.094123 TxDqDly_Margin_A0==98 ps 10
992 23:39:10.098748 RxClkDly_Margin_A1==88 ps 9
993 23:39:10.099197 TxDqDly_Margin_A1==88 ps 9
994 23:39:10.104452 TrainedVREFDQ_A0==77
995 23:39:10.104936 TrainedVREFDQ_A1==77
996 23:39:10.105357 VrefDac_Margin_A0==23
997 23:39:10.110055 DeviceVref_Margin_A0==37
998 23:39:10.110515 VrefDac_Margin_A1==24
999 23:39:10.115665 DeviceVref_Margin_A1==37
1000 23:39:10.116151
1001 23:39:10.116562 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1002 23:39:10.116958
1003 23:39:10.149544 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000019 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1004 23:39:10.150177 2D training succeed
1005 23:39:10.154942 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1006 23:39:10.160462 auto size-- 65535DDR cs0 size: 2048MB
1007 23:39:10.160964 DDR cs1 size: 2048MB
1008 23:39:10.166089 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1009 23:39:10.166574 cs0 DataBus test pass
1010 23:39:10.171669 cs1 DataBus test pass
1011 23:39:10.172197 cs0 AddrBus test pass
1012 23:39:10.172617 cs1 AddrBus test pass
1013 23:39:10.173024
1014 23:39:10.177334 100bdlr_step_size ps== 420
1015 23:39:10.177954 result report
1016 23:39:10.182902 boot times 0Enable ddr reg access
1017 23:39:10.188434 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1018 23:39:10.201604 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1019 23:39:10.773492 0.0;M3 CHK:0;cm4_sp_mode 0
1020 23:39:10.773904 MVN_1=0x00000000
1021 23:39:10.779004 MVN_2=0x00000000
1022 23:39:10.784728 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1023 23:39:10.785183 OPS=0x10
1024 23:39:10.785425 ring efuse init
1025 23:39:10.785633 chipver efuse init
1026 23:39:10.790478 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1027 23:39:10.796036 [0.018961 Inits done]
1028 23:39:10.796545 secure task start!
1029 23:39:10.796989 high task start!
1030 23:39:10.800528 low task start!
1031 23:39:10.801012 run into bl31
1032 23:39:10.807181 NOTICE: BL31: v1.3(release):4fc40b1
1033 23:39:10.815004 NOTICE: BL31: Built : 15:58:17, May 22 2019
1034 23:39:10.815498 NOTICE: BL31: G12A normal boot!
1035 23:39:10.840355 NOTICE: BL31: BL33 decompress pass
1036 23:39:10.846098 ERROR: Error initializing runtime service opteed_fast
1037 23:39:12.079046
1038 23:39:12.079696
1039 23:39:12.087441 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1040 23:39:12.087959
1041 23:39:12.088461 Model: Libre Computer AML-A311D-CC Alta
1042 23:39:12.295908 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1043 23:39:12.319235 DRAM: 2 GiB (effective 3.8 GiB)
1044 23:39:12.462207 Core: 408 devices, 31 uclasses, devicetree: separate
1045 23:39:12.467113 WDT: Not starting watchdog@f0d0
1046 23:39:12.500337 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1047 23:39:12.512858 Loading Environment from FAT... Card did not respond to voltage select! : -110
1048 23:39:12.517013 ** Bad device specification mmc 0 **
1049 23:39:12.528187 Card did not respond to voltage select! : -110
1050 23:39:12.534864 ** Bad device specification mmc 0 **
1051 23:39:12.535371 Couldn't find partition mmc 0
1052 23:39:12.544117 Card did not respond to voltage select! : -110
1053 23:39:12.549633 ** Bad device specification mmc 0 **
1054 23:39:12.550131 Couldn't find partition mmc 0
1055 23:39:12.554689 Error: could not access storage.
1056 23:39:12.897188 Net: eth0: ethernet@ff3f0000
1057 23:39:12.897836 starting USB...
1058 23:39:13.149069 Bus usb@ff500000: Register 3000140 NbrPorts 3
1059 23:39:13.149711 Starting the controller
1060 23:39:13.155932 USB XHCI 1.10
1061 23:39:14.712334 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1062 23:39:14.720556 scanning usb for storage devices... 0 Storage Device(s) found
1064 23:39:14.772297 Hit any key to stop autoboot: 1
1065 23:39:14.773250 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1066 23:39:14.774061 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1067 23:39:14.774582 Setting prompt string to ['=>']
1068 23:39:14.775113 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1069 23:39:14.788110 0
1070 23:39:14.789146 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1071 23:39:14.789732 Sending with 10 millisecond of delay
1073 23:39:15.925070 => setenv autoload no
1074 23:39:15.935935 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1075 23:39:15.941526 setenv autoload no
1076 23:39:15.942410 Sending with 10 millisecond of delay
1078 23:39:17.740397 => setenv initrd_high 0xffffffff
1079 23:39:17.751259 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1080 23:39:17.752301 setenv initrd_high 0xffffffff
1081 23:39:17.753101 Sending with 10 millisecond of delay
1083 23:39:19.370183 => setenv fdt_high 0xffffffff
1084 23:39:19.381010 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1085 23:39:19.381892 setenv fdt_high 0xffffffff
1086 23:39:19.382654 Sending with 10 millisecond of delay
1088 23:39:19.674657 => dhcp
1089 23:39:19.685445 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1090 23:39:19.686323 dhcp
1091 23:39:19.686799 Speed: 1000, full duplex
1092 23:39:19.687256 BOOTP broadcast 1
1093 23:39:19.695711 DHCP client bound to address 192.168.6.27 (12 ms)
1094 23:39:19.696557 Sending with 10 millisecond of delay
1096 23:39:21.373782 => setenv serverip 192.168.6.2
1097 23:39:21.384629 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1098 23:39:21.385633 setenv serverip 192.168.6.2
1099 23:39:21.386376 Sending with 10 millisecond of delay
1101 23:39:25.111768 => tftpboot 0x01080000 950054/tftp-deploy-hplxcz2q/kernel/uImage
1102 23:39:25.122638 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1103 23:39:25.123546 tftpboot 0x01080000 950054/tftp-deploy-hplxcz2q/kernel/uImage
1104 23:39:25.124068 Speed: 1000, full duplex
1105 23:39:25.124531 Using ethernet@ff3f0000 device
1106 23:39:25.125471 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1107 23:39:25.130975 Filename '950054/tftp-deploy-hplxcz2q/kernel/uImage'.
1108 23:39:25.135125 Load address: 0x1080000
1109 23:39:27.989086 Loading: *################################################## 43.6 MiB
1110 23:39:27.989486 15.3 MiB/s
1111 23:39:27.989702 done
1112 23:39:27.992899 Bytes transferred = 45713984 (2b98a40 hex)
1113 23:39:27.993816 Sending with 10 millisecond of delay
1115 23:39:32.682183 => tftpboot 0x08000000 950054/tftp-deploy-hplxcz2q/ramdisk/ramdisk.cpio.gz.uboot
1116 23:39:32.692918 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1117 23:39:32.693494 tftpboot 0x08000000 950054/tftp-deploy-hplxcz2q/ramdisk/ramdisk.cpio.gz.uboot
1118 23:39:32.693747 Speed: 1000, full duplex
1119 23:39:32.693955 Using ethernet@ff3f0000 device
1120 23:39:32.695547 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1121 23:39:32.704342 Filename '950054/tftp-deploy-hplxcz2q/ramdisk/ramdisk.cpio.gz.uboot'.
1122 23:39:32.704690 Load address: 0x8000000
1123 23:39:39.479852 Loading: *############T ##################################### UDP wrong checksum 00000005 000034b9
1124 23:39:44.481134 T UDP wrong checksum 00000005 000034b9
1125 23:39:54.484346 T T UDP wrong checksum 00000005 000034b9
1126 23:40:14.488256 T T T T UDP wrong checksum 00000005 000034b9
1127 23:40:15.602232 UDP wrong checksum 000000ff 00000ed0
1128 23:40:15.665457 UDP wrong checksum 000000ff 00006749
1129 23:40:29.492265 T T
1130 23:40:29.492941 Retry count exceeded; starting again
1132 23:40:29.494506 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1135 23:40:29.496648 end: 2.4 uboot-commands (duration 00:01:52) [common]
1137 23:40:29.498153 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1139 23:40:29.499299 end: 2 uboot-action (duration 00:01:53) [common]
1141 23:40:29.501034 Cleaning after the job
1142 23:40:29.501629 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950054/tftp-deploy-hplxcz2q/ramdisk
1143 23:40:29.502830 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950054/tftp-deploy-hplxcz2q/kernel
1144 23:40:29.551505 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950054/tftp-deploy-hplxcz2q/dtb
1145 23:40:29.552474 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950054/tftp-deploy-hplxcz2q/modules
1146 23:40:29.572660 start: 4.1 power-off (timeout 00:00:30) [common]
1147 23:40:29.573360 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1148 23:40:29.608459 >> OK - accepted request
1149 23:40:29.610610 Returned 0 in 0 seconds
1150 23:40:29.711531 end: 4.1 power-off (duration 00:00:00) [common]
1152 23:40:29.713280 start: 4.2 read-feedback (timeout 00:10:00) [common]
1153 23:40:29.714409 Listened to connection for namespace 'common' for up to 1s
1154 23:40:30.715342 Finalising connection for namespace 'common'
1155 23:40:30.716225 Disconnecting from shell: Finalise
1156 23:40:30.717157 =>
1157 23:40:30.818422 end: 4.2 read-feedback (duration 00:00:01) [common]
1158 23:40:30.819195 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/950054
1159 23:40:31.297895 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/950054
1160 23:40:31.298580 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.