Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 04:34:10.387050 lava-dispatcher, installed at version: 2024.01
2 04:34:10.387843 start: 0 validate
3 04:34:10.388340 Start time: 2024-11-07 04:34:10.388309+00:00 (UTC)
4 04:34:10.388887 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 04:34:10.389422 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 04:34:10.431038 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 04:34:10.431585 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-235-gf366870b9966d%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 04:34:10.462007 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 04:34:10.462624 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-235-gf366870b9966d%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 04:34:10.496192 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 04:34:10.496682 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-235-gf366870b9966d%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 04:34:10.537300 validate duration: 0.15
14 04:34:10.538512 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 04:34:10.539001 start: 1.1 download-retry (timeout 00:10:00) [common]
16 04:34:10.539486 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 04:34:10.540281 Not decompressing ramdisk as can be used compressed.
18 04:34:10.540900 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 04:34:10.541236 saving as /var/lib/lava/dispatcher/tmp/950932/tftp-deploy-kabzueha/ramdisk/rootfs.cpio.gz
20 04:34:10.541764 total size: 47897469 (45 MB)
21 04:34:10.574306 progress 0 % (0 MB)
22 04:34:10.605171 progress 5 % (2 MB)
23 04:34:10.635563 progress 10 % (4 MB)
24 04:34:10.665448 progress 15 % (6 MB)
25 04:34:10.695346 progress 20 % (9 MB)
26 04:34:10.725541 progress 25 % (11 MB)
27 04:34:10.755141 progress 30 % (13 MB)
28 04:34:10.785166 progress 35 % (16 MB)
29 04:34:10.814913 progress 40 % (18 MB)
30 04:34:10.845130 progress 45 % (20 MB)
31 04:34:10.875071 progress 50 % (22 MB)
32 04:34:10.904751 progress 55 % (25 MB)
33 04:34:10.935489 progress 60 % (27 MB)
34 04:34:10.965013 progress 65 % (29 MB)
35 04:34:10.994907 progress 70 % (32 MB)
36 04:34:11.025077 progress 75 % (34 MB)
37 04:34:11.054951 progress 80 % (36 MB)
38 04:34:11.084881 progress 85 % (38 MB)
39 04:34:11.114502 progress 90 % (41 MB)
40 04:34:11.144853 progress 95 % (43 MB)
41 04:34:11.174071 progress 100 % (45 MB)
42 04:34:11.174805 45 MB downloaded in 0.63 s (72.16 MB/s)
43 04:34:11.175384 end: 1.1.1 http-download (duration 00:00:01) [common]
45 04:34:11.176327 end: 1.1 download-retry (duration 00:00:01) [common]
46 04:34:11.176645 start: 1.2 download-retry (timeout 00:09:59) [common]
47 04:34:11.176936 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 04:34:11.177426 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-235-gf366870b9966d/arm64/defconfig/gcc-12/kernel/Image
49 04:34:11.177700 saving as /var/lib/lava/dispatcher/tmp/950932/tftp-deploy-kabzueha/kernel/Image
50 04:34:11.177924 total size: 45713920 (43 MB)
51 04:34:11.178143 No compression specified
52 04:34:11.220846 progress 0 % (0 MB)
53 04:34:11.249259 progress 5 % (2 MB)
54 04:34:11.277740 progress 10 % (4 MB)
55 04:34:11.306123 progress 15 % (6 MB)
56 04:34:11.334509 progress 20 % (8 MB)
57 04:34:11.362797 progress 25 % (10 MB)
58 04:34:11.391229 progress 30 % (13 MB)
59 04:34:11.419695 progress 35 % (15 MB)
60 04:34:11.448134 progress 40 % (17 MB)
61 04:34:11.475947 progress 45 % (19 MB)
62 04:34:11.504778 progress 50 % (21 MB)
63 04:34:11.533102 progress 55 % (24 MB)
64 04:34:11.561737 progress 60 % (26 MB)
65 04:34:11.590074 progress 65 % (28 MB)
66 04:34:11.618316 progress 70 % (30 MB)
67 04:34:11.646785 progress 75 % (32 MB)
68 04:34:11.674962 progress 80 % (34 MB)
69 04:34:11.703189 progress 85 % (37 MB)
70 04:34:11.731454 progress 90 % (39 MB)
71 04:34:11.759630 progress 95 % (41 MB)
72 04:34:11.787748 progress 100 % (43 MB)
73 04:34:11.788286 43 MB downloaded in 0.61 s (71.43 MB/s)
74 04:34:11.788794 end: 1.2.1 http-download (duration 00:00:01) [common]
76 04:34:11.789681 end: 1.2 download-retry (duration 00:00:01) [common]
77 04:34:11.789979 start: 1.3 download-retry (timeout 00:09:59) [common]
78 04:34:11.790263 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 04:34:11.790737 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-235-gf366870b9966d/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 04:34:11.790997 saving as /var/lib/lava/dispatcher/tmp/950932/tftp-deploy-kabzueha/dtb/meson-g12b-a311d-libretech-cc.dtb
81 04:34:11.791213 total size: 54703 (0 MB)
82 04:34:11.791433 No compression specified
83 04:34:11.827506 progress 59 % (0 MB)
84 04:34:11.828383 progress 100 % (0 MB)
85 04:34:11.828955 0 MB downloaded in 0.04 s (1.38 MB/s)
86 04:34:11.829423 end: 1.3.1 http-download (duration 00:00:00) [common]
88 04:34:11.830261 end: 1.3 download-retry (duration 00:00:00) [common]
89 04:34:11.830534 start: 1.4 download-retry (timeout 00:09:59) [common]
90 04:34:11.830806 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 04:34:11.831367 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-235-gf366870b9966d/arm64/defconfig/gcc-12/modules.tar.xz
92 04:34:11.831629 saving as /var/lib/lava/dispatcher/tmp/950932/tftp-deploy-kabzueha/modules/modules.tar
93 04:34:11.831843 total size: 11607584 (11 MB)
94 04:34:11.832097 Using unxz to decompress xz
95 04:34:11.866864 progress 0 % (0 MB)
96 04:34:11.932004 progress 5 % (0 MB)
97 04:34:12.005172 progress 10 % (1 MB)
98 04:34:12.100170 progress 15 % (1 MB)
99 04:34:12.191269 progress 20 % (2 MB)
100 04:34:12.271185 progress 25 % (2 MB)
101 04:34:12.347170 progress 30 % (3 MB)
102 04:34:12.422185 progress 35 % (3 MB)
103 04:34:12.499658 progress 40 % (4 MB)
104 04:34:12.577171 progress 45 % (5 MB)
105 04:34:12.661325 progress 50 % (5 MB)
106 04:34:12.737458 progress 55 % (6 MB)
107 04:34:12.821991 progress 60 % (6 MB)
108 04:34:12.903215 progress 65 % (7 MB)
109 04:34:12.980505 progress 70 % (7 MB)
110 04:34:13.063171 progress 75 % (8 MB)
111 04:34:13.147241 progress 80 % (8 MB)
112 04:34:13.226840 progress 85 % (9 MB)
113 04:34:13.306291 progress 90 % (9 MB)
114 04:34:13.386055 progress 95 % (10 MB)
115 04:34:13.463396 progress 100 % (11 MB)
116 04:34:13.474377 11 MB downloaded in 1.64 s (6.74 MB/s)
117 04:34:13.475135 end: 1.4.1 http-download (duration 00:00:02) [common]
119 04:34:13.477027 end: 1.4 download-retry (duration 00:00:02) [common]
120 04:34:13.477640 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 04:34:13.478228 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 04:34:13.478795 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 04:34:13.479365 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 04:34:13.480461 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi
125 04:34:13.481414 makedir: /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin
126 04:34:13.482174 makedir: /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/tests
127 04:34:13.482884 makedir: /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/results
128 04:34:13.483582 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-add-keys
129 04:34:13.484683 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-add-sources
130 04:34:13.485737 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-background-process-start
131 04:34:13.486809 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-background-process-stop
132 04:34:13.487957 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-common-functions
133 04:34:13.489114 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-echo-ipv4
134 04:34:13.490165 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-install-packages
135 04:34:13.491193 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-installed-packages
136 04:34:13.492248 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-os-build
137 04:34:13.493278 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-probe-channel
138 04:34:13.494307 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-probe-ip
139 04:34:13.495360 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-target-ip
140 04:34:13.496511 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-target-mac
141 04:34:13.497601 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-target-storage
142 04:34:13.498659 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-test-case
143 04:34:13.499701 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-test-event
144 04:34:13.500786 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-test-feedback
145 04:34:13.501816 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-test-raise
146 04:34:13.502833 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-test-reference
147 04:34:13.503859 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-test-runner
148 04:34:13.504961 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-test-set
149 04:34:13.506103 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-test-shell
150 04:34:13.507162 Updating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-install-packages (oe)
151 04:34:13.508300 Updating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/bin/lava-installed-packages (oe)
152 04:34:13.509269 Creating /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/environment
153 04:34:13.510096 LAVA metadata
154 04:34:13.510664 - LAVA_JOB_ID=950932
155 04:34:13.511165 - LAVA_DISPATCHER_IP=192.168.6.2
156 04:34:13.511907 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 04:34:13.513785 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 04:34:13.514413 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 04:34:13.514844 skipped lava-vland-overlay
160 04:34:13.515344 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 04:34:13.515865 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 04:34:13.516356 skipped lava-multinode-overlay
163 04:34:13.516870 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 04:34:13.517392 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 04:34:13.517886 Loading test definitions
166 04:34:13.518455 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 04:34:13.518909 Using /lava-950932 at stage 0
168 04:34:13.520630 uuid=950932_1.5.2.4.1 testdef=None
169 04:34:13.520975 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 04:34:13.521276 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 04:34:13.523117 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 04:34:13.524008 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 04:34:13.526271 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 04:34:13.527168 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 04:34:13.529384 runner path: /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/0/tests/0_igt-gpu-panfrost test_uuid 950932_1.5.2.4.1
178 04:34:13.530002 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 04:34:13.530874 Creating lava-test-runner.conf files
181 04:34:13.531103 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/950932/lava-overlay-frv5v9hi/lava-950932/0 for stage 0
182 04:34:13.531472 - 0_igt-gpu-panfrost
183 04:34:13.531875 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 04:34:13.532243 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 04:34:13.556108 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 04:34:13.556539 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 04:34:13.556836 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 04:34:13.557124 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 04:34:13.557407 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 04:34:20.258539 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 04:34:20.259064 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 04:34:20.259582 extracting modules file /var/lib/lava/dispatcher/tmp/950932/tftp-deploy-kabzueha/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950932/extract-overlay-ramdisk-3va_b4i5/ramdisk
193 04:34:21.652020 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 04:34:21.652499 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 04:34:21.652794 [common] Applying overlay /var/lib/lava/dispatcher/tmp/950932/compress-overlay-ex2qce3u/overlay-1.5.2.5.tar.gz to ramdisk
196 04:34:21.653022 [common] Applying overlay /var/lib/lava/dispatcher/tmp/950932/compress-overlay-ex2qce3u/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/950932/extract-overlay-ramdisk-3va_b4i5/ramdisk
197 04:34:21.682504 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 04:34:21.682862 start: 1.5.6 prepare-kernel (timeout 00:09:49) [common]
199 04:34:21.683149 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:49) [common]
200 04:34:21.683382 Converting downloaded kernel to a uImage
201 04:34:21.683689 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/950932/tftp-deploy-kabzueha/kernel/Image /var/lib/lava/dispatcher/tmp/950932/tftp-deploy-kabzueha/kernel/uImage
202 04:34:22.164744 output: Image Name:
203 04:34:22.165160 output: Created: Thu Nov 7 04:34:21 2024
204 04:34:22.165368 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 04:34:22.165572 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 04:34:22.165773 output: Load Address: 01080000
207 04:34:22.165972 output: Entry Point: 01080000
208 04:34:22.166169 output:
209 04:34:22.166499 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 04:34:22.166765 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 04:34:22.167031 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 04:34:22.167282 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 04:34:22.167539 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 04:34:22.167792 Building ramdisk /var/lib/lava/dispatcher/tmp/950932/extract-overlay-ramdisk-3va_b4i5/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/950932/extract-overlay-ramdisk-3va_b4i5/ramdisk
215 04:34:28.626105 >> 502380 blocks
216 04:34:49.212776 Adding RAMdisk u-boot header.
217 04:34:49.213464 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/950932/extract-overlay-ramdisk-3va_b4i5/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/950932/extract-overlay-ramdisk-3va_b4i5/ramdisk.cpio.gz.uboot
218 04:34:49.855606 output: Image Name:
219 04:34:49.856118 output: Created: Thu Nov 7 04:34:49 2024
220 04:34:49.856558 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 04:34:49.856961 output: Data Size: 65714385 Bytes = 64174.20 KiB = 62.67 MiB
222 04:34:49.857362 output: Load Address: 00000000
223 04:34:49.857755 output: Entry Point: 00000000
224 04:34:49.858143 output:
225 04:34:49.859127 rename /var/lib/lava/dispatcher/tmp/950932/extract-overlay-ramdisk-3va_b4i5/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/950932/tftp-deploy-kabzueha/ramdisk/ramdisk.cpio.gz.uboot
226 04:34:49.859870 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 04:34:49.860469 end: 1.5 prepare-tftp-overlay (duration 00:00:36) [common]
228 04:34:49.861039 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:21) [common]
229 04:34:49.861496 No LXC device requested
230 04:34:49.861991 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 04:34:49.862489 start: 1.7 deploy-device-env (timeout 00:09:21) [common]
232 04:34:49.862973 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 04:34:49.863380 Checking files for TFTP limit of 4294967296 bytes.
234 04:34:49.866074 end: 1 tftp-deploy (duration 00:00:39) [common]
235 04:34:49.866697 start: 2 uboot-action (timeout 00:05:00) [common]
236 04:34:49.867221 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 04:34:49.867752 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 04:34:49.868308 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 04:34:49.868842 Using kernel file from prepare-kernel: 950932/tftp-deploy-kabzueha/kernel/uImage
240 04:34:49.869446 substitutions:
241 04:34:49.869850 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 04:34:49.870248 - {DTB_ADDR}: 0x01070000
243 04:34:49.870643 - {DTB}: 950932/tftp-deploy-kabzueha/dtb/meson-g12b-a311d-libretech-cc.dtb
244 04:34:49.871042 - {INITRD}: 950932/tftp-deploy-kabzueha/ramdisk/ramdisk.cpio.gz.uboot
245 04:34:49.871436 - {KERNEL_ADDR}: 0x01080000
246 04:34:49.871827 - {KERNEL}: 950932/tftp-deploy-kabzueha/kernel/uImage
247 04:34:49.872260 - {LAVA_MAC}: None
248 04:34:49.872698 - {PRESEED_CONFIG}: None
249 04:34:49.873096 - {PRESEED_LOCAL}: None
250 04:34:49.873483 - {RAMDISK_ADDR}: 0x08000000
251 04:34:49.873867 - {RAMDISK}: 950932/tftp-deploy-kabzueha/ramdisk/ramdisk.cpio.gz.uboot
252 04:34:49.874260 - {ROOT_PART}: None
253 04:34:49.874650 - {ROOT}: None
254 04:34:49.875036 - {SERVER_IP}: 192.168.6.2
255 04:34:49.875424 - {TEE_ADDR}: 0x83000000
256 04:34:49.875807 - {TEE}: None
257 04:34:49.876229 Parsed boot commands:
258 04:34:49.876611 - setenv autoload no
259 04:34:49.876997 - setenv initrd_high 0xffffffff
260 04:34:49.877382 - setenv fdt_high 0xffffffff
261 04:34:49.877764 - dhcp
262 04:34:49.878150 - setenv serverip 192.168.6.2
263 04:34:49.878534 - tftpboot 0x01080000 950932/tftp-deploy-kabzueha/kernel/uImage
264 04:34:49.878923 - tftpboot 0x08000000 950932/tftp-deploy-kabzueha/ramdisk/ramdisk.cpio.gz.uboot
265 04:34:49.879310 - tftpboot 0x01070000 950932/tftp-deploy-kabzueha/dtb/meson-g12b-a311d-libretech-cc.dtb
266 04:34:49.879695 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 04:34:49.880114 - bootm 0x01080000 0x08000000 0x01070000
268 04:34:49.880634 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 04:34:49.882136 start: 2.3 connect-device (timeout 00:05:00) [common]
271 04:34:49.882590 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 04:34:49.897237 Setting prompt string to ['lava-test: # ']
273 04:34:49.898754 end: 2.3 connect-device (duration 00:00:00) [common]
274 04:34:49.899353 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 04:34:49.899944 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 04:34:49.900737 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 04:34:49.901942 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 04:34:49.937241 >> OK - accepted request
279 04:34:49.939282 Returned 0 in 0 seconds
280 04:34:50.040380 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 04:34:50.041960 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 04:34:50.042501 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 04:34:50.042997 Setting prompt string to ['Hit any key to stop autoboot']
285 04:34:50.043449 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 04:34:50.045053 Trying 192.168.56.21...
287 04:34:50.045522 Connected to conserv1.
288 04:34:50.045936 Escape character is '^]'.
289 04:34:50.046342
290 04:34:50.046759 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 04:34:50.047179
292 04:35:00.905169 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 04:35:00.905610 bl2_stage_init 0x01
294 04:35:00.905874 bl2_stage_init 0x81
295 04:35:00.910675 hw id: 0x0000 - pwm id 0x01
296 04:35:00.911015 bl2_stage_init 0xc1
297 04:35:00.911260 bl2_stage_init 0x02
298 04:35:00.911492
299 04:35:00.916312 L0:00000000
300 04:35:00.916628 L1:20000703
301 04:35:00.916857 L2:00008067
302 04:35:00.917084 L3:14000000
303 04:35:00.919134 B2:00402000
304 04:35:00.919406 B1:e0f83180
305 04:35:00.919635
306 04:35:00.919860 TE: 58124
307 04:35:00.920121
308 04:35:00.930303 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 04:35:00.930617
310 04:35:00.930852 Board ID = 1
311 04:35:00.931076 Set A53 clk to 24M
312 04:35:00.931296 Set A73 clk to 24M
313 04:35:00.935960 Set clk81 to 24M
314 04:35:00.936428 A53 clk: 1200 MHz
315 04:35:00.936819 A73 clk: 1200 MHz
316 04:35:00.939522 CLK81: 166.6M
317 04:35:00.939943 smccc: 00012a91
318 04:35:00.945082 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 04:35:00.950620 board id: 1
320 04:35:00.955638 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 04:35:00.966306 fw parse done
322 04:35:00.972365 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 04:35:01.014816 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 04:35:01.025950 PIEI prepare done
325 04:35:01.026388 fastboot data load
326 04:35:01.026784 fastboot data verify
327 04:35:01.031455 verify result: 266
328 04:35:01.036999 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 04:35:01.037422 LPDDR4 probe
330 04:35:01.037829 ddr clk to 1584MHz
331 04:35:01.044913 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 04:35:01.082169
333 04:35:01.082644 dmc_version 0001
334 04:35:01.088868 Check phy result
335 04:35:01.094700 INFO : End of CA training
336 04:35:01.095151 INFO : End of initialization
337 04:35:01.100300 INFO : Training has run successfully!
338 04:35:01.100726 Check phy result
339 04:35:01.105908 INFO : End of initialization
340 04:35:01.106351 INFO : End of read enable training
341 04:35:01.109219 INFO : End of fine write leveling
342 04:35:01.114755 INFO : End of Write leveling coarse delay
343 04:35:01.120348 INFO : Training has run successfully!
344 04:35:01.120764 Check phy result
345 04:35:01.121156 INFO : End of initialization
346 04:35:01.125940 INFO : End of read dq deskew training
347 04:35:01.131545 INFO : End of MPR read delay center optimization
348 04:35:01.131968 INFO : End of write delay center optimization
349 04:35:01.137195 INFO : End of read delay center optimization
350 04:35:01.142742 INFO : End of max read latency training
351 04:35:01.143163 INFO : Training has run successfully!
352 04:35:01.148348 1D training succeed
353 04:35:01.154317 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 04:35:01.201918 Check phy result
355 04:35:01.202450 INFO : End of initialization
356 04:35:01.224328 INFO : End of 2D read delay Voltage center optimization
357 04:35:01.244458 INFO : End of 2D read delay Voltage center optimization
358 04:35:01.296385 INFO : End of 2D write delay Voltage center optimization
359 04:35:01.345582 INFO : End of 2D write delay Voltage center optimization
360 04:35:01.351147 INFO : Training has run successfully!
361 04:35:01.351569
362 04:35:01.351966 channel==0
363 04:35:01.356821 RxClkDly_Margin_A0==88 ps 9
364 04:35:01.357256 TxDqDly_Margin_A0==98 ps 10
365 04:35:01.360145 RxClkDly_Margin_A1==88 ps 9
366 04:35:01.360558 TxDqDly_Margin_A1==88 ps 9
367 04:35:01.365656 TrainedVREFDQ_A0==74
368 04:35:01.366086 TrainedVREFDQ_A1==74
369 04:35:01.366478 VrefDac_Margin_A0==24
370 04:35:01.371285 DeviceVref_Margin_A0==40
371 04:35:01.371705 VrefDac_Margin_A1==24
372 04:35:01.376847 DeviceVref_Margin_A1==40
373 04:35:01.377262
374 04:35:01.377659
375 04:35:01.378047 channel==1
376 04:35:01.378434 RxClkDly_Margin_A0==98 ps 10
377 04:35:01.382425 TxDqDly_Margin_A0==88 ps 9
378 04:35:01.382847 RxClkDly_Margin_A1==88 ps 9
379 04:35:01.388084 TxDqDly_Margin_A1==88 ps 9
380 04:35:01.388579 TrainedVREFDQ_A0==77
381 04:35:01.388975 TrainedVREFDQ_A1==77
382 04:35:01.393633 VrefDac_Margin_A0==22
383 04:35:01.394055 DeviceVref_Margin_A0==37
384 04:35:01.399363 VrefDac_Margin_A1==24
385 04:35:01.399861 DeviceVref_Margin_A1==37
386 04:35:01.400352
387 04:35:01.404866 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 04:35:01.405342
389 04:35:01.432900 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 04:35:01.438408 2D training succeed
391 04:35:01.443919 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 04:35:01.444394 auto size-- 65535DDR cs0 size: 2048MB
393 04:35:01.449506 DDR cs1 size: 2048MB
394 04:35:01.449927 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 04:35:01.455089 cs0 DataBus test pass
396 04:35:01.455505 cs1 DataBus test pass
397 04:35:01.455896 cs0 AddrBus test pass
398 04:35:01.460723 cs1 AddrBus test pass
399 04:35:01.461144
400 04:35:01.461537 100bdlr_step_size ps== 420
401 04:35:01.461935 result report
402 04:35:01.466323 boot times 0Enable ddr reg access
403 04:35:01.473861 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 04:35:01.487335 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 04:35:02.059585 0.0;M3 CHK:0;cm4_sp_mode 0
406 04:35:02.060262 MVN_1=0x00000000
407 04:35:02.064867 MVN_2=0x00000000
408 04:35:02.070614 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 04:35:02.071044 OPS=0x10
410 04:35:02.071441 ring efuse init
411 04:35:02.071828 chipver efuse init
412 04:35:02.076284 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 04:35:02.081817 [0.018961 Inits done]
414 04:35:02.082282 secure task start!
415 04:35:02.082675 high task start!
416 04:35:02.086390 low task start!
417 04:35:02.086807 run into bl31
418 04:35:02.093054 NOTICE: BL31: v1.3(release):4fc40b1
419 04:35:02.100843 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 04:35:02.101277 NOTICE: BL31: G12A normal boot!
421 04:35:02.126316 NOTICE: BL31: BL33 decompress pass
422 04:35:02.131905 ERROR: Error initializing runtime service opteed_fast
423 04:35:03.365025
424 04:35:03.365668
425 04:35:03.373221 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 04:35:03.373683
427 04:35:03.374099 Model: Libre Computer AML-A311D-CC Alta
428 04:35:03.581684 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 04:35:03.604962 DRAM: 2 GiB (effective 3.8 GiB)
430 04:35:03.748079 Core: 408 devices, 31 uclasses, devicetree: separate
431 04:35:03.753802 WDT: Not starting watchdog@f0d0
432 04:35:03.786121 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 04:35:03.798592 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 04:35:03.803550 ** Bad device specification mmc 0 **
435 04:35:03.813887 Card did not respond to voltage select! : -110
436 04:35:03.821581 ** Bad device specification mmc 0 **
437 04:35:03.821964 Couldn't find partition mmc 0
438 04:35:03.829865 Card did not respond to voltage select! : -110
439 04:35:03.835365 ** Bad device specification mmc 0 **
440 04:35:03.835733 Couldn't find partition mmc 0
441 04:35:03.840421 Error: could not access storage.
442 04:35:05.105172 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 04:35:05.105787 bl2_stage_init 0x01
444 04:35:05.106220 bl2_stage_init 0x81
445 04:35:05.110731 hw id: 0x0000 - pwm id 0x01
446 04:35:05.111248 bl2_stage_init 0xc1
447 04:35:05.111599 bl2_stage_init 0x02
448 04:35:05.111816
449 04:35:05.116331 L0:00000000
450 04:35:05.116643 L1:20000703
451 04:35:05.117053 L2:00008067
452 04:35:05.117466 L3:14000000
453 04:35:05.121941 B2:00402000
454 04:35:05.122472 B1:e0f83180
455 04:35:05.122892
456 04:35:05.123215 TE: 58124
457 04:35:05.123468
458 04:35:05.127530 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 04:35:05.127821
460 04:35:05.128273 Board ID = 1
461 04:35:05.133148 Set A53 clk to 24M
462 04:35:05.133622 Set A73 clk to 24M
463 04:35:05.134032 Set clk81 to 24M
464 04:35:05.138747 A53 clk: 1200 MHz
465 04:35:05.139222 A73 clk: 1200 MHz
466 04:35:05.139648 CLK81: 166.6M
467 04:35:05.139962 smccc: 00012a91
468 04:35:05.144242 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 04:35:05.149867 board id: 1
470 04:35:05.155834 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 04:35:05.166419 fw parse done
472 04:35:05.172430 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 04:35:05.215093 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 04:35:05.226027 PIEI prepare done
475 04:35:05.226566 fastboot data load
476 04:35:05.226985 fastboot data verify
477 04:35:05.231647 verify result: 266
478 04:35:05.237248 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 04:35:05.237709 LPDDR4 probe
480 04:35:05.238118 ddr clk to 1584MHz
481 04:35:05.245219 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 04:35:05.282459
483 04:35:05.282937 dmc_version 0001
484 04:35:05.289154 Check phy result
485 04:35:05.295022 INFO : End of CA training
486 04:35:05.295474 INFO : End of initialization
487 04:35:05.300648 INFO : Training has run successfully!
488 04:35:05.301085 Check phy result
489 04:35:05.306247 INFO : End of initialization
490 04:35:05.306742 INFO : End of read enable training
491 04:35:05.311808 INFO : End of fine write leveling
492 04:35:05.317438 INFO : End of Write leveling coarse delay
493 04:35:05.317892 INFO : Training has run successfully!
494 04:35:05.318304 Check phy result
495 04:35:05.323022 INFO : End of initialization
496 04:35:05.323455 INFO : End of read dq deskew training
497 04:35:05.328614 INFO : End of MPR read delay center optimization
498 04:35:05.334208 INFO : End of write delay center optimization
499 04:35:05.339821 INFO : End of read delay center optimization
500 04:35:05.340300 INFO : End of max read latency training
501 04:35:05.345415 INFO : Training has run successfully!
502 04:35:05.345855 1D training succeed
503 04:35:05.354592 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 04:35:05.402231 Check phy result
505 04:35:05.402825 INFO : End of initialization
506 04:35:05.424014 INFO : End of 2D read delay Voltage center optimization
507 04:35:05.444200 INFO : End of 2D read delay Voltage center optimization
508 04:35:05.496223 INFO : End of 2D write delay Voltage center optimization
509 04:35:05.545645 INFO : End of 2D write delay Voltage center optimization
510 04:35:05.551291 INFO : Training has run successfully!
511 04:35:05.551890
512 04:35:05.552422 channel==0
513 04:35:05.556934 RxClkDly_Margin_A0==88 ps 9
514 04:35:05.557510 TxDqDly_Margin_A0==98 ps 10
515 04:35:05.562458 RxClkDly_Margin_A1==88 ps 9
516 04:35:05.563022 TxDqDly_Margin_A1==88 ps 9
517 04:35:05.563488 TrainedVREFDQ_A0==74
518 04:35:05.568093 TrainedVREFDQ_A1==74
519 04:35:05.568690 VrefDac_Margin_A0==25
520 04:35:05.569153 DeviceVref_Margin_A0==40
521 04:35:05.573667 VrefDac_Margin_A1==25
522 04:35:05.574250 DeviceVref_Margin_A1==40
523 04:35:05.574711
524 04:35:05.575161
525 04:35:05.575606 channel==1
526 04:35:05.579221 RxClkDly_Margin_A0==98 ps 10
527 04:35:05.579837 TxDqDly_Margin_A0==98 ps 10
528 04:35:05.584837 RxClkDly_Margin_A1==88 ps 9
529 04:35:05.585398 TxDqDly_Margin_A1==88 ps 9
530 04:35:05.590468 TrainedVREFDQ_A0==77
531 04:35:05.591050 TrainedVREFDQ_A1==77
532 04:35:05.591521 VrefDac_Margin_A0==22
533 04:35:05.596093 DeviceVref_Margin_A0==37
534 04:35:05.596662 VrefDac_Margin_A1==24
535 04:35:05.601609 DeviceVref_Margin_A1==37
536 04:35:05.602462
537 04:35:05.602979 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 04:35:05.603437
539 04:35:05.635244 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
540 04:35:05.635922 2D training succeed
541 04:35:05.640860 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 04:35:05.646425 auto size-- 65535DDR cs0 size: 2048MB
543 04:35:05.647026 DDR cs1 size: 2048MB
544 04:35:05.652022 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 04:35:05.652617 cs0 DataBus test pass
546 04:35:05.657633 cs1 DataBus test pass
547 04:35:05.658198 cs0 AddrBus test pass
548 04:35:05.658666 cs1 AddrBus test pass
549 04:35:05.659124
550 04:35:05.663277 100bdlr_step_size ps== 420
551 04:35:05.663905 result report
552 04:35:05.668778 boot times 0Enable ddr reg access
553 04:35:05.674140 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 04:35:05.687516 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 04:35:06.261241 0.0;M3 CHK:0;cm4_sp_mode 0
556 04:35:06.261936 MVN_1=0x00000000
557 04:35:06.266708 MVN_2=0x00000000
558 04:35:06.272422 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 04:35:06.272719 OPS=0x10
560 04:35:06.272941 ring efuse init
561 04:35:06.273151 chipver efuse init
562 04:35:06.278026 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 04:35:06.283635 [0.018961 Inits done]
564 04:35:06.284212 secure task start!
565 04:35:06.284662 high task start!
566 04:35:06.288133 low task start!
567 04:35:06.288671 run into bl31
568 04:35:06.294873 NOTICE: BL31: v1.3(release):4fc40b1
569 04:35:06.302695 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 04:35:06.303014 NOTICE: BL31: G12A normal boot!
571 04:35:06.328106 NOTICE: BL31: BL33 decompress pass
572 04:35:06.333764 ERROR: Error initializing runtime service opteed_fast
573 04:35:07.566843
574 04:35:07.567525
575 04:35:07.575249 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 04:35:07.575817
577 04:35:07.576348 Model: Libre Computer AML-A311D-CC Alta
578 04:35:07.783793 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 04:35:07.807089 DRAM: 2 GiB (effective 3.8 GiB)
580 04:35:07.950112 Core: 408 devices, 31 uclasses, devicetree: separate
581 04:35:07.955898 WDT: Not starting watchdog@f0d0
582 04:35:07.988205 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 04:35:08.000618 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 04:35:08.005618 ** Bad device specification mmc 0 **
585 04:35:08.016124 Card did not respond to voltage select! : -110
586 04:35:08.023661 ** Bad device specification mmc 0 **
587 04:35:08.024281 Couldn't find partition mmc 0
588 04:35:08.031952 Card did not respond to voltage select! : -110
589 04:35:08.037357 ** Bad device specification mmc 0 **
590 04:35:08.037875 Couldn't find partition mmc 0
591 04:35:08.042441 Error: could not access storage.
592 04:35:08.384985 Net: eth0: ethernet@ff3f0000
593 04:35:08.385611 starting USB...
594 04:35:08.636676 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 04:35:08.637271 Starting the controller
596 04:35:08.643800 USB XHCI 1.10
597 04:35:10.355695 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 04:35:10.356431 bl2_stage_init 0x01
599 04:35:10.356902 bl2_stage_init 0x81
600 04:35:10.361316 hw id: 0x0000 - pwm id 0x01
601 04:35:10.361838 bl2_stage_init 0xc1
602 04:35:10.362297 bl2_stage_init 0x02
603 04:35:10.362744
604 04:35:10.366901 L0:00000000
605 04:35:10.367410 L1:20000703
606 04:35:10.367865 L2:00008067
607 04:35:10.368352 L3:14000000
608 04:35:10.372532 B2:00402000
609 04:35:10.373069 B1:e0f83180
610 04:35:10.373536
611 04:35:10.373986 TE: 58159
612 04:35:10.374435
613 04:35:10.378058 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 04:35:10.378593
615 04:35:10.379056 Board ID = 1
616 04:35:10.383709 Set A53 clk to 24M
617 04:35:10.384264 Set A73 clk to 24M
618 04:35:10.384719 Set clk81 to 24M
619 04:35:10.389272 A53 clk: 1200 MHz
620 04:35:10.389784 A73 clk: 1200 MHz
621 04:35:10.390237 CLK81: 166.6M
622 04:35:10.390678 smccc: 00012ab4
623 04:35:10.394890 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 04:35:10.400404 board id: 1
625 04:35:10.406531 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 04:35:10.416914 fw parse done
627 04:35:10.422842 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 04:35:10.465479 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 04:35:10.476350 PIEI prepare done
630 04:35:10.476862 fastboot data load
631 04:35:10.477322 fastboot data verify
632 04:35:10.482052 verify result: 266
633 04:35:10.487637 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 04:35:10.488181 LPDDR4 probe
635 04:35:10.488640 ddr clk to 1584MHz
636 04:35:10.495623 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 04:35:10.532942
638 04:35:10.533515 dmc_version 0001
639 04:35:10.539661 Check phy result
640 04:35:10.545452 INFO : End of CA training
641 04:35:10.545973 INFO : End of initialization
642 04:35:10.551073 INFO : Training has run successfully!
643 04:35:10.551593 Check phy result
644 04:35:10.556674 INFO : End of initialization
645 04:35:10.557191 INFO : End of read enable training
646 04:35:10.562249 INFO : End of fine write leveling
647 04:35:10.567838 INFO : End of Write leveling coarse delay
648 04:35:10.568387 INFO : Training has run successfully!
649 04:35:10.568844 Check phy result
650 04:35:10.573451 INFO : End of initialization
651 04:35:10.573960 INFO : End of read dq deskew training
652 04:35:10.579092 INFO : End of MPR read delay center optimization
653 04:35:10.584653 INFO : End of write delay center optimization
654 04:35:10.590236 INFO : End of read delay center optimization
655 04:35:10.590740 INFO : End of max read latency training
656 04:35:10.595841 INFO : Training has run successfully!
657 04:35:10.596389 1D training succeed
658 04:35:10.604983 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 04:35:10.652690 Check phy result
660 04:35:10.653225 INFO : End of initialization
661 04:35:10.674344 INFO : End of 2D read delay Voltage center optimization
662 04:35:10.694611 INFO : End of 2D read delay Voltage center optimization
663 04:35:10.746598 INFO : End of 2D write delay Voltage center optimization
664 04:35:10.796021 INFO : End of 2D write delay Voltage center optimization
665 04:35:10.801609 INFO : Training has run successfully!
666 04:35:10.802110
667 04:35:10.802565 channel==0
668 04:35:10.807138 RxClkDly_Margin_A0==88 ps 9
669 04:35:10.807649 TxDqDly_Margin_A0==98 ps 10
670 04:35:10.812745 RxClkDly_Margin_A1==88 ps 9
671 04:35:10.813246 TxDqDly_Margin_A1==98 ps 10
672 04:35:10.813704 TrainedVREFDQ_A0==74
673 04:35:10.818357 TrainedVREFDQ_A1==75
674 04:35:10.818882 VrefDac_Margin_A0==25
675 04:35:10.819334 DeviceVref_Margin_A0==40
676 04:35:10.823950 VrefDac_Margin_A1==25
677 04:35:10.824482 DeviceVref_Margin_A1==39
678 04:35:10.824933
679 04:35:10.825377
680 04:35:10.829611 channel==1
681 04:35:10.830113 RxClkDly_Margin_A0==98 ps 10
682 04:35:10.830563 TxDqDly_Margin_A0==88 ps 9
683 04:35:10.835142 RxClkDly_Margin_A1==98 ps 10
684 04:35:10.835646 TxDqDly_Margin_A1==98 ps 10
685 04:35:10.840719 TrainedVREFDQ_A0==75
686 04:35:10.841232 TrainedVREFDQ_A1==78
687 04:35:10.841681 VrefDac_Margin_A0==22
688 04:35:10.846340 DeviceVref_Margin_A0==38
689 04:35:10.846843 VrefDac_Margin_A1==22
690 04:35:10.851977 DeviceVref_Margin_A1==36
691 04:35:10.852512
692 04:35:10.852963 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 04:35:10.857604
694 04:35:10.885561 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
695 04:35:10.886120 2D training succeed
696 04:35:10.891134 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 04:35:10.896742 auto size-- 65535DDR cs0 size: 2048MB
698 04:35:10.897255 DDR cs1 size: 2048MB
699 04:35:10.902356 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 04:35:10.902872 cs0 DataBus test pass
701 04:35:10.907956 cs1 DataBus test pass
702 04:35:10.908495 cs0 AddrBus test pass
703 04:35:10.908947 cs1 AddrBus test pass
704 04:35:10.909388
705 04:35:10.913616 100bdlr_step_size ps== 420
706 04:35:10.914129 result report
707 04:35:10.919121 boot times 0Enable ddr reg access
708 04:35:10.924566 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 04:35:10.938011 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 04:35:11.511779 0.0;M3 CHK:0;cm4_sp_mode 0
711 04:35:11.512528 MVN_1=0x00000000
712 04:35:11.517241 MVN_2=0x00000000
713 04:35:11.523013 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 04:35:11.523578 OPS=0x10
715 04:35:11.524096 ring efuse init
716 04:35:11.524539 chipver efuse init
717 04:35:11.528604 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 04:35:11.534149 [0.018961 Inits done]
719 04:35:11.534656 secure task start!
720 04:35:11.535087 high task start!
721 04:35:11.538705 low task start!
722 04:35:11.539212 run into bl31
723 04:35:11.545359 NOTICE: BL31: v1.3(release):4fc40b1
724 04:35:11.553164 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 04:35:11.553674 NOTICE: BL31: G12A normal boot!
726 04:35:11.578525 NOTICE: BL31: BL33 decompress pass
727 04:35:11.584198 ERROR: Error initializing runtime service opteed_fast
728 04:35:12.817162
729 04:35:12.817812
730 04:35:12.825551 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 04:35:12.826073
732 04:35:12.826533 Model: Libre Computer AML-A311D-CC Alta
733 04:35:13.034030 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 04:35:13.057340 DRAM: 2 GiB (effective 3.8 GiB)
735 04:35:13.200359 Core: 408 devices, 31 uclasses, devicetree: separate
736 04:35:13.206187 WDT: Not starting watchdog@f0d0
737 04:35:13.238538 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 04:35:13.250941 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 04:35:13.255945 ** Bad device specification mmc 0 **
740 04:35:13.266210 Card did not respond to voltage select! : -110
741 04:35:13.273901 ** Bad device specification mmc 0 **
742 04:35:13.274409 Couldn't find partition mmc 0
743 04:35:13.282181 Card did not respond to voltage select! : -110
744 04:35:13.287723 ** Bad device specification mmc 0 **
745 04:35:13.288261 Couldn't find partition mmc 0
746 04:35:13.292782 Error: could not access storage.
747 04:35:13.635236 Net: eth0: ethernet@ff3f0000
748 04:35:13.635852 starting USB...
749 04:35:13.887098 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 04:35:13.887666 Starting the controller
751 04:35:13.894053 USB XHCI 1.10
752 04:35:16.055804 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 04:35:16.056509 bl2_stage_init 0x01
754 04:35:16.056972 bl2_stage_init 0x81
755 04:35:16.061198 hw id: 0x0000 - pwm id 0x01
756 04:35:16.061712 bl2_stage_init 0xc1
757 04:35:16.062163 bl2_stage_init 0x02
758 04:35:16.062605
759 04:35:16.066860 L0:00000000
760 04:35:16.067360 L1:20000703
761 04:35:16.067809 L2:00008067
762 04:35:16.068290 L3:14000000
763 04:35:16.072411 B2:00402000
764 04:35:16.072912 B1:e0f83180
765 04:35:16.073360
766 04:35:16.073804 TE: 58124
767 04:35:16.074245
768 04:35:16.077956 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 04:35:16.078462
770 04:35:16.078916 Board ID = 1
771 04:35:16.083630 Set A53 clk to 24M
772 04:35:16.084157 Set A73 clk to 24M
773 04:35:16.084605 Set clk81 to 24M
774 04:35:16.089172 A53 clk: 1200 MHz
775 04:35:16.089667 A73 clk: 1200 MHz
776 04:35:16.090112 CLK81: 166.6M
777 04:35:16.090551 smccc: 00012a92
778 04:35:16.094774 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 04:35:16.100427 board id: 1
780 04:35:16.106312 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 04:35:16.116968 fw parse done
782 04:35:16.122881 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 04:35:16.165601 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 04:35:16.176361 PIEI prepare done
785 04:35:16.176852 fastboot data load
786 04:35:16.177302 fastboot data verify
787 04:35:16.182060 verify result: 266
788 04:35:16.187664 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 04:35:16.188202 LPDDR4 probe
790 04:35:16.188649 ddr clk to 1584MHz
791 04:35:16.195639 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 04:35:16.232872
793 04:35:16.233373 dmc_version 0001
794 04:35:16.239584 Check phy result
795 04:35:16.245435 INFO : End of CA training
796 04:35:16.245933 INFO : End of initialization
797 04:35:16.251034 INFO : Training has run successfully!
798 04:35:16.251531 Check phy result
799 04:35:16.256644 INFO : End of initialization
800 04:35:16.257139 INFO : End of read enable training
801 04:35:16.262252 INFO : End of fine write leveling
802 04:35:16.267834 INFO : End of Write leveling coarse delay
803 04:35:16.268364 INFO : Training has run successfully!
804 04:35:16.268814 Check phy result
805 04:35:16.273461 INFO : End of initialization
806 04:35:16.273957 INFO : End of read dq deskew training
807 04:35:16.279030 INFO : End of MPR read delay center optimization
808 04:35:16.284623 INFO : End of write delay center optimization
809 04:35:16.290283 INFO : End of read delay center optimization
810 04:35:16.290783 INFO : End of max read latency training
811 04:35:16.295842 INFO : Training has run successfully!
812 04:35:16.296386 1D training succeed
813 04:35:16.305031 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 04:35:16.352639 Check phy result
815 04:35:16.353140 INFO : End of initialization
816 04:35:16.374421 INFO : End of 2D read delay Voltage center optimization
817 04:35:16.394689 INFO : End of 2D read delay Voltage center optimization
818 04:35:16.446710 INFO : End of 2D write delay Voltage center optimization
819 04:35:16.496146 INFO : End of 2D write delay Voltage center optimization
820 04:35:16.501719 INFO : Training has run successfully!
821 04:35:16.502239
822 04:35:16.502701 channel==0
823 04:35:16.507274 RxClkDly_Margin_A0==88 ps 9
824 04:35:16.507781 TxDqDly_Margin_A0==98 ps 10
825 04:35:16.512883 RxClkDly_Margin_A1==88 ps 9
826 04:35:16.513393 TxDqDly_Margin_A1==88 ps 9
827 04:35:16.513860 TrainedVREFDQ_A0==74
828 04:35:16.518554 TrainedVREFDQ_A1==74
829 04:35:16.519108 VrefDac_Margin_A0==25
830 04:35:16.519563 DeviceVref_Margin_A0==40
831 04:35:16.524094 VrefDac_Margin_A1==25
832 04:35:16.524619 DeviceVref_Margin_A1==40
833 04:35:16.525042
834 04:35:16.525469
835 04:35:16.525890 channel==1
836 04:35:16.529701 RxClkDly_Margin_A0==98 ps 10
837 04:35:16.530203 TxDqDly_Margin_A0==88 ps 9
838 04:35:16.535273 RxClkDly_Margin_A1==88 ps 9
839 04:35:16.535779 TxDqDly_Margin_A1==88 ps 9
840 04:35:16.540898 TrainedVREFDQ_A0==76
841 04:35:16.541404 TrainedVREFDQ_A1==77
842 04:35:16.541837 VrefDac_Margin_A0==22
843 04:35:16.546521 DeviceVref_Margin_A0==38
844 04:35:16.547025 VrefDac_Margin_A1==24
845 04:35:16.552099 DeviceVref_Margin_A1==37
846 04:35:16.552589
847 04:35:16.553019 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 04:35:16.553446
849 04:35:16.585523 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
850 04:35:16.586089 2D training succeed
851 04:35:16.591147 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 04:35:16.596751 auto size-- 65535DDR cs0 size: 2048MB
853 04:35:16.597242 DDR cs1 size: 2048MB
854 04:35:16.602376 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 04:35:16.602858 cs0 DataBus test pass
856 04:35:16.607945 cs1 DataBus test pass
857 04:35:16.608465 cs0 AddrBus test pass
858 04:35:16.608893 cs1 AddrBus test pass
859 04:35:16.609315
860 04:35:16.613553 100bdlr_step_size ps== 420
861 04:35:16.614046 result report
862 04:35:16.619141 boot times 0Enable ddr reg access
863 04:35:16.624328 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 04:35:16.637753 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 04:35:17.210893 0.0;M3 CHK:0;cm4_sp_mode 0
866 04:35:17.211535 MVN_1=0x00000000
867 04:35:17.216441 MVN_2=0x00000000
868 04:35:17.222118 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 04:35:17.222617 OPS=0x10
870 04:35:17.223068 ring efuse init
871 04:35:17.223504 chipver efuse init
872 04:35:17.227699 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 04:35:17.233294 [0.018961 Inits done]
874 04:35:17.233785 secure task start!
875 04:35:17.234227 high task start!
876 04:35:17.237869 low task start!
877 04:35:17.238359 run into bl31
878 04:35:17.244553 NOTICE: BL31: v1.3(release):4fc40b1
879 04:35:17.252344 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 04:35:17.252847 NOTICE: BL31: G12A normal boot!
881 04:35:17.277700 NOTICE: BL31: BL33 decompress pass
882 04:35:17.283456 ERROR: Error initializing runtime service opteed_fast
883 04:35:18.516341
884 04:35:18.516996
885 04:35:18.524702 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 04:35:18.525234
887 04:35:18.525694 Model: Libre Computer AML-A311D-CC Alta
888 04:35:18.733079 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 04:35:18.756478 DRAM: 2 GiB (effective 3.8 GiB)
890 04:35:18.899496 Core: 408 devices, 31 uclasses, devicetree: separate
891 04:35:18.905375 WDT: Not starting watchdog@f0d0
892 04:35:18.937644 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 04:35:18.950065 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 04:35:18.955074 ** Bad device specification mmc 0 **
895 04:35:18.965386 Card did not respond to voltage select! : -110
896 04:35:18.973040 ** Bad device specification mmc 0 **
897 04:35:18.973556 Couldn't find partition mmc 0
898 04:35:18.981379 Card did not respond to voltage select! : -110
899 04:35:18.986887 ** Bad device specification mmc 0 **
900 04:35:18.987392 Couldn't find partition mmc 0
901 04:35:18.991960 Error: could not access storage.
902 04:35:19.334485 Net: eth0: ethernet@ff3f0000
903 04:35:19.335142 starting USB...
904 04:35:19.586253 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 04:35:19.586825 Starting the controller
906 04:35:19.593219 USB XHCI 1.10
907 04:35:21.455437 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 04:35:21.456159 bl2_stage_init 0x01
909 04:35:21.456636 bl2_stage_init 0x81
910 04:35:21.461135 hw id: 0x0000 - pwm id 0x01
911 04:35:21.461720 bl2_stage_init 0xc1
912 04:35:21.462180 bl2_stage_init 0x02
913 04:35:21.462622
914 04:35:21.466746 L0:00000000
915 04:35:21.467364 L1:20000703
916 04:35:21.467818 L2:00008067
917 04:35:21.468317 L3:14000000
918 04:35:21.472257 B2:00402000
919 04:35:21.472836 B1:e0f83180
920 04:35:21.473301
921 04:35:21.473755 TE: 58159
922 04:35:21.474201
923 04:35:21.477857 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 04:35:21.478454
925 04:35:21.478916 Board ID = 1
926 04:35:21.483436 Set A53 clk to 24M
927 04:35:21.484039 Set A73 clk to 24M
928 04:35:21.484508 Set clk81 to 24M
929 04:35:21.489078 A53 clk: 1200 MHz
930 04:35:21.489645 A73 clk: 1200 MHz
931 04:35:21.490097 CLK81: 166.6M
932 04:35:21.490540 smccc: 00012ab5
933 04:35:21.494650 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 04:35:21.500220 board id: 1
935 04:35:21.506162 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 04:35:21.516780 fw parse done
937 04:35:21.522774 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 04:35:21.565330 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 04:35:21.576295 PIEI prepare done
940 04:35:21.576809 fastboot data load
941 04:35:21.577244 fastboot data verify
942 04:35:21.581997 verify result: 266
943 04:35:21.587670 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 04:35:21.588209 LPDDR4 probe
945 04:35:21.588641 ddr clk to 1584MHz
946 04:35:21.595671 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 04:35:21.632969
948 04:35:21.633483 dmc_version 0001
949 04:35:21.639534 Check phy result
950 04:35:21.645357 INFO : End of CA training
951 04:35:21.645845 INFO : End of initialization
952 04:35:21.651047 INFO : Training has run successfully!
953 04:35:21.651552 Check phy result
954 04:35:21.656673 INFO : End of initialization
955 04:35:21.657192 INFO : End of read enable training
956 04:35:21.662266 INFO : End of fine write leveling
957 04:35:21.667791 INFO : End of Write leveling coarse delay
958 04:35:21.668321 INFO : Training has run successfully!
959 04:35:21.668769 Check phy result
960 04:35:21.673380 INFO : End of initialization
961 04:35:21.673882 INFO : End of read dq deskew training
962 04:35:21.678857 INFO : End of MPR read delay center optimization
963 04:35:21.684480 INFO : End of write delay center optimization
964 04:35:21.690095 INFO : End of read delay center optimization
965 04:35:21.690601 INFO : End of max read latency training
966 04:35:21.695714 INFO : Training has run successfully!
967 04:35:21.696270 1D training succeed
968 04:35:21.704826 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 04:35:21.752502 Check phy result
970 04:35:21.753071 INFO : End of initialization
971 04:35:21.775137 INFO : End of 2D read delay Voltage center optimization
972 04:35:21.795331 INFO : End of 2D read delay Voltage center optimization
973 04:35:21.847386 INFO : End of 2D write delay Voltage center optimization
974 04:35:21.896723 INFO : End of 2D write delay Voltage center optimization
975 04:35:21.902278 INFO : Training has run successfully!
976 04:35:21.902801
977 04:35:21.903256 channel==0
978 04:35:21.907892 RxClkDly_Margin_A0==88 ps 9
979 04:35:21.908451 TxDqDly_Margin_A0==98 ps 10
980 04:35:21.913480 RxClkDly_Margin_A1==88 ps 9
981 04:35:21.913989 TxDqDly_Margin_A1==98 ps 10
982 04:35:21.914440 TrainedVREFDQ_A0==74
983 04:35:21.919150 TrainedVREFDQ_A1==74
984 04:35:21.919677 VrefDac_Margin_A0==25
985 04:35:21.920168 DeviceVref_Margin_A0==40
986 04:35:21.924696 VrefDac_Margin_A1==24
987 04:35:21.925213 DeviceVref_Margin_A1==40
988 04:35:21.925659
989 04:35:21.926103
990 04:35:21.930286 channel==1
991 04:35:21.930801 RxClkDly_Margin_A0==98 ps 10
992 04:35:21.931250 TxDqDly_Margin_A0==98 ps 10
993 04:35:21.935876 RxClkDly_Margin_A1==88 ps 9
994 04:35:21.936429 TxDqDly_Margin_A1==88 ps 9
995 04:35:21.941478 TrainedVREFDQ_A0==77
996 04:35:21.941995 TrainedVREFDQ_A1==77
997 04:35:21.942444 VrefDac_Margin_A0==22
998 04:35:21.947143 DeviceVref_Margin_A0==37
999 04:35:21.947660 VrefDac_Margin_A1==24
1000 04:35:21.952693 DeviceVref_Margin_A1==37
1001 04:35:21.953208
1002 04:35:21.953661 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 04:35:21.954105
1004 04:35:21.986200 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000017 00000016 00000017 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1005 04:35:21.986782 2D training succeed
1006 04:35:21.991877 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 04:35:21.997477 auto size-- 65535DDR cs0 size: 2048MB
1008 04:35:21.997989 DDR cs1 size: 2048MB
1009 04:35:22.003063 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 04:35:22.003570 cs0 DataBus test pass
1011 04:35:22.008635 cs1 DataBus test pass
1012 04:35:22.009136 cs0 AddrBus test pass
1013 04:35:22.009585 cs1 AddrBus test pass
1014 04:35:22.010023
1015 04:35:22.014245 100bdlr_step_size ps== 420
1016 04:35:22.014777 result report
1017 04:35:22.019910 boot times 0Enable ddr reg access
1018 04:35:22.025285 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 04:35:22.038658 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 04:35:22.612405 0.0;M3 CHK:0;cm4_sp_mode 0
1021 04:35:22.613054 MVN_1=0x00000000
1022 04:35:22.617844 MVN_2=0x00000000
1023 04:35:22.623613 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 04:35:22.624168 OPS=0x10
1025 04:35:22.624634 ring efuse init
1026 04:35:22.625081 chipver efuse init
1027 04:35:22.629222 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 04:35:22.634791 [0.018961 Inits done]
1029 04:35:22.635291 secure task start!
1030 04:35:22.635744 high task start!
1031 04:35:22.639387 low task start!
1032 04:35:22.639887 run into bl31
1033 04:35:22.646057 NOTICE: BL31: v1.3(release):4fc40b1
1034 04:35:22.653859 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 04:35:22.654375 NOTICE: BL31: G12A normal boot!
1036 04:35:22.679317 NOTICE: BL31: BL33 decompress pass
1037 04:35:22.685004 ERROR: Error initializing runtime service opteed_fast
1038 04:35:23.917921
1039 04:35:23.918573
1040 04:35:23.926374 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 04:35:23.926893
1042 04:35:23.927345 Model: Libre Computer AML-A311D-CC Alta
1043 04:35:24.134851 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 04:35:24.158203 DRAM: 2 GiB (effective 3.8 GiB)
1045 04:35:24.301168 Core: 408 devices, 31 uclasses, devicetree: separate
1046 04:35:24.307009 WDT: Not starting watchdog@f0d0
1047 04:35:24.339268 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 04:35:24.351716 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 04:35:24.356740 ** Bad device specification mmc 0 **
1050 04:35:24.367056 Card did not respond to voltage select! : -110
1051 04:35:24.374718 ** Bad device specification mmc 0 **
1052 04:35:24.375247 Couldn't find partition mmc 0
1053 04:35:24.383062 Card did not respond to voltage select! : -110
1054 04:35:24.388604 ** Bad device specification mmc 0 **
1055 04:35:24.389156 Couldn't find partition mmc 0
1056 04:35:24.393625 Error: could not access storage.
1057 04:35:24.737083 Net: eth0: ethernet@ff3f0000
1058 04:35:24.737688 starting USB...
1059 04:35:24.988901 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 04:35:24.989483 Starting the controller
1061 04:35:24.995875 USB XHCI 1.10
1062 04:35:26.549891 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 04:35:26.558130 scanning usb for storage devices... 0 Storage Device(s) found
1065 04:35:26.609808 Hit any key to stop autoboot: 1
1066 04:35:26.610687 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1067 04:35:26.611480 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1068 04:35:26.612049 Setting prompt string to ['=>']
1069 04:35:26.612581 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1070 04:35:26.625547 0
1071 04:35:26.626488 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 04:35:26.627015 Sending with 10 millisecond of delay
1074 04:35:27.761859 => setenv autoload no
1075 04:35:27.772706 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1076 04:35:27.778129 setenv autoload no
1077 04:35:27.778917 Sending with 10 millisecond of delay
1079 04:35:29.575971 => setenv initrd_high 0xffffffff
1080 04:35:29.586864 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1081 04:35:29.587800 setenv initrd_high 0xffffffff
1082 04:35:29.588612 Sending with 10 millisecond of delay
1084 04:35:31.205621 => setenv fdt_high 0xffffffff
1085 04:35:31.216187 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1086 04:35:31.216715 setenv fdt_high 0xffffffff
1087 04:35:31.217214 Sending with 10 millisecond of delay
1089 04:35:31.508746 => dhcp
1090 04:35:31.519361 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1091 04:35:31.519950 dhcp
1092 04:35:31.520240 Speed: 1000, full duplex
1093 04:35:31.520457 BOOTP broadcast 1
1094 04:35:31.760074 DHCP client bound to address 192.168.6.27 (240 ms)
1095 04:35:31.760737 Sending with 10 millisecond of delay
1097 04:35:33.437770 => setenv serverip 192.168.6.2
1098 04:35:33.448334 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1099 04:35:33.448902 setenv serverip 192.168.6.2
1100 04:35:33.449373 Sending with 10 millisecond of delay
1102 04:35:37.174717 => tftpboot 0x01080000 950932/tftp-deploy-kabzueha/kernel/uImage
1103 04:35:37.185547 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1104 04:35:37.186444 tftpboot 0x01080000 950932/tftp-deploy-kabzueha/kernel/uImage
1105 04:35:37.186870 Speed: 1000, full duplex
1106 04:35:37.187267 Using ethernet@ff3f0000 device
1107 04:35:37.188326 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1108 04:35:37.193728 Filename '950932/tftp-deploy-kabzueha/kernel/uImage'.
1109 04:35:37.197770 Load address: 0x1080000
1110 04:35:40.236354 Loading: *################################################## 43.6 MiB
1111 04:35:40.236781 14.3 MiB/s
1112 04:35:40.237000 done
1113 04:35:40.240639 Bytes transferred = 45713984 (2b98a40 hex)
1114 04:35:40.241255 Sending with 10 millisecond of delay
1116 04:35:44.927855 => tftpboot 0x08000000 950932/tftp-deploy-kabzueha/ramdisk/ramdisk.cpio.gz.uboot
1117 04:35:44.938682 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1118 04:35:44.939626 tftpboot 0x08000000 950932/tftp-deploy-kabzueha/ramdisk/ramdisk.cpio.gz.uboot
1119 04:35:44.940142 Speed: 1000, full duplex
1120 04:35:44.940587 Using ethernet@ff3f0000 device
1121 04:35:44.941567 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1122 04:35:44.952412 Filename '950932/tftp-deploy-kabzueha/ramdisk/ramdisk.cpio.gz.uboot'.
1123 04:35:44.952953 Load address: 0x8000000
1124 04:35:54.157625 Loading: *######T ########################################### UDP wrong checksum 0000000f 00007174
1125 04:35:59.157593 T UDP wrong checksum 0000000f 00007174
1126 04:36:09.161048 T T UDP wrong checksum 0000000f 00007174
1127 04:36:29.165159 T T T T UDP wrong checksum 0000000f 00007174
1128 04:36:38.293202 T UDP wrong checksum 000000ff 00005ec8
1129 04:36:38.297515 UDP wrong checksum 000000ff 0000ecba
1130 04:36:44.169013 T
1131 04:36:44.169697 Retry count exceeded; starting again
1133 04:36:44.171218 end: 2.4.3 bootloader-commands (duration 00:01:18) [common]
1136 04:36:44.173282 end: 2.4 uboot-commands (duration 00:01:54) [common]
1138 04:36:44.174760 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1140 04:36:44.175921 end: 2 uboot-action (duration 00:01:54) [common]
1142 04:36:44.177676 Cleaning after the job
1143 04:36:44.178314 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950932/tftp-deploy-kabzueha/ramdisk
1144 04:36:44.179737 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950932/tftp-deploy-kabzueha/kernel
1145 04:36:44.227476 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950932/tftp-deploy-kabzueha/dtb
1146 04:36:44.228397 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950932/tftp-deploy-kabzueha/modules
1147 04:36:44.247226 start: 4.1 power-off (timeout 00:00:30) [common]
1148 04:36:44.247889 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1149 04:36:44.281292 >> OK - accepted request
1150 04:36:44.283116 Returned 0 in 0 seconds
1151 04:36:44.384122 end: 4.1 power-off (duration 00:00:00) [common]
1153 04:36:44.386010 start: 4.2 read-feedback (timeout 00:10:00) [common]
1154 04:36:44.387181 Listened to connection for namespace 'common' for up to 1s
1155 04:36:45.388091 Finalising connection for namespace 'common'
1156 04:36:45.388903 Disconnecting from shell: Finalise
1157 04:36:45.389485 =>
1158 04:36:45.490664 end: 4.2 read-feedback (duration 00:00:01) [common]
1159 04:36:45.491463 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/950932
1160 04:36:46.147372 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/950932
1161 04:36:46.148002 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.