Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 5
- Errors: 0
- Boot result: PASS
- Kernel Errors: 3
1 04:37:10.506532 lava-dispatcher, installed at version: 2024.01
2 04:37:10.507311 start: 0 validate
3 04:37:10.507785 Start time: 2024-11-07 04:37:10.507754+00:00 (UTC)
4 04:37:10.508349 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 04:37:10.508907 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 04:37:10.549016 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 04:37:10.549578 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-235-gf366870b9966d%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 04:37:10.578184 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 04:37:10.578816 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-235-gf366870b9966d%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 04:37:10.608642 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 04:37:10.609232 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 04:37:10.640501 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 04:37:10.640989 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-235-gf366870b9966d%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 04:37:10.679603 validate duration: 0.17
16 04:37:10.680668 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 04:37:10.681084 start: 1.1 download-retry (timeout 00:10:00) [common]
18 04:37:10.681489 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 04:37:10.682225 Not decompressing ramdisk as can be used compressed.
20 04:37:10.682815 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 04:37:10.683189 saving as /var/lib/lava/dispatcher/tmp/950934/tftp-deploy-y6z2r49c/ramdisk/initrd.cpio.gz
22 04:37:10.683541 total size: 5628169 (5 MB)
23 04:37:10.724921 progress 0 % (0 MB)
24 04:37:10.730082 progress 5 % (0 MB)
25 04:37:10.735275 progress 10 % (0 MB)
26 04:37:10.739939 progress 15 % (0 MB)
27 04:37:10.744924 progress 20 % (1 MB)
28 04:37:10.749436 progress 25 % (1 MB)
29 04:37:10.754286 progress 30 % (1 MB)
30 04:37:10.759147 progress 35 % (1 MB)
31 04:37:10.763582 progress 40 % (2 MB)
32 04:37:10.768463 progress 45 % (2 MB)
33 04:37:10.772815 progress 50 % (2 MB)
34 04:37:10.777792 progress 55 % (2 MB)
35 04:37:10.782537 progress 60 % (3 MB)
36 04:37:10.786820 progress 65 % (3 MB)
37 04:37:10.791645 progress 70 % (3 MB)
38 04:37:10.795926 progress 75 % (4 MB)
39 04:37:10.800896 progress 80 % (4 MB)
40 04:37:10.805225 progress 85 % (4 MB)
41 04:37:10.810002 progress 90 % (4 MB)
42 04:37:10.814649 progress 95 % (5 MB)
43 04:37:10.818577 progress 100 % (5 MB)
44 04:37:10.819360 5 MB downloaded in 0.14 s (39.53 MB/s)
45 04:37:10.820028 end: 1.1.1 http-download (duration 00:00:00) [common]
47 04:37:10.821144 end: 1.1 download-retry (duration 00:00:00) [common]
48 04:37:10.821506 start: 1.2 download-retry (timeout 00:10:00) [common]
49 04:37:10.821844 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 04:37:10.822419 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-235-gf366870b9966d/arm64/defconfig/gcc-12/kernel/Image
51 04:37:10.822750 saving as /var/lib/lava/dispatcher/tmp/950934/tftp-deploy-y6z2r49c/kernel/Image
52 04:37:10.823014 total size: 45713920 (43 MB)
53 04:37:10.823277 No compression specified
54 04:37:10.863859 progress 0 % (0 MB)
55 04:37:10.898157 progress 5 % (2 MB)
56 04:37:10.931580 progress 10 % (4 MB)
57 04:37:10.965093 progress 15 % (6 MB)
58 04:37:10.998435 progress 20 % (8 MB)
59 04:37:11.031778 progress 25 % (10 MB)
60 04:37:11.065123 progress 30 % (13 MB)
61 04:37:11.098462 progress 35 % (15 MB)
62 04:37:11.131737 progress 40 % (17 MB)
63 04:37:11.164847 progress 45 % (19 MB)
64 04:37:11.198351 progress 50 % (21 MB)
65 04:37:11.231547 progress 55 % (24 MB)
66 04:37:11.264877 progress 60 % (26 MB)
67 04:37:11.297823 progress 65 % (28 MB)
68 04:37:11.331285 progress 70 % (30 MB)
69 04:37:11.364565 progress 75 % (32 MB)
70 04:37:11.397913 progress 80 % (34 MB)
71 04:37:11.431371 progress 85 % (37 MB)
72 04:37:11.464849 progress 90 % (39 MB)
73 04:37:11.498057 progress 95 % (41 MB)
74 04:37:11.531186 progress 100 % (43 MB)
75 04:37:11.531884 43 MB downloaded in 0.71 s (61.50 MB/s)
76 04:37:11.532526 end: 1.2.1 http-download (duration 00:00:01) [common]
78 04:37:11.533530 end: 1.2 download-retry (duration 00:00:01) [common]
79 04:37:11.533865 start: 1.3 download-retry (timeout 00:09:59) [common]
80 04:37:11.534192 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 04:37:11.534774 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-235-gf366870b9966d/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 04:37:11.535111 saving as /var/lib/lava/dispatcher/tmp/950934/tftp-deploy-y6z2r49c/dtb/meson-g12b-a311d-libretech-cc.dtb
83 04:37:11.535373 total size: 54703 (0 MB)
84 04:37:11.535626 No compression specified
85 04:37:11.581446 progress 59 % (0 MB)
86 04:37:11.582471 progress 100 % (0 MB)
87 04:37:11.583136 0 MB downloaded in 0.05 s (1.09 MB/s)
88 04:37:11.583692 end: 1.3.1 http-download (duration 00:00:00) [common]
90 04:37:11.584742 end: 1.3 download-retry (duration 00:00:00) [common]
91 04:37:11.585066 start: 1.4 download-retry (timeout 00:09:59) [common]
92 04:37:11.585387 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 04:37:11.585947 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 04:37:11.586245 saving as /var/lib/lava/dispatcher/tmp/950934/tftp-deploy-y6z2r49c/nfsrootfs/full.rootfs.tar
95 04:37:11.586496 total size: 120894716 (115 MB)
96 04:37:11.586755 Using unxz to decompress xz
97 04:37:11.626343 progress 0 % (0 MB)
98 04:37:12.408752 progress 5 % (5 MB)
99 04:37:13.254801 progress 10 % (11 MB)
100 04:37:14.041575 progress 15 % (17 MB)
101 04:37:14.772922 progress 20 % (23 MB)
102 04:37:15.362669 progress 25 % (28 MB)
103 04:37:16.180317 progress 30 % (34 MB)
104 04:37:16.963760 progress 35 % (40 MB)
105 04:37:17.312093 progress 40 % (46 MB)
106 04:37:17.685234 progress 45 % (51 MB)
107 04:37:18.411749 progress 50 % (57 MB)
108 04:37:19.289068 progress 55 % (63 MB)
109 04:37:20.065406 progress 60 % (69 MB)
110 04:37:20.882196 progress 65 % (74 MB)
111 04:37:21.801157 progress 70 % (80 MB)
112 04:37:22.769776 progress 75 % (86 MB)
113 04:37:23.699213 progress 80 % (92 MB)
114 04:37:24.468995 progress 85 % (98 MB)
115 04:37:25.409368 progress 90 % (103 MB)
116 04:37:26.231707 progress 95 % (109 MB)
117 04:37:27.055971 progress 100 % (115 MB)
118 04:37:27.068496 115 MB downloaded in 15.48 s (7.45 MB/s)
119 04:37:27.069349 end: 1.4.1 http-download (duration 00:00:15) [common]
121 04:37:27.070912 end: 1.4 download-retry (duration 00:00:15) [common]
122 04:37:27.071418 start: 1.5 download-retry (timeout 00:09:44) [common]
123 04:37:27.071920 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 04:37:27.072877 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-235-gf366870b9966d/arm64/defconfig/gcc-12/modules.tar.xz
125 04:37:27.073342 saving as /var/lib/lava/dispatcher/tmp/950934/tftp-deploy-y6z2r49c/modules/modules.tar
126 04:37:27.073744 total size: 11607584 (11 MB)
127 04:37:27.074154 Using unxz to decompress xz
128 04:37:27.116900 progress 0 % (0 MB)
129 04:37:27.182902 progress 5 % (0 MB)
130 04:37:27.256131 progress 10 % (1 MB)
131 04:37:27.352263 progress 15 % (1 MB)
132 04:37:27.442383 progress 20 % (2 MB)
133 04:37:27.526039 progress 25 % (2 MB)
134 04:37:27.602588 progress 30 % (3 MB)
135 04:37:27.675882 progress 35 % (3 MB)
136 04:37:27.751906 progress 40 % (4 MB)
137 04:37:27.827068 progress 45 % (5 MB)
138 04:37:27.910161 progress 50 % (5 MB)
139 04:37:27.986384 progress 55 % (6 MB)
140 04:37:28.071746 progress 60 % (6 MB)
141 04:37:28.153573 progress 65 % (7 MB)
142 04:37:28.231385 progress 70 % (7 MB)
143 04:37:28.314161 progress 75 % (8 MB)
144 04:37:28.397969 progress 80 % (8 MB)
145 04:37:28.478671 progress 85 % (9 MB)
146 04:37:28.557624 progress 90 % (9 MB)
147 04:37:28.637332 progress 95 % (10 MB)
148 04:37:28.716542 progress 100 % (11 MB)
149 04:37:28.727795 11 MB downloaded in 1.65 s (6.69 MB/s)
150 04:37:28.728752 end: 1.5.1 http-download (duration 00:00:02) [common]
152 04:37:28.730595 end: 1.5 download-retry (duration 00:00:02) [common]
153 04:37:28.731170 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 04:37:28.731736 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 04:37:44.872734 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/950934/extract-nfsrootfs-k6hj5bfk
156 04:37:44.873336 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 04:37:44.873624 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 04:37:44.874375 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u
159 04:37:44.874819 makedir: /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin
160 04:37:44.875139 makedir: /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/tests
161 04:37:44.875450 makedir: /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/results
162 04:37:44.875781 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-add-keys
163 04:37:44.876420 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-add-sources
164 04:37:44.876939 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-background-process-start
165 04:37:44.877436 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-background-process-stop
166 04:37:44.877971 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-common-functions
167 04:37:44.878467 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-echo-ipv4
168 04:37:44.878941 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-install-packages
169 04:37:44.879406 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-installed-packages
170 04:37:44.879863 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-os-build
171 04:37:44.880368 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-probe-channel
172 04:37:44.880861 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-probe-ip
173 04:37:44.881380 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-target-ip
174 04:37:44.881852 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-target-mac
175 04:37:44.882326 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-target-storage
176 04:37:44.882802 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-test-case
177 04:37:44.883273 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-test-event
178 04:37:44.883737 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-test-feedback
179 04:37:44.884234 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-test-raise
180 04:37:44.884728 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-test-reference
181 04:37:44.885229 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-test-runner
182 04:37:44.885706 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-test-set
183 04:37:44.886170 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-test-shell
184 04:37:44.886644 Updating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-add-keys (debian)
185 04:37:44.887163 Updating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-add-sources (debian)
186 04:37:44.887654 Updating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-install-packages (debian)
187 04:37:44.888175 Updating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-installed-packages (debian)
188 04:37:44.888692 Updating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/bin/lava-os-build (debian)
189 04:37:44.889123 Creating /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/environment
190 04:37:44.889493 LAVA metadata
191 04:37:44.889752 - LAVA_JOB_ID=950934
192 04:37:44.889966 - LAVA_DISPATCHER_IP=192.168.6.2
193 04:37:44.890314 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 04:37:44.891234 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 04:37:44.891536 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 04:37:44.891741 skipped lava-vland-overlay
197 04:37:44.892000 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 04:37:44.892261 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 04:37:44.892478 skipped lava-multinode-overlay
200 04:37:44.892715 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 04:37:44.892962 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 04:37:44.893207 Loading test definitions
203 04:37:44.893479 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 04:37:44.893695 Using /lava-950934 at stage 0
205 04:37:44.894750 uuid=950934_1.6.2.4.1 testdef=None
206 04:37:44.895052 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 04:37:44.895313 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 04:37:44.896859 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 04:37:44.897642 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 04:37:44.899522 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 04:37:44.900367 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 04:37:44.902158 runner path: /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/0/tests/0_timesync-off test_uuid 950934_1.6.2.4.1
215 04:37:44.902701 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 04:37:44.903502 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 04:37:44.903724 Using /lava-950934 at stage 0
219 04:37:44.904091 Fetching tests from https://github.com/kernelci/test-definitions.git
220 04:37:44.904381 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/0/tests/1_kselftest-alsa'
221 04:37:48.334850 Running '/usr/bin/git checkout kernelci.org
222 04:37:48.630798 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 04:37:48.632548 uuid=950934_1.6.2.4.5 testdef=None
224 04:37:48.633215 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 04:37:48.634811 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 04:37:48.640737 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 04:37:48.642460 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 04:37:48.650302 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 04:37:48.652145 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 04:37:48.659800 runner path: /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/0/tests/1_kselftest-alsa test_uuid 950934_1.6.2.4.5
234 04:37:48.660478 BOARD='meson-g12b-a311d-libretech-cc'
235 04:37:48.660928 BRANCH='broonie-sound'
236 04:37:48.661362 SKIPFILE='/dev/null'
237 04:37:48.661798 SKIP_INSTALL='True'
238 04:37:48.662227 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-235-gf366870b9966d/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 04:37:48.662666 TST_CASENAME=''
240 04:37:48.663098 TST_CMDFILES='alsa'
241 04:37:48.664194 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 04:37:48.665869 Creating lava-test-runner.conf files
244 04:37:48.666313 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/950934/lava-overlay-catfqh_u/lava-950934/0 for stage 0
245 04:37:48.666996 - 0_timesync-off
246 04:37:48.667485 - 1_kselftest-alsa
247 04:37:48.668218 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 04:37:48.668826 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 04:38:11.986300 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 04:38:11.986750 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 04:38:11.987015 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 04:38:11.987287 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 04:38:11.987552 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 04:38:12.598659 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 04:38:12.599137 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 04:38:12.599388 extracting modules file /var/lib/lava/dispatcher/tmp/950934/tftp-deploy-y6z2r49c/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950934/extract-nfsrootfs-k6hj5bfk
257 04:38:13.940157 extracting modules file /var/lib/lava/dispatcher/tmp/950934/tftp-deploy-y6z2r49c/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950934/extract-overlay-ramdisk-gphrfrnc/ramdisk
258 04:38:15.353896 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 04:38:15.354391 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 04:38:15.354675 [common] Applying overlay to NFS
261 04:38:15.354913 [common] Applying overlay /var/lib/lava/dispatcher/tmp/950934/compress-overlay-kx1j_jmi/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/950934/extract-nfsrootfs-k6hj5bfk
262 04:38:18.116742 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 04:38:18.117226 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 04:38:18.117506 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 04:38:18.117736 Converting downloaded kernel to a uImage
266 04:38:18.118046 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/950934/tftp-deploy-y6z2r49c/kernel/Image /var/lib/lava/dispatcher/tmp/950934/tftp-deploy-y6z2r49c/kernel/uImage
267 04:38:18.680919 output: Image Name:
268 04:38:18.681346 output: Created: Thu Nov 7 04:38:18 2024
269 04:38:18.681556 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 04:38:18.681763 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 04:38:18.681963 output: Load Address: 01080000
272 04:38:18.682162 output: Entry Point: 01080000
273 04:38:18.682358 output:
274 04:38:18.682688 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 04:38:18.682955 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 04:38:18.683225 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 04:38:18.683477 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 04:38:18.683733 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 04:38:18.684025 Building ramdisk /var/lib/lava/dispatcher/tmp/950934/extract-overlay-ramdisk-gphrfrnc/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/950934/extract-overlay-ramdisk-gphrfrnc/ramdisk
280 04:38:20.799292 >> 166792 blocks
281 04:38:28.495724 Adding RAMdisk u-boot header.
282 04:38:28.496485 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/950934/extract-overlay-ramdisk-gphrfrnc/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/950934/extract-overlay-ramdisk-gphrfrnc/ramdisk.cpio.gz.uboot
283 04:38:28.745517 output: Image Name:
284 04:38:28.745933 output: Created: Thu Nov 7 04:38:28 2024
285 04:38:28.746144 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 04:38:28.746350 output: Data Size: 23432398 Bytes = 22883.20 KiB = 22.35 MiB
287 04:38:28.746552 output: Load Address: 00000000
288 04:38:28.746751 output: Entry Point: 00000000
289 04:38:28.747107 output:
290 04:38:28.748275 rename /var/lib/lava/dispatcher/tmp/950934/extract-overlay-ramdisk-gphrfrnc/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/950934/tftp-deploy-y6z2r49c/ramdisk/ramdisk.cpio.gz.uboot
291 04:38:28.749015 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 04:38:28.749594 end: 1.6 prepare-tftp-overlay (duration 00:01:00) [common]
293 04:38:28.750189 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 04:38:28.750780 No LXC device requested
295 04:38:28.751398 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 04:38:28.751941 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 04:38:28.752489 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 04:38:28.752923 Checking files for TFTP limit of 4294967296 bytes.
299 04:38:28.755570 end: 1 tftp-deploy (duration 00:01:18) [common]
300 04:38:28.756235 start: 2 uboot-action (timeout 00:05:00) [common]
301 04:38:28.756837 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 04:38:28.757356 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 04:38:28.757872 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 04:38:28.758410 Using kernel file from prepare-kernel: 950934/tftp-deploy-y6z2r49c/kernel/uImage
305 04:38:28.759046 substitutions:
306 04:38:28.759461 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 04:38:28.759872 - {DTB_ADDR}: 0x01070000
308 04:38:28.760313 - {DTB}: 950934/tftp-deploy-y6z2r49c/dtb/meson-g12b-a311d-libretech-cc.dtb
309 04:38:28.762793 - {INITRD}: 950934/tftp-deploy-y6z2r49c/ramdisk/ramdisk.cpio.gz.uboot
310 04:38:28.763299 - {KERNEL_ADDR}: 0x01080000
311 04:38:28.763716 - {KERNEL}: 950934/tftp-deploy-y6z2r49c/kernel/uImage
312 04:38:28.764159 - {LAVA_MAC}: None
313 04:38:28.764613 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/950934/extract-nfsrootfs-k6hj5bfk
314 04:38:28.765023 - {NFS_SERVER_IP}: 192.168.6.2
315 04:38:28.765420 - {PRESEED_CONFIG}: None
316 04:38:28.765816 - {PRESEED_LOCAL}: None
317 04:38:28.766213 - {RAMDISK_ADDR}: 0x08000000
318 04:38:28.766603 - {RAMDISK}: 950934/tftp-deploy-y6z2r49c/ramdisk/ramdisk.cpio.gz.uboot
319 04:38:28.766995 - {ROOT_PART}: None
320 04:38:28.767387 - {ROOT}: None
321 04:38:28.767776 - {SERVER_IP}: 192.168.6.2
322 04:38:28.768201 - {TEE_ADDR}: 0x83000000
323 04:38:28.768595 - {TEE}: None
324 04:38:28.768987 Parsed boot commands:
325 04:38:28.769368 - setenv autoload no
326 04:38:28.769757 - setenv initrd_high 0xffffffff
327 04:38:28.770145 - setenv fdt_high 0xffffffff
328 04:38:28.770531 - dhcp
329 04:38:28.770916 - setenv serverip 192.168.6.2
330 04:38:28.771311 - tftpboot 0x01080000 950934/tftp-deploy-y6z2r49c/kernel/uImage
331 04:38:28.771703 - tftpboot 0x08000000 950934/tftp-deploy-y6z2r49c/ramdisk/ramdisk.cpio.gz.uboot
332 04:38:28.772149 - tftpboot 0x01070000 950934/tftp-deploy-y6z2r49c/dtb/meson-g12b-a311d-libretech-cc.dtb
333 04:38:28.772555 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/950934/extract-nfsrootfs-k6hj5bfk,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 04:38:28.772962 - bootm 0x01080000 0x08000000 0x01070000
335 04:38:28.773488 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 04:38:28.775006 start: 2.3 connect-device (timeout 00:05:00) [common]
338 04:38:28.775438 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 04:38:28.791877 Setting prompt string to ['lava-test: # ']
340 04:38:28.793433 end: 2.3 connect-device (duration 00:00:00) [common]
341 04:38:28.794068 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 04:38:28.794653 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 04:38:28.795473 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 04:38:28.796734 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 04:38:28.834923 >> OK - accepted request
346 04:38:28.837080 Returned 0 in 0 seconds
347 04:38:28.938180 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 04:38:28.939800 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 04:38:28.940436 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 04:38:28.940951 Setting prompt string to ['Hit any key to stop autoboot']
352 04:38:28.941423 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 04:38:28.942978 Trying 192.168.56.21...
354 04:38:28.943456 Connected to conserv1.
355 04:38:28.943868 Escape character is '^]'.
356 04:38:28.944319
357 04:38:28.944752 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 04:38:28.945192
359 04:38:39.936193 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 04:38:39.936831 bl2_stage_init 0x01
361 04:38:39.937252 bl2_stage_init 0x81
362 04:38:39.941742 hw id: 0x0000 - pwm id 0x01
363 04:38:39.942196 bl2_stage_init 0xc1
364 04:38:39.942609 bl2_stage_init 0x02
365 04:38:39.943007
366 04:38:39.947192 L0:00000000
367 04:38:39.947644 L1:20000703
368 04:38:39.948097 L2:00008067
369 04:38:39.948502 L3:14000000
370 04:38:39.950111 B2:00402000
371 04:38:39.950546 B1:e0f83180
372 04:38:39.950933
373 04:38:39.951319 TE: 58124
374 04:38:39.951700
375 04:38:39.961162 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 04:38:39.961585
377 04:38:39.961968 Board ID = 1
378 04:38:39.962347 Set A53 clk to 24M
379 04:38:39.962725 Set A73 clk to 24M
380 04:38:39.966694 Set clk81 to 24M
381 04:38:39.967108 A53 clk: 1200 MHz
382 04:38:39.967488 A73 clk: 1200 MHz
383 04:38:39.970294 CLK81: 166.6M
384 04:38:39.970697 smccc: 00012a91
385 04:38:39.975891 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 04:38:39.981412 board id: 1
387 04:38:39.986692 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 04:38:39.997373 fw parse done
389 04:38:40.003305 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 04:38:40.045973 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 04:38:40.056861 PIEI prepare done
392 04:38:40.057268 fastboot data load
393 04:38:40.057656 fastboot data verify
394 04:38:40.062489 verify result: 266
395 04:38:40.068100 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 04:38:40.068593 LPDDR4 probe
397 04:38:40.068988 ddr clk to 1584MHz
398 04:38:40.076166 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 04:38:40.113330
400 04:38:40.113758 dmc_version 0001
401 04:38:40.119957 Check phy result
402 04:38:40.125791 INFO : End of CA training
403 04:38:40.126203 INFO : End of initialization
404 04:38:40.131480 INFO : Training has run successfully!
405 04:38:40.131901 Check phy result
406 04:38:40.137002 INFO : End of initialization
407 04:38:40.137414 INFO : End of read enable training
408 04:38:40.140373 INFO : End of fine write leveling
409 04:38:40.145925 INFO : End of Write leveling coarse delay
410 04:38:40.151526 INFO : Training has run successfully!
411 04:38:40.151940 Check phy result
412 04:38:40.152376 INFO : End of initialization
413 04:38:40.157122 INFO : End of read dq deskew training
414 04:38:40.160530 INFO : End of MPR read delay center optimization
415 04:38:40.166035 INFO : End of write delay center optimization
416 04:38:40.171639 INFO : End of read delay center optimization
417 04:38:40.172102 INFO : End of max read latency training
418 04:38:40.177244 INFO : Training has run successfully!
419 04:38:40.177657 1D training succeed
420 04:38:40.185480 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 04:38:40.233043 Check phy result
422 04:38:40.233467 INFO : End of initialization
423 04:38:40.254792 INFO : End of 2D read delay Voltage center optimization
424 04:38:40.274972 INFO : End of 2D read delay Voltage center optimization
425 04:38:40.327117 INFO : End of 2D write delay Voltage center optimization
426 04:38:40.376510 INFO : End of 2D write delay Voltage center optimization
427 04:38:40.382033 INFO : Training has run successfully!
428 04:38:40.382457
429 04:38:40.382853 channel==0
430 04:38:40.387633 RxClkDly_Margin_A0==88 ps 9
431 04:38:40.388098 TxDqDly_Margin_A0==98 ps 10
432 04:38:40.393119 RxClkDly_Margin_A1==88 ps 9
433 04:38:40.393542 TxDqDly_Margin_A1==98 ps 10
434 04:38:40.393931 TrainedVREFDQ_A0==74
435 04:38:40.398804 TrainedVREFDQ_A1==74
436 04:38:40.399218 VrefDac_Margin_A0==25
437 04:38:40.399604 DeviceVref_Margin_A0==40
438 04:38:40.404369 VrefDac_Margin_A1==25
439 04:38:40.404782 DeviceVref_Margin_A1==40
440 04:38:40.405168
441 04:38:40.405552
442 04:38:40.409923 channel==1
443 04:38:40.410339 RxClkDly_Margin_A0==98 ps 10
444 04:38:40.410727 TxDqDly_Margin_A0==98 ps 10
445 04:38:40.415722 RxClkDly_Margin_A1==88 ps 9
446 04:38:40.416184 TxDqDly_Margin_A1==88 ps 9
447 04:38:40.421300 TrainedVREFDQ_A0==77
448 04:38:40.421714 TrainedVREFDQ_A1==77
449 04:38:40.422103 VrefDac_Margin_A0==22
450 04:38:40.426830 DeviceVref_Margin_A0==37
451 04:38:40.427263 VrefDac_Margin_A1==24
452 04:38:40.432420 DeviceVref_Margin_A1==37
453 04:38:40.432833
454 04:38:40.433223 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 04:38:40.433609
456 04:38:40.466000 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
457 04:38:40.466506 2D training succeed
458 04:38:40.471651 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 04:38:40.477073 auto size-- 65535DDR cs0 size: 2048MB
460 04:38:40.477490 DDR cs1 size: 2048MB
461 04:38:40.482677 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 04:38:40.483086 cs0 DataBus test pass
463 04:38:40.488358 cs1 DataBus test pass
464 04:38:40.488768 cs0 AddrBus test pass
465 04:38:40.489154 cs1 AddrBus test pass
466 04:38:40.489537
467 04:38:40.493905 100bdlr_step_size ps== 420
468 04:38:40.494325 result report
469 04:38:40.499527 boot times 0Enable ddr reg access
470 04:38:40.504856 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 04:38:40.518324 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 04:38:41.092216 0.0;M3 CHK:0;cm4_sp_mode 0
473 04:38:41.092833 MVN_1=0x00000000
474 04:38:41.097632 MVN_2=0x00000000
475 04:38:41.103291 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 04:38:41.103719 OPS=0x10
477 04:38:41.104155 ring efuse init
478 04:38:41.104543 chipver efuse init
479 04:38:41.108901 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 04:38:41.114576 [0.018961 Inits done]
481 04:38:41.115000 secure task start!
482 04:38:41.115390 high task start!
483 04:38:41.119061 low task start!
484 04:38:41.119476 run into bl31
485 04:38:41.125738 NOTICE: BL31: v1.3(release):4fc40b1
486 04:38:41.133551 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 04:38:41.134010 NOTICE: BL31: G12A normal boot!
488 04:38:41.158919 NOTICE: BL31: BL33 decompress pass
489 04:38:41.164677 ERROR: Error initializing runtime service opteed_fast
490 04:38:42.397537
491 04:38:42.398157
492 04:38:42.405901 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 04:38:42.406340
494 04:38:42.406741 Model: Libre Computer AML-A311D-CC Alta
495 04:38:42.614391 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 04:38:42.637853 DRAM: 2 GiB (effective 3.8 GiB)
497 04:38:42.781070 Core: 408 devices, 31 uclasses, devicetree: separate
498 04:38:42.786491 WDT: Not starting watchdog@f0d0
499 04:38:42.819001 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 04:38:42.831295 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 04:38:42.836288 ** Bad device specification mmc 0 **
502 04:38:42.846635 Card did not respond to voltage select! : -110
503 04:38:42.854282 ** Bad device specification mmc 0 **
504 04:38:42.854716 Couldn't find partition mmc 0
505 04:38:42.862598 Card did not respond to voltage select! : -110
506 04:38:42.868145 ** Bad device specification mmc 0 **
507 04:38:42.868576 Couldn't find partition mmc 0
508 04:38:42.873127 Error: could not access storage.
509 04:38:44.136472 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
510 04:38:44.137110 bl2_stage_init 0x81
511 04:38:44.142016 hw id: 0x0000 - pwm id 0x01
512 04:38:44.142522 bl2_stage_init 0xc1
513 04:38:44.142940 bl2_stage_init 0x02
514 04:38:44.143339
515 04:38:44.147650 L0:00000000
516 04:38:44.148249 L1:20000703
517 04:38:44.148663 L2:00008067
518 04:38:44.149059 L3:14000000
519 04:38:44.149457 B2:00402000
520 04:38:44.150403 B1:e0f83180
521 04:38:44.150875
522 04:38:44.151294 TE: 58141
523 04:38:44.151701
524 04:38:44.161574 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
525 04:38:44.162061
526 04:38:44.162474 Board ID = 1
527 04:38:44.162879 Set A53 clk to 24M
528 04:38:44.163279 Set A73 clk to 24M
529 04:38:44.167186 Set clk81 to 24M
530 04:38:44.167653 A53 clk: 1200 MHz
531 04:38:44.168090 A73 clk: 1200 MHz
532 04:38:44.172772 CLK81: 166.6M
533 04:38:44.173207 smccc: 00012aa3
534 04:38:44.178367 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
535 04:38:44.178801 board id: 1
536 04:38:44.187057 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
537 04:38:44.197624 fw parse done
538 04:38:44.203580 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 04:38:44.246231 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
540 04:38:44.257131 PIEI prepare done
541 04:38:44.257557 fastboot data load
542 04:38:44.257963 fastboot data verify
543 04:38:44.262719 verify result: 266
544 04:38:44.268313 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
545 04:38:44.268731 LPDDR4 probe
546 04:38:44.269132 ddr clk to 1584MHz
547 04:38:44.276292 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
548 04:38:44.313530
549 04:38:44.313977 dmc_version 0001
550 04:38:44.320226 Check phy result
551 04:38:44.326086 INFO : End of CA training
552 04:38:44.326512 INFO : End of initialization
553 04:38:44.331680 INFO : Training has run successfully!
554 04:38:44.332141 Check phy result
555 04:38:44.337308 INFO : End of initialization
556 04:38:44.337741 INFO : End of read enable training
557 04:38:44.343034 INFO : End of fine write leveling
558 04:38:44.348517 INFO : End of Write leveling coarse delay
559 04:38:44.348939 INFO : Training has run successfully!
560 04:38:44.349338 Check phy result
561 04:38:44.354101 INFO : End of initialization
562 04:38:44.354528 INFO : End of read dq deskew training
563 04:38:44.359703 INFO : End of MPR read delay center optimization
564 04:38:44.365266 INFO : End of write delay center optimization
565 04:38:44.371011 INFO : End of read delay center optimization
566 04:38:44.371437 INFO : End of max read latency training
567 04:38:44.376664 INFO : Training has run successfully!
568 04:38:44.377131 1D training succeed
569 04:38:44.385730 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
570 04:38:44.433491 Check phy result
571 04:38:44.434044 INFO : End of initialization
572 04:38:44.455922 INFO : End of 2D read delay Voltage center optimization
573 04:38:44.476184 INFO : End of 2D read delay Voltage center optimization
574 04:38:44.528309 INFO : End of 2D write delay Voltage center optimization
575 04:38:44.577565 INFO : End of 2D write delay Voltage center optimization
576 04:38:44.583113 INFO : Training has run successfully!
577 04:38:44.583561
578 04:38:44.583976 channel==0
579 04:38:44.588678 RxClkDly_Margin_A0==88 ps 9
580 04:38:44.589113 TxDqDly_Margin_A0==98 ps 10
581 04:38:44.592083 RxClkDly_Margin_A1==88 ps 9
582 04:38:44.592550 TxDqDly_Margin_A1==88 ps 9
583 04:38:44.597582 TrainedVREFDQ_A0==74
584 04:38:44.598034 TrainedVREFDQ_A1==74
585 04:38:44.598441 VrefDac_Margin_A0==24
586 04:38:44.603166 DeviceVref_Margin_A0==40
587 04:38:44.603596 VrefDac_Margin_A1==24
588 04:38:44.608779 DeviceVref_Margin_A1==40
589 04:38:44.609220
590 04:38:44.609627
591 04:38:44.610031 channel==1
592 04:38:44.610425 RxClkDly_Margin_A0==88 ps 9
593 04:38:44.614380 TxDqDly_Margin_A0==98 ps 10
594 04:38:44.614817 RxClkDly_Margin_A1==88 ps 9
595 04:38:44.620067 TxDqDly_Margin_A1==88 ps 9
596 04:38:44.620505 TrainedVREFDQ_A0==77
597 04:38:44.620907 TrainedVREFDQ_A1==77
598 04:38:44.625561 VrefDac_Margin_A0==22
599 04:38:44.626006 DeviceVref_Margin_A0==37
600 04:38:44.631175 VrefDac_Margin_A1==24
601 04:38:44.631604 DeviceVref_Margin_A1==37
602 04:38:44.632021
603 04:38:44.636804 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
604 04:38:44.637237
605 04:38:44.664757 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
606 04:38:44.670332 2D training succeed
607 04:38:44.676010 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
608 04:38:44.676448 auto size-- 65535DDR cs0 size: 2048MB
609 04:38:44.681495 DDR cs1 size: 2048MB
610 04:38:44.681922 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
611 04:38:44.687111 cs0 DataBus test pass
612 04:38:44.687536 cs1 DataBus test pass
613 04:38:44.687933 cs0 AddrBus test pass
614 04:38:44.692712 cs1 AddrBus test pass
615 04:38:44.693152
616 04:38:44.693554 100bdlr_step_size ps== 420
617 04:38:44.693959 result report
618 04:38:44.698301 boot times 0Enable ddr reg access
619 04:38:44.705792 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
620 04:38:44.719343 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
621 04:38:45.293069 0.0;M3 CHK:0;cm4_sp_mode 0
622 04:38:45.293704 MVN_1=0x00000000
623 04:38:45.298537 MVN_2=0x00000000
624 04:38:45.304317 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
625 04:38:45.304812 OPS=0x10
626 04:38:45.305248 ring efuse init
627 04:38:45.305644 chipver efuse init
628 04:38:45.309892 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
629 04:38:45.315491 [0.018961 Inits done]
630 04:38:45.315914 secure task start!
631 04:38:45.316364 high task start!
632 04:38:45.320273 low task start!
633 04:38:45.320707 run into bl31
634 04:38:45.326733 NOTICE: BL31: v1.3(release):4fc40b1
635 04:38:45.334570 NOTICE: BL31: Built : 15:58:17, May 22 2019
636 04:38:45.335062 NOTICE: BL31: G12A normal boot!
637 04:38:45.360035 NOTICE: BL31: BL33 decompress pass
638 04:38:45.365649 ERROR: Error initializing runtime service opteed_fast
639 04:38:46.598815
640 04:38:46.599453
641 04:38:46.607117 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
642 04:38:46.607580
643 04:38:46.608033 Model: Libre Computer AML-A311D-CC Alta
644 04:38:46.815711 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
645 04:38:46.838984 DRAM: 2 GiB (effective 3.8 GiB)
646 04:38:46.982836 Core: 408 devices, 31 uclasses, devicetree: separate
647 04:38:46.987900 WDT: Not starting watchdog@f0d0
648 04:38:47.020144 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
649 04:38:47.032511 Loading Environment from FAT... Card did not respond to voltage select! : -110
650 04:38:47.042530 ** Bad device specification mmc 0 **
651 04:38:47.048148 Card did not respond to voltage select! : -110
652 04:38:47.055626 ** Bad device specification mmc 0 **
653 04:38:47.056077 Couldn't find partition mmc 0
654 04:38:47.063915 Card did not respond to voltage select! : -110
655 04:38:47.069417 ** Bad device specification mmc 0 **
656 04:38:47.069895 Couldn't find partition mmc 0
657 04:38:47.074511 Error: could not access storage.
658 04:38:47.418128 Net: eth0: ethernet@ff3f0000
659 04:38:47.418938 starting USB...
660 04:38:47.669863 Bus usb@ff500000: Register 3000140 NbrPorts 3
661 04:38:47.670647 Starting the controller
662 04:38:47.676944 USB XHCI 1.10
663 04:38:49.387079 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
664 04:38:49.387907 bl2_stage_init 0x81
665 04:38:49.392525 hw id: 0x0000 - pwm id 0x01
666 04:38:49.393156 bl2_stage_init 0xc1
667 04:38:49.393700 bl2_stage_init 0x02
668 04:38:49.394227
669 04:38:49.398095 L0:00000000
670 04:38:49.398685 L1:20000703
671 04:38:49.399206 L2:00008067
672 04:38:49.399726 L3:14000000
673 04:38:49.400279 B2:00402000
674 04:38:49.403709 B1:e0f83180
675 04:38:49.404344
676 04:38:49.404876 TE: 58150
677 04:38:49.405405
678 04:38:49.409306 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
679 04:38:49.409916
680 04:38:49.410446 Board ID = 1
681 04:38:49.415129 Set A53 clk to 24M
682 04:38:49.415698 Set A73 clk to 24M
683 04:38:49.416179 Set clk81 to 24M
684 04:38:49.420530 A53 clk: 1200 MHz
685 04:38:49.421012 A73 clk: 1200 MHz
686 04:38:49.421426 CLK81: 166.6M
687 04:38:49.421830 smccc: 00012aab
688 04:38:49.426020 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
689 04:38:49.431613 board id: 1
690 04:38:49.437427 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
691 04:38:49.448079 fw parse done
692 04:38:49.454065 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
693 04:38:49.496656 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
694 04:38:49.507585 PIEI prepare done
695 04:38:49.508114 fastboot data load
696 04:38:49.508538 fastboot data verify
697 04:38:49.513188 verify result: 266
698 04:38:49.518763 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
699 04:38:49.519234 LPDDR4 probe
700 04:38:49.519644 ddr clk to 1584MHz
701 04:38:49.526764 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
702 04:38:49.564072
703 04:38:49.564605 dmc_version 0001
704 04:38:49.570700 Check phy result
705 04:38:49.576600 INFO : End of CA training
706 04:38:49.577084 INFO : End of initialization
707 04:38:49.582146 INFO : Training has run successfully!
708 04:38:49.582603 Check phy result
709 04:38:49.587771 INFO : End of initialization
710 04:38:49.588260 INFO : End of read enable training
711 04:38:49.593342 INFO : End of fine write leveling
712 04:38:49.598936 INFO : End of Write leveling coarse delay
713 04:38:49.599390 INFO : Training has run successfully!
714 04:38:49.599800 Check phy result
715 04:38:49.604541 INFO : End of initialization
716 04:38:49.605000 INFO : End of read dq deskew training
717 04:38:49.610130 INFO : End of MPR read delay center optimization
718 04:38:49.615774 INFO : End of write delay center optimization
719 04:38:49.621404 INFO : End of read delay center optimization
720 04:38:49.621860 INFO : End of max read latency training
721 04:38:49.626954 INFO : Training has run successfully!
722 04:38:49.627408 1D training succeed
723 04:38:49.636156 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
724 04:38:49.683699 Check phy result
725 04:38:49.684197 INFO : End of initialization
726 04:38:49.705436 INFO : End of 2D read delay Voltage center optimization
727 04:38:49.725730 INFO : End of 2D read delay Voltage center optimization
728 04:38:49.777791 INFO : End of 2D write delay Voltage center optimization
729 04:38:49.827166 INFO : End of 2D write delay Voltage center optimization
730 04:38:49.832717 INFO : Training has run successfully!
731 04:38:49.833177
732 04:38:49.833587 channel==0
733 04:38:49.838245 RxClkDly_Margin_A0==88 ps 9
734 04:38:49.838700 TxDqDly_Margin_A0==98 ps 10
735 04:38:49.844049 RxClkDly_Margin_A1==88 ps 9
736 04:38:49.844503 TxDqDly_Margin_A1==98 ps 10
737 04:38:49.844910 TrainedVREFDQ_A0==74
738 04:38:49.849451 TrainedVREFDQ_A1==74
739 04:38:49.849928 VrefDac_Margin_A0==25
740 04:38:49.850334 DeviceVref_Margin_A0==40
741 04:38:49.855108 VrefDac_Margin_A1==25
742 04:38:49.855559 DeviceVref_Margin_A1==40
743 04:38:49.855962
744 04:38:49.856398
745 04:38:49.860760 channel==1
746 04:38:49.861209 RxClkDly_Margin_A0==98 ps 10
747 04:38:49.861612 TxDqDly_Margin_A0==88 ps 9
748 04:38:49.866262 RxClkDly_Margin_A1==88 ps 9
749 04:38:49.866715 TxDqDly_Margin_A1==88 ps 9
750 04:38:49.872074 TrainedVREFDQ_A0==77
751 04:38:49.872543 TrainedVREFDQ_A1==77
752 04:38:49.872948 VrefDac_Margin_A0==22
753 04:38:49.877536 DeviceVref_Margin_A0==37
754 04:38:49.877986 VrefDac_Margin_A1==24
755 04:38:49.883127 DeviceVref_Margin_A1==37
756 04:38:49.883575
757 04:38:49.884007 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
758 04:38:49.884412
759 04:38:49.916598 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
760 04:38:49.917089 2D training succeed
761 04:38:49.922278 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
762 04:38:49.927872 auto size-- 65535DDR cs0 size: 2048MB
763 04:38:49.928353 DDR cs1 size: 2048MB
764 04:38:49.933380 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
765 04:38:49.933831 cs0 DataBus test pass
766 04:38:49.939029 cs1 DataBus test pass
767 04:38:49.939482 cs0 AddrBus test pass
768 04:38:49.939883 cs1 AddrBus test pass
769 04:38:49.940325
770 04:38:49.944582 100bdlr_step_size ps== 420
771 04:38:49.945043 result report
772 04:38:49.950187 boot times 0Enable ddr reg access
773 04:38:49.955452 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
774 04:38:49.968935 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
775 04:38:50.542677 0.0;M3 CHK:0;cm4_sp_mode 0
776 04:38:50.543295 MVN_1=0x00000000
777 04:38:50.548232 MVN_2=0x00000000
778 04:38:50.554021 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
779 04:38:50.554517 OPS=0x10
780 04:38:50.554913 ring efuse init
781 04:38:50.555293 chipver efuse init
782 04:38:50.559488 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
783 04:38:50.565134 [0.018960 Inits done]
784 04:38:50.565611 secure task start!
785 04:38:50.566000 high task start!
786 04:38:50.569708 low task start!
787 04:38:50.570158 run into bl31
788 04:38:50.576331 NOTICE: BL31: v1.3(release):4fc40b1
789 04:38:50.584151 NOTICE: BL31: Built : 15:58:17, May 22 2019
790 04:38:50.584603 NOTICE: BL31: G12A normal boot!
791 04:38:50.609469 NOTICE: BL31: BL33 decompress pass
792 04:38:50.615195 ERROR: Error initializing runtime service opteed_fast
793 04:38:51.848221
794 04:38:51.848848
795 04:38:51.856453 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
796 04:38:51.856905
797 04:38:51.857324 Model: Libre Computer AML-A311D-CC Alta
798 04:38:52.064868 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
799 04:38:52.088247 DRAM: 2 GiB (effective 3.8 GiB)
800 04:38:52.231211 Core: 408 devices, 31 uclasses, devicetree: separate
801 04:38:52.237181 WDT: Not starting watchdog@f0d0
802 04:38:52.269363 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
803 04:38:52.281844 Loading Environment from FAT... Card did not respond to voltage select! : -110
804 04:38:52.286804 ** Bad device specification mmc 0 **
805 04:38:52.297160 Card did not respond to voltage select! : -110
806 04:38:52.304793 ** Bad device specification mmc 0 **
807 04:38:52.305227 Couldn't find partition mmc 0
808 04:38:52.313151 Card did not respond to voltage select! : -110
809 04:38:52.318655 ** Bad device specification mmc 0 **
810 04:38:52.319086 Couldn't find partition mmc 0
811 04:38:52.323717 Error: could not access storage.
812 04:38:52.666286 Net: eth0: ethernet@ff3f0000
813 04:38:52.666887 starting USB...
814 04:38:52.917960 Bus usb@ff500000: Register 3000140 NbrPorts 3
815 04:38:52.918472 Starting the controller
816 04:38:52.924944 USB XHCI 1.10
817 04:38:55.088523 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
818 04:38:55.089114 bl2_stage_init 0x81
819 04:38:55.093911 hw id: 0x0000 - pwm id 0x01
820 04:38:55.094348 bl2_stage_init 0xc1
821 04:38:55.094755 bl2_stage_init 0x02
822 04:38:55.095154
823 04:38:55.099670 L0:00000000
824 04:38:55.100140 L1:20000703
825 04:38:55.100543 L2:00008067
826 04:38:55.100937 L3:14000000
827 04:38:55.101329 B2:00402000
828 04:38:55.105159 B1:e0f83180
829 04:38:55.105590
830 04:38:55.105996 TE: 58150
831 04:38:55.106396
832 04:38:55.111054 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
833 04:38:55.111488
834 04:38:55.111896 Board ID = 1
835 04:38:55.116335 Set A53 clk to 24M
836 04:38:55.116766 Set A73 clk to 24M
837 04:38:55.117167 Set clk81 to 24M
838 04:38:55.121944 A53 clk: 1200 MHz
839 04:38:55.122365 A73 clk: 1200 MHz
840 04:38:55.122761 CLK81: 166.6M
841 04:38:55.123153 smccc: 00012aac
842 04:38:55.127751 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
843 04:38:55.133065 board id: 1
844 04:38:55.139057 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
845 04:38:55.149529 fw parse done
846 04:38:55.155490 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
847 04:38:55.198122 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
848 04:38:55.208983 PIEI prepare done
849 04:38:55.209408 fastboot data load
850 04:38:55.209810 fastboot data verify
851 04:38:55.214584 verify result: 266
852 04:38:55.220207 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
853 04:38:55.220630 LPDDR4 probe
854 04:38:55.221025 ddr clk to 1584MHz
855 04:38:55.228188 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
856 04:38:55.265440
857 04:38:55.265877 dmc_version 0001
858 04:38:55.272188 Check phy result
859 04:38:55.277994 INFO : End of CA training
860 04:38:55.278422 INFO : End of initialization
861 04:38:55.283603 INFO : Training has run successfully!
862 04:38:55.284071 Check phy result
863 04:38:55.289243 INFO : End of initialization
864 04:38:55.289680 INFO : End of read enable training
865 04:38:55.294853 INFO : End of fine write leveling
866 04:38:55.300467 INFO : End of Write leveling coarse delay
867 04:38:55.300893 INFO : Training has run successfully!
868 04:38:55.301290 Check phy result
869 04:38:55.306007 INFO : End of initialization
870 04:38:55.306432 INFO : End of read dq deskew training
871 04:38:55.311586 INFO : End of MPR read delay center optimization
872 04:38:55.317225 INFO : End of write delay center optimization
873 04:38:55.322852 INFO : End of read delay center optimization
874 04:38:55.323276 INFO : End of max read latency training
875 04:38:55.328480 INFO : Training has run successfully!
876 04:38:55.328912 1D training succeed
877 04:38:55.337694 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
878 04:38:55.385120 Check phy result
879 04:38:55.385570 INFO : End of initialization
880 04:38:55.406001 INFO : End of 2D read delay Voltage center optimization
881 04:38:55.427179 INFO : End of 2D read delay Voltage center optimization
882 04:38:55.479098 INFO : End of 2D write delay Voltage center optimization
883 04:38:55.528483 INFO : End of 2D write delay Voltage center optimization
884 04:38:55.534025 INFO : Training has run successfully!
885 04:38:55.534334
886 04:38:55.534560 channel==0
887 04:38:55.539603 RxClkDly_Margin_A0==88 ps 9
888 04:38:55.540059 TxDqDly_Margin_A0==98 ps 10
889 04:38:55.545197 RxClkDly_Margin_A1==88 ps 9
890 04:38:55.548186 TxDqDly_Margin_A1==98 ps 10
891 04:38:55.548705 TrainedVREFDQ_A0==74
892 04:38:55.550920 TrainedVREFDQ_A1==75
893 04:38:55.551396 VrefDac_Margin_A0==25
894 04:38:55.551795 DeviceVref_Margin_A0==40
895 04:38:55.556542 VrefDac_Margin_A1==25
896 04:38:55.557018 DeviceVref_Margin_A1==39
897 04:38:55.557410
898 04:38:55.557796
899 04:38:55.562131 channel==1
900 04:38:55.562611 RxClkDly_Margin_A0==98 ps 10
901 04:38:55.563002 TxDqDly_Margin_A0==98 ps 10
902 04:38:55.567722 RxClkDly_Margin_A1==98 ps 10
903 04:38:55.568242 TxDqDly_Margin_A1==98 ps 10
904 04:38:55.573320 TrainedVREFDQ_A0==77
905 04:38:55.573801 TrainedVREFDQ_A1==78
906 04:38:55.574193 VrefDac_Margin_A0==22
907 04:38:55.578941 DeviceVref_Margin_A0==37
908 04:38:55.579443 VrefDac_Margin_A1==22
909 04:38:55.584577 DeviceVref_Margin_A1==36
910 04:38:55.585076
911 04:38:55.585469 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
912 04:38:55.590105
913 04:38:55.618071 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
914 04:38:55.618591 2D training succeed
915 04:38:55.623697 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
916 04:38:55.629321 auto size-- 65535DDR cs0 size: 2048MB
917 04:38:55.629803 DDR cs1 size: 2048MB
918 04:38:55.634907 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
919 04:38:55.635387 cs0 DataBus test pass
920 04:38:55.640524 cs1 DataBus test pass
921 04:38:55.641001 cs0 AddrBus test pass
922 04:38:55.641388 cs1 AddrBus test pass
923 04:38:55.641767
924 04:38:55.646104 100bdlr_step_size ps== 420
925 04:38:55.646588 result report
926 04:38:55.651734 boot times 0Enable ddr reg access
927 04:38:55.657247 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
928 04:38:55.670714 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
929 04:38:56.244429 0.0;M3 CHK:0;cm4_sp_mode 0
930 04:38:56.245000 MVN_1=0x00000000
931 04:38:56.249960 MVN_2=0x00000000
932 04:38:56.255760 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
933 04:38:56.256304 OPS=0x10
934 04:38:56.256729 ring efuse init
935 04:38:56.257136 chipver efuse init
936 04:38:56.261282 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
937 04:38:56.266907 [0.018961 Inits done]
938 04:38:56.267404 secure task start!
939 04:38:56.267822 high task start!
940 04:38:56.271490 low task start!
941 04:38:56.272017 run into bl31
942 04:38:56.278148 NOTICE: BL31: v1.3(release):4fc40b1
943 04:38:56.285959 NOTICE: BL31: Built : 15:58:17, May 22 2019
944 04:38:56.286459 NOTICE: BL31: G12A normal boot!
945 04:38:56.311329 NOTICE: BL31: BL33 decompress pass
946 04:38:56.317045 ERROR: Error initializing runtime service opteed_fast
947 04:38:57.549989
948 04:38:57.550604
949 04:38:57.558296 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
950 04:38:57.558816
951 04:38:57.559237 Model: Libre Computer AML-A311D-CC Alta
952 04:38:57.766681 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
953 04:38:57.790092 DRAM: 2 GiB (effective 3.8 GiB)
954 04:38:57.933051 Core: 408 devices, 31 uclasses, devicetree: separate
955 04:38:57.939072 WDT: Not starting watchdog@f0d0
956 04:38:57.971171 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
957 04:38:57.983618 Loading Environment from FAT... Card did not respond to voltage select! : -110
958 04:38:57.988655 ** Bad device specification mmc 0 **
959 04:38:57.998994 Card did not respond to voltage select! : -110
960 04:38:58.006635 ** Bad device specification mmc 0 **
961 04:38:58.007130 Couldn't find partition mmc 0
962 04:38:58.015010 Card did not respond to voltage select! : -110
963 04:38:58.020518 ** Bad device specification mmc 0 **
964 04:38:58.021046 Couldn't find partition mmc 0
965 04:38:58.025561 Error: could not access storage.
966 04:38:58.369101 Net: eth0: ethernet@ff3f0000
967 04:38:58.369636 starting USB...
968 04:38:58.620965 Bus usb@ff500000: Register 3000140 NbrPorts 3
969 04:38:58.621578 Starting the controller
970 04:38:58.627833 USB XHCI 1.10
971 04:39:00.488576 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
972 04:39:00.489199 bl2_stage_init 0x01
973 04:39:00.489623 bl2_stage_init 0x81
974 04:39:00.493947 hw id: 0x0000 - pwm id 0x01
975 04:39:00.494431 bl2_stage_init 0xc1
976 04:39:00.494846 bl2_stage_init 0x02
977 04:39:00.495248
978 04:39:00.499732 L0:00000000
979 04:39:00.500250 L1:20000703
980 04:39:00.500658 L2:00008067
981 04:39:00.501056 L3:14000000
982 04:39:00.505290 B2:00402000
983 04:39:00.505777 B1:e0f83180
984 04:39:00.506183
985 04:39:00.506583 TE: 58167
986 04:39:00.506982
987 04:39:00.510848 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
988 04:39:00.511333
989 04:39:00.511743 Board ID = 1
990 04:39:00.520214 Set A53 clk to 24M
991 04:39:00.520712 Set A73 clk to 24M
992 04:39:00.521124 Set clk81 to 24M
993 04:39:00.522088 A53 clk: 1200 MHz
994 04:39:00.522542 A73 clk: 1200 MHz
995 04:39:00.522948 CLK81: 166.6M
996 04:39:00.523344 smccc: 00012abe
997 04:39:00.532894 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
998 04:39:00.533604 board id: 1
999 04:39:00.539105 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1000 04:39:00.549745 fw parse done
1001 04:39:00.555812 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1002 04:39:00.598217 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 04:39:00.609087 PIEI prepare done
1004 04:39:00.609714 fastboot data load
1005 04:39:00.610243 fastboot data verify
1006 04:39:00.614810 verify result: 266
1007 04:39:00.620423 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1008 04:39:00.621041 LPDDR4 probe
1009 04:39:00.621554 ddr clk to 1584MHz
1010 04:39:00.628408 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1011 04:39:00.665592
1012 04:39:00.666209 dmc_version 0001
1013 04:39:00.672326 Check phy result
1014 04:39:00.678143 INFO : End of CA training
1015 04:39:00.678750 INFO : End of initialization
1016 04:39:00.683866 INFO : Training has run successfully!
1017 04:39:00.684544 Check phy result
1018 04:39:00.689468 INFO : End of initialization
1019 04:39:00.690104 INFO : End of read enable training
1020 04:39:00.694964 INFO : End of fine write leveling
1021 04:39:00.700596 INFO : End of Write leveling coarse delay
1022 04:39:00.701214 INFO : Training has run successfully!
1023 04:39:00.701754 Check phy result
1024 04:39:00.706173 INFO : End of initialization
1025 04:39:00.706799 INFO : End of read dq deskew training
1026 04:39:00.711770 INFO : End of MPR read delay center optimization
1027 04:39:00.717473 INFO : End of write delay center optimization
1028 04:39:00.722951 INFO : End of read delay center optimization
1029 04:39:00.723565 INFO : End of max read latency training
1030 04:39:00.728622 INFO : Training has run successfully!
1031 04:39:00.729226 1D training succeed
1032 04:39:00.737719 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1033 04:39:00.785364 Check phy result
1034 04:39:00.786015 INFO : End of initialization
1035 04:39:00.806974 INFO : End of 2D read delay Voltage center optimization
1036 04:39:00.827082 INFO : End of 2D read delay Voltage center optimization
1037 04:39:00.878994 INFO : End of 2D write delay Voltage center optimization
1038 04:39:00.928329 INFO : End of 2D write delay Voltage center optimization
1039 04:39:00.933892 INFO : Training has run successfully!
1040 04:39:00.934507
1041 04:39:00.935039 channel==0
1042 04:39:00.939615 RxClkDly_Margin_A0==88 ps 9
1043 04:39:00.940270 TxDqDly_Margin_A0==98 ps 10
1044 04:39:00.942776 RxClkDly_Margin_A1==88 ps 9
1045 04:39:00.943374 TxDqDly_Margin_A1==98 ps 10
1046 04:39:00.948353 TrainedVREFDQ_A0==74
1047 04:39:00.948961 TrainedVREFDQ_A1==74
1048 04:39:00.953889 VrefDac_Margin_A0==25
1049 04:39:00.954503 DeviceVref_Margin_A0==40
1050 04:39:00.955030 VrefDac_Margin_A1==25
1051 04:39:00.959635 DeviceVref_Margin_A1==40
1052 04:39:00.960282
1053 04:39:00.960830
1054 04:39:00.961362 channel==1
1055 04:39:00.961874 RxClkDly_Margin_A0==98 ps 10
1056 04:39:00.965099 TxDqDly_Margin_A0==88 ps 9
1057 04:39:00.965714 RxClkDly_Margin_A1==98 ps 10
1058 04:39:00.970765 TxDqDly_Margin_A1==88 ps 9
1059 04:39:00.971371 TrainedVREFDQ_A0==76
1060 04:39:00.971908 TrainedVREFDQ_A1==77
1061 04:39:00.976332 VrefDac_Margin_A0==22
1062 04:39:00.976827 DeviceVref_Margin_A0==38
1063 04:39:00.981912 VrefDac_Margin_A1==22
1064 04:39:00.982519 DeviceVref_Margin_A1==37
1065 04:39:00.983052
1066 04:39:00.987630 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1067 04:39:00.988279
1068 04:39:01.015509 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 0000005f
1069 04:39:01.021017 2D training succeed
1070 04:39:01.026608 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1071 04:39:01.027253 auto size-- 65535DDR cs0 size: 2048MB
1072 04:39:01.032262 DDR cs1 size: 2048MB
1073 04:39:01.032889 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1074 04:39:01.037794 cs0 DataBus test pass
1075 04:39:01.038401 cs1 DataBus test pass
1076 04:39:01.038943 cs0 AddrBus test pass
1077 04:39:01.043493 cs1 AddrBus test pass
1078 04:39:01.044162
1079 04:39:01.044717 100bdlr_step_size ps== 420
1080 04:39:01.045254 result report
1081 04:39:01.048988 boot times 0Enable ddr reg access
1082 04:39:01.056695 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1083 04:39:01.070144 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1084 04:39:01.642214 0.0;M3 CHK:0;cm4_sp_mode 0
1085 04:39:01.643019 MVN_1=0x00000000
1086 04:39:01.647637 MVN_2=0x00000000
1087 04:39:01.653491 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1088 04:39:01.654103 OPS=0x10
1089 04:39:01.654649 ring efuse init
1090 04:39:01.655177 chipver efuse init
1091 04:39:01.658964 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1092 04:39:01.664559 [0.018961 Inits done]
1093 04:39:01.665164 secure task start!
1094 04:39:01.665704 high task start!
1095 04:39:01.669137 low task start!
1096 04:39:01.669753 run into bl31
1097 04:39:01.675765 NOTICE: BL31: v1.3(release):4fc40b1
1098 04:39:01.683588 NOTICE: BL31: Built : 15:58:17, May 22 2019
1099 04:39:01.684249 NOTICE: BL31: G12A normal boot!
1100 04:39:01.708932 NOTICE: BL31: BL33 decompress pass
1101 04:39:01.714617 ERROR: Error initializing runtime service opteed_fast
1102 04:39:02.947529
1103 04:39:02.948379
1104 04:39:02.955895 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1105 04:39:02.956542
1106 04:39:02.957089 Model: Libre Computer AML-A311D-CC Alta
1107 04:39:03.164302 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1108 04:39:03.187762 DRAM: 2 GiB (effective 3.8 GiB)
1109 04:39:03.330706 Core: 408 devices, 31 uclasses, devicetree: separate
1110 04:39:03.336513 WDT: Not starting watchdog@f0d0
1111 04:39:03.368768 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1112 04:39:03.381231 Loading Environment from FAT... Card did not respond to voltage select! : -110
1113 04:39:03.386229 ** Bad device specification mmc 0 **
1114 04:39:03.396548 Card did not respond to voltage select! : -110
1115 04:39:03.404287 ** Bad device specification mmc 0 **
1116 04:39:03.404941 Couldn't find partition mmc 0
1117 04:39:03.412591 Card did not respond to voltage select! : -110
1118 04:39:03.418164 ** Bad device specification mmc 0 **
1119 04:39:03.418880 Couldn't find partition mmc 0
1120 04:39:03.423147 Error: could not access storage.
1121 04:39:03.765560 Net: eth0: ethernet@ff3f0000
1122 04:39:03.766280 starting USB...
1123 04:39:04.017348 Bus usb@ff500000: Register 3000140 NbrPorts 3
1124 04:39:04.017993 Starting the controller
1125 04:39:04.024430 USB XHCI 1.10
1126 04:39:05.580650 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1127 04:39:05.588903 scanning usb for storage devices... 0 Storage Device(s) found
1129 04:39:05.640906 Hit any key to stop autoboot: 1
1130 04:39:05.641825 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1131 04:39:05.642545 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1132 04:39:05.643014 Setting prompt string to ['=>']
1133 04:39:05.643490 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1134 04:39:05.656322 0
1135 04:39:05.657406 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1136 04:39:05.658029 Sending with 10 millisecond of delay
1138 04:39:06.793232 => setenv autoload no
1139 04:39:06.804248 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1140 04:39:06.810468 setenv autoload no
1141 04:39:06.811379 Sending with 10 millisecond of delay
1143 04:39:08.609674 => setenv initrd_high 0xffffffff
1144 04:39:08.620459 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1145 04:39:08.621257 setenv initrd_high 0xffffffff
1146 04:39:08.621947 Sending with 10 millisecond of delay
1148 04:39:10.237846 => setenv fdt_high 0xffffffff
1149 04:39:10.248616 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1150 04:39:10.249398 setenv fdt_high 0xffffffff
1151 04:39:10.250102 Sending with 10 millisecond of delay
1153 04:39:10.541826 => dhcp
1154 04:39:10.552511 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1155 04:39:10.553309 dhcp
1156 04:39:10.553745 Speed: 1000, full duplex
1157 04:39:10.554152 BOOTP broadcast 1
1158 04:39:10.563608 DHCP client bound to address 192.168.6.27 (11 ms)
1159 04:39:10.564359 Sending with 10 millisecond of delay
1161 04:39:12.240469 => setenv serverip 192.168.6.2
1162 04:39:12.251247 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1163 04:39:12.252307 setenv serverip 192.168.6.2
1164 04:39:12.253110 Sending with 10 millisecond of delay
1166 04:39:15.976677 => tftpboot 0x01080000 950934/tftp-deploy-y6z2r49c/kernel/uImage
1167 04:39:15.987410 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1168 04:39:15.987905 tftpboot 0x01080000 950934/tftp-deploy-y6z2r49c/kernel/uImage
1169 04:39:15.988190 Speed: 1000, full duplex
1170 04:39:15.988419 Using ethernet@ff3f0000 device
1171 04:39:15.989883 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1172 04:39:15.995527 Filename '950934/tftp-deploy-y6z2r49c/kernel/uImage'.
1173 04:39:15.999384 Load address: 0x1080000
1174 04:39:19.028593 Loading: *################################################## 43.6 MiB
1175 04:39:19.029418 14.4 MiB/s
1176 04:39:19.030000 done
1177 04:39:19.033161 Bytes transferred = 45713984 (2b98a40 hex)
1178 04:39:19.034189 Sending with 10 millisecond of delay
1180 04:39:23.723482 => tftpboot 0x08000000 950934/tftp-deploy-y6z2r49c/ramdisk/ramdisk.cpio.gz.uboot
1181 04:39:23.734527 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1182 04:39:23.735574 tftpboot 0x08000000 950934/tftp-deploy-y6z2r49c/ramdisk/ramdisk.cpio.gz.uboot
1183 04:39:23.736183 Speed: 1000, full duplex
1184 04:39:23.736726 Using ethernet@ff3f0000 device
1185 04:39:23.737404 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1186 04:39:23.749165 Filename '950934/tftp-deploy-y6z2r49c/ramdisk/ramdisk.cpio.gz.uboot'.
1187 04:39:23.749677 Load address: 0x8000000
1188 04:39:30.912385 Loading: *###########T ####################################### 22.3 MiB
1189 04:39:30.913187 3.1 MiB/s
1190 04:39:30.913750 done
1191 04:39:30.916870 Bytes transferred = 23432462 (1658d0e hex)
1192 04:39:30.917801 Sending with 10 millisecond of delay
1194 04:39:36.088535 => tftpboot 0x01070000 950934/tftp-deploy-y6z2r49c/dtb/meson-g12b-a311d-libretech-cc.dtb
1195 04:39:36.099303 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:53)
1196 04:39:36.100155 tftpboot 0x01070000 950934/tftp-deploy-y6z2r49c/dtb/meson-g12b-a311d-libretech-cc.dtb
1197 04:39:36.100603 Speed: 1000, full duplex
1198 04:39:36.101015 Using ethernet@ff3f0000 device
1199 04:39:36.104522 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1200 04:39:36.116964 Filename '950934/tftp-deploy-y6z2r49c/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1201 04:39:36.117443 Load address: 0x1070000
1202 04:39:36.133303 Loading: *################################################## 53.4 KiB
1203 04:39:36.133770 2.9 MiB/s
1204 04:39:36.134177 done
1205 04:39:36.139636 Bytes transferred = 54703 (d5af hex)
1206 04:39:36.140386 Sending with 10 millisecond of delay
1208 04:39:49.438375 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/950934/extract-nfsrootfs-k6hj5bfk,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1209 04:39:49.449184 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:39)
1210 04:39:49.450042 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/950934/extract-nfsrootfs-k6hj5bfk,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1211 04:39:49.450743 Sending with 10 millisecond of delay
1213 04:39:51.789381 => bootm 0x01080000 0x08000000 0x01070000
1214 04:39:51.800153 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1215 04:39:51.800594 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:37)
1216 04:39:51.801415 bootm 0x01080000 0x08000000 0x01070000
1217 04:39:51.801795 ## Booting kernel from Legacy Image at 01080000 ...
1218 04:39:51.805065 Image Name:
1219 04:39:51.810579 Image Type: AArch64 Linux Kernel Image (uncompressed)
1220 04:39:51.810955 Data Size: 45713920 Bytes = 43.6 MiB
1221 04:39:51.812804 Load Address: 01080000
1222 04:39:51.819241 Entry Point: 01080000
1223 04:39:52.011454 Verifying Checksum ... OK
1224 04:39:52.011948 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1225 04:39:52.016927 Image Name:
1226 04:39:52.022376 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1227 04:39:52.023155 Data Size: 23432398 Bytes = 22.3 MiB
1228 04:39:52.024783 Load Address: 00000000
1229 04:39:52.031969 Entry Point: 00000000
1230 04:39:52.130212 Verifying Checksum ... OK
1231 04:39:52.131062 ## Flattened Device Tree blob at 01070000
1232 04:39:52.135530 Booting using the fdt blob at 0x1070000
1233 04:39:52.136313 Working FDT set to 1070000
1234 04:39:52.139885 Loading Kernel Image
1235 04:39:52.290699 Loading Ramdisk to 7e9a7000, end 7ffffcce ... OK
1236 04:39:52.298899 Loading Device Tree to 000000007e996000, end 000000007e9a65ae ... OK
1237 04:39:52.299296 Working FDT set to 7e996000
1238 04:39:52.299612
1239 04:39:52.300340 end: 2.4.3 bootloader-commands (duration 00:00:47) [common]
1240 04:39:52.300707 start: 2.4.4 auto-login-action (timeout 00:03:36) [common]
1241 04:39:52.300999 Setting prompt string to ['Linux version [0-9]']
1242 04:39:52.301281 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1243 04:39:52.301556 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1244 04:39:52.302249 Starting kernel ...
1245 04:39:52.302522
1246 04:39:52.339227 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1247 04:39:52.339828 start: 2.4.4.1 login-action (timeout 00:03:36) [common]
1248 04:39:52.340156 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1249 04:39:52.340435 Setting prompt string to []
1250 04:39:52.340725 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1251 04:39:52.340993 Using line separator: #'\n'#
1252 04:39:52.341234 No login prompt set.
1253 04:39:52.341491 Parsing kernel messages
1254 04:39:52.341731 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1255 04:39:52.342169 [login-action] Waiting for messages, (timeout 00:03:36)
1256 04:39:52.342440 Waiting using forced prompt support (timeout 00:01:48)
1257 04:39:52.359280 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j366032-arm64-gcc-12-defconfig-s5mz8) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Nov 7 00:44:34 UTC 2024
1258 04:39:52.359568 [ 0.000000] KASLR disabled due to lack of seed
1259 04:39:52.364853 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1260 04:39:52.370290 [ 0.000000] efi: UEFI not found.
1261 04:39:52.375861 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1262 04:39:52.386862 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1263 04:39:52.392518 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1264 04:39:52.403722 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1265 04:39:52.414793 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1266 04:39:52.425636 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1267 04:39:52.431241 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1268 04:39:52.436443 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1269 04:39:52.441953 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1270 04:39:52.447565 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1271 04:39:52.453187 [ 0.000000] Zone ranges:
1272 04:39:52.458736 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1273 04:39:52.459359 [ 0.000000] DMA32 empty
1274 04:39:52.464271 [ 0.000000] Normal empty
1275 04:39:52.469731 [ 0.000000] Movable zone start for each node
1276 04:39:52.470326 [ 0.000000] Early memory node ranges
1277 04:39:52.475258 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1278 04:39:52.480772 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1279 04:39:52.491748 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1280 04:39:52.496875 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1281 04:39:52.521104 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1282 04:39:52.526749 [ 0.000000] psci: probing for conduit method from DT.
1283 04:39:52.527417 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1284 04:39:52.532362 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1285 04:39:52.537778 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1286 04:39:52.543268 [ 0.000000] psci: SMC Calling Convention v1.1
1287 04:39:52.548809 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1288 04:39:52.554290 [ 0.000000] Detected VIPT I-cache on CPU0
1289 04:39:52.559844 [ 0.000000] CPU features: detected: ARM erratum 845719
1290 04:39:52.565390 [ 0.000000] alternatives: applying boot alternatives
1291 04:39:52.581851 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/950934/extract-nfsrootfs-k6hj5bfk,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1292 04:39:52.592898 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1293 04:39:52.598445 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1294 04:39:52.604007 <6>[ 0.000000] Fallback order for Node 0: 0
1295 04:39:52.609578 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1296 04:39:52.615009 <6>[ 0.000000] Policy zone: DMA
1297 04:39:52.620592 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1298 04:39:52.626048 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1299 04:39:52.631627 <6>[ 0.000000] software IO TLB: area num 8.
1300 04:39:52.640602 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1301 04:39:52.687082 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1302 04:39:52.692672 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1303 04:39:52.696289 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1304 04:39:52.701729 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1305 04:39:52.707243 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1306 04:39:52.712779 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1307 04:39:52.723740 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1308 04:39:52.729351 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1309 04:39:52.734919 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1310 04:39:52.745843 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1311 04:39:52.751450 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1312 04:39:52.756916 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1313 04:39:52.762460 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1314 04:39:52.768791 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1315 04:39:52.781394 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1316 04:39:52.792552 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1317 04:39:52.798003 <6>[ 0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1318 04:39:52.803614 <6>[ 0.008796] Console: colour dummy device 80x25
1319 04:39:52.814572 <6>[ 0.012938] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1320 04:39:52.820136 <6>[ 0.023294] pid_max: default: 32768 minimum: 301
1321 04:39:52.825623 <6>[ 0.028191] LSM: initializing lsm=capability
1322 04:39:52.831168 <6>[ 0.032726] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1323 04:39:52.836697 <6>[ 0.040210] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1324 04:39:52.842169 <6>[ 0.052297] rcu: Hierarchical SRCU implementation.
1325 04:39:52.847689 <6>[ 0.053215] rcu: Max phase no-delay instances is 1000.
1326 04:39:52.858700 <6>[ 0.058881] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1327 04:39:52.867162 <6>[ 0.071585] EFI services will not be available.
1328 04:39:52.867817 <6>[ 0.075229] smp: Bringing up secondary CPUs ...
1329 04:39:52.883494 <6>[ 0.077134] Detected VIPT I-cache on CPU1
1330 04:39:52.888942 <6>[ 0.077251] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1331 04:39:52.894488 <6>[ 0.078584] CPU features: detected: Spectre-v2
1332 04:39:52.900007 <6>[ 0.078600] CPU features: detected: Spectre-v4
1333 04:39:52.905627 <6>[ 0.078605] CPU features: detected: Spectre-BHB
1334 04:39:52.911003 <6>[ 0.078611] CPU features: detected: ARM erratum 858921
1335 04:39:52.916608 <6>[ 0.078619] Detected VIPT I-cache on CPU2
1336 04:39:52.922062 <6>[ 0.078692] arch_timer: Enabling local workaround for ARM erratum 858921
1337 04:39:52.927622 <6>[ 0.078709] arch_timer: CPU2: Trapping CNTVCT access
1338 04:39:52.933171 <6>[ 0.078719] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1339 04:39:52.938628 <6>[ 0.083577] Detected VIPT I-cache on CPU3
1340 04:39:52.944189 <6>[ 0.083621] arch_timer: Enabling local workaround for ARM erratum 858921
1341 04:39:52.949663 <6>[ 0.083631] arch_timer: CPU3: Trapping CNTVCT access
1342 04:39:52.955182 <6>[ 0.083639] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1343 04:39:52.960696 <6>[ 0.087615] Detected VIPT I-cache on CPU4
1344 04:39:52.966250 <6>[ 0.087661] arch_timer: Enabling local workaround for ARM erratum 858921
1345 04:39:52.971767 <6>[ 0.087671] arch_timer: CPU4: Trapping CNTVCT access
1346 04:39:52.982744 <6>[ 0.087678] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1347 04:39:52.983396 <6>[ 0.095640] Detected VIPT I-cache on CPU5
1348 04:39:52.993745 <6>[ 0.095687] arch_timer: Enabling local workaround for ARM erratum 858921
1349 04:39:52.994412 <6>[ 0.095697] arch_timer: CPU5: Trapping CNTVCT access
1350 04:39:53.004836 <6>[ 0.095704] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1351 04:39:53.005500 <6>[ 0.095817] smp: Brought up 1 node, 6 CPUs
1352 04:39:53.010377 <6>[ 0.217052] SMP: Total of 6 processors activated.
1353 04:39:53.015899 <6>[ 0.221955] CPU: All CPU(s) started at EL2
1354 04:39:53.021413 <6>[ 0.226298] CPU features: detected: 32-bit EL0 Support
1355 04:39:53.026954 <6>[ 0.231613] CPU features: detected: 32-bit EL1 Support
1356 04:39:53.032561 <6>[ 0.236961] CPU features: detected: CRC32 instructions
1357 04:39:53.037989 <6>[ 0.242362] alternatives: applying system-wide alternatives
1358 04:39:53.055879 <6>[ 0.249546] Memory: 3557436K/4012396K available (17280K kernel code, 4898K rwdata, 11876K rodata, 10432K init, 742K bss, 187796K reserved, 262144K cma-reserved)
1359 04:39:53.056593 <6>[ 0.263898] devtmpfs: initialized
1360 04:39:53.066902 <6>[ 0.273082] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1361 04:39:53.072515 <6>[ 0.277438] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1362 04:39:53.078040 <6>[ 0.288234] 21392 pages in range for non-PLT usage
1363 04:39:53.083613 <6>[ 0.288243] 512912 pages in range for PLT usage
1364 04:39:53.089019 <6>[ 0.289793] pinctrl core: initialized pinctrl subsystem
1365 04:39:53.094637 <6>[ 0.301865] DMI not present or invalid.
1366 04:39:53.100138 <6>[ 0.306156] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1367 04:39:53.105643 <6>[ 0.310899] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1368 04:39:53.116625 <6>[ 0.317674] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1369 04:39:53.122172 <6>[ 0.325780] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1370 04:39:53.127671 <6>[ 0.333269] audit: initializing netlink subsys (disabled)
1371 04:39:53.138742 <5>[ 0.339012] audit: type=2000 audit(0.260:1): state=initialized audit_enabled=0 res=1
1372 04:39:53.144335 <6>[ 0.340513] thermal_sys: Registered thermal governor 'step_wise'
1373 04:39:53.149785 <6>[ 0.346773] thermal_sys: Registered thermal governor 'power_allocator'
1374 04:39:53.155300 <6>[ 0.353035] cpuidle: using governor menu
1375 04:39:53.160817 <6>[ 0.364018] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1376 04:39:53.166339 <6>[ 0.370949] ASID allocator initialised with 65536 entries
1377 04:39:53.174672 <6>[ 0.378476] Serial: AMBA PL011 UART driver
1378 04:39:53.182385 <6>[ 0.389044] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1379 04:39:53.197666 <6>[ 0.404563] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1380 04:39:53.206685 <6>[ 0.407229] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1381 04:39:53.212285 <6>[ 0.420401] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1382 04:39:53.223212 <6>[ 0.423607] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1383 04:39:53.228805 <6>[ 0.432043] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1384 04:39:53.239803 <6>[ 0.439657] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1385 04:39:53.245403 <6>[ 0.453245] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1386 04:39:53.250922 <6>[ 0.455474] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1387 04:39:53.261888 <6>[ 0.461955] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1388 04:39:53.267521 <6>[ 0.468933] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1389 04:39:53.272952 <6>[ 0.475402] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1390 04:39:53.278541 <6>[ 0.482387] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1391 04:39:53.284047 <6>[ 0.488857] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1392 04:39:53.295012 <6>[ 0.495841] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1393 04:39:53.295706 <6>[ 0.503851] ACPI: Interpreter disabled.
1394 04:39:53.300684 <6>[ 0.509333] iommu: Default domain type: Translated
1395 04:39:53.306105 <6>[ 0.511374] iommu: DMA domain TLB invalidation policy: strict mode
1396 04:39:53.311687 <5>[ 0.518063] SCSI subsystem initialized
1397 04:39:53.317140 <6>[ 0.521978] usbcore: registered new interface driver usbfs
1398 04:39:53.322664 <6>[ 0.527432] usbcore: registered new interface driver hub
1399 04:39:53.328189 <6>[ 0.532951] usbcore: registered new device driver usb
1400 04:39:53.333765 <6>[ 0.539222] pps_core: LinuxPPS API ver. 1 registered
1401 04:39:53.344695 <6>[ 0.543368] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1402 04:39:53.345363 <6>[ 0.552688] PTP clock support registered
1403 04:39:53.350279 <6>[ 0.556928] EDAC MC: Ver: 3.0.0
1404 04:39:53.355766 <6>[ 0.560587] scmi_core: SCMI protocol bus registered
1405 04:39:53.361308 <6>[ 0.566236] FPGA manager framework
1406 04:39:53.366823 <6>[ 0.568952] Advanced Linux Sound Architecture Driver Initialized.
1407 04:39:53.367466 <6>[ 0.575889] vgaarb: loaded
1408 04:39:53.372363 <6>[ 0.578442] clocksource: Switched to clocksource arch_sys_counter
1409 04:39:53.377852 <5>[ 0.584607] VFS: Disk quotas dquot_6.6.0
1410 04:39:53.383377 <6>[ 0.588583] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1411 04:39:53.388901 <6>[ 0.595793] pnp: PnP ACPI: disabled
1412 04:39:53.394417 <6>[ 0.604308] NET: Registered PF_INET protocol family
1413 04:39:53.400031 <6>[ 0.604610] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1414 04:39:53.410933 <6>[ 0.614779] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1415 04:39:53.416662 <6>[ 0.620783] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1416 04:39:53.427515 <6>[ 0.628683] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1417 04:39:53.433077 <6>[ 0.636916] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1418 04:39:53.444089 <6>[ 0.644716] TCP: Hash tables configured (established 32768 bind 32768)
1419 04:39:53.449704 <6>[ 0.651189] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1420 04:39:53.455130 <6>[ 0.658038] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1421 04:39:53.460763 <6>[ 0.665461] NET: Registered PF_UNIX/PF_LOCAL protocol family
1422 04:39:53.466204 <6>[ 0.671540] RPC: Registered named UNIX socket transport module.
1423 04:39:53.471697 <6>[ 0.677323] RPC: Registered udp transport module.
1424 04:39:53.477225 <6>[ 0.682232] RPC: Registered tcp transport module.
1425 04:39:53.482737 <6>[ 0.687146] RPC: Registered tcp-with-tls transport module.
1426 04:39:53.488305 <6>[ 0.692839] RPC: Registered tcp NFSv4.1 backchannel transport module.
1427 04:39:53.493774 <6>[ 0.699486] PCI: CLS 0 bytes, default 64
1428 04:39:53.499348 <6>[ 0.703756] Unpacking initramfs...
1429 04:39:53.504853 <6>[ 0.709861] kvm [1]: nv: 554 coarse grained trap handlers
1430 04:39:53.510348 <6>[ 0.713180] kvm [1]: IPA Size Limit: 40 bits
1431 04:39:53.511011 <6>[ 0.718788] kvm [1]: vgic interrupt IRQ9
1432 04:39:53.515874 <6>[ 0.721497] kvm [1]: Hyp nVHE mode initialized successfully
1433 04:39:53.521383 <5>[ 0.728831] Initialise system trusted keyrings
1434 04:39:53.526872 <6>[ 0.732089] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1435 04:39:53.532449 <6>[ 0.738811] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1436 04:39:53.538064 <5>[ 0.744873] NFS: Registering the id_resolver key type
1437 04:39:53.543513 <5>[ 0.749884] Key type id_resolver registered
1438 04:39:53.548995 <5>[ 0.754253] Key type id_legacy registered
1439 04:39:53.554517 <6>[ 0.758505] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1440 04:39:53.565570 <6>[ 0.765378] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1441 04:39:53.569447 <6>[ 0.773132] 9p: Installing v9fs 9p2000 file system support
1442 04:39:53.607397 <5>[ 0.819779] Key type asymmetric registered
1443 04:39:53.612970 <5>[ 0.819824] Asymmetric key parser 'x509' registered
1444 04:39:53.621995 <6>[ 0.823680] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1445 04:39:53.627499 <6>[ 0.831201] io scheduler mq-deadline registered
1446 04:39:53.633000 <6>[ 0.835940] io scheduler kyber registered
1447 04:39:53.633644 <6>[ 0.840204] io scheduler bfq registered
1448 04:39:53.641462 <6>[ 0.846110] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1449 04:39:53.657736 <6>[ 0.866318] ledtrig-cpu: registered to indicate activity on CPUs
1450 04:39:53.690201 <6>[ 0.897684] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1451 04:39:53.710106 <6>[ 0.911293] Serial: 8250/16550 driver, 4 ports,<6>[ 0.916030] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1452 04:39:53.715730 <6>[ 0.925667] printk: legacy console [ttyAML0] enabled
1453 04:39:53.721248 <6>[ 0.925667] printk: legacy console [ttyAML0] enabled
1454 04:39:53.726795 <6>[ 0.930481] printk: legacy bootconsole [meson0] disabled
1455 04:39:53.732346 <6>[ 0.930481] printk: legacy bootconsole [meson0] disabled
1456 04:39:53.737921 <6>[ 0.943252] msm_serial: driver initialized
1457 04:39:53.743434 <6>[ 0.946424] SuperH (H)SCI(F) driver initialized
1458 04:39:53.743964 <6>[ 0.950922] STM32 USART driver initialized
1459 04:39:53.748982 <5>[ 0.957124] random: crng init done
1460 04:39:53.756107 <6>[ 0.962812] loop: module loaded
1461 04:39:53.756611 <6>[ 0.964088] megasas: 07.727.03.00-rc1
1462 04:39:53.761692 <6>[ 0.973093] tun: Universal TUN/TAP device driver, 1.6
1463 04:39:53.767148 <6>[ 0.974308] thunder_xcv, ver 1.0
1464 04:39:53.772722 <6>[ 0.976277] thunder_bgx, ver 1.0
1465 04:39:53.773220 <6>[ 0.979727] nicpf, ver 1.0
1466 04:39:53.778283 <6>[ 0.984289] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1467 04:39:53.783795 <6>[ 0.990114] hns3: Copyright (c) 2017 Huawei Corporation.
1468 04:39:53.789343 <6>[ 0.995699] hclge is initializing
1469 04:39:53.794874 <6>[ 0.999245] e1000: Intel(R) PRO/1000 Network Driver
1470 04:39:53.800468 <6>[ 1.004322] e1000: Copyright (c) 1999-2006 Intel Corporation.
1471 04:39:53.805985 <6>[ 1.010349] e1000e: Intel(R) PRO/1000 Network Driver
1472 04:39:53.811544 <6>[ 1.015500] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1473 04:39:53.817095 <6>[ 1.021684] igb: Intel(R) Gigabit Ethernet Network Driver
1474 04:39:53.822680 <6>[ 1.027287] igb: Copyright (c) 2007-2014 Intel Corporation.
1475 04:39:53.828249 <6>[ 1.033126] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1476 04:39:53.833742 <6>[ 1.039595] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1477 04:39:53.839308 <6>[ 1.046344] sky2: driver version 1.30
1478 04:39:53.844866 <6>[ 1.051504] VFIO - User Level meta-driver version: 0.3
1479 04:39:53.850375 <6>[ 1.058987] usbcore: registered new interface driver usb-storage
1480 04:39:53.856452 <6>[ 1.065190] i2c_dev: i2c /dev entries driver
1481 04:39:53.869369 <6>[ 1.076291] sdhci: Secure Digital Host Controller Interface driver
1482 04:39:53.869870 <6>[ 1.077097] sdhci: Copyright(c) Pierre Ossman
1483 04:39:53.880513 <6>[ 1.082850] Synopsys Designware Multimedia Card Interface Driver
1484 04:39:53.886068 <6>[ 1.089351] sdhci-pltfm: SDHCI platform and OF driver helper
1485 04:39:53.886565 <6>[ 1.097033] meson-sm: secure-monitor enabled
1486 04:39:53.898896 <6>[ 1.099619] usbcore: registered new interface driver usbhid
1487 04:39:53.899398 <6>[ 1.104155] usbhid: USB HID core driver
1488 04:39:53.906717 <6>[ 1.119021] NET: Registered PF_PACKET protocol family
1489 04:39:53.912132 <6>[ 1.119109] 9pnet: Installing 9P2000 support
1490 04:39:53.919374 <5>[ 1.123264] Key type dns_resolver registered
1491 04:39:53.926689 <6>[ 1.135016] registered taskstats version 1
1492 04:39:53.927189 <5>[ 1.135168] Loading compiled-in X.509 certificates
1493 04:39:53.934088 <6>[ 1.143845] Demotion targets for Node 0: null
1494 04:39:53.974509 <6>[ 1.186879] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1495 04:39:53.980055 <6>[ 1.186923] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1496 04:39:53.991049 <4>[ 1.197114] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1497 04:39:53.996717 <4>[ 1.199699] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1498 04:39:54.002240 <6>[ 1.207270] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1499 04:39:54.007750 <6>[ 1.216481] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1500 04:39:54.018814 <6>[ 1.219987] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1501 04:39:54.029897 <6>[ 1.227955] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1502 04:39:54.035510 <6>[ 1.237484] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1503 04:39:54.041052 <6>[ 1.243709] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1504 04:39:54.046607 <6>[ 1.249331] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1505 04:39:54.052131 <6>[ 1.257217] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1506 04:39:54.057722 <6>[ 1.264491] hub 1-0:1.0: USB hub found
1507 04:39:54.063224 <6>[ 1.267986] hub 1-0:1.0: 2 ports detected
1508 04:39:54.068754 <6>[ 1.274052] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1509 04:39:54.074315 <6>[ 1.280959] hub 2-0:1.0: USB hub found
1510 04:39:54.079385 <6>[ 1.284531] hub 2-0:1.0: 1 port detected
1511 04:39:54.105386 <6>[ 1.315246] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1512 04:39:54.117388 <6>[ 1.326554] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1513 04:39:54.152258 <6>[ 1.361055] Trying to probe devices needed for running init ...
1514 04:39:54.314311 <6>[ 1.522482] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1515 04:39:54.458918 <6>[ 1.665778] mmc0: new ultra high speed SDR104 SDXC card at address e624
1516 04:39:54.464605 <6>[ 1.667942] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1517 04:39:54.465303 <6>[ 1.674954] Freeing initrd memory: 22880K
1518 04:39:54.468451 <6>[ 1.678096] mmcblk0: p1
1519 04:39:54.500035 <6>[ 1.712304] hub 1-1:1.0: USB hub found
1520 04:39:54.505732 <6>[ 1.712626] hub 1-1:1.0: 4 ports detected
1521 04:39:54.574471 <6>[ 1.782582] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1522 04:39:54.612604 <6>[ 1.824966] hub 2-1:1.0: USB hub found
1523 04:39:54.618301 <6>[ 1.825787] hub 2-1:1.0: 4 ports detected
1524 04:40:06.438442 <6>[ 13.650535] clk: Disabling unused clocks
1525 04:40:06.443796 <6>[ 13.650781] PM: genpd: Disabling unused power domains
1526 04:40:06.451963 <6>[ 13.654421] ALSA device list:
1527 04:40:06.452618 <6>[ 13.657611] No soundcards found.
1528 04:40:06.459185 <6>[ 13.671605] Freeing unused kernel memory: 10432K
1529 04:40:06.465548 <6>[ 13.671734] Run /init as init process
1530 04:40:06.472073 Loading, please wait...
1531 04:40:06.505981 Starting systemd-udevd version 252.22-1~deb12u1
1532 04:40:06.950543 <6>[ 14.160537] mc: Linux media interface: v0.10
1533 04:40:06.978303 <4>[ 14.185171] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1534 04:40:06.984118 <6>[ 14.191383] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1535 04:40:06.989466 <6>[ 14.195453] panfrost ffe40000.gpu: clock rate = 24000000
1536 04:40:06.995113 <6>[ 14.196533] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1537 04:40:07.006099 <3>[ 14.202572] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1538 04:40:07.011785 <6>[ 14.202807] videodev: Linux video capture interface: v2.00
1539 04:40:07.017351 <6>[ 14.206318] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1540 04:40:07.022856 <6>[ 14.227465] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1541 04:40:07.028442 <6>[ 14.233826] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1542 04:40:07.039357 <6>[ 14.240868] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1543 04:40:07.044953 <6>[ 14.244217] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1544 04:40:07.050318 <6>[ 14.247980] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1545 04:40:07.061528 <6>[ 14.255573] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1546 04:40:07.067074 <6>[ 14.260617] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1547 04:40:07.072606 <6>[ 14.260626] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1548 04:40:07.089186 <6>[ 14.269017] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1549 04:40:07.094798 <6>[ 14.269030] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1550 04:40:07.100384 <6>[ 14.276728] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1551 04:40:07.105905 <6>[ 14.296921] meson-vrtc ff8000a8.rtc: registered as rtc0
1552 04:40:07.111455 <6>[ 14.304070] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1553 04:40:07.122532 <6>[ 14.314259] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1554 04:40:07.128130 <3>[ 14.318772] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1555 04:40:07.133613 <6>[ 14.321352] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1556 04:40:07.139175 <6>[ 14.338012] Registered IR keymap rc-empty
1557 04:40:07.144711 <6>[ 14.344325] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1558 04:40:07.150260 <6>[ 14.354645] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1559 04:40:07.162968 <6>[ 14.360709] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1560 04:40:07.168554 <6>[ 14.376196] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1561 04:40:07.179620 <4>[ 14.379794] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1562 04:40:07.185203 <6>[ 14.379937] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1563 04:40:07.196290 <6>[ 14.388680] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 0
1564 04:40:07.201873 <6>[ 14.404735] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1565 04:40:07.207440 <6>[ 14.406509] rc rc0: sw decoder init
1566 04:40:07.218529 <6>[ 14.415294] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1567 04:40:07.224067 <6>[ 14.417972] meson-ir ff808000.ir: receiver initialized
1568 04:40:07.229584 <6>[ 14.427229] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1569 04:40:07.235143 <3>[ 14.440698] meson-drm ff900000.vpu: DSI transceiver device is disabled
1570 04:40:07.246160 <6>[ 14.447769] usbcore: registered new device driver onboard-usb-dev
1571 04:40:07.251041 <6>[ 14.448059] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 1
1572 04:40:07.262324 <6>[ 14.470711] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1573 04:40:07.437951 <4>[ 14.598461] rc rc0: two consecutive events of type space
1574 04:40:07.448848 <6>[ 14.631219] Console: switching to colour frame buffer device 128x48
1575 04:40:07.452743 <6>[ 14.656630] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1576 04:40:07.530459 <6>[ 14.734389] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1577 04:40:07.684402 <6>[ 14.896465] hub 1-1:1.0: USB hub found
1578 04:40:07.689678 <6>[ 14.896805] hub 1-1:1.0: 4 ports detected
1579 04:40:07.696127 <6>[ 14.902328] onboard-usb-dev 1-1: USB disconnect, device number 2
1580 04:40:07.825048 Begin: Loading essential drivers ... done.
1581 04:40:07.830436 Begin: Running /scripts/init-premount ... done.
1582 04:40:07.835977 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1583 04:40:07.849699 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1584 04:40:07.850315 Device /sys/class/net/end0 found
1585 04:40:07.850860 done.
1586 04:40:07.867685 Begin: Waiting up to 180 secs for any network device to become available ... done.
1587 04:40:07.921165 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.123669] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1588 04:40:07.921796
1589 04:40:08.010348 <6>[ 15.214562] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=32)
1590 04:40:08.022196 <6>[ 15.227809] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1591 04:40:08.027840 <6>[ 15.230001] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1592 04:40:08.035773 <6>[ 15.237344] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1593 04:40:08.066291 <6>[ 15.274492] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1594 04:40:08.260043 <6>[ 15.472372] hub 1-1:1.0: USB hub found
1595 04:40:08.265757 <6>[ 15.472678] hub 1-1:1.0: 4 ports detected
1596 04:40:08.456337 <6>[ 15.664258] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1597 04:40:08.712266 <6>[ 15.920246] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1598 04:40:09.603817 IP-Config: no response after 2 secs - giving up
1599 04:40:09.666082 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1600 04:40:10.987865 <6>[ 18.194145] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1601 04:40:11.875975 IP-Config: end0 guessed broadcast address 192.168.6.255
1602 04:40:11.881363 IP-Config: end0 complete (dhcp from 192.168.6.1):
1603 04:40:11.886898 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1604 04:40:11.897886 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1605 04:40:11.898356 rootserver: 192.168.6.1 rootpath:
1606 04:40:11.901339 filename :
1607 04:40:12.006979 done.
1608 04:40:12.017413 Begin: Running /scripts/nfs-bottom ... done.
1609 04:40:12.036342 Begin: Running /scripts/init-bottom ... done.
1610 04:40:12.376216 <30>[ 19.583906] systemd[1]: System time before build time, advancing clock.
1611 04:40:12.440382 <6>[ 19.652471] NET: Registered PF_INET6 protocol family
1612 04:40:12.445881 <6>[ 19.654515] Segment Routing with IPv6
1613 04:40:12.450988 <6>[ 19.655989] In-situ OAM (IOAM) with IPv6
1614 04:40:12.530556 <30>[ 19.715130] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1615 04:40:12.536989 <30>[ 19.742574] systemd[1]: Detected architecture arm64.
1616 04:40:12.537499
1617 04:40:12.543856 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1618 04:40:12.544389
1619 04:40:12.560192 <30>[ 19.768689] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1620 04:40:13.336553 <30>[ 20.543802] systemd[1]: Queued start job for default target graphical.target.
1621 04:40:13.378061 <30>[ 20.584816] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1622 04:40:13.385814 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1623 04:40:13.396783 <30>[ 20.603487] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1624 04:40:13.405207 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1625 04:40:13.416907 <30>[ 20.623474] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1626 04:40:13.425975 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1627 04:40:13.436667 <30>[ 20.643203] systemd[1]: Created slice user.slice - User and Session Slice.
1628 04:40:13.443116 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1629 04:40:13.454214 <30>[ 20.658709] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1630 04:40:13.465635 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1631 04:40:13.476708 <30>[ 20.678653] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1632 04:40:13.483451 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1633 04:40:13.505436 <30>[ 20.698618] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1634 04:40:13.511032 <30>[ 20.712690] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1635 04:40:13.518729 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1636 04:40:13.529867 <30>[ 20.734540] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1637 04:40:13.535869 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1638 04:40:13.551606 <30>[ 20.758553] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1639 04:40:13.565390 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1640 04:40:13.570960 <30>[ 20.778588] systemd[1]: Reached target paths.target - Path Units.
1641 04:40:13.579400 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1642 04:40:13.584878 <30>[ 20.794555] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1643 04:40:13.596565 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1644 04:40:13.602114 <30>[ 20.810522] systemd[1]: Reached target slices.target - Slice Units.
1645 04:40:13.610271 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1646 04:40:13.615868 <30>[ 20.826560] systemd[1]: Reached target swap.target - Swaps.
1647 04:40:13.623693 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1648 04:40:13.635629 <30>[ 20.842576] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1649 04:40:13.644495 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1650 04:40:13.659754 <30>[ 20.866731] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1651 04:40:13.669065 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1652 04:40:13.681060 <30>[ 20.887962] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1653 04:40:13.689862 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1654 04:40:13.701110 <30>[ 20.908060] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1655 04:40:13.714082 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1656 04:40:13.719658 <30>[ 20.927359] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1657 04:40:13.727840 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1658 04:40:13.745244 <30>[ 20.952190] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1659 04:40:13.754482 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1660 04:40:13.766386 <30>[ 20.973232] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1661 04:40:13.771893 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1662 04:40:13.784279 <30>[ 20.991199] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1663 04:40:13.792760 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1664 04:40:13.847861 <30>[ 21.054805] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1665 04:40:13.854653 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1666 04:40:13.868134 <30>[ 21.075046] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1667 04:40:13.875665 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1668 04:40:13.896140 <30>[ 21.103052] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1669 04:40:13.903584 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1670 04:40:13.926425 <30>[ 21.127159] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1671 04:40:13.934817 <30>[ 21.142895] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1672 04:40:13.944493 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1673 04:40:13.960670 <30>[ 21.167581] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1674 04:40:13.968643 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1675 04:40:13.984751 <30>[ 21.191678] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1676 04:40:13.992427 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1677 04:40:14.006191 <30>[ 21.213132] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1678 04:40:14.017278 <6>[ 21.213777] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1679 04:40:14.022237 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1680 04:40:14.038564 <30>[ 21.245461] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1681 04:40:14.046855 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1682 04:40:14.058080 <30>[ 21.264997] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1683 04:40:14.065351 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1684 04:40:14.082516 <30>[ 21.289396] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1685 04:40:14.088065 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1686 04:40:14.091965 <6>[ 21.302277] fuse: init (API version 7.41)
1687 04:40:14.116297 <30>[ 21.323199] systemd[1]: Starting systemd-journald.service - Journal Service...
1688 04:40:14.122680 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1689 04:40:14.141880 <30>[ 21.348755] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1690 04:40:14.149368 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1691 04:40:14.164751 <30>[ 21.371701] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1692 04:40:14.174111 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1693 04:40:14.185779 <30>[ 21.392731] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1694 04:40:14.194614 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1695 04:40:14.209791 <30>[ 21.416734] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1696 04:40:14.217837 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1697 04:40:14.234273 <30>[ 21.441081] systemd[1]: Started systemd-journald.service - Journal Service.
1698 04:40:14.241068 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1699 04:40:14.256783 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1700 04:40:14.272465 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1701 04:40:14.284465 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1702 04:40:14.296637 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1703 04:40:14.312953 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1704 04:40:14.324912 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1705 04:40:14.340597 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1706 04:40:14.356896 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1707 04:40:14.372679 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1708 04:40:14.388715 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1709 04:40:14.404786 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1710 04:40:14.420708 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1711 04:40:14.436604 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1712 04:40:14.452973 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1713 04:40:14.511335 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1714 04:40:14.528800 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1715 04:40:14.547252 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1716 04:40:14.560822 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1717 04:40:14.576411 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1718 04:40:14.590772 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1719 04:40:14.613609 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m -<46>[ 21.815601] systemd-journald[226]: Received client request to flush runtime journal.
1720 04:40:14.614139 Coldplug All udev Devices.
1721 04:40:14.624534 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1722 04:40:14.640431 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1723 04:40:14.656434 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1724 04:40:14.665091 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1725 04:40:14.712336 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1726 04:40:14.753982 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1727 04:40:14.904617 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1728 04:40:14.912108 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1729 04:40:14.928732 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1730 04:40:14.943487 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1731 04:40:15.011016 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1732 04:40:15.017714 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1733 04:40:15.237497 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1734 04:40:15.283027 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1735 04:40:15.333776 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1736 04:40:15.340994 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1737 04:40:15.403465 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1738 04:40:15.414215 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1739 04:40:15.444111 <5>[ 22.651105] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1740 04:40:15.482509 <5>[ 22.689311] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1741 04:40:15.487929 <5>[ 22.690292] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1742 04:40:15.499127 [<4>[ 22.698155] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1743 04:40:15.499802 <6>[ 22.706492] cfg80211: failed to load regulatory.db
1744 04:40:15.510034 [0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1745 04:40:15.588286 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1746 04:40:15.600412 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1747 04:40:15.620260 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1748 04:40:15.631911 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1749 04:40:15.648658 <46>[ 22.846280] systemd-journald[226]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1750 04:40:15.664616 <46>[ 22.859164] systemd-journald[226]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1751 04:40:15.680280 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1752 04:40:15.695039 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1753 04:40:15.789094 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1754 04:40:15.803795 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1755 04:40:15.811258 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1756 04:40:15.850826 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1757 04:40:15.868057 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1758 04:40:15.878813 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1759 04:40:15.891974 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1760 04:40:15.913564 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1761 04:40:15.926763 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1762 04:40:15.938769 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1763 04:40:15.974701 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1764 04:40:15.991226 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1765 04:40:16.008579 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1766 04:40:16.021251 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1767 04:40:16.058155 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1768 04:40:16.093409 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1769 04:40:16.099944 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1770 04:40:16.115783 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1771 04:40:16.163892 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1772 04:40:16.176934 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1773 04:40:16.195195 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1774 04:40:16.218830 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1775 04:40:16.231701 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1776 04:40:16.238783 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1777 04:40:16.248198 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1778 04:40:16.269049 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1779 04:40:16.275599 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1780 04:40:16.328710 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1781 04:40:16.383857 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1782 04:40:16.457007
1783 04:40:16.457594 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1784 04:40:16.458025
1785 04:40:16.464166 debian-bookworm-arm64 login: root (automatic login)
1786 04:40:16.464681
1787 04:40:16.614735 Linux debian-bookworm-arm64 6.12.0-rc2 #1 SMP PREEMPT Thu Nov 7 00:44:34 UTC 2024 aarch64
1788 04:40:16.615368
1789 04:40:16.620296 The programs included with the Debian GNU/Linux system are free software;
1790 04:40:16.625852 the exact distribution terms for each program are described in the
1791 04:40:16.631361 individual files in /usr/share/doc/*/copyright.
1792 04:40:16.631851
1793 04:40:16.636907 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1794 04:40:16.640060 permitted by applicable law.
1795 04:40:17.291484 Matched prompt #10: / #
1797 04:40:17.293049 Setting prompt string to ['/ #']
1798 04:40:17.293585 end: 2.4.4.1 login-action (duration 00:00:25) [common]
1800 04:40:17.294917 end: 2.4.4 auto-login-action (duration 00:00:25) [common]
1801 04:40:17.295432 start: 2.4.5 expect-shell-connection (timeout 00:03:11) [common]
1802 04:40:17.295859 Setting prompt string to ['/ #']
1803 04:40:17.296348 Forcing a shell prompt, looking for ['/ #']
1805 04:40:17.347269 / #
1806 04:40:17.347868 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1807 04:40:17.348460 Waiting using forced prompt support (timeout 00:02:30)
1808 04:40:17.352722
1809 04:40:17.353513 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1810 04:40:17.354049 start: 2.4.6 export-device-env (timeout 00:03:11) [common]
1811 04:40:17.354502 Sending with 10 millisecond of delay
1813 04:40:22.341130 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/950934/extract-nfsrootfs-k6hj5bfk'
1814 04:40:22.352116 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/950934/extract-nfsrootfs-k6hj5bfk'
1815 04:40:22.352878 Sending with 10 millisecond of delay
1817 04:40:24.450317 / # export NFS_SERVER_IP='192.168.6.2'
1818 04:40:24.461237 export NFS_SERVER_IP='192.168.6.2'
1819 04:40:24.462084 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1820 04:40:24.462670 end: 2.4 uboot-commands (duration 00:01:56) [common]
1821 04:40:24.463259 end: 2 uboot-action (duration 00:01:56) [common]
1822 04:40:24.463817 start: 3 lava-test-retry (timeout 00:06:46) [common]
1823 04:40:24.464457 start: 3.1 lava-test-shell (timeout 00:06:46) [common]
1824 04:40:24.464929 Using namespace: common
1826 04:40:24.566141 / # #
1827 04:40:24.566838 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1828 04:40:24.571812 #
1829 04:40:24.572582 Using /lava-950934
1831 04:40:24.673680 / # export SHELL=/bin/bash
1832 04:40:24.679243 export SHELL=/bin/bash
1834 04:40:24.780632 / # . /lava-950934/environment
1835 04:40:24.784487 . /lava-950934/environment
1837 04:40:24.891213 / # /lava-950934/bin/lava-test-runner /lava-950934/0
1838 04:40:24.891789 Test shell timeout: 10s (minimum of the action and connection timeout)
1839 04:40:24.896093 /lava-950934/bin/lava-test-runner /lava-950934/0
1840 04:40:25.102340 + export TESTRUN_ID=0_timesync-off
1841 04:40:25.110213 + TESTRUN_ID=0_timesync-off
1842 04:40:25.110659 + cd /lava-950934/0/tests/0_timesync-off
1843 04:40:25.111075 ++ cat uuid
1844 04:40:25.115733 + UUID=950934_1.6.2.4.1
1845 04:40:25.116227 + set +x
1846 04:40:25.123382 <LAVA_SIGNAL_STARTRUN 0_timesync-off 950934_1.6.2.4.1>
1847 04:40:25.123819 + systemctl stop systemd-timesyncd
1848 04:40:25.124548 Received signal: <STARTRUN> 0_timesync-off 950934_1.6.2.4.1
1849 04:40:25.124987 Starting test lava.0_timesync-off (950934_1.6.2.4.1)
1850 04:40:25.125504 Skipping test definition patterns.
1851 04:40:25.177374 + set +x
1852 04:40:25.177833 <LAVA_SIGNAL_ENDRUN 0_timesync-off 950934_1.6.2.4.1>
1853 04:40:25.178492 Received signal: <ENDRUN> 0_timesync-off 950934_1.6.2.4.1
1854 04:40:25.178971 Ending use of test pattern.
1855 04:40:25.179377 Ending test lava.0_timesync-off (950934_1.6.2.4.1), duration 0.05
1857 04:40:25.264918 + export TESTRUN_ID=1_kselftest-alsa
1858 04:40:25.273273 + TESTRUN_ID=1_kselftest-alsa
1859 04:40:25.273716 + cd /lava-950934/0/tests/1_kselftest-alsa
1860 04:40:25.274130 ++ cat uuid
1861 04:40:25.283095 + UUID=950934_1.6.2.4.5
1862 04:40:25.283536 + set +x
1863 04:40:25.288529 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 950934_1.6.2.4.5>
1864 04:40:25.288977 + cd ./automated/linux/kselftest/
1865 04:40:25.289647 Received signal: <STARTRUN> 1_kselftest-alsa 950934_1.6.2.4.5
1866 04:40:25.290078 Starting test lava.1_kselftest-alsa (950934_1.6.2.4.5)
1867 04:40:25.290552 Skipping test definition patterns.
1868 04:40:25.319156 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-235-gf366870b9966d/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1869 04:40:25.355869 INFO: install_deps skipped
1870 04:40:25.473405 --2024-11-07 04:40:25-- http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-235-gf366870b9966d/arm64/defconfig/gcc-12/kselftest.tar.xz
1871 04:40:25.729539 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1872 04:40:25.866303 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1873 04:40:26.007247 HTTP request sent, awaiting response... 200 OK
1874 04:40:26.007685 Length: 6921612 (6.6M) [application/octet-stream]
1875 04:40:26.012813 Saving to: 'kselftest_armhf.tar.gz'
1876 04:40:26.013248
1877 04:40:27.264417
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 47.54K 177KB/s
kselftest_armhf.tar 3%[ ] 218.67K 408KB/s
kselftest_armhf.tar 13%[=> ] 893.67K 1.08MB/s
kselftest_armhf.tar 46%[========> ] 3.08M 2.81MB/s
kselftest_armhf.tar 100%[===================>] 6.60M 5.30MB/s in 1.2s
1878 04:40:27.265079
1879 04:40:27.362896 2024-11-07 04:40:27 (5.30 MB/s) - 'kselftest_armhf.tar.gz' saved [6921612/6921612]
1880 04:40:27.363422
1881 04:40:36.549447 skiplist:
1882 04:40:36.550089 ========================================
1883 04:40:36.554953 ========================================
1884 04:40:36.594574 alsa:mixer-test
1885 04:40:36.595050 alsa:pcm-test
1886 04:40:36.595465 alsa:test-pcmtest-driver
1887 04:40:36.598658 alsa:utimer-test
1888 04:40:36.609902 ============== Tests to run ===============
1889 04:40:36.615737 alsa:mixer-test
1890 04:40:36.616220 alsa:pcm-test
1891 04:40:36.616631 alsa:test-pcmtest-driver
1892 04:40:36.621269 alsa:utimer-test
1893 04:40:36.621694 ===========End Tests to run ===============
1894 04:40:36.625674 shardfile-alsa pass
1895 04:40:36.738022 <12>[ 43.948777] kselftest: Running tests in alsa
1896 04:40:36.741532 TAP version 13
1897 04:40:36.751755 1..4
1898 04:40:36.774972 # timeout set to 45
1899 04:40:36.775397 # selftests: alsa: mixer-test
1900 04:40:36.933263 # TAP version 13
1901 04:40:36.933853 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1902 04:40:36.938659 # 1..427
1903 04:40:36.939087 # ok 1 get_value.LCALTA.60
1904 04:40:36.939488 # # LCALTA.60 TDMOUT_A SRC SEL
1905 04:40:36.944230 # ok 2 name.LCALTA.60
1906 04:40:36.944650 # ok 3 write_default.LCALTA.60
1907 04:40:36.949733 # ok 4 write_valid.LCALTA.60
1908 04:40:36.950148 # ok 5 write_invalid.LCALTA.60
1909 04:40:36.955353 # ok 6 event_missing.LCALTA.60
1910 04:40:36.955779 # ok 7 event_spurious.LCALTA.60
1911 04:40:36.960934 # ok 8 get_value.LCALTA.59
1912 04:40:36.961354 # # LCALTA.59 TDMOUT_B SRC SEL
1913 04:40:36.966543 # ok 9 name.LCALTA.59
1914 04:40:36.966974 # ok 10 write_default.LCALTA.59
1915 04:40:36.972078 # ok 11 write_valid.LCALTA.59
1916 04:40:36.972511 # ok 12 write_invalid.LCALTA.59
1917 04:40:36.977678 # ok 13 event_missing.LCALTA.59
1918 04:40:36.978130 # ok 14 event_spurious.LCALTA.59
1919 04:40:36.983046 # ok 15 get_value.LCALTA.58
1920 04:40:36.983545 # # LCALTA.58 TDMOUT_C SRC SEL
1921 04:40:36.988652 # ok 16 name.LCALTA.58
1922 04:40:36.989085 # ok 17 write_default.LCALTA.58
1923 04:40:36.994203 # ok 18 write_valid.LCALTA.58
1924 04:40:36.994626 # ok 19 write_invalid.LCALTA.58
1925 04:40:36.999670 # ok 20 event_missing.LCALTA.58
1926 04:40:37.000124 # ok 21 event_spurious.LCALTA.58
1927 04:40:37.005143 # ok 22 get_value.LCALTA.57
1928 04:40:37.005561 # # LCALTA.57 TDMIN_A SRC SEL
1929 04:40:37.005961 # ok 23 name.LCALTA.57
1930 04:40:37.010714 # ok 24 write_default.LCALTA.57
1931 04:40:37.011138 # ok 25 write_valid.LCALTA.57
1932 04:40:37.016257 # ok 26 write_invalid.LCALTA.57
1933 04:40:37.016679 # ok 27 event_missing.LCALTA.57
1934 04:40:37.021820 # ok 28 event_spurious.LCALTA.57
1935 04:40:37.022272 # ok 29 get_value.LCALTA.56
1936 04:40:37.027482 # # LCALTA.56 TDMIN_B SRC SEL
1937 04:40:37.027976 # ok 30 name.LCALTA.56
1938 04:40:37.032961 # ok 31 write_default.LCALTA.56
1939 04:40:37.033426 # ok 32 write_valid.LCALTA.56
1940 04:40:37.049590 # ok 33 write_invalid<3>[ 44.246689] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1941 04:40:37.050182 .LCALTA.56
1942 04:40:37.050659 # ok 34 event_missing.LCALTA.56
1943 04:40:37.055093 # ok 35 event_spurious.LCALTA.56
1944 04:40:37.055580 # ok 36 get_value.LCALTA.55
1945 04:40:37.060659 # # LCALTA.55 TDMIN_C SRC SEL
1946 04:40:37.061148 # ok 37 name.LCALTA.55
1947 04:40:37.066208 # ok 38 write_default.LCALTA.55
1948 04:40:37.066688 # ok 39 write_valid.LCALTA.55
1949 04:40:37.071738 # ok 40 write_invalid.LCALTA.55
1950 04:40:37.072247 # ok 41 event_missing.LCALTA.55
1951 04:40:37.077283 # ok 42 event_spurious.LCALTA.55
1952 04:40:37.077755 # ok 43 get_value.LCALTA.54
1953 04:40:37.082846 # # LCALTA.54 ACODEC Left DAC Sel
1954 04:40:37.083321 # ok 44 name.LCALTA.54
1955 04:40:37.088452 # ok 45 write_default.LCALTA.54
1956 04:40:37.088922 # ok 46 write_valid.LCALTA.54
1957 04:40:37.093938 # ok 47 write_invalid.LCALTA.54
1958 04:40:37.094405 # ok 48 event_missing.LCALTA.54
1959 04:40:37.099579 # ok 49 event_spurious.LCALTA.54
1960 04:40:37.100079 # ok 50 get_value.LCALTA.53
1961 04:40:37.105022 # # LCALTA.53 ACODEC Right DAC Sel
1962 04:40:37.105491 # ok 51 name.LCALTA.53
1963 04:40:37.110710 # ok 52 write_default.LCALTA.53
1964 04:40:37.111177 # ok 53 write_valid.LCALTA.53
1965 04:40:37.116086 # ok 54 write_invalid.LCALTA.53
1966 04:40:37.116554 # ok 55 event_missing.LCALTA.53
1967 04:40:37.121671 # ok 56 event_spurious.LCALTA.53
1968 04:40:37.122137 # ok 57 get_value.LCALTA.52
1969 04:40:37.127209 # # LCALTA.52 TOACODEC OUT EN Switch
1970 04:40:37.127678 # ok 58 name.LCALTA.52
1971 04:40:37.132753 # ok 59 write_default.LCALTA.52
1972 04:40:37.133223 # ok 60 write_valid.LCALTA.52
1973 04:40:37.138323 # ok 61 write_invalid.LCALTA.52
1974 04:40:37.138791 # ok 62 event_missing.LCALTA.52
1975 04:40:37.143850 # ok 63 event_spurious.LCALTA.52
1976 04:40:37.144367 # ok 64 get_value.LCALTA.51
1977 04:40:37.149470 # # LCALTA.51 TOACODEC SRC
1978 04:40:37.149947 # ok 65 name.LCALTA.51
1979 04:40:37.154940 # ok 66 write_default.LCALTA.51
1980 04:40:37.155412 # ok 67 write_valid.LCALTA.51
1981 04:40:37.160591 # ok 68 write_invalid.LCALTA.51
1982 04:40:37.161063 # ok 69 event_missing.LCALTA.51
1983 04:40:37.166034 # ok 70 event_spurious.LCALTA.51
1984 04:40:37.166502 # ok 71 get_value.LCALTA.50
1985 04:40:37.171619 # # LCALTA.50 TOHDMITX SPDIF SRC
1986 04:40:37.172139 # ok 72 name.LCALTA.50
1987 04:40:37.172592 # ok 73 write_default.LCALTA.50
1988 04:40:37.177136 # ok 74 write_valid.LCALTA.50
1989 04:40:37.177605 # ok 75 write_invalid.LCALTA.50
1990 04:40:37.182665 # ok 76 event_missing.LCALTA.50
1991 04:40:37.188228 # ok 77 event_spurious.LCALTA.50
1992 04:40:37.188697 # ok 78 get_value.LCALTA.49
1993 04:40:37.189137 # # LCALTA.49 TOHDMITX Switch
1994 04:40:37.193771 # ok 79 name.LCALTA.49
1995 04:40:37.194249 # ok 80 write_default.LCALTA.49
1996 04:40:37.199301 # ok 81 write_valid.LCALTA.49
1997 04:40:37.199768 # ok 82 write_invalid.LCALTA.49
1998 04:40:37.204864 # ok 83 event_missing.LCALTA.49
1999 04:40:37.205333 # ok 84 event_spurious.LCALTA.49
2000 04:40:37.210475 # ok 85 get_value.LCALTA.48
2001 04:40:37.210950 # # LCALTA.48 TOHDMITX I2S SRC
2002 04:40:37.215966 # ok 86 name.LCALTA.48
2003 04:40:37.216479 # ok 87 write_default.LCALTA.48
2004 04:40:37.221608 # ok 88 write_valid.LCALTA.48
2005 04:40:37.222073 # ok 89 write_invalid.LCALTA.48
2006 04:40:37.227064 # ok 90 event_missing.LCALTA.48
2007 04:40:37.227527 # ok 91 event_spurious.LCALTA.48
2008 04:40:37.232610 # ok 92 get_value.LCALTA.47
2009 04:40:37.233087 # # LCALTA.47 TODDR_C SRC SEL
2010 04:40:37.238160 # ok 93 name.LCALTA.47
2011 04:40:37.238639 # ok 94 write_default.LCALTA.47
2012 04:40:37.243700 # ok 95 write_valid.LCALTA.47
2013 04:40:37.244213 # ok 96 write_invalid.LCALTA.47
2014 04:40:37.249235 # ok 97 event_missing.LCALTA.47
2015 04:40:37.249706 # ok 98 event_spurious.LCALTA.47
2016 04:40:37.254781 # ok 99 get_value.LCALTA.46
2017 04:40:37.255250 # # LCALTA.46 TODDR_B SRC SEL
2018 04:40:37.255693 # ok 100 name.LCALTA.46
2019 04:40:37.260326 # ok 101 write_default.LCALTA.46
2020 04:40:37.265864 # ok 102 write_valid.LCALTA.46
2021 04:40:37.266336 # ok 103 write_invalid.LCALTA.46
2022 04:40:37.271490 # ok 104 event_missing.LCALTA.46
2023 04:40:37.271969 # ok 105 event_spurious.LCALTA.46
2024 04:40:37.276995 # ok 106 get_value.LCALTA.45
2025 04:40:37.277465 # # LCALTA.45 TODDR_A SRC SEL
2026 04:40:37.277909 # ok 107 name.LCALTA.45
2027 04:40:37.282605 # ok 108 write_default.LCALTA.45
2028 04:40:37.288060 # ok 109 write_valid.LCALTA.45
2029 04:40:37.288525 # ok 110 write_invalid.LCALTA.45
2030 04:40:37.293668 # ok 111 event_missing.LCALTA.45
2031 04:40:37.294150 # ok 112 event_spurious.LCALTA.45
2032 04:40:37.299169 # ok 113 get_value.LCALTA.44
2033 04:40:37.299664 # # LCALTA.44 FRDDR_C SINK 3 SEL
2034 04:40:37.304724 # ok 114 name.LCALTA.44
2035 04:40:37.305192 # ok 115 write_default.LCALTA.44
2036 04:40:37.310250 # ok 116 write_valid.LCALTA.44
2037 04:40:37.310722 # ok 117 write_invalid.LCALTA.44
2038 04:40:37.315798 # ok 118 event_missing.LCALTA.44
2039 04:40:37.316298 # ok 119 event_spurious.LCALTA.44
2040 04:40:37.321363 # ok 120 get_value.LCALTA.43
2041 04:40:37.321833 # # LCALTA.43 FRDDR_C SINK 2 SEL
2042 04:40:37.326907 # ok 121 name.LCALTA.43
2043 04:40:37.327383 # ok 122 write_default.LCALTA.43
2044 04:40:37.332490 # ok 123 write_valid.LCALTA.43
2045 04:40:37.332962 # ok 124 write_invalid.LCALTA.43
2046 04:40:37.337973 # ok 125 event_missing.LCALTA.43
2047 04:40:37.338438 # ok 126 event_spurious.LCALTA.43
2048 04:40:37.343612 # ok 127 get_value.LCALTA.42
2049 04:40:37.344112 # # LCALTA.42 FRDDR_C SINK 1 SEL
2050 04:40:37.349094 # ok 128 name.LCALTA.42
2051 04:40:37.349567 # ok 129 write_default.LCALTA.42
2052 04:40:37.354700 # ok 130 write_valid.LCALTA.42
2053 04:40:37.355170 # ok 131 write_invalid.LCALTA.42
2054 04:40:37.360202 # ok 132 event_missing.LCALTA.42
2055 04:40:37.360673 # ok 133 event_spurious.LCALTA.42
2056 04:40:37.365734 # ok 134 get_value.LCALTA.41
2057 04:40:37.366211 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
2058 04:40:37.371276 # ok 135 name.LCALTA.41
2059 04:40:37.371749 # ok 136 write_default.LCALTA.41
2060 04:40:37.376812 # ok 137 write_valid.LCALTA.41
2061 04:40:37.377289 # ok 138 write_invalid.LCALTA.41
2062 04:40:37.382376 # ok 139 event_missing.LCALTA.41
2063 04:40:37.382860 # ok 140 event_spurious.LCALTA.41
2064 04:40:37.387921 # ok 141 get_value.LCALTA.40
2065 04:40:37.388440 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
2066 04:40:37.393509 # ok 142 name.LCALTA.40
2067 04:40:37.393991 # ok 143 write_default.LCALTA.40
2068 04:40:37.398974 # ok 144 write_valid.LCALTA.40
2069 04:40:37.399452 # ok 145 write_invalid.LCALTA.40
2070 04:40:37.404651 # ok 146 event_missing.LCALTA.40
2071 04:40:37.405134 # ok 147 event_spurious.LCALTA.40
2072 04:40:37.410101 # ok 148 get_value.LCALTA.39
2073 04:40:37.415918 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
2074 04:40:37.416454 # ok 149 name.LCALTA.39
2075 04:40:37.416907 # ok 150 write_default.LCALTA.39
2076 04:40:37.421238 # ok 151 write_valid.LCALTA.39
2077 04:40:37.421720 # ok 152 write_invalid.LCALTA.39
2078 04:40:37.426725 # ok 153 event_missing.LCALTA.39
2079 04:40:37.432287 # ok 154 event_spurious.LCALTA.39
2080 04:40:37.432782 # ok 155 get_value.LCALTA.38
2081 04:40:37.437809 # # LCALTA.38 FRDDR_B SINK 3 SEL
2082 04:40:37.438288 # ok 156 name.LCALTA.38
2083 04:40:37.438735 # ok 157 write_default.LCALTA.38
2084 04:40:37.443387 # ok 158 write_valid.LCALTA.38
2085 04:40:37.443863 # ok 159 write_invalid.LCALTA.38
2086 04:40:37.448906 # ok 160 event_missing.LCALTA.38
2087 04:40:37.454499 # ok 161 event_spurious.LCALTA.38
2088 04:40:37.454977 # ok 162 get_value.LCALTA.37
2089 04:40:37.460027 # # LCALTA.37 FRDDR_B SINK 2 SEL
2090 04:40:37.460505 # ok 163 name.LCALTA.37
2091 04:40:37.460952 # ok 164 write_default.LCALTA.37
2092 04:40:37.465637 # ok 165 write_valid.LCALTA.37
2093 04:40:37.471119 # ok 166 write_invalid.LCALTA.37
2094 04:40:37.471668 # ok 167 event_missing.LCALTA.37
2095 04:40:37.476696 # ok 168 event_spurious.LCALTA.37
2096 04:40:37.477239 # ok 169 get_value.LCALTA.36
2097 04:40:37.482246 # # LCALTA.36 FRDDR_B SINK 1 SEL
2098 04:40:37.482730 # ok 170 name.LCALTA.36
2099 04:40:37.487746 # ok 171 write_default.LCALTA.36
2100 04:40:37.488255 # ok 172 write_valid.LCALTA.36
2101 04:40:37.493281 # ok 173 write_invalid.LCALTA.36
2102 04:40:37.493748 # ok 174 event_missing.LCALTA.36
2103 04:40:37.498838 # ok 175 event_spurious.LCALTA.36
2104 04:40:37.499309 # ok 176 get_value.LCALTA.35
2105 04:40:37.504405 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
2106 04:40:37.504882 # ok 177 name.LCALTA.35
2107 04:40:37.509900 # ok 178 write_default.LCALTA.35
2108 04:40:37.510370 # ok 179 write_valid.LCALTA.35
2109 04:40:37.515493 # ok 180 write_invalid.LCALTA.35
2110 04:40:37.516005 # ok 181 event_missing.LCALTA.35
2111 04:40:37.520994 # ok 182 event_spurious.LCALTA.35
2112 04:40:37.521470 # ok 183 get_value.LCALTA.34
2113 04:40:37.526749 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
2114 04:40:37.527230 # ok 184 name.LCALTA.34
2115 04:40:37.532163 # ok 185 write_default.LCALTA.34
2116 04:40:37.532645 # ok 186 write_valid.LCALTA.34
2117 04:40:37.537684 # ok 187 write_invalid.LCALTA.34
2118 04:40:37.538164 # ok 188 event_missing.LCALTA.34
2119 04:40:37.543207 # ok 189 event_spurious.LCALTA.34
2120 04:40:37.543685 # ok 190 get_value.LCALTA.33
2121 04:40:37.548768 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
2122 04:40:37.549254 # ok 191 name.LCALTA.33
2123 04:40:37.554288 # ok 192 write_default.LCALTA.33
2124 04:40:37.554766 # ok 193 write_valid.LCALTA.33
2125 04:40:37.559849 # ok 194 write_invalid.LCALTA.33
2126 04:40:37.560386 # ok 195 event_missing.LCALTA.33
2127 04:40:37.565394 # ok 196 event_spurious.LCALTA.33
2128 04:40:37.565880 # ok 197 get_value.LCALTA.32
2129 04:40:37.570952 # # LCALTA.32 FRDDR_A SINK 3 SEL
2130 04:40:37.571432 # ok 198 name.LCALTA.32
2131 04:40:37.576507 # ok 199 write_default.LCALTA.32
2132 04:40:37.576990 # ok 200 write_valid.LCALTA.32
2133 04:40:37.582035 # ok 201 write_invalid.LCALTA.32
2134 04:40:37.582509 # ok 202 event_missing.LCALTA.32
2135 04:40:37.587661 # ok 203 event_spurious.LCALTA.32
2136 04:40:37.588183 # ok 204 get_value.LCALTA.31
2137 04:40:37.593144 # # LCALTA.31 FRDDR_A SINK 2 SEL
2138 04:40:37.593616 # ok 205 name.LCALTA.31
2139 04:40:37.598693 # ok 206 write_default.LCALTA.31
2140 04:40:37.599160 # ok 207 write_valid.LCALTA.31
2141 04:40:37.604234 # ok 208 write_invalid.LCALTA.31
2142 04:40:37.604707 # ok 209 event_missing.LCALTA.31
2143 04:40:37.609783 # ok 210 event_spurious.LCALTA.31
2144 04:40:37.610303 # ok 211 get_value.LCALTA.30
2145 04:40:37.615345 # # LCALTA.30 FRDDR_A SINK 1 SEL
2146 04:40:37.615877 # ok 212 name.LCALTA.30
2147 04:40:37.620885 # ok 213 write_default.LCALTA.30
2148 04:40:37.621378 # ok 214 write_valid.LCALTA.30
2149 04:40:37.626397 # ok 215 write_invalid.LCALTA.30
2150 04:40:37.631969 # ok 216 event_missing.LCALTA.30
2151 04:40:37.632488 # ok 217 event_spurious.LCALTA.30
2152 04:40:37.637519 # ok 218 get_value.LCALTA.29
2153 04:40:37.638009 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2154 04:40:37.643044 # ok 219 name.LCALTA.29
2155 04:40:37.643531 # ok 220 write_default.LCALTA.29
2156 04:40:37.648668 # ok 221 write_valid.LCALTA.29
2157 04:40:37.649158 # ok 222 write_invalid.LCALTA.29
2158 04:40:37.654133 # ok 223 event_missing.LCALTA.29
2159 04:40:37.654619 # ok 224 event_spurious.LCALTA.29
2160 04:40:37.659706 # ok 225 get_value.LCALTA.28
2161 04:40:37.660220 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2162 04:40:37.665224 # ok 226 name.LCALTA.28
2163 04:40:37.665709 # ok 227 write_default.LCALTA.28
2164 04:40:37.670770 # ok 228 write_valid.LCALTA.28
2165 04:40:37.671258 # ok 229 write_invalid.LCALTA.28
2166 04:40:37.676317 # ok 230 event_missing.LCALTA.28
2167 04:40:37.676802 # ok 231 event_spurious.LCALTA.28
2168 04:40:37.681892 # ok 232 get_value.LCALTA.27
2169 04:40:37.682375 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2170 04:40:37.687412 # ok 233 name.LCALTA.27
2171 04:40:37.687908 # ok 234 write_default.LCALTA.27
2172 04:40:37.692958 # ok 235 write_valid.LCALTA.27
2173 04:40:37.693444 # ok 236 write_invalid.LCALTA.27
2174 04:40:37.698517 # ok 237 event_missing.LCALTA.27
2175 04:40:37.699003 # ok 238 event_spurious.LCALTA.27
2176 04:40:37.704078 # ok 239 get_value.LCALTA.26
2177 04:40:37.704567 # # LCALTA.26 ELD
2178 04:40:37.709665 # ok 240 name.LCALTA.26
2179 04:40:37.710150 # # ELD is not writeable
2180 04:40:37.715158 # ok 241 # SKIP write_default.LCALTA.26
2181 04:40:37.715647 # # ELD is not writeable
2182 04:40:37.720710 # ok 242 # SKIP write_valid.LCALTA.26
2183 04:40:37.721201 # # ELD is not writeable
2184 04:40:37.726254 # ok 243 # SKIP write_invalid.LCALTA.26
2185 04:40:37.726735 # ok 244 event_missing.LCALTA.26
2186 04:40:37.731775 # ok 245 event_spurious.LCALTA.26
2187 04:40:37.732292 # ok 246 get_value.LCALTA.25
2188 04:40:37.737321 # # LCALTA.25 IEC958 Playback Default
2189 04:40:37.737807 # ok 247 name.LCALTA.25
2190 04:40:37.742878 # ok 248 write_default.LCALTA.25
2191 04:40:37.743378 # ok 249 # SKIP write_valid.LCALTA.25
2192 04:40:37.748427 # ok 250 # SKIP write_invalid.LCALTA.25
2193 04:40:37.753977 # ok 251 event_missing.LCALTA.25
2194 04:40:37.754465 # ok 252 event_spurious.LCALTA.25
2195 04:40:37.759540 # ok 253 get_value.LCALTA.24
2196 04:40:37.760059 # # LCALTA.24 IEC958 Playback Mask
2197 04:40:37.760516 # ok 254 name.LCALTA.24
2198 04:40:37.765073 # # IEC958 Playback Mask is not writeable
2199 04:40:37.770665 # ok 255 # SKIP write_default.LCALTA.24
2200 04:40:37.771152 # # IEC958 Playback Mask is not writeable
2201 04:40:37.776205 # ok 256 # SKIP write_valid.LCALTA.24
2202 04:40:37.781729 # # IEC958 Playback Mask is not writeable
2203 04:40:37.782213 # ok 257 # SKIP write_invalid.LCALTA.24
2204 04:40:37.787248 # ok 258 event_missing.LCALTA.24
2205 04:40:37.787739 # ok 259 event_spurious.LCALTA.24
2206 04:40:37.792793 # ok 260 get_value.LCALTA.23
2207 04:40:37.793283 # # LCALTA.23 Playback Channel Map
2208 04:40:37.798337 # ok 261 name.LCALTA.23
2209 04:40:37.803922 # # Playback Channel Map is not writeable
2210 04:40:37.804435 # ok 262 # SKIP write_default.LCALTA.23
2211 04:40:37.809445 # # Playback Channel Map is not writeable
2212 04:40:37.809928 # ok 263 # SKIP write_valid.LCALTA.23
2213 04:40:37.814997 # # Playback Channel Map is not writeable
2214 04:40:37.820544 # ok 264 # SKIP write_invalid.LCALTA.23
2215 04:40:37.821033 # ok 265 event_missing.LCALTA.23
2216 04:40:37.826070 # ok 266 event_spurious.LCALTA.23
2217 04:40:37.826555 # ok 267 get_value.LCALTA.22
2218 04:40:37.831695 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2219 04:40:37.832215 # ok 268 name.LCALTA.22
2220 04:40:37.837175 # ok 269 write_default.LCALTA.22
2221 04:40:37.837663 # ok 270 write_valid.LCALTA.22
2222 04:40:37.842730 # ok 271 write_invalid.LCALTA.22
2223 04:40:37.843218 # ok 272 event_missing.LCALTA.22
2224 04:40:37.848283 # ok 273 event_spurious.LCALTA.22
2225 04:40:37.853801 # ok 274 get_value.LCALTA.21
2226 04:40:37.854286 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2227 04:40:37.854740 # ok 275 name.LCALTA.21
2228 04:40:37.859369 # ok 276 write_default.LCALTA.21
2229 04:40:37.864915 # ok 277 write_valid.LCALTA.21
2230 04:40:37.865402 # ok 278 write_invalid.LCALTA.21
2231 04:40:37.870453 # ok 279 event_missing.LCALTA.21
2232 04:40:37.870933 # ok 280 event_spurious.LCALTA.21
2233 04:40:37.876031 # ok 281 get_value.LCALTA.20
2234 04:40:37.876523 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2235 04:40:37.881554 # ok 282 name.LCALTA.20
2236 04:40:37.882040 # ok 283 write_default.LCALTA.20
2237 04:40:37.887101 # ok 284 write_valid.LCALTA.20
2238 04:40:37.887588 # ok 285 write_invalid.LCALTA.20
2239 04:40:37.892674 # ok 286 event_missing.LCALTA.20
2240 04:40:37.893162 # ok 287 event_spurious.LCALTA.20
2241 04:40:37.898180 # ok 288 get_value.LCALTA.19
2242 04:40:37.898665 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2243 04:40:37.903734 # ok 289 name.LCALTA.19
2244 04:40:37.904246 # ok 290 write_default.LCALTA.19
2245 04:40:37.909275 # ok 291 write_valid.LCALTA.19
2246 04:40:37.909764 # ok 292 write_invalid.LCALTA.19
2247 04:40:37.914831 # ok 293 event_missing.LCALTA.19
2248 04:40:37.915316 # ok 294 event_spurious.LCALTA.19
2249 04:40:37.920369 # ok 295 get_value.LCALTA.18
2250 04:40:37.920864 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2251 04:40:37.925923 # ok 296 name.LCALTA.18
2252 04:40:37.926407 # ok 297 write_default.LCALTA.18
2253 04:40:37.931471 # ok 298 write_valid.LCALTA.18
2254 04:40:37.931971 # ok 299 write_invalid.LCALTA.18
2255 04:40:37.937016 # ok 300 event_missing.LCALTA.18
2256 04:40:37.937503 # ok 301 event_spurious.LCALTA.18
2257 04:40:37.942557 # ok 302 get_value.LCALTA.17
2258 04:40:37.948111 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2259 04:40:37.948603 # ok 303 name.LCALTA.17
2260 04:40:37.949059 # ok 304 write_default.LCALTA.17
2261 04:40:37.953729 # ok 305 write_valid.LCALTA.17
2262 04:40:37.959204 # ok 306 write_invalid.LCALTA.17
2263 04:40:37.959696 # ok 307 event_missing.LCALTA.17
2264 04:40:37.964749 # ok 308 event_spurious.LCALTA.17
2265 04:40:37.965236 # ok 309 get_value.LCALTA.16
2266 04:40:37.970296 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2267 04:40:37.970784 # ok 310 name.LCALTA.16
2268 04:40:37.975837 # ok 311 write_default.LCALTA.16
2269 04:40:37.976355 # ok 312 write_valid.LCALTA.16
2270 04:40:37.981409 # ok 313 write_invalid.LCALTA.16
2271 04:40:37.981896 # ok 314 event_missing.LCALTA.16
2272 04:40:37.986960 # ok 315 event_spurious.LCALTA.16
2273 04:40:37.987440 # ok 316 get_value.LCALTA.15
2274 04:40:37.992473 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2275 04:40:37.992960 # ok 317 name.LCALTA.15
2276 04:40:37.998034 # ok 318 write_default.LCALTA.15
2277 04:40:37.998525 # ok 319 write_valid.LCALTA.15
2278 04:40:38.003567 # ok 320 write_invalid.LCALTA.15
2279 04:40:38.004091 # ok 321 event_missing.LCALTA.15
2280 04:40:38.009117 # ok 322 event_spurious.LCALTA.15
2281 04:40:38.009605 # ok 323 get_value.LCALTA.14
2282 04:40:38.014702 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2283 04:40:38.015189 # ok 324 name.LCALTA.14
2284 04:40:38.020243 # ok 325 write_default.LCALTA.14
2285 04:40:38.020747 # ok 326 write_valid.LCALTA.14
2286 04:40:38.025765 # ok 327 write_invalid.LCALTA.14
2287 04:40:38.026268 # ok 328 event_missing.LCALTA.14
2288 04:40:38.031362 # ok 329 event_spurious.LCALTA.14
2289 04:40:38.031925 # ok 330 get_value.LCALTA.13
2290 04:40:38.036953 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2291 04:40:38.037559 # ok 331 name.LCALTA.13
2292 04:40:38.042394 # ok 332 write_default.LCALTA.13
2293 04:40:38.042906 # ok 333 write_valid.LCALTA.13
2294 04:40:38.047946 # ok 334 write_invalid.LCALTA.13
2295 04:40:38.048471 # ok 335 event_missing.LCALTA.13
2296 04:40:38.053494 # ok 336 event_spurious.LCALTA.13
2297 04:40:38.054001 # ok 337 get_value.LCALTA.12
2298 04:40:38.059052 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2299 04:40:38.059553 # ok 338 name.LCALTA.12
2300 04:40:38.064704 # ok 339 write_default.LCALTA.12
2301 04:40:38.070134 # ok 340 write_valid.LCALTA.12
2302 04:40:38.070632 # ok 341 write_invalid.LCALTA.12
2303 04:40:38.075704 # ok 342 event_missing.LCALTA.12
2304 04:40:38.076241 # ok 343 event_spurious.LCALTA.12
2305 04:40:38.081223 # ok 344 get_value.LCALTA.11
2306 04:40:38.081715 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2307 04:40:38.086782 # ok 345 name.LCALTA.11
2308 04:40:38.087271 # ok 346 write_default.LCALTA.11
2309 04:40:38.092320 # ok 347 write_valid.LCALTA.11
2310 04:40:38.092809 # ok 348 write_invalid.LCALTA.11
2311 04:40:38.097882 # ok 349 event_missing.LCALTA.11
2312 04:40:38.098371 # ok 350 event_spurious.LCALTA.11
2313 04:40:38.103414 # ok 351 get_value.LCALTA.10
2314 04:40:38.103901 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2315 04:40:38.108952 # ok 352 name.LCALTA.10
2316 04:40:38.109439 # ok 353 write_default.LCALTA.10
2317 04:40:38.114603 # ok 354 write_valid.LCALTA.10
2318 04:40:38.115077 # ok 355 write_invalid.LCALTA.10
2319 04:40:38.120074 # ok 356 event_missing.LCALTA.10
2320 04:40:38.120554 # ok 357 event_spurious.LCALTA.10
2321 04:40:38.125712 # ok 358 get_value.LCALTA.9
2322 04:40:38.126189 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2323 04:40:38.131130 # ok 359 name.LCALTA.9
2324 04:40:38.131598 # ok 360 write_default.LCALTA.9
2325 04:40:38.136713 # ok 361 write_valid.LCALTA.9
2326 04:40:38.137181 # ok 362 write_invalid.LCALTA.9
2327 04:40:38.142241 # ok 363 event_missing.LCALTA.9
2328 04:40:38.142717 # ok 364 event_spurious.LCALTA.9
2329 04:40:38.147783 # ok 365 get_value.LCALTA.8
2330 04:40:38.148285 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2331 04:40:38.153319 # ok 366 name.LCALTA.8
2332 04:40:38.153788 # ok 367 write_default.LCALTA.8
2333 04:40:38.158857 # ok 368 write_valid.LCALTA.8
2334 04:40:38.159326 # ok 369 write_invalid.LCALTA.8
2335 04:40:38.164394 # ok 370 event_missing.LCALTA.8
2336 04:40:38.164863 # ok 371 event_spurious.LCALTA.8
2337 04:40:38.169986 # ok 372 get_value.LCALTA.7
2338 04:40:38.170469 # # LCALTA.7 ACODEC Unmute Ramp Switch
2339 04:40:38.175481 # ok 373 name.LCALTA.7
2340 04:40:38.175944 # ok 374 write_default.LCALTA.7
2341 04:40:38.181102 # ok 375 write_valid.LCALTA.7
2342 04:40:38.181581 # ok 376 write_invalid.LCALTA.7
2343 04:40:38.186719 # ok 377 event_missing.LCALTA.7
2344 04:40:38.187194 # ok 378 event_spurious.LCALTA.7
2345 04:40:38.192184 # ok 379 get_value.LCALTA.6
2346 04:40:38.192663 # # LCALTA.6 ACODEC Mute Ramp Switch
2347 04:40:38.197718 # ok 380 name.LCALTA.6
2348 04:40:38.198189 # ok 381 write_default.LCALTA.6
2349 04:40:38.203254 # ok 382 write_valid.LCALTA.6
2350 04:40:38.203724 # ok 383 write_invalid.LCALTA.6
2351 04:40:38.208813 # ok 384 event_missing.LCALTA.6
2352 04:40:38.209300 # ok 385 event_spurious.LCALTA.6
2353 04:40:38.214360 # ok 386 get_value.LCALTA.5
2354 04:40:38.214838 # # LCALTA.5 ACODEC Volume Ramp Switch
2355 04:40:38.219893 # ok 387 name.LCALTA.5
2356 04:40:38.220396 # ok 388 write_default.LCALTA.5
2357 04:40:38.225423 # ok 389 write_valid.LCALTA.5
2358 04:40:38.225900 # ok 390 write_invalid.LCALTA.5
2359 04:40:38.230997 # ok 391 event_missing.LCALTA.5
2360 04:40:38.231467 # ok 392 event_spurious.LCALTA.5
2361 04:40:38.236632 # ok 393 get_value.LCALTA.4
2362 04:40:38.237107 # # LCALTA.4 ACODEC Ramp Rate
2363 04:40:38.242089 # ok 394 name.LCALTA.4
2364 04:40:38.242561 # ok 395 write_default.LCALTA.4
2365 04:40:38.247721 # ok 396 write_valid.LCALTA.4
2366 04:40:38.248232 # ok 397 write_invalid.LCALTA.4
2367 04:40:38.253160 # ok 398 event_missing.LCALTA.4
2368 04:40:38.253630 # ok 399 event_spurious.LCALTA.4
2369 04:40:38.258736 # ok 400 get_value.LCALTA.3
2370 04:40:38.259207 # # LCALTA.3 ACODEC Playback Volume
2371 04:40:38.264261 # ok 401 name.LCALTA.3
2372 04:40:38.264736 # ok 402 write_default.LCALTA.3
2373 04:40:38.269816 # ok 403 write_valid.LCALTA.3
2374 04:40:38.270287 # ok 404 write_invalid.LCALTA.3
2375 04:40:38.275343 # ok 405 event_missing.LCALTA.3
2376 04:40:38.275813 # ok 406 event_spurious.LCALTA.3
2377 04:40:38.280897 # ok 407 get_value.LCALTA.2
2378 04:40:38.281365 # # LCALTA.2 ACODEC Playback Switch
2379 04:40:38.286467 # ok 408 name.LCALTA.2
2380 04:40:38.286937 # ok 409 write_default.LCALTA.2
2381 04:40:38.292025 # ok 410 write_valid.LCALTA.2
2382 04:40:38.292494 # ok 411 write_invalid.LCALTA.2
2383 04:40:38.297622 # ok 412 event_missing.LCALTA.2
2384 04:40:38.298137 # ok 413 event_spurious.LCALTA.2
2385 04:40:38.303094 # ok 414 get_value.LCALTA.1
2386 04:40:38.303577 # # LCALTA.1 ACODEC Playback Channel Mode
2387 04:40:38.308744 # ok 415 name.LCALTA.1
2388 04:40:38.309222 # ok 416 write_default.LCALTA.1
2389 04:40:38.314180 # ok 417 write_valid.LCALTA.1
2390 04:40:38.314653 # ok 418 write_invalid.LCALTA.1
2391 04:40:38.319730 # ok 419 event_missing.LCALTA.1
2392 04:40:38.320234 # ok 420 event_spurious.LCALTA.1
2393 04:40:38.325365 # ok 421 get_value.LCALTA.0
2394 04:40:38.325852 # # LCALTA.0 TOACODEC Lane Select
2395 04:40:38.330805 # ok 422 name.LCALTA.0
2396 04:40:38.331276 # ok 423 write_default.LCALTA.0
2397 04:40:38.336361 # ok 424 write_valid.LCALTA.0
2398 04:40:38.336830 # ok 425 write_invalid.LCALTA.0
2399 04:40:38.341918 # ok 426 event_missing.LCALTA.0
2400 04:40:38.342383 # ok 427 event_spurious.LCALTA.0
2401 04:40:38.347460 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2402 04:40:38.353005 ok 1 selftests: alsa: mixer-test
2403 04:40:38.353489 # timeout set to 45
2404 04:40:38.353925 # selftests: alsa: pcm-test
2405 04:40:38.358609 # TAP version 13
2406 04:40:38.359081 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2407 04:40:38.364092 # # LCALTA.0 - fe.dai-link-0 (*)
2408 04:40:38.364555 # # LCALTA.0 - fe.dai-link-1 (*)
2409 04:40:38.369735 # # LCALTA.0 - fe.dai-link-2 (*)
2410 04:40:38.370209 # # LCALTA.0 - fe.dai-link-3 (*)
2411 04:40:38.375190 # # LCALTA.0 - fe.dai-link-4 (*)
2412 04:40:38.375660 # # LCALTA.0 - fe.dai-link-5 (*)
2413 04:40:38.380761 # 1..42
2414 04:40:38.386304 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2415 04:40:38.386786 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2416 04:40:38.391845 # # snd_pcm_hw_params: Invalid argument
2417 04:40:38.397362 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2418 04:40:38.403054 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2419 04:40:38.403543 # # snd_pcm_hw_params: Invalid argument
2420 04:40:38.408492 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2421 04:40:38.414116 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2422 04:40:38.419736 # # snd_pcm_hw_params: Invalid argument
2423 04:40:38.425119 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2424 04:40:38.430759 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2425 04:40:38.431240 # # snd_pcm_hw_params: Invalid argument
2426 04:40:38.436274 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2427 04:40:38.441794 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2428 04:40:38.447301 # # snd_pcm_hw_params: Invalid argument
2429 04:40:38.452861 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2430 04:40:38.458385 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2431 04:40:38.458862 # # snd_pcm_hw_params: Invalid argument
2432 04:40:38.463960 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2433 04:40:38.469498 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2434 04:40:38.475012 # # snd_pcm_hw_params: Invalid argument
2435 04:40:38.480660 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2436 04:40:38.481134 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2437 04:40:38.486114 # # snd_pcm_hw_params: Invalid argument
2438 04:40:38.491724 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2439 04:40:38.497238 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2440 04:40:38.497712 # # snd_pcm_hw_params: Invalid argument
2441 04:40:38.508322 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2442 04:40:38.508820 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2443 04:40:38.513866 # # snd_pcm_hw_params: Invalid argument
2444 04:40:38.519412 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2445 04:40:38.524976 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2446 04:40:38.525454 # # snd_pcm_hw_params: Invalid argument
2447 04:40:38.530526 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2448 04:40:38.536094 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2449 04:40:38.541637 # # snd_pcm_hw_params: Invalid argument
2450 04:40:38.547151 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2451 04:40:38.552787 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2452 04:40:38.553270 # # snd_pcm_hw_params: Invalid argument
2453 04:40:38.558248 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2454 04:40:38.563834 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2455 04:40:38.569340 # # snd_pcm_hw_params: Invalid argument
2456 04:40:38.574884 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2457 04:40:38.580431 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2458 04:40:38.580909 # # snd_pcm_hw_params: Invalid argument
2459 04:40:38.585963 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2460 04:40:38.591536 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2461 04:40:38.597061 # # snd_pcm_hw_params: Invalid argument
2462 04:40:38.602641 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2463 04:40:38.603109 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2464 04:40:38.608201 # # snd_pcm_hw_params: Invalid argument
2465 04:40:38.613810 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2466 04:40:38.619263 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2467 04:40:38.624864 # # snd_pcm_hw_params: Invalid argument
2468 04:40:38.630353 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2469 04:40:38.630869 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2470 04:40:38.635932 # # snd_pcm_hw_params: Invalid argument
2471 04:40:38.641471 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2472 04:40:38.647016 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2473 04:40:38.652537 # # snd_pcm_hw_params: Invalid argument
2474 04:40:38.658095 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2475 04:40:38.658580 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2476 04:40:38.663672 # # snd_pcm_hw_params: Invalid argument
2477 04:40:38.669187 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2478 04:40:38.674841 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2479 04:40:38.675330 # # snd_pcm_hw_params: Invalid argument
2480 04:40:38.680308 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2481 04:40:38.685852 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2482 04:40:38.691351 # # snd_pcm_hw_params: Invalid argument
2483 04:40:38.696916 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2484 04:40:38.702460 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2485 04:40:38.702942 # # snd_pcm_hw_params: Invalid argument
2486 04:40:38.708030 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2487 04:40:38.713554 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2488 04:40:38.719068 # # snd_pcm_hw_params: Invalid argument
2489 04:40:38.724670 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2490 04:40:38.730177 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2491 04:40:38.730665 # # snd_pcm_hw_params: Invalid argument
2492 04:40:38.735806 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2493 04:40:38.741293 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2494 04:40:38.746851 # # snd_pcm_hw_params: Invalid argument
2495 04:40:38.752370 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2496 04:40:38.757931 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2497 04:40:38.758412 # # snd_pcm_hw_params: Invalid argument
2498 04:40:38.763471 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2499 04:40:38.769017 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2500 04:40:38.774553 # # snd_pcm_hw_params: Invalid argument
2501 04:40:38.780129 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2502 04:40:38.785669 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2503 04:40:38.786151 # # snd_pcm_hw_params: Invalid argument
2504 04:40:38.791210 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2505 04:40:38.796823 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2506 04:40:38.802303 # # snd_pcm_hw_params: Invalid argument
2507 04:40:38.807866 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2508 04:40:38.813395 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2509 04:40:38.813883 # # snd_pcm_hw_params: Invalid argument
2510 04:40:38.818933 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2511 04:40:38.824469 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2512 04:40:38.830024 # # snd_pcm_hw_params: Invalid argument
2513 04:40:38.835601 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2514 04:40:38.841133 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2515 04:40:38.841618 # # snd_pcm_hw_params: Invalid argument
2516 04:40:38.846685 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2517 04:40:38.852228 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2518 04:40:38.857828 # # snd_pcm_hw_params: Invalid argument
2519 04:40:38.863302 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2520 04:40:38.868866 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2521 04:40:38.869350 # # snd_pcm_hw_params: Invalid argument
2522 04:40:38.874396 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2523 04:40:38.879950 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2524 04:40:38.885482 # # snd_pcm_hw_params: Invalid argument
2525 04:40:38.891050 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2526 04:40:38.896589 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2527 04:40:38.897074 # # snd_pcm_hw_params: Invalid argument
2528 04:40:38.902159 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2529 04:40:38.907693 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2530 04:40:38.913244 # # snd_pcm_hw_params: Invalid argument
2531 04:40:38.918840 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2532 04:40:38.924317 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2533 04:40:38.924802 # # snd_pcm_hw_params: Invalid argument
2534 04:40:38.929881 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2535 04:40:38.935412 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2536 04:40:38.940959 # # snd_pcm_hw_params: Invalid argument
2537 04:40:38.946502 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2538 04:40:38.952057 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2539 04:40:38.952549 # # snd_pcm_hw_params: Invalid argument
2540 04:40:38.957578 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2541 04:40:38.963128 ok 2 selftests: alsa: pcm-test
2542 04:40:38.963615 # timeout set to 45
2543 04:40:38.968758 # selftests: alsa: test-pcmtest-driver
2544 04:40:38.969242 # TAP version 13
2545 04:40:38.969692 # 1..5
2546 04:40:38.974240 # # Starting 5 tests from 1 test cases.
2547 04:40:38.974722 # # RUN pcmtest.playback ...
2548 04:40:38.979898 # # SKIP Can't read patterns. Probably, module isn't loaded
2549 04:40:38.985336 # # OK pcmtest.playback
2550 04:40:38.990964 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2551 04:40:38.996443 # # RUN pcmtest.capture ...
2552 04:40:39.002218 # # SKIP Can't read patterns. Probably, module isn't loaded
2553 04:40:39.007499 # # OK pcmtest.capture
2554 04:40:39.013095 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2555 04:40:39.018615 # # RUN pcmtest.ni_capture ...
2556 04:40:39.024187 # # SKIP Can't read patterns. Probably, module isn't loaded
2557 04:40:39.024711 # # OK pcmtest.ni_capture
2558 04:40:39.035299 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2559 04:40:39.035818 # # RUN pcmtest.ni_playback ...
2560 04:40:39.040853 # # SKIP Can't read patterns. Probably, module isn't loaded
2561 04:40:39.046390 # # OK pcmtest.ni_playback
2562 04:40:39.051922 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2563 04:40:39.057492 # # RUN pcmtest.reset_ioctl ...
2564 04:40:39.063019 # # SKIP Can't read patterns. Probably, module isn't loaded
2565 04:40:39.068571 # # OK pcmtest.reset_ioctl
2566 04:40:39.074117 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2567 04:40:39.079602 # # PASSED: 5 / 5 tests passed.
2568 04:40:39.085173 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2569 04:40:39.085666 ok 3 selftests: alsa: test-pcmtest-driver
2570 04:40:39.090759 # timeout set to 45
2571 04:40:39.091241 # selftests: alsa: utimer-test
2572 04:40:39.091696 # TAP version 13
2573 04:40:39.092196 # 1..2
2574 04:40:39.096318 # # Starting 2 tests from 2 test cases.
2575 04:40:39.101878 # # RUN global.wrong_timers_test ...
2576 04:40:39.107353 # # OK global.wrong_timers_test
2577 04:40:39.107833 # ok 1 global.wrong_timers_test
2578 04:40:39.112923 # # RUN timer_f.utimer ...
2579 04:40:39.118454 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2580 04:40:39.124025 # # utimer: Test terminated by assertion
2581 04:40:39.129529 # # FAIL timer_f.utimer
2582 04:40:39.130015 # not ok 2 timer_f.utimer
2583 04:40:39.135090 # # FAILED: 1 / 2 tests passed.
2584 04:40:39.142511 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2585 04:40:39.142998 not ok 4 selftests: alsa: utimer-test # exit=1
2586 04:40:39.632561 alsa_mixer-test_get_value_LCALTA_60 pass
2587 04:40:39.637916 alsa_mixer-test_name_LCALTA_60 pass
2588 04:40:39.638423 alsa_mixer-test_write_default_LCALTA_60 pass
2589 04:40:39.643398 alsa_mixer-test_write_valid_LCALTA_60 pass
2590 04:40:39.648951 alsa_mixer-test_write_invalid_LCALTA_60 pass
2591 04:40:39.654460 alsa_mixer-test_event_missing_LCALTA_60 pass
2592 04:40:39.654948 alsa_mixer-test_event_spurious_LCALTA_60 pass
2593 04:40:39.660063 alsa_mixer-test_get_value_LCALTA_59 pass
2594 04:40:39.665557 alsa_mixer-test_name_LCALTA_59 pass
2595 04:40:39.666038 alsa_mixer-test_write_default_LCALTA_59 pass
2596 04:40:39.671110 alsa_mixer-test_write_valid_LCALTA_59 pass
2597 04:40:39.676616 alsa_mixer-test_write_invalid_LCALTA_59 pass
2598 04:40:39.676894 alsa_mixer-test_event_missing_LCALTA_59 pass
2599 04:40:39.682248 alsa_mixer-test_event_spurious_LCALTA_59 pass
2600 04:40:39.687771 alsa_mixer-test_get_value_LCALTA_58 pass
2601 04:40:39.688305 alsa_mixer-test_name_LCALTA_58 pass
2602 04:40:39.693290 alsa_mixer-test_write_default_LCALTA_58 pass
2603 04:40:39.698922 alsa_mixer-test_write_valid_LCALTA_58 pass
2604 04:40:39.699421 alsa_mixer-test_write_invalid_LCALTA_58 pass
2605 04:40:39.704401 alsa_mixer-test_event_missing_LCALTA_58 pass
2606 04:40:39.709962 alsa_mixer-test_event_spurious_LCALTA_58 pass
2607 04:40:39.715484 alsa_mixer-test_get_value_LCALTA_57 pass
2608 04:40:39.715961 alsa_mixer-test_name_LCALTA_57 pass
2609 04:40:39.721046 alsa_mixer-test_write_default_LCALTA_57 pass
2610 04:40:39.726576 alsa_mixer-test_write_valid_LCALTA_57 pass
2611 04:40:39.727055 alsa_mixer-test_write_invalid_LCALTA_57 pass
2612 04:40:39.732176 alsa_mixer-test_event_missing_LCALTA_57 pass
2613 04:40:39.737668 alsa_mixer-test_event_spurious_LCALTA_57 pass
2614 04:40:39.738147 alsa_mixer-test_get_value_LCALTA_56 pass
2615 04:40:39.743195 alsa_mixer-test_name_LCALTA_56 pass
2616 04:40:39.748789 alsa_mixer-test_write_default_LCALTA_56 pass
2617 04:40:39.749291 alsa_mixer-test_write_valid_LCALTA_56 pass
2618 04:40:39.754290 alsa_mixer-test_write_invalid_LCALTA_56 pass
2619 04:40:39.759923 alsa_mixer-test_event_missing_LCALTA_56 pass
2620 04:40:39.765417 alsa_mixer-test_event_spurious_LCALTA_56 pass
2621 04:40:39.765902 alsa_mixer-test_get_value_LCALTA_55 pass
2622 04:40:39.770966 alsa_mixer-test_name_LCALTA_55 pass
2623 04:40:39.776493 alsa_mixer-test_write_default_LCALTA_55 pass
2624 04:40:39.776971 alsa_mixer-test_write_valid_LCALTA_55 pass
2625 04:40:39.782057 alsa_mixer-test_write_invalid_LCALTA_55 pass
2626 04:40:39.787629 alsa_mixer-test_event_missing_LCALTA_55 pass
2627 04:40:39.788202 alsa_mixer-test_event_spurious_LCALTA_55 pass
2628 04:40:39.793134 alsa_mixer-test_get_value_LCALTA_54 pass
2629 04:40:39.798674 alsa_mixer-test_name_LCALTA_54 pass
2630 04:40:39.799156 alsa_mixer-test_write_default_LCALTA_54 pass
2631 04:40:39.804224 alsa_mixer-test_write_valid_LCALTA_54 pass
2632 04:40:39.809795 alsa_mixer-test_write_invalid_LCALTA_54 pass
2633 04:40:39.810278 alsa_mixer-test_event_missing_LCALTA_54 pass
2634 04:40:39.815315 alsa_mixer-test_event_spurious_LCALTA_54 pass
2635 04:40:39.820926 alsa_mixer-test_get_value_LCALTA_53 pass
2636 04:40:39.821405 alsa_mixer-test_name_LCALTA_53 pass
2637 04:40:39.826418 alsa_mixer-test_write_default_LCALTA_53 pass
2638 04:40:39.831976 alsa_mixer-test_write_valid_LCALTA_53 pass
2639 04:40:39.837511 alsa_mixer-test_write_invalid_LCALTA_53 pass
2640 04:40:39.837991 alsa_mixer-test_event_missing_LCALTA_53 pass
2641 04:40:39.843024 alsa_mixer-test_event_spurious_LCALTA_53 pass
2642 04:40:39.848618 alsa_mixer-test_get_value_LCALTA_52 pass
2643 04:40:39.849096 alsa_mixer-test_name_LCALTA_52 pass
2644 04:40:39.854161 alsa_mixer-test_write_default_LCALTA_52 pass
2645 04:40:39.859699 alsa_mixer-test_write_valid_LCALTA_52 pass
2646 04:40:39.860219 alsa_mixer-test_write_invalid_LCALTA_52 pass
2647 04:40:39.865249 alsa_mixer-test_event_missing_LCALTA_52 pass
2648 04:40:39.870795 alsa_mixer-test_event_spurious_LCALTA_52 pass
2649 04:40:39.871267 alsa_mixer-test_get_value_LCALTA_51 pass
2650 04:40:39.876353 alsa_mixer-test_name_LCALTA_51 pass
2651 04:40:39.881930 alsa_mixer-test_write_default_LCALTA_51 pass
2652 04:40:39.882406 alsa_mixer-test_write_valid_LCALTA_51 pass
2653 04:40:39.887432 alsa_mixer-test_write_invalid_LCALTA_51 pass
2654 04:40:39.892982 alsa_mixer-test_event_missing_LCALTA_51 pass
2655 04:40:39.898533 alsa_mixer-test_event_spurious_LCALTA_51 pass
2656 04:40:39.899050 alsa_mixer-test_get_value_LCALTA_50 pass
2657 04:40:39.904084 alsa_mixer-test_name_LCALTA_50 pass
2658 04:40:39.909627 alsa_mixer-test_write_default_LCALTA_50 pass
2659 04:40:39.910117 alsa_mixer-test_write_valid_LCALTA_50 pass
2660 04:40:39.915554 alsa_mixer-test_write_invalid_LCALTA_50 pass
2661 04:40:39.920677 alsa_mixer-test_event_missing_LCALTA_50 pass
2662 04:40:39.921166 alsa_mixer-test_event_spurious_LCALTA_50 pass
2663 04:40:39.926262 alsa_mixer-test_get_value_LCALTA_49 pass
2664 04:40:39.931796 alsa_mixer-test_name_LCALTA_49 pass
2665 04:40:39.932311 alsa_mixer-test_write_default_LCALTA_49 pass
2666 04:40:39.937366 alsa_mixer-test_write_valid_LCALTA_49 pass
2667 04:40:39.942947 alsa_mixer-test_write_invalid_LCALTA_49 pass
2668 04:40:39.948436 alsa_mixer-test_event_missing_LCALTA_49 pass
2669 04:40:39.948926 alsa_mixer-test_event_spurious_LCALTA_49 pass
2670 04:40:39.953988 alsa_mixer-test_get_value_LCALTA_48 pass
2671 04:40:39.954473 alsa_mixer-test_name_LCALTA_48 pass
2672 04:40:39.959533 alsa_mixer-test_write_default_LCALTA_48 pass
2673 04:40:39.965071 alsa_mixer-test_write_valid_LCALTA_48 pass
2674 04:40:39.970607 alsa_mixer-test_write_invalid_LCALTA_48 pass
2675 04:40:39.971091 alsa_mixer-test_event_missing_LCALTA_48 pass
2676 04:40:39.976202 alsa_mixer-test_event_spurious_LCALTA_48 pass
2677 04:40:39.981740 alsa_mixer-test_get_value_LCALTA_47 pass
2678 04:40:39.982215 alsa_mixer-test_name_LCALTA_47 pass
2679 04:40:39.987275 alsa_mixer-test_write_default_LCALTA_47 pass
2680 04:40:39.992820 alsa_mixer-test_write_valid_LCALTA_47 pass
2681 04:40:39.993306 alsa_mixer-test_write_invalid_LCALTA_47 pass
2682 04:40:39.998352 alsa_mixer-test_event_missing_LCALTA_47 pass
2683 04:40:40.003955 alsa_mixer-test_event_spurious_LCALTA_47 pass
2684 04:40:40.009448 alsa_mixer-test_get_value_LCALTA_46 pass
2685 04:40:40.009923 alsa_mixer-test_name_LCALTA_46 pass
2686 04:40:40.014990 alsa_mixer-test_write_default_LCALTA_46 pass
2687 04:40:40.020568 alsa_mixer-test_write_valid_LCALTA_46 pass
2688 04:40:40.021064 alsa_mixer-test_write_invalid_LCALTA_46 pass
2689 04:40:40.026093 alsa_mixer-test_event_missing_LCALTA_46 pass
2690 04:40:40.031633 alsa_mixer-test_event_spurious_LCALTA_46 pass
2691 04:40:40.032145 alsa_mixer-test_get_value_LCALTA_45 pass
2692 04:40:40.037213 alsa_mixer-test_name_LCALTA_45 pass
2693 04:40:40.042743 alsa_mixer-test_write_default_LCALTA_45 pass
2694 04:40:40.043223 alsa_mixer-test_write_valid_LCALTA_45 pass
2695 04:40:40.048281 alsa_mixer-test_write_invalid_LCALTA_45 pass
2696 04:40:40.053826 alsa_mixer-test_event_missing_LCALTA_45 pass
2697 04:40:40.054318 alsa_mixer-test_event_spurious_LCALTA_45 pass
2698 04:40:40.059368 alsa_mixer-test_get_value_LCALTA_44 pass
2699 04:40:40.064963 alsa_mixer-test_name_LCALTA_44 pass
2700 04:40:40.065444 alsa_mixer-test_write_default_LCALTA_44 pass
2701 04:40:40.070466 alsa_mixer-test_write_valid_LCALTA_44 pass
2702 04:40:40.076047 alsa_mixer-test_write_invalid_LCALTA_44 pass
2703 04:40:40.081582 alsa_mixer-test_event_missing_LCALTA_44 pass
2704 04:40:40.082064 alsa_mixer-test_event_spurious_LCALTA_44 pass
2705 04:40:40.087088 alsa_mixer-test_get_value_LCALTA_43 pass
2706 04:40:40.092657 alsa_mixer-test_name_LCALTA_43 pass
2707 04:40:40.093133 alsa_mixer-test_write_default_LCALTA_43 pass
2708 04:40:40.098210 alsa_mixer-test_write_valid_LCALTA_43 pass
2709 04:40:40.103751 alsa_mixer-test_write_invalid_LCALTA_43 pass
2710 04:40:40.104256 alsa_mixer-test_event_missing_LCALTA_43 pass
2711 04:40:40.109289 alsa_mixer-test_event_spurious_LCALTA_43 pass
2712 04:40:40.115008 alsa_mixer-test_get_value_LCALTA_42 pass
2713 04:40:40.115486 alsa_mixer-test_name_LCALTA_42 pass
2714 04:40:40.120392 alsa_mixer-test_write_default_LCALTA_42 pass
2715 04:40:40.125970 alsa_mixer-test_write_valid_LCALTA_42 pass
2716 04:40:40.126449 alsa_mixer-test_write_invalid_LCALTA_42 pass
2717 04:40:40.131474 alsa_mixer-test_event_missing_LCALTA_42 pass
2718 04:40:40.137038 alsa_mixer-test_event_spurious_LCALTA_42 pass
2719 04:40:40.142553 alsa_mixer-test_get_value_LCALTA_41 pass
2720 04:40:40.143028 alsa_mixer-test_name_LCALTA_41 pass
2721 04:40:40.148112 alsa_mixer-test_write_default_LCALTA_41 pass
2722 04:40:40.153682 alsa_mixer-test_write_valid_LCALTA_41 pass
2723 04:40:40.154155 alsa_mixer-test_write_invalid_LCALTA_41 pass
2724 04:40:40.159213 alsa_mixer-test_event_missing_LCALTA_41 pass
2725 04:40:40.164841 alsa_mixer-test_event_spurious_LCALTA_41 pass
2726 04:40:40.165321 alsa_mixer-test_get_value_LCALTA_40 pass
2727 04:40:40.170297 alsa_mixer-test_name_LCALTA_40 pass
2728 04:40:40.175971 alsa_mixer-test_write_default_LCALTA_40 pass
2729 04:40:40.176486 alsa_mixer-test_write_valid_LCALTA_40 pass
2730 04:40:40.181407 alsa_mixer-test_write_invalid_LCALTA_40 pass
2731 04:40:40.186977 alsa_mixer-test_event_missing_LCALTA_40 pass
2732 04:40:40.192504 alsa_mixer-test_event_spurious_LCALTA_40 pass
2733 04:40:40.192974 alsa_mixer-test_get_value_LCALTA_39 pass
2734 04:40:40.198029 alsa_mixer-test_name_LCALTA_39 pass
2735 04:40:40.203603 alsa_mixer-test_write_default_LCALTA_39 pass
2736 04:40:40.204107 alsa_mixer-test_write_valid_LCALTA_39 pass
2737 04:40:40.209128 alsa_mixer-test_write_invalid_LCALTA_39 pass
2738 04:40:40.214675 alsa_mixer-test_event_missing_LCALTA_39 pass
2739 04:40:40.215152 alsa_mixer-test_event_spurious_LCALTA_39 pass
2740 04:40:40.220245 alsa_mixer-test_get_value_LCALTA_38 pass
2741 04:40:40.225850 alsa_mixer-test_name_LCALTA_38 pass
2742 04:40:40.226331 alsa_mixer-test_write_default_LCALTA_38 pass
2743 04:40:40.231342 alsa_mixer-test_write_valid_LCALTA_38 pass
2744 04:40:40.236996 alsa_mixer-test_write_invalid_LCALTA_38 pass
2745 04:40:40.237473 alsa_mixer-test_event_missing_LCALTA_38 pass
2746 04:40:40.242427 alsa_mixer-test_event_spurious_LCALTA_38 pass
2747 04:40:40.248007 alsa_mixer-test_get_value_LCALTA_37 pass
2748 04:40:40.248485 alsa_mixer-test_name_LCALTA_37 pass
2749 04:40:40.253514 alsa_mixer-test_write_default_LCALTA_37 pass
2750 04:40:40.259060 alsa_mixer-test_write_valid_LCALTA_37 pass
2751 04:40:40.264597 alsa_mixer-test_write_invalid_LCALTA_37 pass
2752 04:40:40.265075 alsa_mixer-test_event_missing_LCALTA_37 pass
2753 04:40:40.270148 alsa_mixer-test_event_spurious_LCALTA_37 pass
2754 04:40:40.275693 alsa_mixer-test_get_value_LCALTA_36 pass
2755 04:40:40.276213 alsa_mixer-test_name_LCALTA_36 pass
2756 04:40:40.281227 alsa_mixer-test_write_default_LCALTA_36 pass
2757 04:40:40.286865 alsa_mixer-test_write_valid_LCALTA_36 pass
2758 04:40:40.287392 alsa_mixer-test_write_invalid_LCALTA_36 pass
2759 04:40:40.292319 alsa_mixer-test_event_missing_LCALTA_36 pass
2760 04:40:40.298000 alsa_mixer-test_event_spurious_LCALTA_36 pass
2761 04:40:40.298501 alsa_mixer-test_get_value_LCALTA_35 pass
2762 04:40:40.303418 alsa_mixer-test_name_LCALTA_35 pass
2763 04:40:40.308960 alsa_mixer-test_write_default_LCALTA_35 pass
2764 04:40:40.309453 alsa_mixer-test_write_valid_LCALTA_35 pass
2765 04:40:40.314526 alsa_mixer-test_write_invalid_LCALTA_35 pass
2766 04:40:40.320116 alsa_mixer-test_event_missing_LCALTA_35 pass
2767 04:40:40.325622 alsa_mixer-test_event_spurious_LCALTA_35 pass
2768 04:40:40.326101 alsa_mixer-test_get_value_LCALTA_34 pass
2769 04:40:40.331157 alsa_mixer-test_name_LCALTA_34 pass
2770 04:40:40.336711 alsa_mixer-test_write_default_LCALTA_34 pass
2771 04:40:40.337195 alsa_mixer-test_write_valid_LCALTA_34 pass
2772 04:40:40.342261 alsa_mixer-test_write_invalid_LCALTA_34 pass
2773 04:40:40.347874 alsa_mixer-test_event_missing_LCALTA_34 pass
2774 04:40:40.348386 alsa_mixer-test_event_spurious_LCALTA_34 pass
2775 04:40:40.353338 alsa_mixer-test_get_value_LCALTA_33 pass
2776 04:40:40.359004 alsa_mixer-test_name_LCALTA_33 pass
2777 04:40:40.359478 alsa_mixer-test_write_default_LCALTA_33 pass
2778 04:40:40.364434 alsa_mixer-test_write_valid_LCALTA_33 pass
2779 04:40:40.369997 alsa_mixer-test_write_invalid_LCALTA_33 pass
2780 04:40:40.375540 alsa_mixer-test_event_missing_LCALTA_33 pass
2781 04:40:40.376058 alsa_mixer-test_event_spurious_LCALTA_33 pass
2782 04:40:40.381080 alsa_mixer-test_get_value_LCALTA_32 pass
2783 04:40:40.381567 alsa_mixer-test_name_LCALTA_32 pass
2784 04:40:40.386633 alsa_mixer-test_write_default_LCALTA_32 pass
2785 04:40:40.392186 alsa_mixer-test_write_valid_LCALTA_32 pass
2786 04:40:40.397738 alsa_mixer-test_write_invalid_LCALTA_32 pass
2787 04:40:40.398214 alsa_mixer-test_event_missing_LCALTA_32 pass
2788 04:40:40.403331 alsa_mixer-test_event_spurious_LCALTA_32 pass
2789 04:40:40.408911 alsa_mixer-test_get_value_LCALTA_31 pass
2790 04:40:40.409409 alsa_mixer-test_name_LCALTA_31 pass
2791 04:40:40.414574 alsa_mixer-test_write_default_LCALTA_31 pass
2792 04:40:40.420126 alsa_mixer-test_write_valid_LCALTA_31 pass
2793 04:40:40.420627 alsa_mixer-test_write_invalid_LCALTA_31 pass
2794 04:40:40.425496 alsa_mixer-test_event_missing_LCALTA_31 pass
2795 04:40:40.431027 alsa_mixer-test_event_spurious_LCALTA_31 pass
2796 04:40:40.436600 alsa_mixer-test_get_value_LCALTA_30 pass
2797 04:40:40.437087 alsa_mixer-test_name_LCALTA_30 pass
2798 04:40:40.442182 alsa_mixer-test_write_default_LCALTA_30 pass
2799 04:40:40.447720 alsa_mixer-test_write_valid_LCALTA_30 pass
2800 04:40:40.448230 alsa_mixer-test_write_invalid_LCALTA_30 pass
2801 04:40:40.453211 alsa_mixer-test_event_missing_LCALTA_30 pass
2802 04:40:40.458753 alsa_mixer-test_event_spurious_LCALTA_30 pass
2803 04:40:40.459232 alsa_mixer-test_get_value_LCALTA_29 pass
2804 04:40:40.464306 alsa_mixer-test_name_LCALTA_29 pass
2805 04:40:40.469895 alsa_mixer-test_write_default_LCALTA_29 pass
2806 04:40:40.470374 alsa_mixer-test_write_valid_LCALTA_29 pass
2807 04:40:40.475405 alsa_mixer-test_write_invalid_LCALTA_29 pass
2808 04:40:40.481052 alsa_mixer-test_event_missing_LCALTA_29 pass
2809 04:40:40.481532 alsa_mixer-test_event_spurious_LCALTA_29 pass
2810 04:40:40.486479 alsa_mixer-test_get_value_LCALTA_28 pass
2811 04:40:40.492094 alsa_mixer-test_name_LCALTA_28 pass
2812 04:40:40.492580 alsa_mixer-test_write_default_LCALTA_28 pass
2813 04:40:40.497581 alsa_mixer-test_write_valid_LCALTA_28 pass
2814 04:40:40.503160 alsa_mixer-test_write_invalid_LCALTA_28 pass
2815 04:40:40.508688 alsa_mixer-test_event_missing_LCALTA_28 pass
2816 04:40:40.509172 alsa_mixer-test_event_spurious_LCALTA_28 pass
2817 04:40:40.514231 alsa_mixer-test_get_value_LCALTA_27 pass
2818 04:40:40.519808 alsa_mixer-test_name_LCALTA_27 pass
2819 04:40:40.520331 alsa_mixer-test_write_default_LCALTA_27 pass
2820 04:40:40.525325 alsa_mixer-test_write_valid_LCALTA_27 pass
2821 04:40:40.530919 alsa_mixer-test_write_invalid_LCALTA_27 pass
2822 04:40:40.531399 alsa_mixer-test_event_missing_LCALTA_27 pass
2823 04:40:40.536425 alsa_mixer-test_event_spurious_LCALTA_27 pass
2824 04:40:40.542049 alsa_mixer-test_get_value_LCALTA_26 pass
2825 04:40:40.542537 alsa_mixer-test_name_LCALTA_26 pass
2826 04:40:40.547511 alsa_mixer-test_write_default_LCALTA_26 skip
2827 04:40:40.553112 alsa_mixer-test_write_valid_LCALTA_26 skip
2828 04:40:40.553600 alsa_mixer-test_write_invalid_LCALTA_26 skip
2829 04:40:40.558599 alsa_mixer-test_event_missing_LCALTA_26 pass
2830 04:40:40.564203 alsa_mixer-test_event_spurious_LCALTA_26 pass
2831 04:40:40.569695 alsa_mixer-test_get_value_LCALTA_25 pass
2832 04:40:40.570166 alsa_mixer-test_name_LCALTA_25 pass
2833 04:40:40.575233 alsa_mixer-test_write_default_LCALTA_25 pass
2834 04:40:40.580822 alsa_mixer-test_write_valid_LCALTA_25 skip
2835 04:40:40.581320 alsa_mixer-test_write_invalid_LCALTA_25 skip
2836 04:40:40.586332 alsa_mixer-test_event_missing_LCALTA_25 pass
2837 04:40:40.591931 alsa_mixer-test_event_spurious_LCALTA_25 pass
2838 04:40:40.592456 alsa_mixer-test_get_value_LCALTA_24 pass
2839 04:40:40.597439 alsa_mixer-test_name_LCALTA_24 pass
2840 04:40:40.603060 alsa_mixer-test_write_default_LCALTA_24 skip
2841 04:40:40.603540 alsa_mixer-test_write_valid_LCALTA_24 skip
2842 04:40:40.608511 alsa_mixer-test_write_invalid_LCALTA_24 skip
2843 04:40:40.614127 alsa_mixer-test_event_missing_LCALTA_24 pass
2844 04:40:40.619622 alsa_mixer-test_event_spurious_LCALTA_24 pass
2845 04:40:40.620124 alsa_mixer-test_get_value_LCALTA_23 pass
2846 04:40:40.625185 alsa_mixer-test_name_LCALTA_23 pass
2847 04:40:40.630707 alsa_mixer-test_write_default_LCALTA_23 skip
2848 04:40:40.631186 alsa_mixer-test_write_valid_LCALTA_23 skip
2849 04:40:40.636234 alsa_mixer-test_write_invalid_LCALTA_23 skip
2850 04:40:40.641803 alsa_mixer-test_event_missing_LCALTA_23 pass
2851 04:40:40.642278 alsa_mixer-test_event_spurious_LCALTA_23 pass
2852 04:40:40.647362 alsa_mixer-test_get_value_LCALTA_22 pass
2853 04:40:40.652929 alsa_mixer-test_name_LCALTA_22 pass
2854 04:40:40.653401 alsa_mixer-test_write_default_LCALTA_22 pass
2855 04:40:40.658446 alsa_mixer-test_write_valid_LCALTA_22 pass
2856 04:40:40.664079 alsa_mixer-test_write_invalid_LCALTA_22 pass
2857 04:40:40.664552 alsa_mixer-test_event_missing_LCALTA_22 pass
2858 04:40:40.669550 alsa_mixer-test_event_spurious_LCALTA_22 pass
2859 04:40:40.675136 alsa_mixer-test_get_value_LCALTA_21 pass
2860 04:40:40.675607 alsa_mixer-test_name_LCALTA_21 pass
2861 04:40:40.680659 alsa_mixer-test_write_default_LCALTA_21 pass
2862 04:40:40.686209 alsa_mixer-test_write_valid_LCALTA_21 pass
2863 04:40:40.691733 alsa_mixer-test_write_invalid_LCALTA_21 pass
2864 04:40:40.692251 alsa_mixer-test_event_missing_LCALTA_21 pass
2865 04:40:40.697261 alsa_mixer-test_event_spurious_LCALTA_21 pass
2866 04:40:40.702810 alsa_mixer-test_get_value_LCALTA_20 pass
2867 04:40:40.703283 alsa_mixer-test_name_LCALTA_20 pass
2868 04:40:40.708361 alsa_mixer-test_write_default_LCALTA_20 pass
2869 04:40:40.713947 alsa_mixer-test_write_valid_LCALTA_20 pass
2870 04:40:40.714423 alsa_mixer-test_write_invalid_LCALTA_20 pass
2871 04:40:40.719436 alsa_mixer-test_event_missing_LCALTA_20 pass
2872 04:40:40.725076 alsa_mixer-test_event_spurious_LCALTA_20 pass
2873 04:40:40.725554 alsa_mixer-test_get_value_LCALTA_19 pass
2874 04:40:40.730557 alsa_mixer-test_name_LCALTA_19 pass
2875 04:40:40.736154 alsa_mixer-test_write_default_LCALTA_19 pass
2876 04:40:40.736642 alsa_mixer-test_write_valid_LCALTA_19 pass
2877 04:40:40.741625 alsa_mixer-test_write_invalid_LCALTA_19 pass
2878 04:40:40.747195 alsa_mixer-test_event_missing_LCALTA_19 pass
2879 04:40:40.752727 alsa_mixer-test_event_spurious_LCALTA_19 pass
2880 04:40:40.753210 alsa_mixer-test_get_value_LCALTA_18 pass
2881 04:40:40.758270 alsa_mixer-test_name_LCALTA_18 pass
2882 04:40:40.763817 alsa_mixer-test_write_default_LCALTA_18 pass
2883 04:40:40.764342 alsa_mixer-test_write_valid_LCALTA_18 pass
2884 04:40:40.769375 alsa_mixer-test_write_invalid_LCALTA_18 pass
2885 04:40:40.774935 alsa_mixer-test_event_missing_LCALTA_18 pass
2886 04:40:40.775412 alsa_mixer-test_event_spurious_LCALTA_18 pass
2887 04:40:40.780454 alsa_mixer-test_get_value_LCALTA_17 pass
2888 04:40:40.786255 alsa_mixer-test_name_LCALTA_17 pass
2889 04:40:40.786804 alsa_mixer-test_write_default_LCALTA_17 pass
2890 04:40:40.791572 alsa_mixer-test_write_valid_LCALTA_17 pass
2891 04:40:40.797144 alsa_mixer-test_write_invalid_LCALTA_17 pass
2892 04:40:40.802658 alsa_mixer-test_event_missing_LCALTA_17 pass
2893 04:40:40.803144 alsa_mixer-test_event_spurious_LCALTA_17 pass
2894 04:40:40.808232 alsa_mixer-test_get_value_LCALTA_16 pass
2895 04:40:40.808728 alsa_mixer-test_name_LCALTA_16 pass
2896 04:40:40.813752 alsa_mixer-test_write_default_LCALTA_16 pass
2897 04:40:40.819289 alsa_mixer-test_write_valid_LCALTA_16 pass
2898 04:40:40.824847 alsa_mixer-test_write_invalid_LCALTA_16 pass
2899 04:40:40.825332 alsa_mixer-test_event_missing_LCALTA_16 pass
2900 04:40:40.830377 alsa_mixer-test_event_spurious_LCALTA_16 pass
2901 04:40:40.835918 alsa_mixer-test_get_value_LCALTA_15 pass
2902 04:40:40.836423 alsa_mixer-test_name_LCALTA_15 pass
2903 04:40:40.841438 alsa_mixer-test_write_default_LCALTA_15 pass
2904 04:40:40.847119 alsa_mixer-test_write_valid_LCALTA_15 pass
2905 04:40:40.847603 alsa_mixer-test_write_invalid_LCALTA_15 pass
2906 04:40:40.852582 alsa_mixer-test_event_missing_LCALTA_15 pass
2907 04:40:40.858128 alsa_mixer-test_event_spurious_LCALTA_15 pass
2908 04:40:40.863677 alsa_mixer-test_get_value_LCALTA_14 pass
2909 04:40:40.864189 alsa_mixer-test_name_LCALTA_14 pass
2910 04:40:40.869210 alsa_mixer-test_write_default_LCALTA_14 pass
2911 04:40:40.874759 alsa_mixer-test_write_valid_LCALTA_14 pass
2912 04:40:40.875241 alsa_mixer-test_write_invalid_LCALTA_14 pass
2913 04:40:40.880307 alsa_mixer-test_event_missing_LCALTA_14 pass
2914 04:40:40.885863 alsa_mixer-test_event_spurious_LCALTA_14 pass
2915 04:40:40.886399 alsa_mixer-test_get_value_LCALTA_13 pass
2916 04:40:40.891464 alsa_mixer-test_name_LCALTA_13 pass
2917 04:40:40.896981 alsa_mixer-test_write_default_LCALTA_13 pass
2918 04:40:40.897751 alsa_mixer-test_write_valid_LCALTA_13 pass
2919 04:40:40.902496 alsa_mixer-test_write_invalid_LCALTA_13 pass
2920 04:40:40.908208 alsa_mixer-test_event_missing_LCALTA_13 pass
2921 04:40:40.908724 alsa_mixer-test_event_spurious_LCALTA_13 pass
2922 04:40:40.913584 alsa_mixer-test_get_value_LCALTA_12 pass
2923 04:40:40.919169 alsa_mixer-test_name_LCALTA_12 pass
2924 04:40:40.919616 alsa_mixer-test_write_default_LCALTA_12 pass
2925 04:40:40.924668 alsa_mixer-test_write_valid_LCALTA_12 pass
2926 04:40:40.930217 alsa_mixer-test_write_invalid_LCALTA_12 pass
2927 04:40:40.935763 alsa_mixer-test_event_missing_LCALTA_12 pass
2928 04:40:40.936262 alsa_mixer-test_event_spurious_LCALTA_12 pass
2929 04:40:40.941350 alsa_mixer-test_get_value_LCALTA_11 pass
2930 04:40:40.946872 alsa_mixer-test_name_LCALTA_11 pass
2931 04:40:40.947331 alsa_mixer-test_write_default_LCALTA_11 pass
2932 04:40:40.952405 alsa_mixer-test_write_valid_LCALTA_11 pass
2933 04:40:40.957974 alsa_mixer-test_write_invalid_LCALTA_11 pass
2934 04:40:40.958434 alsa_mixer-test_event_missing_LCALTA_11 pass
2935 04:40:40.963482 alsa_mixer-test_event_spurious_LCALTA_11 pass
2936 04:40:40.969097 alsa_mixer-test_get_value_LCALTA_10 pass
2937 04:40:40.969561 alsa_mixer-test_name_LCALTA_10 pass
2938 04:40:40.974581 alsa_mixer-test_write_default_LCALTA_10 pass
2939 04:40:40.980180 alsa_mixer-test_write_valid_LCALTA_10 pass
2940 04:40:40.980632 alsa_mixer-test_write_invalid_LCALTA_10 pass
2941 04:40:40.985703 alsa_mixer-test_event_missing_LCALTA_10 pass
2942 04:40:40.991218 alsa_mixer-test_event_spurious_LCALTA_10 pass
2943 04:40:40.996784 alsa_mixer-test_get_value_LCALTA_9 pass
2944 04:40:40.997242 alsa_mixer-test_name_LCALTA_9 pass
2945 04:40:41.002317 alsa_mixer-test_write_default_LCALTA_9 pass
2946 04:40:41.007882 alsa_mixer-test_write_valid_LCALTA_9 pass
2947 04:40:41.008377 alsa_mixer-test_write_invalid_LCALTA_9 pass
2948 04:40:41.013419 alsa_mixer-test_event_missing_LCALTA_9 pass
2949 04:40:41.018967 alsa_mixer-test_event_spurious_LCALTA_9 pass
2950 04:40:41.019425 alsa_mixer-test_get_value_LCALTA_8 pass
2951 04:40:41.024528 alsa_mixer-test_name_LCALTA_8 pass
2952 04:40:41.030101 alsa_mixer-test_write_default_LCALTA_8 pass
2953 04:40:41.030573 alsa_mixer-test_write_valid_LCALTA_8 pass
2954 04:40:41.035582 alsa_mixer-test_write_invalid_LCALTA_8 pass
2955 04:40:41.041142 alsa_mixer-test_event_missing_LCALTA_8 pass
2956 04:40:41.041610 alsa_mixer-test_event_spurious_LCALTA_8 pass
2957 04:40:41.046739 alsa_mixer-test_get_value_LCALTA_7 pass
2958 04:40:41.052253 alsa_mixer-test_name_LCALTA_7 pass
2959 04:40:41.052723 alsa_mixer-test_write_default_LCALTA_7 pass
2960 04:40:41.057792 alsa_mixer-test_write_valid_LCALTA_7 pass
2961 04:40:41.063350 alsa_mixer-test_write_invalid_LCALTA_7 pass
2962 04:40:41.063814 alsa_mixer-test_event_missing_LCALTA_7 pass
2963 04:40:41.068895 alsa_mixer-test_event_spurious_LCALTA_7 pass
2964 04:40:41.074424 alsa_mixer-test_get_value_LCALTA_6 pass
2965 04:40:41.074884 alsa_mixer-test_name_LCALTA_6 pass
2966 04:40:41.080005 alsa_mixer-test_write_default_LCALTA_6 pass
2967 04:40:41.085525 alsa_mixer-test_write_valid_LCALTA_6 pass
2968 04:40:41.086003 alsa_mixer-test_write_invalid_LCALTA_6 pass
2969 04:40:41.091115 alsa_mixer-test_event_missing_LCALTA_6 pass
2970 04:40:41.096617 alsa_mixer-test_event_spurious_LCALTA_6 pass
2971 04:40:41.097089 alsa_mixer-test_get_value_LCALTA_5 pass
2972 04:40:41.102162 alsa_mixer-test_name_LCALTA_5 pass
2973 04:40:41.107727 alsa_mixer-test_write_default_LCALTA_5 pass
2974 04:40:41.108246 alsa_mixer-test_write_valid_LCALTA_5 pass
2975 04:40:41.113258 alsa_mixer-test_write_invalid_LCALTA_5 pass
2976 04:40:41.118803 alsa_mixer-test_event_missing_LCALTA_5 pass
2977 04:40:41.119264 alsa_mixer-test_event_spurious_LCALTA_5 pass
2978 04:40:41.124359 alsa_mixer-test_get_value_LCALTA_4 pass
2979 04:40:41.129904 alsa_mixer-test_name_LCALTA_4 pass
2980 04:40:41.130362 alsa_mixer-test_write_default_LCALTA_4 pass
2981 04:40:41.135453 alsa_mixer-test_write_valid_LCALTA_4 pass
2982 04:40:41.140995 alsa_mixer-test_write_invalid_LCALTA_4 pass
2983 04:40:41.141470 alsa_mixer-test_event_missing_LCALTA_4 pass
2984 04:40:41.146544 alsa_mixer-test_event_spurious_LCALTA_4 pass
2985 04:40:41.152151 alsa_mixer-test_get_value_LCALTA_3 pass
2986 04:40:41.152610 alsa_mixer-test_name_LCALTA_3 pass
2987 04:40:41.157619 alsa_mixer-test_write_default_LCALTA_3 pass
2988 04:40:41.163172 alsa_mixer-test_write_valid_LCALTA_3 pass
2989 04:40:41.163628 alsa_mixer-test_write_invalid_LCALTA_3 pass
2990 04:40:41.168733 alsa_mixer-test_event_missing_LCALTA_3 pass
2991 04:40:41.174278 alsa_mixer-test_event_spurious_LCALTA_3 pass
2992 04:40:41.174745 alsa_mixer-test_get_value_LCALTA_2 pass
2993 04:40:41.179824 alsa_mixer-test_name_LCALTA_2 pass
2994 04:40:41.185409 alsa_mixer-test_write_default_LCALTA_2 pass
2995 04:40:41.185864 alsa_mixer-test_write_valid_LCALTA_2 pass
2996 04:40:41.190907 alsa_mixer-test_write_invalid_LCALTA_2 pass
2997 04:40:41.196463 alsa_mixer-test_event_missing_LCALTA_2 pass
2998 04:40:41.202013 alsa_mixer-test_event_spurious_LCALTA_2 pass
2999 04:40:41.202470 alsa_mixer-test_get_value_LCALTA_1 pass
3000 04:40:41.207558 alsa_mixer-test_name_LCALTA_1 pass
3001 04:40:41.208041 alsa_mixer-test_write_default_LCALTA_1 pass
3002 04:40:41.213141 alsa_mixer-test_write_valid_LCALTA_1 pass
3003 04:40:41.218656 alsa_mixer-test_write_invalid_LCALTA_1 pass
3004 04:40:41.224211 alsa_mixer-test_event_missing_LCALTA_1 pass
3005 04:40:41.224669 alsa_mixer-test_event_spurious_LCALTA_1 pass
3006 04:40:41.229745 alsa_mixer-test_get_value_LCALTA_0 pass
3007 04:40:41.230203 alsa_mixer-test_name_LCALTA_0 pass
3008 04:40:41.235255 alsa_mixer-test_write_default_LCALTA_0 pass
3009 04:40:41.240807 alsa_mixer-test_write_valid_LCALTA_0 pass
3010 04:40:41.246404 alsa_mixer-test_write_invalid_LCALTA_0 pass
3011 04:40:41.246867 alsa_mixer-test_event_missing_LCALTA_0 pass
3012 04:40:41.251938 alsa_mixer-test_event_spurious_LCALTA_0 pass
3013 04:40:41.252420 alsa_mixer-test pass
3014 04:40:41.257465 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
3015 04:40:41.263137 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
3016 04:40:41.268559 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
3017 04:40:41.274146 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
3018 04:40:41.274607 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
3019 04:40:41.279649 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
3020 04:40:41.285223 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
3021 04:40:41.290762 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
3022 04:40:41.296302 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
3023 04:40:41.301856 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
3024 04:40:41.302317 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
3025 04:40:41.307410 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
3026 04:40:41.313014 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
3027 04:40:41.318498 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
3028 04:40:41.324219 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
3029 04:40:41.329580 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
3030 04:40:41.330048 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
3031 04:40:41.335158 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
3032 04:40:41.340738 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
3033 04:40:41.346291 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
3034 04:40:41.351772 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
3035 04:40:41.357334 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
3036 04:40:41.357812 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
3037 04:40:41.362885 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
3038 04:40:41.368428 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
3039 04:40:41.374077 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
3040 04:40:41.379569 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
3041 04:40:41.385228 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
3042 04:40:41.385793 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
3043 04:40:41.390606 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
3044 04:40:41.396208 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
3045 04:40:41.401799 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
3046 04:40:41.407243 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
3047 04:40:41.412836 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
3048 04:40:41.418507 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
3049 04:40:41.419084 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
3050 04:40:41.423876 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
3051 04:40:41.429422 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
3052 04:40:41.435006 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
3053 04:40:41.440498 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
3054 04:40:41.446141 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
3055 04:40:41.446608 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
3056 04:40:41.451629 alsa_pcm-test pass
3057 04:40:41.457164 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3058 04:40:41.468295 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3059 04:40:41.473760 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3060 04:40:41.484888 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3061 04:40:41.490429 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3062 04:40:41.496052 alsa_test-pcmtest-driver pass
3063 04:40:41.501627 alsa_utimer-test_global_wrong_timers_test pass
3064 04:40:41.502218 alsa_utimer-test_timer_f_utimer fail
3065 04:40:41.507320 alsa_utimer-test fail
3066 04:40:41.508159 + ../../utils/send-to-lava.sh ./output/result.txt
3067 04:40:41.512730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
3068 04:40:41.513943 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
3070 04:40:41.523763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
3071 04:40:41.524740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
3073 04:40:41.529561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
3074 04:40:41.530362 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
3076 04:40:41.552226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
3077 04:40:41.553100 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
3079 04:40:41.609380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
3080 04:40:41.610127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
3082 04:40:41.674357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
3083 04:40:41.675143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
3085 04:40:41.733350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
3086 04:40:41.734164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
3088 04:40:41.788436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
3089 04:40:41.789210 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
3091 04:40:41.836891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
3092 04:40:41.838054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
3094 04:40:41.898258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
3095 04:40:41.899124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
3097 04:40:41.953360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
3098 04:40:41.954361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
3100 04:40:41.996183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
3101 04:40:41.997307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
3103 04:40:42.039129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
3104 04:40:42.040150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
3106 04:40:42.088399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
3107 04:40:42.089391 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
3109 04:40:42.138065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
3110 04:40:42.139235 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
3112 04:40:42.192796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
3113 04:40:42.194016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
3115 04:40:42.245577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
3116 04:40:42.246710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
3118 04:40:42.294215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
3119 04:40:42.295303 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
3121 04:40:42.350847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
3122 04:40:42.351858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
3124 04:40:42.396307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
3125 04:40:42.397326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
3127 04:40:42.451695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
3128 04:40:42.452806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
3130 04:40:42.507055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
3131 04:40:42.508231 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
3133 04:40:42.552697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
3134 04:40:42.553910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
3136 04:40:42.602645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
3137 04:40:42.603556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
3139 04:40:42.656361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
3140 04:40:42.657380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
3142 04:40:42.708415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
3143 04:40:42.709473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
3145 04:40:42.756162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
3146 04:40:42.757403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3148 04:40:42.811512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3149 04:40:42.812783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3151 04:40:42.861110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3152 04:40:42.862241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3154 04:40:42.912029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3155 04:40:42.913174 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3157 04:40:42.964647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3158 04:40:42.965853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3160 04:40:43.010654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3161 04:40:43.011895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3163 04:40:43.059302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3164 04:40:43.060556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3166 04:40:43.111701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3167 04:40:43.112882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3169 04:40:43.157574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3170 04:40:43.158441 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3172 04:40:43.211578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3173 04:40:43.212836 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3175 04:40:43.263696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3176 04:40:43.264566 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3178 04:40:43.313395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3179 04:40:43.314241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3181 04:40:43.361455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3182 04:40:43.362274 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3184 04:40:43.409482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3185 04:40:43.410339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3187 04:40:43.464646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3188 04:40:43.465497 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3190 04:40:43.521928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3191 04:40:43.522780 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3193 04:40:43.577952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3194 04:40:43.578817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3196 04:40:43.638662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3197 04:40:43.639476 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3199 04:40:43.688506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3200 04:40:43.689310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3202 04:40:43.735962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3203 04:40:43.736783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3205 04:40:43.793561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3206 04:40:43.794356 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3208 04:40:43.847621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3209 04:40:43.848446 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3211 04:40:43.903377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3212 04:40:43.904172 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3214 04:40:43.960222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3215 04:40:43.961013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3217 04:40:44.010385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3218 04:40:44.011161 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3220 04:40:44.055578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3221 04:40:44.056402 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3223 04:40:44.110305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3224 04:40:44.111092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3226 04:40:44.156796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3227 04:40:44.157573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3229 04:40:44.212089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3230 04:40:44.212879 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3232 04:40:44.265897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3233 04:40:44.266686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3235 04:40:44.312210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3236 04:40:44.312992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3238 04:40:44.366154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3239 04:40:44.366933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3241 04:40:44.419440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3242 04:40:44.420617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3244 04:40:44.473095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3245 04:40:44.474260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3247 04:40:44.525670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3248 04:40:44.526766 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3250 04:40:44.578923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3251 04:40:44.580094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3253 04:40:44.636321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3254 04:40:44.637307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3256 04:40:44.681688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3257 04:40:44.682707 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3259 04:40:44.726954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3260 04:40:44.728021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3262 04:40:44.771732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3263 04:40:44.772813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3265 04:40:44.823127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3266 04:40:44.824205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3268 04:40:44.875351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3269 04:40:44.876500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3271 04:40:44.932771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3272 04:40:44.933821 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3274 04:40:44.983427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3275 04:40:44.984429 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3277 04:40:45.033442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3278 04:40:45.034275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3280 04:40:45.085306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3281 04:40:45.086092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3283 04:40:45.137409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3284 04:40:45.138146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3286 04:40:45.189980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3287 04:40:45.190780 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3289 04:40:45.235004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3290 04:40:45.235709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3292 04:40:45.281504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3293 04:40:45.282298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3295 04:40:45.332856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3296 04:40:45.333579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3298 04:40:45.381976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3299 04:40:45.382850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3301 04:40:45.429144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3302 04:40:45.429976 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3304 04:40:45.475546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3305 04:40:45.476307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3307 04:40:45.519625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3308 04:40:45.520307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3310 04:40:45.565802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3311 04:40:45.566462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3313 04:40:45.615457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3314 04:40:45.616304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3316 04:40:45.672489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3317 04:40:45.673256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3319 04:40:45.722610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3320 04:40:45.723392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3322 04:40:45.771963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3323 04:40:45.772796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3325 04:40:45.826435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3326 04:40:45.827246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3328 04:40:45.885546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3329 04:40:45.886431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3331 04:40:45.941055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3332 04:40:45.941960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3334 04:40:45.988039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3335 04:40:45.988882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3337 04:40:46.034058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3338 04:40:46.034907 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3340 04:40:46.089886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3341 04:40:46.090737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3343 04:40:46.138874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3344 04:40:46.139709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3346 04:40:46.186997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3347 04:40:46.187832 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3349 04:40:46.240097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3350 04:40:46.240931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3352 04:40:46.290098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3353 04:40:46.290926 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3355 04:40:46.354606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3356 04:40:46.355438 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3358 04:40:46.409135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3359 04:40:46.409986 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3361 04:40:46.461851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3362 04:40:46.462665 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3364 04:40:46.512103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3365 04:40:46.512925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3367 04:40:46.564952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3368 04:40:46.565809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3370 04:40:46.617988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3371 04:40:46.618826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3373 04:40:46.671267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3374 04:40:46.672093 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3376 04:40:46.721434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3377 04:40:46.722258 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3379 04:40:46.777289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3380 04:40:46.778132 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3382 04:40:46.828293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3383 04:40:46.829465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3385 04:40:46.878578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3386 04:40:46.879415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3388 04:40:46.928312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3389 04:40:46.929382 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3391 04:40:46.973930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3392 04:40:46.974744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3394 04:40:47.023174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3395 04:40:47.024031 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3397 04:40:47.073907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3398 04:40:47.074725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3400 04:40:47.129646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3401 04:40:47.130445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3403 04:40:47.181825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3404 04:40:47.182625 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3406 04:40:47.232461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3407 04:40:47.233267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3409 04:40:47.278864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3410 04:40:47.279666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3412 04:40:47.332084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3413 04:40:47.332889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3415 04:40:47.383785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3416 04:40:47.384661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3418 04:40:47.427908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3419 04:40:47.428810 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3421 04:40:47.487897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3422 04:40:47.488804 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3424 04:40:47.534341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3425 04:40:47.535185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3427 04:40:47.585946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3428 04:40:47.586776 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3430 04:40:47.641305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3431 04:40:47.642109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3433 04:40:47.690695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3434 04:40:47.691487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3436 04:40:47.748732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3437 04:40:47.749504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3439 04:40:47.804408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3440 04:40:47.805282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3442 04:40:47.853751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3443 04:40:47.854607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3445 04:40:47.917241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3446 04:40:47.918086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3448 04:40:47.966723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3449 04:40:47.967486 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3451 04:40:48.019780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3452 04:40:48.020622 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3454 04:40:48.073990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3455 04:40:48.074772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3457 04:40:48.129655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3458 04:40:48.130425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3460 04:40:48.188811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3461 04:40:48.189590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3463 04:40:48.241803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3464 04:40:48.242585 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3466 04:40:48.299186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3467 04:40:48.299964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3469 04:40:48.350336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3470 04:40:48.351407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3472 04:40:48.410019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3473 04:40:48.410863 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3475 04:40:48.467019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3476 04:40:48.467861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3478 04:40:48.513207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3479 04:40:48.514047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3481 04:40:48.572389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3482 04:40:48.573255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3484 04:40:48.623568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3485 04:40:48.624415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3487 04:40:48.680808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3488 04:40:48.681630 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3490 04:40:48.733758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3491 04:40:48.734526 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3493 04:40:48.786445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3494 04:40:48.787221 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3496 04:40:48.842658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3497 04:40:48.843448 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3499 04:40:48.895005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3500 04:40:48.895773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3502 04:40:48.952059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3503 04:40:48.952832 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3505 04:40:48.995734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3506 04:40:48.996600 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3508 04:40:49.050823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3509 04:40:49.051631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3511 04:40:49.095418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3512 04:40:49.096149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3514 04:40:49.144931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3515 04:40:49.145641 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3517 04:40:49.191101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3518 04:40:49.191801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3520 04:40:49.247832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3521 04:40:49.248625 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3523 04:40:49.298739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3524 04:40:49.299491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3526 04:40:49.348545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3527 04:40:49.349242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3529 04:40:49.399710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3530 04:40:49.400543 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3532 04:40:49.449057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3533 04:40:49.449846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3535 04:40:49.501656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3536 04:40:49.502437 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3538 04:40:49.555685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3539 04:40:49.556526 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3541 04:40:49.612570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3542 04:40:49.613385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3544 04:40:49.664051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3545 04:40:49.664824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3547 04:40:49.714579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3548 04:40:49.715339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3550 04:40:49.766501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3551 04:40:49.767198 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3553 04:40:49.821573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3554 04:40:49.822371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3556 04:40:49.865560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3557 04:40:49.866261 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3559 04:40:49.911442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3560 04:40:49.912225 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3562 04:40:49.956279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3563 04:40:49.956979 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3565 04:40:50.006443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3566 04:40:50.007190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3568 04:40:50.058568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3569 04:40:50.059321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3571 04:40:50.114186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3572 04:40:50.114997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3574 04:40:50.171628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3575 04:40:50.172454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3577 04:40:50.219656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3578 04:40:50.220561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3580 04:40:50.275510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3581 04:40:50.276334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3583 04:40:50.318645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3584 04:40:50.319424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3586 04:40:50.363964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3587 04:40:50.364724 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3589 04:40:50.407819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3590 04:40:50.408649 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3592 04:40:50.464816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3593 04:40:50.465600 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3595 04:40:50.521652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3596 04:40:50.522461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3598 04:40:50.570658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3599 04:40:50.571466 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3601 04:40:50.617694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3602 04:40:50.618480 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3604 04:40:50.670589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3605 04:40:50.671305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3607 04:40:50.722060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3608 04:40:50.722848 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3610 04:40:50.772711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3611 04:40:50.773491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3613 04:40:50.825555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3614 04:40:50.826335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3616 04:40:50.878392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3617 04:40:50.879102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3619 04:40:50.928736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3620 04:40:50.929463 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3622 04:40:50.975043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3623 04:40:50.975771 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3625 04:40:51.029750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3626 04:40:51.030494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3628 04:40:51.082874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3629 04:40:51.083564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3631 04:40:51.133439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3632 04:40:51.134143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3634 04:40:51.190538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3635 04:40:51.191227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3637 04:40:51.242327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3638 04:40:51.243015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3640 04:40:51.298912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3641 04:40:51.299592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3643 04:40:51.352989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3644 04:40:51.353918 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3646 04:40:51.399325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3647 04:40:51.400135 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3649 04:40:51.453475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3650 04:40:51.454347 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3652 04:40:51.507195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3653 04:40:51.508415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3655 04:40:51.551097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3656 04:40:51.551956 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3658 04:40:51.606262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3659 04:40:51.607062 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3661 04:40:51.657854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3662 04:40:51.658713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3664 04:40:51.719026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3665 04:40:51.719887 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3667 04:40:51.774457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3668 04:40:51.775224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3670 04:40:51.828826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3671 04:40:51.829716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3673 04:40:51.883167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3674 04:40:51.883973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3676 04:40:51.934431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3677 04:40:51.935305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3679 04:40:51.977922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3680 04:40:51.978754 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3682 04:40:52.027392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3683 04:40:52.028294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3685 04:40:52.082058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3686 04:40:52.082856 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3688 04:40:52.131208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3689 04:40:52.132083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3691 04:40:52.189942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3692 04:40:52.190817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3694 04:40:52.239125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3695 04:40:52.239928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3697 04:40:52.283407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3698 04:40:52.284109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3700 04:40:52.336380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3701 04:40:52.337115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3703 04:40:52.380967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3704 04:40:52.381682 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3706 04:40:52.428514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3707 04:40:52.429294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3709 04:40:52.473171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3710 04:40:52.473903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3712 04:40:52.527169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3713 04:40:52.527951 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3715 04:40:52.582772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3716 04:40:52.583564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3718 04:40:52.633655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3719 04:40:52.634406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3721 04:40:52.680910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3722 04:40:52.681605 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3724 04:40:52.733632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3725 04:40:52.734356 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3727 04:40:52.787117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3728 04:40:52.787808 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3730 04:40:52.831606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3731 04:40:52.832361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3733 04:40:52.884011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3734 04:40:52.884712 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3736 04:40:52.935537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3737 04:40:52.936343 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3739 04:40:52.990767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3740 04:40:52.991477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3742 04:40:53.036021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3743 04:40:53.036812 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3745 04:40:53.081353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3746 04:40:53.082051 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3748 04:40:53.127361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3749 04:40:53.128090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3751 04:40:53.178949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3752 04:40:53.179646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3754 04:40:53.234317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3755 04:40:53.235052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3757 04:40:53.278590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3758 04:40:53.279283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3760 04:40:53.326517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3761 04:40:53.327245 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3763 04:40:53.375008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3764 04:40:53.375754 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3766 04:40:53.426869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3767 04:40:53.427640 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3769 04:40:53.474488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3770 04:40:53.475217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3772 04:40:53.530718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3773 04:40:53.531510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3775 04:40:53.581951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3776 04:40:53.582734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3778 04:40:53.638943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3779 04:40:53.639698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3781 04:40:53.684811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3782 04:40:53.685548 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3784 04:40:53.734323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3785 04:40:53.735063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3787 04:40:53.788110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3788 04:40:53.788987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3790 04:40:53.835660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3791 04:40:53.836436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3793 04:40:53.883171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3794 04:40:53.883879 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3796 04:40:53.936600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3797 04:40:53.937352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3799 04:40:53.987353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3800 04:40:53.988058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3802 04:40:54.044218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3803 04:40:54.044988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3805 04:40:54.093143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3806 04:40:54.093841 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3808 04:40:54.141798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3809 04:40:54.142538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3811 04:40:54.186419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3812 04:40:54.187121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3814 04:40:54.235141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3815 04:40:54.235870 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3817 04:40:54.296389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3818 04:40:54.297080 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3820 04:40:54.347595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3821 04:40:54.348360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3823 04:40:54.399144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3824 04:40:54.399866 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3826 04:40:54.451022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3827 04:40:54.451805 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3829 04:40:54.502273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3830 04:40:54.502992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3832 04:40:54.553660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3833 04:40:54.554483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3835 04:40:54.606165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3836 04:40:54.606893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3838 04:40:54.663937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3839 04:40:54.664727 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3841 04:40:54.714416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3842 04:40:54.715121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3844 04:40:54.760566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3845 04:40:54.761293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3847 04:40:54.811208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3848 04:40:54.811901 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3850 04:40:54.861213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3851 04:40:54.861944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3853 04:40:54.913220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3854 04:40:54.913914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3856 04:40:54.956044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3857 04:40:54.956802 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3859 04:40:55.012691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3860 04:40:55.013386 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3862 04:40:55.066248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3863 04:40:55.067021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3865 04:40:55.116680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3866 04:40:55.117385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3868 04:40:55.171604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3869 04:40:55.172373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3871 04:40:55.222302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3872 04:40:55.222994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3874 04:40:55.271671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3875 04:40:55.272447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3877 04:40:55.325765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3878 04:40:55.326524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3880 04:40:55.377935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3881 04:40:55.378750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3883 04:40:55.428941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3884 04:40:55.429783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3886 04:40:55.479314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3887 04:40:55.480137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3889 04:40:55.534443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3890 04:40:55.535237 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3892 04:40:55.593459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3893 04:40:55.594259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3895 04:40:55.646587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3896 04:40:55.647345 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3898 04:40:55.701993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3899 04:40:55.702698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3901 04:40:55.758351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3902 04:40:55.759079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3904 04:40:55.814534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3905 04:40:55.815312 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3907 04:40:55.870980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3908 04:40:55.871710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3910 04:40:55.932552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3911 04:40:55.933318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3913 04:40:55.990064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3914 04:40:55.990764 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3916 04:40:56.043416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3917 04:40:56.044185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3919 04:40:56.093424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3920 04:40:56.094124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3922 04:40:56.136968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3923 04:40:56.137695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3925 04:40:56.200037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3926 04:40:56.200735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3928 04:40:56.248919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3929 04:40:56.249652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3931 04:40:56.302523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3932 04:40:56.303215 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3934 04:40:56.355447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3935 04:40:56.356184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3937 04:40:56.414333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3938 04:40:56.415088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3940 04:40:56.463277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3941 04:40:56.464074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3943 04:40:56.515945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3944 04:40:56.516710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3946 04:40:56.574314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3947 04:40:56.575142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3949 04:40:56.626443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3950 04:40:56.627187 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3952 04:40:56.672023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3953 04:40:56.672765 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3955 04:40:56.991708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3956 04:40:56.992633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3958 04:40:56.994029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3959 04:40:56.994464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3960 04:40:56.994863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3961 04:40:56.995258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3962 04:40:56.995918 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3964 04:40:56.997160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3966 04:40:56.998311 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3968 04:40:56.999463 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3970 04:40:57.000713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3971 04:40:57.001381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3973 04:40:57.028797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3974 04:40:57.029617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3976 04:40:57.079494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3977 04:40:57.080302 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3979 04:40:57.125428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3980 04:40:57.126188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3982 04:40:57.183617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3983 04:40:57.184436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3985 04:40:57.235900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3986 04:40:57.236702 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3988 04:40:57.292802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3989 04:40:57.293504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3991 04:40:57.343437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3992 04:40:57.344298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3994 04:40:57.396027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3995 04:40:57.396777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3997 04:40:57.453291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
3998 04:40:57.454088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
4000 04:40:57.506967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
4001 04:40:57.507692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
4003 04:40:57.564114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
4004 04:40:57.564930 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
4006 04:40:57.621106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
4007 04:40:57.621876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
4009 04:40:57.679086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
4010 04:40:57.679875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
4012 04:40:57.729950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
4013 04:40:57.730668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
4015 04:40:57.780776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
4016 04:40:57.781544 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
4018 04:40:57.829343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
4019 04:40:57.830144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
4021 04:40:57.885695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
4022 04:40:57.886471 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
4024 04:40:57.932823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
4025 04:40:57.933545 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
4027 04:40:57.992081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
4028 04:40:57.992894 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
4030 04:40:58.036679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
4031 04:40:58.037423 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
4033 04:40:58.093327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
4034 04:40:58.094113 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
4036 04:40:58.156184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
4037 04:40:58.156774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
4039 04:40:58.217752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
4040 04:40:58.218561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
4042 04:40:58.273910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
4043 04:40:58.274715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
4045 04:40:58.327973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
4046 04:40:58.328740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
4048 04:40:58.378456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
4049 04:40:58.379261 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
4051 04:40:58.432068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
4052 04:40:58.432813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
4054 04:40:58.477496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
4055 04:40:58.478283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
4057 04:40:58.525854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
4058 04:40:58.526597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
4060 04:40:58.582109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
4061 04:40:58.582930 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
4063 04:40:58.636022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
4064 04:40:58.636787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
4066 04:40:58.680682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
4067 04:40:58.681454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
4069 04:40:58.730831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
4070 04:40:58.731571 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
4072 04:40:58.786920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
4073 04:40:58.787705 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
4075 04:40:58.836833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
4076 04:40:58.837602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
4078 04:40:58.885621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
4079 04:40:58.886395 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
4081 04:40:58.940941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
4082 04:40:58.941648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
4084 04:40:58.995408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
4085 04:40:58.996207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
4087 04:40:59.045560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
4088 04:40:59.046335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
4090 04:40:59.097597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
4091 04:40:59.098322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
4093 04:40:59.154515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
4094 04:40:59.155286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
4096 04:40:59.209445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
4097 04:40:59.210275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
4099 04:40:59.264051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
4100 04:40:59.264833 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
4102 04:40:59.317389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
4103 04:40:59.318126 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
4105 04:40:59.372282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
4106 04:40:59.373071 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
4108 04:40:59.425615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
4109 04:40:59.426354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
4111 04:40:59.483879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
4112 04:40:59.484728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
4114 04:40:59.535697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
4115 04:40:59.536479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
4117 04:40:59.593905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
4118 04:40:59.594729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
4120 04:40:59.646215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
4121 04:40:59.646963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
4123 04:40:59.703950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
4124 04:40:59.704716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
4126 04:40:59.756168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
4127 04:40:59.756917 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
4129 04:40:59.808971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
4130 04:40:59.809831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
4132 04:40:59.865659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
4133 04:40:59.866544 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
4135 04:40:59.918137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
4136 04:40:59.918913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
4138 04:40:59.976068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
4139 04:40:59.976868 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
4141 04:41:00.034477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
4142 04:41:00.035196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
4144 04:41:00.092333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
4145 04:41:00.093073 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4147 04:41:00.150433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4148 04:41:00.151173 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4150 04:41:00.203244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4151 04:41:00.203938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4153 04:41:00.257048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4154 04:41:00.257765 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4156 04:41:00.303256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4157 04:41:00.303949 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4159 04:41:00.357644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4160 04:41:00.358358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4162 04:41:00.413509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4163 04:41:00.414250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4165 04:41:00.466550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4166 04:41:00.467306 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4168 04:41:00.513502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4169 04:41:00.514232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4171 04:41:00.566569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4172 04:41:00.567382 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4174 04:41:00.611535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4175 04:41:00.612300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4177 04:41:00.664030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4178 04:41:00.664751 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4180 04:41:00.715281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4181 04:41:00.715972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4183 04:41:00.766346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4184 04:41:00.767064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4186 04:41:00.821648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4187 04:41:00.822336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4189 04:41:00.874305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4190 04:41:00.875025 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4192 04:41:00.927347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4193 04:41:00.928052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4195 04:41:00.982884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4196 04:41:00.983628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4198 04:41:01.027828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4199 04:41:01.028576 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4201 04:41:01.077834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4202 04:41:01.078568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4204 04:41:01.127180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4205 04:41:01.127873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4207 04:41:01.176778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4208 04:41:01.177496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4210 04:41:01.230093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4211 04:41:01.230770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4213 04:41:01.279365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4214 04:41:01.280086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4216 04:41:01.330592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4217 04:41:01.331276 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4219 04:41:01.382745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4220 04:41:01.383494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4222 04:41:01.435853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4223 04:41:01.436607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4225 04:41:01.487838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4226 04:41:01.488620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4228 04:41:01.539908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4229 04:41:01.540690 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4231 04:41:01.598582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4232 04:41:01.599389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4234 04:41:01.648328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4235 04:41:01.649052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4237 04:41:01.694679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4238 04:41:01.695392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4240 04:41:01.744899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4241 04:41:01.745587 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4243 04:41:01.790096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4244 04:41:01.790811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4246 04:41:01.835867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4247 04:41:01.836668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4249 04:41:01.885423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4250 04:41:01.886140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4252 04:41:01.931136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4253 04:41:01.931819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4255 04:41:01.982866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4256 04:41:01.983653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4258 04:41:02.028393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4259 04:41:02.029109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4261 04:41:02.074941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4262 04:41:02.075693 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4264 04:41:02.124767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4265 04:41:02.125480 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4267 04:41:02.168629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4268 04:41:02.169353 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4270 04:41:02.222606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4271 04:41:02.223302 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4273 04:41:02.267641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4274 04:41:02.268395 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4276 04:41:02.325648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4277 04:41:02.326319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4279 04:41:02.373875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4280 04:41:02.374634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4282 04:41:02.422924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4283 04:41:02.423663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4285 04:41:02.473272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4286 04:41:02.474025 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4288 04:41:02.516569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4289 04:41:02.517302 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4291 04:41:02.567760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4292 04:41:02.568617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4294 04:41:02.611786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4295 04:41:02.612540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4297 04:41:02.659281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4298 04:41:02.659975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4300 04:41:02.713896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4301 04:41:02.714614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4303 04:41:02.765759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4304 04:41:02.766489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4306 04:41:02.810138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4307 04:41:02.810828 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4309 04:41:02.859320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4310 04:41:02.860041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4312 04:41:02.913321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4313 04:41:02.914038 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4315 04:41:02.964891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4316 04:41:02.965731 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4318 04:41:03.016318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4319 04:41:03.017027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4321 04:41:03.061709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4322 04:41:03.062434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4324 04:41:03.107644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4325 04:41:03.108397 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4327 04:41:03.157925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4328 04:41:03.158615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4330 04:41:03.208549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4331 04:41:03.209255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4333 04:41:03.253073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4334 04:41:03.253764 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4336 04:41:03.303693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4337 04:41:03.304426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4339 04:41:03.346890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4340 04:41:03.347622 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4342 04:41:03.394986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4343 04:41:03.395693 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4345 04:41:03.448702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4346 04:41:03.449464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4348 04:41:03.501785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4349 04:41:03.502489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4351 04:41:03.542670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4353 04:41:03.545618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4354 04:41:03.603358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4355 04:41:03.604124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4357 04:41:03.658494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4358 04:41:03.659190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4360 04:41:03.709468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4361 04:41:03.710159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4363 04:41:03.753456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4364 04:41:03.754139 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4366 04:41:03.804444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4367 04:41:03.805131 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4369 04:41:03.850479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4370 04:41:03.851241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4372 04:41:03.899780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4373 04:41:03.900504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4375 04:41:03.946361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4376 04:41:03.947041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4378 04:41:03.994463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4379 04:41:03.995161 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4381 04:41:04.050722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4382 04:41:04.051447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4384 04:41:04.107391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4385 04:41:04.108084 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4387 04:41:04.153929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4388 04:41:04.154626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4390 04:41:04.203689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4391 04:41:04.204413 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4393 04:41:04.256062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4394 04:41:04.256752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4396 04:41:04.303161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4397 04:41:04.303848 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4399 04:41:04.351004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4400 04:41:04.351690 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4402 04:41:04.400907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4403 04:41:04.401603 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4405 04:41:04.448578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4406 04:41:04.449345 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4408 04:41:04.498782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4409 04:41:04.499480 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4411 04:41:04.553661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4412 04:41:04.554436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4414 04:41:04.599117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4415 04:41:04.599832 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4417 04:41:04.646788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4418 04:41:04.647488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4420 04:41:04.691597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4421 04:41:04.692315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4423 04:41:04.737798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4424 04:41:04.738485 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4426 04:41:04.799908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4427 04:41:04.800641 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4429 04:41:04.852075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4430 04:41:04.852769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4432 04:41:04.903461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4433 04:41:04.904150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4435 04:41:04.966559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4436 04:41:04.967248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4438 04:41:05.014451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4439 04:41:05.015154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4441 04:41:05.058953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4442 04:41:05.059664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4444 04:41:05.114578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4445 04:41:05.115277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4447 04:41:05.164313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4448 04:41:05.164993 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4450 04:41:05.214451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4451 04:41:05.215141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4453 04:41:05.266053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4454 04:41:05.266737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4456 04:41:05.316969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4457 04:41:05.317714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4459 04:41:05.368251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4460 04:41:05.369017 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4462 04:41:05.422668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4463 04:41:05.423449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4465 04:41:05.485014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4466 04:41:05.485750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4468 04:41:05.544687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4469 04:41:05.545658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4471 04:41:05.604115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4472 04:41:05.604940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4474 04:41:05.659462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4475 04:41:05.660175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4477 04:41:05.711753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4478 04:41:05.712496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4480 04:41:05.756292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4481 04:41:05.756988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4483 04:41:05.816291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4484 04:41:05.816987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4486 04:41:05.874303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4487 04:41:05.874996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4489 04:41:05.934706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4490 04:41:05.935392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4492 04:41:05.986507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4493 04:41:05.987190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4495 04:41:06.037748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4496 04:41:06.038483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4498 04:41:06.085498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4499 04:41:06.086213 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4501 04:41:06.140125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4502 04:41:06.140892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4504 04:41:06.189937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4505 04:41:06.190643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4507 04:41:06.239168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4509 04:41:06.244387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4510 04:41:06.244831 + set +x
4511 04:41:06.250300 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 950934_1.6.2.4.5>
4512 04:41:06.250733 <LAVA_TEST_RUNNER EXIT>
4513 04:41:06.251376 Received signal: <ENDRUN> 1_kselftest-alsa 950934_1.6.2.4.5
4514 04:41:06.251816 Ending use of test pattern.
4515 04:41:06.252257 Ending test lava.1_kselftest-alsa (950934_1.6.2.4.5), duration 40.96
4517 04:41:06.253729 ok: lava_test_shell seems to have completed
4518 04:41:06.275678 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4519 04:41:06.277382 end: 3.1 lava-test-shell (duration 00:00:42) [common]
4520 04:41:06.277954 end: 3 lava-test-retry (duration 00:00:42) [common]
4521 04:41:06.278515 start: 4 finalize (timeout 00:06:04) [common]
4522 04:41:06.279072 start: 4.1 power-off (timeout 00:00:30) [common]
4523 04:41:06.280027 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4524 04:41:06.315145 >> OK - accepted request
4525 04:41:06.317267 Returned 0 in 0 seconds
4526 04:41:06.418400 end: 4.1 power-off (duration 00:00:00) [common]
4528 04:41:06.420126 start: 4.2 read-feedback (timeout 00:06:04) [common]
4529 04:41:06.421252 Listened to connection for namespace 'common' for up to 1s
4530 04:41:07.421091 Finalising connection for namespace 'common'
4531 04:41:07.421807 Disconnecting from shell: Finalise
4532 04:41:07.422356 / #
4533 04:41:07.523337 end: 4.2 read-feedback (duration 00:00:01) [common]
4534 04:41:07.523872 end: 4 finalize (duration 00:00:01) [common]
4535 04:41:07.524342 Cleaning after the job
4536 04:41:07.524751 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950934/tftp-deploy-y6z2r49c/ramdisk
4537 04:41:07.537379 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950934/tftp-deploy-y6z2r49c/kernel
4538 04:41:07.579373 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950934/tftp-deploy-y6z2r49c/dtb
4539 04:41:07.580309 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950934/tftp-deploy-y6z2r49c/nfsrootfs
4540 04:41:07.744449 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950934/tftp-deploy-y6z2r49c/modules
4541 04:41:07.764613 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/950934
4542 04:41:10.910118 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/950934
4543 04:41:10.910663 Job finished correctly